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-rw-r--r--libc/sysdeps/linux/arm/__longjmp.S8
-rw-r--r--libc/sysdeps/linux/arm/bits/elf-fdpic.h2
-rw-r--r--libc/sysdeps/linux/arm/bits/fcntl.h2
-rw-r--r--libc/sysdeps/linux/arm/bits/fenv.h107
-rw-r--r--libc/sysdeps/linux/arm/bits/hwcap.h50
-rw-r--r--libc/sysdeps/linux/arm/bits/kernel_stat.h1
-rw-r--r--libc/sysdeps/linux/arm/bits/shm.h6
-rw-r--r--libc/sysdeps/linux/arm/bits/uClibc_arch_features.h3
-rw-r--r--libc/sysdeps/linux/arm/crt1.S18
-rw-r--r--libc/sysdeps/linux/arm/fpu_control.h192
-rw-r--r--libc/sysdeps/linux/arm/setjmp.S8
11 files changed, 172 insertions, 225 deletions
diff --git a/libc/sysdeps/linux/arm/__longjmp.S b/libc/sysdeps/linux/arm/__longjmp.S
index 58ae8ab58..a5ffe84e9 100644
--- a/libc/sysdeps/linux/arm/__longjmp.S
+++ b/libc/sysdeps/linux/arm/__longjmp.S
@@ -64,6 +64,13 @@ __longjmp:
#if defined __UCLIBC_HAS_FLOATS__ && ! defined __UCLIBC_HAS_SOFT_FLOAT__
#ifdef __VFP_FP__
+# if __ARM_ARCH >= 8
+ /* Restore the VFP registers. */
+ fldmiax ip!, {d8-d15}
+ /* Restore the floating-point status register. */
+ ldr r1, [ip], #4
+ fmxr fpscr, r1
+# else
/* Restore the VFP registers. */
/* Following instruction is fldmiax ip!, {d8-d15}. */
ldc p11, cr8, [r12], #68
@@ -71,6 +78,7 @@ __longjmp:
ldr r1, [ip], #4
/* Following instruction is fmxr fpscr, r1. */
mcr p10, 7, r1, cr1, cr0, 0
+# endif
# elif defined __MAVERICK__
cfldrd mvd4, [ip], #8 ; nop
cfldrd mvd5, [ip], #8 ; nop
diff --git a/libc/sysdeps/linux/arm/bits/elf-fdpic.h b/libc/sysdeps/linux/arm/bits/elf-fdpic.h
index 3d6db54af..f2ef9aeca 100644
--- a/libc/sysdeps/linux/arm/bits/elf-fdpic.h
+++ b/libc/sysdeps/linux/arm/bits/elf-fdpic.h
@@ -91,7 +91,7 @@ __reloc_pointer (void *p,
/* This should be computed as part of the pointer comparison
above, but we want to use the carry in the comparison, so we
can't convert it to an integer type beforehand. */
- unsigned long offset = p - (void*)map->segs[c].p_vaddr;
+ unsigned long offset = (char*)p - (char*)map->segs[c].p_vaddr;
/* We only check for one-past-the-end for the last segment,
assumed to be the data segment, because other cases are
ambiguous in the absence of padding between segments, and
diff --git a/libc/sysdeps/linux/arm/bits/fcntl.h b/libc/sysdeps/linux/arm/bits/fcntl.h
index 823660648..52dee4287 100644
--- a/libc/sysdeps/linux/arm/bits/fcntl.h
+++ b/libc/sysdeps/linux/arm/bits/fcntl.h
@@ -244,3 +244,5 @@ extern ssize_t tee (int __fdin, int __fdout, size_t __len,
#endif
__END_DECLS
+/* Include generic Linux declarations. */
+#include <bits/fcntl-linux.h>
diff --git a/libc/sysdeps/linux/arm/bits/fenv.h b/libc/sysdeps/linux/arm/bits/fenv.h
index 106bf36c2..ab60b9e70 100644
--- a/libc/sysdeps/linux/arm/bits/fenv.h
+++ b/libc/sysdeps/linux/arm/bits/fenv.h
@@ -1,5 +1,4 @@
-/* Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
+/* Copyright (C) 2004-2025 Free Software Foundation, Inc.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -12,87 +11,77 @@
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
+ License along with the GNU C Library. If not, see
+ <https://www.gnu.org/licenses/>. */
#ifndef _FENV_H
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif
-#ifdef __MAVERICK__
-
/* Define bits representing exceptions in the FPU status word. */
enum
{
- FE_INVALID = 1,
-#define FE_INVALID FE_INVALID
- FE_OVERFLOW = 4,
-#define FE_OVERFLOW FE_OVERFLOW
- FE_UNDERFLOW = 8,
-#define FE_UNDERFLOW FE_UNDERFLOW
- FE_INEXACT = 16,
-#define FE_INEXACT FE_INEXACT
+ FE_INVALID =
+#define FE_INVALID 1
+ FE_INVALID,
+ FE_DIVBYZERO =
+#define FE_DIVBYZERO 2
+ FE_DIVBYZERO,
+ FE_OVERFLOW =
+#define FE_OVERFLOW 4
+ FE_OVERFLOW,
+ FE_UNDERFLOW =
+#define FE_UNDERFLOW 8
+ FE_UNDERFLOW,
+ FE_INEXACT =
+#define FE_INEXACT 16
+ FE_INEXACT,
};
/* Amount to shift by to convert an exception to a mask bit. */
-#define FE_EXCEPT_SHIFT 5
+#define FE_EXCEPT_SHIFT 8
/* All supported exceptions. */
-#define FE_ALL_EXCEPT \
- (FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
-
-/* IEEE rounding modes. */
-enum
- {
- FE_TONEAREST = 0,
-#define FE_TONEAREST FE_TONEAREST
- FE_TOWARDZERO = 0x400,
-#define FE_TOWARDZERO FE_TOWARDZERO
- FE_DOWNWARD = 0x800,
-#define FE_DOWNWARD FE_DOWNWARD
- FE_UPWARD = 0xc00,
-#define FE_UPWARD FE_UPWARD
- };
-
-#define FE_ROUND_MASK (FE_UPWARD)
-
-#else /* !__MAVERICK__ */
+#define FE_ALL_EXCEPT \
+ (FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
-/* Define bits representing exceptions in the FPU status word. */
+/* VFP supports all of the four defined rounding modes. */
enum
{
- FE_INVALID = 1,
-#define FE_INVALID FE_INVALID
- FE_DIVBYZERO = 2,
-#define FE_DIVBYZERO FE_DIVBYZERO
- FE_OVERFLOW = 4,
-#define FE_OVERFLOW FE_OVERFLOW
- FE_UNDERFLOW = 8,
-#define FE_UNDERFLOW FE_UNDERFLOW
- };
-
-/* Amount to shift by to convert an exception to a mask bit. */
-#define FE_EXCEPT_SHIFT 16
-
-/* All supported exceptions. */
-#define FE_ALL_EXCEPT \
- (FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW)
-
-/* The ARM FPU basically only supports round-to-nearest. Other rounding
- modes exist, but you have to encode them in the actual instruction. */
+ FE_TONEAREST =
#define FE_TONEAREST 0
-
-#endif /* __MAVERICK__ */
+ FE_TONEAREST,
+ FE_UPWARD =
+#define FE_UPWARD 0x400000
+ FE_UPWARD,
+ FE_DOWNWARD =
+#define FE_DOWNWARD 0x800000
+ FE_DOWNWARD,
+ FE_TOWARDZERO =
+#define FE_TOWARDZERO 0xc00000
+ FE_TOWARDZERO
+ };
/* Type representing exception flags. */
-typedef unsigned long int fexcept_t;
+typedef unsigned int fexcept_t;
/* Type representing floating-point environment. */
typedef struct
{
- unsigned long int __cw;
+ unsigned int __cw;
}
fenv_t;
/* If the default argument is used we use this value. */
-#define FE_DFL_ENV ((fenv_t *) -1l)
+#define FE_DFL_ENV ((const fenv_t *) -1l)
+
+#ifdef __USE_GNU
+/* Floating-point environment where none of the exceptions are masked. */
+# define FE_NOMASK_ENV ((const fenv_t *) -2)
+#endif
+
+/* Type representing floating-point control modes. */
+typedef unsigned int femode_t;
+
+/* Default floating-point control modes. */
+# define FE_DFL_MODE ((const femode_t *) -1L)
diff --git a/libc/sysdeps/linux/arm/bits/hwcap.h b/libc/sysdeps/linux/arm/bits/hwcap.h
new file mode 100644
index 000000000..0a741b469
--- /dev/null
+++ b/libc/sysdeps/linux/arm/bits/hwcap.h
@@ -0,0 +1,50 @@
+/* Defines for bits in AT_HWCAP. ARM Linux version.
+ Copyright (C) 2012-2023 Free Software Foundation, Inc.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#if !defined (_SYS_AUXV_H) && !defined (_LINUX_ARM_SYSDEP_H)
+# error "Never include <bits/hwcap.h> directly; use <sys/auxv.h> instead."
+#endif
+
+/* The following must match the kernel's <asm/hwcap.h>. */
+#define HWCAP_ARM_SWP 1
+#define HWCAP_ARM_HALF 2
+#define HWCAP_ARM_THUMB 4
+#define HWCAP_ARM_26BIT 8
+#define HWCAP_ARM_FAST_MULT 16
+#define HWCAP_ARM_FPA 32
+#define HWCAP_ARM_VFP 64
+#define HWCAP_ARM_EDSP 128
+#define HWCAP_ARM_JAVA 256
+#define HWCAP_ARM_IWMMXT 512
+#define HWCAP_ARM_CRUNCH 1024
+#define HWCAP_ARM_THUMBEE 2048
+#define HWCAP_ARM_NEON 4096
+#define HWCAP_ARM_VFPv3 8192
+#define HWCAP_ARM_VFPv3D16 16384
+#define HWCAP_ARM_TLS 32768
+#define HWCAP_ARM_VFPv4 65536
+#define HWCAP_ARM_IDIVA 131072
+#define HWCAP_ARM_IDIVT 262144
+#define HWCAP_ARM_VFPD32 524288
+#define HWCAP_ARM_LPAE 1048576
+#define HWCAP_ARM_EVTSTRM 2097152
+#define HWCAP_FPHP 4194304
+#define HWCAP_ASIMDHP 8388608
+#define HWCAP_ASIMDDP 16777216
+#define HWCAP_ASIMDFHM 33554432
+#define HWCAP_ASIMDBF16 67108864
+#define HWCAP_I8MM 134217728
diff --git a/libc/sysdeps/linux/arm/bits/kernel_stat.h b/libc/sysdeps/linux/arm/bits/kernel_stat.h
index b293dfc05..cdbeeb4de 100644
--- a/libc/sysdeps/linux/arm/bits/kernel_stat.h
+++ b/libc/sysdeps/linux/arm/bits/kernel_stat.h
@@ -50,7 +50,6 @@ struct kernel_stat64 {
long long st_size;
unsigned long st_blksize;
unsigned long long st_blocks; /* Number 512-byte blocks allocated. */
-
struct timespec st_atim;
struct timespec st_mtim;
struct timespec st_ctim;
diff --git a/libc/sysdeps/linux/arm/bits/shm.h b/libc/sysdeps/linux/arm/bits/shm.h
index 86245faff..aa1a72e54 100644
--- a/libc/sysdeps/linux/arm/bits/shm.h
+++ b/libc/sysdeps/linux/arm/bits/shm.h
@@ -49,12 +49,18 @@ struct shmid_ds
{
struct ipc_perm shm_perm; /* operation permission struct */
size_t shm_segsz; /* size of segment in bytes */
+#if defined(__UCLIBC_USE_TIME64__)
+ __time_t shm_atime;
+ __time_t shm_dtime;
+ __time_t shm_ctime;
+#else
__time_t shm_atime; /* time of last shmat() */
unsigned long int __uclibc_unused1;
__time_t shm_dtime; /* time of last shmdt() */
unsigned long int __uclibc_unused2;
__time_t shm_ctime; /* time of last change by shmctl() */
unsigned long int __uclibc_unused3;
+#endif
__pid_t shm_cpid; /* pid of creator */
__pid_t shm_lpid; /* pid of last shmop */
shmatt_t shm_nattch; /* number of current attaches */
diff --git a/libc/sysdeps/linux/arm/bits/uClibc_arch_features.h b/libc/sysdeps/linux/arm/bits/uClibc_arch_features.h
index b0b093c99..671afd3ac 100644
--- a/libc/sysdeps/linux/arm/bits/uClibc_arch_features.h
+++ b/libc/sysdeps/linux/arm/bits/uClibc_arch_features.h
@@ -11,9 +11,6 @@
/* can your target use syscall6() for mmap ? */
#undef __UCLIBC_MMAP_HAS_6_ARGS__
-/* does your target use statx */
-#undef __UCLIBC_HAVE_STATX__
-
/* does your target align 64bit values in register pairs ? (32bit arches only) */
#ifdef __ARM_EABI__
#define __UCLIBC_SYSCALL_ALIGN_64BIT__
diff --git a/libc/sysdeps/linux/arm/crt1.S b/libc/sysdeps/linux/arm/crt1.S
index a1d7f0f23..040ddfd27 100644
--- a/libc/sysdeps/linux/arm/crt1.S
+++ b/libc/sysdeps/linux/arm/crt1.S
@@ -245,7 +245,19 @@ _start:
mov fp, #0
mov lr, #0
-#ifdef __ARCH_USE_MMU__
+#if defined(__ARCH_USE_MMU__) || defined(__UCLIBC_FORMAT_ELF__)
+#ifdef L_rcrt1
+ /* We don't need to save a1 since no dynamic linker should have run */
+ adr a1, .L__ehdr_start_off /* Get address of .L__ehdr_start_off */
+ ldr a2, .L__ehdr_start_off /* Offset from .L__ehdr_start_off to __ehdr_start */
+ add a1, a1, a2 /* Address of __ehdr_start = load addr */
+ bl reloc_static_pie
+ mov a1, #0 /* Clean up a1 so that a random address won't get called at the end of program */
+
+ /* Clear the frame pointer and link register again since it might be modified by previous call */
+ mov fp, #0
+ mov lr, #0
+#endif
/* Pop argc off the stack and save a pointer to argv */
ldr a2, [sp], #4
mov a3, sp
@@ -310,6 +322,10 @@ _start:
.word _init(GOT)
.word main(GOT)
#endif
+#ifdef L_rcrt1
+.L__ehdr_start_off:
+ .word __ehdr_start - .L__ehdr_start_off
+#endif
#endif
/* Define a symbol for the first piece of initialized data. */
diff --git a/libc/sysdeps/linux/arm/fpu_control.h b/libc/sysdeps/linux/arm/fpu_control.h
index 1b9b09df6..05ac6a03c 100644
--- a/libc/sysdeps/linux/arm/fpu_control.h
+++ b/libc/sysdeps/linux/arm/fpu_control.h
@@ -1,6 +1,5 @@
-/* FPU control word definitions. ARM version.
- Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
+/* FPU control word definitions. ARM VFP version.
+ Copyright (C) 2004-2025 Free Software Foundation, Inc.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@@ -13,13 +12,22 @@
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
+ License along with the GNU C Library. If not, see
+ <https://www.gnu.org/licenses/>. */
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H
-#ifdef __VFP_FP__
+#if !(defined(_LIBC) && !defined(_LIBC_TEST)) && defined(__SOFTFP__)
+
+#define _FPU_RESERVED 0xffffffff
+#define _FPU_DEFAULT 0x00000000
+typedef unsigned int fpu_control_t;
+#define _FPU_GETCW(cw) (cw) = 0
+#define _FPU_SETCW(cw) (void) (cw)
+extern fpu_control_t __fpu_control;
+
+#else
/* masking of interrupts */
#define _FPU_MASK_IM 0x00000100 /* invalid operation */
@@ -28,175 +36,39 @@
#define _FPU_MASK_UM 0x00000800 /* underflow */
#define _FPU_MASK_PM 0x00001000 /* inexact */
+#define _FPU_MASK_NZCV 0xf0000000 /* NZCV flags */
+#define _FPU_MASK_RM 0x00c00000 /* rounding mode */
+#define _FPU_MASK_EXCEPT 0x00001f1f /* all exception flags */
+
/* Some bits in the FPSCR are not yet defined. They must be preserved when
modifying the contents. */
-#define _FPU_RESERVED 0x0e08e0e0
+#define _FPU_RESERVED 0x00086060
#define _FPU_DEFAULT 0x00000000
-/* Default + exceptions enabled. */
+
+/* Default + exceptions enabled. */
#define _FPU_IEEE (_FPU_DEFAULT | 0x00001f00)
/* Type of the control word. */
typedef unsigned int fpu_control_t;
/* Macros for accessing the hardware control word. */
+#ifdef __SOFTFP__
/* This is fmrx %0, fpscr. */
-#define _FPU_GETCW(cw) \
+# define _FPU_GETCW(cw) \
__asm__ __volatile__ ("mrc p10, 7, %0, cr1, cr0, 0" : "=r" (cw))
/* This is fmxr fpscr, %0. */
-#define _FPU_SETCW(cw) \
+# define _FPU_SETCW(cw) \
__asm__ __volatile__ ("mcr p10, 7, %0, cr1, cr0, 0" : : "r" (cw))
+#else
+# define _FPU_GETCW(cw) \
+ __asm__ __volatile__ ("vmrs %0, fpscr" : "=r" (cw))
+# define _FPU_SETCW(cw) \
+ __asm__ __volatile__ ("vmsr fpscr, %0" : : "r" (cw))
+#endif
-#elif defined __MAVERICK__
-
-/* DSPSC register: (from EP9312 User's Guide)
- *
- * bits 31..29 - DAID
- * bits 28..26 - HVID
- * bits 25..24 - RSVD
- * bit 23 - ISAT
- * bit 22 - UI
- * bit 21 - INT
- * bit 20 - AEXC
- * bits 19..18 - SAT
- * bits 17..16 - FCC
- * bit 15 - V
- * bit 14 - FWDEN
- * bit 13 - Invalid
- * bit 12 - Denorm
- * bits 11..10 - RM
- * bits 9..5 - IXE, UFE, OFE, RSVD, IOE
- * bits 4..0 - IX, UF, OF, RSVD, IO
- */
-
-/* masking of interrupts */
-#define _FPU_MASK_IM (1 << 5) /* invalid operation */
-#define _FPU_MASK_ZM 0 /* divide by zero */
-#define _FPU_MASK_OM (1 << 7) /* overflow */
-#define _FPU_MASK_UM (1 << 8) /* underflow */
-#define _FPU_MASK_PM (1 << 9) /* inexact */
-#define _FPU_MASK_DM 0 /* denormalized operation */
-
-#define _FPU_RESERVED 0xfffff000 /* These bits are reserved. */
-
-#define _FPU_DEFAULT 0x00b00000 /* Default value. */
-#define _FPU_IEEE 0x00b003a0 /* Default + exceptions enabled. */
-
-/* Type of the control word. */
-typedef unsigned int fpu_control_t;
-
-/* Macros for accessing the hardware control word. */
-#define _FPU_GETCW(cw) ({ \
- register int __t1, __t2; \
- \
- __asm__ __volatile__ ( \
- "cfmvr64l %1, mvdx0\n\t" \
- "cfmvr64h %2, mvdx0\n\t" \
- "cfmv32sc mvdx0, dspsc\n\t" \
- "cfmvr64l %0, mvdx0\n\t" \
- "cfmv64lr mvdx0, %1\n\t" \
- "cfmv64hr mvdx0, %2" \
- : "=r" (cw), "=r" (__t1), "=r" (__t2) \
- ); \
-})
-
-#define _FPU_SETCW(cw) ({ \
- register int __t0, __t1, __t2; \
- \
- __asm__ __volatile__ ( \
- "cfmvr64l %1, mvdx0\n\t" \
- "cfmvr64h %2, mvdx0\n\t" \
- "cfmv64lr mvdx0, %0\n\t" \
- "cfmvsc32 dspsc, mvdx0\n\t" \
- "cfmv64lr mvdx0, %1\n\t" \
- "cfmv64hr mvdx0, %2" \
- : "=r" (__t0), "=r" (__t1), "=r" (__t2) \
- : "0" (cw) \
- ); \
-})
-
-#else /* !__MAVERICK__ */
-
-/* We have a slight terminology confusion here. On the ARM, the register
- * we're interested in is actually the FPU status word - the FPU control
- * word is something different (which is implementation-defined and only
- * accessible from supervisor mode.)
- *
- * The FPSR looks like this:
- *
- * 31-24 23-16 15-8 7-0
- * | system ID | trap enable | system control | exception flags |
- *
- * We ignore the system ID bits; for interest's sake they are:
- *
- * 0000 "old" FPE
- * 1000 FPPC hardware
- * 0001 FPE 400
- * 1001 FPA hardware
- *
- * The trap enable and exception flags are both structured like this:
- *
- * 7 - 5 4 3 2 1 0
- * | reserved | INX | UFL | OFL | DVZ | IVO |
- *
- * where a `1' bit in the enable byte means that the trap can occur, and
- * a `1' bit in the flags byte means the exception has occurred.
- *
- * The exceptions are:
- *
- * IVO - invalid operation
- * DVZ - divide by zero
- * OFL - overflow
- * UFL - underflow
- * INX - inexact (do not use; implementations differ)
- *
- * The system control byte looks like this:
- *
- * 7-5 4 3 2 1 0
- * | reserved | AC | EP | SO | NE | ND |
- *
- * where the bits mean
- *
- * ND - no denormalised numbers (force them all to zero)
- * NE - enable NaN exceptions
- * SO - synchronous operation
- * EP - use expanded packed-decimal format
- * AC - use alternate definition for C flag on compare operations
- */
-
-/* masking of interrupts */
-#define _FPU_MASK_IM 0x00010000 /* invalid operation */
-#define _FPU_MASK_ZM 0x00020000 /* divide by zero */
-#define _FPU_MASK_OM 0x00040000 /* overflow */
-#define _FPU_MASK_UM 0x00080000 /* underflow */
-#define _FPU_MASK_PM 0x00100000 /* inexact */
-#define _FPU_MASK_DM 0x00000000 /* denormalized operation */
-
-/* The system id bytes cannot be changed.
- Only the bottom 5 bits in the trap enable byte can be changed.
- Only the bottom 5 bits in the system control byte can be changed.
- Only the bottom 5 bits in the exception flags are used.
- The exception flags are set by the fpu, but can be zeroed by the user. */
-#define _FPU_RESERVED 0xffe0e0e0 /* These bits are reserved. */
-
-/* The fdlibm code requires strict IEEE double precision arithmetic,
- no interrupts for exceptions, rounding to nearest. Changing the
- rounding mode will break long double I/O. Turn on the AC bit,
- the compiler generates code that assumes it is on. */
-#define _FPU_DEFAULT 0x00001000 /* Default value. */
-#define _FPU_IEEE 0x001f1000 /* Default + exceptions enabled. */
-
-/* Type of the control word. */
-typedef unsigned int fpu_control_t;
-
-/* Macros for accessing the hardware control word. */
-#define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
-#define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
-
-#endif /* __MAVERICK__ */
-
-#if 0
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
-#endif
+
+#endif /* __SOFTFP__ */
#endif /* _FPU_CONTROL_H */
diff --git a/libc/sysdeps/linux/arm/setjmp.S b/libc/sysdeps/linux/arm/setjmp.S
index f7a74cc5a..d5bc9ba65 100644
--- a/libc/sysdeps/linux/arm/setjmp.S
+++ b/libc/sysdeps/linux/arm/setjmp.S
@@ -54,6 +54,13 @@ __sigsetjmp:
#endif
#if defined __UCLIBC_HAS_FLOATS__ && ! defined __UCLIBC_HAS_SOFT_FLOAT__
# ifdef __VFP_FP__
+# if __ARM_ARCH >= 8
+ /* Store the VFP registers. */
+ fstmiax ip!, {d8-d15}
+ /* Store the floating-point status register. */
+ fmrx r2, fpscr
+ str r2, [ip], #4
+# else
/* Store the VFP registers. */
/* Following instruction is fstmiax ip!, {d8-d15}. */
stc p11, cr8, [r12], #68
@@ -61,6 +68,7 @@ __sigsetjmp:
/* Following instruction is fmrx r2, fpscr. */
mrc p10, 7, r2, cr1, cr0, 0
str r2, [ip], #4
+# endif
# elif defined __MAVERICK__
cfstrd mvd4, [ip], #8 ; nop
cfstrd mvd5, [ip], #8 ; nop
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 19:07:28 +0000