summaryrefslogtreecommitdiff
path: root/libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S
diff options
context:
space:
mode:
authorAustin Foxley <austinf@cetoncorp.com>2009-10-17 12:26:24 -0700
committerAustin Foxley <austinf@cetoncorp.com>2009-10-17 12:26:24 -0700
commitc68d0fa2d88fc2134a38d99e7e944828384a7671 (patch)
tree6596943bd1c77f18d6e49d4153ddd3f3d67b49f5 /libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S
parent9a03e98a3b418f33c347a6023e9320f3a42cb9e4 (diff)
libpthread/nptl: core of the "Native Posix Threading Library" for uClibc
targetting arm,sh,i386,mips,sparc for now Signed-off-by: Austin Foxley <austinf@cetoncorp.com>
Diffstat (limited to 'libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S')
-rw-r--r--libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S43
1 files changed, 43 insertions, 0 deletions
diff --git a/libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S b/libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S
new file mode 100644
index 000000000..b54732869
--- /dev/null
+++ b/libpthread/nptl/sysdeps/mips/pthread_spin_trylock.S
@@ -0,0 +1,43 @@
+/* Copyright (C) 2005 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#include <sys/asm.h>
+#include <sysdep.h>
+#define _ERRNO_H 1
+#include <bits/errno.h>
+#include <sgidefs.h>
+
+ENTRY (pthread_spin_trylock)
+ .set push
+#if _MIPS_SIM == _ABIO32
+ .set mips2
+#endif
+ ll a2, 0(a0)
+ li a1, 1
+ bnez a2, 1f
+ sc a1, 0(a0)
+ beqz a1, 1f
+ MIPS_SYNC
+ .set pop
+ li v0, 0
+ j ra
+ nop
+1: li v0, EBUSY
+ j ra
+ nop
+END (pthread_spin_trylock)