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authorBernhard Reutner-Fischer <rep.dot.nop@gmail.com>2008-09-15 16:36:11 +0000
committerBernhard Reutner-Fischer <rep.dot.nop@gmail.com>2008-09-15 16:36:11 +0000
commite9a22a46d74aa21284502720dfc5bbd3540d3457 (patch)
tree4f4934122db9560fee6edd676d5901fd3f74303c /libc
parent15ffa43fafc8a2dfd1e69d8d6b05ef55a06ccfbe (diff)
- commentary typo fix
Diffstat (limited to 'libc')
-rw-r--r--libc/string/powerpc/memcpy.c2
-rw-r--r--libc/string/powerpc/memmove.c2
-rw-r--r--libc/string/powerpc/memset.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/libc/string/powerpc/memcpy.c b/libc/string/powerpc/memcpy.c
index dd39e6f9d..f3d800739 100644
--- a/libc/string/powerpc/memcpy.c
+++ b/libc/string/powerpc/memcpy.c
@@ -7,7 +7,7 @@
/* These are carefully optimized mem*() functions for PPC written in C.
* Don't muck around with these function without checking the generated
- * assmbler code.
+ * assembler code.
* It is possible to optimize these significantly more by using specific
* data cache instructions(mainly dcbz). However that requires knownledge
* about the CPU's cache line size.
diff --git a/libc/string/powerpc/memmove.c b/libc/string/powerpc/memmove.c
index d307e74a6..8badae37d 100644
--- a/libc/string/powerpc/memmove.c
+++ b/libc/string/powerpc/memmove.c
@@ -7,7 +7,7 @@
/* These are carefully optimized mem*() functions for PPC written in C.
* Don't muck around with these function without checking the generated
- * assmbler code.
+ * assembler code.
* It is possible to optimize these significantly more by using specific
* data cache instructions(mainly dcbz). However that requires knownledge
* about the CPU's cache line size.
diff --git a/libc/string/powerpc/memset.c b/libc/string/powerpc/memset.c
index 59bec87b9..1cbfd04fc 100644
--- a/libc/string/powerpc/memset.c
+++ b/libc/string/powerpc/memset.c
@@ -7,7 +7,7 @@
/* These are carefully optimized mem*() functions for PPC written in C.
* Don't muck around with these function without checking the generated
- * assmbler code.
+ * assembler code.
* It is possible to optimize these significantly more by using specific
* data cache instructions(mainly dcbz). However that requires knownledge
* about the CPU's cache line size.