diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2015-02-19 19:13:59 +0530 |
|---|---|---|
| committer | Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> | 2015-02-20 11:30:20 +0100 |
| commit | afab56958f1cbb47b831ee3ebff231dfbae74af2 (patch) | |
| tree | c6fdf19ecb770319d72048c7c56bd71964d52948 /libc | |
| parent | 89b63496e88c31c2714e42656212078388718b78 (diff) | |
ARCv2 ISA support
This is next gen Instruction Set Architecture from Synopsys and basis
for the ARC HS family of processors.
http://www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor&elq_mid=5732&elq_cid=458802
http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/arc-hs/Pages/default.aspx
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
Diffstat (limited to 'libc')
| -rw-r--r-- | libc/string/arc/memcmp.S | 29 | ||||
| -rw-r--r-- | libc/sysdeps/linux/arc/bits/syscalls.h | 10 | ||||
| -rwxr-xr-x | libc/sysdeps/linux/arc/bits/uClibc_arch_features.h | 7 |
3 files changed, 45 insertions, 1 deletions
diff --git a/libc/string/arc/memcmp.S b/libc/string/arc/memcmp.S index 4c0e39143..a60757e7a 100644 --- a/libc/string/arc/memcmp.S +++ b/libc/string/arc/memcmp.S @@ -24,14 +24,32 @@ ENTRY(memcmp) ld r4,[r0,0] ld r5,[r1,0] lsr.f lp_count,r3,3 +#ifdef __HS__ + /* In ARCv2 a branch can't be the last instruction in a zero overhead + * loop. + * So we move the branch to the start of the loop, duplicate it + * after the end, and set up r12 so that the branch isn't taken + * initially. + */ + mov_s r12,WORD2 + lpne .Loop_end + brne WORD2,r12,.Lodd + ld WORD2,[r0,4] +#else lpne .Loop_end ld_s WORD2,[r0,4] +#endif ld_s r12,[r1,4] brne r4,r5,.Leven ld.a r4,[r0,8] ld.a r5,[r1,8] +#ifdef __HS__ +.Loop_end: + brne WORD2,r12,.Lodd +#else brne WORD2,r12,.Lodd .Loop_end: +#endif asl_s SHIFT,SHIFT,3 bhs_s .Last_cmp brne r4,r5,.Leven @@ -99,14 +117,25 @@ ENTRY(memcmp) ldb r4,[r0,0] ldb r5,[r1,0] lsr.f lp_count,r3 +#ifdef __HS__ + mov r12,r3 lpne .Lbyte_end + brne r3,r12,.Lbyte_odd +#else + lpne .Lbyte_end +#endif ldb_s r3,[r0,1] ldb r12,[r1,1] brne r4,r5,.Lbyte_even ldb.a r4,[r0,2] ldb.a r5,[r1,2] +#ifdef __HS__ +.Lbyte_end: + brne r3,r12,.Lbyte_odd +#else brne r3,r12,.Lbyte_odd .Lbyte_end: +#endif bcc .Lbyte_even brne r4,r5,.Lbyte_even ldb_s r3,[r0,1] diff --git a/libc/sysdeps/linux/arc/bits/syscalls.h b/libc/sysdeps/linux/arc/bits/syscalls.h index 5da6aadb3..248ef7844 100644 --- a/libc/sysdeps/linux/arc/bits/syscalls.h +++ b/libc/sysdeps/linux/arc/bits/syscalls.h @@ -98,7 +98,11 @@ extern int __syscall_error (int); * for syscall itself. *-------------------------------------------------------------------------*/ -#define ARC_TRAP_INSN "trap0 \n\t" +#ifdef __A7__ +#define ARC_TRAP_INSN "trap0 \n\t" +#elif defined(__HS__) +#define ARC_TRAP_INSN "trap_s 0 \n\t" +#endif #define INTERNAL_SYSCALL_NCS(nm, err, nr_args, args...) \ ({ \ @@ -176,7 +180,11 @@ extern int __syscall_error (int); #else +#ifdef __A7__ #define ARC_TRAP_INSN trap0 +#elif defined(__HS__) +#define ARC_TRAP_INSN trap_s 0 +#endif #endif /* __ASSEMBLER__ */ diff --git a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h index 8af6eca4c..451575586 100755 --- a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h +++ b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h @@ -47,4 +47,11 @@ /* The default ';' is a comment on ARC. */ #define __UCLIBC_ASM_LINE_SEP__ ` +/* does your target align 64bit values in register pairs ? (32bit arches only) */ +#if defined(__A7__) +#undef __UCLIBC_SYSCALL_ALIGN_64BIT__ +#else +#define __UCLIBC_SYSCALL_ALIGN_64BIT__ +#endif + #endif /* _BITS_UCLIBC_ARCH_FEATURES_H */ |