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authorVineet Gupta <vgupta@synopsys.com>2015-02-19 19:14:01 +0530
committerBernhard Reutner-Fischer <rep.dot.nop@gmail.com>2015-02-20 11:34:55 +0100
commit2a2b1d2a3e97b4353eec5a40c0de4b932340b3fc (patch)
tree6769818d75a1c3a8d6b155aa7b6e32c715dcfcd0 /libc/sysdeps/linux/common
parentdf273fedf4fef25983ef6ec7e42b03d54f44960d (diff)
posix_fadvise: handle 2 variants for SYSCALL_ALIGN_64BIT
arm/powerpc/xtensa pass @advice as 2nd arg to syscall (vs. canonical 4th) Current code however does this for UCLIBC_SYSCALL_ALIGN_64BIT which powerpc/xtensa also happen to define. This is not true for ARCv2 ISA and possibly other arch of future with 64-bit even register requirement, which uses the standard syscall handler in kernel. Fix that by providing 2 variants of SYSCALL_ALIGN_64BIT Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
Diffstat (limited to 'libc/sysdeps/linux/common')
-rw-r--r--libc/sysdeps/linux/common/posix_fadvise.c10
-rw-r--r--libc/sysdeps/linux/common/posix_fadvise64.c11
2 files changed, 19 insertions, 2 deletions
diff --git a/libc/sysdeps/linux/common/posix_fadvise.c b/libc/sysdeps/linux/common/posix_fadvise.c
index 14bbeeea1..74d8409c0 100644
--- a/libc/sysdeps/linux/common/posix_fadvise.c
+++ b/libc/sysdeps/linux/common/posix_fadvise.c
@@ -41,9 +41,17 @@ int posix_fadvise(int fd, off_t offset, off_t len, int advice)
# if __WORDSIZE == 64
ret = INTERNAL_SYSCALL(fadvise64_64, err, 4, fd, offset, len, advice);
# else
-# if defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) || defined(__arm__)
+# if defined (__arm__) || \
+ (defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) && (defined(__powerpc__) || defined(__xtensa__)))
+ /* arch with 64-bit data in even reg alignment #1: [powerpc/xtensa]
+ * custom syscall handler (rearranges @advice to avoid register hole punch) */
ret = INTERNAL_SYSCALL(fadvise64_64, err, 6, fd, advice,
OFF_HI_LO (offset), OFF_HI_LO (len));
+# elif defined(__UCLIBC_SYSCALL_ALIGN_64BIT__)
+ /* arch with 64-bit data in even reg alignment #2: [arcv2/others-in-future]
+ * stock syscall handler in kernel (reg hole punched) */
+ ret = INTERNAL_SYSCALL(fadvise64_64, err, 7, fd, 0,
+ OFF_HI_LO (offset), OFF_HI_LO (len), advice);
# else
ret = INTERNAL_SYSCALL(fadvise64_64, err, 6, fd,
OFF_HI_LO (offset), OFF_HI_LO (len), advice);
diff --git a/libc/sysdeps/linux/common/posix_fadvise64.c b/libc/sysdeps/linux/common/posix_fadvise64.c
index 5d8989121..37fb269ca 100644
--- a/libc/sysdeps/linux/common/posix_fadvise64.c
+++ b/libc/sysdeps/linux/common/posix_fadvise64.c
@@ -24,9 +24,18 @@ int posix_fadvise64(int fd, off64_t offset, off64_t len, int advice)
{
INTERNAL_SYSCALL_DECL (err);
/* ARM has always been funky. */
-# if defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) || defined(__arm__)
+#if defined (__arm__) || \
+ (defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) && (defined(__powerpc__) || defined(__xtensa__)))
+ /* arch with 64-bit data in even reg alignment #1: [powerpc/xtensa]
+ * custom syscall handler (rearranges @advice to avoid register hole punch) */
int ret = INTERNAL_SYSCALL (fadvise64_64, err, 6, fd, advice,
OFF64_HI_LO (offset), OFF64_HI_LO (len));
+#elif defined(__UCLIBC_SYSCALL_ALIGN_64BIT__)
+ /* arch with 64-bit data in even reg alignment #2: [arcv2/others-in-future]
+ * stock syscall handler in kernel (reg hole punched) */
+ int ret = INTERNAL_SYSCALL (fadvise64_64, err, 7, fd, 0,
+ OFF64_HI_LO (offset), OFF64_HI_LO (len),
+ advice);
# else
int ret = INTERNAL_SYSCALL (fadvise64_64, err, 6, fd,
OFF64_HI_LO (offset), OFF64_HI_LO (len),