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authorGiuseppe Cavallaro <peppe.cavallaro@st.com>2010-12-13 11:39:36 +0100
committerCarmelo Amoroso <carmelo.amoroso@st.com>2010-12-14 08:08:36 +0100
commit640220faf25659eb4c15b78cf8869251dbadbd16 (patch)
tree763b66c4480ea9839f80afe2b1672ca2f24aa139 /libc/string/sh/sh4/memcpy.S
parent1f674977c0f3ea1e67deea93fa8f4e795cc869ad (diff)
sh: fix memcpy saving/restoring FR12-FR15 registers
This patch fixes a bug in the memcpy that doesn't save/restore the FR12-FR15 registers (callee save registers in ST40 ABI) while copying many cache lines with FPU in single paired precision mode and by using all FPU registers (DR and XD). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Carmelo Amoroso <carmelo.amoroso@st.com> Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Diffstat (limited to 'libc/string/sh/sh4/memcpy.S')
-rw-r--r--libc/string/sh/sh4/memcpy.S18
1 files changed, 15 insertions, 3 deletions
diff --git a/libc/string/sh/sh4/memcpy.S b/libc/string/sh/sh4/memcpy.S
index 5be770a59..6a229a06c 100644
--- a/libc/string/sh/sh4/memcpy.S
+++ b/libc/string/sh/sh4/memcpy.S
@@ -497,6 +497,12 @@ ENTRY(memcpy)
mov r5, r6
add #-0x80, r6 ! prefetch head
+ ! store FPU (in single precision mode, do not check R15 align).
+ fmov fr12, @-r15
+ fmov fr13, @-r15
+ fmov fr14, @-r15
+ fmov fr15, @-r15
+
FPU_SET_PAIRED_PREC
mov #4, r0
@@ -553,16 +559,22 @@ ENTRY(memcpy)
bt/s 67b
pref @r6
+ RESTORE_FPSCR
+
+ ! Restore FPU callee save registers
+ fmov @r15+, fr15
+ fmov @r15+, fr14
+ fmov @r15+, fr13
+ fmov @r15+, fr12
+
! Other cache lines could be copied: so use the FPU in single paired
! precision without prefetching. No check for alignment is necessary.
mov #1, r0
cmp/ge r0, r3
- bt/s 4f
+ bt/s 3f
add #0x60, r5
- RESTORE_FPSCR
-
bra 5f
nop