diff options
Diffstat (limited to 'toolchain/elf2flt/patches/v2021.08')
5 files changed, 213 insertions, 23 deletions
diff --git a/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch b/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch index 278709cb1..616bbc891 100644 --- a/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch +++ b/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch @@ -1,8 +1,7 @@ -From 65ac5f9e69cfb989d970da74c41e478774d29be5 Mon Sep 17 00:00:00 2001 +From a8c9f650b82109abf7aa730f298ea5182ed62613 Mon Sep 17 00:00:00 2001 From: Niklas Cassel <niklas.cassel@wdc.com> Date: Tue, 9 Aug 2022 21:06:05 +0200 -Subject: [PATCH] elf2flt: fix fatal error regression on m68k, xtensa, - riscv64 +Subject: [PATCH] elf2flt: fix fatal error regression on m68k, xtensa, riscv64 Commit ba379d08bb78 ("elf2flt: fix for segfault on some ARM ELFs") changed the condition of which input sections that should be included @@ -12,16 +11,15 @@ to: ((a->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == (SEC_DATA | SEC_READONLY | SEC_RELOC)) -On ARM, the .eh_frame input section does not have the SEC_RELOC flag -set, so this specific change had no effect on ARM. +On ARM, the .eh_frame input section does not have the SEC_RELOC flag set, +so on ARM, this change caused .eh_frame to move from .text to .data. -However, on e.g. m68k and riscv64, the .eh_frame input section does -have the SEC_RELOC flag set, which means that after commit ba379d08bb78 -("elf2flt: fix for segfault on some ARM ELFs"), read-only relocation -data sections were placed in .text output section, instead of .data -output section. +However, on e.g. m68k, xtensa and riscv64, the .eh_frame input section +does have the SEC_RELOC flag set, which means that the change in +commit ba379d08bb78 ("elf2flt: fix for segfault on some ARM ELFs") +caused .eh_frame to move in an opposite way, i.e. from .data to .text. -This will result in a fatal error on m68k, xtensa and riscv64: +This resulted in a fatal error on m68k, xtensa and riscv64: ERROR: text=0x3bab8 overlaps data=0x33f60 ? This is because elf2flt cannot append to .text after .data has been @@ -36,21 +34,26 @@ to .text after .data has been appended to (which will require elf2flt to move/relocate everything that has already been appended to .data, since the virtual addresses are contiguous). -However, for now, add an exception for m68k, xtensa and riscv64 -(specifically for the problematic input section, .eh_frame), so that we -get the same behavior as older elf2flt releases, where we put read-only -relocation data in .data, which was working perfectly fine. +However, for now, add an exception for input sections which have all +three flags SEC_DATA, SEC_READONLY, and SEC_RELOC set, and which have a +name equal to a problematic input section (.eh_frame, .gcc_except_table). +That way, we get the same behavior as older elf2flt releases for m68k, +xtensa and riscv64, where we put read-only relocation data in .data, +which was working perfectly fine. + +This exception will not change any behavior on ARM, as the .eh_frame +input section does not have flag SEC_RELOC set. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> --- - elf2flt.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) + elf2flt.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/elf2flt.c b/elf2flt.c -index 9c32f9a..a680c89 100644 +index e0d7891..39d035f 100644 --- a/elf2flt.c +++ b/elf2flt.c -@@ -340,8 +340,15 @@ compare_relocs (const void *pa, const void *pb) +@@ -341,8 +341,13 @@ compare_relocs (const void *pa, const void *pb) static bool ro_reloc_data_section_should_be_in_text(asection *s) { @@ -58,10 +61,8 @@ index 9c32f9a..a680c89 100644 - (SEC_DATA | SEC_READONLY | SEC_RELOC); + if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == + (SEC_DATA | SEC_READONLY | SEC_RELOC)) { -+#if defined(TARGET_m68k) || defined(TARGET_riscv64) || defined(TARGET_xtensa) -+ if (!strcmp(".eh_frame", s->name)) ++ if (!strcmp(".eh_frame", s->name) || !strcmp(".gcc_except_table", s->name)) + return false; -+#endif + return true; + } + return false; @@ -69,5 +70,5 @@ index 9c32f9a..a680c89 100644 static uint32_t * -- -2.37.1 +2.39.0 diff --git a/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch new file mode 100644 index 000000000..fc8784a1b --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch @@ -0,0 +1,25 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-09 11:08:28.637676113 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-01-09 11:09:04.502804007 +0100 +@@ -835,7 +835,20 @@ + continue; + case R_XTENSA_32: + case R_XTENSA_PLT: +- goto good_32bit_resolved_reloc; ++ if (bfd_big_endian (abs_bfd)) ++ sym_addr = ++ (r_mem[0] << 24) ++ + (r_mem[1] << 16) ++ + (r_mem[2] << 8) ++ + r_mem[3]; ++ else ++ sym_addr = ++ r_mem[0] ++ + (r_mem[1] << 8) ++ + (r_mem[2] << 16) ++ + (r_mem[3] << 24); ++ relocation_needed = 1; ++ break; + default: + goto bad_resolved_reloc; + #elif defined(TARGET_riscv64) diff --git a/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch new file mode 100644 index 000000000..b3c4677be --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch @@ -0,0 +1,56 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-02-26 11:31:48.758810872 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-02-26 11:32:05.714465277 +0100 +@@ -81,7 +81,7 @@ + #include <elf/v850.h> + #elif defined(TARGET_xtensa) + #include <elf/xtensa.h> +-#elif defined(TARGET_riscv64) ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32) + #include <elf/riscv.h> + #endif + +@@ -127,6 +127,8 @@ + #define ARCH "xtensa" + #elif defined(TARGET_riscv64) + #define ARCH "riscv64" ++#elif defined(TARGET_riscv32) ++#define ARCH "riscv32" + #else + #error "Don't know how to support your CPU architecture??" + #endif +@@ -849,12 +851,21 @@ + break; + default: + goto bad_resolved_reloc; +-#elif defined(TARGET_riscv64) ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32) + case R_RISCV_32_PCREL: ++ case R_RISCV_ADD8: ++ case R_RISCV_ADD16: + case R_RISCV_ADD32: + case R_RISCV_ADD64: ++ case R_RISCV_SUB6: ++ case R_RISCV_SUB8: ++ case R_RISCV_SUB16: + case R_RISCV_SUB32: + case R_RISCV_SUB64: ++ case R_RISCV_SET6: ++ case R_RISCV_SET8: ++ case R_RISCV_SET16: ++ case R_RISCV_SET32: + continue; + case R_RISCV_32: + case R_RISCV_64: +diff -Nur elf2flt-v2021.08.orig/ld-elf2flt.c elf2flt-v2021.08/ld-elf2flt.c +--- elf2flt-v2021.08.orig/ld-elf2flt.c 2023-02-26 11:31:21.047376888 +0100 ++++ elf2flt-v2021.08/ld-elf2flt.c 2023-02-26 11:32:05.714465277 +0100 +@@ -327,7 +327,7 @@ + /* riscv adds a global pointer symbol to the linker file with the + "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and + the entire line for other architectures. */ +- if (streq(TARGET_CPU, "riscv64")) ++ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32")) + append_sed(&sed, "^RISCV_GP:", ""); + else + append_sed(&sed, "^RISCV_GP:", NULL); diff --git a/toolchain/elf2flt/patches/v2021.08/0008-remove_BFD_VMA_FMT.patch b/toolchain/elf2flt/patches/v2021.08/0008-remove_BFD_VMA_FMT.patch new file mode 100644 index 000000000..6367f1383 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0008-remove_BFD_VMA_FMT.patch @@ -0,0 +1,97 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-29 16:47:24.791851890 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-01-29 16:49:46.628476326 +0100 +@@ -222,7 +222,7 @@ + long i; + printf("SYMBOL TABLE:\n"); + for (i=0; i<number_of_symbols; i++) { +- printf(" NAME=%s VALUE=0x%"BFD_VMA_FMT"x\n", ++ printf(" NAME=%s VALUE=0x%x\n", + symbol_table[i]->name, symbol_table[i]->value); + } + printf("\n"); +@@ -471,7 +471,7 @@ + if (r == NULL) + continue; + if (verbose) +- printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%"BFD_VMA_FMT"x\n", ++ printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%x\n", + r->name, r, r->flags, elf2flt_bfd_section_vma(r)); + if ((r->flags & SEC_RELOC) == 0) + continue; +@@ -966,8 +966,8 @@ + if (verbose) + fprintf(stderr, + "%s vma=0x%x, " +- "value=0x%"BFD_VMA_FMT"x, " +- "address=0x%"BFD_VMA_FMT"x " ++ "value=0x%x, " ++ "address=0x%x " + "sym_addr=0x%x rs=0x%x, opcode=0x%x\n", + "ABS32", + sym_vma, (*(q->sym_ptr_ptr))->value, +@@ -985,8 +985,8 @@ + if (verbose) + fprintf(stderr, + "%s vma=0x%x, " +- "value=0x%"BFD_VMA_FMT"x, " +- "address=0x%"BFD_VMA_FMT"x " ++ "value=0x%x, " ++ "address=0x%x " + "sym_addr=0x%x rs=0x%x, opcode=0x%x\n", + "PLT32", + sym_vma, (*(q->sym_ptr_ptr))->value, +@@ -1008,7 +1008,7 @@ + case R_V850_ZDA_16_16_OFFSET: + case R_V850_ZDA_16_16_SPLIT_OFFSET: + /* Can't support zero-relocations. */ +- printf ("ERROR: %s+0x%"BFD_VMA_FMT"x: zero relocations not supported\n", ++ printf ("ERROR: %s+0x%x: zero relocations not supported\n", + sym_name, q->addend); + continue; + #endif /* TARGET_v850 */ +@@ -1208,9 +1208,9 @@ + temp |= (exist_val & 0x3f); + *(unsigned long *)r_mem = htoniosl(temp); + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x) GPREL\n", ++ "fixup=0x%x (reloc=0x%x) GPREL\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); +@@ -1228,9 +1228,9 @@ + exist_val |= ((sym_addr & 0xFFFF) << 6); + *(unsigned long *)r_mem = htoniosl(exist_val); + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x) PCREL\n", ++ "fixup=0x%x (reloc=0x%x) PCREL\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); +@@ -1245,7 +1245,7 @@ + && (p[-1]->sym_ptr_ptr == p[0]->sym_ptr_ptr) + && (p[-1]->addend == p[0]->addend)) { + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d LO16\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size); +@@ -1660,9 +1660,9 @@ + */ + if (relocation_needed) { + if (verbose) +- printf(" RELOC[%d]: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf(" RELOC[%d]: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x)\n", ++ "fixup=0x%x (reloc=0x%x)\n", + flat_reloc_count, + q->address, sym_name, addstr, + section_name, sym_reloc_size, diff --git a/toolchain/elf2flt/patches/v2021.08/0009-riscv.patch b/toolchain/elf2flt/patches/v2021.08/0009-riscv.patch new file mode 100644 index 000000000..c1072cb45 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0009-riscv.patch @@ -0,0 +1,11 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-02-26 11:32:05.714465277 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-02-26 15:04:52.726514896 +0100 +@@ -852,6 +852,7 @@ + default: + goto bad_resolved_reloc; + #elif defined(TARGET_riscv64) || defined(TARGET_riscv32) ++ case R_RISCV_NONE: + case R_RISCV_32_PCREL: + case R_RISCV_ADD8: + case R_RISCV_ADD16: |