Age | Commit message (Collapse) | Author |
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Poschwatta
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The attached patch adds support for compiling arm uClibc as pure Thumb code.
This is needed because some recent ARM codes do not implement traditional ARM
mode. Specifically:
* Cortex-M1 - An extremely minimal FPGA based core that only implements
Thumb-1 (aka ARMv6-M).
* Cortex-M3 - A Thumb-2 only ARMv7-M core.
Most of uClibc already builds in Thumb mode, all that is left are a handful of
assembly bits.
Tested on arm-uclinuxeabi.
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Signed-off-by: Chris Zankel <chris@zankel.net>
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This patch uses the HIDDEN_JUMPTARGET instead of the __GI_ prefix in AVR32
assembler files. This is done to follow the code style in uClibc.
Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
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in libc to avoid having to place executable code on stack.
Signed-off-by: Chris Zankel <chris@zankel.net>
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skinkie in #2194
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allocations, dma_memcpy to move stuff between L1 and main memory, and a new
structure to describe the global data in L1 scratchpad memory.
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a problem where the linker was trying to use the wrong symbol name for the
init function.
Define SYMBOL_PREFIX as _ in Rules.mak for h8300, bfin, i960,
microblaze, and v850. Add -D__UCLIBC_UNDERSCORES__ in CFLAGS for targets
which define SYMBOL_PREFIX as _. Remove defines and undefs from
uClibc_arch_features.h of each target.
Add $(SYMBOL_PREFIX) to __uClibc_init when passed by ld option -init.
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doing double negatives
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This was one of the stragglers still bent on __uClibc_start_main
utilization, now it's only FR-V.
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generalizes what Blackfin was already doing)
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The following patches add support for the Xtensa processor architecture
to uClibc. They are based on a recent SVN checkout (12/05/2007).
The first patch (attached to this post) adds Xtensa support to various
shared configuration and make files. The following patches then include
the Xtensa specific files and directories.
I welcome any feedback and would appreciate it if you could include the
patches into the mainline tree. I am certainly committed to maintain the port.
Bob Wilson was kind enough to review the patches.
Some notes about the architecture: Xtensa is a configurable and
extensible processor architecture developed by Tensilica. For more
information, please visit: www.linux-xtensa.org.
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On an i386 platform with no rt_sigsuspend syscall (ie: Linux 2.0), compilation will halt on libc/sysdeps/linux/common/sigsuspend.os with a cryptic error message:
"Error: non-constant expression in ".if" statement"
I've investigated and found that the cause is that a literal '0' is being passed into a block of complex assembler macrology that is only prepared to deal with register names - '%eax', etc.
In turn, that seems to be because of a typo in the GCC register constraints. The constraints for 2 and 3-argument syscalls includes a "C" constraint. To gcc, "C" means an SSE floating point constant -- an unlikely element in a syscall. I suspect the author meant to type "S" (%esi).
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getcwd syscall has an off-by-one allocation bug. As a result, sometimes the returned string has garbage at the end.
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sa_restorer when SA_ONSTACK is set, but it seems to break LTP's
sigaltstack testcase. Some users have reported problems with
sigaltstack as well; hopefully this will fix it.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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__bswap_16 could not assume that it's zero extended when an unsigned short int is loaded into the data register.
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create these for deleted entries in .eh_frame.
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undefined structure. This typedef is used in linuxthreads.old-db, causing a
compilation failure. Fixed by defining an empty structure for it - we don't
have fp regs anyway.
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common directory where SHMLBA = __getpagesize()
This patch fixes the issue.
Khem Raj
MontaVista Software Inc.
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<hcegtvedt@atmel.com>
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Jean-Christian de Rivaz writes:
The attached patch solve an issue I faced while using the libdbus-glib
waiting for a D-Bus message or the end of a glib timer at the same time.
This specific case of use generate a poll call with a zero timeout. On
platformes with the glibc a zero timeout poll return immetiately even if
there is no file descriptor event. But on platformes with uClibc a zero
timeout poll block until a file descriptor event occurs.
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This wants a stub_enosys(readahead) line later on, like many, many others need..
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I got the library to compile with the attached patches, though dynamic
loader crashes early.
In buildroot I changed the architecture name by hand from sparc to
sparc64, otherwise the compiler produced 32-bit files with V9 (64-bit)
instructions. This configuration is not supported by QEMU, so I aimed
for pure 64-bit. I think Sparc64 option needs to be added to
buildroot.
The _Qp_ ops seem to be required by the ABI. This and setjmp patches
are just hacks to get the compilation further. The _Qp_ ops can be
found in glibc, would it be OK to use those?
V9 assembler requires declarations for global register use.
The mem* functions in sparc32 directory did not work. They are
actually used only by the hybrid 32-bit + V9 CPU configuration.
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In MIPS syscall(2), .cpload was added to an the error path, but it was
not enough for ABIs other then O32. Use SETUP_GP, SETUP_GP64 and
RESTORE_GP64 to handle all ABIs. This patch fixes an error path of
MIPS pipe(2) too.
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from i386 and x86_64.
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Make msync.c agree on this.
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them enabled, so let's go all the way. There was a quick discussion on IRC about making the max baud rate configurable. That requires a bunch of #ifdef salting throughout all of the 'termios.h' files for the pre-processor to chew on. I'm going to pass on that for now.
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else.
- internal_function is only used inside libc, so do not define it in
uClibc_arch_features.h on i386 if we are outside of libc.
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Hi All,
this patch fixes a mismatch in ucontext struct between uClibc and kernel.
In this way a signal handler installed by sigaction can access
to the whole machine state correctly.
This can be applied both to trunk and nptl branch
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Current MIPS readahead(), posix_fadvise(), posix_fadvise64() do not
match with kernel on all ABIs.
On O32 ABI, a padding is needed before a long long argument.
On N32/N64, a long long argument should be passed via a single register.
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