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ARMv8 has particular restrictions which coprocessor can be used and as
such these instructions, which were likely used for backwards
compatibility purposes, cannot be used on ARMv8. We solve this by
checking for ARMv8 and then using the corresponding mnemonics which were
placed in comments alongside the instructions causing issues.
Fixes the following errors:
.../setjmp.S:59:6: error: invalid operand for instruction
stc p11, cr8, [r12], #68
^
.../setjmp.S:62:6: error: invalid operand for instruction
mrc p10, 7, r2, cr1, cr0, 0
^
.../__longjmp.S:69:6: error: invalid operand for instruction
ldc p11, cr8, [r12], #68
^
.../__longjmp.S:73:6: error: invalid operand for instruction
mcr p10, 7, r1, cr1, cr0, 0
^
Signed-off-by: Marcus Haehnel <marcus.haehnel@kernkonzept.com>
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Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
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As Will noticed, the header this check is currently done in
is asm-only, and is not meant to be included from C code.
This breaks compilation when compiled for a Thumb2-aware CPU.
Move the BX check to its own header, and revert 7a246fd.
Reported-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
Cc: Will Newton <will.newton@gmail.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
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This matches a similar change made to glibc.
No functional changes here.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Peter S. Mazinger <ps.m@gmx.net>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
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The attached patch adds support for compiling arm uClibc as pure Thumb code.
This is needed because some recent ARM codes do not implement traditional ARM
mode. Specifically:
* Cortex-M1 - An extremely minimal FPGA based core that only implements
Thumb-1 (aka ARMv6-M).
* Cortex-M3 - A Thumb-2 only ARMv7-M core.
Most of uClibc already builds in Thumb mode, all that is left are a handful of
assembly bits.
Tested on arm-uclinuxeabi.
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This patch fixes some of the ARM EABI code to be interworking-safe, using
bx where appropriate. (This code went in around the same time as the
Thumb patches, hence not being fixed by those patches.)
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The patch fixes up the .align directives to '2' (i.e. a multiple
of 4) not '4' (a multiple of 16 - apparently an error since it seems
to be unnecessary, there is no advantage here in cache line alignment).
this is an arm "feature" ... the value given to .align is not in bytes:
.align 4 in arm means .align 2 ^ 4
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missing headers, other jump relocs removed
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http://yann.poupet.free.fr/ep93xx/
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patch from Vadim Lebedev <vadim@7chips.com>.
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-Erik
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on both x86 and arm...
-Erik
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