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This is next gen Instruction Set Architecture from Synopsys and basis
for the ARC HS family of processors.
http://www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor&elq_mid=5732&elq_cid=458802
http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/arc-hs/Pages/default.aspx
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
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ARC CPU may have MMU page size of 4/8(default)/16k.
uClibc needs to have page size configured accodring to HW it will be run on.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
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ARC CPU may have MMU page size of 4/8(default)/16k.
uClibc needs to have page size configured accodring to HW it will be run on.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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For this port, I would like to give due credit to:
- Folks from Codito technologies (Sameer, Amit, Kanika, Ramana,...)
who did the very first port
- ARC UK from 2007-2009 (Joern, Irfan, Khurram, Phil...
- Late Brendan Kehoe (may he RIP)
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
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