| Age | Commit message (Collapse) | Author |
|---|
|
For instance with buildroot config sipeed_maix_bit_defconfig the pre-processor generates
if (1)
r = ({ long _sys_result; { register long int _a7 __asm__ ("a7"); register long _a3 __asm__ ("a3"); long _a3tmp; register long _a2 __asm__ ("a2"); long _a2tmp; register long _a1 __asm__ ("a1"); long _a1tmp; long _a0tmp; register long _a0 __asm__ ("a0"); _a0tmp = (long) (clock_id); _a0 = _a0tmp; _a1tmp = (long) (flags); _a1 = _a1tmp; _a2tmp = (long) (req); _a2 = _a2tmp; _a3tmp = (long) (rem); _a3 = _a3tmp; _a7 = (115); __asm__ volatile ( "scall\n\t" : "=r" (_a0) : "r"(_a7) , "r" (_a0), "r" (_a1), "r" (_a2), "r" (_a3) : "memory"); _sys_result = _a0; } _sys_result; });
else
{
int oldstate = LIBC_CANCEL_ASYNC ();
r = ({ long _sys_result; { register long int _a7 __asm__ ("a7"); register long _a3 __asm__ ("a3"); long _a3tmp; register long _a2 __asm__ ("a2"); long _a2tmp; register long _a1 __asm__ ("a1"); long _a1tmp; long _a0tmp; register long _a0 __asm__ ("a0"); _a0tmp = (long) (clock_id); _a0 = _a0tmp; _a1tmp = (long) (flags); _a1 = _a1tmp; _a2tmp = (long) (req); _a2 = _a2tmp; _a3tmp = (long) (rem); _a3 = _a3tmp; _a7 = (115); __asm__ volatile ( "scall\n\t" : "=r" (_a0) : "r"(_a7) , "r" (_a0), "r" (_a1), "r" (_a2), "r" (_a3) : "memory"); _sys_result = _a0; } _sys_result; })
;
LIBC_CANCEL_RESET (oldstate);
}
And also the compiler issues these warnings:
librt/clock_nanosleep.c: In function 'clock_nanosleep':
librt/clock_nanosleep.c:43:22: warning: implicit declaration of function
'LIBC_CANCEL_ASYNC'; did you mean 'LIBC_CANCEL_HANDLED'?
[-Wimplicit-function-declaration]
43 | int oldstate = LIBC_CANCEL_ASYNC ();
| ^~~~~~~~~~~~~~~~~
| LIBC_CANCEL_HANDLED
librt/clock_nanosleep.c:48:7: warning: implicit declaration of function
'LIBC_CANCEL_RESET'; did you mean 'LIBC_CANCEL_HANDLED'?
[-Wimplicit-function-declaration]
48 | LIBC_CANCEL_RESET (oldstate);
| ^~~~~~~~~~~~~~~~~
| LIBC_CANCEL_HANDLED
So if the compiler is a bit picky and does not optimize the if (1) {} else {} it can fail to link with undefined symbols.
This patch fixes this issue: no more warning.
Btw, that's the solution that is already used in the following cancellation point files:
* libc/sysdeps/linux/common/__syscall_fcntl.c
* libc/sysdeps/linux/common/__syscall_fcntl64.c
* libc/sysdeps/linux/common/ioctl.c
* libc/sysdeps/linux/common/openat.c
* libc/sysdeps/linux/common/open.c
Signed-off-by: Yann Sionneau <yann@sionneau.net>
|
|
This reverts commit 08d46f1ce21e4ec51b2b1626beeaea6cbe7fdc6b.
Signed-off-by: Yann Sionneau <yann@sionneau.net>
|
|
|
|
|
|
|
|
See here for details:
https://sourceware.org/bugzilla/show_bug.cgi?id=28509
|
|
Added definition for MAP_FIXED_NOREPLACE which was added in kernel 4.17
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
Changed linux thread's stack allocation mmap to use new MAP_FIXED_NOREPLACE flag on kernels >4.17.
For older kernels, a check is added to see if requested address matches the address received.
If the addresses don't match, an error is returned and thread creation is aborted.
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
Signed-off-by: Evgeniy Manachkin <sfstudio@wi-cat.ru>
|
|
|
|
|
|
|
|
on MIPS.
Signed-off-by: Evgeniy Manachkin <sfstudio@wi-cat.ru>
|
|
Added 32-bit RISC-V support. I have managed to get 32-bit RISC-V No-MMU
Linux running based on mainstream buildroot. It's nice to have uclibc
support this 32-bit No-MMU target.
There's no substantial code change except definations and config
options.
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
|
|
Modified config files and crt1.S to support static pie elf generation.
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
Add ability to use optimized versions of string functions for ARCv3 32-bit
CPUs with UCLIBC_HAS_STRING_ARCH_OPT option. Add optimized
memcpy/memset/memcmp code for ARCv3 CPUs based on the code from newlib
and adapt for ARCv3 existed optimized strchr/strcmp/strcpy/strlen.
Link to the Synopsys newlib repo with code for ARCv3 on GitHub:
https://github.com/foss-for-synopsys-dwc-arc-processors/newlib
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
|
|
New ARCv3 ISA includes both 64-bit and 32-bit CPU family.
This patch adds support for 32-bit ARCv3 HS5x processors.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
|
|
Add a header file with assembler macros to be able to handle in one
place the differences between ARCv2 and ARCv3 ISAs. It is a preparatory
step before the introduction of support for ARCv3 CPUs.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
|
|
Option '-mno-long-calls' is not supported by all arc gcc compilers.
For instance, this option is not supported by GCC for ARCv3 processors.
Check if this option is supported before applying it.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
|
|
Add missing ARCv2 check in MATCH_MACHINE macro.
Update comment for EM_ARCV2 define.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
|
|
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
Xtensa does not define PERFORM_BOOTSTRAP_RELOC so it doesn't need
ARCH_NEEDS_BOOTSTRAP_RELOCS definition. Remove it.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
Xtensa PERFORM_BOOTSTRAP_GOT macro uses mprotect to make bits of GOT
writable, but noMMU linux kernel returns ENOSYS to mprotect syscalls,
and syscall wrapper tries to update errno with the error code. This
happens well before the relocations are done and results in writes to
unrelated locations, memory corruption or protection violations.
Only define PERFORM_BOOTSTRAP_GOT when building xtensa configuration
with MMU support.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
3 architectures currently define PERFORM_BOOTSTRAP_GOT: avr32, mips and
xtensa. A block of code that applies relative relocations in the
DL_START is disabled when PERFORM_BOOTSTRAP_GOT is defined, unless it's
avr32 or mips, effectively disabling it only for xtensa.
This may be simplified by removing the call to elf_machine_relative from
the xtensa PERFORM_BOOTSTRAP_GOT and always using common code.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
When uclibc is built with static PIE support the _dl_load_base variable
shared between the libc-tls.c and reloc_static_pie.c creates the
dependency that requires linking reloc_static_pie.o into static
position-dependent executables resulting in the following build errors:
gcc -static test.c -o test
...ld:
...usr/lib/libc.a(reloc_static_pie.os):(.text+0x0):
undefined reference to `_DYNAMIC'
Move _dl_load_base definition to libc-tls.c to resolve this dependency
and fix static PDE build.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
Static PIE ELFs may be loaded on noMMU linux platforms with FDPIC
support, but they don't have adjustable brk, and thus cannot allocate
memory for the TLS. Use mmap instead of sbrk to allocate initial TLS
memory when building with static PIE support for noMMU.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
on mips
Updated config to allow compilation of rcrt1.o for mips and modified it's crt1.S to perform relocates in __start.
The mips architecture performs relocations differently then most other architectures. reloc_static_pie was rewritten, taking code from dl-startup.c, in order to perfrom the additional relocations. Modifications were made to mips' dl-startup.h to allow for the use of contained macros without including _start definition.
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
|
|
Patch suggested by Thomas Petazzoni and tested by me.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
|
on aarch64
Updated config to allow compilation of rcrt1.o for aarch64 and modified it's crt1.S to relocate dynamic section prior to __uClibc_main.
Disabled stack protector when compiling reloc_static_pie.c to avoid TLS access prior to it being setup.
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
There is a real-world usage of RUSAGE_THREAD by the pistache project,
https://github.com/oktal/pistache.
Reported-By: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
|
on i386, x86_64, and arm.
This patch adds the generation of rcrt1.o which is used by gcc when compiling with the --static-pie flag.
rcrt1.o differs from crt1.o and Scrt1.o in that it the executable has a dynamic section but no relocations have been performed prior to _start being called.
crt1.o assumes there to be no dynamic relocations, and Scrt1.o has all relocations performed prior to execution by lsdo.
The new reloc_static_pie function handles parsing the dynamic section, and performing the relocations in a architecture agnostic method.
It also sets _dl_load_base which is used when initalizing TLS to ensure loading from the proper location.
This allows for easier porting of static-pie support to additional architectures as only modifications to crt1.S to find the load address are required.
Signed-off-by: linted <linted@users.noreply.github.com>
|
|
Thomas has repored failure building ARM 32-bit systems for ARMv8 cores
CC libpthread/linuxthreads/mutex.os
/tmp/ccn8SFKU.s: Assembler messages:
/tmp/ccn8SFKU.s:162: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:186: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:203: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:224: Error: swp{b} use is obsoleted for ARMv8 and later
make[1]: *** [Makerules:369: libpthread/linuxthreads/mutex.os] Error 1
This is due to libpthread/linuxthreads/sysdeps/arm/pt-machine.h which
uses the swp instruction that is not allowed on ARMv8.
All __ARM_ARCH >= 7 support ldrex/strex instructions, so unlock
testandset() varaint for them.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
|
|
O0 build result in the following codegen
00000000 <ldrex>:
0: b480 push {r7}
2: b085 sub sp, #20
4: af00 add r7, sp, #0
6: 6078 str r0, [r7, #4]
8: 687b ldr r3, [r7, #4]
a: e853 3f00 ldrex r3, [r3]
e: 60fb str r3, [r7, #12]
10: 68fb ldr r3, [r7, #12]
12: 4618 mov r0, r3
14: 3714 adds r7, #20
16: 46bd mov sp, r7
18: f85d 7b04 ldr.w r7, [sp], #4
1c: 4770 bx lr
0000001e <strex>:
1e: b480 push {r7}
20: b085 sub sp, #20
22: af00 add r7, sp, #0
24: 6078 str r0, [r7, #4]
26: 6039 str r1, [r7, #0]
28: 687b ldr r3, [r7, #4]
2a: 683a ldr r2, [r7, #0]
2c: e842 3300 strex r3, r3, [r2]
30: 60fb str r3, [r7, #12]
32: 68fb ldr r3, [r7, #12]
34: 4618 mov r0, r3
36: 3714 adds r7, #20
38: 46bd mov sp, r7
3a: f85d 7b04 ldr.w r7, [sp], #4
3e: 4770 bx lr
00000040 <testandset>:
40: b590 push {r4, r7, lr}
42: b083 sub sp, #12
44: af00 add r7, sp, #0
46: 6078 str r0, [r7, #4]
48: 6878 ldr r0, [r7, #4]
4a: f7ff fffe bl 0 <ldrex>
4e: 4603 mov r3, r0
50: 461c mov r4, r3
52: 6879 ldr r1, [r7, #4]
54: 2001 movs r0, #1
56: f7ff fffe bl 1e <strex>
5a: 4603 mov r3, r0
5c: 2b00 cmp r3, #0
5e: d1f3 bne.n 48 <testandset+0x8>
60: 4623 mov r3, r4
62: 4618 mov r0, r3
64: 370c adds r7, #12
66: 46bd mov sp, r7
68: bd90 pop {r4, r7, pc}
ARM ARM suggests that LoadExcl/StoreExcl loops are guaranteed to make
forward progress only if, for any LoadExcl/StoreExcl loop within a
single thread of execution, the software meets all of the following
conditions:
1 Between the Load-Exclusive and the Store-Exclusive, there are no
explicit memory accesses, preloads, direct or indirect System
register writes, address translation instructions, cache or TLB
maintenance instructions, exception generating instructions,
exception returns, or indirect branches.
...
Obviously condition is not met for O0 builds.
O2 build (which is highly likely the most common setting) able to do
the right thing resulting in
00000000 <ldrex>:
0: e850 0f00 ldrex r0, [r0]
4: 4770 bx lr
6: bf00 nop
00000008 <strex>:
8: e841 0000 strex r0, r0, [r1]
c: 4770 bx lr
e: bf00 nop
00000010 <testandset>:
10: 2101 movs r1, #1
12: 4603 mov r3, r0
14: e853 0f00 ldrex r0, [r3]
18: e843 1200 strex r2, r1, [r3]
1c: 2a00 cmp r2, #0
1e: d1f9 bne.n 14 <testandset+0x4>
20: 4770 bx lr
22: bf00 nop
Rather than depending on level of optimisation implement whole
ldrex/strex loop in inline assembly.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
|
|
See the C11 standard 7.2 §3
The definition is copied from glibc.
Signed-off-by: Nicolas Cavallari <nicolas.cavallari@green-communications.fr>
|
|
Implement getcontext, makecontext, setcontext and swapcontext.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
getaddrinfo() returns addresses from, at least, ip(7) and ipv6(7),
but _addr() always uses sin_addr from struct sockaddr_in;
we're saved from wild unsoundness (or incompatibility)
by virtue of struct sockaddr_in6 having an always-0 u32 sin6_flowinfo
at the same offset, so we end up returning 0 anyway,
but in a round-about and definitely unintended way
Instead, limit the request to AF_INET, and fall through to the end
early, returning the default id=0
Signed-off-by: Ahelenia Ziemiańska <nabijaczleweli@nabijaczleweli.xyz>
|
|
Explicitly include stdint header as logic uses INT[64]_MAX, just
in case for future, even though the chain of headers from existing
includes brings in the definition indirectly as of now.
Cross check for time gap between prngplus reseeding, periodically,
has the internal state is being consumed, so that if there is too
much time gap, then prng reseeding can be forced, before the normal
reseed window is reached. This is useful for long running programs
which trigger dns queries only intermittently.
If clock_gettime is not available, then reseed more frequently, by
default. A platform developer may change the reseed frequence, to
be bit more less often in this case, if needed, by tweaking the
defines in the source.
Signed-off-by: hanishkvc <hanishkvc@gmail.com>
|
|
This borrows getloadavg.c from musl.
getloadavg pops up often. Recently llvm and rust are dependent on it.
glibc and musl have it and no-one actually checks if it's available in your libc.
It's just become way easier to add it in uclibc-ng rather than patch everything else.
Signed-off-by: Lance Fredrickson <lancethepants@gmail.com>
|
|
|
|
This macro exists since Linux 2.6.25 [1] and is defined in glibc
since 2.14 [2] for sparc and most supported architectures.
RLIMIT_RTTIME has been added later for mips [3] and alpha [4].
For example, RLIMIT_RTTIME is needed to build qemu 7.0.0 with
Linux user-land emulation support [5].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=78f2c7db6068fd6ef75b8c120f04a388848eacb5
[2] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=67f86a251e0d36107fe28999281d46e76941c7b9
[3] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=8969f4df1a526aa60dd0bc1c4736cf02104d4a05
[4] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=53c2cb7641bd866398156625ef672bbd2d78a0d8
[5] https://git.qemu.org/?p=qemu.git;a=commitdiff;h=244fd08323088db73590ff2317dfe86f810b51d7
Signed-off-by: Romain Naour <romain.naour@gmail.com>
|
|
Dns lookup logic has been updated to provide a configurable compile
time selection of dns query id generation logics, including random,
where possible, instead of the previous simple counter mode.
This should make dns poison attempts more difficult. The uclibc
developers wish to thank the white hat teams which alerted the
community about the possible weakness in the dns path, given the
increased resources with adversaries today.
Given that embedded systems may or may not have sources for trying
to generate random numbers, and also to try and keep the load on
the system low, by default it uses the standard random prng based
logic to indirectly generate the ids.
However if either urandom or else if realtime clock is available on
the target, then the same is used to reseed the prng periodically
in a slightly non deterministic manner. Also additional transform
(one way where possible) is used to avoid directly exposing the
internal random sequence.
The dns lookup logic maintains its own state wrt the random prng
functions, so that other users of the library's random prng are
not affected wrt their operations with the prng.
Note to Platform developers:
If you want to change from the default prngplus based logic, to one
of the other logics provided, then during compile/config time you can
switch to one of these additional choices wrt dns query id generation,
by using make config and companions.
If your platform doesnt support urandom nor a realtime clock backed
by a source with sufficient resolution, and or for some reason if you
want to revert to previous simple counter, rather than the transformed
random prng plus logic, you can force the same at compile time by
selecting SimpleCounter mode.
If you want to increase the randomness of the generated ids, and dont
mind the increased system load and latency then you could select the
Urandom mode during config. Do note that it will be dipping into the
entropy pool maintained by ur system.
If your target has a system realtime clock available and exposed to
user space, and inturn if you want to keep the underlying logic simple,
you could try using the clock option from the config. However do note
that the clock should have nanosecond resolution to help generate ids
which are plausibly random. Also improvements to processor and or io
performance can affect this.
Wrt the URandom and Clock modes, if there is a failure with generation
of the next random value, the logic tries to fallback to simple counter
mode.
If you want to change the underlying logic to make it more random
and or more simple, look at dnsrand_setup and dnsrand_next.
Signed-off-by: hanishkvc <hanishkvc@gmail.com>
|
|
The ARM implementation of memset has a bug when the fill-value is negative or outside the
[0, 255] range. To reproduce:
char array[256];
memset(array, -5, 256);
This is supposed to fill the array with int8 values -5, -5, -5, ... . On ARM, this does
not work because the implementation assumes the high bytes of the fill-value argument are
already zero. However in this test case they are filled with 1-bits. The aarch64 and x86_64
implementations do not have this problem: they first convert the fill-value to an unsigned
byte following the specification of memset.
With GCC one can use `memset(ptr, (-5 & 0xFF), size)` as a workaround, but for clang
users that does not work: clang optimizes the `& 0xFF` away because it assumes that
memset will do it.
Signed-off-by: Tom Bannink <tombannink@gmail.com>
Acked-by: Peter Korsgaard <peter@korsgaard.com>
|
|
Following test case returns 2, which should be 0.
int main() {
long x = lrint(0.5);
printf("%ld", x);
return 0;
}
Fix from glibc commit 6624dbc07b5a9fb316ed188ef01f65b8eea8b47c
|
|
|
|
When searching for shared libraries, it could happen that redudant '/'
were added to the pathname with would later be reported via dladdr() in
the dli_fname member.
Signed-off-by: Daniel Dorau <d.dorau@avm.de>
|
|
|
|
Defined in kernel v3.14, commit
aab03e05e8f7 ("sched/deadline: Add SCHED_DEADLINE structures & implementation")
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
|
|
|
