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Fixes haveged compile issues in OpenADK and buildroot when
a static toolchain is used.
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Setting signal handler in the kernel and then updating sighandler[sig]
results in a crash if a signal which handler is being changed from
SIG_DFL to a non-default was pending. Improve the race a little and
update the sighandler[sig] before the sigaction syscall. It doesn't
eliminate the race entirely, but fixes this particular failing case.
E.g. this fixes the 100% reproducible segfault in the busybox hush shell
built with FEATURE_EDITING_WINCH on ssh client's terminal window resize,
but in that case there's one more even bigger issue: busybox calls
sigaction with both old and new signal pointers pointing to the same
structure instance, as a result act->sa_handler after the sigaction
syscall is not what the user requested, but the previous handler.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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DES tables take up a huge amount of space in the .bss and they aren't
even variable. Generate constant tables and put them into des_tables.c
and drop constants and code used to generate them from des.c
This saves ~70KBytes of the .bss and ~3KBytes of the total library size:
text data bss dec hex filename
- 618508 25652 89400 733560 b3178 lib/libuClibc-1.0.42.so
+ 685664 25672 19488 730824 b26c8 lib/libuClibc-1.0.42.so
Modified libc passes the DES validation suite from the uclibc-ng-test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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issue with gcc 12
The current definition of __WCHAR_MIN and __WCHAR_MAX are only correct
when wchar_t is an int. This is not the case on ARM/AArch64 where
wchar_t is an unsigned int, or some other architectures where wchar_t
is a long.
The current incorrect definition causes a build issue for example when
building mpd, which uses boost, with gcc 12.x:
In file included from /home/thomas/buildroot/aarch64/host/aarch64-buildroot-linux-uclibc/sysroot/usr/include/boost/integer.hpp:20,
from /home/thomas/buildroot/aarch64/host/aarch64-buildroot-linux-uclibc/sysroot/usr/include/boost/crc.hpp:42,
from ../src/storage/StorageState.cxx:43:
/home/thomas/buildroot/aarch64/host/aarch64-buildroot-linux-uclibc/sysroot/usr/include/boost/integer_traits.hpp:105:69: error: narrowing conversion of ‘-2147483648’ from ‘int’ to ‘wchar_t’ [-Wnarrowing]
105 | public detail::integer_traits_base<wchar_t, WCHAR_MIN, WCHAR_MAX>
| ^
This issue was fixed in glibc in 2013, see bug report
https://sourceware.org/bugzilla/show_bug.cgi?id=15036, and upstream
commit
https://sourceware.org/git/?p=glibc.git;a=commit;h=052aff95782fefe9c63566471063e8b20836bfb8.
Since the i386-specific definition of __WCHAR_MIN and __WCHAR_MAX was
also removed at the same time in glibc, we do the same as part of this
commit.
Reported-by: Clément Ramirez <clement.ramirez@bootlin.com>
With-some-useful-help-from: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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For instance with buildroot config sipeed_maix_bit_defconfig the pre-processor generates
if (1)
r = ({ long _sys_result; { register long int _a7 __asm__ ("a7"); register long _a3 __asm__ ("a3"); long _a3tmp; register long _a2 __asm__ ("a2"); long _a2tmp; register long _a1 __asm__ ("a1"); long _a1tmp; long _a0tmp; register long _a0 __asm__ ("a0"); _a0tmp = (long) (clock_id); _a0 = _a0tmp; _a1tmp = (long) (flags); _a1 = _a1tmp; _a2tmp = (long) (req); _a2 = _a2tmp; _a3tmp = (long) (rem); _a3 = _a3tmp; _a7 = (115); __asm__ volatile ( "scall\n\t" : "=r" (_a0) : "r"(_a7) , "r" (_a0), "r" (_a1), "r" (_a2), "r" (_a3) : "memory"); _sys_result = _a0; } _sys_result; });
else
{
int oldstate = LIBC_CANCEL_ASYNC ();
r = ({ long _sys_result; { register long int _a7 __asm__ ("a7"); register long _a3 __asm__ ("a3"); long _a3tmp; register long _a2 __asm__ ("a2"); long _a2tmp; register long _a1 __asm__ ("a1"); long _a1tmp; long _a0tmp; register long _a0 __asm__ ("a0"); _a0tmp = (long) (clock_id); _a0 = _a0tmp; _a1tmp = (long) (flags); _a1 = _a1tmp; _a2tmp = (long) (req); _a2 = _a2tmp; _a3tmp = (long) (rem); _a3 = _a3tmp; _a7 = (115); __asm__ volatile ( "scall\n\t" : "=r" (_a0) : "r"(_a7) , "r" (_a0), "r" (_a1), "r" (_a2), "r" (_a3) : "memory"); _sys_result = _a0; } _sys_result; })
;
LIBC_CANCEL_RESET (oldstate);
}
And also the compiler issues these warnings:
librt/clock_nanosleep.c: In function 'clock_nanosleep':
librt/clock_nanosleep.c:43:22: warning: implicit declaration of function
'LIBC_CANCEL_ASYNC'; did you mean 'LIBC_CANCEL_HANDLED'?
[-Wimplicit-function-declaration]
43 | int oldstate = LIBC_CANCEL_ASYNC ();
| ^~~~~~~~~~~~~~~~~
| LIBC_CANCEL_HANDLED
librt/clock_nanosleep.c:48:7: warning: implicit declaration of function
'LIBC_CANCEL_RESET'; did you mean 'LIBC_CANCEL_HANDLED'?
[-Wimplicit-function-declaration]
48 | LIBC_CANCEL_RESET (oldstate);
| ^~~~~~~~~~~~~~~~~
| LIBC_CANCEL_HANDLED
So if the compiler is a bit picky and does not optimize the if (1) {} else {} it can fail to link with undefined symbols.
This patch fixes this issue: no more warning.
Btw, that's the solution that is already used in the following cancellation point files:
* libc/sysdeps/linux/common/__syscall_fcntl.c
* libc/sysdeps/linux/common/__syscall_fcntl64.c
* libc/sysdeps/linux/common/ioctl.c
* libc/sysdeps/linux/common/openat.c
* libc/sysdeps/linux/common/open.c
Signed-off-by: Yann Sionneau <yann@sionneau.net>
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This reverts commit 08d46f1ce21e4ec51b2b1626beeaea6cbe7fdc6b.
Signed-off-by: Yann Sionneau <yann@sionneau.net>
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See here for details:
https://sourceware.org/bugzilla/show_bug.cgi?id=28509
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Added definition for MAP_FIXED_NOREPLACE which was added in kernel 4.17
Signed-off-by: linted <linted@users.noreply.github.com>
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Changed linux thread's stack allocation mmap to use new MAP_FIXED_NOREPLACE flag on kernels >4.17.
For older kernels, a check is added to see if requested address matches the address received.
If the addresses don't match, an error is returned and thread creation is aborted.
Signed-off-by: linted <linted@users.noreply.github.com>
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Signed-off-by: Evgeniy Manachkin <sfstudio@wi-cat.ru>
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on MIPS.
Signed-off-by: Evgeniy Manachkin <sfstudio@wi-cat.ru>
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Added 32-bit RISC-V support. I have managed to get 32-bit RISC-V No-MMU
Linux running based on mainstream buildroot. It's nice to have uclibc
support this 32-bit No-MMU target.
There's no substantial code change except definations and config
options.
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
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Modified config files and crt1.S to support static pie elf generation.
Signed-off-by: linted <linted@users.noreply.github.com>
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Add ability to use optimized versions of string functions for ARCv3 32-bit
CPUs with UCLIBC_HAS_STRING_ARCH_OPT option. Add optimized
memcpy/memset/memcmp code for ARCv3 CPUs based on the code from newlib
and adapt for ARCv3 existed optimized strchr/strcmp/strcpy/strlen.
Link to the Synopsys newlib repo with code for ARCv3 on GitHub:
https://github.com/foss-for-synopsys-dwc-arc-processors/newlib
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
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New ARCv3 ISA includes both 64-bit and 32-bit CPU family.
This patch adds support for 32-bit ARCv3 HS5x processors.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
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Add a header file with assembler macros to be able to handle in one
place the differences between ARCv2 and ARCv3 ISAs. It is a preparatory
step before the introduction of support for ARCv3 CPUs.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
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Option '-mno-long-calls' is not supported by all arc gcc compilers.
For instance, this option is not supported by GCC for ARCv3 processors.
Check if this option is supported before applying it.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
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Add missing ARCv2 check in MATCH_MACHINE macro.
Update comment for EM_ARCV2 define.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
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Signed-off-by: linted <linted@users.noreply.github.com>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Xtensa does not define PERFORM_BOOTSTRAP_RELOC so it doesn't need
ARCH_NEEDS_BOOTSTRAP_RELOCS definition. Remove it.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Xtensa PERFORM_BOOTSTRAP_GOT macro uses mprotect to make bits of GOT
writable, but noMMU linux kernel returns ENOSYS to mprotect syscalls,
and syscall wrapper tries to update errno with the error code. This
happens well before the relocations are done and results in writes to
unrelated locations, memory corruption or protection violations.
Only define PERFORM_BOOTSTRAP_GOT when building xtensa configuration
with MMU support.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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3 architectures currently define PERFORM_BOOTSTRAP_GOT: avr32, mips and
xtensa. A block of code that applies relative relocations in the
DL_START is disabled when PERFORM_BOOTSTRAP_GOT is defined, unless it's
avr32 or mips, effectively disabling it only for xtensa.
This may be simplified by removing the call to elf_machine_relative from
the xtensa PERFORM_BOOTSTRAP_GOT and always using common code.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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When uclibc is built with static PIE support the _dl_load_base variable
shared between the libc-tls.c and reloc_static_pie.c creates the
dependency that requires linking reloc_static_pie.o into static
position-dependent executables resulting in the following build errors:
gcc -static test.c -o test
...ld:
...usr/lib/libc.a(reloc_static_pie.os):(.text+0x0):
undefined reference to `_DYNAMIC'
Move _dl_load_base definition to libc-tls.c to resolve this dependency
and fix static PDE build.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Static PIE ELFs may be loaded on noMMU linux platforms with FDPIC
support, but they don't have adjustable brk, and thus cannot allocate
memory for the TLS. Use mmap instead of sbrk to allocate initial TLS
memory when building with static PIE support for noMMU.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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on mips
Updated config to allow compilation of rcrt1.o for mips and modified it's crt1.S to perform relocates in __start.
The mips architecture performs relocations differently then most other architectures. reloc_static_pie was rewritten, taking code from dl-startup.c, in order to perfrom the additional relocations. Modifications were made to mips' dl-startup.h to allow for the use of contained macros without including _start definition.
Signed-off-by: linted <linted@users.noreply.github.com>
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Patch suggested by Thomas Petazzoni and tested by me.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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on aarch64
Updated config to allow compilation of rcrt1.o for aarch64 and modified it's crt1.S to relocate dynamic section prior to __uClibc_main.
Disabled stack protector when compiling reloc_static_pie.c to avoid TLS access prior to it being setup.
Signed-off-by: linted <linted@users.noreply.github.com>
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There is a real-world usage of RUSAGE_THREAD by the pistache project,
https://github.com/oktal/pistache.
Reported-By: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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on i386, x86_64, and arm.
This patch adds the generation of rcrt1.o which is used by gcc when compiling with the --static-pie flag.
rcrt1.o differs from crt1.o and Scrt1.o in that it the executable has a dynamic section but no relocations have been performed prior to _start being called.
crt1.o assumes there to be no dynamic relocations, and Scrt1.o has all relocations performed prior to execution by lsdo.
The new reloc_static_pie function handles parsing the dynamic section, and performing the relocations in a architecture agnostic method.
It also sets _dl_load_base which is used when initalizing TLS to ensure loading from the proper location.
This allows for easier porting of static-pie support to additional architectures as only modifications to crt1.S to find the load address are required.
Signed-off-by: linted <linted@users.noreply.github.com>
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Thomas has repored failure building ARM 32-bit systems for ARMv8 cores
CC libpthread/linuxthreads/mutex.os
/tmp/ccn8SFKU.s: Assembler messages:
/tmp/ccn8SFKU.s:162: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:186: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:203: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:224: Error: swp{b} use is obsoleted for ARMv8 and later
make[1]: *** [Makerules:369: libpthread/linuxthreads/mutex.os] Error 1
This is due to libpthread/linuxthreads/sysdeps/arm/pt-machine.h which
uses the swp instruction that is not allowed on ARMv8.
All __ARM_ARCH >= 7 support ldrex/strex instructions, so unlock
testandset() varaint for them.
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
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O0 build result in the following codegen
00000000 <ldrex>:
0: b480 push {r7}
2: b085 sub sp, #20
4: af00 add r7, sp, #0
6: 6078 str r0, [r7, #4]
8: 687b ldr r3, [r7, #4]
a: e853 3f00 ldrex r3, [r3]
e: 60fb str r3, [r7, #12]
10: 68fb ldr r3, [r7, #12]
12: 4618 mov r0, r3
14: 3714 adds r7, #20
16: 46bd mov sp, r7
18: f85d 7b04 ldr.w r7, [sp], #4
1c: 4770 bx lr
0000001e <strex>:
1e: b480 push {r7}
20: b085 sub sp, #20
22: af00 add r7, sp, #0
24: 6078 str r0, [r7, #4]
26: 6039 str r1, [r7, #0]
28: 687b ldr r3, [r7, #4]
2a: 683a ldr r2, [r7, #0]
2c: e842 3300 strex r3, r3, [r2]
30: 60fb str r3, [r7, #12]
32: 68fb ldr r3, [r7, #12]
34: 4618 mov r0, r3
36: 3714 adds r7, #20
38: 46bd mov sp, r7
3a: f85d 7b04 ldr.w r7, [sp], #4
3e: 4770 bx lr
00000040 <testandset>:
40: b590 push {r4, r7, lr}
42: b083 sub sp, #12
44: af00 add r7, sp, #0
46: 6078 str r0, [r7, #4]
48: 6878 ldr r0, [r7, #4]
4a: f7ff fffe bl 0 <ldrex>
4e: 4603 mov r3, r0
50: 461c mov r4, r3
52: 6879 ldr r1, [r7, #4]
54: 2001 movs r0, #1
56: f7ff fffe bl 1e <strex>
5a: 4603 mov r3, r0
5c: 2b00 cmp r3, #0
5e: d1f3 bne.n 48 <testandset+0x8>
60: 4623 mov r3, r4
62: 4618 mov r0, r3
64: 370c adds r7, #12
66: 46bd mov sp, r7
68: bd90 pop {r4, r7, pc}
ARM ARM suggests that LoadExcl/StoreExcl loops are guaranteed to make
forward progress only if, for any LoadExcl/StoreExcl loop within a
single thread of execution, the software meets all of the following
conditions:
1 Between the Load-Exclusive and the Store-Exclusive, there are no
explicit memory accesses, preloads, direct or indirect System
register writes, address translation instructions, cache or TLB
maintenance instructions, exception generating instructions,
exception returns, or indirect branches.
...
Obviously condition is not met for O0 builds.
O2 build (which is highly likely the most common setting) able to do
the right thing resulting in
00000000 <ldrex>:
0: e850 0f00 ldrex r0, [r0]
4: 4770 bx lr
6: bf00 nop
00000008 <strex>:
8: e841 0000 strex r0, r0, [r1]
c: 4770 bx lr
e: bf00 nop
00000010 <testandset>:
10: 2101 movs r1, #1
12: 4603 mov r3, r0
14: e853 0f00 ldrex r0, [r3]
18: e843 1200 strex r2, r1, [r3]
1c: 2a00 cmp r2, #0
1e: d1f9 bne.n 14 <testandset+0x4>
20: 4770 bx lr
22: bf00 nop
Rather than depending on level of optimisation implement whole
ldrex/strex loop in inline assembly.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
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