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-rw-r--r--libc/sysdeps/linux/mips/sgidefs.h20
-rw-r--r--libc/sysdeps/linux/mips/sys/asm.h473
-rw-r--r--libc/sysdeps/linux/mips/sys/fpregdef.h61
-rw-r--r--libc/sysdeps/linux/mips/sys/regdef.h21
-rw-r--r--libc/sysdeps/linux/mips/sys/ucontext.h160
5 files changed, 684 insertions, 51 deletions
diff --git a/libc/sysdeps/linux/mips/sgidefs.h b/libc/sysdeps/linux/mips/sgidefs.h
index 56567e884..1d4893501 100644
--- a/libc/sysdeps/linux/mips/sgidefs.h
+++ b/libc/sysdeps/linux/mips/sgidefs.h
@@ -1,21 +1,21 @@
-/* Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+/* Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ralf Baechle <ralf@gnu.org>.
The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Library General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Library General Public License for more details.
+ Lesser General Public License for more details.
- You should have received a copy of the GNU Library General Public
- License along with the GNU C Library; see the file COPYING.LIB. If not,
- write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
#ifndef _SGIDEFS_H
#define _SGIDEFS_H 1
@@ -28,6 +28,8 @@
#define _MIPS_ISA_MIPS3 3
#define _MIPS_ISA_MIPS4 4
#define _MIPS_ISA_MIPS5 5
+#define _MIPS_ISA_MIPS32 6
+#define _MIPS_ISA_MIPS64 7
/*
* Subprogram calling convention
diff --git a/libc/sysdeps/linux/mips/sys/asm.h b/libc/sysdeps/linux/mips/sys/asm.h
new file mode 100644
index 000000000..76f6af3e1
--- /dev/null
+++ b/libc/sysdeps/linux/mips/sys/asm.h
@@ -0,0 +1,473 @@
+/* Copyright (C) 1997, 1998, 2002, 2003 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Ralf Baechle <ralf@gnu.org>.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#ifndef _SYS_ASM_H
+#define _SYS_ASM_H
+
+#include <sgidefs.h>
+
+#ifndef CAT
+# ifdef __STDC__
+# define __CAT(str1,str2) str1##str2
+# else
+# define __CAT(str1,str2) str1/**/str2
+# endif
+# define CAT(str1,str2) __CAT(str1,str2)
+#endif
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ *
+ * 64 bit address space isn't used yet, so we may use the R3000 32 bit
+ * defines for now.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+# define PTR .word
+# define PTRSIZE 4
+# define PTRLOG 2
+#elif (_MIPS_SIM == _MIPS_SIM_ABI64)
+# define PTR .dword
+# define PTRSIZE 8
+# define PTRLOG 3
+#endif
+
+/*
+ * PIC specific declarations
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+# ifdef __PIC__
+# define CPRESTORE(register) \
+ .cprestore register
+# define CPLOAD(register) \
+ .cpload register
+# else
+# define CPRESTORE(register)
+# define CPLOAD(register)
+# endif
+
+# define CPADD(register) \
+ .cpadd register
+
+/*
+ * Set gp when at 1st instruction
+ */
+# define SETUP_GP \
+ .set noreorder; \
+ .cpload $25; \
+ .set reorder
+/* Set gp when not at 1st instruction */
+# define SETUP_GPX(r) \
+ .set noreorder; \
+ move r, $31; /* Save old ra. */ \
+ bal 10f; /* Find addr of cpload. */ \
+ nop; \
+10: \
+ .cpload $31; \
+ move $31, r; \
+ .set reorder
+# define SETUP_GPX_L(r, l) \
+ .set noreorder; \
+ move r, $31; /* Save old ra. */ \
+ bal l; /* Find addr of cpload. */ \
+ nop; \
+l: \
+ .cpload $31; \
+ move $31, r; \
+ .set reorder
+# define SAVE_GP(x) \
+ .cprestore x /* Save gp trigger t9/jalr conversion. */
+# define SETUP_GP64(a, b)
+# define SETUP_GPX64(a, b)
+# define SETUP_GPX64_L(cp_reg, ra_save, l)
+# define RESTORE_GP64
+# define USE_ALT_CP(a)
+#else /* (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32) */
+/*
+ * For callee-saved gp calling convention:
+ */
+# define SETUP_GP
+# define SETUP_GPX(r)
+# define SETUP_GPX_L(r, l)
+# define SAVE_GP(x)
+
+# define SETUP_GP64(gpoffset, proc) \
+ .cpsetup $25, gpoffset, proc
+# define SETUP_GPX64(cp_reg, ra_save) \
+ move ra_save, $31; /* Save old ra. */ \
+ .set noreorder; \
+ bal 10f; /* Find addr of .cpsetup. */ \
+ nop; \
+10: \
+ .set reorder; \
+ .cpsetup $31, cp_reg, 10b; \
+ move $31, ra_save
+# define SETUP_GPX64_L(cp_reg, ra_save, l) \
+ move ra_save, $31; /* Save old ra. */ \
+ .set noreorder; \
+ bal l; /* Find addr of .cpsetup. */ \
+ nop; \
+l: \
+ .set reorder; \
+ .cpsetup $31, cp_reg, l; \
+ move $31, ra_save
+# define RESTORE_GP64 \
+ .cpreturn
+/* Use alternate register for context pointer. */
+# define USE_ALT_CP(reg) \
+ .cplocal reg
+#endif /* _MIPS_SIM != _MIPS_SIM_ABI32 */
+
+/*
+ * Stack Frame Definitions
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+# define NARGSAVE 4 /* Space for 4 argument registers must be allocated. */
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32)
+# define NARGSAVE 0 /* No caller responsibilities. */
+#endif
+
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define LEAF(symbol) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol,@function; \
+ .ent symbol,0; \
+symbol: .frame sp,0,ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define NESTED(symbol, framesize, rpc) \
+ .globl symbol; \
+ .align 2; \
+ .type symbol,@function; \
+ .ent symbol,0; \
+symbol: .frame sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#ifndef END
+# define END(function) \
+ .end function; \
+ .size function,.-function
+#endif
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol) \
+ .globl symbol; \
+symbol:
+
+/*
+ * ABS - export absolute symbol
+ */
+#define ABS(symbol,value) \
+ .globl symbol; \
+symbol = value
+
+#define PANIC(msg) \
+ .set push; \
+ .set reorder; \
+ la a0,8f; \
+ jal panic; \
+9: b 9b; \
+ .set pop; \
+ TEXT(msg)
+
+/*
+ * Print formated string
+ */
+#define PRINT(string) \
+ .set push; \
+ .set reorder; \
+ la a0,8f; \
+ jal printk; \
+ .set pop; \
+ TEXT(string)
+
+#define TEXT(msg) \
+ .data; \
+8: .asciiz msg; \
+ .previous;
+
+/*
+ * Build text tables
+ */
+#define TTABLE(string) \
+ .text; \
+ .word 1f; \
+ .previous; \
+ .data; \
+1: .asciz string; \
+ .previous
+
+/*
+ * MIPS IV pref instruction.
+ * Use with .set noreorder only!
+ *
+ * MIPS IV implementations are free to treat this as a nop. The R5000
+ * is one of them. So we should have an option not to use this instruction.
+ */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
+ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+# define PREF(hint,addr) \
+ pref hint,addr
+# define PREFX(hint,addr) \
+ prefx hint,addr
+#else
+# define PREF
+# define PREFX
+#endif
+
+/*
+ * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
+ */
+#if _MIPS_ISA == _MIPS_ISA_MIPS1
+# define MOVN(rd,rs,rt) \
+ .set push; \
+ .set reorder; \
+ beqz rt,9f; \
+ move rd,rs; \
+ .set pop; \
+9:
+# define MOVZ(rd,rs,rt) \
+ .set push; \
+ .set reorder; \
+ bnez rt,9f; \
+ move rd,rt; \
+ .set pop; \
+9:
+#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
+# define MOVN(rd,rs,rt) \
+ .set push; \
+ .set noreorder; \
+ bnezl rt,9f; \
+ move rd,rs; \
+ .set pop; \
+9:
+# define MOVZ(rd,rs,rt) \
+ .set push; \
+ .set noreorder; \
+ beqzl rt,9f; \
+ movz rd,rs; \
+ .set pop; \
+9:
+#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
+ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+# define MOVN(rd,rs,rt) \
+ movn rd,rs,rt
+# define MOVZ(rd,rs,rt) \
+ movz rd,rs,rt
+#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
+
+/*
+ * Stack alignment
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+# define ALSZ 15
+# define ALMASK ~15
+#else
+# define ALSZ 7
+# define ALMASK ~7
+#endif
+
+/*
+ * Size of a register
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI64) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+# define SZREG 8
+#else
+# define SZREG 4
+#endif
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#if (SZREG == 4)
+# define REG_S sw
+# define REG_L lw
+#else
+# define REG_S sd
+# define REG_L ld
+#endif
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#if (_MIPS_SZINT == 32)
+# define INT_ADD add
+# define INT_ADDI addi
+# define INT_ADDU addu
+# define INT_ADDIU addiu
+# define INT_SUB add
+# define INT_SUBI subi
+# define INT_SUBU subu
+# define INT_SUBIU subu
+# define INT_L lw
+# define INT_S sw
+#endif
+
+#if (_MIPS_SZINT == 64)
+# define INT_ADD dadd
+# define INT_ADDI daddi
+# define INT_ADDU daddu
+# define INT_ADDIU daddiu
+# define INT_SUB dadd
+# define INT_SUBI dsubi
+# define INT_SUBU dsubu
+# define INT_SUBIU dsubu
+# define INT_L ld
+# define INT_S sd
+#endif
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#if (_MIPS_SZLONG == 32)
+# define LONG_ADD add
+# define LONG_ADDI addi
+# define LONG_ADDU addu
+# define LONG_ADDIU addiu
+# define LONG_SUB add
+# define LONG_SUBI subi
+# define LONG_SUBU subu
+# define LONG_SUBIU subu
+# define LONG_L lw
+# define LONG_S sw
+# define LONG_SLL sll
+# define LONG_SLLV sllv
+# define LONG_SRL srl
+# define LONG_SRLV srlv
+# define LONG_SRA sra
+# define LONG_SRAV srav
+#endif
+
+#if (_MIPS_SZLONG == 64)
+# define LONG_ADD dadd
+# define LONG_ADDI daddi
+# define LONG_ADDU daddu
+# define LONG_ADDIU daddiu
+# define LONG_SUB dadd
+# define LONG_SUBI dsubi
+# define LONG_SUBU dsubu
+# define LONG_SUBIU dsubu
+# define LONG_L ld
+# define LONG_S sd
+# define LONG_SLL dsll
+# define LONG_SLLV dsllv
+# define LONG_SRL dsrl
+# define LONG_SRLV dsrlv
+# define LONG_SRA dsra
+# define LONG_SRAV dsrav
+#endif
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32 && _MIPS_SZPTR == 32)
+# define PTR_ADD add
+# define PTR_ADDI addi
+# define PTR_ADDU addu
+# define PTR_ADDIU addiu
+# define PTR_SUB add
+# define PTR_SUBI subi
+# define PTR_SUBU subu
+# define PTR_SUBIU subu
+# define PTR_L lw
+# define PTR_LA la
+# define PTR_S sw
+# define PTR_SLL sll
+# define PTR_SLLV sllv
+# define PTR_SRL srl
+# define PTR_SRLV srlv
+# define PTR_SRA sra
+# define PTR_SRAV srav
+
+# define PTR_SCALESHIFT 2
+#endif
+
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+# define PTR_ADD add
+# define PTR_ADDI addi
+# define PTR_ADDU add /* no u */
+# define PTR_ADDIU addi /* no u */
+# define PTR_SUB add
+# define PTR_SUBI subi
+# define PTR_SUBU sub /* no u */
+# define PTR_SUBIU sub /* no u */
+# define PTR_L lw
+# define PTR_LA la
+# define PTR_S sw
+# define PTR_SLL sll
+# define PTR_SLLV sllv
+# define PTR_SRL srl
+# define PTR_SRLV srlv
+# define PTR_SRA sra
+# define PTR_SRAV srav
+
+# define PTR_SCALESHIFT 2
+#endif
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32 && _MIPS_SZPTR == 64 /* o64??? */) \
+ || _MIPS_SIM == _MIPS_SIM_ABI64
+# define PTR_ADD dadd
+# define PTR_ADDI daddi
+# define PTR_ADDU daddu
+# define PTR_ADDIU daddiu
+# define PTR_SUB dadd
+# define PTR_SUBI dsubi
+# define PTR_SUBU dsubu
+# define PTR_SUBIU dsubu
+# define PTR_L ld
+# define PTR_LA dla
+# define PTR_S sd
+# define PTR_SLL dsll
+# define PTR_SLLV dsllv
+# define PTR_SRL dsrl
+# define PTR_SRLV dsrlv
+# define PTR_SRA dsra
+# define PTR_SRAV dsrav
+
+# define PTR_SCALESHIFT 3
+#endif
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
+ (_MIPS_ISA == _MIPS_ISA_MIPS32)
+# define MFC0 mfc0
+# define MTC0 mtc0
+#endif
+#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
+ (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+# define MFC0 dmfc0
+# define MTC0 dmtc0
+#endif
+
+#endif /* sys/asm.h */
diff --git a/libc/sysdeps/linux/mips/sys/fpregdef.h b/libc/sysdeps/linux/mips/sys/fpregdef.h
new file mode 100644
index 000000000..378115274
--- /dev/null
+++ b/libc/sysdeps/linux/mips/sys/fpregdef.h
@@ -0,0 +1,61 @@
+/* Copyright (C) 1991, 92, 94, 95, 96, 97, 98 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+#ifndef _SYS_FPREGDEF_H
+#define _SYS_FPREGDEF_H
+
+/*
+ * These definitions only cover the R3000-ish 16/32 register model.
+ * But we're trying to be R3000 friendly anyway ...
+ */
+#define fv0 $f0 /* return value */
+#define fv0f $f1
+#define fv1 $f2
+#define fv1f $f3
+#define fa0 $f12 /* argument registers */
+#define fa0f $f13
+#define fa1 $f14
+#define fa1f $f15
+#define ft0 $f4 /* caller saved */
+#define ft0f $f5
+#define ft1 $f6
+#define ft1f $f7
+#define ft2 $f8
+#define ft2f $f9
+#define ft3 $f10
+#define ft3f $f11
+#define ft4 $f16
+#define ft4f $f17
+#define ft5 $f18
+#define ft5f $f19
+#define fs0 $f20 /* callee saved */
+#define fs0f $f21
+#define fs1 $f22
+#define fs1f $f23
+#define fs2 $f24
+#define fs2f $f25
+#define fs3 $f26
+#define fs3f $f27
+#define fs4 $f28
+#define fs4f $f29
+#define fs5 $f30
+#define fs5f $f31
+
+#define fcr31 $31 /* FPU status register */
+
+#endif /* sys/fpregdef.h */
diff --git a/libc/sysdeps/linux/mips/sys/regdef.h b/libc/sysdeps/linux/mips/sys/regdef.h
index c4df60383..9d2c4c1c4 100644
--- a/libc/sysdeps/linux/mips/sys/regdef.h
+++ b/libc/sysdeps/linux/mips/sys/regdef.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+/* Copyright (C) 1997, 1998, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ralf Baechle <ralf@gnu.org>.
@@ -31,6 +31,20 @@
#define a1 $5
#define a2 $6
#define a3 $7
+#if _MIPS_SIM != _MIPS_SIM_ABI32
+#define a4 $8
+#define a5 $9
+#define a6 $10
+#define a7 $11
+#define t0 $12
+#define t1 $13
+#define t2 $14
+#define t3 $15
+#define ta0 a4
+#define ta1 a5
+#define ta2 a6
+#define ta3 a7
+#else /* if _MIPS_SIM == _MIPS_SIM_ABI32 */
#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
@@ -39,6 +53,11 @@
#define t5 $13
#define t6 $14
#define t7 $15
+#define ta0 t4
+#define ta1 t5
+#define ta2 t6
+#define ta3 t7
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
diff --git a/libc/sysdeps/linux/mips/sys/ucontext.h b/libc/sysdeps/linux/mips/sys/ucontext.h
index f57b91e4f..90aa09a80 100644
--- a/libc/sysdeps/linux/mips/sys/ucontext.h
+++ b/libc/sysdeps/linux/mips/sys/ucontext.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1997, 1998, 2000 Free Software Foundation, Inc.
+/* Copyright (C) 1998, 1999, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -16,65 +16,143 @@
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
-/* Don't rely on this, the interface is currently messed up and may need to
- be broken to be fixed. */
+/* System V/mips ABI compliant context switching support. */
+
#ifndef _SYS_UCONTEXT_H
#define _SYS_UCONTEXT_H 1
#include <features.h>
#include <signal.h>
-/* We need the signal context definitions even if they are not used
- included in <signal.h>. */
-#include <bits/sigcontext.h>
-
-
/* Type for general register. */
-typedef unsigned long int greg_t;
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+typedef __uint32_t greg_t;
+#else
+typedef __uint64_t greg_t;
+#endif
/* Number of general registers. */
-#define NGREG 37
-#define NFPREG 33
+#define NGREG 36
/* Container for all general registers. */
-/* gregset_t must be an array. The below declared array corresponds to:
-typedef struct gregset {
- greg_t g_regs[32];
- greg_t g_hi;
- greg_t g_lo;
- greg_t g_pad[3];
-} gregset_t; */
typedef greg_t gregset_t[NGREG];
-/* Container for all FPU registers. */
-typedef struct fpregset {
- union {
- double fp_dregs[32];
- struct {
- float _fp_fregs;
- unsigned int _fp_pad;
- } fp_fregs[32];
- } fp_r;
- unsigned int fp_csr;
- unsigned int fp_pad;
-} fpregset_t;
+/* Number of each register is the `gregset_t' array. */
+enum
+{
+ CTX_R0 = 0,
+#define CTX_R0 CTX_R0
+ CTX_AT = 1,
+#define CTX_AT CTX_AT
+ CTX_V0 = 2,
+#define CTX_V0 CTX_V0
+ CTX_V1 = 3,
+#define CTX_V1 CTX_V1
+ CTX_A0 = 4,
+#define CTX_A0 CTX_A0
+ CTX_A1 = 5,
+#define CTX_A1 CTX_A1
+ CTX_A2 = 6,
+#define CTX_A2 CTX_A2
+ CTX_A3 = 7,
+#define CTX_A3 CTX_A3
+ CTX_T0 = 8,
+#define CTX_T0 CTX_T0
+ CTX_T1 = 9,
+#define CTX_T1 CTX_T1
+ CTX_T2 = 10,
+#define CTX_T2 CTX_T2
+ CTX_T3 = 11,
+#define CTX_T3 CTX_T3
+ CTX_T4 = 12,
+#define CTX_T4 CTX_T4
+ CTX_T5 = 13,
+#define CTX_T5 CTX_T5
+ CTX_T6 = 14,
+#define CTX_T6 CTX_T6
+ CTX_T7 = 15,
+#define CTX_T7 CTX_T7
+ CTX_S0 = 16,
+#define CTX_S0 CTX_S0
+ CTX_S1 = 17,
+#define CTX_S1 CTX_S1
+ CTX_S2 = 18,
+#define CTX_S2 CTX_S2
+ CTX_S3 = 19,
+#define CTX_S3 CTX_S3
+ CTX_S4 = 20,
+#define CTX_S4 CTX_S4
+ CTX_S5 = 21,
+#define CTX_S5 CTX_S5
+ CTX_S6 = 22,
+#define CTX_S6 CTX_S6
+ CTX_S7 = 23,
+#define CTX_S7 CTX_S7
+ CTX_T8 = 24,
+#define CTX_T8 CTX_T8
+ CTX_T9 = 25,
+#define CTX_T9 CTX_T9
+ CTX_K0 = 26,
+#define CTX_K0 CTX_K0
+ CTX_K1 = 27,
+#define CTX_K1 CTX_K1
+ CTX_GP = 28,
+#define CTX_GP CTX_GP
+ CTX_SP = 29,
+#define CTX_SP CTX_SP
+ CTX_S8 = 30,
+#define CTX_S8 CTX_S8
+ CTX_RA = 31,
+#define CTX_RA CTX_RA
+ CTX_MDLO = 32,
+#define CTX_MDLO CTX_MDLO
+ CTX_MDHI = 33,
+#define CTX_MDHI CTX_MDHI
+ CTX_CAUSE = 34,
+#define CTX_CAUSE CTX_CAUSE
+ CTX_EPC = 35,
+#define CTX_EPC CTX_EPC
+};
+/* Structure to describe FPU registers. */
+typedef struct fpregset
+{
+ union
+ {
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+ double fp_dregs[16];
+ float fp_fregs[32];
+ unsigned int fp_regs[32];
+#else
+ double fp_dregs[32];
+ /* float fp_fregs[32]; */
+ __uint64_t fp_regs[32];
+#endif
+ } fp_r;
+ unsigned int fp_csr;
+ unsigned int fp_pad;
+} fpregset_t;
/* Context to describe whole processor state. */
typedef struct
- {
- gregset_t gregs;
- fpregset_t fpregs;
- } mcontext_t;
+{
+ gregset_t gpregs;
+ fpregset_t fpregs;
+} mcontext_t;
/* Userlevel context. */
typedef struct ucontext
- {
- unsigned long int uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- mcontext_t uc_mcontext;
- __sigset_t uc_sigmask;
- } ucontext_t;
+{
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+ unsigned long int uc_flags;
+#else
+ __uint64_t uc_flags;
+#endif
+ struct ucontext *uc_link;
+ __sigset_t uc_sigmask;
+ stack_t uc_stack;
+ mcontext_t uc_mcontext;
+ int uc_filler[48];
+} ucontext_t;
#endif /* sys/ucontext.h */
generated by cgit v1.2.3 (git 2.46.0) at 2025-11-04 00:06:09 +0000