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Diffstat (limited to 'libc/sysdeps/linux/arm/fpu_control.h')
-rw-r--r--libc/sysdeps/linux/arm/fpu_control.h72
1 files changed, 72 insertions, 0 deletions
diff --git a/libc/sysdeps/linux/arm/fpu_control.h b/libc/sysdeps/linux/arm/fpu_control.h
index 65912e496..8c13ca3a3 100644
--- a/libc/sysdeps/linux/arm/fpu_control.h
+++ b/libc/sysdeps/linux/arm/fpu_control.h
@@ -20,6 +20,76 @@
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H
+#ifdef __MAVERICK__
+
+/* DSPSC register: (from EP9312 User's Guide)
+ *
+ * bits 31..29 - DAID
+ * bits 28..26 - HVID
+ * bits 25..24 - RSVD
+ * bit 23 - ISAT
+ * bit 22 - UI
+ * bit 21 - INT
+ * bit 20 - AEXC
+ * bits 19..18 - SAT
+ * bits 17..16 - FCC
+ * bit 15 - V
+ * bit 14 - FWDEN
+ * bit 13 - Invalid
+ * bit 12 - Denorm
+ * bits 11..10 - RM
+ * bits 9..5 - IXE, UFE, OFE, RSVD, IOE
+ * bits 4..0 - IX, UF, OF, RSVD, IO
+ */
+
+/* masking of interrupts */
+#define _FPU_MASK_IM (1 << 5) /* invalid operation */
+#define _FPU_MASK_ZM 0 /* divide by zero */
+#define _FPU_MASK_OM (1 << 7) /* overflow */
+#define _FPU_MASK_UM (1 << 8) /* underflow */
+#define _FPU_MASK_PM (1 << 9) /* inexact */
+#define _FPU_MASK_DM 0 /* denormalized operation */
+
+#define _FPU_RESERVED 0xfffff000 /* These bits are reserved. */
+
+#define _FPU_DEFAULT 0x00b00000 /* Default value. */
+#define _FPU_IEEE 0x00b003a0 /* Default + exceptions enabled. */
+
+/* Type of the control word. */
+typedef unsigned int fpu_control_t;
+
+/* Macros for accessing the hardware control word. */
+#define _FPU_GETCW(cw) ({ \
+ register int __t1, __t2; \
+ \
+ __asm__ volatile ( \
+ "cfmvr64l %1, mvdx0\n\t" \
+ "cfmvr64h %2, mvdx0\n\t" \
+ "cfmv32sc mvdx0, dspsc\n\t" \
+ "cfmvr64l %0, mvdx0\n\t" \
+ "cfmv64lr mvdx0, %1\n\t" \
+ "cfmv64hr mvdx0, %2" \
+ : "=r" (cw), "=r" (__t1), "=r" (__t2) \
+ ); \
+})
+
+#define _FPU_SETCW(cw) ({ \
+ register int __t0, __t1, __t2; \
+ \
+ __asm__ volatile ( \
+ "cfmvr64l %1, mvdx0\n\t" \
+ "cfmvr64h %2, mvdx0\n\t" \
+ "cfmv64lr mvdx0, %0\n\t" \
+ "cfmvsc32 dspsc, mvdx0\n\t" \
+ "cfmv64lr mvdx0, %1\n\t" \
+ "cfmv64hr mvdx0, %2" \
+ : "=r" (__t0), "=r" (__t1), "=r" (__t2) \
+ : "0" (cw) \
+ ); \
+})
+
+#else /* !__MAVERICK__ */
+
/* We have a slight terminology confusion here. On the ARM, the register
* we're interested in is actually the FPU status word - the FPU control
* word is something different (which is implementation-defined and only
@@ -96,6 +166,8 @@ typedef unsigned int fpu_control_t;
#define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
#define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
+#endif /* __MAVERICK__ */
+
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;