summaryrefslogtreecommitdiff
path: root/libc/string/ia64/softpipe.h
diff options
context:
space:
mode:
Diffstat (limited to 'libc/string/ia64/softpipe.h')
-rw-r--r--libc/string/ia64/softpipe.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/libc/string/ia64/softpipe.h b/libc/string/ia64/softpipe.h
index cf0eb5355..d71af735e 100644
--- a/libc/string/ia64/softpipe.h
+++ b/libc/string/ia64/softpipe.h
@@ -18,7 +18,7 @@
/* The latency of a memory load assumed by the assembly implementation
of the mem and str functions. Since we don't have any clue about
- where the data might be, let's assume it's in the L2 cache.
+ where the data might be, let's assume it's in the L2 cache.
Assuming L3 would be too pessimistic :-)
Some functions define MEMLAT as 2, because they expect their data