diff options
| author | ustcymgu@gmail.com <ustcymgu@gmail.com> | 2022-11-19 14:02:55 +0000 |
|---|---|---|
| committer | Waldemar Brodkorb <wbx@openadk.org> | 2022-11-20 08:44:03 +0100 |
| commit | 0a5466d8d53bc8045ff56ff76cc1880aa85761c2 (patch) | |
| tree | 5ff1df22a9a052a712318b88cc9c57ff2f963326 /libc/sysdeps | |
| parent | 9e854172e249a383d858fef70368af63a04a28a8 (diff) | |
RISC-V 32-bit support
Added 32-bit RISC-V support. I have managed to get 32-bit RISC-V No-MMU
Linux running based on mainstream buildroot. It's nice to have uclibc
support this 32-bit No-MMU target.
There's no substantial code change except definations and config
options.
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
Diffstat (limited to 'libc/sysdeps')
| l--------- | libc/sysdeps/linux/riscv32 | 1 | ||||
| -rw-r--r-- | libc/sysdeps/linux/riscv64/bits/wordsize.h | 3 | ||||
| -rw-r--r-- | libc/sysdeps/linux/riscv64/sys/asm.h | 6 |
3 files changed, 8 insertions, 2 deletions
diff --git a/libc/sysdeps/linux/riscv32 b/libc/sysdeps/linux/riscv32 new file mode 120000 index 000000000..11677ef05 --- /dev/null +++ b/libc/sysdeps/linux/riscv32 @@ -0,0 +1 @@ +riscv64
\ No newline at end of file diff --git a/libc/sysdeps/linux/riscv64/bits/wordsize.h b/libc/sysdeps/linux/riscv64/bits/wordsize.h index 67a16ba62..1fc649aad 100644 --- a/libc/sysdeps/linux/riscv64/bits/wordsize.h +++ b/libc/sysdeps/linux/riscv64/bits/wordsize.h @@ -25,5 +25,6 @@ #if __riscv_xlen == 64 # define __WORDSIZE_TIME64_COMPAT32 1 #else -# error "rv32i-based targets are not supported" +# define __WORDSIZE_TIME64_COMPAT32 1 +// # warning "rv32i-based targets are experimental" #endif diff --git a/libc/sysdeps/linux/riscv64/sys/asm.h b/libc/sysdeps/linux/riscv64/sys/asm.h index ddb84b683..3c94c9a70 100644 --- a/libc/sysdeps/linux/riscv64/sys/asm.h +++ b/libc/sysdeps/linux/riscv64/sys/asm.h @@ -26,7 +26,11 @@ # define REG_S sd # define REG_L ld #elif __riscv_xlen == 32 -# error "rv32i-based targets are not supported" +# define PTRLOG 2 +# define SZREG 4 +# define REG_S sw +# define REG_L lw +// # warning "rv32i-based targets are experimental" #else # error __riscv_xlen must equal 32 or 64 #endif |