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authorBernhard Reutner-Fischer <rep.dot.nop@gmail.com>2008-03-26 13:40:36 +0000
committerBernhard Reutner-Fischer <rep.dot.nop@gmail.com>2008-03-26 13:40:36 +0000
commitefce79f09ae6daa77cd322df0d532beec3f445f5 (patch)
treeae936850c5671b8bea0abf0d33bf2196f7abc796 /libc/string/arm/strncmp.S
parent17e961d9c708ab202760ce830f8efe73e91bb129 (diff)
Paul Brook writes:
The attached patch adds support for compiling arm uClibc as pure Thumb code. This is needed because some recent ARM codes do not implement traditional ARM mode. Specifically: * Cortex-M1 - An extremely minimal FPGA based core that only implements Thumb-1 (aka ARMv6-M). * Cortex-M3 - A Thumb-2 only ARMv7-M core. Most of uClibc already builds in Thumb mode, all that is left are a handful of assembly bits. Tested on arm-uclinuxeabi.
Diffstat (limited to 'libc/string/arm/strncmp.S')
-rw-r--r--libc/string/arm/strncmp.S33
1 files changed, 33 insertions, 0 deletions
diff --git a/libc/string/arm/strncmp.S b/libc/string/arm/strncmp.S
index eaf0620b4..8487639c8 100644
--- a/libc/string/arm/strncmp.S
+++ b/libc/string/arm/strncmp.S
@@ -30,15 +30,46 @@
*/
#include <features.h>
+#include <bits/arm_asm.h>
.text
.global strncmp
.type strncmp,%function
.align 4
+#if defined(THUMB1_ONLY)
+.thumb_func
strncmp:
/* if (len == 0) return 0 */
cmp r2, #0
+ bne 1f
+ mov r0, #0
+ bx lr
+1:
+ push {r4}
+
+ /* ip == last src address to compare */
+ add r4, r0, r2
+2:
+ cmp r4, r0
+ beq 3f
+ ldrb r2, [r0]
+ add r0, r0, #1
+ ldrb r3, [r1]
+ add r1, r1, #1
+ cmp r2, #0
+ beq 3f
+ cmp r2, r3
+ beq 2b
+3:
+ sub r0, r2, r3
+ pop {r4}
+ bx lr
+#else
+strncmp:
+ /* if (len == 0) return 0 */
+ cmp r2, #0
+ IT(tt, eq)
moveq r0, #0
#if defined(__USE_BX__)
bxeq lr
@@ -53,6 +84,7 @@ strncmp:
ldrb r2, [r0], #1
ldrb r3, [r1], #1
cmp ip, r0
+ IT(tt, cs)
cmpcs r2, #1
cmpcs r2, r3
beq 1b
@@ -62,6 +94,7 @@ strncmp:
#else
mov pc, lr
#endif
+#endif
.size strncmp,.-strncmp