diff options
| author | Waldemar Brodkorb <wbx@openadk.org> | 2016-04-21 01:25:29 +0200 |
|---|---|---|
| committer | Waldemar Brodkorb <wbx@uclibc-ng.org> | 2016-06-30 03:24:42 +0200 |
| commit | ee92c0fe5c1b9d59508273916e2c9a75b68dbc13 (patch) | |
| tree | 65a22258b12f84325910fc2ad47e2b02696ef593 | |
| parent | dd46699e46decb7273f44dc2cbf307f096dc39e8 (diff) | |
nds32: add support for new architecture
Add support for Andes Technology NDS32 architecture.
See here http://www.andestech.com/en/index/index.htm for more
informaton. Verification of the port from an older uClibc
port was done on a sponsored AG101p board.
The testsuite only has 5 errors, three are related to
an existing bug in dlclose() with LT.old, also happening
on cris32 and m68k.
Failures to fallocate/posix_fallocate are unresolved.
Thanks to Andes Technology sponsoring the hardware and
being very helpful while doing the uClibc-ng porting.
Signed-off-by: Waldemar Brodkorb <wbx@uclibc-ng.org>
62 files changed, 4679 insertions, 8 deletions
@@ -12,7 +12,7 @@ Porting applications from glibc to uClibc-ng typically involves just recompiling the source code. uClibc-ng even supports shared libraries and threading. It currently runs on standard Linux and MMU-less (also known as µClinux) systems with support for ARC, ARM, Blackfin, i386, M68K/Coldfire -MIPS, MIPS64, PowerPC, SH, Sparc, X86_64 and XTENSA processors. +MIPS, MIPS64, NDS32, PowerPC, SH, Sparc, X86_64 and XTENSA processors. If you are building an embedded Linux system and you find that glibc is eating up too much space, you should consider using @@ -22,10 +22,10 @@ example, that 12 Terabytes will be Network Attached Storage and you plan to burn Linux into the system's firmware... uClibc-ng is maintained by Waldemar Brodkorb and is licensed under the -GNU LESSER GENERAL PUBLIC LICENSE. This license allows you to +GNU LESSER GENERAL PUBLIC LICENSE. This license allows you to make closed source commercial applications using an unmodified version of uClibc-ng. You do not need to give away all your source code just -because you use uClibc-ng and/or run on Linux. You should, however, +because you use uClibc-ng and/or run on Linux. You should, however, carefuly review the license and make certain you understand and abide by it strictly. @@ -42,7 +42,7 @@ Additional information can be found at http://www.uclibc-ng.org/. uClibc-ng may be freely modified and distributed under the terms of the GNU Lesser General Public License, which can be found in the -file COPYING. +file COPYING.LIB. And most of all, be sure to have some fun! :-) -Waldemar @@ -104,6 +104,7 @@ ifeq ($(TARGET_ARCH),) ARCH ?= $(shell uname -m | $(SED) -e s/i.86/i386/ \ -e s/sun.*/sparc/ -e s/sparc.*/sparc/ \ -e s/arm.*/arm/ -e s/sa110/arm/ \ + -e s/nds32.*/nds32/ \ -e s/sh.*/sh/ \ -e s/s390x/s390/ -e s/parisc.*/hppa/ \ -e s/ppc.*/powerpc/ -e s/mips.*/mips/ \ @@ -300,6 +301,7 @@ ifeq ($(UCLIBC_HAS_SOFT_FLOAT),y) ifneq ($(TARGET_ARCH),bfin) ifneq ($(TARGET_ARCH),lm32) ifneq ($(TARGET_ARCH),nios2) +ifneq ($(TARGET_ARCH),nds32) ifneq ($(TARGET_ARCH),sh) ifneq ($(TARGET_ARCH),c6x) ifneq ($(TARGET_ARCH),h8300) @@ -313,6 +315,7 @@ endif endif endif endif +endif $(eval $(call check-gcc-var,-std=gnu99)) CPU_CFLAGS-y += $(CFLAG_-std=gnu99) @@ -410,6 +413,12 @@ ifeq ($(TARGET_ARCH),mips) CPU_LDFLAGS-y += $(CPU_CFLAGS) endif +ifeq ($(TARGET_ARCH),nds32) + CPU_CFLAGS-$(CONFIG_NDS32_ISA)+=-march=nds32 + CFLAGS-.os+= -DPIC + CFLAGS-.oS+= -DPIC +endif + ifeq ($(TARGET_ARCH),sh) $(eval $(call check-gcc-var,-mprefergot)) OPTIMIZATION += $(CFLAG_-mprefergot) diff --git a/extra/Configs/Config.in b/extra/Configs/Config.in index 4a1509d88..1d97e784e 100644 --- a/extra/Configs/Config.in +++ b/extra/Configs/Config.in @@ -31,6 +31,7 @@ choice default TARGET_metag if DESIRED_TARGET_ARCH = "metag" default TARGET_microblaze if DESIRED_TARGET_ARCH = "microblaze" default TARGET_mips if DESIRED_TARGET_ARCH = "mips" + default TARGET_nds32 if DESIRED_TARGET_ARCH = "nds32" default TARGET_nios2 if DESIRED_TARGET_ARCH = "nios2" default TARGET_or1k if DESIRED_TARGET_ARCH = "or1k" default TARGET_powerpc if DESIRED_TARGET_ARCH = "powerpc" @@ -94,6 +95,9 @@ config TARGET_microblaze config TARGET_mips bool "mips" +config TARGET_nds32 + bool "nds32" + config TARGET_nios2 bool "nios2" @@ -172,6 +176,10 @@ if TARGET_metag source "extra/Configs/Config.metag" endif +if TARGET_nds32 +source "extra/Configs/Config.nds32" +endif + if TARGET_nios2 source "extra/Configs/Config.nios2" endif @@ -476,7 +484,6 @@ config LDSO_GNU_HASH_SUPPORT choice prompt "Thread support" - #default UCLIBC_HAS_THREADS_NATIVE if (TARGET_alpha || TARGET_arm || TARGET_i386 || TARGET_mips || TARGET_powerpc || TARGET_sh || TARGET_sh64) default HAS_NO_THREADS help If you want to compile uClibc with pthread support, then answer Y. @@ -524,6 +531,7 @@ config UCLIBC_HAS_THREADS_NATIVE !TARGET_ia64 && \ !TARGET_m68k && \ !TARGET_microblaze && \ + !TARGET_nds32 && \ !TARGET_nios2 && \ !TARGET_or1k && \ ARCH_USE_MMU @@ -2094,7 +2102,7 @@ menu "Security options" config UCLIBC_BUILD_PIE bool "Build utilities as ET_DYN/PIE executables" depends on HAVE_SHARED - depends on TARGET_arm || TARGET_frv || TARGET_i386 || TARGET_mips || TARGET_powerpc + depends on TARGET_arm || TARGET_frv || TARGET_i386 || TARGET_mips || TARGET_powerpc || TARGET_nds32 select FORCE_SHAREABLE_TEXT_SEGMENTS help If you answer Y here, ldd and iconv are built as ET_DYN/PIE diff --git a/extra/Configs/Config.nds32 b/extra/Configs/Config.nds32 new file mode 100644 index 000000000..a74249947 --- /dev/null +++ b/extra/Configs/Config.nds32 @@ -0,0 +1,31 @@ +# +# For a description of the syntax of this configuration file, +# see extra/config/Kconfig-language.txt +# + +config TARGET_ARCH + string + default "nds32" + +config FORCE_OPTIONS_FOR_ARCH + bool + default y + select ARCH_ANY_ENDIAN + select ARCH_HAS_DEPRECATED_SYSCALLS + select ARCH_HAS_MMU + +choice + prompt "MMU Page Size" + default CONFIG_NDS32_PAGE_SIZE_4K + +config CONFIG_NDS32_PAGE_SIZE_4K + bool "4KB" + help + Use 4k pagesize. + +config CONFIG_NDS32_PAGE_SIZE_8K + bool "8KB" + help + Use 8k pagesize. + +endchoice diff --git a/include/elf.h b/include/elf.h index 4a0280b80..17a6143b5 100644 --- a/include/elf.h +++ b/include/elf.h @@ -264,11 +264,12 @@ typedef struct #define EM_CR 103 /* National Semiconductor CompactRISC */ #define EM_MSP430 105 /* TI msp430 micro controller */ #define EM_BLACKFIN 106 /* Analog Devices Blackfin */ -#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */ +#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */ #define EM_CRX 114 /* National Semiconductor CRX */ #define EM_TI_C6000 140 +#define EM_NDS32 167 /* Andes Tech NDS32 */ #define EM_METAG 174 /* Imagination Technologies Meta */ -#define EM_MICROBLAZE 189 /* Xilinx Microblaze */ +#define EM_MICROBLAZE 189 /* Xilinx Microblaze */ #define EM_ARCV2 195 /* ARCv2 Cores */ /* NEXT FREE NUMBER: Increment this after adding your official arch number */ @@ -2912,6 +2913,174 @@ typedef Elf32_Addr Elf32_Conflict; #define R_H8_ABS32A16 127 #define R_H8_NUM 128 +/* NDS32 relocs. */ +#define R_NDS32_NONE 0 +/* REL relocations */ +#define R_NDS32_16 1 +#define R_NDS32_32 2 +#define R_NDS32_20 3 +#define R_NDS32_9_PCREL 4 +#define R_NDS32_15_PCREL 5 +#define R_NDS32_17_PCREL 6 +#define R_NDS32_25_PCREL 7 +#define R_NDS32_HI20 8 +#define R_NDS32_LO12S3 9 +#define R_NDS32_LO12S2 10 +#define R_NDS32_LO12S1 11 +#define R_NDS32_LO12S0 12 +#define R_NDS32_SDA15S3 13 +#define R_NDS32_SDA15S2 14 +#define R_NDS32_SDA15S1 15 +#define R_NDS32_SDA15S0 16 +#define R_NDS32_GNU_VTINHERIT 17 +#define R_NDS32_GNU_VTENTRY 18 + +/* RELA relocations */ +#define R_NDS32_16_RELA 19 +#define R_NDS32_32_RELA 20 +#define R_NDS32_20_RELA 21 +#define R_NDS32_9_PCREL_RELA 22 +#define R_NDS32_15_PCREL_RELA 23 +#define R_NDS32_17_PCREL_RELA 24 +#define R_NDS32_25_PCREL_RELA 25 +#define R_NDS32_HI20_RELA 26 +#define R_NDS32_LO12S3_RELA 27 +#define R_NDS32_LO12S2_RELA 28 +#define R_NDS32_LO12S1_RELA 29 +#define R_NDS32_LO12S0_RELA 30 +#define R_NDS32_SDA15S3_RELA 31 +#define R_NDS32_SDA15S2_RELA 32 +#define R_NDS32_SDA15S1_RELA 33 +#define R_NDS32_SDA15S0_RELA 34 +#define R_NDS32_RELA_GNU_VTINHERIT 35 +#define R_NDS32_RELA_GNU_VTENTRY 36 +#define R_NDS32_GOT20 37 +#define R_NDS32_25_PLTREL 38 +#define R_NDS32_COPY 39 +#define R_NDS32_GLOB_DAT 40 +#define R_NDS32_JMP_SLOT 41 +#define R_NDS32_RELATIVE 42 +#define R_NDS32_GOTOFF 43 +#define R_NDS32_GOTPC20 44 +#define R_NDS32_GOT_HI20 45 +#define R_NDS32_GOT_LO12 46 +#define R_NDS32_GOTPC_HI20 47 +#define R_NDS32_GOTPC_LO12 48 +#define R_NDS32_GOTOFF_HI20 49 +#define R_NDS32_GOTOFF_LO12 50 +#define R_NDS32_INSN16 51 +#define R_NDS32_LABEL 52 +#define R_NDS32_LONGCALL1 53 +#define R_NDS32_LONGCALL2 54 +#define R_NDS32_LONGCALL3 55 +#define R_NDS32_LONGJUMP1 56 +#define R_NDS32_LONGJUMP2 57 +#define R_NDS32_LONGJUMP3 58 +#define R_NDS32_LOADSTORE 59 +#define R_NDS32_9_FIXED_RELA 60 +#define R_NDS32_15_FIXED_RELA 61 +#define R_NDS32_17_FIXED_RELA 62 +#define R_NDS32_25_FIXED_RELA 63 +#define R_NDS32_PLTREL_HI20 64 +#define R_NDS32_PLTREL_LO12 65 +#define R_NDS32_PLT_GOTREL_HI20 66 +#define R_NDS32_PLT_GOTREL_LO12 67 + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small common symbol. */ +#define SHN_NDS32_SCOMMON 0xff00 + +/* Processor specific section flags. */ + +/* This section contains sufficient relocs to be relaxed. + When relaxing, even relocs of branch instructions the assembler could + complete must be present because relaxing may cause the branch target to + move. */ +#define SHF_NDS32_CAN_RELAX 0x10000000 + +/* ----------------------------------------------------------- */ +/* Processor specific flags for the ELF header e_flags field. */ +/* ----------------------------------------------------------- */ +/* 31 28 27 8 7 4 3 0 */ +/* ---------------------------------------------- */ +/* | ARCH | CONFUGURAION FIELD | ABI | VERSION | */ +/* ---------------------------------------------- */ + +/* ----------------------------------------------------------- */ +/* ARCHITECHURE DEFINITION */ +/* ----------------------------------------------------------- */ +/* 4-bit (b31-b28) nds32 architecture field. */ +/* we can have up to 15 architectures; 0000 is for unknown */ +#define EF_NDS_ARCH 0xF0000000 +/* 0x80000000 is for no 16-bit */ +/* there could be more architectures. but for now, only n1 and n1h */ +#define E_NDS_ARCH_STAR_RESERVED 0x00000000 /* for future extension */ +#define E_NDS_ARCH_STAR_V1_0 0x10000000 +#define E_NDS_ARCH_STAR_V0_9 0x90000000 /* old arch */ + +/* n1 code. */ +#define E_N1_ARCH E_NDS_ARCH_STAR_V0_9 +/* n1h code. */ +#define E_N1H_ARCH E_NDS_ARCH_STAR_V1_0 + +/* ----------------------------------------------------------- */ +/* CONFIGURATION FIELD DEFINITION FOR EACH ARCHITECTURE */ +/* ----------------------------------------------------------- */ +#define EF_NDS_INST 0x0FFFFF00 + +/* E_NDS_ARCH_STAR_V1_0 configuration fields */ + +/* MFUSR rt, PC and correct ISYNC, MSYNC instructions. */ +/* old N1213HC has no such instructions */ +#define E_NDS32_HAS_MFUSR_PC_INST 0x00000100 +/* C/C++ performance extension instructions. */ +#define E_NDS32_HAS_EXT_INST 0x00000200 +/* performance extension set II instructions. */ +#define E_NDS32_HAS_EXT2_INST 0x00000400 +/* Floating point processor instructions. */ +#define E_NDS32_HAS_FPU_INST 0x00000800 +/* audio instructions. */ +#define E_NDS32_HAS_AUDIO_INST 0x00001000 +/* DIV instructions. */ +#define E_NDS32_HAS_DIV_INST 0x00002000 +/* 16-bit instructions. */ +#define E_NDS32_HAS_16BIT_INST 0x00004000 +/* string operation instructions. */ +#define E_NDS32_HAS_STRING_INST 0x00008000 +/* reduced register file */ +#define E_NDS32_HAS_REDUCED_REGS 0x00010000 +/* video instructions */ +#define E_NDS32_HAS_VIDEO_INST 0x00020000 +/* encription instructions */ +#define E_NDS32_HAS_ENCRIPT_INST 0x00040000 +/* Single/Doulbe Precision Floating point processor instructions. */ +#define E_NDS32_HAS_FPU_DP_INST 0x00080000 +/* no MAC instruction used */ +#define E_NDS32_HAS_NO_MAC_INST 0x00100000 +/* L2 cache instruction */ +#define E_NDS32_HAS_L2C_INST 0x00200000 + + +/* 4-bit for ABI signature, allow up to 16 ABIs */ +/* 0 is for OLD ABI V0, 1 is for V1, the rest is reserved */ +/* only old N1213HC use V0 */ +/* New ABI is used due to return register is changed to r0 from r5 */ +#define EF_NDS_ABI 0x000000F0 +#define E_NDS_ABI_V0 0x00000000 +#define E_NDS_ABI_V1 0x00000010 + +/* this flag signifies the version of Andes ELF */ +/* some more information may exist somewhere which is TBD */ +#define EF_NDS32_ELF_VERSION 0x0000000F + +/* Andes ELF Version 1.2 and before */ +#define E_NDS32_ELF_VER_1_2 0x0 +/* Andes ELF Version 1.3 and after */ +#define E_NDS32_ELF_VER_1_3 0x1 + /* NIOS relocations. */ #define R_NIOS_NONE 0 #define R_NIOS_32 1 /* A 32 bit absolute relocation.*/ diff --git a/ldso/ldso/nds32/dl-debug.h b/ldso/ldso/nds32/dl-debug.h new file mode 100644 index 000000000..ef4c57d91 --- /dev/null +++ b/ldso/ldso/nds32/dl-debug.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Andes Technology, Inc. + * Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball. + */ + +static const char *_dl_reltypes_tab[] = +{ + [0] "R_NDS32_NONE", "R_NDS32_16", "R_NDS32_32", "R_NDS32_20", + [4] "R_NDS32_9_PCREL", "R_NDS32_15_PCREL", "R_NDS32_17_PCREL", "R_NDS32_25_PCREL", + [8] "R_NDS32_HI20", "R_NDS32_LO12S3", "R_NDS32_LO12S2", "R_NDS32_LO12S1", + [12] "R_NDS32_LO12S0", "R_NDS32_SDA15S3", "R_NDS32_SDA15S2", "R_NDS32_SDA15S1", + [16] "R_NDS32_SDA15S0", "R_NDS32_GNU_VTINHERIT", "R_NDS32_GNU_VTENTRY", "R_NDS32_16_RELA", + [20] "R_NDS32_32_RELA" "R_NDS32_20_RELA", "R_NDS32_9_PCREL_RELA", "R_NDS32_15_PCREL_RELA", + [24] "R_NDS32_17_PCREL_RELA", "R_NDS32_25_PCREL_RELA", "R_NDS32_HI20_RELA", "R_NDS32_LO12S3_RELA", + [28] "R_NDS32_LO12S2_RELA", "R_NDS32_LO12S1_RELA", "R_NDS32_LO12S0_RELA", "R_NDS32_SDA15S3_RELA", + [32] "R_NDS32_SDA15S2_RELA", "R_NDS32_SDA15S1_RELA", "R_NDS32_SDA15S0_RELA", "R_NDS32_RELA_GNU_VTINHERIT", + [36] "R_NDS32_RELA_GNU_VTENTRY", "R_NDS32_GOT20", "R_NDS32_25_PLTREL", "R_NDS32_COPY", + [40] "R_NDS32_GLOB_DAT", "R_NDS32_JMP_SLOT", "R_NDS32_RELATIVE", "R_NDS32_GOTOFF", + [44] "R_NDS32_GOTPC20", "R_NDS32_GOT_HI20", "R_NDS32_GOT_LO12", "R_NDS32_GOTPC_HI20", + [48] "R_NDS32_GOTPC_LO12", "R_NDS32_GOTOFF_HI20", "R_NDS32_GOTOFF_LO12", "R_NDS32_INSN16", + [52] "R_NDS32_LABEL", "R_NDS32_LONGCALL1", "R_NDS32_LONGCALL2", "R_NDS32_LONGCALL3", + [56] "R_NDS32_LONGJUMP1", "R_NDS32_LONGJUMP2", "R_NDS32_LONGJUMP3", "R_NDS32_LOADSTORE", + [60] "R_NDS32_9_FIXED_RELA", "R_NDS32_15_FIXED_RELA", "R_NDS32_17_FIXED_RELA", "R_NDS32_25_FIXED_RELA", + [64] "R_NDS32_PLTREL_HI20", "R_NDS32_PLTREL_LO12", "R_NDS32_PLT_GOTREL_HI20", "R_NDS32_PLT_GOTREL_LO12", +}; diff --git a/ldso/ldso/nds32/dl-startup.h b/ldso/ldso/nds32/dl-startup.h new file mode 100644 index 000000000..f700531ca --- /dev/null +++ b/ldso/ldso/nds32/dl-startup.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2016 Andes Technology, Inc. + * Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball. + */ + +/* Need bootstrap relocations */ +#define ARCH_NEEDS_BOOTSTRAP_RELOCS + +#if defined(NDS32_ABI_2) || defined(NDS32_ABI_2FP) +# define STACK_PUSH +# define STACK_POP +#else +# define STACK_PUSH "addi $sp, $sp, -24" +# define STACK_POP "addi $sp, $sp, 24" +#endif + + +#ifdef __NDS32_N1213_43U1H__ +__asm__("\ + .text\n\ + .globl _start\n\ + .globl _dl_start\n\ + .globl _dl_start_user\n\ + .type _start,#function\n\ + .type _dl_start,#function\n\ + .type _dl_start_user,#function\n\ + .align 4\n\ + .pic\n\ +1:\n\ + ret\n\ +_start:\n\ + ! we are PIC code, so get global offset table\n\ + jal 1b\n\ + sethi $gp, HI20(_GLOBAL_OFFSET_TABLE_)\n\ + ori $gp, $gp, LO12(_GLOBAL_OFFSET_TABLE_+4)\n\ + add $gp, $lp, $gp\n\ +\n\ + ! at start time, all the args are on the stack\n\ + addi $r0, $sp, 0\n\ + ! adjust stack\n\ + !addi $sp, $sp, -24\n\ + "STACK_PUSH"\n\ + bal _dl_start@PLT\n\ + ! save user entry point in r6\n\ + addi $r6, $r0, 0\n\ + ! adjust sp and reload registers\n\ + !addi $sp, $sp, 24\n\ + "STACK_POP"\n\ +\n\ +_dl_start_user:\n\ +\n\ + ! See if we were run as a command with the executable file\n\ + ! name as an extra leading argument.\n\ + ! skip these arguments\n\ + l.w $r2, _dl_skip_args@GOTOFF ! args to skip\n\ + lwi $r0, [$sp+0] ! original argc\n\ + slli $r1, $r2, 2 ! offset for new sp\n\ + add $sp, $sp, $r1 ! adjust sp to skip args\n\ + sub $r0, $r0, $r2 ! set new argc\n\ + swi $r0, [$sp+0] ! save new argc\n\ +\n\ + ! load address of _dl_fini finalizer function\n\ + la $r5, _dl_fini@GOTOFF\n\ + ! jump to the user_s entry point\n\ + addi $r15, $r6, 0\n\ + jr $r15\n\ + .size _dl_start_user, . - _dl_start_user\n\ + .previous\n\ +"); +#else +__asm__("\ + .text\n\ + .globl _start\n\ + .globl _dl_start\n\ + .globl _dl_start_user\n\ + .type _start,#function\n\ + .type _dl_start,#function\n\ + .type _dl_start_user,#function\n\ + .align 4\n\ + .pic\n\ +_start:\n\ + ! we are PIC code, so get global offset table\n\ + mfusr $r15, $PC \n\ + sethi $gp, HI20(_GLOBAL_OFFSET_TABLE_ + 4)\n\ + ori $gp, $gp, LO12(_GLOBAL_OFFSET_TABLE_ + 8)\n\ + add $gp, $r15, $gp\n\ +\n\ + ! at start time, all the args are on the stack\n\ + addi $r0, $sp, 0\n\ + ! adjust stack\n\ + !addi $sp, $sp, -24\n\ + "STACK_PUSH"\n\ + bal _dl_start@PLT\n\ + ! save user entry point in r6\n\ + addi $r6, $r0, 0\n\ + ! adjust sp and reload registers\n\ + !addi $sp, $sp, 24\n\ + "STACK_POP"\n\ +\n\ +_dl_start_user:\n\ + ! See if we were run as a command with the executable file\n\ + ! name as an extra leading argument.\n\ + ! skip these arguments\n\ + l.w $r2, _dl_skip_args@GOTOFF ! args to skip\n\ + lwi $r0, [$sp+0] ! original argc\n\ + slli $r1, $r2, 2 ! offset for new sp\n\ + add $sp, $sp, $r1 ! adjust sp to skip args\n\ + sub $r0, $r0, $r2 ! set new argc\n\ + swi $r0, [$sp+0] ! save new argc\n\ +\n\ + ! load address of _dl_fini finalizer function\n\ + la $r5, _dl_fini@GOTOFF\n\ + ! jump to the user_s entry point\n\ + jr $r6\n\ + .size _dl_start_user, . - _dl_start_user\n\ + .previous\n\ +"); +#endif + +#define COPY_UNALIGNED_WORD(swp, twp, align) \ + { \ + void *__s = (swp), *__t = (twp); \ + unsigned char *__s1 = __s, *__t1 = __t; \ + unsigned short *__s2 = __s, *__t2 = __t; \ |