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| author | Manuel Novoa III <mjn3@codepoet.org> | 2003-11-16 16:26:35 +0000 |
|---|---|---|
| committer | Manuel Novoa III <mjn3@codepoet.org> | 2003-11-16 16:26:35 +0000 |
| commit | f6552f749d672154866d7b82f4edba2321b80b97 (patch) | |
| tree | 590c3506a00e4bedb174726a46da25b9a5954035 | |
| parent | 9f77c8c4934538ef7bc6964d8a7e6ac0945c8447 (diff) | |
Patch from Jeffrey Baitis <baitisj@evolution.com> for mips arch tuning.
| -rw-r--r-- | Rules.mak | 9 | ||||
| -rw-r--r-- | extra/Configs/Config.mips | 36 |
2 files changed, 45 insertions, 0 deletions
@@ -127,6 +127,15 @@ ifeq ($(strip $(TARGET_ARCH)),arm) CPU_CFLAGS-$(CONFIG_ARM_XSCALE)+=-march=armv4 -Wa,-mcpu=xscale endif +ifeq ($(strip $(TARGET_ARCH)),mips) + CPU_CFLAGS-$(CONFIG_MIPS_ISA_1)+=-mips1 + CPU_CFLAGS-$(CONFIG_MIPS_ISA_2)+=-mips2 -mtune=mips2 + CPU_CFLAGS-$(CONFIG_MIPS_ISA_3)+=-mips3 -mtune=mips3 + CPU_CFLAGS-$(CONFIG_MIPS_ISA_4)+=-mips4 -mtune=mips4 + CPU_CFLAGS-$(CONFIG_MIPS_ISA_MIPS32)+=-mips32 -mtune=mips32 + CPU_CFLAGS-$(CONFIG_MIPS_ISA_MIPS64)+=-mips64 -mtune=mips32 +endif + ifeq ($(strip $(TARGET_ARCH)),sh) OPTIMIZATION+=-fstrict-aliasing OPTIMIZATION+= $(call check_gcc,-mprefergot,) diff --git a/extra/Configs/Config.mips b/extra/Configs/Config.mips index 777c23869..273e8743d 100644 --- a/extra/Configs/Config.mips +++ b/extra/Configs/Config.mips @@ -20,3 +20,39 @@ config ARCH_LDFLAGS config LIBGCC_CFLAGS string +choice + prompt "Target Processor Architecture" + default CONFIG_MIPS_ISA_1 + help + This selects the instruction set architecture of your MIPS CPU. This + information is used for optimizing purposes. To build a library that + will run on any MIPS CPU, you can specify "Generic (MIPS I)" here. + If you pick anything other than "Generic (MIPS I)," there is no + guarantee that uClibc will even run on anything other than the + selected processor type. + + You should probably select the MIPS ISA that best matches the + CPU you will be using on your device. uClibc will be tuned + for that architecture. + + If you don't know what to do, choose "Generic (MIPS I)" + +config CONFIG_MIPS_ISA_1 + bool "Generic (MIPS I)" + +config CONFIG_MIPS_ISA_2 + bool "MIPS II" + +config CONFIG_MIPS_ISA_3 + bool "MIPS III" + +config CONFIG_MIPS_ISA_4 + bool "MIPS IV" + +config CONFIG_MIPS_ISA_MIPS32 + bool "MIPS32" + +config CONFIG_MIPS_ISA_MIPS64 + bool "MIPS64" + +endchoice |