diff options
Diffstat (limited to 'toolchain')
65 files changed, 6482 insertions, 772 deletions
diff --git a/toolchain/binutils/Makefile b/toolchain/binutils/Makefile index c0c61f7b9..63b1080fb 100644 --- a/toolchain/binutils/Makefile +++ b/toolchain/binutils/Makefile @@ -28,6 +28,10 @@ else CONFOPTS+= --disable-gold endif +ifeq ($(ADK_TARGET_ARCH_ARC),y) +CONFOPTS+= --enable-lto --enable-plugins +endif + ifeq ($(ADK_TARGET_ARCH_X86_64)$(ADK_TARGET_CPU_CF),) CONFOPTS+= --disable-multilib else diff --git a/toolchain/binutils/Makefile.inc b/toolchain/binutils/Makefile.inc index e2a91f6b3..758539cf0 100644 --- a/toolchain/binutils/Makefile.inc +++ b/toolchain/binutils/Makefile.inc @@ -2,40 +2,61 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= binutils -ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_38),y) -PKG_VERSION:= 2.38 +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_42),y) +PKG_VERSION:= 2.42 PKG_RELEASE:= 1 -PKG_HASH:= e316477a914f567eccc34d5d29785b8b0f5a10208d36bbacedcc39048ecfe024 +PKG_HASH:= 5d2a6c1d49686a557869caae08b6c2e83699775efd27505e01b2f4db1a024ffc PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_37),y) -PKG_VERSION:= 2.37 +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_41),y) +PKG_VERSION:= 2.41 PKG_RELEASE:= 1 -PKG_HASH:= 820d9724f020a3e69cb337893a0b63c2db161dadcb0e06fc11dc29eb1e84a32c +PKG_HASH:= 48d00a8dc73aa7d2394a7dc069b96191d95e8de8f0da6dc91da5cce655c20e45 PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_28),y) -PKG_VERSION:= 2.28 +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_40),y) +PKG_VERSION:= 2.40 PKG_RELEASE:= 1 -PKG_HASH:= cd717966fc761d840d451dbd58d44e1e5b92949d2073d75b73fccb476d772fcf +PKG_HASH:= d7f82c4047decf43a6f769ac32456a92ddb6932409a585c633cdd4e9df23d956 PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_ARC),y) -PKG_VERSION:= arc-2021.09 -PKG_GIT:= tag -PKG_RELEASE:= 1 -PKG_SITES:= https://github.com/foss-for-synopsys-dwc-arc-processors/binutils-gdb.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_39),y) +PKG_VERSION:= 2.39 +PKG_RELEASE:= 1 +PKG_HASH:= d12ea6f239f1ffe3533ea11ad6e224ffcb89eb5d01bbea589e9158780fa11f10 +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_38),y) +PKG_VERSION:= 2.38 +PKG_RELEASE:= 1 +PKG_HASH:= b3f1dc5b17e75328f19bd88250bee2ef9f91fc8cbb7bd48bdb31390338636052 +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_37),y) +PKG_VERSION:= 2.37 +PKG_RELEASE:= 1 +PKG_HASH:= c44968b97cd86499efbc4b4ab7d98471f673e5414c554ef54afa930062dbbfcb +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_BINUTILS_KVX),y) PKG_VERSION:= 782547a4e2bdf1308728032853678ca69bb154ea PKG_GIT:= hash PKG_RELEASE:= 1 PKG_SITES:= https://github.com/kalray/gdb-binutils.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_ARC),y) +PKG_VERSION:= arc-2023.09 +PKG_GIT:= tag +PKG_RELEASE:= 1 +PKG_SITES:= https://github.com/foss-for-synopsys-dwc-arc-processors/binutils-gdb.git +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_BINUTILS_AVR32),y) PKG_VERSION:= 2.20.1 @@ -48,5 +69,5 @@ ifeq ($(ADK_TOOLCHAIN_BINUTILS_GIT),y) PKG_VERSION:= git PKG_RELEASE:= 1 PKG_SITES:= git://sourceware.org/git/binutils-gdb.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif diff --git a/toolchain/binutils/patches/2.20.1/newer-gcc.patch b/toolchain/binutils/patches/2.20.1/newer-gcc.patch new file mode 100644 index 000000000..b7f42e447 --- /dev/null +++ b/toolchain/binutils/patches/2.20.1/newer-gcc.patch @@ -0,0 +1,24 @@ +diff -Nur binutils-2.20.1.orig/binutils/readelf.c binutils-2.20.1/binutils/readelf.c +--- binutils-2.20.1.orig/binutils/readelf.c 2023-02-03 11:04:53.722082738 +0100 ++++ binutils-2.20.1/binutils/readelf.c 2023-02-03 11:05:27.049296372 +0100 +@@ -150,7 +150,7 @@ + #include "filenames.h" + + char * program_name = "readelf"; +-int do_wide; ++extern int do_wide; + static long archive_file_offset; + static unsigned long archive_file_size; + static unsigned long dynamic_addr; +diff -Nur binutils-2.20.1.orig/gas/config/tc-avr32.c binutils-2.20.1/gas/config/tc-avr32.c +--- binutils-2.20.1.orig/gas/config/tc-avr32.c 2023-02-03 11:04:53.726082644 +0100 ++++ binutils-2.20.1/gas/config/tc-avr32.c 2023-02-03 11:06:12.164234434 +0100 +@@ -47,7 +47,7 @@ + + /* Flags given on the command line */ + static int avr32_pic = FALSE; +-int linkrelax = FALSE; ++//extern int linkrelax = FALSE; + int avr32_iarcompat = FALSE; + + /* This array holds the chars that always start a comment. */ diff --git a/toolchain/binutils/patches/2.28/lm32.patch b/toolchain/binutils/patches/2.28/lm32.patch new file mode 100644 index 000000000..962281625 --- /dev/null +++ b/toolchain/binutils/patches/2.28/lm32.patch @@ -0,0 +1,24 @@ +diff -Nur binutils-2.28.orig/bfd/config.bfd binutils-2.28/bfd/config.bfd +--- binutils-2.28.orig/bfd/config.bfd 2017-03-02 09:23:53.000000000 +0100 ++++ binutils-2.28/bfd/config.bfd 2023-08-27 11:54:08.526040118 +0200 +@@ -924,7 +924,7 @@ + ;; + + lm32-*-*linux*) +- targ_defvec=lm32_elf32_fdpic_vec ++ targ_defvec=lm32_elf32_vec + targ_selvecs=lm32_elf32_vec + ;; + +diff -Nur binutils-2.28.orig/ld/configure.tgt binutils-2.28/ld/configure.tgt +--- binutils-2.28.orig/ld/configure.tgt 2017-03-02 09:23:54.000000000 +0100 ++++ binutils-2.28/ld/configure.tgt 2023-08-27 11:54:43.882874903 +0200 +@@ -416,7 +416,7 @@ + ;; + iq2000-*-elf) targ_emul=elf32iq2000 ; targ_extra_emuls="elf32iq10" + ;; +-lm32-*-*linux*) targ_emul=elf32lm32fd ;; ++lm32-*-*linux*) targ_emul=elf32lm32 ;; + lm32-*-*) targ_emul=elf32lm32 ; targ_extra_emuls="elf32lm32fd" + ;; + m32c-*-elf | m32c-*-rtems*) diff --git a/toolchain/binutils/patches/2.41/lm32.patch b/toolchain/binutils/patches/2.41/lm32.patch new file mode 100644 index 000000000..dcbb0d541 --- /dev/null +++ b/toolchain/binutils/patches/2.41/lm32.patch @@ -0,0 +1,24 @@ +diff -Nur binutils-2.41.orig/bfd/config.bfd binutils-2.41/bfd/config.bfd +--- binutils-2.41.orig/bfd/config.bfd 2023-07-03 01:00:00.000000000 +0200 ++++ binutils-2.41/bfd/config.bfd 2023-09-07 17:03:12.853045008 +0200 +@@ -803,7 +803,7 @@ + ;; + + lm32-*-*linux*) +- targ_defvec=lm32_elf32_fdpic_vec ++ targ_defvec=lm32_elf32_vec + targ_selvecs=lm32_elf32_vec + ;; + +diff -Nur binutils-2.41.orig/ld/configure.tgt binutils-2.41/ld/configure.tgt +--- binutils-2.41.orig/ld/configure.tgt 2023-07-03 01:00:00.000000000 +0200 ++++ binutils-2.41/ld/configure.tgt 2023-09-07 17:03:44.364298973 +0200 +@@ -468,7 +468,7 @@ + targ_extra_emuls="elf32iq10" + targ_extra_ofiles=ldelfgen.o + ;; +-lm32-*-*linux*) targ_emul=elf32lm32fd ++lm32-*-*linux*) targ_emul=elf32lm32 + ;; + lm32-*-*) targ_emul=elf32lm32 + targ_extra_emuls="elf32lm32fd" diff --git a/toolchain/binutils/patches/2.42/j2.patch b/toolchain/binutils/patches/2.42/j2.patch new file mode 100644 index 000000000..42c7274aa --- /dev/null +++ b/toolchain/binutils/patches/2.42/j2.patch @@ -0,0 +1,584 @@ +diff -Nur binutils-2.42.orig/bfd/archures.c binutils-2.42/bfd/archures.c +--- binutils-2.42.orig/bfd/archures.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/bfd/archures.c 2024-02-22 16:50:03.657904349 +0100 +@@ -284,10 +284,12 @@ + .#define bfd_mach_sh_dsp 0x2d + .#define bfd_mach_sh2a 0x2a + .#define bfd_mach_sh2a_nofpu 0x2b ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +diff -Nur binutils-2.42.orig/bfd/bfd-in2.h binutils-2.42/bfd/bfd-in2.h +--- binutils-2.42.orig/bfd/bfd-in2.h 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/bfd/bfd-in2.h 2024-02-22 16:50:03.661904381 +0100 +@@ -1540,10 +1540,12 @@ + #define bfd_mach_sh_dsp 0x2d + #define bfd_mach_sh2a 0x2a + #define bfd_mach_sh2a_nofpu 0x2b ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +diff -Nur binutils-2.42.orig/bfd/cpu-sh.c binutils-2.42/bfd/cpu-sh.c +--- binutils-2.42.orig/bfd/cpu-sh.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/bfd/cpu-sh.c 2024-02-22 16:50:03.661904381 +0100 +@@ -63,7 +63,9 @@ + N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16), + N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17), + N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", false, arch_info_struct + 18), +- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL) ++ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, arch_info_struct + 19), ++ N (bfd_mach_shj2, "j2", false, arch_info_struct + 20), ++ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-nofpu-or-sh3-nommu-or-j2-nofpu", false, NULL) + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -99,6 +101,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +diff -Nur binutils-2.42.orig/binutils/readelf.c binutils-2.42/binutils/readelf.c +--- binutils-2.42.orig/binutils/readelf.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/binutils/readelf.c 2024-02-22 16:53:19.799614987 +0100 +@@ -4326,6 +4326,12 @@ + case EF_SH2A_SH3E: + out = stpcpy (out, ", sh2a-or-sh3e"); + break; ++ case EF_SHJ2: ++ out = stpcpy (out, ", j2"); ++ break; ++ case EF_SH2A_SH3_SHJ2: ++ out = stpcpy (out, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); ++ break; + default: + out = stpcpy (out, _(", unknown ISA")); + break; +diff -Nur binutils-2.42.orig/gas/config/tc-sh.c binutils-2.42/gas/config/tc-sh.c +--- binutils-2.42.orig/gas/config/tc-sh.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/config/tc-sh.c 2024-02-22 16:50:03.685904574 +0100 +@@ -1251,6 +1251,8 @@ + if (*ptr == ',') + ptr++; + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + } + } +@@ -1775,7 +1777,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2024-02-22 16:50:03.685904574 +0100 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2024-02-22 16:50:03.685904574 +0100 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2024-02-22 16:50:03.685904574 +0100 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2024-02-22 16:50:03.689904606 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2024-02-22 16:50:03.689904606 +0100 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a.s 2024-02-22 16:50:03.689904606 +0100 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3-dsp.s 2024-02-22 16:50:03.689904606 +0100 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3e.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3e.s 2024-02-22 16:50:03.689904606 +0100 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3-nommu.s 2024-02-22 16:50:03.689904606 +0100 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3.s 2024-02-22 16:50:03.689904606 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2024-02-22 16:50:03.689904606 +0100 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2024-02-22 16:50:03.693904638 +0100 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4a.s 2024-02-22 16:50:03.693904638 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2024-02-22 16:50:03.693904638 +0100 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2024-02-22 16:50:03.693904638 +0100 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4.s 2024-02-22 16:50:03.693904638 +0100 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/include/elf/sh.h binutils-2.42/include/elf/sh.h +--- binutils-2.42.orig/include/elf/sh.h 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/include/elf/sh.h 2024-02-22 16:50:03.693904638 +0100 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -Nur binutils-2.42.orig/opcodes/sh-dis.c binutils-2.42/opcodes/sh-dis.c +--- binutils-2.42.orig/opcodes/sh-dis.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/opcodes/sh-dis.c 2024-02-22 16:50:03.693904638 +0100 +@@ -866,6 +866,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +diff -Nur binutils-2.42.orig/opcodes/sh-opc.h binutils-2.42/opcodes/sh-opc.h +--- binutils-2.42.orig/opcodes/sh-opc.h 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/opcodes/sh-opc.h 2024-02-22 16:50:03.697904670 +0100 +@@ -192,7 +192,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -216,9 +217,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -256,6 +259,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -320,7 +325,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -346,6 +352,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -714,9 +726,9 @@ + + /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1194,7 +1206,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + diff --git a/toolchain/binutils/patches/2.42/kvx.patch b/toolchain/binutils/patches/2.42/kvx.patch new file mode 100644 index 000000000..c3690ca8e --- /dev/null +++ b/toolchain/binutils/patches/2.42/kvx.patch @@ -0,0 +1,29 @@ +From 234938d8b7df2f069c6cbbaff47eb2ba338ec532 Mon Sep 17 00:00:00 2001 +From: Paul Iannetta <piannetta@kalrayinc.com> +Date: Mon, 4 Sep 2023 15:31:53 +0200 +Subject: [PATCH] kvx: gas: fix the detection of negative powers of 2 + +gas/ChangeLog: + +2023-09-04 Paul Iannetta <piannetta@kalrayinc.com> + + * config/kvx-parse.c (get_token_class): Use the signed value. + +--- + gas/config/kvx-parse.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gas/config/kvx-parse.c b/gas/config/kvx-parse.c +index bb51c861625..0bd6b75ef30 100644 +--- a/gas/config/kvx-parse.c ++++ b/gas/config/kvx-parse.c +@@ -525,7 +525,7 @@ get_token_class (struct token_s *token, struct token_classes *classes, int insn_ + : strtoull (tok + (tok[0] == '-') + (tok[0] == '+'), NULL, 0)); + int64_t val = uval; + int64_t pval = val < 0 ? -uval : uval; +- int neg_power2_p = val < 0 && !(uval & (uval - 1)); ++ int neg_power2_p = val < 0 && !(pval & (pval - 1)); + unsigned len = pval ? 8 * sizeof (pval) - __builtin_clzll (pval) : 0; + while (class[cur].class_id != -1 + && ((unsigned) (class[cur].sz < 0 + diff --git a/toolchain/elf2flt/Makefile b/toolchain/elf2flt/Makefile index c1ee12ca6..8e5fec5a4 100644 --- a/toolchain/elf2flt/Makefile +++ b/toolchain/elf2flt/Makefile @@ -8,23 +8,38 @@ include $(ADK_TOPDIR)/mk/buildhlp.mk ifeq ($(ADK_TOOLCHAIN_BINUTILS_GIT),y) BINUTILS_VERSION:= git +BFDLIB:= .libs/libbfd.a endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_38),y) -BINUTILS_VERSION:= 2.38 +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_42),y) +BINUTILS_VERSION:= 2.42 +BFDLIB:= .libs/libbfd.a +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_41),y) +BINUTILS_VERSION:= 2.41 +BFDLIB:= .libs/libbfd.a +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_40),y) +BINUTILS_VERSION:= 2.40 +BFDLIB:= libbfd.a +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_39),y) +BINUTILS_VERSION:= 2.39 +BFDLIB:= libbfd.a endif ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_28),y) BINUTILS_VERSION:= 2.28 +BFDLIB:= libbfd.a endif $(WRKBUILD)/.configured: - (cd $(WRKBUILD); autoreconf -vif;) + (cd $(WRKBUILD); PATH='${HOST_PATH}' autoreconf -vif;) (cd $(WRKBUILD); \ CPPFLAGS="-idirafter $(ADK_TOPDIR)/adk/include" \ ./configure --prefix=$(STAGING_HOST_DIR)/usr \ --target=$(GNU_TARGET_NAME) \ --with-bfd-include-dir=$(TOOLCHAIN_BUILD_DIR)/w-binutils-$(BINUTILS_VERSION)-1/binutils-$(BINUTILS_VERSION)/bfd \ --with-binutils-include-dir=$(TOOLCHAIN_BUILD_DIR)/w-binutils-$(BINUTILS_VERSION)-1/binutils-$(BINUTILS_VERSION)/include \ - --with-libbfd=$(TOOLCHAIN_BUILD_DIR)/w-binutils-$(BINUTILS_VERSION)-1/binutils-$(BINUTILS_VERSION)/bfd/libbfd.a \ + --with-libbfd=$(TOOLCHAIN_BUILD_DIR)/w-binutils-$(BINUTILS_VERSION)-1/binutils-$(BINUTILS_VERSION)/bfd/$(BFDLIB) \ --with-libiberty=$(TOOLCHAIN_BUILD_DIR)/w-binutils-$(BINUTILS_VERSION)-1/binutils-$(BINUTILS_VERSION)/libiberty/libiberty.a ) touch $@ diff --git a/toolchain/elf2flt/Makefile.inc b/toolchain/elf2flt/Makefile.inc index 15434aeee..dee90e037 100644 --- a/toolchain/elf2flt/Makefile.inc +++ b/toolchain/elf2flt/Makefile.inc @@ -2,7 +2,16 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= elf2flt +ifeq ($(ADK_TOOLCHAIN_ELF2FLT_2024_02),y) +PKG_VERSION:= v2024.02 +PKG_GIT:= tag +PKG_RELEASE:= 1 +PKG_SITES:= https://github.com/uclinux-dev/elf2flt.git +endif +ifeq ($(ADK_TOOLCHAIN_ELF2FLT_OLD),y) PKG_VERSION:= 453398f917d167f8c308c8f997270c48ae8f8b12 PKG_GIT:= hash PKG_RELEASE:= 1 PKG_SITES:= https://github.com/uclinux-dev/elf2flt.git +endif +DISTFILES:= $(PKG_NAME)-$(PKG_VERSION).tar.gz diff --git a/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0001-riscv32.patch b/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0001-riscv32.patch new file mode 100644 index 000000000..a99de4f9f --- /dev/null +++ b/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0001-riscv32.patch @@ -0,0 +1,42 @@ +diff -Nur elf2flt-v2023.04.orig/elf2flt.c elf2flt-v2023.04/elf2flt.c +--- elf2flt-v2023.04.orig/elf2flt.c 2023-09-04 11:29:05.952417209 +0200 ++++ elf2flt-v2023.04/elf2flt.c 2023-09-04 11:30:05.371065966 +0200 +@@ -81,7 +81,7 @@ + #include <elf/v850.h> + #elif defined(TARGET_xtensa) + #include <elf/xtensa.h> +-#elif defined(TARGET_riscv64) ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32) + #include <elf/riscv.h> + #endif + +@@ -127,6 +127,8 @@ + #define ARCH "xtensa" + #elif defined(TARGET_riscv64) + #define ARCH "riscv64" ++#elif defined(TARGET_riscv32) ++#define ARCH "riscv32" + #else + #error "Don't know how to support your CPU architecture??" + #endif +@@ -822,7 +824,7 @@ + goto good_32bit_resolved_reloc_update_text; + default: + goto bad_resolved_reloc; +-#elif defined(TARGET_riscv64) ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32) + case R_RISCV_NONE: + case R_RISCV_32_PCREL: + case R_RISCV_ADD8: +diff -Nur elf2flt-v2023.04.orig/ld-elf2flt.c elf2flt-v2023.04/ld-elf2flt.c +--- elf2flt-v2023.04.orig/ld-elf2flt.c 2023-09-04 11:28:59.072573514 +0200 ++++ elf2flt-v2023.04/ld-elf2flt.c 2023-09-04 11:29:32.507813592 +0200 +@@ -327,7 +327,7 @@ + /* riscv adds a global pointer symbol to the linker file with the + "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and + the entire line for other architectures. */ +- if (streq(TARGET_CPU, "riscv64")) ++ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32")) + append_sed(&sed, "^RISCV_GP:", ""); + else + append_sed(&sed, "^RISCV_GP:", NULL); diff --git a/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0002-lm32.patch b/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0002-lm32.patch new file mode 100644 index 000000000..b24b214c7 --- /dev/null +++ b/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0002-lm32.patch @@ -0,0 +1,167 @@ +diff -Nur elf2flt.orig/elf2flt.c elf2flt/elf2flt.c +--- elf2flt.orig/elf2flt.c 2023-09-07 15:59:10.019349031 +0200 ++++ elf2flt/elf2flt.c 2023-09-07 16:40:06.281961316 +0200 +@@ -62,6 +62,8 @@ + #include <elf/bfin.h> + #elif defined(TARGET_h8300) + #include <elf/h8.h> ++#elif defined(TARGET_lm32) ++#include <elf/lm32.h> + #elif defined(TARGET_m68k) + #include <elf/m68k.h> + #elif defined(TARGET_microblaze) +@@ -123,6 +125,11 @@ + #define ARCH "nios" + #elif defined(TARGET_nios2) + #define ARCH "nios2" ++#elif defined(TARGET_lm32) ++#define ARCH "lm32" ++#define FLAT_LM32_RELOC_TYPE_32_BIT 0 ++#define FLAT_LM32_RELOC_TYPE_HI16_BIT 1 ++#define FLAT_LM32_RELOC_TYPE_LO16_BIT 2 + #elif defined(TARGET_xtensa) + #define ARCH "xtensa" + #elif defined(TARGET_riscv64) +@@ -373,7 +380,7 @@ + int bad_relocs = 0; + asymbol **symb; + long nsymb; +-#ifdef TARGET_bfin ++#if defined (TARGET_bfin) || defined (TARGET_lm32) + unsigned long persistent_data = 0; + #endif + +@@ -690,6 +697,36 @@ + break; + default: + goto bad_resolved_reloc; ++#elif defined(TARGET_lm32) ++ case R_LM32_HI16: ++ case R_LM32_LO16: ++ if (q->howto->type == R_LM32_HI16) { ++ pflags = FLAT_LM32_RELOC_TYPE_HI16_BIT << 29; ++ } else { ++ pflags = FLAT_LM32_RELOC_TYPE_LO16_BIT << 29; ++ } ++ ++ relocation_needed = 1; ++ ++ /* remember the upper 16 bits */ ++ if ((0xffff0000 & sym_addr) != persistent_data) { ++ flat_relocs = (uint32_t *) ++ (realloc (flat_relocs, (flat_reloc_count + 1) * sizeof (uint32_t))); ++ if (verbose) ++ printf ("New persistent data for %08lx\n", sym_addr); ++ persistent_data = 0xffff0000 & sym_addr; ++ flat_relocs[flat_reloc_count++] = (sym_addr >> 16) | (3 << 29); ++ } ++ break; ++ case R_LM32_32: ++ pflags = FLAT_LM32_RELOC_TYPE_32_BIT << 29; ++ relocation_needed = 1; ++ break; ++ case R_LM32_CALL: ++ relocation_needed = 0; ++ break; ++ default: ++ goto bad_resolved_reloc; + #elif defined(TARGET_m68k) + case R_68K_32: + goto good_32bit_resolved_reloc; +@@ -1478,6 +1515,63 @@ + #undef _30BITS_RELOC + #undef _28BITS_RELOC + #endif ++#ifdef TARGET_lm32 ++ case R_LM32_32: ++ { ++ pflags = FLAT_LM32_RELOC_TYPE_32_BIT << 29; ++ sym_vma = elf2flt_bfd_section_vma(sym_section); ++ sym_addr += sym_vma + q->addend; ++ relocation_needed = 1; ++ break; ++ } ++ case R_LM32_CALL: ++ { ++ sym_vma = 0; ++ sym_addr += sym_vma + q->addend; ++ sym_addr -= q->address; ++ sym_addr = (int32_t)sym_addr >> q->howto->rightshift; ++ ++ if ((int32_t)sym_addr < -0x8000000 || (int32_t)sym_addr > 0x7ffffff) { ++ printf("ERROR: Relocation overflow for R_LM32_CALL relocation against %s\n", sym_name); ++ bad_relocs++; ++ continue; ++ } ++ ++ r_mem[0] |= (sym_addr >> 24) & 0x03; ++ r_mem[1] = (sym_addr >> 16) & 0xff; ++ r_mem[2] = (sym_addr >> 8) & 0xff; ++ r_mem[3] = sym_addr & 0xff; ++ break; ++ } ++ case R_LM32_HI16: ++ case R_LM32_LO16: ++ { ++ if (q->howto->type == R_LM32_HI16) { ++ pflags = FLAT_LM32_RELOC_TYPE_HI16_BIT << 29; ++ } else { ++ pflags = FLAT_LM32_RELOC_TYPE_LO16_BIT << 29; ++ } ++ ++ sym_vma = elf2flt_bfd_section_vma(sym_section); ++ sym_addr += sym_vma + q->addend; ++ ++ relocation_needed = 1; ++ ++ /* remember the upper 16 bits */ ++ if ((0xffff0000 & sym_addr) != persistent_data) { ++ flat_relocs = (uint32_t *) ++ (realloc (flat_relocs, (flat_reloc_count + 1) * sizeof (uint32_t))); ++ if (verbose) ++ printf ("New persistent data for %08lx\n", sym_addr); ++ persistent_data = 0xffff0000 & sym_addr; ++ flat_relocs[flat_reloc_count++] = (sym_addr >> 16) | (3 << 29); ++ } ++ ++ r_mem[2] = (sym_addr >> 8) & 0xff; ++ r_mem[3] = sym_addr & 0xff; ++ break; ++ } ++#endif /* TARGET_lm32 */ + default: + /* missing support for other types of relocs */ + printf("ERROR: bad reloc type (%s)%d\n", q->howto->name, (*p)->howto->type); +@@ -1616,6 +1710,13 @@ + break; + #endif + ++#ifdef TARGET_lm32 ++ case R_LM32_HI16: ++ case R_LM32_LO16: ++ case R_LM32_CALL: ++ /* entry has already been written */ ++ break; ++#endif + default: + /* The alignment of the build host + might be stricter than that of the +diff -Nur elf2flt.orig/elf2flt.ld.in elf2flt/elf2flt.ld.in +--- elf2flt.orig/elf2flt.ld.in 2023-09-07 11:32:34.223463015 +0200 ++++ elf2flt/elf2flt.ld.in 2023-09-07 16:06:02.781672190 +0200 +@@ -73,6 +73,7 @@ + W_RODAT: *(.rodata1) + W_RODAT: *(.rodata.*) + W_RODAT: *(.gnu.linkonce.r*) ++W_RODAT: *(.rofixup) + + /* .ARM.extab name sections containing exception unwinding information */ + *(.ARM.extab* .gnu.linkonce.armextab.*) +@@ -111,6 +112,7 @@ + R_RODAT: *(.rodata1) + R_RODAT: *(.rodata.*) + R_RODAT: *(.gnu.linkonce.r*) ++R_RODAT: *(.rofixup) + *(.data) + *(.data1) + *(.data.*) diff --git a/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0003-sh2.patch b/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0003-sh2.patch new file mode 100644 index 000000000..9587a0315 --- /dev/null +++ b/toolchain/elf2flt/patches/26dfb54a59c8c0106418a0c46ccb4288d9e066fd/0003-sh2.patch @@ -0,0 +1,52 @@ +diff -Nur elf2flt-26dfb54a59c8c0106418a0c46ccb4288d9e066fd.orig/elf2flt.c elf2flt-26dfb54a59c8c0106418a0c46ccb4288d9e066fd/elf2flt.c +--- elf2flt-26dfb54a59c8c0106418a0c46ccb4288d9e066fd.orig/elf2flt.c 2023-09-08 08:49:00.529082893 +0200 ++++ elf2flt-26dfb54a59c8c0106418a0c46ccb4288d9e066fd/elf2flt.c 2023-09-08 08:51:08.117679134 +0200 +@@ -75,7 +75,7 @@ + #define FLAT_NIOS2_R_HIADJ_LO 2 + #define FLAT_NIOS2_R_CALL26 4 + #include <elf/nios2.h> +-#elif defined(TARGET_sh) ++#elif defined(TARGET_sh2eb) + #include <elf/sh.h> + #elif defined(TARGET_sparc) + #include <elf/sparc.h> +@@ -111,7 +111,7 @@ + #define ARCH "sparc" + #elif defined(TARGET_v850) + #define ARCH "v850" +-#elif defined(TARGET_sh) ++#elif defined(TARGET_sh2eb) + #define ARCH "sh" + #elif defined(TARGET_h8300) + #define ARCH "h8300" +@@ -795,6 +795,12 @@ + + flat_reloc_count++; + break; ++#elif defined (TARGET_sh2eb) ++ case R_SH_DIR32: ++ goto good_32bit_resolved_reloc; ++ case R_SH_REL32: ++ relocation_needed = 0; ++ continue; + #elif defined (TARGET_h8300) + case R_H8_DIR32: + case R_H8_DIR32A16: +@@ -1328,7 +1334,7 @@ + #endif /* TARGET_sparc */ + + +-#ifdef TARGET_sh ++#ifdef TARGET_sh2eb + case R_SH_DIR32: + relocation_needed = 1; + sym_vma = elf2flt_bfd_section_vma(sym_section); +@@ -1339,7 +1345,7 @@ + sym_addr += sym_vma + q->addend; + sym_addr -= q->address; + break; +-#endif /* TARGET_sh */ ++#endif /* TARGET_sh2eb */ + + #ifdef TARGET_e1 + #define htoe1l(x) htonl(x) diff --git a/toolchain/elf2flt/patches/3051fec89bbd30de6f952dc3100712feff3ca076/0001-.rofixup-fix.patch b/toolchain/elf2flt/patches/3051fec89bbd30de6f952dc3100712feff3ca076/0001-.rofixup-fix.patch new file mode 100644 index 000000000..79186642e --- /dev/null +++ b/toolchain/elf2flt/patches/3051fec89bbd30de6f952dc3100712feff3ca076/0001-.rofixup-fix.patch @@ -0,0 +1,33 @@ +From 270b461e88b47781b3ef9bba2779074d0eb4996b Mon Sep 17 00:00:00 2001 +From: Waldemar Brodkorb <wbx@openadk.org> +Date: Fri, 25 Aug 2023 05:04:53 +0200 +Subject: [PATCH] .rofixup fix + +Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> +--- + elf2flt.ld.in | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/elf2flt.ld.in b/elf2flt.ld.in +index c7e01a6..c69531e 100644 +--- a/elf2flt.ld.in ++++ b/elf2flt.ld.in +@@ -31,6 +31,7 @@ W_RODAT *(.rodata) + W_RODAT *(.rodata1) + W_RODAT *(.rodata.*) + W_RODAT *(.gnu.linkonce.r*) ++W_RODAT *(.rofixup) + + /* This is special code area at the end of the normal + text section. It contains a small lookup table at +@@ -60,6 +61,7 @@ R_RODAT *(.rodata) + R_RODAT *(.rodata1) + R_RODAT *(.rodata.*) + R_RODAT *(.gnu.linkonce.r*) ++R_RODAT *(.rofixup) + *(.data) + *(.data1) + *(.data.*) +-- +2.30.2 + diff --git a/toolchain/elf2flt/patches/453398f917d167f8c308c8f997270c48ae8f8b12/0008-remove_BFD_VMA_FMT.patch b/toolchain/elf2flt/patches/453398f917d167f8c308c8f997270c48ae8f8b12/0008-remove_BFD_VMA_FMT.patch new file mode 100644 index 000000000..d20b993da --- /dev/null +++ b/toolchain/elf2flt/patches/453398f917d167f8c308c8f997270c48ae8f8b12/0008-remove_BFD_VMA_FMT.patch @@ -0,0 +1,125 @@ +diff -Nur elf2flt-453398f917d167f8c308c8f997270c48ae8f8b12.orig/elf2flt.c elf2flt-453398f917d167f8c308c8f997270c48ae8f8b12/elf2flt.c +--- elf2flt-453398f917d167f8c308c8f997270c48ae8f8b12.orig/elf2flt.c 2023-01-30 08:48:56.632981732 +0100 ++++ elf2flt-453398f917d167f8c308c8f997270c48ae8f8b12/elf2flt.c 2023-01-30 08:53:34.510426754 +0100 +@@ -222,7 +222,7 @@ + long i; + printf("SYMBOL TABLE:\n"); + for (i=0; i<number_of_symbols; i++) { +- printf(" NAME=%s VALUE=0x%"BFD_VMA_FMT"x\n", ++ printf(" NAME=%s VALUE=0x%x\n", + symbol_table[i]->name, symbol_table[i]->value); + } + printf("\n"); +@@ -458,7 +458,7 @@ + if (r == NULL) + continue; + if (verbose) +- printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%"BFD_VMA_FMT"x\n", ++ printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%x\n", + r->name, r, r->flags, elf2flt_bfd_section_vma(abs_bfd, r)); + if ((r->flags & SEC_RELOC) == 0) + continue; +@@ -903,8 +903,8 @@ + if (verbose) + fprintf(stderr, + "%s vma=0x%x, " +- "value=0x%"BFD_VMA_FMT"x, " +- "address=0x%"BFD_VMA_FMT"x " ++ "value=0x%x, " ++ "address=0x%x " + "sym_addr=0x%x rs=0x%x, opcode=0x%x\n", + "ABS32", + sym_vma, (*(q->sym_ptr_ptr))->value, +@@ -922,8 +922,8 @@ + if (verbose) + fprintf(stderr, + "%s vma=0x%x, " +- "value=0x%"BFD_VMA_FMT"x, " +- "address=0x%"BFD_VMA_FMT"x " ++ "value=0x%x, " ++ "address=0x%x " + "sym_addr=0x%x rs=0x%x, opcode=0x%x\n", + "PLT32", + sym_vma, (*(q->sym_ptr_ptr))->value, +@@ -945,7 +945,7 @@ + case R_V850_ZDA_16_16_OFFSET: + case R_V850_ZDA_16_16_SPLIT_OFFSET: + /* Can't support zero-relocations. */ +- printf ("ERROR: %s+0x%"BFD_VMA_FMT"x: zero relocations not supported\n", ++ printf ("ERROR: %s+0x%x: zero relocations not supported\n", + sym_name, q->addend); + continue; + #endif /* TARGET_v850 */ +@@ -1038,15 +1038,15 @@ + sprintf(&addstr[0], "+0x%ld", sym_addr - (*(q->sym_ptr_ptr))->value - + elf2flt_bfd_section_vma(abs_bfd, sym_section)); + if (verbose) +- printf(" RELOC[%d]: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf(" RELOC[%d]: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x)\n", ++ "fixup=0x%x (reloc=0x%x)\n", + flat_reloc_count, + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); + if (verbose) +- printf("reloc[%d] = 0x%"BFD_VMA_FMT"x\n", ++ printf("reloc[%d] = 0x%x\n", + flat_reloc_count, section_vma + q->address); + + continue; +@@ -1163,9 +1163,9 @@ + temp |= (exist_val & 0x3f); + *(unsigned long *)r_mem = htoniosl(temp); + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x) GPREL\n", ++ "fixup=0x%x (reloc=0x%x) GPREL\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); +@@ -1183,9 +1183,9 @@ + exist_val |= ((sym_addr & 0xFFFF) << 6); + *(unsigned long *)r_mem = htoniosl(exist_val); + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x) PCREL\n", ++ "fixup=0x%x (reloc=0x%x) PCREL\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); +@@ -1200,7 +1200,7 @@ + && (p[-1]->sym_ptr_ptr == p[0]->sym_ptr_ptr) + && (p[-1]->addend == p[0]->addend)) { + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d LO16\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size); +@@ -1610,9 +1610,9 @@ + } + + if (verbose) +- printf(" RELOC[%d]: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf(" RELOC[%d]: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x)\n", ++ "fixup=0x%x (reloc=0x%x)\n", + flat_reloc_count, + q->address, sym_name, addstr, + section_name, sym_reloc_size, +@@ -1630,7 +1630,7 @@ + (section_vma + q->address); + + if (verbose) +- printf("reloc[%d] = 0x%"BFD_VMA_FMT"x\n", ++ printf("reloc[%d] = 0x%x\n", + flat_reloc_count, section_vma + q->address); + #else + switch ((*p)->howto->type) { diff --git a/toolchain/elf2flt/patches/v2021.08/0001-elf2flt-handle-binutils-2.34.patch b/toolchain/elf2flt/patches/v2021.08/0001-elf2flt-handle-binutils-2.34.patch new file mode 100644 index 000000000..4aa473c24 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0001-elf2flt-handle-binutils-2.34.patch @@ -0,0 +1,377 @@ +From d78acba6510527aaa01a41eaf4c931f7a57e5f44 Mon Sep 17 00:00:00 2001 +From: Romain Naour <romain.naour@smile.fr> +Date: Wed, 5 Feb 2020 10:31:32 +0100 +Subject: [PATCH] elf2flt: handle binutils >= 2.34 + +The latest Binutils release (2.34) is not compatible with elf2flt due +to a change in bfd_section_* macros [1]. The issue has been reported +to the Binutils mailing list but Alan Modra recommend to bundle +libbfd library sources into each projects using it [2]. That's +because the API is not stable over the time without any backward +compatibility guaranties. + +On the other hand, the elf2flt tools needs to support modified +version of binutils for specific arch/target [3]. + +Add two tests in the configure script to detect this API change +in order to support binutils < 2.34 and binutils >= 2.34. + +Upstream status: [4] + +[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=fd3619828e94a24a92cddec42cbc0ab33352eeb4 +[2] https://sourceware.org/ml/binutils/2020-02/msg00044.html +[3] https://github.com/uclinux-dev/elf2flt/issues/14 +[4] https://github.com/uclinux-dev/elf2flt/pull/15 + +Signed-off-by: Romain Naour <romain.naour@smile.fr> +--- + configure.ac | 16 +++++++++++ + elf2flt.c | 81 +++++++++++++++++++++++++++++----------------------- + 2 files changed, 61 insertions(+), 36 deletions(-) + +diff --git a/configure.ac b/configure.ac +index b7db2cb..fdc0876 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -229,6 +229,22 @@ AC_CHECK_FUNCS([ \ + strsignal \ + ]) + ++dnl Various bfd section macros and functions like bfd_section_size() have been ++dnl modified starting with binutils >= 2.34. ++dnl Check if the prototypes take a bfd argument. ++if test "$binutils_build_dir" != "NONE"; then ++ CFLAGS="-I$binutils_include_dir -I$bfd_include_dir $CFLAGS" ++fi ++ ++AC_TRY_COMPILE([#include <bfd.h>], ++ [const asection *sec; bfd_section_size(sec);], ++ bfd_section_api_takes_bfd=no, ++ bfd_section_api_takes_bfd=yes) ++if test "$bfd_section_api_takes_bfd" = "yes" ; then ++ AC_DEFINE(HAVE_BFD_SECTION_API_TAKES_BFD, 1, ++ [define to 1 for binutils < 2.34]) ++fi ++ + if test "$GCC" = yes ; then + CFLAGS="-Wall $CFLAGS" + if test "$werror" = 1 ; then +diff --git a/elf2flt.c b/elf2flt.c +index 7ac0617..ea6b5a1 100644 +--- a/elf2flt.c ++++ b/elf2flt.c +@@ -149,6 +149,17 @@ const char *elf2flt_progname; + #define O_BINARY 0 + #endif + ++/* ++ * The bfd parameter isn't actually used by any of the bfd_section funcs and ++ * have been removed since binutils 2.34. ++ */ ++#ifdef HAVE_BFD_SECTION_API_TAKES_BFD ++#define elf2flt_bfd_section_size(s) bfd_section_size(NULL, s) ++#define elf2flt_bfd_section_vma(s) bfd_section_vma(NULL, s) ++#else ++#define elf2flt_bfd_section_size(s) bfd_section_size(s) ++#define elf2flt_bfd_section_vma(s) bfd_section_vma(s) ++#endif + + /* Extra output when running. */ + static int verbose = 0; +@@ -323,10 +334,8 @@ compare_relocs (const void *pa, const void *pb) + else if (!rb->sym_ptr_ptr || !*rb->sym_ptr_ptr) + return 1; + +- a_vma = bfd_section_vma(compare_relocs_bfd, +- (*(ra->sym_ptr_ptr))->section); +- b_vma = bfd_section_vma(compare_relocs_bfd, +- (*(rb->sym_ptr_ptr))->section); ++ a_vma = elf2flt_bfd_section_vma((*(ra->sym_ptr_ptr))->section); ++ b_vma = elf2flt_bfd_section_vma((*(rb->sym_ptr_ptr))->section); + va = (*(ra->sym_ptr_ptr))->value + a_vma + ra->addend; + vb = (*(rb->sym_ptr_ptr))->value + b_vma + rb->addend; + return va - vb; +@@ -403,7 +412,7 @@ output_relocs ( + } + + for (a = abs_bfd->sections; (a != (asection *) NULL); a = a->next) { +- section_vma = bfd_section_vma(abs_bfd, a); ++ section_vma = elf2flt_bfd_section_vma(a); + + if (verbose) + printf("SECTION: %s [%p]: flags=0x%x vma=0x%"PRIx32"\n", +@@ -443,7 +452,7 @@ output_relocs ( + continue; + if (verbose) + printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%"BFD_VMA_FMT"x\n", +- r->name, r, r->flags, bfd_section_vma(abs_bfd, r)); ++ r->name, r, r->flags, elf2flt_bfd_section_vma(r)); + if ((r->flags & SEC_RELOC) == 0) + continue; + relsize = bfd_get_reloc_upper_bound(rel_bfd, r); +@@ -695,7 +704,7 @@ output_relocs ( + case R_BFIN_RIMM16: + case R_BFIN_LUIMM16: + case R_BFIN_HUIMM16: +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + + if (weak_und_symbol(sym_section->name, (*(q->sym_ptr_ptr)))) +@@ -728,7 +737,7 @@ output_relocs ( + break; + + case R_BFIN_BYTE4_DATA: +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + + if (weak_und_symbol (sym_section->name, (*(q->sym_ptr_ptr)))) +@@ -886,7 +895,7 @@ output_relocs ( + #if defined(TARGET_m68k) + case R_68K_32: + relocation_needed = 1; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_68K_PC16: +@@ -911,7 +920,7 @@ output_relocs ( + q->address, sym_addr, + (*p)->howto->rightshift, + *(uint32_t *)r_mem); +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_ARM_GOT32: +@@ -939,7 +948,7 @@ output_relocs ( + #ifdef TARGET_v850 + case R_V850_ABS32: + relocation_needed = 1; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_V850_ZDA_16_16_OFFSET: +@@ -961,7 +970,7 @@ output_relocs ( + sym_addr = (*(q->sym_ptr_ptr))->value; + q->address -= 1; + r_mem -= 1; /* tracks q->address */ +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + sym_addr |= (*(unsigned char *)r_mem<<24); + break; +@@ -974,7 +983,7 @@ output_relocs ( + /* Absolute symbol done not relocation */ + relocation_needed = !bfd_is_abs_section(sym_section); + sym_addr = (*(q->sym_ptr_ptr))->value; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_H8_DIR32: +@@ -987,7 +996,7 @@ output_relocs ( + } + relocation_needed = 1; + sym_addr = (*(q->sym_ptr_ptr))->value; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_H8_PCREL16: +@@ -1013,7 +1022,7 @@ output_relocs ( + #ifdef TARGET_microblaze + case R_MICROBLAZE_64: + /* work out the relocation */ +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + /* Write relocated pointer back */ + r_mem[2] = (sym_addr >> 24) & 0xff; +@@ -1027,7 +1036,7 @@ output_relocs ( + pflags = 0x80000000; + break; + case R_MICROBLAZE_32: +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + relocation_needed = 1; + break; +@@ -1059,7 +1068,7 @@ output_relocs ( + case R_NIOS2_BFD_RELOC_32: + relocation_needed = 1; + pflags = (FLAT_NIOS2_R_32 << 28); +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + /* modify target, in target order */ + *(unsigned long *)r_mem = htoniosl(sym_addr); +@@ -1069,7 +1078,7 @@ output_relocs ( + unsigned long exist_val; + relocation_needed = 1; + pflags = (FLAT_NIOS2_R_CALL26 << 28); +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + + /* modify target, in target order */ +@@ -1100,7 +1109,7 @@ output_relocs ( + ? FLAT_NIOS2_R_HIADJ_LO : FLAT_NIOS2_R_HI_LO; + pflags <<= 28; + +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(abs_bfd, sym_section); + sym_addr += sym_vma + q->addend; + + /* modify high 16 bits, in target order */ +@@ -1133,7 +1142,7 @@ output_relocs ( + goto NIOS2_RELOC_ERR; + } + /* _gp holds a absolute value, otherwise the ld cannot generate correct code */ +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + //printf("sym=%x, %d, _gp=%x, %d\n", sym_addr+sym_vma, sym_addr+sym_vma, gp, gp); + sym_addr += sym_vma + q->addend; + sym_addr -= gp; +@@ -1214,7 +1223,7 @@ NIOS2_RELOC_ERR: + case R_SPARC_32: + case R_SPARC_UA32: + relocation_needed = 1; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_SPARC_PC22: +@@ -1233,7 +1242,7 @@ NIOS2_RELOC_ERR: + case R_SPARC_HI22: + relocation_needed = 1; + pflags = 0x80000000; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + sym_addr |= ( + htonl(*(uint32_t *)r_mem) +@@ -1243,7 +1252,7 @@ NIOS2_RELOC_ERR: + case R_SPARC_LO10: + relocation_needed = 1; + pflags = 0x40000000; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + sym_addr &= 0x000003ff; + sym_addr |= ( +@@ -1257,7 +1266,7 @@ NIOS2_RELOC_ERR: + #ifdef TARGET_sh + case R_SH_DIR32: + relocation_needed = 1; +- sym_vma = bfd_section_vma(abs_bfd, sym_section); ++ sym_vma = elf2flt_bfd_section_vma(sym_section); + sym_addr += sym_vma + q->addend; + break; + case R_SH_REL32: +@@ -1289,7 +1298,7 @@ NIOS2_RELOC_ERR: + case R_E1_CONST31: + relocation_needed = 1; + DBG_E1("Handling Reloc <CONST31>\n"); +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%x], q->address : [0x%x]\n", + sec_vma, sym_addr, q->address); + sym_addr = sec_vma + sym_addr; +@@ -1304,7 +1313,7 @@ NIOS2_RELOC_ERR: + relocation_needed = 0; + DBG_E1("Handling Reloc <CONST31_PCREL>\n"); + DBG_E1("DONT RELOCATE AT LOADING\n"); +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%x], q->address : [0x%x]\n", + sec_vma, sym_addr, q->address); + sym_addr = sec_vma + sym_addr; +@@ -1331,7 +1340,7 @@ NIOS2_RELOC_ERR: + relocation_needed = 0; + DBG_E1("Handling Reloc <DIS29W_PCREL>\n"); + DBG_E1("DONT RELOCATE AT LOADING\n"); +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%x], q->address : [0x%x]\n", + sec_vma, sym_addr, q->address); + sym_addr = sec_vma + sym_addr; +@@ -1364,7 +1373,7 @@ NIOS2_RELOC_ERR: + DBG_E1("Handling Reloc <DIS29B>\n"); + DIS29_RELOCATION: + relocation_needed = 1; +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%08x]\n", + sec_vma, sym_addr); + sym_addr = sec_vma + sym_addr; +@@ -1381,7 +1390,7 @@ DIS29_RELOCATION: + relocation_needed = 0; + DBG_E1("Handling Reloc <IMM32_PCREL>\n"); + DBG_E1("DONT RELOCATE AT LOADING\n"); +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%x]\n", + sec_vma, sym_addr); + sym_addr = sec_vma + sym_addr; +@@ -1407,7 +1416,7 @@ DIS29_RELOCATION: + case R_E1_IMM32: + relocation_needed = 1; + DBG_E1("Handling Reloc <IMM32>\n"); +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%x]\n", + sec_vma, sym_addr); + sym_addr = sec_vma + sym_addr; +@@ -1423,7 +1432,7 @@ DIS29_RELOCATION: + case R_E1_WORD: + relocation_needed = 1; + DBG_E1("Handling Reloc <WORD>\n"); +- sec_vma = bfd_section_vma(abs_bfd, sym_section); ++ sec_vma = elf2flt_bfd_section_vma(sym_section); + DBG_E1("sec_vma : [0x%x], sym_addr : [0x%x]\n", + sec_vma, sym_addr); + sym_addr = sec_vma + sym_addr; +@@ -1450,7 +1459,7 @@ DIS29_RELOCATION: + } + + sprintf(&addstr[0], "+0x%lx", sym_addr - (*(q->sym_ptr_ptr))->value - +- bfd_section_vma(abs_bfd, sym_section)); ++ elf2flt_bfd_section_vma(sym_section)); + + + /* +@@ -1890,8 +1899,8 @@ int main(int argc, char *argv[]) + } else + continue; + +- sec_size = bfd_section_size(abs_bfd, s); +- sec_vma = bfd_section_vma(abs_bfd, s); ++ sec_size = elf2flt_bfd_section_size(s); ++ sec_vma = elf2flt_bfd_section_vma(s); + + if (sec_vma < *vma) { + if (*len > 0) +@@ -1920,7 +1929,7 @@ int main(int argc, char *argv[]) + (SEC_DATA | SEC_READONLY | SEC_RELOC))) + if (!bfd_get_section_contents(abs_bfd, s, + text + (s->vma - text_vma), 0, +- bfd_section_size(abs_bfd, s))) ++ elf2flt_bfd_section_size(s))) + { + fatal("read error section %s", s->name); + } +@@ -1950,7 +1959,7 @@ int main(int argc, char *argv[]) + (SEC_READONLY | SEC_RELOC))) + if (!bfd_get_section_contents(abs_bfd, s, + data + (s->vma - data_vma), 0, +- bfd_section_size(abs_bfd, s))) ++ elf2flt_bfd_section_size(s))) + { + fatal("read error section %s", s->name); + } +-- +2.35.1 + diff --git a/toolchain/elf2flt/patches/v2021.08/0002-elf2flt.ld-reinstate-32-byte-alignment-for-.data-sec.patch b/toolchain/elf2flt/patches/v2021.08/0002-elf2flt.ld-reinstate-32-byte-alignment-for-.data-sec.patch new file mode 100644 index 000000000..4df3ea592 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0002-elf2flt.ld-reinstate-32-byte-alignment-for-.data-sec.patch @@ -0,0 +1,81 @@ +From 85ba5664eb368eb1cbd2c30b7cd574acd75edd4c Mon Sep 17 00:00:00 2001 +From: Niklas Cassel <niklas.cassel@wdc.com> +Date: Mon, 4 Apr 2022 15:30:24 +0200 +Subject: [PATCH] elf2flt.ld: reinstate 32 byte alignment for .data section + +Commit 8a3e74446fe7 ("allow to build arm flat binaries") moved the +following commands: + . = ALIGN(0x20) ; + @SYMBOL_PREFIX@_etext = . ; +from the .text section to the top level in the SECTIONS node. + +The .text output section is being directed to a memory region using the +"> flatmem :text" output section attribute. Commands in the top level in +the SECTIONS node are not. + +This means that the ALIGN() command is no longer being appended to the +flatmem memory region, it will simply update the Location Counter. + +The heuristic for placing an output section is described here: +https://sourceware.org/binutils/docs-2.38/ld.html#Output-Section-Address + +"If an output memory region is set for the section then it is added to this +region and its address will be the next free address in that region." + +Since the .data section is being directed to the same memory region as the +.text section, this means that the Location Counter is not used when +assigning an address to the .data output section, it will simply use the +next free address. + +No longer directing these commands to the flatmem memory region means that +the .data output section is no longer aligned to a 32 byte boundary. + +Before commit 8a3e74446fe7 ("allow to build arm flat binaries"): +$ readelf -S busybox_unstripped.gdb | grep data + [ 3] .data PROGBITS 0000000000035ac0 00036ac0 +$ readelf -s busybox_unstripped.gdb | grep _etext + 19286: 0000000000035ac0 0 NOTYPE GLOBAL DEFAULT 1 _etext + +After commit 8a3e74446fe7 ("allow to build arm flat binaries"): +$ readelf -S busybox_unstripped.gdb | grep data + [ 3] .data PROGBITS 0000000000035ab0 00036ab0 +$ readelf -s busybox_unstripped.gdb | grep _etext + 19287: 0000000000035ac0 0 NOTYPE GLOBAL DEFAULT 3 _etext + +The .data output section has to be aligned to a 32 byte boundary, see the +FLAT_DATA_ALIGN 0x20 macro and its usage in fs/binfmt_flat.c: +https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/fs/binfmt_flat.c?h=v5.17#n59 + +Readd an explicit ALIGN attribute on the .data section itself, since the +linker will obey this attribute regardless if being directed to a memory +region or not. Also remove the ALIGN() command before the .data section, +since this misleads the reader to think that the Location Counter is used +when assigning an address to the .data section, when it actually is not. + +Fixes: 8a3e74446fe7 ("allow to build arm flat binaries") +Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> +--- + elf2flt.ld.in | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/elf2flt.ld.in b/elf2flt.ld.in +index 0df999d..e5aea14 100644 +--- a/elf2flt.ld.in ++++ b/elf2flt.ld.in +@@ -94,12 +94,9 @@ W_RODAT: *(.gnu.linkonce.r*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flatmem + @SYMBOL_PREFIX@__exidx_end = .; +- +- . = ALIGN(0x20) ; + @SYMBOL_PREFIX@_etext = . ; + +- .data : { +- . = ALIGN(0x4) ; ++ .data ALIGN(0x20): { + @SYMBOL_PREFIX@_sdata = . ; + @SYMBOL_PREFIX@__data_start = . ; + @SYMBOL_PREFIX@data_start = . ; +-- +2.35.1 + diff --git a/toolchain/elf2flt/patches/v2021.08/0003-elf2flt-add-riscv-64-bits-support.patch b/toolchain/elf2flt/patches/v2021.08/0003-elf2flt-add-riscv-64-bits-support.patch new file mode 100644 index 000000000..15c191c83 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0003-elf2flt-add-riscv-64-bits-support.patch @@ -0,0 +1,103 @@ +From 3f1f323feb5cf25d8c80861991d0360784f4d2e6 Mon Sep 17 00:00:00 2001 +From: Damien Le Moal <damien.lemoal@wdc.com> +Date: Wed, 9 Sep 2020 17:31:33 +0900 +Subject: [PATCH] elf2flt: add riscv 64-bits support + +Add support for riscv 64bits ISA by defining the relocation types +R_RISCV_32_PCREL, R_RISCV_ADD32, R_RISCV_SUB32, R_RISCV_32 and +R_RISCV_64. riscv64 support also needs the __global_pointer$ symbol to +be defined right after the relocation tables in the data section. To +define this symbol, the "RISCV_GP" line prefix is added. The "RISCV_GP" +string is removed if the target CPU type is riscv64 and the definition +line is dropped for other CPU types. + +With these changes, buildroot and busybox build and run on riscv NOMMU +systems with Linux kernel including patch 6045ab5fea4c +("binfmt_flat: do not stop relocating GOT entries prematurely on riscv") +fixing the binfmt_flat loader. Tested on QEMU and Canaan Kendryte K210 +boards. + +This patch is based on earlier work by Christoph Hellwig <hch@lst.de>. + +Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> +--- + elf2flt.c | 16 ++++++++++++++++ + elf2flt.ld.in | 1 + + ld-elf2flt.c | 8 ++++++++ + 3 files changed, 25 insertions(+) + +diff --git a/elf2flt.c b/elf2flt.c +index da25e93..a03ea3a 100644 +--- a/elf2flt.c ++++ b/elf2flt.c +@@ -81,6 +81,8 @@ const char *elf2flt_progname; + #include <elf/v850.h> + #elif defined(TARGET_xtensa) + #include <elf/xtensa.h> ++#elif defined(TARGET_riscv64) ++#include <elf/riscv.h> + #endif + + #if defined(__MINGW32__) +@@ -123,6 +125,8 @@ const char *elf2flt_progname; + #define ARCH "nios2" + #elif defined(TARGET_xtensa) + #define ARCH "xtensa" ++#elif defined(TARGET_riscv64) ++#define ARCH "riscv64" + #else + #error "Don't know how to support your CPU architecture??" + #endif +@@ -812,6 +816,18 @@ output_relocs ( + goto good_32bit_resolved_reloc; + default: + goto bad_resolved_reloc; ++#elif defined(TARGET_riscv64) ++ case R_RISCV_32_PCREL: ++ case R_RISCV_ADD32: ++ case R_RISCV_ADD64: ++ case R_RISCV_SUB32: ++ case R_RISCV_SUB64: ++ continue; ++ case R_RISCV_32: ++ case R_RISCV_64: ++ goto good_32bit_resolved_reloc; ++ default: ++ goto bad_resolved_reloc; + #else + default: + /* The default is to assume that the +diff --git a/elf2flt.ld.in b/elf2flt.ld.in +index e5aea14..950849e 100644 +--- a/elf2flt.ld.in ++++ b/elf2flt.ld.in +@@ -106,6 +106,7 @@ W_RODAT: *(.gnu.linkonce.r*) + . = ALIGN(0x20) ; + LONG(-1) + . = ALIGN(0x20) ; ++RISCV_GP: __global_pointer$ = . + 0x800 ; + R_RODAT: *(.rodata) + R_RODAT: *(.rodata1) + R_RODAT: *(.rodata.*) +diff --git a/ld-elf2flt.c b/ld-elf2flt.c +index 7cb02d5..75ee1bb 100644 +--- a/ld-elf2flt.c ++++ b/ld-elf2flt.c +@@ -324,6 +324,14 @@ static int do_final_link(void) + append_option(&other_options, concat(got_offset, "=", buf, NULL)); + } + ++ /* riscv adds a global pointer symbol to the linker file with the ++ "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and ++ the entire line for other architectures. */ ++ if (streq(TARGET_CPU, "riscv64")) ++ append_sed(&sed, "^RISCV_GP:", ""); ++ else ++ append_sed(&sed, "^RISCV_GP:", NULL); ++ + /* Locate the default linker script, if we don't have one provided. */ + if (!linker_script) + linker_script = concat(ldscriptpath, "/elf2flt.ld", NULL); +-- +2.36.1 + diff --git a/toolchain/elf2flt/patches/v2021.08/0004-elf2flt-create-a-common-helper-function.patch b/toolchain/elf2flt/patches/v2021.08/0004-elf2flt-create-a-common-helper-function.patch new file mode 100644 index 000000000..6fee99d45 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0004-elf2flt-create-a-common-helper-function.patch @@ -0,0 +1,76 @@ +From 37e1e0ace8ccebf54ec2f5522bfc1f9db86946ad Mon Sep 17 00:00:00 2001 +From: Niklas Cassel <niklas.cassel@wdc.com> +Date: Tue, 9 Aug 2022 12:13:50 +0200 +Subject: [PATCH] elf2flt: create a common helper function + +In order to make the code more maintainable, +move duplicated code to a common helper function. + +No functional change intended. + +Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> +--- + elf2flt.c | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/elf2flt.c b/elf2flt.c +index 669591e..9c32f9a 100644 +--- a/elf2flt.c ++++ b/elf2flt.c +@@ -337,6 +337,13 @@ compare_relocs (const void *pa, const void *pb) + } + #endif + ++static bool ++ro_reloc_data_section_should_be_in_text(asection *s) ++{ ++ return (s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == ++ (SEC_DATA | SEC_READONLY | SEC_RELOC); ++} ++ + static uint32_t * + output_relocs ( + bfd *abs_bfd, +@@ -428,8 +435,7 @@ output_relocs ( + */ + if ((!pic_with_got || ALWAYS_RELOC_TEXT) && + ((a->flags & SEC_CODE) || +- ((a->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == +- (SEC_DATA | SEC_READONLY | SEC_RELOC)))) ++ ro_reloc_data_section_should_be_in_text(a))) + sectionp = text + (a->vma - text_vma); + else if (a->flags & SEC_DATA) + sectionp = data + (a->vma - data_vma); +@@ -1893,8 +1899,7 @@ int main(int argc, char *argv[]) + bfd_vma sec_vma; + + if ((s->flags & SEC_CODE) || +- ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == +- (SEC_DATA | SEC_READONLY | SEC_RELOC))) { ++ ro_reloc_data_section_should_be_in_text(s)) { + vma = &text_vma; + len = &text_len; + } else if (s->flags & SEC_DATA) { +@@ -1932,8 +1937,7 @@ int main(int argc, char *argv[]) + * data sections.*/ + for (s = abs_bfd->sections; s != NULL; s = s->next) + if ((s->flags & SEC_CODE) || +- ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == +- (SEC_DATA | SEC_READONLY | SEC_RELOC))) ++ ro_reloc_data_section_should_be_in_text(s)) + if (!bfd_get_section_contents(abs_bfd, s, + text + (s->vma - text_vma), 0, + bfd_section_size(abs_bfd, s))) +@@ -1962,8 +1966,7 @@ int main(int argc, char *argv[]) + * data sections already included in the text output section.*/ + for (s = abs_bfd->sections; s != NULL; s = s->next) + if ((s->flags & SEC_DATA) && +- ((s->flags & (SEC_READONLY | SEC_RELOC)) != +- (SEC_READONLY | SEC_RELOC))) ++ !ro_reloc_data_section_should_be_in_text(s)) + if (!bfd_get_section_contents(abs_bfd, s, + data + (s->vma - data_vma), 0, + bfd_section_size(abs_bfd, s))) +-- +2.37.1 + diff --git a/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch b/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch new file mode 100644 index 000000000..616bbc891 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0005-elf2flt-fix-fatal-error-regression-on-m68k-xtensa-ri.patch @@ -0,0 +1,74 @@ +From a8c9f650b82109abf7aa730f298ea5182ed62613 Mon Sep 17 00:00:00 2001 +From: Niklas Cassel <niklas.cassel@wdc.com> +Date: Tue, 9 Aug 2022 21:06:05 +0200 +Subject: [PATCH] elf2flt: fix fatal error regression on m68k, xtensa, riscv64 + +Commit ba379d08bb78 ("elf2flt: fix for segfault on some ARM ELFs") +changed the condition of which input sections that should be included +in the .text output section from: +((a->flags & (SEC_DATA | SEC_READONLY)) == (SEC_DATA | SEC_READONLY)) +to: +((a->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == +(SEC_DATA | SEC_READONLY | SEC_RELOC)) + +On ARM, the .eh_frame input section does not have the SEC_RELOC flag set, +so on ARM, this change caused .eh_frame to move from .text to .data. + +However, on e.g. m68k, xtensa and riscv64, the .eh_frame input section +does have the SEC_RELOC flag set, which means that the change in +commit ba379d08bb78 ("elf2flt: fix for segfault on some ARM ELFs") +caused .eh_frame to move in an opposite way, i.e. from .data to .text. + +This resulted in a fatal error on m68k, xtensa and riscv64: +ERROR: text=0x3bab8 overlaps data=0x33f60 ? + +This is because elf2flt cannot append to .text after .data has been +appended to. + +Note that the binutils maintainer says that the correct thing is +to put read-only relocation data sections in .text: +https://sourceware.org/legacy-ml/binutils/2019-10/msg00132.html + +So the proper fix is probably to rewrite elf2flt so that it can append +to .text after .data has been appended to (which will require elf2flt +to move/relocate everything that has already been appended to .data, +since the virtual addresses are contiguous). + +However, for now, add an exception for input sections which have all +three flags SEC_DATA, SEC_READONLY, and SEC_RELOC set, and which have a +name equal to a problematic input section (.eh_frame, .gcc_except_table). +That way, we get the same behavior as older elf2flt releases for m68k, +xtensa and riscv64, where we put read-only relocation data in .data, +which was working perfectly fine. + +This exception will not change any behavior on ARM, as the .eh_frame +input section does not have flag SEC_RELOC set. + +Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> +--- + elf2flt.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/elf2flt.c b/elf2flt.c +index e0d7891..39d035f 100644 +--- a/elf2flt.c ++++ b/elf2flt.c +@@ -341,8 +341,13 @@ compare_relocs (const void *pa, const void *pb) + static bool + ro_reloc_data_section_should_be_in_text(asection *s) + { +- return (s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == +- (SEC_DATA | SEC_READONLY | SEC_RELOC); ++ if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) == ++ (SEC_DATA | SEC_READONLY | SEC_RELOC)) { ++ if (!strcmp(".eh_frame", s->name) || !strcmp(".gcc_except_table", s->name)) ++ return false; ++ return true; ++ } ++ return false; + } + + static uint32_t * +-- +2.39.0 + diff --git a/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch new file mode 100644 index 000000000..fc8784a1b --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch @@ -0,0 +1,25 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-09 11:08:28.637676113 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-01-09 11:09:04.502804007 +0100 +@@ -835,7 +835,20 @@ + continue; + case R_XTENSA_32: + case R_XTENSA_PLT: +- goto good_32bit_resolved_reloc; ++ if (bfd_big_endian (abs_bfd)) ++ sym_addr = ++ (r_mem[0] << 24) ++ + (r_mem[1] << 16) ++ + (r_mem[2] << 8) ++ + r_mem[3]; ++ else ++ sym_addr = ++ r_mem[0] ++ + (r_mem[1] << 8) ++ + (r_mem[2] << 16) ++ + (r_mem[3] << 24); ++ relocation_needed = 1; ++ break; + default: + goto bad_resolved_reloc; + #elif defined(TARGET_riscv64) diff --git a/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch new file mode 100644 index 000000000..b3c4677be --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch @@ -0,0 +1,56 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-02-26 11:31:48.758810872 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-02-26 11:32:05.714465277 +0100 +@@ -81,7 +81,7 @@ + #include <elf/v850.h> + #elif defined(TARGET_xtensa) + #include <elf/xtensa.h> +-#elif defined(TARGET_riscv64) ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32) + #include <elf/riscv.h> + #endif + +@@ -127,6 +127,8 @@ + #define ARCH "xtensa" + #elif defined(TARGET_riscv64) + #define ARCH "riscv64" ++#elif defined(TARGET_riscv32) ++#define ARCH "riscv32" + #else + #error "Don't know how to support your CPU architecture??" + #endif +@@ -849,12 +851,21 @@ + break; + default: + goto bad_resolved_reloc; +-#elif defined(TARGET_riscv64) ++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32) + case R_RISCV_32_PCREL: ++ case R_RISCV_ADD8: ++ case R_RISCV_ADD16: + case R_RISCV_ADD32: + case R_RISCV_ADD64: ++ case R_RISCV_SUB6: ++ case R_RISCV_SUB8: ++ case R_RISCV_SUB16: + case R_RISCV_SUB32: + case R_RISCV_SUB64: ++ case R_RISCV_SET6: ++ case R_RISCV_SET8: ++ case R_RISCV_SET16: ++ case R_RISCV_SET32: + continue; + case R_RISCV_32: + case R_RISCV_64: +diff -Nur elf2flt-v2021.08.orig/ld-elf2flt.c elf2flt-v2021.08/ld-elf2flt.c +--- elf2flt-v2021.08.orig/ld-elf2flt.c 2023-02-26 11:31:21.047376888 +0100 ++++ elf2flt-v2021.08/ld-elf2flt.c 2023-02-26 11:32:05.714465277 +0100 +@@ -327,7 +327,7 @@ + /* riscv adds a global pointer symbol to the linker file with the + "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and + the entire line for other architectures. */ +- if (streq(TARGET_CPU, "riscv64")) ++ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32")) + append_sed(&sed, "^RISCV_GP:", ""); + else + append_sed(&sed, "^RISCV_GP:", NULL); diff --git a/toolchain/elf2flt/patches/v2021.08/0008-remove_BFD_VMA_FMT.patch b/toolchain/elf2flt/patches/v2021.08/0008-remove_BFD_VMA_FMT.patch new file mode 100644 index 000000000..6367f1383 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0008-remove_BFD_VMA_FMT.patch @@ -0,0 +1,97 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-29 16:47:24.791851890 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-01-29 16:49:46.628476326 +0100 +@@ -222,7 +222,7 @@ + long i; + printf("SYMBOL TABLE:\n"); + for (i=0; i<number_of_symbols; i++) { +- printf(" NAME=%s VALUE=0x%"BFD_VMA_FMT"x\n", ++ printf(" NAME=%s VALUE=0x%x\n", + symbol_table[i]->name, symbol_table[i]->value); + } + printf("\n"); +@@ -471,7 +471,7 @@ + if (r == NULL) + continue; + if (verbose) +- printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%"BFD_VMA_FMT"x\n", ++ printf(" RELOCS: %s [%p]: flags=0x%x vma=0x%x\n", + r->name, r, r->flags, elf2flt_bfd_section_vma(r)); + if ((r->flags & SEC_RELOC) == 0) + continue; +@@ -966,8 +966,8 @@ + if (verbose) + fprintf(stderr, + "%s vma=0x%x, " +- "value=0x%"BFD_VMA_FMT"x, " +- "address=0x%"BFD_VMA_FMT"x " ++ "value=0x%x, " ++ "address=0x%x " + "sym_addr=0x%x rs=0x%x, opcode=0x%x\n", + "ABS32", + sym_vma, (*(q->sym_ptr_ptr))->value, +@@ -985,8 +985,8 @@ + if (verbose) + fprintf(stderr, + "%s vma=0x%x, " +- "value=0x%"BFD_VMA_FMT"x, " +- "address=0x%"BFD_VMA_FMT"x " ++ "value=0x%x, " ++ "address=0x%x " + "sym_addr=0x%x rs=0x%x, opcode=0x%x\n", + "PLT32", + sym_vma, (*(q->sym_ptr_ptr))->value, +@@ -1008,7 +1008,7 @@ + case R_V850_ZDA_16_16_OFFSET: + case R_V850_ZDA_16_16_SPLIT_OFFSET: + /* Can't support zero-relocations. */ +- printf ("ERROR: %s+0x%"BFD_VMA_FMT"x: zero relocations not supported\n", ++ printf ("ERROR: %s+0x%x: zero relocations not supported\n", + sym_name, q->addend); + continue; + #endif /* TARGET_v850 */ +@@ -1208,9 +1208,9 @@ + temp |= (exist_val & 0x3f); + *(unsigned long *)r_mem = htoniosl(temp); + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x) GPREL\n", ++ "fixup=0x%x (reloc=0x%x) GPREL\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); +@@ -1228,9 +1228,9 @@ + exist_val |= ((sym_addr & 0xFFFF) << 6); + *(unsigned long *)r_mem = htoniosl(exist_val); + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x) PCREL\n", ++ "fixup=0x%x (reloc=0x%x) PCREL\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size, + sym_addr, section_vma + q->address); +@@ -1245,7 +1245,7 @@ + && (p[-1]->sym_ptr_ptr == p[0]->sym_ptr_ptr) + && (p[-1]->addend == p[0]->addend)) { + if (verbose) +- printf("omit: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf("omit: offset=0x%x symbol=%s%s " + "section=%s size=%d LO16\n", + q->address, sym_name, addstr, + section_name, sym_reloc_size); +@@ -1660,9 +1660,9 @@ + */ + if (relocation_needed) { + if (verbose) +- printf(" RELOC[%d]: offset=0x%"BFD_VMA_FMT"x symbol=%s%s " ++ printf(" RELOC[%d]: offset=0x%x symbol=%s%s " + "section=%s size=%d " +- "fixup=0x%x (reloc=0x%"BFD_VMA_FMT"x)\n", ++ "fixup=0x%x (reloc=0x%x)\n", + flat_reloc_count, + q->address, sym_name, addstr, + section_name, sym_reloc_size, diff --git a/toolchain/elf2flt/patches/v2021.08/0009-riscv.patch b/toolchain/elf2flt/patches/v2021.08/0009-riscv.patch new file mode 100644 index 000000000..c1072cb45 --- /dev/null +++ b/toolchain/elf2flt/patches/v2021.08/0009-riscv.patch @@ -0,0 +1,11 @@ +diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c +--- elf2flt-v2021.08.orig/elf2flt.c 2023-02-26 11:32:05.714465277 +0100 ++++ elf2flt-v2021.08/elf2flt.c 2023-02-26 15:04:52.726514896 +0100 +@@ -852,6 +852,7 @@ + default: + goto bad_resolved_reloc; + #elif defined(TARGET_riscv64) || defined(TARGET_riscv32) ++ case R_RISCV_NONE: + case R_RISCV_32_PCREL: + case R_RISCV_ADD8: + case R_RISCV_ADD16: diff --git a/toolchain/elf2flt/patches/v2024.02/0001-sh2.patch b/toolchain/elf2flt/patches/v2024.02/0001-sh2.patch new file mode 100644 index 000000000..b14a78e23 --- /dev/null +++ b/toolchain/elf2flt/patches/v2024.02/0001-sh2.patch @@ -0,0 +1,43 @@ +diff -Nur elf2flt-v2023.09.orig/elf2flt.c elf2flt-v2023.09/elf2flt.c +--- elf2flt-v2023.09.orig/elf2flt.c 2023-12-22 10:44:11.000000000 +0100 ++++ elf2flt-v2023.09/elf2flt.c 2023-12-23 02:26:06.323239781 +0100 +@@ -73,7 +73,7 @@ + #define FLAT_NIOS2_R_HIADJ_LO 2 + #define FLAT_NIOS2_R_CALL26 4 + #include <elf/nios2.h> +-#elif defined(TARGET_sh) ++#elif defined(TARGET_sh2) || defined(TARGET_sh2eb) + #include <elf/sh.h> + #elif defined(TARGET_sparc) + #include <elf/sparc.h> +@@ -109,8 +109,10 @@ + #define ARCH "sparc" + #elif defined(TARGET_v850) + #define ARCH "v850" +-#elif defined(TARGET_sh) +-#define ARCH "sh" ++#elif defined(TARGET_sh2) ++#define ARCH "sh2" ++#elif defined(TARGET_sh2eb) ++#define ARCH "sh2" + #elif defined(TARGET_h8300) + #define ARCH "h8300" + #elif defined(TARGET_microblaze) +@@ -1289,7 +1291,7 @@ + #endif /* TARGET_sparc */ + + +-#ifdef TARGET_sh ++#if defined(TARGET_sh2) || defined(TARGET_sh2eb) + case R_SH_DIR32: + relocation_needed = 1; + sym_vma = elf2flt_bfd_section_vma(sym_section); +@@ -1300,7 +1302,7 @@ + sym_addr += sym_vma + q->addend; + sym_addr -= q->address; + break; +-#endif /* TARGET_sh */ ++#endif /* TARGET_sh2 / TARGET_sh2eb */ + + #ifdef TARGET_e1 + #define htoe1l(x) htonl(x) diff --git a/toolchain/elf2flt/patches/v2024.02/0002-h8300.patch b/toolchain/elf2flt/patches/v2024.02/0002-h8300.patch new file mode 100644 index 000000000..2c7b73482 --- /dev/null +++ b/toolchain/elf2flt/patches/v2024.02/0002-h8300.patch @@ -0,0 +1,20 @@ +diff -Nur elf2flt-v2023.09.orig/flthdr.c elf2flt-v2023.09/flthdr.c +--- elf2flt-v2023.09.orig/flthdr.c 2023-12-23 03:20:20.000000000 +0100 ++++ elf2flt-v2023.09/flthdr.c 2023-12-23 17:11:22.699413170 +0100 +@@ -164,8 +164,16 @@ + r = ntohl(relocs[i]); + raddr = flat_get_relocate_addr(r); + printf(" %u\t0x%08lx (0x%08"PRIx32")\t", i, r, raddr); ++#if defined(TARGET_h8300) ++ raddr &= ~0x00000001; ++#endif + fseek_stream(&ifp, sizeof(old_hdr) + raddr, SEEK_SET); + fread_stream(&addr, sizeof(addr), 1, &ifp); ++#if defined(TARGET_h8300) ++ addr = ntohl(addr); ++ if (r & 1) ++ addr &= 0x00ffffff; ++#endif + printf("%"PRIx32"\n", addr); + } + diff --git a/toolchain/elf2flt/patches/v2024.02/0003-riscv64-alignment.patch b/toolchain/elf2flt/patches/v2024.02/0003-riscv64-alignment.patch new file mode 100644 index 000000000..9feef7951 --- /dev/null +++ b/toolchain/elf2flt/patches/v2024.02/0003-riscv64-alignment.patch @@ -0,0 +1,12 @@ +diff -Nur elf2flt-v2024.02.orig/elf2flt.ld.in elf2flt-v2024.02/elf2flt.ld.in +--- elf2flt-v2024.02.orig/elf2flt.ld.in 2024-03-22 04:51:08.000000000 +0100 ++++ elf2flt-v2024.02/elf2flt.ld.in 2024-03-22 13:08:31.793773247 +0100 +@@ -139,7 +139,7 @@ + @SYMBOL_PREFIX@_ssro_size = @SYMBOL_PREFIX@_essro - @SYMBOL_PREFIX@_ssro; + PROVIDE(@SYMBOL_PREFIX@_SDA2_BASE_ = @SYMBOL_PREFIX@_ssro + (@SYMBOL_PREFIX@_ssro_size / 2)); + +- . = ALIGN(4) ; ++ . = ALIGN(8) ; + TOR: @SYMBOL_PREFIX@__CTOR_LIST__ = .; + TOR: LONG((@SYMBOL_PREFIX@__CTOR_END__ - @SYMBOL_PREFIX@__CTOR_LIST__) / 4 - 2) + SINGLE_LINK: /* gcc uses crtbegin.o to find the start of diff --git a/toolchain/gcc/Makefile b/toolchain/gcc/Makefile index 3f533bad9..175af8aae 100644 --- a/toolchain/gcc/Makefile +++ b/toolchain/gcc/Makefile @@ -26,6 +26,15 @@ ifeq ($(ADK_TARGET_ARCH_ARM),y) TARGET_CFLAGS:= $(filter-out -mcpu=cortex-a9,$(TARGET_CFLAGS)) TARGET_CXXFLAGS:= $(filter-out -mcpu=cortex-a9,$(TARGET_CXXFLAGS)) endif +ifeq ($(ADK_TARGET_ARCH_ARM),y) +TARGET_CFLAGS:= $(filter-out -mcpu=cortex-a7,$(TARGET_CFLAGS)) +TARGET_CXXFLAGS:= $(filter-out -mcpu=cortex-a7,$(TARGET_CXXFLAGS)) +endif + +ifeq ($(ADK_TARGET_ARCH_ARM),y) +TARGET_CFLAGS:= $(filter-out -mcpu=xscale,$(TARGET_CFLAGS)) +TARGET_CXXFLAGS:= $(filter-out -mcpu=xscale,$(TARGET_CXXFLAGS)) +endif ifeq ($(ADK_TARGET_USE_STATIC_AND_SHARED_LIBS),y) TARGET_CFLAGS:= $(filter-out -static,$(TARGET_CFLAGS)) @@ -54,6 +63,7 @@ GCC_CONFOPTS:= --prefix=$(TOOLCHAIN_DIR)/usr \ --disable-libquadmath \ --disable-libquadmath-support \ --disable-decimal-float \ + --disable-gcov \ --disable-libstdcxx-pch \ --disable-ppl-version-check \ --disable-cloog-version-check \ @@ -155,10 +165,6 @@ ifeq ($(ADK_TARGET_ARCH_METAG),y) GCC_CONFOPTS+= --with-cpu=2.1 --enable-meta-default --disable-symvers endif -ifeq ($(ADK_TARGET_CPU_CF),y) -GCC_CONFOPTS+= --with-arch=cf --disable-multilib -endif - ifeq ($(ADK_TARGET_ARCH_NDS32),y) GCC_CONFOPTS+= --with-arch=v3 endif @@ -167,6 +173,16 @@ ifeq ($(ADK_TARGET_ARCH_M68K)$(ADK_TARGET_ARCH_X86_64)$(ADK_TARGET_ARCH_X86),) GCC_FINAL_CONFOPTS+= --disable-biarch --disable-multilib endif +ifeq ($(ADK_TARGET_CPU_CF),y) +GCC_CONFOPTS+= --with-arch=cf +GCC_INITIAL_CONFOPTS+= --enable-multilib +ifeq ($(ADK_TARGET_BINFMT_ELF)$(ADK_TARGET_WITH_MMU),y) +GCC_FINAL_CONFOPTS+= --disable-multilib --disable-threads --disable-libatomic +endif +else +GCC_INITIAL_CONFOPTS+= --disable-multilib +endif + ifeq ($(ADK_TARGET_ARCH_SH),y) ifeq ($(ADK_TARGET_LITTLE_ENDIAN),y) @@ -299,6 +315,12 @@ ifeq ($(ADK_TARGET_CPU_SH_SH4A),y) (cd ${STAGING_TARGET_DIR}/ && ln -sf . m4a) endif endif +ifeq ($(ADK_TARGET_ARCH_M68K),y) + # Need to get gcc to generate _all_ the multilib variants + # (so both MMU and non-mmu M68k and ColdFire). + $(SED) 's/M68K_MLIB_CPU +=/#M68K_MLIB_CPU +=/' $(WRKBUILD)/gcc/config/m68k/t-m68k + $(SED) 's/&& (FLAGS ~ "FL_MMU")//' $(WRKBUILD)/gcc/config/m68k/t-linux +endif $(SED) '/k prot/agcc_cv_libc_provides_ssp=yes' $(WRKBUILD)/gcc/configure cd $(GCC_BUILD_DIR_INITIAL); \ PATH='$(TARGET_PATH)' \ @@ -307,13 +329,13 @@ endif CFLAGS="-O0 -g0 -fomit-frame-pointer" \ CXXFLAGS="-O0 -g0 -fomit-frame-pointer" \ $(WRKBUILD)/configure \ + ${GCC_INITIAL_CONFOPTS} \ ${GCC_CONFOPTS} \ ${GCC_TLS_CONFOPTS} \ --enable-languages=c \ --with-newlib \ --disable-shared \ --disable-threads \ - --disable-multilib \ --without-headers touch $@ diff --git a/toolchain/gcc/Makefile.inc b/toolchain/gcc/Makefile.inc index 71c710d93..b6c24865a 100644 --- a/toolchain/gcc/Makefile.inc +++ b/toolchain/gcc/Makefile.inc @@ -2,52 +2,69 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= gcc +ifeq ($(ADK_TOOLCHAIN_GCC_13),y) +PKG_VERSION:= 13.2.0 +PKG_HASH:= 8cb4be3796651976f94b9356fa08d833524f62420d6292c5033a9a26af315078 +PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} +PKG_RELEASE:= 1 +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +LIBSTDCXXVER:= 29 +endif +ifeq ($(ADK_TOOLCHAIN_GCC_12),y) +PKG_VERSION:= 12.3.0 +PKG_HASH:= 11275aa7bb34cd8ab101d01b341015499f8d9466342a2574ece93f954d92273b +PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} +PKG_RELEASE:= 1 +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +LIBSTDCXXVER:= 28 +endif ifeq ($(ADK_TOOLCHAIN_GCC_11),y) -PKG_VERSION:= 11.3.0 -PKG_HASH:= b47cf2818691f5b1e21df2bb38c795fac2cfbd640ede2d0a5e1c89e338a3ac39 +PKG_VERSION:= 11.4.0 +PKG_HASH:= af828619dd1970734dda3cfb792ea3f2cba61b5a00170ba8bce4910749d73c07 PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz LIBSTDCXXVER:= 27 endif ifeq ($(ADK_TOOLCHAIN_GCC_10),y) -PKG_VERSION:= 10.3.0 -PKG_HASH:= 64f404c1a650f27fc33da242e1f2df54952e3963a49e06e73f6940f3223ac344 +PKG_VERSION:= 10.5.0 +PKG_HASH:= eed4dd5fc3cd9f52cb3a51a4fde1728cb19ec76292f559518e83652e7437befe PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz LIBSTDCXXVER:= 26 endif ifeq ($(ADK_TOOLCHAIN_GCC_9),y) -PKG_VERSION:= 9.4.0 -PKG_HASH:= c95da32f440378d7751dd95533186f7fc05ceb4fb65eb5b85234e6299eb9838e +PKG_VERSION:= 9.5.0 +PKG_HASH:= 15b34072105272a3eb37f6927409f7ce9aa0dd1498efebc35f851d6e6f029a4d PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz LIBSTDCXXVER:= 25 endif ifeq ($(ADK_TOOLCHAIN_GCC_8),y) PKG_VERSION:= 8.5.0 -PKG_HASH:= d308841a511bb830a6100397b0042db24ce11f642dab6ea6ee44842e5325ed50 +PKG_HASH:= 6e6e0628573d2185727a2dd83211d04a2b2748e4a262099099b9c8064634c9ee PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz LIBSTDCXXVER:= 24 endif ifeq ($(ADK_TOOLCHAIN_GCC_7),y) PKG_VERSION:= 7.5.0 -PKG_HASH:= b81946e7f01f90528a1f7352ab08cc602b9ccc05d4e44da4bd501c5a189ee661 +PKG_HASH:= 4f518f18cfb694ad7975064e99e200fe98af13603b47e67e801ba9580e50a07f PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz LIBSTDCXXVER:= 23 endif ifeq ($(ADK_TOOLCHAIN_GCC_ARC),y) -PKG_VERSION:= arc-2021.09 +PKG_VERSION:= arc-2023.09 PKG_GIT:= tag PKG_SITES:= https://github.com/foss-for-synopsys-dwc-arc-processors/gcc.git PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +LIBSTDCXXVER:= 29 endif ifeq ($(ADK_TOOLCHAIN_GCC_AVR32),y) PKG_VERSION:= 4.4.7 @@ -57,6 +74,14 @@ PKG_RELEASE:= 1 DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz LIBSTDCXXVER:= 19 endif +ifeq ($(ADK_TOOLCHAIN_GCC_LM32),y) +PKG_VERSION:= 4.5.4 +PKG_HASH:= 33fb968907ef7b6c528f6395ba049eb34c4df859bf5aa6c2bc3856268801e078 +PKG_SITES:= https://ftp.gnu.org/gnu/gcc/gcc-$(PKG_VERSION)/ +PKG_RELEASE:= 1 +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +LIBSTDCXXVER:= 19 +endif ifeq ($(ADK_TOOLCHAIN_GCC_METAG),y) PKG_VERSION:= 4.2.4 PKG_HASH:= 7cb75c5183bd18f415860084440377016dc78feeee2852227b831f2e4fcaa5d6 @@ -70,7 +95,7 @@ PKG_VERSION:= f98c17b1e78dd3a3da45c0ac1af7b105edf2bf66 PKG_GIT:= hash PKG_SITES:= https://github.com/kalray/gcc.git PKG_RELEASE:= 1 -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_GCC_GIT),y) PKG_VERSION:= git diff --git a/toolchain/gcc/patches/10.3.0/add-crtreloc.frv b/toolchain/gcc/patches/10.5.0/add-crtreloc.frv index 30de24cdc..30de24cdc 100644 --- a/toolchain/gcc/patches/10.3.0/add-crtreloc.frv +++ b/toolchain/gcc/patches/10.5.0/add-crtreloc.frv diff --git a/toolchain/gcc/patches/10.3.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/10.5.0/c6x-disable-multilib.patch index cbee6f785..cbee6f785 100644 --- a/toolchain/gcc/patches/10.3.0/c6x-disable-multilib.patch +++ b/toolchain/gcc/patches/10.5.0/c6x-disable-multilib.patch diff --git a/toolchain/gcc/patches/10.3.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/10.5.0/ia64-fix-libgcc.patch index f1f3c8d2d..f1f3c8d2d 100644 --- a/toolchain/gcc/patches/10.3.0/ia64-fix-libgcc.patch +++ b/toolchain/gcc/patches/10.5.0/ia64-fix-libgcc.patch diff --git a/toolchain/gcc/patches/10.3.0/j2.patch b/toolchain/gcc/patches/10.5.0/j2.patch index 416475546..416475546 100644 --- a/toolchain/gcc/patches/10.3.0/j2.patch +++ b/toolchain/gcc/patches/10.5.0/j2.patch diff --git a/toolchain/gcc/patches/10.3.0/nios2-softfp.patch b/toolchain/gcc/patches/10.5.0/nios2-softfp.patch index c677c6c2f..c677c6c2f 100644 --- a/toolchain/gcc/patches/10.3.0/nios2-softfp.patch +++ b/toolchain/gcc/patches/10.5.0/nios2-softfp.patch diff --git a/toolchain/gcc/patches/10.3.0/revert-sparc.patch b/toolchain/gcc/patches/10.5.0/revert-sparc.patch index 2ce948c82..2ce948c82 100644 --- a/toolchain/gcc/patches/10.3.0/revert-sparc.patch +++ b/toolchain/gcc/patches/10.5.0/revert-sparc.patch diff --git a/toolchain/gcc/patches/11.3.0/add-crtreloc.frv b/toolchain/gcc/patches/11.4.0/add-crtreloc.frv index 30de24cdc..30de24cdc 100644 --- a/toolchain/gcc/patches/11.3.0/add-crtreloc.frv +++ b/toolchain/gcc/patches/11.4.0/add-crtreloc.frv diff --git a/toolchain/gcc/patches/11.3.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/11.4.0/c6x-disable-multilib.patch index cbee6f785..cbee6f785 100644 --- a/toolchain/gcc/patches/11.3.0/c6x-disable-multilib.patch +++ b/toolchain/gcc/patches/11.4.0/c6x-disable-multilib.patch diff --git a/toolchain/gcc/patches/11.3.0/csky.patch b/toolchain/gcc/patches/11.4.0/csky.patch index ee352951b..ee352951b 100644 --- a/toolchain/gcc/patches/11.3.0/csky.patch +++ b/toolchain/gcc/patches/11.4.0/csky.patch diff --git a/toolchain/gcc/patches/11.3.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/11.4.0/ia64-fix-libgcc.patch index f1f3c8d2d..f1f3c8d2d 100644 --- a/toolchain/gcc/patches/11.3.0/ia64-fix-libgcc.patch +++ b/toolchain/gcc/patches/11.4.0/ia64-fix-libgcc.patch diff --git a/toolchain/gcc/patches/11.3.0/nios2-softfp.patch b/toolchain/gcc/patches/11.4.0/nios2-softfp.patch index c677c6c2f..c677c6c2f 100644 --- a/toolchain/gcc/patches/11.3.0/nios2-softfp.patch +++ b/toolchain/gcc/patches/11.4.0/nios2-softfp.patch diff --git a/toolchain/gcc/patches/11.3.0/revert.sparc b/toolchain/gcc/patches/11.4.0/revert.sparc index 2ce948c82..2ce948c82 100644 --- a/toolchain/gcc/patches/11.3.0/revert.sparc +++ b/toolchain/gcc/patches/11.4.0/revert.sparc diff --git a/toolchain/gcc/patches/12.3.0/csky.patch b/toolchain/gcc/patches/12.3.0/csky.patch new file mode 100644 index 000000000..ee352951b --- /dev/null +++ b/toolchain/gcc/patches/12.3.0/csky.patch @@ -0,0 +1,12 @@ +diff -Nur gcc-11.2.0.orig/libgcc/config/csky/linux-atomic.c gcc-11.2.0/libgcc/config/csky/linux-atomic.c +--- gcc-11.2.0.orig/libgcc/config/csky/linux-atomic.c 2021-07-28 08:55:08.760307899 +0200 ++++ gcc-11.2.0/libgcc/config/csky/linux-atomic.c 2021-12-14 14:19:23.685729233 +0100 +@@ -24,7 +24,7 @@ + <http://www.gnu.org/licenses/>. */ + + /* Kernel helper for compare-and-exchange. */ +-inline int ++int + __kernel_cmpxchg (int oldval, int newval, volatile int *ptr) + { + register int _a0 asm ("a0") = oldval; diff --git a/toolchain/gcc/patches/12.3.0/nios2-softfp.patch b/toolchain/gcc/patches/12.3.0/nios2-softfp.patch new file mode 100644 index 000000000..c677c6c2f --- /dev/null +++ b/toolchain/gcc/patches/12.3.0/nios2-softfp.patch @@ -0,0 +1,14 @@ +diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host +--- gcc-6.2.0.orig/libgcc/config.host 2016-05-17 08:15:52.000000000 +0200 ++++ gcc-6.2.0/libgcc/config.host 2016-10-15 14:42:53.971919904 +0200 +@@ -962,6 +962,10 @@ + ;; + esac + ;; ++nios2-*-linux-uclibc*) ++ tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp" ++ md_unwind_header=nios2/linux-unwind.h ++ ;; + nios2-*-linux*) + tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc" + md_unwind_header=nios2/linux-unwind.h diff --git a/toolchain/gcc/patches/13.2.0/csky.patch b/toolchain/gcc/patches/13.2.0/csky.patch new file mode 100644 index 000000000..ee352951b --- /dev/null +++ b/toolchain/gcc/patches/13.2.0/csky.patch @@ -0,0 +1,12 @@ +diff -Nur gcc-11.2.0.orig/libgcc/config/csky/linux-atomic.c gcc-11.2.0/libgcc/config/csky/linux-atomic.c +--- gcc-11.2.0.orig/libgcc/config/csky/linux-atomic.c 2021-07-28 08:55:08.760307899 +0200 ++++ gcc-11.2.0/libgcc/config/csky/linux-atomic.c 2021-12-14 14:19:23.685729233 +0100 +@@ -24,7 +24,7 @@ + <http://www.gnu.org/licenses/>. */ + + /* Kernel helper for compare-and-exchange. */ +-inline int ++int + __kernel_cmpxchg (int oldval, int newval, volatile int *ptr) + { + register int _a0 asm ("a0") = oldval; diff --git a/toolchain/gcc/patches/13.2.0/nios2-softfp.patch b/toolchain/gcc/patches/13.2.0/nios2-softfp.patch new file mode 100644 index 000000000..c677c6c2f --- /dev/null +++ b/toolchain/gcc/patches/13.2.0/nios2-softfp.patch @@ -0,0 +1,14 @@ +diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host +--- gcc-6.2.0.orig/libgcc/config.host 2016-05-17 08:15:52.000000000 +0200 ++++ gcc-6.2.0/libgcc/config.host 2016-10-15 14:42:53.971919904 +0200 +@@ -962,6 +962,10 @@ + ;; + esac + ;; ++nios2-*-linux-uclibc*) ++ tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp" ++ md_unwind_header=nios2/linux-unwind.h ++ ;; + nios2-*-linux*) + tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc" + md_unwind_header=nios2/linux-unwind.h diff --git a/toolchain/gcc/patches/4.5.4/gcc.lm32 b/toolchain/gcc/patches/4.5.4/gcc.lm32 index f32fb0dbd..df77ddf83 100644 --- a/toolchain/gcc/patches/4.5.4/gcc.lm32 +++ b/toolchain/gcc/patches/4.5.4/gcc.lm32 @@ -114,7 +114,7 @@ diff -Nur gcc-4.5.4.orig/libgcc/config.host gcc-4.5.4/libgcc/config.host tmake_file="lm32/t-lm32 lm32/t-elf t-softfp" ;; -lm32-*-uclinux*) -+lm32-*-linux*) ++lm32-*-*linux*) extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o" - tmake_file="lm32/t-lm32 lm32/t-uclinux t-softfp" + tmake_file="lm32/t-lm32 t-softfp" diff --git a/toolchain/gdb/Makefile.inc b/toolchain/gdb/Makefile.inc index 220b14383..c38242eef 100644 --- a/toolchain/gdb/Makefile.inc +++ b/toolchain/gdb/Makefile.inc @@ -2,12 +2,26 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= gdb -ifeq ($(ADK_TOOLCHAIN_GDB_11_2),y) -PKG_VERSION:= 11.2 +ifeq ($(ADK_TOOLCHAIN_GDB_14_2),y) +PKG_VERSION:= 14.2 PKG_RELEASE:= 1 -PKG_HASH:= 1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32 +PKG_HASH:= 2de5174762e959a5e529e20c20d88a04735469d8fffd98f61664e70b341dc47c PKG_SITES:= ${MASTER_SITE_GNU:=gdb/} -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_GDB_13_2),y) +PKG_VERSION:= 13.2 +PKG_RELEASE:= 1 +PKG_HASH:= 7ead13d9e19fa0c57bb19104e1a5f67eefa9fc79f2e6360de491e8fddeda1e30 +PKG_SITES:= ${MASTER_SITE_GNU:=gdb/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_GDB_12_1),y) +PKG_VERSION:= 12.1 +PKG_RELEASE:= 1 +PKG_HASH:= 87296a3a9727356b56712c793704082d5df0ff36a34ca9ec9734fc9a8bdfdaab +PKG_SITES:= ${MASTER_SITE_GNU:=gdb/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_GDB_6_7_1),y) PKG_VERSION:= 6.7.1 @@ -22,11 +36,11 @@ PKG_VERSION:= ysato-h8300 PKG_RELEASE:= 1 PKG_GIT:= branch PKG_SITES:= git://git.pf.osdn.jp/gitroot/y/ys/ysato/binutils_gdb.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_GDB_GIT),y) PKG_VERSION:= git PKG_RELEASE:= 1 PKG_SITES:= git://sourceware.org/git/binutils-gdb.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif diff --git a/toolchain/glibc/Makefile.inc b/toolchain/glibc/Makefile.inc index e71786616..0cd8f4987 100644 --- a/toolchain/glibc/Makefile.inc +++ b/toolchain/glibc/Makefile.inc @@ -3,16 +3,16 @@ PKG_NAME:= glibc ifeq ($(ADK_LIBC_VERSION),git) -PKG_VERSION:= 2.35.90 -PKG_GLIBCVER:= 2.35.9000 -PKG_SITES:= git://sourceware.org/git/glibc.git +PKG_VERSION:= 2.39.90 +PKG_GLIBCVER:= 2.39.9000 +PKG_SITES:= https://sourceware.org/git/glibc.git PKG_RELEASE:= 1 endif -ifeq ($(ADK_TARGET_LIB_GLIBC_2_35),y) -PKG_VERSION:= 2.35 -PKG_GLIBCVER:= 2.35 +ifeq ($(ADK_TARGET_LIB_GLIBC_2_39),y) +PKG_VERSION:= 2.39 +PKG_GLIBCVER:= 2.39 PKG_RELEASE:= 1 PKG_SITES:= ${MASTER_SITE_GNU:=glibc/} -PKG_HASH:= 5123732f6b67ccd319305efd399971d58592122bcc2a6518a1bd2510dd0cf52e +PKG_HASH:= f77bd47cf8170c57365ae7bf86696c118adb3b120d3259c64c502d3dc1e2d926 endif DISTFILES:= $(PKG_NAME)-$(PKG_VERSION).tar.xz diff --git a/toolchain/glibc/patches/2.26/0001-Do-not-use-__builtin_types_compatible_p-in-C-mode-bu.patch b/toolchain/glibc/patches/2.26/0001-Do-not-use-__builtin_types_compatible_p-in-C-mode-bu.patch deleted file mode 100644 index 27a785e31..000000000 --- a/toolchain/glibc/patches/2.26/0001-Do-not-use-__builtin_types_compatible_p-in-C-mode-bu.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f7439f9b1089e17b6721f28e228682831a2f0135 Mon Sep 17 00:00:00 2001 -From: "Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> -Date: Mon, 21 Aug 2017 14:23:27 +0200 -Subject: [PATCH] Do not use __builtin_types_compatible_p in C++ mode (bug - 21930) - -The logic to define isinf for float128 depends on the availability of -__builtin_types_compatible_p, which is only available in C mode, -however, the conditionals do not check for C or C++ mode. This lead to -an error in libstdc++ configure, as reported by bug 21930. - -This patch adds a conditional for C mode in the definition of isinf for -float128. No definition is provided in C++ mode, since libstdc++ -headers undefine isinf. - -Tested for powerpc64le (glibc test suite and libstdc++-v3 configure). - - [BZ #21930] - * math/math.h (isinf): Check if in C or C++ mode before using - __builtin_types_compatible_p, since this is a C mode feature. - -(cherry picked from commit 47a67213a9f51c5f8816d240500b10db605d8b77) -[Romain rebase on glibc 2.26] -Signed-off-by: Romain Naour <romain.naour@gmail.com> ---- - math/math.h | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/math/math.h b/math/math.h -index e217080..dea8dbe 100644 ---- a/math/math.h -+++ b/math/math.h -@@ -442,8 +442,12 @@ enum - - /* Return nonzero value if X is positive or negative infinity. */ - # if __HAVE_DISTINCT_FLOAT128 && !__GNUC_PREREQ (7,0) \ -- && !defined __SUPPORT_SNAN__ -- /* __builtin_isinf_sign is broken for float128 only before GCC 7.0. */ -+ && !defined __SUPPORT_SNAN__ && !defined __cplusplus -+ /* Since __builtin_isinf_sign is broken for float128 before GCC 7.0, -+ use the helper function, __isinff128, with older compilers. This is -+ only provided for C mode, because in C++ mode, GCC has no support -+ for __builtin_types_compatible_p (and when in C++ mode, this macro is -+ not used anyway, because libstdc++ headers undefine it). */ - # define isinf(x) \ - (__builtin_types_compatible_p (__typeof (x), _Float128) \ - ? __isinff128 (x) : __builtin_isinf_sign (x)) --- -2.9.5 - diff --git a/toolchain/glibc/patches/2.26/0002-Do-not-use-generic-selection-in-C-mode.patch b/toolchain/glibc/patches/2.26/0002-Do-not-use-generic-selection-in-C-mode.patch deleted file mode 100644 index 7321eebd6..000000000 --- a/toolchain/glibc/patches/2.26/0002-Do-not-use-generic-selection-in-C-mode.patch +++ /dev/null @@ -1,56 +0,0 @@ -From bb21afc362a3ecba07ab386a0bc4385e75fbd4b5 Mon Sep 17 00:00:00 2001 -From: "Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> -Date: Mon, 14 Aug 2017 17:51:51 -0300 -Subject: [PATCH] Do not use generic selection in C++ mode - -The logic to protect the use of generic selection (_Generic) does not -check for C or C++ mode, however, generic selection is a C-only -feature. - -Tested for powerpc64le. - - * misc/sys/cdefs.h (__HAVE_GENERIC_SELECTION): Define to 0, if - in C++ mode. - -(cherry picked from commit 6913ad65e00bb32417ad39c41d292b976171e27e) -[Romain rebase on glibc 2.26] -Signed-off-by: Romain Naour <romain.naour@gmail.com> ---- - misc/sys/cdefs.h | 19 ++++++++++--------- - 1 file changed, 10 insertions(+), 9 deletions(-) - -diff --git a/misc/sys/cdefs.h b/misc/sys/cdefs.h -index 06523bf..0c80821 100644 ---- a/misc/sys/cdefs.h -+++ b/misc/sys/cdefs.h -@@ -464,17 +464,18 @@ - # define __glibc_macro_warning(msg) - #endif - --/* Support for generic selection (ISO C11) is available in GCC since -- version 4.9. Previous versions do not provide generic selection, -- even though they might set __STDC_VERSION__ to 201112L, when in -- -std=c11 mode. Thus, we must check for !defined __GNUC__ when -- testing __STDC_VERSION__ for generic selection support. -+/* Generic selection (ISO C11) is a C-only feature, available in GCC -+ since version 4.9. Previous versions do not provide generic -+ selection, even though they might set __STDC_VERSION__ to 201112L, -+ when in -std=c11 mode. Thus, we must check for !defined __GNUC__ -+ when testing __STDC_VERSION__ for generic selection support. - On the other hand, Clang also defines __GNUC__, so a clang-specific - check is required to enable the use of generic selection. */ --#if __GNUC_PREREQ (4, 9) \ -- || __glibc_clang_has_extension (c_generic_selections) \ -- || (!defined __GNUC__ && defined __STDC_VERSION__ \ -- && __STDC_VERSION__ >= 201112L) -+#if !defined __cplusplus \ -+ && (__GNUC_PREREQ (4, 9) \ -+ || __glibc_clang_has_extension (c_generic_selections) \ -+ || (!defined __GNUC__ && defined __STDC_VERSION__ \ -+ && __STDC_VERSION__ >= 201112L)) - # define __HAVE_GENERIC_SELECTION 1 - #else - # define __HAVE_GENERIC_SELECTION 0 --- -2.9.5 - diff --git a/toolchain/glibc/patches/2.26/0003-Provide-a-C-version-of-issignaling-that-does-not-use.patch b/toolchain/glibc/patches/2.26/0003-Provide-a-C-version-of-issignaling-that-does-not-use.patch deleted file mode 100644 index b9cd3df39..000000000 --- a/toolchain/glibc/patches/2.26/0003-Provide-a-C-version-of-issignaling-that-does-not-use.patch +++ /dev/null @@ -1,225 +0,0 @@ -From 9bcf391a21677c6d5fa1c2be71554ec181e24f39 Mon Sep 17 00:00:00 2001 -From: "Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> -Date: Mon, 14 Aug 2017 13:46:15 -0300 -Subject: [PATCH] Provide a C++ version of issignaling that does not use - __MATH_TG - -The macro __MATH_TG contains the logic to select between long double and -_Float128, when these types are ABI-distinct. This logic relies on -__builtin_types_compatible_p, which is not available in C++ mode. - -On the other hand, C++ function overloading provides the means to -distinguish between the floating-point types. The overloading -resolution will match the correct parameter regardless of type -qualifiers, i.e.: const and volatile. - -Tested for powerpc64le, s390x, and x86_64. - - * math/math.h [defined __cplusplus] (issignaling): Provide a C++ - definition for issignaling that does not rely on __MATH_TG, - since __MATH_TG uses __builtin_types_compatible_p, which is only - available in C mode. - (CFLAGS-test-math-issignaling.cc): New variable. - * math/Makefile [CXX] (tests): Add test-math-issignaling. - * math/test-math-issignaling.cc: New test for C++ implementation - of type-generic issignaling. - * sysdeps/powerpc/powerpc64le/Makefile [subdir == math] - (CXXFLAGS-test-math-issignaling.cc): Add -mfloat128 to the build - options of test-math-issignaling on powerpc64le. - -(cherry picked from commit a16e8bc08edca84d507715c66d6cddbbc7ed3b62) -[Romain rebase on glibc 2.26] -Signed-off-by: Romain Naour <romain.naour@gmail.com> ---- - math/Makefile | 3 +- - math/math.h | 19 +++++- - math/test-math-issignaling.cc | 113 +++++++++++++++++++++++++++++++++++ - sysdeps/powerpc/powerpc64le/Makefile | 1 + - 4 files changed, 134 insertions(+), 2 deletions(-) - create mode 100644 math/test-math-issignaling.cc - -diff --git a/math/Makefile b/math/Makefile -index e09b0c0..0130fcf 100644 ---- a/math/Makefile -+++ b/math/Makefile -@@ -203,7 +203,7 @@ tests-static = test-fpucw-static test-fpucw-ieee-static \ - test-signgam-ullong-static test-signgam-ullong-init-static - - ifneq (,$(CXX)) --tests += test-math-isinff test-math-iszero -+tests += test-math-isinff test-math-iszero test-math-issignaling - endif - - ifneq (no,$(PERL)) -@@ -350,6 +350,7 @@ CFLAGS-test-signgam-ullong-init-static.c = -std=c99 - - CFLAGS-test-math-isinff.cc = -std=gnu++11 - CFLAGS-test-math-iszero.cc = -std=gnu++11 -+CFLAGS-test-math-issignaling.cc = -std=gnu++11 - - CFLAGS-test-iszero-excess-precision.c = -fexcess-precision=standard - CFLAGS-test-iseqsig-excess-precision.c = -fexcess-precision=standard -diff --git a/math/math.h b/math/math.h -index dea8dbe..add86af 100644 ---- a/math/math.h -+++ b/math/math.h -@@ -474,7 +474,24 @@ enum - # include <bits/iscanonical.h> - - /* Return nonzero value if X is a signaling NaN. */ --# define issignaling(x) __MATH_TG ((x), __issignaling, (x)) -+# ifndef __cplusplus -+# define issignaling(x) __MATH_TG ((x), __issignaling, (x)) -+# else -+ /* In C++ mode, __MATH_TG cannot be used, because it relies on -+ __builtin_types_compatible_p, which is a C-only builtin. On the -+ other hand, overloading provides the means to distinguish between -+ the floating-point types. The overloading resolution will match -+ the correct parameter (regardless of type qualifiers (i.e.: const -+ and volatile). */ -+extern "C++" { -+inline int issignaling (float __val) { return __issignalingf (__val); } -+inline int issignaling (double __val) { return __issignaling (__val); } -+inline int issignaling (long double __val) { return __issignalingl (__val); } -+# if __HAVE_DISTINCT_FLOAT128 -+inline int issignaling (_Float128 __val) { return __issignalingf128 (__val); } -+# endif -+} /* extern C++ */ -+# endif - - /* Return nonzero value if X is subnormal. */ - # define issubnormal(x) (fpclassify (x) == FP_SUBNORMAL) -diff --git a/math/test-math-issignaling.cc b/math/test-math-issignaling.cc -new file mode 100644 -index 0000000..22ae9e1 ---- /dev/null -+++ b/math/test-math-issignaling.cc -@@ -0,0 +1,113 @@ -+/* Test for the C++ implementation of issignaling. -+ Copyright (C) 2017 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, see -+ <http://www.gnu.org/licenses/>. */ -+ -+#define _GNU_SOURCE 1 -+#include <math.h> -+#include <stdio.h> -+ -+#include <limits> -+ -+/* There is no signaling_NaN for _Float128 in std::numeric_limits. -+ Include ieee754_float128.h and use the bitfields in the union -+ ieee854_float128.ieee_nan to build a signaling NaN. */ -+#if __HAVE_DISTINCT_FLOAT128 -+# include <ieee754_float128.h> -+#endif -+ -+static bool errors; -+ -+static void -+check (int actual, int expected, const char *actual_expr, int line) -+{ -+ if (actual != expected) -+ { -+ errors = true; -+ printf ("%s:%d: error: %s\n", __FILE__, line, actual_expr); -+ printf ("%s:%d: expected: %d\n", __FILE__, line, expected); -+ printf ("%s:%d: actual: %d\n", __FILE__, line, actual); -+ } -+} -+ -+#define CHECK(actual, expected) \ -+ check ((actual), (expected), #actual, __LINE__) -+ -+template <class T> -+static void -+check_type () -+{ -+ typedef std::numeric_limits<T> limits; -+ CHECK (issignaling (T{0}), 0); -+ if (limits::has_infinity) -+ { -+ CHECK (issignaling (limits::infinity ()), 0); -+ CHECK (issignaling (-limits::infinity ()), 0); -+ } -+ if (limits::has_quiet_NaN) -+ CHECK (issignaling (limits::quiet_NaN ()), 0); -+ if (limits::has_signaling_NaN) -+ CHECK (issignaling (limits::signaling_NaN ()), 1); -+} -+ -+#if __HAVE_DISTINCT_FLOAT128 -+static void -+check_float128 () -+{ -+ ieee854_float128 q; -+ -+ q.d = 0; -+ CHECK (issignaling (q.d), 0); -+ -+ /* Infinity. */ -+ q.ieee.negative = 0; -+ q.ieee.exponent = 0x7FFF; -+ q.ieee.mantissa0 = 0x0000; -+ q.ieee.mantissa1 = 0x00000000; -+ q.ieee.mantissa2 = 0x00000000; -+ q.ieee.mantissa3 = 0x00000000; -+ CHECK (issignaling (q.d), 0); -+ -+ /* Quiet NaN. */ -+ q.ieee_nan.quiet_nan = 1; -+ q.ieee_nan.mantissa0 = 0x0000; -+ CHECK (issignaling (q.d), 0); -+ -+ /* Still a quiet NaN. */ -+ q.ieee_nan.quiet_nan = 1; -+ q.ieee_nan.mantissa0 = 0x4000; -+ CHECK (issignaling (q.d), 0); -+ -+ /* Signaling NaN. */ -+ q.ieee_nan.quiet_nan = 0; -+ q.ieee_nan.mantissa0 = 0x4000; -+ CHECK (issignaling (q.d), 1); -+} -+#endif -+ -+static int -+do_test (void) -+{ -+ check_type<float> (); -+ check_type<double> (); -+ check_type<long double> (); -+#if __HAVE_DISTINCT_FLOAT128 -+ check_float128 (); -+#endif -+ return errors; -+} -+ -+#include <support/test-driver.c> -diff --git a/sysdeps/powerpc/powerpc64le/Makefile b/sysdeps/powerpc/powerpc64le/Makefile -index 77617b6..19adbfa 100644 ---- a/sysdeps/powerpc/powerpc64le/Makefile -+++ b/sysdeps/powerpc/powerpc64le/Makefile -@@ -16,6 +16,7 @@ $(foreach suf,$(all-object-suffixes),%f128_r$(suf)): CFLAGS += -mfloat128 - $(foreach suf,$(all-object-suffixes),$(objpfx)test-float128%$(suf)): CFLAGS += -mfloat128 - $(foreach suf,$(all-object-suffixes),$(objpfx)test-ifloat128%$(suf)): CFLAGS += -mfloat128 - CFLAGS-libm-test-support-float128.c += -mfloat128 -+CFLAGS-test-math-issignaling.cc += -mfloat128 - $(objpfx)test-float128% $(objpfx)test-ifloat128%: \ - gnulib-tests += $(f128-loader-link) - endif --- -2.9.5 - diff --git a/toolchain/glibc/patches/2.26/0004-Fix-the-C-version-of-issignaling-when-__NO_LONG_DOUB.patch b/toolchain/glibc/patches/2.26/0004-Fix-the-C-version-of-issignaling-when-__NO_LONG_DOUB.patch deleted file mode 100644 index 5e32f754d..000000000 --- a/toolchain/glibc/patches/2.26/0004-Fix-the-C-version-of-issignaling-when-__NO_LONG_DOUB.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 9dbd8386a1b706beb30291a7e76bbfe69c2620cf Mon Sep 17 00:00:00 2001 -From: "Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> -Date: Wed, 23 Aug 2017 10:16:54 -0300 -Subject: [PATCH] Fix the C++ version of issignaling when __NO_LONG_DOUBLE_MATH - is defined - -When __NO_LONG_DOUBLE_MATH is defined, __issignalingl is not available, -thus issignaling with long double argument should call __issignaling, -instead. - -Tested for powerpc64le. - - * math/math.h [defined __cplusplus] (issignaling): In the long - double case, call __issignalingl only if __NO_LONG_DOUBLE_MATH - is not defined. Call __issignaling, otherwise. - -(cherry picked from commit 3d7b66f66cb223e899a7ebc0f4c20f13e711c9e0) -[Romain rebase on glibc 2.26] -Signed-off-by: Romain Naour <romain.naour@gmail.com> ---- - math/math.h | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/math/math.h b/math/math.h -index add86af..60dfa31 100644 ---- a/math/math.h -+++ b/math/math.h -@@ -486,7 +486,15 @@ enum - extern "C++" { - inline int issignaling (float __val) { return __issignalingf (__val); } - inline int issignaling (double __val) { return __issignaling (__val); } --inline int issignaling (long double __val) { return __issignalingl (__val); } -+inline int -+issignaling (long double __val) -+{ -+# ifdef __NO_LONG_DOUBLE_MATH -+ return __issignaling (__val); -+# else -+ return __issignalingl (__val); -+# endif -+} - # if __HAVE_DISTINCT_FLOAT128 - inline int issignaling (_Float128 __val) { return __issignalingf128 (__val); } - # endif --- -2.9.5 - diff --git a/toolchain/glibc/patches/2.26/0005-Provide-a-C-version-of-iszero-that-does-not-use-__MA.patch b/toolchain/glibc/patches/2.26/0005-Provide-a-C-version-of-iszero-that-does-not-use-__MA.patch deleted file mode 100644 index e12c8438f..000000000 --- a/toolchain/glibc/patches/2.26/0005-Provide-a-C-version-of-iszero-that-does-not-use-__MA.patch +++ /dev/null @@ -1,210 +0,0 @@ -From 45970aa26d1af87b016ef95b4b35c566aeb6e841 Mon Sep 17 00:00:00 2001 -From: "Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> -Date: Tue, 22 Aug 2017 16:34:42 -0300 -Subject: [PATCH] Provide a C++ version of iszero that does not use __MATH_TG - (bug 21930) - -When signaling nans are enabled (with -fsignaling-nans), the C++ version -of iszero uses the fpclassify macro, which is defined with __MATH_TG. -However, when support for float128 is available, __MATH_TG uses the -builtin __builtin_types_compatible_p, which is only available in C mode. - -This patch refactors the C++ version of iszero so that it uses function -overloading to select between the floating-point types, instead of -relying on fpclassify and __MATH_TG. - -Tested for powerpc64le, s390x, x86_64, and with build-many-glibcs.py. - - [BZ #21930] - * math/math.h [defined __cplusplus && defined __SUPPORT_SNAN__] - (iszero): New C++ implementation that does not use - fpclassify/__MATH_TG/__builtin_types_compatible_p, when - signaling nans are enabled, since __builtin_types_compatible_p - is a C-only feature. - * math/test-math-iszero.cc: When __HAVE_DISTINCT_FLOAT128 is - defined, include ieee754_float128.h for access to the union and - member ieee854_float128.ieee. - [__HAVE_DISTINCT_FLOAT128] (do_test): Call check_float128. - [__HAVE_DISTINCT_FLOAT128] (check_float128): New function. - * sysdeps/powerpc/powerpc64le/Makefile [subdir == math] - (CXXFLAGS-test-math-iszero.cc): Add -mfloat128 to the build - options of test-math-zero on powerpc64le. - -(cherry picked from commit 42496114ec0eb7d6d039d05d4262e109951c600c) -[Romain rebase on glibc 2.26] -Signed-off-by: Romain Naour <romain.naour@gmail.com> ---- - math/math.h | 33 +++++++++++++-- - math/test-math-iszero.cc | 79 ++++++++++++++++++++++++++++++++++++ - sysdeps/powerpc/powerpc64le/Makefile | 3 +- - 3 files changed, 110 insertions(+), 5 deletions(-) - -diff --git a/math/math.h b/math/math.h -index 60dfa31..7c0fc6d 100644 ---- a/math/math.h -+++ b/math/math.h -@@ -513,15 +513,40 @@ inline int issignaling (_Float128 __val) { return __issignalingf128 (__val); } - # endif - # else /* __cplusplus */ - extern "C++" { -+# ifdef __SUPPORT_SNAN__ -+inline int -+iszero (float __val) -+{ -+ return __fpclassifyf (__val) == FP_ZERO; -+} -+inline int -+iszero (double __val) -+{ -+ return __fpclassify (__val) == FP_ZERO; -+} -+inline int -+iszero (long double __val) -+{ -+# ifdef __NO_LONG_DOUBLE_MATH -+ return __fpclassify (__val) == FP_ZERO; -+# else -+ return __fpclassifyl (__val) == FP_ZERO; -+# endif -+} -+# if __HAVE_DISTINCT_FLOAT128 -+inline int -+iszero (_Float128 __val) -+{ -+ return __fpclassifyf128 (__val) == FP_ZERO; -+} -+# endif -+# else - template <class __T> inline bool - iszero (__T __val) - { --# ifdef __SUPPORT_SNAN__ -- return fpclassify (__val) == FP_ZERO; --# else - return __val == 0; --# endif - } -+# endif - } /* extern C++ */ - # endif /* __cplusplus */ - #endif /* Use IEC_60559_BFP_EXT. */ -diff --git a/math/test-math-iszero.cc b/math/test-math-iszero.cc -index 027e972..5c07261 100644 ---- a/math/test-math-iszero.cc -+++ b/math/test-math-iszero.cc -@@ -22,6 +22,13 @@ - - #include <limits> - -+/* Support for _Float128 in std::numeric_limits is limited. -+ Include ieee754_float128.h and use the bitfields in the union -+ ieee854_float128.ieee_nan to build corner-case inputs. */ -+#if __HAVE_DISTINCT_FLOAT128 -+# include <ieee754_float128.h> -+#endif -+ - static bool errors; - - static void -@@ -72,12 +79,84 @@ check_type () - std::numeric_limits<T>::has_denorm == std::denorm_absent); - } - -+#if __HAVE_DISTINCT_FLOAT128 -+static void -+check_float128 () -+{ -+ ieee854_float128 q; -+ -+ q.d = 0.0Q; -+ CHECK (iszero (q.d), 1); -+ q.d = -0.0Q; -+ CHECK (iszero (q.d), 1); -+ q.d = 1.0Q; -+ CHECK (iszero (q.d), 0); -+ q.d = -1.0Q; -+ CHECK (iszero (q.d), 0); -+ -+ /* Normal min. */ -+ q.ieee.negative = 0; -+ q.ieee.exponent = 0x0001; -+ q.ieee.mantissa0 = 0x0000; -+ q.ieee.mantissa1 = 0x00000000; -+ q.ieee.mantissa2 = 0x00000000; -+ q.ieee.mantissa3 = 0x00000000; -+ CHECK (iszero (q.d), 0); -+ q.ieee.negative = 1; -+ CHECK (iszero (q.d), 0); -+ -+ /* Normal max. */ -+ q.ieee.negative = 0; -+ q.ieee.exponent = 0x7FFE; -+ q.ieee.mantissa0 = 0xFFFF; -+ q.ieee.mantissa1 = 0xFFFFFFFF; -+ q.ieee.mantissa2 = 0xFFFFFFFF; -+ q.ieee.mantissa3 = 0xFFFFFFFF; -+ CHECK (iszero (q.d), 0); -+ q.ieee.negative = 1; -+ CHECK (iszero (q.d), 0); -+ -+ /* Infinity. */ -+ q.ieee.negative = 0; -+ q.ieee.exponent = 0x7FFF; -+ q.ieee.mantissa0 = 0x0000; -+ q.ieee.mantissa1 = 0x00000000; -+ q.ieee.mantissa2 = 0x00000000; -+ q.ieee.mantissa3 = 0x00000000; -+ CHECK (iszero (q.d), 0); -+ -+ /* Quiet NaN. */ -+ q.ieee_nan.quiet_nan = 1; -+ q.ieee_nan.mantissa0 = 0x0000; -+ CHECK (iszero (q.d), 0); -+ -+ /* Signaling NaN. */ -+ q.ieee_nan.quiet_nan = 0; -+ q.ieee_nan.mantissa0 = 0x4000; -+ CHECK (iszero (q.d), 0); -+ -+ /* Denormal min. */ -+ q.ieee.negative = 0; -+ q.ieee.exponent = 0x0000; -+ q.ieee.mantissa0 = 0x0000; -+ q.ieee.mantissa1 = 0x00000000; -+ q.ieee.mantissa2 = 0x00000000; -+ q.ieee.mantissa3 = 0x00000001; -+ CHECK (iszero (q.d), 0); -+ q.ieee.negative = 1; -+ CHECK (iszero (q.d), 0); -+} -+#endif -+ - static int - do_test (void) - { - check_type<float> (); - check_type<double> (); - check_type<long double> (); -+#if __HAVE_DISTINCT_FLOAT128 -+ check_float128 (); -+#endif - return errors; - } - -diff --git a/sysdeps/powerpc/powerpc64le/Makefile b/sysdeps/powerpc/powerpc64le/Makefile -index 19adbfa..dea2290 100644 ---- a/sysdeps/powerpc/powerpc64le/Makefile -+++ b/sysdeps/powerpc/powerpc64le/Makefile -@@ -17,7 +17,8 @@ $(foreach suf,$(all-object-suffixes),$(objpfx)test-float128%$(suf)): CFLAGS += - - $(foreach suf,$(all-object-suffixes),$(objpfx)test-ifloat128%$(suf)): CFLAGS += -mfloat128 - CFLAGS-libm-test-support-float128.c += -mfloat128 - CFLAGS-test-math-issignaling.cc += -mfloat128 --$(objpfx)test-float128% $(objpfx)test-ifloat128%: \ -+CFLAGS-test-math-iszero.cc += -mfloat128 -+$(objpfx)test-float128% $(objpfx)test-ifloat128% $(objpfx)test-math-iszero: \ - gnulib-tests += $(f128-loader-link) - endif - --- -2.9.5 - diff --git a/toolchain/glibc/patches/2.26/0006-Let-fpclassify-use-the-builtin-when-optimizing-for-s.patch b/toolchain/glibc/patches/2.26/0006-Let-fpclassify-use-the-builtin-when-optimizing-for-s.patch deleted file mode 100644 index 37807c459..000000000 --- a/toolchain/glibc/patches/2.26/0006-Let-fpclassify-use-the-builtin-when-optimizing-for-s.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 33f54cf4f81a51e5c8cbfb2408edd439bdee9435 Mon Sep 17 00:00:00 2001 -From: "Gabriel F. T. Gomes" <gabriel@inconstante.eti.br> -Date: Wed, 20 Sep 2017 15:10:26 -0300 -Subject: [PATCH] Let fpclassify use the builtin when optimizing for size in - C++ mode (bug 22146) - -When optimization for size is on (-Os), fpclassify does not use the -type-generic __builtin_fpclassify builtin, instead it uses __MATH_TG. -However, when library support for float128 is available, __MATH_TG uses -__builtin_types_compatible_p, which is not available in C++ mode. - -On the other hand, libstdc++ undefines (in cmath) many macros from -math.h, including fpclassify, so that it can provide its own functions. -However, during its configure tests, libstdc++ just tests for the -availability of the macros (it does not undefine them, nor does it -provide its own functions). - -Finally, when libstdc++ is configured with optimization for size -enabled, its configure tests include math.h and get the definition of -fpclassify that uses __MATH_TG (and __builtin_types_compatible_p). -Since libstdc++ does not undefine the macros during its configure tests, -they fail. - -This patch lets fpclassify use the builtin in C++ mode, even when -optimization for size is on. This allows the configure test in -libstdc++ to work. - -Tested for powerpc64le and x86_64. - - [BZ #22146] - math/math.h: Let fpclassify use the builtin in C++ mode, even - when optimazing for size. - -(cherry picked from commit c5c4a626098ec884b8527356abdf2a4bb7b6bf27) - -[Romain rebase on glibc 2.26) -Signed-off-by: Romain Naour <romain.naour@gmail.com> ---- - math/math.h | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/math/math.h b/math/math.h -index 7c0fc6d..f9348ec 100644 ---- a/math/math.h -+++ b/math/math.h -@@ -402,7 +402,13 @@ enum - - /* Return number of classification appropriate for X. */ - # if __GNUC_PREREQ (4,4) && !defined __SUPPORT_SNAN__ \ -- && !defined __OPTIMIZE_SIZE__ -+ && (!defined __OPTIMIZE_SIZE__ || defined __cplusplus) -+ /* The check for __cplusplus allows the use of the builtin, even -+ when optimization for size is on. This is provided for -+ libstdc++, only to let its configure test work when it is built -+ with -Os. No further use of this definition of fpclassify is -+ expected in C++ mode, since libstdc++ provides its own version -+ of fpclassify in cmath (which undefines fpclassify). */ - # define fpclassify(x) __builtin_fpclassify (FP_NAN, FP_INFINITE, \ - FP_NORMAL, FP_SUBNORMAL, FP_ZERO, x) - # else --- -2.9.5 - diff --git a/toolchain/glibc/patches/2.38/0001-m68k-fix-__mpn_lshift-and-__mpn_rshift-for-non-68020.patch b/toolchain/glibc/patches/2.38/0001-m68k-fix-__mpn_lshift-and-__mpn_rshift-for-non-68020.patch new file mode 100644 index 000000000..d5d8e34e9 --- /dev/null +++ b/toolchain/glibc/patches/2.38/0001-m68k-fix-__mpn_lshift-and-__mpn_rshift-for-non-68020.patch @@ -0,0 +1,46 @@ +From 464fd8249e8b791248cab7b0e0cd91757435fa9e Mon Sep 17 00:00:00 2001 +From: Andreas Schwab <schwab@linux-m68k.org> +Date: Thu, 17 Aug 2023 17:15:34 +0200 +Subject: [PATCH] m68k: fix __mpn_lshift and __mpn_rshift for non-68020 + +From revision 03f3d275d0d6 in the gmp repository. + +Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> +--- + sysdeps/m68k/m680x0/lshift.S | 4 ++-- + sysdeps/m68k/m680x0/rshift.S | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/sysdeps/m68k/m680x0/lshift.S b/sysdeps/m68k/m680x0/lshift.S +index 2aee10348e..4240738959 100644 +--- a/sysdeps/m68k/m680x0/lshift.S ++++ b/sysdeps/m68k/m680x0/lshift.S +@@ -77,8 +77,8 @@ L(Lnormal:) + #else /* not mc68000 */ + movel R(s_size),R(d0) + asll #2,R(d0) +- addl R(s_size),R(s_ptr) +- addl R(s_size),R(res_ptr) ++ addl R(d0),R(s_ptr) ++ addl R(d0),R(res_ptr) + #endif + movel MEM_PREDEC(s_ptr),R(d2) + movel R(d2),R(d0) +diff --git a/sysdeps/m68k/m680x0/rshift.S b/sysdeps/m68k/m680x0/rshift.S +index d16bca9307..d56a2b4a44 100644 +--- a/sysdeps/m68k/m680x0/rshift.S ++++ b/sysdeps/m68k/m680x0/rshift.S +@@ -127,8 +127,8 @@ L(Lspecial:) + #else /* not mc68000 */ + movel R(s_size),R(d0) + asll #2,R(d0) +- addl R(s_size),R(s_ptr) +- addl R(s_size),R(res_ptr) ++ addl R(d0),R(s_ptr) ++ addl R(d0),R(res_ptr) + #endif + + clrl R(d0) /* initialize carry */ +-- +2.39.2 + diff --git a/toolchain/glibc/patches/2.38/0004-ARC-Add-support-for-ARCv3-processors.patch b/toolchain/glibc/patches/2.38/0004-ARC-Add-support-for-ARCv3-processors.patch new file mode 100644 index 000000000..cf4ca7352 --- /dev/null +++ b/toolchain/glibc/patches/2.38/0004-ARC-Add-support-for-ARCv3-processors.patch @@ -0,0 +1,4036 @@ +From ac6163148698545dd56471edabf97ffc23a519da Mon Sep 17 00:00:00 2001 +From: Alexey Brodkin <abrodkin@synopsys.com> +Date: Tue, 2 Jan 2024 03:38:32 -0800 +Subject: [PATCH] ARC: Add support for ARCv3 processors + +Signed-off-by: Vineet Gupta <vgupta@kernel.org> +Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com> +Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> +--- + config.h.in | 6 + + elf/dl-runtime.c | 4 +- + elf/elf.h | 5 +- + nptl/Makefile | 5 +- + scripts/build-many-glibcs.py | 6 + + scripts/config.sub | 8 + + sysdeps/arc/Implies | 1 - + sysdeps/arc/__longjmp.S | 62 +- + sysdeps/arc/arc32/Implies | 1 + + sysdeps/arc/arc64/Implies | 1 + + sysdeps/arc/arc64/fpu/libm-test-ulps | 1141 +++++++++++++++++ + sysdeps/arc/arc64/fpu/libm-test-ulps-name | 1 + + sysdeps/arc/{ => arc64}/nofpu/libm-test-ulps | 1 + + sysdeps/arc/arc64/nofpu/libm-test-ulps-name | 1 + + sysdeps/arc/atomic-machine.h | 41 +- + sysdeps/arc/bits/setjmp.h | 6 +- + sysdeps/arc/configure | 80 +- + sysdeps/arc/configure.ac | 36 + + sysdeps/arc/dl-machine.h | 75 +- + sysdeps/arc/dl-trampoline.S | 89 +- + sysdeps/arc/fpu/math-use-builtins-fma.h | 18 +- + sysdeps/arc/fpu/math-use-builtins-sqrt.h | 18 +- + sysdeps/arc/isa-asm-macro-32.h | 61 + + sysdeps/arc/isa-asm-macro-64.h | 86 ++ + sysdeps/arc/isa-asm-macros.h | 35 + + sysdeps/arc/nofpu/libm-test-ulps | 1 + + sysdeps/arc/nptl/pthreaddef.h | 2 +- + sysdeps/arc/preconfigure | 18 +- + sysdeps/arc/setjmp.S | 55 +- + sysdeps/arc/sfp-machine.h | 55 +- + sysdeps/arc/start.S | 14 +- + sysdeps/arc/sysdep.h | 5 +- + sysdeps/unix/sysv/linux/arc/Makefile | 8 +- + sysdeps/unix/sysv/linux/arc/arc32/Implies | 1 + + .../sysv/linux/arc/{ => arc32}/arch-syscall.h | 0 + .../sysv/linux/arc/{ => arc32}/c++-types.data | 0 + .../linux/arc/{ => arc32}/fixup-asm-unistd.h | 0 + .../sysv/linux/arc/{ => arc32}/ld.abilist | 0 + .../arc/{ => arc32}/libBrokenLocale.abilist | 0 + .../sysv/linux/arc/{ => arc32}/libanl.abilist | 0 + .../sysv/linux/arc/{ => arc32}/libc.abilist | 0 + .../arc/{ => arc32}/libc_malloc_debug.abilist | 0 + .../linux/arc/{ => arc32}/libcrypt.abilist | 0 + .../sysv/linux/arc/{ => arc32}/libdl.abilist | 0 + .../sysv/linux/arc/{ => arc32}/libm.abilist | 0 + .../linux/arc/{ => arc32}/libpthread.abilist | 0 + .../linux/arc/{ => arc32}/libresolv.abilist | 0 + .../sysv/linux/arc/{ => arc32}/librt.abilist | 0 + .../arc/{ => arc32}/libthread_db.abilist | 0 + .../linux/arc/{ => arc32}/libutil.abilist | 0 + sysdeps/unix/sysv/linux/arc/arc64/Implies | 2 + + .../sysv/linux/arc/{ => arc64}/arch-syscall.h | 59 +- + .../sysv/linux/arc/{ => arc64}/c++-types.data | 48 +- + .../sysv/linux/arc/{ => arc64}/ld.abilist | 8 +- + .../arc/{ => arc64}/libBrokenLocale.abilist | 0 + .../sysv/linux/arc/{ => arc64}/libanl.abilist | 0 + .../sysv/linux/arc/{ => arc64}/libc.abilist | 82 +- + .../arc/{ => arc64}/libc_malloc_debug.abilist | 8 +- + .../linux/arc/{ => arc64}/libcrypt.abilist | 0 + .../sysv/linux/arc/{ => arc64}/libdl.abilist | 0 + .../sysv/linux/arc/{ => arc64}/libm.abilist | 0 + .../linux/arc/{ => arc64}/libpthread.abilist | 0 + .../linux/arc/{ => arc64}/libresolv.abilist | 4 +- + .../sysv/linux/arc/{ => arc64}/librt.abilist | 0 + .../arc/{ => arc64}/libthread_db.abilist | 0 + .../linux/arc/{ => arc64}/libutil.abilist | 0 + sysdeps/unix/sysv/linux/arc/bits/fcntl.h | 62 + + .../sysv/linux/arc/bits/types/__sigset_t.h | 2 +- + sysdeps/unix/sysv/linux/arc/clone.S | 30 +- + sysdeps/unix/sysv/linux/arc/clone3.S | 14 +- + sysdeps/unix/sysv/linux/arc/getcontext.S | 71 +- + sysdeps/unix/sysv/linux/arc/setcontext.S | 88 +- + sysdeps/unix/sysv/linux/arc/shlib-versions | 8 + + sysdeps/unix/sysv/linux/arc/swapcontext.S | 129 +- + sysdeps/unix/sysv/linux/arc/sys/ucontext.h | 1 + + sysdeps/unix/sysv/linux/arc/syscall.S | 16 +- + sysdeps/unix/sysv/linux/arc/sysdep.h | 16 +- + sysdeps/unix/sysv/linux/arc/vfork.S | 4 +- + timezone/zic.c | 2 +- + 79 files changed, 2211 insertions(+), 390 deletions(-) + mode change 100755 => 100644 scripts/config.sub + create mode 100644 sysdeps/arc/arc32/Implies + create mode 100644 sysdeps/arc/arc64/Implies + create mode 100644 sysdeps/arc/arc64/fpu/libm-test-ulps + create mode 100644 sysdeps/arc/arc64/fpu/libm-test-ulps-name + copy sysdeps/arc/{ => arc64}/nofpu/libm-test-ulps (99%) + create mode 100644 sysdeps/arc/arc64/nofpu/libm-test-ulps-name + create mode 100644 sysdeps/arc/isa-asm-macro-32.h + create mode 100644 sysdeps/arc/isa-asm-macro-64.h + create mode 100644 sysdeps/arc/isa-asm-macros.h + create mode 100644 sysdeps/unix/sysv/linux/arc/arc32/Implies + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/arch-syscall.h (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/c++-types.data (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc32}/fixup-asm-unistd.h (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/ld.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libBrokenLocale.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libanl.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libc.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libc_malloc_debug.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libcrypt.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libdl.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libm.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libpthread.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libresolv.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/librt.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libthread_db.abilist (100%) + copy sysdeps/unix/sysv/linux/arc/{ => arc32}/libutil.abilist (100%) + create mode 100644 sysdeps/unix/sysv/linux/arc/arc64/Implies + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/arch-syscall.h (89%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/c++-types.data (73%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/ld.abilist (54%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libBrokenLocale.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libanl.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libc.abilist (97%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libc_malloc_debug.abilist (80%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libcrypt.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libdl.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libm.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libpthread.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libresolv.abilist (95%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/librt.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libthread_db.abilist (100%) + rename sysdeps/unix/sysv/linux/arc/{ => arc64}/libutil.abilist (100%) + create mode 100644 sysdeps/unix/sysv/linux/arc/bits/fcntl.h + +diff --git a/config.h.in b/config.h.in +index 0dedc124f7..d69b4166c0 100644 +--- a/config.h.in ++++ b/config.h.in +@@ -120,6 +120,12 @@ + /* ARC big endian ABI */ + #undef HAVE_ARC_BE + ++/* ARC64:32 ABI */ ++#undef HAVE_ARC32 ++ ++/* ARC64:64 ABI */ ++#undef HAVE_ARC64 ++ + /* C-SKY ABI version. */ + #undef CSKYABI + +diff --git a/elf/dl-runtime.c b/elf/dl-runtime.c +index 32a8bfcf74..68ffdb1c24 100644 +--- a/elf/dl-runtime.c ++++ b/elf/dl-runtime.c +@@ -42,7 +42,7 @@ _dl_fixup ( + # ifdef ELF_MACHINE_RUNTIME_FIXUP_ARGS + ELF_MACHINE_RUNTIME_FIXUP_ARGS, + # endif +- struct link_map *l, ElfW(Word) reloc_arg) ++ struct link_map *l, uintptr_t reloc_arg) + { + const ElfW(Sym) *const symtab + = (const void *) D_PTR (l, l_info[DT_SYMTAB]); +@@ -170,7 +170,7 @@ _dl_profile_fixup ( + #ifdef ELF_MACHINE_RUNTIME_FIXUP_ARGS + ELF_MACHINE_RUNTIME_FIXUP_ARGS, + #endif +- struct link_map *l, ElfW(Word) reloc_arg, ++ struct link_map *l, uintptr_t reloc_arg, + ElfW(Addr) retaddr, void *regs, long int *framesizep) + { + void (*mcount_fct) (ElfW(Addr), ElfW(Addr)) = _dl_mcount; +diff --git a/elf/elf.h b/elf/elf.h +index 89fc8021e9..05cc75c631 100644 +--- a/elf/elf.h ++++ b/elf/elf.h +@@ -358,6 +358,8 @@ typedef struct + + #define EM_BPF 247 /* Linux BPF -- in-kernel virtual machine */ + #define EM_CSKY 252 /* C-SKY */ ++#define EM_ARCV3 253 /* Synopsys ARCv3 64-bit ISA */ ++#define EM_ARCV3_32 255 /* Synopsys ARCv3 32-bit ISA */ + #define EM_LOONGARCH 258 /* LoongArch */ + + #define EM_NUM 259 +@@ -4216,12 +4218,13 @@ enum + /* Processor specific values for the Shdr sh_type field. */ + #define SHT_ARC_ATTRIBUTES (SHT_LOPROC + 1) /* ARC attributes section. */ + +-/* ARCompact/ARCv2 specific relocs. */ ++/* ARCompact/ARCv2/ARCv3 specific relocs. */ + #define R_ARC_NONE 0x0 + #define R_ARC_8 0x1 + #define R_ARC_16 0x2 + #define R_ARC_24 0x3 + #define R_ARC_32 0x4 ++#define R_ARC_64 0x5 + + #define R_ARC_B22_PCREL 0x6 + #define R_ARC_H30 0x7 +diff --git a/nptl/Makefile b/nptl/Makefile +index ffa5722e48..c8b7674c27 100644 +--- a/nptl/Makefile ++++ b/nptl/Makefile +@@ -353,6 +353,7 @@ tests = \ + tst-thread-exit-clobber \ + tst-thread-setspecific \ + tst-thread_local1 \ ++ tst-eintr1 \ + tst-tsd3 \ + tst-tsd4 \ + # tests +@@ -397,10 +398,6 @@ tests-time64 := \ + tst-cancel4_2-time64 + # tests-time64 + +-# This test can run into task limits because of a linux kernel bug +-# and then cause the make process to fail too, see bug 24537. +-xtests += tst-eintr1 +- + test-srcs = tst-oddstacklimit + + gen-as-const-headers = unwindbuf.sym +diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py +index 73ffc57c86..6f53c195cd 100755 +--- a/scripts/build-many-glibcs.py ++++ b/scripts/build-many-glibcs.py +@@ -172,6 +172,12 @@ class Context(object): + self.add_config(arch='arceb', + os_name='linux-gnu', + gcc_cfg=['--disable-multilib', '--with-cpu=hs38']) ++ self.add_config(arch='arc64', ++ os_name='linux-gnu', ++ gcc_cfg=['--disable-multilib']) ++ self.add_config(arch='arc64', ++ os_name='linux-gnuhf', ++ gcc_cfg=['--disable-multilib', '--with-fpu=fpud']) + self.add_config(arch='alpha', + os_name='linux-gnu') + self.add_config(arch='arm', +diff --git a/scripts/config.sub b/scripts/config.sub +old mode 100755 +new mode 100644 +index dba16e84c7..4d9a117c9c +--- a/scripts/config.sub ++++ b/scripts/config.sub +@@ -1170,6 +1170,14 @@ case $cpu-$vendor in + cpu=mipsallegrexel + vendor=sony + ;; ++ arc32*-*) ++ cpu=arc32 ++ vendor=linux ++ ;; ++ arc64*-*) ++ cpu=arc64 ++ vendor=linux ++ ;; + tile*-*) + basic_os=${basic_os:-linux-gnu} + ;; +diff --git a/sysdeps/arc/Implies b/sysdeps/arc/Implies +index 780c4e2467..12ca48b4c9 100644 +--- a/sysdeps/arc/Implies ++++ b/sysdeps/arc/Implies +@@ -1,3 +1,2 @@ +-wordsize-32 + ieee754/flt-32 + ieee754/dbl-64 +diff --git a/sysdeps/arc/__longjmp.S b/sysdeps/arc/__longjmp.S +index a57054bce0..920e535ffd 100644 +--- a/sysdeps/arc/__longjmp.S ++++ b/sysdeps/arc/__longjmp.S +@@ -24,25 +24,49 @@ + + ENTRY (__longjmp) + +- LDR (blink, r0, 0) +- LDR (sp, r0, 1) +- LDR (fp, r0, 2) +- LDR (gp, r0, 3) +- +- LDR (r13, r0, 4) +- LDR (r14, r0, 5) +- LDR (r15, r0, 6) +- LDR (r16, r0, 7) +- LDR (r17, r0, 8) +- LDR (r18, r0, 9) +- LDR (r19, r0, 10) +- LDR (r20, r0, 11) +- LDR (r21, r0, 12) +- LDR (r22, r0, 13) +- LDR (r23, r0, 14) +- LDR (r24, r0, 15) +- +- mov.f r0, r1 ++ LDR.as blink, r0, 0 ++ LDR.as sp, r0, 1 ++ LDR.as fp, r0, 2 ++ LDR.as gp, r0, 3 ++ ++ LDR.as r13, r0, 4 ++ LDR.as r14, r0, 5 ++ LDR.as r15, r0, 6 ++ LDR.as r16, r0, 7 ++ LDR.as r17, r0, 8 ++ LDR.as r18, r0, 9 ++ LDR.as r19, r0, 10 ++ LDR.as r20, r0, 11 ++ LDR.as r21, r0, 12 ++ LDR.as r22, r0, 13 ++ LDR.as r23, r0, 14 ++ LDR.as r24, r0, 15 ++ ++#if defined(__ARCV3__) ++ LDR.as r25, r0, 16 ++ LDR.as r26, r0, 17 ++#endif ++ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FLDR.as f16, r0, 18 ++ FLDR.as f17, r0, 19 ++ FLDR.as f18, r0, 20 ++ FLDR.as f19, r0, 21 ++ FLDR.as f20, r0, 22 ++ FLDR.as f21, r0, 23 ++ FLDR.as f22, r0, 24 ++ FLDR.as f23, r0, 25 ++ FLDR.as f24, r0, 26 ++ FLDR.as f25, r0, 27 ++ FLDR.as f26, r0, 28 ++ FLDR.as f27, r0, 29 ++ FLDR.as f28, r0, 30 ++ FLDR.as f29, r0, 31 ++ FLDR.as f30, r0, 32 ++ FLDR.as f31, r0, 33 ++#endif ++ ++ MOVR.f r0, r1 + j.d [blink] + mov.z r0, 1 /* don't return 0 to setjmp callsite from longjmp. */ + +diff --git a/sysdeps/arc/arc32/Implies b/sysdeps/arc/arc32/Implies +new file mode 100644 +index 0000000000..39a34c5f57 +--- /dev/null ++++ b/sysdeps/arc/arc32/Implies +@@ -0,0 +1 @@ ++wordsize-32 +diff --git a/sysdeps/arc/arc64/Implies b/sysdeps/arc/arc64/Implies +new file mode 100644 +index 0000000000..a8cae95f9d +--- /dev/null ++++ b/sysdeps/arc/arc64/Implies +@@ -0,0 +1 @@ ++wordsize-64 +diff --git a/sysdeps/arc/arc64/fpu/libm-test-ulps b/sysdeps/arc/arc64/fpu/libm-test-ulps +new file mode 100644 +index 0000000000..f3b8753c4d +--- /dev/null ++++ b/sysdeps/arc/arc64/fpu/libm-test-ulps +@@ -0,0 +1,1141 @@ ++# Begin of automatic generation ++ ++# Maximal error of functions: ++Function: "acos": ++double: 1 ++float: 1 ++ ++Function: "acos_downward": ++double: 1 ++float: 1 ++ ++Function: "acos_towardzero": ++double: 1 ++float: 1 ++ ++Function: "acos_upward": ++double: 1 ++float: 1 ++ ++Function: "acosh": ++double: 2 ++float: 2 ++ ++Function: "acosh_downward": ++double: 2 ++float: 2 ++ ++Function: "acosh_towardzero": ++double: 2 ++float: 2 ++ ++Function: "acosh_upward": ++double: 2 ++float: 2 ++ ++Function: "asin": ++double: 1 ++float: 1 ++ ++Function: "asin_downward": ++double: 1 ++float: 1 ++ ++Function: "asin_towardzero": ++double: 1 ++float: 1 ++ ++Function: "asin_upward": ++double: 2 ++float: 1 ++ ++Function: "asinh": ++double: 2 ++float: 2 ++ ++Function: "asinh_downward": ++double: 3 ++float: 3 ++ ++Function: "asinh_towardzero": ++double: 2 ++float: 2 ++ ++Function: "asinh_upward": ++double: 3 ++float: 3 ++ ++Function: "atan": ++double: 1 ++float: 1 ++ ++Function: "atan2": ++float: 1 ++ ++Function: "atan2_downward": ++double: 1 ++float: 2 ++ ++Function: "atan2_towardzero": ++double: 1 ++float: 2 ++ ++Function: "atan2_upward": ++double: 1 ++float: 1 ++ ++Function: "atan_downward": ++double: 1 ++float: 2 ++ ++Function: "atan_towardzero": ++double: 1 ++float: 1 ++ ++Function: "atan_upward": ++double: 1 ++float: 2 ++ ++Function: "atanh": ++double: 2 ++float: 2 ++ ++Function: "atanh_downward": ++double: 3 ++float: 3 ++ ++Function: "atanh_towardzero": ++double: 2 ++float: 2 ++ ++Function: "atanh_upward": ++double: 3 ++float: 3 ++ ++Function: "cabs": ++double: 1 ++ ++Function: "cabs_downward": ++double: 1 ++ ++Function: "cabs_towardzero": ++double: 1 ++ ++Function: "cabs_upward": ++double: 1 ++float: 1 ++ ++Function: Real part of "cacos": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "cacos": ++double: 2 ++float: 2 ++ ++Function: Real part of "cacos_downward": ++double: 3 ++float: 2 ++ ++Function: Imaginary part of "cacos_downward": ++double: 5 ++float: 3 ++ ++Function: Real part of "cacos_towardzero": ++double: 3 ++float: 2 ++ ++Function: Imaginary part of "cacos_towardzero": ++double: 4 ++float: 2 ++ ++Function: Real part of "cacos_upward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "cacos_upward": ++double: 5 ++float: 5 ++ ++Function: Real part of "cacosh": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "cacosh": ++double: 1 ++float: 2 ++ ++Function: Real part of "cacosh_downward": ++double: 4 ++float: 2 ++ ++Function: Imaginary part of "cacosh_downward": ++double: 3 ++float: 3 ++ ++Function: Real part of "cacosh_towardzero": ++double: 4 ++float: 2 ++ ++Function: Imaginary part of "cacosh_towardzero": ++double: 3 ++float: 2 ++ ++Function: Real part of "cacosh_upward": ++double: 4 ++float: 3 ++ ++Function: Imaginary part of "cacosh_upward": ++double: 3 ++float: 2 ++ ++Function: "carg": ++float: 1 ++ ++Function: "carg_downward": ++double: 1 ++float: 2 ++ ++Function: "carg_towardzero": ++double: 1 ++float: 2 ++ ++Function: "carg_upward": ++double: 1 ++float: 1 ++ ++Function: Real part of "casin": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "casin": ++double: 2 ++float: 2 ++ ++Function: Real part of "casin_downward": ++double: 3 ++float: 2 ++ ++Function: Imaginary part of "casin_downward": ++double: 5 ++float: 3 ++ ++Function: Real part of "casin_towardzero": ++double: 3 ++float: 1 ++ ++Function: Imaginary part of "casin_towardzero": ++double: 4 ++float: 2 ++ ++Function: Real part of "casin_upward": ++double: 3 ++float: 2 ++ ++Function: Imaginary part of "casin_upward": ++double: 5 ++float: 5 ++ ++Function: Real part of "casinh": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "casinh": ++double: 1 ++float: 1 ++ ++Function: Real part of "casinh_downward": ++double: 5 ++float: 3 ++ ++Function: Imaginary part of "casinh_downward": ++double: 3 ++float: 2 ++ ++Function: Real part of "casinh_towardzero": ++double: 4 ++float: 2 ++ ++Function: Imaginary part of "casinh_towardzero": ++double: 3 ++float: 1 ++ ++Function: Real part of "casinh_upward": ++double: 5 ++float: 5 ++ ++Function: Imaginary part of "casinh_upward": ++double: 3 ++float: 2 ++ ++Function: Real part of "catan": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "catan": ++double: 1 ++float: 1 ++ ++Function: Real part of "catan_downward": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "catan_downward": ++double: 2 ++float: 2 ++ ++Function: Real part of "catan_towardzero": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "catan_towardzero": ++double: 2 ++float: 2 ++ ++Function: Real part of "catan_upward": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "catan_upward": ++double: 2 ++float: 2 ++ ++Function: Real part of "catanh": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "catanh": ++double: 1 ++float: 1 ++ ++Function: Real part of "catanh_downward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "catanh_downward": ++double: 1 ++float: 2 ++ ++Function: Real part of "catanh_towardzero": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "catanh_towardzero": ++double: 1 ++float: 2 ++ ++Function: Real part of "catanh_upward": ++double: 4 ++float: 4 ++ ++Function: Imaginary part of "catanh_upward": ++double: 1 ++float: 1 ++ ++Function: "cbrt": ++double: 4 ++float: 1 ++ ++Function: "cbrt_downward": ++double: 4 ++float: 1 ++ ++Function: "cbrt_towardzero": ++double: 3 ++float: 1 ++ ++Function: "cbrt_upward": ++double: 5 ++float: 1 ++ ++Function: Real part of "ccos": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "ccos": ++double: 1 ++float: 1 ++ ++Function: Real part of "ccos_downward": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "ccos_downward": ++double: 3 ++float: 3 ++ ++Function: Real part of "ccos_towardzero": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "ccos_towardzero": ++double: 3 ++float: 3 ++ ++Function: Real part of "ccos_upward": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "ccos_upward": ++double: 2 ++float: 2 ++ ++Function: Real part of "ccosh": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "ccosh": ++double: 1 ++float: 1 ++ ++Function: Real part of "ccosh_downward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "ccosh_downward": ++double: 3 ++float: 3 ++ ++Function: Real part of "ccosh_towardzero": ++double: 2 ++float: 3 ++ ++Function: Imaginary part of "ccosh_towardzero": ++double: 3 ++float: 3 ++ ++Function: Real part of "ccosh_upward": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "ccosh_upward": ++double: 2 ++float: 2 ++ ++Function: Real part of "cexp": ++double: 2 ++float: 1 ++ ++Function: Imaginary part of "cexp": ++double: 1 ++float: 2 ++ ++Function: Real part of "cexp_downward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "cexp_downward": ++double: 3 ++float: 3 ++ ++Function: Real part of "cexp_towardzero": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "cexp_towardzero": ++double: 3 ++float: 3 ++ ++Function: Real part of "cexp_upward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "cexp_upward": ++double: 3 ++float: 2 ++ ++Function: Real part of "clog": ++double: 3 ++float: 3 ++ ++Function: Imaginary part of "clog": ++double: 1 ++float: 1 ++ ++Function: Real part of "clog10": ++double: 3 ++float: 4 ++ ++Function: Imaginary part of "clog10": ++double: 2 ++float: 2 ++ ++Function: Real part of "clog10_downward": ++double: 5 ++float: 5 ++ ++Function: Imaginary part of "clog10_downward": ++double: 2 ++float: 4 ++ ++Function: Real part of "clog10_towardzero": ++double: 5 ++float: 6 ++ ++Function: Imaginary part of "clog10_towardzero": ++double: 2 ++float: 4 ++ ++Function: Real part of "clog10_upward": ++double: 6 ++float: 5 ++ ++Function: Imaginary part of "clog10_upward": ++double: 2 ++float: 4 ++ ++Function: Real part of "clog_downward": ++double: 4 ++float: 3 ++ ++Function: Imaginary part of "clog_downward": ++double: 1 ++float: 2 ++ ++Function: Real part of "clog_towardzero": ++double: 4 ++float: 4 ++ ++Function: Imaginary part of "clog_towardzero": ++double: 1 ++float: 3 ++ ++Function: Real part of "clog_upward": ++double: 4 ++float: 3 ++ ++Function: Imaginary part of "clog_upward": ++double: 1 ++float: 2 ++ ++Function: "cos": ++double: 1 ++float: 1 ++ ++Function: "cos_downward": ++double: 1 ++float: 1 ++ ++Function: "cos_towardzero": ++double: 1 ++float: 1 ++ ++Function: "cos_upward": ++double: 1 ++float: 1 ++ ++Function: "cosh": ++double: 2 ++float: 2 ++ ++Function: "cosh_downward": ++double: 3 ++float: 2 ++ ++Function: "cosh_towardzero": ++double: 3 ++float: 2 ++ ++Function: "cosh_upward": ++double: 2 ++float: 2 ++ ++Function: Real part of "cpow": ++double: 2 ++float: 5 ++ ++Function: Imaginary part of "cpow": ++float: 2 ++ ++Function: Real part of "cpow_downward": ++double: 5 ++float: 8 ++ ++Function: Imaginary part of "cpow_downward": ++double: 1 ++float: 2 ++ ++Function: Real part of "cpow_towardzero": ++double: 5 ++float: 8 ++ ++Function: Imaginary part of "cpow_towardzero": ++double: 1 ++float: 2 ++ ++Function: Real part of "cpow_upward": ++double: 4 ++float: 1 ++ ++Function: Imaginary part of "cpow_upward": ++double: 1 ++float: 2 ++ ++Function: Real part of "csin": ++double: 1 ++float: 1 ++ ++Function: Real part of "csin_downward": ++double: 3 ++float: 3 ++ ++Function: Imaginary part of "csin_downward": ++double: 1 ++float: 1 ++ ++Function: Real part of "csin_towardzero": ++double: 3 ++float: 3 ++ ++Function: Imaginary part of "csin_towardzero": ++double: 1 ++float: 1 ++ ++Function: Real part of "csin_upward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "csin_upward": ++double: 1 ++float: 2 ++ ++Function: Real part of "csinh": ++float: 1 ++ ++Function: Imaginary part of "csinh": ++double: 1 ++float: 1 ++ ++Function: Real part of "csinh_downward": ++double: 2 ++float: 1 ++ ++Function: Imaginary part of "csinh_downward": ++double: 3 ++float: 3 ++ ++Function: Real part of "csinh_towardzero": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "csinh_towardzero": ++double: 3 ++float: 3 ++ ++Function: Real part of "csinh_upward": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "csinh_upward": ++double: 2 ++float: 2 ++ ++Function: Real part of "csqrt": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "csqrt": ++double: 2 ++float: 2 ++ ++Function: Real part of "csqrt_downward": ++double: 5 ++float: 4 ++ ++Function: Imaginary part of "csqrt_downward": ++double: 4 ++float: 3 ++ ++Function: Real part of "csqrt_towardzero": ++double: 4 ++float: 3 ++ ++Function: Imaginary part of "csqrt_towardzero": ++double: 4 ++float: 3 ++ ++Function: Real part of "csqrt_upward": ++double: 5 ++float: 4 ++ ++Function: Imaginary part of "csqrt_upward": ++double: 3 ++float: 3 ++ ++Function: Real part of "ctan": ++double: 1 ++float: 1 ++ ++Function: Imaginary part of "ctan": ++double: 2 ++float: 2 ++ ++Function: Real part of "ctan_downward": ++double: 6 ++float: 5 ++ ++Function: Imaginary part of "ctan_downward": ++double: 2 ++float: 2 ++ ++Function: Real part of "ctan_towardzero": ++double: 5 ++float: 2 ++ ++Function: Imaginary part of "ctan_towardzero": ++double: 2 ++float: 2 ++ ++Function: Real part of "ctan_upward": ++double: 2 ++float: 4 ++ ++Function: Imaginary part of "ctan_upward": ++double: 1 ++float: 2 ++ ++Function: Real part of "ctanh": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "ctanh": ++double: 2 ++float: 2 ++ ++Function: Real part of "ctanh_downward": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "ctanh_downward": ++double: 6 ++float: 5 ++ ++Function: Real part of "ctanh_towardzero": ++double: 2 ++float: 2 ++ ++Function: Imaginary part of "ctanh_towardzero": ++double: 5 ++float: 2 ++ ++Function: Real part of "ctanh_upward": ++double: 1 ++float: 2 ++ ++Function: Imaginary part of "ctanh_upward": ++double: 3 ++float: 3 ++ ++Function: "erf": ++double: 1 ++float: 1 ++ ++Function: "erf_downward": ++double: 1 ++float: 1 ++ ++Function: "erf_towardzero": ++double: 1 ++float: 1 ++ ++Function: "erf_upward": ++double: 1 ++float: 1 ++ ++Function: "erfc": ++double: 3 ++float: 3 ++ ++Function: "erfc_downward": ++double: 4 ++float: 4 ++ ++Function: "erfc_towardzero": ++double: 3 ++float: 3 ++ ++Function: "erfc_upward": ++double: 4 ++float: 4 ++ ++Function: "exp": ++double: 1 ++float: 1 ++ ++Function: "exp10": ++double: 2 ++float: 1 ++ ++Function: "exp10_downward": ++double: 3 ++float: 1 ++ ++Function: "exp10_towardzero": ++double: 3 ++float: 1 ++ ++Function: "exp10_upward": ++double: 2 ++float: 1 ++ ++Function: "exp2": ++double: 1 ++ ++Function: "exp2_downward": ++double: 1 ++float: 1 ++ ++Function: "exp2_towardzero": ++double: 1 ++float: 1 ++ ++Function: "exp2_upward": ++double: 1 ++float: 1 ++ ++Function: "exp_downward": ++double: 1 ++float: 1 ++ ++Function: "exp_towardzero": ++double: 1 ++float: 1 ++ ++Function: "exp_upward": ++double: 1 ++float: 1 ++ ++Function: "expm1": ++double: 1 ++float: 1 ++ ++Function: "expm1_downward": ++double: 1 ++float: 1 ++ ++Function: "expm1_towardzero": ++double: 1 ++float: 2 ++ ++Function: "expm1_upward": ++double: 1 ++float: 1 ++ ++Function: "gamma": ++double: 4 ++float: 7 ++ ++Function: "gamma_downward": ++double: 4 ++float: 4 ++ ++Function: "gamma_towardzero": ++double: 4 ++float: 3 ++ ++Function: "gamma_upward": ++double: 4 ++float: 5 ++ ++Function: "hypot": ++double: 1 ++float: 1 ++ ++Function: "hypot_downward": ++double: 1 ++float: 1 ++ ++Function: "hypot_towardzero": ++double: 1 ++float: 1 ++ ++Function: "hypot_upward": ++double: 1 ++float: 1 ++ ++Function: "j0": ++double: 4 ++float: 9 ++ ++Function: "j0_downward": ++double: 6 ++float: 8 ++ ++Function: "j0_towardzero": ++double: 4 ++float: 9 ++ ++Function: "j0_upward": ++double: 4 ++float: 9 ++ ++Function: "j1": ++double: 3 ++float: 9 ++ ++Function: "j1_downward": ++double: 9 ++float: 9 ++ ++Function: "j1_towardzero": ++double: 5 ++float: 9 ++ ++Function: "j1_upward": ++double: 5 ++float: 8 ++ ++Function: "jn": ++double: 4 ++float: 4 ++ ++Function: "jn_downward": ++double: 4 ++float: 5 ++ ++Function: "jn_towardzero": ++double: 4 ++float: 5 ++ ++Function: "jn_upward": ++double: 5 ++float: 5 ++ ++Function: "lgamma": ++double: 4 ++float: 7 ++ ++Function: "lgamma_downward": ++double: 4 ++float: 4 ++ ++Function: "lgamma_towardzero": ++double: 4 ++float: 3 ++ ++Function: "lgamma_upward": ++double: 4 ++float: 5 ++ ++Function: "log": ++double: 1 ++ ++Function: "log10": ++double: 2 ++float: 2 ++ ++Function: "log10_downward": ++double: 2 ++float: 3 ++ ++Function: "log10_towardzero": ++double: 2 ++float: 2 ++ ++Function: "log10_upward": ++double: 2 ++float: 2 ++ ++Function: "log1p": ++double: 1 ++float: 1 ++ ++Function: "log1p_downward": ++double: 1 ++float: 2 ++ ++Function: "log1p_towardzero": ++double: 2 ++float: 2 ++ ++Function: "log1p_upward": ++double: 2 ++float: 2 ++ ++Function: "log2": ++double: 2 ++float: 1 ++ ++Function: "log2_downward": ++double: 1 ++float: 1 ++ ++Function: "log2_towardzero": ++double: 1 ++float: 1 ++ ++Function: "log2_upward": ++double: 1 ++float: 1 ++ ++Function: "log_downward": ++double: 1 ++float: 1 ++ ++Function: "log_towardzero": ++double: 1 ++float: 1 ++ ++Function: "log_upward": ++double: 1 ++float: 1 ++ ++Function: "pow": ++double: 1 ++ ++Function: "pow_downward": ++double: 1 ++float: 1 ++ ++Function: "pow_towardzero": ++double: 1 ++float: 1 ++ ++Function: "pow_upward": ++double: 1 ++float: 1 ++ ++Function: "sin": ++double: 1 ++float: 1 ++ ++Function: "sin_downward": ++double: 1 ++float: 1 ++ ++Function: "sin_towardzero": ++double: 1 ++float: 1 ++ ++Function: "sin_upward": ++double: 1 ++float: 1 ++ ++Function: "sincos": ++double: 1 ++float: 1 ++ ++Function: "sincos_downward": ++double: 1 ++float: 1 ++ ++Function: "sincos_towardzero": ++double: 1 ++float: 1 ++ ++Function: "sincos_upward": ++double: 1 ++float: 1 ++ ++Function: "sinh": ++double: 2 ++float: 2 ++ ++Function: "sinh_downward": ++double: 3 ++float: 3 ++ ++Function: "sinh_towardzero": ++double: 3 ++float: 2 ++ ++Function: "sinh_upward": ++double: 3 ++float: 3 ++ ++Function: "tan": ++float: 1 ++ ++Function: "tan_downward": ++double: 1 ++float: 2 ++ ++Function: "tan_towardzero": ++double: 1 ++float: 1 ++ ++Function: "tan_upward": ++double: 1 ++float: 1 ++ ++Function: "tanh": ++double: 2 ++float: 2 ++ ++Function: "tanh_downward": ++double: 3 ++float: 3 ++ ++Function: "tanh_towardzero": ++double: 2 ++float: 2 ++ ++Function: "tanh_upward": ++double: 3 ++float: 3 ++ ++Function: "tgamma": ++double: 9 ++float: 8 ++ ++Function: "tgamma_downward": ++double: 9 ++float: 7 ++ ++Function: "tgamma_towardzero": ++double: 9 ++float: 7 ++ ++Function: "tgamma_upward": ++double: 8 ++float: 8 ++ ++Function: "y0": ++double: 3 ++float: 8 ++ ++Function: "y0_downward": ++double: 3 ++float: 8 ++ ++Function: "y0_towardzero": ++double: 3 ++float: 8 ++ ++Function: "y0_upward": ++double: 2 ++float: 8 ++ ++Function: "y1": ++double: 3 ++float: 9 ++ ++Function: "y1_downward": ++double: 6 ++float: 8 ++ ++Function: "y1_towardzero": ++double: 3 ++float: 9 ++ ++Function: "y1_upward": ++double: 6 ++float: 9 ++ ++Function: "yn": ++double: 3 ++float: 3 ++ ++Function: "yn_downward": ++double: 3 ++float: 4 ++ ++Function: "yn_towardzero": ++double: 3 ++float: 3 ++ ++Function: "yn_upward": ++double: 4 ++float: 5 ++ ++# end of automatic generation +diff --git a/sysdeps/arc/arc64/fpu/libm-test-ulps-name b/sysdeps/arc/arc64/fpu/libm-test-ulps-name +new file mode 100644 +index 0000000000..8c4fba4f9a +--- /dev/null ++++ b/sysdeps/arc/arc64/fpu/libm-test-ulps-name +@@ -0,0 +1 @@ ++ARC +diff --git a/sysdeps/arc/nofpu/libm-test-ulps b/sysdeps/arc/arc64/nofpu/libm-test-ulps +similarity index 99% +copy from sysdeps/arc/nofpu/libm-test-ulps +copy to sysdeps/arc/arc64/nofpu/libm-test-ulps +index 6ac2830b25..26632ff8f2 100644 +--- a/sysdeps/arc/nofpu/libm-test-ulps ++++ b/sysdeps/arc/arc64/nofpu/libm-test-ulps +@@ -205,6 +205,7 @@ float: 7 + + Function: "hypot": + double: 1 ++float: 1 + + Function: "j0": + double: 2 +diff --git a/sysdeps/arc/arc64/nofpu/libm-test-ulps-name b/sysdeps/arc/arc64/nofpu/libm-test-ulps-name +new file mode 100644 +index 0000000000..8a9879ebd6 +--- /dev/null ++++ b/sysdeps/arc/arc64/nofpu/libm-test-ulps-name +@@ -0,0 +1 @@ ++ARC soft-float +diff --git a/sysdeps/arc/atomic-machine.h b/sysdeps/arc/atomic-machine.h +index 6ac3d87dd9..f1565b317b 100644 +--- a/sysdeps/arc/atomic-machine.h ++++ b/sysdeps/arc/atomic-machine.h +@@ -19,7 +19,23 @@ + #ifndef _ARC_BITS_ATOMIC_H + #define _ARC_BITS_ATOMIC_H 1 + +-#define __HAVE_64B_ATOMICS 0 ++#include <stdint.h> ++ ++typedef int32_t atomic32_t; ++typedef uint32_t uatomic32_t; ++typedef int64_t atomic64_t; ++typedef uint64_t uatomic64_t; ++ ++typedef intptr_t atomicptr_t; ++typedef uintptr_t uatomicptr_t; ++typedef intmax_t atomic_max_t; ++typedef uintmax_t uatomic_max_t; ++ ++# if defined(__ARC64_ARCH64__) ++# define __HAVE_64B_ATOMICS 1 ++# else ++# define __HAVE_64B_ATOMICS 0 ++# endif + #define USE_ATOMIC_COMPILER_BUILTINS 1 + + /* ARC does have legacy atomic EX reg, [mem] instruction but the micro-arch +@@ -30,15 +46,16 @@ + (abort (), 0) + #define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \ + (abort (), 0) +-#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \ +- (abort (), 0) ++ ++# if !defined(__ARC64__) ++# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \ ++ (abort (), 0) ++#endif + + #define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \ + (abort (), (__typeof (*mem)) 0) + #define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \ + (abort (), (__typeof (*mem)) 0) +-#define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ +- (abort (), (__typeof (*mem)) 0) + + #define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \ + ({ \ +@@ -48,6 +65,20 @@ + __oldval; \ + }) + ++# if defined(__ARC64__) ++# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ ++ ({ \ ++ typeof (*mem) __oldval = (oldval); \ ++ __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \ ++ model, __ATOMIC_RELAXED); \ ++ __oldval; \ ++ }) ++# else ++/* ARCv2 has LOCKD/SCOND but not sure if gcc atomic builtins exist. */ ++# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \ ++ (abort (), (__typeof (*mem)) 0) ++#endif ++ + #define atomic_compare_and_exchange_val_acq(mem, new, old) \ + __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ + mem, new, old, __ATOMIC_ACQUIRE) +diff --git a/sysdeps/arc/bits/setjmp.h b/sysdeps/arc/bits/setjmp.h +index d1604cde1f..2ca85a679d 100644 +--- a/sysdeps/arc/bits/setjmp.h ++++ b/sysdeps/arc/bits/setjmp.h +@@ -20,7 +20,11 @@ + #define _ARC_BITS_SETJMP_H 1 + + /* Saves r13-r25 (callee-saved), fp (frame pointer), sp (stack pointer), +- blink (branch-n-link). */ ++ blink (branch-n-link), FP regs. */ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++typedef long int __jmp_buf[64]; ++#else + typedef long int __jmp_buf[32]; ++#endif + + #endif +diff --git a/sysdeps/arc/configure b/sysdeps/arc/configure +index 7b27e26490..d7b19db793 100644 +--- a/sysdeps/arc/configure ++++ b/sysdeps/arc/configure +@@ -10,7 +10,7 @@ libc_cv_asm_line_sep='`' + printf "%s\n" "#define ASM_LINE_SEP $libc_cv_asm_line_sep" >>confdefs.h + + +-# For big endian ABI, generate a symbol for selecting right dynamic linker ++# For arc64:64 generate a symbol for selecting right dynamic linker + + + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +@@ -155,6 +155,77 @@ printf "%s\n" "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + ++{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for arc64" >&5 ++printf %s "checking for arc64... " >&6; } ++if test ${libc_cv_arc64+y} ++then : ++ printf %s "(cached) " >&6 ++else $as_nop ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++#ifdef __ARC64_ARCH64__ ++ yes ++ #endif ++ ++_ACEOF ++if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | ++ $EGREP "yes" >/dev/null 2>&1 ++then : ++ libc_cv_arc64=yes ++else $as_nop ++ libc_cv_arc64=no ++fi ++rm -rf conftest* ++ ++fi ++{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_arc64" >&5 ++printf "%s\n" "$libc_cv_arc64" >&6; } ++if test $libc_cv_arc64 = yes; then ++ # For shlib-versions. ++ printf "%s\n" "#define HAVE_ARC64 1" >>confdefs.h ++ ++ config_vars="$config_vars ++default-abi = arc64le" ++ ++else ++ ++# For arc64:32 generate a symbol for selecting right dynamic linker ++{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for arc32" >&5 ++printf %s "checking for arc32... " >&6; } ++if test ${libc_cv_arc32+y} ++then : ++ printf %s "(cached) " >&6 ++else $as_nop ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++#ifdef __ARC64_ARCH32__ ++ yes ++ #endif ++ ++_ACEOF ++if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | ++ $EGREP "yes" >/dev/null 2>&1 ++then : ++ libc_cv_arc32=yes ++else $as_nop ++ libc_cv_arc32=no ++fi ++rm -rf conftest* ++ ++fi ++{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_arc32" >&5 ++printf "%s\n" "$libc_cv_arc32" >&6; } ++ ++if test $libc_cv_arc32 = yes; then ++ # For shlib-versions. ++ printf "%s\n" "#define HAVE_ARC32 1" >>confdefs.h ++ ++ config_vars="$config_vars ++default-abi = arc32le" ++ ++else ++ ++# For big endian ABI, generate a symbol for selecting right dynamic linker + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for big endian" >&5 + printf %s "checking for big endian... " >&6; } + if test ${libc_cv_arc_be+y} +@@ -189,5 +260,12 @@ default-abi = arcbe" + else + config_vars="$config_vars + default-abi = arcle" ++# big endian ++fi ++ ++# arc64:32 ++fi ++ ++# arc64:64 + fi + +diff --git a/sysdeps/arc/configure.ac b/sysdeps/arc/configure.ac +index 619da4e088..4e84f17105 100644 +--- a/sysdeps/arc/configure.ac ++++ b/sysdeps/arc/configure.ac +@@ -9,6 +9,35 @@ libc_cv_have_sdata_section=no + libc_cv_asm_line_sep='`' + AC_DEFINE_UNQUOTED(ASM_LINE_SEP, $libc_cv_asm_line_sep) + ++# For arc64:64 generate a symbol for selecting right dynamic linker ++AC_CACHE_CHECK([for arc64], ++ [libc_cv_arc64], ++ [AC_EGREP_CPP(yes,[#ifdef __ARC64_ARCH64__ ++ yes ++ #endif ++ ], libc_cv_arc64=yes, libc_cv_arc64=no)]) ++if test $libc_cv_arc64 = yes; then ++ # For shlib-versions. ++ AC_DEFINE(HAVE_ARC64) ++ LIBC_CONFIG_VAR([default-abi], [arc64le]) ++ ++else ++ ++# For arc64:32 generate a symbol for selecting right dynamic linker ++AC_CACHE_CHECK([for arc32], ++ [libc_cv_arc32], ++ [AC_EGREP_CPP(yes,[#ifdef __ARC64_ARCH32__ ++ yes ++ #endif ++ ], libc_cv_arc32=yes, libc_cv_arc32=no)]) ++ ++if test $libc_cv_arc32 = yes; then ++ # For shlib-versions. ++ AC_DEFINE(HAVE_ARC32) ++ LIBC_CONFIG_VAR([default-abi], [arc32le]) ++ ++else ++ + # For big endian ABI, generate a symbol for selecting right dynamic linker + AC_CACHE_CHECK([for big endian], + [libc_cv_arc_be], +@@ -22,4 +51,11 @@ if test $libc_cv_arc_be = yes; then + LIBC_CONFIG_VAR([default-abi], [arcbe]) + else + LIBC_CONFIG_VAR([default-abi], [arcle]) ++# big endian ++fi ++ ++# arc64:32 ++fi ++ ++# arc64:64 + fi +diff --git a/sysdeps/arc/dl-machine.h b/sysdeps/arc/dl-machine.h +index 4dc652a449..dbb7394c27 100644 +--- a/sysdeps/arc/dl-machine.h ++++ b/sysdeps/arc/dl-machine.h +@@ -32,18 +32,19 @@ + #include <dl-tls.h> + #include <dl-static-tls.h> + #include <dl-machine-rel.h> ++#include <sysdep.h> + + /* Dynamic Linking ABI for ARCv2 ISA. + +- PLT ++ .plt + -------------------------------- <---- DT_PLTGOT + | ld r11, [pcl, off-to-GOT[1] | 0 + | | 4 +- plt0 | ld r10, [pcl, off-to-GOT[2] | 8 ++ PLT0 | ld r10, [pcl, off-to-GOT[2] | 8 + | | 12 + | j [r10] | 16 + -------------------------------- +- | Base address of GOT | 20 ++ | Base address of .got.plt | 20 + -------------------------------- + | ld r12, [pcl, off-to-GOT[3] | 24 + plt1 | | +@@ -69,11 +70,11 @@ + -------------- + | [1] | Module info - setup by ld.so + -------------- +- | [2] | resolver entry point ++ | [2] | resolver entry point: _dl_runtime_resolve + -------------- + | [3] | + | ... | Runtime address for function symbols +- | [f] | ++ | [f] | Initially point to PLT0 + -------------- + + For ARCompact, the PLT is 12 bytes due to short instructions +@@ -91,6 +92,8 @@ static inline int + elf_machine_matches_host (const ElfW(Ehdr) *ehdr) + { + return (ehdr->e_machine == EM_ARCV2 /* ARC HS. */ ++ || ehdr->e_machine == EM_ARCV3 /* ARCv3: ARC64. */ ++ || ehdr->e_machine == EM_ARCV3_32 /* ARCv3: ARC32. */ + || ehdr->e_machine == EM_ARC_COMPACT); /* ARC 700. */ + } + +@@ -114,7 +117,7 @@ elf_machine_load_address (void) + /* For build address, below generates + ld r0, [pcl, _GLOBAL_OFFSET_TABLE_@pcl]. */ + build_addr = elf_machine_dynamic (); +- __asm__ ("add %0, pcl, _DYNAMIC@pcl \n" : "=r" (run_addr)); ++ __asm__ ("ADDR %0, pcl, _DYNAMIC@pcl \n" : "=r" (run_addr)); + + return run_addr - build_addr; + } +@@ -131,10 +134,13 @@ elf_machine_runtime_setup (struct link_map *l, struct r_scope_elem *scope[], + + if (l->l_info[DT_JMPREL] && lazy) + { +- /* On ARC DT_PLTGOT point to .plt whose 5th word (after the PLT header) +- contains the address of .got. */ ++ /* update .got.plt[1] and .got.plt[2]. ++ DT_PLTGOT point to base of .plt and PLT0 is 3 instructions ++ for total of 20 bytes, see illustration at top. ++ The word right after contains base address of .got.plt. */ + ElfW(Addr) *plt_base = (ElfW(Addr) *) D_PTR (l, l_info[DT_PLTGOT]); +- ElfW(Addr) *got = (ElfW(Addr) *) (plt_base[5] + l->l_addr); ++ ElfW(Addr) *got_build = (ElfW(Addr) *) ((uintptr_t)plt_base + 20); ++ ElfW(Addr) *got = (ElfW(Addr) *) (*got_build + l->l_addr); + + got[1] = (ElfW(Addr)) l; /* Identify this shared object. */ + +@@ -152,6 +158,8 @@ elf_machine_runtime_setup (struct link_map *l, struct r_scope_elem *scope[], + -optionally adjusts argc for executable if exec passed as cmd + -calls into app main with address of finaliser. */ + ++#ifdef __ARC64_ARCH64__ ++ + #define RTLD_START asm ("\ + .text \n\ + .globl __start \n\ +@@ -159,25 +167,55 @@ elf_machine_runtime_setup (struct link_map *l, struct r_scope_elem *scope[], + __start: \n\ + /* (1). bootstrap ld.so. */ \n\ + bl.d _dl_start \n\ +- mov_s r0, sp /* pass ptr to aux vector tbl. */ \n\ +- mov r13, r0 /* safekeep app elf entry point. */ \n\ +- ld_s r1, [sp] /* orig argc. */ \n\ ++ MOVR r0, sp /* pass ptr to aux vector tbl. */ \n\ ++ MOVR r14, r0 /* safekeep app elf entry point. */ \n\ ++ LDR r1, sp /* orig argc. */ \n\ + \n\ + /* (2). call preinit stuff. */ \n\ +- ld r0, [pcl, _rtld_local@pcl] \n\ +- add r2, sp, 4 ; argv \n\ +- add2 r3, r2, r1 \n\ +- add r3, r3, 4 ; env \n\ ++ LDR r0, pcl, _rtld_local@pcl \n\ ++ ADDR r2, sp, 8 ; argv \n\ ++ ADD3R r3, r2, r1 \n\ ++ ADDR r3, r3, 8 ; env \n\ + bl _dl_init@plt \n\ + \n\ + /* (3) call app elf entry point. */ \n\ +- add r0, pcl, _dl_fini@pcl \n\ +- j [r13] \n\ ++ ADDR r0, pcl, _dl_fini@pcl \n\ ++ j [r14] \n\ + \n\ + .size __start,.-__start \n\ + .previous \n\ + "); + ++#else ++ ++#define RTLD_START asm ("\ ++.text \n\ ++.globl __start \n\ ++.type __start, @function \n\ ++__start: \n\ ++ /* (1). bootstrap ld.so. */ \n\ ++ bl.d _dl_start \n\ ++ MOVR r0, sp /* pass ptr to aux vector tbl. */ \n\ ++ MOVR r14, r0 /* safekeep app elf entry point. */ \n\ ++ LDR r1, sp /* orig argc. */ \n\ ++ \n\ ++ /* (2). call preinit stuff. */ \n\ ++ LDR r0, pcl, _rtld_local@pcl \n\ ++ ADDR r2, sp, 4 ; argv \n\ ++ ADD2R r3, r2, r1 \n\ ++ ADDR r3, r3, 4 ; env \n\ ++ bl _dl_init@plt \n\ ++ \n\ ++ /* (3) call app elf entry point. */ \n\ ++ ADDR r0, pcl, _dl_fini@pcl \n\ ++ j [r14] \n\ ++ \n\ ++ .size __start,.-__start \n\ ++ .previous \n\ ++"); ++ ++#endif ++ + /* ELF_RTYPE_CLASS_PLT iff TYPE describes relocation of a PLT entry, so + PLT entries should not be allowed to define the value. + ELF_RTYPE_CLASS_NOCOPY iff TYPE should not be allowed to resolve to one +@@ -289,6 +327,7 @@ elf_machine_rela (struct link_map *map, struct r_scope_elem *scope[], + break; + + case R_ARC_32: ++ case R_ARC_64: + *reloc_addr += value + reloc->r_addend; + break; + +diff --git a/sysdeps/arc/dl-trampoline.S b/sysdeps/arc/dl-trampoline.S +index 1b307a616f..386009d41e 100644 +--- a/sysdeps/arc/dl-trampoline.S ++++ b/sysdeps/arc/dl-trampoline.S +@@ -31,42 +31,71 @@ + ENTRY (_dl_runtime_resolve) + + /* save args to func being resolved before entering resolver. */ +- push_s r0 +- push_s r1 +- push_s r2 +- push_s r3 +- st.a r4, [sp, -4] +- st.a r5, [sp, -4] +- st.a r6, [sp, -4] +- st.a r7, [sp, -4] +- st.a r8, [sp, -4] +- st.a r9, [sp, -4] +- cfi_adjust_cfa_offset (40) +- push_s blink +- cfi_adjust_cfa_offset (4) ++ PUSHR r0 ++ PUSHR r1 ++ PUSHR r2 ++ PUSHR r3 ++ PUSHR r4 ++ PUSHR r5 ++ PUSHR r6 ++ PUSHR r7 ++ PUSHR r8 ++ PUSHR r9 ++ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FPUSHR f0 ++ FPUSHR f1 ++ FPUSHR f2 ++ FPUSHR f3 ++ FPUSHR f4 ++ FPUSHR f5 ++ FPUSHR f6 ++ FPUSHR f7 ++ cfi_adjust_cfa_offset (18*REGSZ) ++#else ++ cfi_adjust_cfa_offset (10*REGSZ) ++#endif ++ ++ PUSHR blink ++ cfi_adjust_cfa_offset (REGSZ) + cfi_rel_offset (blink, 0) + +- mov_s r1, r12 ++ MOVR r1, r12 + bl.d _dl_fixup +- mov r0, r11 ++ MOVR r0, r11 + + /* restore regs back. */ +- ld.ab blink,[sp, 4] +- cfi_adjust_cfa_offset (-4) ++ POPR blink ++ cfi_adjust_cfa_offset (-REGSZ) + cfi_restore (blink) +- ld.ab r9, [sp, 4] +- ld.ab r8, [sp, 4] +- ld.ab r7, [sp, 4] +- ld.ab r6, [sp, 4] +- ld.ab r5, [sp, 4] +- ld.ab r4, [sp, 4] +- pop_s r3 +- pop_s r2 +- pop_s r1 +- cfi_adjust_cfa_offset (-36) + +- j_s.d [r0] /* r0 has resolved function addr. */ +- pop_s r0 /* restore first arg to resolved call. */ +- cfi_adjust_cfa_offset (-4) ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FPOPR f7 ++ FPOPR f6 ++ FPOPR f5 ++ FPOPR f4 ++ FPOPR f3 ++ FPOPR f2 ++ FPOPR f1 ++ FPOPR f0 ++#endif ++ POPR r9 ++ POPR r8 ++ POPR r7 ++ POPR r6 ++ POPR r5 ++ POPR r4 ++ POPR r3 ++ POPR r2 ++ POPR r1 ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ cfi_adjust_cfa_offset (-17*REGSZ) ++#else ++ cfi_adjust_cfa_offset (-9*REGSZ) ++#endif ++ ++ j.d [r0] /* r0 has resolved function addr. */ ++ POPR r0 /* restore first arg to resolved call. */ ++ cfi_adjust_cfa_offset (-REGSZ) + cfi_restore (r0) + END (_dl_runtime_resolve) +diff --git a/sysdeps/arc/fpu/math-use-builtins-fma.h b/sysdeps/arc/fpu/math-use-builtins-fma.h +index 2acd8113ce..59c7ed0343 100644 +--- a/sysdeps/arc/fpu/math-use-builtins-fma.h ++++ b/sysdeps/arc/fpu/math-use-builtins-fma.h +@@ -1,13 +1,17 @@ +-#if defined __ARC_FPU_DP_FMA__ ++#if defined __ARCV3__ + # define USE_FMA_BUILTIN 1 +-#else +-# define USE_FMA_BUILTIN 0 +-#endif +- +-#if defined __ARC_FPU_SP_FMA__ + # define USE_FMAF_BUILTIN 1 + #else +-# define USE_FMAF_BUILTIN 0 ++# if defined __ARC_FPU_DP_FMA__ ++# define USE_FMA_BUILTIN 1 ++# else ++# define USE_FMA_BUILTIN 0 ++# endif ++# if defined __ARC_FPU_SP_FMA__ ++# define USE_FMAF_BUILTIN 1 ++# else ++# define USE_FMAF_BUILTIN 0 ++# endif + #endif + + #define USE_FMAL_BUILTIN 0 +diff --git a/sysdeps/arc/fpu/math-use-builtins-sqrt.h b/sysdeps/arc/fpu/math-use-builtins-sqrt.h +index a449bc6092..40a07730ea 100644 +--- a/sysdeps/arc/fpu/math-use-builtins-sqrt.h ++++ b/sysdeps/arc/fpu/math-use-builtins-sqrt.h +@@ -1,13 +1,17 @@ +-#if defined __ARC_FPU_DP_DIV__ ++#if defined __ARCV3__ + # define USE_SQRT_BUILTIN 1 +-#else +-# define USE_SQRT_BUILTIN 0 +-#endif +- +-#if defined __ARC_FPU_SP_DIV__ + # define USE_SQRTF_BUILTIN 1 + #else +-# define USE_SQRTF_BUILTIN 0 ++# if defined __ARC_FPU_DP_DIV__ ++# define USE_SQRT_BUILTIN 1 ++# else ++# define USE_SQRT_BUILTIN 0 ++# endif ++# if defined __ARC_FPU_SP_DIV__ ++# define USE_SQRTF_BUILTIN 1 ++# else ++# define USE_SQRTF_BUILTIN 0 ++# endif + #endif + + #define USE_SQRTL_BUILTIN 0 +diff --git a/sysdeps/arc/isa-asm-macro-32.h b/sysdeps/arc/isa-asm-macro-32.h +new file mode 100644 +index 0000000000..98cd249059 +--- /dev/null ++++ b/sysdeps/arc/isa-asm-macro-32.h +@@ -0,0 +1,61 @@ ++# define REGSZ 4 ++ ++.irp aa,,.as ++.macro LDR\aa d, s, off=0 ++ ld\aa \d, [\s, \off] ++.endm ++.endr ++ ++.irp aa,,.as ++.macro STR\aa d, s, off=0 ++ st\aa \d, [\s, \off] ++.endm ++.endr ++ ++.macro PUSHR r ++ push \r ++.endm ++ ++.macro POPR r ++ pop \r ++.endm ++ ++.irp cc,,.f ++.macro MOVR\cc d, s ++ mov\cc \d, \s ++.endm ++.endr ++ ++.irp cc,,.nz ++.macro ADDR\cc d, s, v ++ add\cc \d, \s, \v ++.endm ++.endr ++ ++.macro ADD2R d, s, v ++ add2 \d, \s, \v ++.endm ++ ++.macro ADD3R d, s, v ++ add3 \d, \s, \v ++.endm ++ ++.macro SUBR d, s, v ++ sub \d, \s, \v ++.endm ++ ++.macro ANDR d, s, v ++ and \d, \s, \v ++.endm ++ ++.irp cc,,eq,hi ++.macro BRR\cc d, s, v ++ br\cc \d, \s, \v ++.endm ++.endr ++ ++.irp cc,,.ne ++.macro CMPR\cc d, s ++ cmp\cc \d, \s ++.endm ++.endr +diff --git a/sysdeps/arc/isa-asm-macro-64.h b/sysdeps/arc/isa-asm-macro-64.h +new file mode 100644 +index 0000000000..02b1dc2c37 +--- /dev/null ++++ b/sysdeps/arc/isa-asm-macro-64.h +@@ -0,0 +1,86 @@ ++# define REGSZ 8 ++ ++.irp aa,,.as ++.macro LDR\aa d, s, off=0 ++ ldl\aa \d, [\s, \off] ++.endm ++.endr ++ ++.irp aa,,.as ++.macro STR\aa d, s, off=0 ++ stl\aa \d, [\s, \off] ++.endm ++.endr ++ ++.macro PUSHR r ++ pushl \r ++.endm ++ ++.macro POPR r ++ popl \r ++.endm ++ ++.irp cc,,.f ++.macro MOVR\cc d, s ++ movl\cc \d, \s ++.endm ++.endr ++ ++.irp cc,,.nz ++.macro ADDR\cc d, s, v ++ addl\cc \d, \s, \v ++.endm ++.endr ++ ++.macro ADD2R d, s, v ++ add2l \d, \s, \v ++.endm ++ ++.macro ADD3R d, s, v ++ add3l \d, \s, \v ++.endm ++ ++.macro SUBR d, s, v ++ subl \d, \s, \v ++.endm ++ ++.macro ANDR d, s, v ++ andl \d, \s, \v ++.endm ++ ++.irp cc,eq,hi ++.macro BRR\cc d, s, v ++; arc64 gas doesn't support BRHIL pseudo-instruction ++.ifeqs "\cc","hi" ++ brlo\()l \s, \d, \v ++.else ++ br\cc\()l \d, \s, \v ++.endif ++.endm ++.endr ++ ++.irp cc,,.ne ++.macro CMPR\cc d, s ++ cmpl\cc \d, \s ++.endm ++.endr ++ ++.irp aa,,.as,.aw,.ab ++.macro FLDR\aa d, s, off=0 ++ fld64\aa \d, [\s, \off] ++.endm ++.endr ++ ++.irp aa,,.as,.aw,.ab ++.macro FSTR\aa d, s, off=0 ++ fst64\aa \d, [\s, \off] ++.endm ++.endr ++ ++.macro FPUSHR r ++ FSTR.aw \r, sp, -REGSZ ++.endm ++ ++.macro FPOPR r ++ FLDR.ab \r, sp, REGSZ ++.endm +diff --git a/sysdeps/arc/isa-asm-macros.h b/sysdeps/arc/isa-asm-macros.h +new file mode 100644 +index 0000000000..f9f5e4f630 +--- /dev/null ++++ b/sysdeps/arc/isa-asm-macros.h +@@ -0,0 +1,35 @@ ++/* ISA Specific Assembler macros for ARC. ++ Copyright (C) 2020 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public License as ++ published by the Free Software Foundation; either version 2.1 of the ++ License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ <https://www.gnu.org/licenses/>. */ ++ ++#ifdef __ASSEMBLER__ ++ ++# ifdef __ARC64_ARCH64__ ++# include <sysdeps/arc/isa-asm-macro-64.h> ++# else ++# include <sysdeps/arc/isa-asm-macro-32.h> ++# endif ++ ++#else ++ ++# ifdef __ARC64_ARCH64__ ++asm(".include \"sysdeps/arc/isa-asm-macro-64.h\"\n"); ++# else ++asm(".include \"sysdeps/arc/isa-asm-macro-32.h\"\n"); ++# endif ++ ++#endif +diff --git a/sysdeps/arc/nofpu/libm-test-ulps b/sysdeps/arc/nofpu/libm-test-ulps +index 6ac2830b25..26632ff8f2 100644 +--- a/sysdeps/arc/nofpu/libm-test-ulps ++++ b/sysdeps/arc/nofpu/libm-test-ulps +@@ -205,6 +205,7 @@ float: 7 + + Function: "hypot": + double: 1 ++float: 1 + + Function: "j0": + double: 2 +diff --git a/sysdeps/arc/nptl/pthreaddef.h b/sysdeps/arc/nptl/pthreaddef.h +index 336eded15c..3b51e59a35 100644 +--- a/sysdeps/arc/nptl/pthreaddef.h ++++ b/sysdeps/arc/nptl/pthreaddef.h +@@ -23,7 +23,7 @@ + #define ARCH_MIN_GUARD_SIZE 0 + + /* Required stack pointer alignment at beginning. */ +-#define STACK_ALIGN 4 ++#define STACK_ALIGN 8 + + /* Minimal stack size after allocating thread descriptor and guard size. */ + #define MINIMAL_REST_STACK 2048 +diff --git a/sysdeps/arc/preconfigure b/sysdeps/arc/preconfigure +index a79db0239a..eab4af0eab 100644 +--- a/sysdeps/arc/preconfigure ++++ b/sysdeps/arc/preconfigure +@@ -1,14 +1,22 @@ + case "$machine" in + arc*) +- base_machine=arc +- machine=arc ++ with_fp_cond=0 ++ isarc64=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep __LP64__| wc -l` ++ ++ case "$isarc64" in ++ 0) ++ base_machine=arc ++ machine=arc/arc32 ++ ;; ++ 1) ++ base_machine=arc ++ machine=arc/arc64 ++ ;; ++ esac + + gccfloat=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep __ARC_FPU_| wc -l` + if test "$gccfloat" != "0"; then + with_fp_cond=1 +- else +- with_fp_cond=0 + fi + ;; +- + esac +diff --git a/sysdeps/arc/setjmp.S b/sysdeps/arc/setjmp.S +index 9ecdb9daae..e39b526837 100644 +--- a/sysdeps/arc/setjmp.S ++++ b/sysdeps/arc/setjmp.S +@@ -41,24 +41,47 @@ ENTRY (__sigsetjmp) + that will be right next to this setjmp call-site in BLINK + since "C" caller of this routine will do a branch-n-link. */ + +- STR (blink, r0, 0) +- STR (sp, r0, 1) +- STR (fp, r0, 2) +- STR (gp, r0, 3) ++ STR.as blink, r0, 0 ++ STR.as sp, r0, 1 ++ STR.as fp, r0, 2 ++ STR.as gp, r0, 3 + +- STR (r13, r0, 4) +- STR (r14, r0, 5) +- STR (r15, r0, 6) +- STR (r16, r0, 7) +- STR (r17, r0, 8) +- STR (r18, r0, 9) +- STR (r19, r0, 10) +- STR (r20, r0, 11) +- STR (r21, r0, 12) +- STR (r22, r0, 13) +- STR (r23, r0, 14) +- STR (r24, r0, 15) ++ STR.as r13, r0, 4 ++ STR.as r14, r0, 5 ++ STR.as r15, r0, 6 ++ STR.as r16, r0, 7 ++ STR.as r17, r0, 8 ++ STR.as r18, r0, 9 ++ STR.as r19, r0, 10 ++ STR.as r20, r0, 11 ++ STR.as r21, r0, 12 ++ STR.as r22, r0, 13 ++ STR.as r23, r0, 14 ++ STR.as r24, r0, 15 + ++#if defined(__ARCV3__) ++ STR.as r25, r0, 16 ++ STR.as r26, r0, 17 ++#endif ++ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FSTR.as f16, r0, 18 ++ FSTR.as f17, r0, 19 ++ FSTR.as f18, r0, 20 ++ FSTR.as f19, r0, 21 ++ FSTR.as f20, r0, 22 ++ FSTR.as f21, r0, 23 ++ FSTR.as f22, r0, 24 ++ FSTR.as f23, r0, 25 ++ FSTR.as f24, r0, 26 ++ FSTR.as f25, r0, 27 ++ FSTR.as f26, r0, 28 ++ FSTR.as f27, r0, 29 ++ FSTR.as f28, r0, 30 ++ FSTR.as f29, r0, 31 ++ FSTR.as f30, r0, 32 ++ FSTR.as f31, r0, 33 ++#endif + b __sigjmp_save + + END (__sigsetjmp) +diff --git a/sysdeps/arc/sfp-machine.h b/sysdeps/arc/sfp-machine.h +index 0917a7ae17..4743b694a2 100644 +--- a/sysdeps/arc/sfp-machine.h ++++ b/sysdeps/arc/sfp-machine.h +@@ -17,10 +17,12 @@ + <https://www.gnu.org/licenses/>. */ + + +-#define _FP_W_TYPE_SIZE 32 +-#define _FP_W_TYPE unsigned long +-#define _FP_WS_TYPE signed long +-#define _FP_I_TYPE long ++#ifndef __ARC64__ ++ ++# define _FP_W_TYPE_SIZE 32 ++# define _FP_W_TYPE unsigned long ++# define _FP_WS_TYPE signed long ++# define _FP_I_TYPE long + + #define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +@@ -67,4 +69,49 @@ + R##_c = FP_CLS_NAN; \ + } while (0) + ++#else ++ ++# define _FP_W_TYPE_SIZE 64 ++# define _FP_W_TYPE unsigned long long ++# define _FP_WS_TYPE signed long long ++# define _FP_I_TYPE long long ++ ++# define _FP_MUL_MEAT_S(R, X, Y) \ ++ _FP_MUL_MEAT_1_imm (_FP_WFRACBITS_S, R, X, Y) ++# define _FP_MUL_MEAT_D(R, X, Y) \ ++ _FP_MUL_MEAT_1_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) ++# define _FP_MUL_MEAT_Q(R, X, Y) \ ++ _FP_MUL_MEAT_2_wide_3mul (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) ++ ++# define _FP_MUL_MEAT_DW_S(R, X, Y) \ ++ _FP_MUL_MEAT_DW_1_imm (_FP_WFRACBITS_S, R, X, Y) ++# define _FP_MUL_MEAT_DW_D(R, X, Y) \ ++ _FP_MUL_MEAT_DW_1_wide (_FP_WFRACBITS_D, R, X, Y, umul_ppmm) ++# define _FP_MUL_MEAT_DW_Q(R, X, Y) \ ++ _FP_MUL_MEAT_DW_2_wide_3mul (_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) ++ ++# define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_imm (S, R, X, Y, _FP_DIV_HELP_imm) ++# define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_1_udiv_norm (D, R, X, Y) ++# define _FP_DIV_MEAT_Q(R, X, Y) _FP_DIV_MEAT_2_udiv (Q, R, X, Y) ++ ++# define _FP_NANFRAC_S _FP_QNANBIT_S ++# define _FP_NANFRAC_D _FP_QNANBIT_D ++# define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0 ++ ++#define _FP_NANSIGN_S 0 ++#define _FP_NANSIGN_D 0 ++#define _FP_NANSIGN_Q 0 ++ ++#define _FP_KEEPNANFRACP 0 ++#define _FP_QNANNEGATEDP 0 ++ ++#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ ++ do { \ ++ R##_s = _FP_NANSIGN_##fs; \ ++ _FP_FRAC_SET_##wc (R, _FP_NANFRAC_##fs); \ ++ R##_c = FP_CLS_NAN; \ ++ } while (0) ++ ++#endif ++ + #define _FP_TININESS_AFTER_ROUNDING 1 +diff --git a/sysdeps/arc/start.S b/sysdeps/arc/start.S +index db3bab6395..42ead9d302 100644 +--- a/sysdeps/arc/start.S ++++ b/sysdeps/arc/start.S +@@ -57,12 +57,12 @@ ENTRY (ENTRY_POINT) + cfi_undefined (blink) + + mov fp, 0 +- ld_s r1, [sp] /* argc. */ ++ LDR r1, sp /* argc. */ + +- mov_s r5, r0 /* rltd_fini. */ +- add_s r2, sp, 4 /* argv. */ +- and sp, sp, -8 +- mov r6, sp ++ MOVR r5, r0 /* rltd_fini. */ ++ ADDR r2, sp, REGSZ /* argv. */ ++ ANDR sp, sp, -2*REGSZ ++ MOVR r6, sp + + /* __libc_start_main (main, argc, argv, init, fini, rtld_fini, stack_end). */ + +@@ -70,10 +70,10 @@ ENTRY (ENTRY_POINT) + mov r4, 0 /* Used to be fini. */ + + #ifdef SHARED +- ld r0, [pcl, @main@gotpc] ++ LDR r0, pcl, @main@gotpc + bl __libc_start_main@plt + #else +- mov_s r0, main ++ MOVR r0, main + bl __libc_start_main + #endif + +diff --git a/sysdeps/arc/sysdep.h b/sysdeps/arc/sysdep.h +index 4f024f6b73..ba6ecddbac 100644 +--- a/sysdeps/arc/sysdep.h ++++ b/sysdeps/arc/sysdep.h +@@ -47,7 +47,6 @@ + + # define CALL_MCOUNT /* Do nothing for now. */ + +-# define STR(reg, rbase, off) st reg, [rbase, off * 4] +-# define LDR(reg, rbase, off) ld reg, [rbase, off * 4] +- + #endif /* __ASSEMBLER__ */ ++ ++#include <sysdeps/arc/isa-asm-macros.h> +diff --git a/sysdeps/unix/sysv/linux/arc/Makefile b/sysdeps/unix/sysv/linux/arc/Makefile +index eca9a9fd3a..00d655bcd3 100644 +--- a/sysdeps/unix/sysv/linux/arc/Makefile ++++ b/sysdeps/unix/sysv/linux/arc/Makefile +@@ -12,11 +12,13 @@ sysdep_headers += sys/cachectl.h + sysdep_routines += cacheflush + endif + +-abi-variants := arcle arcbe ++abi-variants := arcle arcbe arc32le arc64le + + ifeq (,$(filter $(default-abi),$(abi-variants))) + $(error Unknown ABI $(default-abi), must be one of $(abi-variants)) + endif + +-abi-arcle-condition := !defined __BIG_ENDIAN__ +-abi-arcbe-condition := defined __BIG_ENDIAN__ ++abi-arcle-condition := !defined __ARC64__ && !defined __BIG_ENDIAN__ ++abi-arcbe-condition := !defined __ARC64__ && defined __BIG_ENDIAN__ ++abi-arc32le-condition := defined __ARC64_ARCH32__ && !defined __BIG_ENDIAN__ ++abi-arc64le-condition := defined __ARC64_ARCH64__ && !defined __BIG_ENDIAN__ +diff --git a/sysdeps/unix/sysv/linux/arc/arc32/Implies b/sysdeps/unix/sysv/linux/arc/arc32/Implies +new file mode 100644 +index 0000000000..9670973cfa +--- /dev/null ++++ b/sysdeps/unix/sysv/linux/arc/arc32/Implies +@@ -0,0 +1 @@ ++unix/sysv/linux/arc +diff --git a/sysdeps/unix/sysv/linux/arc/arch-syscall.h b/sysdeps/unix/sysv/linux/arc/arc32/arch-syscall.h +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/arch-syscall.h +copy to sysdeps/unix/sysv/linux/arc/arc32/arch-syscall.h +diff --git a/sysdeps/unix/sysv/linux/arc/c++-types.data b/sysdeps/unix/sysv/linux/arc/arc32/c++-types.data +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/c++-types.data +copy to sysdeps/unix/sysv/linux/arc/arc32/c++-types.data +diff --git a/sysdeps/unix/sysv/linux/arc/fixup-asm-unistd.h b/sysdeps/unix/sysv/linux/arc/arc32/fixup-asm-unistd.h +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/fixup-asm-unistd.h +rename to sysdeps/unix/sysv/linux/arc/arc32/fixup-asm-unistd.h +diff --git a/sysdeps/unix/sysv/linux/arc/ld.abilist b/sysdeps/unix/sysv/linux/arc/arc32/ld.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/ld.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/ld.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libBrokenLocale.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libBrokenLocale.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libBrokenLocale.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libBrokenLocale.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libanl.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libanl.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libanl.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libanl.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libc.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libc.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libc.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libc.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libc_malloc_debug.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libc_malloc_debug.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libc_malloc_debug.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libc_malloc_debug.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libcrypt.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libcrypt.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libcrypt.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libcrypt.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libdl.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libdl.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libdl.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libdl.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libm.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libm.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libm.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libm.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libpthread.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libpthread.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libpthread.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libpthread.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libresolv.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libresolv.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libresolv.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libresolv.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/librt.abilist b/sysdeps/unix/sysv/linux/arc/arc32/librt.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/librt.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/librt.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libthread_db.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libthread_db.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libthread_db.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libthread_db.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libutil.abilist b/sysdeps/unix/sysv/linux/arc/arc32/libutil.abilist +similarity index 100% +copy from sysdeps/unix/sysv/linux/arc/libutil.abilist +copy to sysdeps/unix/sysv/linux/arc/arc32/libutil.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/arc64/Implies b/sysdeps/unix/sysv/linux/arc/arc64/Implies +new file mode 100644 +index 0000000000..05abf4461a +--- /dev/null ++++ b/sysdeps/unix/sysv/linux/arc/arc64/Implies +@@ -0,0 +1,2 @@ ++unix/sysv/linux/arc ++unix/sysv/linux/wordsize-64 +diff --git a/sysdeps/unix/sysv/linux/arc/arch-syscall.h b/sysdeps/unix/sysv/linux/arc/arc64/arch-syscall.h +similarity index 89% +rename from sysdeps/unix/sysv/linux/arc/arch-syscall.h +rename to sysdeps/unix/sysv/linux/arc/arc64/arch-syscall.h +index c1207aaa12..c73f38e567 100644 +--- a/sysdeps/unix/sysv/linux/arc/arch-syscall.h ++++ b/sysdeps/unix/sysv/linux/arc/arc64/arch-syscall.h +@@ -15,11 +15,11 @@ + #define __NR_capset 91 + #define __NR_chdir 49 + #define __NR_chroot 51 +-#define __NR_clock_adjtime64 405 +-#define __NR_clock_getres_time64 406 +-#define __NR_clock_gettime64 403 +-#define __NR_clock_nanosleep_time64 407 +-#define __NR_clock_settime64 404 ++#define __NR_clock_adjtime 266 ++#define __NR_clock_getres 114 ++#define __NR_clock_gettime 113 ++#define __NR_clock_nanosleep 115 ++#define __NR_clock_settime 112 + #define __NR_clone 220 + #define __NR_clone3 435 + #define __NR_close 57 +@@ -40,7 +40,7 @@ + #define __NR_exit_group 94 + #define __NR_faccessat 48 + #define __NR_faccessat2 439 +-#define __NR_fadvise64_64 223 ++#define __NR_fadvise64 223 + #define __NR_fallocate 47 + #define __NR_fanotify_init 262 + #define __NR_fanotify_mark 263 +@@ -49,7 +49,7 @@ + #define __NR_fchmodat 53 + #define __NR_fchown 55 + #define __NR_fchownat 54 +-#define __NR_fcntl64 25 ++#define __NR_fcntl 25 + #define __NR_fdatasync 83 + #define __NR_fgetxattr 10 + #define __NR_finit_module 273 +@@ -61,10 +61,11 @@ + #define __NR_fsmount 432 + #define __NR_fsopen 430 + #define __NR_fspick 433 +-#define __NR_fstatfs64 44 ++#define __NR_fstat 80 ++#define __NR_fstatfs 44 + #define __NR_fsync 82 +-#define __NR_ftruncate64 46 +-#define __NR_futex_time64 422 ++#define __NR_ftruncate 46 ++#define __NR_futex 98 + #define __NR_futex_waitv 449 + #define __NR_get_mempolicy 236 + #define __NR_get_robust_list 100 +@@ -101,7 +102,6 @@ + #define __NR_io_destroy 1 + #define __NR_io_getevents 4 + #define __NR_io_pgetevents 292 +-#define __NR_io_pgetevents_time64 416 + #define __NR_io_setup 0 + #define __NR_io_submit 2 + #define __NR_io_uring_enter 426 +@@ -123,9 +123,9 @@ + #define __NR_listen 201 + #define __NR_listxattr 11 + #define __NR_llistxattr 12 +-#define __NR_llseek 62 + #define __NR_lookup_dcookie 18 + #define __NR_lremovexattr 15 ++#define __NR_lseek 62 + #define __NR_lsetxattr 6 + #define __NR_madvise 233 + #define __NR_mbind 235 +@@ -138,7 +138,7 @@ + #define __NR_mlock 228 + #define __NR_mlock2 284 + #define __NR_mlockall 230 +-#define __NR_mmap2 222 ++#define __NR_mmap 222 + #define __NR_mount 40 + #define __NR_mount_setattr 442 + #define __NR_move_mount 429 +@@ -147,8 +147,8 @@ + #define __NR_mq_getsetattr 185 + #define __NR_mq_notify 184 + #define __NR_mq_open 180 +-#define __NR_mq_timedreceive_time64 419 +-#define __NR_mq_timedsend_time64 418 ++#define __NR_mq_timedreceive 183 ++#define __NR_mq_timedsend 182 + #define __NR_mq_unlink 181 + #define __NR_mremap 216 + #define __NR_msgctl 187 +@@ -161,6 +161,7 @@ + #define __NR_munmap 215 + #define __NR_name_to_handle_at 264 + #define __NR_nanosleep 101 ++#define __NR_newfstatat 79 + #define __NR_nfsservctl 42 + #define __NR_open_by_handle_at 265 + #define __NR_open_tree 428 +@@ -176,7 +177,7 @@ + #define __NR_pkey_alloc 289 + #define __NR_pkey_free 290 + #define __NR_pkey_mprotect 288 +-#define __NR_ppoll_time64 414 ++#define __NR_ppoll 73 + #define __NR_prctl 167 + #define __NR_pread64 67 + #define __NR_preadv 69 +@@ -186,7 +187,7 @@ + #define __NR_process_mrelease 448 + #define __NR_process_vm_readv 270 + #define __NR_process_vm_writev 271 +-#define __NR_pselect6_time64 413 ++#define __NR_pselect6 72 + #define __NR_ptrace 117 + #define __NR_pwrite64 68 + #define __NR_pwritev 70 +@@ -199,7 +200,7 @@ + #define __NR_readv 65 + #define __NR_reboot 142 + #define __NR_recvfrom 207 +-#define __NR_recvmmsg_time64 417 ++#define __NR_recvmmsg 243 + #define __NR_recvmsg 212 + #define __NR_remap_file_pages 234 + #define __NR_removexattr 14 +@@ -214,7 +215,7 @@ + #define __NR_rt_sigqueueinfo 138 + #define __NR_rt_sigreturn 139 + #define __NR_rt_sigsuspend 133 +-#define __NR_rt_sigtimedwait_time64 421 ++#define __NR_rt_sigtimedwait 137 + #define __NR_rt_tgsigqueueinfo 240 + #define __NR_sched_get_priority_max 125 + #define __NR_sched_get_priority_min 126 +@@ -222,7 +223,7 @@ + #define __NR_sched_getattr 275 + #define __NR_sched_getparam 121 + #define __NR_sched_getscheduler 120 +-#define __NR_sched_rr_get_interval_time64 423 ++#define __NR_sched_rr_get_interval 127 + #define __NR_sched_setaffinity 122 + #define __NR_sched_setattr 274 + #define __NR_sched_setparam 118 +@@ -232,8 +233,8 @@ + #define __NR_semctl 191 + #define __NR_semget 190 + #define __NR_semop 193 +-#define __NR_semtimedop_time64 420 +-#define __NR_sendfile64 71 ++#define __NR_semtimedop 192 ++#define __NR_sendfile 71 + #define __NR_sendmmsg 269 + #define __NR_sendmsg 211 + #define __NR_sendto 206 +@@ -271,7 +272,7 @@ + #define __NR_socket 198 + #define __NR_socketpair 199 + #define __NR_splice 76 +-#define __NR_statfs64 43 ++#define __NR_statfs 43 + #define __NR_statx 291 + #define __NR_swapoff 225 + #define __NR_swapon 224 +@@ -287,21 +288,21 @@ + #define __NR_timer_create 107 + #define __NR_timer_delete 111 + #define __NR_timer_getoverrun 109 +-#define __NR_timer_gettime64 408 +-#define __NR_timer_settime64 409 ++#define __NR_timer_gettime 108 ++#define __NR_timer_settime 110 + #define __NR_timerfd_create 85 +-#define __NR_timerfd_gettime64 410 +-#define __NR_timerfd_settime64 411 ++#define __NR_timerfd_gettime 87 ++#define __NR_timerfd_settime 86 + #define __NR_times 153 + #define __NR_tkill 130 +-#define __NR_truncate64 45 ++#define __NR_truncate 45 + #define __NR_umask 166 + #define __NR_umount2 39 + #define __NR_uname 160 + #define __NR_unlinkat 35 + #define __NR_unshare 97 + #define __NR_userfaultfd 282 +-#define __NR_utimensat_time64 412 ++#define __NR_utimensat 88 + #define __NR_vhangup 58 + #define __NR_vmsplice 75 + #define __NR_wait4 260 +diff --git a/sysdeps/unix/sysv/linux/arc/c++-types.data b/sysdeps/unix/sysv/linux/arc/arc64/c++-types.data +similarity index 73% +rename from sysdeps/unix/sysv/linux/arc/c++-types.data +rename to sysdeps/unix/sysv/linux/arc/arc64/c++-types.data +index 0fb0143ae7..ac925ccb36 100644 +--- a/sysdeps/unix/sysv/linux/arc/c++-types.data ++++ b/sysdeps/unix/sysv/linux/arc/arc64/c++-types.data +@@ -1,32 +1,32 @@ +-blkcnt64_t:x +-blkcnt_t:x ++blkcnt64_t:l ++blkcnt_t:l + blksize_t:i + caddr_t:Pc + clockid_t:i + clock_t:l + daddr_t:i +-dev_t:y ++dev_t:m + fd_mask:l +-fsblkcnt64_t:y +-fsblkcnt_t:y +-fsfilcnt64_t:y +-fsfilcnt_t:y ++fsblkcnt64_t:m ++fsblkcnt_t:m ++fsfilcnt64_t:m ++fsfilcnt_t:m + fsid_t:8__fsid_t + gid_t:j + id_t:j +-ino64_t:y +-ino_t:y ++ino64_t:m ++ino_t:m + int16_t:s + int32_t:i +-int64_t:x ++int64_t:l + int8_t:a +-intptr_t:i ++intptr_t:l + key_t:i +-loff_t:x ++loff_t:l + mode_t:j + nlink_t:j +-off64_t:x +-off_t:x ++off64_t:l ++off_t:l + pid_t:i + pthread_attr_t:14pthread_attr_t + pthread_barrier_t:17pthread_barrier_t +@@ -41,27 +41,27 @@ pthread_rwlock_t:16pthread_rwlock_t + pthread_rwlockattr_t:20pthread_rwlockattr_t + pthread_spinlock_t:i + pthread_t:m +-quad_t:x +-register_t:i +-rlim64_t:y +-rlim_t:y ++quad_t:l ++register_t:l ++rlim64_t:m ++rlim_t:m + sigset_t:10__sigset_t +-size_t:j ++size_t:m + socklen_t:j +-ssize_t:i +-suseconds_t:x +-time_t:x ++ssize_t:l ++suseconds_t:l ++time_t:l + u_char:h + uid_t:j + uint:j + u_int:j + u_int16_t:t + u_int32_t:j +-u_int64_t:y ++u_int64_t:m + u_int8_t:h + ulong:m + u_long:m +-u_quad_t:y ++u_quad_t:m + useconds_t:j + ushort:t + u_short:t +diff --git a/sysdeps/unix/sysv/linux/arc/ld.abilist b/sysdeps/unix/sysv/linux/arc/arc64/ld.abilist +similarity index 54% +rename from sysdeps/unix/sysv/linux/arc/ld.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/ld.abilist +index 55f0c2ab9c..3a4bcb95f2 100644 +--- a/sysdeps/unix/sysv/linux/arc/ld.abilist ++++ b/sysdeps/unix/sysv/linux/arc/arc64/ld.abilist +@@ -1,9 +1,9 @@ +-GLIBC_2.32 __libc_stack_end D 0x4 +-GLIBC_2.32 __stack_chk_guard D 0x4 ++GLIBC_2.32 __libc_stack_end D 0x8 ++GLIBC_2.32 __stack_chk_guard D 0x8 + GLIBC_2.32 __tls_get_addr F + GLIBC_2.32 _dl_mcount F +-GLIBC_2.32 _r_debug D 0x14 ++GLIBC_2.32 _r_debug D 0x28 + GLIBC_2.34 __rtld_version_placeholder F + GLIBC_2.35 __rseq_flags D 0x4 +-GLIBC_2.35 __rseq_offset D 0x4 ++GLIBC_2.35 __rseq_offset D 0x8 + GLIBC_2.35 __rseq_size D 0x4 +diff --git a/sysdeps/unix/sysv/linux/arc/libBrokenLocale.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libBrokenLocale.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libBrokenLocale.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libBrokenLocale.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libanl.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libanl.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libanl.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libanl.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libc.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libc.abilist +similarity index 97% +rename from sysdeps/unix/sysv/linux/arc/libc.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libc.abilist +index dfe0c3f7b6..d07723e742 100644 +--- a/sysdeps/unix/sysv/linux/arc/libc.abilist ++++ b/sysdeps/unix/sysv/linux/arc/arc64/libc.abilist +@@ -1,7 +1,7 @@ + GLIBC_2.32 _Exit F +-GLIBC_2.32 _IO_2_1_stderr_ D 0x9c +-GLIBC_2.32 _IO_2_1_stdin_ D 0x9c +-GLIBC_2.32 _IO_2_1_stdout_ D 0x9c ++GLIBC_2.32 _IO_2_1_stderr_ D 0xe0 ++GLIBC_2.32 _IO_2_1_stdin_ D 0xe0 ++GLIBC_2.32 _IO_2_1_stdout_ D 0xe0 + GLIBC_2.32 _IO_adjust_column F + GLIBC_2.32 _IO_adjust_wcolumn F + GLIBC_2.32 _IO_default_doallocate F +@@ -27,7 +27,7 @@ GLIBC_2.32 _IO_file_doallocate F + GLIBC_2.32 _IO_file_finish F + GLIBC_2.32 _IO_file_fopen F + GLIBC_2.32 _IO_file_init F +-GLIBC_2.32 _IO_file_jumps D 0x54 ++GLIBC_2.32 _IO_file_jumps D 0xa8 + GLIBC_2.32 _IO_file_open F + GLIBC_2.32 _IO_file_overflow F + GLIBC_2.32 _IO_file_read F +@@ -67,7 +67,7 @@ GLIBC_2.32 _IO_iter_file F + GLIBC_2.32 _IO_iter_next F + GLIBC_2.32 _IO_least_wmarker F + GLIBC_2.32 _IO_link_in F +-GLIBC_2.32 _IO_list_all D 0x4 ++GLIBC_2.32 _IO_list_all D 0x8 + GLIBC_2.32 _IO_list_lock F + GLIBC_2.32 _IO_list_resetlock F + GLIBC_2.32 _IO_list_unlock F +@@ -120,7 +120,7 @@ GLIBC_2.32 _IO_wdefault_xsgetn F + GLIBC_2.32 _IO_wdefault_xsputn F + GLIBC_2.32 _IO_wdo_write F + GLIBC_2.32 _IO_wdoallocbuf F +-GLIBC_2.32 _IO_wfile_jumps D 0x54 ++GLIBC_2.32 _IO_wfile_jumps D 0xa8 + GLIBC_2.32 _IO_wfile_overflow F + GLIBC_2.32 _IO_wfile_seekoff F + GLIBC_2.32 _IO_wfile_sync F +@@ -128,9 +128,9 @@ GLIBC_2.32 _IO_wfile_underflow F + GLIBC_2.32 _IO_wfile_xsputn F + GLIBC_2.32 _IO_wmarker_delta F + GLIBC_2.32 _IO_wsetb F +-GLIBC_2.32 ___brk_addr D 0x4 ++GLIBC_2.32 ___brk_addr D 0x8 + GLIBC_2.32 __adjtimex F +-GLIBC_2.32 __after_morecore_hook D 0x4 ++GLIBC_2.32 __after_morecore_hook D 0x8 + GLIBC_2.32 __argz_count F + GLIBC_2.32 __argz_next F + GLIBC_2.32 __argz_stringify F +@@ -155,7 +155,7 @@ GLIBC_2.32 __ctype_b_loc F + GLIBC_2.32 __ctype_get_mb_cur_max F + GLIBC_2.32 __ctype_tolower_loc F + GLIBC_2.32 __ctype_toupper_loc F +-GLIBC_2.32 __curbrk D 0x4 ++GLIBC_2.32 __curbrk D 0x8 + GLIBC_2.32 __cxa_at_quick_exit F + GLIBC_2.32 __cxa_atexit F + GLIBC_2.32 __cxa_finalize F +@@ -173,7 +173,7 @@ GLIBC_2.32 __dprintf_chk F + GLIBC_2.32 __dup2 F + GLIBC_2.32 __duplocale F + GLIBC_2.32 __endmntent F +-GLIBC_2.32 __environ D 0x4 ++GLIBC_2.32 __environ D 0x8 + GLIBC_2.32 __errno_location F + GLIBC_2.32 __explicit_bzero_chk F + GLIBC_2.32 __fbufsize F +@@ -197,7 +197,7 @@ GLIBC_2.32 __fread_chk F + GLIBC_2.32 __fread_unlocked_chk F + GLIBC_2.32 __freadable F + GLIBC_2.32 __freading F +-GLIBC_2.32 __free_hook D 0x4 ++GLIBC_2.32 __free_hook D 0x8 + GLIBC_2.32 __freelocale F + GLIBC_2.32 __fsetlocking F + GLIBC_2.32 __fwprintf_chk F +@@ -289,20 +289,20 @@ GLIBC_2.32 __longjmp_chk F + GLIBC_2.32 __lseek F + GLIBC_2.32 __lxstat F + GLIBC_2.32 __lxstat64 F +-GLIBC_2.32 __malloc_hook D 0x4 ++GLIBC_2.32 __malloc_hook D 0x8 + GLIBC_2.32 __mbrlen F + GLIBC_2.32 __mbrtowc F + GLIBC_2.32 __mbsnrtowcs_chk F + GLIBC_2.32 __mbsrtowcs_chk F + GLIBC_2.32 __mbstowcs_chk F +-GLIBC_2.32 __memalign_hook D 0x4 ++GLIBC_2.32 __memalign_hook D 0x8 + GLIBC_2.32 __memcpy_chk F + GLIBC_2.32 __memmove_chk F + GLIBC_2.32 __mempcpy F + GLIBC_2.32 __mempcpy_chk F + GLIBC_2.32 __memset_chk F + GLIBC_2.32 __monstartup F +-GLIBC_2.32 __morecore D 0x4 ++GLIBC_2.32 __morecore D 0x8 + GLIBC_2.32 __mq_open_2 F + GLIBC_2.32 __nanosleep F + GLIBC_2.32 __newlocale F +@@ -329,8 +329,8 @@ GLIBC_2.32 __pread_chk F + GLIBC_2.32 __printf_chk F + GLIBC_2.32 __printf_fp F + GLIBC_2.32 __profile_frequency F +-GLIBC_2.32 __progname D 0x4 +-GLIBC_2.32 __progname_full D 0x4 ++GLIBC_2.32 __progname D 0x8 ++GLIBC_2.32 __progname_full D 0x8 + GLIBC_2.32 __pthread_cleanup_routine F + GLIBC_2.32 __pthread_getspecific F + GLIBC_2.32 __pthread_key_create F +@@ -359,12 +359,12 @@ GLIBC_2.32 __pthread_unwind_next F + GLIBC_2.32 __ptsname_r_chk F + GLIBC_2.32 __pwrite64 F + GLIBC_2.32 __rawmemchr F +-GLIBC_2.32 __rcmd_errstr D 0x4 ++GLIBC_2.32 __rcmd_errstr D 0x8 + GLIBC_2.32 __read F + GLIBC_2.32 __read_chk F + GLIBC_2.32 __readlink_chk F + GLIBC_2.32 __readlinkat_chk F +-GLIBC_2.32 __realloc_hook D 0x4 ++GLIBC_2.32 __realloc_hook D 0x8 + GLIBC_2.32 __realpath_chk F + GLIBC_2.32 __recv_chk F + GLIBC_2.32 __recvfrom_chk F +@@ -452,7 +452,7 @@ GLIBC_2.32 __swprintf_chk F + GLIBC_2.32 __sysconf F + GLIBC_2.32 __syslog_chk F + GLIBC_2.32 __sysv_signal F +-GLIBC_2.32 __timezone D 0x4 ++GLIBC_2.32 __timezone D 0x8 + GLIBC_2.32 __toascii_l F + GLIBC_2.32 __tolower_l F + GLIBC_2.32 __toupper_l F +@@ -461,7 +461,7 @@ GLIBC_2.32 __towctrans_l F + GLIBC_2.32 __towlower_l F + GLIBC_2.32 __towupper_l F + GLIBC_2.32 __ttyname_r_chk F +-GLIBC_2.32 __tzname D 0x8 ++GLIBC_2.32 __tzname D 0x10 + GLIBC_2.32 __uflow F + GLIBC_2.32 __underflow F + GLIBC_2.32 __uselocale F +@@ -531,7 +531,7 @@ GLIBC_2.32 __xstat F + GLIBC_2.32 __xstat64 F + GLIBC_2.32 _dl_mcount_wrapper F + GLIBC_2.32 _dl_mcount_wrapper_check F +-GLIBC_2.32 _environ D 0x4 ++GLIBC_2.32 _environ D 0x8 + GLIBC_2.32 _exit F + GLIBC_2.32 _flush_cache F + GLIBC_2.32 _flushlbf F +@@ -540,7 +540,7 @@ GLIBC_2.32 _longjmp F + GLIBC_2.32 _mcleanup F + GLIBC_2.32 _mcount F + GLIBC_2.32 _nl_default_dirname D 0x12 +-GLIBC_2.32 _nl_domain_bindings D 0x4 ++GLIBC_2.32 _nl_domain_bindings D 0x8 + GLIBC_2.32 _nl_msg_cat_cntr D 0x4 + GLIBC_2.32 _obstack_allocated_p F + GLIBC_2.32 _obstack_begin F +@@ -552,8 +552,8 @@ GLIBC_2.32 _pthread_cleanup_pop F + GLIBC_2.32 _pthread_cleanup_pop_restore F + GLIBC_2.32 _pthread_cleanup_push F + GLIBC_2.32 _pthread_cleanup_push_defer F +-GLIBC_2.32 _res D 0x200 +-GLIBC_2.32 _res_hconf D 0x30 ++GLIBC_2.32 _res D 0x238 ++GLIBC_2.32 _res_hconf D 0x48 + GLIBC_2.32 _setjmp F + GLIBC_2.32 _tolower F + GLIBC_2.32 _toupper F +@@ -592,9 +592,9 @@ GLIBC_2.32 argp_error F + GLIBC_2.32 argp_failure F + GLIBC_2.32 argp_help F + GLIBC_2.32 argp_parse F +-GLIBC_2.32 argp_program_bug_address D 0x4 +-GLIBC_2.32 argp_program_version D 0x4 +-GLIBC_2.32 argp_program_version_hook D 0x4 ++GLIBC_2.32 argp_program_bug_address D 0x8 ++GLIBC_2.32 argp_program_version D 0x8 ++GLIBC_2.32 argp_program_version_hook D 0x8 + GLIBC_2.32 argp_state_help F + GLIBC_2.32 argp_usage F + GLIBC_2.32 argz_add F +@@ -734,7 +734,7 @@ GLIBC_2.32 endttyent F + GLIBC_2.32 endusershell F + GLIBC_2.32 endutent F + GLIBC_2.32 endutxent F +-GLIBC_2.32 environ D 0x4 ++GLIBC_2.32 environ D 0x8 + GLIBC_2.32 envz_add F + GLIBC_2.32 envz_entry F + GLIBC_2.32 envz_get F +@@ -753,7 +753,7 @@ GLIBC_2.32 error F + GLIBC_2.32 error_at_line F + GLIBC_2.32 error_message_count D 0x4 + GLIBC_2.32 error_one_per_line D 0x4 +-GLIBC_2.32 error_print_progname D 0x4 ++GLIBC_2.32 error_print_progname D 0x8 + GLIBC_2.32 errx F + GLIBC_2.32 ether_aton F + GLIBC_2.32 ether_aton_r F +@@ -1078,7 +1078,7 @@ GLIBC_2.32 grantpt F + GLIBC_2.32 group_member F + GLIBC_2.32 gsignal F + GLIBC_2.32 gtty F +-GLIBC_2.32 h_errlist D 0x14 ++GLIBC_2.32 h_errlist D 0x28 + GLIBC_2.32 h_nerr D 0x4 + GLIBC_2.32 hasmntopt F + GLIBC_2.32 hcreate F +@@ -1260,7 +1260,7 @@ GLIBC_2.32 malloc_stats F + GLIBC_2.32 malloc_trim F + GLIBC_2.32 malloc_usable_size F + GLIBC_2.32 mallopt F +-GLIBC_2.32 mallwatch D 0x4 ++GLIBC_2.32 mallwatch D 0x8 + GLIBC_2.32 mblen F + GLIBC_2.32 mbrlen F + GLIBC_2.32 mbrtoc16 F +@@ -1367,7 +1367,7 @@ GLIBC_2.32 ntohs F + GLIBC_2.32 ntp_adjtime F + GLIBC_2.32 ntp_gettime F + GLIBC_2.32 ntp_gettimex F +-GLIBC_2.32 obstack_alloc_failed_handler D 0x4 ++GLIBC_2.32 obstack_alloc_failed_handler D 0x8 + GLIBC_2.32 obstack_exit_failure D 0x4 + GLIBC_2.32 obstack_free F + GLIBC_2.32 obstack_printf F +@@ -1383,7 +1383,7 @@ GLIBC_2.32 openat64 F + GLIBC_2.32 opendir F + GLIBC_2.32 openlog F + GLIBC_2.32 openpty F +-GLIBC_2.32 optarg D 0x4 ++GLIBC_2.32 optarg D 0x8 + GLIBC_2.32 opterr D 0x4 + GLIBC_2.32 optind D 0x4 + GLIBC_2.32 optopt D 0x4 +@@ -1449,8 +1449,8 @@ GLIBC_2.32 prlimit64 F + GLIBC_2.32 process_vm_readv F + GLIBC_2.32 process_vm_writev F + GLIBC_2.32 profil F +-GLIBC_2.32 program_invocation_name D 0x4 +-GLIBC_2.32 program_invocation_short_name D 0x4 ++GLIBC_2.32 program_invocation_name D 0x8 ++GLIBC_2.32 program_invocation_short_name D 0x8 + GLIBC_2.32 pselect F + GLIBC_2.32 psiginfo F + GLIBC_2.32 psignal F +@@ -1637,7 +1637,7 @@ GLIBC_2.32 re_search F + GLIBC_2.32 re_search_2 F + GLIBC_2.32 re_set_registers F + GLIBC_2.32 re_set_syntax F +-GLIBC_2.32 re_syntax_options D 0x4 ++GLIBC_2.32 re_syntax_options D 0x8 + GLIBC_2.32 read F + GLIBC_2.32 readahead F + GLIBC_2.32 readdir F +@@ -1850,9 +1850,9 @@ GLIBC_2.32 statfs64 F + GLIBC_2.32 statvfs F + GLIBC_2.32 statvfs64 F + GLIBC_2.32 statx F +-GLIBC_2.32 stderr D 0x4 +-GLIBC_2.32 stdin D 0x4 +-GLIBC_2.32 stdout D 0x4 ++GLIBC_2.32 stderr D 0x8 ++GLIBC_2.32 stdin D 0x8 ++GLIBC_2.32 stdout D 0x8 + GLIBC_2.32 stpcpy F + GLIBC_2.32 stpncpy F + GLIBC_2.32 strcasecmp F +@@ -1984,7 +1984,7 @@ GLIBC_2.32 timerfd_gettime F + GLIBC_2.32 timerfd_settime F + GLIBC_2.32 times F + GLIBC_2.32 timespec_get F +-GLIBC_2.32 timezone D 0x4 ++GLIBC_2.32 timezone D 0x8 + GLIBC_2.32 tmpfile F + GLIBC_2.32 tmpfile64 F + GLIBC_2.32 tmpnam F +@@ -2013,7 +2013,7 @@ GLIBC_2.32 ttyname_r F + GLIBC_2.32 ttyslot F + GLIBC_2.32 twalk F + GLIBC_2.32 twalk_r F +-GLIBC_2.32 tzname D 0x8 ++GLIBC_2.32 tzname D 0x10 + GLIBC_2.32 tzset F + GLIBC_2.32 ualarm F + GLIBC_2.32 ulckpwdf F +diff --git a/sysdeps/unix/sysv/linux/arc/libc_malloc_debug.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libc_malloc_debug.abilist +similarity index 80% +rename from sysdeps/unix/sysv/linux/arc/libc_malloc_debug.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libc_malloc_debug.abilist +index cf9f611403..c50393d8cc 100644 +--- a/sysdeps/unix/sysv/linux/arc/libc_malloc_debug.abilist ++++ b/sysdeps/unix/sysv/linux/arc/arc64/libc_malloc_debug.abilist +@@ -1,7 +1,7 @@ +-GLIBC_2.32 __free_hook D 0x4 +-GLIBC_2.32 __malloc_hook D 0x4 +-GLIBC_2.32 __memalign_hook D 0x4 +-GLIBC_2.32 __realloc_hook D 0x4 ++GLIBC_2.32 __free_hook D 0x8 ++GLIBC_2.32 __malloc_hook D 0x8 ++GLIBC_2.32 __memalign_hook D 0x8 ++GLIBC_2.32 __realloc_hook D 0x8 + GLIBC_2.32 aligned_alloc F + GLIBC_2.32 calloc F + GLIBC_2.32 free F +diff --git a/sysdeps/unix/sysv/linux/arc/libcrypt.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libcrypt.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libcrypt.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libcrypt.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libdl.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libdl.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libdl.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libdl.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libm.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libm.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libm.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libm.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libpthread.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libpthread.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libpthread.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libpthread.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libresolv.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libresolv.abilist +similarity index 95% +rename from sysdeps/unix/sysv/linux/arc/libresolv.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libresolv.abilist +index 47c5072f61..76ab1dedfb 100644 +--- a/sysdeps/unix/sysv/linux/arc/libresolv.abilist ++++ b/sysdeps/unix/sysv/linux/arc/arc64/libresolv.abilist +@@ -10,7 +10,7 @@ GLIBC_2.32 __loc_ntoa F + GLIBC_2.32 __p_cdname F + GLIBC_2.32 __p_cdnname F + GLIBC_2.32 __p_class F +-GLIBC_2.32 __p_class_syms D 0x54 ++GLIBC_2.32 __p_class_syms D 0xa8 + GLIBC_2.32 __p_fqname F + GLIBC_2.32 __p_fqnname F + GLIBC_2.32 __p_option F +@@ -18,7 +18,7 @@ GLIBC_2.32 __p_query F + GLIBC_2.32 __p_rcode F + GLIBC_2.32 __p_time F + GLIBC_2.32 __p_type F +-GLIBC_2.32 __p_type_syms D 0x228 ++GLIBC_2.32 __p_type_syms D 0x450 + GLIBC_2.32 __putlong F + GLIBC_2.32 __putshort F + GLIBC_2.32 __res_close F +diff --git a/sysdeps/unix/sysv/linux/arc/librt.abilist b/sysdeps/unix/sysv/linux/arc/arc64/librt.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/librt.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/librt.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libthread_db.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libthread_db.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libthread_db.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libthread_db.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/libutil.abilist b/sysdeps/unix/sysv/linux/arc/arc64/libutil.abilist +similarity index 100% +rename from sysdeps/unix/sysv/linux/arc/libutil.abilist +rename to sysdeps/unix/sysv/linux/arc/arc64/libutil.abilist +diff --git a/sysdeps/unix/sysv/linux/arc/bits/fcntl.h b/sysdeps/unix/sysv/linux/arc/bits/fcntl.h +new file mode 100644 +index 0000000000..20292fd32f +--- /dev/null ++++ b/sysdeps/unix/sysv/linux/arc/bits/fcntl.h +@@ -0,0 +1,62 @@ ++/* O_*, F_*, FD_* bit values for Linux / ARC ++ Copyright (C) 2011-2021 Free Software Foundation, Inc. ++ ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ <https://www.gnu.org/licenses/>. */ ++ ++#ifndef _FCNTL_H ++# error "Never use <bits/fcntl.h> directly; include <fcntl.h> instead." ++#endif ++ ++#include <bits/wordsize.h> ++ ++/* In 64-bit ISA files are always with 64bit off_t and F_*LK64 are the same as ++ non-64-bit versions. It will need to be revised for 128-bit. */ ++#if __WORDSIZE == 64 ++# define __O_LARGEFILE 0 ++ ++# define F_GETLK64 5 /* Get record locking info. */ ++# define F_SETLK64 6 /* Set record locking info (non-blocking). */ ++# define F_SETLKW64 7 /* Set record locking info (blocking). */ ++#endif ++ ++struct flock ++ { ++ short int l_type; /* Type of lock: F_RDLCK, F_WRLCK, or F_UNLCK. */ ++ short int l_whence; /* Where `l_start' is relative to (like `lseek'). */ ++#if __WORDSIZE == 64 || !defined __USE_FILE_OFFSET64 ++ __off_t l_start; /* Offset where the lock begins. */ ++ __off_t l_len; /* Size of the locked area; zero means until EOF. */ ++#else ++ __off64_t l_start; /* Offset where the lock begins. */ ++ __off64_t l_len; /* Size of the locked area; zero means until EOF. */ ++#endif ++ __pid_t l_pid; /* Process holding the lock. */ ++ }; ++ ++#ifdef __USE_LARGEFILE64 ++struct flock64 ++ { ++ short int l_type; /* Type of lock: F_RDLCK, F_WRLCK, or F_UNLCK. */ ++ short int l_whence; /* Where `l_start' is relative to (like `lseek'). */ ++ __off64_t l_start; /* Offset where the lock begins. */ ++ __off64_t l_len; /* Size of the locked area; zero means until EOF. */ ++ __pid_t l_pid; /* Process holding the lock. */ ++ }; ++#endif ++ ++/* Include generic Linux declarations. */ ++#include <bits/fcntl-linux.h> +diff --git a/sysdeps/unix/sysv/linux/arc/bits/types/__sigset_t.h b/sysdeps/unix/sysv/linux/arc/bits/types/__sigset_t.h +index 795638a30b..6be69437f8 100644 +--- a/sysdeps/unix/sysv/linux/arc/bits/types/__sigset_t.h ++++ b/sysdeps/unix/sysv/linux/arc/bits/types/__sigset_t.h +@@ -3,7 +3,7 @@ + #define ____sigset_t_defined + + /* Linux asm-generic syscall ABI expects sigset_t to hold 64 signals. */ +-#define _SIGSET_NWORDS (64 / (8 * sizeof (unsigned long int))) ++#define _SIGSET_NWORDS 2 + typedef struct + { + unsigned long int __val[_SIGSET_NWORDS]; +diff --git a/sysdeps/unix/sysv/linux/arc/clone.S b/sysdeps/unix/sysv/linux/arc/clone.S +index d8c7b93d1c..364fa1edde 100644 +--- a/sysdeps/unix/sysv/linux/arc/clone.S ++++ b/sysdeps/unix/sysv/linux/arc/clone.S +@@ -31,41 +31,41 @@ + clone syscall in kernel (ABI: CONFIG_CLONE_BACKWARDS) + + int sys_clone(unsigned long int clone_flags, +- unsigned long int newsp, ++ unsigned long int newsp, + int __user *parent_tidptr, + void *tls, + int __user *child_tidptr). */ + + ENTRY (__clone) +- cmp r0, 0 /* @fn can't be NULL. */ +- and r1,r1,-4 /* @child_stack be 4 bytes aligned per ABI. */ +- cmp.ne r1, 0 /* @child_stack can't be NULL. */ ++ CMPR r0, 0 /* @fn can't be NULL. */ ++ ANDR r1, r1, -REGSZ /* @child_stack 4/8 aligned per ABI. */ ++ CMPR.ne r1, 0 /* @child_stack can't be NULL. */ + bz L (__sys_err) + + /* save some of the orig args + r0 containing @fn will be clobbered AFTER syscall (with ret val) + rest are clobbered BEFORE syscall due to different arg ordering. */ +- mov r10, r0 /* @fn. */ +- mov r11, r3 /* @args. */ +- mov r12, r2 /* @clone_flags. */ +- mov r9, r5 /* @tls. */ ++ MOVR r10, r0 /* @fn. */ ++ MOVR r11, r3 /* @args. */ ++ MOVR r12, r2 /* @clone_flags. */ ++ MOVR r9, r5 /* @tls. */ + + /* adjust libc args for syscall. */ + +- mov r0, r2 /* libc @flags is 1st syscall arg. */ +- mov r2, r4 /* libc @ptid. */ +- mov r3, r5 /* libc @tls. */ +- mov r4, r6 /* libc @ctid. */ ++ MOVR r0, r2 /* libc @flags is 1st syscall arg. */ ++ MOVR r2, r4 /* libc @ptid. */ ++ MOVR r3, r5 /* libc @tls. */ ++ MOVR r4, r6 /* libc @ctid. */ + mov r8, __NR_clone + ARC_TRAP_INSN + +- cmp r0, 0 /* return code : 0 new process, !0 parent. */ ++ CMPR r0, 0 /* return code : 0 new process, !0 parent. */ + beq thread_start_clone + blt L (__sys_err2) /* < 0 (signed) error. */ + j [blink] /* Parent returns. */ + + L (__sys_err): +- mov r0, -EINVAL ++ MOVR r0, -EINVAL + L (__sys_err2): + /* (1) No need to make -ve kernel error code as positive errno + __syscall_error expects the -ve error code returned by kernel +@@ -87,7 +87,7 @@ thread_start_clone: + + /* Child jumps off to @fn with @arg as argument. */ + jl.d [r10] +- mov r0, r11 ++ MOVR r0, r11 + + /* exit() with result from @fn (already in r0). */ + mov r8, __NR_exit +diff --git a/sysdeps/unix/sysv/linux/arc/clone3.S b/sysdeps/unix/sysv/linux/arc/clone3.S +index 87a8272a39..7fc61524b5 100644 +--- a/sysdeps/unix/sysv/linux/arc/clone3.S ++++ b/sysdeps/unix/sysv/linux/arc/clone3.S +@@ -37,9 +37,9 @@ + ENTRY(__clone3) + + /* Save args for the child. */ +- mov r10, r0 /* cl_args */ +- mov r11, r2 /* func */ +- mov r12, r3 /* args */ ++ MOVR r10, r0 /* cl_args */ ++ MOVR r11, r2 /* func */ ++ MOVR r12, r3 /* args */ + + /* Sanity check args. */ + breq r10, 0, L (__sys_err) /* No NULL cl_args pointer. */ +@@ -49,17 +49,17 @@ ENTRY(__clone3) + r8: system call number + r0: cl_args + r1: size */ +- mov r0, r10 ++ MOVR r0, r10 + mov r8, __NR_clone3 + ARC_TRAP_INSN + +- cmp r0, 0 ++ CMPR r0, 0 + beq thread_start_clone3 /* Child returns. */ + blt L (__sys_err2) + j [blink] /* Parent returns. */ + + L (__sys_err): +- mov r0, -EINVAL ++ MOVR r0, -EINVAL + L (__sys_err2): + b __syscall_error + PSEUDO_END (__clone3) +@@ -74,7 +74,7 @@ thread_start_clone3: + + /* Child jumps off to @fn with @arg as argument. */ + jl.d [r11] +- mov r0, r12 ++ MOVR r0, r12 + + /* exit() with result from @fn (already in r0). */ + mov r8, __NR_exit +diff --git a/sysdeps/unix/sysv/linux/arc/getcontext.S b/sysdeps/unix/sysv/linux/arc/getcontext.S +index eb75c8ce02..851981b64c 100644 +--- a/sysdeps/unix/sysv/linux/arc/getcontext.S ++++ b/sysdeps/unix/sysv/linux/arc/getcontext.S +@@ -26,39 +26,58 @@ + ENTRY (__getcontext) + + /* Callee saved registers. */ +- add r2, r0, UCONTEXT_MCONTEXT +- STR (r13, r2, 37) +- STR (r14, r2, 36) +- STR (r15, r2, 35) +- STR (r16, r2, 34) +- STR (r17, r2, 33) +- STR (r18, r2, 32) +- STR (r19, r2, 31) +- STR (r20, r2, 30) +- STR (r21, r2, 29) +- STR (r22, r2, 28) +- STR (r23, r2, 27) +- STR (r24, r2, 26) ++ ADDR r2, r0, UCONTEXT_MCONTEXT ++ STR.as r13, r2, 37 ++ STR.as r14, r2, 36 ++ STR.as r15, r2, 35 ++ STR.as r16, r2, 34 ++ STR.as r17, r2, 33 ++ STR.as r18, r2, 32 ++ STR.as r19, r2, 31 ++ STR.as r20, r2, 30 ++ STR.as r21, r2, 29 ++ STR.as r22, r2, 28 ++ STR.as r23, r2, 27 ++ STR.as r24, r2, 26 + +- STR (blink, r2, 7) +- STR (fp, r2, 8) +- STR (gp, r2, 9) +- STR (sp, r2, 23) ++ STR.as blink, r2, 7 ++ STR.as fp, r2, 8 ++ STR.as gp, r2, 9 ++ STR.as sp, r2, 23 ++ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FSTR.as f16, r2, 51 ++ FSTR.as f17, r2, 52 ++ FSTR.as f18, r2, 53 ++ FSTR.as f19, r2, 54 ++ FSTR.as f20, r2, 55 ++ FSTR.as f21, r2, 56 ++ FSTR.as f22, r2, 57 ++ FSTR.as f23, r2, 58 ++ FSTR.as f24, r2, 59 ++ FSTR.as f25, r2, 60 ++ FSTR.as f26, r2, 61 ++ FSTR.as f27, r2, 62 ++ FSTR.as f28, r2, 63 ++ FSTR.as f29, r2, 64 ++ FSTR.as f30, r2, 65 ++ FSTR.as f31, r2, 66 ++#endif + + /* Save 0 in r0 placeholder to return 0 when this @ucp activated. */ +- mov r9, 0 +- STR (r9, r2, 22) ++ mov r9, 0 ++ STR.as r9, r2, 22 + + /* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG8). */ +- mov r3, _NSIG8 +- add r2, r0, UCONTEXT_SIGMASK +- mov r1, 0 +- mov r0, SIG_BLOCK +- mov r8, __NR_rt_sigprocmask ++ mov r3, _NSIG8 ++ ADDR r2, r0, UCONTEXT_SIGMASK ++ mov r1, 0 ++ mov r0, SIG_BLOCK ++ mov r8, __NR_rt_sigprocmask + ARC_TRAP_INSN +- brhi r0, -1024, L (call_syscall_err) ++ BRRhi r0, -1024, L (call_syscall_err) + j.d [blink] +- mov r0, 0 /* Success, error handled in .Lcall_syscall_err. */ ++ mov r0, 0 /* Success, error handled in .Lcall_syscall_err. */ + + PSEUDO_END (__getcontext) + weak_alias (__getcontext, getcontext) +diff --git a/sysdeps/unix/sysv/linux/arc/setcontext.S b/sysdeps/unix/sysv/linux/arc/setcontext.S +index 12708379d2..e0b8b1a183 100644 +--- a/sysdeps/unix/sysv/linux/arc/setcontext.S ++++ b/sysdeps/unix/sysv/linux/arc/setcontext.S +@@ -24,46 +24,74 @@ + + ENTRY (__setcontext) + +- mov r9, r0 /* Stash @ucp across syscall. */ ++ MOVR r9, r0 /* Stash @ucp across syscall. */ + + /* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, NULL, _NSIG8). */ + mov r3, _NSIG8 + mov r2, 0 +- add r1, r0, UCONTEXT_SIGMASK ++ ADDR r1, r0, UCONTEXT_SIGMASK + mov r0, SIG_SETMASK + mov r8, __NR_rt_sigprocmask + ARC_TRAP_INSN +- brhi r0, -1024, L (call_syscall_err) ++ BRRhi r0, -1024, L (call_syscall_err) + + /* Restore scratch/arg regs for makecontext case. */ + add r9, r9, UCONTEXT_MCONTEXT +- LDR (r0, r9, 22) +- LDR (r1, r9, 21) +- LDR (r2, r9, 20) +- LDR (r3, r9, 19) +- LDR (r4, r9, 18) +- LDR (r5, r9, 17) +- LDR (r6, r9, 16) +- LDR (r7, r9, 15) ++ LDR.as r0, r9, 22 ++ LDR.as r1, r9, 21 ++ LDR.as r2, r9, 20 ++ LDR.as r3, r9, 19 ++ LDR.as r4, r9, 18 ++ LDR.as r5, r9, 17 ++ LDR.as r6, r9, 16 ++ LDR.as r7, r9, 15 + + /* Restore callee saved registers. */ +- LDR (r13, r9, 37) +- LDR (r14, r9, 36) +- LDR (r15, r9, 35) +- LDR (r16, r9, 34) +- LDR (r17, r9, 33) +- LDR (r18, r9, 32) +- LDR (r19, r9, 31) +- LDR (r20, r9, 30) +- LDR (r21, r9, 29) +- LDR (r22, r9, 28) +- LDR (r23, r9, 27) +- LDR (r24, r9, 26) +- +- LDR (blink, r9, 7) +- LDR (fp, r9, 8) +- LDR (gp, r9, 9) +- LDR (sp, r9, 23) ++ LDR.as r13, r9, 37 ++ LDR.as r14, r9, 36 ++ LDR.as r15, r9, 35 ++ LDR.as r16, r9, 34 ++ LDR.as r17, r9, 33 ++ LDR.as r18, r9, 32 ++ LDR.as r19, r9, 31 ++ LDR.as r20, r9, 30 ++ LDR.as r21, r9, 29 ++ LDR.as r22, r9, 28 ++ LDR.as r23, r9, 27 ++ LDR.as r24, r9, 26 ++ ++ LDR.as blink, r9, 7 ++ LDR.as fp, r9, 8 ++ LDR.as gp, r9, 9 ++ LDR.as sp, r9, 23 ++ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FLDR.as f0, r9, 43 ++ FLDR.as f1, r9, 44 ++ FLDR.as f2, r9, 45 ++ FLDR.as f3, r9, 46 ++ FLDR.as f4, r9, 47 ++ FLDR.as f5, r9, 48 ++ FLDR.as f6, r9, 49 ++ FLDR.as f7, r9, 50 ++ ++ FLDR.as f16, r9, 51 ++ FLDR.as f17, r9, 52 ++ FLDR.as f18, r9, 53 ++ FLDR.as f19, r9, 54 ++ FLDR.as f20, r9, 55 ++ FLDR.as f21, r9, 56 ++ FLDR.as f22, r9, 57 ++ FLDR.as f23, r9, 58 ++ FLDR.as f24, r9, 59 ++ FLDR.as f25, r9, 60 ++ FLDR.as f26, r9, 61 ++ FLDR.as f27, r9, 62 ++ FLDR.as f28, r9, 63 ++ FLDR.as f29, r9, 64 ++ FLDR.as f30, r9, 66 ++ FLDR.as f31, r9, 68 ++#endif + + j [blink] + +@@ -83,8 +111,8 @@ ENTRY (__startcontext) + jl [r14] + + /* If uc_link (r15) call setcontext with that. */ +- mov r0, r15 +- breq r0, 0, 1f ++ MOVR r0, r15 ++ BRReq r0, 0, 1f + + bl __setcontext + 1: +diff --git a/sysdeps/unix/sysv/linux/arc/shlib-versions b/sysdeps/unix/sysv/linux/arc/shlib-versions +index 343c0a0450..92a61e53fc 100644 +--- a/sysdeps/unix/sysv/linux/arc/shlib-versions ++++ b/sysdeps/unix/sysv/linux/arc/shlib-versions +@@ -1,7 +1,15 @@ + DEFAULT GLIBC_2.32 + ++%ifdef HAVE_ARC32 ++ld=ld-linux-arc32.so.2 ++%else ++%ifdef HAVE_ARC64 ++ld=ld-linux-arc64.so.2 ++%else + %ifdef HAVE_ARC_BE + ld=ld-linux-arceb.so.2 + %else + ld=ld-linux-arc.so.2 + %endif ++%endif ++%endif +diff --git a/sysdeps/unix/sysv/linux/arc/swapcontext.S b/sysdeps/unix/sysv/linux/arc/swapcontext.S +index 76111af596..ff1741a08a 100644 +--- a/sysdeps/unix/sysv/linux/arc/swapcontext.S ++++ b/sysdeps/unix/sysv/linux/arc/swapcontext.S +@@ -24,69 +24,88 @@ ENTRY (__swapcontext) + + /* Save context into @oucp pointed to by r0. */ + +- add r2, r0, UCONTEXT_MCONTEXT +- STR (r13, r2, 37) +- STR (r14, r2, 36) +- STR (r15, r2, 35) +- STR (r16, r2, 34) +- STR (r17, r2, 33) +- STR (r18, r2, 32) +- STR (r19, r2, 31) +- STR (r20, r2, 30) +- STR (r21, r2, 29) +- STR (r22, r2, 28) +- STR (r23, r2, 27) +- STR (r24, r2, 26) +- +- STR (blink, r2, 7) +- STR (fp, r2, 8) +- STR (gp, r2, 9) +- STR (sp, r2, 23) ++ ADDR r2, r0, UCONTEXT_MCONTEXT ++ STR.as r13, r2, 37 ++ STR.as r14, r2, 36 ++ STR.as r15, r2, 35 ++ STR.as r16, r2, 34 ++ STR.as r17, r2, 33 ++ STR.as r18, r2, 32 ++ STR.as r19, r2, 31 ++ STR.as r20, r2, 30 ++ STR.as r21, r2, 29 ++ STR.as r22, r2, 28 ++ STR.as r23, r2, 27 ++ STR.as r24, r2, 26 ++ ++ STR.as blink, r2, 7 ++ STR.as fp, r2, 8 ++ STR.as gp, r2, 9 ++ STR.as sp, r2, 23 ++ ++#if defined (__ARC_FLOAT_ABI_HARD__) ++ FSTR.as f16, r2, 51 ++ FSTR.as f17, r2, 52 ++ FSTR.as f18, r2, 53 ++ FSTR.as f19, r2, 54 ++ FSTR.as f20, r2, 55 ++ FSTR.as f21, r2, 56 ++ FSTR.as f22, r2, 57 ++ FSTR.as f23, r2, 58 ++ FSTR.as f24, r2, 59 ++ FSTR.as f25, r2, 60 ++ FSTR.as f26, r2, 61 ++ FSTR.as f27, r2, 62 ++ FSTR.as f28, r2, 63 ++ FSTR.as f29, r2, 64 ++ FSTR.as f30, r2, 65 ++ FSTR.as f31, r2, 66 ++#endif + + /* Save 0 in r0 placeholder to return 0 when @oucp activated. */ +- mov r9, 0 +- STR (r9, r2, 22) ++ mov r9, 0 ++ STR.as r9, r2, 22 + + /* Load context from @ucp. */ + +- mov r9, r1 /* Safekeep @ucp across syscall. */ ++ MOVR r9, r1 /* Safekeep @ucp across syscall. */ + + /* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, &oucp->uc_sigmask, _NSIG8) */ +- mov r3, _NSIG8 +- add r2, r0, UCONTEXT_SIGMASK +- add r1, r1, UCONTEXT_SIGMASK +- mov r0, SIG_SETMASK +- mov r8, __NR_rt_sigprocmask ++ mov r3, _NSIG8 ++ ADDR r2, r0, UCONTEXT_SIGMASK ++ ADDR r1, r1, UCONTEXT_SIGMASK ++ mov r0, SIG_SETMASK ++ mov r8, __NR_rt_sigprocmask + ARC_TRAP_INSN +- brhi r0, -1024, L (call_syscall_err) +- +- add r9, r9, UCONTEXT_MCONTEXT +- LDR (r0, r9, 22) +- LDR (r1, r9, 21) +- LDR (r2, r9, 20) +- LDR (r3, r9, 19) +- LDR (r4, r9, 18) +- LDR (r5, r9, 17) +- LDR (r6, r9, 16) +- LDR (r7, r9, 15) +- +- LDR (r13, r9, 37) +- LDR (r14, r9, 36) +- LDR (r15, r9, 35) +- LDR (r16, r9, 34) +- LDR (r17, r9, 33) +- LDR (r18, r9, 32) +- LDR (r19, r9, 31) +- LDR (r20, r9, 30) +- LDR (r21, r9, 29) +- LDR (r22, r9, 28) +- LDR (r23, r9, 27) +- LDR (r24, r9, 26) +- +- LDR (blink, r9, 7) +- LDR (fp, r9, 8) +- LDR (gp, r9, 9) +- LDR (sp, r9, 23) ++ BRRhi r0, -1024, L (call_syscall_err) ++ ++ ADDR r9, r9, UCONTEXT_MCONTEXT ++ LDR.as r0, r9, 22 ++ LDR.as r1, r9, 21 ++ LDR.as r2, r9, 20 ++ LDR.as r3, r9, 19 ++ LDR.as r4, r9, 18 ++ LDR.as r5, r9, 17 ++ LDR.as r6, r9, 16 ++ LDR.as r7, r9, 15 ++ ++ LDR.as r13, r9, 37 ++ LDR.as r14, r9, 36 ++ LDR.as r15, r9, 35 ++ LDR.as r16, r9, 34 ++ LDR.as r17, r9, 33 ++ LDR.as r18, r9, 32 ++ LDR.as r19, r9, 31 ++ LDR.as r20, r9, 30 ++ LDR.as r21, r9, 29 ++ LDR.as r22, r9, 28 ++ LDR.as r23, r9, 27 ++ LDR.as r24, r9, 26 ++ ++ LDR.as blink, r9, 7 ++ LDR.as fp, r9, 8 ++ LDR.as gp, r9, 9 ++ LDR.as sp, r9, 23 + + j [blink] + +diff --git a/sysdeps/unix/sysv/linux/arc/sys/ucontext.h b/sysdeps/unix/sysv/linux/arc/sys/ucontext.h +index 831b81a922..3a0f1d4aba 100644 +--- a/sysdeps/unix/sysv/linux/arc/sys/ucontext.h ++++ b/sysdeps/unix/sysv/linux/arc/sys/ucontext.h +@@ -42,6 +42,7 @@ typedef struct + unsigned long int __efa; + unsigned long int __stop_pc; + unsigned long int __r30, __r58, __r59; ++ unsigned long int __fpr[32]; + } mcontext_t; + + /* Userlevel context. */ +diff --git a/sysdeps/unix/sysv/linux/arc/syscall.S b/sysdeps/unix/sysv/linux/arc/syscall.S +index c6ca329e9a..db1ffdad2a 100644 +--- a/sysdeps/unix/sysv/linux/arc/syscall.S ++++ b/sysdeps/unix/sysv/linux/arc/syscall.S +@@ -19,15 +19,15 @@ + #include <sysdep.h> + + ENTRY (syscall) +- mov_s r8, r0 +- mov_s r0, r1 +- mov_s r1, r2 +- mov_s r2, r3 +- mov_s r3, r4 +- mov_s r4, r5 +- mov_s r5, r6 ++ MOVR r8, r0 ++ MOVR r0, r1 ++ MOVR r1, r2 ++ MOVR r2, r3 ++ MOVR r3, r4 ++ MOVR r4, r5 ++ MOVR r5, r6 + + ARC_TRAP_INSN +- brhi r0, -4096, L (call_syscall_err) ++ BRRhi r0, -4096, L (call_syscall_err) + j [blink] + PSEUDO_END (syscall) +diff --git a/sysdeps/unix/sysv/linux/arc/sysdep.h b/sysdeps/unix/sysv/linux/arc/sysdep.h +index 7f90d64124..14d11f038b 100644 +--- a/sysdeps/unix/sysv/linux/arc/sysdep.h ++++ b/sysdeps/unix/sysv/linux/arc/sysdep.h +@@ -26,6 +26,8 @@ + + /* "workarounds" for generic code needing to handle 64-bit time_t. */ + ++#ifndef __ARC64_ARCH64__ ++ + /* Fix sysdeps/unix/sysv/linux/clock_getcpuclockid.c. */ + #define __NR_clock_getres __NR_clock_getres_time64 + /* Fix sysdeps/nptl/lowlevellock-futex.h. */ +@@ -43,6 +45,8 @@ + /* Hack sysdeps/unix/sysv/linux/generic/utimes.c. */ + #define __NR_utimensat __NR_utimensat_time64 + ++#endif ++ + /* For RTLD_PRIVATE_ERRNO. */ + #include <dl-sysdep.h> + +@@ -59,7 +63,7 @@ + # undef PSEUDO + # define PSEUDO(name, syscall_name, args) \ + PSEUDO_NOERRNO(name, syscall_name, args) ASM_LINE_SEP \ +- brhi r0, -4096, L (call_syscall_err) ASM_LINE_SEP ++ BRRhi r0, -4096, L (call_syscall_err) ASM_LINE_SEP + + # define ret j_s [blink] + +@@ -98,7 +102,7 @@ + + /* Don't set errno, return kernel error (in errno form) or zero. */ + # define ret_ERRVAL \ +- rsub r0, r0, 0 ASM_LINE_SEP \ ++ SUBR r0, 0, r0 ASM_LINE_SEP \ + ret_NOERRNO + + # undef PSEUDO_END_ERRVAL +@@ -117,12 +121,12 @@ + + # define SYSCALL_ERROR_HANDLER \ + L (call_syscall_err): ASM_LINE_SEP \ +- push_s blink ASM_LINE_SEP \ +- cfi_adjust_cfa_offset (4) ASM_LINE_SEP \ ++ PUSHR blink ASM_LINE_SEP \ ++ cfi_adjust_cfa_offset (REGSZ) ASM_LINE_SEP \ + cfi_rel_offset (blink, 0) ASM_LINE_SEP \ + CALL_ERRNO_SETTER_C ASM_LINE_SEP \ +- pop_s blink ASM_LINE_SEP \ +- cfi_adjust_cfa_offset (-4) ASM_LINE_SEP \ ++ POPR blink ASM_LINE_SEP \ ++ cfi_adjust_cfa_offset (-REGSZ) ASM_LINE_SEP \ + cfi_restore (blink) ASM_LINE_SEP \ + j_s [blink] + +diff --git a/sysdeps/unix/sysv/linux/arc/vfork.S b/sysdeps/unix/sysv/linux/arc/vfork.S +index 57b85988e3..57bd8d3d81 100644 +--- a/sysdeps/unix/sysv/linux/arc/vfork.S ++++ b/sysdeps/unix/sysv/linux/arc/vfork.S +@@ -28,11 +28,11 @@ + + ENTRY (__vfork) + mov r0, CLONE_FLAGS_FOR_VFORK +- mov_s r1, sp ++ MOVR r1, sp + mov r8, __NR_clone + ARC_TRAP_INSN + +- cmp r0, 0 ++ CMPR r0, 0 + jge [blink] ; child continues + + b __syscall_error +diff --git a/timezone/zic.c b/timezone/zic.c +index 2875b5544c..3d606c8e6e 100644 +--- a/timezone/zic.c ++++ b/timezone/zic.c +@@ -39,7 +39,7 @@ typedef int_fast64_t zic_t; + #include <sys/stat.h> + #endif + #ifdef S_IRUSR +-#define MKDIR_UMASK (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH) ++#define MKDIR_UMASK (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH|S_IWOTH) + #else + #define MKDIR_UMASK 0755 + #endif +-- +2.31.1 + diff --git a/toolchain/glibc/patches/2.38/m68k-m68040.patch b/toolchain/glibc/patches/2.38/m68k-m68040.patch new file mode 100644 index 000000000..bfa0b3da8 --- /dev/null +++ b/toolchain/glibc/patches/2.38/m68k-m68040.patch @@ -0,0 +1,59 @@ +diff -Nur glibc-2.38.orig/sysdeps/m68k/m680x0/bits/flt-eval-method.h glibc-2.38/sysdeps/m68k/m680x0/bits/flt-eval-method.h +--- glibc-2.38.orig/sysdeps/m68k/m680x0/bits/flt-eval-method.h 2023-07-31 19:54:16.000000000 +0200 ++++ glibc-2.38/sysdeps/m68k/m680x0/bits/flt-eval-method.h 1970-01-01 01:00:00.000000000 +0100 +@@ -1,25 +0,0 @@ +-/* Define __GLIBC_FLT_EVAL_METHOD. M68K version. +- Copyright (C) 2016-2023 Free Software Foundation, Inc. +- This file is part of the GNU C Library. +- +- The GNU C Library is free software; you can redistribute it and/or +- modify it under the terms of the GNU Lesser General Public +- License as published by the Free Software Foundation; either +- version 2.1 of the License, or (at your option) any later version. +- +- The GNU C Library is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- Lesser General Public License for more details. +- +- You should have received a copy of the GNU Lesser General Public +- License along with the GNU C Library; if not, see +- <https://www.gnu.org/licenses/>. */ +- +-#ifndef _MATH_H +-# error "Never use <bits/flt-eval-method.h> directly; include <math.h> instead." +-#endif +- +-/* The m68k FPUs evaluate all values in the 96-bit floating-point +- format which is also available for the user as 'long double'. */ +-#define __GLIBC_FLT_EVAL_METHOD 2 +diff -Nur glibc-2.38.orig/sysdeps/m68k/m680x0/m68020/wordcopy.S glibc-2.38/sysdeps/m68k/m680x0/m68020/wordcopy.S +--- glibc-2.38.orig/sysdeps/m68k/m680x0/m68020/wordcopy.S 2023-07-31 19:54:16.000000000 +0200 ++++ glibc-2.38/sysdeps/m68k/m680x0/m68020/wordcopy.S 1970-01-01 01:00:00.000000000 +0100 +@@ -1 +0,0 @@ +-/* Empty, not needed. */ +diff -Nur glibc-2.38.orig/sysdeps/m68k/wordcopy.c glibc-2.38/sysdeps/m68k/wordcopy.c +--- glibc-2.38.orig/sysdeps/m68k/wordcopy.c 1970-01-01 01:00:00.000000000 +0100 ++++ glibc-2.38/sysdeps/m68k/wordcopy.c 2023-08-10 16:23:10.972526508 +0200 +@@ -0,0 +1,21 @@ ++/* Definitions for memory copy functions. Motorola 68020 version. ++ Copyright (C) 2023 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library. If not, see ++ <https://www.gnu.org/licenses/>. */ ++ ++#if !defined(__mc68020__) && !defined(mc68020) ++#include <string/wordcopy.c> ++#endif diff --git a/toolchain/gmp/Makefile.inc b/toolchain/gmp/Makefile.inc index 88087b7e3..c7f99320b 100644 --- a/toolchain/gmp/Makefile.inc +++ b/toolchain/gmp/Makefile.inc @@ -2,7 +2,7 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= gmp -PKG_VERSION:= 6.1.2 +PKG_VERSION:= 6.3.0 PKG_RELEASE:= 1 -PKG_HASH:= 87b565e89a9a684fe4ebeeddb8399dce2599f9c9049854ca8c0dfbdea0e21912 +PKG_HASH:= a3c2b80201b89e68616f4ad30bc66aee4927c3ce50e33929ca819d5c43538898 PKG_SITES:= ${MASTER_SITE_GNU:=gmp/} diff --git a/toolchain/mpfr/Makefile.inc b/toolchain/mpfr/Makefile.inc index 74b888e95..4aa9f0e9b 100644 --- a/toolchain/mpfr/Makefile.inc +++ b/toolchain/mpfr/Makefile.inc @@ -2,7 +2,7 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= mpfr -PKG_VERSION:= 4.1.0 +PKG_VERSION:= 4.2.1 PKG_RELEASE:= 1 -PKG_HASH:= 0c98a3f1732ff6ca4ea690552079da9c597872d30e96ec28414ee23c95558a7f +PKG_HASH:= 277807353a6726978996945af13e52829e3abd7a9a5b7fb2793894e18f1fcbb2 PKG_SITES:= http://www.mpfr.org/mpfr-current/ diff --git a/toolchain/musl/Makefile.inc b/toolchain/musl/Makefile.inc index c5db52f4f..b5e1800f0 100644 --- a/toolchain/musl/Makefile.inc +++ b/toolchain/musl/Makefile.inc @@ -8,10 +8,10 @@ PKG_RELEASE:= 1 PKG_SITES:= git://git.musl-libc.org/musl DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz endif -ifeq ($(ADK_TARGET_LIB_MUSL_1_2_3),y) -PKG_VERSION:= 1.2.3 +ifeq ($(ADK_TARGET_LIB_MUSL_1_2_5),y) +PKG_VERSION:= 1.2.5 PKG_RELEASE:= 1 -PKG_HASH:= 7d5b0b6062521e4627e099e4c9dc8248d32a30285e959b7eecaa780cf8cfd4a4 +PKG_HASH:= a9a118bbe84d8764da0ea0d28b3ab3fae8477fc7e4085d90102b8596fc7c75e4 PKG_SITES:= http://www.musl-libc.org/releases/ DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif diff --git a/toolchain/newlib/Makefile.inc b/toolchain/newlib/Makefile.inc index 591377022..c9ce3a2ad 100644 --- a/toolchain/newlib/Makefile.inc +++ b/toolchain/newlib/Makefile.inc @@ -8,17 +8,10 @@ PKG_RELEASE:= 1 PKG_SITES:= git://sourceware.org/git/newlib-cygwin.git DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz endif -ifeq ($(ADK_TARGET_LIB_NEWLIB_4_1_0),y) -PKG_VERSION:= 4.1.0 +ifeq ($(ADK_TARGET_LIB_NEWLIB_4_4_0),y) +PKG_VERSION:= 4.4.0.20231231 PKG_RELEASE:= 1 -PKG_HASH:= f296e372f51324224d387cc116dc37a6bd397198756746f93a2b02e9a5d40154 +PKG_HASH:= 0c166a39e1bf0951dfafcd68949fe0e4b6d3658081d6282f39aeefc6310f2f13 PKG_SITES:= ftp://sourceware.org/pub/newlib/ DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TARGET_LIB_NEWLIB_XTENSA),y) -PKG_VERSION:= xtensa -PKG_GIT:= branch -PKG_RELEASE:= 1 -PKG_SITES:= https://github.com/jcmvbkbc/newlib-xtensa.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz -endif diff --git a/toolchain/newlib/patches/3.1.0/fix-tooldir.patch b/toolchain/newlib/patches/3.1.0/fix-tooldir.patch deleted file mode 100644 index 652f7494b..000000000 --- a/toolchain/newlib/patches/3.1.0/fix-tooldir.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur newlib-2.2.0-1.orig/configure newlib-2.2.0-1/configure ---- newlib-2.2.0-1.orig/configure 2014-07-05 23:09:07.000000000 +0200 -+++ newlib-2.2.0-1/configure 2015-11-25 06:33:11.461178398 +0100 -@@ -6985,7 +6985,7 @@ - - # Some systems (e.g., one of the i386-aix systems the gas testers are - # using) don't handle "\$" correctly, so don't use it here. --tooldir='${exec_prefix}'/${target_noncanonical} -+tooldir='${exec_prefix}' - build_tooldir=${tooldir} - - # Create a .gdbinit file which runs the one in srcdir diff --git a/toolchain/newlib/patches/git/fix-tooldir.patch b/toolchain/newlib/patches/git/fix-tooldir.patch deleted file mode 100644 index 652f7494b..000000000 --- a/toolchain/newlib/patches/git/fix-tooldir.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur newlib-2.2.0-1.orig/configure newlib-2.2.0-1/configure ---- newlib-2.2.0-1.orig/configure 2014-07-05 23:09:07.000000000 +0200 -+++ newlib-2.2.0-1/configure 2015-11-25 06:33:11.461178398 +0100 -@@ -6985,7 +6985,7 @@ - - # Some systems (e.g., one of the i386-aix systems the gas testers are - # using) don't handle "\$" correctly, so don't use it here. --tooldir='${exec_prefix}'/${target_noncanonical} -+tooldir='${exec_prefix}' - build_tooldir=${tooldir} - - # Create a .gdbinit file which runs the one in srcdir diff --git a/toolchain/newlib/patches/newlib-xtensa/fix-tooldir.patch b/toolchain/newlib/patches/newlib-xtensa/fix-tooldir.patch deleted file mode 100644 index 1ad0f373d..000000000 --- a/toolchain/newlib/patches/newlib-xtensa/fix-tooldir.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur newlib-xtensa.orig/configure newlib-xtensa/configure ---- newlib-xtensa.orig/configure 2017-12-29 15:26:12.000000000 +0100 -+++ newlib-xtensa/configure 2017-12-29 15:35:01.420208845 +0100 -@@ -6847,7 +6847,7 @@ - - # Some systems (e.g., one of the i386-aix systems the gas testers are - # using) don't handle "\$" correctly, so don't use it here. --tooldir='${exec_prefix}'/${target_noncanonical} -+tooldir='${exec_prefix}' - build_tooldir=${tooldir} - - # Create a .gdbinit file which runs the one in srcdir diff --git a/toolchain/uclibc-ng/Makefile b/toolchain/uclibc-ng/Makefile index e07ab8ece..6b1fd31ce 100644 --- a/toolchain/uclibc-ng/Makefile +++ b/toolchain/uclibc-ng/Makefile @@ -50,8 +50,13 @@ UCLIBC_MAKEOPTS+= -j${ADK_MAKE_JOBS} endif $(WRKBUILD)/.configured: $(WRKBUILD)/.prepared +ifeq ($(ADK_TARGET_WITH_MMU),y) PATH='$(HOST_PATH)' sed -e 's^KERNEL_HEADERS.*$$KERNEL_HEADERS=\"${STAGING_TARGET_DIR}/usr/include\"' \ $(ADK_TOPDIR)/target/$(ADK_TARGET_ARCH)/uclibc-ng.config >${WRKBUILD}/.config +else + PATH='$(HOST_PATH)' sed -e 's^KERNEL_HEADERS.*$$KERNEL_HEADERS=\"${STAGING_TARGET_DIR}/usr/include\"' \ + $(ADK_TOPDIR)/target/$(ADK_TARGET_ARCH)/uclibc-ng-nommu.config >${WRKBUILD}/.config +endif $(SED) 's^.*\(CROSS_COMPILER_PREFIX\).*^\1=\"$(TARGET_CROSS)\"^' ${WRKBUILD}/.config ifeq ($(ADK_TARGET_ENDIAN),little) $(SED) 's/.*\(ARCH_LITTLE_ENDIAN\).*/\1=y/' ${WRKBUILD}/.config @@ -80,8 +85,16 @@ ifeq ($(ADK_TARGET_HARD_FLOAT_DP),y) $(SED) 's/.*\(UCLIBC_HAS_FPU\).*/\1=y/' ${WRKBUILD}/.config $(SED) 's/.*\(UCLIBC_HAS_SOFT_FLOAT\).*/# \1 is not set/' ${WRKBUILD}/.config endif +ifeq ($(ADK_TARGET_BINFMT_ELF),y) + $(SED) 's/.*\(UCLIBC_FORMAT_ELF\).*/\1=y/' ${WRKBUILD}/.config + $(SED) 's/.*\(UCLIBC_FORMAT_FDPIC_ELF\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(UCLIBC_FORMAT_FLAT\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(UCLIBC_FORMAT_FLAT_SEP_DATA\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(UCLIBC_FORMAT_SHARED_FLAT\).*/# \1 is not set/' ${WRKBUILD}/.config +endif ifeq ($(ADK_TARGET_BINFMT_FDPIC),y) $(SED) 's/.*\(UCLIBC_FORMAT_FDPIC_ELF\).*/\1=y/' ${WRKBUILD}/.config + $(SED) 's/.*\(UCLIBC_FORMAT_ELF\).*/# \1 is not set/' ${WRKBUILD}/.config $(SED) 's/.*\(UCLIBC_FORMAT_FLAT\).*/# \1 is not set/' ${WRKBUILD}/.config $(SED) 's/.*\(UCLIBC_FORMAT_FLAT_SEP_DATA\).*/# \1 is not set/' ${WRKBUILD}/.config $(SED) 's/.*\(UCLIBC_FORMAT_SHARED_FLAT\).*/# \1 is not set/' ${WRKBUILD}/.config @@ -174,12 +187,19 @@ endif # arc ifeq ($(ADK_TARGET_ARCH_ARC),y) ifeq ($(ADK_TARGET_CPU_ARC_ARC700),y) - $(SED) 's/.*\(CONFIG_ARC_CPU_HS\).*/# \1 is not set/' ${WRKBUILD}/.config - $(SED) 's/.*\(CONFIG_ARC_CPU_700\).*/\1=y/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_16K\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_4K\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_8K\).*/\1=y/' ${WRKBUILD}/.config +endif +ifeq ($(ADK_TARGET_CPU_ARC_ARCHS),y) + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_16K\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_4K\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_8K\).*/\1=y/' ${WRKBUILD}/.config endif -ifeq ($(ADK_TARGET_CPU_ARC_ARC_HS),y) - $(SED) 's/.*\(CONFIG_ARC_CPU_700\).*/# \1 is not set/' ${WRKBUILD}/.config - $(SED) 's/.*\(CONFIG_ARC_CPU_HS\).*/\1=y/' ${WRKBUILD}/.config +ifeq ($(ADK_TARGET_CPU_ARC_ARC32),y) + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_16K\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_8K\).*/# \1 is not set/' ${WRKBUILD}/.config + $(SED) 's/.*\(CONFIG_ARC_PAGE_SIZE_4K\).*/\1=y/' ${WRKBUILD}/.config endif endif @@ -368,6 +388,8 @@ $(WRKBUILD)/.installed: $(WRKBUILD)/.compiled UCLIBC_EXTRA_LDFLAGS="$(TARGET_LDFLAGS)" \ VERBOSE=1 \ install_runtime install_dev + ln -f ${STAGING_TARGET_DIR}/usr/lib/crt1.o \ + ${STAGING_TARGET_DIR}/usr/lib/Scrt1.o ifeq ($(ADK_TARGET_LIBC_UTILS),y) PATH='$(HOST_PATH)' $(MAKE) -C $(WRKBUILD) \ ARCH="$(ADK_TARGET_ARCH)" \ diff --git a/toolchain/uclibc-ng/Makefile.inc b/toolchain/uclibc-ng/Makefile.inc index 7d1bf4d1f..c4b4745fa 100644 --- a/toolchain/uclibc-ng/Makefile.inc +++ b/toolchain/uclibc-ng/Makefile.inc @@ -7,10 +7,10 @@ PKG_VERSION:= git PKG_RELEASE:= 1 PKG_SITES:= https://git.uclibc-ng.org/git/uclibc-ng.git endif -ifeq ($(ADK_TARGET_LIB_UCLIBC_NG_1_0_40),y) -PKG_VERSION:= 1.0.40 +ifeq ($(ADK_TARGET_LIB_UCLIBC_NG_1_0_47),y) +PKG_VERSION:= 1.0.47 PKG_RELEASE:= 1 -PKG_SITES:= http://downloads.uclibc-ng.org/releases/1.0.40/ -PKG_HASH:= d863f01815a64174d5019c73475e8aff5b60848a13876e79daf5d3d83ce7f889 +PKG_SITES:= http://downloads.uclibc-ng.org/releases/1.0.47/ +PKG_HASH:= c58640ba7c2ce70f09574365bc8039cf580b52e1ce369db527376891b2249028 endif -DISTFILES:= $(PKG_NAME)-$(PKG_VERSION).tar.xz +DISTFILES:= $(PKG_NAME)-$(PKG_VERSION).tar.gz |