diff options
Diffstat (limited to 'toolchain/binutils')
| -rw-r--r-- | toolchain/binutils/Makefile | 8 | ||||
| -rw-r--r-- | toolchain/binutils/Makefile.inc | 63 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.20.1/newer-gcc.patch | 24 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.28/lm32.patch | 24 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.37/0001-i386-Allow-GOT32-relocations-against-ABS-symbols.patch | 47 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.37/nds32-uclibc.patch | 15 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.38/0001-binutils-2.38-vs.-ppc32-linux-kernel.patch | 55 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.38/nds32-uclibc.patch | 15 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.41/lm32.patch | 24 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.42/j2.patch | 584 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.42/kvx.patch | 29 |
11 files changed, 865 insertions, 23 deletions
diff --git a/toolchain/binutils/Makefile b/toolchain/binutils/Makefile index 7136cf66e..63b1080fb 100644 --- a/toolchain/binutils/Makefile +++ b/toolchain/binutils/Makefile @@ -28,6 +28,10 @@ else CONFOPTS+= --disable-gold endif +ifeq ($(ADK_TARGET_ARCH_ARC),y) +CONFOPTS+= --enable-lto --enable-plugins +endif + ifeq ($(ADK_TARGET_ARCH_X86_64)$(ADK_TARGET_CPU_CF),) CONFOPTS+= --disable-multilib else @@ -44,7 +48,6 @@ ifeq ($(ADK_TARGET_ARCH_XTENSA),y) --strip-components=1 -C $(WRKSRC) binutils endif (cd $(WRKBUILD); PATH='$(HOST_PATH)' \ - LDFLAGS=-ldl \ MAKEINFO=true \ M4='${STAGING_HOST_DIR}/usr/bin/m4' \ $(WRKBUILD)/configure \ @@ -58,6 +61,7 @@ endif --disable-gdb \ --enable-obsolete \ --disable-werror \ + --disable-gprof \ --disable-install-libiberty \ ${CONFOPTS} \ ); @@ -70,7 +74,7 @@ $(WRKBUILD)/.compiled: $(WRKBUILD)/.configured $(WRKBUILD)/.installed: $(WRKBUILD)/.compiled PATH='$(HOST_PATH)' $(MAKE) MAKEINFO=true -C $(WRKBUILD) install -ifeq ($(ADK_TARGET_ARCH_H8300)$(ADK_TARGET_ARCH_NDS32)$(ADK_TARGET_ARCH_SH),y) +ifeq ($(ADK_TARGET_ARCH_KVX)$(ADK_TARGET_ARCH_H8300)$(ADK_TARGET_ARCH_NDS32)$(ADK_TARGET_ARCH_SH),y) $(INSTALL_DIR) $(STAGING_TARGET_DIR)/usr/lib/ldscripts $(CP) $(WRKBUILD)/ld/ldscripts/* $(STAGING_TARGET_DIR)/usr/lib/ldscripts/ endif diff --git a/toolchain/binutils/Makefile.inc b/toolchain/binutils/Makefile.inc index ac252de32..758539cf0 100644 --- a/toolchain/binutils/Makefile.inc +++ b/toolchain/binutils/Makefile.inc @@ -2,40 +2,61 @@ # material, please see the LICENCE file in the top-level directory. PKG_NAME:= binutils -ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_37),y) -PKG_VERSION:= 2.37 +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_42),y) +PKG_VERSION:= 2.42 PKG_RELEASE:= 1 -PKG_HASH:= 820d9724f020a3e69cb337893a0b63c2db161dadcb0e06fc11dc29eb1e84a32c +PKG_HASH:= 5d2a6c1d49686a557869caae08b6c2e83699775efd27505e01b2f4db1a024ffc PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_28),y) -PKG_VERSION:= 2.28 +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_41),y) +PKG_VERSION:= 2.41 PKG_RELEASE:= 1 -PKG_HASH:= cd717966fc761d840d451dbd58d44e1e5b92949d2073d75b73fccb476d772fcf +PKG_HASH:= 48d00a8dc73aa7d2394a7dc069b96191d95e8de8f0da6dc91da5cce655c20e45 PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_ARC),y) -PKG_VERSION:= arc-2020.09 -PKG_GIT:= tag -PKG_RELEASE:= 1 -PKG_SITES:= https://github.com/foss-for-synopsys-dwc-arc-processors/binutils-gdb.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_40),y) +PKG_VERSION:= 2.40 +PKG_RELEASE:= 1 +PKG_HASH:= d7f82c4047decf43a6f769ac32456a92ddb6932409a585c633cdd4e9df23d956 +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_39),y) +PKG_VERSION:= 2.39 +PKG_RELEASE:= 1 +PKG_HASH:= d12ea6f239f1ffe3533ea11ad6e224ffcb89eb5d01bbea589e9158780fa11f10 +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_38),y) +PKG_VERSION:= 2.38 +PKG_RELEASE:= 1 +PKG_HASH:= b3f1dc5b17e75328f19bd88250bee2ef9f91fc8cbb7bd48bdb31390338636052 +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz +endif +ifeq ($(ADK_TOOLCHAIN_BINUTILS_2_37),y) +PKG_VERSION:= 2.37 +PKG_RELEASE:= 1 +PKG_HASH:= c44968b97cd86499efbc4b4ab7d98471f673e5414c554ef54afa930062dbbfcb +PKG_SITES:= ${MASTER_SITE_GNU:=binutils/} +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_BINUTILS_KVX),y) -PKG_VERSION:= c5e8437af055869c8666a1c1e5a391d9af5be0c0 +PKG_VERSION:= 782547a4e2bdf1308728032853678ca69bb154ea PKG_GIT:= hash PKG_RELEASE:= 1 PKG_SITES:= https://github.com/kalray/gdb-binutils.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif -ifeq ($(ADK_TOOLCHAIN_BINUTILS_NDS32),y) -PKG_VERSION:= nds32-binutils-2.30-branch-open -PKG_GIT:= branch +ifeq ($(ADK_TOOLCHAIN_BINUTILS_ARC),y) +PKG_VERSION:= arc-2023.09 +PKG_GIT:= tag PKG_RELEASE:= 1 -PKG_SITES:= https://github.com/andestech/binutils.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +PKG_SITES:= https://github.com/foss-for-synopsys-dwc-arc-processors/binutils-gdb.git +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif ifeq ($(ADK_TOOLCHAIN_BINUTILS_AVR32),y) PKG_VERSION:= 2.20.1 @@ -48,5 +69,5 @@ ifeq ($(ADK_TOOLCHAIN_BINUTILS_GIT),y) PKG_VERSION:= git PKG_RELEASE:= 1 PKG_SITES:= git://sourceware.org/git/binutils-gdb.git -DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz +DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.gz endif diff --git a/toolchain/binutils/patches/2.20.1/newer-gcc.patch b/toolchain/binutils/patches/2.20.1/newer-gcc.patch new file mode 100644 index 000000000..b7f42e447 --- /dev/null +++ b/toolchain/binutils/patches/2.20.1/newer-gcc.patch @@ -0,0 +1,24 @@ +diff -Nur binutils-2.20.1.orig/binutils/readelf.c binutils-2.20.1/binutils/readelf.c +--- binutils-2.20.1.orig/binutils/readelf.c 2023-02-03 11:04:53.722082738 +0100 ++++ binutils-2.20.1/binutils/readelf.c 2023-02-03 11:05:27.049296372 +0100 +@@ -150,7 +150,7 @@ + #include "filenames.h" + + char * program_name = "readelf"; +-int do_wide; ++extern int do_wide; + static long archive_file_offset; + static unsigned long archive_file_size; + static unsigned long dynamic_addr; +diff -Nur binutils-2.20.1.orig/gas/config/tc-avr32.c binutils-2.20.1/gas/config/tc-avr32.c +--- binutils-2.20.1.orig/gas/config/tc-avr32.c 2023-02-03 11:04:53.726082644 +0100 ++++ binutils-2.20.1/gas/config/tc-avr32.c 2023-02-03 11:06:12.164234434 +0100 +@@ -47,7 +47,7 @@ + + /* Flags given on the command line */ + static int avr32_pic = FALSE; +-int linkrelax = FALSE; ++//extern int linkrelax = FALSE; + int avr32_iarcompat = FALSE; + + /* This array holds the chars that always start a comment. */ diff --git a/toolchain/binutils/patches/2.28/lm32.patch b/toolchain/binutils/patches/2.28/lm32.patch new file mode 100644 index 000000000..962281625 --- /dev/null +++ b/toolchain/binutils/patches/2.28/lm32.patch @@ -0,0 +1,24 @@ +diff -Nur binutils-2.28.orig/bfd/config.bfd binutils-2.28/bfd/config.bfd +--- binutils-2.28.orig/bfd/config.bfd 2017-03-02 09:23:53.000000000 +0100 ++++ binutils-2.28/bfd/config.bfd 2023-08-27 11:54:08.526040118 +0200 +@@ -924,7 +924,7 @@ + ;; + + lm32-*-*linux*) +- targ_defvec=lm32_elf32_fdpic_vec ++ targ_defvec=lm32_elf32_vec + targ_selvecs=lm32_elf32_vec + ;; + +diff -Nur binutils-2.28.orig/ld/configure.tgt binutils-2.28/ld/configure.tgt +--- binutils-2.28.orig/ld/configure.tgt 2017-03-02 09:23:54.000000000 +0100 ++++ binutils-2.28/ld/configure.tgt 2023-08-27 11:54:43.882874903 +0200 +@@ -416,7 +416,7 @@ + ;; + iq2000-*-elf) targ_emul=elf32iq2000 ; targ_extra_emuls="elf32iq10" + ;; +-lm32-*-*linux*) targ_emul=elf32lm32fd ;; ++lm32-*-*linux*) targ_emul=elf32lm32 ;; + lm32-*-*) targ_emul=elf32lm32 ; targ_extra_emuls="elf32lm32fd" + ;; + m32c-*-elf | m32c-*-rtems*) diff --git a/toolchain/binutils/patches/2.37/0001-i386-Allow-GOT32-relocations-against-ABS-symbols.patch b/toolchain/binutils/patches/2.37/0001-i386-Allow-GOT32-relocations-against-ABS-symbols.patch new file mode 100644 index 000000000..3e2928226 --- /dev/null +++ b/toolchain/binutils/patches/2.37/0001-i386-Allow-GOT32-relocations-against-ABS-symbols.patch @@ -0,0 +1,47 @@ +From 30a954525f4e53a9cd50a1a8a6f201c7cf6595c7 Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" <hjl.tools@gmail.com> +Date: Mon, 7 Feb 2022 15:22:19 -0800 +Subject: [PATCH] i386: Allow GOT32 relocations against ABS symbols + +GOT32 relocations are allowed since absolute value + addend is stored in +the GOT slot. + +Tested on glibc 2.35 build with GCC 11.2 and -Os. + +bfd/ + + PR ld/28870 + * elfxx-x86.c (_bfd_elf_x86_valid_reloc_p): Also allow GOT32 + relocations. + + +Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> + +diff --git a/bfd/elfxx-x86.c b/bfd/elfxx-x86.c +index 7ac2411fc80..d00dc45677b 100644 +--- a/bfd/elfxx-x86.c ++++ b/bfd/elfxx-x86.c +@@ -1942,9 +1942,9 @@ _bfd_elf_x86_valid_reloc_p (asection *input_section, + irel = *rel; + + /* Only allow relocations against absolute symbol, which can be +- resolved as absolute value + addend. GOTPCREL relocations +- are allowed since absolute value + addend is stored in the +- GOT slot. */ ++ resolved as absolute value + addend. GOTPCREL and GOT32 ++ relocations are allowed since absolute value + addend is ++ stored in the GOT slot. */ + if (bed->target_id == X86_64_ELF_DATA) + { + r_type &= ~R_X86_64_converted_reloc_bit; +@@ -1965,7 +1965,9 @@ _bfd_elf_x86_valid_reloc_p (asection *input_section, + else + valid_p = (r_type == R_386_32 + || r_type == R_386_16 +- || r_type == R_386_8); ++ || r_type == R_386_8 ++ || r_type == R_386_GOT32 ++ || r_type == R_386_GOT32X); + + if (valid_p) + *no_dynreloc_p = true; diff --git a/toolchain/binutils/patches/2.37/nds32-uclibc.patch b/toolchain/binutils/patches/2.37/nds32-uclibc.patch new file mode 100644 index 000000000..b14e98511 --- /dev/null +++ b/toolchain/binutils/patches/2.37/nds32-uclibc.patch @@ -0,0 +1,15 @@ +diff -Nur binutils-2.37.orig/ld/configure.tgt binutils-2.37/ld/configure.tgt +--- binutils-2.37.orig/ld/configure.tgt 2021-07-08 13:37:20.000000000 +0200 ++++ binutils-2.37/ld/configure.tgt 2022-01-21 03:23:49.296011413 +0100 +@@ -594,9 +594,9 @@ + nds32*be-*-elf*) targ_emul=nds32belf + targ_extra_emuls="nds32elf nds32elf16m nds32belf16m" + ;; +-nds32*le-*-linux-gnu*) targ_emul=nds32elf_linux ++nds32*le-*-linux-*) targ_emul=nds32elf_linux + ;; +-nds32*be-*-linux-gnu*) targ_emul=nds32belf_linux ++nds32*be-*-linux-*) targ_emul=nds32belf_linux + ;; + nios2*-*-linux*) targ_emul=nios2linux + ;; diff --git a/toolchain/binutils/patches/2.38/0001-binutils-2.38-vs.-ppc32-linux-kernel.patch b/toolchain/binutils/patches/2.38/0001-binutils-2.38-vs.-ppc32-linux-kernel.patch new file mode 100644 index 000000000..c62652c95 --- /dev/null +++ b/toolchain/binutils/patches/2.38/0001-binutils-2.38-vs.-ppc32-linux-kernel.patch @@ -0,0 +1,55 @@ +From ed9b2e40ebffec835d63473367da8dd8f80d7d5b Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@gmail.com> +Date: Mon, 21 Feb 2022 10:58:57 +1030 +Subject: [PATCH] binutils 2.38 vs. ppc32 linux kernel + +Commit b25f942e18d6 made .machine more strict. Weaken it again. + + * config/tc-ppc.c (ppc_machine): Treat an early .machine specially, + keeping sticky options to work around gcc bugs. + +(cherry picked from commit cebc89b9328eab994f6b0314c263f94e7949a553) +Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> +--- + gas/config/tc-ppc.c | 25 ++++++++++++++++++++++++- + 1 file changed, 24 insertions(+), 1 deletion(-) + +diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c +index 054f9c72161..89bc7d3f9b9 100644 +--- a/gas/config/tc-ppc.c ++++ b/gas/config/tc-ppc.c +@@ -5965,7 +5965,30 @@ ppc_machine (int ignore ATTRIBUTE_UNUSED) + options do not count as a new machine, instead they add + to currently selected opcodes. */ + ppc_cpu_t machine_sticky = 0; +- new_cpu = ppc_parse_cpu (ppc_cpu, &machine_sticky, cpu_string); ++ /* Unfortunately, some versions of gcc emit a .machine ++ directive very near the start of the compiler's assembly ++ output file. This is bad because it overrides user -Wa ++ cpu selection. Worse, there are versions of gcc that ++ emit the *wrong* cpu, not even respecting the -mcpu given ++ to gcc. See gcc pr101393. And to compound the problem, ++ as of 20220222 gcc doesn't pass the correct cpu option to ++ gas on the command line. See gcc pr59828. Hack around ++ this by keeping sticky options for an early .machine. */ ++ asection *sec; ++ for (sec = stdoutput->sections; sec != NULL; sec = sec->next) ++ { ++ segment_info_type *info = seg_info (sec); ++ /* Are the frags for this section perturbed from their ++ initial state? Even .align will count here. */ ++ if (info != NULL ++ && (info->frchainP->frch_root != info->frchainP->frch_last ++ || info->frchainP->frch_root->fr_type != rs_fill ++ || info->frchainP->frch_root->fr_fix != 0)) ++ break; ++ } ++ new_cpu = ppc_parse_cpu (ppc_cpu, ++ sec == NULL ? &sticky : &machine_sticky, ++ cpu_string); + if (new_cpu != 0) + ppc_cpu = new_cpu; + else +-- +2.30.2 + diff --git a/toolchain/binutils/patches/2.38/nds32-uclibc.patch b/toolchain/binutils/patches/2.38/nds32-uclibc.patch new file mode 100644 index 000000000..b14e98511 --- /dev/null +++ b/toolchain/binutils/patches/2.38/nds32-uclibc.patch @@ -0,0 +1,15 @@ +diff -Nur binutils-2.37.orig/ld/configure.tgt binutils-2.37/ld/configure.tgt +--- binutils-2.37.orig/ld/configure.tgt 2021-07-08 13:37:20.000000000 +0200 ++++ binutils-2.37/ld/configure.tgt 2022-01-21 03:23:49.296011413 +0100 +@@ -594,9 +594,9 @@ + nds32*be-*-elf*) targ_emul=nds32belf + targ_extra_emuls="nds32elf nds32elf16m nds32belf16m" + ;; +-nds32*le-*-linux-gnu*) targ_emul=nds32elf_linux ++nds32*le-*-linux-*) targ_emul=nds32elf_linux + ;; +-nds32*be-*-linux-gnu*) targ_emul=nds32belf_linux ++nds32*be-*-linux-*) targ_emul=nds32belf_linux + ;; + nios2*-*-linux*) targ_emul=nios2linux + ;; diff --git a/toolchain/binutils/patches/2.41/lm32.patch b/toolchain/binutils/patches/2.41/lm32.patch new file mode 100644 index 000000000..dcbb0d541 --- /dev/null +++ b/toolchain/binutils/patches/2.41/lm32.patch @@ -0,0 +1,24 @@ +diff -Nur binutils-2.41.orig/bfd/config.bfd binutils-2.41/bfd/config.bfd +--- binutils-2.41.orig/bfd/config.bfd 2023-07-03 01:00:00.000000000 +0200 ++++ binutils-2.41/bfd/config.bfd 2023-09-07 17:03:12.853045008 +0200 +@@ -803,7 +803,7 @@ + ;; + + lm32-*-*linux*) +- targ_defvec=lm32_elf32_fdpic_vec ++ targ_defvec=lm32_elf32_vec + targ_selvecs=lm32_elf32_vec + ;; + +diff -Nur binutils-2.41.orig/ld/configure.tgt binutils-2.41/ld/configure.tgt +--- binutils-2.41.orig/ld/configure.tgt 2023-07-03 01:00:00.000000000 +0200 ++++ binutils-2.41/ld/configure.tgt 2023-09-07 17:03:44.364298973 +0200 +@@ -468,7 +468,7 @@ + targ_extra_emuls="elf32iq10" + targ_extra_ofiles=ldelfgen.o + ;; +-lm32-*-*linux*) targ_emul=elf32lm32fd ++lm32-*-*linux*) targ_emul=elf32lm32 + ;; + lm32-*-*) targ_emul=elf32lm32 + targ_extra_emuls="elf32lm32fd" diff --git a/toolchain/binutils/patches/2.42/j2.patch b/toolchain/binutils/patches/2.42/j2.patch new file mode 100644 index 000000000..42c7274aa --- /dev/null +++ b/toolchain/binutils/patches/2.42/j2.patch @@ -0,0 +1,584 @@ +diff -Nur binutils-2.42.orig/bfd/archures.c binutils-2.42/bfd/archures.c +--- binutils-2.42.orig/bfd/archures.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/bfd/archures.c 2024-02-22 16:50:03.657904349 +0100 +@@ -284,10 +284,12 @@ + .#define bfd_mach_sh_dsp 0x2d + .#define bfd_mach_sh2a 0x2a + .#define bfd_mach_sh2a_nofpu 0x2b ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +diff -Nur binutils-2.42.orig/bfd/bfd-in2.h binutils-2.42/bfd/bfd-in2.h +--- binutils-2.42.orig/bfd/bfd-in2.h 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/bfd/bfd-in2.h 2024-02-22 16:50:03.661904381 +0100 +@@ -1540,10 +1540,12 @@ + #define bfd_mach_sh_dsp 0x2d + #define bfd_mach_sh2a 0x2a + #define bfd_mach_sh2a_nofpu 0x2b ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +diff -Nur binutils-2.42.orig/bfd/cpu-sh.c binutils-2.42/bfd/cpu-sh.c +--- binutils-2.42.orig/bfd/cpu-sh.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/bfd/cpu-sh.c 2024-02-22 16:50:03.661904381 +0100 +@@ -63,7 +63,9 @@ + N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16), + N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17), + N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", false, arch_info_struct + 18), +- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL) ++ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, arch_info_struct + 19), ++ N (bfd_mach_shj2, "j2", false, arch_info_struct + 20), ++ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-nofpu-or-sh3-nommu-or-j2-nofpu", false, NULL) + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -99,6 +101,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +diff -Nur binutils-2.42.orig/binutils/readelf.c binutils-2.42/binutils/readelf.c +--- binutils-2.42.orig/binutils/readelf.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/binutils/readelf.c 2024-02-22 16:53:19.799614987 +0100 +@@ -4326,6 +4326,12 @@ + case EF_SH2A_SH3E: + out = stpcpy (out, ", sh2a-or-sh3e"); + break; ++ case EF_SHJ2: ++ out = stpcpy (out, ", j2"); ++ break; ++ case EF_SH2A_SH3_SHJ2: ++ out = stpcpy (out, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); ++ break; + default: + out = stpcpy (out, _(", unknown ISA")); + break; +diff -Nur binutils-2.42.orig/gas/config/tc-sh.c binutils-2.42/gas/config/tc-sh.c +--- binutils-2.42.orig/gas/config/tc-sh.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/config/tc-sh.c 2024-02-22 16:50:03.685904574 +0100 +@@ -1251,6 +1251,8 @@ + if (*ptr == ',') + ptr++; + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + } + } +@@ -1775,7 +1777,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2024-02-22 16:50:03.685904574 +0100 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2024-02-22 16:50:03.685904574 +0100 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2024-02-22 16:50:03.685904574 +0100 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2024-02-22 16:50:03.689904606 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2024-02-22 16:50:03.689904606 +0100 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.42/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh2a.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh2a.s 2024-02-22 16:50:03.689904606 +0100 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3-dsp.s 2024-02-22 16:50:03.689904606 +0100 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3e.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3e.s 2024-02-22 16:50:03.689904606 +0100 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3-nommu.s 2024-02-22 16:50:03.689904606 +0100 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.42/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh3.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh3.s 2024-02-22 16:50:03.689904606 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2024-02-22 16:50:03.689904606 +0100 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2024-02-22 16:50:03.693904638 +0100 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4a.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4a.s 2024-02-22 16:50:03.693904638 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2024-02-22 16:50:03.693904638 +0100 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2024-02-22 16:50:03.693904638 +0100 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.42/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.42.orig/gas/testsuite/gas/sh/arch/sh4.s 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/gas/testsuite/gas/sh/arch/sh4.s 2024-02-22 16:50:03.693904638 +0100 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.42.orig/include/elf/sh.h binutils-2.42/include/elf/sh.h +--- binutils-2.42.orig/include/elf/sh.h 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/include/elf/sh.h 2024-02-22 16:50:03.693904638 +0100 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -Nur binutils-2.42.orig/opcodes/sh-dis.c binutils-2.42/opcodes/sh-dis.c +--- binutils-2.42.orig/opcodes/sh-dis.c 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/opcodes/sh-dis.c 2024-02-22 16:50:03.693904638 +0100 +@@ -866,6 +866,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +diff -Nur binutils-2.42.orig/opcodes/sh-opc.h binutils-2.42/opcodes/sh-opc.h +--- binutils-2.42.orig/opcodes/sh-opc.h 2024-01-29 01:00:00.000000000 +0100 ++++ binutils-2.42/opcodes/sh-opc.h 2024-02-22 16:50:03.697904670 +0100 +@@ -192,7 +192,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -216,9 +217,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -256,6 +259,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -320,7 +325,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -346,6 +352,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -714,9 +726,9 @@ + + /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1194,7 +1206,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + diff --git a/toolchain/binutils/patches/2.42/kvx.patch b/toolchain/binutils/patches/2.42/kvx.patch new file mode 100644 index 000000000..c3690ca8e --- /dev/null +++ b/toolchain/binutils/patches/2.42/kvx.patch @@ -0,0 +1,29 @@ +From 234938d8b7df2f069c6cbbaff47eb2ba338ec532 Mon Sep 17 00:00:00 2001 +From: Paul Iannetta <piannetta@kalrayinc.com> +Date: Mon, 4 Sep 2023 15:31:53 +0200 +Subject: [PATCH] kvx: gas: fix the detection of negative powers of 2 + +gas/ChangeLog: + +2023-09-04 Paul Iannetta <piannetta@kalrayinc.com> + + * config/kvx-parse.c (get_token_class): Use the signed value. + +--- + gas/config/kvx-parse.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gas/config/kvx-parse.c b/gas/config/kvx-parse.c +index bb51c861625..0bd6b75ef30 100644 +--- a/gas/config/kvx-parse.c ++++ b/gas/config/kvx-parse.c +@@ -525,7 +525,7 @@ get_token_class (struct token_s *token, struct token_classes *classes, int insn_ + : strtoull (tok + (tok[0] == '-') + (tok[0] == '+'), NULL, 0)); + int64_t val = uval; + int64_t pval = val < 0 ? -uval : uval; +- int neg_power2_p = val < 0 && !(uval & (uval - 1)); ++ int neg_power2_p = val < 0 && !(pval & (pval - 1)); + unsigned len = pval ? 8 * sizeof (pval) - __builtin_clzll (pval) : 0; + while (class[cur].class_id != -1 + && ((unsigned) (class[cur].sz < 0 + |