diff options
Diffstat (limited to 'target/or1k')
| -rw-r--r-- | target/or1k/Makefile | 4 | ||||
| -rw-r--r-- | target/or1k/or1ksim.cfg | 888 | ||||
| -rw-r--r-- | target/or1k/systems/or1k-sim | 1 |
3 files changed, 893 insertions, 0 deletions
diff --git a/target/or1k/Makefile b/target/or1k/Makefile index dc40475f7..31f8e8aab 100644 --- a/target/or1k/Makefile +++ b/target/or1k/Makefile @@ -27,6 +27,10 @@ endif ifeq ($(ADK_TARGET_FS),initramfspiggyback) targethelp: @echo 'The kernel+initramfs file is: $(FW_DIR)/${TARGET_KERNEL}' +ifeq ($(ADK_TARGET_SYSTEM_OR1K_SIM),y) + @echo "Start or1ksim via:" + @echo 'sim -f target/or1k/or1ksim.cfg $(FW_DIR)/${TARGET_KERNEL}' +endif ifeq ($(ADK_TARGET_QEMU),y) @echo "Start qemu with following command line:" @echo 'qemu-system-or32 ${QEMU_ARGS} -kernel $(FW_DIR)/$(TARGET_KERNEL)' diff --git a/target/or1k/or1ksim.cfg b/target/or1k/or1ksim.cfg new file mode 100644 index 000000000..47ed45998 --- /dev/null +++ b/target/or1k/or1ksim.cfg @@ -0,0 +1,888 @@ +/* sim.cfg -- Simulator configuration script file + Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. +It contains the default configuration and help about configuring +the simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* INTRODUCTION + + The ork1sim has various parameters, that are set in configuration files + like this one. The user can switch between configurations at startup by + specifying the required configuration file with the -f <filename.cfg> option. + If no configuration file is specified or1ksim searches for the default + configuration file sim.cfg. First it searches for './sim.cfg'. If this + file is not found, it searches for '~/or1k/sim.cfg'. If this file is + not found too, it reverts to the built-in default configuration. + + NOTE: Users should not rely on the built-in configuration, since the + default configuration may differ between version. + Rather create a configuration file that sets all critical values. + + This file may contain (standard C) comments only - no // support. + + Configure files may be be included, using: + include "file_name_to_include" + + Like normal configuration files, the included file is divided into + sections. Each section is described in detail also. + + Some section have subsections. One example of such a subsection is: + + device <index> + instance specific parameters... + enddevice + + which creates a device instance. +*/ + + +/* MEMORY SECTION + + This section specifies how the memory is generated and the blocks + it consists of. + + type = random/unknown/pattern + Specifies the initial memory values. + 'random' generates random memory using seed 'random_seed'. + 'pattern' fills memory with 'pattern'. + 'unknown' does not specify how memory should be generated, + leaving the memory in a undefined state. This is the fastest + option. + + random_seed = <value> + random seed for randomizer, used if type = 'random'. + + pattern = <value> + pattern to fill memory, used if type = 'pattern'. + + nmemories = <value> + number of memory instances connected + + baseaddr = <hex_value> + memory start address + + size = <hex_value> + memory size + + name = "<string>" + memory block name + + ce = <value> + chip enable index of the memory instance + + mc = <value> + memory controller this memory is connected to + + delayr = <value> + cycles, required for read access, -1 if instance does not support reading + + delayw = <value> + cycles, required for write access, -1 if instance does not support writing + + log = "<filename>" + filename, where to log memory accesses to, no log, if log command is not specified +*/ + + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "FLASH" + ce = 0 + mc = 0 + baseaddr = 0xf0000000 + size = 0x01000000 + delayr = 1 + delayw = -1 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "RAM" + ce = 1 + mc = 0 + baseaddr = 0x00000000 + size = 0x02000000 + delayr = 1 + delayw = 1 +end + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + name = "SRAM" + mc = 0 + ce = 2 + baseaddr = 0xa4000000 + size = 0x00100000 + delayr = 1 + delayw = 2 +end + + +/* IMMU SECTION + + This section configures the Instruction Memory Manangement Unit + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of ITLB sets; must be power of two + + nways = <value> + number of ITLB ways + + pagesize = <value> + instruction page size; must be power of two + + entrysize = <value> + instruction entry size in bytes + + ustates = <value> + number of ITLB usage states (2, 3, 4 etc., max is 4) + + hitdelay = <value> + number of cycles immu hit costs + + missdelay = <value> + number of cycles immu miss costs +*/ + +section immu + enabled = 1 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end + + +/* DMMU SECTION + + This section configures the Data Memory Manangement Unit + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of DTLB sets; must be power of two + + nways = <value> + number of DTLB ways + + pagesize = <value> + data page size; must be power of two + + entrysize = <value> + data entry size in bytes + + ustates = <value> + number of DTLB usage states (2, 3, 4 etc., max is 4) + + hitdelay = <value> + number of cycles dmmu hit costs + + missdelay = <value> + number of cycles dmmu miss costs +*/ + +section dmmu + enabled = 1 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end + + +/* IC SECTION + + This section configures the Instruction Cache + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of IC sets; must be power of two + + nways = <value> + number of IC ways + + blocksize = <value> + IC block size in bytes; must be power of two + + ustates = <value> + number of IC usage states (2, 3, 4 etc., max is 4) + + hitdelay = <value> + number of cycles ic hit costs + + missdelay = <value> + number of cycles ic miss costs +*/ + +section ic + enabled = 0 + nsets = 512 + nways = 1 + blocksize = 16 + hitdelay = 1 + missdelay = 1 +end + + +/* DC SECTION + + This section configures the Data Cache + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of DC sets; must be power of two + + nways = <value> + number of DC ways + + blocksize = <value> + DC block size in bytes; must be power of two + + ustates = <value> + number of DC usage states (2, 3, 4 etc., max is 4) + + load_hitdelay = <value> + number of cycles dc load hit costs + + load_missdelay = <value> + number of cycles dc load miss costs + + store_hitdelay = <value> + number of cycles dc load hit costs + + store_missdelay = <value> + number of cycles dc load miss costs +*/ + +section dc + enabled = 0 + nsets = 512 + nways = 1 + blocksize = 16 + load_hitdelay = 1 + load_missdelay = 1 + store_hitdelay = 1 + store_missdelay = 1 +end + + +/* SIM SECTION + + This section specifies how or1ksim should behave. + + verbose = 0/1 + '0': don't print extra messages + '1': print extra messages + + debug = 0-9 + 0 : no debug messages + 1-9: debug message level. + higher numbers produce more messages + + profile = 0/1 + '0': don't generate profiling file 'sim.profile' + '1': don't generate profiling file 'sim.profile' + + prof_fn = "<filename>" + optional filename for the profiling file. + valid only if 'profile' is set + + mprofile = 0/1 + '0': don't generate memory profiling file 'sim.mprofile' + '1': generate memory profiling file 'sim.mprofile' + + mprof_fn = "<filename>" + optional filename for the memory profiling file. + valid only if 'mprofile' is set + + history = 0/1 + '0': don't track execution flow + '1': track execution flow + Execution flow can be tracked for the simulator's + 'hist' command. Useful for back-trace debugging. + + iprompt = 0/1 + '0': start in <not interactive prompt> (so what do we start in ???) + '1': start in interactive prompt. + + exe_log = 0/1 + '0': don't generate execution log. + '1': generate execution log. + + exe_log = default/hardware/simple/software + type of execution log, default is used when not specified + + exe_log_start = <value> + index of first instruction to start logging, default = 0 + + exe_log_end = <value> + index of last instruction to end logging; not limited, if omitted + + exe_log_marker = <value> + <value> specifies number of instructions before horizontal marker is + printed; if zero, markers are disabled (default) + + exe_log_fn = "<filename>" + filename for the exection log file. + valid only if 'exe_log' is set + + clkcycle = <value>[ps|ns|us|ms] + specifies time measurement for one cycle +*/ + +section sim + verbose = 1 + debug = 0 + profile = 0 + history = 0 + + clkcycle = 10ns +end + + +/* SECTION VAPI + + This section configures the Verification API, used for Advanced + Core Verification. + + enabled = 0/1 + '0': disbable VAPI server + '1': enable/start VAPI server + + server_port = <value> + TCP/IP port to start VAPI server on + + log_enabled = 0/1 + '0': disable VAPI requests logging + '1': enable VAPI requests logging + + hide_device_id = 0/1 + '0': don't log device id (for compatability with old version) + '1': log device id + + + vapi_fn = <filename> + filename for the log file. + valid only if log_enabled is set +*/ + +section VAPI + enabled = 0 + server_port = 9998 + log_enabled = 0 + vapi_log_fn = "vapi.log" +end + + +/* CPU SECTION + + This section specifies various CPU parameters. + + ver = <value> + rev = <value> + specifies version and revision of the CPU used + + upr = <value> + changes the upr register + + sr = <value> + sets the initial Supervision Register value + supervisor mode (SM) and fixed one (FO) set = 0x8001 + exception prefix high (EPH, vectors@0xf0000000) = 0x4000 + together, (SM | FO | EPH) = 0xc001 + superscalar = 0/1 + '0': CPU is scalar + '1': CPU is superscalar + (modify cpu/or32/execute.c to tune superscalar model) + + hazards = 0/1 + '0': don't track data hazards in superscalar CPU + '1': track data hazards in superscalar CPU + If tracked, data hazards can be displayed using the + simulator's 'r' command. + + dependstats = 0/1 + '0': don't calculate inter-instruction dependencies. + '1': calculate inter-instruction dependencies. + If calculated, inter-instruction dependencies can be + displayed using the simulator's 'stat' command. + + sbuf_len = <value> + length of store buffer (<= 256), 0 = disabled +*/ + +section cpu + ver = 0x12 + cfg = 0x00 + rev = 0x01 + sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */ + /* upr = */ + superscalar = 0 + hazards = 0 + dependstats = 0 + sbuf_len = 0 +end + + +/* PM SECTION + + This section specifies Power Management parameters + + enabled = 0/1 + '0': disable power management + '1': enable power management +*/ + +section pm + enabled = 0 +end + + +/* BPB SECTION + + This section specifies how branch prediction should behave. + + enabled = 0/1 + '0': disable branch prediction + '1': enable branch prediction + + btic = 0/1 + '0': disable branch target instruction cache model + '1': enable branch target instruction cache model + + sbp_bf_fwd = 0/1 + Static branch prediction for 'l.bf' + '0': don't use forward prediction + '1': use forward prediction + + sbp_bnf_fwd = 0/1 + Static branch prediction for 'l.bnf' + '0': don't use forward prediction + '1': use forward prediction + + hitdelay = <value> + number of cycles bpb hit costs + + missdelay = <value> + number of cycles bpb miss costs +*/ + +section bpb + enabled = 0 + btic = 0 + sbp_bf_fwd = 0 + sbp_bnf_fwd = 0 + hitdelay = 0 + missdelay = 0 +end + + +/* DEBUG SECTION + + This sections specifies how the debug unit should behave. + + enabled = 0/1 + '0': disable debug unit + '1': enable debug unit + + gdb_enabled = 0/1 + '0': don't start gdb server + '1': start gdb server at port 'server_port' + + server_port = <value> + TCP/IP port to start gdb server on + valid only if gdb_enabled is set + + vapi_id = <hex_value> + Used to create "fake" vapi log file containing the JTAG proxy messages. +*/ +section debug + enabled = 0 +/* gdb_enabled = 0 */ +/* server_port = 9999*/ + rsp_enabled = 1 + rsp_port = 50001 +end + + +/* MC SECTION + + This section configures the memory controller + + enabled = 0/1 + '0': disable memory controller + '1': enable memory controller + + baseaddr = <hex_value> + address of first MC register + + POC = <hex_value> + Power On Configuration register + + index = <value> + Index of this memory controller amongst all the memory controllers +*/ + +section mc + enabled = 0 + baseaddr = 0x93000000 + POC = 0x00000008 /* Power on configuration register */ + index = 0 +end + + +/* UART SECTION + + This section configures the UARTs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first UART register for this device + + + channel = <channeltype>:<args> + + The channel parameter indicates the source of received UART characters + and the sink for transmitted UART characters. + + The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty" + (without quotes). + + A) To send/receive characters from a pair of files, use a file + channel: + + channel=file:<rxfile>,<txfile> + + B) To create an interactive terminal window, use an xterm channel: + + channel=xterm:[<xterm_arg>]* + + C) To create a bidirectional tcp socket which one could, for example, + access via telnet, use a tcp channel: + + channel=tcp:<port number> + + D) To cause the UART to read/write from existing numeric file + descriptors, use an fd channel: + + channel=fd:<rx file descriptor num>,<tx file descriptor num> + + E) To connect the UART to a physical serial port, create a tty + channel: + + channel=tty:device=/dev/ttyS0,baud=9600 + + irq = <value> + irq number for this device + + 16550 = 0/1 + '0': this device is a UART16450 + '1': this device is a UART16550 + + jitter = <value> + in msecs... time to block, -1 to disable it + + vapi_id = <hex_value> + VAPI id of this instance +*/ + +section uart + enabled = 1 + baseaddr = 0x90000000 + irq = 2 + /* channel = "file:uart0.rx,uart0.tx" */ + channel = "tcp:2000" +/* channel = "xterm:" */ + jitter = -1 /* async behaviour */ + 16550 = 1 +end + + +/* DMA SECTION + + This section configures the DMAs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first DMA register for this device + + irq = <value> + irq number for this device + + vapi_id = <hex_value> + VAPI id of this instance +*/ + +section dma + enabled = 1 + baseaddr = 0x9a000000 + irq = 11 +end + + +/* ETHERNET SECTION + + This section configures the ETHERNETs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first ethernet register for this device + + dma = <value> + which controller is this ethernet "connected" to + + irq = <value> + ethernet mac IRQ level + + rtx_type = <value> + use 0 - file interface, 1 - socket interface + + rx_channel = <value> + DMA channel used for RX + + tx_channel = <value> + DMA channel used for TX + + rxfile = "<filename>" + filename, where to read data from + + txfile = "<filename>" + filename, where to write data to + + sockif = "<ifacename>" + interface name of ethernet socket + + vapi_id = <hex_value> + VAPI id of this instance +*/ + +section ethernet + enabled = 0 + baseaddr = 0x92000000 + /* dma = 0 */ + irq = 4 + rtx_type = "tap" + tap_dev = "tap0" + /* tx_channel = 0 */ + /* rx_channel = 1 */ + rxfile = "eth0.rx" + txfile = "eth0.tx" + sockif = "eth0" +end + + +/* GPIO SECTION + + This section configures the GPIOs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first GPIO register for this device + + irq = <value> + irq number for this device + + base_vapi_id = <hex_value> + first VAPI id of this instance + GPIO uses 8 consecutive VAPI IDs +*/ + +section gpio + enabled = 0 + baseaddr = 0x91000000 + irq = 3 + base_vapi_id = 0x0200 +end + +/* VGA SECTION + + This section configures the VGA/LCD controller + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first VGA register + + irq = <value> + irq number for this device + + refresh_rate = <value> + number of cycles between screen dumps + + filename = "<filename>" + template name for generated names (e.g. "primary" produces "primary0023.bmp") +*/ + +section vga + enabled = 0 + baseaddr = 0x97100000 + irq = 8 + refresh_rate = 100000 + filename = "primary" +end + + +/* TICK TIMER SECTION + + This section configures tick timer + + enabled = 0/1 + whether tick timer is enabled +*/ + +section pic + enabled = 1 + edge_trigger = 1 +end + +/* FB SECTION + + This section configures the frame buffer + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + base address of frame buffer + + paladdr = <hex_value> + base address of first palette entry + + refresh_rate = <value> + number of cycles between screen dumps + + filename = "<filename>" + template name for generated names (e.g. "primary" produces "primary0023.bmp") +*/ + +section fb + enabled = 0 + baseaddr = 0x97000000 + refresh_rate = 1000000 + filename = "primary" +end + + +/* KBD SECTION + + This section configures the PS/2 compatible keyboard + + baseaddr = <hex_value> + base address of the keyboard device + + rxfile = "<filename>" + filename, where to read data from +*/ + +section kbd + enabled = 0 + irq = 5 + baseaddr = 0x94000000 + rxfile = "kbd.rx" +end + + +/* ATA SECTION + + This section configures the ATA/ATAPI host controller + + baseaddr = <hex_value> + address of first ATA register + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + irq = <value> + irq number for this device + + debug = <value> + debug level for ata models. + 0: no debug messages + 1: verbose messages + 3: normal messages (more messages than verbose) + 5: debug messages (normal debug messages) + 7: flow control messages (debug statemachine flows) + 9: low priority message (display everything the code does) + + dev_type0/1 = <value> + ata device 0 type + 0: NO_CONNeCT: none (not connected) + 1: FILE : simulated harddisk + 2: LOCAL : local system harddisk + + dev_file0/1 = "<filename>" + filename for simulated ATA device + valid only if dev_type0 == 1 + + dev_size0/1 = <value> + size of simulated hard-disk (in MBytes) + valid only if dev_type0 == 1 + + dev_packet0/1 = <value> + 0: simulated ATA device does NOT implement PACKET command feature set + 1: simulated ATA device does implement PACKET command feature set + + FIXME: irq number +*/ + +section ata + enabled = 0 + baseaddr = 0x9e000000 + irq = 15 + +end diff --git a/target/or1k/systems/or1k-sim b/target/or1k/systems/or1k-sim index 29cbaf74b..3f77324b1 100644 --- a/target/or1k/systems/or1k-sim +++ b/target/or1k/systems/or1k-sim @@ -1,6 +1,7 @@ config ADK_TARGET_SYSTEM_OR1K_SIM bool "OR1K Simulator" select ADK_CPU_OR1K + select ADK_TARGET_WITH_SERIAL help Simulator for OR1K architecture. |