diff options
Diffstat (limited to 'target/mips64el/patches')
| -rw-r--r-- | target/mips64el/patches/io_map_base.patch | 52 | ||||
| -rw-r--r-- | target/mips64el/patches/lemote.patch | 4267 |
2 files changed, 4319 insertions, 0 deletions
diff --git a/target/mips64el/patches/io_map_base.patch b/target/mips64el/patches/io_map_base.patch new file mode 100644 index 000000000..be39ffe09 --- /dev/null +++ b/target/mips64el/patches/io_map_base.patch @@ -0,0 +1,52 @@ +diff -Nur linux-2.6.28.orig/arch/mips/include/asm/mips-boards/generic.h linux-2.6.28/arch/mips/include/asm/mips-boards/generic.h +--- linux-2.6.28.orig/arch/mips/include/asm/mips-boards/generic.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28/arch/mips/include/asm/mips-boards/generic.h 2009-01-09 23:03:02.000000000 +0100 +@@ -92,7 +92,7 @@ + extern void mips_reboot_setup(void); + + #ifdef CONFIG_PCI +-extern void mips_pcibios_init(void); ++extern int mips_pcibios_init(void); + #else + #define mips_pcibios_init() do { } while (0) + #endif +diff -Nur linux-2.6.28.orig/arch/mips/mti-malta/malta-pci.c linux-2.6.28/arch/mips/mti-malta/malta-pci.c +--- linux-2.6.28.orig/arch/mips/mti-malta/malta-pci.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28/arch/mips/mti-malta/malta-pci.c 2009-01-09 23:02:02.000000000 +0100 +@@ -87,10 +87,11 @@ + .mem_resource = &msc_mem_resource, + }; + +-void __init mips_pcibios_init(void) ++int __init mips_pcibios_init(void) + { + struct pci_controller *controller; + resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; ++ void __iomem *io_map_base; + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_GT64120: +@@ -230,7 +231,7 @@ + controller = &msc_controller; + break; + default: +- return; ++ return 0; + } + + if (controller->io_resource->start < 0x00001000UL) /* FIXME */ +@@ -239,5 +240,14 @@ + iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ + ioport_resource.end = controller->io_resource->end; + ++ io_map_base = ioremap(MIPS_MSC01_PCI_REG_BASE, ++ controller->io_resource->end - controller->io_resource->start + 1); ++ if (!io_map_base) ++ return -EBUSY; ++ ++ controller->io_map_base = (unsigned long)io_map_base; ++ + register_pci_controller(controller); ++ ++ return 0; + } diff --git a/target/mips64el/patches/lemote.patch b/target/mips64el/patches/lemote.patch new file mode 100644 index 000000000..dce900900 --- /dev/null +++ b/target/mips64el/patches/lemote.patch @@ -0,0 +1,4267 @@ +diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig +--- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/Kconfig 2010-11-18 11:47:59.000000000 +0100 +@@ -205,7 +205,7 @@ + + config MACH_LOONGSON + bool "Loongson family of machines" +- select SYS_SUPPORTS_ZBOOT ++ select SYS_SUPPORTS_ZBOOT_UART16550 + help + This enables the support of Loongson family of machines. + +@@ -1093,6 +1093,8 @@ + bool "Loongson 2E" + depends on SYS_HAS_CPU_LOONGSON2E + select CPU_LOONGSON2 ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB + help + The Loongson 2E processor implements the MIPS III instruction set + with many extensions. +@@ -2012,6 +2014,18 @@ + source "kernel/time/Kconfig" + + # ++# High Resolution sched_clock() Configuration ++# ++ ++config CPU_HAS_FIXED_C0_COUNT ++ bool ++ ++config CPU_SUPPORTS_HR_SCHED_CLOCK ++ bool ++ depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ ++ default y ++ ++# + # Timer Interrupt Frequency Configuration + # + +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/dma-mapping.h linux-2.6.36/arch/mips/include/asm/dma-mapping.h +--- linux-2.6.36.orig/arch/mips/include/asm/dma-mapping.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/include/asm/dma-mapping.h 2010-11-18 11:47:59.000000000 +0100 +@@ -65,4 +65,8 @@ + extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction); + ++#define ARCH_HAS_DMA_MMAP_COHERENT ++extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, ++ void *cpu_addr, dma_addr_t handle, size_t size); ++ + #endif /* _ASM_DMA_MAPPING_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2010-11-18 11:47:59.000000000 +0100 +@@ -255,21 +255,12 @@ + * IDE STANDARD + */ + #define IDE_CAP 0x00 +-#define IDE_CONFIG 0x01 +-#define IDE_SMI 0x02 +-#define IDE_ERROR 0x03 +-#define IDE_PM 0x04 +-#define IDE_DIAG 0x05 +- +-/* +- * IDE SPEC. +- */ + #define IDE_IO_BAR 0x08 + #define IDE_CFG 0x10 + #define IDE_DTC 0x12 + #define IDE_CAST 0x13 + #define IDE_ETC 0x14 +-#define IDE_INTERNAL_PM 0x15 ++#define IDE_PM 0x15 + + /* + * ACC STANDARD +@@ -301,5 +292,40 @@ + /* GPIO : I/O SPACE; REG : 32BITS */ + #define GPIOL_OUT_VAL 0x00 + #define GPIOL_OUT_EN 0x04 ++#define GPIOL_OUT_AUX1_SEL 0x10 ++/* SMB : I/O SPACE, REG : 8BITS WIDTH */ ++#define SMB_SDA 0x00 ++#define SMB_STS 0x01 ++#define SMB_STS_SLVSTP (1 << 7) ++#define SMB_STS_SDAST (1 << 6) ++#define SMB_STS_BER (1 << 5) ++#define SMB_STS_NEGACK (1 << 4) ++#define SMB_STS_STASTR (1 << 3) ++#define SMB_STS_NMATCH (1 << 2) ++#define SMB_STS_MASTER (1 << 1) ++#define SMB_STS_XMIT (1 << 0) ++#define SMB_CTRL_STS 0x02 ++#define SMB_CSTS_TGSTL (1 << 5) ++#define SMB_CSTS_TSDA (1 << 4) ++#define SMB_CSTS_GCMTCH (1 << 3) ++#define SMB_CSTS_MATCH (1 << 2) ++#define SMB_CSTS_BB (1 << 1) ++#define SMB_CSTS_BUSY (1 << 0) ++#define SMB_CTRL1 0x03 ++#define SMB_CTRL1_STASTRE (1 << 7) ++#define SMB_CTRL1_NMINTE (1 << 6) ++#define SMB_CTRL1_GCMEN (1 << 5) ++#define SMB_CTRL1_ACK (1 << 4) ++#define SMB_CTRL1_RSVD (1 << 3) ++#define SMB_CTRL1_INTEN (1 << 2) ++#define SMB_CTRL1_STOP (1 << 1) ++#define SMB_CTRL1_START (1 << 0) ++#define SMB_ADDR 0x04 ++#define SMB_ADDR_SAEN (1 << 7) ++#define SMB_CONTROLLER_ADDR (0xef << 0) ++#define SMB_CTRL2 0x05 ++#define SMB_FREQ (0x20 << 1) ++#define SMB_ENABLE (0x01 << 0) ++#define SMB_CTRL3 0x06 + + #endif /* _CS5536_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2010-11-18 11:47:59.000000000 +0100 +@@ -32,4 +32,9 @@ + #define MFGPT0_CNT (MFGPT_BASE + 4) + #define MFGPT0_SETUP (MFGPT_BASE + 6) + ++#define MFGPT2_CMP1 (MFGPT_BASE + 0x10) ++#define MFGPT2_CMP2 (MFGPT_BASE + 0x12) ++#define MFGPT2_CNT (MFGPT_BASE + 0x14) ++#define MFGPT2_SETUP (MFGPT_BASE + 0x16) ++ + #endif /*!_CS5536_MFGPT_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h linux-2.6.36/arch/mips/include/asm/mach-loongson/ec_kb3310b.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 2010-11-18 11:47:59.000000000 +0100 +@@ -0,0 +1,191 @@ ++/* ++ * KB3310B Embedded Controller ++ * ++ * Copyright (C) 2008 Lemote Inc. ++ * Author: liujl <liujl@lemote.com>, 2008-03-14 ++ * Copyright (C) 2009 Lemote Inc. ++ * Author: Wu Zhangjin <wuzhangjin@gmail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _EC_KB3310B_H ++#define _EC_KB3310B_H ++ ++extern unsigned char ec_read(unsigned short addr); ++extern void ec_write(unsigned short addr, unsigned char val); ++extern int ec_query_seq(unsigned char cmd); ++extern int ec_query_event_num(void); ++extern int ec_get_event_num(void); ++ ++typedef int (*sci_handler) (int status); ++extern sci_handler yeeloong_report_lid_status; ++ ++#define SCI_IRQ_NUM 0x0A ++ ++/* ++ * The following registers are determined by the EC index configuration. ++ * 1, fill the PORT_HIGH as EC register high part. ++ * 2, fill the PORT_LOW as EC register low part. ++ * 3, fill the PORT_DATA as EC register write data or get the data from it. ++ */ ++#define EC_IO_PORT_HIGH 0x0381 ++#define EC_IO_PORT_LOW 0x0382 ++#define EC_IO_PORT_DATA 0x0383 ++ ++/* ++ * EC delay time is 500us for register and status access ++ */ ++#define EC_REG_DELAY 500 /* unit : us */ ++#define EC_CMD_TIMEOUT 0x1000 ++ ++/* ++ * EC access port for SCI communication ++ */ ++#define EC_CMD_PORT 0x66 ++#define EC_STS_PORT 0x66 ++#define EC_DAT_PORT 0x62 ++#define CMD_INIT_IDLE_MODE 0xdd ++#define CMD_EXIT_IDLE_MODE 0xdf ++#define CMD_INIT_RESET_MODE 0xd8 ++#define CMD_REBOOT_SYSTEM 0x8c ++#define CMD_GET_EVENT_NUM 0x84 ++#define CMD_PROGRAM_PIECE 0xda ++ ++/* Temperature & Fan registers */ ++#define REG_TEMPERATURE_VALUE 0xF458 ++#define REG_FAN_AUTO_MAN_SWITCH 0xF459 ++#define BIT_FAN_AUTO 0 ++#define BIT_FAN_MANUAL 1 ++#define REG_FAN_CONTROL 0xF4D2 ++#define BIT_FAN_CONTROL_ON (1 << 0) ++#define BIT_FAN_CONTROL_OFF (0 << 0) ++#define REG_FAN_STATUS 0xF4DA ++#define BIT_FAN_STATUS_ON (1 << 0) ++#define BIT_FAN_STATUS_OFF (0 << 0) ++#define REG_FAN_SPEED_HIGH 0xFE22 ++#define REG_FAN_SPEED_LOW 0xFE23 ++#define REG_FAN_SPEED_LEVEL 0xF4CC ++/* Fan speed divider */ ++#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/ ++ ++/* Battery registers */ ++#define REG_BAT_DESIGN_CAP_HIGH 0xF77D ++#define REG_BAT_DESIGN_CAP_LOW 0xF77E ++#define REG_BAT_FULLCHG_CAP_HIGH 0xF780 ++#define REG_BAT_FULLCHG_CAP_LOW 0xF781 ++#define REG_BAT_DESIGN_VOL_HIGH 0xF782 ++#define REG_BAT_DESIGN_VOL_LOW 0xF783 ++#define REG_BAT_CURRENT_HIGH 0xF784 ++#define REG_BAT_CURRENT_LOW 0xF785 ++#define REG_BAT_VOLTAGE_HIGH 0xF786 ++#define REG_BAT_VOLTAGE_LOW 0xF787 ++#define REG_BAT_TEMPERATURE_HIGH 0xF788 ++#define REG_BAT_TEMPERATURE_LOW 0xF789 ++#define REG_BAT_RELATIVE_CAP_HIGH 0xF492 ++#define REG_BAT_RELATIVE_CAP_LOW 0xF493 ++#define REG_BAT_VENDOR 0xF4C4 ++#define FLAG_BAT_VENDOR_SANYO 0x01 ++#define FLAG_BAT_VENDOR_SIMPLO 0x02 ++#define REG_BAT_CELL_COUNT 0xF4C6 ++#define FLAG_BAT_CELL_3S1P 0x03 ++#define FLAG_BAT_CELL_3S2P 0x06 ++#define REG_BAT_CHARGE 0xF4A2 ++#define FLAG_BAT_CHARGE_DISCHARGE 0x01 ++#define FLAG_BAT_CHARGE_CHARGE 0x02 ++#define FLAG_BAT_CHARGE_ACPOWER 0x00 ++#define REG_BAT_STATUS 0xF4B0 ++#define BIT_BAT_STATUS_LOW (1 << 5) ++#define BIT_BAT_STATUS_DESTROY (1 << 2) ++#define BIT_BAT_STATUS_FULL (1 << 1) ++#define BIT_BAT_STATUS_IN (1 << 0) ++#define REG_BAT_CHARGE_STATUS 0xF4B1 ++#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2) ++#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1) ++#define REG_BAT_STATE 0xF482 ++#define BIT_BAT_STATE_CHARGING (1 << 1) ++#define BIT_BAT_STATE_DISCHARGING (1 << 0) ++#define REG_BAT_POWER 0xF440 ++#define BIT_BAT_POWER_S3 (1 << 2) ++#define BIT_BAT_POWER_ON (1 << 1) ++#define BIT_BAT_POWER_ACIN (1 << 0) ++ ++/* Audio: rd/wr */ ++#define REG_AUDIO_VOLUME 0xF46C ++#define REG_AUDIO_MUTE 0xF4E7 ++#define REG_AUDIO_BEEP 0xF4D0 ++/* USB port power or not: rd/wr */ ++#define REG_USB0_FLAG 0xF461 ++#define REG_USB1_FLAG 0xF462 ++#define REG_USB2_FLAG 0xF463 ++#define BIT_USB_FLAG_ON 1 ++#define BIT_USB_FLAG_OFF 0 ++/* LID */ ++#define REG_LID_DETECT 0xF4BD ++#define BIT_LID_DETECT_ON 1 ++#define BIT_LID_DETECT_OFF 0 ++/* CRT */ ++#define REG_CRT_DETECT 0xF4AD ++#define BIT_CRT_DETECT_PLUG 1 ++#define BIT_CRT_DETECT_UNPLUG 0 ++/* LCD backlight brightness adjust: 9 levels */ ++#define REG_DISPLAY_BRIGHTNESS 0xF4F5 ++/* Black screen Status */ ++#define BIT_DISPLAY_LCD_ON 1 ++#define BIT_DISPLAY_LCD_OFF 0 ++/* LCD backlight control: off/restore */ ++#define REG_BACKLIGHT_CTRL 0xF7BD ++#define BIT_BACKLIGHT_ON 1 ++#define BIT_BACKLIGHT_OFF 0 ++/* Reset the machine auto-clear: rd/wr */ ++#define REG_RESET 0xF4EC ++#define BIT_RESET_ON 1 ++/* Light the led: rd/wr */ ++#define REG_LED 0xF4C8 ++#define BIT_LED_RED_POWER (1 << 0) ++#define BIT_LED_ORANGE_POWER (1 << 1) ++#define BIT_LED_GREEN_CHARGE (1 << 2) ++#define BIT_LED_RED_CHARGE (1 << 3) ++#define BIT_LED_NUMLOCK (1 << 4) ++/* Test led mode, all led on/off */ ++#define REG_LED_TEST 0xF4C2 ++#define BIT_LED_TEST_IN 1 ++#define BIT_LED_TEST_OUT 0 ++/* Camera on/off */ ++#define REG_CAMERA_STATUS 0xF46A ++#define BIT_CAMERA_STATUS_ON 1 ++#define BIT_CAMERA_STATUS_OFF 0 ++#define REG_CAMERA_CONTROL 0xF7B7 ++#define BIT_CAMERA_CONTROL_OFF 0 ++#define BIT_CAMERA_CONTROL_ON 1 ++/* Wlan Status */ ++#define REG_WLAN 0xF4FA ++#define BIT_WLAN_ON 1 ++#define BIT_WLAN_OFF 0 ++#define REG_DISPLAY_LCD 0xF79F ++ ++/* SCI Event Number from EC */ ++enum { ++ EVENT_LID = 0x23, /* Turn on/off LID */ ++ EVENT_SWITCHVIDEOMODE, /* Fn+F3 for display switch */ ++ EVENT_SLEEP, /* Fn+F1 for entering sleep mode */ ++ EVENT_OVERTEMP, /* Over-temperature happened */ ++ EVENT_CRT_DETECT, /* CRT is connected */ ++ EVENT_CAMERA, /* Camera on/off */ ++ EVENT_USB_OC2, /* USB2 Over Current occurred */ ++ EVENT_USB_OC0, /* USB0 Over Current occurred */ ++ EVENT_DISPLAYTOGGLE, /* Fn+F2, Turn on/off backlight */ ++ EVENT_AUDIO_MUTE, /* Fn+F4, Mute on/off */ ++ EVENT_DISPLAY_BRIGHTNESS,/* Fn+^/V, LCD backlight brightness adjust */ ++ EVENT_AC_BAT, /* AC & Battery relative issue */ ++ EVENT_AUDIO_VOLUME, /* Fn+<|>, Volume adjust */ ++ EVENT_WLAN, /* Wlan on/off */ ++}; ++ ++#define EVENT_START EVENT_LID ++#define EVENT_END EVENT_WLAN ++ ++#endif /* !_EC_KB3310B_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/loongson.h linux-2.6.36/arch/mips/include/asm/mach-loongson/loongson.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/loongson.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/include/asm/mach-loongson/loongson.h 2010-11-18 11:47:59.000000000 +0100 +@@ -42,6 +42,12 @@ + #endif + } + ++/* ++ * Copy kernel command line from arcs_cmdline ++ */ ++#include <asm/setup.h> ++extern char loongson_cmdline[COMMAND_LINE_SIZE]; ++ + /* irq operation functions */ + extern void bonito_irqdispatch(void); + extern void __init bonito_irq_init(void); +diff -Nur linux-2.6.36.orig/arch/mips/kernel/csrc-r4k.c linux-2.6.36/arch/mips/kernel/csrc-r4k.c +--- linux-2.6.36.orig/arch/mips/kernel/csrc-r4k.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/kernel/csrc-r4k.c 2010-11-18 11:47:59.000000000 +0100 +@@ -6,10 +6,66 @@ + * Copyright (C) 2007 by Ralf Baechle + */ + #include <linux/clocksource.h> ++#include <linux/cnt32_to_63.h> + #include <linux/init.h> ++#include <linux/timer.h> + + #include <asm/time.h> + ++#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK ++/* ++ * MIPS sched_clock implementation. ++ * ++ * Because the hardware timer period is quite short and because cnt32_to_63() ++ * needs to be called at least once per half period to work properly, a kernel ++ * timer is set up to ensure this requirement is always met. ++ * ++ * Please refer to include/linux/cnt32_to_63.h and arch/arm/plat-orion/time.c ++ */ ++#define CLOCK2NS_SCALE_FACTOR 8 ++ ++static unsigned long clock2ns_scale __read_mostly; ++ ++unsigned long long notrace sched_clock(void) ++{ ++ unsigned long long v = cnt32_to_63(read_c0_count()); ++ return (v * clock2ns_scale) >> CLOCK2NS_SCALE_FACTOR; ++} ++ ++static struct timer_list cnt32_to_63_keepwarm_timer; ++ ++static void cnt32_to_63_keepwarm(unsigned long data) ++{ ++ mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); ++ sched_clock(); ++} ++#endif ++ ++static inline void setup_hres_sched_clock(unsigned long clock) ++{ ++#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK ++ unsigned long long v; ++ unsigned long data; ++ ++ v = NSEC_PER_SEC; ++ v <<= CLOCK2NS_SCALE_FACTOR; ++ v += clock/2; ++ do_div(v, clock); ++ /* ++ * We want an even value to automatically clear the top bit ++ * returned by cnt32_to_63() without an additional run time ++ * instruction. So if the LSB is 1 then round it up. ++ */ ++ if (v & 1) ++ v++; ++ clock2ns_scale = v; ++ ++ data = 0x80000000UL / clock * HZ; ++ setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); ++ mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); ++#endif ++} ++ + static cycle_t c0_hpt_read(struct clocksource *cs) + { + return read_c0_count(); +@@ -27,6 +83,8 @@ + if (!cpu_has_counter || !mips_hpt_frequency) + return -ENXIO; + ++ setup_hres_sched_clock(mips_hpt_frequency); ++ + /* Calculate a somewhat reasonable rating value */ + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + +diff -Nur linux-2.6.36.orig/arch/mips/kernel/time.c linux-2.6.36/arch/mips/kernel/time.c +--- linux-2.6.36.orig/arch/mips/kernel/time.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/kernel/time.c 2010-11-18 11:47:59.000000000 +0100 +@@ -119,6 +119,11 @@ + + void __init time_init(void) + { ++#ifdef CONFIG_HR_SCHED_CLOCK ++ if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) ++ write_c0_count(0); ++#endif ++ + plat_time_init(); + + if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) +diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cmdline.c linux-2.6.36/arch/mips/loongson/common/cmdline.c +--- linux-2.6.36.orig/arch/mips/loongson/common/cmdline.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/loongson/common/cmdline.c 2010-11-18 11:47:59.000000000 +0100 +@@ -17,10 +17,15 @@ + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ ++#include <linux/module.h> + #include <asm/bootinfo.h> + + #include <loongson.h> + ++/* the kernel command line copied from arcs_cmdline */ ++char loongson_cmdline[COMMAND_LINE_SIZE]; ++EXPORT_SYMBOL(loongson_cmdline); ++ + void __init prom_init_cmdline(void) + { + int prom_argc; +@@ -50,4 +55,26 @@ + strcat(arcs_cmdline, " root=/dev/hda1"); + + prom_init_machtype(); ++ ++ /* append machine specific command line */ ++ switch (mips_machtype) { ++ case MACH_LEMOTE_LL2F: ++ if ((strstr(arcs_cmdline, "video=")) == NULL) ++ strcat(arcs_cmdline, " video=sisfb:1360x768-16@60"); ++ break; ++ case MACH_LEMOTE_FL2F: ++ if ((strstr(arcs_cmdline, "ide_core.ignore_cable=")) == NULL) ++ strcat(arcs_cmdline, " ide_core.ignore_cable=0"); ++ break; ++ case MACH_LEMOTE_ML2F7: ++ /* Mengloong-2F has a 800x480 screen */ ++ if ((strstr(arcs_cmdline, "vga=")) == NULL) ++ strcat(arcs_cmdline, " vga=0x313"); ++ break; ++ default: ++ break; ++ } ++ ++ /* copy arcs_cmdline into loongson_cmdline */ ++ strncpy(loongson_cmdline, arcs_cmdline, COMMAND_LINE_SIZE); + } +diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_acc.c +--- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_acc.c 2010-11-18 11:47:59.000000000 +0100 +@@ -18,7 +18,7 @@ + + void pci_acc_write_reg(int reg, u32 value) + { +- u32 hi = 0, lo = value; ++ u32 hi, lo; + + switch (reg) { + case PCI_COMMAND: +@@ -66,75 +66,73 @@ + u32 pci_acc_read_reg(int reg) + { + u32 hi, lo; +- u32 conf_data = 0; ++ u32 cfg = 0; + + switch (reg) { + case PCI_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, ++ CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); + if (((lo & 0xfff00000) || (hi & 0x000000ff)) + && ((hi & 0xf0000000) == 0xa0000000)) +- conf_data |= PCI_COMMAND_IO; ++ cfg |= PCI_COMMAND_IO; + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if ((lo & 0x300) == 0x300) +- conf_data |= PCI_COMMAND_MASTER; ++ cfg |= PCI_COMMAND_MASTER; + break; + case PCI_STATUS: +- conf_data |= PCI_STATUS_66MHZ; +- conf_data |= PCI_STATUS_FAST_BACK; ++ cfg |= PCI_STATUS_66MHZ; ++ cfg |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) +- conf_data |= PCI_STATUS_PARITY; +- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ cfg |= PCI_STATUS_PARITY; ++ cfg |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); +- conf_data = lo & 0x000000ff; +- conf_data |= (CS5536_ACC_CLASS_CODE << 8); ++ cfg = lo & 0x000000ff; ++ cfg |= (CS5536_ACC_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: +- conf_data = +- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, +- PCI_NORMAL_LATENCY_TIMER); ++ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_ACC_FLAG) { +- conf_data = CS5536_ACC_RANGE | ++ cfg = CS5536_ACC_RANGE | + PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~SOFT_BAR_ACC_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); +- conf_data = (hi & 0x000000ff) << 12; +- conf_data |= (lo & 0xfff00000) >> 20; +- conf_data |= 0x01; +- conf_data &= ~0x02; ++ cfg = (hi & 0x000000ff) << 12; ++ cfg |= (lo & 0xfff00000) >> 20; ++ cfg |= 0x01; ++ cfg &= ~0x02; + } + break; + case PCI_CARDBUS_CIS: +- conf_data = PCI_CARDBUS_CIS_POINTER; ++ cfg = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, ++ CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: +- conf_data = PCI_EXPANSION_ROM_BAR; ++ cfg = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: +- conf_data = PCI_CAPLIST_USB_POINTER; ++ cfg = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: +- conf_data = +- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); ++ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); + break; + default: + break; + } + +- return conf_data; ++ return cfg; + } +diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ehci.c +--- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2010-11-18 11:47:59.000000000 +0100 +@@ -18,7 +18,7 @@ + + void pci_ehci_write_reg(int reg, u32 value) + { +- u32 hi = 0, lo = value; ++ u32 hi, lo; + + switch (reg) { + case PCI_COMMAND: +@@ -78,83 +78,81 @@ + + u32 pci_ehci_read_reg(int reg) + { +- u32 conf_data = 0; ++ u32 cfg = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, ++ CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + if (hi & PCI_COMMAND_MASTER) +- conf_data |= PCI_COMMAND_MASTER; ++ cfg |= PCI_COMMAND_MASTER; + if (hi & PCI_COMMAND_MEMORY) +- conf_data |= PCI_COMMAND_MEMORY; ++ cfg |= PCI_COMMAND_MEMORY; + break; + case PCI_STATUS: +- conf_data |= PCI_STATUS_66MHZ; +- conf_data |= PCI_STATUS_FAST_BACK; ++ cfg |= PCI_STATUS_66MHZ; ++ cfg |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) +- conf_data |= PCI_STATUS_PARITY; +- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ cfg |= PCI_STATUS_PARITY; ++ cfg |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); +- conf_data = lo & 0x000000ff; +- conf_data |= (CS5536_EHCI_CLASS_CODE << 8); ++ cfg = lo & 0x000000ff; ++ cfg |= (CS5536_EHCI_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: +- conf_data = +- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, +- PCI_NORMAL_LATENCY_TIMER); ++ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_EHCI_FLAG) { +- conf_data = CS5536_EHCI_RANGE | ++ cfg = CS5536_EHCI_RANGE | + PCI_BASE_ADDRESS_SPACE_MEMORY; + lo &= ~SOFT_BAR_EHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); +- conf_data = lo & 0xfffff000; ++ cfg = lo & 0xfffff000; + } + break; + case PCI_CARDBUS_CIS: +- conf_data = PCI_CARDBUS_CIS_POINTER; ++ cfg = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, ++ CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: +- conf_data = PCI_EXPANSION_ROM_BAR; ++ cfg = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: +- conf_data = PCI_CAPLIST_USB_POINTER; ++ cfg = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: +- conf_data = +- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); ++ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); + break; + case PCI_EHCI_LEGSMIEN_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); +- conf_data = (hi & 0x003f0000) >> 16; ++ cfg = (hi & 0x003f0000) >> 16; + break; + case PCI_EHCI_LEGSMISTS_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); +- conf_data = (hi & 0x3f000000) >> 24; ++ cfg = (hi & 0x3f000000) >> 24; + break; + case PCI_EHCI_FLADJ_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); +- conf_data = hi & 0x00003f00; ++ cfg = hi & 0x00003f00; + break; + default: + break; + } + +- return conf_data; ++ return cfg; + } +diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ide.c +--- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ide.c 2010-11-18 11:47:59.000000000 +0100 +@@ -18,7 +18,7 @@ + + void pci_ide_write_reg(int reg, u32 value) + { +- u32 hi = 0, lo = value; ++ u32 hi, lo; + + switch (reg) { + case PCI_COMMAND: +@@ -72,26 +72,16 @@ + _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); + } + break; +- case PCI_IDE_DTC_REG: +- _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); +- lo = value; +- _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); +- break; +- case PCI_IDE_CAST_REG: +- _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); +- lo = value; +- _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); +- break; +- case PCI_IDE_ETC_REG: +- _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); +- lo = value; +- _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); +- break; +- case PCI_IDE_PM_REG: +- _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); +- lo = value; +- _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); +- break; ++#define SET_PCI_IDE_REG(r) \ ++ case PCI_IDE_##r##_REG: \ ++ _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &lo); \ ++ lo = value; \ ++ _wrmsr(IDE_MSR_REG(IDE_##r), hi, lo); \ ++ break; ++ SET_PCI_IDE_REG(DTC) ++ SET_PCI_IDE_REG(CAST) ++ SET_PCI_IDE_REG(ETC) ++ SET_PCI_IDE_REG(PM) + default: + break; + } +@@ -99,94 +89,82 @@ + + u32 pci_ide_read_reg(int reg) + { +- u32 conf_data = 0; ++ u32 cfg = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, ++ CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); + if (lo & 0xfffffff0) +- conf_data |= PCI_COMMAND_IO; ++ cfg |= PCI_COMMAND_IO; + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if ((lo & 0x30) == 0x30) +- conf_data |= PCI_COMMAND_MASTER; ++ cfg |= PCI_COMMAND_MASTER; + break; + case PCI_STATUS: +- conf_data |= PCI_STATUS_66MHZ; +- conf_data |= PCI_STATUS_FAST_BACK; ++ cfg |= PCI_STATUS_66MHZ; ++ cfg |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) +- conf_data |= PCI_STATUS_PARITY; +- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ cfg |= PCI_STATUS_PARITY; ++ cfg |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); +- conf_data = lo & 0x000000ff; +- conf_data |= (CS5536_IDE_CLASS_CODE << 8); ++ cfg = lo & 0x000000ff; ++ cfg |= (CS5536_IDE_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0x000000f8; +- conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); ++ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); + break; + case PCI_BAR4_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_IDE_FLAG) { +- conf_data = CS5536_IDE_RANGE | ++ cfg = CS5536_IDE_RANGE | + PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~SOFT_BAR_IDE_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); +- conf_data = lo & 0xfffffff0; +- conf_data |= 0x01; +- conf_data &= ~0x02; ++ cfg = lo & 0xfffffff0; ++ cfg |= 0x01; ++ cfg &= ~0x02; + } + break; + case PCI_CARDBUS_CIS: +- conf_data = PCI_CARDBUS_CIS_POINTER; ++ cfg = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, ++ CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: +- conf_data = PCI_EXPANSION_ROM_BAR; ++ cfg = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: +- conf_data = PCI_CAPLIST_POINTER; ++ cfg = PCI_CAPLIST_POINTER; + break; + case PCI_INTERRUPT_LINE: +- conf_data = +- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); +- break; +- case PCI_IDE_CFG_REG: +- _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); +- conf_data = lo; +- break; +- case PCI_IDE_DTC_REG: +- _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); +- conf_data = lo; +- break; +- case PCI_IDE_CAST_REG: +- _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); +- conf_data = lo; +- break; +- case PCI_IDE_ETC_REG: +- _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); +- conf_data = lo; +- break; +- case PCI_IDE_PM_REG: +- _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); +- conf_data = lo; ++ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); + break; ++#define GET_PCI_IDE_REG(r) \ ++ case PCI_IDE_##r##_REG: \ ++ _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &cfg); \ ++ break; ++ GET_PCI_IDE_REG(CFG) ++ GET_PCI_IDE_REG(DTC) ++ GET_PCI_IDE_REG(CAST) ++ GET_PCI_IDE_REG(ETC) ++ GET_PCI_IDE_REG(PM) + default: + break; + } + +- return conf_data; ++ return cfg; + } +diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ohci.c +--- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2010-11-18 11:47:59.000000000 +0100 +@@ -18,7 +18,7 @@ + + void pci_ohci_write_reg(int reg, u32 value) + { +- u32 hi = 0, lo = value; ++ u32 hi, lo; + + switch (reg) { + case PCI_COMMAND: +@@ -73,77 +73,75 @@ + + u32 pci_ohci_read_reg(int reg) + { +- u32 conf_data = 0; ++ u32 cfg = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, ++ CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + if (hi & PCI_COMMAND_MASTER) +- conf_data |= PCI_COMMAND_MASTER; ++ cfg |= PCI_COMMAND_MASTER; + if (hi & PCI_COMMAND_MEMORY) +- conf_data |= PCI_COMMAND_MEMORY; ++ cfg |= PCI_COMMAND_MEMORY; + break; + case PCI_STATUS: +- conf_data |= PCI_STATUS_66MHZ; +- conf_data |= PCI_STATUS_FAST_BACK; ++ cfg |= PCI_STATUS_66MHZ; ++ cfg |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) +- conf_data |= PCI_STATUS_PARITY; +- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; ++ cfg |= PCI_STATUS_PARITY; ++ cfg |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); +- conf_data = lo & 0x000000ff; +- conf_data |= (CS5536_OHCI_CLASS_CODE << 8); ++ cfg = lo & 0x000000ff; ++ cfg |= (CS5536_OHCI_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: +- conf_data = +- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, +- PCI_NORMAL_LATENCY_TIMER); ++ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, ++ PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_OHCI_FLAG) { +- conf_data = CS5536_OHCI_RANGE | ++ cfg = CS5536_OHCI_RANGE | + PCI_BASE_ADDRESS_SPACE_MEMORY; + lo &= ~SOFT_BAR_OHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); +- conf_data = lo & 0xffffff00; +- conf_data &= ~0x0000000f; /* 32bit mem */ ++ cfg = lo & 0xffffff00; ++ cfg &= ~0x0000000f; /* 32bit mem */ + } + break; + case PCI_CARDBUS_CIS: +- conf_data = PCI_CARDBUS_CIS_POINTER; ++ cfg = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: +- conf_data = +- CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); ++ cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, ++ CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: +- conf_data = PCI_EXPANSION_ROM_BAR; ++ cfg = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: +- conf_data = PCI_CAPLIST_USB_POINTER; ++ cfg = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: +- conf_data = +- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); ++ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); + break; + case PCI_OHCI_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + if ((lo & 0x00000f00) == CS5536_USB_INTR) +- conf_data = 1; ++ cfg = 1; + break; + default: + break; + } + +- return conf_data; ++ return cfg; + } +diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/mtd.c linux-2.6.36/arch/mips/loongson/common/mtd.c +--- linux-2.6.36.orig/arch/mips/loongson/common/mtd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/loongson/common/mtd.c 2010-11-18 11:47:59.000000000 +0100 +@@ -0,0 +1,91 @@ ++/* ++ * Driver for flushing/dumping ROM of PMON on loongson family machines ++ * ++ * Copyright (C) 2008-2009 Lemote Inc. ++ * Author: Yan Hua <yanh@lemote.com> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ |