diff options
Diffstat (limited to 'target/linux/patches/4.9.287')
| -rw-r--r-- | target/linux/patches/4.9.287/alpha-remove-coff.patch | 43 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/arm-nommu.patch | 80 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/arm-thumb2.patch | 16 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/crisv32_ethernet_driver.patch | 4048 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/h8300.patch | 44 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/hppa-remove-debug.patch | 12 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/initramfs-nosizelimit.patch | 57 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/ld-or1k.patch | 12 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/macsonic.patch | 11 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/microblaze-sigaltstack.patch | 12 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/or1k-more-ram.patch | 12 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/patch-realtime | 27718 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/sh2.patch | 11 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/startup.patch | 25 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/stm32.patch | 12 | ||||
| -rw-r--r-- | target/linux/patches/4.9.287/vdso2.patch | 27 |
16 files changed, 32140 insertions, 0 deletions
diff --git a/target/linux/patches/4.9.287/alpha-remove-coff.patch b/target/linux/patches/4.9.287/alpha-remove-coff.patch new file mode 100644 index 000000000..176db3c88 --- /dev/null +++ b/target/linux/patches/4.9.287/alpha-remove-coff.patch @@ -0,0 +1,43 @@ +diff -Nur linux-4.9.71.orig/arch/alpha/boot/tools/objstrip.c linux-4.9.71/arch/alpha/boot/tools/objstrip.c +--- linux-4.9.71.orig/arch/alpha/boot/tools/objstrip.c 2017-12-20 10:07:34.000000000 +0100 ++++ linux-4.9.71/arch/alpha/boot/tools/objstrip.c 2017-12-30 21:23:09.114510547 +0100 +@@ -191,38 +191,8 @@ + prog_name, (long) elf_phdr->p_vaddr, + elf_phdr->p_vaddr + fil_size, offset); + } +- } else +-#endif +- { +- aout = (struct exec *) buf; +- +- if (!(aout->fh.f_flags & COFF_F_EXEC)) { +- fprintf(stderr, "%s: %s is not in executable format\n", +- prog_name, inname); +- exit(1); +- } +- +- if (aout->fh.f_opthdr != sizeof(aout->ah)) { +- fprintf(stderr, "%s: %s has unexpected optional header size\n", +- prog_name, inname); +- exit(1); +- } +- +- if (N_MAGIC(*aout) != OMAGIC) { +- fprintf(stderr, "%s: %s is not an OMAGIC file\n", +- prog_name, inname); +- exit(1); +- } +- offset = N_TXTOFF(*aout); +- fil_size = aout->ah.tsize + aout->ah.dsize; +- mem_size = fil_size + aout->ah.bsize; +- +- if (verbose) { +- fprintf(stderr, "%s: extracting %#016lx-%#016lx (at %lx)\n", +- prog_name, aout->ah.text_start, +- aout->ah.text_start + fil_size, offset); +- } + } ++#endif + + if (lseek(fd, offset, SEEK_SET) != offset) { + perror("lseek"); diff --git a/target/linux/patches/4.9.287/arm-nommu.patch b/target/linux/patches/4.9.287/arm-nommu.patch new file mode 100644 index 000000000..a9e80f197 --- /dev/null +++ b/target/linux/patches/4.9.287/arm-nommu.patch @@ -0,0 +1,80 @@ +diff -Nur linux-4.9.88.orig/arch/arm/Kconfig linux-4.9.88/arch/arm/Kconfig +--- linux-4.9.88.orig/arch/arm/Kconfig 2018-03-18 11:18:56.000000000 +0100 ++++ linux-4.9.88/arch/arm/Kconfig 2018-04-01 04:36:26.415410694 +0100 +@@ -362,6 +362,17 @@ + help + Support for the Cortina Systems Gemini family SoCs + ++config ARM_SINGLE_ARCH_VERSATILE ++ bool "ARM Ltd. Versatile family" ++ depends on !MMU ++ select AUTO_ZRELADDR ++ select CLKSRC_OF ++ select COMMON_CLK ++ select GENERIC_CLOCKEVENTS ++ select GPIOLIB ++ select SPARSE_IRQ ++ select USE_OF ++ + config ARCH_EBSA110 + bool "EBSA-110" + select ARCH_USES_GETTIMEOFFSET +diff -Nur linux-4.9.88.orig/arch/arm/Kconfig.debug linux-4.9.88/arch/arm/Kconfig.debug +--- linux-4.9.88.orig/arch/arm/Kconfig.debug 2018-03-18 11:18:56.000000000 +0100 ++++ linux-4.9.88/arch/arm/Kconfig.debug 2018-04-01 04:36:26.415410694 +0100 +@@ -1712,7 +1712,8 @@ + config UNCOMPRESS_INCLUDE + string + default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ +- PLAT_SAMSUNG || ARM_SINGLE_ARMV7M ++ PLAT_SAMSUNG || ARM_SINGLE_ARMV7M || \ ++ ARM_SINGLE_ARCH_VERSATILE + default "mach/uncompress.h" + + config EARLY_PRINTK +diff -Nur linux-4.9.88.orig/arch/arm/include/asm/mach/map.h linux-4.9.88/arch/arm/include/asm/mach/map.h +--- linux-4.9.88.orig/arch/arm/include/asm/mach/map.h 2018-03-18 11:18:56.000000000 +0100 ++++ linux-4.9.88/arch/arm/include/asm/mach/map.h 2018-04-01 04:36:26.416410682 +0100 +@@ -62,6 +62,7 @@ + #else + #define iotable_init(map,num) do { } while (0) + #define vm_reserve_area_early(a,s,c) do { } while (0) ++#define debug_ll_io_init() do { } while (0) + #endif + + #endif +diff -Nur linux-4.9.88.orig/arch/arm/mach-versatile/Kconfig linux-4.9.88/arch/arm/mach-versatile/Kconfig +--- linux-4.9.88.orig/arch/arm/mach-versatile/Kconfig 2018-03-18 11:18:56.000000000 +0100 ++++ linux-4.9.88/arch/arm/mach-versatile/Kconfig 2018-04-01 04:37:41.424472952 +0100 +@@ -1,6 +1,7 @@ + config ARCH_VERSATILE +- bool "ARM Ltd. Versatile family" +- depends on ARCH_MULTI_V5 ++ bool "ARM Ltd. Versatile family" if ARCH_MULTI_V5 ++ depends on ARCH_MULTI_V5 || ARM_SINGLE_ARCH_VERSATILE ++ default y if ARM_SINGLE_ARCH_VERSATILE + select ARM_AMBA + select ARM_TIMER_SP804 + select ARM_VIC +diff -Nur linux-4.9.88.orig/arch/arm/mach-versatile/Makefile.boot linux-4.9.88/arch/arm/mach-versatile/Makefile.boot +--- linux-4.9.88.orig/arch/arm/mach-versatile/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 ++++ linux-4.9.88/arch/arm/mach-versatile/Makefile.boot 2018-04-01 04:36:26.417410669 +0100 +@@ -0,0 +1,3 @@ ++# Empty file waiting for deletion once Makefile.boot isn't needed any more. ++# Patch waits for application at ++# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . +diff -Nur linux-4.9.88.orig/arch/arm/mach-versatile/versatile_dt.c linux-4.9.88/arch/arm/mach-versatile/versatile_dt.c +--- linux-4.9.88.orig/arch/arm/mach-versatile/versatile_dt.c 2018-03-18 11:18:56.000000000 +0100 ++++ linux-4.9.88/arch/arm/mach-versatile/versatile_dt.c 2018-04-01 04:36:26.417410669 +0100 +@@ -37,7 +37,11 @@ + #include <asm/mach/map.h> + + /* macro to get at MMIO space when running virtually */ ++#ifdef CONFIG_MMU + #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++#else ++#define IO_ADDRESS(x) (x) ++#endif + #define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n)) + + /* diff --git a/target/linux/patches/4.9.287/arm-thumb2.patch b/target/linux/patches/4.9.287/arm-thumb2.patch new file mode 100644 index 000000000..6a42899b6 --- /dev/null +++ b/target/linux/patches/4.9.287/arm-thumb2.patch @@ -0,0 +1,16 @@ +diff -Nur linux-4.9.94.orig/arch/arm/include/asm/assembler.h linux-4.9.94/arch/arm/include/asm/assembler.h +--- linux-4.9.94.orig/arch/arm/include/asm/assembler.h 2018-04-13 18:48:37.000000000 +0100 ++++ linux-4.9.94/arch/arm/include/asm/assembler.h 2018-04-22 10:51:50.317450040 +0100 +@@ -192,10 +192,9 @@ + */ + .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo + .macro badr\c, rd, sym +-#ifdef CONFIG_THUMB2_KERNEL +- adr\c \rd, \sym + 1 +-#else + adr\c \rd, \sym ++#ifdef CONFIG_THUMB2_KERNEL ++ orr\c \rd, \rd, 1 + #endif + .endm + .endr diff --git a/target/linux/patches/4.9.287/crisv32_ethernet_driver.patch b/target/linux/patches/4.9.287/crisv32_ethernet_driver.patch new file mode 100644 index 000000000..0cef202fc --- /dev/null +++ b/target/linux/patches/4.9.287/crisv32_ethernet_driver.patch @@ -0,0 +1,4048 @@ +diff -Nur linux-4.7.3.orig/arch/cris/arch-v32/drivers/Kconfig linux-4.7.3/arch/cris/arch-v32/drivers/Kconfig +--- linux-4.7.3.orig/arch/cris/arch-v32/drivers/Kconfig 2016-09-07 08:35:12.000000000 +0200 ++++ linux-4.7.3/arch/cris/arch-v32/drivers/Kconfig 2016-09-13 01:47:09.507717605 +0200 +@@ -8,9 +8,18 @@ + This option enables the ETRAX FS built-in 10/100Mbit Ethernet + controller. + ++config ETRAX_HAVE_PHY ++ bool "PHY present" ++ default y ++ help ++ Search and use the first PHY available on the MDIO bus. Fail ++ if none is found. Say Y here if you are not in a switched ++ environment (single port device). ++ + config ETRAX_NO_PHY + bool "PHY not present" + depends on ETRAX_ETHERNET ++ default n + help + This option disables all MDIO communication with an ethernet + transceiver connected to the MII interface. This option shall +@@ -18,6 +27,70 @@ + switch. This option should normally be disabled. If enabled, + speed and duplex will be locked to 100 Mbit and full duplex. + ++config ETRAX_PHY_FALLBACK ++ bool "Fixed PHY fallback" ++ depends on ETRAX_ETHERNET ++ default n ++ help ++ If no PHY is found on the MDIO bus, fall back on a fixed ++ 100/Full fixed PHY. Say Y here if you need dynamic PHY ++ presence detection (switch connection where some but not ++ all ports have integrated PHYs), otherwise say N. ++ ++config ETRAX_ETHERNET_IFACE0 ++ depends on ETRAX_ETHERNET ++ bool "Enable network interface 0" ++ ++config ETRAX_ETHERNET_IFACE1 ++ depends on (ETRAX_ETHERNET && ETRAXFS) ++ bool "Enable network interface 1 (uses DMA6 and DMA7)" ++ ++choice ++ prompt "Eth0 led group" ++ depends on ETRAX_ETHERNET_IFACE0 ++ default ETRAX_ETH0_USE_LEDGRP0 ++ ++config ETRAX_ETH0_USE_LEDGRP0 ++ bool "Use LED grp 0" ++ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO ++ help ++ Use LED grp 0 for eth0 ++ ++config ETRAX_ETH0_USE_LEDGRP1 ++ bool "Use LED grp 1" ++ depends on ETRAX_NBR_LED_GRP_TWO ++ help ++ Use LED grp 1 for eth0 ++ ++config ETRAX_ETH0_USE_LEDGRPNULL ++ bool "Use no LEDs for eth0" ++ help ++ Use no LEDs for eth0 ++endchoice ++ ++choice ++ prompt "Eth1 led group" ++ depends on ETRAX_ETHERNET_IFACE1 ++ default ETRAX_ETH1_USE_LEDGRP1 ++ ++config ETRAX_ETH1_USE_LEDGRP0 ++ bool "Use LED grp 0" ++ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO ++ help ++ Use LED grp 0 for eth1 ++ ++config ETRAX_ETH1_USE_LEDGRP1 ++ bool "Use LED grp 1" ++ depends on ETRAX_NBR_LED_GRP_TWO ++ help ++ Use LED grp 1 for eth1 ++ ++config ETRAX_ETH1_USE_LEDGRPNULL ++ bool "Use no LEDs for eth1" ++ help ++ Use no LEDs for eth1 ++endchoice ++ + config ETRAXFS_SERIAL + bool "Serial-port support" + depends on ETRAX_ARCH_V32 +diff -Nur linux-4.7.3.orig/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h linux-4.7.3/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h +--- linux-4.7.3.orig/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h 2016-09-07 08:35:12.000000000 +0200 ++++ linux-4.7.3/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h 2016-09-13 01:47:09.527718381 +0200 +@@ -2,69 +2,64 @@ + #define __eth_defs_h + + /* +- * This file is autogenerated from +- * file: eth.r +- * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp +- * last modfied: Mon Jan 9 06:06:41 2006 +- * +- * by /n/asic/design/tools/rdesc/rdes2c eth.r +- * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ +- * Any changes here will be lost. +- * +- * -*- buffer-read-only: t -*- ++ * Note: Previously this was autogenerated code from the hardware ++ * implementation. However, to enable the same file to be used ++ * for both ARTPEC-3 and ETRAX FS this file is now hand-edited. ++ * Be careful. + */ ++ + /* Main access macros */ + #ifndef REG_RD + #define REG_RD( scope, inst, reg ) \ +- REG_READ( reg_##scope##_##reg, \ +- (inst) + REG_RD_ADDR_##scope##_##reg ) ++ REG_READ( reg_##scope##_##reg, \ ++ (inst) + REG_RD_ADDR_##scope##_##reg ) + #endif + + #ifndef REG_WR + #define REG_WR( scope, inst, reg, val ) \ +- REG_WRITE( reg_##scope##_##reg, \ +- (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) ++ REG_WRITE( reg_##scope##_##reg, \ ++ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) + #endif + + #ifndef REG_RD_VECT + #define REG_RD_VECT( scope, inst, reg, index ) \ +- REG_READ( reg_##scope##_##reg, \ +- (inst) + REG_RD_ADDR_##scope##_##reg + \ +- (index) * STRIDE_##scope##_##reg ) ++ REG_READ( reg_##scope##_##reg, \ ++ (inst) + REG_RD_ADDR_##scope##_##reg + \ ++ (index) * STRIDE_##scope##_##reg ) + #endif + + #ifndef REG_WR_VECT + #define REG_WR_VECT( scope, inst, reg, index, val ) \ +- REG_WRITE( reg_##scope##_##reg, \ +- (inst) + REG_WR_ADDR_##scope##_##reg + \ +- (index) * STRIDE_##scope##_##reg, (val) ) ++ REG_WRITE( reg_##scope##_##reg, \ ++ (inst) + REG_WR_ADDR_##scope##_##reg + \ ++ (index) * STRIDE_##scope##_##reg, (val) ) + #endif + + #ifndef REG_RD_INT + #define REG_RD_INT( scope, inst, reg ) \ +- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) ++ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) + #endif + + #ifndef REG_WR_INT + #define REG_WR_INT( scope, inst, reg, val ) \ +- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) ++ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) + #endif + + #ifndef REG_RD_INT_VECT + #define REG_RD_INT_VECT( scope, inst, reg, index ) \ +- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ +- (index) * STRIDE_##scope##_##reg ) ++ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ ++ (index) * STRIDE_##scope##_##reg ) + #endif + + #ifndef REG_WR_INT_VECT + #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ +- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ +- (index) * STRIDE_##scope##_##reg, (val) ) ++ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ ++ (index) * STRIDE_##scope##_##reg, (val) ) + #endif + + #ifndef REG_TYPE_CONV + #define REG_TYPE_CONV( type, orgtype, val ) \ +- ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) ++ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) + #endif + + #ifndef reg_page_size +@@ -73,306 +68,332 @@ + + #ifndef REG_ADDR + #define REG_ADDR( scope, inst, reg ) \ +- ( (inst) + REG_RD_ADDR_##scope##_##reg ) ++ ( (inst) + REG_RD_ADDR_##scope##_##reg ) + #endif + + #ifndef REG_ADDR_VECT + #define REG_ADDR_VECT( scope, inst, reg, index ) \ +- ( (inst) + REG_RD_ADDR_##scope##_##reg + \ +- (index) * STRIDE_##scope##_##reg ) ++ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ ++ (index) * STRIDE_##scope##_##reg ) + #endif + + /* C-code for register scope eth */ + + /* Register rw_ma0_lo, scope eth, type rw */ + typedef struct { +- unsigned int addr : 32; ++ unsigned int addr : 32; + } reg_eth_rw_ma0_lo; + #define REG_RD_ADDR_eth_rw_ma0_lo 0 + #define REG_WR_ADDR_eth_rw_ma0_lo 0 + + /* Register rw_ma0_hi, scope eth, type rw */ + typedef struct { +- unsigned int addr : 16; +- unsigned int dummy1 : 16; ++ unsigned int addr : 16; ++ unsigned int dummy1 : 16; + } reg_eth_rw_ma0_hi; + #define REG_RD_ADDR_eth_rw_ma0_hi 4 + #define REG_WR_ADDR_eth_rw_ma0_hi 4 + + /* Register rw_ma1_lo, scope eth, type rw */ + typedef struct { +- unsigned int addr : 32; ++ unsigned int addr : 32; + } reg_eth_rw_ma1_lo; + #define REG_RD_ADDR_eth_rw_ma1_lo 8 + #define REG_WR_ADDR_eth_rw_ma1_lo 8 + + /* Register rw_ma1_hi, scope eth, type rw */ + typedef struct { +- unsigned int addr : 16; +- unsigned int dummy1 : 16; ++ unsigned int addr : 16; ++ unsigned int dummy1 : 16; + } reg_eth_rw_ma1_hi; + #define REG_RD_ADDR_eth_rw_ma1_hi 12 + #define REG_WR_ADDR_eth_rw_ma1_hi 12 + + /* Register rw_ga_lo, scope eth, type rw */ + typedef struct { +- unsigned int tbl : 32; ++ unsigned int table : 32; + } reg_eth_rw_ga_lo; + #define REG_RD_ADDR_eth_rw_ga_lo 16 + #define REG_WR_ADDR_eth_rw_ga_lo 16 + + /* Register rw_ga_hi, scope eth, type rw */ + typedef struct { +- unsigned int tbl : 32; ++ unsigned int table : 32; + } reg_eth_rw_ga_hi; + #define REG_RD_ADDR_eth_rw_ga_hi 20 + #define REG_WR_ADDR_eth_rw_ga_hi 20 + + /* Register rw_gen_ctrl, scope eth, type rw */ + typedef struct { +- unsigned int en : 1; +- unsigned int phy : 2; +- unsigned int protocol : 1; +- unsigned int loopback : 1; +- unsigned int flow_ctrl : 1; +- unsigned int gtxclk_out : 1; +- unsigned int phyrst_n : 1; +- unsigned int dummy1 : 24; ++ unsigned int en : 1; ++ unsigned int phy : 2; ++ unsigned int protocol : 1; ++ unsigned int loopback : 1; ++ unsigned int flow_ctrl : 1; ++ unsigned int gtxclk_out : 1; ++ unsigned int phyrst_n : 1; ++ unsigned int dummy1 : 24; + } reg_eth_rw_gen_ctrl; + #define REG_RD_ADDR_eth_rw_gen_ctrl 24 + #define REG_WR_ADDR_eth_rw_gen_ctrl 24 + + /* Register rw_rec_ctrl, scope eth, type rw */ + typedef struct { +- unsigned int ma0 : 1; +- unsigned int ma1 : 1; +- unsigned int individual : 1; +- unsigned int broadcast : 1; +- unsigned int undersize : 1; +- unsigned int oversize : 1; +- unsigned int bad_crc : 1; +- unsigned int duplex : 1; +- unsigned int max_size : 16; +- unsigned int dummy1 : 8; ++ unsigned int ma0 : 1; ++ unsigned int ma1 : 1; ++ unsigned int individual : 1; ++ unsigned int broadcast : 1; ++ unsigned int undersize : 1; ++ unsigned int oversize : 1; ++ unsigned int bad_crc : 1; ++ unsigned int duplex : 1; ++#ifdef CONFIG_CRIS_MACH_ARTPEC3 ++ unsigned int max_size : 16; ++ unsigned int dummy1 : 8; ++#else ++ unsigned int max_size : 1; ++ unsigned int dummy1 : 23; ++#endif + } reg_eth_rw_rec_ctrl; + #define REG_RD_ADDR_eth_rw_rec_ctrl 28 + #define REG_WR_ADDR_eth_rw_rec_ctrl 28 + + /* Register rw_tr_ctrl, scope eth, type rw */ + typedef struct { +- unsigned int crc : 1; +- unsigned int pad : 1; +- unsigned int retry : 1; +- unsigned int ignore_col : 1; +- unsigned int cancel : 1; +- unsigned int hsh_delay : 1; +- unsigned int ignore_crs : 1; +- unsigned int carrier_ext : 1; +- unsigned int dummy1 : 24; ++ unsigned int crc : 1; ++ unsigned int pad : 1; ++ unsigned int retry : 1; ++ unsigned int ignore_col : 1; ++ unsigned int cancel : 1; ++ unsigned int hsh_delay : 1; ++ unsigned int ignore_crs : 1; ++ unsigned int carrier_ext : 1; ++ unsigned int dummy1 : 24; + } reg_eth_rw_tr_ctrl; + #define REG_RD_ADDR_eth_rw_tr_ctrl 32 + #define REG_WR_ADDR_eth_rw_tr_ctrl 32 + + /* Register rw_clr_err, scope eth, type rw */ + typedef struct { +- unsigned int clr : 1; +- unsigned int dummy1 : 31; ++ unsigned int clr : 1; ++ unsigned int dummy1 : 31; + } reg_eth_rw_clr_err; + #define REG_RD_ADDR_eth_rw_clr_err 36 + #define REG_WR_ADDR_eth_rw_clr_err 36 + + /* Register rw_mgm_ctrl, scope eth, type rw */ + typedef struct { +- unsigned int mdio : 1; +- unsigned int mdoe : 1; +- unsigned int mdc : 1; +- unsigned int dummy1 : 29; ++ unsigned int mdio : 1; ++ unsigned int mdoe : 1; ++ unsigned int mdc : 1; ++ unsigned int phyclk : 1; ++ unsigned int txdata : 4; ++ unsigned int txen : 1; ++ unsigned int dummy1 : 23; + } reg_eth_rw_mgm_ctrl; + #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 + #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 + + /* Register r_stat, scope eth, type r */ + typedef struct { +- unsigned int mdio : 1; +- unsigned int exc_col : 1; +- unsigned int urun : 1; +- unsigned int clk_125 : 1; +- unsigned int dummy1 : 28; ++ unsigned int mdio : 1; ++ unsigned int exc_col : 1; ++ unsigned int urun : 1; ++#ifdef CONFIG_CRIS_MACH_ARTPEC3 ++ unsigned int clk_125 : 1; ++#else ++ unsigned int phyclk : 1; ++#endif ++ unsigned int txdata : 4; ++ unsigned int txen : 1; ++ unsigned int col : 1; ++ unsigned int crs : 1; ++ unsigned int txclk : 1; ++ unsigned int rxdata : 4; ++ unsigned int rxer : 1; ++ unsigned int rxdv : 1; ++ unsigned int rxclk : 1; ++ unsigned int dummy1 : 13; + } reg_eth_r_stat; + #define REG_RD_ADDR_eth_r_stat 44 + + /* Register rs_rec_cnt, scope eth, type rs */ + typedef struct { +- unsigned int crc_err : 8; +- unsigned int align_err : 8; +- unsigned int oversize : 8; +- unsigned int congestion : 8; ++ unsigned int crc_err : 8; ++ unsigned int align_err : 8; ++ unsigned int oversize : 8; ++ unsigned int congestion : 8; + } reg_eth_rs_rec_cnt; + #define REG_RD_ADDR_eth_rs_rec_cnt 48 + + /* Register r_rec_cnt, scope eth, type r */ + typedef struct { +- unsigned int crc_err : 8; +- unsigned int align_err : 8; +- unsigned int oversize : 8; +- unsigned int congestion : 8; ++ unsigned int crc_err : 8; ++ unsigned int align_err : 8; ++ unsigned int oversize : 8; ++ unsigned int congestion : 8; + } reg_eth_r_rec_cnt; + #define REG_RD_ADDR_eth_r_rec_cnt 52 + + /* Register rs_tr_cnt, scope eth, type rs */ + typedef struct { +- unsigned int single_col : 8; +- unsigned int mult_col : 8; +- unsigned int late_col : 8; +- unsigned int deferred : 8; ++ unsigned int single_col : 8; ++ unsigned int mult_col : 8; ++ unsigned int late_col : 8; ++ unsigned int deferred : 8; + } reg_eth_rs_tr_cnt; + #define REG_RD_ADDR_eth_rs_tr_cnt 56 + + /* Register r_tr_cnt, scope eth, type r */ + typedef struct { +- unsigned int single_col : 8; +- unsigned int mult_col : 8; +- unsigned int late_col : 8; +- unsigned int deferred : 8; ++ unsigned int single_col : 8; ++ unsigned int mult_col : 8; ++ unsigned int late_col : 8; ++ unsigned int deferred : 8; + } reg_eth_r_tr_cnt; + #define REG_RD_ADDR_eth_r_tr_cnt 60 + + /* Register rs_phy_cnt, scope eth, type rs */ + typedef struct { +- unsigned int carrier_loss : 8; +- unsigned int sqe_err : 8; +- unsigned int dummy1 : 16; ++ unsigned int carrier_loss : 8; ++ unsigned int sqe_err : 8; ++ unsigned int dummy1 : 16; + } reg_eth_rs_phy_cnt; + #define REG_RD_ADDR_eth_rs_phy_cnt 64 + + /* Register r_phy_cnt, scope eth, type r */ + typedef struct { +- unsigned int carrier_loss : 8; +- unsigned int sqe_err : 8; +- unsigned int dummy1 : 16; ++ unsigned int carrier_loss : 8; ++ unsigned int sqe_err : 8; ++ unsigned int dummy1 : 16; + } reg_eth_r_phy_cnt; + #define REG_RD_ADDR_eth_r_phy_cnt 68 + + /* Register rw_test_ctrl, scope eth, type rw */ + typedef struct { +- unsigned int snmp_inc : 1; +- unsigned int snmp : 1; +- unsigned int backoff : 1; +- unsigned int dummy1 : 29; ++ unsigned int snmp_inc : 1; ++ unsigned int snmp : 1; ++ unsigned int backoff : 1; ++ unsigned int dummy1 : 29; + } reg_eth_rw_test_ctrl; + #define REG_RD_ADDR_eth_rw_test_ctrl 72 + #define REG_WR_ADDR_eth_rw_test_ctrl 72 + + /* Register rw_intr_mask, scope eth, type rw */ + typedef struct { +- unsigned int crc : 1; +- unsigned int align : 1; +- unsigned int oversize : 1; +- unsigned int congestion : 1; +- unsigned int single_col : 1; +- unsigned int mult_col : 1; +- unsigned int late_col : 1; +- unsigned int deferred : 1; +- unsigned int carrier_loss : 1; +- unsigned int sqe_test_err : 1; +- unsigned int orun : 1; +- unsigned int urun : 1; +- unsigned int exc_col : 1; +- unsigned int mdio : 1; +- unsigned int dummy1 : 18; ++ unsigned int crc : 1; ++ unsigned int align : 1; ++ unsigned int oversize : 1; ++ unsigned int congestion : 1; ++ unsigned int single_col : 1; ++ unsigned int mult_col : 1; ++ unsigned int late_col : 1; ++ unsigned int deferred : 1; ++ unsigned int carrier_loss : 1; ++ unsigned int sqe_test_err : 1; ++ unsigned int orun : 1; ++ unsigned int urun : 1; ++ unsigned int exc_col : 1; ++ unsigned int mdio : 1; ++ unsigned int dummy1 : 18; + } reg_eth_rw_intr_mask; + #define REG_RD_ADDR_eth_rw_intr_mask 76 + #define REG_WR_ADDR_eth_rw_intr_mask 76 + + /* Register rw_ack_intr, scope eth, type rw */ + typedef struct { +- unsigned int crc : 1; +- unsigned int align : 1; +- unsigned int oversize : 1; +- unsigned int congestion : 1; +- unsigned int single_col : 1; +- unsigned int mult_col : 1; +- unsigned int late_col : 1; +- unsigned int deferred : 1; +- unsigned int carrier_loss : 1; +- unsigned int sqe_test_err : 1; +- unsigned int orun : 1; +- unsigned int urun : 1; +- unsigned int exc_col : 1; +- unsigned int mdio : 1; +- unsigned int dummy1 : 18; ++ unsigned int crc : 1; ++ unsigned int align : 1; ++ unsigned int oversize : 1; ++ unsigned int congestion : 1; ++ unsigned int single_col : 1; ++ unsigned int mult_col : 1; ++ unsigned int late_col : 1; ++ unsigned int deferred : 1; ++ unsigned int carrier_loss : 1; ++ unsigned int sqe_test_err : 1; ++ unsigned int orun : 1; ++ unsigned int urun : 1; ++ unsigned int exc_col : 1; ++ unsigned int mdio : 1; ++ unsigned int dummy1 : 18; + } reg_eth_rw_ack_intr; + #define REG_RD_ADDR_eth_rw_ack_intr 80 + #define REG_WR_ADDR_eth_rw_ack_intr 80 + + /* Register r_intr, scope eth, type r */ + typedef struct { +- unsigned int crc : 1; +- unsigned int align : 1; +- unsigned int oversize : 1; +- unsigned int congestion : 1; +- unsigned int single_col : 1; +- unsigned int mult_col : 1; +- unsigned int late_col : 1; +- unsigned int deferred : 1; +- unsigned int carrier_loss : 1; +- unsigned int sqe_test_err : 1; +- unsigned int orun : 1; +- unsigned int urun : 1; +- unsigned int exc_col : 1; +- unsigned int mdio : 1; +- unsigned int dummy1 : 18; ++ unsigned int crc : 1; ++ unsigned int align : 1; ++ unsigned int oversize : 1; ++ unsigned int congestion : 1; ++ unsigned int single_col : 1; ++ unsigned int mult_col : 1; ++ unsigned int late_col : 1; ++ unsigned int deferred : 1; ++ unsigned int carrier_loss : 1; ++ unsigned int sqe_test_err : 1; ++ unsigned int orun : 1; ++ unsigned int urun : 1; ++ unsigned int exc_col : 1; ++ unsigned int mdio : 1; ++ unsigned int dummy1 : 18; + } reg_eth_r_intr; + #define REG_RD_ADDR_eth_r_intr 84 + + /* Register r_masked_intr, scope eth, type r */ + typedef struct { +- unsigned int crc : 1; +- unsigned int align : 1; +- unsigned int oversize : 1; +- unsigned int congestion : 1; +- unsigned int single_col : 1; +- unsigned int mult_col : 1; +- unsigned int late_col : 1; +- unsigned int deferred : 1; +- unsigned int carrier_loss : 1; +- unsigned int sqe_test_err : 1; +- unsigned int orun : 1; +- unsigned int urun : 1; +- unsigned int exc_col : 1; +- unsigned int mdio : 1; +- unsigned int dummy1 : 18; ++ unsigned int crc : 1; ++ unsigned int align : 1; ++ unsigned int oversize : 1; ++ unsigned int congestion : 1; ++ unsigned int single_col : 1; ++ unsigned int mult_col : 1; ++ unsigned int late_col : 1; ++ unsigned int deferred : 1; ++ unsigned int carrier_loss : 1; ++ unsigned int sqe_test_err : 1; ++ unsigned int orun : 1; ++ unsigned int urun : 1; ++ unsigned int exc_col : 1; ++ unsigned int mdio : 1; ++ unsigned int dummy1 : 18; + } reg_eth_r_masked_intr; + #define REG_RD_ADDR_eth_r_masked_intr 88 + +- + /* Constants */ + enum { +- regk_eth_discard = 0x00000000, +- regk_eth_ether = 0x00000000, +- regk_eth_full = 0x00000001, +- regk_eth_gmii = 0x00000003, +- regk_eth_gtxclk = 0x00000001, +- regk_eth_half = 0x00000000, +- regk_eth_hsh = 0x00000001, +- regk_eth_mii = 0x00000001, +- regk_eth_mii_arec = 0x00000002, +- regk_eth_mii_clk = 0x00000000, +- regk_eth_no = 0x00000000, +- regk_eth_phyrst = 0x00000000, +- regk_eth_rec = 0x00000001, +- regk_eth_rw_ga_hi_default = 0x00000000, +- regk_eth_rw_ga_lo_default = 0x00000000, +- regk_eth_rw_gen_ctrl_default = 0x00000000, +- regk_eth_rw_intr_mask_default = 0x00000000, +- regk_eth_rw_ma0_hi_default = 0x00000000, +- regk_eth_rw_ma0_lo_default = 0x00000000, +- regk_eth_rw_ma1_hi_default = 0x00000000, +- regk_eth_rw_ma1_lo_default = 0x00000000, +- regk_eth_rw_mgm_ctrl_default = 0x00000000, +- regk_eth_rw_test_ctrl_default = 0x00000000, +- regk_eth_size1518 = 0x000005ee, +- regk_eth_size1522 = 0x000005f2, +- regk_eth_yes = 0x00000001 ++ regk_eth_discard = 0x00000000, ++ regk_eth_ether = 0x00000000, ++ regk_eth_full = 0x00000001, ++ regk_eth_gmii = 0x00000003, ++ regk_eth_gtxclk = 0x00000001, ++ regk_eth_half = 0x00000000, ++ regk_eth_hsh = 0x00000001, ++ regk_eth_mii = 0x00000001, ++ regk_eth_mii_arec = 0x00000002, ++ regk_eth_mii_clk = 0x00000000, ++ regk_eth_no = 0x00000000, ++ regk_eth_phyrst = 0x00000000, ++ regk_eth_rec = 0x00000001, ++ regk_eth_rw_ga_hi_default = 0x00000000, ++ regk_eth_rw_ga_lo_default = 0x00000000, ++ regk_eth_rw_gen_ctrl_default = 0x00000000, ++ regk_eth_rw_intr_mask_default = 0x00000000, ++ regk_eth_rw_ma0_hi_default = 0x00000000, ++ regk_eth_rw_ma0_lo_default = 0x00000000, ++ regk_eth_rw_ma1_hi_default = 0x00000000, ++ regk_eth_rw_ma1_lo_default = 0x00000000, ++ regk_eth_rw_mgm_ctrl_default = 0x00000000, ++ regk_eth_rw_test_ctrl_default = 0x00000000, ++#ifdef CONFIG_CRIS_MACH_ARTPEC3 ++ regk_eth_size1518 = 0x000005ee, ++ regk_eth_size1522 = 0x000005f2, ++#else ++ regk_eth_size1518 = 0x00000000, ++ regk_eth_size1522 = 0x00000001, ++#endif ++ regk_eth_yes = 0x00000001 + }; ++ + #endif /* __eth_defs_h */ +diff -Nur linux-4.7.3.orig/drivers/net/cris/eth_v32.c linux-4.7.3/drivers/net/cris/eth_v32.c +--- linux-4.7.3.orig/drivers/net/cris/eth_v32.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-4.7.3/drivers/net/cris/eth_v32.c 2016-09-13 01:48:05.953910422 +0200 +@@ -0,0 +1,3060 @@ ++/* ++ * Driver for the ETRAX FS/Artpec-3 network controller. ++ * ++ * Copyright (c) 2003-2008 Axis Communications AB. ++ * ++ * TODO: ++ * * Decrease the amount of code running with interrupts disabled. ++ * * Rework the error handling so that we do not need to touch the tx ++ * ring from the error interrupts. When done, we should be able to ++ * do tx completition from the NAPI loop without disabling interrupts. ++ * * Remove the gigabit code. It's probably never going to be used. ++ */ ++ ++#include <linux/module.h> ++ ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/delay.h> ++#include <linux/types.h> ++#include <linux/fcntl.h> ++#include <linux/interrupt.h> ++#include <linux/spinlock.h> ++#include <linux/errno.h> ++#include <linux/init.h> ++ ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/ethtool.h> ++#include <linux/mii.h> ++ ++#include <asm/io.h> /* CRIS_LED_* I/O functions */ ++#include <asm/irq.h> ++#include <hwregs/reg_map.h> ++#include <hwregs/reg_rdwr.h> ++#include <hwregs/dma.h> ++#include <hwregs/eth_defs.h> ++#ifdef CONFIG_ETRAXFS ++#include <hwregs/config_defs.h> ++#else ++#include <hwregs/clkgen_defs.h> ++#endif ++#include <hwregs/intr_vect_defs.h> ++#include <hwregs/strmux_defs.h> ++#include <asm/bitops.h> ++#include <asm/ethernet.h> ++#include <mach/dma.h> ++#include <pinmux.h> ++ ++#include "eth_v32.h" ++ ++#ifndef CONFIG_ETRAXFS ++#define ETH0_INTR_VECT ETH_INTR_VECT ++#define ETH1_INTR_VECT ETH_INTR_VECT ++#define regi_eth0 regi_eth ++#define regi_eth1 regi_ ++#endif ++ ++#define DEBUG(x) ++#define GET_BIT(bit,val) (((val) >> (bit)) & 0x01) ++ ++#if defined(CONFIG_ETRAX_HAVE_PHY) || defined(CONFIG_ETRAX_PHY_FALLBACK) ++#define RESET_PHY 1 ++#else ++#define RESET_PHY 0 ++#endif ++ ++enum { ++ HAVE_PHY, ++ NO_PHY, ++ FALLBACK_PHY, ++}; ++#if defined(CONFIG_ETRAX_PHY_FALLBACK) ++#define PHY_MODE (FALLBACK_PHY) ++#elif defined(CONFIG_ETRAX_NO_PHY) ++#define PHY_MODE (NO_PHY) ++#elif defined(CONFIG_ETRAX_HAVE_PHY) ++#define PHY_MODE (HAVE_PHY) ++#else ++#error Unknown PHY behaviour ++#endif ++ ++static struct { ++ const char str[ETH_GSTRING_LEN]; ++} const ethtool_stats_keys[] = { ++ { "tx_dma_restarts" }, ++ { "tx_mac_resets" }, ++ { "rx_dma_restarts" }, ++ { "rx_dma_timeouts" }, ++ { " dropped_rx" } ++}; |