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-rw-r--r--target/config/Config.in.binfmt3
-rw-r--r--target/config/Config.in.cpu3
-rw-r--r--target/config/Config.in.libc1
-rw-r--r--target/linux/patches/6.0.15/riscv32.patch49
-rw-r--r--target/riscv32/Makefile3
-rw-r--r--target/riscv32/kernel/qemu-riscv3222
-rw-r--r--toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch46
-rw-r--r--toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch66
8 files changed, 177 insertions, 16 deletions
diff --git a/target/config/Config.in.binfmt b/target/config/Config.in.binfmt
index 0986c6f23..7da792992 100644
--- a/target/config/Config.in.binfmt
+++ b/target/config/Config.in.binfmt
@@ -16,7 +16,8 @@ config ADK_TARGET_BINFMT_FLAT
depends on ADK_TARGET_LIB_UCLIBC_NG
depends on !ADK_TARGET_WITH_MMU
depends on ADK_TARGET_ARCH_ARM || ADK_TARGET_ARCH_M68K || ADK_TARGET_ARCH_SH || ADK_TARGET_ARCH_XTENSA \
- || ADK_TARGET_ARCH_H8300 || ADK_TARGET_ARCH_LM32 || ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_RISCV64
+ || ADK_TARGET_ARCH_H8300 || ADK_TARGET_ARCH_LM32 || ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_RISCV64 \
+ || ADK_TARGET_ARCH_RISCV32
config ADK_TARGET_BINFMT_FDPIC
bool "FDPIC"
diff --git a/target/config/Config.in.cpu b/target/config/Config.in.cpu
index 56befd8ef..eaf0eea02 100644
--- a/target/config/Config.in.cpu
+++ b/target/config/Config.in.cpu
@@ -1146,7 +1146,6 @@ config ADK_TARGET_CPU_RISCV32_RV32IMAC
bool "rv32imac"
select ADK_TARGET_SUPPORTS_THREADS
select ADK_TARGET_SUPPORTS_NPTL
- select ADK_TARGET_WITH_MMU
select ADK_TARGET_ABI_ILP32
depends on ADK_TARGET_ARCH_RISCV32
@@ -1154,7 +1153,6 @@ config ADK_TARGET_CPU_RISCV32_RV32IMAFC
bool "rv32imafc"
select ADK_TARGET_SUPPORTS_THREADS
select ADK_TARGET_SUPPORTS_NPTL
- select ADK_TARGET_WITH_MMU
select ADK_TARGET_ABI_ILP32F
depends on ADK_TARGET_ARCH_RISCV32
@@ -1162,7 +1160,6 @@ config ADK_TARGET_CPU_RISCV32_RV32IMADC
bool "rv32imadc"
select ADK_TARGET_SUPPORTS_THREADS
select ADK_TARGET_SUPPORTS_NPTL
- select ADK_TARGET_WITH_MMU
select ADK_TARGET_ABI_ILP32D
depends on ADK_TARGET_ARCH_RISCV32
diff --git a/target/config/Config.in.libc b/target/config/Config.in.libc
index 477dcd10a..5a75cdb1c 100644
--- a/target/config/Config.in.libc
+++ b/target/config/Config.in.libc
@@ -34,6 +34,7 @@ config ADK_TARGET_LIB_UCLIBC_NG
ADK_TARGET_ARCH_NIOS2 || \
ADK_TARGET_ARCH_OR1K || \
ADK_TARGET_ARCH_PPC || \
+ ADK_TARGET_ARCH_RISCV32 || \
ADK_TARGET_ARCH_RISCV64 || \
ADK_TARGET_ARCH_SH || \
ADK_TARGET_ARCH_SPARC || \
diff --git a/target/linux/patches/6.0.15/riscv32.patch b/target/linux/patches/6.0.15/riscv32.patch
new file mode 100644
index 000000000..648b0de4d
--- /dev/null
+++ b/target/linux/patches/6.0.15/riscv32.patch
@@ -0,0 +1,49 @@
+diff -Nur linux-6.0.15.orig/arch/riscv/include/uapi/asm/unistd.h linux-6.0.15/arch/riscv/include/uapi/asm/unistd.h
+--- linux-6.0.15.orig/arch/riscv/include/uapi/asm/unistd.h 2022-12-21 17:41:16.000000000 +0100
++++ linux-6.0.15/arch/riscv/include/uapi/asm/unistd.h 2023-01-09 11:28:16.590796198 +0100
+@@ -15,9 +15,14 @@
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+-#if defined(__LP64__) && !defined(__SYSCALL_COMPAT)
++#ifndef __SYSCALL_COMPAT
+ #define __ARCH_WANT_NEW_STAT
+ #define __ARCH_WANT_SET_GET_RLIMIT
++#endif /* __SYSCALL_COMPAT */
++
++#ifndef __LP64__
++#define __ARCH_WANT_STAT64
++#define __ARCH_WANT_TIME32_SYSCALLS
+ #endif /* __LP64__ */
+
+ #define __ARCH_WANT_SYS_CLONE3
+diff -Nur linux-6.0.15.orig/arch/riscv/Kconfig linux-6.0.15/arch/riscv/Kconfig
+--- linux-6.0.15.orig/arch/riscv/Kconfig 2022-12-21 17:41:16.000000000 +0100
++++ linux-6.0.15/arch/riscv/Kconfig 2023-01-09 14:27:16.560750598 +0100
+@@ -163,8 +163,9 @@
+
+ config PAGE_OFFSET
+ hex
+- default 0xC0000000 if 32BIT
++ default 0xC0000000 if 32BIT && MMU
+ default 0x80000000 if 64BIT && !MMU
++ default 0x80000000 if !MMU
+ default 0xff60000000000000 if 64BIT
+
+ config KASAN_SHADOW_OFFSET
+@@ -262,7 +263,6 @@
+ select GENERIC_LIB_ASHRDI3
+ select GENERIC_LIB_LSHRDI3
+ select GENERIC_LIB_UCMPDI2
+- select MMU
+
+ config ARCH_RV64I
+ bool "RV64I"
+@@ -670,7 +670,6 @@
+ default !NONPORTABLE
+ select EFI
+ select OF
+- select MMU
+
+ menu "Power management options"
+
diff --git a/target/riscv32/Makefile b/target/riscv32/Makefile
index 577ef3f15..08d4d57ba 100644
--- a/target/riscv32/Makefile
+++ b/target/riscv32/Makefile
@@ -7,6 +7,9 @@ include $(ADK_TOPDIR)/mk/image.mk
KERNEL:=$(LINUX_DIR)/arch/riscv/boot/Image
QEMU_ARGS:=-M virt -m 512 -nographic
+ifeq ($(ADK_TARGET_LIB_UCLIBC_NG),y)
+QEMU_ARGS+=-bios none
+endif
ifeq ($(ADK_TARGET_QEMU_WITH_VIRTIO),y)
QEMU_ARGS+=-netdev user,id=eth0 -device virtio-net-device,netdev=eth0
endif
diff --git a/target/riscv32/kernel/qemu-riscv32 b/target/riscv32/kernel/qemu-riscv32
index a1ef83228..8fa8b13ac 100644
--- a/target/riscv32/kernel/qemu-riscv32
+++ b/target/riscv32/kernel/qemu-riscv32
@@ -1,14 +1,12 @@
CONFIG_RISCV=y
-CONFIG_ARCH_RV32I=y
-CONFIG_CMODEL_MEDANY=y
-CONFIG_CPU_RV_GENERIC=y
-CONFIG_RV_SYSRISCV_ATOMIC=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_32BIT=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_RISCV_SBI=y
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_SOC_SIFIVE=y
-CONFIG_SERIAL_SIFIVE=y
-CONFIG_SERIAL_SIFIVE_CONSOLE=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_ARCH_RV32I=y
+CONFIG_SOC_VIRT=y
+CONFIG_NONPORTABLE=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
diff --git a/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch
new file mode 100644
index 000000000..be5b0c33e
--- /dev/null
+++ b/toolchain/elf2flt/patches/v2021.08/0006-elf2flt-xtensa-fix-text-relocations.patch
@@ -0,0 +1,46 @@
+diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c
+--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-09 11:08:28.637676113 +0100
++++ elf2flt-v2021.08/elf2flt.c 2023-01-09 11:09:04.502804007 +0100
+@@ -835,7 +835,20 @@
+ continue;
+ case R_XTENSA_32:
+ case R_XTENSA_PLT:
+- goto good_32bit_resolved_reloc;
++ if (bfd_big_endian (abs_bfd))
++ sym_addr =
++ (r_mem[0] << 24)
++ + (r_mem[1] << 16)
++ + (r_mem[2] << 8)
++ + r_mem[3];
++ else
++ sym_addr =
++ r_mem[0]
++ + (r_mem[1] << 8)
++ + (r_mem[2] << 16)
++ + (r_mem[3] << 24);
++ relocation_needed = 1;
++ break;
+ default:
+ goto bad_resolved_reloc;
+ #elif defined(TARGET_riscv64)
+diff -Nur elf2flt-v2021.08.orig/elf2flt.c.orig elf2flt-v2021.08/elf2flt.c.orig
+--- elf2flt-v2021.08.orig/elf2flt.c.orig 2023-01-09 11:08:22.417478947 +0100
++++ elf2flt-v2021.08/elf2flt.c.orig 2023-01-09 11:08:28.637676113 +0100
+@@ -349,8 +349,15 @@
+ static bool
+ ro_reloc_data_section_should_be_in_text(asection *s)
+ {
+- return (s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
+- (SEC_DATA | SEC_READONLY | SEC_RELOC);
++ if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
++ (SEC_DATA | SEC_READONLY | SEC_RELOC)) {
++#if defined(TARGET_m68k) || defined(TARGET_riscv64) || defined(TARGET_xtensa)
++ if (!strcmp(".eh_frame", s->name))
++ return false;
++#endif
++ return true;
++ }
++ return false;
+ }
+
+ static uint32_t *
diff --git a/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch
new file mode 100644
index 000000000..dad501482
--- /dev/null
+++ b/toolchain/elf2flt/patches/v2021.08/0007-riscv32.patch
@@ -0,0 +1,66 @@
+diff -Nur elf2flt-v2021.08.orig/elf2flt.c elf2flt-v2021.08/elf2flt.c
+--- elf2flt-v2021.08.orig/elf2flt.c 2023-01-09 11:08:28.637676113 +0100
++++ elf2flt-v2021.08/elf2flt.c 2023-01-09 11:16:05.447182514 +0100
+@@ -81,7 +81,7 @@
+ #include <elf/v850.h>
+ #elif defined(TARGET_xtensa)
+ #include <elf/xtensa.h>
+-#elif defined(TARGET_riscv64)
++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
+ #include <elf/riscv.h>
+ #endif
+
+@@ -127,6 +127,8 @@
+ #define ARCH "xtensa"
+ #elif defined(TARGET_riscv64)
+ #define ARCH "riscv64"
++#elif defined(TARGET_riscv32)
++#define ARCH "riscv32"
+ #else
+ #error "Don't know how to support your CPU architecture??"
+ #endif
+@@ -351,7 +353,8 @@
+ {
+ if ((s->flags & (SEC_DATA | SEC_READONLY | SEC_RELOC)) ==
+ (SEC_DATA | SEC_READONLY | SEC_RELOC)) {
+-#if defined(TARGET_m68k) || defined(TARGET_riscv64) || defined(TARGET_xtensa)
++#if defined(TARGET_m68k) || defined(TARGET_riscv64) || \
++ defined(TARGET_xtensa) || defined(TARGET_riscv32)
+ if (!strcmp(".eh_frame", s->name))
+ return false;
+ #endif
+@@ -838,12 +841,21 @@
+ goto good_32bit_resolved_reloc;
+ default:
+ goto bad_resolved_reloc;
+-#elif defined(TARGET_riscv64)
++#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
+ case R_RISCV_32_PCREL:
++ case R_RISCV_ADD8:
++ case R_RISCV_ADD16:
+ case R_RISCV_ADD32:
+ case R_RISCV_ADD64:
++ case R_RISCV_SUB6:
++ case R_RISCV_SUB8:
++ case R_RISCV_SUB16:
+ case R_RISCV_SUB32:
+ case R_RISCV_SUB64:
++ case R_RISCV_SET6:
++ case R_RISCV_SET8:
++ case R_RISCV_SET16:
++ case R_RISCV_SET32:
+ continue;
+ case R_RISCV_32:
+ case R_RISCV_64:
+diff -Nur elf2flt-v2021.08.orig/ld-elf2flt.c elf2flt-v2021.08/ld-elf2flt.c
+--- elf2flt-v2021.08.orig/ld-elf2flt.c 2023-01-09 11:08:16.441289072 +0100
++++ elf2flt-v2021.08/ld-elf2flt.c 2023-01-09 11:16:43.236237537 +0100
+@@ -327,7 +327,7 @@
+ /* riscv adds a global pointer symbol to the linker file with the
+ "RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
+ the entire line for other architectures. */
+- if (streq(TARGET_CPU, "riscv64"))
++ if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
+ append_sed(&sed, "^RISCV_GP:", "");
+ else
+ append_sed(&sed, "^RISCV_GP:", NULL);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 12:25:28 +0000