diff options
| -rw-r--r-- | mk/image.mk | 2 | ||||
| -rw-r--r-- | mk/kernel-ver.mk | 6 | ||||
| -rw-r--r-- | package/musl/Makefile | 7 | ||||
| -rw-r--r-- | target/config/Config.in.binfmt | 3 | ||||
| -rw-r--r-- | target/config/Config.in.binutils | 3 | ||||
| -rw-r--r-- | target/config/Config.in.compiler | 3 | ||||
| -rw-r--r-- | target/config/Config.in.cpu | 14 | ||||
| -rw-r--r-- | target/config/Config.in.kernelcfg | 4 | ||||
| -rw-r--r-- | target/config/Config.in.kernelcmd | 1 | ||||
| -rw-r--r-- | target/config/Config.in.kernelversion | 16 | ||||
| -rw-r--r-- | target/config/Config.in.libc | 4 | ||||
| -rw-r--r-- | target/config/Config.in.runtime | 1 | ||||
| -rw-r--r-- | target/config/Config.in.toolchain | 3 | ||||
| -rw-r--r-- | target/config/Config.in.tools | 4 | ||||
| -rw-r--r-- | target/linux/config/Config.in.serial | 6 | ||||
| -rw-r--r-- | target/linux/patches/4.8.11/sh2.patch | 11 | ||||
| -rw-r--r-- | target/sh/Makefile | 8 | ||||
| -rw-r--r-- | target/sh/kernel/numato-mimasv2 | 21 | ||||
| -rw-r--r-- | target/sh/systems/numato-mimasv2 | 6 | ||||
| -rw-r--r-- | toolchain/binutils/Makefile | 2 | ||||
| -rw-r--r-- | toolchain/binutils/patches/2.27/j2.patch | 936 | ||||
| -rw-r--r-- | toolchain/gcc/Makefile | 7 | ||||
| -rw-r--r-- | toolchain/gcc/patches/6.2.0/j2.patch | 342 |
23 files changed, 1391 insertions, 19 deletions
diff --git a/mk/image.mk b/mk/image.mk index 3485b43b6..023b303b3 100644 --- a/mk/image.mk +++ b/mk/image.mk @@ -170,6 +170,8 @@ ${STAGING_TARGET_DIR}/${INITRAMFS}_list: ${TARGET_DIR}/.adk echo "nod /dev/ttySC1 0660 0 0 c 204 9"; \ echo "nod /dev/ttyBF0 0660 0 0 c 204 64"; \ echo "nod /dev/ttyBF1 0660 0 0 c 204 65"; \ + echo "nod /dev/ttyUL0 0660 0 0 c 204 187"; \ + echo "nod /dev/ttyUL1 0660 0 0 c 204 188"; \ ) >>$@ diff --git a/mk/kernel-ver.mk b/mk/kernel-ver.mk index a13d97049..ade00b4f1 100644 --- a/mk/kernel-ver.mk +++ b/mk/kernel-ver.mk @@ -15,6 +15,12 @@ KERNEL_FILE_VER:= $(ADK_TARGET_KERNEL_GIT) KERNEL_RELEASE:= 1 KERNEL_VERSION:= $(ADK_TARGET_KERNEL_GIT_VER) endif +ifeq ($(ADK_TARGET_KERNEL_VERSION_4_9),y) +KERNEL_FILE_VER:= 4.9 +KERNEL_RELEASE:= 1 +KERNEL_VERSION:= $(KERNEL_FILE_VER)-$(KERNEL_RELEASE) +KERNEL_HASH:= 029098dcffab74875e086ae970e3828456838da6e0ba22ce3f64ef764f3d7f1a +endif ifeq ($(ADK_TARGET_KERNEL_VERSION_4_8),y) KERNEL_FILE_VER:= 4.8.11 KERNEL_RELEASE:= 1 diff --git a/package/musl/Makefile b/package/musl/Makefile index a7bd3a80d..55323c5a9 100644 --- a/package/musl/Makefile +++ b/package/musl/Makefile @@ -49,6 +49,13 @@ endif ifeq ($(ADK_TARGET_CPU_ARCH),ppc64le) MARCH:= powerpc64le endif +ifeq ($(ADK_TARGET_CPU_ARCH),sh2eb) +ifeq ($(ADK_TARGET_BINFMT_FDPIC),y) +MARCH:= sheb-nofpu-fdpic +else +MARCH:= sheb-nofpu +endif +endif ifeq ($(ADK_TARGET_CPU_ARCH),sh4) MARCH:= sh endif diff --git a/target/config/Config.in.binfmt b/target/config/Config.in.binfmt index 13e28f6b5..03f2c6003 100644 --- a/target/config/Config.in.binfmt +++ b/target/config/Config.in.binfmt @@ -12,12 +12,13 @@ config ADK_TARGET_BINFMT_ELF config ADK_TARGET_BINFMT_FLAT bool "FLAT" select ADK_TARGET_UCLINUX if ADK_TARGET_ARCH_BFIN + depends on ADK_TARGET_LIB_UCLIBC_NG depends on (ADK_TARGET_ARCH_ARM || ADK_TARGET_ARCH_M68K || ADK_TARGET_ARCH_SH || ADK_TARGET_ARCH_XTENSA) && ADK_TARGET_WITHOUT_MMU \ || ADK_TARGET_ARCH_H8300 || ADK_TARGET_ARCH_LM32 || ADK_TARGET_ARCH_BFIN config ADK_TARGET_BINFMT_FDPIC bool "FDPIC" - depends on ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_FRV + depends on ADK_TARGET_ARCH_BFIN || ADK_TARGET_ARCH_FRV || (ADK_TARGET_CPU_SH_J2 && ADK_TARGET_LIB_MUSL) config ADK_TARGET_BINFMT_DSBT bool "DSBT" diff --git a/target/config/Config.in.binutils b/target/config/Config.in.binutils index fa29adb99..e05a8c0bd 100644 --- a/target/config/Config.in.binutils +++ b/target/config/Config.in.binutils @@ -13,6 +13,7 @@ default ADK_TOOLCHAIN_BINUTILS_2_27 if ADK_TARGET_ARCH_FRV default ADK_TOOLCHAIN_BINUTILS_2_27 if ADK_TARGET_ARCH_H8300 default ADK_TOOLCHAIN_BINUTILS_2_27 if ADK_TARGET_ARCH_NIOS2 default ADK_TOOLCHAIN_BINUTILS_2_27 if ADK_TARGET_ARCH_XTENSA && ADK_TARGET_LITTLE_ENDIAN +default ADK_TOOLCHAIN_BINUTILS_2_27 if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default ADK_TOOLCHAIN_BINUTILS_2_26_1 config ADK_TOOLCHAIN_BINUTILS_GIT @@ -38,6 +39,7 @@ config ADK_TOOLCHAIN_BINUTILS_2_26_1 depends on !ADK_TARGET_ARCH_H8300 depends on !ADK_TARGET_ARCH_LM32 depends on !ADK_TARGET_ARCH_NDS32 + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 config ADK_TOOLCHAIN_BINUTILS_2_25_1 bool "2.25.1" @@ -49,6 +51,7 @@ config ADK_TOOLCHAIN_BINUTILS_2_25_1 depends on !ADK_TARGET_ARCH_MOXIE depends on !ADK_TARGET_ARCH_NDS32 depends on !ADK_TARGET_CPU_CRIS_CRISV10 + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 config ADK_TOOLCHAIN_BINUTILS_NDS32 bool "2.24-nds32" diff --git a/target/config/Config.in.compiler b/target/config/Config.in.compiler index 7c1dc7d3d..b804334a5 100644 --- a/target/config/Config.in.compiler +++ b/target/config/Config.in.compiler @@ -33,6 +33,7 @@ default ADK_TOOLCHAIN_GCC_6 if ADK_TARGET_ARCH_FRV default ADK_TOOLCHAIN_GCC_6 if ADK_TARGET_ARCH_M32R default ADK_TOOLCHAIN_GCC_6 if ADK_TARGET_CPU_MIPS_MIPS32R6 || ADK_TARGET_CPU_MIPS64_MIPS64R6 default ADK_TOOLCHAIN_GCC_6 if ADK_TARGET_LIB_MUSL && ADK_TARGET_ARCH_S390 +default ADK_TOOLCHAIN_GCC_6 if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default ADK_TOOLCHAIN_GCC_5 config ADK_TOOLCHAIN_GCC_GIT @@ -71,6 +72,7 @@ config ADK_TOOLCHAIN_GCC_5 depends on !(ADK_TARGET_LIB_GLIBC && ADK_TARGET_ARCH_SH) depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 config ADK_TOOLCHAIN_GCC_4_9 bool "4.9.4" @@ -87,6 +89,7 @@ config ADK_TOOLCHAIN_GCC_4_9 depends on !ADK_TARGET_ARCH_TILE depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 config ADK_TOOLCHAIN_GCC_OR1K bool "or1k" diff --git a/target/config/Config.in.cpu b/target/config/Config.in.cpu index f0d1b71c4..7cea653de 100644 --- a/target/config/Config.in.cpu +++ b/target/config/Config.in.cpu @@ -980,10 +980,19 @@ config ADK_TARGET_CPU_S390_Z900 depends on ADK_TARGET_ARCH_S390 # sh +config ADK_TARGET_CPU_SH_J2 + bool "j2" + select ADK_TARGET_SUPPORTS_THREADS + select ADK_TARGET_SUPPORTS_NPTL if ADK_TARGET_LIB_MUSL + select ADK_TARGET_SUPPORTS_LT if ADK_TARGET_LIB_UCLIBC_NG + select ADK_TARGET_WITHOUT_MMU + depends on ADK_TARGET_ARCH_SH + config ADK_TARGET_CPU_SH_SH2 bool "sh2" select ADK_TARGET_SUPPORTS_THREADS - select ADK_TARGET_SUPPORTS_LT + select ADK_TARGET_SUPPORTS_NPTL if ADK_TARGET_LIB_MUSL + select ADK_TARGET_SUPPORTS_LT if ADK_TARGET_LIB_UCLIBC_NG select ADK_TARGET_WITHOUT_MMU depends on ADK_TARGET_ARCH_SH @@ -1815,6 +1824,7 @@ config ADK_TARGET_CPU_FLAGS default "-mcpu=v32" if ADK_TARGET_CPU_CRIS_CRISV32 default "-mmetac=2.1" if ADK_TARGET_CPU_METAG default "-mcpu=v7.10.d" if ADK_TARGET_CPU_MICROBLAZE + default "-mj2" if ADK_TARGET_CPU_SH_J2 default "-m2" if ADK_TARGET_CPU_SH_SH2 default "-m2a" if ADK_TARGET_CPU_SH_SH2A default "-m3" if ADK_TARGET_CPU_SH_SH3 @@ -1921,6 +1931,7 @@ config ADK_TARGET_CPU_TYPE default "fsf" if ADK_TARGET_CPU_XTENSA_FSF default "crisv10" if ADK_TARGET_CPU_CRIS_CRISV10 default "crisv32" if ADK_TARGET_CPU_CRIS_CRISV32 + default "j2" if ADK_TARGET_CPU_SH_J2 default "sh2" if ADK_TARGET_CPU_SH_SH2 default "sh2a" if ADK_TARGET_CPU_SH_SH2A default "sh3" if ADK_TARGET_CPU_SH_SH3 @@ -1977,6 +1988,7 @@ config ADK_TARGET_CPU_ARCH default "s390x" if ADK_TARGET_ARCH_S390 default "sh2" if ADK_TARGET_CPU_SH_SH2 && ADK_TARGET_LITTLE_ENDIAN default "sh2eb" if ADK_TARGET_CPU_SH_SH2 && ADK_TARGET_BIG_ENDIAN + default "sh2eb" if ADK_TARGET_CPU_SH_J2 && ADK_TARGET_BIG_ENDIAN default "sh2a" if ADK_TARGET_CPU_SH_SH2A default "sh3" if ADK_TARGET_CPU_SH_SH3 && ADK_TARGET_LITTLE_ENDIAN default "sh3eb" if ADK_TARGET_CPU_SH_SH3 && ADK_TARGET_BIG_ENDIAN diff --git a/target/config/Config.in.kernelcfg b/target/config/Config.in.kernelcfg index eb971fdf8..f9f5ec491 100644 --- a/target/config/Config.in.kernelcfg +++ b/target/config/Config.in.kernelcfg @@ -21,7 +21,7 @@ config ADK_TARGET_KERNEL_USE_CUSTOMCONFIG endchoice config ADK_TARGET_KERNEL_DEFCONFIG - string + string "Defconfig name" depends on ADK_TARGET_KERNEL_USE_DEFCONFIG default "bcmrpi_defconfig" if ADK_TARGET_SYSTEM_RASPBERRY_PI default "bcm2709_defconfig" if ADK_TARGET_SYSTEM_RASPBERRY_PI2 @@ -34,6 +34,8 @@ config ADK_TARGET_KERNEL_DEFCONFIG default "10m50_defconfig" if ADK_TARGET_SYSTEM_QEMU_NIOS2 default "orca_defconfig" if ADK_TARGET_SYSTEM_ANDES_AG101P default "bb.org_defconfig" if ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK + default "j2_defconfig" if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 + default "" config ADK_TARGET_KERNEL_CUSTOMCONFIG_PATH string "Kernel configuration file location" diff --git a/target/config/Config.in.kernelcmd b/target/config/Config.in.kernelcmd index d630eb86c..5a2b30599 100644 --- a/target/config/Config.in.kernelcmd +++ b/target/config/Config.in.kernelcmd @@ -9,5 +9,6 @@ config ADK_TARGET_CMDLINE default "metag_da.console_poll=1" if ADK_TARGET_SYSTEM_QEMU_METAG default "earlycon=uart8250,mmio32,0x9d050020,115200n8 console=ttyS0,115200n8" if ADK_TARGET_CPU_XTENSA_DE212 default "earlyprintk=uart8250-32bit,0x99600000" if ADK_TARGET_SYSTEM_ANDES_AG101P + default "earlycon noiotrap" if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default "" diff --git a/target/config/Config.in.kernelversion b/target/config/Config.in.kernelversion index f6da4281b..5f50bbcbf 100644 --- a/target/config/Config.in.kernelversion +++ b/target/config/Config.in.kernelversion @@ -13,6 +13,7 @@ default ADK_TARGET_KERNEL_VERSION_GIT if ADK_TARGET_ARCH_LM32 default ADK_TARGET_KERNEL_VERSION_4_4 if ADK_TARGET_ARCH_CRIS default ADK_TARGET_KERNEL_VERSION_4_4 if ADK_TARGET_ARCH_METAG default ADK_TARGET_KERNEL_VERSION_4_4 if ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU +default ADK_TARGET_KERNEL_VERSION_4_9 if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default ADK_TARGET_KERNEL_VERSION_4_8 config ADK_TARGET_KERNEL_VERSION_GIT @@ -23,12 +24,20 @@ config ADK_TARGET_KERNEL_VERSION_GIT select ADK_TARGET_KERNEL_IMAGE if ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 select ADK_TARGET_KERNEL_IMAGE if ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK +config ADK_TARGET_KERNEL_VERSION_4_9 + bool "4.9" + depends on !ADK_TARGET_ARCH_CRIS + depends on !ADK_TARGET_ARCH_METAG + depends on !ADK_TARGET_ARCH_NDS32 + depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + config ADK_TARGET_KERNEL_VERSION_4_8 bool "4.8.11" depends on !ADK_TARGET_ARCH_CRIS depends on !ADK_TARGET_ARCH_METAG depends on !ADK_TARGET_ARCH_NDS32 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 config ADK_TARGET_KERNEL_VERSION_4_4 bool "4.4.30" @@ -38,6 +47,7 @@ config ADK_TARGET_KERNEL_VERSION_4_4 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 config ADK_TARGET_KERNEL_VERSION_4_1 bool "4.1.35" @@ -70,6 +80,7 @@ config ADK_TARGET_KERNEL_VERSION_3_18 depends on !ADK_TARGET_SYSTEM_BEAGLEBONE_BLACK depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -89,6 +100,7 @@ config ADK_TARGET_KERNEL_VERSION_3_12 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -109,6 +121,7 @@ config ADK_TARGET_KERNEL_VERSION_3_10 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -127,6 +140,7 @@ config ADK_TARGET_KERNEL_VERSION_3_4 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -146,6 +160,7 @@ config ADK_TARGET_KERNEL_VERSION_3_2 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 @@ -165,6 +180,7 @@ config ADK_TARGET_KERNEL_VERSION_2_6_32 depends on !ADK_TARGET_SYSTEM_SOLIDRUN_IMX6 depends on !ADK_TARGET_SYSTEM_QEMU_M68K_MCF5208 depends on !ADK_TARGET_SYSTEM_QEMU_ARM_VERSATILEPB_NOMMU + depends on !ADK_TARGET_SYSTEM_NUMATO_MIMASV2 depends on !ADK_TARGET_CPU_MIPS_MIPS32R6 depends on !ADK_TARGET_CPU_MIPS64_MIPS64R6 diff --git a/target/config/Config.in.libc b/target/config/Config.in.libc index 009b327a2..c384434fa 100644 --- a/target/config/Config.in.libc +++ b/target/config/Config.in.libc @@ -76,7 +76,8 @@ config ADK_TARGET_LIB_GLIBC ADK_TARGET_ARCH_PPC || \ ADK_TARGET_ARCH_PPC64 || \ ADK_TARGET_ARCH_S390 || \ - ADK_TARGET_ARCH_SH || \ + ADK_TARGET_CPU_SH_SH4 || \ + ADK_TARGET_CPU_SH_SH4A || \ ADK_TARGET_ARCH_SPARC || \ ADK_TARGET_ARCH_SPARC64 || \ ADK_TARGET_ARCH_TILE || \ @@ -273,6 +274,7 @@ config ADK_TARGET_SUFFIX default "muslabi32" if ADK_TARGET_LIB_MUSL && ADK_TARGET_ABI_O32 default "musl32" if ADK_TARGET_LIB_MUSL && ADK_TARGET_ABI_32 && ADK_LINUX_64 default "muslx32" if ADK_TARGET_LIB_MUSL && ADK_TARGET_ABI_X32 && ADK_LINUX_64 + default "muslfdpic" if ADK_TARGET_LIB_MUSL && ADK_TARGET_BINFMT_FDPIC default "musl" if ADK_TARGET_LIB_MUSL default "eabi" if ADK_TARGET_LIB_NEWLIB && ADK_TARGET_ARCH_ARM default "elf" if ADK_TARGET_LIB_NEWLIB diff --git a/target/config/Config.in.runtime b/target/config/Config.in.runtime index 6dc61e668..22bce28f2 100644 --- a/target/config/Config.in.runtime +++ b/target/config/Config.in.runtime @@ -361,7 +361,6 @@ config ADK_RUNTIME_CONSOLE_SERIAL_SPEED || ADK_TARGET_QEMU \ || ADK_TARGET_SIM default "9600" if ADK_TARGET_SYSTEM_FON_FON2100 - default "9600" if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default "9600" if ADK_TARGET_SYSTEM_SGI_O2 default "38400" if ADK_TARGET_SYSTEM_PCENGINES_WRAP default "38400" if ADK_TARGET_SYSTEM_ANDES_AG101P diff --git a/target/config/Config.in.toolchain b/target/config/Config.in.toolchain index 33c5eacb4..3cf310e68 100644 --- a/target/config/Config.in.toolchain +++ b/target/config/Config.in.toolchain @@ -7,11 +7,11 @@ bool "Library support" config ADK_TARGET_USE_SHARED_LIBS_ONLY bool "Create shared libraries only and link dynamically" + depends on !ADK_TARGET_BINFMT_FLAT && !ADK_TARGET_BINFMT_DSBT config ADK_TARGET_USE_STATIC_LIBS_ONLY bool "Create static libraries only and link statically" select BUSYBOX_STATIC - depends on !ADK_TARGET_BINFMT_FLAT && !ADK_TARGET_BINFMT_DSBT help Useful for debugging of dynamic linker problems. Be aware of the fact, that uClibc and glibc still requires libgcc_so.so.1 for pthread_cancel. Glibc also requires libnss_*.so libraries @@ -19,6 +19,7 @@ config ADK_TARGET_USE_STATIC_LIBS_ONLY config ADK_TARGET_USE_SHARED_AND_STATIC_LIBS bool "Create shared and static libraries and link dynamically" + depends on !ADK_TARGET_BINFMT_FLAT && !ADK_TARGET_BINFMT_DSBT endchoice diff --git a/target/config/Config.in.tools b/target/config/Config.in.tools index 7b8bb219c..4d4fb73e5 100644 --- a/target/config/Config.in.tools +++ b/target/config/Config.in.tools @@ -23,6 +23,10 @@ config ADK_HOST_BUILD_BISON bool default y +config ADK_HOST_BUILD_DTC + bool + default n + config ADK_HOST_BUILD_FAKEROOT bool default n diff --git a/target/linux/config/Config.in.serial b/target/linux/config/Config.in.serial index 9252b8fa7..6044481fc 100644 --- a/target/linux/config/Config.in.serial +++ b/target/linux/config/Config.in.serial @@ -258,11 +258,13 @@ config ADK_KERNEL_SERIAL_OMAP config ADK_KERNEL_SERIAL_UARTLITE bool "uartlite serial driver" select ADK_KERNEL_SERIAL_UARTLITE_CONSOLE - depends on ADK_TARGET_SYSTEM_QEMU_MICROBLAZE_S3ADSP1800 + depends on ADK_TARGET_SYSTEM_QEMU_MICROBLAZE_S3ADSP1800 \ + || ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default y if ADK_TARGET_SYSTEM_QEMU_MICROBLAZE_S3ADSP1800 + default y if ADK_TARGET_SYSTEM_NUMATO_MIMASV2 default n help - Serial driver for Microblaze S3ADSP1800 + Serial driver for UART lite hardware. config ADK_KERNEL_SERIAL_ATMEL bool "AT32 serial driver" diff --git a/target/linux/patches/4.8.11/sh2.patch b/target/linux/patches/4.8.11/sh2.patch new file mode 100644 index 000000000..9debe80ad --- /dev/null +++ b/target/linux/patches/4.8.11/sh2.patch @@ -0,0 +1,11 @@ +diff -Nur linux-4.8.11.orig/arch/sh/kernel/cpu/sh2/probe.c linux-4.8.11/arch/sh/kernel/cpu/sh2/probe.c +--- linux-4.8.11.orig/arch/sh/kernel/cpu/sh2/probe.c 2016-11-26 09:57:13.000000000 +0100 ++++ linux-4.8.11/arch/sh/kernel/cpu/sh2/probe.c 2016-12-10 10:38:27.997954035 +0100 +@@ -15,6 +15,7 @@ + #include <linux/io.h> + #include <asm/processor.h> + #include <asm/cache.h> ++#include <asm/smp.h> + + #if defined(CONFIG_CPU_J2) + extern u32 __iomem *j2_ccr_base; diff --git a/target/sh/Makefile b/target/sh/Makefile index 70df270be..58823b38d 100644 --- a/target/sh/Makefile +++ b/target/sh/Makefile @@ -67,6 +67,12 @@ endif kernel-install: kernel-strip @cp $(BUILD_DIR)/$(TARGET_KERNEL) $(FW_DIR)/${TARGET_KERNEL} +dtb-install: +ifeq ($(ADK_TARGET_SYSTEM_NUMATO_MIMASV2),y) + PATH='$(HOST_PATH)' dtc -O dtb -o $(FW_DIR)/dt.dtb \ + $(LINUX_DIR)/arch/sh/boot/dts/j2_mimas_v2.dts +endif + # filesystem specific targets ifeq ($(ADK_TARGET_FS),archive) imageinstall: $(FW_DIR)/$(ROOTFSTARBALL) targethelp @@ -78,5 +84,5 @@ ifeq ($(ADK_TARGET_FS),initramfsarchive) imageinstall: kernel-install $(FW_DIR)/$(ROOTFSUSERTARBALL) targethelp endif ifeq ($(ADK_TARGET_FS),initramfspiggyback) -imageinstall: createinitramfs targethelp +imageinstall: dtb-install createinitramfs targethelp endif diff --git a/target/sh/kernel/numato-mimasv2 b/target/sh/kernel/numato-mimasv2 index f66b31fa1..ca290f15d 100644 --- a/target/sh/kernel/numato-mimasv2 +++ b/target/sh/kernel/numato-mimasv2 @@ -1,10 +1,17 @@ CONFIG_SUPERH=y CONFIG_SUPERH32=y CONFIG_CPU_SH2=y -CONFIG_0PF_FPGA=y -CONFIG_CPU_SUBTYPE_0PF=y -CONFIG_CACHE_OFF=y -CONFIG_CMDLINE_EXTEND=y -CONFIG_SERIAL_UARTLITE=y -CONFIG_SERIAL_UARTLITE_0PF=y -CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_CPU_SUBTYPE_J2=y +CONFIG_SH_JCORE_SOC=y +CONFIG_SMP=y +CONFIG_MEMORY_START=0x10000000 +CONFIG_MEMORY_SIZE=0x04000000 +CONFIG_SH_DEVICE_TREE=y +CONFIG_I2C=y +CONFIG_SPI=y +CONFIG_SPI_JCORE=y +CONFIG_MMC=y +CONFIG_MMC_SPI=y +CONFIG_CLKSRC_JCORE_PIT=y +CONFIG_JCORE_AIC=y +CONFIG_SERIAL_EARLYCON=y diff --git a/target/sh/systems/numato-mimasv2 b/target/sh/systems/numato-mimasv2 index 088fc5a73..e14d4ce71 100644 --- a/target/sh/systems/numato-mimasv2 +++ b/target/sh/systems/numato-mimasv2 @@ -1,7 +1,9 @@ config ADK_TARGET_SYSTEM_NUMATO_MIMASV2 bool "Numato Mimas v2 FPGA" - select ADK_TARGET_CPU_SH_SH2 + select ADK_TARGET_CPU_SH_J2 select ADK_TARGET_WITH_SERIAL + select ADK_TARGET_WITH_BLOCK + select ADK_HOST_BUILD_DTC help - Support for Numato Mimas v2 FPGA with J2 Core Bitstream, sh2 architecture. + Support for Numato Mimas v2 FPGA with J2 Core Bitstream (sh2eb). diff --git a/toolchain/binutils/Makefile b/toolchain/binutils/Makefile index 290aed6d6..083d11287 100644 --- a/toolchain/binutils/Makefile +++ b/toolchain/binutils/Makefile @@ -70,7 +70,7 @@ $(WRKBUILD)/.compiled: $(WRKBUILD)/.configured $(WRKBUILD)/.installed: $(WRKBUILD)/.compiled PATH='$(HOST_PATH)' $(MAKE) MAKEINFO=true -C $(WRKBUILD) install -ifeq ($(ADK_TARGET_ARCH_H8300)$(ADK_TARGET_ARCH_NDS32),y) +ifeq ($(ADK_TARGET_ARCH_H8300)$(ADK_TARGET_ARCH_NDS32)$(ADK_TARGET_CPU_SH_J2),y) $(INSTALL_DIR) $(STAGING_TARGET_DIR)/usr/lib/ldscripts $(CP) $(WRKBUILD)/ld/ldscripts/* $(STAGING_TARGET_DIR)/usr/lib/ldscripts/ endif diff --git a/toolchain/binutils/patches/2.27/j2.patch b/toolchain/binutils/patches/2.27/j2.patch new file mode 100644 index 000000000..2861d9a48 --- /dev/null +++ b/toolchain/binutils/patches/2.27/j2.patch @@ -0,0 +1,936 @@ +diff -Nur binutils-2.27.orig/bfd/archures.c binutils-2.27/bfd/archures.c +--- binutils-2.27.orig/bfd/archures.c 2016-08-03 09:36:50.000000000 +0200 ++++ binutils-2.27/bfd/archures.c 2016-12-10 15:34:01.954875361 +0100 +@@ -310,10 +310,12 @@ + .#define bfd_mach_sh_dsp 0x2d + .#define bfd_mach_sh2a 0x2a + .#define bfd_mach_sh2a_nofpu 0x2b ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +diff -Nur binutils-2.27.orig/bfd/bfd-in2.h binutils-2.27/bfd/bfd-in2.h +--- binutils-2.27.orig/bfd/bfd-in2.h 2016-08-03 09:36:50.000000000 +0200 ++++ binutils-2.27/bfd/bfd-in2.h 2016-12-10 15:34:01.978874153 +0100 +@@ -2121,10 +2121,12 @@ + #define bfd_mach_sh_dsp 0x2d + #define bfd_mach_sh2a 0x2a + #define bfd_mach_sh2a_nofpu 0x2b ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +diff -Nur binutils-2.27.orig/bfd/cpu-sh.c binutils-2.27/bfd/cpu-sh.c +--- binutils-2.27.orig/bfd/cpu-sh.c 2016-08-03 09:36:50.000000000 +0200 ++++ binutils-2.27/bfd/cpu-sh.c 2016-12-10 15:34:01.978874153 +0100 +@@ -44,7 +44,9 @@ + #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 + #define SH2A_OR_SH4_NEXT arch_info_struct + 18 + #define SH2A_OR_SH3E_NEXT arch_info_struct + 19 +-#define SH64_NEXT NULL ++#define SH64_NEXT arch_info_struct + 20 ++#define SHJ2_NEXT arch_info_struct + 21 ++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL + + static const bfd_arch_info_type arch_info_struct[] = + { +@@ -348,6 +350,36 @@ + bfd_arch_default_fill, + SH64_NEXT + }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_shj2, ++ "sh", /* Architecture name. . */ ++ "j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SHJ2_NEXT ++ }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, ++ "sh", /* Architecture name. . */ ++ "sh2a-or-sh3e-or-j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT ++ }, + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -398,6 +430,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +diff -Nur binutils-2.27.orig/bfd/elf32-sh.c binutils-2.27/bfd/elf32-sh.c +--- binutils-2.27.orig/bfd/elf32-sh.c 2016-08-03 09:36:51.000000000 +0200 ++++ binutils-2.27/bfd/elf32-sh.c 2016-12-10 15:34:06.138680918 +0100 +@@ -5682,220 +5682,6 @@ + return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); + } + +-/* Update the got entry reference counts for the section being removed. */ +- +-static bfd_boolean +-sh_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info, +- asection *sec, const Elf_Internal_Rela *relocs) +-{ +- Elf_Internal_Shdr *symtab_hdr; +- struct elf_link_hash_entry **sym_hashes; +- bfd_signed_vma *local_got_refcounts; +- union gotref *local_funcdesc; +- const Elf_Internal_Rela *rel, *relend; +- +- if (bfd_link_relocatable (info)) +- return TRUE; +- +- elf_section_data (sec)->local_dynrel = NULL; +- +- symtab_hdr = &elf_symtab_hdr (abfd); +- sym_hashes = elf_sym_hashes (abfd); +- local_got_refcounts = elf_local_got_refcounts (abfd); +- local_funcdesc = sh_elf_local_funcdesc (abfd); +- +- relend = relocs + sec->reloc_count; +- for (rel = relocs; rel < relend; rel++) +- { +- unsigned long r_symndx; +- unsigned int r_type; +- struct elf_link_hash_entry *h = NULL; +-#ifdef INCLUDE_SHMEDIA +- int seen_stt_datalabel = 0; +-#endif +- +- r_symndx = ELF32_R_SYM (rel->r_info); +- if (r_symndx >= symtab_hdr->sh_info) +- { +- struct elf_sh_link_hash_entry *eh; +- struct elf_sh_dyn_relocs **pp; +- struct elf_sh_dyn_relocs *p; +- +- h = sym_hashes[r_symndx - symtab_hdr->sh_info]; +- while (h->root.type == bfd_link_hash_indirect +- || h->root.type == bfd_link_hash_warning) +- { +-#ifdef INCLUDE_SHMEDIA +- seen_stt_datalabel |= h->type == STT_DATALABEL; +-#endif +- h = (struct elf_link_hash_entry *) h->root.u.i.link; +- } +- eh = (struct elf_sh_link_hash_entry *) h; +- for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next) +- if (p->sec == sec) +- { +- /* Everything must go for SEC. */ +- *pp = p->next; +- break; +- } +- } +- +- r_type = ELF32_R_TYPE (rel->r_info); +- switch (sh_elf_optimized_tls_reloc (info, r_type, h != NULL)) +- { +- case R_SH_TLS_LD_32: +- if (sh_elf_hash_table (info)->tls_ldm_got.refcount > 0) +- sh_elf_hash_table (info)->tls_ldm_got.refcount -= 1; +- break; +- +- case R_SH_GOT32: +- case R_SH_GOT20: +- case R_SH_GOTOFF: +- case R_SH_GOTOFF20: +- case R_SH_GOTPC: +-#ifdef INCLUDE_SHMEDIA +- case R_SH_GOT_LOW16: +- case R_SH_GOT_MEDLOW16: +- case R_SH_GOT_MEDHI16: +- case R_SH_GOT_HI16: +- case R_SH_GOT10BY4: +- case R_SH_GOT10BY8: +- case R_SH_GOTOFF_LOW16: +- case R_SH_GOTOFF_MEDLOW16: +- case R_SH_GOTOFF_MEDHI16: +- case R_SH_GOTOFF_HI16: +- case R_SH_GOTPC_LOW16: +- case R_SH_GOTPC_MEDLOW16: +- case R_SH_GOTPC_MEDHI16: +- case R_SH_GOTPC_HI16: +-#endif +- case R_SH_TLS_GD_32: +- case R_SH_TLS_IE_32: +- case R_SH_GOTFUNCDESC: +- case R_SH_GOTFUNCDESC20: +- if (h != NULL) +- { +-#ifdef INCLUDE_SHMEDIA +- if (seen_stt_datalabel) +- { +- struct elf_sh_link_hash_entry *eh; +- eh = (struct elf_sh_link_hash_entry *) h; +- if (eh->datalabel_got.refcount > 0) +- eh->datalabel_got.refcount -= 1; +- } +- else +-#endif +- if (h->got.refcount > 0) +- h->got.refcount -= 1; +- } +- else if (local_got_refcounts != NULL) +- { +-#ifdef INCLUDE_SHMEDIA +- if (rel->r_addend & 1) +- { +- if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0) +- local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1; +- } +- else +-#endif +- if (local_got_refcounts[r_symndx] > 0) +- local_got_refcounts[r_symndx] -= 1; +- } +- break; +- +- case R_SH_FUNCDESC: +- if (h != NULL) +- sh_elf_hash_entry (h)->abs_funcdesc_refcount -= 1; +- else if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info)) +- sh_elf_hash_table (info)->srofixup->size -= 4; +- +- /* Fall through. */ +- +- case R_SH_GOTOFFFUNCDESC: +- case R_SH_GOTOFFFUNCDESC20: +- if (h != NULL) +- sh_elf_hash_entry (h)->funcdesc.refcount -= 1; +- else +- local_funcdesc[r_symndx].refcount -= 1; +- break; +- +- case R_SH_DIR32: +- if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info) +- && (sec->flags & SEC_ALLOC) != 0) +- sh_elf_hash_table (info)->srofixup->size -= 4; +- /* Fall thru */ +- +- case R_SH_REL32: +- if (bfd_link_pic (info)) +- break; +- /* Fall thru */ +- +- case R_SH_PLT32: +-#ifdef INCLUDE_SHMEDIA +- case R_SH_PLT_LOW16: +- case R_SH_PLT_MEDLOW16: +- case R_SH_PLT_MEDHI16: +- case R_SH_PLT_HI16: +-#endif +- if (h != NULL) +- { +- if (h->plt.refcount > 0) +- h->plt.refcount -= 1; +- } +- break; +- +- case R_SH_GOTPLT32: +-#ifdef INCLUDE_SHMEDIA +- case R_SH_GOTPLT_LOW16: +- case R_SH_GOTPLT_MEDLOW16: +- case R_SH_GOTPLT_MEDHI16: +- case R_SH_GOTPLT_HI16: +- case R_SH_GOTPLT10BY4: +- case R_SH_GOTPLT10BY8: +-#endif +- if (h != NULL) +- { +- struct elf_sh_link_hash_entry *eh; +- eh = (struct elf_sh_link_hash_entry *) h; +- if (eh->gotplt_refcount > 0) +- { +- eh->gotplt_refcount -= 1; +- if (h->plt.refcount > 0) +- h->plt.refcount -= 1; +- } +-#ifdef INCLUDE_SHMEDIA +- else if (seen_stt_datalabel) +- { +- if (eh->datalabel_got.refcount > 0) +- eh->datalabel_got.refcount -= 1; +- } +-#endif +- else if (h->got.refcount > 0) +- h->got.refcount -= 1; +- } +- else if (local_got_refcounts != NULL) +- { +-#ifdef INCLUDE_SHMEDIA +- if (rel->r_addend & 1) +- { +- if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0) +- local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1; +- } +- else +-#endif +- if (local_got_refcounts[r_symndx] > 0) +- local_got_refcounts[r_symndx] -= 1; +- } +- break; +- +- default: +- break; +- } +- } +- +- return TRUE; +-} +- + /* Copy the extra info we tack onto an elf_link_hash_entry. */ + + static void +@@ -7455,7 +7241,6 @@ + sh_elf_merge_private_data + + #define elf_backend_gc_mark_hook sh_elf_gc_mark_hook +-#define elf_backend_gc_sweep_hook sh_elf_gc_sweep_hook + #define elf_backend_check_relocs sh_elf_check_relocs + #define elf_backend_copy_indirect_symbol \ + sh_elf_copy_indirect_symbol +diff -Nur binutils-2.27.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c +--- binutils-2.27.orig/binutils/readelf.c 2016-08-03 09:36:51.000000000 +0200 ++++ binutils-2.27/binutils/readelf.c 2016-12-10 15:34:01.978874153 +0100 +@@ -3307,6 +3307,8 @@ + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +diff -Nur binutils-2.27.orig/gas/config/tc-sh.c binutils-2.27/gas/config/tc-sh.c +--- binutils-2.27.orig/gas/config/tc-sh.c 2016-08-03 09:36:51.000000000 +0200 ++++ binutils-2.27/gas/config/tc-sh.c 2016-12-10 15:34:01.982873978 +0100 +@@ -1648,6 +1648,8 @@ + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -2187,7 +2189,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2016-12-10 15:34:01.994873426 +0100 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2016-12-10 15:34:02.006872864 +0100 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2016-12-10 15:34:02.006872864 +0100 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2016-12-10 15:34:02.006872864 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2016-12-10 15:34:02.010872679 +0100 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s 2016-12-10 15:34:02.010872679 +0100 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s 2016-12-10 15:34:02.010872679 +0100 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s 2016-12-10 15:34:02.010872679 +0100 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s 2016-12-10 15:34:02.010872679 +0100 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s 2016-12-10 15:34:02.010872679 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2016-12-10 15:34:02.018872308 +0100 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2016-12-10 15:34:02.014872493 +0100 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s 2016-12-10 15:34:02.014872493 +0100 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2016-12-10 15:34:02.014872493 +0100 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2016-12-10 15:34:02.014872493 +0100 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s 2015-11-13 09:27:41.000000000 +0100 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s 2016-12-10 15:34:02.014872493 +0100 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -Nur binutils-2.27.orig/include/elf/sh.h binutils-2.27/include/elf/sh.h +--- binutils-2.27.orig/include/elf/sh.h 2016-08-03 09:36:53.000000000 +0200 ++++ binutils-2.27/include/elf/sh.h 2016-12-10 15:34:02.018872308 +0100 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -Nur binutils-2.27.orig/ld/emulparams/shelf32.sh binutils-2.27/ld/emulparams/shelf32.sh +--- binutils-2.27.orig/ld/emulparams/shelf32.sh 2013-11-04 16:33:39.000000000 +0100 ++++ binutils-2.27/ld/emulparams/shelf32.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -11,6 +11,9 @@ + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + EMBEDDED=yes ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + DATA_START_SYMBOLS='PROVIDE (___data = .);' + +diff -Nur binutils-2.27.orig/ld/emulparams/shelf_nto.sh binutils-2.27/ld/emulparams/shelf_nto.sh +--- binutils-2.27.orig/ld/emulparams/shelf_nto.sh 2013-11-04 16:33:39.000000000 +0100 ++++ binutils-2.27/ld/emulparams/shelf_nto.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -9,3 +9,6 @@ + GENERATE_SHLIB_SCRIPT=yes + TEXT_START_SYMBOLS='_btext = .;' + ENTRY=_start ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes +diff -Nur binutils-2.27.orig/ld/emulparams/shelf.sh binutils-2.27/ld/emulparams/shelf.sh +--- binutils-2.27.orig/ld/emulparams/shelf.sh 2016-08-03 09:36:54.000000000 +0200 ++++ binutils-2.27/ld/emulparams/shelf.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -11,6 +11,9 @@ + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + EMBEDDED=yes ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + # These are for compatibility with the COFF toolchain. + ENTRY=start +diff -Nur binutils-2.27.orig/ld/emulparams/shelf_vxworks.sh binutils-2.27/ld/emulparams/shelf_vxworks.sh +--- binutils-2.27.orig/ld/emulparams/shelf_vxworks.sh 2013-11-04 16:33:39.000000000 +0100 ++++ binutils-2.27/ld/emulparams/shelf_vxworks.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -14,6 +14,10 @@ + GENERATE_SHLIB_SCRIPT=yes + ENTRY=__start + SYMPREFIX=_ ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes ++ + GOT=".got ${RELOCATING-0} : { + PROVIDE(__GLOBAL_OFFSET_TABLE_ = .); + *(.got.plt) *(.got) }" +diff -Nur binutils-2.27.orig/ld/emulparams/shlelf32_linux.sh binutils-2.27/ld/emulparams/shlelf32_linux.sh +--- binutils-2.27.orig/ld/emulparams/shlelf32_linux.sh 2013-11-04 16:33:39.000000000 +0100 ++++ binutils-2.27/ld/emulparams/shlelf32_linux.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -13,7 +13,9 @@ + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes +- ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + DATA_START_SYMBOLS='PROVIDE (___data = .);' + +diff -Nur binutils-2.27.orig/ld/emulparams/shlelf_linux.sh binutils-2.27/ld/emulparams/shlelf_linux.sh +--- binutils-2.27.orig/ld/emulparams/shlelf_linux.sh 2013-11-04 16:33:39.000000000 +0100 ++++ binutils-2.27/ld/emulparams/shlelf_linux.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -12,6 +12,9 @@ + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + DATA_START_SYMBOLS='PROVIDE (__data_start = .);'; + +diff -Nur binutils-2.27.orig/ld/emulparams/shlelf_nto.sh binutils-2.27/ld/emulparams/shlelf_nto.sh +--- binutils-2.27.orig/ld/emulparams/shlelf_nto.sh 2013-11-04 16:33:39.000000000 +0100 ++++ binutils-2.27/ld/emulparams/shlelf_nto.sh 2016-12-10 15:34:06.138680918 +0100 +@@ -9,3 +9,6 @@ + GENERATE_SHLIB_SCRIPT=yes + TEXT_START_SYMBOLS='_btext = .;' + ENTRY=_start ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes +diff -Nur binutils-2.27.orig/opcodes/sh-dis.c binutils-2.27/opcodes/sh-dis.c +--- binutils-2.27.orig/opcodes/sh-dis.c 2016-08-03 09:36:55.000000000 +0200 ++++ binutils-2.27/opcodes/sh-dis.c 2016-12-10 15:34:02.038871379 +0100 +@@ -868,6 +868,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +diff -Nur binutils-2.27.orig/opcodes/sh-opc.h binutils-2.27/opcodes/sh-opc.h +--- binutils-2.27.orig/opcodes/sh-opc.h 2016-08-03 09:36:55.000000000 +0200 ++++ binutils-2.27/opcodes/sh-opc.h 2016-12-10 15:34:02.046871007 +0100 +@@ -191,7 +191,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -218,9 +219,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -258,6 +261,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -323,7 +328,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -349,6 +355,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -717,9 +729,9 @@ + + /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1197,7 +1209,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + diff --git a/toolchain/gcc/Makefile b/toolchain/gcc/Makefile index ba00225f5..6af157934 100644 --- a/toolchain/gcc/Makefile +++ b/toolchain/gcc/Makefile @@ -140,6 +140,10 @@ GCC_CONFOPTS+= --with-endian=little else GCC_CONFOPTS+= --with-endian=big endif +ifeq ($(ADK_TARGET_CPU_SH_J2),y) +GCC_CONFOPTS+= --enable-fdpic +GCC_FINAL_CONFOPTS+= --with-multilib-list=mj2 +endif ifeq ($(ADK_TARGET_CPU_SH_SH2),y) GCC_FINAL_CONFOPTS+= --with-multilib-list=m2 endif @@ -229,6 +233,9 @@ endif (cd $(TOOLCHAIN_DIR)/usr/$(GNU_TARGET_NAME); \ ln -s ../$(STAGING_HOST2TARGET)/usr/lib lib) ifeq ($(ADK_TARGET_ARCH_SH),y) +ifeq ($(ADK_TARGET_CPU_SH_J2),y) + (cd ${STAGING_TARGET_DIR}/ && ln -sf . mj2) +endif ifeq ($(ADK_TARGET_CPU_SH_SH3),y) (cd ${STAGING_TARGET_DIR}/ && ln -sf . m3) endif diff --git a/toolchain/gcc/patches/6.2.0/j2.patch b/toolchain/gcc/patches/6.2.0/j2.patch new file mode 100644 index 000000000..8efe2cdf3 --- /dev/null +++ b/toolchain/gcc/patches/6.2.0/j2.patch @@ -0,0 +1,342 @@ +diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.c gcc-6.2.0/gcc/config/sh/sh.c +--- gcc-6.2.0.orig/gcc/config/sh/sh.c 2016-04-22 13:09:22.000000000 +0200 ++++ gcc-6.2.0/gcc/config/sh/sh.c 2016-12-10 19:58:58.649784537 +0100 +@@ -692,6 +692,7 @@ + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -699,6 +700,7 @@ + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -780,6 +782,9 @@ + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -845,6 +850,8 @@ + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.h gcc-6.2.0/gcc/config/sh/sh.h +--- gcc-6.2.0.orig/gcc/config/sh/sh.h 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.2.0/gcc/config/sh/sh.h 2016-12-10 19:58:58.649784537 +0100 +@@ -106,6 +106,7 @@ + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_INV \ +@@ -157,6 +158,7 @@ + #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) + #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) + #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -164,6 +166,7 @@ + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -211,7 +214,7 @@ + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -289,8 +292,8 @@ + %{m5-compact*:--isa=SHcompact} \ + %{m5-32media*:--isa=SHmedia --abi=32} \ + %{m5-64media*:--isa=SHmedia --abi=64} \ +-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" +- ++%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \ ++%{mj2:-isa=j2}" + #define ASM_SPEC SH_ASM_SPEC + + #ifndef SUBTARGET_ASM_ENDIAN_SPEC +@@ -1853,7 +1856,7 @@ + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -2185,6 +2188,7 @@ + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh.opt gcc-6.2.0/gcc/config/sh/sh.opt +--- gcc-6.2.0.orig/gcc/config/sh/sh.opt 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.2.0/gcc/config/sh/sh.opt 2016-12-10 19:58:58.649784537 +0100 +@@ -71,6 +71,10 @@ + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff -Nur gcc-6.2.0.orig/gcc/config/sh/sh-protos.h gcc-6.2.0/gcc/config/sh/sh-protos.h +--- gcc-6.2.0.orig/gcc/config/sh/sh-protos.h 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.2.0/gcc/config/sh/sh-protos.h 2016-12-10 19:58:58.641785064 +0100 +@@ -45,6 +45,7 @@ + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -88,6 +89,9 @@ + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #ifdef RTX_CODE + extern rtx sh_fsca_sf2int (void); + extern rtx sh_fsca_int2sf (void); +diff -Nur gcc-6.2.0.orig/gcc/config/sh/sync.md gcc-6.2.0/gcc/config/sh/sync.md +--- gcc-6.2.0.orig/gcc/config/sh/sync.md 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.2.0/gcc/config/sh/sync.md 2016-12-10 19:58:58.649784537 +0100 +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff -Nur gcc-6.2.0.orig/gcc/config/sh/t-sh gcc-6.2.0/gcc/config/sh/t-sh +--- gcc-6.2.0.orig/gcc/config/sh/t-sh 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.2.0/gcc/config/sh/t-sh 2016-12-10 19:58:58.649784537 +0100 +@@ -52,7 +52,7 @@ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ + m4,m4-100,m4-200,m4-300,m4a \ + m5-32media,m5-compact,m5-32media \ +- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \ ++ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -65,9 +65,9 @@ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -96,6 +96,7 @@ + m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \ + m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \ + m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true +diff -Nur gcc-6.2.0.orig/gcc/config.gcc gcc-6.2.0/gcc/config.gcc +--- gcc-6.2.0.orig/gcc/config.gcc 2016-06-08 15:34:25.000000000 +0200 ++++ gcc-6.2.0/gcc/config.gcc 2016-12-10 19:58:58.641785064 +0100 +@@ -471,7 +471,7 @@ + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2613,19 +2613,19 @@ + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \ + sh64-*-netbsd* | sh64l*-*-netbsd*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh64l* | sh*-*-linux* | \ + sh5l* | sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2715,6 +2715,7 @@ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2739,7 +2740,7 @@ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2750,9 +2751,9 @@ + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2770,7 +2771,8 @@ + m2a | m2a-single | m2a-single-only | m2a-nofpu | \ + m5-64media | m5-64media-nofpu | \ + m5-32media | m5-32media-nofpu | \ +- m5-compact | m5-compact-nofpu) ++ m5-compact | m5-compact-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2787,7 +2789,7 @@ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4268,6 +4270,8 @@ + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4477,7 +4481,7 @@ + tmake_file="rs6000/t-rs6000 ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; 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