gcc: update 10.x/13.x

6 files changed, 0 insertions, 682 deletions

diff --git a/toolchain/gcc/patches/10.3.0/add-crtreloc.frv b/toolchain/gcc/patches/10.3.0/add-crtreloc.frv
deleted file mode 100644
index 30de24cdc..000000000
--- a/toolchain/gcc/patches/10.3.0/add-crtreloc.frv
+++ /dev/null
@@ -1,12 +0,0 @@
-diff -Nur gcc-8.3.0.orig/gcc/config/frv/linux.h gcc-8.3.0/gcc/config/frv/linux.h
---- gcc-8.3.0.orig/gcc/config/frv/linux.h	2018-01-03 11:03:58.000000000 +0100
-+++ gcc-8.3.0/gcc/config/frv/linux.h	2019-10-08 10:52:00.176295821 +0200
-@@ -27,7 +27,7 @@
- 
- #undef STARTFILE_SPEC
- #define STARTFILE_SPEC \
--  "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
-+  "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} crtreloc.o%s \
-    crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}"
- 
- #undef ENDFILE_SPEC
diff --git a/toolchain/gcc/patches/10.3.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/10.3.0/c6x-disable-multilib.patch
deleted file mode 100644
index cbee6f785..000000000
--- a/toolchain/gcc/patches/10.3.0/c6x-disable-multilib.patch
+++ /dev/null
@@ -1,10 +0,0 @@
-diff -Nur gcc-8.3.0.orig/gcc/config/c6x/t-c6x-uclinux gcc-8.3.0/gcc/config/c6x/t-c6x-uclinux
---- gcc-8.3.0.orig/gcc/config/c6x/t-c6x-uclinux	2011-11-02 16:23:48.000000000 +0100
-+++ gcc-8.3.0/gcc/config/c6x/t-c6x-uclinux	2019-10-08 07:49:50.255159650 +0200
-@@ -1,3 +1,3 @@
--MULTILIB_OSDIRNAMES    = march.c674x=!c674x
--MULTILIB_OSDIRNAMES   += mbig-endian=!be
--MULTILIB_OSDIRNAMES   += mbig-endian/march.c674x=!be/c674x
-+MULTILIB_OSDIRNAMES    =
-+#MULTILIB_OSDIRNAMES   += mbig-endian=!be
-+#MULTILIB_OSDIRNAMES   += mbig-endian/march.c674x=!be/c674x
diff --git a/toolchain/gcc/patches/10.3.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/10.3.0/ia64-fix-libgcc.patch
deleted file mode 100644
index f1f3c8d2d..000000000
--- a/toolchain/gcc/patches/10.3.0/ia64-fix-libgcc.patch
+++ /dev/null
@@ -1,17 +0,0 @@
-diff -Nur gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c gcc-6.3.0/libgcc/config/ia64/fde-glibc.c
---- gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c	2016-01-04 15:30:50.000000000 +0100
-+++ gcc-6.3.0/libgcc/config/ia64/fde-glibc.c	2017-03-05 13:07:33.316600613 +0100
-@@ -25,6 +25,8 @@
- /* Locate the FDE entry for a given address, using glibc ld.so routines
-    to avoid register/deregister calls at DSO load/unload.  */
- 
-+#ifndef inhibit_libc
-+
- #ifndef _GNU_SOURCE
- #define _GNU_SOURCE 1
- #endif
-@@ -159,3 +161,4 @@
- 
-   return data.ret;
- }
-+#endif
diff --git a/toolchain/gcc/patches/10.3.0/j2.patch b/toolchain/gcc/patches/10.3.0/j2.patch
deleted file mode 100644
index 416475546..000000000
--- a/toolchain/gcc/patches/10.3.0/j2.patch
+++ /dev/null
@@ -1,346 +0,0 @@
-diff --git a/gcc/config.gcc b/gcc/config.gcc
-index 6fcdd771d4c..839a60d866e 100644
---- a/gcc/config.gcc
-+++ b/gcc/config.gcc
-@@ -547,7 +547,7 @@ s390*-*-*)
- 	extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
- 	;;
- # Note the 'l'; we need to be able to match e.g. "shle" or "shl".
--sh[123456789lbe]*-*-* | sh-*-*)
-+sh[123456789lbej]*-*-* | sh-*-*)
- 	cpu_type=sh
- 	extra_options="${extra_options} fused-madd.opt"
- 	extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
-@@ -3149,18 +3149,18 @@ s390x-ibm-tpf*)
- 	extra_options="${extra_options} s390/tpf.opt"
- 	tmake_file="${tmake_file} s390/t-s390"
- 	;;
--sh-*-elf* | sh[12346l]*-*-elf* | \
--  sh-*-linux* | sh[2346lbe]*-*-linux* | \
-+sh-*-elf* | sh[12346lj]*-*-elf* | \
-+  sh-*-linux* | sh[2346lbej]*-*-linux* | \
-   sh-*-netbsdelf* | shl*-*-netbsdelf*)
- 	tmake_file="${tmake_file} sh/t-sh sh/t-elf"
- 	if test x${with_endian} = x; then
- 		case ${target} in
--		sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
-+		sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
- 		shbe-*-* | sheb-*-*)		   with_endian=big,little ;;
- 		sh[1234]l* | sh[34]*-*-linux*)	   with_endian=little ;;
- 		shl* | sh*-*-linux* | \
- 		  sh-superh-elf)		   with_endian=little,big ;;
--		sh[1234]*-*-*)			   with_endian=big ;;
-+		sh[j1234]*-*-*)			   with_endian=big ;;
- 		*)				   with_endian=big,little ;;
- 		esac
- 	fi
-@@ -3227,6 +3227,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
- 	sh2a_nofpu*)		sh_cpu_target=sh2a-nofpu ;;
- 	sh2a*)			sh_cpu_target=sh2a ;;
- 	sh2e*)			sh_cpu_target=sh2e ;;
-+	shj2*)			sh_cpu_target=shj2;;
- 	sh2*)			sh_cpu_target=sh2 ;;
- 	*)			sh_cpu_target=sh1 ;;
- 	esac
-@@ -3248,7 +3249,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
- 	  sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
- 	  sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
- 	  sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
--	  sh3e | sh3 | sh2e | sh2 | sh1) ;;
-+	  sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
- 	"")	sh_cpu_default=${sh_cpu_target} ;;
- 	*)	echo "with_cpu=$with_cpu not supported"; exit 1 ;;
- 	esac
-@@ -3257,9 +3258,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
- 		case ${target} in
- 		sh[1234]*)	sh_multilibs=${sh_cpu_target} ;;
- 		sh-superh-*)	sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
--		sh*-*-linux*)	sh_multilibs=m1,m2,m2a,m3e,m4 ;;
-+		sh*-*-linux*)	sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
- 		sh*-*-netbsd*)	sh_multilibs=m3,m3e,m4 ;;
--		*) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
-+		*) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
- 		esac
- 		if test x$with_fp = xno; then
- 			sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
-@@ -3274,7 +3275,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
- 		m1 | m2 | m2e | m3 | m3e | \
- 		m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
- 		m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
--		m2a | m2a-single | m2a-single-only | m2a-nofpu)
-+		m2a | m2a-single | m2a-single-only | m2a-nofpu | \
-+		mj2)
- 			# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
- 			# It is passed to MULTIILIB_OPTIONS verbatim.
- 			TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
-@@ -3291,7 +3293,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
- 	done
- 	TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
- 	if test x${enable_incomplete_targets} = xyes ; then
--		tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
-+		tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
- 	fi
- 	tm_file="$tm_file ./sysroot-suffix.h"
- 	tmake_file="$tmake_file t-sysroot-suffix"
-@@ -5105,6 +5107,8 @@ case "${target}" in
- 			;;
- 		m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
- 		        ;;
-+		mj2)
-+			;;
- 		*)
- 			echo "Unknown CPU used in --with-cpu=$with_cpu, known values:"  1>&2
- 			echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
-@@ -5315,7 +5319,7 @@ case ${target} in
- 		tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
- 		;;
- 
--	sh[123456ble]*-*-* | sh-*-*)
-+	sh[123456blej]*-*-* | sh-*-*)
- 		c_target_objs="${c_target_objs} sh-c.o"
- 		cxx_target_objs="${cxx_target_objs} sh-c.o"
- 		;;
-diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
-index 84c0ea025b4..f15552af011 100644
---- a/gcc/config/sh/sh.c
-+++ b/gcc/config/sh/sh.c
-@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
-   model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
-   model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
-   model_names[sh_atomic_model::soft_imask] = "soft-imask";
-+  model_names[sh_atomic_model::hard_cas] = "hard-cas";
- 
-   const char* model_cdef_names[sh_atomic_model::num_models];
-   model_cdef_names[sh_atomic_model::none] = "NONE";
-@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
-   model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
-   model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
-   model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
-+  model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
- 
-   sh_atomic_model ret;
-   ret.type = sh_atomic_model::none;
-@@ -771,6 +773,9 @@ got_mode_name:;
-   if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
-     err_ret ("cannot use atomic model %s in user mode", ret.name);
- 
-+  if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
-+    err_ret ("atomic model %s is only available J2 targets", ret.name);
-+
-   return ret;
- 
- #undef err_ret
-@@ -827,6 +832,8 @@ sh_option_override (void)
-     sh_cpu = PROCESSOR_SH2E;
-   if (TARGET_SH2A)
-     sh_cpu = PROCESSOR_SH2A;
-+  if (TARGET_SHJ2)
-+    sh_cpu = PROCESSOR_SHJ2;
-   if (TARGET_SH3)
-     sh_cpu = PROCESSOR_SH3;
-   if (TARGET_SH3E)
-diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
-index 8ab5455505c..6ffed6da403 100644
---- a/gcc/config/sh/sh.h
-+++ b/gcc/config/sh/sh.h
-@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
- #define SUPPORT_SH4_SINGLE 1
- #define SUPPORT_SH2A 1
- #define SUPPORT_SH2A_SINGLE 1
-+#define SUPPORT_SHJ2 1
- #endif
- 
- #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
-@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
- #define SELECT_SH4A_SINGLE_ONLY  (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
- #define SELECT_SH4A		 (MASK_SH4A | SELECT_SH4)
- #define SELECT_SH4A_SINGLE	 (MASK_SH4A | SELECT_SH4_SINGLE)
-+#define SELECT_SHJ2		 (MASK_SHJ2 | SELECT_SH2)
- 
- #if SUPPORT_SH1
- #define SUPPORT_SH2 1
-@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
- #if SUPPORT_SH2
- #define SUPPORT_SH3 1
- #define SUPPORT_SH2A_NOFPU 1
-+#define SUPPORT_SHJ2 1
- #endif
- #if SUPPORT_SH3
- #define SUPPORT_SH4_NOFPU 1
-@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
- #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
- 		   | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
- 		   | MASK_HARD_SH4 | MASK_FPU_SINGLE \
--		   | MASK_FPU_SINGLE_ONLY)
-+		   | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
- 
- /* This defaults us to big-endian.  */
- #ifndef TARGET_ENDIAN_DEFAULT
-@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
- %{m2a-single:--isa=sh2a} \
- %{m2a-single-only:--isa=sh2a} \
- %{m2a-nofpu:--isa=sh2a-nofpu} \
--%{m4al:-dsp}"
-+%{m4al:-dsp} \
-+%{mj2:-isa=j2}"
- 
- #define ASM_SPEC SH_ASM_SPEC
- 
-@@ -347,6 +351,7 @@ struct sh_atomic_model
-     hard_llcs,
-     soft_tcb,
-     soft_imask,
-+    hard_cas,
- 
-     num_models
-   };
-@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
- #define TARGET_ATOMIC_SOFT_IMASK \
-   (selected_atomic_model ().type == sh_atomic_model::soft_imask)
- 
-+#define TARGET_ATOMIC_HARD_CAS \
-+  (selected_atomic_model ().type == sh_atomic_model::hard_cas)
-+
- #endif // __cplusplus
- 
- #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
-@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
- 
- /* Nonzero if the target supports dynamic shift instructions
-    like shad and shld.  */
--#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
-+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
- 
- /* The cost of using the dynamic shift insns (shad, shld) are the same
-    if they are available.  If they are not available a library function will
-@@ -1747,6 +1755,7 @@ enum processor_type {
-   PROCESSOR_SH2,
-   PROCESSOR_SH2E,
-   PROCESSOR_SH2A,
-+  PROCESSOR_SHJ2,
-   PROCESSOR_SH3,
-   PROCESSOR_SH3E,
-   PROCESSOR_SH4,
-diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
-index 908603b92e1..e6108dabbc6 100644
---- a/gcc/config/sh/sh.opt
-+++ b/gcc/config/sh/sh.opt
-@@ -65,6 +65,10 @@ m2e
- Target RejectNegative Condition(SUPPORT_SH2E)
- Generate SH2e code.
- 
-+mj2
-+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
-+Generate J2 code.
-+
- m3
- Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
- Generate SH3 code.
-diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
-index 25f3b695d2f..55119386a18 100644
---- a/gcc/config/sh/sync.md
-+++ b/gcc/config/sh/sync.md
-@@ -240,6 +240,9 @@
-       || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
-     atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
- 							  exp_val, new_val);
-+  else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
-+    atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
-+							 exp_val, new_val);
-   else if (TARGET_ATOMIC_SOFT_GUSA)
-     atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
- 		      exp_val, new_val);
-@@ -306,6 +309,57 @@
- }
-   [(set_attr "length" "14")])
- 
-+(define_expand "atomic_compare_and_swapsi_cas"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(unspec_volatile:SI
-+	  [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
-+	   (match_operand:SI 2 "register_operand" "r")
-+	   (match_operand:SI 3 "register_operand" "r")]
-+	  UNSPECV_CMPXCHG_1))]
-+  "TARGET_ATOMIC_HARD_CAS"
-+{
-+  rtx mem = gen_rtx_REG (SImode, 0);
-+  emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
-+  emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
-+  DONE;
-+})
-+
-+(define_insn "shj2_cas"
-+  [(set (match_operand:SI 0 "register_operand" "=&r")
-+  (unspec_volatile:SI
-+   [(match_operand:SI 1 "register_operand" "=r")
-+   (match_operand:SI 2 "register_operand" "r")
-+   (match_operand:SI 3 "register_operand" "0")]
-+   UNSPECV_CMPXCHG_1))
-+   (set (reg:SI T_REG)
-+	(unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
-+  "TARGET_ATOMIC_HARD_CAS"
-+  "cas.l	%2,%0,@%1"
-+  [(set_attr "length" "2")]
-+)
-+
-+(define_expand "atomic_compare_and_swapqi_cas"
-+  [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
-+	(unspec_volatile:SI
-+	  [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
-+	   (match_operand:SI 2 "arith_operand" "rI08")
-+	   (match_operand:SI 3 "arith_operand" "rI08")]
-+	  UNSPECV_CMPXCHG_1))]
-+  "TARGET_ATOMIC_HARD_CAS"
-+{FAIL;}
-+)
-+
-+(define_expand "atomic_compare_and_swaphi_cas"
-+  [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
-+	(unspec_volatile:SI
-+	  [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
-+	   (match_operand:SI 2 "arith_operand" "rI08")
-+	   (match_operand:SI 3 "arith_operand" "rI08")]
-+	  UNSPECV_CMPXCHG_1))]
-+  "TARGET_ATOMIC_HARD_CAS"
-+{FAIL;}
-+)
-+
- ;; The QIHImode llcs patterns modify the address register of the memory
- ;; operand.  In order to express that, we have to open code the memory
- ;; operand.  Initially the insn is expanded like every other atomic insn
-diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
-index a402359be72..dbd0bf992bf 100644
---- a/gcc/config/sh/t-sh
-+++ b/gcc/config/sh/t-sh
-@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
-              m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
-              m2a-single,m2a-single-only \
-              m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
--             m4,m4-100,m4-200,m4-300,m4a; do \
-+             m4,m4-100,m4-200,m4-300,m4a \
-+             mj2; do \
-     subst= ; \
-     for lib in `echo $$abi|tr , ' '` ; do \
-       if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
-@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
- 
- # SH1 and SH2A support big endian only.
- ifeq ($(DEFAULT_ENDIAN),ml)
--MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
-+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
- else
--MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
-+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
- endif
- 
- MULTILIB_OSDIRNAMES = \
-@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
- 	m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
- 	m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
- 	m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
--	m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
-+	m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
-+	mj2=!j2
- 
- $(out_object_file): gt-sh.h
- gt-sh.h : s-gtype ; @true
diff --git a/toolchain/gcc/patches/10.3.0/nios2-softfp.patch b/toolchain/gcc/patches/10.3.0/nios2-softfp.patch
deleted file mode 100644
index c677c6c2f..000000000
--- a/toolchain/gcc/patches/10.3.0/nios2-softfp.patch
+++ /dev/null
@@ -1,14 +0,0 @@
-diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host
---- gcc-6.2.0.orig/libgcc/config.host	2016-05-17 08:15:52.000000000 +0200
-+++ gcc-6.2.0/libgcc/config.host	2016-10-15 14:42:53.971919904 +0200
-@@ -962,6 +962,10 @@
- 		;;
- 	esac
- 	;;
-+nios2-*-linux-uclibc*)
-+	tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp"
-+	md_unwind_header=nios2/linux-unwind.h
-+	;;
- nios2-*-linux*)
- 	tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc"
- 	md_unwind_header=nios2/linux-unwind.h
diff --git a/toolchain/gcc/patches/10.3.0/revert-sparc.patch b/toolchain/gcc/patches/10.3.0/revert-sparc.patch
deleted file mode 100644
index 2ce948c82..000000000
--- a/toolchain/gcc/patches/10.3.0/revert-sparc.patch
+++ /dev/null
@@ -1,283 +0,0 @@
-diff -Nur gcc-10.3.0.orig/gcc/config/sparc/sparc.c gcc-10.3.0/gcc/config/sparc/sparc.c
---- gcc-10.3.0.orig/gcc/config/sparc/sparc.c	2021-04-08 13:56:28.201742273 +0200
-+++ gcc-10.3.0/gcc/config/sparc/sparc.c	2022-01-24 10:19:53.724121161 +0100
-@@ -4157,6 +4157,13 @@
- static bool
- sparc_cannot_force_const_mem (machine_mode mode, rtx x)
- {
-+  /* After IRA has run in PIC mode, it is too late to put anything into the
-+     constant pool if the PIC register hasn't already been initialized.  */
-+  if ((lra_in_progress || reload_in_progress)
-+      && flag_pic
-+      && !crtl->uses_pic_offset_table)
-+    return true;
-+
-   switch (GET_CODE (x))
-     {
-     case CONST_INT:
-@@ -4192,11 +4199,9 @@
- }
- 
- /* Global Offset Table support.  */
--static GTY(()) rtx got_symbol_rtx = NULL_RTX;
--static GTY(()) rtx got_register_rtx = NULL_RTX;
- static GTY(()) rtx got_helper_rtx = NULL_RTX;
--
--static GTY(()) bool got_helper_needed = false;
-+static GTY(()) rtx got_register_rtx = NULL_RTX;
-+static GTY(()) rtx got_symbol_rtx = NULL_RTX;
- 
- /* Return the SYMBOL_REF for the Global Offset Table.  */
- 
-@@ -4209,6 +4214,27 @@
-   return got_symbol_rtx;
- }
- 
-+#ifdef HAVE_GAS_HIDDEN
-+# define USE_HIDDEN_LINKONCE 1
-+#else
-+# define USE_HIDDEN_LINKONCE 0
-+#endif
-+
-+static void
-+get_pc_thunk_name (char name[32], unsigned int regno)
-+{
-+  const char *reg_name = reg_names[regno];
-+
-+  /* Skip the leading '%' as that cannot be used in a
-+     symbol name.  */
-+  reg_name += 1;
-+
-+  if (USE_HIDDEN_LINKONCE)
-+    sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
-+  else
-+    ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
-+}
-+
- /* Wrapper around the load_pcrel_sym{si,di} patterns.  */
- 
- static rtx
-@@ -4228,78 +4254,30 @@
-   return insn;
- }
- 
--/* Output the load_pcrel_sym{si,di} patterns.  */
--
--const char *
--output_load_pcrel_sym (rtx *operands)
--{
--  if (flag_delayed_branch)
--    {
--      output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
--      output_asm_insn ("call\t%a2", operands);
--      output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
--    }
--  else
--    {
--      output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
--      output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
--      output_asm_insn ("call\t%a2", operands);
--      output_asm_insn (" nop", NULL);
--    }
--
--  if (operands[2] == got_helper_rtx)
--    got_helper_needed = true;
--
--  return "";
--}
--
--#ifdef HAVE_GAS_HIDDEN
--# define USE_HIDDEN_LINKONCE 1
--#else
--# define USE_HIDDEN_LINKONCE 0
--#endif
--
- /* Emit code to load the GOT register.  */
- 
- void
- load_got_register (void)
- {
--  rtx insn;
-+  if (!got_register_rtx)
-+    got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
- 
-   if (TARGET_VXWORKS_RTP)
--    {
--      if (!got_register_rtx)
--	got_register_rtx = pic_offset_table_rtx;
--
--      insn = gen_vxworks_load_got ();
--    }
-+    emit_insn (gen_vxworks_load_got ());
-   else
-     {
--      if (!got_register_rtx)
--	got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
--
-       /* The GOT symbol is subject to a PC-relative relocation so we need a
- 	 helper function to add the PC value and thus get the final value.  */
-       if (!got_helper_rtx)
- 	{
- 	  char name[32];
--
--	  /* Skip the leading '%' as that cannot be used in a symbol name.  */
--	  if (USE_HIDDEN_LINKONCE)
--	    sprintf (name, "__sparc_get_pc_thunk.%s",
--		     reg_names[REGNO (got_register_rtx)] + 1);
--	  else
--	    ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
--					 REGNO (got_register_rtx));
--
-+	  get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
- 	  got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
- 	}
- 
--      insn
--	= gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
-+      emit_insn (gen_load_pcrel_sym (got_register_rtx, sparc_got (),
-+				     got_helper_rtx));
-     }
--
--  emit_insn (insn);
- }
- 
- /* Ensure that we are not using patterns that are not OK with PIC.  */
-@@ -5464,7 +5442,7 @@
-     return true;
- 
-   /* GOT register (%l7) if needed.  */
--  if (got_register_rtx && regno == REGNO (got_register_rtx))
-+  if (regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx)
-     return true;
- 
-   /* If the function accesses prior frames, the frame pointer and the return
-@@ -12507,9 +12485,10 @@
- sparc_file_end (void)
- {
-   /* If we need to emit the special GOT helper function, do so now.  */
--  if (got_helper_needed)
-+  if (got_helper_rtx)
-     {
-       const char *name = XSTR (got_helper_rtx, 0);
-+      const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
- #ifdef DWARF2_UNWIND_INFO
-       bool do_cfi;
- #endif
-@@ -12546,22 +12525,17 @@
- #ifdef DWARF2_UNWIND_INFO
-       do_cfi = dwarf2out_do_cfi_asm ();
-       if (do_cfi)
--	output_asm_insn (".cfi_startproc", NULL);
-+	fprintf (asm_out_file, "\t.cfi_startproc\n");
- #endif
-       if (flag_delayed_branch)
--	{
--	  output_asm_insn ("jmp\t%%o7+8", NULL);
--	  output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
--	}
-+	fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
-+		 reg_name, reg_name);
-       else
--	{
--	  output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
--	  output_asm_insn ("jmp\t%%o7+8", NULL);
--	  output_asm_insn (" nop", NULL);
--	}
-+	fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
-+		 reg_name, reg_name);
- #ifdef DWARF2_UNWIND_INFO
-       if (do_cfi)
--	output_asm_insn (".cfi_endproc", NULL);
-+	fprintf (asm_out_file, "\t.cfi_endproc\n");
- #endif
-     }
- 
-@@ -13056,10 +13030,7 @@
-   edge entry_edge;
-   rtx_insn *seq;
- 
--  /* In PIC mode, we need to always initialize the PIC register if optimization
--     is enabled, because we are called from IRA and LRA may later force things
--     to the constant pool for optimization purposes.  */
--  if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
-+  if (!crtl->uses_pic_offset_table)
-     return;
- 
-   start_sequence ();
-diff -Nur gcc-10.3.0.orig/gcc/config/sparc/sparc.md gcc-10.3.0/gcc/config/sparc/sparc.md
---- gcc-10.3.0.orig/gcc/config/sparc/sparc.md	2021-04-08 13:56:28.205742322 +0200
-+++ gcc-10.3.0/gcc/config/sparc/sparc.md	2022-01-24 10:19:54.504102046 +0100
-@@ -1601,7 +1601,10 @@
-    (clobber (reg:P O7_REG))]
-   "REGNO (operands[0]) == INTVAL (operands[3])"
- {
--  return output_load_pcrel_sym (operands);
-+  if (flag_delayed_branch)
-+    return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
-+  else
-+    return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
- }
-   [(set (attr "type") (const_string "multi"))
-    (set (attr "length")
-diff -Nur gcc-10.3.0.orig/gcc/config/sparc/sparc-protos.h gcc-10.3.0/gcc/config/sparc/sparc-protos.h
---- gcc-10.3.0.orig/gcc/config/sparc/sparc-protos.h	2021-04-08 13:56:28.201742273 +0200
-+++ gcc-10.3.0/gcc/config/sparc/sparc-protos.h	2022-01-24 10:19:54.548100968 +0100
-@@ -69,7 +69,6 @@
- extern void sparc_split_mem_reg (rtx, rtx, machine_mode);
- extern int sparc_split_reg_reg_legitimate (rtx, rtx);
- extern void sparc_split_reg_reg (rtx, rtx, machine_mode);
--extern const char *output_load_pcrel_sym (rtx *);
- extern const char *output_ubranch (rtx, rtx_insn *);
- extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
- extern const char *output_return (rtx_insn *);
-diff -Nur gcc-10.3.0.orig/gcc/testsuite/gcc.c-torture/compile/20191108-1.c gcc-10.3.0/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
---- gcc-10.3.0.orig/gcc/testsuite/gcc.c-torture/compile/20191108-1.c	2021-04-08 13:56:28.929751064 +0200
-+++ gcc-10.3.0/gcc/testsuite/gcc.c-torture/compile/20191108-1.c	1970-01-01 01:00:00.000000000 +0100
-@@ -1,14 +0,0 @@
--/* PR target/92095 */
--/* Testcase by Sergei Trofimovich <slyfox@inbox.ru> */
--
--typedef union {
--  double a;
--  int b[2];
--} c;
--
--double d(int e)
--{
--  c f;
--  (&f)->b[0] = 15728640;
--  return e ? -(&f)->a : (&f)->a;
--}
-diff -Nur gcc-10.3.0.orig/gcc/testsuite/gcc.target/sparc/overflow-3.c gcc-10.3.0/gcc/testsuite/gcc.target/sparc/overflow-3.c
---- gcc-10.3.0.orig/gcc/testsuite/gcc.target/sparc/overflow-3.c	2021-04-08 13:56:29.453757389 +0200
-+++ gcc-10.3.0/gcc/testsuite/gcc.target/sparc/overflow-3.c	2022-01-24 10:19:54.688097536 +0100
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target lp64 } */
--/* { dg-options "-O -fno-pie" } */
-+/* { dg-options "-O" } */
- 
- #include <stdbool.h>
- #include <stdint.h>
-diff -Nur gcc-10.3.0.orig/gcc/testsuite/gcc.target/sparc/overflow-4.c gcc-10.3.0/gcc/testsuite/gcc.target/sparc/overflow-4.c
---- gcc-10.3.0.orig/gcc/testsuite/gcc.target/sparc/overflow-4.c	2021-04-08 13:56:29.453757389 +0200
-+++ gcc-10.3.0/gcc/testsuite/gcc.target/sparc/overflow-4.c	2022-01-24 10:19:55.336081656 +0100
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target lp64 } */
--/* { dg-options "-O -fno-pie -mno-vis3 -mno-vis4" } */
-+/* { dg-options "-O -mno-vis3 -mno-vis4" } */
- 
- #include <stdbool.h>
- #include <stdint.h>
-diff -Nur gcc-10.3.0.orig/gcc/testsuite/gcc.target/sparc/overflow-5.c gcc-10.3.0/gcc/testsuite/gcc.target/sparc/overflow-5.c
---- gcc-10.3.0.orig/gcc/testsuite/gcc.target/sparc/overflow-5.c	2021-04-08 13:56:29.453757389 +0200
-+++ gcc-10.3.0/gcc/testsuite/gcc.target/sparc/overflow-5.c	2022-01-24 10:19:55.336081656 +0100
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target lp64 } */
--/* { dg-options "-O -fno-pie -mvis3" } */
-+/* { dg-options "-O -mvis3" } */
- 
- #include <stdbool.h>
- #include <stdint.h>