convert microblaze to miniconfig kernel config generation, add support for squashfs and jffs2 rootfs for qemu-microblaze, add support for both machine emulations

1 files changed, 399 insertions, 0 deletions

diff --git a/target/microblaze/ml605.dts b/target/microblaze/ml605.dts
new file mode 100644
index 000000000..6ba0da255
--- /dev/null
+++ b/target/microblaze/ml605.dts
@@ -0,0 +1,399 @@
+/dts-v1/;
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "xlnx,microblaze";
+	model = "petalogix-ml605";
+	ddr3_sdram: memory@50000000 {
+		device_type = "memory";
+		reg = < 0x50000000 0x4000000 >;
+	} ;
+	aliases {
+		ethernet0 = &ethernet;
+		serial0 = &rs232_uart_1;
+	} ;
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		linux,stdout-path = "/axi@1/serial@83e00000";
+	} ;
+	cpus {
+		#address-cells = <1>;
+		#cpus = <0x1>;
+		#size-cells = <0>;
+		microblaze_0: cpu@0 {
+			clock-frequency = <100000000>;
+			compatible = "xlnx,microblaze-8.40.a";
+			d-cache-baseaddr = <0x50000000>;
+			d-cache-highaddr = <0x53ffffff>;
+			d-cache-line-size = <0x10>;
+			d-cache-size = <0x8000>;
+			device_type = "cpu";
+			i-cache-baseaddr = <0x50000000>;
+			i-cache-highaddr = <0x53ffffff>;
+			i-cache-line-size = <0x10>;
+			i-cache-size = <0x8000>;
+			model = "microblaze,8.40.a";
+			reg = <0>;
+			timebase-frequency = <100000000>;
+			xlnx,addr-tag-bits = <0xb>;
+			xlnx,allow-dcache-wr = <0x1>;
+			xlnx,allow-icache-wr = <0x1>;
+			xlnx,area-optimized = <0x0>;
+			xlnx,avoid-primitives = <0x0>;
+			xlnx,branch-target-cache-size = <0x0>;
+			xlnx,cache-byte-size = <0x8000>;
+			xlnx,d-axi = <0x1>;
+			xlnx,d-lmb = <0x1>;
+			xlnx,d-plb = <0x0>;
+			xlnx,data-size = <0x20>;
+			xlnx,dcache-addr-tag = <0xb>;
+			xlnx,dcache-always-used = <0x1>;
+			xlnx,dcache-byte-size = <0x8000>;
+			xlnx,dcache-data-width = <0x0>;
+			xlnx,dcache-force-tag-lutram = <0x0>;
+			xlnx,dcache-interface = <0x0>;
+			xlnx,dcache-line-len = <0x4>;
+			xlnx,dcache-use-fsl = <0x0>;
+			xlnx,dcache-use-writeback = <0x0>;
+			xlnx,dcache-victims = <0x0>;
+			xlnx,debug-enabled = <0x0>;
+			xlnx,div-zero-exception = <0x1>;
+			xlnx,dynamic-bus-sizing = <0x1>;
+			xlnx,ecc-use-ce-exception = <0x0>;
+			xlnx,edge-is-positive = <0x1>;
+			xlnx,endianness = <0x1>;
+			xlnx,family = "virtex6";
+			xlnx,fault-tolerant = <0x0>;
+			xlnx,fpu-exception = <0x1>;
+			xlnx,freq = <0x5f5e100>;
+			xlnx,fsl-data-size = <0x20>;
+			xlnx,fsl-exception = <0x0>;
+			xlnx,fsl-links = <0x0>;
+			xlnx,i-axi = <0x1>;
+			xlnx,i-lmb = <0x1>;
+			xlnx,i-plb = <0x0>;
+			xlnx,icache-always-used = <0x1>;
+			xlnx,icache-data-width = <0x0>;
+			xlnx,icache-force-tag-lutram = <0x0>;
+			xlnx,icache-interface = <0x0>;
+			xlnx,icache-line-len = <0x4>;
+			xlnx,icache-streams = <0x0>;
+			xlnx,icache-use-fsl = <0x0>;
+			xlnx,icache-victims = <0x0>;
+			xlnx,ill-opcode-exception = <0x1>;
+			xlnx,instance = "microblaze_0";
+			xlnx,interconnect = <0x2>;
+			xlnx,interrupt-is-edge = <0x0>;
+			xlnx,lockstep-slave = <0x0>;
+			xlnx,mmu-dtlb-size = <0x2>;
+			xlnx,mmu-itlb-size = <0x4>;
+			xlnx,mmu-privileged-instr = <0x0>;
+			xlnx,mmu-tlb-access = <0x3>;
+			xlnx,mmu-zones = <0x2>;
+			xlnx,number-of-pc-brk = <0x1>;
+			xlnx,number-of-rd-addr-brk = <0x0>;
+			xlnx,number-of-wr-addr-brk = <0x0>;
+			xlnx,opcode-0x0-illegal = <0x0>;
+			xlnx,optimization = <0x0>;
+			xlnx,pc-width = <0x20>;
+			xlnx,pvr = <0x2>;
+			xlnx,pvr-user1 = <0x0>;
+			xlnx,pvr-user2 = <0x0>;
+			xlnx,reset-msr = <0x0>;
+			xlnx,sco = <0x0>;
+			xlnx,stream-interconnect = <0x0>;
+			xlnx,unaligned-exceptions = <0x0>;
+			xlnx,use-barrel = <0x1>;
+			xlnx,use-branch-target-cache = <0x0>;
+			xlnx,use-dcache = <0x1>;
+			xlnx,use-div = <0x1>;
+			xlnx,use-ext-brk = <0x1>;
+			xlnx,use-ext-nm-brk = <0x1>;
+			xlnx,use-extended-fsl-instr = <0x0>;
+			xlnx,use-fpu = <0x1>;
+			xlnx,use-hw-mul = <0x2>;
+			xlnx,use-icache = <0x1>;
+			xlnx,use-interrupt = <0x1>;
+			xlnx,use-mmu = <0x3>;
+			xlnx,use-msr-instr = <0x1>;
+			xlnx,use-pcmp-instr = <0x1>;
+			xlnx,use-reorder-instr = <0x1>;
+			xlnx,use-stack-protection = <0x0>;
+		} ;
+	} ;
+	axi4_0: axi@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
+		ranges ;
+	} ;
+	axi4lite_0: axi@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
+		ranges ;
+		ethernet: axi-ethernet@82780000 {
+			axistream-connected = <&ethernet_dma>;
+			axistream-control-connected = <&ethernet_dma>;
+			clock-frequency = <100000000>;
+			compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a";
+			device_type = "network";
+			interrupt-parent = <&microblaze_0_intc>;
+			interrupts = < 3 2 >;
+			local-mac-address = [ 00 0a 35 00 81 91 ];
+			phy-handle = <&phy0>;
+			reg = < 0x82780000 0x40000 >;
+			xlnx,avb = <0x0>;
+			xlnx,halfdup = <0x0>;
+			xlnx,include-io = <0x1>;
+			xlnx,mcast-extend = <0x0>;
+			xlnx,phy-type = <0x1>;
+			xlnx,phyaddr = "0B00001";
+			xlnx,rxcsum = <0x0>;
+			xlnx,rxmem = <0x1000>;
+			xlnx,rxvlan-strp = <0x0>;
+			xlnx,rxvlan-tag = <0x0>;
+			xlnx,rxvlan-tran = <0x0>;
+			xlnx,stats = <0x0>;
+			xlnx,txcsum = <0x0>;
+			xlnx,txmem = <0x1000>;
+			xlnx,txvlan-strp = <0x0>;
+			xlnx,txvlan-tag = <0x0>;
+			xlnx,txvlan-tran = <0x0>;
+			xlnx,type = <0x2>;
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				phy0: phy@7 {
+					compatible = "marvell,88e1111";
+					device_type = "ethernet-phy";
+					reg = <7>;
+				} ;
+			} ;
+		} ;
+		ethernet_dma: axi-dma@84600000 {
+			axistream-connected = <&ethernet>;
+			axistream-control-connected = <&ethernet>;
+			compatible = "xlnx,axi-dma-4.00.a", "xlnx,axi-dma-1.00.a";
+			interrupt-parent = <&microblaze_0_intc>;
+			interrupts = < 1 2 0 2 >;
+			reg = < 0x84600000 0x10000 >;
+			xlnx,dlytmr-resolution = <0x4e2>;
+			xlnx,family = "virtex6";
+			xlnx,include-mm2s = <0x1>;
+			xlnx,include-mm2s-dre = <0x1>;
+			xlnx,include-s2mm = <0x1>;
+			xlnx,include-s2mm-dre = <0x1>;
+			xlnx,include-sg = <0x1>;
+			xlnx,mm2s-burst-size = <0x10>;
+			xlnx,prmry-is-aclk-async = <0x0>;
+			xlnx,s2mm-burst-size = <0x10>;
+			xlnx,sg-include-desc-queue = <0x1>;
+			xlnx,sg-include-stscntrl-strm = <0x1>;
+			xlnx,sg-length-width = <0x10>;
+			xlnx,sg-use-stsapp-length = <0x1>;
+		} ;
+		rs232_uart_1: serial@83e00000 {
+			clock-frequency = <100000000>;
+			compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a";
+			current-speed = <115200>;
+			device_type = "serial";
+			interrupt-parent = <&microblaze_0_intc>;
+			interrupts = < 5 2 >;
+			reg = < 0x83e00000 0x10000 >;
+			reg-offset = <0x1000>;
+			reg-shift = <2>;
+			xlnx,external-xin-clk-hz = <0x17d7840>;
+			xlnx,family = "virtex6";
+			xlnx,has-external-rclk = <0x0>;
+			xlnx,has-external-xin = <0x0>;
+			xlnx,instance = "RS232_Uart_1";
+			xlnx,is-a-16550 = <0x1>;
+			xlnx,use-modem-ports = <0x0>;
+			xlnx,use-user-ports = <0x0>;
+		} ;
+		pflash: flash@86000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "xlnx,axi-emc-1.03.a", "cfi-flash";
+			bank-width = <2>;
+			reg = < 0x86000000 0x02000000 >;
+			xlnx,axi-clk-period-ps = <0x2710>;
+			xlnx,family = "virtex6";
+			xlnx,include-datawidth-matching-0 = <0x1>;
+			xlnx,include-datawidth-matching-1 = <0x0>;
+			xlnx,include-datawidth-matching-2 = <0x0>;
+			xlnx,include-datawidth-matching-3 = <0x0>;
+			xlnx,include-negedge-ioregs = <0x0>;
+			xlnx,instance = "Linear_Flash";
+			xlnx,lflash-period-ps = <0x4e20>;
+			xlnx,linear-flash-sync-burst = <0x0>;
+			xlnx,max-mem-width = <0x10>;
+			xlnx,mem0-type = <0x2>;
+			xlnx,mem0-width = <0x10>;
+			xlnx,mem1-type = <0x0>;
+			xlnx,mem1-width = <0x20>;
+			xlnx,mem2-type = <0x0>;
+			xlnx,mem2-width = <0x20>;
+			xlnx,mem3-type = <0x0>;
+			xlnx,mem3-width = <0x20>;
+			xlnx,num-banks-mem = <0x1>;
+			xlnx,parity-type-mem-0 = <0x0>;
+			xlnx,parity-type-mem-1 = <0x0>;
+			xlnx,parity-type-mem-2 = <0x0>;
+			xlnx,parity-type-mem-3 = <0x0>;
+			xlnx,s-axi-en-reg = <0x0>;
+			xlnx,s-axi-mem-addr-width = <0x20>;
+			xlnx,s-axi-mem-data-width = <0x20>;
+			xlnx,s-axi-mem-id-width = <0x1>;
+			xlnx,s-axi-mem-protocol = "AXI4LITE";
+			xlnx,s-axi-reg-addr-width = <0x5>;
+			xlnx,s-axi-reg-data-width = <0x20>;
+			xlnx,s-axi-reg-protocol = "axi4";
+			xlnx,synch-pipedelay-0 = <0x2>;
+			xlnx,synch-pipedelay-1 = <0x2>;
+			xlnx,synch-pipedelay-2 = <0x2>;
+			xlnx,synch-pipedelay-3 = <0x2>;
+			xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
+			xlnx,tavdv-ps-mem-1 = <0x3a98>;
+			xlnx,tavdv-ps-mem-2 = <0x3a98>;
+			xlnx,tavdv-ps-mem-3 = <0x3a98>;
+			xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
+			xlnx,tcedv-ps-mem-1 = <0x3a98>;
+			xlnx,tcedv-ps-mem-2 = <0x3a98>;
+			xlnx,tcedv-ps-mem-3 = <0x3a98>;
+			xlnx,thzce-ps-mem-0 = <0x88b8>;
+			xlnx,thzce-ps-mem-1 = <0x1b58>;
+			xlnx,thzce-ps-mem-2 = <0x1b58>;
+			xlnx,thzce-ps-mem-3 = <0x1b58>;
+			xlnx,thzoe-ps-mem-0 = <0x1b58>;
+			xlnx,thzoe-ps-mem-1 = <0x1b58>;
+			xlnx,thzoe-ps-mem-2 = <0x1b58>;
+			xlnx,thzoe-ps-mem-3 = <0x1b58>;
+			xlnx,tlzwe-ps-mem-0 = <0x88b8>;
+			xlnx,tlzwe-ps-mem-1 = <0x0>;
+			xlnx,tlzwe-ps-mem-2 = <0x0>;
+			xlnx,tlzwe-ps-mem-3 = <0x0>;
+			xlnx,tpacc-ps-flash-0 = <0x61a8>;
+			xlnx,tpacc-ps-flash-1 = <0x61a8>;
+			xlnx,tpacc-ps-flash-2 = <0x61a8>;
+			xlnx,tpacc-ps-flash-3 = <0x61a8>;
+			xlnx,twc-ps-mem-0 = <0x11170>;
+			xlnx,twc-ps-mem-1 = <0x3a98>;
+			xlnx,twc-ps-mem-2 = <0x3a98>;
+			xlnx,twc-ps-mem-3 = <0x3a98>;
+			xlnx,twp-ps-mem-0 = <0x11170>;
+			xlnx,twp-ps-mem-1 = <0x2ee0>;
+			xlnx,twp-ps-mem-2 = <0x2ee0>;
+			xlnx,twp-ps-mem-3 = <0x2ee0>;
+			xlnx,twph-ps-mem-0 = <0x2ee0>;
+			xlnx,twph-ps-mem-1 = <0x2ee0>;
+			xlnx,twph-ps-mem-2 = <0x2ee0>;
+			xlnx,twph-ps-mem-3 = <0x2ee0>;
+			xlnx,wr-rec-time-mem-0 = <0x186a0>;
+			xlnx,wr-rec-time-mem-1 = <0x186a0>;
+			xlnx,wr-rec-time-mem-2 = <0x186a0>;
+			xlnx,wr-rec-time-mem-3 = <0x186a0>;
+			partition@0x00000000 {
+				label = "rootfs";
+				reg = <0x00000000 0x02000000>;
+			};
+		} ;
+		microblaze_0_intc: interrupt-controller@81800000 {
+			#interrupt-cells = <0x2>;
+			compatible = "xlnx,axi-intc-1.02.a", "xlnx,xps-intc-1.00.a";
+			interrupt-controller ;
+			reg = < 0x81800000 0x10000 >;
+			xlnx,kind-of-intr = <0x0>;
+			xlnx,num-intr-inputs = <0x7>;
+		} ;
+		system_timer: system-timer@83c00000 {
+			clock-frequency = <100000000>;
+			compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a";
+			interrupt-parent = <&microblaze_0_intc>;
+			interrupts = < 2 2 >;
+			reg = < 0x83c00000 0x10000 >;
+			xlnx,count-width = <0x20>;
+			xlnx,family = "virtex6";
+			xlnx,gen0-assert = <0x1>;
+			xlnx,gen1-assert = <0x1>;
+			xlnx,instance = "system_timer";
+			xlnx,one-timer-only = <0x0>;
+			xlnx,trig0-assert = <0x1>;
+			xlnx,trig1-assert = <0x1>;
+		} ;
+       axi_pcie_0: axi-pcie@80000000 {
+           #address-cells = <2>;
+           #size-cells = <2>;
+           compatible = "xlnx,axi-pcie-1.05.a";
+           interrupt-parent = <&microblaze_0_intc>;
+           interrupts = < 6 2 >;
+           ranges = < 0x00000002 0x00000000 0x40000000 0x70000000 0x00000000 0x00000000 0x10000000 >;
+           reg = < 0x80000000 0x1000000 >;
+           xlnx,axi-aclk-freq-hz = <0x7735940>;
+           xlnx,axibar-0 = <0x70000000>;
+           xlnx,axibar-1 = <0xffffffff>;
+           xlnx,axibar-2 = <0xffffffff>;
+           xlnx,axibar-3 = <0xffffffff>;
+           xlnx,axibar-4 = <0xffffffff>;
+           xlnx,axibar-5 = <0xffffffff>;
+           xlnx,axibar-as-0 = <0x0>;
+           xlnx,axibar-as-1 = <0x0>;
+           xlnx,axibar-as-2 = <0x0>;
+           xlnx,axibar-as-3 = <0x0>;
+           xlnx,axibar-as-4 = <0x0>;
+           xlnx,axibar-as-5 = <0x0>;
+           xlnx,axibar-highaddr-0 = <0x7fffffff>;
+           xlnx,axibar-highaddr-1 = <0x0>;
+           xlnx,axibar-highaddr-2 = <0x0>;
+           xlnx,axibar-highaddr-3 = <0x0>;
+           xlnx,axibar-highaddr-4 = <0x0>;
+           xlnx,axibar-highaddr-5 = <0x0>;
+           xlnx,axibar-num = <0x1>;
+           xlnx,axibar2pciebar-0 = <0x40000000>;
+           xlnx,axibar2pciebar-1 = <0x0>;
+           xlnx,axibar2pciebar-2 = <0x0>;
+           xlnx,axibar2pciebar-3 = <0x0>;
+           xlnx,axibar2pciebar-4 = <0x0>;
+           xlnx,axibar2pciebar-5 = <0x0>;
+           xlnx,class-code = <0x60400>;
+           xlnx,comp-timeout = <0x1>;
+           xlnx,device-id = <0x705>;
+           xlnx,family = "virtex6";
+           xlnx,include-baroffset-reg = <0x0>;
+           xlnx,include-rc = <0x1>;
+           xlnx,instance = "axi_pcie_0";
+           xlnx,interrupt-pin = <0x0>;
+           xlnx,max-link-speed = <0x0>;
+           xlnx,no-of-lanes = <0x1>;
+           xlnx,num-msi-req = <0x0>;
+           xlnx,pcie-cap-slot-implemented = <0x0>;
+           xlnx,pcie-use-mode = "1.0";
+           xlnx,pciebar-as = <0x0>;
+           xlnx,pciebar-len-0 = <0x1c>;
+           xlnx,pciebar-len-1 = <0xd>;
+           xlnx,pciebar-len-2 = <0xd>;
+           xlnx,pciebar-num = <0x1>;
+           xlnx,pciebar2axibar-0 = <0xc0000000>;
+           xlnx,pciebar2axibar-0-sec = <0x0>;
+           xlnx,pciebar2axibar-1 = <0xffffffff>;
+           xlnx,pciebar2axibar-1-sec = <0x0>;
+           xlnx,pciebar2axibar-2 = <0xffffffff>;
+           xlnx,pciebar2axibar-2-sec = <0x0>;
+           xlnx,ref-clk-freq = <0x0>;
+           xlnx,ref-clk-freq-hz = <0x5f5e100>;
+           xlnx,rev-id = <0x0>;
+           xlnx,s-axi-ctl-aclk-freq-hz = <0x7735940>;
+           xlnx,s-axi-ctl-protocol = "AXI4LITE";
+           xlnx,s-axi-id-width = <0x1>;
+           xlnx,s-axi-support-threads = <0x1>;
+           xlnx,s-axi-supports-narrow-burst = <0x0>;
+           xlnx,s-axi-supports-read = <0x1>;
+           xlnx,s-axi-supports-write = <0x1>;
+           xlnx,subsystem-id = <0x0>;
+           xlnx,subsystem-vendor-id = <0x0>;
+           xlnx,vendor-id = <0x10ee>;
+       } ;
+		
+	} ;
+} ;