cleanup patch, remove orig file

1 files changed, 0 insertions, 3508 deletions

diff --git a/target/m68k/qemu-m68k-mcf5208/patches/4.1.20/m68k-coldfire-fec.patch b/target/m68k/qemu-m68k-mcf5208/patches/4.1.20/m68k-coldfire-fec.patch
index daebb62ae..690befe8f 100644
--- a/target/m68k/qemu-m68k-mcf5208/patches/4.1.20/m68k-coldfire-fec.patch
+++ b/target/m68k/qemu-m68k-mcf5208/patches/4.1.20/m68k-coldfire-fec.patch
@@ -116,3511 +116,3 @@ diff -Nur linux-4.1.10.orig/drivers/net/ethernet/freescale/fec_main.c linux-4.1.
  	/* default enable pause frame auto negotiation */
  	if (fep->quirks & FEC_QUIRK_HAS_GBIT)
  		fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
-diff -Nur linux-4.1.10.orig/drivers/net/ethernet/freescale/fec_main.c.orig linux-4.1.10/drivers/net/ethernet/freescale/fec_main.c.orig
---- linux-4.1.10.orig/drivers/net/ethernet/freescale/fec_main.c.orig	1970-01-01 01:00:00.000000000 +0100
-+++ linux-4.1.10/drivers/net/ethernet/freescale/fec_main.c.orig	2015-10-03 13:49:38.000000000 +0200
-@@ -0,0 +1,3504 @@
-+/*
-+ * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
-+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
-+ *
-+ * Right now, I am very wasteful with the buffers.  I allocate memory
-+ * pages and then divide them into 2K frame buffers.  This way I know I
-+ * have buffers large enough to hold one frame within one buffer descriptor.
-+ * Once I get this working, I will use 64 or 128 byte CPM buffers, which
-+ * will be much more memory efficient and will easily handle lots of
-+ * small packets.
-+ *
-+ * Much better multiple PHY support by Magnus Damm.
-+ * Copyright (c) 2000 Ericsson Radio Systems AB.
-+ *
-+ * Support for FEC controller of ColdFire processors.
-+ * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
-+ *
-+ * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
-+ * Copyright (c) 2004-2006 Macq Electronique SA.
-+ *
-+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/ptrace.h>
-+#include <linux/errno.h>
-+#include <linux/ioport.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/in.h>
-+#include <linux/ip.h>
-+#include <net/ip.h>
-+#include <net/tso.h>
-+#include <linux/tcp.h>
-+#include <linux/udp.h>
-+#include <linux/icmp.h>
-+#include <linux/spinlock.h>
-+#include <linux/workqueue.h>
-+#include <linux/bitops.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/phy.h>
-+#include <linux/fec.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_gpio.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_net.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/if_vlan.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/prefetch.h>
-+
-+#include <asm/cacheflush.h>
-+
-+#include "fec.h"
-+
-+static void set_multicast_list(struct net_device *ndev);
-+static void fec_enet_itr_coal_init(struct net_device *ndev);
-+
-+#define DRIVER_NAME	"fec"
-+
-+#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
-+
-+/* Pause frame feild and FIFO threshold */
-+#define FEC_ENET_FCE	(1 << 5)
-+#define FEC_ENET_RSEM_V	0x84
-+#define FEC_ENET_RSFL_V	16
-+#define FEC_ENET_RAEM_V	0x8
-+#define FEC_ENET_RAFL_V	0x8
-+#define FEC_ENET_OPD_V	0xFFF0
-+
-+static struct platform_device_id fec_devtype[] = {
-+	{
-+		/* keep it for coldfire */
-+		.name = DRIVER_NAME,
-+		.driver_data = 0,
-+	}, {
-+		.name = "imx25-fec",
-+		.driver_data = FEC_QUIRK_USE_GASKET,
-+	}, {
-+		.name = "imx27-fec",
-+		.driver_data = 0,
-+	}, {
-+		.name = "imx28-fec",
-+		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
-+				FEC_QUIRK_SINGLE_MDIO,
-+	}, {
-+		.name = "imx6q-fec",
-+		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
-+				FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
-+				FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
-+	}, {
-+		.name = "mvf600-fec",
-+		.driver_data = FEC_QUIRK_ENET_MAC,
-+	}, {
-+		.name = "imx6sx-fec",
-+		.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
-+				FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
-+				FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
-+				FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+MODULE_DEVICE_TABLE(platform, fec_devtype);
-+
-+enum imx_fec_type {
-+	IMX25_FEC = 1,	/* runs on i.mx25/50/53 */
-+	IMX27_FEC,	/* runs on i.mx27/35/51 */
-+	IMX28_FEC,
-+	IMX6Q_FEC,
-+	MVF600_FEC,
-+	IMX6SX_FEC,
-+};
-+
-+static const struct of_device_id fec_dt_ids[] = {
-+	{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
-+	{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
-+	{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
-+	{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
-+	{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
-+	{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, fec_dt_ids);
-+
-+static unsigned char macaddr[ETH_ALEN];
-+module_param_array(macaddr, byte, NULL, 0);
-+MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
-+
-+#if defined(CONFIG_M5272)
-+/*
-+ * Some hardware gets it MAC address out of local flash memory.
-+ * if this is non-zero then assume it is the address to get MAC from.
-+ */
-+#if defined(CONFIG_NETtel)
-+#define	FEC_FLASHMAC	0xf0006006
-+#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
-+#define	FEC_FLASHMAC	0xf0006000
-+#elif defined(CONFIG_CANCam)
-+#define	FEC_FLASHMAC	0xf0020000
-+#elif defined (CONFIG_M5272C3)
-+#define	FEC_FLASHMAC	(0xffe04000 + 4)
-+#elif defined(CONFIG_MOD5272)
-+#define FEC_FLASHMAC	0xffc0406b
-+#else
-+#define	FEC_FLASHMAC	0
-+#endif
-+#endif /* CONFIG_M5272 */
-+
-+/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
-+ */
-+#define PKT_MAXBUF_SIZE		1522
-+#define PKT_MINBUF_SIZE		64
-+#define PKT_MAXBLR_SIZE		1536
-+
-+/* FEC receive acceleration */
-+#define FEC_RACC_IPDIS		(1 << 1)
-+#define FEC_RACC_PRODIS		(1 << 2)
-+#define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
-+
-+/*
-+ * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
-+ * size bits. Other FEC hardware does not, so we need to take that into
-+ * account when setting it.
-+ */
-+#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
-+#define	OPT_FRAME_SIZE	(PKT_MAXBUF_SIZE << 16)
-+#else
-+#define	OPT_FRAME_SIZE	0
-+#endif
-+
-+/* FEC MII MMFR bits definition */
-+#define FEC_MMFR_ST		(1 << 30)
-+#define FEC_MMFR_OP_READ	(2 << 28)
-+#define FEC_MMFR_OP_WRITE	(1 << 28)
-+#define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
-+#define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
-+#define FEC_MMFR_TA		(2 << 16)
-+#define FEC_MMFR_DATA(v)	(v & 0xffff)
-+/* FEC ECR bits definition */
-+#define FEC_ECR_MAGICEN		(1 << 2)
-+#define FEC_ECR_SLEEP		(1 << 3)
-+
-+#define FEC_MII_TIMEOUT		30000 /* us */
-+
-+/* Transmitter timeout */
-+#define TX_TIMEOUT (2 * HZ)
-+
-+#define FEC_PAUSE_FLAG_AUTONEG	0x1
-+#define FEC_PAUSE_FLAG_ENABLE	0x2
-+#define FEC_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
-+#define FEC_WOL_FLAG_ENABLE		(0x1 << 1)
-+#define FEC_WOL_FLAG_SLEEP_ON		(0x1 << 2)
-+
-+#define COPYBREAK_DEFAULT	256
-+
-+#define TSO_HEADER_SIZE		128
-+/* Max number of allowed TCP segments for software TSO */
-+#define FEC_MAX_TSO_SEGS	100
-+#define FEC_MAX_SKB_DESCS	(FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
-+
-+#define IS_TSO_HEADER(txq, addr) \
-+	((addr >= txq->tso_hdrs_dma) && \
-+	(addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
-+
-+static int mii_cnt;
-+
-+static inline
-+struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
-+				      struct fec_enet_private *fep,
-+				      int queue_id)
-+{
-+	struct bufdesc *new_bd = bdp + 1;
-+	struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
-+	struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
-+	struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
-+	struct bufdesc_ex *ex_base;
-+	struct bufdesc *base;
-+	int ring_size;
-+
-+	if (bdp >= txq->tx_bd_base) {
-+		base = txq->tx_bd_base;
-+		ring_size = txq->tx_ring_size;
-+		ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
-+	} else {
-+		base = rxq->rx_bd_base;
-+		ring_size = rxq->rx_ring_size;
-+		ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
-+	}
-+
-+	if (fep->bufdesc_ex)
-+		return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
-+			ex_base : ex_new_bd);
-+	else
-+		return (new_bd >= (base + ring_size)) ?
-+			base : new_bd;
-+}
-+
-+static inline
-+struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
-+				      struct fec_enet_private *fep,
-+				      int queue_id)
-+{
-+	struct bufdesc *new_bd = bdp - 1;
-+	struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
-+	struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
-+	struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
-+	struct bufdesc_ex *ex_base;
-+	struct bufdesc *base;
-+	int ring_size;
-+
-+	if (bdp >= txq->tx_bd_base) {
-+		base = txq->tx_bd_base;
-+		ring_size = txq->tx_ring_size;
-+		ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
-+	} else {
-+		base = rxq->rx_bd_base;
-+		ring_size = rxq->rx_ring_size;
-+		ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
-+	}
-+
-+	if (fep->bufdesc_ex)
-+		return (struct bufdesc *)((ex_new_bd < ex_base) ?
-+			(ex_new_bd + ring_size) : ex_new_bd);
-+	else
-+		return (new_bd < base) ? (new_bd + ring_size) : new_bd;
-+}
-+
-+static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
-+				struct fec_enet_private *fep)
-+{
-+	return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
-+}
-+
-+static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
-+					struct fec_enet_priv_tx_q *txq)
-+{
-+	int entries;
-+
-+	entries = ((const char *)txq->dirty_tx -
-+			(const char *)txq->cur_tx) / fep->bufdesc_size - 1;
-+
-+	return entries > 0 ? entries : entries + txq->tx_ring_size;
-+}
-+
-+static void swap_buffer(void *bufaddr, int len)
-+{
-+	int i;
-+	unsigned int *buf = bufaddr;
-+
-+	for (i = 0; i < len; i += 4, buf++)
-+		swab32s(buf);
-+}
-+
-+static void swap_buffer2(void *dst_buf, void *src_buf, int len)
-+{
-+	int i;
-+	unsigned int *src = src_buf;
-+	unsigned int *dst = dst_buf;
-+
-+	for (i = 0; i < len; i += 4, src++, dst++)
-+		*dst = swab32p(src);
-+}
-+
-+static void fec_dump(struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	struct bufdesc *bdp;
-+	struct fec_enet_priv_tx_q *txq;
-+	int index = 0;
-+
-+	netdev_info(ndev, "TX ring dump\n");
-+	pr_info("Nr     SC     addr       len  SKB\n");
-+
-+	txq = fep->tx_queue[0];
-+	bdp = txq->tx_bd_base;
-+
-+	do {
-+		pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
-+			index,
-+			bdp == txq->cur_tx ? 'S' : ' ',
-+			bdp == txq->dirty_tx ? 'H' : ' ',
-+			bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
-+			txq->tx_skbuff[index]);
-+		bdp = fec_enet_get_nextdesc(bdp, fep, 0);
-+		index++;
-+	} while (bdp != txq->tx_bd_base);
-+}
-+
-+static inline bool is_ipv4_pkt(struct sk_buff *skb)
-+{
-+	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
-+}
-+
-+static int
-+fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
-+{
-+	/* Only run for packets requiring a checksum. */
-+	if (skb->ip_summed != CHECKSUM_PARTIAL)
-+		return 0;
-+
-+	if (unlikely(skb_cow_head(skb, 0)))
-+		return -1;
-+
-+	if (is_ipv4_pkt(skb))
-+		ip_hdr(skb)->check = 0;
-+	*(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
-+
-+	return 0;
-+}
-+
-+static int
-+fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
-+			     struct sk_buff *skb,
-+			     struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	struct bufdesc *bdp = txq->cur_tx;
-+	struct bufdesc_ex *ebdp;
-+	int nr_frags = skb_shinfo(skb)->nr_frags;
-+	unsigned short queue = skb_get_queue_mapping(skb);
-+	int frag, frag_len;
-+	unsigned short status;
-+	unsigned int estatus = 0;
-+	skb_frag_t *this_frag;
-+	unsigned int index;
-+	void *bufaddr;
-+	dma_addr_t addr;
-+	int i;
-+
-+	for (frag = 0; frag < nr_frags; frag++) {
-+		this_frag = &skb_shinfo(skb)->frags[frag];
-+		bdp = fec_enet_get_nextdesc(bdp, fep, queue);
-+		ebdp = (struct bufdesc_ex *)bdp;
-+
-+		status = bdp->cbd_sc;
-+		status &= ~BD_ENET_TX_STATS;
-+		status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
-+		frag_len = skb_shinfo(skb)->frags[frag].size;
-+
-+		/* Handle the last BD specially */
-+		if (frag == nr_frags - 1) {
-+			status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
-+			if (fep->bufdesc_ex) {
-+				estatus |= BD_ENET_TX_INT;
-+				if (unlikely(skb_shinfo(skb)->tx_flags &
-+					SKBTX_HW_TSTAMP && fep->hwts_tx_en))
-+					estatus |= BD_ENET_TX_TS;
-+			}
-+		}
-+
-+		if (fep->bufdesc_ex) {
-+			if (fep->quirks & FEC_QUIRK_HAS_AVB)
-+				estatus |= FEC_TX_BD_FTYPE(queue);
-+			if (skb->ip_summed == CHECKSUM_PARTIAL)
-+				estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
-+			ebdp->cbd_bdu = 0;
-+			ebdp->cbd_esc = estatus;
-+		}
-+
-+		bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
-+
-+		index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
-+		if (((unsigned long) bufaddr) & fep->tx_align ||
-+			fep->quirks & FEC_QUIRK_SWAP_FRAME) {
-+			memcpy(txq->tx_bounce[index], bufaddr, frag_len);
-+			bufaddr = txq->tx_bounce[index];
-+
-+			if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
-+				swap_buffer(bufaddr, frag_len);
-+		}
-+
-+		addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
-+				      DMA_TO_DEVICE);
-+		if (dma_mapping_error(&fep->pdev->dev, addr)) {
-+			dev_kfree_skb_any(skb);
-+			if (net_ratelimit())
-+				netdev_err(ndev, "Tx DMA memory map failed\n");
-+			goto dma_mapping_error;
-+		}
-+
-+		bdp->cbd_bufaddr = addr;
-+		bdp->cbd_datlen = frag_len;
-+		bdp->cbd_sc = status;
-+	}
-+
-+	txq->cur_tx = bdp;
-+
-+	return 0;
-+
-+dma_mapping_error:
-+	bdp = txq->cur_tx;
-+	for (i = 0; i < frag; i++) {
-+		bdp = fec_enet_get_nextdesc(bdp, fep, queue);
-+		dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
-+				bdp->cbd_datlen, DMA_TO_DEVICE);
-+	}
-+	return NETDEV_TX_OK;
-+}
-+
-+static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
-+				   struct sk_buff *skb, struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	int nr_frags = skb_shinfo(skb)->nr_frags;
-+	struct bufdesc *bdp, *last_bdp;
-+	void *bufaddr;
-+	dma_addr_t addr;
-+	unsigned short status;
-+	unsigned short buflen;
-+	unsigned short queue;
-+	unsigned int estatus = 0;
-+	unsigned int index;
-+	int entries_free;
-+	int ret;
-+
-+	entries_free = fec_enet_get_free_txdesc_num(fep, txq);
-+	if (entries_free < MAX_SKB_FRAGS + 1) {
-+		dev_kfree_skb_any(skb);
-+		if (net_ratelimit())
-+			netdev_err(ndev, "NOT enough BD for SG!\n");
-+		return NETDEV_TX_OK;
-+	}
-+
-+	/* Protocol checksum off-load for TCP and UDP. */
-+	if (fec_enet_clear_csum(skb, ndev)) {
-+		dev_kfree_skb_any(skb);
-+		return NETDEV_TX_OK;
-+	}
-+
-+	/* Fill in a Tx ring entry */
-+	bdp = txq->cur_tx;
-+	status = bdp->cbd_sc;
-+	status &= ~BD_ENET_TX_STATS;
-+
-+	/* Set buffer length and buffer pointer */
-+	bufaddr = skb->data;
-+	buflen = skb_headlen(skb);
-+
-+	queue = skb_get_queue_mapping(skb);
-+	index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
-+	if (((unsigned long) bufaddr) & fep->tx_align ||
-+		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
-+		memcpy(txq->tx_bounce[index], skb->data, buflen);
-+		bufaddr = txq->tx_bounce[index];
-+
-+		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
-+			swap_buffer(bufaddr, buflen);
-+	}
-+
-+	/* Push the data cache so the CPM does not get stale memory data. */
-+	addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
-+	if (dma_mapping_error(&fep->pdev->dev, addr)) {
-+		dev_kfree_skb_any(skb);
-+		if (net_ratelimit())
-+			netdev_err(ndev, "Tx DMA memory map failed\n");
-+		return NETDEV_TX_OK;
-+	}
-+
-+	if (nr_frags) {
-+		ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
-+		if (ret)
-+			return ret;
-+	} else {
-+		status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
-+		if (fep->bufdesc_ex) {
-+			estatus = BD_ENET_TX_INT;
-+			if (unlikely(skb_shinfo(skb)->tx_flags &
-+				SKBTX_HW_TSTAMP && fep->hwts_tx_en))
-+				estatus |= BD_ENET_TX_TS;
-+		}
-+	}
-+
-+	if (fep->bufdesc_ex) {
-+
-+		struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
-+
-+		if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
-+			fep->hwts_tx_en))
-+			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
-+
-+		if (fep->quirks & FEC_QUIRK_HAS_AVB)
-+			estatus |= FEC_TX_BD_FTYPE(queue);
-+
-+		if (skb->ip_summed == CHECKSUM_PARTIAL)
-+			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
-+
-+		ebdp->cbd_bdu = 0;
-+		ebdp->cbd_esc = estatus;
-+	}
-+
-+	last_bdp = txq->cur_tx;
-+	index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
-+	/* Save skb pointer */
-+	txq->tx_skbuff[index] = skb;
-+
-+	bdp->cbd_datlen = buflen;
-+	bdp->cbd_bufaddr = addr;
-+
-+	/* Send it on its way.  Tell FEC it's ready, interrupt when done,
-+	 * it's the last BD of the frame, and to put the CRC on the end.
-+	 */
-+	status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
-+	bdp->cbd_sc = status;
-+
-+	/* If this was the last BD in the ring, start at the beginning again. */
-+	bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
-+
-+	skb_tx_timestamp(skb);
-+
-+	txq->cur_tx = bdp;
-+
-+	/* Trigger transmission start */
-+	writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
-+
-+	return 0;
-+}
-+
-+static int
-+fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
-+			  struct net_device *ndev,
-+			  struct bufdesc *bdp, int index, char *data,
-+			  int size, bool last_tcp, bool is_last)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
-+	unsigned short queue = skb_get_queue_mapping(skb);
-+	unsigned short status;
-+	unsigned int estatus = 0;
-+	dma_addr_t addr;
-+
-+	status = bdp->cbd_sc;
-+	status &= ~BD_ENET_TX_STATS;
-+
-+	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
-+
-+	if (((unsigned long) data) & fep->tx_align ||
-+		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
-+		memcpy(txq->tx_bounce[index], data, size);
-+		data = txq->tx_bounce[index];
-+
-+		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
-+			swap_buffer(data, size);
-+	}
-+
-+	addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
-+	if (dma_mapping_error(&fep->pdev->dev, addr)) {
-+		dev_kfree_skb_any(skb);
-+		if (net_ratelimit())
-+			netdev_err(ndev, "Tx DMA memory map failed\n");
-+		return NETDEV_TX_BUSY;
-+	}
-+
-+	bdp->cbd_datlen = size;
-+	bdp->cbd_bufaddr = addr;
-+
-+	if (fep->bufdesc_ex) {
-+		if (fep->quirks & FEC_QUIRK_HAS_AVB)
-+			estatus |= FEC_TX_BD_FTYPE(queue);
-+		if (skb->ip_summed == CHECKSUM_PARTIAL)
-+			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
-+		ebdp->cbd_bdu = 0;
-+		ebdp->cbd_esc = estatus;
-+	}
-+
-+	/* Handle the last BD specially */
-+	if (last_tcp)
-+		status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
-+	if (is_last) {
-+		status |= BD_ENET_TX_INTR;
-+		if (fep->bufdesc_ex)
-+			ebdp->cbd_esc |= BD_ENET_TX_INT;
-+	}
-+
-+	bdp->cbd_sc = status;
-+
-+	return 0;
-+}
-+
-+static int
-+fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
-+			 struct sk_buff *skb, struct net_device *ndev,
-+			 struct bufdesc *bdp, int index)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
-+	struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
-+	unsigned short queue = skb_get_queue_mapping(skb);
-+	void *bufaddr;
-+	unsigned long dmabuf;
-+	unsigned short status;
-+	unsigned int estatus = 0;
-+
-+	status = bdp->cbd_sc;
-+	status &= ~BD_ENET_TX_STATS;
-+	status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
-+
-+	bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
-+	dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
-+	if (((unsigned long)bufaddr) & fep->tx_align ||
-+		fep->quirks & FEC_QUIRK_SWAP_FRAME) {
-+		memcpy(txq->tx_bounce[index], skb->data, hdr_len);
-+		bufaddr = txq->tx_bounce[index];
-+
-+		if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
-+			swap_buffer(bufaddr, hdr_len);
-+
-+		dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
-+					hdr_len, DMA_TO_DEVICE);
-+		if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
-+			dev_kfree_skb_any(skb);
-+			if (net_ratelimit())
-+				netdev_err(ndev, "Tx DMA memory map failed\n");
-+			return NETDEV_TX_BUSY;
-+		}
-+	}
-+
-+	bdp->cbd_bufaddr = dmabuf;
-+	bdp->cbd_datlen = hdr_len;
-+
-+	if (fep->bufdesc_ex) {
-+		if (fep->quirks & FEC_QUIRK_HAS_AVB)
-+			estatus |= FEC_TX_BD_FTYPE(queue);
-+		if (skb->ip_summed == CHECKSUM_PARTIAL)
-+			estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
-+		ebdp->cbd_bdu = 0;
-+		ebdp->cbd_esc = estatus;
-+	}
-+
-+	bdp->cbd_sc = status;
-+
-+	return 0;
-+}
-+
-+static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
-+				   struct sk_buff *skb,
-+				   struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
-+	int total_len, data_left;
-+	struct bufdesc *bdp = txq->cur_tx;
-+	unsigned short queue = skb_get_queue_mapping(skb);
-+	struct tso_t tso;
-+	unsigned int index = 0;
-+	int ret;
-+
-+	if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
-+		dev_kfree_skb_any(skb);
-+		if (net_ratelimit())
-+			netdev_err(ndev, "NOT enough BD for TSO!\n");
-+		return NETDEV_TX_OK;
-+	}
-+
-+	/* Protocol checksum off-load for TCP and UDP. */
-+	if (fec_enet_clear_csum(skb, ndev)) {
-+		dev_kfree_skb_any(skb);
-+		return NETDEV_TX_OK;
-+	}
-+
-+	/* Initialize the TSO handler, and prepare the first payload */
-+	tso_start(skb, &tso);
-+
-+	total_len = skb->len - hdr_len;
-+	while (total_len > 0) {
-+		char *hdr;
-+
-+		index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
-+		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
-+		total_len -= data_left;
-+
-+		/* prepare packet headers: MAC + IP + TCP */
-+		hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
-+		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
-+		ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
-+		if (ret)
-+			goto err_release;
-+
-+		while (data_left > 0) {
-+			int size;
-+
-+			size = min_t(int, tso.size, data_left);
-+			bdp = fec_enet_get_nextdesc(bdp, fep, queue);
-+			index = fec_enet_get_bd_index(txq->tx_bd_base,
-+						      bdp, fep);
-+			ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
-+							bdp, index,
-+							tso.data, size,
-+							size == data_left,
-+							total_len == 0);
-+			if (ret)
-+				goto err_release;
-+
-+			data_left -= size;
-+			tso_build_data(skb, &tso, size);
-+		}
-+
-+		bdp = fec_enet_get_nextdesc(bdp, fep, queue);
-+	}
-+
-+	/* Save skb pointer */
-+	txq->tx_skbuff[index] = skb;
-+
-+	skb_tx_timestamp(skb);
-+	txq->cur_tx = bdp;
-+
-+	/* Trigger transmission start */
-+	if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
-+	    !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
-+	    !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
-+	    !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
-+	    !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
-+		writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
-+
-+	return 0;
-+
-+err_release:
-+	/* TODO: Release all used data descriptors for TSO */
-+	return ret;
-+}
-+
-+static netdev_tx_t
-+fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	int entries_free;
-+	unsigned short queue;
-+	struct fec_enet_priv_tx_q *txq;
-+	struct netdev_queue *nq;
-+	int ret;
-+
-+	queue = skb_get_queue_mapping(skb);
-+	txq = fep->tx_queue[queue];
-+	nq = netdev_get_tx_queue(ndev, queue);
-+
-+	if (skb_is_gso(skb))
-+		ret = fec_enet_txq_submit_tso(txq, skb, ndev);
-+	else
-+		ret = fec_enet_txq_submit_skb(txq, skb, ndev);
-+	if (ret)
-+		return ret;
-+
-+	entries_free = fec_enet_get_free_txdesc_num(fep, txq);
-+	if (entries_free <= txq->tx_stop_threshold)
-+		netif_tx_stop_queue(nq);
-+
-+	return NETDEV_TX_OK;
-+}
-+
-+/* Init RX & TX buffer descriptors
-+ */
-+static void fec_enet_bd_init(struct net_device *dev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(dev);
-+	struct fec_enet_priv_tx_q *txq;
-+	struct fec_enet_priv_rx_q *rxq;
-+	struct bufdesc *bdp;
-+	unsigned int i;
-+	unsigned int q;
-+
-+	for (q = 0; q < fep->num_rx_queues; q++) {
-+		/* Initialize the receive buffer descriptors. */
-+		rxq = fep->rx_queue[q];
-+		bdp = rxq->rx_bd_base;
-+
-+		for (i = 0; i < rxq->rx_ring_size; i++) {
-+
-+			/* Initialize the BD for every fragment in the page. */
-+			if (bdp->cbd_bufaddr)
-+				bdp->cbd_sc = BD_ENET_RX_EMPTY;
-+			else
-+				bdp->cbd_sc = 0;
-+			bdp = fec_enet_get_nextdesc(bdp, fep, q);
-+		}
-+
-+		/* Set the last buffer to wrap */
-+		bdp = fec_enet_get_prevdesc(bdp, fep, q);
-+		bdp->cbd_sc |= BD_SC_WRAP;
-+
-+		rxq->cur_rx = rxq->rx_bd_base;
-+	}
-+
-+	for (q = 0; q < fep->num_tx_queues; q++) {
-+		/* ...and the same for transmit */
-+		txq = fep->tx_queue[q];
-+		bdp = txq->tx_bd_base;
-+		txq->cur_tx = bdp;
-+
-+		for (i = 0; i < txq->tx_ring_size; i++) {
-+			/* Initialize the BD for every fragment in the page. */
-+			bdp->cbd_sc = 0;
-+			if (txq->tx_skbuff[i]) {
-+				dev_kfree_skb_any(txq->tx_skbuff[i]);
-+				txq->tx_skbuff[i] = NULL;
-+			}
-+			bdp->cbd_bufaddr = 0;
-+			bdp = fec_enet_get_nextdesc(bdp, fep, q);
-+		}
-+
-+		/* Set the last buffer to wrap */
-+		bdp = fec_enet_get_prevdesc(bdp, fep, q);
-+		bdp->cbd_sc |= BD_SC_WRAP;
-+		txq->dirty_tx = bdp;
-+	}
-+}
-+
-+static void fec_enet_active_rxring(struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	int i;
-+
-+	for (i = 0; i < fep->num_rx_queues; i++)
-+		writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
-+}
-+
-+static void fec_enet_enable_ring(struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	struct fec_enet_priv_tx_q *txq;
-+	struct fec_enet_priv_rx_q *rxq;
-+	int i;
-+
-+	for (i = 0; i < fep->num_rx_queues; i++) {
-+		rxq = fep->rx_queue[i];
-+		writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
-+		writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
-+
-+		/* enable DMA1/2 */
-+		if (i)
-+			writel(RCMR_MATCHEN | RCMR_CMP(i),
-+			       fep->hwp + FEC_RCMR(i));
-+	}
-+
-+	for (i = 0; i < fep->num_tx_queues; i++) {
-+		txq = fep->tx_queue[i];
-+		writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
-+
-+		/* enable DMA1/2 */
-+		if (i)
-+			writel(DMA_CLASS_EN | IDLE_SLOPE(i),
-+			       fep->hwp + FEC_DMA_CFG(i));
-+	}
-+}
-+
-+static void fec_enet_reset_skb(struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	struct fec_enet_priv_tx_q *txq;
-+	int i, j;
-+
-+	for (i = 0; i < fep->num_tx_queues; i++) {
-+		txq = fep->tx_queue[i];
-+
-+		for (j = 0; j < txq->tx_ring_size; j++) {
-+			if (txq->tx_skbuff[j]) {
-+				dev_kfree_skb_any(txq->tx_skbuff[j]);
-+				txq->tx_skbuff[j] = NULL;
-+			}
-+		}
-+	}
-+}
-+
-+/*
-+ * This function is called to start or restart the FEC during a link
-+ * change, transmit timeout, or to reconfigure the FEC.  The network
-+ * packet processing for this device must be stopped before this call.
-+ */
-+static void
-+fec_restart(struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	u32 val;
-+	u32 temp_mac[2];
-+	u32 rcntl = OPT_FRAME_SIZE | 0x04;
-+	u32 ecntl = 0x2; /* ETHEREN */
-+
-+	/* Whack a reset.  We should wait for this.
-+	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
-+	 * instead of reset MAC itself.
-+	 */
-+	if (fep->quirks & FEC_QUIRK_HAS_AVB) {
-+		writel(0, fep->hwp + FEC_ECNTRL);
-+	} else {
-+		writel(1, fep->hwp + FEC_ECNTRL);
-+		udelay(10);
-+	}
-+
-+	/*
-+	 * enet-mac reset will reset mac address registers too,
-+	 * so need to reconfigure it.
-+	 */
-+	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
-+		memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
-+		writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
-+		writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
-+	}
-+
-+	/* Clear any outstanding interrupt. */
-+	writel(0xffffffff, fep->hwp + FEC_IEVENT);
-+
-+	fec_enet_bd_init(ndev);
-+
-+	fec_enet_enable_ring(ndev);
-+
-+	/* Reset tx SKB buffers. */
-+	fec_enet_reset_skb(ndev);
-+
-+	/* Enable MII mode */
-+	if (fep->full_duplex == DUPLEX_FULL) {
-+		/* FD enable */
-+		writel(0x04, fep->hwp + FEC_X_CNTRL);
-+	} else {
-+		/* No Rcv on Xmit */
-+		rcntl |= 0x02;
-+		writel(0x0, fep->hwp + FEC_X_CNTRL);
-+	}
-+
-+	/* Set MII speed */
-+	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
-+
-+#if !defined(CONFIG_M5272)
-+	/* set RX checksum */
-+	val = readl(fep->hwp + FEC_RACC);
-+	if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
-+		val |= FEC_RACC_OPTIONS;
-+	else
-+		val &= ~FEC_RACC_OPTIONS;
-+	writel(val, fep->hwp + FEC_RACC);
-+#endif
-+
-+	/*
-+	 * The phy interface and speed need to get configured
-+	 * differently on enet-mac.
-+	 */
-+	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
-+		/* Enable flow control and length check */
-+		rcntl |= 0x40000000 | 0x00000020;
-+
-+		/* RGMII, RMII or MII */
-+		if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
-+		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
-+		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-+		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
-+			rcntl |= (1 << 6);
-+		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
-+			rcntl |= (1 << 8);
-+		else
-+			rcntl &= ~(1 << 8);
-+
-+		/* 1G, 100M or 10M */
-+		if (fep->phy_dev) {
-+			if (fep->phy_dev->speed == SPEED_1000)
-+				ecntl |= (1 << 5);
-+			else if (fep->phy_dev->speed == SPEED_100)
-+				rcntl &= ~(1 << 9);
-+			else
-+				rcntl |= (1 << 9);
-+		}
-+	} else {
-+#ifdef FEC_MIIGSK_ENR
-+		if (fep->quirks & FEC_QUIRK_USE_GASKET) {
-+			u32 cfgr;
-+			/* disable the gasket and wait */
-+			writel(0, fep->hwp + FEC_MIIGSK_ENR);
-+			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
-+				udelay(1);
-+
-+			/*
-+			 * configure the gasket:
-+			 *   RMII, 50 MHz, no loopback, no echo
-+			 *   MII, 25 MHz, no loopback, no echo
-+			 */
-+			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
-+				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
-+			if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
-+				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
-+			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
-+
-+			/* re-enable the gasket */
-+			writel(2, fep->hwp + FEC_MIIGSK_ENR);
-+		}
-+#endif
-+	}
-+
-+#if !defined(CONFIG_M5272)
-+	/* enable pause frame*/
-+	if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
-+	    ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
-+	     fep->phy_dev && fep->phy_dev->pause)) {
-+		rcntl |= FEC_ENET_FCE;
-+
-+		/* set FIFO threshold parameter to reduce overrun */
-+		writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
-+		writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
-+		writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
-+		writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
-+
-+		/* OPD */
-+		writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
-+	} else {
-+		rcntl &= ~FEC_ENET_FCE;
-+	}
-+#endif /* !defined(CONFIG_M5272) */
-+
-+	writel(rcntl, fep->hwp + FEC_R_CNTRL);
-+
-+	/* Setup multicast filter. */
-+	set_multicast_list(ndev);
-+#ifndef CONFIG_M5272
-+	writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
-+	writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
-+#endif
-+
-+	if (fep->quirks & FEC_QUIRK_ENET_MAC) {
-+		/* enable ENET endian swap */
-+		ecntl |= (1 << 8);
-+		/* enable ENET store and forward mode */
-+		writel(1 << 8, fep->hwp + FEC_X_WMRK);
-+	}
-+
-+	if (fep->bufdesc_ex)
-+		ecntl |= (1 << 4);
-+
-+#ifndef CONFIG_M5272
-+	/* Enable the MIB statistic event counters */
-+	writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
-+#endif
-+
-+	/* And last, enable the transmit and receive processing */
-+	writel(ecntl, fep->hwp + FEC_ECNTRL);
-+	fec_enet_active_rxring(ndev);
-+
-+	if (fep->bufdesc_ex)
-+		fec_ptp_start_cyclecounter(ndev);
-+
-+	/* Enable interrupts we wish to service */
-+	if (fep->link)
-+		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
-+	else
-+		writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
-+
-+	/* Init the interrupt coalescing */
-+	fec_enet_itr_coal_init(ndev);
-+
-+}
-+
-+static void
-+fec_stop(struct net_device *ndev)
-+{
-+	struct fec_enet_private *fep = netdev_priv(ndev);
-+	struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
-+	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
-+	u32 val;
-+