linux: update to 4.9.13

1 files changed, 23868 insertions, 0 deletions

diff --git a/target/linux/patches/4.9.13/patch-realtime b/target/linux/patches/4.9.13/patch-realtime
new file mode 100644
index 000000000..abc03f9f5
--- /dev/null
+++ b/target/linux/patches/4.9.13/patch-realtime
@@ -0,0 +1,23868 @@
+diff -Nur linux-4.9.6.orig/arch/arm/include/asm/irq.h linux-4.9.6/arch/arm/include/asm/irq.h
+--- linux-4.9.6.orig/arch/arm/include/asm/irq.h	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/include/asm/irq.h	2017-01-28 13:59:09.887654498 +0100
+@@ -22,6 +22,8 @@
+ #endif
+ 
+ #ifndef __ASSEMBLY__
++#include <linux/cpumask.h>
++
+ struct irqaction;
+ struct pt_regs;
+ extern void migrate_irqs(void);
+diff -Nur linux-4.9.6.orig/arch/arm/include/asm/switch_to.h linux-4.9.6/arch/arm/include/asm/switch_to.h
+--- linux-4.9.6.orig/arch/arm/include/asm/switch_to.h	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/include/asm/switch_to.h	2017-01-28 13:59:09.887654498 +0100
+@@ -3,6 +3,13 @@
+ 
+ #include <linux/thread_info.h>
+ 
++#if defined CONFIG_PREEMPT_RT_FULL && defined CONFIG_HIGHMEM
++void switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p);
++#else
++static inline void
++switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p) { }
++#endif
++
+ /*
+  * For v7 SMP cores running a preemptible kernel we may be pre-empted
+  * during a TLB maintenance operation, so execute an inner-shareable dsb
+@@ -25,6 +32,7 @@
+ #define switch_to(prev,next,last)					\
+ do {									\
+ 	__complete_pending_tlbi();					\
++	switch_kmaps(prev, next);					\
+ 	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
+ } while (0)
+ 
+diff -Nur linux-4.9.6.orig/arch/arm/include/asm/thread_info.h linux-4.9.6/arch/arm/include/asm/thread_info.h
+--- linux-4.9.6.orig/arch/arm/include/asm/thread_info.h	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/include/asm/thread_info.h	2017-01-28 13:59:09.887654498 +0100
+@@ -49,6 +49,7 @@
+ struct thread_info {
+ 	unsigned long		flags;		/* low level flags */
+ 	int			preempt_count;	/* 0 => preemptable, <0 => bug */
++	int			preempt_lazy_count; /* 0 => preemptable, <0 => bug */
+ 	mm_segment_t		addr_limit;	/* address limit */
+ 	struct task_struct	*task;		/* main task structure */
+ 	__u32			cpu;		/* cpu */
+@@ -142,7 +143,8 @@
+ #define TIF_SYSCALL_TRACE	4	/* syscall trace active */
+ #define TIF_SYSCALL_AUDIT	5	/* syscall auditing active */
+ #define TIF_SYSCALL_TRACEPOINT	6	/* syscall tracepoint instrumentation */
+-#define TIF_SECCOMP		7	/* seccomp syscall filtering active */
++#define TIF_SECCOMP		8	/* seccomp syscall filtering active */
++#define TIF_NEED_RESCHED_LAZY	7
+ 
+ #define TIF_NOHZ		12	/* in adaptive nohz mode */
+ #define TIF_USING_IWMMXT	17
+@@ -152,6 +154,7 @@
+ #define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
+ #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
+ #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
++#define _TIF_NEED_RESCHED_LAZY	(1 << TIF_NEED_RESCHED_LAZY)
+ #define _TIF_UPROBE		(1 << TIF_UPROBE)
+ #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
+ #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
+@@ -167,7 +170,8 @@
+  * Change these and you break ASM code in entry-common.S
+  */
+ #define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
+-				 _TIF_NOTIFY_RESUME | _TIF_UPROBE)
++				 _TIF_NOTIFY_RESUME | _TIF_UPROBE | \
++				 _TIF_NEED_RESCHED_LAZY)
+ 
+ #endif /* __KERNEL__ */
+ #endif /* __ASM_ARM_THREAD_INFO_H */
+diff -Nur linux-4.9.6.orig/arch/arm/Kconfig linux-4.9.6/arch/arm/Kconfig
+--- linux-4.9.6.orig/arch/arm/Kconfig	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/Kconfig	2017-01-28 13:59:09.887654498 +0100
+@@ -36,7 +36,7 @@
+ 	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
+ 	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
+ 	select HAVE_ARCH_HARDENED_USERCOPY
+-	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
++	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && !PREEMPT_RT_BASE
+ 	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
+ 	select HAVE_ARCH_MMAP_RND_BITS if MMU
+ 	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
+@@ -75,6 +75,7 @@
+ 	select HAVE_PERF_EVENTS
+ 	select HAVE_PERF_REGS
+ 	select HAVE_PERF_USER_STACK_DUMP
++	select HAVE_PREEMPT_LAZY
+ 	select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
+ 	select HAVE_REGS_AND_STACK_ACCESS_API
+ 	select HAVE_SYSCALL_TRACEPOINTS
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/asm-offsets.c linux-4.9.6/arch/arm/kernel/asm-offsets.c
+--- linux-4.9.6.orig/arch/arm/kernel/asm-offsets.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/asm-offsets.c	2017-01-28 13:59:09.887654498 +0100
+@@ -65,6 +65,7 @@
+   BLANK();
+   DEFINE(TI_FLAGS,		offsetof(struct thread_info, flags));
+   DEFINE(TI_PREEMPT,		offsetof(struct thread_info, preempt_count));
++  DEFINE(TI_PREEMPT_LAZY,	offsetof(struct thread_info, preempt_lazy_count));
+   DEFINE(TI_ADDR_LIMIT,		offsetof(struct thread_info, addr_limit));
+   DEFINE(TI_TASK,		offsetof(struct thread_info, task));
+   DEFINE(TI_CPU,		offsetof(struct thread_info, cpu));
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/entry-armv.S linux-4.9.6/arch/arm/kernel/entry-armv.S
+--- linux-4.9.6.orig/arch/arm/kernel/entry-armv.S	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/entry-armv.S	2017-01-28 13:59:09.887654498 +0100
+@@ -220,11 +220,18 @@
+ 
+ #ifdef CONFIG_PREEMPT
+ 	ldr	r8, [tsk, #TI_PREEMPT]		@ get preempt count
+-	ldr	r0, [tsk, #TI_FLAGS]		@ get flags
+ 	teq	r8, #0				@ if preempt count != 0
++	bne	1f				@ return from exeption
++	ldr	r0, [tsk, #TI_FLAGS]		@ get flags
++	tst	r0, #_TIF_NEED_RESCHED		@ if NEED_RESCHED is set
++	blne	svc_preempt			@ preempt!
++
++	ldr	r8, [tsk, #TI_PREEMPT_LAZY]	@ get preempt lazy count
++	teq	r8, #0				@ if preempt lazy count != 0
+ 	movne	r0, #0				@ force flags to 0
+-	tst	r0, #_TIF_NEED_RESCHED
++	tst	r0, #_TIF_NEED_RESCHED_LAZY
+ 	blne	svc_preempt
++1:
+ #endif
+ 
+ 	svc_exit r5, irq = 1			@ return from exception
+@@ -239,8 +246,14 @@
+ 1:	bl	preempt_schedule_irq		@ irq en/disable is done inside
+ 	ldr	r0, [tsk, #TI_FLAGS]		@ get new tasks TI_FLAGS
+ 	tst	r0, #_TIF_NEED_RESCHED
++	bne	1b
++	tst	r0, #_TIF_NEED_RESCHED_LAZY
+ 	reteq	r8				@ go again
+-	b	1b
++	ldr	r0, [tsk, #TI_PREEMPT_LAZY]	@ get preempt lazy count
++	teq	r0, #0				@ if preempt lazy count != 0
++	beq	1b
++	ret	r8				@ go again
++
+ #endif
+ 
+ __und_fault:
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/entry-common.S linux-4.9.6/arch/arm/kernel/entry-common.S
+--- linux-4.9.6.orig/arch/arm/kernel/entry-common.S	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/entry-common.S	2017-01-28 13:59:09.887654498 +0100
+@@ -36,7 +36,9 @@
+  UNWIND(.cantunwind	)
+ 	disable_irq_notrace			@ disable interrupts
+ 	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
+-	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
++	tst	r1, #((_TIF_SYSCALL_WORK | _TIF_WORK_MASK) & ~_TIF_SECCOMP)
++	bne	fast_work_pending
++	tst	r1, #_TIF_SECCOMP
+ 	bne	fast_work_pending
+ 
+ 	/* perform architecture specific actions before user return */
+@@ -62,8 +64,11 @@
+ 	str	r0, [sp, #S_R0 + S_OFF]!	@ save returned r0
+ 	disable_irq_notrace			@ disable interrupts
+ 	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
+-	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
++	tst	r1, #((_TIF_SYSCALL_WORK | _TIF_WORK_MASK) & ~_TIF_SECCOMP)
++	bne 	do_slower_path
++	tst	r1, #_TIF_SECCOMP
+ 	beq	no_work_pending
++do_slower_path:
+  UNWIND(.fnend		)
+ ENDPROC(ret_fast_syscall)
+ 
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/patch.c linux-4.9.6/arch/arm/kernel/patch.c
+--- linux-4.9.6.orig/arch/arm/kernel/patch.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/patch.c	2017-01-28 13:59:09.895654805 +0100
+@@ -15,7 +15,7 @@
+ 	unsigned int insn;
+ };
+ 
+-static DEFINE_SPINLOCK(patch_lock);
++static DEFINE_RAW_SPINLOCK(patch_lock);
+ 
+ static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
+ 	__acquires(&patch_lock)
+@@ -32,7 +32,7 @@
+ 		return addr;
+ 
+ 	if (flags)
+-		spin_lock_irqsave(&patch_lock, *flags);
++		raw_spin_lock_irqsave(&patch_lock, *flags);
+ 	else
+ 		__acquire(&patch_lock);
+ 
+@@ -47,7 +47,7 @@
+ 	clear_fixmap(fixmap);
+ 
+ 	if (flags)
+-		spin_unlock_irqrestore(&patch_lock, *flags);
++		raw_spin_unlock_irqrestore(&patch_lock, *flags);
+ 	else
+ 		__release(&patch_lock);
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/process.c linux-4.9.6/arch/arm/kernel/process.c
+--- linux-4.9.6.orig/arch/arm/kernel/process.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/process.c	2017-01-28 13:59:09.895654805 +0100
+@@ -322,6 +322,30 @@
+ }
+ 
+ #ifdef CONFIG_MMU
++/*
++ * CONFIG_SPLIT_PTLOCK_CPUS results in a page->ptl lock.  If the lock is not
++ * initialized by pgtable_page_ctor() then a coredump of the vector page will
++ * fail.
++ */
++static int __init vectors_user_mapping_init_page(void)
++{
++	struct page *page;
++	unsigned long addr = 0xffff0000;
++	pgd_t *pgd;
++	pud_t *pud;
++	pmd_t *pmd;
++
++	pgd = pgd_offset_k(addr);
++	pud = pud_offset(pgd, addr);
++	pmd = pmd_offset(pud, addr);
++	page = pmd_page(*(pmd));
++
++	pgtable_page_ctor(page);
++
++	return 0;
++}
++late_initcall(vectors_user_mapping_init_page);
++
+ #ifdef CONFIG_KUSER_HELPERS
+ /*
+  * The vectors page is always readable from user space for the
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/signal.c linux-4.9.6/arch/arm/kernel/signal.c
+--- linux-4.9.6.orig/arch/arm/kernel/signal.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/signal.c	2017-01-28 13:59:09.895654805 +0100
+@@ -572,7 +572,8 @@
+ 	 */
+ 	trace_hardirqs_off();
+ 	do {
+-		if (likely(thread_flags & _TIF_NEED_RESCHED)) {
++		if (likely(thread_flags & (_TIF_NEED_RESCHED |
++					   _TIF_NEED_RESCHED_LAZY))) {
+ 			schedule();
+ 		} else {
+ 			if (unlikely(!user_mode(regs)))
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/smp.c linux-4.9.6/arch/arm/kernel/smp.c
+--- linux-4.9.6.orig/arch/arm/kernel/smp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/smp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -234,8 +234,6 @@
+ 	flush_cache_louis();
+ 	local_flush_tlb_all();
+ 
+-	clear_tasks_mm_cpumask(cpu);
+-
+ 	return 0;
+ }
+ 
+@@ -251,6 +249,9 @@
+ 		pr_err("CPU%u: cpu didn't die\n", cpu);
+ 		return;
+ 	}
++
++	clear_tasks_mm_cpumask(cpu);
++
+ 	pr_notice("CPU%u: shutdown\n", cpu);
+ 
+ 	/*
+diff -Nur linux-4.9.6.orig/arch/arm/kernel/unwind.c linux-4.9.6/arch/arm/kernel/unwind.c
+--- linux-4.9.6.orig/arch/arm/kernel/unwind.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kernel/unwind.c	2017-01-28 13:59:09.895654805 +0100
+@@ -93,7 +93,7 @@
+ static const struct unwind_idx *__origin_unwind_idx;
+ extern const struct unwind_idx __stop_unwind_idx[];
+ 
+-static DEFINE_SPINLOCK(unwind_lock);
++static DEFINE_RAW_SPINLOCK(unwind_lock);
+ static LIST_HEAD(unwind_tables);
+ 
+ /* Convert a prel31 symbol to an absolute address */
+@@ -201,7 +201,7 @@
+ 		/* module unwind tables */
+ 		struct unwind_table *table;
+ 
+-		spin_lock_irqsave(&unwind_lock, flags);
++		raw_spin_lock_irqsave(&unwind_lock, flags);
+ 		list_for_each_entry(table, &unwind_tables, list) {
+ 			if (addr >= table->begin_addr &&
+ 			    addr < table->end_addr) {
+@@ -213,7 +213,7 @@
+ 				break;
+ 			}
+ 		}
+-		spin_unlock_irqrestore(&unwind_lock, flags);
++		raw_spin_unlock_irqrestore(&unwind_lock, flags);
+ 	}
+ 
+ 	pr_debug("%s: idx = %p\n", __func__, idx);
+@@ -529,9 +529,9 @@
+ 	tab->begin_addr = text_addr;
+ 	tab->end_addr = text_addr + text_size;
+ 
+-	spin_lock_irqsave(&unwind_lock, flags);
++	raw_spin_lock_irqsave(&unwind_lock, flags);
+ 	list_add_tail(&tab->list, &unwind_tables);
+-	spin_unlock_irqrestore(&unwind_lock, flags);
++	raw_spin_unlock_irqrestore(&unwind_lock, flags);
+ 
+ 	return tab;
+ }
+@@ -543,9 +543,9 @@
+ 	if (!tab)
+ 		return;
+ 
+-	spin_lock_irqsave(&unwind_lock, flags);
++	raw_spin_lock_irqsave(&unwind_lock, flags);
+ 	list_del(&tab->list);
+-	spin_unlock_irqrestore(&unwind_lock, flags);
++	raw_spin_unlock_irqrestore(&unwind_lock, flags);
+ 
+ 	kfree(tab);
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/kvm/arm.c linux-4.9.6/arch/arm/kvm/arm.c
+--- linux-4.9.6.orig/arch/arm/kvm/arm.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/kvm/arm.c	2017-01-28 13:59:09.895654805 +0100
+@@ -619,7 +619,7 @@
+ 		 * involves poking the GIC, which must be done in a
+ 		 * non-preemptible context.
+ 		 */
+-		preempt_disable();
++		migrate_disable();
+ 		kvm_pmu_flush_hwstate(vcpu);
+ 		kvm_timer_flush_hwstate(vcpu);
+ 		kvm_vgic_flush_hwstate(vcpu);
+@@ -640,7 +640,7 @@
+ 			kvm_pmu_sync_hwstate(vcpu);
+ 			kvm_timer_sync_hwstate(vcpu);
+ 			kvm_vgic_sync_hwstate(vcpu);
+-			preempt_enable();
++			migrate_enable();
+ 			continue;
+ 		}
+ 
+@@ -696,7 +696,7 @@
+ 
+ 		kvm_vgic_sync_hwstate(vcpu);
+ 
+-		preempt_enable();
++		migrate_enable();
+ 
+ 		ret = handle_exit(vcpu, run, ret);
+ 	}
+diff -Nur linux-4.9.6.orig/arch/arm/mach-exynos/platsmp.c linux-4.9.6/arch/arm/mach-exynos/platsmp.c
+--- linux-4.9.6.orig/arch/arm/mach-exynos/platsmp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-exynos/platsmp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -229,7 +229,7 @@
+ 	return (void __iomem *)(S5P_VA_SCU);
+ }
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ static void exynos_secondary_init(unsigned int cpu)
+ {
+@@ -242,8 +242,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
+@@ -307,7 +307,7 @@
+ 	 * Set synchronisation state between this boot processor
+ 	 * and the secondary one
+ 	 */
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * The secondary processor is waiting to be released from
+@@ -334,7 +334,7 @@
+ 
+ 		if (timeout == 0) {
+ 			printk(KERN_ERR "cpu1 power enable failed");
+-			spin_unlock(&boot_lock);
++			raw_spin_unlock(&boot_lock);
+ 			return -ETIMEDOUT;
+ 		}
+ 	}
+@@ -380,7 +380,7 @@
+ 	 * calibrations, then wait for it to finish
+ 	 */
+ fail:
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return pen_release != -1 ? ret : 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mach-hisi/platmcpm.c linux-4.9.6/arch/arm/mach-hisi/platmcpm.c
+--- linux-4.9.6.orig/arch/arm/mach-hisi/platmcpm.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-hisi/platmcpm.c	2017-01-28 13:59:09.895654805 +0100
+@@ -61,7 +61,7 @@
+ 
+ static void __iomem *sysctrl, *fabric;
+ static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ static u32 fabric_phys_addr;
+ /*
+  * [0]: bootwrapper physical address
+@@ -113,7 +113,7 @@
+ 	if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
+ 		return -EINVAL;
+ 
+-	spin_lock_irq(&boot_lock);
++	raw_spin_lock_irq(&boot_lock);
+ 
+ 	if (hip04_cpu_table[cluster][cpu])
+ 		goto out;
+@@ -147,7 +147,7 @@
+ 
+ out:
+ 	hip04_cpu_table[cluster][cpu]++;
+-	spin_unlock_irq(&boot_lock);
++	raw_spin_unlock_irq(&boot_lock);
+ 
+ 	return 0;
+ }
+@@ -162,11 +162,11 @@
+ 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+ 
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 	hip04_cpu_table[cluster][cpu]--;
+ 	if (hip04_cpu_table[cluster][cpu] == 1) {
+ 		/* A power_up request went ahead of us. */
+-		spin_unlock(&boot_lock);
++		raw_spin_unlock(&boot_lock);
+ 		return;
+ 	} else if (hip04_cpu_table[cluster][cpu] > 1) {
+ 		pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
+@@ -174,7 +174,7 @@
+ 	}
+ 
+ 	last_man = hip04_cluster_is_down(cluster);
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 	if (last_man) {
+ 		/* Since it's Cortex A15, disable L2 prefetching. */
+ 		asm volatile(
+@@ -203,7 +203,7 @@
+ 	       cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
+ 
+ 	count = TIMEOUT_MSEC / POLL_MSEC;
+-	spin_lock_irq(&boot_lock);
++	raw_spin_lock_irq(&boot_lock);
+ 	for (tries = 0; tries < count; tries++) {
+ 		if (hip04_cpu_table[cluster][cpu])
+ 			goto err;
+@@ -211,10 +211,10 @@
+ 		data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
+ 		if (data & CORE_WFI_STATUS(cpu))
+ 			break;
+-		spin_unlock_irq(&boot_lock);
++		raw_spin_unlock_irq(&boot_lock);
+ 		/* Wait for clean L2 when the whole cluster is down. */
+ 		msleep(POLL_MSEC);
+-		spin_lock_irq(&boot_lock);
++		raw_spin_lock_irq(&boot_lock);
+ 	}
+ 	if (tries >= count)
+ 		goto err;
+@@ -231,10 +231,10 @@
+ 		goto err;
+ 	if (hip04_cluster_is_down(cluster))
+ 		hip04_set_snoop_filter(cluster, 0);
+-	spin_unlock_irq(&boot_lock);
++	raw_spin_unlock_irq(&boot_lock);
+ 	return 1;
+ err:
+-	spin_unlock_irq(&boot_lock);
++	raw_spin_unlock_irq(&boot_lock);
+ 	return 0;
+ }
+ #endif
+diff -Nur linux-4.9.6.orig/arch/arm/mach-omap2/omap-smp.c linux-4.9.6/arch/arm/mach-omap2/omap-smp.c
+--- linux-4.9.6.orig/arch/arm/mach-omap2/omap-smp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-omap2/omap-smp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -64,7 +64,7 @@
+ 	.startup_addr = omap5_secondary_startup,
+ };
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ void __iomem *omap4_get_scu_base(void)
+ {
+@@ -131,8 +131,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
+@@ -146,7 +146,7 @@
+ 	 * Set synchronisation state between this boot processor
+ 	 * and the secondary one
+ 	 */
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * Update the AuxCoreBoot0 with boot state for secondary core.
+@@ -223,7 +223,7 @@
+ 	 * Now the secondary core is starting up let it run its
+ 	 * calibrations, then wait for it to finish
+ 	 */
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mach-prima2/platsmp.c linux-4.9.6/arch/arm/mach-prima2/platsmp.c
+--- linux-4.9.6.orig/arch/arm/mach-prima2/platsmp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-prima2/platsmp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -22,7 +22,7 @@
+ 
+ static void __iomem *clk_base;
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ static void sirfsoc_secondary_init(unsigned int cpu)
+ {
+@@ -36,8 +36,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ static const struct of_device_id clk_ids[]  = {
+@@ -75,7 +75,7 @@
+ 	/* make sure write buffer is drained */
+ 	mb();
+ 
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * The secondary processor is waiting to be released from
+@@ -107,7 +107,7 @@
+ 	 * now the secondary core is starting up let it run its
+ 	 * calibrations, then wait for it to finish
+ 	 */
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return pen_release != -1 ? -ENOSYS : 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mach-qcom/platsmp.c linux-4.9.6/arch/arm/mach-qcom/platsmp.c
+--- linux-4.9.6.orig/arch/arm/mach-qcom/platsmp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-qcom/platsmp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -46,7 +46,7 @@
+ 
+ extern void secondary_startup_arm(void);
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ #ifdef CONFIG_HOTPLUG_CPU
+ static void qcom_cpu_die(unsigned int cpu)
+@@ -60,8 +60,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ static int scss_release_secondary(unsigned int cpu)
+@@ -284,7 +284,7 @@
+ 	 * set synchronisation state between this boot processor
+ 	 * and the secondary one
+ 	 */
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * Send the secondary CPU a soft interrupt, thereby causing
+@@ -297,7 +297,7 @@
+ 	 * now the secondary core is starting up let it run its
+ 	 * calibrations, then wait for it to finish
+ 	 */
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return ret;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mach-spear/platsmp.c linux-4.9.6/arch/arm/mach-spear/platsmp.c
+--- linux-4.9.6.orig/arch/arm/mach-spear/platsmp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-spear/platsmp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -32,7 +32,7 @@
+ 	sync_cache_w(&pen_release);
+ }
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
+ 
+@@ -47,8 +47,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
+@@ -59,7 +59,7 @@
+ 	 * set synchronisation state between this boot processor
+ 	 * and the secondary one
+ 	 */
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * The secondary processor is waiting to be released from
+@@ -84,7 +84,7 @@
+ 	 * now the secondary core is starting up let it run its
+ 	 * calibrations, then wait for it to finish
+ 	 */
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return pen_release != -1 ? -ENOSYS : 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mach-sti/platsmp.c linux-4.9.6/arch/arm/mach-sti/platsmp.c
+--- linux-4.9.6.orig/arch/arm/mach-sti/platsmp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mach-sti/platsmp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -35,7 +35,7 @@
+ 	sync_cache_w(&pen_release);
+ }
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ static void sti_secondary_init(unsigned int cpu)
+ {
+@@ -48,8 +48,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
+@@ -60,7 +60,7 @@
+ 	 * set synchronisation state between this boot processor
+ 	 * and the secondary one
+ 	 */
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * The secondary processor is waiting to be released from
+@@ -91,7 +91,7 @@
+ 	 * now the secondary core is starting up let it run its
+ 	 * calibrations, then wait for it to finish
+ 	 */
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return pen_release != -1 ? -ENOSYS : 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mm/fault.c linux-4.9.6/arch/arm/mm/fault.c
+--- linux-4.9.6.orig/arch/arm/mm/fault.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mm/fault.c	2017-01-28 13:59:09.895654805 +0100
+@@ -430,6 +430,9 @@
+ 	if (addr < TASK_SIZE)
+ 		return do_page_fault(addr, fsr, regs);
+ 
++	if (interrupts_enabled(regs))
++		local_irq_enable();
++
+ 	if (user_mode(regs))
+ 		goto bad_area;
+ 
+@@ -497,6 +500,9 @@
+ static int
+ do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+ {
++	if (interrupts_enabled(regs))
++		local_irq_enable();
++
+ 	do_bad_area(addr, fsr, regs);
+ 	return 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm/mm/highmem.c linux-4.9.6/arch/arm/mm/highmem.c
+--- linux-4.9.6.orig/arch/arm/mm/highmem.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/mm/highmem.c	2017-01-28 13:59:09.895654805 +0100
+@@ -34,6 +34,11 @@
+ 	return *ptep;
+ }
+ 
++static unsigned int fixmap_idx(int type)
++{
++	return FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id();
++}
++
+ void *kmap(struct page *page)
+ {
+ 	might_sleep();
+@@ -54,12 +59,13 @@
+ 
+ void *kmap_atomic(struct page *page)
+ {
++	pte_t pte = mk_pte(page, kmap_prot);
+ 	unsigned int idx;
+ 	unsigned long vaddr;
+ 	void *kmap;
+ 	int type;
+ 
+-	preempt_disable();
++	preempt_disable_nort();
+ 	pagefault_disable();
+ 	if (!PageHighMem(page))
+ 		return page_address(page);
+@@ -79,7 +85,7 @@
+ 
+ 	type = kmap_atomic_idx_push();
+ 
+-	idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id();
++	idx = fixmap_idx(type);
+ 	vaddr = __fix_to_virt(idx);
+ #ifdef CONFIG_DEBUG_HIGHMEM
+ 	/*
+@@ -93,7 +99,10 @@
+ 	 * in place, so the contained TLB flush ensures the TLB is updated
+ 	 * with the new mapping.
+ 	 */
+-	set_fixmap_pte(idx, mk_pte(page, kmap_prot));
++#ifdef CONFIG_PREEMPT_RT_FULL
++	current->kmap_pte[type] = pte;
++#endif
++	set_fixmap_pte(idx, pte);
+ 
+ 	return (void *)vaddr;
+ }
+@@ -106,44 +115,75 @@
+ 
+ 	if (kvaddr >= (void *)FIXADDR_START) {
+ 		type = kmap_atomic_idx();
+-		idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id();
++		idx = fixmap_idx(type);
+ 
+ 		if (cache_is_vivt())
+ 			__cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
++#ifdef CONFIG_PREEMPT_RT_FULL
++		current->kmap_pte[type] = __pte(0);
++#endif
+ #ifdef CONFIG_DEBUG_HIGHMEM
+ 		BUG_ON(vaddr != __fix_to_virt(idx));
+-		set_fixmap_pte(idx, __pte(0));
+ #else
+ 		(void) idx;  /* to kill a warning */
+ #endif
++		set_fixmap_pte(idx, __pte(0));
+ 		kmap_atomic_idx_pop();
+ 	} else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) {
+ 		/* this address was obtained through kmap_high_get() */
+ 		kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)]));
+ 	}
+ 	pagefault_enable();
+-	preempt_enable();
++	preempt_enable_nort();
+ }
+ EXPORT_SYMBOL(__kunmap_atomic);
+ 
+ void *kmap_atomic_pfn(unsigned long pfn)
+ {
++	pte_t pte = pfn_pte(pfn, kmap_prot);
+ 	unsigned long vaddr;
+ 	int idx, type;
+ 	struct page *page = pfn_to_page(pfn);
+ 
+-	preempt_disable();
++	preempt_disable_nort();
+ 	pagefault_disable();
+ 	if (!PageHighMem(page))
+ 		return page_address(page);
+ 
+ 	type = kmap_atomic_idx_push();
+-	idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id();
++	idx = fixmap_idx(type);
+ 	vaddr = __fix_to_virt(idx);
+ #ifdef CONFIG_DEBUG_HIGHMEM
+ 	BUG_ON(!pte_none(get_fixmap_pte(vaddr)));
+ #endif
+-	set_fixmap_pte(idx, pfn_pte(pfn, kmap_prot));
++#ifdef CONFIG_PREEMPT_RT_FULL
++	current->kmap_pte[type] = pte;
++#endif
++	set_fixmap_pte(idx, pte);
+ 
+ 	return (void *)vaddr;
+ }
++#if defined CONFIG_PREEMPT_RT_FULL
++void switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p)
++{
++	int i;
++
++	/*
++	 * Clear @prev's kmap_atomic mappings
++	 */
++	for (i = 0; i < prev_p->kmap_idx; i++) {
++		int idx = fixmap_idx(i);
++
++		set_fixmap_pte(idx, __pte(0));
++	}
++	/*
++	 * Restore @next_p's kmap_atomic mappings
++	 */
++	for (i = 0; i < next_p->kmap_idx; i++) {
++		int idx = fixmap_idx(i);
++
++		if (!pte_none(next_p->kmap_pte[i]))
++			set_fixmap_pte(idx, next_p->kmap_pte[i]);
++	}
++}
++#endif
+diff -Nur linux-4.9.6.orig/arch/arm/plat-versatile/platsmp.c linux-4.9.6/arch/arm/plat-versatile/platsmp.c
+--- linux-4.9.6.orig/arch/arm/plat-versatile/platsmp.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm/plat-versatile/platsmp.c	2017-01-28 13:59:09.895654805 +0100
+@@ -32,7 +32,7 @@
+ 	sync_cache_w(&pen_release);
+ }
+ 
+-static DEFINE_SPINLOCK(boot_lock);
++static DEFINE_RAW_SPINLOCK(boot_lock);
+ 
+ void versatile_secondary_init(unsigned int cpu)
+ {
+@@ -45,8 +45,8 @@
+ 	/*
+ 	 * Synchronise with the boot thread.
+ 	 */
+-	spin_lock(&boot_lock);
+-	spin_unlock(&boot_lock);
++	raw_spin_lock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ }
+ 
+ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
+@@ -57,7 +57,7 @@
+ 	 * Set synchronisation state between this boot processor
+ 	 * and the secondary one
+ 	 */
+-	spin_lock(&boot_lock);
++	raw_spin_lock(&boot_lock);
+ 
+ 	/*
+ 	 * This is really belt and braces; we hold unintended secondary
+@@ -87,7 +87,7 @@
+ 	 * now the secondary core is starting up let it run its
+ 	 * calibrations, then wait for it to finish
+ 	 */
+-	spin_unlock(&boot_lock);
++	raw_spin_unlock(&boot_lock);
+ 
+ 	return pen_release != -1 ? -ENOSYS : 0;
+ }
+diff -Nur linux-4.9.6.orig/arch/arm64/include/asm/thread_info.h linux-4.9.6/arch/arm64/include/asm/thread_info.h
+--- linux-4.9.6.orig/arch/arm64/include/asm/thread_info.h	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm64/include/asm/thread_info.h	2017-01-28 13:59:09.895654805 +0100
+@@ -49,6 +49,7 @@
+ 	mm_segment_t		addr_limit;	/* address limit */
+ 	struct task_struct	*task;		/* main task structure */
+ 	int			preempt_count;	/* 0 => preemptable, <0 => bug */
++	int			preempt_lazy_count; /* 0 => preemptable, <0 => bug */
+ 	int			cpu;		/* cpu */
+ };
+ 
+@@ -112,6 +113,7 @@
+ #define TIF_NEED_RESCHED	1
+ #define TIF_NOTIFY_RESUME	2	/* callback before returning to user */
+ #define TIF_FOREIGN_FPSTATE	3	/* CPU's FP state is not current's */
++#define TIF_NEED_RESCHED_LAZY	4
+ #define TIF_NOHZ		7
+ #define TIF_SYSCALL_TRACE	8
+ #define TIF_SYSCALL_AUDIT	9
+@@ -127,6 +129,7 @@
+ #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
+ #define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
+ #define _TIF_FOREIGN_FPSTATE	(1 << TIF_FOREIGN_FPSTATE)
++#define _TIF_NEED_RESCHED_LAZY	(1 << TIF_NEED_RESCHED_LAZY)
+ #define _TIF_NOHZ		(1 << TIF_NOHZ)
+ #define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
+ #define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)
+@@ -135,7 +138,9 @@
+ #define _TIF_32BIT		(1 << TIF_32BIT)
+ 
+ #define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
+-				 _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE)
++				 _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \
++				 _TIF_NEED_RESCHED_LAZY)
++#define _TIF_NEED_RESCHED_MASK	(_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY)
+ 
+ #define _TIF_SYSCALL_WORK	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
+ 				 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \
+diff -Nur linux-4.9.6.orig/arch/arm64/Kconfig linux-4.9.6/arch/arm64/Kconfig
+--- linux-4.9.6.orig/arch/arm64/Kconfig	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm64/Kconfig	2017-01-28 13:59:09.895654805 +0100
+@@ -91,6 +91,7 @@
+ 	select HAVE_PERF_EVENTS
+ 	select HAVE_PERF_REGS
+ 	select HAVE_PERF_USER_STACK_DUMP
++	select HAVE_PREEMPT_LAZY
+ 	select HAVE_REGS_AND_STACK_ACCESS_API
+ 	select HAVE_RCU_TABLE_FREE
+ 	select HAVE_SYSCALL_TRACEPOINTS
+@@ -694,7 +695,7 @@
+ 
+ config XEN
+ 	bool "Xen guest support on ARM64"
+-	depends on ARM64 && OF
++	depends on ARM64 && OF && !PREEMPT_RT_FULL
+ 	select SWIOTLB_XEN
+ 	select PARAVIRT
+ 	help
+diff -Nur linux-4.9.6.orig/arch/arm64/kernel/asm-offsets.c linux-4.9.6/arch/arm64/kernel/asm-offsets.c
+--- linux-4.9.6.orig/arch/arm64/kernel/asm-offsets.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm64/kernel/asm-offsets.c	2017-01-28 13:59:09.895654805 +0100
+@@ -38,6 +38,7 @@
+   BLANK();
+   DEFINE(TI_FLAGS,		offsetof(struct thread_info, flags));
+   DEFINE(TI_PREEMPT,		offsetof(struct thread_info, preempt_count));
++  DEFINE(TI_PREEMPT_LAZY,	offsetof(struct thread_info, preempt_lazy_count));
+   DEFINE(TI_ADDR_LIMIT,		offsetof(struct thread_info, addr_limit));
+   DEFINE(TI_TASK,		offsetof(struct thread_info, task));
+   DEFINE(TI_CPU,		offsetof(struct thread_info, cpu));
+diff -Nur linux-4.9.6.orig/arch/arm64/kernel/entry.S linux-4.9.6/arch/arm64/kernel/entry.S
+--- linux-4.9.6.orig/arch/arm64/kernel/entry.S	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm64/kernel/entry.S	2017-01-28 13:59:09.895654805 +0100
+@@ -428,11 +428,16 @@
+ 
+ #ifdef CONFIG_PREEMPT
+ 	ldr	w24, [tsk, #TI_PREEMPT]		// get preempt count
+-	cbnz	w24, 1f				// preempt count != 0
++	cbnz	w24, 2f				// preempt count != 0
+ 	ldr	x0, [tsk, #TI_FLAGS]		// get flags
+-	tbz	x0, #TIF_NEED_RESCHED, 1f	// needs rescheduling?
+-	bl	el1_preempt
++	tbnz	x0, #TIF_NEED_RESCHED, 1f	// needs rescheduling?
++
++	ldr	w24, [tsk, #TI_PREEMPT_LAZY]	// get preempt lazy count
++	cbnz	w24, 2f				// preempt lazy count != 0
++	tbz	x0, #TIF_NEED_RESCHED_LAZY, 2f	// needs rescheduling?
+ 1:
++	bl	el1_preempt
++2:
+ #endif
+ #ifdef CONFIG_TRACE_IRQFLAGS
+ 	bl	trace_hardirqs_on
+@@ -446,6 +451,7 @@
+ 1:	bl	preempt_schedule_irq		// irq en/disable is done inside
+ 	ldr	x0, [tsk, #TI_FLAGS]		// get new tasks TI_FLAGS
+ 	tbnz	x0, #TIF_NEED_RESCHED, 1b	// needs rescheduling?
++	tbnz	x0, #TIF_NEED_RESCHED_LAZY, 1b	// needs rescheduling?
+ 	ret	x24
+ #endif
+ 
+diff -Nur linux-4.9.6.orig/arch/arm64/kernel/signal.c linux-4.9.6/arch/arm64/kernel/signal.c
+--- linux-4.9.6.orig/arch/arm64/kernel/signal.c	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/arm64/kernel/signal.c	2017-01-28 13:59:09.895654805 +0100
+@@ -409,7 +409,7 @@
+ 	 */
+ 	trace_hardirqs_off();
+ 	do {
+-		if (thread_flags & _TIF_NEED_RESCHED) {
++		if (thread_flags & _TIF_NEED_RESCHED_MASK) {
+ 			schedule();
+ 		} else {
+ 			local_irq_enable();
+diff -Nur linux-4.9.6.orig/arch/Kconfig linux-4.9.6/arch/Kconfig
+--- linux-4.9.6.orig/arch/Kconfig	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/Kconfig	2017-01-28 13:59:09.887654498 +0100
+@@ -9,6 +9,7 @@
+ 	tristate "OProfile system profiling"
+ 	depends on PROFILING
+ 	depends on HAVE_OPROFILE
++	depends on !PREEMPT_RT_FULL
+ 	select RING_BUFFER
+ 	select RING_BUFFER_ALLOW_SWAP
+ 	help
+@@ -52,6 +53,7 @@
+ config JUMP_LABEL
+        bool "Optimize very unlikely/likely branches"
+        depends on HAVE_ARCH_JUMP_LABEL
++       depends on (!INTERRUPT_OFF_HIST && !PREEMPT_OFF_HIST && !WAKEUP_LATENCY_HIST && !MISSED_TIMER_OFFSETS_HIST)
+        help
+          This option enables a transparent branch optimization that
+ 	 makes certain almost-always-true or almost-always-false branch
+diff -Nur linux-4.9.6.orig/arch/mips/Kconfig linux-4.9.6/arch/mips/Kconfig
+--- linux-4.9.6.orig/arch/mips/Kconfig	2017-01-26 08:25:24.000000000 +0100
++++ linux-4.9.6/arch/mips/Kconfig	2017-01-28 13:59:09.895654805 +0100
+@@ -2514,7 +2514,7 @@
+ #
+ config HIGHMEM
+ 	bool "High Memory Support"
+-	depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
++	depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA && !PREEMPT_RT_FULL
+ 
+ config CPU_SUPPORTS_HIGHMEM
+ 	bool