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authorWaldemar Brodkorb <wbx@openadk.org>2015-09-01 22:25:19 +0200
committerWaldemar Brodkorb <wbx@openadk.org>2015-09-01 22:26:50 +0200
commit77dcf4f883cd9ee840e7d431ed982fa982a60405 (patch)
tree36a8d3f098d3271d632157e98898d7fd201bca65 /target/arm/bcm28xx
parent6a8a13075e6dd6ff646fca3dd1c5dae0ed88c41f (diff)
rpi2: unbreak bootop with 4.1.x kernel
Add missing kernel symbols. NOL2CACHE and *BSG to allow bootup. Remove support patches for older kernels. Enable REGMAP by default.
Diffstat (limited to 'target/arm/bcm28xx')
-rw-r--r--target/arm/bcm28xx/patches/3.12.44/0000-raspberry-pi.patch126864
-rw-r--r--target/arm/bcm28xx/patches/3.12.44/0001-rpi-proto-driver.patch235
-rw-r--r--target/arm/bcm28xx/patches/3.18.16/0000-raspberry-pi.patch139856
-rw-r--r--target/arm/bcm28xx/patches/3.18.16/0001-i2s-allow-to-enable-ALSA-MMAP.patch54
4 files changed, 0 insertions, 267009 deletions
diff --git a/target/arm/bcm28xx/patches/3.12.44/0000-raspberry-pi.patch b/target/arm/bcm28xx/patches/3.12.44/0000-raspberry-pi.patch
deleted file mode 100644
index 4da1e179f..000000000
--- a/target/arm/bcm28xx/patches/3.12.44/0000-raspberry-pi.patch
+++ /dev/null
@@ -1,126864 +0,0 @@
-diff -Nur linux-3.12.38/arch/arm/boot/dts/imx25.dtsi linux-rpi/arch/arm/boot/dts/imx25.dtsi
---- linux-3.12.38/arch/arm/boot/dts/imx25.dtsi 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/boot/dts/imx25.dtsi 2015-03-10 17:26:49.674216697 +0100
-@@ -158,7 +158,7 @@
- #size-cells = <0>;
- compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
- reg = <0x43fa4000 0x4000>;
-- clocks = <&clks 78>, <&clks 78>;
-+ clocks = <&clks 62>, <&clks 62>;
- clock-names = "ipg", "per";
- interrupts = <14>;
- status = "disabled";
-@@ -352,7 +352,7 @@
- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
- reg = <0x53fa0000 0x4000>;
-- clocks = <&clks 106>, <&clks 52>;
-+ clocks = <&clks 106>, <&clks 36>;
- clock-names = "ipg", "per";
- interrupts = <36>;
- };
-@@ -371,7 +371,7 @@
- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
- reg = <0x53fa8000 0x4000>;
-- clocks = <&clks 107>, <&clks 52>;
-+ clocks = <&clks 107>, <&clks 36>;
- clock-names = "ipg", "per";
- interrupts = <41>;
- };
-@@ -412,7 +412,7 @@
- pwm4: pwm@53fc8000 {
- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- reg = <0x53fc8000 0x4000>;
-- clocks = <&clks 108>, <&clks 52>;
-+ clocks = <&clks 108>, <&clks 36>;
- clock-names = "ipg", "per";
- interrupts = <42>;
- };
-@@ -458,7 +458,7 @@
- compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
- reg = <0x53fe0000 0x4000>;
-- clocks = <&clks 105>, <&clks 52>;
-+ clocks = <&clks 105>, <&clks 36>;
- clock-names = "ipg", "per";
- interrupts = <26>;
- };
-diff -Nur linux-3.12.38/arch/arm/boot/dts/Makefile.orig linux-rpi/arch/arm/boot/dts/Makefile.orig
---- linux-3.12.38/arch/arm/boot/dts/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/boot/dts/Makefile.orig 2015-03-09 10:39:28.450893747 +0100
-@@ -0,0 +1,573 @@
-+ifeq ($(CONFIG_OF),y)
-+
-+# Keep at91 dtb files sorted alphabetically for each SoC
-+# rm9200
-+dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb
-+# sam9260
-+dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91-qil_a9260.dtb
-+dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
-+dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
-+dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
-+dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
-+dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
-+# sam9261
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9261ek.dtb
-+# sam9263
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
-+dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
-+# sam9g20
-+dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
-+dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
-+dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
-+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
-+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
-+# sam9g45
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
-+# sam9n12
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
-+# sam9rl
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9rlek.dtb
-+# sam9x5
-+dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
-+# sama5d3
-+dtb-$(CONFIG_ARCH_AT91) += at91-sama5d3_xplained.dtb
-+dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
-+dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
-+# sama5d4
-+dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
-+
-+dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
-+dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
-+
-+# Raspberry Pi
-+ifeq ($(CONFIG_BCM2708_DT),y)
-+ RPI_DT_OVERLAYS=y
-+endif
-+ifeq ($(CONFIG_BCM2709_DT),y)
-+ RPI_DT_OVERLAYS=y
-+endif
-+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb
-+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb
-+dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb
-+dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += ds1307-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += i2c-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-digi-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hy28a-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hy28b-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pcf2127-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pcf8523-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb
-+dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
-+
-+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
-+dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
-+dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
-+ bcm21664-garnet.dtb
-+dtb-$(CONFIG_ARCH_BERLIN) += \
-+ berlin2-sony-nsz-gs7.dtb \
-+ berlin2cd-google-chromecast.dtb \
-+ berlin2q-marvell-dmp.dtb
-+dtb-$(CONFIG_ARCH_BRCMSTB) += \
-+ bcm7445-bcm97445svmb.dtb
-+dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
-+ da850-evm.dtb
-+dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
-+dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
-+ exynos4210-smdkv310.dtb \
-+ exynos4210-trats.dtb \
-+ exynos4210-universal_c210.dtb \
-+ exynos4412-odroidu3.dtb \
-+ exynos4412-odroidx.dtb \
-+ exynos4412-odroidx2.dtb \
-+ exynos4412-origen.dtb \
-+ exynos4412-smdk4412.dtb \
-+ exynos4412-tiny4412.dtb \
-+ exynos4412-trats2.dtb \
-+ exynos5250-arndale.dtb \
-+ exynos5250-smdk5250.dtb \
-+ exynos5250-snow.dtb \
-+ exynos5260-xyref5260.dtb \
-+ exynos5410-smdk5410.dtb \
-+ exynos5420-arndale-octa.dtb \
-+ exynos5420-peach-pit.dtb \
-+ exynos5420-smdk5420.dtb \
-+ exynos5440-sd5v1.dtb \
-+ exynos5440-ssdk5440.dtb \
-+ exynos5800-peach-pi.dtb
-+dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
-+dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
-+dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
-+ ecx-2000.dtb
-+dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb
-+dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
-+ integratorcp.dtb
-+dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
-+ k2l-evm.dtb \
-+ k2e-evm.dtb
-+dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
-+ kirkwood-cloudbox.dtb \
-+ kirkwood-d2net.dtb \
-+ kirkwood-db-88f6281.dtb \
-+ kirkwood-db-88f6282.dtb \
-+ kirkwood-dns320.dtb \
-+ kirkwood-dns325.dtb \
-+ kirkwood-dockstar.dtb \
-+ kirkwood-dreamplug.dtb \
-+ kirkwood-ds109.dtb \
-+ kirkwood-ds110jv10.dtb \
-+ kirkwood-ds111.dtb \
-+ kirkwood-ds209.dtb \
-+ kirkwood-ds210.dtb \
-+ kirkwood-ds212.dtb \
-+ kirkwood-ds212j.dtb \
-+ kirkwood-ds409.dtb \
-+ kirkwood-ds409slim.dtb \
-+ kirkwood-ds411.dtb \
-+ kirkwood-ds411j.dtb \
-+ kirkwood-ds411slim.dtb \
-+ kirkwood-goflexnet.dtb \
-+ kirkwood-guruplug-server-plus.dtb \
-+ kirkwood-ib62x0.dtb \
-+ kirkwood-iconnect.dtb \
-+ kirkwood-iomega_ix2_200.dtb \
-+ kirkwood-is2.dtb \
-+ kirkwood-km_kirkwood.dtb \
-+ kirkwood-laplug.dtb \
-+ kirkwood-lschlv2.dtb \
-+ kirkwood-lsxhl.dtb \
-+ kirkwood-mplcec4.dtb \
-+ kirkwood-mv88f6281gtw-ge.dtb \
-+ kirkwood-net2big.dtb \
-+ kirkwood-net5big.dtb \
-+ kirkwood-netgear_readynas_duo_v2.dtb \
-+ kirkwood-netgear_readynas_nv+_v2.dtb \
-+ kirkwood-ns2.dtb \
-+ kirkwood-ns2lite.dtb \
-+ kirkwood-ns2max.dtb \
-+ kirkwood-ns2mini.dtb \
-+ kirkwood-nsa310.dtb \
-+ kirkwood-nsa310a.dtb \
-+ kirkwood-openblocks_a6.dtb \
-+ kirkwood-openblocks_a7.dtb \
-+ kirkwood-openrd-base.dtb \
-+ kirkwood-openrd-client.dtb \
-+ kirkwood-openrd-ultimate.dtb \
-+ kirkwood-rd88f6192.dtb \
-+ kirkwood-rd88f6281-z0.dtb \
-+ kirkwood-rd88f6281-a.dtb \
-+ kirkwood-rs212.dtb \
-+ kirkwood-rs409.dtb \
-+ kirkwood-rs411.dtb \
-+ kirkwood-sheevaplug.dtb \
-+ kirkwood-sheevaplug-esata.dtb \
-+ kirkwood-t5325.dtb \
-+ kirkwood-topkick.dtb \
-+ kirkwood-ts219-6281.dtb \
-+ kirkwood-ts219-6282.dtb \
-+ kirkwood-ts419-6281.dtb \
-+ kirkwood-ts419-6282.dtb
-+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
-+dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
-+dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
-+dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
-+dtb-$(CONFIG_ARCH_MXC) += \
-+ imx1-ads.dtb \
-+ imx1-apf9328.dtb \
-+ imx25-eukrea-mbimxsd25-baseboard.dtb \
-+ imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
-+ imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
-+ imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \
-+ imx25-karo-tx25.dtb \
-+ imx25-pdk.dtb \
-+ imx27-apf27.dtb \
-+ imx27-apf27dev.dtb \
-+ imx27-eukrea-mbimxsd27-baseboard.dtb \
-+ imx27-pdk.dtb \
-+ imx27-phytec-phycore-rdk.dtb \
-+ imx27-phytec-phycard-s-rdk.dtb \
-+ imx31-bug.dtb \
-+ imx35-eukrea-mbimxsd35-baseboard.dtb \
-+ imx35-pdk.dtb \
-+ imx50-evk.dtb \
-+ imx51-apf51.dtb \
-+ imx51-apf51dev.dtb \
-+ imx51-babbage.dtb \
-+ imx51-digi-connectcore-jsk.dtb \
-+ imx51-eukrea-mbimxsd51-baseboard.dtb \
-+ imx53-ard.dtb \
-+ imx53-m53evk.dtb \
-+ imx53-mba53.dtb \
-+ imx53-qsb.dtb \
-+ imx53-qsrb.dtb \
-+ imx53-smd.dtb \
-+ imx53-tx53-x03x.dtb \
-+ imx53-tx53-x13x.dtb \
-+ imx53-voipac-bsb.dtb \
-+ imx6dl-aristainetos_4.dtb \
-+ imx6dl-aristainetos_7.dtb \
-+ imx6dl-cubox-i.dtb \
-+ imx6dl-dfi-fs700-m60.dtb \
-+ imx6dl-gw51xx.dtb \
-+ imx6dl-gw52xx.dtb \
-+ imx6dl-gw53xx.dtb \
-+ imx6dl-gw54xx.dtb \
-+ imx6dl-gw552x.dtb \
-+ imx6dl-hummingboard.dtb \
-+ imx6dl-nitrogen6x.dtb \
-+ imx6dl-phytec-pbab01.dtb \
-+ imx6dl-rex-basic.dtb \
-+ imx6dl-riotboard.dtb \
-+ imx6dl-sabreauto.dtb \
-+ imx6dl-sabrelite.dtb \
-+ imx6dl-sabresd.dtb \
-+ imx6dl-tx6dl-comtft.dtb \
-+ imx6dl-tx6u-801x.dtb \
-+ imx6dl-tx6u-811x.dtb \
-+ imx6dl-wandboard.dtb \
-+ imx6dl-wandboard-revb1.dtb \
-+ imx6q-arm2.dtb \
-+ imx6q-cm-fx6.dtb \
-+ imx6q-cubox-i.dtb \
-+ imx6q-dfi-fs700-m60.dtb \
-+ imx6q-dmo-edmqmx6.dtb \
-+ imx6q-gk802.dtb \
-+ imx6q-gw51xx.dtb \
-+ imx6q-gw52xx.dtb \
-+ imx6q-gw53xx.dtb \
-+ imx6q-gw5400-a.dtb \
-+ imx6q-gw54xx.dtb \
-+ imx6q-gw552x.dtb \
-+ imx6q-hummingboard.dtb \
-+ imx6q-nitrogen6x.dtb \
-+ imx6q-phytec-pbab01.dtb \
-+ imx6q-rex-pro.dtb \
-+ imx6q-sabreauto.dtb \
-+ imx6q-sabrelite.dtb \
-+ imx6q-sabresd.dtb \
-+ imx6q-sbc6x.dtb \
-+ imx6q-udoo.dtb \
-+ imx6q-wandboard.dtb \
-+ imx6q-wandboard-revb1.dtb \
-+ imx6q-tx6q-1010.dtb \
-+ imx6q-tx6q-1010-comtft.dtb \
-+ imx6q-tx6q-1020.dtb \
-+ imx6q-tx6q-1020-comtft.dtb \
-+ imx6q-tx6q-1110.dtb \
-+ imx6sl-evk.dtb \
-+ imx6sx-sdb.dtb \
-+ vf610-colibri-eval-v3.dtb \
-+ vf610-cosmic.dtb \
-+ vf610-twr.dtb
-+dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
-+ imx23-olinuxino.dtb \
-+ imx23-stmp378x_devb.dtb \
-+ imx28-apf28.dtb \
-+ imx28-apf28dev.dtb \
-+ imx28-apx4devkit.dtb \
-+ imx28-cfa10036.dtb \
-+ imx28-cfa10037.dtb \
-+ imx28-cfa10049.dtb \
-+ imx28-cfa10055.dtb \
-+ imx28-cfa10056.dtb \
-+ imx28-cfa10057.dtb \
-+ imx28-cfa10058.dtb \
-+ imx28-duckbill.dtb \
-+ imx28-eukrea-mbmx283lc.dtb \
-+ imx28-eukrea-mbmx287lc.dtb \
-+ imx28-evk.dtb \
-+ imx28-m28cu3.dtb \
-+ imx28-m28evk.dtb \
-+ imx28-sps1.dtb \
-+ imx28-tx28.dtb
-+dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
-+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
-+ nspire-tp.dtb \
-+ nspire-clp.dtb
-+dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \
-+ omap2420-n800.dtb \
-+ omap2420-n810.dtb \
-+ omap2420-n810-wimax.dtb \
-+ omap2430-sdp.dtb
-+dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
-+ am3517-evm.dtb \
-+ am3517_mt_ventoux.dtb \
-+ omap3430-sdp.dtb \
-+ omap3-beagle.dtb \
-+ omap3-beagle-xm.dtb \
-+ omap3-beagle-xm-ab.dtb \
-+ omap3-cm-t3517.dtb \
-+ omap3-cm-t3530.dtb \
-+ omap3-cm-t3730.dtb \
-+ omap3-devkit8000.dtb \
-+ omap3-evm.dtb \
-+ omap3-evm-37xx.dtb \
-+ omap3-gta04a3.dtb \
-+ omap3-gta04a4.dtb \
-+ omap3-gta04a5.dtb \
-+ omap3-ha.dtb \
-+ omap3-ha-lcd.dtb \
-+ omap3-igep0020.dtb \
-+ omap3-igep0030.dtb \
-+ omap3-ldp.dtb \
-+ omap3-lilly-dbb056.dtb \
-+ omap3-n900.dtb \
-+ omap3-n9.dtb \
-+ omap3-n950.dtb \
-+ omap3-overo-alto35.dtb \
-+ omap3-overo-chestnut43.dtb \
-+ omap3-overo-gallop43.dtb \
-+ omap3-overo-palo43.dtb \
-+ omap3-overo-storm-alto35.dtb \
-+ omap3-overo-storm-chestnut43.dtb \
-+ omap3-overo-storm-gallop43.dtb \
-+ omap3-overo-storm-palo43.dtb \
-+ omap3-overo-storm-summit.dtb \
-+ omap3-overo-storm-tobi.dtb \
-+ omap3-overo-summit.dtb \
-+ omap3-overo-tobi.dtb \
-+ omap3-sbc-t3517.dtb \
-+ omap3-sbc-t3530.dtb \
-+ omap3-sbc-t3730.dtb \
-+ omap3-thunder.dtb \
-+ omap3-zoom3.dtb
-+dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
-+ am335x-bone.dtb \
-+ am335x-boneblack.dtb \
-+ am335x-evm.dtb \
-+ am335x-evmsk.dtb \
-+ am335x-nano.dtb \
-+ am335x-pepper.dtb
-+dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
-+ omap4-panda.dtb \
-+ omap4-panda-a4.dtb \
-+ omap4-panda-es.dtb \
-+ omap4-sdp.dtb \
-+ omap4-sdp-es23plus.dtb \
-+ omap4-var-dvk-om44.dtb \
-+ omap4-var-stk-om44.dtb
-+dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
-+ am437x-sk-evm.dtb \
-+ am437x-gp-evm.dtb
-+dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
-+ omap5-sbc-t54.dtb \
-+ omap5-uevm.dtb
-+dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
-+ dra72-evm.dtb
-+dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
-+ orion5x-lacie-ethernet-disk-mini-v2.dtb \
-+ orion5x-maxtor-shared-storage-2.dtb \
-+ orion5x-rd88f5182-nas.dtb
-+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-+dtb-$(CONFIG_ARCH_QCOM) += \
-+ qcom-apq8064-cm-qs600.dtb \
-+ qcom-apq8064-ifc6410.dtb \
-+ qcom-apq8074-dragonboard.dtb \
-+ qcom-apq8084-ifc6540.dtb \
-+ qcom-apq8084-mtp.dtb \
-+ qcom-ipq8064-ap148.dtb \
-+ qcom-msm8660-surf.dtb \
-+ qcom-msm8960-cdp.dtb \
-+ qcom-msm8974-sony-xperia-honami.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += \
-+ rk3066a-bqcurie2.dtb \
-+ rk3188-radxarock.dtb \
-+ rk3288-evb-act8846.dtb \
-+ rk3288-evb-rk808.dtb
-+dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
-+dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
-+ s3c6410-smdk6410.dtb
-+dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
-+ s5pv210-goni.dtb \
-+ s5pv210-smdkc110.dtb \
-+ s5pv210-smdkv210.dtb \
-+ s5pv210-torbreck.dtb
-+dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
-+ r8a7740-armadillo800eva.dtb \
-+ r8a7778-bockw.dtb \
-+ r8a7778-bockw-reference.dtb \
-+ r8a7779-marzen.dtb \
-+ r8a7791-koelsch.dtb \
-+ r8a7790-lager.dtb \
-+ sh73a0-kzm9g.dtb \
-+ sh73a0-kzm9g-reference.dtb \
-+ r8a73a4-ape6evm.dtb \
-+ r8a73a4-ape6evm-reference.dtb \
-+ sh7372-mackerel.dtb
-+dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
-+ r7s72100-genmai.dtb \
-+ r8a7740-armadillo800eva.dtb \
-+ r8a7791-henninger.dtb \
-+ r8a7791-koelsch.dtb \
-+ r8a7790-lager.dtb \
-+ r8a7779-marzen.dtb \
-+ r8a7794-alt.dtb
-+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
-+ socfpga_cyclone5_socdk.dtb \
-+ socfpga_cyclone5_sockit.dtb \
-+ socfpga_cyclone5_socrates.dtb \
-+ socfpga_vt.dtb
-+dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
-+ spear1340-evb.dtb
-+dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
-+ spear310-evb.dtb \
-+ spear320-evb.dtb \
-+ spear320-hmi.dtb
-+dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
-+dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
-+ stih415-b2000.dtb \
-+ stih415-b2020.dtb \
-+ stih416-b2000.dtb \
-+ stih416-b2020.dtb \
-+ stih416-b2020e.dtb
-+dtb-$(CONFIG_MACH_SUN4I) += \
-+ sun4i-a10-a1000.dtb \
-+ sun4i-a10-ba10-tvbox.dtb \
-+ sun4i-a10-cubieboard.dtb \
-+ sun4i-a10-mini-xplus.dtb \
-+ sun4i-a10-hackberry.dtb \
-+ sun4i-a10-inet97fv2.dtb \
-+ sun4i-a10-olinuxino-lime.dtb \
-+ sun4i-a10-pcduino.dtb
-+dtb-$(CONFIG_MACH_SUN5I) += \
-+ sun5i-a10s-olinuxino-micro.dtb \
-+ sun5i-a10s-r7-tv-dongle.dtb \
-+ sun5i-a13-hsg-h702.dtb \
-+ sun5i-a13-olinuxino.dtb \
-+ sun5i-a13-olinuxino-micro.dtb
-+dtb-$(CONFIG_MACH_SUN6I) += \
-+ sun6i-a31-app4-evb1.dtb \
-+ sun6i-a31-colombus.dtb \
-+ sun6i-a31-hummingbird.dtb \
-+ sun6i-a31-m9.dtb
-+dtb-$(CONFIG_MACH_SUN7I) += \
-+ sun7i-a20-cubieboard2.dtb \
-+ sun7i-a20-cubietruck.dtb \
-+ sun7i-a20-hummingbird.dtb \
-+ sun7i-a20-i12-tvbox.dtb \
-+ sun7i-a20-olinuxino-lime.dtb \
-+ sun7i-a20-olinuxino-micro.dtb \
-+ sun7i-a20-pcduino3.dtb
-+dtb-$(CONFIG_MACH_SUN8I) += \
-+ sun8i-a23-ippo-q8h-v5.dtb
-+dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
-+ tegra20-iris-512.dtb \
-+ tegra20-medcom-wide.dtb \
-+ tegra20-paz00.dtb \
-+ tegra20-plutux.dtb \
-+ tegra20-seaboard.dtb \
-+ tegra20-tec.dtb \
-+ tegra20-trimslice.dtb \
-+ tegra20-ventana.dtb \
-+ tegra20-whistler.dtb \
-+ tegra30-apalis-eval.dtb \
-+ tegra30-beaver.dtb \
-+ tegra30-cardhu-a02.dtb \
-+ tegra30-cardhu-a04.dtb \
-+ tegra30-colibri-eval-v3.dtb \
-+ tegra114-dalmore.dtb \
-+ tegra114-roth.dtb \
-+ tegra114-tn7.dtb \
-+ tegra124-jetson-tk1.dtb \
-+ tegra124-nyan-big.dtb \
-+ tegra124-venice2.dtb
-+dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
-+dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
-+ ste-hrefprev60-stuib.dtb \
-+ ste-hrefprev60-tvk.dtb \
-+ ste-hrefv60plus-stuib.dtb \
-+ ste-hrefv60plus-tvk.dtb \
-+ ste-ccu8540.dtb \
-+ ste-ccu9540.dtb
-+dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
-+ versatile-pb.dtb
-+dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
-+ vexpress-v2p-ca9.dtb \
-+ vexpress-v2p-ca15-tc1.dtb \
-+ vexpress-v2p-ca15_a7.dtb
-+dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
-+dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
-+ wm8505-ref.dtb \
-+ wm8650-mid.dtb \
-+ wm8750-apc8750.dtb \
-+ wm8850-w70v2.dtb
-+dtb-$(CONFIG_ARCH_ZYNQ) += \
-+ zynq-parallella.dtb \
-+ zynq-zc702.dtb \
-+ zynq-zc706.dtb \
-+ zynq-zed.dtb
-+dtb-$(CONFIG_MACH_ARMADA_370) += \
-+ armada-370-db.dtb \
-+ armada-370-mirabox.dtb \
-+ armada-370-netgear-rn102.dtb \
-+ armada-370-netgear-rn104.dtb \
-+ armada-370-rd.dtb
-+dtb-$(CONFIG_MACH_ARMADA_375) += \
-+ armada-375-db.dtb
-+dtb-$(CONFIG_MACH_ARMADA_38X) += \
-+ armada-385-db.dtb \
-+ armada-385-rd.dtb
-+dtb-$(CONFIG_MACH_ARMADA_XP) += \
-+ armada-xp-axpwifiap.dtb \
-+ armada-xp-db.dtb \
-+ armada-xp-gp.dtb \
-+ armada-xp-lenovo-ix4-300d.dtb \
-+ armada-xp-matrix.dtb \
-+ armada-xp-netgear-rn2120.dtb \
-+ armada-xp-openblocks-ax3-4.dtb
-+dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
-+ dove-cubox.dtb \
-+ dove-cubox-es.dtb \
-+ dove-d2plug.dtb \
-+ dove-d3plug.dtb \
-+ dove-dove-db.dtb
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb
-+
-+targets += dtbs dtbs_install
-+targets += $(dtb-y)
-+
-+endif
-+
-+# Enable fixups to support overlays on BCM2708 platforms
-+ifeq ($(RPI_DT_OVERLAYS),y)
-+ DTC_FLAGS ?= -@
-+endif
-+
-+# *.dtb used to be generated in the directory above. Clean out the
-+# old build results so people don't accidentally use them.
-+dtbs: $(addprefix $(obj)/, $(dtb-y))
-+ $(Q)rm -f $(obj)/../*.dtb
-+
-+clean-files := *.dtb
-+
-+dtbs_install: $(addsuffix _dtbinst_, $(dtb-y))
-diff -Nur linux-3.12.38/arch/arm/configs/bcmrpi_cutdown_defconfig linux-rpi/arch/arm/configs/bcmrpi_cutdown_defconfig
---- linux-3.12.38/arch/arm/configs/bcmrpi_cutdown_defconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/configs/bcmrpi_cutdown_defconfig 2015-03-10 17:26:49.690216697 +0100
-@@ -0,0 +1,463 @@
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+# CONFIG_UID16 is not set
-+# CONFIG_KALLSYMS is not set
-+CONFIG_EMBEDDED=y
-+# CONFIG_VM_EVENT_COUNTERS is not set
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_SLAB=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+# CONFIG_BLK_DEV_BSG is not set
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_ARCH_BCM2708=y
-+CONFIG_AEABI=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
-+CONFIG_CPU_IDLE=y
-+CONFIG_VFP=y
-+CONFIG_BINFMT_MISC=m
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_SYN_COOKIES=y
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+# CONFIG_IPV6 is not set
-+CONFIG_NET_PKTGEN=m
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_BT=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_CFG80211=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_RC_PID=y
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_NFC_PN533=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_SCSI_MULTI_LUN=y
-+# CONFIG_SCSI_LOWLEVEL is not set
-+CONFIG_NETDEVICES=y
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_KC2190=y
-+# CONFIG_USB_NET_ZAURUS is not set
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_RTL8187=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_B43=m
-+CONFIG_B43LEGACY=m
-+CONFIG_HOSTAP=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RTL8192CU=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_INPUT_POLLDEV=m
-+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+# CONFIG_HW_RANDOM is not set
-+CONFIG_RAW_DRIVER=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2708=m
-+CONFIG_GPIO_SYSFS=y
-+# CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2708_WDT=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_SEQUENCER_OSS=y
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_BCM2835=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SOUND_PRIME=m
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_LED=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_MMC=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_BCM2708=y
-+CONFIG_MMC_SDHCI_BCM2708_DMA=y
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_FSCACHE=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_CONFIGFS_FS=y
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_9P_FS=m
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_NLS_UTF8=m
-+# CONFIG_SCHED_DEBUG is not set
-+# CONFIG_DEBUG_BUGVERBOSE is not set
-+# CONFIG_FTRACE is not set
-+# CONFIG_ARM_UNWIND is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+CONFIG_CRYPTO_SEQIV=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_HMAC=y
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_MD5=y
-+CONFIG_CRYPTO_SHA1=y
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_DEFLATE=m
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-diff -Nur linux-3.12.38/arch/arm/configs/bcmrpi_defconfig linux-rpi/arch/arm/configs/bcmrpi_defconfig
---- linux-3.12.38/arch/arm/configs/bcmrpi_defconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/configs/bcmrpi_defconfig 2015-03-10 17:26:49.690216697 +0100
-@@ -0,0 +1,1119 @@
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_FHANDLE=y
-+CONFIG_AUDIT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+CONFIG_TASK_XACCT=y
-+CONFIG_TASK_IO_ACCOUNTING=y
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_RESOURCE_COUNTERS=y
-+CONFIG_MEMCG=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_NAMESPACES=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_RELAY=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_JUMP_LABEL=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_BCM2708=y
-+CONFIG_PREEMPT=y
-+CONFIG_AEABI=y
-+CONFIG_CLEANCACHE=y
-+CONFIG_FRONTSWAP=y
-+CONFIG_CMA=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_SECCOMP=y
-+CONFIG_CC_STACKPROTECTOR=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_KEXEC=y
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_STAT=m
-+CONFIG_CPU_FREQ_STAT_DETAILS=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_CPU_IDLE=y
-+CONFIG_VFP=y
-+CONFIG_BINFMT_MISC=m
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE_DEMUX=m
-+CONFIG_NET_IPGRE=m
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IP_PIMSM_V1=y
-+CONFIG_IP_PIMSM_V2=y
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+CONFIG_INET_IPCOMP=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+CONFIG_INET_LRO=m
-+CONFIG_INET_DIAG=m
-+CONFIG_IPV6_PRIVACY=y
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_IPV6_TUNNEL=m
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IPV6_PIMSM_V2=y
-+CONFIG_NETFILTER=y
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_ZONES=y
-+CONFIG_NF_CONNTRACK_EVENTS=y
-+CONFIG_NF_CONNTRACK_TIMESTAMP=y
-+CONFIG_NF_CT_PROTO_DCCP=m
-+CONFIG_NF_CT_PROTO_UDPLITE=m
-+CONFIG_NF_CONNTRACK_AMANDA=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_H323=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-+CONFIG_NF_CONNTRACK_SNMP=m
-+CONFIG_NF_CONNTRACK_PPTP=m
-+CONFIG_NF_CONNTRACK_SANE=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CONNTRACK_TFTP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XT_SET=m
-+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-+CONFIG_NETFILTER_XT_TARGET_DSCP=m
-+CONFIG_NETFILTER_XT_TARGET_HMARK=m
-+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-+CONFIG_NETFILTER_XT_TARGET_LED=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TEE=m
-+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-+CONFIG_NETFILTER_XT_TARGET_TRACE=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_BPF=m
-+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_CPU=m
-+CONFIG_NETFILTER_XT_MATCH_DCCP=m
-+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-+CONFIG_NETFILTER_XT_MATCH_DSCP=m
-+CONFIG_NETFILTER_XT_MATCH_ESP=m
-+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_HELPER=m
-+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-+CONFIG_NETFILTER_XT_MATCH_IPVS=m
-+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-+CONFIG_NETFILTER_XT_MATCH_OSF=m
-+CONFIG_NETFILTER_XT_MATCH_OWNER=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-+CONFIG_NETFILTER_XT_MATCH_REALM=m
-+CONFIG_NETFILTER_XT_MATCH_RECENT=m
-+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-+CONFIG_NETFILTER_XT_MATCH_STRING=m
-+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NETFILTER_XT_MATCH_U32=m
-+CONFIG_IP_SET=m
-+CONFIG_IP_SET_BITMAP_IP=m
-+CONFIG_IP_SET_BITMAP_IPMAC=m
-+CONFIG_IP_SET_BITMAP_PORT=m
-+CONFIG_IP_SET_HASH_IP=m
-+CONFIG_IP_SET_HASH_IPPORT=m
-+CONFIG_IP_SET_HASH_IPPORTIP=m
-+CONFIG_IP_SET_HASH_IPPORTNET=m
-+CONFIG_IP_SET_HASH_NET=m
-+CONFIG_IP_SET_HASH_NETPORT=m
-+CONFIG_IP_SET_HASH_NETIFACE=m
-+CONFIG_IP_SET_LIST_SET=m
-+CONFIG_IP_VS=m
-+CONFIG_IP_VS_PROTO_TCP=y
-+CONFIG_IP_VS_PROTO_UDP=y
-+CONFIG_IP_VS_PROTO_ESP=y
-+CONFIG_IP_VS_PROTO_AH=y
-+CONFIG_IP_VS_PROTO_SCTP=y
-+CONFIG_IP_VS_RR=m
-+CONFIG_IP_VS_WRR=m
-+CONFIG_IP_VS_LC=m
-+CONFIG_IP_VS_WLC=m
-+CONFIG_IP_VS_LBLC=m
-+CONFIG_IP_VS_LBLCR=m
-+CONFIG_IP_VS_DH=m
-+CONFIG_IP_VS_SH=m
-+CONFIG_IP_VS_SED=m
-+CONFIG_IP_VS_NQ=m
-+CONFIG_IP_VS_FTP=m
-+CONFIG_IP_VS_PE_SIP=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_MATCH_AH=m
-+CONFIG_IP_NF_MATCH_ECN=m
-+CONFIG_IP_NF_MATCH_TTL=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_TARGET_ULOG=m
-+CONFIG_NF_NAT_IPV4=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_NETMAP=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_TARGET_ECN=m
-+CONFIG_IP_NF_TARGET_TTL=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_IP_NF_ARPTABLES=m
-+CONFIG_IP_NF_ARPFILTER=m
-+CONFIG_IP_NF_ARP_MANGLE=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_HL=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_TARGET_HL=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_NF_NAT_IPV6=m
-+CONFIG_IP6_NF_TARGET_MASQUERADE=m
-+CONFIG_IP6_NF_TARGET_NPT=m
-+CONFIG_BRIDGE_NF_EBTABLES=m
-+CONFIG_BRIDGE_EBT_BROUTE=m
-+CONFIG_BRIDGE_EBT_T_FILTER=m
-+CONFIG_BRIDGE_EBT_T_NAT=m
-+CONFIG_BRIDGE_EBT_802_3=m
-+CONFIG_BRIDGE_EBT_AMONG=m
-+CONFIG_BRIDGE_EBT_ARP=m
-+CONFIG_BRIDGE_EBT_IP=m
-+CONFIG_BRIDGE_EBT_IP6=m
-+CONFIG_BRIDGE_EBT_LIMIT=m
-+CONFIG_BRIDGE_EBT_MARK=m
-+CONFIG_BRIDGE_EBT_PKTTYPE=m
-+CONFIG_BRIDGE_EBT_STP=m
-+CONFIG_BRIDGE_EBT_VLAN=m
-+CONFIG_BRIDGE_EBT_ARPREPLY=m
-+CONFIG_BRIDGE_EBT_DNAT=m
-+CONFIG_BRIDGE_EBT_MARK_T=m
-+CONFIG_BRIDGE_EBT_REDIRECT=m
-+CONFIG_BRIDGE_EBT_SNAT=m
-+CONFIG_BRIDGE_EBT_LOG=m
-+CONFIG_BRIDGE_EBT_ULOG=m
-+CONFIG_BRIDGE_EBT_NFLOG=m
-+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-+CONFIG_ATM=m
-+CONFIG_L2TP=m
-+CONFIG_L2TP_V3=y
-+CONFIG_L2TP_IP=m
-+CONFIG_L2TP_ETH=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+CONFIG_VLAN_8021Q_GVRP=y
-+CONFIG_ATALK=m
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_CBQ=m
-+CONFIG_NET_SCH_HTB=m
-+CONFIG_NET_SCH_HFSC=m
-+CONFIG_NET_SCH_PRIO=m
-+CONFIG_NET_SCH_MULTIQ=m
-+CONFIG_NET_SCH_RED=m
-+CONFIG_NET_SCH_SFB=m
-+CONFIG_NET_SCH_SFQ=m
-+CONFIG_NET_SCH_TEQL=m
-+CONFIG_NET_SCH_TBF=m
-+CONFIG_NET_SCH_GRED=m
-+CONFIG_NET_SCH_DSMARK=m
-+CONFIG_NET_SCH_NETEM=m
-+CONFIG_NET_SCH_DRR=m
-+CONFIG_NET_SCH_MQPRIO=m
-+CONFIG_NET_SCH_CHOKE=m
-+CONFIG_NET_SCH_QFQ=m
-+CONFIG_NET_SCH_CODEL=m
-+CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_INGRESS=m
-+CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_CLS_BASIC=m
-+CONFIG_NET_CLS_TCINDEX=m
-+CONFIG_NET_CLS_ROUTE4=m
-+CONFIG_NET_CLS_FW=m
-+CONFIG_NET_CLS_U32=m
-+CONFIG_CLS_U32_MARK=y
-+CONFIG_NET_CLS_RSVP=m
-+CONFIG_NET_CLS_RSVP6=m
-+CONFIG_NET_CLS_FLOW=m
-+CONFIG_NET_CLS_CGROUP=m
-+CONFIG_NET_EMATCH=y
-+CONFIG_NET_EMATCH_CMP=m
-+CONFIG_NET_EMATCH_NBYTE=m
-+CONFIG_NET_EMATCH_U32=m
-+CONFIG_NET_EMATCH_META=m
-+CONFIG_NET_EMATCH_TEXT=m
-+CONFIG_NET_EMATCH_IPSET=m
-+CONFIG_NET_CLS_ACT=y
-+CONFIG_NET_ACT_POLICE=m
-+CONFIG_NET_ACT_GACT=m
-+CONFIG_GACT_PROB=y
-+CONFIG_NET_ACT_MIRRED=m
-+CONFIG_NET_ACT_IPT=m
-+CONFIG_NET_ACT_NAT=m
-+CONFIG_NET_ACT_PEDIT=m
-+CONFIG_NET_ACT_SIMP=m
-+CONFIG_NET_ACT_SKBEDIT=m
-+CONFIG_NET_ACT_CSUM=m
-+CONFIG_BATMAN_ADV=m
-+CONFIG_OPENVSWITCH=m
-+CONFIG_NET_PKTGEN=m
-+CONFIG_HAMRADIO=y
-+CONFIG_AX25=m
-+CONFIG_NETROM=m
-+CONFIG_ROSE=m
-+CONFIG_MKISS=m
-+CONFIG_6PACK=m
-+CONFIG_BPQETHER=m
-+CONFIG_BAYCOM_SER_FDX=m
-+CONFIG_BAYCOM_SER_HDX=m
-+CONFIG_YAM=m
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_BT=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_BT_WILINK=m
-+CONFIG_CFG80211=m
-+CONFIG_CFG80211_WEXT=y
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_RC_PID=y
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_RFKILL=m
-+CONFIG_RFKILL_INPUT=y
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_NFC_PN533=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_DRBD=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_EEPROM_AT24=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_CHR_DEV_ST=m
-+CONFIG_CHR_DEV_OSST=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_CHR_DEV_SG=m
-+CONFIG_SCSI_MULTI_LUN=y
-+CONFIG_SCSI_ISCSI_ATTRS=y
-+CONFIG_ISCSI_TCP=m
-+CONFIG_ISCSI_BOOT_SYSFS=m
-+CONFIG_MD=y
-+CONFIG_MD_LINEAR=m
-+CONFIG_MD_RAID0=m
-+CONFIG_BLK_DEV_DM=m
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_RAID=m
-+CONFIG_DM_LOG_USERSPACE=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_DELAY=m
-+CONFIG_NETDEVICES=y
-+CONFIG_BONDING=m
-+CONFIG_DUMMY=m
-+CONFIG_IFB=m
-+CONFIG_MACVLAN=m
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_VETH=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOATM=m
-+CONFIG_PPPOE=m
-+CONFIG_PPPOL2TP=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_SLIP_SMART=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_RTL8152=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_AX88179_178A=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_CDC_NCM=m
-+CONFIG_USB_NET_CDC_MBIM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_EPSON2888=y
-+CONFIG_USB_KC2190=y
-+CONFIG_USB_NET_ZAURUS=m
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_QMI_WWAN=m
-+CONFIG_USB_HSO=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_RTL8187=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_ATH_CARDS=m
-+CONFIG_ATH9K=m
-+CONFIG_ATH9K_HTC=m
-+CONFIG_CARL9170=m
-+CONFIG_ATH6KL=m
-+CONFIG_ATH6KL_USB=m
-+CONFIG_AR5523=m
-+CONFIG_B43=m
-+# CONFIG_B43_PHY_N is not set
-+CONFIG_B43LEGACY=m
-+CONFIG_BRCMFMAC=m
-+# CONFIG_BRCMFMAC_SDIO is not set
-+CONFIG_BRCMFMAC_USB=y
-+CONFIG_HOSTAP=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT3573=y
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RT2800USB_RT55XX=y
-+CONFIG_RT2800USB_UNKNOWN=y
-+CONFIG_RTL8192CU=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_INPUT_POLLDEV=m
-+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_JOYSTICK=y
-+CONFIG_JOYSTICK_IFORCE=m
-+CONFIG_JOYSTICK_IFORCE_USB=y
-+CONFIG_JOYSTICK_XPAD=m
-+CONFIG_JOYSTICK_XPAD_FF=y
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_HW_RANDOM_BCM2708=m
-+CONFIG_RAW_DRIVER=y
-+CONFIG_BRCM_CHAR_DRIVERS=y
-+CONFIG_BCM_VC_CMA=y
-+CONFIG_BCM_VC_SM=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2708=m
-+CONFIG_SPI_SPIDEV=y
-+CONFIG_PPS=m
-+CONFIG_PPS_CLIENT_LDISC=m
-+CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_GPIO_SYSFS=y
-+CONFIG_W1=m
-+CONFIG_W1_MASTER_DS2490=m
-+CONFIG_W1_MASTER_DS2482=m
-+CONFIG_W1_MASTER_DS1WM=m
-+CONFIG_W1_MASTER_GPIO=m
-+CONFIG_W1_SLAVE_THERM=m
-+CONFIG_W1_SLAVE_SMEM=m
-+CONFIG_W1_SLAVE_DS2408=m
-+CONFIG_W1_SLAVE_DS2413=m
-+CONFIG_W1_SLAVE_DS2423=m
-+CONFIG_W1_SLAVE_DS2431=m
-+CONFIG_W1_SLAVE_DS2433=m
-+CONFIG_W1_SLAVE_DS2760=m
-+CONFIG_W1_SLAVE_DS2780=m
-+CONFIG_W1_SLAVE_DS2781=m
-+CONFIG_W1_SLAVE_DS28E04=m
-+CONFIG_W1_SLAVE_BQ27000=m
-+CONFIG_BATTERY_DS2760=m
-+# CONFIG_HWMON is not set
-+CONFIG_THERMAL=y
-+CONFIG_THERMAL_BCM2835=y
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2708_WDT=m
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_RC_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_LIRC=m
-+CONFIG_RC_DEVICES=y
-+CONFIG_RC_ATI_REMOTE=m
-+CONFIG_IR_IMON=m
-+CONFIG_IR_MCEUSB=m
-+CONFIG_IR_REDRAT3=m
-+CONFIG_IR_STREAMZAP=m
-+CONFIG_IR_IGUANA=m
-+CONFIG_IR_TTUSBIR=m
-+CONFIG_RC_LOOPBACK=m
-+CONFIG_IR_GPIO_CIR=m
-+CONFIG_MEDIA_USB_SUPPORT=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_M5602=m
-+CONFIG_USB_STV06XX=m
-+CONFIG_USB_GL860=m
-+CONFIG_USB_GSPCA_BENQ=m
-+CONFIG_USB_GSPCA_CONEX=m
-+CONFIG_USB_GSPCA_CPIA1=m
-+CONFIG_USB_GSPCA_ETOMS=m
-+CONFIG_USB_GSPCA_FINEPIX=m
-+CONFIG_USB_GSPCA_JEILINJ=m
-+CONFIG_USB_GSPCA_JL2005BCD=m
-+CONFIG_USB_GSPCA_KINECT=m
-+CONFIG_USB_GSPCA_KONICA=m
-+CONFIG_USB_GSPCA_MARS=m
-+CONFIG_USB_GSPCA_MR97310A=m
-+CONFIG_USB_GSPCA_NW80X=m
-+CONFIG_USB_GSPCA_OV519=m
-+CONFIG_USB_GSPCA_OV534=m
-+CONFIG_USB_GSPCA_OV534_9=m
-+CONFIG_USB_GSPCA_PAC207=m
-+CONFIG_USB_GSPCA_PAC7302=m
-+CONFIG_USB_GSPCA_PAC7311=m
-+CONFIG_USB_GSPCA_SE401=m
-+CONFIG_USB_GSPCA_SN9C2028=m
-+CONFIG_USB_GSPCA_SN9C20X=m
-+CONFIG_USB_GSPCA_SONIXB=m
-+CONFIG_USB_GSPCA_SONIXJ=m
-+CONFIG_USB_GSPCA_SPCA500=m
-+CONFIG_USB_GSPCA_SPCA501=m
-+CONFIG_USB_GSPCA_SPCA505=m
-+CONFIG_USB_GSPCA_SPCA506=m
-+CONFIG_USB_GSPCA_SPCA508=m
-+CONFIG_USB_GSPCA_SPCA561=m
-+CONFIG_USB_GSPCA_SPCA1528=m
-+CONFIG_USB_GSPCA_SQ905=m
-+CONFIG_USB_GSPCA_SQ905C=m
-+CONFIG_USB_GSPCA_SQ930X=m
-+CONFIG_USB_GSPCA_STK014=m
-+CONFIG_USB_GSPCA_STK1135=m
-+CONFIG_USB_GSPCA_STV0680=m
-+CONFIG_USB_GSPCA_SUNPLUS=m
-+CONFIG_USB_GSPCA_T613=m
-+CONFIG_USB_GSPCA_TOPRO=m
-+CONFIG_USB_GSPCA_TV8532=m
-+CONFIG_USB_GSPCA_VC032X=m
-+CONFIG_USB_GSPCA_VICAM=m
-+CONFIG_USB_GSPCA_XIRLINK_CIT=m
-+CONFIG_USB_GSPCA_ZC3XX=m
-+CONFIG_USB_PWC=m
-+CONFIG_VIDEO_CPIA2=m
-+CONFIG_USB_ZR364XX=m
-+CONFIG_USB_STKWEBCAM=m
-+CONFIG_USB_S2255=m
-+CONFIG_USB_SN9C102=m
-+CONFIG_VIDEO_USBTV=m
-+CONFIG_VIDEO_PVRUSB2=m
-+CONFIG_VIDEO_HDPVR=m
-+CONFIG_VIDEO_TLG2300=m
-+CONFIG_VIDEO_USBVISION=m
-+CONFIG_VIDEO_STK1160_COMMON=m
-+CONFIG_VIDEO_AU0828=m
-+CONFIG_VIDEO_CX231XX=m
-+CONFIG_VIDEO_CX231XX_ALSA=m
-+CONFIG_VIDEO_CX231XX_DVB=m
-+CONFIG_VIDEO_TM6000=m
-+CONFIG_VIDEO_TM6000_ALSA=m
-+CONFIG_VIDEO_TM6000_DVB=m
-+CONFIG_DVB_USB=m
-+CONFIG_DVB_USB_A800=m
-+CONFIG_DVB_USB_DIBUSB_MB=m
-+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-+CONFIG_DVB_USB_DIBUSB_MC=m
-+CONFIG_DVB_USB_DIB0700=m
-+CONFIG_DVB_USB_UMT_010=m
-+CONFIG_DVB_USB_CXUSB=m
-+CONFIG_DVB_USB_M920X=m
-+CONFIG_DVB_USB_DIGITV=m
-+CONFIG_DVB_USB_VP7045=m
-+CONFIG_DVB_USB_VP702X=m
-+CONFIG_DVB_USB_GP8PSK=m
-+CONFIG_DVB_USB_NOVA_T_USB2=m
-+CONFIG_DVB_USB_TTUSB2=m
-+CONFIG_DVB_USB_DTT200U=m
-+CONFIG_DVB_USB_OPERA1=m
-+CONFIG_DVB_USB_AF9005=m
-+CONFIG_DVB_USB_AF9005_REMOTE=m
-+CONFIG_DVB_USB_PCTV452E=m
-+CONFIG_DVB_USB_DW2102=m
-+CONFIG_DVB_USB_CINERGY_T2=m
-+CONFIG_DVB_USB_DTV5100=m
-+CONFIG_DVB_USB_FRIIO=m
-+CONFIG_DVB_USB_AZ6027=m
-+CONFIG_DVB_USB_TECHNISAT_USB2=m
-+CONFIG_DVB_USB_V2=m
-+CONFIG_DVB_USB_AF9015=m
-+CONFIG_DVB_USB_AF9035=m
-+CONFIG_DVB_USB_ANYSEE=m
-+CONFIG_DVB_USB_AU6610=m
-+CONFIG_DVB_USB_AZ6007=m
-+CONFIG_DVB_USB_CE6230=m
-+CONFIG_DVB_USB_EC168=m
-+CONFIG_DVB_USB_GL861=m
-+CONFIG_DVB_USB_IT913X=m
-+CONFIG_DVB_USB_LME2510=m
-+CONFIG_DVB_USB_MXL111SF=m
-+CONFIG_DVB_USB_RTL28XXU=m
-+CONFIG_SMS_USB_DRV=m
-+CONFIG_DVB_B2C2_FLEXCOP_USB=m
-+CONFIG_VIDEO_EM28XX=m
-+CONFIG_VIDEO_EM28XX_ALSA=m
-+CONFIG_VIDEO_EM28XX_DVB=m
-+CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_BCM2835=y
-+CONFIG_VIDEO_BCM2835_MMAL=m
-+CONFIG_RADIO_SI470X=y
-+CONFIG_USB_SI470X=m
-+CONFIG_I2C_SI470X=m
-+CONFIG_USB_MR800=m
-+CONFIG_USB_DSBR=m
-+CONFIG_RADIO_SHARK=m
-+CONFIG_RADIO_SHARK2=m
-+CONFIG_RADIO_SI4713=m
-+CONFIG_USB_KEENE=m
-+CONFIG_USB_MA901=m
-+CONFIG_RADIO_TEA5764=m
-+CONFIG_RADIO_SAA7706H=m
-+CONFIG_RADIO_TEF6862=m
-+CONFIG_RADIO_WL1273=m
-+CONFIG_RADIO_WL128X=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_SEQUENCER_OSS=y
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_BCM2835=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_CAIAQ_INPUT=y
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_SOC=m
-+CONFIG_SND_BCM2708_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
-+CONFIG_SND_BCM2708_SOC_RPI_DAC=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
-+CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_SOUND_PRIME=m
-+CONFIG_HIDRAW=y
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_ELO=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THINGM=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_WACOM=m
-+CONFIG_HID_WIIMOTE=m
-+CONFIG_HID_XINMO=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_F81232=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_METRO=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_XSENS_MT=m
-+CONFIG_USB_SERIAL_WISHBONE=m
-+CONFIG_USB_SERIAL_ZTE=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_QT2=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_LED=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_USB_ATM=m
-+CONFIG_USB_SPEEDTOUCH=m
-+CONFIG_USB_CXACRU=m
-+CONFIG_USB_UEAGLEATM=m
-+CONFIG_USB_XUSBATM=m
-+CONFIG_MMC=y
-+CONFIG_MMC_BLOCK_MINORS=32
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_BCM2708=y
-+CONFIG_MMC_SDHCI_BCM2708_DMA=y
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_MMC_SPI=m
-+CONFIG_LEDS_GPIO=m
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_ONESHOT=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-+CONFIG_LEDS_TRIGGER_CPU=y
-+CONFIG_LEDS_TRIGGER_GPIO=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TRANSIENT=m
-+CONFIG_LEDS_TRIGGER_CAMERA=m
-+CONFIG_RTC_CLASS=y
-+# CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_DS1307=m
-+CONFIG_RTC_DRV_DS1374=m
-+CONFIG_RTC_DRV_DS1672=m
-+CONFIG_RTC_DRV_DS3232=m
-+CONFIG_RTC_DRV_MAX6900=m
-+CONFIG_RTC_DRV_RS5C372=m
-+CONFIG_RTC_DRV_ISL1208=m
-+CONFIG_RTC_DRV_ISL12022=m
-+CONFIG_RTC_DRV_X1205=m
-+CONFIG_RTC_DRV_PCF2127=m
-+CONFIG_RTC_DRV_PCF8523=m
-+CONFIG_RTC_DRV_PCF8563=m
-+CONFIG_RTC_DRV_PCF8583=m
-+CONFIG_RTC_DRV_M41T80=m
-+CONFIG_RTC_DRV_BQ32K=m
-+CONFIG_RTC_DRV_S35390A=m
-+CONFIG_RTC_DRV_FM3130=m
-+CONFIG_RTC_DRV_RX8581=m
-+CONFIG_RTC_DRV_RX8025=m
-+CONFIG_RTC_DRV_EM3027=m
-+CONFIG_RTC_DRV_RV3029C2=m
-+CONFIG_RTC_DRV_M41T93=m
-+CONFIG_RTC_DRV_M41T94=m
-+CONFIG_RTC_DRV_DS1305=m
-+CONFIG_RTC_DRV_DS1390=m
-+CONFIG_RTC_DRV_MAX6902=m
-+CONFIG_RTC_DRV_R9701=m
-+CONFIG_RTC_DRV_RS5C348=m
-+CONFIG_RTC_DRV_DS3234=m
-+CONFIG_RTC_DRV_PCF2123=m
-+CONFIG_RTC_DRV_RX4581=m
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_BCM2708=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+CONFIG_STAGING=y
-+CONFIG_W35UND=m
-+CONFIG_PRISM2_USB=m
-+CONFIG_R8712U=m
-+CONFIG_VT6656=m
-+CONFIG_SPEAKUP=m
-+CONFIG_SPEAKUP_SYNTH_SOFT=m
-+CONFIG_STAGING_MEDIA=y
-+CONFIG_DVB_AS102=m
-+CONFIG_LIRC_STAGING=y
-+CONFIG_LIRC_IGORPLUGUSB=m
-+CONFIG_LIRC_IMON=m
-+CONFIG_LIRC_RPI=m
-+CONFIG_LIRC_SASEM=m
-+CONFIG_LIRC_SERIAL=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_FANOTIFY=y
-+CONFIG_QFMT_V1=m
-+CONFIG_QFMT_V2=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_NTFS_RW=y
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_CONFIGFS_FS=y
-+CONFIG_ECRYPT_FS=m
-+CONFIG_HFS_FS=m
-+CONFIG_HFSPLUS_FS=m
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_F2FS_FS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_SWAP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3_ACL=y
-+CONFIG_NFSD_V4=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_DLM=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_FS=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+CONFIG_TIMER_STATS=y
-+# CONFIG_DEBUG_PREEMPT is not set
-+CONFIG_LATENCYTOP=y
-+# CONFIG_KPROBE_EVENT is not set
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_STRICT_DEVMEM=y
-+CONFIG_CRYPTO_USER=m
-+CONFIG_CRYPTO_NULL=m
-+CONFIG_CRYPTO_CRYPTD=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_CTS=m
-+CONFIG_CRYPTO_XTS=m
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_SHA1_ARM=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_AES_ARM=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-diff -Nur linux-3.12.38/arch/arm/configs/bcmrpi_emergency_defconfig linux-rpi/arch/arm/configs/bcmrpi_emergency_defconfig
---- linux-3.12.38/arch/arm/configs/bcmrpi_emergency_defconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/configs/bcmrpi_emergency_defconfig 2015-03-10 17:26:49.690216697 +0100
-@@ -0,0 +1,495 @@
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_FHANDLE=y
-+CONFIG_AUDIT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_RESOURCE_COUNTERS=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_NAMESPACES=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE="../target_fs"
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_SLAB=y
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+# CONFIG_BLK_DEV_BSG is not set
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_BCM2708=y
-+CONFIG_AEABI=y
-+CONFIG_SECCOMP=y
-+CONFIG_CC_STACKPROTECTOR=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
-+CONFIG_KEXEC=y
-+CONFIG_CPU_IDLE=y
-+CONFIG_VFP=y
-+CONFIG_BINFMT_MISC=m
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_SYN_COOKIES=y
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+# CONFIG_IPV6 is not set
-+CONFIG_NET_PKTGEN=m
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_BT=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_CFG80211=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_RC_PID=y
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_NFC_PN533=m
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_SCSI_MULTI_LUN=y
-+# CONFIG_SCSI_LOWLEVEL is not set
-+CONFIG_MD=y
-+CONFIG_NETDEVICES=y
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_KC2190=y
-+# CONFIG_USB_NET_ZAURUS is not set
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_RTL8187=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_B43=m
-+CONFIG_B43LEGACY=m
-+CONFIG_HOSTAP=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RTL8192CU=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_INPUT_POLLDEV=m
-+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+# CONFIG_HW_RANDOM is not set
-+CONFIG_RAW_DRIVER=y
-+CONFIG_GPIO_SYSFS=y
-+# CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2708_WDT=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_SEQUENCER_OSS=y
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_BCM2835=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SOUND_PRIME=m
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_LED=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_MMC=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_BCM2708=y
-+CONFIG_MMC_SDHCI_BCM2708_DMA=y
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_FANOTIFY=y
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_CONFIGFS_FS=y
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_NLS_UTF8=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_INFO=y
-+CONFIG_DEBUG_STACK_USAGE=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+CONFIG_TIMER_STATS=y
-+CONFIG_LATENCYTOP=y
-+CONFIG_IRQSOFF_TRACER=y
-+CONFIG_SCHED_TRACER=y
-+CONFIG_STACK_TRACER=y
-+CONFIG_BLK_DEV_IO_TRACE=y
-+CONFIG_FUNCTION_PROFILER=y
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_STRICT_DEVMEM=y
-+CONFIG_CRYPTO_AUTHENC=m
-+CONFIG_CRYPTO_SEQIV=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_HMAC=y
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_MD5=y
-+CONFIG_CRYPTO_SHA1=y
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_DEFLATE=m
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-diff -Nur linux-3.12.38/arch/arm/configs/bcmrpi_quick_defconfig linux-rpi/arch/arm/configs/bcmrpi_quick_defconfig
---- linux-3.12.38/arch/arm/configs/bcmrpi_quick_defconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/configs/bcmrpi_quick_defconfig 2015-03-10 17:26:49.690216697 +0100
-@@ -0,0 +1,201 @@
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+CONFIG_LOCALVERSION="-quick"
-+# CONFIG_LOCALVERSION_AUTO is not set
-+# CONFIG_SWAP is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_KALLSYMS_ALL=y
-+CONFIG_EMBEDDED=y
-+CONFIG_PERF_EVENTS=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_SLAB=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+# CONFIG_BLK_DEV_BSG is not set
-+CONFIG_ARCH_BCM2708=y
-+CONFIG_PREEMPT=y
-+CONFIG_AEABI=y
-+CONFIG_CMA=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_CPU_IDLE=y
-+CONFIG_VFP=y
-+CONFIG_BINFMT_MISC=y
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_SYN_COOKIES=y
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_WIRELESS is not set
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_NET_VENDOR_BROADCOM is not set
-+# CONFIG_NET_VENDOR_CIRRUS is not set
-+# CONFIG_NET_VENDOR_FARADAY is not set
-+# CONFIG_NET_VENDOR_INTEL is not set
-+# CONFIG_NET_VENDOR_MARVELL is not set
-+# CONFIG_NET_VENDOR_MICREL is not set
-+# CONFIG_NET_VENDOR_NATSEMI is not set
-+# CONFIG_NET_VENDOR_SEEQ is not set
-+# CONFIG_NET_VENDOR_STMICRO is not set
-+# CONFIG_NET_VENDOR_WIZNET is not set
-+CONFIG_USB_USBNET=y
-+# CONFIG_USB_NET_AX8817X is not set
-+# CONFIG_USB_NET_CDCETHER is not set
-+# CONFIG_USB_NET_CDC_NCM is not set
-+CONFIG_USB_NET_SMSC95XX=y
-+# CONFIG_USB_NET_NET1080 is not set
-+# CONFIG_USB_NET_CDC_SUBSET is not set
-+# CONFIG_USB_NET_ZAURUS is not set
-+# CONFIG_WLAN is not set
-+# CONFIG_INPUT_MOUSEDEV is not set
-+CONFIG_INPUT_EVDEV=y
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_SERIO is not set
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_HW_RANDOM_BCM2708=y
-+CONFIG_RAW_DRIVER=y
-+CONFIG_THERMAL=y
-+CONFIG_THERMAL_BCM2835=y
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2708_WDT=y
-+CONFIG_REGULATOR=y
-+CONFIG_REGULATOR_DEBUG=y
-+CONFIG_REGULATOR_FIXED_VOLTAGE=y
-+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
-+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=y
-+CONFIG_SND_BCM2835=y
-+# CONFIG_SND_USB is not set
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_DWCOTG=y
-+CONFIG_MMC=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_BCM2708=y
-+CONFIG_MMC_SDHCI_BCM2708_DMA=y
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_TRIGGERS=y
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FSCACHE=y
-+CONFIG_CACHEFILES=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_CONFIGFS_FS=y
-+# CONFIG_MISC_FILESYSTEMS is not set
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=y
-+CONFIG_NLS_CODEPAGE_775=y
-+CONFIG_NLS_CODEPAGE_850=y
-+CONFIG_NLS_CODEPAGE_852=y
-+CONFIG_NLS_CODEPAGE_855=y
-+CONFIG_NLS_CODEPAGE_857=y
-+CONFIG_NLS_CODEPAGE_860=y
-+CONFIG_NLS_CODEPAGE_861=y
-+CONFIG_NLS_CODEPAGE_862=y
-+CONFIG_NLS_CODEPAGE_863=y
-+CONFIG_NLS_CODEPAGE_864=y
-+CONFIG_NLS_CODEPAGE_865=y
-+CONFIG_NLS_CODEPAGE_866=y
-+CONFIG_NLS_CODEPAGE_869=y
-+CONFIG_NLS_CODEPAGE_936=y
-+CONFIG_NLS_CODEPAGE_950=y
-+CONFIG_NLS_CODEPAGE_932=y
-+CONFIG_NLS_CODEPAGE_949=y
-+CONFIG_NLS_CODEPAGE_874=y
-+CONFIG_NLS_ISO8859_8=y
-+CONFIG_NLS_CODEPAGE_1250=y
-+CONFIG_NLS_CODEPAGE_1251=y
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=y
-+CONFIG_NLS_ISO8859_2=y
-+CONFIG_NLS_ISO8859_3=y
-+CONFIG_NLS_ISO8859_4=y
-+CONFIG_NLS_ISO8859_5=y
-+CONFIG_NLS_ISO8859_6=y
-+CONFIG_NLS_ISO8859_7=y
-+CONFIG_NLS_ISO8859_9=y
-+CONFIG_NLS_ISO8859_13=y
-+CONFIG_NLS_ISO8859_14=y
-+CONFIG_NLS_ISO8859_15=y
-+CONFIG_NLS_UTF8=y
-+CONFIG_PRINTK_TIME=y
-+CONFIG_DEBUG_FS=y
-+CONFIG_DETECT_HUNG_TASK=y
-+# CONFIG_DEBUG_PREEMPT is not set
-+# CONFIG_DEBUG_BUGVERBOSE is not set
-+# CONFIG_FTRACE is not set
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+# CONFIG_ARM_UNWIND is not set
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_HMAC=y
-+CONFIG_CRYPTO_MD5=y
-+CONFIG_CRYPTO_SHA1=y
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-diff -Nur linux-3.12.38/arch/arm/configs/multi_v7_defconfig linux-rpi/arch/arm/configs/multi_v7_defconfig
---- linux-3.12.38/arch/arm/configs/multi_v7_defconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/configs/multi_v7_defconfig 2015-03-10 17:26:49.694216697 +0100
-@@ -116,7 +116,6 @@
- CONFIG_USB=y
- CONFIG_USB_XHCI_HCD=y
- CONFIG_USB_EHCI_HCD=y
--CONFIG_USB_EHCI_EXYNOS=y
- CONFIG_USB_EHCI_TEGRA=y
- CONFIG_USB_EHCI_HCD_PLATFORM=y
- CONFIG_USB_ISP1760_HCD=y
-diff -Nur linux-3.12.38/arch/arm/crypto/aes_glue.c linux-rpi/arch/arm/crypto/aes_glue.c
---- linux-3.12.38/arch/arm/crypto/aes_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/crypto/aes_glue.c 2015-03-10 17:26:49.698216697 +0100
-@@ -103,6 +103,6 @@
-
- MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm (ASM)");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("aes");
--MODULE_ALIAS_CRYPTO("aes-asm");
-+MODULE_ALIAS("aes");
-+MODULE_ALIAS("aes-asm");
- MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
-diff -Nur linux-3.12.38/arch/arm/crypto/sha1_glue.c linux-rpi/arch/arm/crypto/sha1_glue.c
---- linux-3.12.38/arch/arm/crypto/sha1_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/crypto/sha1_glue.c 2015-03-10 17:26:49.698216697 +0100
-@@ -175,5 +175,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm (ARM)");
--MODULE_ALIAS_CRYPTO("sha1");
-+MODULE_ALIAS("sha1");
- MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
-diff -Nur linux-3.12.38/arch/arm/include/asm/irqflags.h linux-rpi/arch/arm/include/asm/irqflags.h
---- linux-3.12.38/arch/arm/include/asm/irqflags.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/include/asm/irqflags.h 2015-03-09 10:39:28.526893747 +0100
-@@ -145,12 +145,22 @@
- }
-
- /*
-- * restore saved IRQ & FIQ state
-+ * restore saved IRQ state
- */
- static inline void arch_local_irq_restore(unsigned long flags)
- {
-- asm volatile(
-- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
-+ unsigned long temp = 0;
-+ flags &= ~(1 << 6);
-+ asm volatile (
-+ " mrs %0, cpsr"
-+ : "=r" (temp)
-+ :
-+ : "memory", "cc");
-+ /* Preserve FIQ bit */
-+ temp &= (1 << 6);
-+ flags = flags | temp;
-+ asm volatile (
-+ " msr cpsr_c, %0 @ local_irq_restore"
- :
- : "r" (flags)
- : "memory", "cc");
-diff -Nur linux-3.12.38/arch/arm/include/asm/string.h linux-rpi/arch/arm/include/asm/string.h
---- linux-3.12.38/arch/arm/include/asm/string.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/include/asm/string.h 2015-03-09 10:39:28.530893747 +0100
-@@ -24,6 +24,11 @@
- #define __HAVE_ARCH_MEMSET
- extern void * memset(void *, int, __kernel_size_t);
-
-+#ifdef CONFIG_MACH_BCM2708
-+#define __HAVE_ARCH_MEMCMP
-+extern int memcmp(const void *, const void *, size_t);
-+#endif
-+
- extern void __memzero(void *ptr, __kernel_size_t n);
-
- #define memset(p,v,n) \
-diff -Nur linux-3.12.38/arch/arm/include/asm/uaccess.h linux-rpi/arch/arm/include/asm/uaccess.h
---- linux-3.12.38/arch/arm/include/asm/uaccess.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/include/asm/uaccess.h 2015-03-10 17:26:49.702216697 +0100
-@@ -427,6 +427,7 @@
-
- #ifdef CONFIG_MMU
- extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n);
-+extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n);
- extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n);
- extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n);
- extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
-diff -Nur linux-3.12.38/arch/arm/Kconfig linux-rpi/arch/arm/Kconfig
---- linux-3.12.38/arch/arm/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/Kconfig 2015-03-10 17:26:49.670216697 +0100
-@@ -369,6 +369,24 @@
- This enables support for systems based on Atmel
- AT91RM9200 and AT91SAM9* processors.
-
-+config ARCH_BCM2708
-+ bool "Broadcom BCM2708 family"
-+ select CPU_V6
-+ select ARM_AMBA
-+ select HAVE_CLK
-+ select HAVE_SCHED_CLOCK
-+ select NEED_MACH_GPIO_H
-+ select NEED_MACH_MEMORY_H
-+ select CLKDEV_LOOKUP
-+ select ARCH_HAS_CPUFREQ
-+ select GENERIC_CLOCKEVENTS
-+ select ARM_ERRATA_411920
-+ select MACH_BCM2708
-+ select VC4
-+ select FIQ
-+ help
-+ This enables support for Broadcom BCM2708 boards.
-+
- config ARCH_CLPS711X
- bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
- select ARCH_REQUIRE_GPIOLIB
-@@ -1044,6 +1062,7 @@
- source "arch/arm/mach-vt8500/Kconfig"
-
- source "arch/arm/mach-w90x900/Kconfig"
-+source "arch/arm/mach-bcm2708/Kconfig"
-
- source "arch/arm/mach-zynq/Kconfig"
-
-diff -Nur linux-3.12.38/arch/arm/Kconfig.debug linux-rpi/arch/arm/Kconfig.debug
---- linux-3.12.38/arch/arm/Kconfig.debug 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/Kconfig.debug 2015-03-10 17:26:49.670216697 +0100
-@@ -847,6 +847,14 @@
- options; the platform specific options are deprecated
- and will be soon removed.
-
-+ config DEBUG_BCM2708_UART0
-+ bool "Broadcom BCM2708 UART0 (PL011)"
-+ depends on MACH_BCM2708
-+ help
-+ Say Y here if you want the debug print routines to direct
-+ their output to UART 0. The port must have been initialised
-+ by the boot-loader before use.
-+
- endchoice
-
- config DEBUG_EXYNOS_UART
-diff -Nur linux-3.12.38/arch/arm/kernel/fiqasm.S linux-rpi/arch/arm/kernel/fiqasm.S
---- linux-3.12.38/arch/arm/kernel/fiqasm.S 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/kernel/fiqasm.S 2015-03-10 17:26:49.702216697 +0100
-@@ -47,3 +47,7 @@
- mov r0, r0 @ avoid hazard prior to ARMv4
- mov pc, lr
- ENDPROC(__get_fiq_regs)
-+
-+ENTRY(__FIQ_Branch)
-+ mov pc, r8
-+ENDPROC(__FIQ_Branch)
-diff -Nur linux-3.12.38/arch/arm/kernel/process.c linux-rpi/arch/arm/kernel/process.c
---- linux-3.12.38/arch/arm/kernel/process.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/kernel/process.c 2015-03-10 17:26:49.706216697 +0100
-@@ -176,6 +176,16 @@
- default_idle();
- }
-
-+char bcm2708_reboot_mode = 'h';
-+
-+int __init reboot_setup(char *str)
-+{
-+ bcm2708_reboot_mode = str[0];
-+ return 1;
-+}
-+
-+__setup("reboot=", reboot_setup);
-+
- /*
- * Called by kexec, immediately prior to machine_kexec().
- *
-diff -Nur linux-3.12.38/arch/arm/kernel/setup.c linux-rpi/arch/arm/kernel/setup.c
---- linux-3.12.38/arch/arm/kernel/setup.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/kernel/setup.c 2015-03-10 17:26:49.706216697 +0100
-@@ -1016,15 +1016,6 @@
- seq_printf(m, "model name\t: %s rev %d (%s)\n",
- cpu_name, cpuid & 15, elf_platform);
-
--#if defined(CONFIG_SMP)
-- seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
-- per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
-- (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
--#else
-- seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
-- loops_per_jiffy / (500000/HZ),
-- (loops_per_jiffy / (5000/HZ)) % 100);
--#endif
- /* dump out the processor features */
- seq_puts(m, "Features\t: ");
-
-diff -Nur linux-3.12.38/arch/arm/kernel/smp.c linux-rpi/arch/arm/kernel/smp.c
---- linux-3.12.38/arch/arm/kernel/smp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/kernel/smp.c 2015-03-10 17:26:49.706216697 +0100
-@@ -383,17 +383,8 @@
-
- void __init smp_cpus_done(unsigned int max_cpus)
- {
-- int cpu;
-- unsigned long bogosum = 0;
--
-- for_each_online_cpu(cpu)
-- bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
--
-- printk(KERN_INFO "SMP: Total of %d processors activated "
-- "(%lu.%02lu BogoMIPS).\n",
-- num_online_cpus(),
-- bogosum / (500000/HZ),
-- (bogosum / (5000/HZ)) % 100);
-+ printk(KERN_INFO "SMP: Total of %d processors activated.\n",
-+ num_online_cpus());
-
- hyp_mode_check();
- }
-diff -Nur linux-3.12.38/arch/arm/lib/arm-mem.h linux-rpi/arch/arm/lib/arm-mem.h
---- linux-3.12.38/arch/arm/lib/arm-mem.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/arm-mem.h 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,159 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+.macro myfunc fname
-+ .func fname
-+ .global fname
-+fname:
-+.endm
-+
-+.macro preload_leading_step1 backwards, ptr, base
-+/* If the destination is already 16-byte aligned, then we need to preload
-+ * between 0 and prefetch_distance (inclusive) cache lines ahead so there
-+ * are no gaps when the inner loop starts.
-+ */
-+ .if backwards
-+ sub ptr, base, #1
-+ bic ptr, ptr, #31
-+ .else
-+ bic ptr, base, #31
-+ .endif
-+ .set OFFSET, 0
-+ .rept prefetch_distance+1
-+ pld [ptr, #OFFSET]
-+ .if backwards
-+ .set OFFSET, OFFSET-32
-+ .else
-+ .set OFFSET, OFFSET+32
-+ .endif
-+ .endr
-+.endm
-+
-+.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp
-+/* However, if the destination is not 16-byte aligned, we may need to
-+ * preload one more cache line than that. The question we need to ask is:
-+ * are the leading bytes more than the amount by which the source
-+ * pointer will be rounded down for preloading, and if so, by how many
-+ * cache lines?
-+ */
-+ .if backwards
-+/* Here we compare against how many bytes we are into the
-+ * cache line, counting down from the highest such address.
-+ * Effectively, we want to calculate
-+ * leading_bytes = dst&15
-+ * cacheline_offset = 31-((src-leading_bytes-1)&31)
-+ * extra_needed = leading_bytes - cacheline_offset
-+ * and test if extra_needed is <= 0, or rearranging:
-+ * leading_bytes + (src-leading_bytes-1)&31 <= 31
-+ */
-+ mov tmp, base, lsl #32-5
-+ sbc tmp, tmp, leading_bytes, lsl #32-5
-+ adds tmp, tmp, leading_bytes, lsl #32-5
-+ bcc 61f
-+ pld [ptr, #-32*(prefetch_distance+1)]
-+ .else
-+/* Effectively, we want to calculate
-+ * leading_bytes = (-dst)&15
-+ * cacheline_offset = (src+leading_bytes)&31
-+ * extra_needed = leading_bytes - cacheline_offset
-+ * and test if extra_needed is <= 0.
-+ */
-+ mov tmp, base, lsl #32-5
-+ add tmp, tmp, leading_bytes, lsl #32-5
-+ rsbs tmp, tmp, leading_bytes, lsl #32-5
-+ bls 61f
-+ pld [ptr, #32*(prefetch_distance+1)]
-+ .endif
-+61:
-+.endm
-+
-+.macro preload_trailing backwards, base, remain, tmp
-+ /* We need either 0, 1 or 2 extra preloads */
-+ .if backwards
-+ rsb tmp, base, #0
-+ mov tmp, tmp, lsl #32-5
-+ .else
-+ mov tmp, base, lsl #32-5
-+ .endif
-+ adds tmp, tmp, remain, lsl #32-5
-+ adceqs tmp, tmp, #0
-+ /* The instruction above has two effects: ensures Z is only
-+ * set if C was clear (so Z indicates that both shifted quantities
-+ * were 0), and clears C if Z was set (so C indicates that the sum
-+ * of the shifted quantities was greater and not equal to 32) */
-+ beq 82f
-+ .if backwards
-+ sub tmp, base, #1
-+ bic tmp, tmp, #31
-+ .else
-+ bic tmp, base, #31
-+ .endif
-+ bcc 81f
-+ .if backwards
-+ pld [tmp, #-32*(prefetch_distance+1)]
-+81:
-+ pld [tmp, #-32*prefetch_distance]
-+ .else
-+ pld [tmp, #32*(prefetch_distance+2)]
-+81:
-+ pld [tmp, #32*(prefetch_distance+1)]
-+ .endif
-+82:
-+.endm
-+
-+.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1
-+ .if backwards
-+ sub tmp0, base, #1
-+ bic tmp0, tmp0, #31
-+ pld [tmp0]
-+ sub tmp1, base, remain, lsl #shift
-+ .else
-+ bic tmp0, base, #31
-+ pld [tmp0]
-+ add tmp1, base, remain, lsl #shift
-+ sub tmp1, tmp1, #1
-+ .endif
-+ bic tmp1, tmp1, #31
-+ cmp tmp1, tmp0
-+ beq 92f
-+ .if narrow_case
-+ /* In this case, all the data fits in either 1 or 2 cache lines */
-+ pld [tmp1]
-+ .else
-+91:
-+ .if backwards
-+ sub tmp0, tmp0, #32
-+ .else
-+ add tmp0, tmp0, #32
-+ .endif
-+ cmp tmp0, tmp1
-+ pld [tmp0]
-+ bne 91b
-+ .endif
-+92:
-+.endm
-diff -Nur linux-3.12.38/arch/arm/lib/copy_from_user.S linux-rpi/arch/arm/lib/copy_from_user.S
---- linux-3.12.38/arch/arm/lib/copy_from_user.S 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/lib/copy_from_user.S 2015-03-09 10:39:28.574893746 +0100
-@@ -84,11 +84,13 @@
-
- .text
-
--ENTRY(__copy_from_user)
-+ENTRY(__copy_from_user_std)
-+WEAK(__copy_from_user)
-
- #include "copy_template.S"
-
- ENDPROC(__copy_from_user)
-+ENDPROC(__copy_from_user_std)
-
- .pushsection .fixup,"ax"
- .align 0
-diff -Nur linux-3.12.38/arch/arm/lib/exports_rpi.c linux-rpi/arch/arm/lib/exports_rpi.c
---- linux-3.12.38/arch/arm/lib/exports_rpi.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/exports_rpi.c 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,37 @@
-+/**
-+ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+
-+EXPORT_SYMBOL(memcmp);
-diff -Nur linux-3.12.38/arch/arm/lib/Makefile linux-rpi/arch/arm/lib/Makefile
---- linux-3.12.38/arch/arm/lib/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/lib/Makefile 2015-03-10 17:26:49.710216697 +0100
-@@ -6,15 +6,24 @@
-
- lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
- csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
-- delay.o delay-loop.o findbit.o memchr.o memcpy.o \
-- memmove.o memset.o memzero.o setbit.o \
-- strchr.o strrchr.o \
-+ delay.o delay-loop.o findbit.o memchr.o memzero.o \
-+ setbit.o strchr.o strrchr.o \
- testchangebit.o testclearbit.o testsetbit.o \
- ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
- ucmpdi2.o lib1funcs.o div64.o \
- io-readsb.o io-writesb.o io-readsl.o io-writesl.o \
- call_with_stack.o
-
-+# Choose optimised implementations for Raspberry Pi
-+ifeq ($(CONFIG_MACH_BCM2708),y)
-+ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600
-+ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672
-+ obj-$(CONFIG_MODULES) += exports_rpi.o
-+ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o
-+else
-+ lib-y += memcpy.o memmove.o memset.o
-+endif
-+
- mmu-y := clear_user.o copy_page.o getuser.o putuser.o
-
- # the code in uaccess.S is not preemption safe and
-diff -Nur linux-3.12.38/arch/arm/lib/memcmp_rpi.S linux-rpi/arch/arm/lib/memcmp_rpi.S
---- linux-3.12.38/arch/arm/lib/memcmp_rpi.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/memcmp_rpi.S 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,285 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+.macro memcmp_process_head unaligned
-+ .if unaligned
-+ ldr DAT0, [S_1], #4
-+ ldr DAT1, [S_1], #4
-+ ldr DAT2, [S_1], #4
-+ ldr DAT3, [S_1], #4
-+ .else
-+ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3}
-+ .endif
-+ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7}
-+.endm
-+
-+.macro memcmp_process_tail
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ cmpeq DAT2, DAT6
-+ cmpeq DAT3, DAT7
-+ bne 200f
-+.endm
-+
-+.macro memcmp_leading_31bytes
-+ movs DAT0, OFF, lsl #31
-+ ldrmib DAT0, [S_1], #1
-+ ldrcsh DAT1, [S_1], #2
-+ ldrmib DAT4, [S_2], #1
-+ ldrcsh DAT5, [S_2], #2
-+ movpl DAT0, #0
-+ movcc DAT1, #0
-+ movpl DAT4, #0
-+ movcc DAT5, #0
-+ submi N, N, #1
-+ subcs N, N, #2
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ bne 200f
-+ movs DAT0, OFF, lsl #29
-+ ldrmi DAT0, [S_1], #4
-+ ldrcs DAT1, [S_1], #4
-+ ldrcs DAT2, [S_1], #4
-+ ldrmi DAT4, [S_2], #4
-+ ldmcsia S_2!, {DAT5, DAT6}
-+ movpl DAT0, #0
-+ movcc DAT1, #0
-+ movcc DAT2, #0
-+ movpl DAT4, #0
-+ movcc DAT5, #0
-+ movcc DAT6, #0
-+ submi N, N, #4
-+ subcs N, N, #8
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ cmpeq DAT2, DAT6
-+ bne 200f
-+ tst OFF, #16
-+ beq 105f
-+ memcmp_process_head 1
-+ sub N, N, #16
-+ memcmp_process_tail
-+105:
-+.endm
-+
-+.macro memcmp_trailing_15bytes unaligned
-+ movs N, N, lsl #29
-+ .if unaligned
-+ ldrcs DAT0, [S_1], #4
-+ ldrcs DAT1, [S_1], #4
-+ .else
-+ ldmcsia S_1!, {DAT0, DAT1}
-+ .endif
-+ ldrmi DAT2, [S_1], #4
-+ ldmcsia S_2!, {DAT4, DAT5}
-+ ldrmi DAT6, [S_2], #4
-+ movcc DAT0, #0
-+ movcc DAT1, #0
-+ movpl DAT2, #0
-+ movcc DAT4, #0
-+ movcc DAT5, #0
-+ movpl DAT6, #0
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ cmpeq DAT2, DAT6
-+ bne 200f
-+ movs N, N, lsl #2
-+ ldrcsh DAT0, [S_1], #2
-+ ldrmib DAT1, [S_1]
-+ ldrcsh DAT4, [S_2], #2
-+ ldrmib DAT5, [S_2]
-+ movcc DAT0, #0
-+ movpl DAT1, #0
-+ movcc DAT4, #0
-+ movpl DAT5, #0
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ bne 200f
-+.endm
-+
-+.macro memcmp_long_inner_loop unaligned
-+110:
-+ memcmp_process_head unaligned
-+ pld [S_2, #prefetch_distance*32 + 16]
-+ memcmp_process_tail
-+ memcmp_process_head unaligned
-+ pld [S_1, OFF]
-+ memcmp_process_tail
-+ subs N, N, #32
-+ bhs 110b
-+ /* Just before the final (prefetch_distance+1) 32-byte blocks,
-+ * deal with final preloads */
-+ preload_trailing 0, S_1, N, DAT0
-+ preload_trailing 0, S_2, N, DAT0
-+ add N, N, #(prefetch_distance+2)*32 - 16
-+120:
-+ memcmp_process_head unaligned
-+ memcmp_process_tail
-+ subs N, N, #16
-+ bhs 120b
-+ /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ memcmp_trailing_15bytes unaligned
-+199: /* Reached end without detecting a difference */
-+ mov a1, #0
-+ setend le
-+ pop {DAT1-DAT6, pc}
-+.endm
-+
-+.macro memcmp_short_inner_loop unaligned
-+ subs N, N, #16 /* simplifies inner loop termination */
-+ blo 122f
-+120:
-+ memcmp_process_head unaligned
-+ memcmp_process_tail
-+ subs N, N, #16
-+ bhs 120b
-+122: /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ memcmp_trailing_15bytes unaligned
-+199: /* Reached end without detecting a difference */
-+ mov a1, #0
-+ setend le
-+ pop {DAT1-DAT6, pc}
-+.endm
-+
-+/*
-+ * int memcmp(const void *s1, const void *s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to buffer 1
-+ * a2 = pointer to buffer 2
-+ * a3 = number of bytes to compare (as unsigned chars)
-+ * On exit:
-+ * a1 = >0/=0/<0 if s1 >/=/< s2
-+ */
-+
-+.set prefetch_distance, 2
-+
-+ENTRY(memcmp)
-+ S_1 .req a1
-+ S_2 .req a2
-+ N .req a3
-+ DAT0 .req a4
-+ DAT1 .req v1
-+ DAT2 .req v2
-+ DAT3 .req v3
-+ DAT4 .req v4
-+ DAT5 .req v5
-+ DAT6 .req v6
-+ DAT7 .req ip
-+ OFF .req lr
-+
-+ push {DAT1-DAT6, lr}
-+ setend be /* lowest-addressed bytes are most significant */
-+
-+ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
-+ cmp N, #(prefetch_distance+3)*32 - 1
-+ blo 170f
-+
-+ /* Long case */
-+ /* Adjust N so that the decrement instruction can also test for
-+ * inner loop termination. We want it to stop when there are
-+ * (prefetch_distance+1) complete blocks to go. */
-+ sub N, N, #(prefetch_distance+2)*32
-+ preload_leading_step1 0, DAT0, S_1
-+ preload_leading_step1 0, DAT1, S_2
-+ tst S_2, #31
-+ beq 154f
-+ rsb OFF, S_2, #0 /* no need to AND with 15 here */
-+ preload_leading_step2 0, DAT0, S_1, OFF, DAT2
-+ preload_leading_step2 0, DAT1, S_2, OFF, DAT2
-+ memcmp_leading_31bytes
-+154: /* Second source now cacheline (32-byte) aligned; we have at
-+ * least one prefetch to go. */
-+ /* Prefetch offset is best selected such that it lies in the
-+ * first 8 of each 32 bytes - but it's just as easy to aim for
-+ * the first one */
-+ and OFF, S_1, #31
-+ rsb OFF, OFF, #32*prefetch_distance
-+ tst S_1, #3
-+ bne 140f
-+ memcmp_long_inner_loop 0
-+140: memcmp_long_inner_loop 1
-+
-+170: /* Short case */
-+ teq N, #0
-+ beq 199f
-+ preload_all 0, 0, 0, S_1, N, DAT0, DAT1
-+ preload_all 0, 0, 0, S_2, N, DAT0, DAT1
-+ tst S_2, #3
-+ beq 174f
-+172: subs N, N, #1
-+ blo 199f
-+ ldrb DAT0, [S_1], #1
-+ ldrb DAT4, [S_2], #1
-+ cmp DAT0, DAT4
-+ bne 200f
-+ tst S_2, #3
-+ bne 172b
-+174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */
-+ tst S_1, #3
-+ bne 140f
-+ memcmp_short_inner_loop 0
-+140: memcmp_short_inner_loop 1
-+
-+200: /* Difference found: determine sign. */
-+ movhi a1, #1
-+ movlo a1, #-1
-+ setend le
-+ pop {DAT1-DAT6, pc}
-+
-+ .unreq S_1
-+ .unreq S_2
-+ .unreq N
-+ .unreq DAT0
-+ .unreq DAT1
-+ .unreq DAT2
-+ .unreq DAT3
-+ .unreq DAT4
-+ .unreq DAT5
-+ .unreq DAT6
-+ .unreq DAT7
-+ .unreq OFF
-+ENDPROC(memcmp)
-diff -Nur linux-3.12.38/arch/arm/lib/memcpymove.h linux-rpi/arch/arm/lib/memcpymove.h
---- linux-3.12.38/arch/arm/lib/memcpymove.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/memcpymove.h 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,506 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8
-+ .if words == 1
-+ .if backwards
-+ mov r1, r0, lsl #32-align*8
-+ ldr r0, [S, #-4]!
-+ orr r1, r1, r0, lsr #align*8
-+ str r1, [D, #-4]!
-+ .else
-+ mov r0, r1, lsr #align*8
-+ ldr r1, [S, #4]!
-+ orr r0, r0, r1, lsl #32-align*8
-+ str r0, [D], #4
-+ .endif
-+ .elseif words == 2
-+ .if backwards
-+ ldr r1, [S, #-4]!
-+ mov r2, r0, lsl #32-align*8
-+ ldr r0, [S, #-4]!
-+ orr r2, r2, r1, lsr #align*8
-+ mov r1, r1, lsl #32-align*8
-+ orr r1, r1, r0, lsr #align*8
-+ stmdb D!, {r1, r2}
-+ .else
-+ ldr r1, [S, #4]!
-+ mov r0, r2, lsr #align*8
-+ ldr r2, [S, #4]!
-+ orr r0, r0, r1, lsl #32-align*8
-+ mov r1, r1, lsr #align*8
-+ orr r1, r1, r2, lsl #32-align*8
-+ stmia D!, {r0, r1}
-+ .endif
-+ .elseif words == 4
-+ .if backwards
-+ ldmdb S!, {r2, r3}
-+ mov r4, r0, lsl #32-align*8
-+ ldmdb S!, {r0, r1}
-+ orr r4, r4, r3, lsr #align*8
-+ mov r3, r3, lsl #32-align*8
-+ orr r3, r3, r2, lsr #align*8
-+ mov r2, r2, lsl #32-align*8
-+ orr r2, r2, r1, lsr #align*8
-+ mov r1, r1, lsl #32-align*8
-+ orr r1, r1, r0, lsr #align*8
-+ stmdb D!, {r1, r2, r3, r4}
-+ .else
-+ ldmib S!, {r1, r2}
-+ mov r0, r4, lsr #align*8
-+ ldmib S!, {r3, r4}
-+ orr r0, r0, r1, lsl #32-align*8
-+ mov r1, r1, lsr #align*8
-+ orr r1, r1, r2, lsl #32-align*8
-+ mov r2, r2, lsr #align*8
-+ orr r2, r2, r3, lsl #32-align*8
-+ mov r3, r3, lsr #align*8
-+ orr r3, r3, r4, lsl #32-align*8
-+ stmia D!, {r0, r1, r2, r3}
-+ .endif
-+ .elseif words == 8
-+ .if backwards
-+ ldmdb S!, {r4, r5, r6, r7}
-+ mov r8, r0, lsl #32-align*8
-+ ldmdb S!, {r0, r1, r2, r3}
-+ .if use_pld
-+ pld [S, OFF]
-+ .endif
-+ orr r8, r8, r7, lsr #align*8
-+ mov r7, r7, lsl #32-align*8
-+ orr r7, r7, r6, lsr #align*8
-+ mov r6, r6, lsl #32-align*8
-+ orr r6, r6, r5, lsr #align*8
-+ mov r5, r5, lsl #32-align*8
-+ orr r5, r5, r4, lsr #align*8
-+ mov r4, r4, lsl #32-align*8
-+ orr r4, r4, r3, lsr #align*8
-+ mov r3, r3, lsl #32-align*8
-+ orr r3, r3, r2, lsr #align*8
-+ mov r2, r2, lsl #32-align*8
-+ orr r2, r2, r1, lsr #align*8
-+ mov r1, r1, lsl #32-align*8
-+ orr r1, r1, r0, lsr #align*8
-+ stmdb D!, {r5, r6, r7, r8}
-+ stmdb D!, {r1, r2, r3, r4}
-+ .else
-+ ldmib S!, {r1, r2, r3, r4}
-+ mov r0, r8, lsr #align*8
-+ ldmib S!, {r5, r6, r7, r8}
-+ .if use_pld
-+ pld [S, OFF]
-+ .endif
-+ orr r0, r0, r1, lsl #32-align*8
-+ mov r1, r1, lsr #align*8
-+ orr r1, r1, r2, lsl #32-align*8
-+ mov r2, r2, lsr #align*8
-+ orr r2, r2, r3, lsl #32-align*8
-+ mov r3, r3, lsr #align*8
-+ orr r3, r3, r4, lsl #32-align*8
-+ mov r4, r4, lsr #align*8
-+ orr r4, r4, r5, lsl #32-align*8
-+ mov r5, r5, lsr #align*8
-+ orr r5, r5, r6, lsl #32-align*8
-+ mov r6, r6, lsr #align*8
-+ orr r6, r6, r7, lsl #32-align*8
-+ mov r7, r7, lsr #align*8
-+ orr r7, r7, r8, lsl #32-align*8
-+ stmia D!, {r0, r1, r2, r3}
-+ stmia D!, {r4, r5, r6, r7}
-+ .endif
-+ .endif
-+.endm
-+
-+.macro memcpy_leading_15bytes backwards, align
-+ movs DAT1, DAT2, lsl #31
-+ sub N, N, DAT2
-+ .if backwards
-+ ldrmib DAT0, [S, #-1]!
-+ ldrcsh DAT1, [S, #-2]!
-+ strmib DAT0, [D, #-1]!
-+ strcsh DAT1, [D, #-2]!
-+ .else
-+ ldrmib DAT0, [S], #1
-+ ldrcsh DAT1, [S], #2
-+ strmib DAT0, [D], #1
-+ strcsh DAT1, [D], #2
-+ .endif
-+ movs DAT1, DAT2, lsl #29
-+ .if backwards
-+ ldrmi DAT0, [S, #-4]!
-+ .if align == 0
-+ ldmcsdb S!, {DAT1, DAT2}
-+ .else
-+ ldrcs DAT2, [S, #-4]!
-+ ldrcs DAT1, [S, #-4]!
-+ .endif
-+ strmi DAT0, [D, #-4]!
-+ stmcsdb D!, {DAT1, DAT2}
-+ .else
-+ ldrmi DAT0, [S], #4
-+ .if align == 0
-+ ldmcsia S!, {DAT1, DAT2}
-+ .else
-+ ldrcs DAT1, [S], #4
-+ ldrcs DAT2, [S], #4
-+ .endif
-+ strmi DAT0, [D], #4
-+ stmcsia D!, {DAT1, DAT2}
-+ .endif
-+.endm
-+
-+.macro memcpy_trailing_15bytes backwards, align
-+ movs N, N, lsl #29
-+ .if backwards
-+ .if align == 0
-+ ldmcsdb S!, {DAT0, DAT1}
-+ .else
-+ ldrcs DAT1, [S, #-4]!
-+ ldrcs DAT0, [S, #-4]!
-+ .endif
-+ ldrmi DAT2, [S, #-4]!
-+ stmcsdb D!, {DAT0, DAT1}
-+ strmi DAT2, [D, #-4]!
-+ .else
-+ .if align == 0
-+ ldmcsia S!, {DAT0, DAT1}
-+ .else
-+ ldrcs DAT0, [S], #4
-+ ldrcs DAT1, [S], #4
-+ .endif
-+ ldrmi DAT2, [S], #4
-+ stmcsia D!, {DAT0, DAT1}
-+ strmi DAT2, [D], #4
-+ .endif
-+ movs N, N, lsl #2
-+ .if backwards
-+ ldrcsh DAT0, [S, #-2]!
-+ ldrmib DAT1, [S, #-1]
-+ strcsh DAT0, [D, #-2]!
-+ strmib DAT1, [D, #-1]
-+ .else
-+ ldrcsh DAT0, [S], #2
-+ ldrmib DAT1, [S]
-+ strcsh DAT0, [D], #2
-+ strmib DAT1, [D]
-+ .endif
-+.endm
-+
-+.macro memcpy_long_inner_loop backwards, align
-+ .if align != 0
-+ .if backwards
-+ ldr DAT0, [S, #-align]!
-+ .else
-+ ldr LAST, [S, #-align]!
-+ .endif
-+ .endif
-+110:
-+ .if align == 0
-+ .if backwards
-+ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ pld [S, OFF]
-+ stmdb D!, {DAT4, DAT5, DAT6, LAST}
-+ stmdb D!, {DAT0, DAT1, DAT2, DAT3}
-+ .else
-+ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ pld [S, OFF]
-+ stmia D!, {DAT0, DAT1, DAT2, DAT3}
-+ stmia D!, {DAT4, DAT5, DAT6, LAST}
-+ .endif
-+ .else
-+ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
-+ .endif
-+ subs N, N, #32
-+ bhs 110b
-+ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */
-+ preload_trailing backwards, S, N, OFF
-+ add N, N, #(prefetch_distance+2)*32 - 32
-+120:
-+ .if align == 0
-+ .if backwards
-+ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ stmdb D!, {DAT4, DAT5, DAT6, LAST}
-+ stmdb D!, {DAT0, DAT1, DAT2, DAT3}
-+ .else
-+ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ stmia D!, {DAT0, DAT1, DAT2, DAT3}
-+ stmia D!, {DAT4, DAT5, DAT6, LAST}
-+ .endif
-+ .else
-+ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
-+ .endif
-+ subs N, N, #32
-+ bhs 120b
-+ tst N, #16
-+ .if align == 0
-+ .if backwards
-+ ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
-+ stmnedb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldmneia S!, {DAT0, DAT1, DAT2, LAST}
-+ stmneia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+ .else
-+ beq 130f
-+ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST
-+130:
-+ .endif
-+ /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ .if align != 0
-+ add S, S, #align
-+ .endif
-+ memcpy_trailing_15bytes backwards, align
-+199:
-+ pop {DAT3, DAT4, DAT5, DAT6, DAT7}
-+ pop {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy_medium_inner_loop backwards, align
-+120:
-+ .if backwards
-+ .if align == 0
-+ ldmdb S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldr LAST, [S, #-4]!
-+ ldr DAT2, [S, #-4]!
-+ ldr DAT1, [S, #-4]!
-+ ldr DAT0, [S, #-4]!
-+ .endif
-+ stmdb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ .if align == 0
-+ ldmia S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldr DAT0, [S], #4
-+ ldr DAT1, [S], #4
-+ ldr DAT2, [S], #4
-+ ldr LAST, [S], #4
-+ .endif
-+ stmia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+ subs N, N, #16
-+ bhs 120b
-+ /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ memcpy_trailing_15bytes backwards, align
-+199:
-+ pop {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy_short_inner_loop backwards, align
-+ tst N, #16
-+ .if backwards
-+ .if align == 0
-+ ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldrne LAST, [S, #-4]!
-+ ldrne DAT2, [S, #-4]!
-+ ldrne DAT1, [S, #-4]!
-+ ldrne DAT0, [S, #-4]!
-+ .endif
-+ stmnedb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ .if align == 0
-+ ldmneia S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldrne DAT0, [S], #4
-+ ldrne DAT1, [S], #4
-+ ldrne DAT2, [S], #4
-+ ldrne LAST, [S], #4
-+ .endif
-+ stmneia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+ memcpy_trailing_15bytes backwards, align
-+199:
-+ pop {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy backwards
-+ D .req a1
-+ S .req a2
-+ N .req a3
-+ DAT0 .req a4
-+ DAT1 .req v1
-+ DAT2 .req v2
-+ DAT3 .req v3
-+ DAT4 .req v4
-+ DAT5 .req v5
-+ DAT6 .req v6
-+ DAT7 .req sl
-+ LAST .req ip
-+ OFF .req lr
-+
-+ .cfi_startproc
-+
-+ push {D, DAT1, DAT2, lr}
-+
-+ .cfi_def_cfa_offset 16
-+ .cfi_rel_offset D, 0
-+ .cfi_undefined S
-+ .cfi_undefined N
-+ .cfi_undefined DAT0
-+ .cfi_rel_offset DAT1, 4
-+ .cfi_rel_offset DAT2, 8
-+ .cfi_undefined LAST
-+ .cfi_rel_offset lr, 12
-+
-+ .if backwards
-+ add D, D, N
-+ add S, S, N
-+ .endif
-+
-+ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
-+ cmp N, #31
-+ blo 170f
-+ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
-+ cmp N, #(prefetch_distance+3)*32 - 1
-+ blo 160f
-+
-+ /* Long case */
-+ push {DAT3, DAT4, DAT5, DAT6, DAT7}
-+
-+ .cfi_def_cfa_offset 36
-+ .cfi_rel_offset D, 20
-+ .cfi_rel_offset DAT1, 24
-+ .cfi_rel_offset DAT2, 28
-+ .cfi_rel_offset DAT3, 0
-+ .cfi_rel_offset DAT4, 4
-+ .cfi_rel_offset DAT5, 8
-+ .cfi_rel_offset DAT6, 12
-+ .cfi_rel_offset DAT7, 16
-+ .cfi_rel_offset lr, 32
-+
-+ /* Adjust N so that the decrement instruction can also test for
-+ * inner loop termination. We want it to stop when there are
-+ * (prefetch_distance+1) complete blocks to go. */
-+ sub N, N, #(prefetch_distance+2)*32
-+ preload_leading_step1 backwards, DAT0, S
-+ .if backwards
-+ /* Bug in GAS: it accepts, but mis-assembles the instruction
-+ * ands DAT2, D, #60, 2
-+ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow)
-+ */
-+ .word 0xE210513C
-+ beq 154f
-+ .else
-+ ands DAT2, D, #15
-+ beq 154f
-+ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */
-+ .endif
-+ preload_leading_step2 backwards, DAT0, S, DAT2, OFF
-+ memcpy_leading_15bytes backwards, 1
-+154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */
-+ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */
-+ .if backwards
-+ rsb OFF, S, #3
-+ and OFF, OFF, #28
-+ sub OFF, OFF, #32*(prefetch_distance+1)
-+ .else
-+ and OFF, S, #28
-+ rsb OFF, OFF, #32*prefetch_distance
-+ .endif
-+ movs DAT0, S, lsl #31
-+ bhi 157f
-+ bcs 156f
-+ bmi 155f
-+ memcpy_long_inner_loop backwards, 0
-+155: memcpy_long_inner_loop backwards, 1
-+156: memcpy_long_inner_loop backwards, 2
-+157: memcpy_long_inner_loop backwards, 3
-+
-+ .cfi_def_cfa_offset 16
-+ .cfi_rel_offset D, 0
-+ .cfi_rel_offset DAT1, 4
-+ .cfi_rel_offset DAT2, 8
-+ .cfi_same_value DAT3
-+ .cfi_same_value DAT4
-+ .cfi_same_value DAT5
-+ .cfi_same_value DAT6
-+ .cfi_same_value DAT7
-+ .cfi_rel_offset lr, 12
-+
-+160: /* Medium case */
-+ preload_all backwards, 0, 0, S, N, DAT2, OFF
-+ sub N, N, #16 /* simplifies inner loop termination */
-+ .if backwards
-+ ands DAT2, D, #15
-+ beq 164f
-+ .else
-+ ands DAT2, D, #15
-+ beq 164f
-+ rsb DAT2, DAT2, #16
-+ .endif
-+ memcpy_leading_15bytes backwards, align
-+164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */
-+ tst S, #3
-+ bne 140f
-+ memcpy_medium_inner_loop backwards, 0
-+140: memcpy_medium_inner_loop backwards, 1
-+
-+170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */
-+ teq N, #0
-+ beq 199f
-+ preload_all backwards, 1, 0, S, N, DAT2, LAST
-+ tst D, #3
-+ beq 174f
-+172: subs N, N, #1
-+ blo 199f
-+ .if backwards
-+ ldrb DAT0, [S, #-1]!
-+ strb DAT0, [D, #-1]!
-+ .else
-+ ldrb DAT0, [S], #1
-+ strb DAT0, [D], #1
-+ .endif
-+ tst D, #3
-+ bne 172b
-+174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */
-+ tst S, #3
-+ bne 140f
-+ memcpy_short_inner_loop backwards, 0
-+140: memcpy_short_inner_loop backwards, 1
-+
-+ .cfi_endproc
-+
-+ .unreq D
-+ .unreq S
-+ .unreq N
-+ .unreq DAT0
-+ .unreq DAT1
-+ .unreq DAT2
-+ .unreq DAT3
-+ .unreq DAT4
-+ .unreq DAT5
-+ .unreq DAT6
-+ .unreq DAT7
-+ .unreq LAST
-+ .unreq OFF
-+.endm
-diff -Nur linux-3.12.38/arch/arm/lib/memcpy_rpi.S linux-rpi/arch/arm/lib/memcpy_rpi.S
---- linux-3.12.38/arch/arm/lib/memcpy_rpi.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/memcpy_rpi.S 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,59 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+#include "memcpymove.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+/*
-+ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to destination
-+ * a2 = pointer to source
-+ * a3 = number of bytes to copy
-+ * On exit:
-+ * a1 preserved
-+ */
-+
-+.set prefetch_distance, 3
-+
-+ENTRY(memcpy)
-+ memcpy 0
-+ENDPROC(memcpy)
-diff -Nur linux-3.12.38/arch/arm/lib/memmove_rpi.S linux-rpi/arch/arm/lib/memmove_rpi.S
---- linux-3.12.38/arch/arm/lib/memmove_rpi.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/memmove_rpi.S 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,61 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+#include "memcpymove.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+/*
-+ * void *memmove(void *s1, const void *s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to destination
-+ * a2 = pointer to source
-+ * a3 = number of bytes to copy
-+ * On exit:
-+ * a1 preserved
-+ */
-+
-+.set prefetch_distance, 3
-+
-+ENTRY(memmove)
-+ cmp a2, a1
-+ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */
-+ memcpy 1
-+ENDPROC(memmove)
-diff -Nur linux-3.12.38/arch/arm/lib/memset_rpi.S linux-rpi/arch/arm/lib/memset_rpi.S
---- linux-3.12.38/arch/arm/lib/memset_rpi.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/lib/memset_rpi.S 2015-03-09 10:39:28.574893746 +0100
-@@ -0,0 +1,121 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+/*
-+ * void *memset(void *s, int c, size_t n);
-+ * On entry:
-+ * a1 = pointer to buffer to fill
-+ * a2 = byte pattern to fill with (caller-narrowed)
-+ * a3 = number of bytes to fill
-+ * On exit:
-+ * a1 preserved
-+ */
-+ENTRY(memset)
-+ S .req a1
-+ DAT0 .req a2
-+ N .req a3
-+ DAT1 .req a4
-+ DAT2 .req ip
-+ DAT3 .req lr
-+
-+ orr DAT0, DAT0, lsl #8
-+ push {S, lr}
-+ orr DAT0, DAT0, lsl #16
-+ mov DAT1, DAT0
-+
-+ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
-+ cmp N, #31
-+ blo 170f
-+
-+161: sub N, N, #16 /* simplifies inner loop termination */
-+ /* Leading words and bytes */
-+ tst S, #15
-+ beq 164f
-+ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */
-+ movs DAT2, DAT3, lsl #31
-+ submi N, N, #1
-+ strmib DAT0, [S], #1
-+ subcs N, N, #2
-+ strcsh DAT0, [S], #2
-+ movs DAT2, DAT3, lsl #29
-+ submi N, N, #4
-+ strmi DAT0, [S], #4
-+ subcs N, N, #8
-+ stmcsia S!, {DAT0, DAT1}
-+164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */
-+ mov DAT2, DAT0
-+ mov DAT3, DAT0
-+ /* Now the inner loop of 16-byte stores */
-+165: stmia S!, {DAT0, DAT1, DAT2, DAT3}
-+ subs N, N, #16
-+ bhs 165b
-+166: /* Trailing words and bytes */
-+ movs N, N, lsl #29
-+ stmcsia S!, {DAT0, DAT1}
-+ strmi DAT0, [S], #4
-+ movs N, N, lsl #2
-+ strcsh DAT0, [S], #2
-+ strmib DAT0, [S]
-+199: pop {S, pc}
-+
-+170: /* Short case */
-+ mov DAT2, DAT0
-+ mov DAT3, DAT0
-+ tst S, #3
-+ beq 174f
-+172: subs N, N, #1
-+ blo 199b
-+ strb DAT0, [S], #1
-+ tst S, #3
-+ bne 172b
-+174: tst N, #16
-+ stmneia S!, {DAT0, DAT1, DAT2, DAT3}
-+ b 166b
-+
-+ .unreq S
-+ .unreq DAT0
-+ .unreq N
-+ .unreq DAT1
-+ .unreq DAT2
-+ .unreq DAT3
-+ENDPROC(memset)
-diff -Nur linux-3.12.38/arch/arm/lib/uaccess_with_memcpy.c linux-rpi/arch/arm/lib/uaccess_with_memcpy.c
---- linux-3.12.38/arch/arm/lib/uaccess_with_memcpy.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/lib/uaccess_with_memcpy.c 2015-03-10 17:26:49.710216697 +0100
-@@ -21,6 +21,14 @@
- #include <asm/current.h>
- #include <asm/page.h>
-
-+#ifndef COPY_FROM_USER_THRESHOLD
-+#define COPY_FROM_USER_THRESHOLD 64
-+#endif
-+
-+#ifndef COPY_TO_USER_THRESHOLD
-+#define COPY_TO_USER_THRESHOLD 64
-+#endif
-+
- static int
- pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
- {
-@@ -56,7 +64,44 @@
- return 1;
- }
-
--static unsigned long noinline
-+static int
-+pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
-+{
-+ unsigned long addr = (unsigned long)_addr;
-+ pgd_t *pgd;
-+ pmd_t *pmd;
-+ pte_t *pte;
-+ pud_t *pud;
-+ spinlock_t *ptl;
-+
-+ pgd = pgd_offset(current->mm, addr);
-+ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))
-+ {
-+ return 0;
-+ }
-+ pud = pud_offset(pgd, addr);
-+ if (unlikely(pud_none(*pud) || pud_bad(*pud)))
-+ {
-+ return 0;
-+ }
-+
-+ pmd = pmd_offset(pud, addr);
-+ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))
-+ return 0;
-+
-+ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl);
-+ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) {
-+ pte_unmap_unlock(pte, ptl);
-+ return 0;
-+ }
-+
-+ *ptep = pte;
-+ *ptlp = ptl;
-+
-+ return 1;
-+}
-+
-+unsigned long noinline
- __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)
- {
- int atomic;
-@@ -103,6 +148,54 @@
- return n;
- }
-
-+unsigned long noinline
-+__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n)
-+{
-+ int atomic;
-+
-+ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) {
-+ memcpy(to, (const void *)from, n);
-+ return 0;
-+ }
-+
-+ /* the mmap semaphore is taken only if not in an atomic context */
-+ atomic = in_atomic();
-+
-+ if (!atomic)
-+ down_read(&current->mm->mmap_sem);
-+ while (n) {
-+ pte_t *pte;
-+ spinlock_t *ptl;
-+ int tocopy;
-+
-+ while (!pin_page_for_read(from, &pte, &ptl)) {
-+ char temp;
-+ if (!atomic)
-+ up_read(&current->mm->mmap_sem);
-+ if (__get_user(temp, (char __user *)from))
-+ goto out;
-+ if (!atomic)
-+ down_read(&current->mm->mmap_sem);
-+ }
-+
-+ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1;
-+ if (tocopy > n)
-+ tocopy = n;
-+
-+ memcpy(to, (const void *)from, tocopy);
-+ to += tocopy;
-+ from += tocopy;
-+ n -= tocopy;
-+
-+ pte_unmap_unlock(pte, ptl);
-+ }
-+ if (!atomic)
-+ up_read(&current->mm->mmap_sem);
-+
-+out:
-+ return n;
-+}
-+
- unsigned long
- __copy_to_user(void __user *to, const void *from, unsigned long n)
- {
-@@ -113,10 +206,25 @@
- * With frame pointer disabled, tail call optimization kicks in
- * as well making this test almost invisible.
- */
-- if (n < 64)
-+ if (n < COPY_TO_USER_THRESHOLD)
- return __copy_to_user_std(to, from, n);
- return __copy_to_user_memcpy(to, from, n);
- }
-+
-+unsigned long
-+__copy_from_user(void *to, const void __user *from, unsigned long n)
-+{
-+ /*
-+ * This test is stubbed out of the main function above to keep
-+ * the overhead for small copies low by avoiding a large
-+ * register dump on the stack just to reload them right away.
-+ * With frame pointer disabled, tail call optimization kicks in
-+ * as well making this test almost invisible.
-+ */
-+ if (n < COPY_FROM_USER_THRESHOLD)
-+ return __copy_from_user_std(to, from, n);
-+ return __copy_from_user_memcpy(to, from, n);
-+}
-
- static unsigned long noinline
- __clear_user_memset(void __user *addr, unsigned long n)
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/armctrl.c linux-rpi/arch/arm/mach-bcm2708/armctrl.c
---- linux-3.12.38/arch/arm/mach-bcm2708/armctrl.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/armctrl.c 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,219 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/armctrl.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/init.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/version.h>
-+#include <linux/syscore_ops.h>
-+#include <linux/interrupt.h>
-+
-+#include <asm/mach/irq.h>
-+#include <mach/hardware.h>
-+#include "armctrl.h"
-+
-+/* For support of kernels >= 3.0 assume only one VIC for now*/
-+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
-+ INTERRUPT_VC_JPEG,
-+ INTERRUPT_VC_USB,
-+ INTERRUPT_VC_3D,
-+ INTERRUPT_VC_DMA2,
-+ INTERRUPT_VC_DMA3,
-+ INTERRUPT_VC_I2C,
-+ INTERRUPT_VC_SPI,
-+ INTERRUPT_VC_I2SPCM,
-+ INTERRUPT_VC_SDIO,
-+ INTERRUPT_VC_UART,
-+ INTERRUPT_VC_ARASANSDIO
-+};
-+
-+static void armctrl_mask_irq(struct irq_data *d)
-+{
-+ static const unsigned int disables[4] = {
-+ ARM_IRQ_DIBL1,
-+ ARM_IRQ_DIBL2,
-+ ARM_IRQ_DIBL3,
-+ 0
-+ };
-+
-+ if (d->irq >= FIQ_START) {
-+ writel(0, __io_address(ARM_IRQ_FAST));
-+ } else {
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
-+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
-+ }
-+}
-+
-+static void armctrl_unmask_irq(struct irq_data *d)
-+{
-+ static const unsigned int enables[4] = {
-+ ARM_IRQ_ENBL1,
-+ ARM_IRQ_ENBL2,
-+ ARM_IRQ_ENBL3,
-+ 0
-+ };
-+
-+ if (d->irq >= FIQ_START) {
-+ unsigned int data =
-+ (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
-+ writel(0x80 | data, __io_address(ARM_IRQ_FAST));
-+ } else {
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
-+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
-+ }
-+}
-+
-+#if defined(CONFIG_PM)
-+
-+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
-+
-+/* Static defines
-+ * struct armctrl_device - VIC PM device (< 3.xx)
-+ * @sysdev: The system device which is registered. (< 3.xx)
-+ * @irq: The IRQ number for the base of the VIC.
-+ * @base: The register base for the VIC.
-+ * @resume_sources: A bitmask of interrupts for resume.
-+ * @resume_irqs: The IRQs enabled for resume.
-+ * @int_select: Save for VIC_INT_SELECT.
-+ * @int_enable: Save for VIC_INT_ENABLE.
-+ * @soft_int: Save for VIC_INT_SOFT.
-+ * @protect: Save for VIC_PROTECT.
-+ */
-+struct armctrl_info {
-+ void __iomem *base;
-+ int irq;
-+ u32 resume_sources;
-+ u32 resume_irqs;
-+ u32 int_select;
-+ u32 int_enable;
-+ u32 soft_int;
-+ u32 protect;
-+} armctrl;
-+
-+static int armctrl_suspend(void)
-+{
-+ return 0;
-+}
-+
-+static void armctrl_resume(void)
-+{
-+ return;
-+}
-+
-+/**
-+ * armctrl_pm_register - Register a VIC for later power management control
-+ * @base: The base address of the VIC.
-+ * @irq: The base IRQ for the VIC.
-+ * @resume_sources: bitmask of interrupts allowed for resume sources.
-+ *
-+ * For older kernels (< 3.xx) do -
-+ * Register the VIC with the system device tree so that it can be notified
-+ * of suspend and resume requests and ensure that the correct actions are
-+ * taken to re-instate the settings on resume.
-+ */
-+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
-+ u32 resume_sources)
-+{
-+ armctrl.base = base;
-+ armctrl.resume_sources = resume_sources;
-+ armctrl.irq = irq;
-+}
-+
-+static int armctrl_set_wake(struct irq_data *d, unsigned int on)
-+{
-+ unsigned int off = d->irq & 31;
-+ u32 bit = 1 << off;
-+
-+ if (!(bit & armctrl.resume_sources))
-+ return -EINVAL;
-+
-+ if (on)
-+ armctrl.resume_irqs |= bit;
-+ else
-+ armctrl.resume_irqs &= ~bit;
-+
-+ return 0;
-+}
-+
-+#else
-+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
-+ u32 arg1)
-+{
-+}
-+
-+#define armctrl_suspend NULL
-+#define armctrl_resume NULL
-+#define armctrl_set_wake NULL
-+#endif /* CONFIG_PM */
-+
-+static struct syscore_ops armctrl_syscore_ops = {
-+ .suspend = armctrl_suspend,
-+ .resume = armctrl_resume,
-+};
-+
-+/**
-+ * armctrl_syscore_init - initicall to register VIC pm functions
-+ *
-+ * This is called via late_initcall() to register
-+ * the resources for the VICs due to the early
-+ * nature of the VIC's registration.
-+*/
-+static int __init armctrl_syscore_init(void)
-+{
-+ register_syscore_ops(&armctrl_syscore_ops);
-+ return 0;
-+}
-+
-+late_initcall(armctrl_syscore_init);
-+
-+static struct irq_chip armctrl_chip = {
-+ .name = "ARMCTRL",
-+ .irq_ack = NULL,
-+ .irq_mask = armctrl_mask_irq,
-+ .irq_unmask = armctrl_unmask_irq,
-+ .irq_set_wake = armctrl_set_wake,
-+};
-+
-+/**
-+ * armctrl_init - initialise a vectored interrupt controller
-+ * @base: iomem base address
-+ * @irq_start: starting interrupt number, must be muliple of 32
-+ * @armctrl_sources: bitmask of interrupt sources to allow
-+ * @resume_sources: bitmask of interrupt sources to allow for resume
-+ */
-+int __init armctrl_init(void __iomem * base, unsigned int irq_start,
-+ u32 armctrl_sources, u32 resume_sources)
-+{
-+ unsigned int irq;
-+
-+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
-+ unsigned int data = irq;
-+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
-+ data = remap_irqs[irq - INTERRUPT_JPEG];
-+
-+ irq_set_chip(irq, &armctrl_chip);
-+ irq_set_chip_data(irq, (void *)data);
-+ irq_set_handler(irq, handle_level_irq);
-+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
-+ }
-+
-+ armctrl_pm_register(base, irq_start, resume_sources);
-+ init_FIQ(FIQ_START);
-+ return 0;
-+}
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/armctrl.h linux-rpi/arch/arm/mach-bcm2708/armctrl.h
---- linux-3.12.38/arch/arm/mach-bcm2708/armctrl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/armctrl.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,27 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/armctrl.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_ARMCTRL_H
-+#define __BCM2708_ARMCTRL_H
-+
-+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
-+ u32 armctrl_sources, u32 resume_sources);
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/bcm2708.c linux-rpi/arch/arm/mach-bcm2708/bcm2708.c
---- linux-3.12.38/arch/arm/mach-bcm2708/bcm2708.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.c 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,1139 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/serial_8250.h>
-+#include <linux/platform_device.h>
-+#include <linux/syscore_ops.h>
-+#include <linux/interrupt.h>
-+#include <linux/amba/bus.h>
-+#include <linux/amba/clcd.h>
-+#include <linux/clockchips.h>
-+#include <linux/cnt32_to_63.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/spi/spi.h>
-+#include <linux/w1-gpio.h>
-+#include <linux/pps-gpio.h>
-+
-+#include <linux/version.h>
-+#include <linux/clkdev.h>
-+#include <asm/system.h>
-+#include <mach/hardware.h>
-+#include <asm/irq.h>
-+#include <linux/leds.h>
-+#include <asm/mach-types.h>
-+#include <linux/sched_clock.h>
-+
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+#include <asm/mach/irq.h>
-+#include <asm/mach/time.h>
-+#include <asm/mach/map.h>
-+
-+#include <mach/timex.h>
-+#include <mach/dma.h>
-+#include <mach/vcio.h>
-+#include <mach/system.h>
-+
-+#include <linux/delay.h>
-+
-+#include "bcm2708.h"
-+#include "armctrl.h"
-+#include "clock.h"
-+
-+#ifdef CONFIG_BCM_VC_CMA
-+#include <linux/broadcom/vc_cma.h>
-+#endif
-+
-+
-+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
-+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
-+ * represent this window by setting our dmamasks to 26 bits but, in fact
-+ * we're not going to use addresses outside this range (they're not in real
-+ * memory) so we don't bother.
-+ *
-+ * In the future we might include code to use this IOMMU to remap other
-+ * physical addresses onto VideoCore memory then the use of 32-bits would be
-+ * more legitimate.
-+ */
-+#define DMA_MASK_BITS_COMMON 32
-+
-+// use GPIO 4 for the one-wire GPIO pin, if enabled
-+#define W1_GPIO 4
-+// ensure one-wire GPIO pullup is disabled by default
-+#define W1_PULLUP -1
-+
-+/* command line parameters */
-+static unsigned boardrev, serial;
-+static unsigned uart_clock;
-+static unsigned disk_led_gpio = 16;
-+static unsigned disk_led_active_low = 1;
-+static unsigned reboot_part = 0;
-+static unsigned w1_gpio_pin = W1_GPIO;
-+static unsigned w1_gpio_pullup = W1_PULLUP;
-+static int pps_gpio_pin = -1;
-+static unsigned bcm2835_mmc = 1;
-+static bool vc_i2c_override = false;
-+
-+static void __init bcm2708_init_led(void);
-+
-+void __init bcm2708_init_irq(void)
-+{
-+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
-+}
-+
-+static struct map_desc bcm2708_io_desc[] __initdata = {
-+ {
-+ .virtual = IO_ADDRESS(ARMCTRL_BASE),
-+ .pfn = __phys_to_pfn(ARMCTRL_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(UART0_BASE),
-+ .pfn = __phys_to_pfn(UART0_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(UART1_BASE),
-+ .pfn = __phys_to_pfn(UART1_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(DMA_BASE),
-+ .pfn = __phys_to_pfn(DMA_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(MCORE_BASE),
-+ .pfn = __phys_to_pfn(MCORE_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(ST_BASE),
-+ .pfn = __phys_to_pfn(ST_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(USB_BASE),
-+ .pfn = __phys_to_pfn(USB_BASE),
-+ .length = SZ_128K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(PM_BASE),
-+ .pfn = __phys_to_pfn(PM_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(GPIO_BASE),
-+ .pfn = __phys_to_pfn(GPIO_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE}
-+};
-+
-+void __init bcm2708_map_io(void)
-+{
-+ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
-+}
-+
-+/* The STC is a free running counter that increments at the rate of 1MHz */
-+#define STC_FREQ_HZ 1000000
-+
-+static inline uint32_t timer_read(void)
-+{
-+ /* STC: a free running counter that increments at the rate of 1MHz */
-+ return readl(__io_address(ST_BASE + 0x04));
-+}
-+
-+static unsigned long bcm2708_read_current_timer(void)
-+{
-+ return timer_read();
-+}
-+
-+static u32 notrace bcm2708_read_sched_clock(void)
-+{
-+ return timer_read();
-+}
-+
-+static cycle_t clksrc_read(struct clocksource *cs)
-+{
-+ return timer_read();
-+}
-+
-+static struct clocksource clocksource_stc = {
-+ .name = "stc",
-+ .rating = 300,
-+ .read = clksrc_read,
-+ .mask = CLOCKSOURCE_MASK(32),
-+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+unsigned long frc_clock_ticks32(void)
-+{
-+ return timer_read();
-+}
-+
-+static void __init bcm2708_clocksource_init(void)
-+{
-+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
-+ printk(KERN_ERR "timer: failed to initialize clock "
-+ "source %s\n", clocksource_stc.name);
-+ }
-+}
-+
-+
-+/*
-+ * These are fixed clocks.
-+ */
-+static struct clk ref24_clk = {
-+ .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
-+};
-+
-+static struct clk osc_clk = {
-+#ifdef CONFIG_ARCH_BCM2708_CHIPIT
-+ .rate = 27000000,
-+#else
-+ .rate = 500000000, /* ARM clock is set from the VideoCore booter */
-+#endif
-+};
-+
-+/* warning - the USB needs a clock > 34MHz */
-+
-+static struct clk sdhost_clk = {
-+#ifdef CONFIG_ARCH_BCM2708_CHIPIT
-+ .rate = 4000000, /* 4MHz */
-+#else
-+ .rate = 250000000, /* 250MHz */
-+#endif
-+};
-+
-+static struct clk_lookup lookups[] = {
-+ { /* UART0 */
-+ .dev_id = "dev:f1",
-+ .clk = &ref24_clk,
-+ },
-+ { /* USB */
-+ .dev_id = "bcm2708_usb",
-+ .clk = &osc_clk,
-+ }, { /* SPI */
-+ .dev_id = "bcm2708_spi.0",
-+ .clk = &sdhost_clk,
-+ }, { /* BSC0 */
-+ .dev_id = "bcm2708_i2c.0",
-+ .clk = &sdhost_clk,
-+ }, { /* BSC1 */
-+ .dev_id = "bcm2708_i2c.1",
-+ .clk = &sdhost_clk,
-+ }
-+};
-+
-+#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
-+#define UART0_DMA { 15, 14 }
-+
-+AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
-+
-+static struct amba_device *amba_devs[] __initdata = {
-+ &uart0_device,
-+};
-+
-+static struct resource bcm2708_dmaman_resources[] = {
-+ {
-+ .start = DMA_BASE,
-+ .end = DMA_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct platform_device bcm2708_dmaman_device = {
-+ .name = BCM_DMAMAN_DRIVER_NAME,
-+ .id = 0, /* first bcm2708_dma */
-+ .resource = bcm2708_dmaman_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
-+};
-+
-+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-+static struct w1_gpio_platform_data w1_gpio_pdata = {
-+ .pin = W1_GPIO,
-+ .ext_pullup_enable_pin = W1_PULLUP,
-+ .is_open_drain = 0,
-+};
-+
-+static struct platform_device w1_device = {
-+ .name = "w1-gpio",
-+ .id = -1,
-+ .dev.platform_data = &w1_gpio_pdata,
-+};
-+#endif
-+
-+static struct pps_gpio_platform_data pps_gpio_info = {
-+ .assert_falling_edge = false,
-+ .capture_clear = false,
-+ .gpio_pin = -1,
-+ .gpio_label = "PPS",
-+};
-+
-+static struct platform_device pps_gpio_device = {
-+ .name = "pps-gpio",
-+ .id = PLATFORM_DEVID_NONE,
-+ .dev.platform_data = &pps_gpio_info,
-+};
-+
-+static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_fb_device = {
-+ .name = "bcm2708_fb",
-+ .id = -1, /* only one bcm2708_fb */
-+ .resource = NULL,
-+ .num_resources = 0,
-+ .dev = {
-+ .dma_mask = &fb_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
-+ {
-+ .mapbase = UART1_BASE + 0x40,
-+ .irq = IRQ_AUX,
-+ .uartclk = 125000000,
-+ .regshift = 2,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
-+ .type = PORT_8250,
-+ },
-+ {},
-+};
-+
-+static struct platform_device bcm2708_uart1_device = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = bcm2708_uart1_platform_data,
-+ },
-+};
-+
-+static struct resource bcm2708_usb_resources[] = {
-+ [0] = {
-+ .start = USB_BASE,
-+ .end = USB_BASE + SZ_128K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = MPHI_BASE,
-+ .end = MPHI_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [2] = {
-+ .start = IRQ_HOSTPORT,
-+ .end = IRQ_HOSTPORT,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ [3] = {
-+ .start = IRQ_USB,
-+ .end = IRQ_USB,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+
-+static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_usb_device = {
-+ .name = "bcm2708_usb",
-+ .id = -1, /* only one bcm2708_usb */
-+ .resource = bcm2708_usb_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
-+ .dev = {
-+ .dma_mask = &usb_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+static struct resource bcm2708_vcio_resources[] = {
-+ [0] = { /* mailbox/semaphore/doorbell access */
-+ .start = MCORE_BASE,
-+ .end = MCORE_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_vcio_device = {
-+ .name = BCM_VCIO_DRIVER_NAME,
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_vcio_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
-+ .dev = {
-+ .dma_mask = &vcio_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+#ifdef CONFIG_BCM2708_GPIO
-+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
-+
-+static struct resource bcm2708_gpio_resources[] = {
-+ [0] = { /* general purpose I/O */
-+ .start = GPIO_BASE,
-+ .end = GPIO_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_gpio_device = {
-+ .name = BCM_GPIO_DRIVER_NAME,
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_gpio_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
-+ .dev = {
-+ .dma_mask = &gpio_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+#endif
-+
-+static struct resource bcm2708_systemtimer_resources[] = {
-+ [0] = { /* system timer access */
-+ .start = ST_BASE,
-+ .end = ST_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_TIMER3,
-+ .end = IRQ_TIMER3,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+
-+};
-+
-+static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_systemtimer_device = {
-+ .name = "bcm2708_systemtimer",
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_systemtimer_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
-+ .dev = {
-+ .dma_mask = &systemtimer_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */
-+static struct resource bcm2708_emmc_resources[] = {
-+ [0] = {
-+ .start = EMMC_BASE,
-+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
-+ /* the memory map actually makes SZ_4K available */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_ARASANSDIO,
-+ .end = IRQ_ARASANSDIO,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
-+
-+struct platform_device bcm2708_emmc_device = {
-+ .name = "bcm2708_sdhci",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
-+ .resource = bcm2708_emmc_resources,
-+ .dev = {
-+ .dma_mask = &bcm2708_emmc_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+#endif /* CONFIG_MMC_SDHCI_BCM2708 */
-+
-+#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
-+static struct resource bcm2835_emmc_resources[] = {
-+ [0] = {
-+ .start = EMMC_BASE,
-+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
-+ /* the memory map actually makes SZ_4K available */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_ARASANSDIO,
-+ .end = IRQ_ARASANSDIO,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
-+
-+struct platform_device bcm2835_emmc_device = {
-+ .name = "mmc-bcm2835",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
-+ .resource = bcm2835_emmc_resources,
-+ .dev = {
-+ .dma_mask = &bcm2835_emmc_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+#endif /* CONFIG_MMC_BCM2835 */
-+
-+static struct resource bcm2708_powerman_resources[] = {
-+ [0] = {
-+ .start = PM_BASE,
-+ .end = PM_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+struct platform_device bcm2708_powerman_device = {
-+ .name = "bcm2708_powerman",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
-+ .resource = bcm2708_powerman_resources,
-+ .dev = {
-+ .dma_mask = &powerman_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+
-+
-+static struct platform_device bcm2708_alsa_devices[] = {
-+ [0] = {
-+ .name = "bcm2835_AUD0",
-+ .id = 0, /* first audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [1] = {
-+ .name = "bcm2835_AUD1",
-+ .id = 1, /* second audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [2] = {
-+ .name = "bcm2835_AUD2",
-+ .id = 2, /* third audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [3] = {
-+ .name = "bcm2835_AUD3",
-+ .id = 3, /* forth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [4] = {
-+ .name = "bcm2835_AUD4",
-+ .id = 4, /* fifth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [5] = {
-+ .name = "bcm2835_AUD5",
-+ .id = 5, /* sixth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [6] = {
-+ .name = "bcm2835_AUD6",
-+ .id = 6, /* seventh audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [7] = {
-+ .name = "bcm2835_AUD7",
-+ .id = 7, /* eighth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+};
-+
-+static struct resource bcm2708_spi_resources[] = {
-+ {
-+ .start = SPI0_BASE,
-+ .end = SPI0_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = IRQ_SPI,
-+ .end = IRQ_SPI,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+
-+static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+static struct platform_device bcm2708_spi_device = {
-+ .name = "bcm2708_spi",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
-+ .resource = bcm2708_spi_resources,
-+ .dev = {
-+ .dma_mask = &bcm2708_spi_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
-+};
-+
-+#ifdef CONFIG_BCM2708_SPIDEV
-+static struct spi_board_info bcm2708_spi_devices[] = {
-+#ifdef CONFIG_SPI_SPIDEV
-+ {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_0,
-+ }, {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 1,
-+ .mode = SPI_MODE_0,
-+ }
-+#endif
-+};
-+#endif
-+
-+static struct resource bcm2708_bsc0_resources[] = {
-+ {
-+ .start = BSC0_BASE,
-+ .end = BSC0_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = INTERRUPT_I2C,
-+ .end = INTERRUPT_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device bcm2708_bsc0_device = {
-+ .name = "bcm2708_i2c",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
-+ .resource = bcm2708_bsc0_resources,
-+};
-+
-+
-+static struct resource bcm2708_bsc1_resources[] = {
-+ {
-+ .start = BSC1_BASE,
-+ .end = BSC1_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = INTERRUPT_I2C,
-+ .end = INTERRUPT_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device bcm2708_bsc1_device = {
-+ .name = "bcm2708_i2c",
-+ .id = 1,
-+ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
-+ .resource = bcm2708_bsc1_resources,
-+};
-+
-+static struct platform_device bcm2835_hwmon_device = {
-+ .name = "bcm2835_hwmon",
-+};
-+
-+static struct platform_device bcm2835_thermal_device = {
-+ .name = "bcm2835_thermal",
-+};
-+
-+#ifdef CONFIG_SND_BCM2708_SOC_I2S_MODULE
-+static struct resource bcm2708_i2s_resources[] = {
-+ {
-+ .start = I2S_BASE,
-+ .end = I2S_BASE + 0x20,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = PCM_CLOCK_BASE,
-+ .end = PCM_CLOCK_BASE + 0x02,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct platform_device bcm2708_i2s_device = {
-+ .name = "bcm2708-i2s",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
-+ .resource = bcm2708_i2s_resources,
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
-+static struct platform_device snd_hifiberry_dac_device = {
-+ .name = "snd-hifiberry-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct platform_device snd_pcm5102a_codec_device = {
-+ .name = "pcm5102a-codec",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
-+static struct platform_device snd_rpi_hifiberry_dacplus_device = {
-+ .name = "snd-rpi-hifiberry-dacplus",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pcm5122", 0x4d)
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
-+static struct platform_device snd_hifiberry_digi_device = {
-+ .name = "snd-hifiberry-digi",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("wm8804", 0x3b)
-+ },
-+};
-+
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
-+static struct platform_device snd_hifiberry_amp_device = {
-+ .name = "snd-hifiberry-amp",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("tas5713", 0x1b)
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
-+static struct platform_device snd_rpi_dac_device = {
-+ .name = "snd-rpi-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct platform_device snd_pcm1794a_codec_device = {
-+ .name = "pcm1794a-codec",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+#endif
-+
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
-+static struct platform_device snd_rpi_iqaudio_dac_device = {
-+ .name = "snd-rpi-iqaudio-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+// Use the actual device name rather than generic driver name
-+static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pcm5122", 0x4c)
-+ },
-+};
-+#endif
-+
-+int __init bcm_register_device(struct platform_device *pdev)
-+{
-+ int ret;
-+
-+ ret = platform_device_register(pdev);
-+ if (ret)
-+ pr_debug("Unable to register platform device '%s': %d\n",
-+ pdev->name, ret);
-+
-+ return ret;
-+}
-+
-+int calc_rsts(int partition)
-+{
-+ return PM_PASSWORD |
-+ ((partition & (1 << 0)) << 0) |
-+ ((partition & (1 << 1)) << 1) |
-+ ((partition & (1 << 2)) << 2) |
-+ ((partition & (1 << 3)) << 3) |
-+ ((partition & (1 << 4)) << 4) |
-+ ((partition & (1 << 5)) << 5);
-+}
-+
-+static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
-+{
-+ extern char bcm2708_reboot_mode;
-+ uint32_t pm_rstc, pm_wdog;
-+ uint32_t timeout = 10;
-+ uint32_t pm_rsts = 0;
-+
-+ if(bcm2708_reboot_mode == 'q')
-+ {
-+ // NOOBS < 1.3 booting with reboot=q
-+ pm_rsts = readl(__io_address(PM_RSTS));
-+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
-+ }
-+ else if(bcm2708_reboot_mode == 'p')
-+ {
-+ // NOOBS < 1.3 halting
-+ pm_rsts = readl(__io_address(PM_RSTS));
-+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
-+ }
-+ else
-+ {
-+ pm_rsts = calc_rsts(reboot_part);
-+ }
-+
-+ writel(pm_rsts, __io_address(PM_RSTS));
-+
-+ /* Setup watchdog for reset */
-+ pm_rstc = readl(__io_address(PM_RSTC));
-+
-+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
-+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
-+
-+ writel(pm_wdog, __io_address(PM_WDOG));
-+ writel(pm_rstc, __io_address(PM_RSTC));
-+}
-+
-+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
-+static void bcm2708_power_off(void)
-+{
-+ extern char bcm2708_reboot_mode;
-+ if(bcm2708_reboot_mode == 'q')
-+ {
-+ // NOOBS < v1.3
-+ bcm2708_restart('p', "");
-+ }
-+ else
-+ {
-+ /* partition 63 is special code for HALT the bootloader knows not to boot*/
-+ reboot_part = 63;
-+ /* continue with normal reset mechanism */
-+ bcm2708_restart(0, "");
-+ }
-+}
-+
-+void __init bcm2708_init(void)
-+{
-+ int i;
-+
-+#if defined(CONFIG_BCM_VC_CMA)
-+ vc_cma_early_init();
-+#endif
-+ printk("bcm2708.uart_clock = %d\n", uart_clock);
-+ pm_power_off = bcm2708_power_off;
-+
-+ if (uart_clock)
-+ lookups[0].clk->rate = uart_clock;
-+
-+ for (i = 0; i < ARRAY_SIZE(lookups); i++)
-+ clkdev_add(&lookups[i]);
-+
-+ bcm_register_device(&bcm2708_dmaman_device);
-+ bcm_register_device(&bcm2708_vcio_device);
-+#ifdef CONFIG_BCM2708_GPIO
-+ bcm_register_device(&bcm2708_gpio_device);
-+ if (pps_gpio_pin >= 0) {
-+ pr_info("bcm2708: GPIO %d setup as pps-gpio device\n", pps_gpio_pin);
-+ pps_gpio_info.gpio_pin = pps_gpio_pin;
-+ pps_gpio_device.id = pps_gpio_pin;
-+ bcm_register_device(&pps_gpio_device);
-+ }
-+#endif
-+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-+ w1_gpio_pdata.pin = w1_gpio_pin;
-+ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
-+ platform_device_register(&w1_device);
-+#endif
-+ bcm_register_device(&bcm2708_systemtimer_device);
-+ bcm_register_device(&bcm2708_fb_device);
-+ bcm_register_device(&bcm2708_usb_device);
-+ bcm_register_device(&bcm2708_uart1_device);
-+ bcm_register_device(&bcm2708_powerman_device);
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708
-+ if (!bcm2835_mmc)
-+ bcm_register_device(&bcm2708_emmc_device);
-+#endif
-+#ifdef CONFIG_MMC_BCM2835
-+ if (bcm2835_mmc)
-+ bcm_register_device(&bcm2835_emmc_device);
-+#endif
-+ bcm2708_init_led();
-+ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
-+ bcm_register_device(&bcm2708_alsa_devices[i]);
-+
-+ bcm_register_device(&bcm2708_spi_device);
-+
-+ if (vc_i2c_override) {
-+ bcm_register_device(&bcm2708_bsc0_device);
-+ bcm_register_device(&bcm2708_bsc1_device);
-+ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) {
-+ bcm_register_device(&bcm2708_bsc0_device);
-+ } else {
-+ bcm_register_device(&bcm2708_bsc1_device);
-+ }
-+
-+ bcm_register_device(&bcm2835_hwmon_device);
-+ bcm_register_device(&bcm2835_thermal_device);
-+
-+#ifdef CONFIG_SND_BCM2708_SOC_I2S_MODULE
-+ bcm_register_device(&bcm2708_i2s_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
-+ bcm_register_device(&snd_hifiberry_dac_device);
-+ bcm_register_device(&snd_pcm5102a_codec_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
-+ bcm_register_device(&snd_rpi_hifiberry_dacplus_device);
-+ i2c_register_board_info(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
-+ bcm_register_device(&snd_hifiberry_digi_device);
-+ i2c_register_board_info(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
-+ bcm_register_device(&snd_hifiberry_amp_device);
-+ i2c_register_board_info(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
-+#endif
-+
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
-+ bcm_register_device(&snd_rpi_dac_device);
-+ bcm_register_device(&snd_pcm1794a_codec_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
-+ bcm_register_device(&snd_rpi_iqaudio_dac_device);
-+ i2c_register_board_info(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
-+#endif
-+
-+
-+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-+ struct amba_device *d = amba_devs[i];
-+ amba_device_register(d, &iomem_resource);
-+ }
-+ system_rev = boardrev;
-+ system_serial_low = serial;
-+
-+#ifdef CONFIG_BCM2708_SPIDEV
-+ spi_register_board_info(bcm2708_spi_devices,
-+ ARRAY_SIZE(bcm2708_spi_devices));
-+#endif
-+}
-+
-+static void timer_set_mode(enum clock_event_mode mode,
-+ struct clock_event_device *clk)
-+{
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ break;
-+ case CLOCK_EVT_MODE_PERIODIC:
-+
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_RESUME:
-+
-+ default:
-+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
-+ (int)mode);
-+ break;
-+ }
-+
-+}
-+
-+static int timer_set_next_event(unsigned long cycles,
-+ struct clock_event_device *unused)
-+{
-+ unsigned long stc;
-+ do {
-+ stc = readl(__io_address(ST_BASE + 0x04));
-+ /* We could take a FIQ here, which may push ST above STC3 */
-+ writel(stc + cycles, __io_address(ST_BASE + 0x18));
-+ } while ((signed long) cycles >= 0 &&
-+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
-+ >= (signed long) cycles);
-+ return 0;
-+}
-+
-+static struct clock_event_device timer0_clockevent = {
-+ .name = "timer0",
-+ .shift = 32,
-+ .features = CLOCK_EVT_FEAT_ONESHOT,
-+ .set_mode = timer_set_mode,
-+ .set_next_event = timer_set_next_event,
-+};
-+
-+/*
-+ * IRQ handler for the timer
-+ */
-+static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *evt = &timer0_clockevent;
-+
-+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
-+
-+ evt->event_handler(evt);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction bcm2708_timer_irq = {
-+ .name = "BCM2708 Timer Tick",
-+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = bcm2708_timer_interrupt,
-+};
-+
-+/*
-+ * Set up timer interrupt, and return the current time in seconds.
-+ */
-+
-+static struct delay_timer bcm2708_delay_timer = {
-+ .read_current_timer = bcm2708_read_current_timer,
-+ .freq = STC_FREQ_HZ,
-+};
-+
-+static void __init bcm2708_timer_init(void)
-+{
-+ /* init high res timer */
-+ bcm2708_clocksource_init();
-+
-+ /*
-+ * Initialise to a known state (all timers off)
-+ */
-+ writel(0, __io_address(ARM_T_CONTROL));
-+ /*
-+ * Make irqs happen for the system timer
-+ */
-+ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
-+
-+ setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
-+
-+ timer0_clockevent.mult =
-+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
-+ timer0_clockevent.max_delta_ns =
-+ clockevent_delta2ns(0xffffffff, &timer0_clockevent);
-+ timer0_clockevent.min_delta_ns =
-+ clockevent_delta2ns(0xf, &timer0_clockevent);
-+
-+ timer0_clockevent.cpumask = cpumask_of(0);
-+ clockevents_register_device(&timer0_clockevent);
-+
-+ register_current_timer_delay(&bcm2708_delay_timer);
-+}
-+
-+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-+#include <linux/leds.h>
-+
-+static struct gpio_led bcm2708_leds[] = {
-+ [0] = {
-+ .gpio = 16,
-+ .name = "led0",
-+ .default_trigger = "mmc0",
-+ .active_low = 1,
-+ },
-+};
-+
-+static struct gpio_led_platform_data bcm2708_led_pdata = {
-+ .num_leds = ARRAY_SIZE(bcm2708_leds),
-+ .leds = bcm2708_leds,
-+};
-+
-+static struct platform_device bcm2708_led_device = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &bcm2708_led_pdata,
-+ },
-+};
-+
-+static void __init bcm2708_init_led(void)
-+{
-+ bcm2708_leds[0].gpio = disk_led_gpio;
-+ bcm2708_leds[0].active_low = disk_led_active_low;
-+ platform_device_register(&bcm2708_led_device);
-+}
-+#else
-+static inline void bcm2708_init_led(void)
-+{
-+}
-+#endif
-+
-+void __init bcm2708_init_early(void)
-+{
-+ /*
-+ * Some devices allocate their coherent buffers from atomic
-+ * context. Increase size of atomic coherent pool to make sure such
-+ * the allocations won't fail.
-+ */
-+ init_dma_coherent_pool_size(SZ_4M);
-+}
-+
-+static void __init board_reserve(void)
-+{
-+#if defined(CONFIG_BCM_VC_CMA)
-+ vc_cma_reserve();
-+#endif
-+}
-+
-+MACHINE_START(BCM2708, "BCM2708")
-+ /* Maintainer: Broadcom Europe Ltd. */
-+ .map_io = bcm2708_map_io,
-+ .init_irq = bcm2708_init_irq,
-+ .init_time = bcm2708_timer_init,
-+ .init_machine = bcm2708_init,
-+ .init_early = bcm2708_init_early,
-+ .reserve = board_reserve,
-+ .restart = bcm2708_restart,
-+MACHINE_END
-+
-+module_param(boardrev, uint, 0644);
-+module_param(serial, uint, 0644);
-+module_param(uart_clock, uint, 0644);
-+module_param(disk_led_gpio, uint, 0644);
-+module_param(disk_led_active_low, uint, 0644);
-+module_param(reboot_part, uint, 0644);
-+module_param(w1_gpio_pin, uint, 0644);
-+module_param(w1_gpio_pullup, uint, 0644);
-+module_param(pps_gpio_pin, int, 0644);
-+MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS");
-+module_param(bcm2835_mmc, uint, 0644);
-+module_param(vc_i2c_override, bool, 0644);
-+MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral.");
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c
---- linux-3.12.38/arch/arm/mach-bcm2708/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,401 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/spinlock.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <mach/gpio.h>
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <mach/platform.h>
-+
-+#include <linux/platform_data/bcm2708.h>
-+
-+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
-+#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
-+#define BCM_GPIO_USE_IRQ 1
-+
-+#define GPIOFSEL(x) (0x00+(x)*4)
-+#define GPIOSET(x) (0x1c+(x)*4)
-+#define GPIOCLR(x) (0x28+(x)*4)
-+#define GPIOLEV(x) (0x34+(x)*4)
-+#define GPIOEDS(x) (0x40+(x)*4)
-+#define GPIOREN(x) (0x4c+(x)*4)
-+#define GPIOFEN(x) (0x58+(x)*4)
-+#define GPIOHEN(x) (0x64+(x)*4)
-+#define GPIOLEN(x) (0x70+(x)*4)
-+#define GPIOAREN(x) (0x7c+(x)*4)
-+#define GPIOAFEN(x) (0x88+(x)*4)
-+#define GPIOUD(x) (0x94+(x)*4)
-+#define GPIOUDCLK(x) (0x98+(x)*4)
-+
-+enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
-+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
-+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
-+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
-+};
-+
-+ /* Each of the two spinlocks protects a different set of hardware
-+ * regiters and data structurs. This decouples the code of the IRQ from
-+ * the GPIO code. This also makes the case of a GPIO routine call from
-+ * the IRQ code simpler.
-+ */
-+static DEFINE_SPINLOCK(lock); /* GPIO registers */
-+
-+struct bcm2708_gpio {
-+ struct list_head list;
-+ void __iomem *base;
-+ struct gpio_chip gc;
-+ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
-+};
-+
-+static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
-+ int function)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned long flags;
-+ unsigned gpiodir;
-+ unsigned gpio_bank = offset / 10;
-+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
-+
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&lock, flags);
-+
-+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
-+ gpiodir &= ~(7 << gpio_field_offset);
-+ gpiodir |= function << gpio_field_offset;
-+ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
-+ spin_unlock_irqrestore(&lock, flags);
-+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
-+
-+ return 0;
-+}
-+
-+static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
-+{
-+ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
-+}
-+
-+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
-+static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
-+ int value)
-+{
-+ int ret;
-+ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
-+ if (ret >= 0)
-+ bcm2708_gpio_set(gc, offset, value);
-+ return ret;
-+}
-+
-+static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+ unsigned lev;
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return 0;
-+ lev = readl(gpio->base + GPIOLEV(gpio_bank));
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
-+ return 0x1 & (lev >> gpio_field_offset);
-+}
-+
-+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return;
-+ if (value)
-+ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
-+ else
-+ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
-+}
-+
-+/**********************
-+ * extension to configure pullups
-+ */
-+int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
-+ bcm2708_gpio_pull_t value)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ switch (value) {
-+ case BCM2708_PULL_UP:
-+ writel(2, gpio->base + GPIOUD(0));
-+ break;
-+ case BCM2708_PULL_DOWN:
-+ writel(1, gpio->base + GPIOUD(0));
-+ break;
-+ case BCM2708_PULL_OFF:
-+ writel(0, gpio->base + GPIOUD(0));
-+ break;
-+ }
-+
-+ udelay(5);
-+ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
-+ udelay(5);
-+ writel(0, gpio->base + GPIOUD(0));
-+ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(bcm2708_gpio_setpull);
-+
-+/*************************************************************************************************************************
-+ * bcm2708 GPIO IRQ
-+ */
-+
-+#if BCM_GPIO_USE_IRQ
-+
-+static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return gpio_to_irq(gpio);
-+}
-+
-+static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned go = gn % 32;
-+
-+ gpio->rising[gb] &= ~(1 << go);
-+ gpio->falling[gb] &= ~(1 << go);
-+ gpio->high[gb] &= ~(1 << go);
-+ gpio->low[gb] &= ~(1 << go);
-+
-+ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-+ return -EINVAL;
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ gpio->rising[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ gpio->falling[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_LEVEL_HIGH)
-+ gpio->high[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_LEVEL_LOW)
-+ gpio->low[gb] |= (1 << go);
-+ return 0;
-+}
-+
-+static void bcm2708_gpio_irq_mask(struct irq_data *d)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned long rising = readl(gpio->base + GPIOREN(gb));
-+ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
-+ unsigned long high = readl(gpio->base + GPIOHEN(gb));
-+ unsigned long low = readl(gpio->base + GPIOLEN(gb));
-+
-+ gn = gn % 32;
-+
-+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
-+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
-+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
-+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
-+}
-+
-+static void bcm2708_gpio_irq_unmask(struct irq_data *d)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned go = gn % 32;
-+ unsigned long rising = readl(gpio->base + GPIOREN(gb));
-+ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
-+ unsigned long high = readl(gpio->base + GPIOHEN(gb));
-+ unsigned long low = readl(gpio->base + GPIOLEN(gb));
-+
-+ writel(1 << go, gpio->base + GPIOEDS(gb));
-+
-+ if (gpio->rising[gb] & (1 << go)) {
-+ writel(rising | (1 << go), gpio->base + GPIOREN(gb));
-+ } else {
-+ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
-+ }
-+
-+ if (gpio->falling[gb] & (1 << go)) {
-+ writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
-+ } else {
-+ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
-+ }
-+
-+ if (gpio->high[gb] & (1 << go)) {
-+ writel(high | (1 << go), gpio->base + GPIOHEN(gb));
-+ } else {
-+ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
-+ }
-+
-+ if (gpio->low[gb] & (1 << go)) {
-+ writel(low | (1 << go), gpio->base + GPIOLEN(gb));
-+ } else {
-+ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
-+ }
-+}
-+
-+static struct irq_chip bcm2708_irqchip = {
-+ .name = "GPIO",
-+ .irq_enable = bcm2708_gpio_irq_unmask,
-+ .irq_disable = bcm2708_gpio_irq_mask,
-+ .irq_unmask = bcm2708_gpio_irq_unmask,
-+ .irq_mask = bcm2708_gpio_irq_mask,
-+ .irq_set_type = bcm2708_gpio_irq_set_type,
-+};
-+
-+static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
-+{
-+ unsigned long edsr;
-+ unsigned bank;
-+ int i;
-+ unsigned gpio;
-+ for (bank = 0; bank <= 1; bank++) {
-+ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
-+ for_each_set_bit(i, &edsr, 32) {
-+ gpio = i + bank * 32;
-+ generic_handle_irq(gpio_to_irq(gpio));
-+ writel(1<<i,__io_address(GPIO_BASE) + GPIOEDS(bank));
-+ }
-+ }
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction bcm2708_gpio_irq = {
-+ .name = "BCM2708 GPIO catchall handler",
-+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = bcm2708_gpio_interrupt,
-+};
-+
-+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
-+{
-+ unsigned irq;
-+
-+ ucb->gc.to_irq = bcm2708_gpio_to_irq;
-+
-+ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
-+ irq_set_chip_data(irq, ucb);
-+ irq_set_chip(irq, &bcm2708_irqchip);
-+ set_irq_flags(irq, IRQF_VALID);
-+ }
-+ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
-+}
-+
-+#else
-+
-+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
-+{
-+}
-+
-+#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
-+
-+static int bcm2708_gpio_probe(struct platform_device *dev)
-+{
-+ struct bcm2708_gpio *ucb;
-+ struct resource *res;
-+ int err = 0;
-+
-+ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
-+
-+ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
-+ if (NULL == ucb) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "mailbox memory\n");
-+ err = -ENOMEM;
-+ goto err;
-+ }
-+
-+ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-+
-+ platform_set_drvdata(dev, ucb);
-+ ucb->base = __io_address(GPIO_BASE);
-+
-+ ucb->gc.label = "bcm2708_gpio";
-+ ucb->gc.base = 0;
-+ ucb->gc.ngpio = BCM2708_NR_GPIOS;
-+ ucb->gc.owner = THIS_MODULE;
-+
-+ ucb->gc.direction_input = bcm2708_gpio_dir_in;
-+ ucb->gc.direction_output = bcm2708_gpio_dir_out;
-+ ucb->gc.get = bcm2708_gpio_get;
-+ ucb->gc.set = bcm2708_gpio_set;
-+ ucb->gc.can_sleep = 0;
-+
-+ bcm2708_gpio_irq_init(ucb);
-+
-+ err = gpiochip_add(&ucb->gc);
-+ if (err)
-+ goto err;
-+
-+err:
-+ return err;
-+
-+}
-+
-+static int bcm2708_gpio_remove(struct platform_device *dev)
-+{
-+ int err = 0;
-+ struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
-+
-+ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
-+
-+ err = gpiochip_remove(&ucb->gc);
-+
-+ platform_set_drvdata(dev, NULL);
-+ kfree(ucb);
-+
-+ return err;
-+}
-+
-+static struct platform_driver bcm2708_gpio_driver = {
-+ .probe = bcm2708_gpio_probe,
-+ .remove = bcm2708_gpio_remove,
-+ .driver = {
-+ .name = "bcm2708_gpio"},
-+};
-+
-+static int __init bcm2708_gpio_init(void)
-+{
-+ return platform_driver_register(&bcm2708_gpio_driver);
-+}
-+
-+static void __exit bcm2708_gpio_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_gpio_driver);
-+}
-+
-+module_init(bcm2708_gpio_init);
-+module_exit(bcm2708_gpio_exit);
-+
-+MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/bcm2708.h linux-rpi/arch/arm/mach-bcm2708/bcm2708.h
---- linux-3.12.38/arch/arm/mach-bcm2708/bcm2708.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,49 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708.h
-+ *
-+ * BCM2708 machine support header
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_BCM2708_H
-+#define __BCM2708_BCM2708_H
-+
-+#include <linux/amba/bus.h>
-+
-+extern void __init bcm2708_init(void);
-+extern void __init bcm2708_init_irq(void);
-+extern void __init bcm2708_map_io(void);
-+extern struct sys_timer bcm2708_timer;
-+extern unsigned int mmc_status(struct device *dev);
-+
-+#define AMBA_DEVICE(name, busid, base, plat) \
-+static struct amba_device name##_device = { \
-+ .dev = { \
-+ .coherent_dma_mask = ~0, \
-+ .init_name = busid, \
-+ .platform_data = plat, \
-+ }, \
-+ .res = { \
-+ .start = base##_BASE, \
-+ .end = (base##_BASE) + SZ_4K - 1,\
-+ .flags = IORESOURCE_MEM, \
-+ }, \
-+ .irq = base##_IRQ, \
-+}
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/clock.c linux-rpi/arch/arm/mach-bcm2708/clock.c
---- linux-3.12.38/arch/arm/mach-bcm2708/clock.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/clock.c 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,61 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/clock.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/device.h>
-+#include <linux/list.h>
-+#include <linux/errno.h>
-+#include <linux/err.h>
-+#include <linux/string.h>
-+#include <linux/clk.h>
-+#include <linux/mutex.h>
-+
-+#include <asm/clkdev.h>
-+
-+#include "clock.h"
-+
-+int clk_enable(struct clk *clk)
-+{
-+ return 0;
-+}
-+EXPORT_SYMBOL(clk_enable);
-+
-+void clk_disable(struct clk *clk)
-+{
-+}
-+EXPORT_SYMBOL(clk_disable);
-+
-+unsigned long clk_get_rate(struct clk *clk)
-+{
-+ return clk->rate;
-+}
-+EXPORT_SYMBOL(clk_get_rate);
-+
-+long clk_round_rate(struct clk *clk, unsigned long rate)
-+{
-+ return clk->rate;
-+}
-+EXPORT_SYMBOL(clk_round_rate);
-+
-+int clk_set_rate(struct clk *clk, unsigned long rate)
-+{
-+ return -EIO;
-+}
-+EXPORT_SYMBOL(clk_set_rate);
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/clock.h linux-rpi/arch/arm/mach-bcm2708/clock.h
---- linux-3.12.38/arch/arm/mach-bcm2708/clock.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/clock.h 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,24 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/clock.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+struct module;
-+
-+struct clk {
-+ unsigned long rate;
-+};
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/dma.c linux-rpi/arch/arm/mach-bcm2708/dma.c
---- linux-3.12.38/arch/arm/mach-bcm2708/dma.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/dma.c 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,409 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/dma.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/slab.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/scatterlist.h>
-+
-+#include <mach/dma.h>
-+#include <mach/irqs.h>
-+
-+/*****************************************************************************\
-+ * *
-+ * Configuration *
-+ * *
-+\*****************************************************************************/
-+
-+#define CACHE_LINE_MASK 31
-+#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
-+#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
-+
-+/* valid only for channels 0 - 14, 15 has its own base address */
-+#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
-+#define BCM2708_DMA_CHANIO(dma_base, n) \
-+ ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
-+
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Auxilliary Functions *
-+ * *
-+\*****************************************************************************/
-+
-+/* A DMA buffer on an arbitrary boundary may separate a cache line into a
-+ section inside the DMA buffer and another section outside it.
-+ Even if we flush DMA buffers from the cache there is always the chance that
-+ during a DMA someone will access the part of a cache line that is outside
-+ the DMA buffer - which will then bring in unwelcome data.
-+ Without being able to dictate our own buffer pools we must insist that
-+ DMA buffers consist of a whole number of cache lines.
-+*/
-+
-+extern int
-+bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
-+{
-+ int i;
-+
-+ for (i = 0; i < sg_len; i++) {
-+ if (sg_ptr[i].offset & CACHE_LINE_MASK ||
-+ sg_ptr[i].length & CACHE_LINE_MASK)
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
-+
-+extern void
-+bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
-+{
-+ dsb(); /* ARM data synchronization (push) operation */
-+
-+ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
-+ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
-+}
-+
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
-+{
-+ dsb();
-+
-+ /* ugly busy wait only option for now */
-+ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
-+ cpu_relax();
-+}
-+
-+EXPORT_SYMBOL_GPL(bcm_dma_start);
-+
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
-+{
-+ dsb();
-+
-+ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
-+
-+/* Complete an ongoing DMA (assuming its results are to be ignored)
-+ Does nothing if there is no DMA in progress.
-+ This routine waits for the current AXI transfer to complete before
-+ terminating the current DMA. If the current transfer is hung on a DREQ used
-+ by an uncooperative peripheral the AXI transfer may never complete. In this
-+ case the routine times out and return a non-zero error code.
-+ Use of this routine doesn't guarantee that the ongoing or aborted DMA
-+ does not produce an interrupt.
-+*/
-+extern int
-+bcm_dma_abort(void __iomem *dma_chan_base)
-+{
-+ unsigned long int cs;
-+ int rc = 0;
-+
-+ cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (BCM2708_DMA_ACTIVE & cs) {
-+ long int timeout = 10000;
-+
-+ /* write 0 to the active bit - pause the DMA */
-+ writel(0, dma_chan_base + BCM2708_DMA_CS);
-+
-+ /* wait for any current AXI transfer to complete */
-+ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
-+ cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
-+ /* we'll un-pause when we set of our next DMA */
-+ rc = -ETIMEDOUT;
-+
-+ } else if (BCM2708_DMA_ACTIVE & cs) {
-+ /* terminate the control block chain */
-+ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
-+
-+ /* abort the whole DMA */
-+ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
-+ dma_chan_base + BCM2708_DMA_CS);
-+ }
-+ }
-+
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_abort);
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * DMA Manager Device Methods *
-+ * *
-+\*****************************************************************************/
-+
-+struct vc_dmaman {
-+ void __iomem *dma_base;
-+ u32 chan_available; /* bitmap of available channels */
-+ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
-+};
-+
-+static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
-+ u32 chans_available)
-+{
-+ dmaman->dma_base = dma_base;
-+ dmaman->chan_available = chans_available;
-+ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */
-+}
-+
-+static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
-+ unsigned preferred_feature_set)
-+{
-+ u32 chans;
-+ int feature;
-+
-+ chans = dmaman->chan_available;
-+ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
-+ /* select the subset of available channels with the desired
-+ feature so long as some of the candidate channels have that
-+ feature */
-+ if ((preferred_feature_set & (1 << feature)) &&
-+ (chans & dmaman->has_feature[feature]))
-+ chans &= dmaman->has_feature[feature];
-+
-+ if (chans) {
-+ int chan = 0;
-+ /* return the ordinal of the first channel in the bitmap */
-+ while (chans != 0 && (chans & 1) == 0) {
-+ chans >>= 1;
-+ chan++;
-+ }
-+ /* claim the channel */
-+ dmaman->chan_available &= ~(1 << chan);
-+ return chan;
-+ } else
-+ return -ENOMEM;
-+}
-+
-+static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
-+{
-+ if (chan < 0)
-+ return -EINVAL;
-+ else if ((1 << chan) & dmaman->chan_available)
-+ return -EIDRM;
-+ else {
-+ dmaman->chan_available |= (1 << chan);
-+ return 0;
-+ }
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA IRQs *
-+ * *
-+\*****************************************************************************/
-+
-+static unsigned char bcm_dma_irqs[] = {
-+ IRQ_DMA0,
-+ IRQ_DMA1,
-+ IRQ_DMA2,
-+ IRQ_DMA3,
-+ IRQ_DMA4,
-+ IRQ_DMA5,
-+ IRQ_DMA6,
-+ IRQ_DMA7,
-+ IRQ_DMA8,
-+ IRQ_DMA9,
-+ IRQ_DMA10,
-+ IRQ_DMA11,
-+ IRQ_DMA12
-+};
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * DMA Manager Monitor *
-+ * *
-+\*****************************************************************************/
-+
-+static struct device *dmaman_dev; /* we assume there's only one! */
-+
-+extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+ void __iomem **out_dma_base, int *out_dma_irq)
-+{
-+ if (!dmaman_dev)
-+ return -ENODEV;
-+ else {
-+ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
-+ int rc;
-+
-+ device_lock(dmaman_dev);
-+ rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
-+ if (rc >= 0) {
-+ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
-+ rc);
-+ *out_dma_irq = bcm_dma_irqs[rc];
-+ }
-+ device_unlock(dmaman_dev);
-+
-+ return rc;
-+ }
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
-+
-+extern int bcm_dma_chan_free(int channel)
-+{
-+ if (dmaman_dev) {
-+ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
-+ int rc;
-+
-+ device_lock(dmaman_dev);
-+ rc = vc_dmaman_chan_free(dmaman, channel);
-+ device_unlock(dmaman_dev);
-+
-+ return rc;
-+ } else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
-+
-+static int dev_dmaman_register(const char *dev_name, struct device *dev)
-+{
-+ int rc = dmaman_dev ? -EINVAL : 0;
-+ dmaman_dev = dev;
-+ return rc;
-+}
-+
-+static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
-+{
-+ dmaman_dev = NULL;
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Device *
-+ * *
-+\*****************************************************************************/
-+
-+static int dmachans = -1; /* module parameter */
-+
-+static int bcm_dmaman_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+ struct vc_dmaman *dmaman;
-+ struct resource *dma_res = NULL;
-+ void __iomem *dma_base = NULL;
-+ int have_dma_region = 0;
-+
-+ dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
-+ if (NULL == dmaman) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "DMA management memory\n");
-+ ret = -ENOMEM;
-+ } else {
-+
-+ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (dma_res == NULL) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
-+ "resource\n");
-+ ret = -ENODEV;
-+ } else if (!request_mem_region(dma_res->start,
-+ resource_size(dma_res),
-+ DRIVER_NAME)) {
-+ dev_err(&pdev->dev, "cannot obtain DMA region\n");
-+ ret = -EBUSY;
-+ } else {
-+ have_dma_region = 1;
-+ dma_base = ioremap(dma_res->start,
-+ resource_size(dma_res));
-+ if (!dma_base) {
-+ dev_err(&pdev->dev, "cannot map DMA region\n");
-+ ret = -ENOMEM;
-+ } else {
-+ /* use module parameter if one was provided */
-+ if (dmachans > 0)
-+ vc_dmaman_init(dmaman, dma_base,
-+ dmachans);
-+ else
-+ vc_dmaman_init(dmaman, dma_base,
-+ DEFAULT_DMACHAN_BITMAP);
-+
-+ platform_set_drvdata(pdev, dmaman);
-+ dev_dmaman_register(DRIVER_NAME, &pdev->dev);
-+
-+ printk(KERN_INFO DRIVER_NAME ": DMA manager "
-+ "at %p\n", dma_base);
-+ }
-+ }
-+ }
-+ if (ret != 0) {
-+ if (dma_base)
-+ iounmap(dma_base);
-+ if (dma_res && have_dma_region)
-+ release_mem_region(dma_res->start,
-+ resource_size(dma_res));
-+ if (dmaman)
-+ kfree(dmaman);
-+ }
-+ return ret;
-+}
-+
-+static int bcm_dmaman_remove(struct platform_device *pdev)
-+{
-+ struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
-+ kfree(dmaman);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm_dmaman_driver = {
-+ .probe = bcm_dmaman_probe,
-+ .remove = bcm_dmaman_remove,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+/*****************************************************************************\
-+ * *
-+ * Driver init/exit *
-+ * *
-+\*****************************************************************************/
-+
-+static int __init bcm_dmaman_drv_init(void)
-+{
-+ int ret;
-+
-+ ret = platform_driver_register(&bcm_dmaman_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to register "
-+ "on platform\n");
-+ }
-+
-+ return ret;
-+}
-+
-+static void __exit bcm_dmaman_drv_exit(void)
-+{
-+ platform_driver_unregister(&bcm_dmaman_driver);
-+}
-+
-+module_init(bcm_dmaman_drv_init);
-+module_exit(bcm_dmaman_drv_exit);
-+
-+module_param(dmachans, int, 0644);
-+
-+MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
-+MODULE_DESCRIPTION("DMA channel manager driver");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,419 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/arm_control.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_ARM_CONTROL_H
-+#define __BCM2708_ARM_CONTROL_H
-+
-+/*
-+ * Definitions and addresses for the ARM CONTROL logic
-+ * This file is manually generated.
-+ */
-+
-+#define ARM_BASE 0x7E00B000
-+
-+/* Basic configuration */
-+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
-+#define ARM_C0_SIZ128M 0x00000000
-+#define ARM_C0_SIZ256M 0x00000001
-+#define ARM_C0_SIZ512M 0x00000002
-+#define ARM_C0_SIZ1G 0x00000003
-+#define ARM_C0_BRESP0 0x00000000
-+#define ARM_C0_BRESP1 0x00000004
-+#define ARM_C0_BRESP2 0x00000008
-+#define ARM_C0_BOOTHI 0x00000010
-+#define ARM_C0_UNUSED05 0x00000020 /* free */
-+#define ARM_C0_FULLPERI 0x00000040
-+#define ARM_C0_UNUSED78 0x00000180 /* free */
-+#define ARM_C0_JTAGMASK 0x00000E00
-+#define ARM_C0_JTAGOFF 0x00000000
-+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
-+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
-+#define ARM_C0_APROTMSK 0x0000F000
-+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
-+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
-+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
-+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
-+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
-+#define ARM_C0_PRIO_L2 0x0F000000
-+#define ARM_C0_PRIO_UC 0xF0000000
-+
-+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
-+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
-+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
-+
-+
-+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
-+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
-+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
-+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
-+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
-+#define ARM_C1_PERSON 0x00000100 /* peripherals on */
-+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
-+
-+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
-+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
-+#define ARM_S_READPEND 0x000003FF /* pending reads counter */
-+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
-+
-+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
-+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
-+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
-+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
-+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
-+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
-+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
-+
-+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
-+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
-+#define ARM_IDVAL 0x364D5241
-+
-+/* Translation memory */
-+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
-+/* 32 locations: 0x100.. 0x17F */
-+/* 32 spare means we CAN go to 64 pages.... */
-+
-+
-+/* Interrupts */
-+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
-+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
-+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
-+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
-+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
-+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
-+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
-+
-+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
-+/* todo: all I1_interrupt sources */
-+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
-+/* todo: all I2_interrupt sources */
-+
-+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
-+#define ARM_IF_INDEX 0x0000007F /* FIQ select */
-+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
-+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
-+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
-+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
-+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
-+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
-+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
-+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
-+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
-+
-+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
-+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
-+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
-+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
-+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
-+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
-+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
-+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
-+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
-+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
-+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
-+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
-+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
-+
-+/* Timer */
-+/* For reg. fields see sp804 spec. */
-+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
-+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
-+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
-+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
-+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
-+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
-+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
-+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
-+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
-+
-+#define TIMER_CTRL_ONESHOT (1 << 0)
-+#define TIMER_CTRL_32BIT (1 << 1)
-+#define TIMER_CTRL_DIV1 (0 << 2)
-+#define TIMER_CTRL_DIV16 (1 << 2)
-+#define TIMER_CTRL_DIV256 (2 << 2)
-+#define TIMER_CTRL_IE (1 << 5)
-+#define TIMER_CTRL_PERIODIC (1 << 6)
-+#define TIMER_CTRL_ENABLE (1 << 7)
-+#define TIMER_CTRL_DBGHALT (1 << 8)
-+#define TIMER_CTRL_ENAFREE (1 << 9)
-+#define TIMER_CTRL_FREEDIV_SHIFT 16)
-+#define TIMER_CTRL_FREEDIV_MASK 0xff
-+
-+/* Semaphores, Doorbells, Mailboxes */
-+#define ARM_SBM_OWN0 (ARM_BASE+0x800)
-+#define ARM_SBM_OWN1 (ARM_BASE+0x900)
-+#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
-+#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
-+
-+/* MAILBOXES
-+ * Register flags are common across all
-+ * owner registers. See end of this section
-+ *
-+ * Semaphores, Doorbells, Mailboxes Owner 0
-+ *
-+ */
-+
-+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
-+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
-+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
-+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
-+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
-+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
-+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
-+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
-+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
-+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
-+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
-+/* MAILBOX 0 access in Owner 0 area */
-+/* Some addresses should ONLY be used by owner 0 */
-+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
-+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
-+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
-+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
-+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
-+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
-+/* MAILBOX 1 access in Owner 0 area */
-+/* Owner 0 should only WRITE to this mailbox */
-+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
-+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
-+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
-+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
-+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 1 */
-+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
-+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
-+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
-+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
-+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
-+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
-+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
-+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
-+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
-+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
-+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
-+/* MAILBOX 0 access in Owner 0 area */
-+/* Owner 1 should only WRITE to this mailbox */
-+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
-+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 0 area */
-+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
-+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
-+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
-+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
-+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
-+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
-+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
-+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
-+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 2 */
-+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
-+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
-+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
-+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
-+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
-+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
-+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
-+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
-+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
-+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
-+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
-+/* MAILBOX 0 access in Owner 2 area */
-+/* Owner 2 should only WRITE to this mailbox */
-+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
-+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 2 area */
-+/* Owner 2 should only WRITE to this mailbox */
-+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
-+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
-+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
-+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
-+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 3 */
-+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
-+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
-+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
-+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
-+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
-+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
-+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
-+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
-+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
-+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
-+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
-+/* MAILBOX 0 access in Owner 3 area */
-+/* Owner 3 should only WRITE to this mailbox */
-+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
-+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 3 area */
-+/* Owner 3 should only WRITE to this mailbox */
-+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
-+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
-+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
-+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
-+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
-+
-+
-+
-+/* Mailbox flags. Valid for all owners */
-+
-+/* Mailbox status register (...0x98) */
-+#define ARM_MS_FULL 0x80000000
-+#define ARM_MS_EMPTY 0x40000000
-+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
-+
-+/* MAILBOX config/status register (...0x9C) */
-+/* ANY write to this register clears the error bits! */
-+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
-+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
-+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
-+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
-+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
-+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
-+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
-+/* Bit 7 is unused */
-+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
-+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
-+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
-+
-+/* Semaphore clear/debug register (...0xE0) */
-+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
-+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
-+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
-+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
-+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
-+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
-+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
-+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
-+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
-+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
-+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
-+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
-+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
-+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
-+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
-+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
-+
-+/* Doorbells clear/debug register (...0xE4) */
-+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
-+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
-+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
-+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
-+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
-+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
-+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
-+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
-+
-+/* MY IRQS register (...0xF8) */
-+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
-+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
-+
-+/* ALL IRQS register (...0xF8) */
-+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
-+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
-+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
-+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
-+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
-+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
-+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
-+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
-+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
-+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
-+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
-+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
-+/* */
-+/* ARM JTAG BASH */
-+/* */
-+#define AJB_BASE 0x7e2000c0
-+
-+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
-+#define AJB_BITS0 0x000000
-+#define AJB_BITS4 0x000004
-+#define AJB_BITS8 0x000008
-+#define AJB_BITS12 0x00000C
-+#define AJB_BITS16 0x000010
-+#define AJB_BITS20 0x000014
-+#define AJB_BITS24 0x000018
-+#define AJB_BITS28 0x00001C
-+#define AJB_BITS32 0x000020
-+#define AJB_BITS34 0x000022
-+#define AJB_OUT_MS 0x000040
-+#define AJB_OUT_LS 0x000000
-+#define AJB_INV_CLK 0x000080
-+#define AJB_D0_RISE 0x000100
-+#define AJB_D0_FALL 0x000000
-+#define AJB_D1_RISE 0x000200
-+#define AJB_D1_FALL 0x000000
-+#define AJB_IN_RISE 0x000400
-+#define AJB_IN_FALL 0x000000
-+#define AJB_ENABLE 0x000800
-+#define AJB_HOLD0 0x000000
-+#define AJB_HOLD1 0x001000
-+#define AJB_HOLD2 0x002000
-+#define AJB_HOLD3 0x003000
-+#define AJB_RESETN 0x004000
-+#define AJB_CLKSHFT 16
-+#define AJB_BUSY 0x80000000
-+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
-+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
-+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/arm_power.h linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_power.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/arm_power.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_power.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,62 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _ARM_POWER_H
-+#define _ARM_POWER_H
-+
-+/* Use meaningful names on each side */
-+#ifdef __VIDEOCORE__
-+#define PREFIX(x) ARM_##x
-+#else
-+#define PREFIX(x) BCM_##x
-+#endif
-+
-+enum {
-+ PREFIX(POWER_SDCARD_BIT),
-+ PREFIX(POWER_UART_BIT),
-+ PREFIX(POWER_MINIUART_BIT),
-+ PREFIX(POWER_USB_BIT),
-+ PREFIX(POWER_I2C0_BIT),
-+ PREFIX(POWER_I2C1_BIT),
-+ PREFIX(POWER_I2C2_BIT),
-+ PREFIX(POWER_SPI_BIT),
-+ PREFIX(POWER_CCP2TX_BIT),
-+ PREFIX(POWER_DSI_BIT),
-+
-+ PREFIX(POWER_MAX)
-+};
-+
-+enum {
-+ PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
-+ PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
-+ PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
-+ PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
-+ PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
-+ PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
-+ PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
-+ PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
-+ PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
-+ PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
-+
-+ PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
-+ PREFIX(POWER_NONE) = 0
-+};
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,7 @@
-+#ifndef __ASM_MACH_CLKDEV_H
-+#define __ASM_MACH_CLKDEV_H
-+
-+#define __clk_get(clk) ({ 1; })
-+#define __clk_put(clk) do { } while (0)
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,22 @@
-+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
-+ *
-+ * Debugging macro include header
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 1994-1999 Russell King
-+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+*/
-+
-+#include <mach/platform.h>
-+
-+ .macro addruart, rp, rv, tmp
-+ ldr \rp, =UART0_BASE
-+ ldr \rv, =IO_ADDRESS(UART0_BASE)
-+ .endm
-+
-+#include <debug/pl01x.S>
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/dma.h linux-rpi/arch/arm/mach-bcm2708/include/mach/dma.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/dma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/dma.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,94 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/include/mach/dma.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+
-+#ifndef _MACH_BCM2708_DMA_H
-+#define _MACH_BCM2708_DMA_H
-+
-+#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
-+
-+/* DMA CS Control and Status bits */
-+#define BCM2708_DMA_ACTIVE (1 << 0)
-+#define BCM2708_DMA_INT (1 << 2)
-+#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
-+#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
-+#define BCM2708_DMA_ERR (1 << 8)
-+#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
-+#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
-+
-+/* DMA control block "info" field bits */
-+#define BCM2708_DMA_INT_EN (1 << 0)
-+#define BCM2708_DMA_TDMODE (1 << 1)
-+#define BCM2708_DMA_WAIT_RESP (1 << 3)
-+#define BCM2708_DMA_D_INC (1 << 4)
-+#define BCM2708_DMA_D_WIDTH (1 << 5)
-+#define BCM2708_DMA_D_DREQ (1 << 6)
-+#define BCM2708_DMA_S_INC (1 << 8)
-+#define BCM2708_DMA_S_WIDTH (1 << 9)
-+#define BCM2708_DMA_S_DREQ (1 << 10)
-+
-+#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
-+#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
-+#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
-+
-+#define BCM2708_DMA_DREQ_EMMC 11
-+#define BCM2708_DMA_DREQ_SDHOST 13
-+
-+#define BCM2708_DMA_CS 0x00 /* Control and Status */
-+#define BCM2708_DMA_ADDR 0x04
-+/* the current control block appears in the following registers - read only */
-+#define BCM2708_DMA_INFO 0x08
-+#define BCM2708_DMA_SOURCE_AD 0x0c
-+#define BCM2708_DMA_DEST_AD 0x10
-+#define BCM2708_DMA_NEXTCB 0x1C
-+#define BCM2708_DMA_DEBUG 0x20
-+
-+#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
-+#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
-+
-+#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
-+
-+struct bcm2708_dma_cb {
-+ unsigned long info;
-+ unsigned long src;
-+ unsigned long dst;
-+ unsigned long length;
-+ unsigned long stride;
-+ unsigned long next;
-+ unsigned long pad[2];
-+};
-+struct scatterlist;
-+
-+extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
-+extern void bcm_dma_start(void __iomem *dma_chan_base,
-+ dma_addr_t control_block);
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base);
-+extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
-+
-+/* When listing features we can ask for when allocating DMA channels give
-+ those with higher priority smaller ordinal numbers */
-+#define BCM_DMA_FEATURE_FAST_ORD 0
-+#define BCM_DMA_FEATURE_BULK_ORD 1
-+#define BCM_DMA_FEATURE_NORMAL_ORD 2
-+#define BCM_DMA_FEATURE_LITE_ORD 3
-+#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
-+#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
-+#define BCM_DMA_FEATURE_NORMAL (1<<BCM_DMA_FEATURE_NORMAL_ORD)
-+#define BCM_DMA_FEATURE_LITE (1<<BCM_DMA_FEATURE_LITE_ORD)
-+#define BCM_DMA_FEATURE_COUNT 4
-+
-+/* return channel no or -ve error */
-+extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+ void __iomem **out_dma_base, int *out_dma_irq);
-+extern int bcm_dma_chan_free(int channel);
-+
-+
-+#endif /* _MACH_BCM2708_DMA_H */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,69 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/entry-macro.S
-+ *
-+ * Low-level IRQ helper macros for BCM2708 platforms
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <mach/hardware.h>
-+
-+ .macro disable_fiq
-+ .endm
-+
-+ .macro get_irqnr_preamble, base, tmp
-+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
-+ .endm
-+
-+ .macro arch_ret_to_user, tmp1, tmp2
-+ .endm
-+
-+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-+ /* get masked status */
-+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
-+ mov \irqnr, #(ARM_IRQ0_BASE + 31)
-+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
-+ /* clear bits 8 and 9, and test */
-+ bics \irqstat, \irqstat, #0x300
-+ bne 1010f
-+
-+ tst \tmp, #0x100
-+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
-+ movne \irqnr, #(ARM_IRQ1_BASE + 31)
-+ @ Mask out the interrupts also present in PEND0 - see SW-5809
-+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
-+ bicne \irqstat, #((1<<18) | (1<<19))
-+ bne 1010f
-+
-+ tst \tmp, #0x200
-+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
-+ movne \irqnr, #(ARM_IRQ2_BASE + 31)
-+ @ Mask out the interrupts also present in PEND0 - see SW-5809
-+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
-+ bicne \irqstat, #((1<<30))
-+ beq 1020f
-+
-+1010:
-+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
-+ @ N.B. CLZ is an ARM5 instruction.
-+ sub \tmp, \irqstat, #1
-+ eor \irqstat, \irqstat, \tmp
-+ clz \tmp, \irqstat
-+ sub \irqnr, \tmp
-+
-+1020: @ EQ will be set if no irqs pending
-+
-+ .endm
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,38 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/timex.h
-+ *
-+ * BCM2708 free running counter (timer)
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _MACH_FRC_H
-+#define _MACH_FRC_H
-+
-+#define FRC_TICK_RATE (1000000)
-+
-+/*! Free running counter incrementing at the CLOCK_TICK_RATE
-+ (slightly faster than frc_clock_ticks63()
-+ */
-+extern unsigned long frc_clock_ticks32(void);
-+
-+/*! Free running counter incrementing at the CLOCK_TICK_RATE
-+ * Note - top bit should be ignored (see cnt32_to_63)
-+ */
-+extern unsigned long long frc_clock_ticks63(void);
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,17 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/gpio.h
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef __ASM_ARCH_GPIO_H
-+#define __ASM_ARCH_GPIO_H
-+
-+#define BCM2708_NR_GPIOS 54 // number of gpio lines
-+
-+#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
-+#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,28 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/hardware.h
-+ *
-+ * This file contains the hardware definitions of the BCM2708 devices.
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_HARDWARE_H
-+#define __ASM_ARCH_HARDWARE_H
-+
-+#include <asm/sizes.h>
-+#include <mach/platform.h>
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/io.h linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,27 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/io.h
-+ *
-+ * Copyright (C) 2003 ARM Limited
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARM_ARCH_IO_H
-+#define __ASM_ARM_ARCH_IO_H
-+
-+#define IO_SPACE_LIMIT 0xffffffff
-+
-+#define __io(a) __typesafe_io(a)
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,199 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/irqs.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _BCM2708_IRQS_H_
-+#define _BCM2708_IRQS_H_
-+
-+#include <mach/platform.h>
-+
-+/*
-+ * IRQ interrupts definitions are the same as the INT definitions
-+ * held within platform.h
-+ */
-+#define IRQ_ARMCTRL_START 0
-+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
-+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
-+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
-+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
-+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
-+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
-+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
-+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
-+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
-+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
-+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
-+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
-+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
-+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
-+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
-+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
-+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
-+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
-+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
-+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
-+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
-+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
-+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
-+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
-+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
-+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
-+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
-+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
-+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
-+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
-+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
-+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
-+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
-+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
-+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
-+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
-+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
-+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
-+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
-+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
-+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
-+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
-+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
-+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
-+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
-+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
-+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
-+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
-+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
-+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
-+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
-+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
-+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
-+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
-+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
-+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
-+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
-+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
-+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
-+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
-+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
-+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
-+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
-+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
-+
-+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
-+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
-+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
-+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
-+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
-+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
-+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
-+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
-+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
-+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
-+
-+#define FIQ_START HARD_IRQS
-+
-+/*
-+ * FIQ interrupts definitions are the same as the INT definitions.
-+ */
-+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
-+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
-+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
-+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
-+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
-+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
-+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
-+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
-+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
-+#define FIQ_USB (FIQ_START+INTERRUPT_USB)
-+#define FIQ_3D (FIQ_START+INTERRUPT_3D)
-+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
-+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
-+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
-+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
-+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
-+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
-+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
-+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
-+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
-+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
-+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
-+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
-+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
-+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
-+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
-+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
-+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
-+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
-+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
-+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
-+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
-+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
-+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
-+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
-+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
-+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
-+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
-+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
-+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
-+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
-+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
-+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
-+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
-+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
-+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
-+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
-+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
-+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
-+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
-+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
-+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
-+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
-+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
-+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
-+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
-+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
-+#define FIQ_UART (FIQ_START+INTERRUPT_UART)
-+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
-+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
-+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
-+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
-+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
-+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
-+
-+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
-+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
-+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
-+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
-+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
-+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
-+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
-+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
-+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
-+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
-+
-+#define HARD_IRQS (64 + 21)
-+#define FIQ_IRQS (64 + 21)
-+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
-+#define GPIO_IRQS (32*5)
-+#define SPARE_ALLOC_IRQS 64
-+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
-+#define FREE_IRQS 128
-+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
-+
-+#endif /* _BCM2708_IRQS_H_ */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,57 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/memory.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_MEMORY_H
-+#define __ASM_ARCH_MEMORY_H
-+
-+/* Memory overview:
-+
-+ [ARMcore] <--virtual addr-->
-+ [ARMmmu] <--physical addr-->
-+ [GERTmap] <--bus add-->
-+ [VCperiph]
-+
-+*/
-+
-+/*
-+ * Physical DRAM offset.
-+ */
-+#define PLAT_PHYS_OFFSET UL(0x00000000)
-+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
-+
-+#ifdef CONFIG_BCM2708_NOL2CACHE
-+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
-+#else
-+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
-+#endif
-+
-+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
-+ * will provide the offset into this area as well as setting the bits that
-+ * stop the L1 and L2 cache from being used
-+ *
-+ * WARNING: this only works because the ARM is given memory at a fixed location
-+ * (ARMMEM_OFFSET)
-+ */
-+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
-+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
-+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
-+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
-+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,228 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/platform.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _BCM2708_PLATFORM_H
-+#define _BCM2708_PLATFORM_H
-+
-+
-+/* macros to get at IO space when running virtually */
-+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-+
-+#define __io_address(n) IOMEM(IO_ADDRESS(n))
-+
-+
-+/*
-+ * SDRAM
-+ */
-+#define BCM2708_SDRAM_BASE 0x00000000
-+
-+/*
-+ * Logic expansion modules
-+ *
-+ */
-+
-+
-+/* ------------------------------------------------------------------------
-+ * BCM2708 ARMCTRL Registers
-+ * ------------------------------------------------------------------------
-+ */
-+
-+#define HW_REGISTER_RW(addr) (addr)
-+#define HW_REGISTER_RO(addr) (addr)
-+
-+#include "arm_control.h"
-+#undef ARM_BASE
-+
-+/*
-+ * Definitions and addresses for the ARM CONTROL logic
-+ * This file is manually generated.
-+ */
-+
-+#define BCM2708_PERI_BASE 0x20000000
-+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
-+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
-+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
-+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
-+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
-+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
-+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
-+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
-+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
-+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
-+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
-+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
-+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
-+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
-+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
-+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
-+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
-+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
-+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
-+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
-+
-+#define ARMCTRL_BASE (ARM_BASE + 0x000)
-+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
-+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
-+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
-+
-+
-+/*
-+ * Interrupt assignments
-+ */
-+
-+#define ARM_IRQ1_BASE 0
-+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
-+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
-+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
-+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
-+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
-+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
-+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
-+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
-+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
-+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
-+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
-+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
-+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
-+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
-+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
-+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
-+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
-+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
-+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
-+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
-+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
-+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
-+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
-+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
-+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
-+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
-+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
-+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
-+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
-+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
-+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
-+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
-+
-+#define ARM_IRQ2_BASE 32
-+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
-+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
-+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
-+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
-+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
-+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
-+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
-+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
-+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
-+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
-+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
-+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
-+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
-+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
-+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
-+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
-+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
-+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
-+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
-+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
-+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
-+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
-+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
-+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
-+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
-+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
-+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
-+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
-+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
-+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
-+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
-+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
-+
-+#define ARM_IRQ0_BASE 64
-+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
-+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
-+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
-+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
-+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
-+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
-+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
-+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
-+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
-+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
-+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
-+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
-+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
-+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
-+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
-+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
-+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
-+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
-+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
-+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
-+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
-+
-+#define MAXIRQNUM (32 + 32 + 20)
-+#define MAXFIQNUM (32 + 32 + 20)
-+
-+#define MAX_TIMER 2
-+#define MAX_PERIOD 699050
-+#define TICKS_PER_uSEC 1
-+
-+/*
-+ * These are useconds NOT ticks.
-+ *
-+ */
-+#define mSEC_1 1000
-+#define mSEC_5 (mSEC_1 * 5)
-+#define mSEC_10 (mSEC_1 * 10)
-+#define mSEC_25 (mSEC_1 * 25)
-+#define SEC_1 (mSEC_1 * 1000)
-+
-+/*
-+ * Watchdog
-+ */
-+#define PM_RSTC (PM_BASE+0x1c)
-+#define PM_RSTS (PM_BASE+0x20)
-+#define PM_WDOG (PM_BASE+0x24)
-+
-+#define PM_WDOG_RESET 0000000000
-+#define PM_PASSWORD 0x5a000000
-+#define PM_WDOG_TIME_SET 0x000fffff
-+#define PM_RSTC_WRCFG_CLR 0xffffffcf
-+#define PM_RSTC_WRCFG_SET 0x00000030
-+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
-+#define PM_RSTC_RESET 0x00000102
-+
-+#define PM_RSTS_HADPOR_SET 0x00001000
-+#define PM_RSTS_HADSRH_SET 0x00000400
-+#define PM_RSTS_HADSRF_SET 0x00000200
-+#define PM_RSTS_HADSRQ_SET 0x00000100
-+#define PM_RSTS_HADWRH_SET 0x00000040
-+#define PM_RSTS_HADWRF_SET 0x00000020
-+#define PM_RSTS_HADWRQ_SET 0x00000010
-+#define PM_RSTS_HADDRH_SET 0x00000004
-+#define PM_RSTS_HADDRF_SET 0x00000002
-+#define PM_RSTS_HADDRQ_SET 0x00000001
-+
-+#define UART0_CLOCK 3000000
-+
-+#endif
-+
-+/* END */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/power.h linux-rpi/arch/arm/mach-bcm2708/include/mach/power.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/power.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/power.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,26 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/power.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for controlling the power to
-+ * VideoCore subsystems.
-+ */
-+
-+#ifndef _MACH_BCM2708_POWER_H
-+#define _MACH_BCM2708_POWER_H
-+
-+#include <linux/types.h>
-+#include <mach/arm_power.h>
-+
-+typedef unsigned int BCM_POWER_HANDLE_T;
-+
-+extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
-+extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
-+extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/system.h linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,38 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/system.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_SYSTEM_H
-+#define __ASM_ARCH_SYSTEM_H
-+
-+#include <linux/io.h>
-+#include <mach/hardware.h>
-+#include <mach/platform.h>
-+
-+static inline void arch_idle(void)
-+{
-+ /*
-+ * This should do all the clock switching
-+ * and wait for interrupt tricks
-+ */
-+ cpu_do_idle();
-+}
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,23 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/timex.h
-+ *
-+ * BCM2708 sysem clock frequency
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#define CLOCK_TICK_RATE (1000000)
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,84 @@
-+/*
-+ * arch/arm/mach-bcn2708/include/mach/uncompress.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/amba/serial.h>
-+#include <mach/hardware.h>
-+
-+#define UART_BAUD 115200
-+
-+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
-+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
-+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
-+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
-+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
-+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
-+
-+/*
-+ * This does not append a newline
-+ */
-+static inline void putc(int c)
-+{
-+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
-+ barrier();
-+
-+ __raw_writel(c, BCM2708_UART_DR);
-+}
-+
-+static inline void flush(void)
-+{
-+ int fr;
-+
-+ do {
-+ fr = __raw_readl(BCM2708_UART_FR);
-+ barrier();
-+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
-+}
-+
-+static inline void arch_decomp_setup(void)
-+{
-+ int temp, div, rem, frac;
-+
-+ temp = 16 * UART_BAUD;
-+ div = UART0_CLOCK / temp;
-+ rem = UART0_CLOCK % temp;
-+ temp = (8 * rem) / UART_BAUD;
-+ frac = (temp >> 1) + (temp & 1);
-+
-+ /* Make sure the UART is disabled before we start */
-+ __raw_writel(0, BCM2708_UART_CR);
-+
-+ /* Set the baud rate */
-+ __raw_writel(div, BCM2708_UART_IBRD);
-+ __raw_writel(frac, BCM2708_UART_FBRD);
-+
-+ /* Set the UART to 8n1, FIFO enabled */
-+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
-+
-+ /* Enable the UART */
-+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
-+ BCM2708_UART_CR);
-+}
-+
-+/*
-+ * nothing to do
-+ */
-+#define arch_decomp_wdog()
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vcio.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vcio.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vcio.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vcio.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,165 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/vcio.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef _MACH_BCM2708_VCIO_H
-+#define _MACH_BCM2708_VCIO_H
-+
-+/* Routines to handle I/O via the VideoCore "ARM control" registers
-+ * (semaphores, doorbells, mailboxes)
-+ */
-+
-+#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
-+
-+/* Constants shared with the ARM identifying separate mailbox channels */
-+#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
-+#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
-+#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
-+#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
-+#define MBOX_CHAN_COUNT 9
-+
-+enum {
-+ VCMSG_PROCESS_REQUEST = 0x00000000
-+};
-+enum {
-+ VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
-+ VCMSG_REQUEST_FAILED = 0x80000001
-+};
-+/* Mailbox property tags */
-+enum {
-+ VCMSG_PROPERTY_END = 0x00000000,
-+ VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
-+ VCMSG_GET_BOARD_MODEL = 0x00010001,
-+ VCMSG_GET_BOARD_REVISION = 0x00010002,
-+ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
-+ VCMSG_GET_BOARD_SERIAL = 0x00010004,
-+ VCMSG_GET_ARM_MEMORY = 0x00010005,
-+ VCMSG_GET_VC_MEMORY = 0x00010006,
-+ VCMSG_GET_CLOCKS = 0x00010007,
-+ VCMSG_GET_COMMAND_LINE = 0x00050001,
-+ VCMSG_GET_DMA_CHANNELS = 0x00060001,
-+ VCMSG_GET_POWER_STATE = 0x00020001,
-+ VCMSG_GET_TIMING = 0x00020002,
-+ VCMSG_SET_POWER_STATE = 0x00028001,
-+ VCMSG_GET_CLOCK_STATE = 0x00030001,
-+ VCMSG_SET_CLOCK_STATE = 0x00038001,
-+ VCMSG_GET_CLOCK_RATE = 0x00030002,
-+ VCMSG_SET_CLOCK_RATE = 0x00038002,
-+ VCMSG_GET_VOLTAGE = 0x00030003,
-+ VCMSG_SET_VOLTAGE = 0x00038003,
-+ VCMSG_GET_MAX_CLOCK = 0x00030004,
-+ VCMSG_GET_MAX_VOLTAGE = 0x00030005,
-+ VCMSG_GET_TEMPERATURE = 0x00030006,
-+ VCMSG_GET_MIN_CLOCK = 0x00030007,
-+ VCMSG_GET_MIN_VOLTAGE = 0x00030008,
-+ VCMSG_GET_TURBO = 0x00030009,
-+ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
-+ VCMSG_GET_STC = 0x0003000b,
-+ VCMSG_SET_TURBO = 0x00038009,
-+ VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
-+ VCMSG_SET_LOCK_MEM = 0x0003000d,
-+ VCMSG_SET_UNLOCK_MEM = 0x0003000e,
-+ VCMSG_SET_RELEASE_MEM = 0x0003000f,
-+ VCMSG_SET_EXECUTE_CODE = 0x00030010,
-+ VCMSG_SET_EXECUTE_QPU = 0x00030011,
-+ VCMSG_SET_ENABLE_QPU = 0x00030012,
-+ VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
-+ VCMSG_GET_EDID_BLOCK = 0x00030020,
-+ VCMSG_GET_CUSTOMER_OTP = 0x00030021,
-+ VCMSG_SET_CUSTOMER_OTP = 0x00038021,
-+ VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
-+ VCMSG_SET_RELEASE_BUFFER = 0x00048001,
-+ VCMSG_SET_BLANK_SCREEN = 0x00040002,
-+ VCMSG_TST_BLANK_SCREEN = 0x00044002,
-+ VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
-+ VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
-+ VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
-+ VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
-+ VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
-+ VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
-+ VCMSG_GET_DEPTH = 0x00040005,
-+ VCMSG_TST_DEPTH = 0x00044005,
-+ VCMSG_SET_DEPTH = 0x00048005,
-+ VCMSG_GET_PIXEL_ORDER = 0x00040006,
-+ VCMSG_TST_PIXEL_ORDER = 0x00044006,
-+ VCMSG_SET_PIXEL_ORDER = 0x00048006,
-+ VCMSG_GET_ALPHA_MODE = 0x00040007,
-+ VCMSG_TST_ALPHA_MODE = 0x00044007,
-+ VCMSG_SET_ALPHA_MODE = 0x00048007,
-+ VCMSG_GET_PITCH = 0x00040008,
-+ VCMSG_TST_PITCH = 0x00044008,
-+ VCMSG_SET_PITCH = 0x00048008,
-+ VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
-+ VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
-+ VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
-+ VCMSG_GET_OVERSCAN = 0x0004000a,
-+ VCMSG_TST_OVERSCAN = 0x0004400a,
-+ VCMSG_SET_OVERSCAN = 0x0004800a,
-+ VCMSG_GET_PALETTE = 0x0004000b,
-+ VCMSG_TST_PALETTE = 0x0004400b,
-+ VCMSG_SET_PALETTE = 0x0004800b,
-+ VCMSG_GET_LAYER = 0x0004000c,
-+ VCMSG_TST_LAYER = 0x0004400c,
-+ VCMSG_SET_LAYER = 0x0004800c,
-+ VCMSG_GET_TRANSFORM = 0x0004000d,
-+ VCMSG_TST_TRANSFORM = 0x0004400d,
-+ VCMSG_SET_TRANSFORM = 0x0004800d,
-+ VCMSG_TST_VSYNC = 0x0004400e,
-+ VCMSG_SET_VSYNC = 0x0004800e,
-+ VCMSG_SET_CURSOR_INFO = 0x00008010,
-+ VCMSG_SET_CURSOR_STATE = 0x00008011,
-+};
-+
-+extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
-+extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
-+extern int /*rc*/ bcm_mailbox_property(void *data, int size);
-+
-+#include <linux/ioctl.h>
-+
-+/*
-+ * The major device number. We can't rely on dynamic
-+ * registration any more, because ioctls need to know
-+ * it.
-+ */
-+#define MAJOR_NUM 100
-+
-+/*
-+ * Set the message of the device driver
-+ */
-+#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
-+/*
-+ * _IOWR means that we're creating an ioctl command
-+ * number for passing information from a user process
-+ * to the kernel module and from the kernel module to user process
-+ *
-+ * The first arguments, MAJOR_NUM, is the major device
-+ * number we're using.
-+ *
-+ * The second argument is the number of the command
-+ * (there could be several with different meanings).
-+ *
-+ * The third argument is the type we want to get from
-+ * the process to the kernel.
-+ */
-+
-+/*
-+ * The name of the device file
-+ */
-+#define DEVICE_FILE_NAME "vcio"
-+
-+#endif
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_mem.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_mem.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_mem.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,35 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#if !defined( VC_MEM_H )
-+#define VC_MEM_H
-+
-+#include <linux/ioctl.h>
-+
-+#define VC_MEM_IOC_MAGIC 'v'
-+
-+#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
-+#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
-+#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
-+#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
-+
-+#if defined( __KERNEL__ )
-+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
-+
-+extern unsigned long mm_vc_mem_phys_addr;
-+extern unsigned int mm_vc_mem_size;
-+extern int vc_mem_get_current_size( void );
-+#endif
-+
-+#endif /* VC_MEM_H */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,181 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __VC_SM_DEFS_H__INCLUDED__
-+#define __VC_SM_DEFS_H__INCLUDED__
-+
-+/* FourCC code used for VCHI connection */
-+#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM")
-+
-+/* Maximum message length */
-+#define VC_SM_MAX_MSG_LEN (sizeof(VC_SM_MSG_UNION_T) + \
-+ sizeof(VC_SM_MSG_HDR_T))
-+#define VC_SM_MAX_RSP_LEN (sizeof(VC_SM_MSG_UNION_T))
-+
-+/* Resource name maximum size */
-+#define VC_SM_RESOURCE_NAME 32
-+
-+/* All message types supported for HOST->VC direction */
-+typedef enum {
-+ /* Allocate shared memory block */
-+ VC_SM_MSG_TYPE_ALLOC,
-+ /* Lock allocated shared memory block */
-+ VC_SM_MSG_TYPE_LOCK,
-+ /* Unlock allocated shared memory block */
-+ VC_SM_MSG_TYPE_UNLOCK,
-+ /* Unlock allocated shared memory block, do not answer command */
-+ VC_SM_MSG_TYPE_UNLOCK_NOANS,
-+ /* Free shared memory block */
-+ VC_SM_MSG_TYPE_FREE,
-+ /* Resize a shared memory block */
-+ VC_SM_MSG_TYPE_RESIZE,
-+ /* Walk the allocated shared memory block(s) */
-+ VC_SM_MSG_TYPE_WALK_ALLOC,
-+
-+ /* A previously applied action will need to be reverted */
-+ VC_SM_MSG_TYPE_ACTION_CLEAN,
-+ VC_SM_MSG_TYPE_MAX
-+} VC_SM_MSG_TYPE;
-+
-+/* Type of memory to be allocated */
-+typedef enum {
-+ VC_SM_ALLOC_CACHED,
-+ VC_SM_ALLOC_NON_CACHED,
-+
-+} VC_SM_ALLOC_TYPE_T;
-+
-+/* Message header for all messages in HOST->VC direction */
-+typedef struct {
-+ int32_t type;
-+ uint32_t trans_id;
-+ uint8_t body[0];
-+
-+} VC_SM_MSG_HDR_T;
-+
-+/* Request to allocate memory (HOST->VC) */
-+typedef struct {
-+ /* type of memory to allocate */
-+ VC_SM_ALLOC_TYPE_T type;
-+ /* byte amount of data to allocate per unit */
-+ uint32_t base_unit;
-+ /* number of unit to allocate */
-+ uint32_t num_unit;
-+ /* alignement to be applied on allocation */
-+ uint32_t alignement;
-+ /* identity of who allocated this block */
-+ uint32_t allocator;
-+ /* resource name (for easier tracking on vc side) */
-+ char name[VC_SM_RESOURCE_NAME];
-+
-+} VC_SM_ALLOC_T;
-+
-+/* Result of a requested memory allocation (VC->HOST) */
-+typedef struct {
-+ /* Transaction identifier */
-+ uint32_t trans_id;
-+
-+ /* Resource handle */
-+ uint32_t res_handle;
-+ /* Pointer to resource buffer */
-+ void *res_mem;
-+ /* Resource base size (bytes) */
-+ uint32_t res_base_size;
-+ /* Resource number */
-+ uint32_t res_num;
-+
-+} VC_SM_ALLOC_RESULT_T;
-+
-+/* Request to free a previously allocated memory (HOST->VC) */
-+typedef struct {
-+ /* Resource handle (returned from alloc) */
-+ uint32_t res_handle;
-+ /* Resource buffer (returned from alloc) */
-+ void *res_mem;
-+
-+} VC_SM_FREE_T;
-+
-+/* Request to lock a previously allocated memory (HOST->VC) */
-+typedef struct {
-+ /* Resource handle (returned from alloc) */
-+ uint32_t res_handle;
-+ /* Resource buffer (returned from alloc) */
-+ void *res_mem;
-+
-+} VC_SM_LOCK_UNLOCK_T;
-+
-+/* Request to resize a previously allocated memory (HOST->VC) */
-+typedef struct {
-+ /* Resource handle (returned from alloc) */
-+ uint32_t res_handle;
-+ /* Resource buffer (returned from alloc) */
-+ void *res_mem;
-+ /* Resource *new* size requested (bytes) */
-+ uint32_t res_new_size;
-+
-+} VC_SM_RESIZE_T;
-+
-+/* Result of a requested memory lock (VC->HOST) */
-+typedef struct {
-+ /* Transaction identifier */
-+ uint32_t trans_id;
-+
-+ /* Resource handle */
-+ uint32_t res_handle;
-+ /* Pointer to resource buffer */
-+ void *res_mem;
-+ /* Pointer to former resource buffer if the memory
-+ * was reallocated */
-+ void *res_old_mem;
-+
-+} VC_SM_LOCK_RESULT_T;
-+
-+/* Generic result for a request (VC->HOST) */
-+typedef struct {
-+ /* Transaction identifier */
-+ uint32_t trans_id;
-+
-+ int32_t success;
-+
-+} VC_SM_RESULT_T;
-+
-+/* Request to revert a previously applied action (HOST->VC) */
-+typedef struct {
-+ /* Action of interest */
-+ VC_SM_MSG_TYPE res_action;
-+ /* Transaction identifier for the action of interest */
-+ uint32_t action_trans_id;
-+
-+} VC_SM_ACTION_CLEAN_T;
-+
-+/* Request to remove all data associated with a given allocator (HOST->VC) */
-+typedef struct {
-+ /* Allocator identifier */
-+ uint32_t allocator;
-+
-+} VC_SM_FREE_ALL_T;
-+
-+/* Union of ALL messages */
-+typedef union {
-+ VC_SM_ALLOC_T alloc;
-+ VC_SM_ALLOC_RESULT_T alloc_result;
-+ VC_SM_FREE_T free;
-+ VC_SM_ACTION_CLEAN_T action_clean;
-+ VC_SM_RESIZE_T resize;
-+ VC_SM_LOCK_RESULT_T lock_result;
-+ VC_SM_RESULT_T result;
-+ VC_SM_FREE_ALL_T free_all;
-+
-+} VC_SM_MSG_UNION_T;
-+
-+#endif /* __VC_SM_DEFS_H__INCLUDED__ */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,55 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __VC_SM_KNL_H__INCLUDED__
-+#define __VC_SM_KNL_H__INCLUDED__
-+
-+#if !defined(__KERNEL__)
-+#error "This interface is for kernel use only..."
-+#endif
-+
-+/* Type of memory to be locked (ie mapped) */
-+typedef enum {
-+ VC_SM_LOCK_CACHED,
-+ VC_SM_LOCK_NON_CACHED,
-+
-+} VC_SM_LOCK_CACHE_MODE_T;
-+
-+/* Allocate a shared memory handle and block.
-+*/
-+int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle);
-+
-+/* Free a previously allocated shared memory handle and block.
-+*/
-+int vc_sm_free(int handle);
-+
-+/* Lock a memory handle for use by kernel.
-+*/
-+int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data);
-+
-+/* Unlock a memory handle in use by kernel.
-+*/
-+int vc_sm_unlock(int handle, int flush, int no_vc_unlock);
-+
-+/* Get an internal resource handle mapped from the external one.
-+*/
-+int vc_sm_int_handle(int handle);
-+
-+/* Map a shared memory region for use by kernel.
-+*/
-+int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data);
-+
-+#endif /* __VC_SM_KNL_H__INCLUDED__ */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,82 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __VC_VCHI_SM_H__INCLUDED__
-+#define __VC_VCHI_SM_H__INCLUDED__
-+
-+#include "interface/vchi/vchi.h"
-+
-+#include "vc_sm_defs.h"
-+
-+/* Forward declare.
-+*/
-+typedef struct sm_instance *VC_VCHI_SM_HANDLE_T;
-+
-+/* Initialize the shared memory service, opens up vchi connection to talk to it.
-+*/
-+VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
-+ VCHI_CONNECTION_T **vchi_connections,
-+ uint32_t num_connections);
-+
-+/* Terminates the shared memory service.
-+*/
-+int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle);
-+
-+/* Ask the shared memory service to allocate some memory on videocre and
-+** return the result of this allocation (which upon success will be a pointer
-+** to some memory in videocore space).
-+*/
-+int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_ALLOC_T *alloc,
-+ VC_SM_ALLOC_RESULT_T *alloc_result, uint32_t *trans_id);
-+
-+/* Ask the shared memory service to free up some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_FREE_T *free, uint32_t *trans_id);
-+
-+/* Ask the shared memory service to lock up some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *lock_unlock,
-+ VC_SM_LOCK_RESULT_T *lock_result, uint32_t *trans_id);
-+
-+/* Ask the shared memory service to unlock some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *lock_unlock,
-+ uint32_t *trans_id, uint8_t wait_reply);
-+
-+/* Ask the shared memory service to resize some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_RESIZE_T *resize, uint32_t *trans_id);
-+
-+/* Walk the allocated resources on the videocore side, the allocation will
-+** show up in the log. This is purely for debug/information and takes no
-+** specific actions.
-+*/
-+int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle);
-+
-+/* Clean up following a previously interrupted action which left the system
-+** in a bad state of some sort.
-+*/
-+int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_ACTION_CLEAN_T *action_clean);
-+
-+#endif /* __VC_VCHI_SM_H__INCLUDED__ */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,20 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#define VMALLOC_END (0xe8000000)
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h
---- linux-3.12.38/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,233 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*
-+*****************************************************************************/
-+
-+#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__)
-+#define __VMCS_SM_IOCTL_H__INCLUDED__
-+
-+/* ---- Include Files ---------------------------------------------------- */
-+
-+#if defined(__KERNEL__)
-+#include <linux/types.h> /* Needed for standard types */
-+#else
-+#include <stdint.h>
-+#endif
-+
-+#include <linux/ioctl.h>
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+#define VMCS_SM_RESOURCE_NAME 32
-+#define VMCS_SM_RESOURCE_NAME_DEFAULT "sm-host-resource"
-+
-+/* Type define used to create unique IOCTL number */
-+#define VMCS_SM_MAGIC_TYPE 'I'
-+
-+/* IOCTL commands */
-+enum vmcs_sm_cmd_e {
-+ VMCS_SM_CMD_ALLOC = 0x5A, /* Start at 0x5A arbitrarily */
-+ VMCS_SM_CMD_ALLOC_SHARE,
-+ VMCS_SM_CMD_LOCK,
-+ VMCS_SM_CMD_LOCK_CACHE,
-+ VMCS_SM_CMD_UNLOCK,
-+ VMCS_SM_CMD_RESIZE,
-+ VMCS_SM_CMD_UNMAP,
-+ VMCS_SM_CMD_FREE,
-+ VMCS_SM_CMD_FLUSH,
-+ VMCS_SM_CMD_INVALID,
-+
-+ VMCS_SM_CMD_SIZE_USR_HANDLE,
-+ VMCS_SM_CMD_CHK_USR_HANDLE,
-+
-+ VMCS_SM_CMD_MAPPED_USR_HANDLE,
-+ VMCS_SM_CMD_MAPPED_USR_ADDRESS,
-+ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,
-+ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,
-+ VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,
-+
-+ VMCS_SM_CMD_VC_WALK_ALLOC,
-+ VMCS_SM_CMD_HOST_WALK_MAP,
-+ VMCS_SM_CMD_HOST_WALK_PID_ALLOC,
-+ VMCS_SM_CMD_HOST_WALK_PID_MAP,
-+
-+ VMCS_SM_CMD_LAST /* Do no delete */
-+};
-+
-+/* Cache type supported, conveniently matches the user space definition in
-+** user-vcsm.h.
-+*/
-+enum vmcs_sm_cache_e {
-+ VMCS_SM_CACHE_NONE,
-+ VMCS_SM_CACHE_HOST,
-+ VMCS_SM_CACHE_VC,
-+ VMCS_SM_CACHE_BOTH,
-+};
-+
-+/* IOCTL Data structures */
-+struct vmcs_sm_ioctl_alloc {
-+ /* user -> kernel */
-+ unsigned int size;
-+ unsigned int num;
-+ enum vmcs_sm_cache_e cached;
-+ char name[VMCS_SM_RESOURCE_NAME];
-+
-+ /* kernel -> user */
-+ unsigned int handle;
-+ /* unsigned int base_addr; */
-+};
-+
-+struct vmcs_sm_ioctl_alloc_share {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_free {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ /* unsigned int base_addr; */
-+};
-+
-+struct vmcs_sm_ioctl_lock_unlock {
-+ /* user -> kernel */
-+ unsigned int handle;
-+
-+ /* kernel -> user */
-+ unsigned int addr;
-+};
-+
-+struct vmcs_sm_ioctl_lock_cache {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ enum vmcs_sm_cache_e cached;
-+};
-+
-+struct vmcs_sm_ioctl_resize {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ unsigned int new_size;
-+
-+ /* kernel -> user */
-+ unsigned int old_size;
-+};
-+
-+struct vmcs_sm_ioctl_map {
-+ /* user -> kernel */
-+ /* and kernel -> user */
-+ unsigned int pid;
-+ unsigned int handle;
-+ unsigned int addr;
-+
-+ /* kernel -> user */
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_walk {
-+ /* user -> kernel */
-+ unsigned int pid;
-+};
-+
-+struct vmcs_sm_ioctl_chk {
-+ /* user -> kernel */
-+ unsigned int handle;
-+
-+ /* kernel -> user */
-+ unsigned int addr;
-+ unsigned int size;
-+ enum vmcs_sm_cache_e cache;
-+};
-+
-+struct vmcs_sm_ioctl_size {
-+ /* user -> kernel */
-+ unsigned int handle;
-+
-+ /* kernel -> user */
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_cache {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ unsigned int addr;
-+ unsigned int size;
-+};
-+
-+/* IOCTL numbers */
-+#define VMCS_SM_IOCTL_MEM_ALLOC\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\
-+ struct vmcs_sm_ioctl_alloc)
-+#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\
-+ struct vmcs_sm_ioctl_alloc_share)
-+#define VMCS_SM_IOCTL_MEM_LOCK\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\
-+ struct vmcs_sm_ioctl_lock_unlock)
-+#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\
-+ struct vmcs_sm_ioctl_lock_cache)
-+#define VMCS_SM_IOCTL_MEM_UNLOCK\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\
-+ struct vmcs_sm_ioctl_lock_unlock)
-+#define VMCS_SM_IOCTL_MEM_RESIZE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\
-+ struct vmcs_sm_ioctl_resize)
-+#define VMCS_SM_IOCTL_MEM_FREE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\
-+ struct vmcs_sm_ioctl_free)
-+#define VMCS_SM_IOCTL_MEM_FLUSH\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\
-+ struct vmcs_sm_ioctl_cache)
-+#define VMCS_SM_IOCTL_MEM_INVALID\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\
-+ struct vmcs_sm_ioctl_cache)
-+
-+#define VMCS_SM_IOCTL_SIZE_USR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\
-+ struct vmcs_sm_ioctl_size)
-+#define VMCS_SM_IOCTL_CHK_USR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\
-+ struct vmcs_sm_ioctl_chk)
-+
-+#define VMCS_SM_IOCTL_MAP_USR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\
-+ struct vmcs_sm_ioctl_map)
-+
-+#define VMCS_SM_IOCTL_VC_WALK_ALLOC\
-+ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC)
-+#define VMCS_SM_IOCTL_HOST_WALK_MAP\
-+ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP)
-+#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\
-+ struct vmcs_sm_ioctl_walk)
-+#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\
-+ struct vmcs_sm_ioctl_walk)
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/Kconfig linux-rpi/arch/arm/mach-bcm2708/Kconfig
---- linux-3.12.38/arch/arm/mach-bcm2708/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/Kconfig 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,41 @@
-+menu "Broadcom BCM2708 Implementations"
-+ depends on ARCH_BCM2708
-+
-+config MACH_BCM2708
-+ bool "Broadcom BCM2708 Development Platform"
-+ select NEED_MACH_MEMORY_H
-+ select NEED_MACH_IO_H
-+ select CPU_V6
-+ help
-+ Include support for the Broadcom(R) BCM2708 platform.
-+
-+config BCM2708_GPIO
-+ bool "BCM2708 gpio support"
-+ depends on MACH_BCM2708
-+ select ARCH_REQUIRE_GPIOLIB
-+ default y
-+ help
-+ Include support for the Broadcom(R) BCM2708 gpio.
-+
-+config BCM2708_VCMEM
-+ bool "Videocore Memory"
-+ depends on MACH_BCM2708
-+ default y
-+ help
-+ Helper for videocore memory access and total size allocation.
-+
-+config BCM2708_NOL2CACHE
-+ bool "Videocore L2 cache disable"
-+ depends on MACH_BCM2708
-+ default n
-+ help
-+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
-+
-+config BCM2708_SPIDEV
-+ bool "Bind spidev to SPI0 master"
-+ depends on MACH_BCM2708
-+ depends on SPI
-+ default y
-+ help
-+ Binds spidev driver to the SPI0 master
-+endmenu
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/Makefile linux-rpi/arch/arm/mach-bcm2708/Makefile
---- linux-3.12.38/arch/arm/mach-bcm2708/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/Makefile 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,7 @@
-+#
-+# Makefile for the linux kernel.
-+#
-+
-+obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
-+obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
-+obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/Makefile.boot linux-rpi/arch/arm/mach-bcm2708/Makefile.boot
---- linux-3.12.38/arch/arm/mach-bcm2708/Makefile.boot 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/Makefile.boot 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,3 @@
-+ zreladdr-y := 0x00008000
-+params_phys-y := 0x00000100
-+initrd_phys-y := 0x00800000
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/power.c linux-rpi/arch/arm/mach-bcm2708/power.c
---- linux-3.12.38/arch/arm/mach-bcm2708/power.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/power.c 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,194 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/power.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for controlling the power to
-+ * VideoCore subsystems.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/semaphore.h>
-+#include <linux/bug.h>
-+#include <mach/power.h>
-+#include <mach/vcio.h>
-+#include <mach/arm_power.h>
-+
-+#define DRIVER_NAME "bcm2708_power"
-+
-+#define BCM_POWER_MAXCLIENTS 4
-+#define BCM_POWER_NOCLIENT (1<<31)
-+
-+/* Some drivers expect there devices to be permanently powered */
-+#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
-+
-+#if 1
-+#define DPRINTK printk
-+#else
-+#define DPRINTK if (0) printk
-+#endif
-+
-+struct state_struct {
-+ uint32_t global_request;
-+ uint32_t client_request[BCM_POWER_MAXCLIENTS];
-+ struct semaphore client_mutex;
-+ struct semaphore mutex;
-+} g_state;
-+
-+int bcm_power_open(BCM_POWER_HANDLE_T *handle)
-+{
-+ BCM_POWER_HANDLE_T i;
-+ int ret = -EBUSY;
-+
-+ down(&g_state.client_mutex);
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
-+ if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
-+ g_state.client_request[i] = BCM_POWER_NONE;
-+ *handle = i;
-+ ret = 0;
-+ break;
-+ }
-+ }
-+
-+ up(&g_state.client_mutex);
-+
-+ DPRINTK("bcm_power_open() -> %d\n", *handle);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_open);
-+
-+int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
-+{
-+ int rc = 0;
-+
-+ DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
-+
-+ if ((handle < BCM_POWER_MAXCLIENTS) &&
-+ (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
-+ if (down_interruptible(&g_state.mutex) != 0) {
-+ DPRINTK("bcm_power_request -> interrupted\n");
-+ return -EINTR;
-+ }
-+
-+ if (request != g_state.client_request[handle]) {
-+ uint32_t others_request = 0;
-+ uint32_t global_request;
-+ BCM_POWER_HANDLE_T i;
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
-+ if (i != handle)
-+ others_request |=
-+ g_state.client_request[i];
-+ }
-+ others_request &= ~BCM_POWER_NOCLIENT;
-+
-+ global_request = request | others_request;
-+ if (global_request != g_state.global_request) {
-+ uint32_t actual;
-+
-+ /* Send a request to VideoCore */
-+ bcm_mailbox_write(MBOX_CHAN_POWER,
-+ global_request << 4);
-+
-+ /* Wait for a response during power-up */
-+ if (global_request & ~g_state.global_request) {
-+ rc = bcm_mailbox_read(MBOX_CHAN_POWER,
-+ &actual);
-+ DPRINTK
-+ ("bcm_mailbox_read -> %08x, %d\n",
-+ actual, rc);
-+ actual >>= 4;
-+ } else {
-+ rc = 0;
-+ actual = global_request;
-+ }
-+
-+ if (rc == 0) {
-+ if (actual != global_request) {
-+ printk(KERN_ERR
-+ "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
-+ __func__,
-+ g_state.global_request,
-+ global_request, actual, request, others_request);
-+ /* A failure */
-+ BUG_ON((others_request & actual)
-+ != others_request);
-+ request &= actual;
-+ rc = -EIO;
-+ }
-+
-+ g_state.global_request = actual;
-+ g_state.client_request[handle] =
-+ request;
-+ }
-+ }
-+ }
-+ up(&g_state.mutex);
-+ } else {
-+ rc = -EINVAL;
-+ }
-+ DPRINTK("bcm_power_request -> %d\n", rc);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_request);
-+
-+int bcm_power_close(BCM_POWER_HANDLE_T handle)
-+{
-+ int rc;
-+
-+ DPRINTK("bcm_power_close(%d)\n", handle);
-+
-+ rc = bcm_power_request(handle, BCM_POWER_NONE);
-+ if (rc == 0)
-+ g_state.client_request[handle] = BCM_POWER_NOCLIENT;
-+
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_close);
-+
-+static int __init bcm_power_init(void)
-+{
-+#if defined(BCM_POWER_ALWAYS_ON)
-+ BCM_POWER_HANDLE_T always_on_handle;
-+#endif
-+ int rc = 0;
-+ int i;
-+
-+ printk(KERN_INFO "bcm_power: Broadcom power driver\n");
-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0);
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
-+ g_state.client_request[i] = BCM_POWER_NOCLIENT;
-+
-+ sema_init(&g_state.client_mutex, 1);
-+ sema_init(&g_state.mutex, 1);
-+
-+ g_state.global_request = 0;
-+
-+#if defined(BCM_POWER_ALWAYS_ON)
-+ if (BCM_POWER_ALWAYS_ON) {
-+ bcm_power_open(&always_on_handle);
-+ bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
-+ }
-+#endif
-+
-+ return rc;
-+}
-+
-+static void __exit bcm_power_exit(void)
-+{
-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0);
-+}
-+
-+arch_initcall(bcm_power_init); /* Initialize early */
-+module_exit(bcm_power_exit);
-+
-+MODULE_AUTHOR("Phil Elwell");
-+MODULE_DESCRIPTION("Interface to BCM2708 power management");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/vcio.c linux-rpi/arch/arm/mach-bcm2708/vcio.c
---- linux-3.12.38/arch/arm/mach-bcm2708/vcio.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/vcio.c 2015-03-10 17:26:49.718216697 +0100
-@@ -0,0 +1,474 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/vcio.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for writing to the mailboxes,
-+ * semaphores, doorbells etc. that are shared between the ARM and the
-+ * VideoCore processor
-+ */
-+
-+#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include <linux/module.h>
-+#include <linux/console.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+#include <linux/sysrq.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+
-+#include <linux/io.h>
-+
-+#include <mach/vcio.h>
-+#include <mach/platform.h>
-+
-+#include <asm/uaccess.h>
-+
-+
-+#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
-+
-+/* ----------------------------------------------------------------------
-+ * Mailbox
-+ * -------------------------------------------------------------------- */
-+
-+/* offsets from a mail box base address */
-+#define MAIL_WRT 0x00 /* write - and next 4 words */
-+#define MAIL_RD 0x00 /* read - and next 4 words */
-+#define MAIL_POL 0x10 /* read without popping the fifo */
-+#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
-+#define MAIL_STA 0x18 /* status */
-+#define MAIL_CNF 0x1C /* configuration */
-+
-+#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
-+#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
-+#define MBOX_CHAN(msg) ((msg) & 0xf)
-+#define MBOX_DATA28(msg) ((msg) & ~0xf)
-+#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
-+
-+#define MBOX_MAGIC 0xd0d0c0de
-+
-+struct vc_mailbox {
-+ struct device *dev; /* parent device */
-+ void __iomem *status;
-+ void __iomem *config;
-+ void __iomem *read;
-+ void __iomem *write;
-+ uint32_t msg[MBOX_CHAN_COUNT];
-+ struct semaphore sema[MBOX_CHAN_COUNT];
-+ uint32_t magic;
-+};
-+
-+static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
-+ uint32_t addr_mbox)
-+{
-+ int i;
-+
-+ mbox_out->dev = dev;
-+ mbox_out->status = __io_address(addr_mbox + MAIL_STA);
-+ mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
-+ mbox_out->read = __io_address(addr_mbox + MAIL_RD);
-+ /* Write to the other mailbox */
-+ mbox_out->write =
-+ __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
-+ MAIL_WRT);
-+
-+ for (i = 0; i < MBOX_CHAN_COUNT; i++) {
-+ mbox_out->msg[i] = 0;
-+ sema_init(&mbox_out->sema[i], 0);
-+ }
-+
-+ /* Enable the interrupt on data reception */
-+ writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
-+
-+ mbox_out->magic = MBOX_MAGIC;
-+}
-+
-+static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
-+{
-+ int rc;
-+
-+ if (mbox->magic != MBOX_MAGIC)
-+ rc = -EINVAL;
-+ else {
-+ /* wait for the mailbox FIFO to have some space in it */
-+ while (0 != (readl(mbox->status) & ARM_MS_FULL))
-+ cpu_relax();
-+
-+ writel(MBOX_MSG(chan, data28), mbox->write);
-+ rc = 0;
-+ }
-+ return rc;
-+}
-+
-+static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
-+{
-+ int rc;
-+
-+ if (mbox->magic != MBOX_MAGIC)
-+ rc = -EINVAL;
-+ else {
-+ down(&mbox->sema[chan]);
-+ *data28 = MBOX_DATA28(mbox->msg[chan]);
-+ mbox->msg[chan] = 0;
-+ rc = 0;
-+ }
-+ return rc;
-+}
-+
-+static irqreturn_t mbox_irq(int irq, void *dev_id)
-+{
-+ /* wait for the mailbox FIFO to have some data in it */
-+ struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
-+ int status = readl(mbox->status);
-+ int ret = IRQ_NONE;
-+
-+ while (!(status & ARM_MS_EMPTY)) {
-+ uint32_t msg = readl(mbox->read);
-+ int chan = MBOX_CHAN(msg);
-+ if (chan < MBOX_CHAN_COUNT) {
-+ if (mbox->msg[chan]) {
-+ /* Overflow */
-+ printk(KERN_ERR DRIVER_NAME
-+ ": mbox chan %d overflow - drop %08x\n",
-+ chan, msg);
-+ } else {
-+ mbox->msg[chan] = (msg | 0xf);
-+ up(&mbox->sema[chan]);
-+ }
-+ } else {
-+ printk(KERN_ERR DRIVER_NAME
-+ ": invalid channel selector (msg %08x)\n", msg);
-+ }
-+ ret = IRQ_HANDLED;
-+ status = readl(mbox->status);
-+ }
-+ return ret;
-+}
-+
-+static struct irqaction mbox_irqaction = {
-+ .name = "ARM Mailbox IRQ",
-+ .flags = IRQF_DISABLED | IRQF_IRQPOLL,
-+ .handler = mbox_irq,
-+};
-+
-+/* ----------------------------------------------------------------------
-+ * Mailbox Methods
-+ * -------------------------------------------------------------------- */
-+
-+static struct device *mbox_dev; /* we assume there's only one! */
-+
-+static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
-+{
-+ int rc;
-+
-+ struct vc_mailbox *mailbox = dev_get_drvdata(dev);
-+ device_lock(dev);
-+ rc = mbox_write(mailbox, chan, data28);
-+ device_unlock(dev);
-+
-+ return rc;
-+}
-+
-+static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
-+{
-+ int rc;
-+
-+ struct vc_mailbox *mailbox = dev_get_drvdata(dev);
-+ device_lock(dev);
-+ rc = mbox_read(mailbox, chan, data28);
-+ device_unlock(dev);
-+
-+ return rc;
-+}
-+
-+extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
-+{
-+ if (mbox_dev)
-+ return dev_mbox_write(mbox_dev, chan, data28);
-+ else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_write);
-+
-+extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
-+{
-+ if (mbox_dev)
-+ return dev_mbox_read(mbox_dev, chan, data28);
-+ else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_read);
-+
-+static void dev_mbox_register(const char *dev_name, struct device *dev)
-+{
-+ mbox_dev = dev;
-+}
-+
-+static int mbox_copy_from_user(void *dst, const void *src, int size)
-+{
-+ if ( (uint32_t)src < TASK_SIZE)
-+ {
-+ return copy_from_user(dst, src, size);
-+ }
-+ else
-+ {
-+ memcpy( dst, src, size );
-+ return 0;
-+ }
-+}
-+
-+static int mbox_copy_to_user(void *dst, const void *src, int size)
-+{
-+ if ( (uint32_t)dst < TASK_SIZE)
-+ {
-+ return copy_to_user(dst, src, size);
-+ }
-+ else
-+ {
-+ memcpy( dst, src, size );
-+ return 0;
-+ }
-+}
-+
-+static DEFINE_MUTEX(mailbox_lock);
-+extern int bcm_mailbox_property(void *data, int size)
-+{
-+ uint32_t success;
-+ dma_addr_t mem_bus; /* the memory address accessed from videocore */
-+ void *mem_kern; /* the memory address accessed from driver */
-+ int s = 0;
-+
-+ mutex_lock(&mailbox_lock);
-+ /* allocate some memory for the messages communicating with GPU */
-+ mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
-+ if (mem_kern) {
-+ /* create the message */
-+ mbox_copy_from_user(mem_kern, data, size);
-+
-+ /* send the message */
-+ wmb();
-+ s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
-+ if (s == 0) {
-+ s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
-+ }
-+ if (s == 0) {
-+ /* copy the response */
-+ rmb();
-+ mbox_copy_to_user(data, mem_kern, size);
-+ }
-+ dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
-+ } else {
-+ s = -ENOMEM;
-+ }
-+ if (s != 0)
-+ printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
-+
-+ mutex_unlock(&mailbox_lock);
-+ return s;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_property);
-+
-+/* ----------------------------------------------------------------------
-+ * Platform Device for Mailbox
-+ * -------------------------------------------------------------------- */
-+
-+/*
-+ * Is the device open right now? Used to prevent
-+ * concurent access into the same device
-+ */
-+static int Device_Open = 0;
-+
-+/*
-+ * This is called whenever a process attempts to open the device file
-+ */
-+static int device_open(struct inode *inode, struct file *file)
-+{
-+ /*
-+ * We don't want to talk to two processes at the same time
-+ */
-+ if (Device_Open)
-+ return -EBUSY;
-+
-+ Device_Open++;
-+ /*
-+ * Initialize the message
-+ */
-+ try_module_get(THIS_MODULE);
-+ return 0;
-+}
-+
-+static int device_release(struct inode *inode, struct file *file)
-+{
-+ /*
-+ * We're now ready for our next caller
-+ */
-+ Device_Open--;
-+
-+ module_put(THIS_MODULE);
-+ return 0;
-+}
-+
-+/*
-+ * This function is called whenever a process tries to do an ioctl on our
-+ * device file. We get two extra parameters (additional to the inode and file
-+ * structures, which all device functions get): the number of the ioctl called
-+ * and the parameter given to the ioctl function.
-+ *
-+ * If the ioctl is write or read/write (meaning output is returned to the
-+ * calling process), the ioctl call returns the output of this function.
-+ *
-+ */
-+static long device_ioctl(struct file *file, /* see include/linux/fs.h */
-+ unsigned int ioctl_num, /* number and param for ioctl */
-+ unsigned long ioctl_param)
-+{
-+ unsigned size;
-+ /*
-+ * Switch according to the ioctl called
-+ */
-+ switch (ioctl_num) {
-+ case IOCTL_MBOX_PROPERTY:
-+ /*
-+ * Receive a pointer to a message (in user space) and set that
-+ * to be the device's message. Get the parameter given to
-+ * ioctl by the process.
-+ */
-+ mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
-+ return bcm_mailbox_property((void *)ioctl_param, size);
-+ break;
-+ default:
-+ printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/* Module Declarations */
-+
-+/*
-+ * This structure will hold the functions to be called
-+ * when a process does something to the device we
-+ * created. Since a pointer to this structure is kept in
-+ * the devices table, it can't be local to
-+ * init_module. NULL is for unimplemented functios.
-+ */
-+struct file_operations fops = {
-+ .unlocked_ioctl = device_ioctl,
-+ .open = device_open,
-+ .release = device_release, /* a.k.a. close */
-+};
-+
-+static int bcm_vcio_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+ struct vc_mailbox *mailbox;
-+
-+ mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
-+ if (NULL == mailbox) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "mailbox memory\n");
-+ ret = -ENOMEM;
-+ } else {
-+ struct resource *res;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (res == NULL) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
-+ "resource\n");
-+ ret = -ENODEV;
-+ kfree(mailbox);
-+ } else {
-+ /* should be based on the registers from res really */
-+ mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
-+
-+ platform_set_drvdata(pdev, mailbox);
-+ dev_mbox_register(DRIVER_NAME, &pdev->dev);
-+
-+ mbox_irqaction.dev_id = mailbox;
-+ setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
-+ printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
-+ __io_address(ARM_0_MAIL0_RD));
-+ }
-+ }
-+
-+ if (ret == 0) {
-+ /*
-+ * Register the character device
-+ */
-+ ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
-+
-+ /*
-+ * Negative values signify an error
-+ */
-+ if (ret < 0) {
-+ printk(KERN_ERR DRIVER_NAME
-+ "Failed registering the character device %d\n", ret);
-+ return ret;
-+ }
-+ }
-+ return ret;
-+}
-+
-+static int bcm_vcio_remove(struct platform_device *pdev)
-+{
-+ struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(mailbox);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm_mbox_driver = {
-+ .probe = bcm_vcio_probe,
-+ .remove = bcm_vcio_remove,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init bcm_mbox_init(void)
-+{
-+ int ret;
-+
-+ printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
-+
-+ ret = platform_driver_register(&bcm_mbox_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to register "
-+ "on platform\n");
-+ }
-+
-+ return ret;
-+}
-+
-+static void __exit bcm_mbox_exit(void)
-+{
-+ platform_driver_unregister(&bcm_mbox_driver);
-+}
-+
-+arch_initcall(bcm_mbox_init); /* Initialize early */
-+module_exit(bcm_mbox_exit);
-+
-+MODULE_AUTHOR("Gray Girling");
-+MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:bcm-mbox");
-diff -Nur linux-3.12.38/arch/arm/mach-bcm2708/vc_mem.c linux-rpi/arch/arm/mach-bcm2708/vc_mem.c
---- linux-3.12.38/arch/arm/mach-bcm2708/vc_mem.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/arch/arm/mach-bcm2708/vc_mem.c 2015-03-09 10:39:28.582893746 +0100
-@@ -0,0 +1,432 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/debugfs.h>
-+#include <asm/uaccess.h>
-+#include <linux/dma-mapping.h>
-+
-+#ifdef CONFIG_ARCH_KONA
-+#include <chal/chal_ipc.h>
-+#elif CONFIG_ARCH_BCM2708
-+#else
-+#include <csp/chal_ipc.h>
-+#endif
-+
-+#include "mach/vc_mem.h"
-+#include <mach/vcio.h>
-+
-+#define DRIVER_NAME "vc-mem"
-+
-+// Device (/dev) related variables
-+static dev_t vc_mem_devnum = 0;
-+static struct class *vc_mem_class = NULL;
-+static struct cdev vc_mem_cdev;
-+static int vc_mem_inited = 0;
-+
-+#ifdef CONFIG_DEBUG_FS
-+static struct dentry *vc_mem_debugfs_entry;
-+#endif
-+
-+/*
-+ * Videocore memory addresses and size
-+ *
-+ * Drivers that wish to know the videocore memory addresses and sizes should
-+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
-+ * headers. This allows the other drivers to not be tied down to a a certain
-+ * address/size at compile time.
-+ *
-+ * In the future, the goal is to have the videocore memory virtual address and
-+ * size be calculated at boot time rather than at compile time. The decision of
-+ * where the videocore memory resides and its size would be in the hands of the
-+ * bootloader (and/or kernel). When that happens, the values of these variables
-+ * would be calculated and assigned in the init function.
-+ */
-+// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
-+unsigned long mm_vc_mem_phys_addr = 0x00000000;
-+unsigned int mm_vc_mem_size = 0;
-+unsigned int mm_vc_mem_base = 0;
-+
-+EXPORT_SYMBOL(mm_vc_mem_phys_addr);
-+EXPORT_SYMBOL(mm_vc_mem_size);
-+EXPORT_SYMBOL(mm_vc_mem_base);
-+
-+static uint phys_addr = 0;
-+static uint mem_size = 0;
-+static uint mem_base = 0;
-+
-+
-+/****************************************************************************
-+*
-+* vc_mem_open
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_open(struct inode *inode, struct file *file)
-+{
-+ (void) inode;
-+ (void) file;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_release
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_release(struct inode *inode, struct file *file)
-+{
-+ (void) inode;
-+ (void) file;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_size
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_size(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_base
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_base(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_current_size
-+*
-+***************************************************************************/
-+
-+int
-+vc_mem_get_current_size(void)
-+{
-+ return mm_vc_mem_size;
-+}
-+
-+EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
-+
-+/****************************************************************************
-+*
-+* vc_mem_ioctl
-+*
-+***************************************************************************/
-+
-+static long
-+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int rc = 0;
-+
-+ (void) cmd;
-+ (void) arg;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ switch (cmd) {
-+ case VC_MEM_IOC_MEM_PHYS_ADDR:
-+ {
-+ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
-+ __func__, (void *) mm_vc_mem_phys_addr);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
-+ sizeof (mm_vc_mem_phys_addr)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_SIZE:
-+ {
-+ // Get the videocore memory size first
-+ vc_mem_get_size();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
-+ mm_vc_mem_size);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_size,
-+ sizeof (mm_vc_mem_size)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_BASE:
-+ {
-+ // Get the videocore memory base
-+ vc_mem_get_base();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
-+ mm_vc_mem_base);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+ sizeof (mm_vc_mem_base)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_LOAD:
-+ {
-+ // Get the videocore memory base
-+ vc_mem_get_base();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
-+ mm_vc_mem_base);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+ sizeof (mm_vc_mem_base)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ default:
-+ {
-+ return -ENOTTY;
-+ }
-+ }
-+ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_mmap
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+ int rc = 0;
-+ unsigned long length = vma->vm_end - vma->vm_start;
-+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
-+
-+ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
-+ __func__, (long) vma->vm_start, (long) vma->vm_end,
-+ (long) vma->vm_pgoff);
-+
-+ if (offset + length > mm_vc_mem_size) {
-+ pr_err("%s: length %ld is too big\n", __func__, length);
-+ return -EINVAL;
-+ }
-+ // Do not cache the memory map
-+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+
-+ rc = remap_pfn_range(vma, vma->vm_start,
-+ (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
-+ vma->vm_pgoff, length, vma->vm_page_prot);
-+ if (rc != 0) {
-+ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
-+ }
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for the driver.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_mem_fops = {
-+ .owner = THIS_MODULE,
-+ .open = vc_mem_open,
-+ .release = vc_mem_release,
-+ .unlocked_ioctl = vc_mem_ioctl,
-+ .mmap = vc_mem_mmap,
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void vc_mem_debugfs_deinit(void)
-+{
-+ debugfs_remove_recursive(vc_mem_debugfs_entry);
-+ vc_mem_debugfs_entry = NULL;
-+}
-+
-+
-+static int vc_mem_debugfs_init(
-+ struct device *dev)
-+{
-+ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
-+ if (!vc_mem_debugfs_entry) {
-+ dev_warn(dev, "could not create debugfs entry\n");
-+ return -EFAULT;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_phys_addr",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_phys_addr)) {
-+ dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_size",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_size)) {
-+ dev_warn(dev, "%s:could not create vc_mem_size entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_base",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_base)) {
-+ dev_warn(dev, "%s:could not create vc_mem_base entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ return 0;
-+
-+fail:
-+ vc_mem_debugfs_deinit();
-+ return -EFAULT;
-+}
-+
-+#endif /* CONFIG_DEBUG_FS */
-+
-+
-+/****************************************************************************
-+*
-+* vc_mem_init
-+*
-+***************************************************************************/
-+
-+static int __init
-+vc_mem_init(void)
-+{
-+ int rc = -EFAULT;
-+ struct device *dev;
-+
-+ pr_debug("%s: called\n", __func__);
-+
-+ mm_vc_mem_phys_addr = phys_addr;
-+ mm_vc_mem_size = mem_size;
-+ mm_vc_mem_base = mem_base;
-+
-+ vc_mem_get_size();
-+
-+ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
-+ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
-+
-+ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
-+ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
-+ __func__, rc);
-+ goto out_err;
-+ }
-+
-+ cdev_init(&vc_mem_cdev, &vc_mem_fops);
-+ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
-+ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
-+ goto out_unregister;
-+ }
-+
-+ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
-+ if (IS_ERR(vc_mem_class)) {
-+ rc = PTR_ERR(vc_mem_class);
-+ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
-+ goto out_cdev_del;
-+ }
-+
-+ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
-+ DRIVER_NAME);
-+ if (IS_ERR(dev)) {
-+ rc = PTR_ERR(dev);
-+ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
-+ goto out_class_destroy;
-+ }
-+
-+#ifdef CONFIG_DEBUG_FS
-+ /* don't fail if the debug entries cannot be created */
-+ vc_mem_debugfs_init(dev);
-+#endif
-+
-+ vc_mem_inited = 1;
-+ return 0;
-+
-+ device_destroy(vc_mem_class, vc_mem_devnum);
-+
-+ out_class_destroy:
-+ class_destroy(vc_mem_class);
-+ vc_mem_class = NULL;
-+
-+ out_cdev_del:
-+ cdev_del(&vc_mem_cdev);
-+
-+ out_unregister:
-+ unregister_chrdev_region(vc_mem_devnum, 1);
-+
-+ out_err:
-+ return -1;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_exit
-+*
-+***************************************************************************/
-+
-+static void __exit
-+vc_mem_exit(void)
-+{
-+ pr_debug("%s: called\n", __func__);
-+
-+ if (vc_mem_inited) {
-+#if CONFIG_DEBUG_FS
-+ vc_mem_debugfs_deinit();
-+#endif
-+ device_destroy(vc_mem_class, vc_mem_devnum);
-+ class_destroy(vc_mem_class);
-+ cdev_del(&vc_mem_cdev);
-+ unregister_chrdev_region(vc_mem_devnum, 1);
-+ }
-+}
-+
-+module_init(vc_mem_init);
-+module_exit(vc_mem_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-+
-+module_param(phys_addr, uint, 0644);
-+module_param(mem_size, uint, 0644);
-+module_param(mem_base, uint, 0644);
-+
-diff -Nur linux-3.12.38/arch/arm/mach-imx/clk-imx6q.c linux-rpi/arch/arm/mach-imx/clk-imx6q.c
---- linux-3.12.38/arch/arm/mach-imx/clk-imx6q.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mach-imx/clk-imx6q.c 2015-03-10 17:26:49.726216697 +0100
-@@ -304,8 +304,8 @@
- post_div_table[1].div = 1;
- post_div_table[2].div = 1;
- video_div_table[1].div = 1;
-- video_div_table[3].div = 1;
-- }
-+ video_div_table[2].div = 1;
-+ };
-
- /* type name parent_name base div_mask */
- clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
-diff -Nur linux-3.12.38/arch/arm/mach-mvebu/coherency.c linux-rpi/arch/arm/mach-mvebu/coherency.c
---- linux-3.12.38/arch/arm/mach-mvebu/coherency.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mach-mvebu/coherency.c 2015-03-10 17:26:49.738216697 +0100
-@@ -124,29 +124,6 @@
- {
- struct device_node *np;
-
-- /*
-- * The coherency fabric is needed:
-- * - For coherency between processors on Armada XP, so only
-- * when SMP is enabled.
-- * - For coherency between the processor and I/O devices, but
-- * this coherency requires many pre-requisites (write
-- * allocate cache policy, shareable pages, SMP bit set) that
-- * are only meant in SMP situations.
-- *
-- * Note that this means that on Armada 370, there is currently
-- * no way to use hardware I/O coherency, because even when
-- * CONFIG_SMP is enabled, is_smp() returns false due to the
-- * Armada 370 being a single-core processor. To lift this
-- * limitation, we would have to find a way to make the cache
-- * policy set to write-allocate (on all Armada SoCs), and to
-- * set the shareable attribute in page tables (on all Armada
-- * SoCs except the Armada 370). Unfortunately, such decisions
-- * are taken very early in the kernel boot process, at a point
-- * where we don't know yet on which SoC we are running.
-- */
-- if (!is_smp())
-- return 0;
--
- np = of_find_matching_node(NULL, of_coherency_table);
- if (np) {
- struct resource res;
-@@ -173,9 +150,6 @@
- {
- struct device_node *np;
-
-- if (!is_smp())
-- return 0;
--
- np = of_find_matching_node(NULL, of_coherency_table);
- if (np) {
- bus_register_notifier(&platform_bus_type,
-diff -Nur linux-3.12.38/arch/arm/mach-omap2/pm44xx.c linux-rpi/arch/arm/mach-omap2/pm44xx.c
---- linux-3.12.38/arch/arm/mach-omap2/pm44xx.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mach-omap2/pm44xx.c 2015-03-10 17:26:49.754216697 +0100
-@@ -146,6 +146,26 @@
- struct clockdomain *ducati_clkdm, *l3_2_clkdm;
- int ret = 0;
-
-+ if (omap_rev() == OMAP4430_REV_ES1_0) {
-+ WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
-+ return -ENODEV;
-+ }
-+
-+ pr_err("Power Management for TI OMAP4.\n");
-+ /*
-+ * OMAP4 chip PM currently works only with certain (newer)
-+ * versions of bootloaders. This is due to missing code in the
-+ * kernel to properly reset and initialize some devices.
-+ * http://www.spinics.net/lists/arm-kernel/msg218641.html
-+ */
-+ pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
-+
-+ ret = pwrdm_for_each(pwrdms_setup, NULL);
-+ if (ret) {
-+ pr_err("Failed to setup powerdomains\n");
-+ return ret;
-+ }
-+
- /*
- * The dynamic dependency between MPUSS -> MEMIF and
- * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
-@@ -196,15 +216,6 @@
-
- pr_info("Power Management for TI OMAP4+ devices.\n");
-
-- /*
-- * OMAP4 chip PM currently works only with certain (newer)
-- * versions of bootloaders. This is due to missing code in the
-- * kernel to properly reset and initialize some devices.
-- * http://www.spinics.net/lists/arm-kernel/msg218641.html
-- */
-- if (cpu_is_omap44xx())
-- pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
--
- ret = pwrdm_for_each(pwrdms_setup, NULL);
- if (ret) {
- pr_err("Failed to setup powerdomains.\n");
-diff -Nur linux-3.12.38/arch/arm/mach-omap2/timer.c linux-rpi/arch/arm/mach-omap2/timer.c
---- linux-3.12.38/arch/arm/mach-omap2/timer.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mach-omap2/timer.c 2015-03-10 17:26:49.758216697 +0100
-@@ -503,11 +503,11 @@
- rate = clk_get_rate(sys_clk);
- /* Numerator/denumerator values refer TRM Realtime Counter section */
- switch (rate) {
-- case 12000000:
-+ case 1200000:
- num = 64;
- den = 125;
- break;
-- case 13000000:
-+ case 1300000:
- num = 768;
- den = 1625;
- break;
-@@ -515,11 +515,11 @@
- num = 8;
- den = 25;
- break;
-- case 26000000:
-+ case 2600000:
- num = 384;
- den = 1625;
- break;
-- case 27000000:
-+ case 2700000:
- num = 256;
- den = 1125;
- break;
-diff -Nur linux-3.12.38/arch/arm/mach-shmobile/setup-sh73a0.c linux-rpi/arch/arm/mach-shmobile/setup-sh73a0.c
---- linux-3.12.38/arch/arm/mach-shmobile/setup-sh73a0.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mach-shmobile/setup-sh73a0.c 2015-03-10 17:26:49.782216697 +0100
-@@ -746,7 +746,6 @@
-
- static struct renesas_intc_irqpin_config irqpin0_platform_data = {
- .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
-- .control_parent = true,
- };
-
- static struct resource irqpin0_resources[] = {
-@@ -808,7 +807,6 @@
-
- static struct renesas_intc_irqpin_config irqpin2_platform_data = {
- .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
-- .control_parent = true,
- };
-
- static struct resource irqpin2_resources[] = {
-@@ -839,7 +837,6 @@
-
- static struct renesas_intc_irqpin_config irqpin3_platform_data = {
- .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
-- .control_parent = true,
- };
-
- static struct resource irqpin3_resources[] = {
-diff -Nur linux-3.12.38/arch/arm/Makefile linux-rpi/arch/arm/Makefile
---- linux-3.12.38/arch/arm/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/Makefile 2015-03-10 17:26:49.670216697 +0100
-@@ -146,6 +146,7 @@
- # by CONFIG_* macro name.
- machine-$(CONFIG_ARCH_AT91) += at91
- machine-$(CONFIG_ARCH_BCM) += bcm
-+machine-$(CONFIG_ARCH_BCM2708) += bcm2708
- machine-$(CONFIG_ARCH_BCM2835) += bcm2835
- machine-$(CONFIG_ARCH_CLPS711X) += clps711x
- machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
-diff -Nur linux-3.12.38/arch/arm/mm/dma-mapping.c linux-rpi/arch/arm/mm/dma-mapping.c
---- linux-3.12.38/arch/arm/mm/dma-mapping.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mm/dma-mapping.c 2015-03-10 17:26:49.790216697 +0100
-@@ -429,21 +429,12 @@
- map.type = MT_MEMORY_DMA_READY;
-
- /*
-- * Clear previous low-memory mapping to ensure that the
-- * TLB does not see any conflicting entries, then flush
-- * the TLB of the old entries before creating new mappings.
-- *
-- * This ensures that any speculatively loaded TLB entries
-- * (even though they may be rare) can not cause any problems,
-- * and ensures that this code is architecturally compliant.
-+ * Clear previous low-memory mapping
- */
- for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
- addr += PMD_SIZE)
- pmd_clear(pmd_off_k(addr));
-
-- flush_tlb_kernel_range(__phys_to_virt(start),
-- __phys_to_virt(end));
--
- iotable_init(&map, 1);
- }
- }
-diff -Nur linux-3.12.38/arch/arm/mm/Kconfig linux-rpi/arch/arm/mm/Kconfig
---- linux-3.12.38/arch/arm/mm/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mm/Kconfig 2015-03-10 17:26:49.790216697 +0100
-@@ -358,7 +358,7 @@
-
- # ARMv6
- config CPU_V6
-- bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
-+ bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
- select CPU_32v6
- select CPU_ABRT_EV6
- select CPU_CACHE_V6
-diff -Nur linux-3.12.38/arch/arm/mm/proc-v6.S linux-rpi/arch/arm/mm/proc-v6.S
---- linux-3.12.38/arch/arm/mm/proc-v6.S 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/mm/proc-v6.S 2015-03-10 17:26:49.790216697 +0100
-@@ -73,10 +73,19 @@
- *
- * IRQs are already disabled.
- */
-+
-+/* See jira SW-5991 for details of this workaround */
- ENTRY(cpu_v6_do_idle)
-- mov r1, #0
-- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
-- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
-+ .align 5
-+ mov r1, #2
-+1: subs r1, #1
-+ nop
-+ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
-+ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
-+ nop
-+ nop
-+ nop
-+ bne 1b
- mov pc, lr
-
- ENTRY(cpu_v6_dcache_clean_area)
-diff -Nur linux-3.12.38/arch/arm/tools/mach-types linux-rpi/arch/arm/tools/mach-types
---- linux-3.12.38/arch/arm/tools/mach-types 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm/tools/mach-types 2015-03-10 17:26:49.798216697 +0100
-@@ -522,6 +522,7 @@
- prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
- paz00 MACH_PAZ00 PAZ00 3128
- acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
-+bcm2708 MACH_BCM2708 BCM2708 3138
- ag5evm MACH_AG5EVM AG5EVM 3189
- ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
- wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
-diff -Nur linux-3.12.38/arch/arm64/include/asm/cputype.h linux-rpi/arch/arm64/include/asm/cputype.h
---- linux-3.12.38/arch/arm64/include/asm/cputype.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm64/include/asm/cputype.h 2015-03-10 17:26:49.798216697 +0100
-@@ -77,8 +77,6 @@
- return read_cpuid(ID_CTR_EL0);
- }
-
--void cpuinfo_store_cpu(void);
--
- #endif /* __ASSEMBLY__ */
-
- #endif
-diff -Nur linux-3.12.38/arch/arm64/kernel/setup.c linux-rpi/arch/arm64/kernel/setup.c
---- linux-3.12.38/arch/arm64/kernel/setup.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm64/kernel/setup.c 2015-03-10 17:26:49.802216697 +0100
-@@ -41,7 +41,6 @@
- #include <linux/memblock.h>
- #include <linux/of_fdt.h>
- #include <linux/of_platform.h>
--#include <linux/personality.h>
-
- #include <asm/cputype.h>
- #include <asm/elf.h>
-@@ -98,19 +97,6 @@
- printk("%s", buf);
- }
-
--struct cpuinfo_arm64 {
-- struct cpu cpu;
-- u32 reg_midr;
--};
--
--static DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
--
--void cpuinfo_store_cpu(void)
--{
-- struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
-- info->reg_midr = read_cpuid_id();
--}
--
- static void __init setup_processor(void)
- {
- struct cpu_info *cpu_info;
-@@ -141,8 +127,6 @@
- struct boot_param_header *devtree;
- unsigned long dt_root;
-
-- cpuinfo_store_cpu();
--
- /* Check we have a non-NULL DT pointer */
- if (!dt_phys) {
- early_print("\n"
-@@ -301,12 +285,14 @@
- }
- arch_initcall(arm64_device_init);
-
-+static DEFINE_PER_CPU(struct cpu, cpu_data);
-+
- static int __init topology_init(void)
- {
- int i;
-
- for_each_possible_cpu(i) {
-- struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
-+ struct cpu *cpu = &per_cpu(cpu_data, i);
- cpu->hotpluggable = 1;
- register_cpu(cpu, i);
- }
-@@ -321,41 +307,14 @@
- NULL
- };
-
--#ifdef CONFIG_COMPAT
--static const char *compat_hwcap_str[] = {
-- "swp",
-- "half",
-- "thumb",
-- "26bit",
-- "fastmult",
-- "fpa",
-- "vfp",
-- "edsp",
-- "java",
-- "iwmmxt",
-- "crunch",
-- "thumbee",
-- "neon",
-- "vfpv3",
-- "vfpv3d16",
-- "tls",
-- "vfpv4",
-- "idiva",
-- "idivt",
-- "vfpd32",
-- "lpae",
-- "evtstrm"
--};
--#endif /* CONFIG_COMPAT */
--
- static int c_show(struct seq_file *m, void *v)
- {
-- int i, j;
-+ int i;
-
-- for_each_online_cpu(i) {
-- struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
-- u32 midr = cpuinfo->reg_midr;
-+ seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-+ cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
-
-+ for_each_online_cpu(i) {
- /*
- * glibc reads /proc/cpuinfo to determine the number of
- * online processors, looking for lines beginning with
-@@ -364,34 +323,25 @@
- #ifdef CONFIG_SMP
- seq_printf(m, "processor\t: %d\n", i);
- #endif
--
-- /*
-- * Dump out the common processor features in a single line.
-- * Userspace should read the hwcaps with getauxval(AT_HWCAP)
-- * rather than attempting to parse this, but there's a body of
-- * software which does already (at least for 32-bit).
-- */
-- seq_puts(m, "Features\t:");
-- if (personality(current->personality) == PER_LINUX32) {
--#ifdef CONFIG_COMPAT
-- for (j = 0; compat_hwcap_str[j]; j++)
-- if (COMPAT_ELF_HWCAP & (1 << j))
-- seq_printf(m, " %s", compat_hwcap_str[j]);
--#endif /* CONFIG_COMPAT */
-- } else {
-- for (j = 0; hwcap_str[j]; j++)
-- if (elf_hwcap & (1 << j))
-- seq_printf(m, " %s", hwcap_str[j]);
-- }
-- seq_puts(m, "\n");
--
-- seq_printf(m, "CPU implementer\t: 0x%02x\n", (midr >> 24));
-- seq_printf(m, "CPU architecture: 8\n");
-- seq_printf(m, "CPU variant\t: 0x%x\n", ((midr >> 20) & 0xf));
-- seq_printf(m, "CPU part\t: 0x%03x\n", ((midr >> 4) & 0xfff));
-- seq_printf(m, "CPU revision\t: %d\n\n", (midr & 0xf));
- }
-
-+ /* dump out the processor features */
-+ seq_puts(m, "Features\t: ");
-+
-+ for (i = 0; hwcap_str[i]; i++)
-+ if (elf_hwcap & (1 << i))
-+ seq_printf(m, "%s ", hwcap_str[i]);
-+
-+ seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
-+ seq_printf(m, "CPU architecture: AArch64\n");
-+ seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
-+ seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
-+ seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
-+
-+ seq_puts(m, "\n");
-+
-+ seq_printf(m, "Hardware\t: %s\n", machine_name);
-+
- return 0;
- }
-
-diff -Nur linux-3.12.38/arch/arm64/kernel/smp.c linux-rpi/arch/arm64/kernel/smp.c
---- linux-3.12.38/arch/arm64/kernel/smp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/arm64/kernel/smp.c 2015-03-10 17:26:49.806216697 +0100
-@@ -200,11 +200,6 @@
- raw_spin_unlock(&boot_lock);
-
- /*
-- * Log the CPU info before it is marked online and might get read.
-- */
-- cpuinfo_store_cpu();
--
-- /*
- * OK, now it's safe to let the boot CPU continue. Wait for
- * the CPU migration code to notice that the CPU is online
- * before we continue.
-diff -Nur linux-3.12.38/arch/mips/kernel/irq_cpu.c linux-rpi/arch/mips/kernel/irq_cpu.c
---- linux-3.12.38/arch/mips/kernel/irq_cpu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/mips/kernel/irq_cpu.c 2015-03-10 17:26:49.886216696 +0100
-@@ -56,8 +56,6 @@
- .irq_mask_ack = mask_mips_irq,
- .irq_unmask = unmask_mips_irq,
- .irq_eoi = unmask_mips_irq,
-- .irq_disable = mask_mips_irq,
-- .irq_enable = unmask_mips_irq,
- };
-
- /*
-@@ -94,8 +92,6 @@
- .irq_mask_ack = mips_mt_cpu_irq_ack,
- .irq_unmask = unmask_mips_irq,
- .irq_eoi = unmask_mips_irq,
-- .irq_disable = mask_mips_irq,
-- .irq_enable = unmask_mips_irq,
- };
-
- void __init mips_cpu_irq_init(void)
-diff -Nur linux-3.12.38/arch/mips/kernel/smp.c linux-rpi/arch/mips/kernel/smp.c
---- linux-3.12.38/arch/mips/kernel/smp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/mips/kernel/smp.c 2015-03-10 17:26:49.886216696 +0100
-@@ -109,10 +109,10 @@
- else
- #endif /* CONFIG_MIPS_MT_SMTC */
- cpu_probe();
-+ cpu_report();
- per_cpu_trap_init(false);
- mips_clockevent_init();
- mp_ops->init_secondary();
-- cpu_report();
-
- /*
- * XXX parity protection should be folded in here when it's converted
-diff -Nur linux-3.12.38/arch/powerpc/crypto/sha1.c linux-rpi/arch/powerpc/crypto/sha1.c
---- linux-3.12.38/arch/powerpc/crypto/sha1.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/powerpc/crypto/sha1.c 2015-03-10 17:26:49.930216696 +0100
-@@ -154,5 +154,4 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm");
-
--MODULE_ALIAS_CRYPTO("sha1");
--MODULE_ALIAS_CRYPTO("sha1-powerpc");
-+MODULE_ALIAS("sha1-powerpc");
-diff -Nur linux-3.12.38/arch/powerpc/include/asm/reg.h linux-rpi/arch/powerpc/include/asm/reg.h
---- linux-3.12.38/arch/powerpc/include/asm/reg.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/powerpc/include/asm/reg.h 2015-03-10 17:26:49.934216696 +0100
-@@ -116,7 +116,6 @@
-
- /* Server variant */
- #define MSR_ (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
--#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
- #define MSR_KERNEL (MSR_ | MSR_64BIT)
- #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
- #define MSR_USER64 (MSR_USER32 | MSR_64BIT)
-diff -Nur linux-3.12.38/arch/powerpc/kernel/idle_power7.S linux-rpi/arch/powerpc/kernel/idle_power7.S
---- linux-3.12.38/arch/powerpc/kernel/idle_power7.S 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/powerpc/kernel/idle_power7.S 2015-03-10 17:26:49.942216696 +0100
-@@ -84,22 +84,6 @@
- std r9,_MSR(r1)
- std r1,PACAR1(r13)
-
-- /*
-- * Go to real mode to do the nap, as required by the architecture.
-- * Also, we need to be in real mode before setting hwthread_state,
-- * because as soon as we do that, another thread can switch
-- * the MMU context to the guest.
-- */
-- LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
-- li r6, MSR_RI
-- andc r6, r9, r6
-- LOAD_REG_ADDR(r7, power7_enter_nap_mode)
-- mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
-- mtspr SPRN_SRR0, r7
-- mtspr SPRN_SRR1, r5
-- rfid
--
--power7_enter_nap_mode:
- #ifdef CONFIG_KVM_BOOK3S_64_HV
- /* Tell KVM we're napping */
- li r4,KVM_HWTHREAD_IN_NAP
-diff -Nur linux-3.12.38/arch/powerpc/kernel/udbg_16550.c linux-rpi/arch/powerpc/kernel/udbg_16550.c
---- linux-3.12.38/arch/powerpc/kernel/udbg_16550.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/powerpc/kernel/udbg_16550.c 2015-03-10 17:26:49.950216696 +0100
-@@ -69,12 +69,8 @@
-
- static int udbg_uart_getc_poll(void)
- {
-- if (!udbg_uart_in)
-- return -1;
--
-- if (!(udbg_uart_in(UART_LSR) & LSR_DR))
-+ if (!udbg_uart_in || !(udbg_uart_in(UART_LSR) & LSR_DR))
- return udbg_uart_in(UART_RBR);
--
- return -1;
- }
-
-diff -Nur linux-3.12.38/arch/powerpc/platforms/cell/spufs/inode.c linux-rpi/arch/powerpc/platforms/cell/spufs/inode.c
---- linux-3.12.38/arch/powerpc/platforms/cell/spufs/inode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/powerpc/platforms/cell/spufs/inode.c 2015-03-10 17:26:49.966216696 +0100
-@@ -164,7 +164,7 @@
- struct dentry *dentry, *tmp;
-
- mutex_lock(&dir->d_inode->i_mutex);
-- list_for_each_entry_safe(dentry, tmp, &dir->d_subdirs, d_child) {
-+ list_for_each_entry_safe(dentry, tmp, &dir->d_subdirs, d_u.d_child) {
- spin_lock(&dentry->d_lock);
- if (!(d_unhashed(dentry)) && dentry->d_inode) {
- dget_dlock(dentry);
-diff -Nur linux-3.12.38/arch/powerpc/xmon/xmon.c linux-rpi/arch/powerpc/xmon/xmon.c
---- linux-3.12.38/arch/powerpc/xmon/xmon.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/powerpc/xmon/xmon.c 2015-03-10 17:26:49.978216695 +0100
-@@ -288,7 +288,6 @@
- args.token = rtas_token("set-indicator");
- if (args.token == RTAS_UNKNOWN_SERVICE)
- return;
-- args.token = cpu_to_be32(args.token);
- args.nargs = cpu_to_be32(3);
- args.nret = cpu_to_be32(1);
- args.rets = &args.args[3];
-diff -Nur linux-3.12.38/arch/s390/crypto/aes_s390.c linux-rpi/arch/s390/crypto/aes_s390.c
---- linux-3.12.38/arch/s390/crypto/aes_s390.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/s390/crypto/aes_s390.c 2015-03-10 17:26:49.982216695 +0100
-@@ -967,7 +967,7 @@
- module_init(aes_s390_init);
- module_exit(aes_s390_fini);
-
--MODULE_ALIAS_CRYPTO("aes-all");
-+MODULE_ALIAS("aes-all");
-
- MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
- MODULE_LICENSE("GPL");
-diff -Nur linux-3.12.38/arch/s390/crypto/des_s390.c linux-rpi/arch/s390/crypto/des_s390.c
---- linux-3.12.38/arch/s390/crypto/des_s390.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/s390/crypto/des_s390.c 2015-03-10 17:26:49.982216695 +0100
-@@ -616,8 +616,8 @@
- module_init(des_s390_init);
- module_exit(des_s390_exit);
-
--MODULE_ALIAS_CRYPTO("des");
--MODULE_ALIAS_CRYPTO("des3_ede");
-+MODULE_ALIAS("des");
-+MODULE_ALIAS("des3_ede");
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms");
-diff -Nur linux-3.12.38/arch/s390/crypto/ghash_s390.c linux-rpi/arch/s390/crypto/ghash_s390.c
---- linux-3.12.38/arch/s390/crypto/ghash_s390.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/s390/crypto/ghash_s390.c 2015-03-10 17:26:49.982216695 +0100
-@@ -160,7 +160,7 @@
- module_init(ghash_mod_init);
- module_exit(ghash_mod_exit);
-
--MODULE_ALIAS_CRYPTO("ghash");
-+MODULE_ALIAS("ghash");
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("GHASH Message Digest Algorithm, s390 implementation");
-diff -Nur linux-3.12.38/arch/s390/crypto/sha1_s390.c linux-rpi/arch/s390/crypto/sha1_s390.c
---- linux-3.12.38/arch/s390/crypto/sha1_s390.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/s390/crypto/sha1_s390.c 2015-03-10 17:26:49.982216695 +0100
-@@ -103,6 +103,6 @@
- module_init(sha1_s390_init);
- module_exit(sha1_s390_fini);
-
--MODULE_ALIAS_CRYPTO("sha1");
-+MODULE_ALIAS("sha1");
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm");
-diff -Nur linux-3.12.38/arch/s390/crypto/sha256_s390.c linux-rpi/arch/s390/crypto/sha256_s390.c
---- linux-3.12.38/arch/s390/crypto/sha256_s390.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/s390/crypto/sha256_s390.c 2015-03-10 17:26:49.982216695 +0100
-@@ -143,7 +143,7 @@
- module_init(sha256_s390_init);
- module_exit(sha256_s390_fini);
-
--MODULE_ALIAS_CRYPTO("sha256");
--MODULE_ALIAS_CRYPTO("sha224");
-+MODULE_ALIAS("sha256");
-+MODULE_ALIAS("sha224");
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA256 and SHA224 Secure Hash Algorithm");
-diff -Nur linux-3.12.38/arch/s390/crypto/sha512_s390.c linux-rpi/arch/s390/crypto/sha512_s390.c
---- linux-3.12.38/arch/s390/crypto/sha512_s390.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/s390/crypto/sha512_s390.c 2015-03-10 17:26:49.982216695 +0100
-@@ -86,7 +86,7 @@
- }
- };
-
--MODULE_ALIAS_CRYPTO("sha512");
-+MODULE_ALIAS("sha512");
-
- static int sha384_init(struct shash_desc *desc)
- {
-@@ -126,7 +126,7 @@
- }
- };
-
--MODULE_ALIAS_CRYPTO("sha384");
-+MODULE_ALIAS("sha384");
-
- static int __init init(void)
- {
-diff -Nur linux-3.12.38/arch/sparc/crypto/aes_glue.c linux-rpi/arch/sparc/crypto/aes_glue.c
---- linux-3.12.38/arch/sparc/crypto/aes_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/aes_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -499,6 +499,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("AES Secure Hash Algorithm, sparc64 aes opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("aes");
-+MODULE_ALIAS("aes");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/camellia_glue.c linux-rpi/arch/sparc/crypto/camellia_glue.c
---- linux-3.12.38/arch/sparc/crypto/camellia_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/camellia_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -322,6 +322,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Camellia Cipher Algorithm, sparc64 camellia opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("aes");
-+MODULE_ALIAS("aes");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/crc32c_glue.c linux-rpi/arch/sparc/crypto/crc32c_glue.c
---- linux-3.12.38/arch/sparc/crypto/crc32c_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/crc32c_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -176,6 +176,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("CRC32c (Castagnoli), sparc64 crc32c opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("crc32c");
-+MODULE_ALIAS("crc32c");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/des_glue.c linux-rpi/arch/sparc/crypto/des_glue.c
---- linux-3.12.38/arch/sparc/crypto/des_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/des_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -532,6 +532,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms, sparc64 des opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("des");
-+MODULE_ALIAS("des");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/md5_glue.c linux-rpi/arch/sparc/crypto/md5_glue.c
---- linux-3.12.38/arch/sparc/crypto/md5_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/md5_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -185,6 +185,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("MD5 Secure Hash Algorithm, sparc64 md5 opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("md5");
-+MODULE_ALIAS("md5");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/sha1_glue.c linux-rpi/arch/sparc/crypto/sha1_glue.c
---- linux-3.12.38/arch/sparc/crypto/sha1_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/sha1_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -180,6 +180,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, sparc64 sha1 opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("sha1");
-+MODULE_ALIAS("sha1");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/sha256_glue.c linux-rpi/arch/sparc/crypto/sha256_glue.c
---- linux-3.12.38/arch/sparc/crypto/sha256_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/sha256_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -237,7 +237,7 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm, sparc64 sha256 opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("sha224");
--MODULE_ALIAS_CRYPTO("sha256");
-+MODULE_ALIAS("sha224");
-+MODULE_ALIAS("sha256");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/sparc/crypto/sha512_glue.c linux-rpi/arch/sparc/crypto/sha512_glue.c
---- linux-3.12.38/arch/sparc/crypto/sha512_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/sparc/crypto/sha512_glue.c 2015-03-10 17:26:50.006216695 +0100
-@@ -222,7 +222,7 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA-384 and SHA-512 Secure Hash Algorithm, sparc64 sha512 opcode accelerated");
-
--MODULE_ALIAS_CRYPTO("sha384");
--MODULE_ALIAS_CRYPTO("sha512");
-+MODULE_ALIAS("sha384");
-+MODULE_ALIAS("sha512");
-
- #include "crop_devid.c"
-diff -Nur linux-3.12.38/arch/um/Kconfig.common linux-rpi/arch/um/Kconfig.common
---- linux-3.12.38/arch/um/Kconfig.common 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/um/Kconfig.common 2015-03-10 17:26:50.026216695 +0100
-@@ -7,7 +7,6 @@
- bool
- default y
- select HAVE_UID16
-- select HAVE_FUTEX_CMPXCHG if FUTEX
- select GENERIC_IRQ_SHOW
- select GENERIC_CPU_DEVICES
- select GENERIC_IO
-diff -Nur linux-3.12.38/arch/x86/boot/compressed/misc.c linux-rpi/arch/x86/boot/compressed/misc.c
---- linux-3.12.38/arch/x86/boot/compressed/misc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/boot/compressed/misc.c 2015-03-10 17:26:50.034216695 +0100
-@@ -401,8 +401,6 @@
- unsigned char *output,
- unsigned long output_len)
- {
-- unsigned char *output_orig = output;
--
- real_mode = rmode;
-
- sanitize_boot_params(real_mode);
-@@ -441,12 +439,7 @@
- debug_putstr("\nDecompressing Linux... ");
- decompress(input_data, input_len, NULL, NULL, output, NULL, error);
- parse_elf(output);
-- /*
-- * 32-bit always performs relocations. 64-bit relocations are only
-- * needed if kASLR has chosen a different load address.
-- */
-- if (!IS_ENABLED(CONFIG_X86_64) || output != output_orig)
-- handle_relocations(output, output_len);
-+ handle_relocations(output, output_len);
- debug_putstr("done.\nBooting the kernel.\n");
- return;
- }
-diff -Nur linux-3.12.38/arch/x86/crypto/aes_glue.c linux-rpi/arch/x86/crypto/aes_glue.c
---- linux-3.12.38/arch/x86/crypto/aes_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/aes_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -66,5 +66,5 @@
-
- MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm, asm optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("aes");
--MODULE_ALIAS_CRYPTO("aes-asm");
-+MODULE_ALIAS("aes");
-+MODULE_ALIAS("aes-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/aesni-intel_glue.c linux-rpi/arch/x86/crypto/aesni-intel_glue.c
---- linux-3.12.38/arch/x86/crypto/aesni-intel_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/aesni-intel_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -1373,4 +1373,4 @@
-
- MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm, Intel AES-NI instructions optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("aes");
-+MODULE_ALIAS("aes");
-diff -Nur linux-3.12.38/arch/x86/crypto/blowfish_glue.c linux-rpi/arch/x86/crypto/blowfish_glue.c
---- linux-3.12.38/arch/x86/crypto/blowfish_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/blowfish_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -481,5 +481,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Blowfish Cipher Algorithm, asm optimized");
--MODULE_ALIAS_CRYPTO("blowfish");
--MODULE_ALIAS_CRYPTO("blowfish-asm");
-+MODULE_ALIAS("blowfish");
-+MODULE_ALIAS("blowfish-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/camellia_aesni_avx2_glue.c linux-rpi/arch/x86/crypto/camellia_aesni_avx2_glue.c
---- linux-3.12.38/arch/x86/crypto/camellia_aesni_avx2_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/camellia_aesni_avx2_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -582,5 +582,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Camellia Cipher Algorithm, AES-NI/AVX2 optimized");
--MODULE_ALIAS_CRYPTO("camellia");
--MODULE_ALIAS_CRYPTO("camellia-asm");
-+MODULE_ALIAS("camellia");
-+MODULE_ALIAS("camellia-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/camellia_aesni_avx_glue.c linux-rpi/arch/x86/crypto/camellia_aesni_avx_glue.c
---- linux-3.12.38/arch/x86/crypto/camellia_aesni_avx_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/camellia_aesni_avx_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -574,5 +574,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Camellia Cipher Algorithm, AES-NI/AVX optimized");
--MODULE_ALIAS_CRYPTO("camellia");
--MODULE_ALIAS_CRYPTO("camellia-asm");
-+MODULE_ALIAS("camellia");
-+MODULE_ALIAS("camellia-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/camellia_glue.c linux-rpi/arch/x86/crypto/camellia_glue.c
---- linux-3.12.38/arch/x86/crypto/camellia_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/camellia_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -1725,5 +1725,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Camellia Cipher Algorithm, asm optimized");
--MODULE_ALIAS_CRYPTO("camellia");
--MODULE_ALIAS_CRYPTO("camellia-asm");
-+MODULE_ALIAS("camellia");
-+MODULE_ALIAS("camellia-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/cast5_avx_glue.c linux-rpi/arch/x86/crypto/cast5_avx_glue.c
---- linux-3.12.38/arch/x86/crypto/cast5_avx_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/cast5_avx_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -494,4 +494,4 @@
-
- MODULE_DESCRIPTION("Cast5 Cipher Algorithm, AVX optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("cast5");
-+MODULE_ALIAS("cast5");
-diff -Nur linux-3.12.38/arch/x86/crypto/cast6_avx_glue.c linux-rpi/arch/x86/crypto/cast6_avx_glue.c
---- linux-3.12.38/arch/x86/crypto/cast6_avx_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/cast6_avx_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -611,4 +611,4 @@
-
- MODULE_DESCRIPTION("Cast6 Cipher Algorithm, AVX optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("cast6");
-+MODULE_ALIAS("cast6");
-diff -Nur linux-3.12.38/arch/x86/crypto/crc32c-intel_glue.c linux-rpi/arch/x86/crypto/crc32c-intel_glue.c
---- linux-3.12.38/arch/x86/crypto/crc32c-intel_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/crc32c-intel_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -280,5 +280,5 @@
- MODULE_DESCRIPTION("CRC32c (Castagnoli) optimization using Intel Hardware.");
- MODULE_LICENSE("GPL");
-
--MODULE_ALIAS_CRYPTO("crc32c");
--MODULE_ALIAS_CRYPTO("crc32c-intel");
-+MODULE_ALIAS("crc32c");
-+MODULE_ALIAS("crc32c-intel");
-diff -Nur linux-3.12.38/arch/x86/crypto/crc32-pclmul_glue.c linux-rpi/arch/x86/crypto/crc32-pclmul_glue.c
---- linux-3.12.38/arch/x86/crypto/crc32-pclmul_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/crc32-pclmul_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -197,5 +197,5 @@
- MODULE_AUTHOR("Alexander Boyko <alexander_boyko@xyratex.com>");
- MODULE_LICENSE("GPL");
-
--MODULE_ALIAS_CRYPTO("crc32");
--MODULE_ALIAS_CRYPTO("crc32-pclmul");
-+MODULE_ALIAS("crc32");
-+MODULE_ALIAS("crc32-pclmul");
-diff -Nur linux-3.12.38/arch/x86/crypto/crct10dif-pclmul_glue.c linux-rpi/arch/x86/crypto/crct10dif-pclmul_glue.c
---- linux-3.12.38/arch/x86/crypto/crct10dif-pclmul_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/crct10dif-pclmul_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -147,5 +147,5 @@
- MODULE_DESCRIPTION("T10 DIF CRC calculation accelerated with PCLMULQDQ.");
- MODULE_LICENSE("GPL");
-
--MODULE_ALIAS_CRYPTO("crct10dif");
--MODULE_ALIAS_CRYPTO("crct10dif-pclmul");
-+MODULE_ALIAS("crct10dif");
-+MODULE_ALIAS("crct10dif-pclmul");
-diff -Nur linux-3.12.38/arch/x86/crypto/fpu.c linux-rpi/arch/x86/crypto/fpu.c
---- linux-3.12.38/arch/x86/crypto/fpu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/fpu.c 2015-03-10 17:26:50.034216695 +0100
-@@ -17,7 +17,6 @@
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/slab.h>
--#include <linux/crypto.h>
- #include <asm/i387.h>
-
- struct crypto_fpu_ctx {
-@@ -160,5 +159,3 @@
- {
- crypto_unregister_template(&crypto_fpu_tmpl);
- }
--
--MODULE_ALIAS_CRYPTO("fpu");
-diff -Nur linux-3.12.38/arch/x86/crypto/ghash-clmulni-intel_glue.c linux-rpi/arch/x86/crypto/ghash-clmulni-intel_glue.c
---- linux-3.12.38/arch/x86/crypto/ghash-clmulni-intel_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/ghash-clmulni-intel_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -341,4 +341,4 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("GHASH Message Digest Algorithm, "
- "acclerated by PCLMULQDQ-NI");
--MODULE_ALIAS_CRYPTO("ghash");
-+MODULE_ALIAS("ghash");
-diff -Nur linux-3.12.38/arch/x86/crypto/salsa20_glue.c linux-rpi/arch/x86/crypto/salsa20_glue.c
---- linux-3.12.38/arch/x86/crypto/salsa20_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/salsa20_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -119,5 +119,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION ("Salsa20 stream cipher algorithm (optimized assembly version)");
--MODULE_ALIAS_CRYPTO("salsa20");
--MODULE_ALIAS_CRYPTO("salsa20-asm");
-+MODULE_ALIAS("salsa20");
-+MODULE_ALIAS("salsa20-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/serpent_avx2_glue.c linux-rpi/arch/x86/crypto/serpent_avx2_glue.c
---- linux-3.12.38/arch/x86/crypto/serpent_avx2_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/serpent_avx2_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -558,5 +558,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Serpent Cipher Algorithm, AVX2 optimized");
--MODULE_ALIAS_CRYPTO("serpent");
--MODULE_ALIAS_CRYPTO("serpent-asm");
-+MODULE_ALIAS("serpent");
-+MODULE_ALIAS("serpent-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/serpent_avx_glue.c linux-rpi/arch/x86/crypto/serpent_avx_glue.c
---- linux-3.12.38/arch/x86/crypto/serpent_avx_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/serpent_avx_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -617,4 +617,4 @@
-
- MODULE_DESCRIPTION("Serpent Cipher Algorithm, AVX optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("serpent");
-+MODULE_ALIAS("serpent");
-diff -Nur linux-3.12.38/arch/x86/crypto/serpent_sse2_glue.c linux-rpi/arch/x86/crypto/serpent_sse2_glue.c
---- linux-3.12.38/arch/x86/crypto/serpent_sse2_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/serpent_sse2_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -618,4 +618,4 @@
-
- MODULE_DESCRIPTION("Serpent Cipher Algorithm, SSE2 optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("serpent");
-+MODULE_ALIAS("serpent");
-diff -Nur linux-3.12.38/arch/x86/crypto/sha1_ssse3_glue.c linux-rpi/arch/x86/crypto/sha1_ssse3_glue.c
---- linux-3.12.38/arch/x86/crypto/sha1_ssse3_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/sha1_ssse3_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -237,4 +237,4 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
-
--MODULE_ALIAS_CRYPTO("sha1");
-+MODULE_ALIAS("sha1");
-diff -Nur linux-3.12.38/arch/x86/crypto/sha256_ssse3_glue.c linux-rpi/arch/x86/crypto/sha256_ssse3_glue.c
---- linux-3.12.38/arch/x86/crypto/sha256_ssse3_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/sha256_ssse3_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -318,5 +318,5 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated");
-
--MODULE_ALIAS_CRYPTO("sha256");
--MODULE_ALIAS_CRYPTO("sha224");
-+MODULE_ALIAS("sha256");
-+MODULE_ALIAS("sha384");
-diff -Nur linux-3.12.38/arch/x86/crypto/sha512_ssse3_glue.c linux-rpi/arch/x86/crypto/sha512_ssse3_glue.c
---- linux-3.12.38/arch/x86/crypto/sha512_ssse3_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/sha512_ssse3_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -326,5 +326,5 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA512 Secure Hash Algorithm, Supplemental SSE3 accelerated");
-
--MODULE_ALIAS_CRYPTO("sha512");
--MODULE_ALIAS_CRYPTO("sha384");
-+MODULE_ALIAS("sha512");
-+MODULE_ALIAS("sha384");
-diff -Nur linux-3.12.38/arch/x86/crypto/twofish_avx_glue.c linux-rpi/arch/x86/crypto/twofish_avx_glue.c
---- linux-3.12.38/arch/x86/crypto/twofish_avx_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/twofish_avx_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -579,4 +579,4 @@
-
- MODULE_DESCRIPTION("Twofish Cipher Algorithm, AVX optimized");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("twofish");
-+MODULE_ALIAS("twofish");
-diff -Nur linux-3.12.38/arch/x86/crypto/twofish_glue_3way.c linux-rpi/arch/x86/crypto/twofish_glue_3way.c
---- linux-3.12.38/arch/x86/crypto/twofish_glue_3way.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/twofish_glue_3way.c 2015-03-10 17:26:50.034216695 +0100
-@@ -495,5 +495,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Twofish Cipher Algorithm, 3-way parallel asm optimized");
--MODULE_ALIAS_CRYPTO("twofish");
--MODULE_ALIAS_CRYPTO("twofish-asm");
-+MODULE_ALIAS("twofish");
-+MODULE_ALIAS("twofish-asm");
-diff -Nur linux-3.12.38/arch/x86/crypto/twofish_glue.c linux-rpi/arch/x86/crypto/twofish_glue.c
---- linux-3.12.38/arch/x86/crypto/twofish_glue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/crypto/twofish_glue.c 2015-03-10 17:26:50.034216695 +0100
-@@ -96,5 +96,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION ("Twofish Cipher Algorithm, asm optimized");
--MODULE_ALIAS_CRYPTO("twofish");
--MODULE_ALIAS_CRYPTO("twofish-asm");
-+MODULE_ALIAS("twofish");
-+MODULE_ALIAS("twofish-asm");
-diff -Nur linux-3.12.38/arch/x86/include/asm/desc.h linux-rpi/arch/x86/include/asm/desc.h
---- linux-3.12.38/arch/x86/include/asm/desc.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/include/asm/desc.h 2015-03-10 17:26:50.038216695 +0100
-@@ -251,8 +251,7 @@
- gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
- }
-
--/* This intentionally ignores lm, since 32-bit apps don't have that field. */
--#define LDT_empty(info) \
-+#define _LDT_empty(info) \
- ((info)->base_addr == 0 && \
- (info)->limit == 0 && \
- (info)->contents == 0 && \
-@@ -262,18 +261,11 @@
- (info)->seg_not_present == 1 && \
- (info)->useable == 0)
-
--/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
--static inline bool LDT_zero(const struct user_desc *info)
--{
-- return (info->base_addr == 0 &&
-- info->limit == 0 &&
-- info->contents == 0 &&
-- info->read_exec_only == 0 &&
-- info->seg_32bit == 0 &&
-- info->limit_in_pages == 0 &&
-- info->seg_not_present == 0 &&
-- info->useable == 0);
--}
-+#ifdef CONFIG_X86_64
-+#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
-+#else
-+#define LDT_empty(info) (_LDT_empty(info))
-+#endif
-
- static inline void clear_LDT(void)
- {
-diff -Nur linux-3.12.38/arch/x86/include/asm/vsyscall.h linux-rpi/arch/x86/include/asm/vsyscall.h
---- linux-3.12.38/arch/x86/include/asm/vsyscall.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/include/asm/vsyscall.h 2015-03-10 17:26:50.042216695 +0100
-@@ -34,7 +34,7 @@
- native_read_tscp(&p);
- } else {
- /* Load per CPU data from GDT */
-- asm volatile ("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
-+ asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG));
- }
-
- return p;
-diff -Nur linux-3.12.38/arch/x86/Kconfig linux-rpi/arch/x86/Kconfig
---- linux-3.12.38/arch/x86/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/Kconfig 2015-03-10 17:26:50.030216695 +0100
-@@ -861,7 +861,7 @@
-
- config X86_UP_APIC
- bool "Local APIC support on uniprocessors"
-- depends on X86_32 && !SMP && !X86_32_NON_STANDARD
-+ depends on X86_32 && !SMP && !X86_32_NON_STANDARD && !PCI_MSI
- ---help---
- A local APIC (Advanced Programmable Interrupt Controller) is an
- integrated interrupt controller in the CPU. If you have a single-CPU
-@@ -872,10 +872,6 @@
- performance counters), and the NMI watchdog which detects hard
- lockups.
-
--config X86_UP_APIC_MSI
-- def_bool y
-- select X86_UP_APIC if X86_32 && !SMP && !X86_32_NON_STANDARD && PCI_MSI
--
- config X86_UP_IOAPIC
- bool "IO-APIC support on uniprocessors"
- depends on X86_UP_APIC
-diff -Nur linux-3.12.38/arch/x86/kernel/acpi/cstate.c linux-rpi/arch/x86/kernel/acpi/cstate.c
---- linux-3.12.38/arch/x86/kernel/acpi/cstate.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/acpi/cstate.c 2015-03-10 17:26:50.046216695 +0100
-@@ -87,9 +87,7 @@
- num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
-
- retval = 0;
-- /* If the HW does not support any sub-states in this C-state */
-- if (num_cstate_subtype == 0) {
-- pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", cx->address, edx_part);
-+ if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
- retval = -1;
- goto out;
- }
-diff -Nur linux-3.12.38/arch/x86/kernel/cpu/mshyperv.c linux-rpi/arch/x86/kernel/cpu/mshyperv.c
---- linux-3.12.38/arch/x86/kernel/cpu/mshyperv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/cpu/mshyperv.c 2015-03-10 17:26:50.050216695 +0100
-@@ -63,7 +63,6 @@
- .rating = 400, /* use this when running on Hyperv*/
- .read = read_hv_clock,
- .mask = CLOCKSOURCE_MASK(64),
-- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
- };
-
- static void __init ms_hyperv_init_platform(void)
-diff -Nur linux-3.12.38/arch/x86/kernel/cpu/perf_event_intel_uncore.c linux-rpi/arch/x86/kernel/cpu/perf_event_intel_uncore.c
---- linux-3.12.38/arch/x86/kernel/cpu/perf_event_intel_uncore.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/cpu/perf_event_intel_uncore.c 2015-03-10 17:26:50.054216695 +0100
-@@ -2764,17 +2764,6 @@
- return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
- }
-
--/*
-- * Using uncore_pmu_event_init pmu event_init callback
-- * as a detection point for uncore events.
-- */
--static int uncore_pmu_event_init(struct perf_event *event);
--
--static bool is_uncore_event(struct perf_event *event)
--{
-- return event->pmu->event_init == uncore_pmu_event_init;
--}
--
- static int
- uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
- {
-@@ -2789,18 +2778,13 @@
- return -EINVAL;
-
- n = box->n_events;
--
-- if (is_uncore_event(leader)) {
-- box->event_list[n] = leader;
-- n++;
-- }
--
-+ box->event_list[n] = leader;
-+ n++;
- if (!dogrp)
- return n;
-
- list_for_each_entry(event, &leader->sibling_list, group_entry) {
-- if (!is_uncore_event(event) ||
-- event->state <= PERF_EVENT_STATE_OFF)
-+ if (event->state <= PERF_EVENT_STATE_OFF)
- continue;
-
- if (n >= max_count)
-diff -Nur linux-3.12.38/arch/x86/kernel/early-quirks.c linux-rpi/arch/x86/kernel/early-quirks.c
---- linux-3.12.38/arch/x86/kernel/early-quirks.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/early-quirks.c 2015-03-10 17:26:50.054216695 +0100
-@@ -317,8 +317,8 @@
- INTEL_I915GM_IDS(gen3_stolen_size),
- INTEL_I945G_IDS(gen3_stolen_size),
- INTEL_I945GM_IDS(gen3_stolen_size),
-- INTEL_VLV_M_IDS(gen6_stolen_size),
-- INTEL_VLV_D_IDS(gen6_stolen_size),
-+ INTEL_VLV_M_IDS(gen3_stolen_size),
-+ INTEL_VLV_D_IDS(gen3_stolen_size),
- INTEL_PINEVIEW_IDS(gen3_stolen_size),
- INTEL_I965G_IDS(gen3_stolen_size),
- INTEL_G33_IDS(gen3_stolen_size),
-diff -Nur linux-3.12.38/arch/x86/kernel/kprobes/core.c linux-rpi/arch/x86/kernel/kprobes/core.c
---- linux-3.12.38/arch/x86/kernel/kprobes/core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/kprobes/core.c 2015-03-10 17:26:50.054216695 +0100
-@@ -1017,15 +1017,6 @@
- regs->flags &= ~X86_EFLAGS_IF;
- trace_hardirqs_off();
- regs->ip = (unsigned long)(jp->entry);
--
-- /*
-- * jprobes use jprobe_return() which skips the normal return
-- * path of the function, and this messes up the accounting of the
-- * function graph tracer to get messed up.
-- *
-- * Pause function graph tracing while performing the jprobe function.
-- */
-- pause_graph_tracing();
- return 1;
- }
-
-@@ -1051,25 +1042,24 @@
- struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
- u8 *addr = (u8 *) (regs->ip - 1);
- struct jprobe *jp = container_of(p, struct jprobe, kp);
-- void *saved_sp = kcb->jprobe_saved_sp;
-
- if ((addr > (u8 *) jprobe_return) &&
- (addr < (u8 *) jprobe_return_end)) {
-- if (stack_addr(regs) != saved_sp) {
-+ if (stack_addr(regs) != kcb->jprobe_saved_sp) {
- struct pt_regs *saved_regs = &kcb->jprobe_saved_regs;
- printk(KERN_ERR
- "current sp %p does not match saved sp %p\n",
-- stack_addr(regs), saved_sp);
-+ stack_addr(regs), kcb->jprobe_saved_sp);
- printk(KERN_ERR "Saved registers for jprobe %p\n", jp);
- show_regs(saved_regs);
- printk(KERN_ERR "Current registers\n");
- show_regs(regs);
- BUG();
- }
-- /* It's OK to start function graph tracing again */
-- unpause_graph_tracing();
- *regs = kcb->jprobe_saved_regs;
-- memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp));
-+ memcpy((kprobe_opcode_t *)(kcb->jprobe_saved_sp),
-+ kcb->jprobes_stack,
-+ MIN_STACK_SIZE(kcb->jprobe_saved_sp));
- preempt_enable_no_resched();
- return 1;
- }
-diff -Nur linux-3.12.38/arch/x86/kernel/tls.c linux-rpi/arch/x86/kernel/tls.c
---- linux-3.12.38/arch/x86/kernel/tls.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/tls.c 2015-03-10 17:26:50.058216695 +0100
-@@ -29,28 +29,7 @@
-
- static bool tls_desc_okay(const struct user_desc *info)
- {
-- /*
-- * For historical reasons (i.e. no one ever documented how any
-- * of the segmentation APIs work), user programs can and do
-- * assume that a struct user_desc that's all zeros except for
-- * entry_number means "no segment at all". This never actually
-- * worked. In fact, up to Linux 3.19, a struct user_desc like
-- * this would create a 16-bit read-write segment with base and
-- * limit both equal to zero.
-- *
-- * That was close enough to "no segment at all" until we
-- * hardened this function to disallow 16-bit TLS segments. Fix
-- * it up by interpreting these zeroed segments the way that they
-- * were almost certainly intended to be interpreted.
-- *
-- * The correct way to ask for "no segment at all" is to specify
-- * a user_desc that satisfies LDT_empty. To keep everything
-- * working, we accept both.
-- *
-- * Note that there's a similar kludge in modify_ldt -- look at
-- * the distinction between modes 1 and 0x11.
-- */
-- if (LDT_empty(info) || LDT_zero(info))
-+ if (LDT_empty(info))
- return true;
-
- /*
-@@ -92,7 +71,7 @@
- cpu = get_cpu();
-
- while (n-- > 0) {
-- if (LDT_empty(info) || LDT_zero(info))
-+ if (LDT_empty(info))
- desc->a = desc->b = 0;
- else
- fill_ldt(desc, info);
-diff -Nur linux-3.12.38/arch/x86/kernel/traps.c linux-rpi/arch/x86/kernel/traps.c
---- linux-3.12.38/arch/x86/kernel/traps.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/traps.c 2015-03-10 17:26:50.058216695 +0100
-@@ -369,7 +369,7 @@
- * for scheduling or signal handling. The actual stack switch is done in
- * entry.S
- */
--asmlinkage notrace __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
-+asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
- {
- struct pt_regs *regs = eregs;
- /* Did already sync */
-@@ -394,7 +394,7 @@
- struct pt_regs regs;
- };
-
--asmlinkage __visible notrace __kprobes
-+asmlinkage __visible
- struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
- {
- /*
-diff -Nur linux-3.12.38/arch/x86/kernel/tsc.c linux-rpi/arch/x86/kernel/tsc.c
---- linux-3.12.38/arch/x86/kernel/tsc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kernel/tsc.c 2015-03-10 17:26:50.058216695 +0100
-@@ -386,7 +386,7 @@
- goto success;
- }
- }
-- pr_info("Fast TSC calibration failed\n");
-+ pr_err("Fast TSC calibration failed\n");
- return 0;
-
- success:
-diff -Nur linux-3.12.38/arch/x86/kvm/cpuid.c linux-rpi/arch/x86/kvm/cpuid.c
---- linux-3.12.38/arch/x86/kvm/cpuid.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/cpuid.c 2015-03-10 17:26:50.062216695 +0100
-@@ -23,14 +23,14 @@
- #include "mmu.h"
- #include "trace.h"
-
--int kvm_update_cpuid(struct kvm_vcpu *vcpu)
-+void kvm_update_cpuid(struct kvm_vcpu *vcpu)
- {
- struct kvm_cpuid_entry2 *best;
- struct kvm_lapic *apic = vcpu->arch.apic;
-
- best = kvm_find_cpuid_entry(vcpu, 1, 0);
- if (!best)
-- return 0;
-+ return;
-
- /* Update OSXSAVE bit */
- if (cpu_has_xsave && best->function == 0x1) {
-@@ -46,15 +46,7 @@
- apic->lapic_timer.timer_mode_mask = 1 << 17;
- }
-
-- /* The existing code assumes virtual address is 48-bit in the canonical
-- * address checks; exit if it is ever changed */
-- best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
-- if (best && ((best->eax & 0xff00) >> 8) != 48 &&
-- ((best->eax & 0xff00) >> 8) != 0)
-- return -EINVAL;
--
- kvm_pmu_cpuid_update(vcpu);
-- return 0;
- }
-
- static int is_efer_nx(void)
-@@ -117,9 +109,10 @@
- }
- vcpu->arch.cpuid_nent = cpuid->nent;
- cpuid_fix_nx_cap(vcpu);
-+ r = 0;
- kvm_apic_set_version(vcpu);
- kvm_x86_ops->cpuid_update(vcpu);
-- r = kvm_update_cpuid(vcpu);
-+ kvm_update_cpuid(vcpu);
-
- out_free:
- vfree(cpuid_entries);
-@@ -143,7 +136,9 @@
- vcpu->arch.cpuid_nent = cpuid->nent;
- kvm_apic_set_version(vcpu);
- kvm_x86_ops->cpuid_update(vcpu);
-- r = kvm_update_cpuid(vcpu);
-+ kvm_update_cpuid(vcpu);
-+ return 0;
-+
- out:
- return r;
- }
-diff -Nur linux-3.12.38/arch/x86/kvm/cpuid.h linux-rpi/arch/x86/kvm/cpuid.h
---- linux-3.12.38/arch/x86/kvm/cpuid.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/cpuid.h 2015-03-10 17:26:50.062216695 +0100
-@@ -3,7 +3,7 @@
-
- #include "x86.h"
-
--int kvm_update_cpuid(struct kvm_vcpu *vcpu);
-+void kvm_update_cpuid(struct kvm_vcpu *vcpu);
- struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
- u32 function, u32 index);
- int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
-diff -Nur linux-3.12.38/arch/x86/kvm/emulate.c linux-rpi/arch/x86/kvm/emulate.c
---- linux-3.12.38/arch/x86/kvm/emulate.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/emulate.c 2015-03-10 17:26:50.062216695 +0100
-@@ -161,7 +161,6 @@
- #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
- #define NoWrite ((u64)1 << 45) /* No writeback */
- #define SrcWrite ((u64)1 << 46) /* Write back src operand */
--#define NearBranch ((u64)1 << 52) /* Near branches */
-
- #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
-
-@@ -1444,8 +1443,7 @@
-
- /* Does not support long mode */
- static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
-- u16 selector, int seg,
-- struct desc_struct *desc)
-+ u16 selector, int seg)
- {
- struct desc_struct seg_desc, old_desc;
- u8 dpl, rpl, cpl;
-@@ -1533,15 +1531,6 @@
- if (rpl > cpl || dpl != cpl)
- goto exception;
- }
-- /* in long-mode d/b must be clear if l is set */
-- if (seg_desc.d && seg_desc.l) {
-- u64 efer = 0;
--
-- ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
-- if (efer & EFER_LMA)
-- goto exception;
-- }
--
- /* CS(RPL) <- CPL */
- selector = (selector & 0xfffc) | cpl;
- break;
-@@ -1581,8 +1570,6 @@
- }
- load:
- ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
-- if (desc)
-- *desc = seg_desc;
- return X86EMUL_CONTINUE;
- exception:
- emulate_exception(ctxt, err_vec, err_code, true);
-@@ -1789,7 +1776,7 @@
- if (rc != X86EMUL_CONTINUE)
- return rc;
-
-- rc = load_segment_descriptor(ctxt, (u16)selector, seg, NULL);
-+ rc = load_segment_descriptor(ctxt, (u16)selector, seg);
- return rc;
- }
-
-@@ -1878,7 +1865,7 @@
- if (rc != X86EMUL_CONTINUE)
- return rc;
-
-- rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS, NULL);
-+ rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
- if (rc != X86EMUL_CONTINUE)
- return rc;
-
-@@ -1944,7 +1931,7 @@
- if (rc != X86EMUL_CONTINUE)
- return rc;
-
-- rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, NULL);
-+ rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
-
- if (rc != X86EMUL_CONTINUE)
- return rc;
-@@ -1983,47 +1970,44 @@
- static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
- {
- int rc;
-- unsigned short sel, old_sel;
-- struct desc_struct old_desc, new_desc;
-- const struct x86_emulate_ops *ops = ctxt->ops;
--
-- /* Assignment of RIP may only fail in 64-bit mode */
-- if (ctxt->mode == X86EMUL_MODE_PROT64)
-- ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
-- VCPU_SREG_CS);
-+ unsigned short sel;
-
- memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
-
-- rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, &new_desc);
-+ rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
- if (rc != X86EMUL_CONTINUE)
- return rc;
-
-- rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
-- if (rc != X86EMUL_CONTINUE) {
-- WARN_ON(!ctxt->mode != X86EMUL_MODE_PROT64);
-- /* assigning eip failed; restore the old cs */
-- ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
-- return rc;
-- }
-- return rc;
--}
--
--static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
--{
-- return assign_eip_near(ctxt, ctxt->src.val);
-+ ctxt->_eip = 0;
-+ memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
-+ return X86EMUL_CONTINUE;
- }
-
--static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
-+static int em_grp45(struct x86_emulate_ctxt *ctxt)
- {
-- int rc;
-- long int old_eip;
-+ int rc = X86EMUL_CONTINUE;
-
-- old_eip = ctxt->_eip;
-- rc = assign_eip_near(ctxt, ctxt->src.val);
-- if (rc != X86EMUL_CONTINUE)
-- return rc;
-- ctxt->src.val = old_eip;
-- rc = em_push(ctxt);
-+ switch (ctxt->modrm_reg) {
-+ case 2: /* call near abs */ {
-+ long int old_eip;
-+ old_eip = ctxt->_eip;
-+ rc = assign_eip_near(ctxt, ctxt->src.val);
-+ if (rc != X86EMUL_CONTINUE)
-+ break;
-+ ctxt->src.val = old_eip;
-+ rc = em_push(ctxt);
-+ break;
-+ }
-+ case 4: /* jmp abs */
-+ rc = assign_eip_near(ctxt, ctxt->src.val);
-+ break;
-+ case 5: /* jmp far */
-+ rc = em_jmp_far(ctxt);
-+ break;
-+ case 6: /* push */
-+ rc = em_push(ctxt);
-+ break;
-+ }
- return rc;
- }
-
-@@ -2060,33 +2044,21 @@
- static int em_ret_far(struct x86_emulate_ctxt *ctxt)
- {
- int rc;
-- unsigned long eip, cs;
-- u16 old_cs;
-+ unsigned long cs;
- int cpl = ctxt->ops->cpl(ctxt);
-- struct desc_struct old_desc, new_desc;
-- const struct x86_emulate_ops *ops = ctxt->ops;
-
-- if (ctxt->mode == X86EMUL_MODE_PROT64)
-- ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
-- VCPU_SREG_CS);
--
-- rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
-+ rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
- if (rc != X86EMUL_CONTINUE)
- return rc;
-+ if (ctxt->op_bytes == 4)
-+ ctxt->_eip = (u32)ctxt->_eip;
- rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
- if (rc != X86EMUL_CONTINUE)
- return rc;
- /* Outer-privilege level return is not implemented */
- if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
- return X86EMUL_UNHANDLEABLE;
-- rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, &new_desc);
-- if (rc != X86EMUL_CONTINUE)
-- return rc;
-- rc = assign_eip_far(ctxt, eip, new_desc.l);
-- if (rc != X86EMUL_CONTINUE) {
-- WARN_ON(!ctxt->mode != X86EMUL_MODE_PROT64);
-- ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
-- }
-+ rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
- return rc;
- }
-
-@@ -2127,7 +2099,7 @@
-
- memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
-
-- rc = load_segment_descriptor(ctxt, sel, seg, NULL);
-+ rc = load_segment_descriptor(ctxt, sel, seg);
- if (rc != X86EMUL_CONTINUE)
- return rc;
-
-@@ -2372,8 +2344,6 @@
- if ((msr_data & 0xfffc) == 0x0)
- return emulate_gp(ctxt, 0);
- ss_sel = (u16)(msr_data + 24);
-- rcx = (u32)rcx;
-- rdx = (u32)rdx;
- break;
- case X86EMUL_MODE_PROT64:
- cs_sel = (u16)(msr_data + 32);
-@@ -2509,19 +2479,19 @@
- * Now load segment descriptors. If fault happens at this stage
- * it is handled in a context of new task
- */
-- ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-
-@@ -2650,26 +2620,25 @@
- * Now load segment descriptors. If fault happenes at this stage
- * it is handled in a context of new task
- */
-- ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
-- NULL);
-+ ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-- ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, NULL);
-+ ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
- if (ret != X86EMUL_CONTINUE)
- return ret;
-
-@@ -2949,37 +2918,24 @@
- u16 sel, old_cs;
- ulong old_eip;
- int rc;
-- struct desc_struct old_desc, new_desc;
-- const struct x86_emulate_ops *ops = ctxt->ops;
-
-+ old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
- old_eip = ctxt->_eip;
-- ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
-
- memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
-- rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, &new_desc);
-- if (rc != X86EMUL_CONTINUE)
-+ if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
- return X86EMUL_CONTINUE;
-
-- rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
-- if (rc != X86EMUL_CONTINUE)
-- goto fail;
-+ ctxt->_eip = 0;
-+ memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
-
- ctxt->src.val = old_cs;
- rc = em_push(ctxt);
- if (rc != X86EMUL_CONTINUE)
-- goto fail;
-+ return rc;
-
- ctxt->src.val = old_eip;
-- rc = em_push(ctxt);
-- /* If we failed, we tainted the memory, but the very least we should
-- restore cs */
-- if (rc != X86EMUL_CONTINUE)
-- goto fail;
-- return rc;
--fail:
-- ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
-- return rc;
--
-+ return em_push(ctxt);
- }
-
- static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
-@@ -3125,7 +3081,7 @@
-
- /* Disable writeback. */
- ctxt->dst.type = OP_NONE;
-- return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg, NULL);
-+ return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
- }
-
- static int em_lldt(struct x86_emulate_ctxt *ctxt)
-@@ -3134,7 +3090,7 @@
-
- /* Disable writeback. */
- ctxt->dst.type = OP_NONE;
-- return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR, NULL);
-+ return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
- }
-
- static int em_ltr(struct x86_emulate_ctxt *ctxt)
-@@ -3143,7 +3099,7 @@
-
- /* Disable writeback. */
- ctxt->dst.type = OP_NONE;
-- return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR, NULL);
-+ return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
- }
-
- static int em_invlpg(struct x86_emulate_ctxt *ctxt)
-@@ -3658,11 +3614,11 @@
- static const struct opcode group5[] = {
- F(DstMem | SrcNone | Lock, em_inc),
- F(DstMem | SrcNone | Lock, em_dec),
-- I(SrcMem | NearBranch, em_call_near_abs),
-+ I(SrcMem | Stack, em_grp45),
- I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
-- I(SrcMem | NearBranch, em_jmp_abs),
-- I(SrcMemFAddr | ImplicitOps, em_jmp_far),
-- I(SrcMem | Stack, em_push), D(Undefined),
-+ I(SrcMem | Stack, em_grp45),
-+ I(SrcMemFAddr | ImplicitOps, em_grp45),
-+ I(SrcMem | Stack, em_grp45), D(Undefined),
- };
-
- static const struct opcode group6[] = {
-@@ -3824,7 +3780,7 @@
- I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
- I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
- /* 0x70 - 0x7F */
-- X16(D(SrcImmByte | NearBranch)),
-+ X16(D(SrcImmByte)),
- /* 0x80 - 0x87 */
- G(ByteOp | DstMem | SrcImm, group1),
- G(DstMem | SrcImm, group1),
-@@ -3862,8 +3818,8 @@
- X8(I(DstReg | SrcImm64 | Mov, em_mov)),
- /* 0xC0 - 0xC7 */
- G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
-- I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
-- I(ImplicitOps | NearBranch, em_ret),
-+ I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
-+ I(ImplicitOps | Stack, em_ret),
- I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
- I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
- G(ByteOp, group11), G(0, group11),
-@@ -3884,11 +3840,11 @@
- N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
- /* 0xE0 - 0xE7 */
- X3(I(SrcImmByte, em_loop)),
-- I(SrcImmByte | NearBranch, em_jcxz),
-+ I(SrcImmByte, em_jcxz),
- I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
- I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
- /* 0xE8 - 0xEF */
-- I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps),
-+ I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
- I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
- I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
- I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
-@@ -4368,12 +4324,8 @@
- if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
- return EMULATION_FAILED;
-
-- if (mode == X86EMUL_MODE_PROT64) {
-- if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
-- ctxt->op_bytes = 8;
-- else if (ctxt->d & NearBranch)
-- ctxt->op_bytes = 8;
-- }
-+ if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
-+ ctxt->op_bytes = 8;
-
- if (ctxt->d & Op3264) {
- if (mode == X86EMUL_MODE_PROT64)
-diff -Nur linux-3.12.38/arch/x86/kvm/mmu.c linux-rpi/arch/x86/kvm/mmu.c
---- linux-3.12.38/arch/x86/kvm/mmu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/mmu.c 2015-03-10 17:26:50.062216695 +0100
-@@ -4429,7 +4429,7 @@
- * zap all shadow pages.
- */
- if (unlikely(kvm_current_mmio_generation(kvm) == 0)) {
-- printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
-+ printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
- kvm_mmu_invalidate_zap_all_pages(kvm);
- }
- }
-diff -Nur linux-3.12.38/arch/x86/kvm/vmx.c linux-rpi/arch/x86/kvm/vmx.c
---- linux-3.12.38/arch/x86/kvm/vmx.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/vmx.c 2015-03-10 17:26:50.062216695 +0100
-@@ -439,7 +439,6 @@
- #endif
- int gs_ldt_reload_needed;
- int fs_reload_needed;
-- unsigned long vmcs_host_cr4; /* May not match real cr4 */
- } host_state;
- struct {
- int vm86_active;
-@@ -2520,8 +2519,6 @@
- break;
- case MSR_IA32_CR_PAT:
- if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
-- if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
-- return 1;
- vmcs_write64(GUEST_IA32_PAT, data);
- vcpu->arch.pat = data;
- break;
-@@ -4130,16 +4127,11 @@
- u32 low32, high32;
- unsigned long tmpl;
- struct desc_ptr dt;
-- unsigned long cr4;
-
- vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
-+ vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
- vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
-
-- /* Save the most likely value for this task's CR4 in the VMCS. */
-- cr4 = read_cr4();
-- vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
-- vmx->host_state.vmcs_host_cr4 = cr4;
--
- vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
- #ifdef CONFIG_X86_64
- /*
-@@ -7132,7 +7124,7 @@
- static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
- {
- struct vcpu_vmx *vmx = to_vmx(vcpu);
-- unsigned long debugctlmsr, cr4;
-+ unsigned long debugctlmsr;
-
- /* Record the guest's net vcpu time for enforced NMI injections. */
- if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
-@@ -7153,12 +7145,6 @@
- if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
- vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
-
-- cr4 = read_cr4();
-- if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
-- vmcs_writel(HOST_CR4, cr4);
-- vmx->host_state.vmcs_host_cr4 = cr4;
-- }
--
- /* When single-stepping over STI and MOV SS, we must clear the
- * corresponding interruptibility bits in the guest state. Otherwise
- * vmentry fails as it then expects bit 14 (BS) in pending debug
-diff -Nur linux-3.12.38/arch/x86/kvm/x86.c linux-rpi/arch/x86/kvm/x86.c
---- linux-3.12.38/arch/x86/kvm/x86.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/x86.c 2015-03-10 17:26:50.066216695 +0100
-@@ -1707,7 +1707,7 @@
- return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
- }
-
--bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
-+static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
- {
- int i;
-
-@@ -1733,13 +1733,12 @@
- /* variable MTRRs */
- return valid_mtrr_type(data & 0xff);
- }
--EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
-
- static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
- {
- u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
-
-- if (!kvm_mtrr_valid(vcpu, msr, data))
-+ if (!mtrr_valid(vcpu, msr, data))
- return 1;
-
- if (msr == MSR_MTRRdefType) {
-diff -Nur linux-3.12.38/arch/x86/kvm/x86.h linux-rpi/arch/x86/kvm/x86.h
---- linux-3.12.38/arch/x86/kvm/x86.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/kvm/x86.h 2015-03-10 17:26:50.066216695 +0100
-@@ -132,8 +132,6 @@
- gva_t addr, void *val, unsigned int bytes,
- struct x86_exception *exception);
-
--bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
--
- extern u64 host_xcr0;
-
- extern unsigned int min_timer_period_us;
-diff -Nur linux-3.12.38/arch/x86/pci/common.c linux-rpi/arch/x86/pci/common.c
---- linux-3.12.38/arch/x86/pci/common.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/pci/common.c 2015-03-10 17:26:50.070216695 +0100
-@@ -448,22 +448,6 @@
- DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
- },
- },
-- {
-- .callback = set_scan_all,
-- .ident = "Stratus/NEC ftServer",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R32"),
-- },
-- },
-- {
-- .callback = set_scan_all,
-- .ident = "Stratus/NEC ftServer",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R31"),
-- },
-- },
- {}
- };
-
-diff -Nur linux-3.12.38/arch/x86/platform/uv/tlb_uv.c linux-rpi/arch/x86/platform/uv/tlb_uv.c
---- linux-3.12.38/arch/x86/platform/uv/tlb_uv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/platform/uv/tlb_uv.c 2015-03-10 17:26:50.070216695 +0100
-@@ -1367,10 +1367,6 @@
- }
- if (cpu < num_possible_cpus() && cpu_online(cpu)) {
- bcp = &per_cpu(bau_control, cpu);
-- if (bcp->nobau) {
-- seq_printf(file, "cpu %d bau disabled\n", cpu);
-- return 0;
-- }
- stat = bcp->statp;
- /* source side statistics */
- seq_printf(file,
-diff -Nur linux-3.12.38/arch/x86/um/sys_call_table_32.c linux-rpi/arch/x86/um/sys_call_table_32.c
---- linux-3.12.38/arch/x86/um/sys_call_table_32.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/um/sys_call_table_32.c 2015-03-10 17:26:50.074216695 +0100
-@@ -34,7 +34,7 @@
-
- extern asmlinkage void sys_ni_syscall(void);
-
--const sys_call_ptr_t sys_call_table[] ____cacheline_aligned = {
-+const sys_call_ptr_t sys_call_table[] __cacheline_aligned = {
- /*
- * Smells like a compiler bug -- it doesn't work
- * when the & below is removed.
-diff -Nur linux-3.12.38/arch/x86/um/sys_call_table_64.c linux-rpi/arch/x86/um/sys_call_table_64.c
---- linux-3.12.38/arch/x86/um/sys_call_table_64.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/um/sys_call_table_64.c 2015-03-10 17:26:50.074216695 +0100
-@@ -46,7 +46,7 @@
-
- extern void sys_ni_syscall(void);
-
--const sys_call_ptr_t sys_call_table[] ____cacheline_aligned = {
-+const sys_call_ptr_t sys_call_table[] __cacheline_aligned = {
- /*
- * Smells like a compiler bug -- it doesn't work
- * when the & below is removed.
-diff -Nur linux-3.12.38/arch/x86/vdso/vma.c linux-rpi/arch/x86/vdso/vma.c
---- linux-3.12.38/arch/x86/vdso/vma.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/arch/x86/vdso/vma.c 2015-03-10 17:26:50.074216695 +0100
-@@ -117,45 +117,30 @@
-
- struct linux_binprm;
-
--/*
-- * Put the vdso above the (randomized) stack with another randomized
-- * offset. This way there is no hole in the middle of address space.
-- * To save memory make sure it is still in the same PTE as the stack
-- * top. This doesn't give that many random bits.
-- *
-- * Note that this algorithm is imperfect: the distribution of the vdso
-- * start address within a PMD is biased toward the end.
-- *
-- * Only used for the 64-bit and x32 vdsos.
-- */
-+/* Put the vdso above the (randomized) stack with another randomized offset.
-+ This way there is no hole in the middle of address space.
-+ To save memory make sure it is still in the same PTE as the stack top.
-+ This doesn't give that many random bits */
- static unsigned long vdso_addr(unsigned long start, unsigned len)
- {
- unsigned long addr, end;
- unsigned offset;
--
-- /*
-- * Round up the start address. It can start out unaligned as a result
-- * of stack start randomization.
-- */
-- start = PAGE_ALIGN(start);
--
-- /* Round the lowest possible end address up to a PMD boundary. */
-- end = (start + len + PMD_SIZE - 1) & PMD_MASK;
-+ end = (start + PMD_SIZE - 1) & PMD_MASK;
- if (end >= TASK_SIZE_MAX)
- end = TASK_SIZE_MAX;
- end -= len;
--
-- if (end > start) {
-- offset = get_random_int() % (((end - start) >> PAGE_SHIFT) + 1);
-- addr = start + (offset << PAGE_SHIFT);
-- } else {
-- addr = start;
-- }
-+ /* This loses some more bits than a modulo, but is cheaper */
-+ offset = get_random_int() & (PTRS_PER_PTE - 1);
-+ addr = start + (offset << PAGE_SHIFT);
-+ if (addr >= end)
-+ addr = end;
-
- /*
-- * Forcibly align the final address in case we have a hardware
-- * issue that requires alignment for performance reasons.
-+ * page-align it here so that get_unmapped_area doesn't
-+ * align it wrongfully again to the next page. addr can come in 4K
-+ * unaligned here as a result of stack start randomization.
- */
-+ addr = PAGE_ALIGN(addr);
- addr = align_vdso_addr(addr);
-
- return addr;
-diff -Nur linux-3.12.38/block/genhd.c linux-rpi/block/genhd.c
---- linux-3.12.38/block/genhd.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/block/genhd.c 2015-03-10 17:26:50.086216695 +0100
-@@ -1070,16 +1070,9 @@
- struct disk_part_tbl *old_ptbl = disk->part_tbl;
- struct disk_part_tbl *new_ptbl;
- int len = old_ptbl ? old_ptbl->len : 0;
-- int i, target;
-+ int target = partno + 1;
- size_t size;
--
-- /*
-- * check for int overflow, since we can get here from blkpg_ioctl()
-- * with a user passed 'partno'.
-- */
-- target = partno + 1;
-- if (target < 0)
-- return -EINVAL;
-+ int i;
-
- /* disk_max_parts() is zero during initialization, ignore if so */
- if (disk_max_parts(disk) && target > disk_max_parts(disk))
-diff -Nur linux-3.12.38/crypto/842.c linux-rpi/crypto/842.c
---- linux-3.12.38/crypto/842.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/842.c 2015-03-10 17:26:50.086216695 +0100
-@@ -180,4 +180,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("842 Compression Algorithm");
--MODULE_ALIAS_CRYPTO("842");
-diff -Nur linux-3.12.38/crypto/aes_generic.c linux-rpi/crypto/aes_generic.c
---- linux-3.12.38/crypto/aes_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/aes_generic.c 2015-03-10 17:26:50.086216695 +0100
-@@ -1474,5 +1474,4 @@
-
- MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
- MODULE_LICENSE("Dual BSD/GPL");
--MODULE_ALIAS_CRYPTO("aes");
--MODULE_ALIAS_CRYPTO("aes-generic");
-+MODULE_ALIAS("aes");
-diff -Nur linux-3.12.38/crypto/algapi.c linux-rpi/crypto/algapi.c
---- linux-3.12.38/crypto/algapi.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/algapi.c 2015-03-10 17:26:50.086216695 +0100
-@@ -495,8 +495,8 @@
-
- struct crypto_template *crypto_lookup_template(const char *name)
- {
-- return try_then_request_module(__crypto_lookup_template(name),
-- "crypto-%s", name);
-+ return try_then_request_module(__crypto_lookup_template(name), "%s",
-+ name);
- }
- EXPORT_SYMBOL_GPL(crypto_lookup_template);
-
-diff -Nur linux-3.12.38/crypto/ansi_cprng.c linux-rpi/crypto/ansi_cprng.c
---- linux-3.12.38/crypto/ansi_cprng.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/ansi_cprng.c 2015-03-10 17:26:50.086216695 +0100
-@@ -476,5 +476,4 @@
- MODULE_PARM_DESC(dbg, "Boolean to enable debugging (0/1 == off/on)");
- module_init(prng_mod_init);
- module_exit(prng_mod_fini);
--MODULE_ALIAS_CRYPTO("stdrng");
--MODULE_ALIAS_CRYPTO("ansi_cprng");
-+MODULE_ALIAS("stdrng");
-diff -Nur linux-3.12.38/crypto/anubis.c linux-rpi/crypto/anubis.c
---- linux-3.12.38/crypto/anubis.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/anubis.c 2015-03-10 17:26:50.086216695 +0100
-@@ -704,4 +704,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Anubis Cryptographic Algorithm");
--MODULE_ALIAS_CRYPTO("anubis");
-diff -Nur linux-3.12.38/crypto/api.c linux-rpi/crypto/api.c
---- linux-3.12.38/crypto/api.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/api.c 2015-03-10 17:26:50.086216695 +0100
-@@ -216,11 +216,11 @@
-
- alg = crypto_alg_lookup(name, type, mask);
- if (!alg) {
-- request_module("crypto-%s", name);
-+ request_module("%s", name);
-
- if (!((type ^ CRYPTO_ALG_NEED_FALLBACK) & mask &
- CRYPTO_ALG_NEED_FALLBACK))
-- request_module("crypto-%s-all", name);
-+ request_module("%s-all", name);
-
- alg = crypto_alg_lookup(name, type, mask);
- }
-diff -Nur linux-3.12.38/crypto/arc4.c linux-rpi/crypto/arc4.c
---- linux-3.12.38/crypto/arc4.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/arc4.c 2015-03-10 17:26:50.086216695 +0100
-@@ -166,4 +166,3 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("ARC4 Cipher Algorithm");
- MODULE_AUTHOR("Jon Oberheide <jon@oberheide.org>");
--MODULE_ALIAS_CRYPTO("arc4");
-diff -Nur linux-3.12.38/crypto/authenc.c linux-rpi/crypto/authenc.c
---- linux-3.12.38/crypto/authenc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/authenc.c 2015-03-10 17:26:50.086216695 +0100
-@@ -709,4 +709,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Simple AEAD wrapper for IPsec");
--MODULE_ALIAS_CRYPTO("authenc");
-diff -Nur linux-3.12.38/crypto/authencesn.c linux-rpi/crypto/authencesn.c
---- linux-3.12.38/crypto/authencesn.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/authencesn.c 2015-03-10 17:26:50.086216695 +0100
-@@ -832,4 +832,3 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Steffen Klassert <steffen.klassert@secunet.com>");
- MODULE_DESCRIPTION("AEAD wrapper for IPsec with extended sequence numbers");
--MODULE_ALIAS_CRYPTO("authencesn");
-diff -Nur linux-3.12.38/crypto/blowfish_generic.c linux-rpi/crypto/blowfish_generic.c
---- linux-3.12.38/crypto/blowfish_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/blowfish_generic.c 2015-03-10 17:26:50.086216695 +0100
-@@ -138,5 +138,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Blowfish Cipher Algorithm");
--MODULE_ALIAS_CRYPTO("blowfish");
--MODULE_ALIAS_CRYPTO("blowfish-generic");
-+MODULE_ALIAS("blowfish");
-diff -Nur linux-3.12.38/crypto/camellia_generic.c linux-rpi/crypto/camellia_generic.c
---- linux-3.12.38/crypto/camellia_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/camellia_generic.c 2015-03-10 17:26:50.086216695 +0100
-@@ -1098,5 +1098,4 @@
-
- MODULE_DESCRIPTION("Camellia Cipher Algorithm");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("camellia");
--MODULE_ALIAS_CRYPTO("camellia-generic");
-+MODULE_ALIAS("camellia");
-diff -Nur linux-3.12.38/crypto/cast5_generic.c linux-rpi/crypto/cast5_generic.c
---- linux-3.12.38/crypto/cast5_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/cast5_generic.c 2015-03-10 17:26:50.086216695 +0100
-@@ -549,5 +549,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Cast5 Cipher Algorithm");
--MODULE_ALIAS_CRYPTO("cast5");
--MODULE_ALIAS_CRYPTO("cast5-generic");
-+MODULE_ALIAS("cast5");
-diff -Nur linux-3.12.38/crypto/cast6_generic.c linux-rpi/crypto/cast6_generic.c
---- linux-3.12.38/crypto/cast6_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/cast6_generic.c 2015-03-10 17:26:50.086216695 +0100
-@@ -291,5 +291,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Cast6 Cipher Algorithm");
--MODULE_ALIAS_CRYPTO("cast6");
--MODULE_ALIAS_CRYPTO("cast6-generic");
-+MODULE_ALIAS("cast6");
-diff -Nur linux-3.12.38/crypto/cbc.c linux-rpi/crypto/cbc.c
---- linux-3.12.38/crypto/cbc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/cbc.c 2015-03-10 17:26:50.086216695 +0100
-@@ -289,4 +289,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("CBC block cipher algorithm");
--MODULE_ALIAS_CRYPTO("cbc");
-diff -Nur linux-3.12.38/crypto/ccm.c linux-rpi/crypto/ccm.c
---- linux-3.12.38/crypto/ccm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/ccm.c 2015-03-10 17:26:50.090216695 +0100
-@@ -879,6 +879,5 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Counter with CBC MAC");
--MODULE_ALIAS_CRYPTO("ccm_base");
--MODULE_ALIAS_CRYPTO("rfc4309");
--MODULE_ALIAS_CRYPTO("ccm");
-+MODULE_ALIAS("ccm_base");
-+MODULE_ALIAS("rfc4309");
-diff -Nur linux-3.12.38/crypto/chainiv.c linux-rpi/crypto/chainiv.c
---- linux-3.12.38/crypto/chainiv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/chainiv.c 2015-03-10 17:26:50.090216695 +0100
-@@ -359,4 +359,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Chain IV Generator");
--MODULE_ALIAS_CRYPTO("chainiv");
-diff -Nur linux-3.12.38/crypto/cmac.c linux-rpi/crypto/cmac.c
---- linux-3.12.38/crypto/cmac.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/cmac.c 2015-03-10 17:26:50.090216695 +0100
-@@ -313,4 +313,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("CMAC keyed hash algorithm");
--MODULE_ALIAS_CRYPTO("cmac");
-diff -Nur linux-3.12.38/crypto/crc32.c linux-rpi/crypto/crc32.c
---- linux-3.12.38/crypto/crc32.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/crc32.c 2015-03-10 17:26:50.090216695 +0100
-@@ -156,4 +156,3 @@
- MODULE_AUTHOR("Alexander Boyko <alexander_boyko@xyratex.com>");
- MODULE_DESCRIPTION("CRC32 calculations wrapper for lib/crc32");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("crc32");
-diff -Nur linux-3.12.38/crypto/crc32c.c linux-rpi/crypto/crc32c.c
---- linux-3.12.38/crypto/crc32c.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/crc32c.c 2015-03-10 17:26:50.090216695 +0100
-@@ -170,4 +170,3 @@
- MODULE_AUTHOR("Clay Haapala <chaapala@cisco.com>");
- MODULE_DESCRIPTION("CRC32c (Castagnoli) calculations wrapper for lib/crc32c");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("crc32c");
-diff -Nur linux-3.12.38/crypto/crct10dif_generic.c linux-rpi/crypto/crct10dif_generic.c
---- linux-3.12.38/crypto/crct10dif_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/crct10dif_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -124,5 +124,4 @@
- MODULE_AUTHOR("Tim Chen <tim.c.chen@linux.intel.com>");
- MODULE_DESCRIPTION("T10 DIF CRC calculation.");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("crct10dif");
--MODULE_ALIAS_CRYPTO("crct10dif-generic");
-+MODULE_ALIAS("crct10dif");
-diff -Nur linux-3.12.38/crypto/cryptd.c linux-rpi/crypto/cryptd.c
---- linux-3.12.38/crypto/cryptd.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/cryptd.c 2015-03-10 17:26:50.090216695 +0100
-@@ -955,4 +955,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Software async crypto daemon");
--MODULE_ALIAS_CRYPTO("cryptd");
-diff -Nur linux-3.12.38/crypto/crypto_null.c linux-rpi/crypto/crypto_null.c
---- linux-3.12.38/crypto/crypto_null.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/crypto_null.c 2015-03-10 17:26:50.090216695 +0100
-@@ -149,9 +149,9 @@
- .coa_decompress = null_compress } }
- } };
-
--MODULE_ALIAS_CRYPTO("compress_null");
--MODULE_ALIAS_CRYPTO("digest_null");
--MODULE_ALIAS_CRYPTO("cipher_null");
-+MODULE_ALIAS("compress_null");
-+MODULE_ALIAS("digest_null");
-+MODULE_ALIAS("cipher_null");
-
- static int __init crypto_null_mod_init(void)
- {
-diff -Nur linux-3.12.38/crypto/ctr.c linux-rpi/crypto/ctr.c
---- linux-3.12.38/crypto/ctr.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/ctr.c 2015-03-10 17:26:50.090216695 +0100
-@@ -466,5 +466,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("CTR Counter block mode");
--MODULE_ALIAS_CRYPTO("rfc3686");
--MODULE_ALIAS_CRYPTO("ctr");
-+MODULE_ALIAS("rfc3686");
-diff -Nur linux-3.12.38/crypto/cts.c linux-rpi/crypto/cts.c
---- linux-3.12.38/crypto/cts.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/cts.c 2015-03-10 17:26:50.090216695 +0100
-@@ -350,4 +350,3 @@
-
- MODULE_LICENSE("Dual BSD/GPL");
- MODULE_DESCRIPTION("CTS-CBC CipherText Stealing for CBC");
--MODULE_ALIAS_CRYPTO("cts");
-diff -Nur linux-3.12.38/crypto/deflate.c linux-rpi/crypto/deflate.c
---- linux-3.12.38/crypto/deflate.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/deflate.c 2015-03-10 17:26:50.090216695 +0100
-@@ -222,4 +222,4 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Deflate Compression Algorithm for IPCOMP");
- MODULE_AUTHOR("James Morris <jmorris@intercode.com.au>");
--MODULE_ALIAS_CRYPTO("deflate");
-+
-diff -Nur linux-3.12.38/crypto/des_generic.c linux-rpi/crypto/des_generic.c
---- linux-3.12.38/crypto/des_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/des_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -971,6 +971,8 @@
- .cia_decrypt = des3_ede_decrypt } }
- } };
-
-+MODULE_ALIAS("des3_ede");
-+
- static int __init des_generic_mod_init(void)
- {
- return crypto_register_algs(des_algs, ARRAY_SIZE(des_algs));
-@@ -987,7 +989,4 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("DES & Triple DES EDE Cipher Algorithms");
- MODULE_AUTHOR("Dag Arne Osvik <da@osvik.no>");
--MODULE_ALIAS_CRYPTO("des");
--MODULE_ALIAS_CRYPTO("des-generic");
--MODULE_ALIAS_CRYPTO("des3_ede");
--MODULE_ALIAS_CRYPTO("des3_ede-generic");
-+MODULE_ALIAS("des");
-diff -Nur linux-3.12.38/crypto/ecb.c linux-rpi/crypto/ecb.c
---- linux-3.12.38/crypto/ecb.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/ecb.c 2015-03-10 17:26:50.090216695 +0100
-@@ -185,4 +185,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("ECB block cipher algorithm");
--MODULE_ALIAS_CRYPTO("ecb");
-diff -Nur linux-3.12.38/crypto/eseqiv.c linux-rpi/crypto/eseqiv.c
---- linux-3.12.38/crypto/eseqiv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/eseqiv.c 2015-03-10 17:26:50.090216695 +0100
-@@ -267,4 +267,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Encrypted Sequence Number IV Generator");
--MODULE_ALIAS_CRYPTO("eseqiv");
-diff -Nur linux-3.12.38/crypto/fcrypt.c linux-rpi/crypto/fcrypt.c
---- linux-3.12.38/crypto/fcrypt.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/fcrypt.c 2015-03-10 17:26:50.090216695 +0100
-@@ -420,4 +420,3 @@
- MODULE_LICENSE("Dual BSD/GPL");
- MODULE_DESCRIPTION("FCrypt Cipher Algorithm");
- MODULE_AUTHOR("David Howells <dhowells@redhat.com>");
--MODULE_ALIAS_CRYPTO("fcrypt");
-diff -Nur linux-3.12.38/crypto/gcm.c linux-rpi/crypto/gcm.c
---- linux-3.12.38/crypto/gcm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/gcm.c 2015-03-10 17:26:50.090216695 +0100
-@@ -1441,7 +1441,6 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Galois/Counter Mode");
- MODULE_AUTHOR("Mikko Herranen <mh1@iki.fi>");
--MODULE_ALIAS_CRYPTO("gcm_base");
--MODULE_ALIAS_CRYPTO("rfc4106");
--MODULE_ALIAS_CRYPTO("rfc4543");
--MODULE_ALIAS_CRYPTO("gcm");
-+MODULE_ALIAS("gcm_base");
-+MODULE_ALIAS("rfc4106");
-+MODULE_ALIAS("rfc4543");
-diff -Nur linux-3.12.38/crypto/ghash-generic.c linux-rpi/crypto/ghash-generic.c
---- linux-3.12.38/crypto/ghash-generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/ghash-generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -172,5 +172,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("GHASH Message Digest Algorithm");
--MODULE_ALIAS_CRYPTO("ghash");
--MODULE_ALIAS_CRYPTO("ghash-generic");
-+MODULE_ALIAS("ghash");
-diff -Nur linux-3.12.38/crypto/hmac.c linux-rpi/crypto/hmac.c
---- linux-3.12.38/crypto/hmac.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/hmac.c 2015-03-10 17:26:50.090216695 +0100
-@@ -271,4 +271,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("HMAC hash algorithm");
--MODULE_ALIAS_CRYPTO("hmac");
-diff -Nur linux-3.12.38/crypto/khazad.c linux-rpi/crypto/khazad.c
---- linux-3.12.38/crypto/khazad.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/khazad.c 2015-03-10 17:26:50.090216695 +0100
-@@ -880,4 +880,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Khazad Cryptographic Algorithm");
--MODULE_ALIAS_CRYPTO("khazad");
-diff -Nur linux-3.12.38/crypto/krng.c linux-rpi/crypto/krng.c
---- linux-3.12.38/crypto/krng.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/krng.c 2015-03-10 17:26:50.090216695 +0100
-@@ -62,5 +62,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Kernel Random Number Generator");
--MODULE_ALIAS_CRYPTO("stdrng");
--MODULE_ALIAS_CRYPTO("krng");
-+MODULE_ALIAS("stdrng");
-diff -Nur linux-3.12.38/crypto/lrw.c linux-rpi/crypto/lrw.c
---- linux-3.12.38/crypto/lrw.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/lrw.c 2015-03-10 17:26:50.090216695 +0100
-@@ -400,4 +400,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("LRW block cipher mode");
--MODULE_ALIAS_CRYPTO("lrw");
-diff -Nur linux-3.12.38/crypto/lz4.c linux-rpi/crypto/lz4.c
---- linux-3.12.38/crypto/lz4.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/lz4.c 2015-03-10 17:26:50.090216695 +0100
-@@ -104,4 +104,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("LZ4 Compression Algorithm");
--MODULE_ALIAS_CRYPTO("lz4");
-diff -Nur linux-3.12.38/crypto/lz4hc.c linux-rpi/crypto/lz4hc.c
---- linux-3.12.38/crypto/lz4hc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/lz4hc.c 2015-03-10 17:26:50.090216695 +0100
-@@ -104,4 +104,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("LZ4HC Compression Algorithm");
--MODULE_ALIAS_CRYPTO("lz4hc");
-diff -Nur linux-3.12.38/crypto/lzo.c linux-rpi/crypto/lzo.c
---- linux-3.12.38/crypto/lzo.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/lzo.c 2015-03-10 17:26:50.090216695 +0100
-@@ -103,4 +103,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("LZO Compression Algorithm");
--MODULE_ALIAS_CRYPTO("lzo");
-diff -Nur linux-3.12.38/crypto/md4.c linux-rpi/crypto/md4.c
---- linux-3.12.38/crypto/md4.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/md4.c 2015-03-10 17:26:50.090216695 +0100
-@@ -255,4 +255,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("MD4 Message Digest Algorithm");
--MODULE_ALIAS_CRYPTO("md4");
-+
-diff -Nur linux-3.12.38/crypto/md5.c linux-rpi/crypto/md5.c
---- linux-3.12.38/crypto/md5.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/md5.c 2015-03-10 17:26:50.090216695 +0100
-@@ -168,4 +168,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("MD5 Message Digest Algorithm");
--MODULE_ALIAS_CRYPTO("md5");
-diff -Nur linux-3.12.38/crypto/michael_mic.c linux-rpi/crypto/michael_mic.c
---- linux-3.12.38/crypto/michael_mic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/michael_mic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -184,4 +184,3 @@
- MODULE_LICENSE("GPL v2");
- MODULE_DESCRIPTION("Michael MIC");
- MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
--MODULE_ALIAS_CRYPTO("michael_mic");
-diff -Nur linux-3.12.38/crypto/pcbc.c linux-rpi/crypto/pcbc.c
---- linux-3.12.38/crypto/pcbc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/pcbc.c 2015-03-10 17:26:50.090216695 +0100
-@@ -295,4 +295,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("PCBC block cipher algorithm");
--MODULE_ALIAS_CRYPTO("pcbc");
-diff -Nur linux-3.12.38/crypto/pcrypt.c linux-rpi/crypto/pcrypt.c
---- linux-3.12.38/crypto/pcrypt.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/pcrypt.c 2015-03-10 17:26:50.090216695 +0100
-@@ -565,4 +565,3 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Steffen Klassert <steffen.klassert@secunet.com>");
- MODULE_DESCRIPTION("Parallel crypto wrapper");
--MODULE_ALIAS_CRYPTO("pcrypt");
-diff -Nur linux-3.12.38/crypto/rmd128.c linux-rpi/crypto/rmd128.c
---- linux-3.12.38/crypto/rmd128.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/rmd128.c 2015-03-10 17:26:50.090216695 +0100
-@@ -327,4 +327,3 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Adrian-Ken Rueegsegger <ken@codelabs.ch>");
- MODULE_DESCRIPTION("RIPEMD-128 Message Digest");
--MODULE_ALIAS_CRYPTO("rmd128");
-diff -Nur linux-3.12.38/crypto/rmd160.c linux-rpi/crypto/rmd160.c
---- linux-3.12.38/crypto/rmd160.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/rmd160.c 2015-03-10 17:26:50.090216695 +0100
-@@ -371,4 +371,3 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Adrian-Ken Rueegsegger <ken@codelabs.ch>");
- MODULE_DESCRIPTION("RIPEMD-160 Message Digest");
--MODULE_ALIAS_CRYPTO("rmd160");
-diff -Nur linux-3.12.38/crypto/rmd256.c linux-rpi/crypto/rmd256.c
---- linux-3.12.38/crypto/rmd256.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/rmd256.c 2015-03-10 17:26:50.090216695 +0100
-@@ -346,4 +346,3 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Adrian-Ken Rueegsegger <ken@codelabs.ch>");
- MODULE_DESCRIPTION("RIPEMD-256 Message Digest");
--MODULE_ALIAS_CRYPTO("rmd256");
-diff -Nur linux-3.12.38/crypto/rmd320.c linux-rpi/crypto/rmd320.c
---- linux-3.12.38/crypto/rmd320.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/rmd320.c 2015-03-10 17:26:50.090216695 +0100
-@@ -395,4 +395,3 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Adrian-Ken Rueegsegger <ken@codelabs.ch>");
- MODULE_DESCRIPTION("RIPEMD-320 Message Digest");
--MODULE_ALIAS_CRYPTO("rmd320");
-diff -Nur linux-3.12.38/crypto/salsa20_generic.c linux-rpi/crypto/salsa20_generic.c
---- linux-3.12.38/crypto/salsa20_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/salsa20_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -248,5 +248,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION ("Salsa20 stream cipher algorithm");
--MODULE_ALIAS_CRYPTO("salsa20");
--MODULE_ALIAS_CRYPTO("salsa20-generic");
-+MODULE_ALIAS("salsa20");
-diff -Nur linux-3.12.38/crypto/seed.c linux-rpi/crypto/seed.c
---- linux-3.12.38/crypto/seed.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/seed.c 2015-03-10 17:26:50.090216695 +0100
-@@ -476,4 +476,3 @@
- MODULE_DESCRIPTION("SEED Cipher Algorithm");
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Hye-Shik Chang <perky@FreeBSD.org>, Kim Hyun <hkim@kisa.or.kr>");
--MODULE_ALIAS_CRYPTO("seed");
-diff -Nur linux-3.12.38/crypto/seqiv.c linux-rpi/crypto/seqiv.c
---- linux-3.12.38/crypto/seqiv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/seqiv.c 2015-03-10 17:26:50.090216695 +0100
-@@ -362,4 +362,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Sequence Number IV Generator");
--MODULE_ALIAS_CRYPTO("seqiv");
-diff -Nur linux-3.12.38/crypto/serpent_generic.c linux-rpi/crypto/serpent_generic.c
---- linux-3.12.38/crypto/serpent_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/serpent_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -665,6 +665,5 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Serpent and tnepres (kerneli compatible serpent reversed) Cipher Algorithm");
- MODULE_AUTHOR("Dag Arne Osvik <osvik@ii.uib.no>");
--MODULE_ALIAS_CRYPTO("tnepres");
--MODULE_ALIAS_CRYPTO("serpent");
--MODULE_ALIAS_CRYPTO("serpent-generic");
-+MODULE_ALIAS("tnepres");
-+MODULE_ALIAS("serpent");
-diff -Nur linux-3.12.38/crypto/sha1_generic.c linux-rpi/crypto/sha1_generic.c
---- linux-3.12.38/crypto/sha1_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/sha1_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -153,5 +153,4 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm");
-
--MODULE_ALIAS_CRYPTO("sha1");
--MODULE_ALIAS_CRYPTO("sha1-generic");
-+MODULE_ALIAS("sha1");
-diff -Nur linux-3.12.38/crypto/sha256_generic.c linux-rpi/crypto/sha256_generic.c
---- linux-3.12.38/crypto/sha256_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/sha256_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -384,7 +384,5 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA-224 and SHA-256 Secure Hash Algorithm");
-
--MODULE_ALIAS_CRYPTO("sha224");
--MODULE_ALIAS_CRYPTO("sha224-generic");
--MODULE_ALIAS_CRYPTO("sha256");
--MODULE_ALIAS_CRYPTO("sha256-generic");
-+MODULE_ALIAS("sha224");
-+MODULE_ALIAS("sha256");
-diff -Nur linux-3.12.38/crypto/sha512_generic.c linux-rpi/crypto/sha512_generic.c
---- linux-3.12.38/crypto/sha512_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/sha512_generic.c 2015-03-10 17:26:50.090216695 +0100
-@@ -287,7 +287,5 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("SHA-512 and SHA-384 Secure Hash Algorithms");
-
--MODULE_ALIAS_CRYPTO("sha384");
--MODULE_ALIAS_CRYPTO("sha384-generic");
--MODULE_ALIAS_CRYPTO("sha512");
--MODULE_ALIAS_CRYPTO("sha512-generic");
-+MODULE_ALIAS("sha384");
-+MODULE_ALIAS("sha512");
-diff -Nur linux-3.12.38/crypto/tea.c linux-rpi/crypto/tea.c
---- linux-3.12.38/crypto/tea.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/tea.c 2015-03-10 17:26:50.090216695 +0100
-@@ -270,9 +270,8 @@
- crypto_unregister_algs(tea_algs, ARRAY_SIZE(tea_algs));
- }
-
--MODULE_ALIAS_CRYPTO("tea");
--MODULE_ALIAS_CRYPTO("xtea");
--MODULE_ALIAS_CRYPTO("xeta");
-+MODULE_ALIAS("xtea");
-+MODULE_ALIAS("xeta");
-
- module_init(tea_mod_init);
- module_exit(tea_mod_fini);
-diff -Nur linux-3.12.38/crypto/tgr192.c linux-rpi/crypto/tgr192.c
---- linux-3.12.38/crypto/tgr192.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/tgr192.c 2015-03-10 17:26:50.094216695 +0100
-@@ -676,9 +676,8 @@
- crypto_unregister_shashes(tgr_algs, ARRAY_SIZE(tgr_algs));
- }
-
--MODULE_ALIAS_CRYPTO("tgr192");
--MODULE_ALIAS_CRYPTO("tgr160");
--MODULE_ALIAS_CRYPTO("tgr128");
-+MODULE_ALIAS("tgr160");
-+MODULE_ALIAS("tgr128");
-
- module_init(tgr192_mod_init);
- module_exit(tgr192_mod_fini);
-diff -Nur linux-3.12.38/crypto/twofish_generic.c linux-rpi/crypto/twofish_generic.c
---- linux-3.12.38/crypto/twofish_generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/twofish_generic.c 2015-03-10 17:26:50.094216695 +0100
-@@ -211,5 +211,4 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION ("Twofish Cipher Algorithm");
--MODULE_ALIAS_CRYPTO("twofish");
--MODULE_ALIAS_CRYPTO("twofish-generic");
-+MODULE_ALIAS("twofish");
-diff -Nur linux-3.12.38/crypto/vmac.c linux-rpi/crypto/vmac.c
---- linux-3.12.38/crypto/vmac.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/vmac.c 2015-03-10 17:26:50.094216695 +0100
-@@ -713,4 +713,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("VMAC hash algorithm");
--MODULE_ALIAS_CRYPTO("vmac");
-diff -Nur linux-3.12.38/crypto/wp512.c linux-rpi/crypto/wp512.c
---- linux-3.12.38/crypto/wp512.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/wp512.c 2015-03-10 17:26:50.098216695 +0100
-@@ -1167,9 +1167,8 @@
- crypto_unregister_shashes(wp_algs, ARRAY_SIZE(wp_algs));
- }
-
--MODULE_ALIAS_CRYPTO("wp512");
--MODULE_ALIAS_CRYPTO("wp384");
--MODULE_ALIAS_CRYPTO("wp256");
-+MODULE_ALIAS("wp384");
-+MODULE_ALIAS("wp256");
-
- module_init(wp512_mod_init);
- module_exit(wp512_mod_fini);
-diff -Nur linux-3.12.38/crypto/xcbc.c linux-rpi/crypto/xcbc.c
---- linux-3.12.38/crypto/xcbc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/xcbc.c 2015-03-10 17:26:50.098216695 +0100
-@@ -286,4 +286,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("XCBC keyed hash algorithm");
--MODULE_ALIAS_CRYPTO("xcbc");
-diff -Nur linux-3.12.38/crypto/xts.c linux-rpi/crypto/xts.c
---- linux-3.12.38/crypto/xts.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/xts.c 2015-03-10 17:26:50.098216695 +0100
-@@ -362,4 +362,3 @@
-
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("XTS block cipher mode");
--MODULE_ALIAS_CRYPTO("xts");
-diff -Nur linux-3.12.38/crypto/zlib.c linux-rpi/crypto/zlib.c
---- linux-3.12.38/crypto/zlib.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/crypto/zlib.c 2015-03-10 17:26:50.098216695 +0100
-@@ -378,4 +378,3 @@
- MODULE_LICENSE("GPL");
- MODULE_DESCRIPTION("Zlib Compression Algorithm");
- MODULE_AUTHOR("Sony Corporation");
--MODULE_ALIAS_CRYPTO("zlib");
-diff -Nur linux-3.12.38/Documentation/kernel-parameters.txt linux-rpi/Documentation/kernel-parameters.txt
---- linux-3.12.38/Documentation/kernel-parameters.txt 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/Documentation/kernel-parameters.txt 2015-03-10 17:26:49.638216698 +0100
-@@ -1119,7 +1119,6 @@
- i8042.notimeout [HW] Ignore timeout condition signalled by controller
- i8042.reset [HW] Reset the controller during init and cleanup
- i8042.unlock [HW] Unlock (ignore) the keylock
-- i8042.kbdreset [HW] Reset device connected to KBD port
-
- i810= [HW,DRM]
-
-diff -Nur linux-3.12.38/Documentation/ramoops.txt linux-rpi/Documentation/ramoops.txt
---- linux-3.12.38/Documentation/ramoops.txt 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/Documentation/ramoops.txt 2015-03-10 17:26:49.646216698 +0100
-@@ -14,19 +14,11 @@
-
- 1. Ramoops concepts
-
--Ramoops uses a predefined memory area to store the dump. The start and size
--and type of the memory area are set using three variables:
-+Ramoops uses a predefined memory area to store the dump. The start and size of
-+the memory area are set using two variables:
- * "mem_address" for the start
- * "mem_size" for the size. The memory size will be rounded down to a
- power of two.
-- * "mem_type" to specifiy if the memory type (default is pgprot_writecombine).
--
--Typically the default value of mem_type=0 should be used as that sets the pstore
--mapping to pgprot_writecombine. Setting mem_type=1 attempts to use
--pgprot_noncached, which only works on some platforms. This is because pstore
--depends on atomic operations. At least on ARM, pgprot_noncached causes the
--memory to be mapped strongly ordered, and atomic operations on strongly ordered
--memory are implementation defined, and won't work on many ARMs such as omaps.
-
- The memory area is divided into "record_size" chunks (also rounded down to
- power of two) and each oops/panic writes a "record_size" chunk of
-@@ -63,7 +55,6 @@
- static struct ramoops_platform_data ramoops_data = {
- .mem_size = <...>,
- .mem_address = <...>,
-- .mem_type = <...>,
- .record_size = <...>,
- .dump_oops = <...>,
- .ecc = <...>,
-diff -Nur linux-3.12.38/Documentation/video4linux/bcm2835-v4l2.txt linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt
---- linux-3.12.38/Documentation/video4linux/bcm2835-v4l2.txt 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt 2015-03-09 10:39:28.418893747 +0100
-@@ -0,0 +1,60 @@
-+
-+BCM2835 (aka Raspberry Pi) V4L2 driver
-+======================================
-+
-+1. Copyright
-+============
-+
-+Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+
-+2. License
-+==========
-+
-+This program is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 2 of the License, or
-+(at your option) any later version.
-+
-+This program is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with this program; if not, write to the Free Software
-+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+
-+3. Quick Start
-+==============
-+
-+You need a version 1.0 or later of v4l2-ctl, available from:
-+ git://git.linuxtv.org/v4l-utils.git
-+
-+$ sudo modprobe bcm2835-v4l2
-+
-+Turn on the overlay:
-+
-+$ v4l2-ctl --overlay=1
-+
-+Turn off the overlay:
-+
-+$ v4l2-ctl --overlay=0
-+
-+Set the capture format for video:
-+
-+$ v4l2-ctl --set-fmt-video=width=1920,height=1088,pixelformat=4
-+
-+(Note: 1088 not 1080).
-+
-+Capture:
-+
-+$ v4l2-ctl --stream-mmap=3 --stream-count=100 --stream-to=somefile.h264
-+
-+Stills capture:
-+
-+$ v4l2-ctl --set-fmt-video=width=2592,height=1944,pixelformat=3
-+$ v4l2-ctl --stream-mmap=3 --stream-count=1 --stream-to=somefile.jpg
-+
-+List of available formats:
-+
-+$ v4l2-ctl --list-formats
-diff -Nur linux-3.12.38/drivers/acpi/osl.c linux-rpi/drivers/acpi/osl.c
---- linux-3.12.38/drivers/acpi/osl.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/acpi/osl.c 2015-03-10 17:26:50.118216695 +0100
-@@ -421,7 +421,7 @@
- static void acpi_os_map_cleanup(struct acpi_ioremap *map)
- {
- if (!map->refcount) {
-- synchronize_rcu_expedited();
-+ synchronize_rcu();
- acpi_unmap(map->phys, map->virt);
- kfree(map);
- }
-@@ -1748,16 +1748,6 @@
- acpi_os_map_generic_address(&acpi_gbl_FADT.xpm1b_event_block);
- acpi_os_map_generic_address(&acpi_gbl_FADT.xgpe0_block);
- acpi_os_map_generic_address(&acpi_gbl_FADT.xgpe1_block);
-- if (acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) {
-- /*
-- * Use acpi_os_map_generic_address to pre-map the reset
-- * register if it's in system memory.
-- */
-- int rv;
--
-- rv = acpi_os_map_generic_address(&acpi_gbl_FADT.reset_register);
-- pr_debug(PREFIX "%s: map reset_reg status %d\n", __func__, rv);
-- }
-
- return AE_OK;
- }
-@@ -1786,8 +1776,6 @@
- acpi_os_unmap_generic_address(&acpi_gbl_FADT.xgpe0_block);
- acpi_os_unmap_generic_address(&acpi_gbl_FADT.xpm1b_event_block);
- acpi_os_unmap_generic_address(&acpi_gbl_FADT.xpm1a_event_block);
-- if (acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER)
-- acpi_os_unmap_generic_address(&acpi_gbl_FADT.reset_register);
-
- destroy_workqueue(kacpid_wq);
- destroy_workqueue(kacpi_notify_wq);
-diff -Nur linux-3.12.38/drivers/ata/libata-sff.c linux-rpi/drivers/ata/libata-sff.c
---- linux-3.12.38/drivers/ata/libata-sff.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/ata/libata-sff.c 2015-03-10 17:26:50.126216695 +0100
-@@ -1333,19 +1333,7 @@
- DPRINTK("ENTER\n");
-
- cancel_delayed_work_sync(&ap->sff_pio_task);
--
-- /*
-- * We wanna reset the HSM state to IDLE. If we do so without
-- * grabbing the port lock, critical sections protected by it which
-- * expect the HSM state to stay stable may get surprised. For
-- * example, we may set IDLE in between the time
-- * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
-- * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
-- */
-- spin_lock_irq(ap->lock);
- ap->hsm_task_state = HSM_ST_IDLE;
-- spin_unlock_irq(ap->lock);
--
- ap->sff_pio_task_link = NULL;
-
- if (ata_msg_ctl(ap))
-diff -Nur linux-3.12.38/drivers/ata/sata_dwc_460ex.c linux-rpi/drivers/ata/sata_dwc_460ex.c
---- linux-3.12.38/drivers/ata/sata_dwc_460ex.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/ata/sata_dwc_460ex.c 2015-03-10 17:26:50.134216695 +0100
-@@ -797,7 +797,7 @@
- if (err) {
- dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
- " %d\n", __func__, err);
-- return err;
-+ goto error_out;
- }
-
- /* Enabe DMA */
-@@ -808,6 +808,11 @@
- sata_dma_regs);
-
- return 0;
-+
-+error_out:
-+ dma_dwc_exit(hsdev);
-+
-+ return err;
- }
-
- static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
-@@ -1657,7 +1662,7 @@
- char *ver = (char *)&versionr;
- u8 *base = NULL;
- int err = 0;
-- int irq;
-+ int irq, rc;
- struct ata_host *host;
- struct ata_port_info pi = sata_dwc_port_info[0];
- const struct ata_port_info *ppi[] = { &pi, NULL };
-@@ -1720,7 +1725,7 @@
- if (irq == NO_IRQ) {
- dev_err(&ofdev->dev, "no SATA DMA irq\n");
- err = -ENODEV;
-- goto error_iomap;
-+ goto error_out;
- }
-
- /* Get physical SATA DMA register base address */
-@@ -1729,16 +1734,14 @@
- dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
- " address\n");
- err = -ENODEV;
-- goto error_iomap;
-+ goto error_out;
- }
-
- /* Save dev for later use in dev_xxx() routines */
- host_pvt.dwc_dev = &ofdev->dev;
-
- /* Initialize AHB DMAC */
-- err = dma_dwc_init(hsdev, irq);
-- if (err)
-- goto error_dma_iomap;
-+ dma_dwc_init(hsdev, irq);
-
- /* Enable SATA Interrupts */
- sata_dwc_enable_interrupts(hsdev);
-@@ -1756,8 +1759,9 @@
- * device discovery process, invoking our port_start() handler &
- * error_handler() to execute a dummy Softreset EH session
- */
-- err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
-- if (err)
-+ rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
-+
-+ if (rc != 0)
- dev_err(&ofdev->dev, "failed to activate host");
-
- dev_set_drvdata(&ofdev->dev, host);
-@@ -1766,8 +1770,7 @@
- error_out:
- /* Free SATA DMA resources */
- dma_dwc_exit(hsdev);
--error_dma_iomap:
-- iounmap((void __iomem *)host_pvt.sata_dma_regs);
-+
- error_iomap:
- iounmap(base);
- error_kmalloc:
-@@ -1788,7 +1791,6 @@
- /* Free SATA DMA resources */
- dma_dwc_exit(hsdev);
-
-- iounmap((void __iomem *)host_pvt.sata_dma_regs);
- iounmap(hsdev->reg_base);
- kfree(hsdev);
- kfree(host);
-diff -Nur linux-3.12.38/drivers/base/bus.c linux-rpi/drivers/base/bus.c
---- linux-3.12.38/drivers/base/bus.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/base/bus.c 2015-03-10 17:26:50.138216695 +0100
-@@ -243,15 +243,13 @@
- const char *buf, size_t count)
- {
- struct device *dev;
-- int err = -EINVAL;
-
- dev = bus_find_device_by_name(bus, NULL, buf);
- if (!dev)
- return -ENODEV;
-- if (bus_rescan_devices_helper(dev, NULL) == 0)
-- err = count;
-- put_device(dev);
-- return err;
-+ if (bus_rescan_devices_helper(dev, NULL) != 0)
-+ return -EINVAL;
-+ return count;
- }
-
- static struct device *next_device(struct klist_iter *i)
-diff -Nur linux-3.12.38/drivers/block/drbd/drbd_req.c linux-rpi/drivers/block/drbd/drbd_req.c
---- linux-3.12.38/drivers/block/drbd/drbd_req.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/block/drbd/drbd_req.c 2015-03-10 17:26:50.150216694 +0100
-@@ -1309,7 +1309,6 @@
- struct request_queue * const b =
- mdev->ldev->backing_bdev->bd_disk->queue;
- if (b->merge_bvec_fn) {
-- bvm->bi_bdev = mdev->ldev->backing_bdev;
- backing_limit = b->merge_bvec_fn(b, bvm, bvec);
- limit = min(limit, backing_limit);
- }
-diff -Nur linux-3.12.38/drivers/block/rbd.c linux-rpi/drivers/block/rbd.c
---- linux-3.12.38/drivers/block/rbd.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/block/rbd.c 2015-03-10 17:26:50.158216694 +0100
-@@ -1945,26 +1945,32 @@
- * If an image has a non-zero parent overlap, get a reference to its
- * parent.
- *
-+ * We must get the reference before checking for the overlap to
-+ * coordinate properly with zeroing the parent overlap in
-+ * rbd_dev_v2_parent_info() when an image gets flattened. We
-+ * drop it again if there is no overlap.
-+ *
- * Returns true if the rbd device has a parent with a non-zero
- * overlap and a reference for it was successfully taken, or
- * false otherwise.
- */
- static bool rbd_dev_parent_get(struct rbd_device *rbd_dev)
- {
-- int counter = 0;
-+ int counter;
-
- if (!rbd_dev->parent_spec)
- return false;
-
-- down_read(&rbd_dev->header_rwsem);
-- if (rbd_dev->parent_overlap)
-- counter = atomic_inc_return_safe(&rbd_dev->parent_ref);
-- up_read(&rbd_dev->header_rwsem);
-+ counter = atomic_inc_return_safe(&rbd_dev->parent_ref);
-+ if (counter > 0 && rbd_dev->parent_overlap)
-+ return true;
-+
-+ /* Image was flattened, but parent is not yet torn down */
-
- if (counter < 0)
- rbd_warn(rbd_dev, "parent reference overflow\n");
-
-- return counter > 0;
-+ return false;
- }
-
- /*
-@@ -2137,6 +2143,7 @@
- rbd_assert(img_request->obj_request_count > 0);
- rbd_assert(which != BAD_WHICH);
- rbd_assert(which < img_request->obj_request_count);
-+ rbd_assert(which >= img_request->next_completion);
-
- spin_lock_irq(&img_request->completion_lock);
- if (which != img_request->next_completion)
-@@ -3887,6 +3894,7 @@
- */
- if (rbd_dev->parent_overlap) {
- rbd_dev->parent_overlap = 0;
-+ smp_mb();
- rbd_dev_parent_put(rbd_dev);
- pr_info("%s: clone image has been flattened\n",
- rbd_dev->disk->disk_name);
-@@ -3930,6 +3938,7 @@
- * treat it specially.
- */
- rbd_dev->parent_overlap = overlap;
-+ smp_mb();
- if (!overlap) {
-
- /* A null parent_spec indicates it's the initial probe */
-@@ -4773,7 +4782,10 @@
- {
- struct rbd_image_header *header;
-
-- rbd_dev_parent_put(rbd_dev);
-+ /* Drop parent reference unless it's already been done (or none) */
-+
-+ if (rbd_dev->parent_overlap)
-+ rbd_dev_parent_put(rbd_dev);
-
- /* Free dynamic fields from the header, then zero it out */
-
-diff -Nur linux-3.12.38/drivers/bluetooth/ath3k.c linux-rpi/drivers/bluetooth/ath3k.c
---- linux-3.12.38/drivers/bluetooth/ath3k.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/bluetooth/ath3k.c 2015-03-10 17:26:50.158216694 +0100
-@@ -168,8 +168,6 @@
- #define USB_REQ_DFU_DNLOAD 1
- #define BULK_SIZE 4096
- #define FW_HDR_SIZE 20
--#define TIMEGAP_USEC_MIN 50
--#define TIMEGAP_USEC_MAX 100
-
- static int ath3k_load_firmware(struct usb_device *udev,
- const struct firmware *firmware)
-@@ -200,9 +198,6 @@
- count -= 20;
-
- while (count) {
-- /* workaround the compatibility issue with xHCI controller*/
-- usleep_range(TIMEGAP_USEC_MIN, TIMEGAP_USEC_MAX);
--
- size = min_t(uint, count, BULK_SIZE);
- pipe = usb_sndbulkpipe(udev, 0x02);
- memcpy(send_buf, firmware->data + sent, size);
-@@ -299,9 +294,6 @@
- count -= size;
-
- while (count) {
-- /* workaround the compatibility issue with xHCI controller*/
-- usleep_range(TIMEGAP_USEC_MIN, TIMEGAP_USEC_MAX);
--
- size = min_t(uint, count, BULK_SIZE);
- pipe = usb_sndbulkpipe(udev, 0x02);
-
-diff -Nur linux-3.12.38/drivers/bus/mvebu-mbus.c linux-rpi/drivers/bus/mvebu-mbus.c
---- linux-3.12.38/drivers/bus/mvebu-mbus.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/bus/mvebu-mbus.c 2015-03-10 17:26:50.162216694 +0100
-@@ -181,25 +181,12 @@
- }
-
- /* Checks whether the given window number is available */
--
--/* On Armada XP, 375 and 38x the MBus window 13 has the remap
-- * capability, like windows 0 to 7. However, the mvebu-mbus driver
-- * isn't currently taking into account this special case, which means
-- * that when window 13 is actually used, the remap registers are left
-- * to 0, making the device using this MBus window unavailable. The
-- * quick fix for stable is to not use window 13. A follow up patch
-- * will correctly handle this window.
--*/
- static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
- const int win)
- {
- void __iomem *addr = mbus->mbuswins_base +
- mbus->soc->win_cfg_offset(win);
- u32 ctrl = readl(addr + WIN_CTRL_OFF);
--
-- if (win == 13)
-- return false;
--
- return !(ctrl & WIN_CTRL_ENABLE);
- }
-
-diff -Nur linux-3.12.38/drivers/char/broadcom/Kconfig linux-rpi/drivers/char/broadcom/Kconfig
---- linux-3.12.38/drivers/char/broadcom/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/Kconfig 2015-03-09 10:39:29.730893739 +0100
-@@ -0,0 +1,22 @@
-+#
-+# Broadcom char driver config
-+#
-+
-+menuconfig BRCM_CHAR_DRIVERS
-+ bool "Broadcom Char Drivers"
-+ help
-+ Broadcom's char drivers
-+
-+config BCM_VC_CMA
-+ bool "Videocore CMA"
-+ depends on CMA && BRCM_CHAR_DRIVERS && BCM2708_VCHIQ
-+ default n
-+ help
-+ Helper for videocore CMA access.
-+
-+config BCM_VC_SM
-+ tristate "VMCS Shared Memory"
-+ default n
-+ help
-+ Support for the VC shared memory on the Broadcom reference
-+ design. Uses the VCHIQ stack.
-diff -Nur linux-3.12.38/drivers/char/broadcom/Makefile linux-rpi/drivers/char/broadcom/Makefile
---- linux-3.12.38/drivers/char/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/Makefile 2015-03-09 10:39:29.730893739 +0100
-@@ -0,0 +1,2 @@
-+obj-$(CONFIG_BCM_VC_CMA) += vc_cma/
-+obj-$(CONFIG_BCM_VC_SM) += vc_sm/
-diff -Nur linux-3.12.38/drivers/char/broadcom/vc_cma/Makefile linux-rpi/drivers/char/broadcom/vc_cma/Makefile
---- linux-3.12.38/drivers/char/broadcom/vc_cma/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/vc_cma/Makefile 2015-03-09 10:39:29.730893739 +0100
-@@ -0,0 +1,14 @@
-+ccflags-y += -Wall -Wstrict-prototypes -Wno-trigraphs
-+ccflags-y += -Werror
-+ccflags-y += -Iinclude/linux/broadcom
-+ccflags-y += -Idrivers/misc/vc04_services
-+ccflags-y += -Idrivers/misc/vc04_services/interface/vchi
-+ccflags-y += -Idrivers/misc/vc04_services/interface/vchiq_arm
-+
-+ccflags-y += -D__KERNEL__
-+ccflags-y += -D__linux__
-+ccflags-y += -Werror
-+
-+obj-$(CONFIG_BCM_VC_CMA) += vc-cma.o
-+
-+vc-cma-objs := vc_cma.o
-diff -Nur linux-3.12.38/drivers/char/broadcom/vc_cma/vc_cma.c linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c
---- linux-3.12.38/drivers/char/broadcom/vc_cma/vc_cma.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c 2015-03-10 17:26:50.166216694 +0100
-@@ -0,0 +1,1143 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/kthread.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dma-contiguous.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+#include <asm/cacheflush.h>
-+
-+#include "vc_cma.h"
-+
-+#include "vchiq_util.h"
-+#include "vchiq_connected.h"
-+//#include "debug_sym.h"
-+//#include "vc_mem.h"
-+
-+#define DRIVER_NAME "vc-cma"
-+
-+#define LOG_DBG(fmt, ...) \
-+ if (vc_cma_debug) \
-+ printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
-+#define LOG_ERR(fmt, ...) \
-+ printk(KERN_ERR fmt "\n", ##__VA_ARGS__)
-+
-+#define VC_CMA_FOURCC VCHIQ_MAKE_FOURCC('C', 'M', 'A', ' ')
-+#define VC_CMA_VERSION 2
-+
-+#define VC_CMA_CHUNK_ORDER 6 /* 256K */
-+#define VC_CMA_CHUNK_SIZE (4096 << VC_CMA_CHUNK_ORDER)
-+#define VC_CMA_MAX_PARAMS_PER_MSG \
-+ ((VCHIQ_MAX_MSG_SIZE - sizeof(unsigned short))/sizeof(unsigned short))
-+#define VC_CMA_RESERVE_COUNT_MAX 16
-+
-+#define PAGES_PER_CHUNK (VC_CMA_CHUNK_SIZE / PAGE_SIZE)
-+
-+#define VCADDR_TO_PHYSADDR(vcaddr) (mm_vc_mem_phys_addr + vcaddr)
-+
-+#define loud_error(...) \
-+ LOG_ERR("===== " __VA_ARGS__)
-+
-+enum {
-+ VC_CMA_MSG_QUIT,
-+ VC_CMA_MSG_OPEN,
-+ VC_CMA_MSG_TICK,
-+ VC_CMA_MSG_ALLOC, /* chunk count */
-+ VC_CMA_MSG_FREE, /* chunk, chunk, ... */
-+ VC_CMA_MSG_ALLOCATED, /* chunk, chunk, ... */
-+ VC_CMA_MSG_REQUEST_ALLOC, /* chunk count */
-+ VC_CMA_MSG_REQUEST_FREE, /* chunk count */
-+ VC_CMA_MSG_RESERVE, /* bytes lo, bytes hi */
-+ VC_CMA_MSG_UPDATE_RESERVE,
-+ VC_CMA_MSG_MAX
-+};
-+
-+struct cma_msg {
-+ unsigned short type;
-+ unsigned short params[VC_CMA_MAX_PARAMS_PER_MSG];
-+};
-+
-+struct vc_cma_reserve_user {
-+ unsigned int pid;
-+ unsigned int reserve;
-+};
-+
-+/* Device (/dev) related variables */
-+static dev_t vc_cma_devnum;
-+static struct class *vc_cma_class;
-+static struct cdev vc_cma_cdev;
-+static int vc_cma_inited;
-+static int vc_cma_debug;
-+
-+/* Proc entry */
-+static struct proc_dir_entry *vc_cma_proc_entry;
-+
-+phys_addr_t vc_cma_base;
-+struct page *vc_cma_base_page;
-+unsigned int vc_cma_size;
-+EXPORT_SYMBOL(vc_cma_size);
-+unsigned int vc_cma_initial;
-+unsigned int vc_cma_chunks;
-+unsigned int vc_cma_chunks_used;
-+unsigned int vc_cma_chunks_reserved;
-+
-+static int in_loud_error;
-+
-+unsigned int vc_cma_reserve_total;
-+unsigned int vc_cma_reserve_count;
-+struct vc_cma_reserve_user vc_cma_reserve_users[VC_CMA_RESERVE_COUNT_MAX];
-+static DEFINE_SEMAPHORE(vc_cma_reserve_mutex);
-+static DEFINE_SEMAPHORE(vc_cma_worker_queue_push_mutex);
-+
-+static u64 vc_cma_dma_mask = DMA_BIT_MASK(32);
-+static struct platform_device vc_cma_device = {
-+ .name = "vc-cma",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &vc_cma_dma_mask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+static VCHIQ_INSTANCE_T cma_instance;
-+static VCHIQ_SERVICE_HANDLE_T cma_service;
-+static VCHIU_QUEUE_T cma_msg_queue;
-+static struct task_struct *cma_worker;
-+
-+static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid);
-+static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply);
-+static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T * header,
-+ VCHIQ_SERVICE_HANDLE_T service,
-+ void *bulk_userdata);
-+static void send_vc_msg(unsigned short type,
-+ unsigned short param1, unsigned short param2);
-+static bool send_worker_msg(VCHIQ_HEADER_T * msg);
-+
-+static int early_vc_cma_mem(char *p)
-+{
-+ unsigned int new_size;
-+ printk(KERN_NOTICE "early_vc_cma_mem(%s)", p);
-+ vc_cma_size = memparse(p, &p);
-+ vc_cma_initial = vc_cma_size;
-+ if (*p == '/')
-+ vc_cma_size = memparse(p + 1, &p);
-+ if (*p == '@')
-+ vc_cma_base = memparse(p + 1, &p);
-+
-+ new_size = (vc_cma_size - ((-vc_cma_base) & (VC_CMA_CHUNK_SIZE - 1)))
-+ & ~(VC_CMA_CHUNK_SIZE - 1);
-+ if (new_size > vc_cma_size)
-+ vc_cma_size = 0;
-+ vc_cma_initial = (vc_cma_initial + VC_CMA_CHUNK_SIZE - 1)
-+ & ~(VC_CMA_CHUNK_SIZE - 1);
-+ if (vc_cma_initial > vc_cma_size)
-+ vc_cma_initial = vc_cma_size;
-+ vc_cma_base = (vc_cma_base + VC_CMA_CHUNK_SIZE - 1)
-+ & ~(VC_CMA_CHUNK_SIZE - 1);
-+
-+ printk(KERN_NOTICE " -> initial %x, size %x, base %x", vc_cma_initial,
-+ vc_cma_size, (unsigned int)vc_cma_base);
-+
-+ return 0;
-+}
-+
-+early_param("vc-cma-mem", early_vc_cma_mem);
-+
-+void vc_cma_early_init(void)
-+{
-+ LOG_DBG("vc_cma_early_init - vc_cma_chunks = %d", vc_cma_chunks);
-+ if (vc_cma_size) {
-+ int rc = platform_device_register(&vc_cma_device);
-+ LOG_DBG("platform_device_register -> %d", rc);
-+ }
-+}
-+
-+void vc_cma_reserve(void)
-+{
-+ /* if vc_cma_size is set, then declare vc CMA area of the same
-+ * size from the end of memory
-+ */
-+ if (vc_cma_size) {
-+ if (dma_declare_contiguous(NULL /*&vc_cma_device.dev*/, vc_cma_size,
-+ vc_cma_base, 0) == 0) {
-+ } else {
-+ LOG_ERR("vc_cma: dma_declare_contiguous(%x,%x) failed",
-+ vc_cma_size, (unsigned int)vc_cma_base);
-+ vc_cma_size = 0;
-+ }
-+ }
-+ vc_cma_chunks = vc_cma_size / VC_CMA_CHUNK_SIZE;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_open
-+*
-+***************************************************************************/
-+
-+static int vc_cma_open(struct inode *inode, struct file *file)
-+{
-+ (void)inode;
-+ (void)file;
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_release
-+*
-+***************************************************************************/
-+
-+static int vc_cma_release(struct inode *inode, struct file *file)
-+{
-+ (void)inode;
-+ (void)file;
-+
-+ vc_cma_set_reserve(0, current->tgid);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_ioctl
-+*
-+***************************************************************************/
-+
-+static long vc_cma_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int rc = 0;
-+
-+ (void)cmd;
-+ (void)arg;
-+
-+ switch (cmd) {
-+ case VC_CMA_IOC_RESERVE:
-+ rc = vc_cma_set_reserve((unsigned int)arg, current->tgid);
-+ if (rc >= 0)
-+ rc = 0;
-+ break;
-+ default:
-+ LOG_ERR("vc-cma: Unknown ioctl %x", cmd);
-+ return -ENOTTY;
-+ }
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for the driver.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_cma_fops = {
-+ .owner = THIS_MODULE,
-+ .open = vc_cma_open,
-+ .release = vc_cma_release,
-+ .unlocked_ioctl = vc_cma_ioctl,
-+};
-+
-+/****************************************************************************
-+*
-+* vc_cma_proc_open
-+*
-+***************************************************************************/
-+
-+static int vc_cma_show_info(struct seq_file *m, void *v)
-+{
-+ int i;
-+
-+ seq_printf(m, "Videocore CMA:\n");
-+ seq_printf(m, " Base : %08x\n", (unsigned int)vc_cma_base);
-+ seq_printf(m, " Length : %08x\n", vc_cma_size);
-+ seq_printf(m, " Initial : %08x\n", vc_cma_initial);
-+ seq_printf(m, " Chunk size : %08x\n", VC_CMA_CHUNK_SIZE);
-+ seq_printf(m, " Chunks : %4d (%d bytes)\n",
-+ (int)vc_cma_chunks,
-+ (int)(vc_cma_chunks * VC_CMA_CHUNK_SIZE));
-+ seq_printf(m, " Used : %4d (%d bytes)\n",
-+ (int)vc_cma_chunks_used,
-+ (int)(vc_cma_chunks_used * VC_CMA_CHUNK_SIZE));
-+ seq_printf(m, " Reserved : %4d (%d bytes)\n",
-+ (unsigned int)vc_cma_chunks_reserved,
-+ (int)(vc_cma_chunks_reserved * VC_CMA_CHUNK_SIZE));
-+
-+ for (i = 0; i < vc_cma_reserve_count; i++) {
-+ struct vc_cma_reserve_user *user = &vc_cma_reserve_users[i];
-+ seq_printf(m, " PID %5d: %d bytes\n", user->pid,
-+ user->reserve);
-+ }
-+
-+ seq_printf(m, "\n");
-+
-+ return 0;
-+}
-+
-+static int vc_cma_proc_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, vc_cma_show_info, NULL);
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_proc_write
-+*
-+***************************************************************************/
-+
-+static int vc_cma_proc_write(struct file *file,
-+ const char __user *buffer,
-+ size_t size, loff_t *ppos)
-+{
-+ int rc = -EFAULT;
-+ char input_str[20];
-+
-+ memset(input_str, 0, sizeof(input_str));
-+
-+ if (size > sizeof(input_str)) {
-+ LOG_ERR("%s: input string length too long", __func__);
-+ goto out;
-+ }
-+
-+ if (copy_from_user(input_str, buffer, size - 1)) {
-+ LOG_ERR("%s: failed to get input string", __func__);
-+ goto out;
-+ }
-+#define ALLOC_STR "alloc"
-+#define FREE_STR "free"
-+#define DEBUG_STR "debug"
-+#define RESERVE_STR "reserve"
-+ if (strncmp(input_str, ALLOC_STR, strlen(ALLOC_STR)) == 0) {
-+ int size;
-+ char *p = input_str + strlen(ALLOC_STR);
-+
-+ while (*p == ' ')
-+ p++;
-+ size = memparse(p, NULL);
-+ LOG_ERR("/proc/vc-cma: alloc %d", size);
-+ if (size)
-+ send_vc_msg(VC_CMA_MSG_REQUEST_FREE,
-+ size / VC_CMA_CHUNK_SIZE, 0);
-+ else
-+ LOG_ERR("invalid size '%s'", p);
-+ rc = size;
-+ } else if (strncmp(input_str, FREE_STR, strlen(FREE_STR)) == 0) {
-+ int size;
-+ char *p = input_str + strlen(FREE_STR);
-+
-+ while (*p == ' ')
-+ p++;
-+ size = memparse(p, NULL);
-+ LOG_ERR("/proc/vc-cma: free %d", size);
-+ if (size)
-+ send_vc_msg(VC_CMA_MSG_REQUEST_ALLOC,
-+ size / VC_CMA_CHUNK_SIZE, 0);
-+ else
-+ LOG_ERR("invalid size '%s'", p);
-+ rc = size;
-+ } else if (strncmp(input_str, DEBUG_STR, strlen(DEBUG_STR)) == 0) {
-+ char *p = input_str + strlen(DEBUG_STR);
-+ while (*p == ' ')
-+ p++;
-+ if ((strcmp(p, "on") == 0) || (strcmp(p, "1") == 0))
-+ vc_cma_debug = 1;
-+ else if ((strcmp(p, "off") == 0) || (strcmp(p, "0") == 0))
-+ vc_cma_debug = 0;
-+ LOG_ERR("/proc/vc-cma: debug %s", vc_cma_debug ? "on" : "off");
-+ rc = size;
-+ } else if (strncmp(input_str, RESERVE_STR, strlen(RESERVE_STR)) == 0) {
-+ int size;
-+ int reserved;
-+ char *p = input_str + strlen(RESERVE_STR);
-+ while (*p == ' ')
-+ p++;
-+ size = memparse(p, NULL);
-+
-+ reserved = vc_cma_set_reserve(size, current->tgid);
-+ rc = (reserved >= 0) ? size : reserved;
-+ }
-+
-+out:
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for /proc interface.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_cma_proc_fops = {
-+ .open = vc_cma_proc_open,
-+ .read = seq_read,
-+ .write = vc_cma_proc_write,
-+ .llseek = seq_lseek,
-+ .release = single_release
-+};
-+
-+static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid)
-+{
-+ struct vc_cma_reserve_user *user = NULL;
-+ int delta = 0;
-+ int i;
-+
-+ if (down_interruptible(&vc_cma_reserve_mutex))
-+ return -ERESTARTSYS;
-+
-+ for (i = 0; i < vc_cma_reserve_count; i++) {
-+ if (pid == vc_cma_reserve_users[i].pid) {
-+ user = &vc_cma_reserve_users[i];
-+ delta = reserve - user->reserve;
-+ if (reserve)
-+ user->reserve = reserve;
-+ else {
-+ /* Remove this entry by copying downwards */
-+ while ((i + 1) < vc_cma_reserve_count) {
-+ user[0].pid = user[1].pid;
-+ user[0].reserve = user[1].reserve;
-+ user++;
-+ i++;
-+ }
-+ vc_cma_reserve_count--;
-+ user = NULL;
-+ }
-+ break;
-+ }
-+ }
-+
-+ if (reserve && !user) {
-+ if (vc_cma_reserve_count == VC_CMA_RESERVE_COUNT_MAX) {
-+ LOG_ERR("vc-cma: Too many reservations - "
-+ "increase CMA_RESERVE_COUNT_MAX");
-+ up(&vc_cma_reserve_mutex);
-+ return -EBUSY;
-+ }
-+ user = &vc_cma_reserve_users[vc_cma_reserve_count];
-+ user->pid = pid;
-+ user->reserve = reserve;
-+ delta = reserve;
-+ vc_cma_reserve_count++;
-+ }
-+
-+ vc_cma_reserve_total += delta;
-+
-+ send_vc_msg(VC_CMA_MSG_RESERVE,
-+ vc_cma_reserve_total & 0xffff, vc_cma_reserve_total >> 16);
-+
-+ send_worker_msg((VCHIQ_HEADER_T *) VC_CMA_MSG_UPDATE_RESERVE);
-+
-+ LOG_DBG("/proc/vc-cma: reserve %d (PID %d) - total %u",
-+ reserve, pid, vc_cma_reserve_total);
-+
-+ up(&vc_cma_reserve_mutex);
-+
-+ return vc_cma_reserve_total;
-+}
-+
-+static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T * header,
-+ VCHIQ_SERVICE_HANDLE_T service,
-+ void *bulk_userdata)
-+{
-+ switch (reason) {
-+ case VCHIQ_MESSAGE_AVAILABLE:
-+ if (!send_worker_msg(header))
-+ return VCHIQ_RETRY;
-+ break;
-+ case VCHIQ_SERVICE_CLOSED:
-+ LOG_DBG("CMA service closed");
-+ break;
-+ default:
-+ LOG_ERR("Unexpected CMA callback reason %d", reason);
-+ break;
-+ }
-+ return VCHIQ_SUCCESS;
-+}
-+
-+static void send_vc_msg(unsigned short type,
-+ unsigned short param1, unsigned short param2)
-+{
-+ unsigned short msg[] = { type, param1, param2 };
-+ VCHIQ_ELEMENT_T elem = { &msg, sizeof(msg) };
-+ VCHIQ_STATUS_T ret;
-+ vchiq_use_service(cma_service);
-+ ret = vchiq_queue_message(cma_service, &elem, 1);
-+ vchiq_release_service(cma_service);
-+ if (ret != VCHIQ_SUCCESS)
-+ LOG_ERR("vchiq_queue_message returned %x", ret);
-+}
-+
-+static bool send_worker_msg(VCHIQ_HEADER_T * msg)
-+{
-+ if (down_interruptible(&vc_cma_worker_queue_push_mutex))
-+ return false;
-+ vchiu_queue_push(&cma_msg_queue, msg);
-+ up(&vc_cma_worker_queue_push_mutex);
-+ return true;
-+}
-+
-+static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply)
-+{
-+ int i;
-+ for (i = 0; i < num_chunks; i++) {
-+ struct page *chunk;
-+ unsigned int chunk_num;
-+ uint8_t *chunk_addr;
-+ size_t chunk_size = PAGES_PER_CHUNK << PAGE_SHIFT;
-+
-+ chunk = dma_alloc_from_contiguous(NULL /*&vc_cma_device.dev*/,
-+ PAGES_PER_CHUNK,
-+ VC_CMA_CHUNK_ORDER);
-+ if (!chunk)
-+ break;
-+
-+ chunk_addr = page_address(chunk);
-+ dmac_flush_range(chunk_addr, chunk_addr + chunk_size);
-+ outer_inv_range(__pa(chunk_addr), __pa(chunk_addr) +
-+ chunk_size);
-+
-+ chunk_num =
-+ (page_to_phys(chunk) - vc_cma_base) / VC_CMA_CHUNK_SIZE;
-+ BUG_ON(((page_to_phys(chunk) - vc_cma_base) %
-+ VC_CMA_CHUNK_SIZE) != 0);
-+ if (chunk_num >= vc_cma_chunks) {
-+ LOG_ERR("%s: ===============================",
-+ __func__);
-+ LOG_ERR("%s: chunk phys %x, vc_cma %x-%x - "
-+ "bad SPARSEMEM configuration?",
-+ __func__, (unsigned int)page_to_phys(chunk),
-+ vc_cma_base, vc_cma_base + vc_cma_size - 1);
-+ LOG_ERR("%s: dev->cma_area = %p\n", __func__,
-+ (void*)0/*vc_cma_device.dev.cma_area*/);
-+ LOG_ERR("%s: ===============================",
-+ __func__);
-+ break;
-+ }
-+ reply->params[i] = chunk_num;
-+ vc_cma_chunks_used++;
-+ }
-+
-+ if (i < num_chunks) {
-+ LOG_ERR("%s: dma_alloc_from_contiguous failed "
-+ "for %x bytes (alloc %d of %d, %d free)",
-+ __func__, VC_CMA_CHUNK_SIZE, i,
-+ num_chunks, vc_cma_chunks - vc_cma_chunks_used);
-+ num_chunks = i;
-+ }
-+
-+ LOG_DBG("CMA allocated %d chunks -> %d used",
-+ num_chunks, vc_cma_chunks_used);
-+ reply->type = VC_CMA_MSG_ALLOCATED;
-+
-+ {
-+ VCHIQ_ELEMENT_T elem = {
-+ reply,
-+ offsetof(struct cma_msg, params[0]) +
-+ num_chunks * sizeof(reply->params[0])
-+ };
-+ VCHIQ_STATUS_T ret;
-+ vchiq_use_service(cma_service);
-+ ret = vchiq_queue_message(cma_service, &elem, 1);
-+ vchiq_release_service(cma_service);
-+ if (ret != VCHIQ_SUCCESS)
-+ LOG_ERR("vchiq_queue_message return " "%x", ret);
-+ }
-+
-+ return num_chunks;
-+}
-+
-+static int cma_worker_proc(void *param)
-+{
-+ static struct cma_msg reply;
-+ (void)param;
-+
-+ while (1) {
-+ VCHIQ_HEADER_T *msg;
-+ static struct cma_msg msg_copy;
-+ struct cma_msg *cma_msg = &msg_copy;
-+ int type, msg_size;
-+
-+ msg = vchiu_queue_pop(&cma_msg_queue);
-+ if ((unsigned int)msg >= VC_CMA_MSG_MAX) {
-+ msg_size = msg->size;
-+ memcpy(&msg_copy, msg->data, msg_size);
-+ type = cma_msg->type;
-+ vchiq_release_message(cma_service, msg);
-+ } else {
-+ msg_size = 0;
-+ type = (int)msg;
-+ if (type == VC_CMA_MSG_QUIT)
-+ break;
-+ else if (type == VC_CMA_MSG_UPDATE_RESERVE) {
-+ msg = NULL;
-+ cma_msg = NULL;
-+ } else {
-+ BUG();
-+ continue;
-+ }
-+ }
-+
-+ switch (type) {
-+ case VC_CMA_MSG_ALLOC:{
-+ int num_chunks, free_chunks;
-+ num_chunks = cma_msg->params[0];
-+ free_chunks =
-+ vc_cma_chunks - vc_cma_chunks_used;
-+ LOG_DBG("CMA_MSG_ALLOC(%d chunks)", num_chunks);
-+ if (num_chunks > VC_CMA_MAX_PARAMS_PER_MSG) {
-+ LOG_ERR
-+ ("CMA_MSG_ALLOC - chunk count (%d) "
-+ "exceeds VC_CMA_MAX_PARAMS_PER_MSG (%d)",
-+ num_chunks,
-+ VC_CMA_MAX_PARAMS_PER_MSG);
-+ num_chunks = VC_CMA_MAX_PARAMS_PER_MSG;
-+ }
-+
-+ if (num_chunks > free_chunks) {
-+ LOG_ERR
-+ ("CMA_MSG_ALLOC - chunk count (%d) "
-+ "exceeds free chunks (%d)",
-+ num_chunks, free_chunks);
-+ num_chunks = free_chunks;
-+ }
-+
-+ vc_cma_alloc_chunks(num_chunks, &reply);
-+ }
-+ break;
-+
-+ case VC_CMA_MSG_FREE:{
-+ int chunk_count =
-+ (msg_size -
-+ offsetof(struct cma_msg,
-+ params)) /
-+ sizeof(cma_msg->params[0]);
-+ int i;
-+ BUG_ON(chunk_count <= 0);
-+
-+ LOG_DBG("CMA_MSG_FREE(%d chunks - %x, ...)",
-+ chunk_count, cma_msg->params[0]);
-+ for (i = 0; i < chunk_count; i++) {
-+ int chunk_num = cma_msg->params[i];
-+ struct page *page = vc_cma_base_page +
-+ chunk_num * PAGES_PER_CHUNK;
-+ if (chunk_num >= vc_cma_chunks) {
-+ LOG_ERR
-+ ("CMA_MSG_FREE - chunk %d of %d"
-+ " (value %x) exceeds maximum "
-+ "(%x)", i, chunk_count,
-+ chunk_num,
-+ vc_cma_chunks - 1);
-+ break;
-+ }
-+
-+ if (!dma_release_from_contiguous
-+ (NULL /*&vc_cma_device.dev*/, page,
-+ PAGES_PER_CHUNK)) {
-+ LOG_ERR
-+ ("CMA_MSG_FREE - failed to "
-+ "release chunk %d (phys %x, "
-+ "page %x)", chunk_num,
-+ page_to_phys(page),
-+ (unsigned int)page);
-+ }
-+ vc_cma_chunks_used--;
-+ }
-+ LOG_DBG("CMA released %d chunks -> %d used",
-+ i, vc_cma_chunks_used);
-+ }
-+ break;
-+
-+ case VC_CMA_MSG_UPDATE_RESERVE:{
-+ int chunks_needed =
-+ ((vc_cma_reserve_total + VC_CMA_CHUNK_SIZE -
-+ 1)
-+ / VC_CMA_CHUNK_SIZE) -
-+ vc_cma_chunks_reserved;
-+
-+ LOG_DBG
-+ ("CMA_MSG_UPDATE_RESERVE(%d chunks needed)",
-+ chunks_needed);
-+
-+ /* Cap the reservations to what is available */
-+ if (chunks_needed > 0) {
-+ if (chunks_needed >
-+ (vc_cma_chunks -
-+ vc_cma_chunks_used))
-+ chunks_needed =
-+ (vc_cma_chunks -
-+ vc_cma_chunks_used);
-+
-+ chunks_needed =
-+ vc_cma_alloc_chunks(chunks_needed,
-+ &reply);
-+ }
-+
-+ LOG_DBG
-+ ("CMA_MSG_UPDATE_RESERVE(%d chunks allocated)",
-+ chunks_needed);
-+ vc_cma_chunks_reserved += chunks_needed;
-+ }
-+ break;
-+
-+ default:
-+ LOG_ERR("unexpected msg type %d", type);
-+ break;
-+ }
-+ }
-+
-+ LOG_DBG("quitting...");
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_connected_init
-+*
-+* This function is called once the videocore has been connected.
-+*
-+***************************************************************************/
-+
-+static void vc_cma_connected_init(void)
-+{
-+ VCHIQ_SERVICE_PARAMS_T service_params;
-+
-+ LOG_DBG("vc_cma_connected_init");
-+
-+ if (!vchiu_queue_init(&cma_msg_queue, 16)) {
-+ LOG_ERR("could not create CMA msg queue");
-+ goto fail_queue;
-+ }
-+
-+ if (vchiq_initialise(&cma_instance) != VCHIQ_SUCCESS)
-+ goto fail_vchiq_init;
-+
-+ vchiq_connect(cma_instance);
-+
-+ service_params.fourcc = VC_CMA_FOURCC;
-+ service_params.callback = cma_service_callback;
-+ service_params.userdata = NULL;
-+ service_params.version = VC_CMA_VERSION;
-+ service_params.version_min = VC_CMA_VERSION;
-+
-+ if (vchiq_open_service(cma_instance, &service_params,
-+ &cma_service) != VCHIQ_SUCCESS) {
-+ LOG_ERR("failed to open service - already in use?");
-+ goto fail_vchiq_open;
-+ }
-+
-+ vchiq_release_service(cma_service);
-+
-+ cma_worker = kthread_create(cma_worker_proc, NULL, "cma_worker");
-+ if (!cma_worker) {
-+ LOG_ERR("could not create CMA worker thread");
-+ goto fail_worker;
-+ }
-+ set_user_nice(cma_worker, -20);
-+ wake_up_process(cma_worker);
-+
-+ return;
-+
-+fail_worker:
-+ vchiq_close_service(cma_service);
-+fail_vchiq_open:
-+ vchiq_shutdown(cma_instance);
-+fail_vchiq_init:
-+ vchiu_queue_delete(&cma_msg_queue);
-+fail_queue:
-+ return;
-+}
-+
-+void
-+loud_error_header(void)
-+{
-+ if (in_loud_error)
-+ return;
-+
-+ LOG_ERR("============================================================"
-+ "================");
-+ LOG_ERR("============================================================"
-+ "================");
-+ LOG_ERR("=====");
-+
-+ in_loud_error = 1;
-+}
-+
-+void
-+loud_error_footer(void)
-+{
-+ if (!in_loud_error)
-+ return;
-+
-+ LOG_ERR("=====");
-+ LOG_ERR("============================================================"
-+ "================");
-+ LOG_ERR("============================================================"
-+ "================");
-+
-+ in_loud_error = 0;
-+}
-+
-+#if 1
-+static int check_cma_config(void) { return 1; }
-+#else
-+static int
-+read_vc_debug_var(VC_MEM_ACCESS_HANDLE_T handle,
-+ const char *symbol,
-+ void *buf, size_t bufsize)
-+{
-+ VC_MEM_ADDR_T vcMemAddr;
-+ size_t vcMemSize;
-+ uint8_t *mapAddr;
-+ off_t vcMapAddr;
-+
-+ if (!LookupVideoCoreSymbol(handle, symbol,
-+ &vcMemAddr,
-+ &vcMemSize)) {
-+ loud_error_header();
-+ loud_error(
-+ "failed to find VC symbol \"%s\".",
-+ symbol);
-+ loud_error_footer();
-+ return 0;
-+ }
-+
-+ if (vcMemSize != bufsize) {
-+ loud_error_header();
-+ loud_error(
-+ "VC symbol \"%s\" is the wrong size.",
-+ symbol);
-+ loud_error_footer();
-+ return 0;
-+ }
-+
-+ vcMapAddr = (off_t)vcMemAddr & VC_MEM_TO_ARM_ADDR_MASK;
-+ vcMapAddr += mm_vc_mem_phys_addr;
-+ mapAddr = ioremap_nocache(vcMapAddr, vcMemSize);
-+ if (mapAddr == 0) {
-+ loud_error_header();
-+ loud_error(
-+ "failed to ioremap \"%s\" @ 0x%x "
-+ "(phys: 0x%x, size: %u).",
-+ symbol,
-+ (unsigned int)vcMapAddr,
-+ (unsigned int)vcMemAddr,
-+ (unsigned int)vcMemSize);
-+ loud_error_footer();
-+ return 0;
-+ }
-+
-+ memcpy(buf, mapAddr, bufsize);
-+ iounmap(mapAddr);
-+
-+ return 1;
-+}
-+
-+
-+static int
-+check_cma_config(void)
-+{
-+ VC_MEM_ACCESS_HANDLE_T mem_hndl;
-+ VC_MEM_ADDR_T mempool_start;
-+ VC_MEM_ADDR_T mempool_end;
-+ VC_MEM_ADDR_T mempool_offline_start;
-+ VC_MEM_ADDR_T mempool_offline_end;
-+ VC_MEM_ADDR_T cam_alloc_base;
-+ VC_MEM_ADDR_T cam_alloc_size;
-+ VC_MEM_ADDR_T cam_alloc_end;
-+ int success = 0;
-+
-+ if (OpenVideoCoreMemory(&mem_hndl) != 0)
-+ goto out;
-+
-+ /* Read the relevant VideoCore variables */
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_START",
-+ &mempool_start,
-+ sizeof(mempool_start)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_END",
-+ &mempool_end,
-+ sizeof(mempool_end)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_START",
-+ &mempool_offline_start,
-+ sizeof(mempool_offline_start)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_END",
-+ &mempool_offline_end,
-+ sizeof(mempool_offline_end)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "cam_alloc_base",
-+ &cam_alloc_base,
-+ sizeof(cam_alloc_base)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "cam_alloc_size",
-+ &cam_alloc_size,
-+ sizeof(cam_alloc_size)))
-+ goto close;
-+
-+ cam_alloc_end = cam_alloc_base + cam_alloc_size;
-+
-+ success = 1;
-+
-+ /* Now the sanity checks */
-+ if (!mempool_offline_start)
-+ mempool_offline_start = mempool_start;
-+ if (!mempool_offline_end)
-+ mempool_offline_end = mempool_end;
-+
-+ if (VCADDR_TO_PHYSADDR(mempool_offline_start) != vc_cma_base) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_START(%x -> %lx) doesn't match "
-+ "vc_cma_base(%x)",
-+ mempool_offline_start,
-+ VCADDR_TO_PHYSADDR(mempool_offline_start),
-+ vc_cma_base);
-+ success = 0;
-+ }
-+
-+ if (VCADDR_TO_PHYSADDR(mempool_offline_end) !=
-+ (vc_cma_base + vc_cma_size)) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_END(%x -> %lx) doesn't match "
-+ "vc_cma_base(%x) + vc_cma_size(%x) = %x",
-+ mempool_offline_start,
-+ VCADDR_TO_PHYSADDR(mempool_offline_end),
-+ vc_cma_base, vc_cma_size, vc_cma_base + vc_cma_size);
-+ success = 0;
-+ }
-+
-+ if (mempool_end < mempool_start) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_END(%x) must not be before "
-+ "__MEMPOOL_START(%x)",
-+ mempool_end,
-+ mempool_start);
-+ success = 0;
-+ }
-+
-+ if (mempool_offline_end < mempool_offline_start) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_END(%x) must not be before "
-+ "__MEMPOOL_OFFLINE_START(%x)",
-+ mempool_offline_end,
-+ mempool_offline_start);
-+ success = 0;
-+ }
-+
-+ if (mempool_offline_start < mempool_start) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_START(%x) must not be before "
-+ "__MEMPOOL_START(%x)",
-+ mempool_offline_start,
-+ mempool_start);
-+ success = 0;
-+ }
-+
-+ if (mempool_offline_end > mempool_end) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_END(%x) must not be after "
-+ "__MEMPOOL_END(%x)",
-+ mempool_offline_end,
-+ mempool_end);
-+ success = 0;
-+ }
-+
-+ if ((cam_alloc_base < mempool_end) &&
-+ (cam_alloc_end > mempool_start)) {
-+ loud_error_header();
-+ loud_error(
-+ "cam_alloc pool(%x-%x) overlaps "
-+ "mempool(%x-%x)",
-+ cam_alloc_base, cam_alloc_end,
-+ mempool_start, mempool_end);
-+ success = 0;
-+ }
-+
-+ loud_error_footer();
-+
-+close:
-+ CloseVideoCoreMemory(mem_hndl);
-+
-+out:
-+ return success;
-+}
-+#endif
-+
-+static int vc_cma_init(void)
-+{
-+ int rc = -EFAULT;
-+ struct device *dev;
-+
-+ if (!check_cma_config())
-+ goto out_release;
-+
-+ printk(KERN_INFO "vc-cma: Videocore CMA driver\n");
-+ printk(KERN_INFO "vc-cma: vc_cma_base = 0x%08x\n", vc_cma_base);
-+ printk(KERN_INFO "vc-cma: vc_cma_size = 0x%08x (%u MiB)\n",
-+ vc_cma_size, vc_cma_size / (1024 * 1024));
-+ printk(KERN_INFO "vc-cma: vc_cma_initial = 0x%08x (%u MiB)\n",
-+ vc_cma_initial, vc_cma_initial / (1024 * 1024));
-+
-+ vc_cma_base_page = phys_to_page(vc_cma_base);
-+
-+ if (vc_cma_chunks) {
-+ int chunks_needed = vc_cma_initial / VC_CMA_CHUNK_SIZE;
-+
-+ for (vc_cma_chunks_used = 0;
-+ vc_cma_chunks_used < chunks_needed; vc_cma_chunks_used++) {
-+ struct page *chunk;
-+ chunk = dma_alloc_from_contiguous(NULL /*&vc_cma_device.dev*/,
-+ PAGES_PER_CHUNK,
-+ VC_CMA_CHUNK_ORDER);
-+ if (!chunk)
-+ break;
-+ BUG_ON(((page_to_phys(chunk) - vc_cma_base) %
-+ VC_CMA_CHUNK_SIZE) != 0);
-+ }
-+ if (vc_cma_chunks_used != chunks_needed) {
-+ LOG_ERR("%s: dma_alloc_from_contiguous failed (%d "
-+ "bytes, allocation %d of %d)",
-+ __func__, VC_CMA_CHUNK_SIZE,
-+ vc_cma_chunks_used, chunks_needed);
-+ goto out_release;
-+ }
-+
-+ vchiq_add_connected_callback(vc_cma_connected_init);
-+ }
-+
-+ rc = alloc_chrdev_region(&vc_cma_devnum, 0, 1, DRIVER_NAME);
-+ if (rc < 0) {
-+ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
-+ goto out_release;
-+ }
-+
-+ cdev_init(&vc_cma_cdev, &vc_cma_fops);
-+ rc = cdev_add(&vc_cma_cdev, vc_cma_devnum, 1);
-+ if (rc != 0) {
-+ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
-+ goto out_unregister;
-+ }
-+
-+ vc_cma_class = class_create(THIS_MODULE, DRIVER_NAME);
-+ if (IS_ERR(vc_cma_class)) {
-+ rc = PTR_ERR(vc_cma_class);
-+ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
-+ goto out_cdev_del;
-+ }
-+
-+ dev = device_create(vc_cma_class, NULL, vc_cma_devnum, NULL,
-+ DRIVER_NAME);
-+ if (IS_ERR(dev)) {
-+ rc = PTR_ERR(dev);
-+ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
-+ goto out_class_destroy;
-+ }
-+
-+ vc_cma_proc_entry = proc_create(DRIVER_NAME, 0444, NULL, &vc_cma_proc_fops);
-+ if (vc_cma_proc_entry == NULL) {
-+ rc = -EFAULT;
-+ LOG_ERR("%s: proc_create failed", __func__);
-+ goto out_device_destroy;
-+ }
-+
-+ vc_cma_inited = 1;
-+ return 0;
-+
-+out_device_destroy:
-+ device_destroy(vc_cma_class, vc_cma_devnum);
-+
-+out_class_destroy:
-+ class_destroy(vc_cma_class);
-+ vc_cma_class = NULL;
-+
-+out_cdev_del:
-+ cdev_del(&vc_cma_cdev);
-+
-+out_unregister:
-+ unregister_chrdev_region(vc_cma_devnum, 1);
-+
-+out_release:
-+ /* It is tempting to try to clean up by calling
-+ dma_release_from_contiguous for all allocated chunks, but it isn't
-+ a very safe thing to do. If vc_cma_initial is non-zero it is because
-+ VideoCore is already using that memory, so giving it back to Linux
-+ is likely to be fatal.
-+ */
-+ return -1;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_exit
-+*
-+***************************************************************************/
-+
-+static void __exit vc_cma_exit(void)
-+{
-+ LOG_DBG("%s: called", __func__);
-+
-+ if (vc_cma_inited) {
-+ remove_proc_entry(DRIVER_NAME, NULL);
-+ device_destroy(vc_cma_class, vc_cma_devnum);
-+ class_destroy(vc_cma_class);
-+ cdev_del(&vc_cma_cdev);
-+ unregister_chrdev_region(vc_cma_devnum, 1);
-+ }
-+}
-+
-+module_init(vc_cma_init);
-+module_exit(vc_cma_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-diff -Nur linux-3.12.38/drivers/char/broadcom/vc_sm/Makefile linux-rpi/drivers/char/broadcom/vc_sm/Makefile
---- linux-3.12.38/drivers/char/broadcom/vc_sm/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/vc_sm/Makefile 2015-03-09 10:39:29.730893739 +0100
-@@ -0,0 +1,21 @@
-+EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2
-+
-+EXTRA_CFLAGS += -I"./arch/arm/mach-bcm2708/include/mach"
-+EXTRA_CFLAGS += -I"drivers/misc/vc04_services"
-+EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchi"
-+EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm"
-+EXTRA_CFLAGS += -I"$(srctree)/fs/"
-+
-+EXTRA_CFLAGS += -DOS_ASSERT_FAILURE
-+EXTRA_CFLAGS += -D__STDC_VERSION=199901L
-+EXTRA_CFLAGS += -D__STDC_VERSION__=199901L
-+EXTRA_CFLAGS += -D__VCCOREVER__=0
-+EXTRA_CFLAGS += -D__KERNEL__
-+EXTRA_CFLAGS += -D__linux__
-+EXTRA_CFLAGS += -Werror
-+
-+obj-$(CONFIG_BCM_VC_SM) := vc-sm.o
-+
-+vc-sm-objs := \
-+ vmcs_sm.o \
-+ vc_vchi_sm.o
-diff -Nur linux-3.12.38/drivers/char/broadcom/vc_sm/vc_vchi_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c
---- linux-3.12.38/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 2015-03-09 10:39:29.730893739 +0100
-@@ -0,0 +1,492 @@
-+/*****************************************************************************
-+* Copyright 2011-2012 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/semaphore.h>
-+#include <linux/mutex.h>
-+#include <linux/slab.h>
-+#include <linux/kthread.h>
-+
-+#include "vc_vchi_sm.h"
-+
-+#define VC_SM_VER 1
-+#define VC_SM_MIN_VER 0
-+
-+/* ---- Private Constants and Types -------------------------------------- */
-+
-+/* Command blocks come from a pool */
-+#define SM_MAX_NUM_CMD_RSP_BLKS 32
-+
-+struct sm_cmd_rsp_blk {
-+ struct list_head head; /* To create lists */
-+ struct semaphore sema; /* To be signaled when the response is there */
-+
-+ uint16_t id;
-+ uint16_t length;
-+
-+ uint8_t msg[VC_SM_MAX_MSG_LEN];
-+
-+ uint32_t wait:1;
-+ uint32_t sent:1;
-+ uint32_t alloc:1;
-+
-+};
-+
-+struct sm_instance {
-+ uint32_t num_connections;
-+ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
-+ struct task_struct *io_thread;
-+ struct semaphore io_sema;
-+
-+ uint32_t trans_id;
-+
-+ struct mutex lock;
-+ struct list_head cmd_list;
-+ struct list_head rsp_list;
-+ struct list_head dead_list;
-+
-+ struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS];
-+ struct list_head free_list;
-+ struct mutex free_lock;
-+ struct semaphore free_sema;
-+
-+};
-+
-+/* ---- Private Variables ------------------------------------------------ */
-+
-+/* ---- Private Function Prototypes -------------------------------------- */
-+
-+/* ---- Private Functions ------------------------------------------------ */
-+static struct
-+sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance,
-+ VC_SM_MSG_TYPE id, void *msg,
-+ uint32_t size, int wait)
-+{
-+ struct sm_cmd_rsp_blk *blk;
-+ VC_SM_MSG_HDR_T *hdr;
-+
-+ if (down_interruptible(&instance->free_sema)) {
-+ blk = kmalloc(sizeof(*blk), GFP_KERNEL);
-+ if (!blk)
-+ return NULL;
-+
-+ blk->alloc = 1;
-+ sema_init(&blk->sema, 0);
-+ } else {
-+ mutex_lock(&instance->free_lock);
-+ blk =
-+ list_first_entry(&instance->free_list,
-+ struct sm_cmd_rsp_blk, head);
-+ list_del(&blk->head);
-+ mutex_unlock(&instance->free_lock);
-+ }
-+
-+ blk->sent = 0;
-+ blk->wait = wait;
-+ blk->length = sizeof(*hdr) + size;
-+
-+ hdr = (VC_SM_MSG_HDR_T *) blk->msg;
-+ hdr->type = id;
-+ mutex_lock(&instance->lock);
-+ hdr->trans_id = blk->id = ++instance->trans_id;
-+ mutex_unlock(&instance->lock);
-+
-+ if (size)
-+ memcpy(hdr->body, msg, size);
-+
-+ return blk;
-+}
-+
-+static void
-+vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk)
-+{
-+ if (blk->alloc) {
-+ kfree(blk);
-+ return;
-+ }
-+
-+ mutex_lock(&instance->free_lock);
-+ list_add(&blk->head, &instance->free_list);
-+ mutex_unlock(&instance->free_lock);
-+ up(&instance->free_sema);
-+}
-+
-+static int vc_vchi_sm_videocore_io(void *arg)
-+{
-+ struct sm_instance *instance = arg;
-+ struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp;
-+ VC_SM_RESULT_T *reply;
-+ uint32_t reply_len;
-+ int32_t status;
-+ int svc_use = 1;
-+
-+ while (1) {
-+ if (svc_use)
-+ vchi_service_release(instance->vchi_handle[0]);
-+ svc_use = 0;
-+ if (!down_interruptible(&instance->io_sema)) {
-+ vchi_service_use(instance->vchi_handle[0]);
-+ svc_use = 1;
-+
-+ do {
-+ unsigned int flags;
-+ /*
-+ * Get new command and move it to response list
-+ */
-+ mutex_lock(&instance->lock);
-+ if (list_empty(&instance->cmd_list)) {
-+ /* no more commands to process */
-+ mutex_unlock(&instance->lock);
-+ break;
-+ }
-+ cmd =
-+ list_first_entry(&instance->cmd_list,
-+ struct sm_cmd_rsp_blk,
-+ head);
-+ list_move(&cmd->head, &instance->rsp_list);
-+ cmd->sent = 1;
-+ mutex_unlock(&instance->lock);
-+
-+ /* Send the command */
-+ flags = VCHI_FLAGS_BLOCK_UNTIL_QUEUED;
-+ status = vchi_msg_queue(
-+ instance->vchi_handle[0],
-+ cmd->msg, cmd->length,
-+ flags, NULL);
-+ if (status) {
-+ pr_err("%s: failed to queue message (%d)",
-+ __func__, status);
-+ }
-+
-+ /* If no reply is needed then we're done */
-+ if (!cmd->wait) {
-+ mutex_lock(&instance->lock);
-+ list_del(&cmd->head);
-+ mutex_unlock(&instance->lock);
-+ vc_vchi_cmd_delete(instance, cmd);
-+ continue;
-+ }
-+
-+ if (status) {
-+ up(&cmd->sema);
-+ continue;
-+ }
-+
-+ } while (1);
-+
-+ while (!vchi_msg_peek
-+ (instance->vchi_handle[0], (void **)&reply,
-+ &reply_len, VCHI_FLAGS_NONE)) {
-+ mutex_lock(&instance->lock);
-+ list_for_each_entry(cmd, &instance->rsp_list,
-+ head) {
-+ if (cmd->id == reply->trans_id)
-+ break;
-+ }
-+ mutex_unlock(&instance->lock);
-+
-+ if (&cmd->head == &instance->rsp_list) {
-+ pr_debug("%s: received response %u, throw away...",
-+ __func__, reply->trans_id);
-+ } else if (reply_len > sizeof(cmd->msg)) {
-+ pr_err("%s: reply too big (%u) %u, throw away...",
-+ __func__, reply_len,
-+ reply->trans_id);
-+ } else {
-+ memcpy(cmd->msg, reply, reply_len);
-+ up(&cmd->sema);
-+ }
-+
-+ vchi_msg_remove(instance->vchi_handle[0]);
-+ }
-+
-+ /* Go through the dead list and free them */
-+ mutex_lock(&instance->lock);
-+ list_for_each_entry_safe(cmd, cmd_tmp,
-+ &instance->dead_list, head) {
-+ list_del(&cmd->head);
-+ vc_vchi_cmd_delete(instance, cmd);
-+ }
-+ mutex_unlock(&instance->lock);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void vc_sm_vchi_callback(void *param,
-+ const VCHI_CALLBACK_REASON_T reason,
-+ void *msg_handle)
-+{
-+ struct sm_instance *instance = param;
-+
-+ (void)msg_handle;
-+
-+ switch (reason) {
-+ case VCHI_CALLBACK_MSG_AVAILABLE:
-+ up(&instance->io_sema);
-+ break;
-+
-+ case VCHI_CALLBACK_SERVICE_CLOSED:
-+ pr_info("%s: service CLOSED!!", __func__);
-+ default:
-+ break;
-+ }
-+}
-+
-+VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
-+ VCHI_CONNECTION_T **vchi_connections,
-+ uint32_t num_connections)
-+{
-+ uint32_t i;
-+ struct sm_instance *instance;
-+ int status;
-+
-+ pr_debug("%s: start", __func__);
-+
-+ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
-+ pr_err("%s: unsupported number of connections %u (max=%u)",
-+ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
-+
-+ goto err_null;
-+ }
-+ /* Allocate memory for this instance */
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+
-+ /* Misc initialisations */
-+ mutex_init(&instance->lock);
-+ sema_init(&instance->io_sema, 0);
-+ INIT_LIST_HEAD(&instance->cmd_list);
-+ INIT_LIST_HEAD(&instance->rsp_list);
-+ INIT_LIST_HEAD(&instance->dead_list);
-+ INIT_LIST_HEAD(&instance->free_list);
-+ sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS);
-+ mutex_init(&instance->free_lock);
-+ for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) {
-+ sema_init(&instance->free_blk[i].sema, 0);
-+ list_add(&instance->free_blk[i].head, &instance->free_list);
-+ }
-+
-+ /* Open the VCHI service connections */
-+ instance->num_connections = num_connections;
-+ for (i = 0; i < num_connections; i++) {
-+ SERVICE_CREATION_T params = {
-+ VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER),
-+ VC_SM_SERVER_NAME,
-+ vchi_connections[i],
-+ 0,
-+ 0,
-+ vc_sm_vchi_callback,
-+ instance,
-+ 0,
-+ 0,
-+ 0,
-+ };
-+
-+ status = vchi_service_open(vchi_instance,
-+ &params, &instance->vchi_handle[i]);
-+ if (status) {
-+ pr_err("%s: failed to open VCHI service (%d)",
-+ __func__, status);
-+
-+ goto err_close_services;
-+ }
-+ }
-+
-+ /* Create the thread which takes care of all io to/from videoocore. */
-+ instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io,
-+ (void *)instance, "SMIO");
-+ if (instance->io_thread == NULL) {
-+ pr_err("%s: failed to create SMIO thread", __func__);
-+
-+ goto err_close_services;
-+ }
-+ set_user_nice(instance->io_thread, -10);
-+ wake_up_process(instance->io_thread);
-+
-+ pr_debug("%s: success - instance 0x%x", __func__, (unsigned)instance);
-+ return instance;
-+
-+err_close_services:
-+ for (i = 0; i < instance->num_connections; i++) {
-+ if (instance->vchi_handle[i] != NULL)
-+ vchi_service_close(instance->vchi_handle[i]);
-+ }
-+ kfree(instance);
-+err_null:
-+ pr_debug("%s: FAILED", __func__);
-+ return NULL;
-+}
-+
-+int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle)
-+{
-+ struct sm_instance *instance;
-+ uint32_t i;
-+
-+ if (handle == NULL) {
-+ pr_err("%s: invalid pointer to handle %p", __func__, handle);
-+ goto lock;
-+ }
-+
-+ if (*handle == NULL) {
-+ pr_err("%s: invalid handle %p", __func__, *handle);
-+ goto lock;
-+ }
-+
-+ instance = *handle;
-+
-+ /* Close all VCHI service connections */
-+ for (i = 0; i < instance->num_connections; i++) {
-+ int32_t success;
-+ vchi_service_use(instance->vchi_handle[i]);
-+
-+ success = vchi_service_close(instance->vchi_handle[i]);
-+ }
-+
-+ kfree(instance);
-+
-+ *handle = NULL;
-+ return 0;
-+
-+lock:
-+ return -EINVAL;
-+}
-+
-+int vc_vchi_sm_send_msg(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_MSG_TYPE msg_id,
-+ void *msg, uint32_t msg_size,
-+ void *result, uint32_t result_size,
-+ uint32_t *cur_trans_id, uint8_t wait_reply)
-+{
-+ int status = 0;
-+ struct sm_instance *instance = handle;
-+ struct sm_cmd_rsp_blk *cmd_blk;
-+
-+ if (handle == NULL) {
-+ pr_err("%s: invalid handle", __func__);
-+ return -EINVAL;
-+ }
-+ if (msg == NULL) {
-+ pr_err("%s: invalid msg pointer", __func__);
-+ return -EINVAL;
-+ }
-+
-+ cmd_blk =
-+ vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply);
-+ if (cmd_blk == NULL) {
-+ pr_err("[%s]: failed to allocate global tracking resource",
-+ __func__);
-+ return -ENOMEM;
-+ }
-+
-+ if (cur_trans_id != NULL)
-+ *cur_trans_id = cmd_blk->id;
-+
-+ mutex_lock(&instance->lock);
-+ list_add_tail(&cmd_blk->head, &instance->cmd_list);
-+ mutex_unlock(&instance->lock);
-+ up(&instance->io_sema);
-+
-+ if (!wait_reply)
-+ /* We're done */
-+ return 0;
-+
-+ /* Wait for the response */
-+ if (down_interruptible(&cmd_blk->sema)) {
-+ mutex_lock(&instance->lock);
-+ if (!cmd_blk->sent) {
-+ list_del(&cmd_blk->head);
-+ mutex_unlock(&instance->lock);
-+ vc_vchi_cmd_delete(instance, cmd_blk);
-+ return -ENXIO;
-+ }
-+ mutex_unlock(&instance->lock);
-+
-+ mutex_lock(&instance->lock);
-+ list_move(&cmd_blk->head, &instance->dead_list);
-+ mutex_unlock(&instance->lock);
-+ up(&instance->io_sema);
-+ return -EINTR; /* We're done */
-+ }
-+
-+ if (result && result_size) {
-+ memcpy(result, cmd_blk->msg, result_size);
-+ } else {
-+ VC_SM_RESULT_T *res = (VC_SM_RESULT_T *) cmd_blk->msg;
-+ status = (res->success == 0) ? 0 : -ENXIO;
-+ }
-+
-+ mutex_lock(&instance->lock);
-+ list_del(&cmd_blk->head);
-+ mutex_unlock(&instance->lock);
-+ vc_vchi_cmd_delete(instance, cmd_blk);
-+ return status;
-+}
-+
-+int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, VC_SM_ALLOC_T *msg,
-+ VC_SM_ALLOC_RESULT_T *result, uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC,
-+ msg, sizeof(*msg), result, sizeof(*result),
-+ cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_FREE_T *msg, uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE,
-+ msg, sizeof(*msg), 0, 0, cur_trans_id, 0);
-+}
-+
-+int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *msg,
-+ VC_SM_LOCK_RESULT_T *result, uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK,
-+ msg, sizeof(*msg), result, sizeof(*result),
-+ cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *msg,
-+ uint32_t *cur_trans_id, uint8_t wait_reply)
-+{
-+ return vc_vchi_sm_send_msg(handle, wait_reply ?
-+ VC_SM_MSG_TYPE_UNLOCK :
-+ VC_SM_MSG_TYPE_UNLOCK_NOANS, msg,
-+ sizeof(*msg), 0, 0, cur_trans_id,
-+ wait_reply);
-+}
-+
-+int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, VC_SM_RESIZE_T *msg,
-+ uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE,
-+ msg, sizeof(*msg), 0, 0, cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC,
-+ 0, 0, 0, 0, 0, 0);
-+}
-+
-+int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, VC_SM_ACTION_CLEAN_T *msg)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN,
-+ msg, sizeof(*msg), 0, 0, 0, 0);
-+}
-diff -Nur linux-3.12.38/drivers/char/broadcom/vc_sm/vmcs_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c
---- linux-3.12.38/drivers/char/broadcom/vc_sm/vmcs_sm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c 2015-03-09 10:39:29.730893739 +0100
-@@ -0,0 +1,3163 @@
-+/*****************************************************************************
-+* Copyright 2011-2012 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+#include <linux/cdev.h>
-+#include <linux/device.h>
-+#include <linux/debugfs.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/errno.h>
-+#include <linux/fs.h>
-+#include <linux/hugetlb.h>
-+#include <linux/ioctl.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/mm.h>
-+#include <linux/pfn.h>
-+#include <linux/proc_fs.h>
-+#include <linux/pagemap.h>
-+#include <linux/semaphore.h>
-+#include <linux/slab.h>
-+#include <linux/seq_file.h>
-+#include <linux/types.h>
-+#include <asm/cacheflush.h>
-+
-+#include <vc_mem.h>
-+
-+#include "vchiq_connected.h"
-+#include "vc_vchi_sm.h"
-+
-+#include <vmcs_sm_ioctl.h>
-+#include "vc_sm_knl.h"
-+
-+/* ---- Private Constants and Types --------------------------------------- */
-+
-+#define DEVICE_NAME "vcsm"
-+#define DEVICE_MINOR 0
-+
-+#define VC_SM_DIR_ROOT_NAME "vc-smem"
-+#define VC_SM_DIR_ALLOC_NAME "alloc"
-+#define VC_SM_STATE "state"
-+#define VC_SM_STATS "statistics"
-+#define VC_SM_RESOURCES "resources"
-+#define VC_SM_DEBUG "debug"
-+#define VC_SM_WRITE_BUF_SIZE 128
-+
-+/* Statistics tracked per resource and globally.
-+*/
-+enum SM_STATS_T {
-+ /* Attempt. */
-+ ALLOC,
-+ FREE,
-+ LOCK,
-+ UNLOCK,
-+ MAP,
-+ FLUSH,
-+ INVALID,
-+
-+ END_ATTEMPT,
-+
-+ /* Failure. */
-+ ALLOC_FAIL,
-+ FREE_FAIL,
-+ LOCK_FAIL,
-+ UNLOCK_FAIL,
-+ MAP_FAIL,
-+ FLUSH_FAIL,
-+ INVALID_FAIL,
-+
-+ END_ALL,
-+
-+};
-+
-+static const char *const sm_stats_human_read[] = {
-+ "Alloc",
-+ "Free",
-+ "Lock",
-+ "Unlock",
-+ "Map",
-+ "Cache Flush",
-+ "Cache Invalidate",
-+};
-+
-+typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v);
-+struct SM_PDE_T {
-+ VC_SM_SHOW show; /* Debug fs function hookup. */
-+ struct dentry *dir_entry; /* Debug fs directory entry. */
-+ void *priv_data; /* Private data */
-+
-+};
-+
-+/* Single resource allocation tracked for all devices.
-+*/
-+struct sm_mmap {
-+ struct list_head map_list; /* Linked list of maps. */
-+
-+ struct SM_RESOURCE_T *resource; /* Pointer to the resource. */
-+
-+ pid_t res_pid; /* PID owning that resource. */
-+ unsigned int res_vc_hdl; /* Resource handle (videocore). */
-+ unsigned int res_usr_hdl; /* Resource handle (user). */
-+
-+ long unsigned int res_addr; /* Mapped virtual address. */
-+ struct vm_area_struct *vma; /* VM area for this mapping. */
-+ unsigned int ref_count; /* Reference count to this vma. */
-+
-+ /* Used to link maps associated with a resource. */
-+ struct list_head resource_map_list;
-+};
-+
-+/* Single resource allocation tracked for each opened device.
-+*/
-+struct SM_RESOURCE_T {
-+ struct list_head resource_list; /* List of resources. */
-+ struct list_head global_resource_list; /* Global list of resources. */
-+
-+ pid_t pid; /* PID owning that resource. */
-+ uint32_t res_guid; /* Unique identifier. */
-+ uint32_t lock_count; /* Lock count for this resource. */
-+ uint32_t ref_count; /* Ref count for this resource. */
-+
-+ uint32_t res_handle; /* Resource allocation handle. */
-+ void *res_base_mem; /* Resource base memory address. */
-+ uint32_t res_size; /* Resource size allocated. */
-+ enum vmcs_sm_cache_e res_cached; /* Resource cache type. */
-+ struct SM_RESOURCE_T *res_shared; /* Shared resource */
-+
-+ enum SM_STATS_T res_stats[END_ALL]; /* Resource statistics. */
-+
-+ uint8_t map_count; /* Counter of mappings for this resource. */
-+ struct list_head map_list; /* Maps associated with a resource. */
-+
-+ struct SM_PRIV_DATA_T *private;
-+};
-+
-+/* Private file data associated with each opened device.
-+*/
-+struct SM_PRIV_DATA_T {
-+ struct list_head resource_list; /* List of resources. */
-+
-+ pid_t pid; /* PID of creator. */
-+
-+ struct dentry *dir_pid; /* Debug fs entries root. */
-+ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */
-+ struct SM_PDE_T dir_res; /* Debug fs resource sub-tree. */
-+
-+ int restart_sys; /* Tracks restart on interrupt. */
-+ VC_SM_MSG_TYPE int_action; /* Interrupted action. */
-+ uint32_t int_trans_id; /* Interrupted transaction. */
-+
-+};
-+
-+/* Global state information.
-+*/
-+struct SM_STATE_T {
-+ VC_VCHI_SM_HANDLE_T sm_handle; /* Handle for videocore service. */
-+ struct dentry *dir_root; /* Debug fs entries root. */
-+ struct dentry *dir_alloc; /* Debug fs entries allocations. */
-+ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */
-+ struct SM_PDE_T dir_state; /* Debug fs entries state sub-tree. */
-+ struct dentry *debug; /* Debug fs entries debug. */
-+
-+ struct mutex map_lock; /* Global map lock. */
-+ struct list_head map_list; /* List of maps. */
-+ struct list_head resource_list; /* List of resources. */
-+
-+ enum SM_STATS_T deceased[END_ALL]; /* Natural termination stats. */
-+ enum SM_STATS_T terminated[END_ALL]; /* Forced termination stats. */
-+ uint32_t res_deceased_cnt; /* Natural termination counter. */
-+ uint32_t res_terminated_cnt; /* Forced termination counter. */
-+
-+ struct cdev sm_cdev; /* Device. */
-+ dev_t sm_devid; /* Device identifier. */
-+ struct class *sm_class; /* Class. */
-+ struct device *sm_dev; /* Device. */
-+
-+ struct SM_PRIV_DATA_T *data_knl; /* Kernel internal data tracking. */
-+
-+ struct mutex lock; /* Global lock. */
-+ uint32_t guid; /* GUID (next) tracker. */
-+
-+};
-+
-+/* ---- Private Variables ----------------------------------------------- */
-+
-+static struct SM_STATE_T *sm_state;
-+static int sm_inited;
-+
-+static const char *const sm_cache_map_vector[] = {
-+ "(null)",
-+ "host",
-+ "videocore",
-+ "host+videocore",
-+};
-+
-+/* ---- Private Function Prototypes -------------------------------------- */
-+
-+/* ---- Private Functions ------------------------------------------------ */
-+
-+static inline unsigned vcaddr_to_pfn(unsigned long vc_addr)
-+{
-+ unsigned long pfn = vc_addr & 0x3FFFFFFF;
-+ pfn += mm_vc_mem_phys_addr;
-+ pfn >>= PAGE_SHIFT;
-+ return pfn;
-+}
-+
-+/* Carries over to the state statistics the statistics once owned by a deceased
-+** resource.
-+*/
-+static void vc_sm_resource_deceased(struct SM_RESOURCE_T *p_res, int terminated)
-+{
-+ if (sm_state != NULL) {
-+ if (p_res != NULL) {
-+ int ix;
-+
-+ if (terminated)
-+ sm_state->res_terminated_cnt++;
-+ else
-+ sm_state->res_deceased_cnt++;
-+
-+ for (ix = 0; ix < END_ALL; ix++) {
-+ if (terminated)
-+ sm_state->terminated[ix] +=
-+ p_res->res_stats[ix];
-+ else
-+ sm_state->deceased[ix] +=
-+ p_res->res_stats[ix];
-+ }
-+ }
-+ }
-+}
-+
-+/* Fetch a videocore handle corresponding to a mapping of the pid+address
-+** returns 0 (ie NULL) if no such handle exists in the global map.
-+*/
-+static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid,
-+ unsigned int addr)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int handle = 0;
-+
-+ if (!sm_state || addr == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_addr != addr)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n",
-+ __func__, map, map->res_pid, map->res_addr,
-+ map->res_vc_hdl, map->res_usr_hdl);
-+
-+ handle = map->res_vc_hdl;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ ** for something that is not mapped, we do not want a kernel log each
-+ ** time around.
-+ **
-+ ** There are other error log that would pop up accordingly if someone
-+ ** subsequently tries to use something invalid after being told not to
-+ ** use it...
-+ */
-+ if (handle == 0) {
-+ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
-+ __func__, pid, addr);
-+ }
-+
-+ return handle;
-+}
-+
-+/* Fetch a user handle corresponding to a mapping of the pid+address
-+** returns 0 (ie NULL) if no such handle exists in the global map.
-+*/
-+static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid,
-+ unsigned int addr)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int handle = 0;
-+
-+ if (!sm_state || addr == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_addr != addr)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n",
-+ __func__, map, map->res_pid, map->res_addr,
-+ map->res_usr_hdl, map->res_vc_hdl);
-+
-+ handle = map->res_usr_hdl;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ * for something that is not mapped yet.
-+ *
-+ * There are other error log that would pop up accordingly if someone
-+ * subsequently tries to use something invalid after being told not to
-+ * use it...
-+ */
-+ if (handle == 0)
-+ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
-+ __func__, pid, addr);
-+
-+ return handle;
-+}
-+
-+#if defined(DO_NOT_USE)
-+/* Fetch an address corresponding to a mapping of the pid+handle
-+** returns 0 (ie NULL) if no such address exists in the global map.
-+*/
-+static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid,
-+ unsigned int hdl)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int addr = 0;
-+
-+ if (sm_state == NULL || hdl == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_vc_hdl != hdl)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+
-+ addr = map->res_addr;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ ** for something that is not mapped, we do not want a kernel log each
-+ ** time around.
-+ **
-+ ** There are other error log that would pop up accordingly if someone
-+ ** subsequently tries to use something invalid after being told not to
-+ ** use it...
-+ */
-+ if (addr == 0)
-+ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n",
-+ __func__, pid, hdl);
-+
-+ return addr;
-+}
-+#endif
-+
-+/* Fetch an address corresponding to a mapping of the pid+handle
-+** returns 0 (ie NULL) if no such address exists in the global map.
-+*/
-+static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int
-+ pid,
-+ unsigned int
-+ hdl)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int addr = 0;
-+
-+ if (sm_state == NULL || hdl == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_usr_hdl != hdl)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+
-+ addr = map->res_addr;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ * for something that is not mapped, we do not want a kernel log each
-+ * time around.
-+ *
-+ * There are other error log that would pop up accordingly if someone
-+ * subsequently tries to use something invalid after being told not to
-+ * use it...
-+ */
-+ if (addr == 0)
-+ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__,
-+ pid, hdl);
-+
-+ return addr;
-+}
-+
-+/* Adds a resource mapping to the global data list.
-+*/
-+static void vmcs_sm_add_map(struct SM_STATE_T *state,
-+ struct SM_RESOURCE_T *resource, struct sm_mmap *map)
-+{
-+ mutex_lock(&(state->map_lock));
-+
-+ /* Add to the global list of mappings
-+ */
-+ list_add(&map->map_list, &state->map_list);
-+
-+ /* Add to the list of mappings for this resource
-+ */
-+ list_add(&map->resource_map_list, &resource->map_list);
-+ resource->map_count++;
-+
-+ mutex_unlock(&(state->map_lock));
-+
-+ pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+}
-+
-+/* Removes a resource mapping from the global data list.
-+*/
-+static void vmcs_sm_remove_map(struct SM_STATE_T *state,
-+ struct SM_RESOURCE_T *resource,
-+ struct sm_mmap *map)
-+{
-+ mutex_lock(&(state->map_lock));
-+
-+ /* Remove from the global list of mappings
-+ */
-+ list_del(&map->map_list);
-+
-+ /* Remove from the list of mapping for this resource
-+ */
-+ list_del(&map->resource_map_list);
-+ if (resource->map_count > 0)
-+ resource->map_count--;
-+
-+ mutex_unlock(&(state->map_lock));
-+
-+ pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl,
-+ map->res_addr);
-+
-+ kfree(map);
-+}
-+
-+/* Read callback for the global state proc entry.
-+*/
-+static int vc_sm_global_state_show(struct seq_file *s, void *v)
-+{
-+ struct sm_mmap *map = NULL;
-+ int map_count = 0;
-+
-+ if (sm_state == NULL)
-+ return 0;
-+
-+ seq_printf(s, "\nVC-ServiceHandle 0x%x\n",
-+ (unsigned int)sm_state->sm_handle);
-+
-+ /* Log all applicable mapping(s).
-+ */
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ map_count++;
-+
-+ seq_printf(s, "\nMapping 0x%x\n",
-+ (unsigned int)map);
-+ seq_printf(s, " TGID %u\n",
-+ map->res_pid);
-+ seq_printf(s, " VC-HDL 0x%x\n",
-+ map->res_vc_hdl);
-+ seq_printf(s, " USR-HDL 0x%x\n",
-+ map->res_usr_hdl);
-+ seq_printf(s, " USR-ADDR 0x%lx\n",
-+ map->res_addr);
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+ seq_printf(s, "\n\nTotal map count: %d\n\n", map_count);
-+
-+ return 0;
-+}
-+
-+static int vc_sm_global_statistics_show(struct seq_file *s, void *v)
-+{
-+ int ix;
-+
-+ /* Global state tracked statistics.
-+ */
-+ if (sm_state != NULL) {
-+ seq_puts(s, "\nDeceased Resources Statistics\n");
-+
-+ seq_printf(s, "\nNatural Cause (%u occurences)\n",
-+ sm_state->res_deceased_cnt);
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->deceased[ix] > 0) {
-+ seq_printf(s, " %u\t%s\n",
-+ sm_state->deceased[ix],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ seq_puts(s, "\n");
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->deceased[ix + END_ATTEMPT] > 0) {
-+ seq_printf(s, " %u\tFAILED %s\n",
-+ sm_state->deceased[ix + END_ATTEMPT],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+
-+ seq_printf(s, "\nForcefull (%u occurences)\n",
-+ sm_state->res_terminated_cnt);
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->terminated[ix] > 0) {
-+ seq_printf(s, " %u\t%s\n",
-+ sm_state->terminated[ix],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ seq_puts(s, "\n");
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->terminated[ix + END_ATTEMPT] > 0) {
-+ seq_printf(s, " %u\tFAILED %s\n",
-+ sm_state->terminated[ix +
-+ END_ATTEMPT],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+#if 0
-+/* Read callback for the statistics proc entry.
-+*/
-+static int vc_sm_statistics_show(struct seq_file *s, void *v)
-+{
-+ int ix;
-+ struct SM_PRIV_DATA_T *file_data;
-+ struct SM_RESOURCE_T *resource;
-+ int res_count = 0;
-+ struct SM_PDE_T *p_pde;
-+
-+ p_pde = (struct SM_PDE_T *)(s->private);
-+ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data);
-+
-+ if (file_data == NULL)
-+ return 0;
-+
-+ /* Per process statistics.
-+ */
-+
-+ seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid);
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&file_data->resource_list)) {
-+ list_for_each_entry(resource, &file_data->resource_list,
-+ resource_list) {
-+ res_count++;
-+
-+ seq_printf(s, "\nGUID: 0x%x\n\n",
-+ resource->res_guid);
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (resource->res_stats[ix] > 0) {
-+ seq_printf(s,
-+ " %u\t%s\n",
-+ resource->res_stats[ix],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ seq_puts(s, "\n");
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (resource->res_stats[ix + END_ATTEMPT] > 0) {
-+ seq_printf(s,
-+ " %u\tFAILED %s\n",
-+ resource->res_stats[
-+ ix + END_ATTEMPT],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ seq_printf(s, "\nResources Count %d\n", res_count);
-+
-+ return 0;
-+}
-+#endif
-+
-+#if 0
-+/* Read callback for the allocation proc entry. */
-+static int vc_sm_alloc_show(struct seq_file *s, void *v)
-+{
-+ struct SM_PRIV_DATA_T *file_data;
-+ struct SM_RESOURCE_T *resource;
-+ int alloc_count = 0;
-+ struct SM_PDE_T *p_pde;
-+
-+ p_pde = (struct SM_PDE_T *)(s->private);
-+ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data);
-+
-+ if (!file_data)
-+ return 0;
-+
-+ /* Per process statistics. */
-+ seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid);
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&file_data->resource_list)) {
-+ list_for_each_entry(resource, &file_data->resource_list,
-+ resource_list) {
-+ alloc_count++;
-+
-+ seq_printf(s, "\nGUID: 0x%x\n",
-+ resource->res_guid);
-+ seq_printf(s, "Lock Count: %u\n",
-+ resource->lock_count);
-+ seq_printf(s, "Mapped: %s\n",
-+ (resource->map_count ? "yes" : "no"));
-+ seq_printf(s, "VC-handle: 0x%x\n",
-+ resource->res_handle);
-+ seq_printf(s, "VC-address: 0x%p\n",
-+ resource->res_base_mem);
-+ seq_printf(s, "VC-size (bytes): %u\n",
-+ resource->res_size);
-+ seq_printf(s, "Cache: %s\n",
-+ sm_cache_map_vector[resource->res_cached]);
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count);
-+
-+ return 0;
-+}
-+#endif
-+
-+static int vc_sm_seq_file_show(struct seq_file *s, void *v)
-+{
-+ struct SM_PDE_T *sm_pde;
-+
-+ sm_pde = (struct SM_PDE_T *)(s->private);
-+
-+ if (sm_pde && sm_pde->show)
-+ sm_pde->show(s, v);
-+
-+ return 0;
-+}
-+
-+static int vc_sm_single_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, vc_sm_seq_file_show, inode->i_private);
-+}
-+
-+static const struct file_operations vc_sm_debug_fs_fops = {
-+ .open = vc_sm_single_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+/* Adds a resource to the private data list which tracks all the allocated
-+** data.
-+*/
-+static void vmcs_sm_add_resource(struct SM_PRIV_DATA_T *privdata,
-+ struct SM_RESOURCE_T *resource)
-+{
-+ mutex_lock(&(sm_state->map_lock));
-+ list_add(&resource->resource_list, &privdata->resource_list);
-+ list_add(&resource->global_resource_list, &sm_state->resource_list);
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_base_mem,
-+ resource->res_handle, resource->res_size, resource->res_cached);
-+}
-+
-+/* Locates a resource and acquire a reference on it.
-+** The resource won't be deleted while there is a reference on it.
-+*/
-+static struct SM_RESOURCE_T *vmcs_sm_acquire_resource(struct SM_PRIV_DATA_T
-+ *private,
-+ unsigned int res_guid)
-+{
-+ struct SM_RESOURCE_T *resource, *ret = NULL;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ list_for_each_entry(resource, &private->resource_list, resource_list) {
-+ if (resource->res_guid != res_guid)
-+ continue;
-+
-+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_guid,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, resource->res_cached);
-+ resource->ref_count++;
-+ ret = resource;
-+ break;
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return ret;
-+}
-+
-+/* Locates a resource and acquire a reference on it.
-+** The resource won't be deleted while there is a reference on it.
-+*/
-+static struct SM_RESOURCE_T *vmcs_sm_acquire_first_resource(
-+ struct SM_PRIV_DATA_T *private)
-+{
-+ struct SM_RESOURCE_T *resource, *ret = NULL;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ list_for_each_entry(resource, &private->resource_list, resource_list) {
-+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_guid,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, resource->res_cached);
-+ resource->ref_count++;
-+ ret = resource;
-+ break;
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return ret;
-+}
-+
-+/* Locates a resource and acquire a reference on it.
-+** The resource won't be deleted while there is a reference on it.
-+*/
-+static struct SM_RESOURCE_T *vmcs_sm_acquire_global_resource(unsigned int
-+ res_guid)
-+{
-+ struct SM_RESOURCE_T *resource, *ret = NULL;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ list_for_each_entry(resource, &sm_state->resource_list,
-+ global_resource_list) {
-+ if (resource->res_guid != res_guid)
-+ continue;
-+
-+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_guid,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, resource->res_cached);
-+ resource->ref_count++;
-+ ret = resource;
-+ break;
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return ret;
-+}
-+
-+/* Release a previously acquired resource.
-+** The resource will be deleted when its refcount reaches 0.
-+*/
-+static void vmcs_sm_release_resource(struct SM_RESOURCE_T *resource, int force)
-+{
-+ struct SM_PRIV_DATA_T *private = resource->private;
-+ struct sm_mmap *map, *map_tmp;
-+ struct SM_RESOURCE_T *res_tmp;
-+ int ret;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (--resource->ref_count) {
-+ if (force)
-+ pr_err("[%s]: resource %p in use\n", __func__, resource);
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+ return;
-+ }
-+
-+ /* Time to free the resource. Start by removing it from the list */
-+ list_del(&resource->resource_list);
-+ list_del(&resource->global_resource_list);
-+
-+ /* Walk the global resource list, find out if the resource is used
-+ * somewhere else. In which case we don't want to delete it.
-+ */
-+ list_for_each_entry(res_tmp, &sm_state->resource_list,
-+ global_resource_list) {
-+ if (res_tmp->res_handle == resource->res_handle) {
-+ resource->res_handle = 0;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem);
-+ resource->res_stats[FREE]++;
-+
-+ /* Make sure the resource we're removing is unmapped first */
-+ if (resource->map_count && !list_empty(&resource->map_list)) {
-+ down_write(&current->mm->mmap_sem);
-+ list_for_each_entry_safe(map, map_tmp, &resource->map_list,
-+ resource_map_list) {
-+ ret =
-+ do_munmap(current->mm, map->res_addr,
-+ resource->res_size);
-+ if (ret) {
-+ pr_err("[%s]: could not unmap resource %p\n",
-+ __func__, resource);
-+ }
-+ }
-+ up_write(&current->mm->mmap_sem);
-+ }
-+
-+ /* Free up the videocore allocated resource.
-+ */
-+ if (resource->res_handle) {
-+ VC_SM_FREE_T free = {
-+ resource->res_handle, resource->res_base_mem
-+ };
-+ int status = vc_vchi_sm_free(sm_state->sm_handle, &free,
-+ &private->int_trans_id);
-+ if (status != 0 && status != -EINTR) {
-+ pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ resource->res_stats[FREE_FAIL]++;
-+ ret = -EPERM;
-+ }
-+ }
-+
-+ /* Free up the shared resource.
-+ */
-+ if (resource->res_shared)
-+ vmcs_sm_release_resource(resource->res_shared, 0);
-+
-+ /* Free up the local resource tracking this allocation.
-+ */
-+ vc_sm_resource_deceased(resource, force);
-+ kfree(resource);
-+}
-+
-+/* Dump the map table for the driver. If process is -1, dumps the whole table,
-+** if process is a valid pid (non -1) dump only the entries associated with the
-+** pid of interest.
-+*/
-+static void vmcs_sm_host_walk_map_per_pid(int pid)
-+{
-+ struct sm_mmap *map = NULL;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if (sm_state == NULL) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ return;
-+ }
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Log all applicable mapping(s).
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (pid == -1 || map->res_pid == pid) {
-+ pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n",
-+ __func__, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+ }
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return;
-+}
-+
-+/* Dump the allocation table from host side point of view. This only dumps the
-+** data allocated for this process/device referenced by the file_data.
-+*/
-+static void vmcs_sm_host_walk_alloc(struct SM_PRIV_DATA_T *file_data)
-+{
-+ struct SM_RESOURCE_T *resource = NULL;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if ((sm_state == NULL) || (file_data == NULL)) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ return;
-+ }
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&file_data->resource_list)) {
-+ list_for_each_entry(resource, &file_data->resource_list,
-+ resource_list) {
-+ pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem, resource->res_size,
-+ resource->res_cached);
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return;
-+}
-+
-+/* Create support for private data tracking.
-+*/
-+static struct SM_PRIV_DATA_T *vc_sm_create_priv_data(pid_t id)
-+{
-+ char alloc_name[32];
-+ struct SM_PRIV_DATA_T *file_data = NULL;
-+
-+ /* Allocate private structure. */
-+ file_data = kzalloc(sizeof(*file_data), GFP_KERNEL);
-+
-+ if (!file_data) {
-+ pr_err("[%s]: cannot allocate file data\n", __func__);
-+ goto out;
-+ }
-+
-+ snprintf(alloc_name, sizeof(alloc_name), "%d", id);
-+
-+ INIT_LIST_HEAD(&file_data->resource_list);
-+ file_data->pid = id;
-+ file_data->dir_pid = debugfs_create_dir(alloc_name,
-+ sm_state->dir_alloc);
-+#if 0
-+ /* TODO: fix this to support querying statistics per pid */
-+
-+ if (IS_ERR_OR_NULL(file_data->dir_pid)) {
-+ file_data->dir_pid = NULL;
-+ } else {
-+ struct dentry *dir_entry;
-+
-+ dir_entry = debugfs_create_file(VC_SM_RESOURCES, S_IRUGO,
-+ file_data->dir_pid, file_data,
-+ vc_sm_debug_fs_fops);
-+
-+ file_data->dir_res.dir_entry = dir_entry;
-+ file_data->dir_res.priv_data = file_data;
-+ file_data->dir_res.show = &vc_sm_alloc_show;
-+
-+ dir_entry = debugfs_create_file(VC_SM_STATS, S_IRUGO,
-+ file_data->dir_pid, file_data,
-+ vc_sm_debug_fs_fops);
-+
-+ file_data->dir_res.dir_entry = dir_entry;
-+ file_data->dir_res.priv_data = file_data;
-+ file_data->dir_res.show = &vc_sm_statistics_show;
-+ }
-+ pr_debug("[%s]: private data allocated %p\n", __func__, file_data);
-+
-+#endif
-+out:
-+ return file_data;
-+}
-+
-+/* Open the device. Creates a private state to help track all allocation
-+** associated with this device.
-+*/
-+static int vc_sm_open(struct inode *inode, struct file *file)
-+{
-+ int ret = 0;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if (!sm_state) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ file->private_data = vc_sm_create_priv_data(current->tgid);
-+ if (file->private_data == NULL) {
-+ pr_err("[%s]: failed to create data tracker\n", __func__);
-+
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/* Close the device. Free up all resources still associated with this device
-+** at the time.
-+*/
-+static int vc_sm_release(struct inode *inode, struct file *file)
-+{
-+ struct SM_PRIV_DATA_T *file_data =
-+ (struct SM_PRIV_DATA_T *)file->private_data;
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if (sm_state == NULL || file_data == NULL) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ pr_debug("[%s]: using private data %p\n", __func__, file_data);
-+
-+ if (file_data->restart_sys == -EINTR) {
-+ VC_SM_ACTION_CLEAN_T action_clean;
-+
-+ pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n",
-+ __func__, file_data->int_action,
-+ file_data->int_trans_id);
-+
-+ action_clean.res_action = file_data->int_action;
-+ action_clean.action_trans_id = file_data->int_trans_id;
-+
-+ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
-+ }
-+
-+ while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) {
-+ vmcs_sm_release_resource(resource, 0);
-+ vmcs_sm_release_resource(resource, 1);
-+ }
-+
-+ /* Remove the corresponding proc entry. */
-+ debugfs_remove_recursive(file_data->dir_pid);
-+
-+ /* Terminate the private data.
-+ */
-+ kfree(file_data);
-+
-+out:
-+ return ret;
-+}
-+
-+static void vcsm_vma_open(struct vm_area_struct *vma)
-+{
-+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+
-+ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
-+ __func__, vma->vm_start, vma->vm_end, (int)current->tgid,
-+ (int)vma->vm_pgoff);
-+
-+ map->ref_count++;
-+}
-+
-+static void vcsm_vma_close(struct vm_area_struct *vma)
-+{
-+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+
-+ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
-+ __func__, vma->vm_start, vma->vm_end, (int)current->tgid,
-+ (int)vma->vm_pgoff);
-+
-+ map->ref_count--;
-+
-+ /* Remove from the map table.
-+ */
-+ if (map->ref_count == 0)
-+ vmcs_sm_remove_map(sm_state, map->resource, map);
-+}
-+
-+static int vcsm_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
-+{
-+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+ struct SM_RESOURCE_T *resource = map->resource;
-+ pgoff_t page_offset;
-+ unsigned long pfn;
-+ int ret = 0;
-+
-+ /* Lock the resource if necessary.
-+ */
-+ if (!resource->lock_count) {
-+ VC_SM_LOCK_UNLOCK_T lock_unlock;
-+ VC_SM_LOCK_RESULT_T lock_result;
-+ int status;
-+
-+ lock_unlock.res_handle = resource->res_handle;
-+ lock_unlock.res_mem = resource->res_base_mem;
-+
-+ pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n",
-+ __func__, lock_unlock.res_handle, lock_unlock.res_mem);
-+
-+ /* Lock the videocore allocated resource.
-+ */
-+ status = vc_vchi_sm_lock(sm_state->sm_handle,
-+ &lock_unlock, &lock_result, 0);
-+ if ((status != 0) ||
-+ ((status == 0) && (lock_result.res_mem == NULL))) {
-+ pr_err("[%s]: failed to lock memory on videocore (status: %u)\n",
-+ __func__, status);
-+ resource->res_stats[LOCK_FAIL]++;
-+ return VM_FAULT_SIGBUS;
-+ }
-+
-+ pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem);
-+ outer_inv_range(__pfn_to_phys(pfn),
-+ __pfn_to_phys(pfn) + resource->res_size);
-+
-+ resource->res_stats[LOCK]++;
-+ resource->lock_count++;
-+
-+ /* Keep track of the new base memory.
-+ */
-+ if ((lock_result.res_mem != NULL) &&
-+ (lock_result.res_old_mem != NULL) &&
-+ (lock_result.res_mem != lock_result.res_old_mem)) {
-+ resource->res_base_mem = lock_result.res_mem;
-+ }
-+ }
-+
-+ /* We don't use vmf->pgoff since that has the fake offset */
-+ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start);
-+ pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF;
-+ pfn += mm_vc_mem_phys_addr;
-+ pfn += page_offset;
-+ pfn >>= PAGE_SHIFT;
-+
-+ /* Finally, remap it */
-+ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
-+
-+ switch (ret) {
-+ case 0:
-+ case -ERESTARTSYS:
-+ return VM_FAULT_NOPAGE;
-+ case -ENOMEM:
-+ case -EAGAIN:
-+ return VM_FAULT_OOM;
-+ default:
-+ return VM_FAULT_SIGBUS;
-+ }
-+}
-+
-+static struct vm_operations_struct vcsm_vm_ops = {
-+ .open = vcsm_vma_open,
-+ .close = vcsm_vma_close,
-+ .fault = vcsm_vma_fault,
-+};
-+
-+/* Walks a VMA and clean each valid page from the cache */
-+static void vcsm_vma_cache_clean_page_range(unsigned long addr,
-+ unsigned long end)
-+{
-+ pgd_t *pgd;
-+ pud_t *pud;
-+ pmd_t *pmd;
-+ pte_t *pte;
-+ unsigned long pgd_next, pud_next, pmd_next;
-+
-+ if (addr >= end)
-+ return;
-+
-+ /* Walk PGD */
-+ pgd = pgd_offset(current->mm, addr);
-+ do {
-+ pgd_next = pgd_addr_end(addr, end);
-+
-+ if (pgd_none(*pgd) || pgd_bad(*pgd))
-+ continue;
-+
-+ /* Walk PUD */
-+ pud = pud_offset(pgd, addr);
-+ do {
-+ pud_next = pud_addr_end(addr, pgd_next);
-+ if (pud_none(*pud) || pud_bad(*pud))
-+ continue;
-+
-+ /* Walk PMD */
-+ pmd = pmd_offset(pud, addr);
-+ do {
-+ pmd_next = pmd_addr_end(addr, pud_next);
-+ if (pmd_none(*pmd) || pmd_bad(*pmd))
-+ continue;
-+
-+ /* Walk PTE */
-+ pte = pte_offset_map(pmd, addr);
-+ do {
-+ if (pte_none(*pte)
-+ || !pte_present(*pte))
-+ continue;
-+
-+ /* Clean + invalidate */
-+ dmac_flush_range((const void *) addr,
-+ (const void *)
-+ (addr + PAGE_SIZE));
-+
-+ } while (pte++, addr +=
-+ PAGE_SIZE, addr != pmd_next);
-+ pte_unmap(pte);
-+
-+ } while (pmd++, addr = pmd_next, addr != pud_next);
-+
-+ } while (pud++, addr = pud_next, addr != pgd_next);
-+ } while (pgd++, addr = pgd_next, addr != end);
-+}
-+
-+/* Map an allocated data into something that the user space.
-+*/
-+static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma)
-+{
-+ int ret = 0;
-+ struct SM_PRIV_DATA_T *file_data =
-+ (struct SM_PRIV_DATA_T *)file->private_data;
-+ struct SM_RESOURCE_T *resource = NULL;
-+ struct sm_mmap *map = NULL;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if ((sm_state == NULL) || (file_data == NULL)) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data,
-+ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
-+
-+ /* We lookup to make sure that the data we are being asked to mmap is
-+ ** something that we allocated.
-+ **
-+ ** We use the offset information as the key to tell us which resource
-+ ** we are mapping.
-+ */
-+ resource = vmcs_sm_acquire_resource(file_data,
-+ ((unsigned int)vma->vm_pgoff <<
-+ PAGE_SHIFT));
-+ if (resource == NULL) {
-+ pr_err("[%s]: failed to locate resource for guid %x\n", __func__,
-+ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
-+ return -ENOMEM;
-+ }
-+
-+ pr_debug("[%s]: guid %x, tgid %u, %u, %u\n",
-+ __func__, resource->res_guid, current->tgid, resource->pid,
-+ file_data->pid);
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n",
-+ __func__, current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ /* Verify that what we are asked to mmap is proper.
-+ */
-+ if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) {
-+ pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n",
-+ __func__,
-+ resource->res_size,
-+ (unsigned int)(vma->vm_end - vma->vm_start));
-+
-+ ret = -EINVAL;
-+ goto error;
-+ }
-+
-+ /* Keep track of the tuple in the global resource list such that one
-+ * can do a mapping lookup for address/memory handle.
-+ */
-+ map = kzalloc(sizeof(*map), GFP_KERNEL);
-+ if (map == NULL) {
-+ pr_err("[%s]: failed to allocate global tracking resource\n",
-+ __func__);
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+
-+ map->res_pid = current->tgid;
-+ map->res_vc_hdl = resource->res_handle;
-+ map->res_usr_hdl = resource->res_guid;
-+ map->res_addr = (long unsigned int)vma->vm_start;
-+ map->resource = resource;
-+ map->vma = vma;
-+ vmcs_sm_add_map(sm_state, resource, map);
-+
-+ /* We are not actually mapping the pages, we just provide a fault
-+ ** handler to allow pages to be mapped when accessed
-+ */
-+ vma->vm_flags |=
-+ VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND;
-+ vma->vm_ops = &vcsm_vm_ops;
-+ vma->vm_private_data = map;
-+
-+ /* vm_pgoff is the first PFN of the mapped memory */
-+ vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF;
-+ vma->vm_pgoff += mm_vc_mem_phys_addr;
-+ vma->vm_pgoff >>= PAGE_SHIFT;
-+
-+ if ((resource->res_cached == VMCS_SM_CACHE_NONE) ||
-+ (resource->res_cached == VMCS_SM_CACHE_VC)) {
-+ /* Allocated non host cached memory, honour it.
-+ */
-+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+ }
-+
-+ pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n",
-+ __func__,
-+ resource, resource->res_guid, resource->lock_count,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start),
-+ resource->res_cached);
-+
-+ pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n",
-+ __func__, resource, resource->res_base_mem,
-+ resource->res_handle, resource->map_count,
-+ (unsigned int)vma->vm_start);
-+
-+ vcsm_vma_open(vma);
-+ resource->res_stats[MAP]++;
-+ vmcs_sm_release_resource(resource, 0);
-+ return 0;
-+
-+error:
-+ vmcs_sm_release_resource(resource, 0);
-+ resource->res_stats[MAP_FAIL]++;
-+ return ret;
-+}
-+
-+/* Allocate a shared memory handle and block.
-+*/
-+int vc_sm_ioctl_alloc(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_alloc *ioparam)
-+{
-+ int ret = 0;
-+ int status;
-+ struct SM_RESOURCE_T *resource;
-+ VC_SM_ALLOC_T alloc = { 0 };
-+ VC_SM_ALLOC_RESULT_T result = { 0 };
-+
-+ /* Setup our allocation parameters */
-+ alloc.type = ((ioparam->cached == VMCS_SM_CACHE_VC)
-+ || (ioparam->cached ==
-+ VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED :
-+ VC_SM_ALLOC_NON_CACHED;
-+ alloc.base_unit = ioparam->size;
-+ alloc.num_unit = ioparam->num;
-+ alloc.allocator = current->tgid;
-+ /* Align to kernel page size */
-+ alloc.alignement = 4096;
-+ /* Align the size to the kernel page size */
-+ alloc.base_unit =
-+ (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1);
-+ if (*ioparam->name) {
-+ memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1);
-+ } else {
-+ memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT,
-+ sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT));
-+ }
-+
-+ pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n",
-+ __func__, alloc.name, alloc.type, ioparam->size,
-+ alloc.base_unit, alloc.num_unit, alloc.alignement);
-+
-+ /* Allocate local resource to track this allocation.
-+ */
-+ resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+ if (!resource) {
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+ INIT_LIST_HEAD(&resource->map_list);
-+ resource->ref_count++;
-+ resource->pid = current->tgid;
-+
-+ /* Allocate the videocore resource.
-+ */
-+ status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result,
-+ &private->int_trans_id);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+ ret = -ERESTARTSYS;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_ALLOC;
-+ goto error;
-+ } else if (status != 0 || (status == 0 && result.res_mem == NULL)) {
-+ pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ ret = -ENOMEM;
-+ resource->res_stats[ALLOC_FAIL]++;
-+ goto error;
-+ }
-+
-+ /* Keep track of the resource we created.
-+ */
-+ resource->private = private;
-+ resource->res_handle = result.res_handle;
-+ resource->res_base_mem = result.res_mem;
-+ resource->res_size = alloc.base_unit * alloc.num_unit;
-+ resource->res_cached = ioparam->cached;
-+
-+ /* Kernel/user GUID. This global identifier is used for mmap'ing the
-+ * allocated region from user space, it is passed as the mmap'ing
-+ * offset, we use it to 'hide' the videocore handle/address.
-+ */
-+ mutex_lock(&sm_state->lock);
-+ resource->res_guid = ++sm_state->guid;
-+ mutex_unlock(&sm_state->lock);
-+ resource->res_guid <<= PAGE_SHIFT;
-+
-+ vmcs_sm_add_resource(private, resource);
-+
-+ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem, resource->res_size,
-+ resource->res_cached);
-+
-+ /* We're done */
-+ resource->res_stats[ALLOC]++;
-+ ioparam->handle = resource->res_guid;
-+ return 0;
-+
-+error:
-+ pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n",
-+ __func__, alloc.name, ret, alloc.type, ioparam->size,
-+ alloc.base_unit, alloc.num_unit, alloc.alignement);
-+ if (resource != NULL) {
-+ vc_sm_resource_deceased(resource, 1);
-+ kfree(resource);
-+ }
-+ return ret;
-+}
-+
-+/* Share an allocate memory handle and block.
-+*/
-+int vc_sm_ioctl_alloc_share(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_alloc_share *ioparam)
-+{
-+ struct SM_RESOURCE_T *resource, *shared_resource;
-+ int ret = 0;
-+
-+ pr_debug("[%s]: attempt to share resource %u\n", __func__,
-+ ioparam->handle);
-+
-+ shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle);
-+ if (shared_resource == NULL) {
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+
-+ /* Allocate local resource to track this allocation.
-+ */
-+ resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+ if (resource == NULL) {
-+ pr_err("[%s]: failed to allocate local tracking resource\n",
-+ __func__);
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+ INIT_LIST_HEAD(&resource->map_list);
-+ resource->ref_count++;
-+ resource->pid = current->tgid;
-+
-+ /* Keep track of the resource we created.
-+ */
-+ resource->private = private;
-+ resource->res_handle = shared_resource->res_handle;
-+ resource->res_base_mem = shared_resource->res_base_mem;
-+ resource->res_size = shared_resource->res_size;
-+ resource->res_cached = shared_resource->res_cached;
-+ resource->res_shared = shared_resource;
-+
-+ mutex_lock(&sm_state->lock);
-+ resource->res_guid = ++sm_state->guid;
-+ mutex_unlock(&sm_state->lock);
-+ resource->res_guid <<= PAGE_SHIFT;
-+
-+ vmcs_sm_add_resource(private, resource);
-+
-+ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem, resource->res_size,
-+ resource->res_cached);
-+
-+ /* We're done */
-+ resource->res_stats[ALLOC]++;
-+ ioparam->handle = resource->res_guid;
-+ ioparam->size = resource->res_size;
-+ return 0;
-+
-+error:
-+ pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle);
-+ if (shared_resource != NULL)
-+ vmcs_sm_release_resource(shared_resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Free a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_free(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_free *ioparam)
-+{
-+ struct SM_RESOURCE_T *resource =
-+ vmcs_sm_acquire_resource(private, ioparam->handle);
-+
-+ if (resource == NULL) {
-+ pr_err("[%s]: resource for guid %u does not exist\n", __func__,
-+ ioparam->handle);
-+ return -EINVAL;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n",
-+ __func__, current->tgid, resource->pid);
-+ vmcs_sm_release_resource(resource, 0);
-+ return -EPERM;
-+ }
-+
-+ vmcs_sm_release_resource(resource, 0);
-+ vmcs_sm_release_resource(resource, 0);
-+ return 0;
-+}
-+
-+/* Resize a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_resize(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_resize *ioparam)
-+{
-+ int ret = 0;
-+ int status;
-+ VC_SM_RESIZE_T resize;
-+ struct SM_RESOURCE_T *resource;
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+ if (!resource) {
-+ pr_err("[%s]: failed resource - guid %x\n",
-+ __func__, ioparam->handle);
-+ ret = -EFAULT;
-+ goto error;
-+ }
-+
-+ /* If the resource is locked, its reference count will be not NULL,
-+ ** in which case we will not be allowed to resize it anyways, so
-+ ** reject the attempt here.
-+ */
-+ if (resource->lock_count != 0) {
-+ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
-+ __func__, ioparam->handle, resource->lock_count);
-+ ret = -EFAULT;
-+ goto error;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n", __func__,
-+ current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ if (resource->map_count != 0) {
-+ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
-+ __func__, ioparam->handle, resource->map_count);
-+ ret = -EFAULT;
-+ goto error;
-+ }
-+
-+ resize.res_handle = resource->res_handle;
-+ resize.res_mem = resource->res_base_mem;
-+ resize.res_new_size = ioparam->new_size;
-+
-+ pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n",
-+ __func__, ioparam->handle, resize.res_handle, resize.res_mem);
-+
-+ /* Resize the videocore allocated resource.
-+ */
-+ status = vc_vchi_sm_resize(sm_state->sm_handle, &resize,
-+ &private->int_trans_id);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+ ret = -ERESTARTSYS;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_RESIZE;
-+ goto error;
-+ } else if (status != 0) {
-+ pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n",
-+ __func__, resize.res_handle, resource->res_size,
-+ resize.res_new_size);
-+
-+ /* Successfully resized, save the information and inform the user.
-+ */
-+ ioparam->old_size = resource->res_size;
-+ resource->res_size = resize.res_new_size;
-+
-+error:
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Lock a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_lock(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_lock_unlock *ioparam,
-+ int change_cache, enum vmcs_sm_cache_e cache_type,
-+ unsigned int vc_addr)
-+{
-+ int status;
-+ VC_SM_LOCK_UNLOCK_T lock;
-+ VC_SM_LOCK_RESULT_T result;
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+ struct sm_mmap *map, *map_tmp;
-+ long unsigned int phys_addr;
-+
-+ map = NULL;
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+ if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto error;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n", __func__,
-+ current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ lock.res_handle = resource->res_handle;
-+ lock.res_mem = resource->res_base_mem;
-+
-+ /* Take the lock and get the address to be mapped.
-+ */
-+ if (vc_addr == 0) {
-+ pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n",
-+ __func__, ioparam->handle, lock.res_handle,
-+ lock.res_mem);
-+
-+ /* Lock the videocore allocated resource.
-+ */
-+ status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result,
-+ &private->int_trans_id);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+ ret = -ERESTARTSYS;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_LOCK;
-+ goto error;
-+ } else if (status != 0 ||
-+ (status == 0 && result.res_mem == NULL)) {
-+ pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ ret = -EPERM;
-+ resource->res_stats[LOCK_FAIL]++;
-+ goto error;
-+ }
-+
-+ pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n",
-+ __func__, lock.res_handle, result.res_mem,
-+ lock.res_mem, resource->lock_count);
-+ }
-+ /* Lock assumed taken already, address to be mapped is known.
-+ */
-+ else
-+ resource->res_base_mem = (void *)vc_addr;
-+
-+ resource->res_stats[LOCK]++;
-+ resource->lock_count++;
-+
-+ /* Keep track of the new base memory allocation if it has changed.
-+ */
-+ if ((vc_addr == 0) &&
-+ (result.res_mem != NULL) &&
-+ (result.res_old_mem != NULL) &&
-+ (result.res_mem != result.res_old_mem)) {
-+ resource->res_base_mem = result.res_mem;
-+
-+ /* Kernel allocated resources.
-+ */
-+ if (resource->pid == 0) {
-+ if (!list_empty(&resource->map_list)) {
-+ list_for_each_entry_safe(map, map_tmp,
-+ &resource->map_list,
-+ resource_map_list) {
-+ if (map->res_addr) {
-+ iounmap((void *)map->res_addr);
-+ map->res_addr = 0;
-+
-+ vmcs_sm_remove_map(sm_state,
-+ map->resource,
-+ map);
-+ break;
-+ }
-+ }
-+ }
-+ }
-+ }
-+
-+ if (change_cache)
-+ resource->res_cached = cache_type;
-+
-+ if (resource->map_count) {
-+ ioparam->addr =
-+ vmcs_sm_usr_address_from_pid_and_usr_handle(
-+ current->tgid, ioparam->handle);
-+
-+ pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n",
-+ __func__, resource->map_count, private->pid,
-+ current->tgid, ioparam->handle, ioparam->addr);
-+ } else {
-+ /* Kernel allocated resources.
-+ */
-+ if (resource->pid == 0) {
-+ pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n",
-+ __func__, ioparam->handle, lock.res_handle);
-+
-+ ioparam->addr = 0;
-+
-+ map = kzalloc(sizeof(*map), GFP_KERNEL);
-+ if (map == NULL) {
-+ pr_err("[%s]: failed allocating tracker\n",
-+ __func__);
-+ ret = -ENOMEM;
-+ goto error;
-+ } else {
-+ phys_addr = (uint32_t)resource->res_base_mem &
-+ 0x3FFFFFFF;
-+ phys_addr += mm_vc_mem_phys_addr;
-+ if (resource->res_cached
-+ == VMCS_SM_CACHE_HOST) {
-+ ioparam->addr = (long unsigned int)
-+ /* TODO - make cached work */
-+ ioremap_nocache(phys_addr,
-+ resource->res_size);
-+
-+ pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n",
-+ __func__, ioparam->handle,
-+ lock.res_handle, ioparam->addr);
-+ } else {
-+ ioparam->addr = (long unsigned int)
-+ ioremap_nocache(phys_addr,
-+ resource->res_size);
-+
-+ pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n",
-+ __func__, ioparam->handle,
-+ lock.res_handle, ioparam->addr);
-+ }
-+
-+ map->res_pid = 0;
-+ map->res_vc_hdl = resource->res_handle;
-+ map->res_usr_hdl = resource->res_guid;
-+ map->res_addr = ioparam->addr;
-+ map->resource = resource;
-+ map->vma = NULL;
-+
-+ vmcs_sm_add_map(sm_state, resource, map);
-+ }
-+ } else
-+ ioparam->addr = 0;
-+ }
-+
-+error:
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Unlock a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_unlock(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_lock_unlock *ioparam,
-+ int flush, int wait_reply, int no_vc_unlock)
-+{
-+ int status;
-+ VC_SM_LOCK_UNLOCK_T unlock;
-+ struct sm_mmap *map, *map_tmp;
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+
-+ map = NULL;
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+ if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto error;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n",
-+ __func__, current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ unlock.res_handle = resource->res_handle;
-+ unlock.res_mem = resource->res_base_mem;
-+
-+ pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n",
-+ __func__, ioparam->handle, unlock.res_handle, unlock.res_mem);
-+
-+ /* User space allocated resources.
-+ */
-+ if (resource->pid) {
-+ /* Flush if requested */
-+ if (resource->res_cached && flush) {
-+ dma_addr_t phys_addr = 0;
-+ resource->res_stats[FLUSH]++;
-+
-+ phys_addr =
-+ (dma_addr_t)((uint32_t)resource->res_base_mem &
-+ 0x3FFFFFFF);
-+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+ /* L1 cache flush */
-+ down_read(&current->mm->mmap_sem);
-+ list_for_each_entry(map, &resource->map_list,
-+ resource_map_list) {
-+ if (map->vma) {
-+ unsigned long start;
-+ unsigned long end;
-+ start = map->vma->vm_start;
-+ end = map->vma->vm_end;
-+
-+ vcsm_vma_cache_clean_page_range(
-+ start, end);
-+ }
-+ }
-+ up_read(&current->mm->mmap_sem);
-+
-+ /* L2 cache flush */
-+ outer_clean_range(phys_addr,
-+ phys_addr +
-+ (size_t) resource->res_size);
-+ }
-+
-+ /* We need to zap all the vmas associated with this resource */
-+ if (resource->lock_count == 1) {
-+ down_read(&current->mm->mmap_sem);
-+ list_for_each_entry(map, &resource->map_list,
-+ resource_map_list) {
-+ if (map->vma) {
-+ zap_vma_ptes(map->vma,
-+ map->vma->vm_start,
-+ map->vma->vm_end -
-+ map->vma->vm_start);
-+ }
-+ }
-+ up_read(&current->mm->mmap_sem);
-+ }
-+ }
-+ /* Kernel allocated resources. */
-+ else {
-+ /* Global + Taken in this context */
-+ if (resource->ref_count == 2) {
-+ if (!list_empty(&resource->map_list)) {
-+ list_for_each_entry_safe(map, map_tmp,
-+ &resource->map_list,
-+ resource_map_list) {
-+ if (map->res_addr) {
-+ if (flush &&
-+ (resource->res_cached ==
-+ VMCS_SM_CACHE_HOST)) {
-+ long unsigned int
-+ phys_addr;
-+ phys_addr = (uint32_t)
-+ resource->res_base_mem & 0x3FFFFFFF;
-+ phys_addr +=
-+ mm_vc_mem_phys_addr;
-+
-+ /* L1 cache flush */
-+ dmac_flush_range((const
-+ void
-+ *)
-+ map->res_addr, (const void *)
-+ (map->res_addr + resource->res_size));
-+
-+ /* L2 cache flush */
-+ outer_clean_range
-+ (phys_addr,
-+ phys_addr +
-+ (size_t)
-+ resource->res_size);
-+ }
-+
-+ iounmap((void *)map->res_addr);
-+ map->res_addr = 0;
-+
-+ vmcs_sm_remove_map(sm_state,
-+ map->resource,
-+ map);
-+ break;
-+ }
-+ }
-+ }
-+ }
-+ }
-+
-+ if (resource->lock_count) {
-+ /* Bypass the videocore unlock.
-+ */
-+ if (no_vc_unlock)
-+ status = 0;
-+ /* Unlock the videocore allocated resource.
-+ */
-+ else {
-+ status =
-+ vc_vchi_sm_unlock(sm_state->sm_handle, &unlock,
-+ &private->int_trans_id,
-+ wait_reply);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+
-+ ret = -ERESTARTSYS;
-+ resource->res_stats[UNLOCK]--;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_UNLOCK;
-+ goto error;
-+ } else if (status != 0) {
-+ pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+
-+ ret = -EPERM;
-+ resource->res_stats[UNLOCK_FAIL]++;
-+ goto error;
-+ }
-+ }
-+
-+ resource->res_stats[UNLOCK]++;
-+ resource->lock_count--;
-+ }
-+
-+ pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n",
-+ __func__, unlock.res_handle, unlock.res_mem,
-+ resource->lock_count);
-+
-+error:
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Handle control from host. */
-+static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int ret = 0;
-+ unsigned int cmdnr = _IOC_NR(cmd);
-+ struct SM_PRIV_DATA_T *file_data =
-+ (struct SM_PRIV_DATA_T *)file->private_data;
-+ struct SM_RESOURCE_T *resource = NULL;
-+
-+ /* Validate we can work with this device. */
-+ if ((sm_state == NULL) || (file_data == NULL)) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr,
-+ current->tgid, file_data->pid);
-+
-+ /* Action is a re-post of a previously interrupted action? */
-+ if (file_data->restart_sys == -EINTR) {
-+ VC_SM_ACTION_CLEAN_T action_clean;
-+
-+ pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n",
-+ __func__, file_data->int_action,
-+ file_data->int_trans_id);
-+
-+ action_clean.res_action = file_data->int_action;
-+ action_clean.action_trans_id = file_data->int_trans_id;
-+
-+ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
-+
-+ file_data->restart_sys = 0;
-+ }
-+
-+ /* Now process the command.
-+ */
-+ switch (cmdnr) {
-+ /* New memory allocation.
-+ */
-+ case VMCS_SM_CMD_ALLOC:
-+ {
-+ struct vmcs_sm_ioctl_alloc ioparam;
-+
-+ /* Get the parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_alloc(file_data, &ioparam);
-+ if (!ret &&
-+ (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0)) {
-+ struct vmcs_sm_ioctl_free freeparam = {
-+ ioparam.handle
-+ };
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ vc_sm_ioctl_free(file_data, &freeparam);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Share existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_ALLOC_SHARE:
-+ {
-+ struct vmcs_sm_ioctl_alloc_share ioparam;
-+
-+ /* Get the parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_alloc_share(file_data, &ioparam);
-+
-+ /* Copy result back to user.
-+ */
-+ if (!ret
-+ && copy_to_user((void *)arg, &ioparam,
-+ sizeof(ioparam)) != 0) {
-+ struct vmcs_sm_ioctl_free freeparam = {
-+ ioparam.handle
-+ };
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ vc_sm_ioctl_free(file_data, &freeparam);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Lock (attempt to) *and* register a cache behavior change.
-+ */
-+ case VMCS_SM_CMD_LOCK_CACHE:
-+ {
-+ struct vmcs_sm_ioctl_lock_cache ioparam;
-+ struct vmcs_sm_ioctl_lock_unlock lock;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ lock.handle = ioparam.handle;
-+ ret =
-+ vc_sm_ioctl_lock(file_data, &lock, 1,
-+ ioparam.cached, 0);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Lock (attempt to) existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_LOCK:
-+ {
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0);
-+
-+ /* Copy result back to user.
-+ */
-+ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
-+ != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Unlock (attempt to) existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_UNLOCK:
-+ {
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Resize (attempt to) existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_RESIZE:
-+ {
-+ struct vmcs_sm_ioctl_resize ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_resize(file_data, &ioparam);
-+
-+ /* Copy result back to user.
-+ */
-+ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
-+ != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Terminate existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_FREE:
-+ {
-+ struct vmcs_sm_ioctl_free ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_free(file_data, &ioparam);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Walk allocation on videocore, information shows up in the
-+ ** videocore log.
-+ */
-+ case VMCS_SM_CMD_VC_WALK_ALLOC:
-+ {
-+ pr_debug("[%s]: invoking walk alloc\n", __func__);
-+
-+ if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0)
-+ pr_err("[%s]: failed to walk-alloc on videocore\n",
-+ __func__);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+/* Walk mapping table on host, information shows up in the
-+ ** kernel log.
-+ */
-+ case VMCS_SM_CMD_HOST_WALK_MAP:
-+ {
-+ /* Use pid of -1 to tell to walk the whole map. */
-+ vmcs_sm_host_walk_map_per_pid(-1);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Walk mapping table per process on host. */
-+ case VMCS_SM_CMD_HOST_WALK_PID_ALLOC:
-+ {
-+ struct vmcs_sm_ioctl_walk ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ vmcs_sm_host_walk_alloc(file_data);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Walk allocation per process on host. */
-+ case VMCS_SM_CMD_HOST_WALK_PID_MAP:
-+ {
-+ struct vmcs_sm_ioctl_walk ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ vmcs_sm_host_walk_map_per_pid(ioparam.pid);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Gets the size of the memory associated with a user handle. */
-+ case VMCS_SM_CMD_SIZE_USR_HANDLE:
-+ {
-+ struct vmcs_sm_ioctl_size ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource != NULL) {
-+ ioparam.size = resource->res_size;
-+ vmcs_sm_release_resource(resource, 0);
-+ } else {
-+ ioparam.size = 0;
-+ }
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Verify we are dealing with a valid resource. */
-+ case VMCS_SM_CMD_CHK_USR_HANDLE:
-+ {
-+ struct vmcs_sm_ioctl_chk ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource == NULL)
-+ ret = -EINVAL;
-+ /* If the resource is cacheable, return additional
-+ * information that may be needed to flush the cache.
-+ */
-+ else if ((resource->res_cached == VMCS_SM_CACHE_HOST) ||
-+ (resource->res_cached == VMCS_SM_CACHE_BOTH)) {
-+ ioparam.addr =
-+ vmcs_sm_usr_address_from_pid_and_usr_handle
-+ (current->tgid, ioparam.handle);
-+ ioparam.size = resource->res_size;
-+ ioparam.cache = resource->res_cached;
-+ } else {
-+ ioparam.addr = 0;
-+ ioparam.size = 0;
-+ ioparam.cache = resource->res_cached;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /*
-+ * Maps a user handle given the process and the virtual address.
-+ */
-+ case VMCS_SM_CMD_MAPPED_USR_HANDLE:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ioparam.handle =
-+ vmcs_sm_usr_handle_from_pid_and_address(
-+ ioparam.pid, ioparam.addr);
-+
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if ((resource != NULL)
-+ && ((resource->res_cached == VMCS_SM_CACHE_HOST)
-+ || (resource->res_cached ==
-+ VMCS_SM_CACHE_BOTH))) {
-+ ioparam.size = resource->res_size;
-+ } else {
-+ ioparam.size = 0;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /*
-+ * Maps a videocore handle given process and virtual address.
-+ */
-+ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address(
-+ ioparam.pid, ioparam.addr);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Maps a videocore handle given process and user handle. */
-+ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource != NULL) {
-+ ioparam.handle = resource->res_handle;
-+ vmcs_sm_release_resource(resource, 0);
-+ } else {
-+ ioparam.handle = 0;
-+ }
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /*
-+ * Maps a videocore address given process and videocore handle.
-+ */
-+ case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource != NULL) {
-+ ioparam.addr =
-+ (unsigned int)resource->res_base_mem;
-+ vmcs_sm_release_resource(resource, 0);
-+ } else {
-+ ioparam.addr = 0;
-+ }
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Maps a user address given process and vc handle.
-+ */
-+ case VMCS_SM_CMD_MAPPED_USR_ADDRESS:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /*
-+ * Return the address information from the mapping,
-+ * 0 (ie NULL) if it cannot locate the actual mapping.
-+ */
-+ ioparam.addr =
-+ vmcs_sm_usr_address_from_pid_and_usr_handle
-+ (ioparam.pid, ioparam.handle);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Flush the cache for a given mapping. */
-+ case VMCS_SM_CMD_FLUSH:
-+ {
-+ struct vmcs_sm_ioctl_cache ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+
-+ if ((resource != NULL) && resource->res_cached) {
-+ dma_addr_t phys_addr = 0;
-+
-+ resource->res_stats[FLUSH]++;
-+
-+ phys_addr =
-+ (dma_addr_t)((uint32_t)
-+ resource->res_base_mem &
-+ 0x3FFFFFFF);
-+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+ /* L1 cache flush */
-+ down_read(&current->mm->mmap_sem);
-+ vcsm_vma_cache_clean_page_range((unsigned long)
-+ ioparam.addr,
-+ (unsigned long)
-+ ioparam.addr +
-+ ioparam.size);
-+ up_read(&current->mm->mmap_sem);
-+
-+ /* L2 cache flush */
-+ outer_clean_range(phys_addr,
-+ phys_addr +
-+ (size_t) ioparam.size);
-+ } else if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Invalidate the cache for a given mapping. */
-+ case VMCS_SM_CMD_INVALID:
-+ {
-+ struct vmcs_sm_ioctl_cache ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+
-+ if ((resource != NULL) && resource->res_cached) {
-+ dma_addr_t phys_addr = 0;
-+
-+ resource->res_stats[INVALID]++;
-+
-+ phys_addr =
-+ (dma_addr_t)((uint32_t)
-+ resource->res_base_mem &
-+ 0x3FFFFFFF);
-+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+ /* L2 cache invalidate */
-+ outer_inv_range(phys_addr,
-+ phys_addr +
-+ (size_t) ioparam.size);
-+
-+ /* L1 cache invalidate */
-+ down_read(&current->mm->mmap_sem);
-+ vcsm_vma_cache_clean_page_range((unsigned long)
-+ ioparam.addr,
-+ (unsigned long)
-+ ioparam.addr +
-+ ioparam.size);
-+ up_read(&current->mm->mmap_sem);
-+ } else if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ default:
-+ {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ break;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/* Device operations that we managed in this driver.
-+*/
-+static const struct file_operations vmcs_sm_ops = {
-+ .owner = THIS_MODULE,
-+ .unlocked_ioctl = vc_sm_ioctl,
-+ .open = vc_sm_open,
-+ .release = vc_sm_release,
-+ .mmap = vc_sm_mmap,
-+};
-+
-+/* Creation of device.
-+*/
-+static int vc_sm_create_sharedmemory(void)
-+{
-+ int ret;
-+
-+ if (sm_state == NULL) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ /* Create a device class for creating dev nodes.
-+ */
-+ sm_state->sm_class = class_create(THIS_MODULE, "vc-sm");
-+ if (IS_ERR(sm_state->sm_class)) {
-+ pr_err("[%s]: unable to create device class\n", __func__);
-+ ret = PTR_ERR(sm_state->sm_class);
-+ goto out;
-+ }
-+
-+ /* Create a character driver.
-+ */
-+ ret = alloc_chrdev_region(&sm_state->sm_devid,
-+ DEVICE_MINOR, 1, DEVICE_NAME);
-+ if (ret != 0) {
-+ pr_err("[%s]: unable to allocate device number\n", __func__);
-+ goto out_dev_class_destroy;
-+ }
-+
-+ cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops);
-+ ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1);
-+ if (ret != 0) {
-+ pr_err("[%s]: unable to register device\n", __func__);
-+ goto out_chrdev_unreg;
-+ }
-+
-+ /* Create a device node.
-+ */
-+ sm_state->sm_dev = device_create(sm_state->sm_class,
-+ NULL,
-+ MKDEV(MAJOR(sm_state->sm_devid),
-+ DEVICE_MINOR), NULL,
-+ DEVICE_NAME);
-+ if (IS_ERR(sm_state->sm_dev)) {
-+ pr_err("[%s]: unable to create device node\n", __func__);
-+ ret = PTR_ERR(sm_state->sm_dev);
-+ goto out_chrdev_del;
-+ }
-+
-+ goto out;
-+
-+out_chrdev_del:
-+ cdev_del(&sm_state->sm_cdev);
-+out_chrdev_unreg:
-+ unregister_chrdev_region(sm_state->sm_devid, 1);
-+out_dev_class_destroy:
-+ class_destroy(sm_state->sm_class);
-+ sm_state->sm_class = NULL;
-+out:
-+ return ret;
-+}
-+
-+/* Termination of the device.
-+*/
-+static int vc_sm_remove_sharedmemory(void)
-+{
-+ int ret;
-+
-+ if (sm_state == NULL) {
-+ /* Nothing to do.
-+ */
-+ ret = 0;
-+ goto out;
-+ }
-+
-+ /* Remove the sharedmemory character driver.
-+ */
-+ cdev_del(&sm_state->sm_cdev);
-+
-+ /* Unregister region.
-+ */
-+ unregister_chrdev_region(sm_state->sm_devid, 1);
-+
-+ ret = 0;
-+ goto out;
-+
-+out:
-+ return ret;
-+}
-+
-+/* Videocore connected. */
-+static void vc_sm_connected_init(void)
-+{
-+ int ret;
-+ VCHI_INSTANCE_T vchi_instance;
-+ VCHI_CONNECTION_T *vchi_connection = NULL;
-+
-+ pr_info("[%s]: start\n", __func__);
-+
-+ /* Allocate memory for the state structure.
-+ */
-+ sm_state = kzalloc(sizeof(struct SM_STATE_T), GFP_KERNEL);
-+ if (sm_state == NULL) {
-+ pr_err("[%s]: failed to allocate memory\n", __func__);
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ mutex_init(&sm_state->lock);
-+ mutex_init(&sm_state->map_lock);
-+
-+ /* Initialize and create a VCHI connection for the shared memory service
-+ ** running on videocore.
-+ */
-+ ret = vchi_initialise(&vchi_instance);
-+ if (ret != 0) {
-+ pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+
-+ ret = vchi_connect(NULL, 0, vchi_instance);
-+ if (ret != 0) {
-+ pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+
-+ /* Initialize an instance of the shared memory service. */
-+ sm_state->sm_handle =
-+ vc_vchi_sm_init(vchi_instance, &vchi_connection, 1);
-+ if (sm_state->sm_handle == NULL) {
-+ pr_err("[%s]: failed to initialize shared memory service\n",
-+ __func__);
-+
-+ ret = -EPERM;
-+ goto err_free_mem;
-+ }
-+
-+ /* Create a debug fs directory entry (root). */
-+ sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL);
-+ if (!sm_state->dir_root) {
-+ pr_err("[%s]: failed to create \'%s\' directory entry\n",
-+ __func__, VC_SM_DIR_ROOT_NAME);
-+
-+ ret = -EPERM;
-+ goto err_stop_sm_service;
-+ }
-+
-+ sm_state->dir_state.show = &vc_sm_global_state_show;
-+ sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE,
-+ S_IRUGO, sm_state->dir_root, &sm_state->dir_state,
-+ &vc_sm_debug_fs_fops);
-+
-+ sm_state->dir_stats.show = &vc_sm_global_statistics_show;
-+ sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS,
-+ S_IRUGO, sm_state->dir_root, &sm_state->dir_stats,
-+ &vc_sm_debug_fs_fops);
-+
-+ /* Create the proc entry children. */
-+ sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME,
-+ sm_state->dir_root);
-+
-+ /* Create a shared memory device. */
-+ ret = vc_sm_create_sharedmemory();
-+ if (ret != 0) {
-+ pr_err("[%s]: failed to create shared memory device\n",
-+ __func__);
-+ goto err_remove_debugfs;
-+ }
-+
-+ INIT_LIST_HEAD(&sm_state->map_list);
-+ INIT_LIST_HEAD(&sm_state->resource_list);
-+
-+ sm_state->data_knl = vc_sm_create_priv_data(0);
-+ if (sm_state->data_knl == NULL) {
-+ pr_err("[%s]: failed to create kernel private data tracker\n",
-+ __func__);
-+ goto err_remove_shared_memory;
-+ }
-+
-+ /* Done!
-+ */
-+ sm_inited = 1;
-+ goto out;
-+
-+err_remove_shared_memory:
-+ vc_sm_remove_sharedmemory();
-+err_remove_debugfs:
-+ debugfs_remove_recursive(sm_state->dir_root);
-+err_stop_sm_service:
-+ vc_vchi_sm_stop(&sm_state->sm_handle);
-+err_free_mem:
-+ kfree(sm_state);
-+out:
-+ pr_info("[%s]: end - returning %d\n", __func__, ret);
-+}
-+
-+/* Driver loading. */
-+static int __init vc_sm_init(void)
-+{
-+ pr_info("vc-sm: Videocore shared memory driver\n");
-+ vchiq_add_connected_callback(vc_sm_connected_init);
-+ return 0;
-+}
-+
-+/* Driver unloading. */
-+static void __exit vc_sm_exit(void)
-+{
-+ pr_debug("[%s]: start\n", __func__);
-+ if (sm_inited) {
-+ /* Remove shared memory device.
-+ */
-+ vc_sm_remove_sharedmemory();
-+
-+ /* Remove all proc entries.
-+ */
-+ debugfs_remove_recursive(sm_state->dir_root);
-+
-+ /* Stop the videocore shared memory service.
-+ */
-+ vc_vchi_sm_stop(&sm_state->sm_handle);
-+
-+ /* Free the memory for the state structure.
-+ */
-+ mutex_destroy(&(sm_state->map_lock));
-+ kfree(sm_state);
-+ }
-+
-+ pr_debug("[%s]: end\n", __func__);
-+}
-+
-+#if defined(__KERNEL__)
-+/* Allocate a shared memory handle and block. */
-+int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle)
-+{
-+ struct vmcs_sm_ioctl_alloc ioparam = { 0 };
-+ int ret;
-+ struct SM_RESOURCE_T *resource;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || alloc == NULL || handle == NULL) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ ioparam.size = alloc->base_unit;
-+ ioparam.num = alloc->num_unit;
-+ ioparam.cached =
-+ alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0;
-+
-+ ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam);
-+
-+ if (ret == 0) {
-+ resource =
-+ vmcs_sm_acquire_resource(sm_state->data_knl,
-+ ioparam.handle);
-+ if (resource) {
-+ resource->pid = 0;
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ /* Assign valid handle at this time.
-+ */
-+ *handle = ioparam.handle;
-+ } else {
-+ ret = -ENOMEM;
-+ }
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_alloc);
-+
-+/* Get an internal resource handle mapped from the external one.
-+*/
-+int vc_sm_int_handle(int handle)
-+{
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return 0;
-+ }
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle);
-+ if (resource) {
-+ ret = resource->res_handle;
-+ vmcs_sm_release_resource(resource, 0);
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_int_handle);
-+
-+/* Free a previously allocated shared memory handle and block.
-+*/
-+int vc_sm_free(int handle)
-+{
-+ struct vmcs_sm_ioctl_free ioparam = { handle };
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ return vc_sm_ioctl_free(sm_state->data_knl, &ioparam);
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_free);
-+
-+/* Lock a memory handle for use by kernel.
-+*/
-+int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data)
-+{
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+ int ret;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0 || data == NULL) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ *data = 0;
-+
-+ ioparam.handle = handle;
-+ ret = vc_sm_ioctl_lock(sm_state->data_knl,
-+ &ioparam,
-+ 1,
-+ ((mode ==
-+ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
-+ VMCS_SM_CACHE_NONE), 0);
-+
-+ *data = ioparam.addr;
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_lock);
-+
-+/* Unlock a memory handle in use by kernel.
-+*/
-+int vc_sm_unlock(int handle, int flush, int no_vc_unlock)
-+{
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ ioparam.handle = handle;
-+ return vc_sm_ioctl_unlock(sm_state->data_knl,
-+ &ioparam, flush, 0, no_vc_unlock);
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_unlock);
-+
-+/* Map a shared memory region for use by kernel.
-+*/
-+int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data)
-+{
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+ int ret;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ *data = 0;
-+
-+ ioparam.handle = handle;
-+ ret = vc_sm_ioctl_lock(sm_state->data_knl,
-+ &ioparam,
-+ 1,
-+ ((mode ==
-+ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
-+ VMCS_SM_CACHE_NONE), sm_addr);
-+
-+ *data = ioparam.addr;
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_map);
-+#endif
-+
-+late_initcall(vc_sm_init);
-+module_exit(vc_sm_exit);
-+
-+MODULE_AUTHOR("Broadcom");
-+MODULE_DESCRIPTION("VideoCore SharedMemory Driver");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/drivers/char/hw_random/bcm2708-rng.c linux-rpi/drivers/char/hw_random/bcm2708-rng.c
---- linux-3.12.38/drivers/char/hw_random/bcm2708-rng.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/char/hw_random/bcm2708-rng.c 2015-03-10 17:26:50.166216694 +0100
-@@ -0,0 +1,117 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/hw_random.h>
-+#include <linux/printk.h>
-+
-+#include <asm/io.h>
-+#include <mach/hardware.h>
-+#include <mach/platform.h>
-+
-+#define RNG_CTRL (0x0)
-+#define RNG_STATUS (0x4)
-+#define RNG_DATA (0x8)
-+#define RNG_FF_THRESHOLD (0xc)
-+
-+/* enable rng */
-+#define RNG_RBGEN 0x1
-+/* double speed, less random mode */
-+#define RNG_RBG2X 0x2
-+
-+/* the initial numbers generated are "less random" so will be discarded */
-+#define RNG_WARMUP_COUNT 0x40000
-+
-+static int bcm2708_rng_data_read(struct hwrng *rng, u32 *buffer)
-+{
-+ void __iomem *rng_base = (void __iomem *)rng->priv;
-+ unsigned words;
-+ /* wait for a random number to be in fifo */
-+ do {
-+ words = __raw_readl(rng_base + RNG_STATUS)>>24;
-+ }
-+ while (words == 0);
-+ /* read the random number */
-+ *buffer = __raw_readl(rng_base + RNG_DATA);
-+ return 4;
-+}
-+
-+static struct hwrng bcm2708_rng_ops = {
-+ .name = "bcm2708",
-+ .data_read = bcm2708_rng_data_read,
-+};
-+
-+static int __init bcm2708_rng_init(void)
-+{
-+ void __iomem *rng_base;
-+ int err;
-+
-+ /* map peripheral */
-+ rng_base = ioremap(RNG_BASE, 0x10);
-+ pr_info("bcm2708_rng_init=%p\n", rng_base);
-+ if (!rng_base) {
-+ pr_err("bcm2708_rng_init failed to ioremap\n");
-+ return -ENOMEM;
-+ }
-+ bcm2708_rng_ops.priv = (unsigned long)rng_base;
-+ /* register driver */
-+ err = hwrng_register(&bcm2708_rng_ops);
-+ if (err) {
-+ pr_err("bcm2708_rng_init hwrng_register()=%d\n", err);
-+ iounmap(rng_base);
-+ } else {
-+ /* set warm-up count & enable */
-+ __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS);
-+ __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL);
-+ }
-+ return err;
-+}
-+
-+static void __exit bcm2708_rng_exit(void)
-+{
-+ void __iomem *rng_base = (void __iomem *)bcm2708_rng_ops.priv;
-+ pr_info("bcm2708_rng_exit\n");
-+ /* disable rng hardware */
-+ __raw_writel(0, rng_base + RNG_CTRL);
-+ /* unregister driver */
-+ hwrng_unregister(&bcm2708_rng_ops);
-+ iounmap(rng_base);
-+}
-+
-+module_init(bcm2708_rng_init);
-+module_exit(bcm2708_rng_exit);
-+
-+MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver");
-+MODULE_LICENSE("GPL and additional rights");
-diff -Nur linux-3.12.38/drivers/char/hw_random/Kconfig linux-rpi/drivers/char/hw_random/Kconfig
---- linux-3.12.38/drivers/char/hw_random/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/char/hw_random/Kconfig 2015-03-10 17:26:50.166216694 +0100
-@@ -314,3 +314,14 @@
- module will be called tpm-rng.
-
- If unsure, say Y.
-+
-+config HW_RANDOM_BCM2708
-+ tristate "BCM2708 generic true random number generator support"
-+ depends on HW_RANDOM && ARCH_BCM2708
-+ ---help---
-+ This driver provides the kernel-side support for the BCM2708 hardware.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called bcm2708-rng.
-+
-+ If unsure, say N.
-diff -Nur linux-3.12.38/drivers/char/hw_random/Makefile linux-rpi/drivers/char/hw_random/Makefile
---- linux-3.12.38/drivers/char/hw_random/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/char/hw_random/Makefile 2015-03-10 17:26:50.166216694 +0100
-@@ -27,3 +27,4 @@
- obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-rng.o
- obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
- obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
-+obj-$(CONFIG_HW_RANDOM_BCM2708) += bcm2708-rng.o
-diff -Nur linux-3.12.38/drivers/char/Kconfig linux-rpi/drivers/char/Kconfig
---- linux-3.12.38/drivers/char/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/char/Kconfig 2015-03-10 17:26:50.162216694 +0100
-@@ -574,6 +574,8 @@
-
- source "drivers/s390/char/Kconfig"
-
-+source "drivers/char/broadcom/Kconfig"
-+
- config MSM_SMD_PKT
- bool "Enable device interface for some SMD packet ports"
- default n
-diff -Nur linux-3.12.38/drivers/char/Makefile linux-rpi/drivers/char/Makefile
---- linux-3.12.38/drivers/char/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/char/Makefile 2015-03-10 17:26:50.162216694 +0100
-@@ -62,3 +62,5 @@
- js-rtc-y = rtc.o
-
- obj-$(CONFIG_TILE_SROM) += tile-srom.o
-+
-+obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/
-diff -Nur linux-3.12.38/drivers/clocksource/exynos_mct.c linux-rpi/drivers/clocksource/exynos_mct.c
---- linux-3.12.38/drivers/clocksource/exynos_mct.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/clocksource/exynos_mct.c 2015-03-10 17:26:50.178216694 +0100
-@@ -94,8 +94,8 @@
- __raw_writel(value, reg_base + offset);
-
- if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
-- stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
-- switch (offset & ~EXYNOS4_MCT_L_MASK) {
-+ stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
-+ switch (offset & EXYNOS4_MCT_L_MASK) {
- case MCT_L_TCON_OFFSET:
- mask = 1 << 3; /* L_TCON write status */
- break;
-diff -Nur linux-3.12.38/drivers/cpufreq/bcm2835-cpufreq.c linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c
---- linux-3.12.38/drivers/cpufreq/bcm2835-cpufreq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c 2015-03-10 17:26:50.182216694 +0100
-@@ -0,0 +1,239 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+/*****************************************************************************
-+* FILENAME: bcm2835-cpufreq.h
-+* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM
-+* processor. Messages are sent to Videocore either setting or requesting the
-+* frequency of the ARM in order to match an appropiate frequency to the current
-+* usage of the processor. The policy which selects the frequency to use is
-+* defined in the kernel .config file, but can be changed during runtime.
-+*****************************************************************************/
-+
-+/* ---------- INCLUDES ---------- */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <mach/vcio.h>
-+
-+/* ---------- DEFINES ---------- */
-+/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */
-+#define MODULE_NAME "bcm2835-cpufreq"
-+
-+#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */
-+
-+/* debug printk macros */
-+#ifdef CPUFREQ_DEBUG_ENABLE
-+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__)
-+
-+/* tag part of the message */
-+struct vc_msg_tag {
-+ uint32_t tag_id; /* the message id */
-+ uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */
-+ uint32_t data_size; /* amount of data being sent or received */
-+ uint32_t dev_id; /* the ID of the clock/voltage to get or set */
-+ uint32_t val; /* the value (e.g. rate (in Hz)) to set */
-+};
-+
-+/* message structure to be sent to videocore */
-+struct vc_msg {
-+ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */
-+ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */
-+ struct vc_msg_tag tag; /* the tag structure above to make */
-+ uint32_t end_tag; /* an end identifier, should be set to NULL */
-+};
-+
-+/* ---------- GLOBALS ---------- */
-+static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */
-+
-+/*
-+ ===============================================
-+ clk_rate either gets or sets the clock rates.
-+ ===============================================
-+*/
-+static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate)
-+{
-+ int s, actual_rate=0;
-+ struct vc_msg msg;
-+
-+ /* wipe all previous message data */
-+ memset(&msg, 0, sizeof msg);
-+
-+ msg.msg_size = sizeof msg;
-+
-+ msg.tag.tag_id = VCMSG_SET_CLOCK_RATE;
-+ msg.tag.buffer_size = 8;
-+ msg.tag.data_size = 8; /* we're sending the clock ID and the new rates which is a total of 2 words */
-+ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK;
-+ msg.tag.val = arm_rate * 1000;
-+
-+ /* send the message */
-+ s = bcm_mailbox_property(&msg, sizeof msg);
-+
-+ /* check if it was all ok and return the rate in KHz */
-+ if (s == 0 && (msg.request_code & 0x80000000))
-+ actual_rate = msg.tag.val/1000;
-+
-+ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, actual_rate);
-+ return actual_rate;
-+}
-+
-+static uint32_t bcm2835_cpufreq_get_clock(int tag)
-+{
-+ int s;
-+ int arm_rate = 0;
-+ struct vc_msg msg;
-+
-+ /* wipe all previous message data */
-+ memset(&msg, 0, sizeof msg);
-+
-+ msg.msg_size = sizeof msg;
-+ msg.tag.tag_id = tag;
-+ msg.tag.buffer_size = 8;
-+ msg.tag.data_size = 4; /* we're just sending the clock ID which is one word long */
-+ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK;
-+
-+ /* send the message */
-+ s = bcm_mailbox_property(&msg, sizeof msg);
-+
-+ /* check if it was all ok and return the rate in KHz */
-+ if (s == 0 && (msg.request_code & 0x80000000))
-+ arm_rate = msg.tag.val/1000;
-+
-+ print_debug("%s frequency = %d\n",
-+ tag == VCMSG_GET_CLOCK_RATE ? "Current":
-+ tag == VCMSG_GET_MIN_CLOCK ? "Min":
-+ tag == VCMSG_GET_MAX_CLOCK ? "Max":
-+ "Unexpected", arm_rate);
-+
-+ return arm_rate;
-+}
-+
-+/*
-+ ====================================================
-+ Module Initialisation registers the cpufreq driver
-+ ====================================================
-+*/
-+static int __init bcm2835_cpufreq_module_init(void)
-+{
-+ print_debug("IN\n");
-+ return cpufreq_register_driver(&bcm2835_cpufreq_driver);
-+}
-+
-+/*
-+ =============
-+ Module exit
-+ =============
-+*/
-+static void __exit bcm2835_cpufreq_module_exit(void)
-+{
-+ print_debug("IN\n");
-+ cpufreq_unregister_driver(&bcm2835_cpufreq_driver);
-+ return;
-+}
-+
-+/*
-+ ==============================================================
-+ Initialisation function sets up the CPU policy for first use
-+ ==============================================================
-+*/
-+static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy)
-+{
-+ /* measured value of how long it takes to change frequency */
-+ policy->cpuinfo.transition_latency = 355000; /* ns */
-+
-+ /* now find out what the maximum and minimum frequencies are */
-+ policy->min = policy->cpuinfo.min_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK);
-+ policy->max = policy->cpuinfo.max_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK);
-+ policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE);
-+
-+ print_info("min=%d max=%d cur=%d\n", policy->min, policy->max, policy->cur);
-+ return 0;
-+}
-+
-+/*
-+ =================================================================================
-+ Target function chooses the most appropriate frequency from the table to enable
-+ =================================================================================
-+*/
-+
-+static int bcm2835_cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation)
-+{
-+ unsigned int target = target_freq;
-+#ifdef CPUFREQ_DEBUG_ENABLE
-+ unsigned int cur = policy->cur;
-+#endif
-+ print_debug("%s: min=%d max=%d cur=%d target=%d\n",policy->governor->name,policy->min,policy->max,policy->cur,target_freq);
-+
-+ /* if we are above min and using ondemand, then just use max */
-+ if (strcmp("ondemand", policy->governor->name)==0 && target > policy->min)
-+ target = policy->max;
-+ /* if the frequency is the same, just quit */
-+ if (target == policy->cur)
-+ return 0;
-+
-+ /* otherwise were good to set the clock frequency */
-+ policy->cur = bcm2835_cpufreq_set_clock(policy->cur, target);
-+
-+ if (!policy->cur)
-+ {
-+ print_err("Error occurred setting a new frequency (%d)!\n", target);
-+ policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE);
-+ return -EINVAL;
-+ }
-+ print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)\n", cur, policy->cur, policy->min, policy->max, target_freq, target);
-+ return 0;
-+}
-+
-+static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu)
-+{
-+ unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE);
-+ print_debug("cpu=%d\n", actual_rate);
-+ return actual_rate;
-+}
-+
-+/*
-+ =================================================================================
-+ Verify ensures that when a policy is changed, it is suitable for the CPU to use
-+ =================================================================================
-+*/
-+
-+static int bcm2835_cpufreq_driver_verify(struct cpufreq_policy *policy)
-+{
-+ print_info("switching to governor %s\n", policy->governor->name);
-+ return 0;
-+}
-+
-+
-+/* the CPUFreq driver */
-+static struct cpufreq_driver bcm2835_cpufreq_driver = {
-+ .name = "BCM2835 CPUFreq",
-+ .init = bcm2835_cpufreq_driver_init,
-+ .verify = bcm2835_cpufreq_driver_verify,
-+ .target = bcm2835_cpufreq_driver_target,
-+ .get = bcm2835_cpufreq_driver_get
-+};
-+
-+MODULE_AUTHOR("Dorian Peake and Dom Cobley");
-+MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip");
-+MODULE_LICENSE("GPL");
-+
-+module_init(bcm2835_cpufreq_module_init);
-+module_exit(bcm2835_cpufreq_module_exit);
-diff -Nur linux-3.12.38/drivers/cpufreq/Kconfig.arm linux-rpi/drivers/cpufreq/Kconfig.arm
---- linux-3.12.38/drivers/cpufreq/Kconfig.arm 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/cpufreq/Kconfig.arm 2015-03-10 17:26:50.182216694 +0100
-@@ -228,6 +228,14 @@
- help
- This adds the CPUFreq driver support for SPEAr SOCs.
-
-+config ARM_BCM2835_CPUFREQ
-+ bool "BCM2835 Driver"
-+ default y
-+ help
-+ This adds the CPUFreq driver for BCM2835
-+
-+ If in doubt, say N.
-+
- config ARM_TEGRA_CPUFREQ
- bool "TEGRA CPUFreq support"
- depends on ARCH_TEGRA
-diff -Nur linux-3.12.38/drivers/cpufreq/Makefile linux-rpi/drivers/cpufreq/Makefile
---- linux-3.12.38/drivers/cpufreq/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/cpufreq/Makefile 2015-03-10 17:26:50.182216694 +0100
-@@ -76,6 +76,7 @@
- obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o
- obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
- obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
-+obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o
-
- ##################################################################################
-diff -Nur linux-3.12.38/drivers/crypto/padlock-aes.c linux-rpi/drivers/crypto/padlock-aes.c
---- linux-3.12.38/drivers/crypto/padlock-aes.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/crypto/padlock-aes.c 2015-03-10 17:26:50.190216694 +0100
-@@ -563,4 +563,4 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Michal Ludvig");
-
--MODULE_ALIAS_CRYPTO("aes");
-+MODULE_ALIAS("aes");
-diff -Nur linux-3.12.38/drivers/crypto/padlock-sha.c linux-rpi/drivers/crypto/padlock-sha.c
---- linux-3.12.38/drivers/crypto/padlock-sha.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/crypto/padlock-sha.c 2015-03-10 17:26:50.190216694 +0100
-@@ -593,7 +593,7 @@
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Michal Ludvig");
-
--MODULE_ALIAS_CRYPTO("sha1-all");
--MODULE_ALIAS_CRYPTO("sha256-all");
--MODULE_ALIAS_CRYPTO("sha1-padlock");
--MODULE_ALIAS_CRYPTO("sha256-padlock");
-+MODULE_ALIAS("sha1-all");
-+MODULE_ALIAS("sha256-all");
-+MODULE_ALIAS("sha1-padlock");
-+MODULE_ALIAS("sha256-padlock");
-diff -Nur linux-3.12.38/drivers/crypto/ux500/cryp/cryp_core.c linux-rpi/drivers/crypto/ux500/cryp/cryp_core.c
---- linux-3.12.38/drivers/crypto/ux500/cryp/cryp_core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/crypto/ux500/cryp/cryp_core.c 2015-03-10 17:26:50.194216694 +0100
-@@ -1810,7 +1810,7 @@
- module_param(cryp_mode, int, 0);
-
- MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 CRYP crypto engine.");
--MODULE_ALIAS_CRYPTO("aes-all");
--MODULE_ALIAS_CRYPTO("des-all");
-+MODULE_ALIAS("aes-all");
-+MODULE_ALIAS("des-all");
-
- MODULE_LICENSE("GPL");
-diff -Nur linux-3.12.38/drivers/crypto/ux500/hash/hash_core.c linux-rpi/drivers/crypto/ux500/hash/hash_core.c
---- linux-3.12.38/drivers/crypto/ux500/hash/hash_core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/crypto/ux500/hash/hash_core.c 2015-03-10 17:26:50.194216694 +0100
-@@ -1995,7 +1995,7 @@
- MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
- MODULE_LICENSE("GPL");
-
--MODULE_ALIAS_CRYPTO("sha1-all");
--MODULE_ALIAS_CRYPTO("sha256-all");
--MODULE_ALIAS_CRYPTO("hmac-sha1-all");
--MODULE_ALIAS_CRYPTO("hmac-sha256-all");
-+MODULE_ALIAS("sha1-all");
-+MODULE_ALIAS("sha256-all");
-+MODULE_ALIAS("hmac-sha1-all");
-+MODULE_ALIAS("hmac-sha256-all");
-diff -Nur linux-3.12.38/drivers/dma/bcm2708-dmaengine.c linux-rpi/drivers/dma/bcm2708-dmaengine.c
---- linux-3.12.38/drivers/dma/bcm2708-dmaengine.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/dma/bcm2708-dmaengine.c 2015-03-10 17:26:50.194216694 +0100
-@@ -0,0 +1,1052 @@
-+/*
-+ * BCM2835 DMA engine support
-+ *
-+ * This driver supports cyclic and scatter/gather DMA transfers.
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Gellert Weisz <gellert@raspberrypi.org>
-+ * Copyright 2013-2014
-+ *
-+ * Based on
-+ * OMAP DMAengine support by Russell King
-+ *
-+ * BCM2708 DMA Driver
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * Raspberry Pi PCM I2S ALSA Driver
-+ * Copyright (c) by Phil Poole 2013
-+ *
-+ * MARVELL MMP Peripheral DMA Driver
-+ * Copyright 2012 Marvell International Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/spinlock.h>
-+
-+#ifndef CONFIG_OF
-+
-+/* dma manager */
-+#include <mach/dma.h>
-+
-+#define DMA_COMPLETE DMA_SUCCESS
-+
-+#endif
-+
-+#include <linux/of.h>
-+#include <linux/of_dma.h>
-+
-+#include "virt-dma.h"
-+
-+
-+struct bcm2835_dmadev {
-+ struct dma_device ddev;
-+ spinlock_t lock;
-+ void __iomem *base;
-+ struct device_dma_parameters dma_parms;
-+};
-+
-+struct bcm2835_dma_cb {
-+ uint32_t info;
-+ uint32_t src;
-+ uint32_t dst;
-+ uint32_t length;
-+ uint32_t stride;
-+ uint32_t next;
-+ uint32_t pad[2];
-+};
-+
-+struct bcm2835_chan {
-+ struct virt_dma_chan vc;
-+ struct list_head node;
-+
-+ struct dma_slave_config cfg;
-+ bool cyclic;
-+
-+ int ch;
-+ struct bcm2835_desc *desc;
-+
-+ void __iomem *chan_base;
-+ int irq_number;
-+
-+ unsigned int dreq;
-+};
-+
-+struct bcm2835_desc {
-+ struct virt_dma_desc vd;
-+ enum dma_transfer_direction dir;
-+
-+ unsigned int control_block_size;
-+ struct bcm2835_dma_cb *control_block_base;
-+ dma_addr_t control_block_base_phys;
-+
-+ unsigned int frames;
-+ size_t size;
-+};
-+
-+#define BCM2835_DMA_CS 0x00
-+#define BCM2835_DMA_ADDR 0x04
-+#define BCM2835_DMA_SOURCE_AD 0x0c
-+#define BCM2835_DMA_DEST_AD 0x10
-+#define BCM2835_DMA_NEXTCB 0x1C
-+
-+/* DMA CS Control and Status bits */
-+#define BCM2835_DMA_ACTIVE BIT(0)
-+#define BCM2835_DMA_INT BIT(2)
-+#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
-+#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
-+#define BCM2835_DMA_ERR BIT(8)
-+#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
-+#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
-+
-+#define BCM2835_DMA_INT_EN BIT(0)
-+#define BCM2835_DMA_WAIT_RESP BIT(3)
-+#define BCM2835_DMA_D_INC BIT(4)
-+#define BCM2835_DMA_D_WIDTH BIT(5)
-+#define BCM2835_DMA_D_DREQ BIT(6)
-+#define BCM2835_DMA_S_INC BIT(8)
-+#define BCM2835_DMA_S_WIDTH BIT(9)
-+#define BCM2835_DMA_S_DREQ BIT(10)
-+
-+#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
-+#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21)
-+
-+#define SDHCI_BCM_DMA_WAITS 20 /* delays slowing DMA transfers: 0-31 */
-+
-+#define BCM2835_DMA_DATA_TYPE_S8 1
-+#define BCM2835_DMA_DATA_TYPE_S16 2
-+#define BCM2835_DMA_DATA_TYPE_S32 4
-+#define BCM2835_DMA_DATA_TYPE_S128 16
-+
-+#define BCM2835_DMA_BULK_MASK BIT(0)
-+#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
-+
-+
-+/* Valid only for channels 0 - 14, 15 has its own base address */
-+#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
-+#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
-+
-+#define MAX_LITE_TRANSFER 32768
-+#define MAX_NORMAL_TRANSFER 1073741824
-+
-+static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
-+{
-+ return container_of(d, struct bcm2835_dmadev, ddev);
-+}
-+
-+static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
-+{
-+ return container_of(c, struct bcm2835_chan, vc.chan);
-+}
-+
-+static inline struct bcm2835_desc *to_bcm2835_dma_desc(
-+ struct dma_async_tx_descriptor *t)
-+{
-+ return container_of(t, struct bcm2835_desc, vd.tx);
-+}
-+
-+static void dma_dumpregs(struct bcm2835_chan *c)
-+{
-+ pr_debug("-------------DMA DUMPREGS-------------\n");
-+ pr_debug("CS= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_CS));
-+ pr_debug("ADDR= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_ADDR));
-+ pr_debug("SOURCE_ADDR= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_SOURCE_AD));
-+ pr_debug("DEST_AD= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_DEST_AD));
-+ pr_debug("NEXTCB= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_NEXTCB));
-+ pr_debug("--------------------------------------\n");
-+}
-+
-+static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
-+{
-+ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
-+ dma_free_coherent(desc->vd.tx.chan->device->dev,
-+ desc->control_block_size,
-+ desc->control_block_base,
-+ desc->control_block_base_phys);
-+ kfree(desc);
-+}
-+
-+static int bcm2835_dma_abort(void __iomem *chan_base)
-+{
-+ unsigned long cs;
-+ long int timeout = 10000;
-+
-+ cs = readl(chan_base + BCM2835_DMA_CS);
-+ if (!(cs & BCM2835_DMA_ACTIVE))
-+ return 0;
-+
-+ /* Write 0 to the active bit - Pause the DMA */
-+ writel(0, chan_base + BCM2835_DMA_CS);
-+
-+ /* Wait for any current AXI transfer to complete */
-+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
-+ cpu_relax();
-+ cs = readl(chan_base + BCM2835_DMA_CS);
-+ }
-+
-+ /* We'll un-pause when we set of our next DMA */
-+ if (!timeout)
-+ return -ETIMEDOUT;
-+
-+ if (!(cs & BCM2835_DMA_ACTIVE))
-+ return 0;
-+
-+ /* Terminate the control block chain */
-+ writel(0, chan_base + BCM2835_DMA_NEXTCB);
-+
-+ /* Abort the whole DMA */
-+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
-+ chan_base + BCM2835_DMA_CS);
-+
-+ return 0;
-+}
-+
-+
-+static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
-+{
-+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
-+ struct bcm2835_desc *d;
-+
-+ if (!vd) {
-+ c->desc = NULL;
-+ return;
-+ }
-+
-+ list_del(&vd->node);
-+
-+ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
-+
-+ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
-+ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
-+
-+}
-+
-+static irqreturn_t bcm2835_dma_callback(int irq, void *data)
-+{
-+ struct bcm2835_chan *c = data;
-+ struct bcm2835_desc *d;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+
-+ /* Acknowledge interrupt */
-+ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
-+
-+ d = c->desc;
-+
-+ if (d) {
-+ if (c->cyclic) {
-+ vchan_cyclic_callback(&d->vd);
-+
-+ /* Keep the DMA engine running */
-+ writel(BCM2835_DMA_ACTIVE,
-+ c->chan_base + BCM2835_DMA_CS);
-+
-+ } else {
-+ vchan_cookie_complete(&c->desc->vd);
-+ bcm2835_dma_start_desc(c);
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ int ret;
-+
-+ dev_dbg(c->vc.chan.device->dev,
-+ "Allocating DMA channel %d\n", c->ch);
-+
-+ ret = request_irq(c->irq_number,
-+ bcm2835_dma_callback, 0, "DMA IRQ", c);
-+
-+ return ret;
-+}
-+
-+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+
-+ vchan_free_chan_resources(&c->vc);
-+ free_irq(c->irq_number, c);
-+
-+ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
-+}
-+
-+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
-+{
-+ return d->size;
-+}
-+
-+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
-+{
-+ unsigned int i;
-+ size_t size;
-+
-+ for (size = i = 0; i < d->frames; i++) {
-+ struct bcm2835_dma_cb *control_block =
-+ &d->control_block_base[i];
-+ size_t this_size = control_block->length;
-+ dma_addr_t dma;
-+
-+ if (d->dir == DMA_DEV_TO_MEM)
-+ dma = control_block->dst;
-+ else
-+ dma = control_block->src;
-+
-+ if (size)
-+ size += this_size;
-+ else if (addr >= dma && addr < dma + this_size)
-+ size += dma + this_size - addr;
-+ }
-+
-+ return size;
-+}
-+
-+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
-+ dma_cookie_t cookie, struct dma_tx_state *txstate)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ struct bcm2835_desc *d;
-+ struct virt_dma_desc *vd;
-+ enum dma_status ret;
-+ unsigned long flags;
-+ dma_addr_t pos;
-+
-+ ret = dma_cookie_status(chan, cookie, txstate);
-+ if (ret == DMA_COMPLETE || !txstate)
-+ return ret;
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+ vd = vchan_find_desc(&c->vc, cookie);
-+ if (vd) {
-+ txstate->residue =
-+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
-+ } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
-+ d = c->desc;
-+
-+ if (d->dir == DMA_MEM_TO_DEV)
-+ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
-+ else if (d->dir == DMA_DEV_TO_MEM)
-+ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
-+ else
-+ pos = 0;
-+
-+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
-+ } else {
-+ txstate->residue = 0;
-+ }
-+
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+
-+ return ret;
-+}
-+
-+static void bcm2835_dma_issue_pending(struct dma_chan *chan)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+ if (vchan_issue_pending(&c->vc) && !c->desc)
-+ bcm2835_dma_start_desc(c);
-+
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+}
-+
-+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
-+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
-+ size_t period_len, enum dma_transfer_direction direction,
-+ unsigned long flags, void *context)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ enum dma_slave_buswidth dev_width;
-+ struct bcm2835_desc *d;
-+ dma_addr_t dev_addr;
-+ unsigned int es, sync_type;
-+ unsigned int frame, max_size;
-+
-+ /* Grab configuration */
-+ if (!is_slave_direction(direction)) {
-+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
-+ return NULL;
-+ }
-+
-+ if (direction == DMA_DEV_TO_MEM) {
-+ dev_addr = c->cfg.src_addr;
-+ dev_width = c->cfg.src_addr_width;
-+ sync_type = BCM2835_DMA_S_DREQ;
-+ } else {
-+ dev_addr = c->cfg.dst_addr;
-+ dev_width = c->cfg.dst_addr_width;
-+ sync_type = BCM2835_DMA_D_DREQ;
-+ }
-+
-+ /* Bus width translates to the element size (ES) */
-+ switch (dev_width) {
-+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
-+ es = BCM2835_DMA_DATA_TYPE_S32;
-+ break;
-+ default:
-+ return NULL;
-+ }
-+
-+ /* Now allocate and setup the descriptor. */
-+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
-+ if (!d)
-+ return NULL;
-+
-+ d->dir = direction;
-+
-+ if (c->ch >= 8) /* we have a LITE channel */
-+ max_size = MAX_LITE_TRANSFER;
-+ else
-+ max_size = MAX_NORMAL_TRANSFER;
-+ period_len = min(period_len, max_size);
-+
-+ d->frames = (buf_len-1) / period_len + 1;
-+
-+ /* Allocate memory for control blocks */
-+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
-+ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
-+ d->control_block_size, &d->control_block_base_phys,
-+ GFP_NOWAIT);
-+
-+ if (!d->control_block_base) {
-+ kfree(d);
-+ return NULL;
-+ }
-+
-+ /*
-+ * Iterate over all frames, create a control block
-+ * for each frame and link them together.
-+ */
-+ for (frame = 0; frame < d->frames; frame++) {
-+ struct bcm2835_dma_cb *control_block =
-+ &d->control_block_base[frame];
-+
-+ /* Setup adresses */
-+ if (d->dir == DMA_DEV_TO_MEM) {
-+ control_block->info = BCM2835_DMA_D_INC;
-+ control_block->src = dev_addr;
-+ control_block->dst = buf_addr + frame * period_len;
-+ } else {
-+ control_block->info = BCM2835_DMA_S_INC;
-+ control_block->src = buf_addr + frame * period_len;
-+ control_block->dst = dev_addr;
-+ }
-+
-+ /* Enable interrupt */
-+ control_block->info |= BCM2835_DMA_INT_EN;
-+
-+ /* Setup synchronization */
-+ if (sync_type != 0)
-+ control_block->info |= sync_type;
-+
-+ /* Setup DREQ channel */
-+ if (c->cfg.slave_id != 0)
-+ control_block->info |=
-+ BCM2835_DMA_PER_MAP(c->cfg.slave_id);
-+
-+ /* Length of a frame */
-+ if (frame != d->frames-1)
-+ control_block->length = period_len;
-+ else
-+ control_block->length = buf_len - (d->frames - 1) * period_len;
-+
-+ d->size += control_block->length;
-+
-+ /*
-+ * Next block is the next frame.
-+ * This function is called on cyclic DMA transfers.
-+ * Therefore, wrap around at number of frames.
-+ */
-+ control_block->next = d->control_block_base_phys +
-+ sizeof(struct bcm2835_dma_cb)
-+ * ((frame + 1) % d->frames);
-+ }
-+
-+ c->cyclic = true;
-+
-+ return vchan_tx_prep(&c->vc, &d->vd, flags);
-+}
-+
-+
-+static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
-+ struct dma_chan *chan, struct scatterlist *sgl,
-+ unsigned int sg_len, enum dma_transfer_direction direction,
-+ unsigned long flags, void *context)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ enum dma_slave_buswidth dev_width;
-+ struct bcm2835_desc *d;
-+ dma_addr_t dev_addr;
-+ struct scatterlist *sgent;
-+ unsigned int es, sync_type;
-+ unsigned int i, j, splitct, max_size;
-+
-+ if (!is_slave_direction(direction)) {
-+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
-+ return NULL;
-+ }
-+
-+ if (direction == DMA_DEV_TO_MEM) {
-+ dev_addr = c->cfg.src_addr;
-+ dev_width = c->cfg.src_addr_width;
-+ sync_type = BCM2835_DMA_S_DREQ;
-+ } else {
-+ dev_addr = c->cfg.dst_addr;
-+ dev_width = c->cfg.dst_addr_width;
-+ sync_type = BCM2835_DMA_D_DREQ;
-+ }
-+
-+ /* Bus width translates to the element size (ES) */
-+ switch (dev_width) {
-+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
-+ es = BCM2835_DMA_DATA_TYPE_S32;
-+ break;
-+ default:
-+ return NULL;
-+ }
-+
-+ /* Now allocate and setup the descriptor. */
-+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
-+ if (!d)
-+ return NULL;
-+
-+ d->dir = direction;
-+
-+ if (c->ch >= 8) /* we have a LITE channel */
-+ max_size = MAX_LITE_TRANSFER;
-+ else
-+ max_size = MAX_NORMAL_TRANSFER;
-+
-+ /* We store the length of the SG list in d->frames
-+ taking care to account for splitting up transfers
-+ too large for a LITE channel */
-+
-+ d->frames = 0;
-+ for_each_sg(sgl, sgent, sg_len, i) {
-+ uint32_t len = sg_dma_len(sgent);
-+ d->frames += 1 + len / max_size;
-+ }
-+
-+ /* Allocate memory for control blocks */
-+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
-+ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
-+ d->control_block_size, &d->control_block_base_phys,
-+ GFP_NOWAIT);
-+
-+ if (!d->control_block_base) {
-+ kfree(d);
-+ return NULL;
-+ }
-+
-+ /*
-+ * Iterate over all SG entries, create a control block
-+ * for each frame and link them together.
-+ */
-+
-+ /* we count the number of times an SG entry had to be splitct
-+ as a result of using a LITE channel */
-+ splitct = 0;
-+
-+ for_each_sg(sgl, sgent, sg_len, i) {
-+ dma_addr_t addr = sg_dma_address(sgent);
-+ uint32_t len = sg_dma_len(sgent);
-+
-+ for (j = 0; j < len; j += max_size) {
-+ struct bcm2835_dma_cb *control_block =
-+ &d->control_block_base[i+splitct];
-+
-+ /* Setup adresses */
-+ if (d->dir == DMA_DEV_TO_MEM) {
-+ control_block->info = BCM2835_DMA_D_INC |
-+ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ;
-+ control_block->src = dev_addr;
-+ control_block->dst = addr + (dma_addr_t)j;
-+ } else {
-+ control_block->info = BCM2835_DMA_S_INC |
-+ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ;
-+ control_block->src = addr + (dma_addr_t)j;
-+ control_block->dst = dev_addr;
-+ }
-+
-+ /* Common part */
-+ control_block->info |= BCM2835_DMA_WAITS(SDHCI_BCM_DMA_WAITS);
-+ control_block->info |= BCM2835_DMA_WAIT_RESP;
-+
-+ /* Enable */
-+ if (i == sg_len-1 && len-j <= max_size)
-+ control_block->info |= BCM2835_DMA_INT_EN;
-+
-+ /* Setup synchronization */
-+ if (sync_type != 0)
-+ control_block->info |= sync_type;
-+
-+ /* Setup DREQ channel */
-+ c->dreq = c->cfg.slave_id; /* DREQ loaded from config */
-+
-+ if (c->dreq != 0)
-+ control_block->info |=
-+ BCM2835_DMA_PER_MAP(c->dreq);
-+
-+ /* Length of a frame */
-+ control_block->length = min(len-j, max_size);
-+ d->size += control_block->length;
-+
-+ /*
-+ * Next block is the next frame.
-+ */
-+ if (i < sg_len-1 || len-j > max_size) {
-+ /* next block is the next frame. */
-+ control_block->next = d->control_block_base_phys +
-+ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1);
-+ } else {
-+ /* next block is empty. */
-+ control_block->next = 0;
-+ }
-+
-+ if (len-j > max_size)
-+ splitct++;
-+ }
-+ }
-+
-+ c->cyclic = false;
-+
-+ return vchan_tx_prep(&c->vc, &d->vd, flags);
-+}
-+
-+static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
-+ struct dma_slave_config *cfg)
-+{
-+ if ((cfg->direction == DMA_DEV_TO_MEM &&
-+ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
-+ (cfg->direction == DMA_MEM_TO_DEV &&
-+ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
-+ !is_slave_direction(cfg->direction)) {
-+ return -EINVAL;
-+ }
-+
-+ c->cfg = *cfg;
-+
-+ return 0;
-+}
-+
-+static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
-+{
-+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
-+ unsigned long flags;
-+ int timeout = 10000;
-+ LIST_HEAD(head);
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+
-+ /* Prevent this channel being scheduled */
-+ spin_lock(&d->lock);
-+ list_del_init(&c->node);
-+ spin_unlock(&d->lock);
-+
-+ /*
-+ * Stop DMA activity: we assume the callback will not be called
-+ * after bcm_dma_abort() returns (even if it does, it will see
-+ * c->desc is NULL and exit.)
-+ */
-+ if (c->desc) {
-+ c->desc = NULL;
-+ bcm2835_dma_abort(c->chan_base);
-+
-+ /* Wait for stopping */
-+ while (--timeout) {
-+ if (!(readl(c->chan_base + BCM2835_DMA_CS) &
-+ BCM2835_DMA_ACTIVE))
-+ break;
-+
-+ cpu_relax();
-+ }
-+
-+ if (!timeout)
-+ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
-+ }
-+
-+ vchan_get_all_descriptors(&c->vc, &head);
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+ vchan_dma_desc_free_list(&c->vc, &head);
-+
-+ return 0;
-+}
-+
-+static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-+ unsigned long arg)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+
-+ switch (cmd) {
-+ case DMA_SLAVE_CONFIG:
-+ return bcm2835_dma_slave_config(c,
-+ (struct dma_slave_config *)arg);
-+
-+ case DMA_TERMINATE_ALL:
-+ return bcm2835_dma_terminate_all(c);
-+
-+ default:
-+ return -ENXIO;
-+ }
-+}
-+
-+#ifdef CONFIG_OF
-+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
-+{
-+ struct bcm2835_chan *c;
-+
-+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
-+ if (!c)
-+ return -ENOMEM;
-+
-+ c->vc.desc_free = bcm2835_dma_desc_free;
-+ vchan_init(&c->vc, &d->ddev);
-+ INIT_LIST_HEAD(&c->node);
-+
-+ d->ddev.chancnt++;
-+
-+ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
-+ c->ch = chan_id;
-+ c->irq_number = irq;
-+
-+ return 0;
-+}
-+#endif
-+
-+static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d,
-+ void __iomem *chan_base, int chan_id, int irq)
-+{
-+ struct bcm2835_chan *c;
-+
-+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
-+ if (!c)
-+ return -ENOMEM;
-+
-+ c->vc.desc_free = bcm2835_dma_desc_free;
-+ vchan_init(&c->vc, &d->ddev);
-+ INIT_LIST_HEAD(&c->node);
-+
-+ d->ddev.chancnt++;
-+
-+ c->chan_base = chan_base;
-+ c->ch = chan_id;
-+ c->irq_number = irq;
-+
-+ return 0;
-+}
-+
-+
-+static void bcm2835_dma_free(struct bcm2835_dmadev *od)
-+{
-+ struct bcm2835_chan *c, *next;
-+
-+ list_for_each_entry_safe(c, next, &od->ddev.channels,
-+ vc.chan.device_node) {
-+ list_del(&c->vc.chan.device_node);
-+ tasklet_kill(&c->vc.task);
-+ }
-+}
-+
-+static const struct of_device_id bcm2835_dma_of_match[] = {
-+ { .compatible = "brcm,bcm2835-dma", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
-+
-+#ifdef CONFIG_OF
-+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
-+ struct of_dma *ofdma)
-+{
-+ struct bcm2835_dmadev *d = ofdma->of_dma_data;
-+ struct dma_chan *chan;
-+
-+ chan = dma_get_any_slave_channel(&d->ddev);
-+ if (!chan)
-+ return NULL;
-+
-+ /* Set DREQ from param */
-+ to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
-+
-+ return chan;
-+}
-+#endif
-+
-+static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
-+ struct dma_slave_caps *caps)
-+{
-+ caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
-+ caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
-+ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
-+ caps->cmd_pause = false;
-+ caps->cmd_terminate = true;
-+
-+ return 0;
-+}
-+
-+static int bcm2835_dma_probe(struct platform_device *pdev)
-+{
-+ struct bcm2835_dmadev *od;
-+#ifdef CONFIG_OF
-+ struct resource *res;
-+ void __iomem *base;
-+ uint32_t chans_available;
-+#endif
-+ int rc;
-+ int i;
-+ int irq;
-+
-+
-+ if (!pdev->dev.dma_mask)
-+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
-+
-+ /* If CONFIG_OF is selected, device tree is used */
-+ /* hence the difference between probing */
-+
-+#ifndef CONFIG_OF
-+
-+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
-+ if (rc)
-+ return rc;
-+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-+
-+
-+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
-+ if (!od)
-+ return -ENOMEM;
-+
-+ pdev->dev.dma_parms = &od->dma_parms;
-+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
-+
-+
-+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
-+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
-+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
-+ od->ddev.device_tx_status = bcm2835_dma_tx_status;
-+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
-+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
-+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
-+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
-+ od->ddev.device_control = bcm2835_dma_control;
-+ od->ddev.dev = &pdev->dev;
-+ INIT_LIST_HEAD(&od->ddev.channels);
-+ spin_lock_init(&od->lock);
-+
-+ platform_set_drvdata(pdev, od);
-+
-+ for (i = 0; i < 5; i++) {
-+ void __iomem *chan_base;
-+ int chan_id;
-+
-+ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE,
-+ &chan_base,
-+ &irq);
-+
-+ if (chan_id < 0)
-+ break;
-+
-+ rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
-+ if (rc)
-+ goto err_no_dma;
-+ }
-+#else
-+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
-+ if (rc)
-+ return rc;
-+
-+
-+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
-+ if (!od)
-+ return -ENOMEM;
-+
-+ pdev->dev.dma_parms = &od->dma_parms;
-+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
-+
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ od->base = base;
-+
-+
-+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
-+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
-+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
-+ od->ddev.device_tx_status = bcm2835_dma_tx_status;
-+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
-+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
-+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
-+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
-+ od->ddev.device_control = bcm2835_dma_control;
-+ od->ddev.dev = &pdev->dev;
-+ INIT_LIST_HEAD(&od->ddev.channels);
-+ spin_lock_init(&od->lock);
-+
-+ platform_set_drvdata(pdev, od);
-+
-+
-+ /* Request DMA channel mask from device tree */
-+ if (of_property_read_u32(pdev->dev.of_node,
-+ "brcm,dma-channel-mask",
-+ &chans_available)) {
-+ dev_err(&pdev->dev, "Failed to get channel mask\n");
-+ rc = -EINVAL;
-+ goto err_no_dma;
-+ }
-+
-+
-+ /*
-+ * Do not use the FIQ and BULK channels,
-+ * because they are used by the GPU.
-+ */
-+ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
-+
-+
-+ for (i = 0; i < pdev->num_resources; i++) {
-+ irq = platform_get_irq(pdev, i);
-+ if (irq < 0)
-+ break;
-+
-+ if (chans_available & (1 << i)) {
-+ rc = bcm2835_dma_chan_init(od, i, irq);
-+ if (rc)
-+ goto err_no_dma;
-+ }
-+ }
-+
-+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
-+
-+ /* Device-tree DMA controller registration */
-+ rc = of_dma_controller_register(pdev->dev.of_node,
-+ bcm2835_dma_xlate, od);
-+ if (rc) {
-+ dev_err(&pdev->dev, "Failed to register DMA controller\n");
-+ goto err_no_dma;
-+ }
-+#endif
-+
-+ rc = dma_async_device_register(&od->ddev);
-+ if (rc) {
-+ dev_err(&pdev->dev,
-+ "Failed to register slave DMA engine device: %d\n", rc);
-+ goto err_no_dma;
-+ }
-+
-+ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n");
-+
-+ return 0;
-+
-+err_no_dma:
-+ bcm2835_dma_free(od);
-+ return rc;
-+}
-+
-+static int bcm2835_dma_remove(struct platform_device *pdev)
-+{
-+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
-+
-+ dma_async_device_unregister(&od->ddev);
-+ bcm2835_dma_free(od);
-+
-+ return 0;
-+}
-+
-+#ifndef CONFIG_OF
-+
-+
-+static struct platform_driver bcm2835_dma_driver = {
-+ .probe = bcm2835_dma_probe,
-+ .remove = bcm2835_dma_remove,
-+ .driver = {
-+ .name = "bcm2708-dmaengine",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_device *pdev;
-+
-+static const struct platform_device_info bcm2835_dma_dev_info = {
-+ .name = "bcm2708-dmaengine",
-+ .id = -1,
-+};
-+
-+static int bcm2835_dma_init(void)
-+{
-+ int rc = platform_driver_register(&bcm2835_dma_driver);
-+
-+ if (rc == 0) {
-+ pdev = platform_device_register_full(&bcm2835_dma_dev_info);
-+ if (IS_ERR(pdev)) {
-+ platform_driver_unregister(&bcm2835_dma_driver);
-+ rc = PTR_ERR(pdev);
-+ }
-+ }
-+
-+ return rc;
-+}
-+module_init(bcm2835_dma_init); /* preferable to subsys_initcall */
-+
-+static void __exit bcm2835_dma_exit(void)
-+{
-+ platform_device_unregister(pdev);
-+ platform_driver_unregister(&bcm2835_dma_driver);
-+}
-+module_exit(bcm2835_dma_exit);
-+
-+#else
-+
-+static struct platform_driver bcm2835_dma_driver = {
-+ .probe = bcm2835_dma_probe,
-+ .remove = bcm2835_dma_remove,
-+ .driver = {
-+ .name = "bcm2835-dma",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(bcm2835_dma_of_match),
-+ },
-+};
-+
-+module_platform_driver(bcm2835_dma_driver);
-+
-+#endif
-+
-+MODULE_ALIAS("platform:bcm2835-dma");
-+MODULE_DESCRIPTION("BCM2835 DMA engine driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/drivers/dma/Kconfig linux-rpi/drivers/dma/Kconfig
---- linux-3.12.38/drivers/dma/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/dma/Kconfig 2015-03-10 17:26:50.194216694 +0100
-@@ -288,6 +288,12 @@
- select DMA_ENGINE
- select DMA_VIRTUAL_CHANNELS
-
-+config DMA_BCM2708
-+ tristate "BCM2708 DMA engine support"
-+ depends on MACH_BCM2708
-+ select DMA_ENGINE
-+ select DMA_VIRTUAL_CHANNELS
-+
- config TI_CPPI41
- tristate "AM33xx CPPI41 DMA support"
- depends on ARCH_OMAP
-diff -Nur linux-3.12.38/drivers/dma/Makefile linux-rpi/drivers/dma/Makefile
---- linux-3.12.38/drivers/dma/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/dma/Makefile 2015-03-10 17:26:50.194216694 +0100
-@@ -37,6 +37,7 @@
- obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
- obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
- obj-$(CONFIG_DMA_OMAP) += omap-dma.o
-+obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
- obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
- obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
- obj-$(CONFIG_TI_CPPI41) += cppi41.o
-diff -Nur linux-3.12.38/drivers/firmware/iscsi_ibft.c linux-rpi/drivers/firmware/iscsi_ibft.c
---- linux-3.12.38/drivers/firmware/iscsi_ibft.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/firmware/iscsi_ibft.c 2015-03-10 17:26:50.210216694 +0100
-@@ -756,7 +756,6 @@
- */
- { ACPI_SIG_IBFT },
- { "iBFT" },
-- { "BIFT" }, /* Broadcom iSCSI Offload */
- };
-
- static void __init acpi_find_ibft_region(void)
-diff -Nur linux-3.12.38/drivers/gpio/gpiolib.c linux-rpi/drivers/gpio/gpiolib.c
---- linux-3.12.38/drivers/gpio/gpiolib.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpio/gpiolib.c 2015-03-10 17:26:50.218216694 +0100
-@@ -362,7 +362,7 @@
- return status;
- }
-
--static DEVICE_ATTR(value, 0644,
-+static const DEVICE_ATTR(value, 0644,
- gpio_value_show, gpio_value_store);
-
- static irqreturn_t gpio_sysfs_irq(int irq, void *priv)
-@@ -580,16 +580,18 @@
- return status ? : size;
- }
-
--static DEVICE_ATTR(active_low, 0644,
-+static const DEVICE_ATTR(active_low, 0644,
- gpio_active_low_show, gpio_active_low_store);
-
--static struct attribute *gpio_attrs[] = {
-+static const struct attribute *gpio_attrs[] = {
- &dev_attr_value.attr,
- &dev_attr_active_low.attr,
- NULL,
- };
-
--ATTRIBUTE_GROUPS(gpio);
-+static const struct attribute_group gpio_attr_group = {
-+ .attrs = (struct attribute **) gpio_attrs,
-+};
-
- /*
- * /sys/class/gpio/gpiochipN/
-@@ -625,13 +627,16 @@
- }
- static DEVICE_ATTR(ngpio, 0444, chip_ngpio_show, NULL);
-
--static struct attribute *gpiochip_attrs[] = {
-+static const struct attribute *gpiochip_attrs[] = {
- &dev_attr_base.attr,
- &dev_attr_label.attr,
- &dev_attr_ngpio.attr,
- NULL,
- };
--ATTRIBUTE_GROUPS(gpiochip);
-+
-+static const struct attribute_group gpiochip_attr_group = {
-+ .attrs = (struct attribute **) gpiochip_attrs,
-+};
-
- /*
- * /sys/class/gpio/export ... write-only
-@@ -786,15 +791,18 @@
- if (desc->chip->names && desc->chip->names[offset])
- ioname = desc->chip->names[offset];
-
-- dev = device_create_with_groups(&gpio_class, desc->chip->dev,
-- MKDEV(0, 0), desc, gpio_groups,
-- ioname ? ioname : "gpio%u",
-- desc_to_gpio(desc));
-+ dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0),
-+ desc, ioname ? ioname : "gpio%u",
-+ desc_to_gpio(desc));
- if (IS_ERR(dev)) {
- status = PTR_ERR(dev);
- goto fail_unlock;
- }
-
-+ status = sysfs_create_group(&dev->kobj, &gpio_attr_group);
-+ if (status)
-+ goto fail_unregister_device;
-+
- if (direction_may_change) {
- status = device_create_file(dev, &dev_attr_direction);
- if (status)
-@@ -805,15 +813,13 @@
- !test_bit(FLAG_IS_OUT, &desc->flags))) {
- status = device_create_file(dev, &dev_attr_edge);
- if (status)
-- goto fail_remove_attr_direction;
-+ goto fail_unregister_device;
- }
-
- set_bit(FLAG_EXPORT, &desc->flags);
- mutex_unlock(&sysfs_lock);
- return 0;
-
--fail_remove_attr_direction:
-- device_remove_file(dev, &dev_attr_direction);
- fail_unregister_device:
- device_unregister(dev);
- fail_unlock:
-@@ -864,7 +870,6 @@
- if (tdev != NULL) {
- status = sysfs_create_link(&dev->kobj, &tdev->kobj,
- name);
-- put_device(tdev);
- } else {
- status = -ENODEV;
- }
-@@ -918,7 +923,7 @@
- }
-
- status = sysfs_set_active_low(desc, dev, value);
-- put_device(dev);
-+
- unlock:
- mutex_unlock(&sysfs_lock);
-
-@@ -966,8 +971,6 @@
- mutex_unlock(&sysfs_lock);
-
- if (dev) {
-- device_remove_file(dev, &dev_attr_edge);
-- device_remove_file(dev, &dev_attr_direction);
- device_unregister(dev);
- put_device(dev);
- }
-@@ -998,13 +1001,13 @@
-
- /* use chip->base for the ID; it's already known to be unique */
- mutex_lock(&sysfs_lock);
-- dev = device_create_with_groups(&gpio_class, chip->dev, MKDEV(0, 0),
-- chip, gpiochip_groups,
-- "gpiochip%d", chip->base);
-- if (IS_ERR(dev))
-+ dev = device_create(&gpio_class, chip->dev, MKDEV(0, 0), chip,
-+ "gpiochip%d", chip->base);
-+ if (!IS_ERR(dev)) {
-+ status = sysfs_create_group(&dev->kobj,
-+ &gpiochip_attr_group);
-+ } else
- status = PTR_ERR(dev);
-- else
-- status = 0;
- chip->exported = (status == 0);
- mutex_unlock(&sysfs_lock);
-
-@@ -1213,20 +1216,18 @@
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
-- if (status)
-- goto fail;
--
- #ifdef CONFIG_PINCTRL
- INIT_LIST_HEAD(&chip->pin_ranges);
- #endif
-
- of_gpiochip_add(chip);
-
-+ if (status)
-+ goto fail;
-+
- status = gpiochip_export(chip);
-- if (status) {
-- of_gpiochip_remove(chip);
-+ if (status)
- goto fail;
-- }
-
- pr_debug("gpiochip_add: registered GPIOs %d to %d on device: %s\n",
- chip->base, chip->base + chip->ngpio - 1,
-diff -Nur linux-3.12.38/drivers/gpio/gpiolib-of.c linux-rpi/drivers/gpio/gpiolib-of.c
---- linux-3.12.38/drivers/gpio/gpiolib-of.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpio/gpiolib-of.c 2015-03-10 17:26:50.218216694 +0100
-@@ -12,7 +12,6 @@
- */
-
- #include <linux/device.h>
--#include <linux/err.h>
- #include <linux/errno.h>
- #include <linux/module.h>
- #include <linux/io.h>
-@@ -43,14 +42,8 @@
- return false;
-
- ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags);
-- if (ret < 0) {
-- /* We've found the gpio chip, but the translation failed.
-- * Return true to stop looking and return the translation
-- * error via out_gpio
-- */
-- gg_data->out_gpio = ERR_PTR(ret);
-- return true;
-- }
-+ if (ret < 0)
-+ return false;
-
- gg_data->out_gpio = ret + gc->base;
- return true;
-diff -Nur linux-3.12.38/drivers/gpu/drm/i915/i915_gem.c linux-rpi/drivers/gpu/drm/i915/i915_gem.c
---- linux-3.12.38/drivers/gpu/drm/i915/i915_gem.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/i915/i915_gem.c 2015-03-10 17:26:50.234216694 +0100
-@@ -2788,13 +2788,6 @@
- u32 size = i915_gem_obj_ggtt_size(obj);
- uint64_t val;
-
-- /* Adjust fence size to match tiled area */
-- if (obj->tiling_mode != I915_TILING_NONE) {
-- uint32_t row_size = obj->stride *
-- (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
-- size = (size / row_size) * row_size;
-- }
--
- val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
- 0xfffff000) << 32;
- val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
-@@ -4802,7 +4795,7 @@
- if (!mutex_is_locked(mutex))
- return false;
-
--#if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES)
-+#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
- return mutex->owner == task;
- #else
- /* Since UP may be pre-empted, we cannot assume that we own the lock */
-diff -Nur linux-3.12.38/drivers/gpu/drm/i915/i915_gem_stolen.c linux-rpi/drivers/gpu/drm/i915/i915_gem_stolen.c
---- linux-3.12.38/drivers/gpu/drm/i915/i915_gem_stolen.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/i915/i915_gem_stolen.c 2015-03-10 17:26:50.234216694 +0100
-@@ -126,26 +126,9 @@
- r = devm_request_mem_region(dev->dev, base, dev_priv->gtt.stolen_size,
- "Graphics Stolen Memory");
- if (r == NULL) {
-- /*
-- * One more attempt but this time requesting region from
-- * base + 1, as we have seen that this resolves the region
-- * conflict with the PCI Bus.
-- * This is a BIOS w/a: Some BIOS wrap stolen in the root
-- * PCI bus, but have an off-by-one error. Hence retry the
-- * reservation starting from 1 instead of 0.
-- */
-- r = devm_request_mem_region(dev->dev, base + 1,
-- dev_priv->gtt.stolen_size - 1,
-- "Graphics Stolen Memory");
-- /*
-- * GEN3 firmware likes to smash pci bridges into the stolen
-- * range. Apparently this works.
-- */
-- if (r == NULL && !IS_GEN3(dev)) {
-- DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
-- base, base + (uint32_t)dev_priv->gtt.stolen_size);
-- base = 0;
-- }
-+ DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
-+ base, base + (uint32_t)dev_priv->gtt.stolen_size);
-+ base = 0;
- }
-
- return base;
-diff -Nur linux-3.12.38/drivers/gpu/drm/i915/i915_reg.h linux-rpi/drivers/gpu/drm/i915/i915_reg.h
---- linux-3.12.38/drivers/gpu/drm/i915/i915_reg.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/i915/i915_reg.h 2015-03-10 17:26:50.238216694 +0100
-@@ -309,7 +309,6 @@
- #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
- #define PIPE_CONTROL_CS_STALL (1<<20)
- #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
--#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
- #define PIPE_CONTROL_QW_WRITE (1<<14)
- #define PIPE_CONTROL_DEPTH_STALL (1<<13)
- #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
-diff -Nur linux-3.12.38/drivers/gpu/drm/i915/intel_ringbuffer.c linux-rpi/drivers/gpu/drm/i915/intel_ringbuffer.c
---- linux-3.12.38/drivers/gpu/drm/i915/intel_ringbuffer.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/i915/intel_ringbuffer.c 2015-03-10 17:26:50.242216694 +0100
-@@ -322,15 +322,12 @@
- flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
- flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
- flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-- flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
- /*
- * TLB invalidate requires a post-sync write.
- */
- flags |= PIPE_CONTROL_QW_WRITE;
- flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
-
-- flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
--
- /* Workaround: we must issue a pipe_control with CS-stall bit
- * set before a pipe_control command that has the state cache
- * invalidate bit set. */
-diff -Nur linux-3.12.38/drivers/gpu/drm/radeon/atombios_dp.c linux-rpi/drivers/gpu/drm/radeon/atombios_dp.c
---- linux-3.12.38/drivers/gpu/drm/radeon/atombios_dp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/radeon/atombios_dp.c 2015-03-10 17:26:50.274216694 +0100
-@@ -574,10 +574,6 @@
- struct radeon_connector_atom_dig *dig_connector;
- int dp_clock;
-
-- if ((mode->clock > 340000) &&
-- (!radeon_connector_is_dp12_capable(connector)))
-- return MODE_CLOCK_HIGH;
--
- if (!radeon_connector->con_priv)
- return MODE_CLOCK_HIGH;
- dig_connector = radeon_connector->con_priv;
-diff -Nur linux-3.12.38/drivers/gpu/drm/radeon/ci_dpm.c linux-rpi/drivers/gpu/drm/radeon/ci_dpm.c
---- linux-3.12.38/drivers/gpu/drm/radeon/ci_dpm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/radeon/ci_dpm.c 2015-03-10 17:26:50.274216694 +0100
-@@ -4698,7 +4698,7 @@
- ci_enable_spread_spectrum(rdev, false);
- ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
- ci_stop_dpm(rdev);
-- ci_enable_ds_master_switch(rdev, false);
-+ ci_enable_ds_master_switch(rdev, true);
- ci_enable_ulv(rdev, false);
- ci_clear_vc(rdev);
- ci_reset_to_default(rdev);
-diff -Nur linux-3.12.38/drivers/gpu/drm/radeon/cik.c linux-rpi/drivers/gpu/drm/radeon/cik.c
---- linux-3.12.38/drivers/gpu/drm/radeon/cik.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/radeon/cik.c 2015-03-10 17:26:50.278216694 +0100
-@@ -5167,7 +5167,6 @@
- }
-
- orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
-- data |= 0x00000001;
- data &= 0xfffffffd;
- if (orig != data)
- WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
-@@ -5199,7 +5198,7 @@
- }
- } else {
- orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
-- data |= 0x00000003;
-+ data |= 0x00000002;
- if (orig != data)
- WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
-
-diff -Nur linux-3.12.38/drivers/gpu/drm/radeon/radeon_ttm.c linux-rpi/drivers/gpu/drm/radeon/radeon_ttm.c
---- linux-3.12.38/drivers/gpu/drm/radeon/radeon_ttm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/radeon/radeon_ttm.c 2015-03-10 17:26:50.294216694 +0100
-@@ -189,7 +189,7 @@
- rbo = container_of(bo, struct radeon_bo, tbo);
- switch (bo->mem.mem_type) {
- case TTM_PL_VRAM:
-- if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
-+ if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
- radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
- else
- radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
-diff -Nur linux-3.12.38/drivers/gpu/drm/radeon/si_dpm.c linux-rpi/drivers/gpu/drm/radeon/si_dpm.c
---- linux-3.12.38/drivers/gpu/drm/radeon/si_dpm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/radeon/si_dpm.c 2015-03-10 17:26:50.298216694 +0100
-@@ -2901,22 +2901,6 @@
- return ret;
- }
-
--struct si_dpm_quirk {
-- u32 chip_vendor;
-- u32 chip_device;
-- u32 subsys_vendor;
-- u32 subsys_device;
-- u32 max_sclk;
-- u32 max_mclk;
--};
--
--/* cards with dpm stability problems */
--static struct si_dpm_quirk si_dpm_quirk_list[] = {
-- /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
-- { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
-- { 0, 0, 0, 0 },
--};
--
- static void si_apply_state_adjust_rules(struct radeon_device *rdev,
- struct radeon_ps *rps)
- {
-@@ -2927,22 +2911,7 @@
- u32 mclk, sclk;
- u16 vddc, vddci;
- u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
-- u32 max_sclk = 0, max_mclk = 0;
- int i;
-- struct si_dpm_quirk *p = si_dpm_quirk_list;
--
-- /* Apply dpm quirks */
-- while (p && p->chip_device != 0) {
-- if (rdev->pdev->vendor == p->chip_vendor &&
-- rdev->pdev->device == p->chip_device &&
-- rdev->pdev->subsystem_vendor == p->subsys_vendor &&
-- rdev->pdev->subsystem_device == p->subsys_device) {
-- max_sclk = p->max_sclk;
-- max_mclk = p->max_mclk;
-- break;
-- }
-- ++p;
-- }
-
- if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
- ni_dpm_vblank_too_short(rdev))
-@@ -2996,14 +2965,6 @@
- if (ps->performance_levels[i].mclk > max_mclk_vddc)
- ps->performance_levels[i].mclk = max_mclk_vddc;
- }
-- if (max_mclk) {
-- if (ps->performance_levels[i].mclk > max_mclk)
-- ps->performance_levels[i].mclk = max_mclk;
-- }
-- if (max_sclk) {
-- if (ps->performance_levels[i].sclk > max_sclk)
-- ps->performance_levels[i].sclk = max_sclk;
-- }
- }
-
- /* XXX validate the min clocks required for display */
-diff -Nur linux-3.12.38/drivers/gpu/drm/ttm/ttm_page_alloc.c linux-rpi/drivers/gpu/drm/ttm/ttm_page_alloc.c
---- linux-3.12.38/drivers/gpu/drm/ttm/ttm_page_alloc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/ttm/ttm_page_alloc.c 2015-03-10 17:26:50.302216694 +0100
-@@ -297,12 +297,11 @@
- *
- * @pool: to free the pages from
- * @free_all: If set to true will free all pages in pool
-- * @use_static: Safe to use static buffer
-+ * @gfp: GFP flags.
- **/
- static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free,
-- bool use_static)
-+ gfp_t gfp)
- {
-- static struct page *static_buf[NUM_PAGES_TO_ALLOC];
- unsigned long irq_flags;
- struct page *p;
- struct page **pages_to_free;
-@@ -312,11 +311,7 @@
- if (NUM_PAGES_TO_ALLOC < nr_free)
- npages_to_free = NUM_PAGES_TO_ALLOC;
-
-- if (use_static)
-- pages_to_free = static_buf;
-- else
-- pages_to_free = kmalloc(npages_to_free * sizeof(struct page *),
-- GFP_KERNEL);
-+ pages_to_free = kmalloc(npages_to_free * sizeof(struct page *), gfp);
- if (!pages_to_free) {
- pr_err("Failed to allocate memory for pool free operation\n");
- return 0;
-@@ -379,8 +374,7 @@
- if (freed_pages)
- ttm_pages_put(pages_to_free, freed_pages);
- out:
-- if (pages_to_free != static_buf)
-- kfree(pages_to_free);
-+ kfree(pages_to_free);
- return nr_free;
- }
-
-@@ -389,6 +383,8 @@
- *
- * XXX: (dchinner) Deadlock warning!
- *
-+ * We need to pass sc->gfp_mask to ttm_page_pool_free().
-+ *
- * This code is crying out for a shrinker per pool....
- */
- static unsigned long
-@@ -411,8 +407,8 @@
- if (shrink_pages == 0)
- break;
- pool = &_manager->pools[(i + pool_offset)%NUM_POOLS];
-- /* OK to use static buffer since global mutex is held. */
-- shrink_pages = ttm_page_pool_free(pool, nr_free, true);
-+ shrink_pages = ttm_page_pool_free(pool, nr_free,
-+ sc->gfp_mask);
- freed += nr_free - shrink_pages;
- }
- mutex_unlock(&lock);
-@@ -714,7 +710,7 @@
- }
- spin_unlock_irqrestore(&pool->lock, irq_flags);
- if (npages)
-- ttm_page_pool_free(pool, npages, false);
-+ ttm_page_pool_free(pool, npages, GFP_KERNEL);
- }
-
- /*
-@@ -853,9 +849,9 @@
- pr_info("Finalizing pool allocator\n");
- ttm_pool_mm_shrink_fini(_manager);
-
-- /* OK to use static buffer since global mutex is no longer used. */
- for (i = 0; i < NUM_POOLS; ++i)
-- ttm_page_pool_free(&_manager->pools[i], FREE_ALL_PAGES, true);
-+ ttm_page_pool_free(&_manager->pools[i], FREE_ALL_PAGES,
-+ GFP_KERNEL);
-
- kobject_put(&_manager->kobj);
- _manager = NULL;
-diff -Nur linux-3.12.38/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c linux-rpi/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
---- linux-3.12.38/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 2015-03-10 17:26:50.302216694 +0100
-@@ -410,12 +410,11 @@
- *
- * @pool: to free the pages from
- * @nr_free: If set to true will free all pages in pool
-- * @use_static: Safe to use static buffer
-+ * @gfp: GFP flags.
- **/
- static unsigned ttm_dma_page_pool_free(struct dma_pool *pool, unsigned nr_free,
-- bool use_static)
-+ gfp_t gfp)
- {
-- static struct page *static_buf[NUM_PAGES_TO_ALLOC];
- unsigned long irq_flags;
- struct dma_page *dma_p, *tmp;
- struct page **pages_to_free;
-@@ -432,11 +431,7 @@
- npages_to_free, nr_free);
- }
- #endif
-- if (use_static)
-- pages_to_free = static_buf;
-- else
-- pages_to_free = kmalloc(npages_to_free * sizeof(struct page *),
-- GFP_KERNEL);
-+ pages_to_free = kmalloc(npages_to_free * sizeof(struct page *), gfp);
-
- if (!pages_to_free) {
- pr_err("%s: Failed to allocate memory for pool free operation\n",
-@@ -506,8 +501,7 @@
- if (freed_pages)
- ttm_dma_pages_put(pool, &d_pages, pages_to_free, freed_pages);
- out:
-- if (pages_to_free != static_buf)
-- kfree(pages_to_free);
-+ kfree(pages_to_free);
- return nr_free;
- }
-
-@@ -536,8 +530,7 @@
- if (pool->type != type)
- continue;
- /* Takes a spinlock.. */
-- /* OK to use static buffer since global mutex is held. */
-- ttm_dma_page_pool_free(pool, FREE_ALL_PAGES, true);
-+ ttm_dma_page_pool_free(pool, FREE_ALL_PAGES, GFP_KERNEL);
- WARN_ON(((pool->npages_in_use + pool->npages_free) != 0));
- /* This code path is called after _all_ references to the
- * struct device has been dropped - so nobody should be
-@@ -990,7 +983,7 @@
-
- /* shrink pool if necessary (only on !is_cached pools)*/
- if (npages)
-- ttm_dma_page_pool_free(pool, npages, false);
-+ ttm_dma_page_pool_free(pool, npages, GFP_KERNEL);
- ttm->state = tt_unpopulated;
- }
- EXPORT_SYMBOL_GPL(ttm_dma_unpopulate);
-@@ -1000,6 +993,8 @@
- *
- * XXX: (dchinner) Deadlock warning!
- *
-+ * We need to pass sc->gfp_mask to ttm_dma_page_pool_free().
-+ *
- * I'm getting sadder as I hear more pathetical whimpers about needing per-pool
- * shrinkers
- */
-@@ -1032,8 +1027,8 @@
- if (++idx < pool_offset)
- continue;
- nr_free = shrink_pages;
-- /* OK to use static buffer since global mutex is held. */
-- shrink_pages = ttm_dma_page_pool_free(p->pool, nr_free, true);
-+ shrink_pages = ttm_dma_page_pool_free(p->pool, nr_free,
-+ sc->gfp_mask);
- freed += nr_free - shrink_pages;
-
- pr_debug("%s: (%s:%d) Asked to shrink %d, have %d more to go\n",
-diff -Nur linux-3.12.38/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c linux-rpi/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
---- linux-3.12.38/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c 2015-03-10 17:26:50.306216693 +0100
-@@ -1049,8 +1049,6 @@
- if (ret != 0)
- goto out_no_queue;
-
-- return 0;
--
- out_no_queue:
- event->base.destroy(&event->base);
- out_no_event:
-@@ -1125,10 +1123,17 @@
-
- BUG_ON(fence == NULL);
-
-- ret = vmw_event_fence_action_create(file_priv, fence,
-- arg->flags,
-- arg->user_data,
-- true);
-+ if (arg->flags & DRM_VMW_FE_FLAG_REQ_TIME)
-+ ret = vmw_event_fence_action_create(file_priv, fence,
-+ arg->flags,
-+ arg->user_data,
-+ true);
-+ else
-+ ret = vmw_event_fence_action_create(file_priv, fence,
-+ arg->flags,
-+ arg->user_data,
-+ true);
-+
- if (unlikely(ret != 0)) {
- if (ret != -ERESTARTSYS)
- DRM_ERROR("Failed to attach event to fence.\n");
-diff -Nur linux-3.12.38/drivers/hid/hid-core.c linux-rpi/drivers/hid/hid-core.c
---- linux-3.12.38/drivers/hid/hid-core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/hid-core.c 2015-03-10 17:26:50.310216693 +0100
-@@ -1743,7 +1743,6 @@
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_ERGO_525V) },
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_I405X) },
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X) },
-- { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2) },
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X) },
- { HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD) },
- { HID_USB_DEVICE(USB_VENDOR_ID_LCPOWER, USB_DEVICE_ID_LCPOWER_LC1000 ) },
-diff -Nur linux-3.12.38/drivers/hid/hid-ids.h linux-rpi/drivers/hid/hid-ids.h
---- linux-3.12.38/drivers/hid/hid-ids.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/hid-ids.h 2015-03-10 17:26:50.310216693 +0100
-@@ -501,7 +501,6 @@
- #define USB_DEVICE_ID_KYE_GPEN_560 0x5003
- #define USB_DEVICE_ID_KYE_EASYPEN_I405X 0x5010
- #define USB_DEVICE_ID_KYE_MOUSEPEN_I608X 0x5011
--#define USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2 0x501a
- #define USB_DEVICE_ID_KYE_EASYPEN_M610X 0x5013
-
- #define USB_VENDOR_ID_LABTEC 0x1020
-diff -Nur linux-3.12.38/drivers/hid/hid-input.c linux-rpi/drivers/hid/hid-input.c
---- linux-3.12.38/drivers/hid/hid-input.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/hid-input.c 2015-03-10 17:26:50.310216693 +0100
-@@ -312,9 +312,6 @@
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_ANSI),
- HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE },
- { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE,
-- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_ISO),
-- HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE },
-- { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE,
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI),
- HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE },
- {}
-diff -Nur linux-3.12.38/drivers/hid/hid-kye.c linux-rpi/drivers/hid/hid-kye.c
---- linux-3.12.38/drivers/hid/hid-kye.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/hid-kye.c 2015-03-10 17:26:50.310216693 +0100
-@@ -323,7 +323,6 @@
- }
- break;
- case USB_DEVICE_ID_KYE_MOUSEPEN_I608X:
-- case USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2:
- if (*rsize == MOUSEPEN_I608X_RDESC_ORIG_SIZE) {
- rdesc = mousepen_i608x_rdesc_fixed;
- *rsize = sizeof(mousepen_i608x_rdesc_fixed);
-@@ -416,7 +415,6 @@
- switch (id->product) {
- case USB_DEVICE_ID_KYE_EASYPEN_I405X:
- case USB_DEVICE_ID_KYE_MOUSEPEN_I608X:
-- case USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2:
- case USB_DEVICE_ID_KYE_EASYPEN_M610X:
- ret = kye_tablet_enable(hdev);
- if (ret) {
-@@ -440,8 +438,6 @@
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE,
- USB_DEVICE_ID_KYE_MOUSEPEN_I608X) },
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE,
-- USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2) },
-- { HID_USB_DEVICE(USB_VENDOR_ID_KYE,
- USB_DEVICE_ID_KYE_EASYPEN_M610X) },
- { HID_USB_DEVICE(USB_VENDOR_ID_KYE,
- USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) },
-diff -Nur linux-3.12.38/drivers/hid/hid-roccat-pyra.c linux-rpi/drivers/hid/hid-roccat-pyra.c
---- linux-3.12.38/drivers/hid/hid-roccat-pyra.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/hid-roccat-pyra.c 2015-03-10 17:26:50.314216693 +0100
-@@ -35,8 +35,6 @@
- static void profile_activated(struct pyra_device *pyra,
- unsigned int new_profile)
- {
-- if (new_profile >= ARRAY_SIZE(pyra->profile_settings))
-- return;
- pyra->actual_profile = new_profile;
- pyra->actual_cpi = pyra->profile_settings[pyra->actual_profile].y_cpi;
- }
-@@ -259,12 +257,10 @@
- if (off != 0 || count != PYRA_SIZE_SETTINGS)
- return -EINVAL;
-
-- settings = (struct pyra_settings const *)buf;
-- if (settings->startup_profile >= ARRAY_SIZE(pyra->profile_settings))
-- return -EINVAL;
--
- mutex_lock(&pyra->pyra_lock);
-
-+ settings = (struct pyra_settings const *)buf;
-+
- retval = pyra_set_settings(usb_dev, settings);
- if (retval) {
- mutex_unlock(&pyra->pyra_lock);
-diff -Nur linux-3.12.38/drivers/hid/i2c-hid/i2c-hid.c linux-rpi/drivers/hid/i2c-hid/i2c-hid.c
---- linux-3.12.38/drivers/hid/i2c-hid/i2c-hid.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/i2c-hid/i2c-hid.c 2015-03-10 17:26:50.314216693 +0100
-@@ -136,7 +136,6 @@
- * descriptor. */
- unsigned int bufsize; /* i2c buffer size */
- char *inbuf; /* Input buffer */
-- char *rawbuf; /* Raw Input buffer */
- char *cmdbuf; /* Command buffer */
- char *argsbuf; /* Command arguments buffer */
-
-@@ -356,7 +355,7 @@
- static void i2c_hid_get_input(struct i2c_hid *ihid)
- {
- int ret, ret_size;
-- int size = ihid->bufsize;
-+ int size = le16_to_cpu(ihid->hdesc.wMaxInputLength);
-
- ret = i2c_master_recv(ihid->client, ihid->inbuf, size);
- if (ret != size) {
-@@ -487,11 +486,9 @@
- static void i2c_hid_free_buffers(struct i2c_hid *ihid)
- {
- kfree(ihid->inbuf);
-- kfree(ihid->rawbuf);
- kfree(ihid->argsbuf);
- kfree(ihid->cmdbuf);
- ihid->inbuf = NULL;
-- ihid->rawbuf = NULL;
- ihid->cmdbuf = NULL;
- ihid->argsbuf = NULL;
- ihid->bufsize = 0;
-@@ -507,11 +504,10 @@
- report_size; /* report */
-
- ihid->inbuf = kzalloc(report_size, GFP_KERNEL);
-- ihid->rawbuf = kzalloc(report_size, GFP_KERNEL);
- ihid->argsbuf = kzalloc(args_len, GFP_KERNEL);
- ihid->cmdbuf = kzalloc(sizeof(union command) + args_len, GFP_KERNEL);
-
-- if (!ihid->inbuf || !ihid->rawbuf || !ihid->argsbuf || !ihid->cmdbuf) {
-+ if (!ihid->inbuf || !ihid->argsbuf || !ihid->cmdbuf) {
- i2c_hid_free_buffers(ihid);
- return -ENOMEM;
- }
-@@ -538,12 +534,12 @@
-
- ret = i2c_hid_get_report(client,
- report_type == HID_FEATURE_REPORT ? 0x03 : 0x01,
-- report_number, ihid->rawbuf, ask_count);
-+ report_number, ihid->inbuf, ask_count);
-
- if (ret < 0)
- return ret;
-
-- ret_count = ihid->rawbuf[0] | (ihid->rawbuf[1] << 8);
-+ ret_count = ihid->inbuf[0] | (ihid->inbuf[1] << 8);
-
- if (ret_count <= 2)
- return 0;
-@@ -552,7 +548,7 @@
-
- /* The query buffer contains the size, dropping it in the reply */
- count = min(count, ret_count - 2);
-- memcpy(buf, ihid->rawbuf + 2, count);
-+ memcpy(buf, ihid->inbuf + 2, count);
-
- return count;
- }
-diff -Nur linux-3.12.38/drivers/hid/usbhid/hid-core.c linux-rpi/drivers/hid/usbhid/hid-core.c
---- linux-3.12.38/drivers/hid/usbhid/hid-core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/usbhid/hid-core.c 2015-03-10 17:26:50.314216693 +0100
-@@ -49,7 +49,7 @@
- * Module parameters.
- */
-
--static unsigned int hid_mousepoll_interval;
-+static unsigned int hid_mousepoll_interval = ~0;
- module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644);
- MODULE_PARM_DESC(mousepoll, "Polling interval of mice");
-
-@@ -1081,8 +1081,12 @@
- }
-
- /* Change the polling interval of mice. */
-- if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0)
-- interval = hid_mousepoll_interval;
-+ if (hid->collection->usage == HID_GD_MOUSE) {
-+ if (hid_mousepoll_interval == ~0 && interval < 16)
-+ interval = 16;
-+ else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0)
-+ interval = hid_mousepoll_interval;
-+ }
-
- ret = -ENOMEM;
- if (usb_endpoint_dir_in(endpoint)) {
-diff -Nur linux-3.12.38/drivers/hid/usbhid/hid-quirks.c linux-rpi/drivers/hid/usbhid/hid-quirks.c
---- linux-3.12.38/drivers/hid/usbhid/hid-quirks.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hid/usbhid/hid-quirks.c 2015-03-10 17:26:50.314216693 +0100
-@@ -119,7 +119,6 @@
- { USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_WIRELESS, HID_QUIRK_MULTI_INPUT },
- { USB_VENDOR_ID_SIGMA_MICRO, USB_DEVICE_ID_SIGMA_MICRO_KEYBOARD, HID_QUIRK_NO_INIT_REPORTS },
- { USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X, HID_QUIRK_MULTI_INPUT },
-- { USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_2, HID_QUIRK_MULTI_INPUT },
- { USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X, HID_QUIRK_MULTI_INPUT },
- { USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_DUOSENSE, HID_QUIRK_NO_INIT_REPORTS },
- { USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD, HID_QUIRK_NO_INIT_REPORTS },
-diff -Nur linux-3.12.38/drivers/hv/channel_mgmt.c linux-rpi/drivers/hv/channel_mgmt.c
---- linux-3.12.38/drivers/hv/channel_mgmt.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hv/channel_mgmt.c 2015-03-10 17:26:50.314216693 +0100
-@@ -202,16 +202,9 @@
- unsigned long flags;
- struct vmbus_channel *primary_channel;
- struct vmbus_channel_relid_released msg;
-- struct device *dev;
--
-- if (channel->device_obj) {
-- dev = get_device(&channel->device_obj->device);
-- if (dev) {
-- vmbus_device_unregister(channel->device_obj);
-- put_device(dev);
-- }
-- }
-
-+ if (channel->device_obj)
-+ vmbus_device_unregister(channel->device_obj);
- memset(&msg, 0, sizeof(struct vmbus_channel_relid_released));
- msg.child_relid = channel->offermsg.child_relid;
- msg.header.msgtype = CHANNELMSG_RELID_RELEASED;
-diff -Nur linux-3.12.38/drivers/hwmon/bcm2835-hwmon.c linux-rpi/drivers/hwmon/bcm2835-hwmon.c
---- linux-3.12.38/drivers/hwmon/bcm2835-hwmon.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/hwmon/bcm2835-hwmon.c 2015-03-09 10:39:30.290893736 +0100
-@@ -0,0 +1,219 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/hwmon.h>
-+#include <linux/hwmon-sysfs.h>
-+#include <linux/platform_device.h>
-+#include <linux/sysfs.h>
-+#include <mach/vcio.h>
-+#include <linux/slab.h>
-+#include <linux/err.h>
-+
-+#define MODULE_NAME "bcm2835_hwmon"
-+
-+/*#define HWMON_DEBUG_ENABLE*/
-+
-+#ifdef HWMON_DEBUG_ENABLE
-+#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+#define print_info(fmt,...) printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ##__VA_ARGS__)
-+
-+#define VC_TAG_GET_TEMP 0x00030006
-+#define VC_TAG_GET_MAX_TEMP 0x0003000A
-+
-+/* --- STRUCTS --- */
-+struct bcm2835_hwmon_data {
-+ struct device *hwmon_dev;
-+};
-+
-+/* tag part of the message */
-+struct vc_msg_tag {
-+ uint32_t tag_id; /* the tag ID for the temperature */
-+ uint32_t buffer_size; /* size of the buffer (should be 8) */
-+ uint32_t request_code; /* identifies message as a request (should be 0) */
-+ uint32_t id; /* extra ID field (should be 0) */
-+ uint32_t val; /* returned value of the temperature */
-+};
-+
-+/* message structure to be sent to videocore */
-+struct vc_msg {
-+ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */
-+ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */
-+ struct vc_msg_tag tag; /* the tag structure above to make */
-+ uint32_t end_tag; /* an end identifier, should be set to NULL */
-+};
-+
-+typedef enum {
-+ TEMP,
-+ MAX_TEMP,
-+} temp_type;
-+
-+/* --- PROTOTYPES --- */
-+static ssize_t bcm2835_get_temp(struct device *dev, struct device_attribute *attr, char *buf);
-+static ssize_t bcm2835_get_name(struct device *dev, struct device_attribute *attr, char *buf);
-+
-+/* --- GLOBALS --- */
-+
-+static struct bcm2835_hwmon_data *bcm2835_data;
-+static struct platform_driver bcm2835_hwmon_driver;
-+
-+static SENSOR_DEVICE_ATTR(name, S_IRUGO,bcm2835_get_name,NULL,0);
-+static SENSOR_DEVICE_ATTR(temp1_input,S_IRUGO,bcm2835_get_temp,NULL,TEMP);
-+static SENSOR_DEVICE_ATTR(temp1_max,S_IRUGO,bcm2835_get_temp,NULL,MAX_TEMP);
-+
-+static struct attribute* bcm2835_attributes[] = {
-+ &sensor_dev_attr_name.dev_attr.attr,
-+ &sensor_dev_attr_temp1_input.dev_attr.attr,
-+ &sensor_dev_attr_temp1_max.dev_attr.attr,
-+ NULL,
-+};
-+
-+static struct attribute_group bcm2835_attr_group = {
-+ .attrs = bcm2835_attributes,
-+};
-+
-+/* --- FUNCTIONS --- */
-+
-+static ssize_t bcm2835_get_name(struct device *dev, struct device_attribute *attr, char *buf)
-+{
-+ return sprintf(buf,"bcm2835_hwmon\n");
-+}
-+
-+static ssize_t bcm2835_get_temp(struct device *dev, struct device_attribute *attr, char *buf)
-+{
-+ struct vc_msg msg;
-+ int result;
-+ uint temp = 0;
-+ int index = ((struct sensor_device_attribute*)to_sensor_dev_attr(attr))->index;
-+
-+ print_debug("IN");
-+
-+ /* wipe all previous message data */
-+ memset(&msg, 0, sizeof msg);
-+
-+ /* determine the message type */
-+ if(index == TEMP)
-+ msg.tag.tag_id = VC_TAG_GET_TEMP;
-+ else if (index == MAX_TEMP)
-+ msg.tag.tag_id = VC_TAG_GET_MAX_TEMP;
-+ else
-+ {
-+ print_debug("Unknown temperature message!");
-+ return -EINVAL;
-+ }
-+
-+ msg.msg_size = sizeof msg;
-+ msg.tag.buffer_size = 8;
-+
-+ /* send the message */
-+ result = bcm_mailbox_property(&msg, sizeof msg);
-+
-+ /* check if it was all ok and return the rate in milli degrees C */
-+ if (result == 0 && (msg.request_code & 0x80000000))
-+ temp = (uint)msg.tag.val;
-+ #ifdef HWMON_DEBUG_ENABLE
-+ else
-+ print_debug("Failed to get temperature!");
-+ #endif
-+ print_debug("Got temperature as %u",temp);
-+ print_debug("OUT");
-+ return sprintf(buf, "%u\n", temp);
-+}
-+
-+
-+static int bcm2835_hwmon_probe(struct platform_device *pdev)
-+{
-+ int err;
-+
-+ print_debug("IN");
-+ print_debug("HWMON Driver has been probed!");
-+
-+ /* check that the device isn't null!*/
-+ if(pdev == NULL)
-+ {
-+ print_debug("Platform device is empty!");
-+ return -ENODEV;
-+ }
-+
-+ /* allocate memory for neccessary data */
-+ bcm2835_data = kzalloc(sizeof(struct bcm2835_hwmon_data),GFP_KERNEL);
-+ if(!bcm2835_data)
-+ {
-+ print_debug("Unable to allocate memory for hwmon data!");
-+ err = -ENOMEM;
-+ goto kzalloc_error;
-+ }
-+
-+ /* create the sysfs files */
-+ if(sysfs_create_group(&pdev->dev.kobj, &bcm2835_attr_group))
-+ {
-+ print_debug("Unable to create sysfs files!");
-+ err = -EFAULT;
-+ goto sysfs_error;
-+ }
-+
-+ /* register the hwmon device */
-+ bcm2835_data->hwmon_dev = hwmon_device_register(&pdev->dev);
-+ if (IS_ERR(bcm2835_data->hwmon_dev))
-+ {
-+ err = PTR_ERR(bcm2835_data->hwmon_dev);
-+ goto hwmon_error;
-+ }
-+ print_debug("OUT");
-+ return 0;
-+
-+ /* error goto's */
-+ hwmon_error:
-+ sysfs_remove_group(&pdev->dev.kobj, &bcm2835_attr_group);
-+
-+ sysfs_error:
-+ kfree(bcm2835_data);
-+
-+ kzalloc_error:
-+
-+ return err;
-+
-+}
-+
-+static int bcm2835_hwmon_remove(struct platform_device *pdev)
-+{
-+ print_debug("IN");
-+ hwmon_device_unregister(bcm2835_data->hwmon_dev);
-+
-+ sysfs_remove_group(&pdev->dev.kobj, &bcm2835_attr_group);
-+ print_debug("OUT");
-+ return 0;
-+}
-+
-+/* Hwmon Driver */
-+static struct platform_driver bcm2835_hwmon_driver = {
-+ .probe = bcm2835_hwmon_probe,
-+ .remove = bcm2835_hwmon_remove,
-+ .driver = {
-+ .name = "bcm2835_hwmon",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Dorian Peake");
-+MODULE_DESCRIPTION("HW Monitor driver for bcm2835 chip");
-+
-+module_platform_driver(bcm2835_hwmon_driver);
-diff -Nur linux-3.12.38/drivers/hwmon/Kconfig linux-rpi/drivers/hwmon/Kconfig
---- linux-3.12.38/drivers/hwmon/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hwmon/Kconfig 2015-03-10 17:26:50.314216693 +0100
-@@ -1553,6 +1553,16 @@
- help
- Support for the A/D converter on MC13783 and MC13892 PMIC.
-
-+config SENSORS_BCM2835
-+ depends on THERMAL_BCM2835=n
-+ tristate "Broadcom BCM2835 HWMON Driver"
-+ help
-+ If you say yes here you get support for the hardware
-+ monitoring features of the BCM2835 Chip
-+
-+ This driver can also be built as a module. If so, the module
-+ will be called bcm2835-hwmon.
-+
- if ACPI
-
- comment "ACPI drivers"
-diff -Nur linux-3.12.38/drivers/hwmon/Makefile linux-rpi/drivers/hwmon/Makefile
---- linux-3.12.38/drivers/hwmon/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/hwmon/Makefile 2015-03-10 17:26:50.314216693 +0100
-@@ -142,6 +142,7 @@
- obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
- obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o
- obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o
-+obj-$(CONFIG_SENSORS_BCM2835) += bcm2835-hwmon.o
-
- obj-$(CONFIG_PMBUS) += pmbus/
-
-diff -Nur linux-3.12.38/drivers/i2c/busses/i2c-bcm2708.c linux-rpi/drivers/i2c/busses/i2c-bcm2708.c
---- linux-3.12.38/drivers/i2c/busses/i2c-bcm2708.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/i2c/busses/i2c-bcm2708.c 2015-03-10 17:26:50.334216693 +0100
-@@ -0,0 +1,489 @@
-+/*
-+ * Driver for Broadcom BCM2708 BSC Controllers
-+ *
-+ * Copyright (C) 2012 Chris Boot & Frank Buss
-+ *
-+ * This driver is inspired by:
-+ * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/slab.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+
-+/* BSC register offsets */
-+#define BSC_C 0x00
-+#define BSC_S 0x04
-+#define BSC_DLEN 0x08
-+#define BSC_A 0x0c
-+#define BSC_FIFO 0x10
-+#define BSC_DIV 0x14
-+#define BSC_DEL 0x18
-+#define BSC_CLKT 0x1c
-+
-+/* Bitfields in BSC_C */
-+#define BSC_C_I2CEN 0x00008000
-+#define BSC_C_INTR 0x00000400
-+#define BSC_C_INTT 0x00000200
-+#define BSC_C_INTD 0x00000100
-+#define BSC_C_ST 0x00000080
-+#define BSC_C_CLEAR_1 0x00000020
-+#define BSC_C_CLEAR_2 0x00000010
-+#define BSC_C_READ 0x00000001
-+
-+/* Bitfields in BSC_S */
-+#define BSC_S_CLKT 0x00000200
-+#define BSC_S_ERR 0x00000100
-+#define BSC_S_RXF 0x00000080
-+#define BSC_S_TXE 0x00000040
-+#define BSC_S_RXD 0x00000020
-+#define BSC_S_TXD 0x00000010
-+#define BSC_S_RXR 0x00000008
-+#define BSC_S_TXW 0x00000004
-+#define BSC_S_DONE 0x00000002
-+#define BSC_S_TA 0x00000001
-+
-+#define I2C_TIMEOUT_MS 150
-+#define I2C_WAIT_LOOP_COUNT 40
-+
-+#define DRV_NAME "bcm2708_i2c"
-+
-+static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE;
-+module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(baudrate, "The I2C baudrate");
-+
-+static bool combined = false;
-+module_param(combined, bool, 0644);
-+MODULE_PARM_DESC(combined, "Use combined transactions");
-+
-+struct bcm2708_i2c {
-+ struct i2c_adapter adapter;
-+
-+ spinlock_t lock;
-+ void __iomem *base;
-+ int irq;
-+ struct clk *clk;
-+ u32 cdiv;
-+
-+ struct completion done;
-+
-+ struct i2c_msg *msg;
-+ int pos;
-+ int nmsgs;
-+ bool error;
-+};
-+
-+/*
-+ * This function sets the ALT mode on the I2C pins so that we can use them with
-+ * the BSC hardware.
-+ *
-+ * FIXME: This is a hack. Use pinmux / pinctrl.
-+ */
-+static void bcm2708_i2c_init_pinmode(int id)
-+{
-+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
-+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
-+
-+ int pin;
-+ u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
-+
-+ BUG_ON(id != 0 && id != 1);
-+ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */
-+ for (pin = id*2+0; pin <= id*2+1; pin++) {
-+ printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin);
-+ INP_GPIO(pin); /* set mode to GPIO input first */
-+ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
-+ }
-+
-+ iounmap(gpio);
-+
-+#undef INP_GPIO
-+#undef SET_GPIO_ALT
-+}
-+
-+static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
-+{
-+ return readl(bi->base + reg);
-+}
-+
-+static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
-+{
-+ writel(val, bi->base + reg);
-+}
-+
-+static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
-+{
-+ bcm2708_wr(bi, BSC_C, 0);
-+ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
-+}
-+
-+static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
-+{
-+ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len))
-+ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
-+}
-+
-+static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
-+{
-+ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len))
-+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
-+}
-+
-+static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi)
-+{
-+ u32 cdiv, s;
-+ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
-+ int wait_loops = I2C_WAIT_LOOP_COUNT;
-+
-+ /* Can't call clk_get_rate as it locks a mutex and here we are spinlocked.
-+ * Use the value that we cached in the probe.
-+ */
-+ cdiv = bi->cdiv;
-+
-+ if (bi->msg->flags & I2C_M_RD)
-+ c |= BSC_C_INTR | BSC_C_READ;
-+ else
-+ c |= BSC_C_INTT;
-+
-+ bcm2708_wr(bi, BSC_DIV, cdiv);
-+ bcm2708_wr(bi, BSC_A, bi->msg->addr);
-+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
-+ if (combined)
-+ {
-+ /* Do the next two messages meet combined transaction criteria?
-+ - Current message is a write, next message is a read
-+ - Both messages to same slave address
-+ - Write message can fit inside FIFO (16 bytes or less) */
-+ if ( (bi->nmsgs > 1) &&
-+ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) &&
-+ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) {
-+ /* Fill FIFO with entire write message (16 byte FIFO) */
-+ while (bi->pos < bi->msg->len) {
-+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
-+ }
-+ /* Start write transfer (no interrupts, don't clear FIFO) */
-+ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST);
-+
-+ /* poll for transfer start bit (should only take 1-20 polls) */
-+ do {
-+ s = bcm2708_rd(bi, BSC_S);
-+ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0);
-+
-+ /* did we time out or some error occured? */
-+ if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) {
-+ return -1;
-+ }
-+
-+ /* Send next read message before the write transfer finishes. */
-+ bi->nmsgs--;
-+ bi->msg++;
-+ bi->pos = 0;
-+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
-+ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ;
-+ }
-+ }
-+ bcm2708_wr(bi, BSC_C, c);
-+
-+ return 0;
-+}
-+
-+static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
-+{
-+ struct bcm2708_i2c *bi = dev_id;
-+ bool handled = true;
-+ u32 s;
-+ int ret;
-+
-+ spin_lock(&bi->lock);
-+
-+ /* we may see camera interrupts on the "other" I2C channel
-+ Just return if we've not sent anything */
-+ if (!bi->nmsgs || !bi->msg) {
-+ goto early_exit;
-+ }
-+
-+ s = bcm2708_rd(bi, BSC_S);
-+
-+ if (s & (BSC_S_CLKT | BSC_S_ERR)) {
-+ bcm2708_bsc_reset(bi);
-+ bi->error = true;
-+
-+ bi->msg = 0; /* to inform the that all work is done */
-+ bi->nmsgs = 0;
-+ /* wake up our bh */
-+ complete(&bi->done);
-+ } else if (s & BSC_S_DONE) {
-+ bi->nmsgs--;
-+
-+ if (bi->msg->flags & I2C_M_RD) {
-+ bcm2708_bsc_fifo_drain(bi);
-+ }
-+
-+ bcm2708_bsc_reset(bi);
-+
-+ if (bi->nmsgs) {
-+ /* advance to next message */
-+ bi->msg++;
-+ bi->pos = 0;
-+ ret = bcm2708_bsc_setup(bi);
-+ if (ret < 0) {
-+ bcm2708_bsc_reset(bi);
-+ bi->error = true;
-+ bi->msg = 0; /* to inform the that all work is done */
-+ bi->nmsgs = 0;
-+ /* wake up our bh */
-+ complete(&bi->done);
-+ goto early_exit;
-+ }
-+ } else {
-+ bi->msg = 0; /* to inform the that all work is done */
-+ bi->nmsgs = 0;
-+ /* wake up our bh */
-+ complete(&bi->done);
-+ }
-+ } else if (s & BSC_S_TXW) {
-+ bcm2708_bsc_fifo_fill(bi);
-+ } else if (s & BSC_S_RXR) {
-+ bcm2708_bsc_fifo_drain(bi);
-+ } else {
-+ handled = false;
-+ }
-+
-+early_exit:
-+ spin_unlock(&bi->lock);
-+
-+ return handled ? IRQ_HANDLED : IRQ_NONE;
-+}
-+
-+static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
-+ struct i2c_msg *msgs, int num)
-+{
-+ struct bcm2708_i2c *bi = adap->algo_data;
-+ unsigned long flags;
-+ int ret;
-+
-+ spin_lock_irqsave(&bi->lock, flags);
-+
-+ INIT_COMPLETION(bi->done);
-+ bi->msg = msgs;
-+ bi->pos = 0;
-+ bi->nmsgs = num;
-+ bi->error = false;
-+
-+ ret = bcm2708_bsc_setup(bi);
-+
-+ spin_unlock_irqrestore(&bi->lock, flags);
-+
-+ /* check the result of the setup */
-+ if (ret < 0)
-+ {
-+ dev_err(&adap->dev, "transfer setup timed out\n");
-+ goto error_timeout;
-+ }
-+
-+ ret = wait_for_completion_timeout(&bi->done, msecs_to_jiffies(I2C_TIMEOUT_MS));
-+ if (ret == 0) {
-+ dev_err(&adap->dev, "transfer timed out\n");
-+ goto error_timeout;
-+ }
-+
-+ ret = bi->error ? -EIO : num;
-+ return ret;
-+
-+error_timeout:
-+ spin_lock_irqsave(&bi->lock, flags);
-+ bcm2708_bsc_reset(bi);
-+ bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */
-+ bi->nmsgs = 0;
-+ spin_unlock_irqrestore(&bi->lock, flags);
-+ return -ETIMEDOUT;
-+}
-+
-+static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
-+{
-+ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static struct i2c_algorithm bcm2708_i2c_algorithm = {
-+ .master_xfer = bcm2708_i2c_master_xfer,
-+ .functionality = bcm2708_i2c_functionality,
-+};
-+
-+static int bcm2708_i2c_probe(struct platform_device *pdev)
-+{
-+ struct resource *regs;
-+ int irq, err = -ENOMEM;
-+ struct clk *clk;
-+ struct bcm2708_i2c *bi;
-+ struct i2c_adapter *adap;
-+ unsigned long bus_hz;
-+ u32 cdiv;
-+
-+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!regs) {
-+ dev_err(&pdev->dev, "could not get IO memory\n");
-+ return -ENXIO;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "could not get IRQ\n");
-+ return irq;
-+ }
-+
-+ clk = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
-+ return PTR_ERR(clk);
-+ }
-+
-+ bcm2708_i2c_init_pinmode(pdev->id);
-+
-+ bi = kzalloc(sizeof(*bi), GFP_KERNEL);
-+ if (!bi)
-+ goto out_clk_put;
-+
-+ platform_set_drvdata(pdev, bi);
-+
-+ adap = &bi->adapter;
-+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
-+ adap->algo = &bcm2708_i2c_algorithm;
-+ adap->algo_data = bi;
-+ adap->dev.parent = &pdev->dev;
-+ adap->nr = pdev->id;
-+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+
-+ switch (pdev->id) {
-+ case 0:
-+ adap->class = I2C_CLASS_HWMON;
-+ break;
-+ case 1:
-+ adap->class = I2C_CLASS_DDC;
-+ break;
-+ default:
-+ dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n");
-+ err = -ENXIO;
-+ goto out_free_bi;
-+ }
-+
-+ spin_lock_init(&bi->lock);
-+ init_completion(&bi->done);
-+
-+ bi->base = ioremap(regs->start, resource_size(regs));
-+ if (!bi->base) {
-+ dev_err(&pdev->dev, "could not remap memory\n");
-+ goto out_free_bi;
-+ }
-+
-+ bi->irq = irq;
-+ bi->clk = clk;
-+
-+ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
-+ dev_name(&pdev->dev), bi);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
-+ goto out_iounmap;
-+ }
-+
-+ bcm2708_bsc_reset(bi);
-+
-+ err = i2c_add_numbered_adapter(adap);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
-+ goto out_free_irq;
-+ }
-+
-+ bus_hz = clk_get_rate(bi->clk);
-+ cdiv = bus_hz / baudrate;
-+ if (cdiv > 0xffff) {
-+ cdiv = 0xffff;
-+ baudrate = bus_hz / cdiv;
-+ }
-+ bi->cdiv = cdiv;
-+
-+ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
-+ pdev->id, (unsigned long)regs->start, irq, baudrate);
-+
-+ return 0;
-+
-+out_free_irq:
-+ free_irq(bi->irq, bi);
-+out_iounmap:
-+ iounmap(bi->base);
-+out_free_bi:
-+ kfree(bi);
-+out_clk_put:
-+ clk_put(clk);
-+ return err;
-+}
-+
-+static int bcm2708_i2c_remove(struct platform_device *pdev)
-+{
-+ struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+
-+ i2c_del_adapter(&bi->adapter);
-+ free_irq(bi->irq, bi);
-+ iounmap(bi->base);
-+ clk_disable(bi->clk);
-+ clk_put(bi->clk);
-+ kfree(bi);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm2708_i2c_driver = {
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = bcm2708_i2c_probe,
-+ .remove = bcm2708_i2c_remove,
-+};
-+
-+// module_platform_driver(bcm2708_i2c_driver);
-+
-+
-+static int __init bcm2708_i2c_init(void)
-+{
-+ return platform_driver_register(&bcm2708_i2c_driver);
-+}
-+
-+static void __exit bcm2708_i2c_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_i2c_driver);
-+}
-+
-+module_init(bcm2708_i2c_init);
-+module_exit(bcm2708_i2c_exit);
-+
-+
-+
-+MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
-+MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRV_NAME);
-diff -Nur linux-3.12.38/drivers/i2c/busses/i2c-s3c2410.c linux-rpi/drivers/i2c/busses/i2c-s3c2410.c
---- linux-3.12.38/drivers/i2c/busses/i2c-s3c2410.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/i2c/busses/i2c-s3c2410.c 2015-03-10 17:26:50.338216693 +0100
-@@ -711,16 +711,14 @@
- int ret;
-
- pm_runtime_get_sync(&adap->dev);
-- ret = clk_enable(i2c->clk);
-- if (ret)
-- return ret;
-+ clk_prepare_enable(i2c->clk);
-
- for (retry = 0; retry < adap->retries; retry++) {
-
- ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
-
- if (ret != -EAGAIN) {
-- clk_disable(i2c->clk);
-+ clk_disable_unprepare(i2c->clk);
- pm_runtime_put(&adap->dev);
- return ret;
- }
-@@ -730,7 +728,7 @@
- udelay(100);
- }
-
-- clk_disable(i2c->clk);
-+ clk_disable_unprepare(i2c->clk);
- pm_runtime_put(&adap->dev);
- return -EREMOTEIO;
- }
-@@ -1110,7 +1108,7 @@
-
- clk_prepare_enable(i2c->clk);
- ret = s3c24xx_i2c_init(i2c);
-- clk_disable(i2c->clk);
-+ clk_disable_unprepare(i2c->clk);
- if (ret != 0) {
- dev_err(&pdev->dev, "I2C controller init failed\n");
- return ret;
-@@ -1122,7 +1120,6 @@
- i2c->irq = ret = platform_get_irq(pdev, 0);
- if (ret <= 0) {
- dev_err(&pdev->dev, "cannot find IRQ\n");
-- clk_unprepare(i2c->clk);
- return ret;
- }
-
-@@ -1131,14 +1128,12 @@
-
- if (ret != 0) {
- dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
-- clk_unprepare(i2c->clk);
- return ret;
- }
-
- ret = s3c24xx_i2c_register_cpufreq(i2c);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
-- clk_unprepare(i2c->clk);
- return ret;
- }
-
-@@ -1155,7 +1150,6 @@
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to add bus to i2c core\n");
- s3c24xx_i2c_deregister_cpufreq(i2c);
-- clk_unprepare(i2c->clk);
- return ret;
- }
-
-@@ -1177,8 +1171,6 @@
- {
- struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
-
-- clk_unprepare(i2c->clk);
--
- pm_runtime_disable(&i2c->adap.dev);
- pm_runtime_disable(&pdev->dev);
-
-@@ -1207,13 +1199,10 @@
- {
- struct platform_device *pdev = to_platform_device(dev);
- struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
-- int ret;
-
-- ret = clk_enable(i2c->clk);
-- if (ret)
-- return ret;
-+ clk_prepare_enable(i2c->clk);
- s3c24xx_i2c_init(i2c);
-- clk_disable(i2c->clk);
-+ clk_disable_unprepare(i2c->clk);
- i2c->suspended = 0;
-
- return 0;
-diff -Nur linux-3.12.38/drivers/i2c/busses/Kconfig linux-rpi/drivers/i2c/busses/Kconfig
---- linux-3.12.38/drivers/i2c/busses/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/i2c/busses/Kconfig 2015-03-10 17:26:50.334216693 +0100
-@@ -348,6 +348,25 @@
- This support is also available as a module. If so, the module
- will be called i2c-bcm2835.
-
-+config I2C_BCM2708
-+ tristate "BCM2708 BSC"
-+ depends on MACH_BCM2708
-+ help
-+ Enabling this option will add BSC (Broadcom Serial Controller)
-+ support for the BCM2708. BSC is a Broadcom proprietary bus compatible
-+ with I2C/TWI/SMBus.
-+
-+config I2C_BCM2708_BAUDRATE
-+ prompt "BCM2708 I2C baudrate"
-+ depends on I2C_BCM2708
-+ int
-+ default 100000
-+ help
-+ Set the I2C baudrate. This will alter the default value. A
-+ different baudrate can be set by using a module parameter as well. If
-+ no parameter is provided when loading, this is the value that will be
-+ used.
-+
- config I2C_BLACKFIN_TWI
- tristate "Blackfin TWI I2C support"
- depends on BLACKFIN
-diff -Nur linux-3.12.38/drivers/i2c/busses/Makefile linux-rpi/drivers/i2c/busses/Makefile
---- linux-3.12.38/drivers/i2c/busses/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/i2c/busses/Makefile 2015-03-10 17:26:50.334216693 +0100
-@@ -32,6 +32,7 @@
- obj-$(CONFIG_I2C_AT91) += i2c-at91.o
- obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
- obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
-+obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o
- obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
- obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
- obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
-diff -Nur linux-3.12.38/drivers/infiniband/ulp/isert/ib_isert.c linux-rpi/drivers/infiniband/ulp/isert/ib_isert.c
---- linux-3.12.38/drivers/infiniband/ulp/isert/ib_isert.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/infiniband/ulp/isert/ib_isert.c 2015-03-10 17:26:50.374216693 +0100
-@@ -40,7 +40,6 @@
- static LIST_HEAD(device_list);
- static struct workqueue_struct *isert_rx_wq;
- static struct workqueue_struct *isert_comp_wq;
--static struct workqueue_struct *isert_release_wq;
-
- static void
- isert_unmap_cmd(struct isert_cmd *isert_cmd, struct isert_conn *isert_conn);
-@@ -52,11 +51,6 @@
- static int
- isert_reg_rdma_frwr(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
- struct isert_rdma_wr *wr);
--static int
--isert_rdma_post_recvl(struct isert_conn *isert_conn);
--static int
--isert_rdma_accept(struct isert_conn *isert_conn);
--struct rdma_cm_id *isert_setup_id(struct isert_np *isert_np);
-
- static void
- isert_qp_event_callback(struct ib_event *e, void *context)
-@@ -137,18 +131,12 @@
- ret = rdma_create_qp(cma_id, isert_conn->conn_pd, &attr);
- if (ret) {
- pr_err("rdma_create_qp failed for cma_id %d\n", ret);
-- goto err;
-+ return ret;
- }
- isert_conn->conn_qp = cma_id->qp;
- pr_debug("rdma_create_qp() returned success >>>>>>>>>>>>>>>>>>>>>>>>>.\n");
-
- return 0;
--err:
-- mutex_lock(&device_list_mutex);
-- device->cq_active_qps[min_index]--;
-- mutex_unlock(&device_list_mutex);
--
-- return ret;
- }
-
- static void
-@@ -505,8 +493,8 @@
- static int
- isert_connect_request(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
- {
-- struct isert_np *isert_np = cma_id->context;
-- struct iscsi_np *np = isert_np->np;
-+ struct iscsi_np *np = cma_id->context;
-+ struct isert_np *isert_np = np->np_context;
- struct isert_conn *isert_conn;
- struct isert_device *device;
- struct ib_device *ib_dev = cma_id->device;
-@@ -531,7 +519,6 @@
- isert_conn->state = ISER_CONN_INIT;
- INIT_LIST_HEAD(&isert_conn->conn_accept_node);
- init_completion(&isert_conn->conn_login_comp);
-- init_completion(&isert_conn->login_req_comp);
- init_completion(&isert_conn->conn_wait);
- init_completion(&isert_conn->conn_wait_comp_err);
- kref_init(&isert_conn->conn_kref);
-@@ -539,6 +526,7 @@
- spin_lock_init(&isert_conn->conn_lock);
- INIT_LIST_HEAD(&isert_conn->conn_frwr_pool);
-
-+ cma_id->context = isert_conn;
- isert_conn->conn_cm_id = cma_id;
- isert_conn->responder_resources = event->param.conn.responder_resources;
- isert_conn->initiator_depth = event->param.conn.initiator_depth;
-@@ -598,14 +586,6 @@
- if (ret)
- goto out_conn_dev;
-
-- ret = isert_rdma_post_recvl(isert_conn);
-- if (ret)
-- goto out_conn_dev;
--
-- ret = isert_rdma_accept(isert_conn);
-- if (ret)
-- goto out_conn_dev;
--
- mutex_lock(&isert_np->np_accept_mutex);
- list_add_tail(&isert_conn->conn_accept_node, &isert_np->np_accept_list);
- mutex_unlock(&isert_np->np_accept_mutex);
-@@ -626,7 +606,6 @@
- kfree(isert_conn->login_buf);
- out:
- kfree(isert_conn);
-- rdma_reject(cma_id, NULL, 0);
- return ret;
- }
-
-@@ -642,20 +621,18 @@
- if (device && device->use_frwr)
- isert_conn_free_frwr_pool(isert_conn);
-
-- isert_free_rx_descriptors(isert_conn);
-- rdma_destroy_id(isert_conn->conn_cm_id);
--
- if (isert_conn->conn_qp) {
- cq_index = ((struct isert_cq_desc *)
- isert_conn->conn_qp->recv_cq->cq_context)->cq_index;
- pr_debug("isert_connect_release: cq_index: %d\n", cq_index);
-- mutex_lock(&device_list_mutex);
- isert_conn->conn_device->cq_active_qps[cq_index]--;
-- mutex_unlock(&device_list_mutex);
-
-- ib_destroy_qp(isert_conn->conn_qp);
-+ rdma_destroy_qp(isert_conn->conn_cm_id);
- }
-
-+ isert_free_rx_descriptors(isert_conn);
-+ rdma_destroy_id(isert_conn->conn_cm_id);
-+
- if (isert_conn->login_buf) {
- ib_dma_unmap_single(ib_dev, isert_conn->login_rsp_dma,
- ISER_RX_LOGIN_SIZE, DMA_TO_DEVICE);
-@@ -675,19 +652,9 @@
- static void
- isert_connected_handler(struct rdma_cm_id *cma_id)
- {
-- struct isert_conn *isert_conn = cma_id->qp->qp_context;
--
-- pr_info("conn %p\n", isert_conn);
--
-- if (!kref_get_unless_zero(&isert_conn->conn_kref)) {
-- pr_warn("conn %p connect_release is running\n", isert_conn);
-- return;
-- }
-+ struct isert_conn *isert_conn = cma_id->context;
-
-- mutex_lock(&isert_conn->conn_mutex);
-- if (isert_conn->state != ISER_CONN_FULL_FEATURE)
-- isert_conn->state = ISER_CONN_UP;
-- mutex_unlock(&isert_conn->conn_mutex);
-+ kref_get(&isert_conn->conn_kref);
- }
-
- static void
-@@ -708,108 +675,65 @@
- kref_put(&isert_conn->conn_kref, isert_release_conn_kref);
- }
-
--/**
-- * isert_conn_terminate() - Initiate connection termination
-- * @isert_conn: isert connection struct
-- *
-- * Notes:
-- * In case the connection state is FULL_FEATURE, move state
-- * to TEMINATING and start teardown sequence (rdma_disconnect).
-- * In case the connection state is UP, complete flush as well.
-- *
-- * This routine must be called with conn_mutex held. Thus it is
-- * safe to call multiple times.
-- */
- static void
--isert_conn_terminate(struct isert_conn *isert_conn)
-+isert_disconnect_work(struct work_struct *work)
- {
-- int err;
-+ struct isert_conn *isert_conn = container_of(work,
-+ struct isert_conn, conn_logout_work);
-
-- switch (isert_conn->state) {
-- case ISER_CONN_TERMINATING:
-- break;
-- case ISER_CONN_UP:
-- /*
-- * No flush completions will occur as we didn't
-- * get to ISER_CONN_FULL_FEATURE yet, complete
-- * to allow teardown progress.
-- */
-- complete(&isert_conn->conn_wait_comp_err);
-- case ISER_CONN_FULL_FEATURE: /* FALLTHRU */
-- pr_info("Terminating conn %p state %d\n",
-- isert_conn, isert_conn->state);
-+ pr_debug("isert_disconnect_work(): >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
-+ mutex_lock(&isert_conn->conn_mutex);
-+ if (isert_conn->state == ISER_CONN_UP)
- isert_conn->state = ISER_CONN_TERMINATING;
-- err = rdma_disconnect(isert_conn->conn_cm_id);
-- if (err)
-- pr_warn("Failed rdma_disconnect isert_conn %p\n",
-- isert_conn);
-- break;
-- default:
-- pr_warn("conn %p teminating in state %d\n",
-- isert_conn, isert_conn->state);
-- }
--}
-
--static int
--isert_np_cma_handler(struct isert_np *isert_np,
-- enum rdma_cm_event_type event)
--{
-- pr_debug("isert np %p, handling event %d\n", isert_np, event);
-+ if (isert_conn->post_recv_buf_count == 0 &&
-+ atomic_read(&isert_conn->post_send_buf_count) == 0) {
-+ mutex_unlock(&isert_conn->conn_mutex);
-+ goto wake_up;
-+ }
-+ if (!isert_conn->conn_cm_id) {
-+ mutex_unlock(&isert_conn->conn_mutex);
-+ isert_put_conn(isert_conn);
-+ return;
-+ }
-
-- switch (event) {
-- case RDMA_CM_EVENT_DEVICE_REMOVAL:
-- isert_np->np_cm_id = NULL;
-- break;
-- case RDMA_CM_EVENT_ADDR_CHANGE:
-- isert_np->np_cm_id = isert_setup_id(isert_np);
-- if (IS_ERR(isert_np->np_cm_id)) {
-- pr_err("isert np %p setup id failed: %ld\n",
-- isert_np, PTR_ERR(isert_np->np_cm_id));
-- isert_np->np_cm_id = NULL;
-- }
-- break;
-- default:
-- pr_err("isert np %p Unexpected event %d\n",
-- isert_np, event);
-+ if (isert_conn->disconnect) {
-+ /* Send DREQ/DREP towards our initiator */
-+ rdma_disconnect(isert_conn->conn_cm_id);
- }
-
-- return -1;
-+ mutex_unlock(&isert_conn->conn_mutex);
-+
-+wake_up:
-+ complete(&isert_conn->conn_wait);
- }
-
- static int
--isert_disconnected_handler(struct rdma_cm_id *cma_id,
-- enum rdma_cm_event_type event)
-+isert_disconnected_handler(struct rdma_cm_id *cma_id, bool disconnect)
- {
-- struct isert_np *isert_np = cma_id->context;
- struct isert_conn *isert_conn;
-
-- if (isert_np->np_cm_id == cma_id)
-- return isert_np_cma_handler(cma_id->context, event);
-+ if (!cma_id->qp) {
-+ struct isert_np *isert_np = cma_id->context;
-
-- isert_conn = cma_id->qp->qp_context;
-+ isert_np->np_cm_id = NULL;
-+ return -1;
-+ }
-
-- mutex_lock(&isert_conn->conn_mutex);
-- isert_conn_terminate(isert_conn);
-- mutex_unlock(&isert_conn->conn_mutex);
-+ isert_conn = (struct isert_conn *)cma_id->context;
-
-- pr_info("conn %p completing conn_wait\n", isert_conn);
-- complete(&isert_conn->conn_wait);
-+ isert_conn->disconnect = disconnect;
-+ INIT_WORK(&isert_conn->conn_logout_work, isert_disconnect_work);
-+ schedule_work(&isert_conn->conn_logout_work);
-
- return 0;
- }
-
--static void
--isert_connect_error(struct rdma_cm_id *cma_id)
--{
-- struct isert_conn *isert_conn = cma_id->qp->qp_context;
--
-- isert_put_conn(isert_conn);
--}
--
- static int
- isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
- {
- int ret = 0;
-+ bool disconnect = false;
-
- pr_debug("isert_cma_handler: event %d status %d conn %p id %p\n",
- event->event, event->status, cma_id->context, cma_id);
-@@ -827,14 +751,11 @@
- case RDMA_CM_EVENT_ADDR_CHANGE: /* FALLTHRU */
- case RDMA_CM_EVENT_DISCONNECTED: /* FALLTHRU */
- case RDMA_CM_EVENT_DEVICE_REMOVAL: /* FALLTHRU */
-+ disconnect = true;
- case RDMA_CM_EVENT_TIMEWAIT_EXIT: /* FALLTHRU */
-- ret = isert_disconnected_handler(cma_id, event->event);
-+ ret = isert_disconnected_handler(cma_id, disconnect);
- break;
-- case RDMA_CM_EVENT_REJECTED: /* FALLTHRU */
-- case RDMA_CM_EVENT_UNREACHABLE: /* FALLTHRU */
- case RDMA_CM_EVENT_CONNECT_ERROR:
-- isert_connect_error(cma_id);
-- break;
- default:
- pr_err("Unhandled RDMA CMA event: %d\n", event->event);
- break;
-@@ -1045,10 +966,7 @@
- if (ret)
- return ret;
-
-- /* Now we are in FULL_FEATURE phase */
-- mutex_lock(&isert_conn->conn_mutex);
-- isert_conn->state = ISER_CONN_FULL_FEATURE;
-- mutex_unlock(&isert_conn->conn_mutex);
-+ isert_conn->state = ISER_CONN_UP;
- goto post_send;
- }
-
-@@ -1065,17 +983,18 @@
- }
-
- static void
--isert_rx_login_req(struct isert_conn *isert_conn)
-+isert_rx_login_req(struct iser_rx_desc *rx_desc, int rx_buflen,
-+ struct isert_conn *isert_conn)
- {
-- struct iser_rx_desc *rx_desc = (void *)isert_conn->login_req_buf;
-- int rx_buflen = isert_conn->login_req_len;
- struct iscsi_conn *conn = isert_conn->conn;
- struct iscsi_login *login = conn->conn_login;
- int size;
-
-- pr_info("conn %p\n", isert_conn);
--
-- WARN_ON_ONCE(!login);
-+ if (!login) {
-+ pr_err("conn->conn_login is NULL\n");
-+ dump_stack();
-+ return;
-+ }
-
- if (login->first_request) {
- struct iscsi_login_req *login_req =
-@@ -1438,20 +1357,11 @@
- hdr->opcode, hdr->itt, hdr->flags,
- (int)(xfer_len - ISER_HEADERS_LEN));
-
-- if ((char *)desc == isert_conn->login_req_buf) {
-- isert_conn->login_req_len = xfer_len - ISER_HEADERS_LEN;
-- if (isert_conn->conn) {
-- struct iscsi_login *login = isert_conn->conn->conn_login;
--
-- if (login && !login->first_request)
-- isert_rx_login_req(isert_conn);
-- }
-- mutex_lock(&isert_conn->conn_mutex);
-- complete(&isert_conn->login_req_comp);
-- mutex_unlock(&isert_conn->conn_mutex);
-- } else {
-+ if ((char *)desc == isert_conn->login_req_buf)
-+ isert_rx_login_req(desc, xfer_len - ISER_HEADERS_LEN,
-+ isert_conn);
-+ else
- isert_rx_do_work(desc, isert_conn);
-- }
-
- ib_dma_sync_single_for_device(ib_dev, rx_dma, rx_buflen,
- DMA_FROM_DEVICE);
-@@ -1796,7 +1706,7 @@
- msleep(3000);
-
- mutex_lock(&isert_conn->conn_mutex);
-- isert_conn_terminate(isert_conn);
-+ isert_conn->state = ISER_CONN_DOWN;
- mutex_unlock(&isert_conn->conn_mutex);
-
- iscsit_cause_connection_reinstatement(isert_conn->conn, 0);
-@@ -2576,51 +2486,13 @@
- return ret;
- }
-
--struct rdma_cm_id *
--isert_setup_id(struct isert_np *isert_np)
--{
-- struct iscsi_np *np = isert_np->np;
-- struct rdma_cm_id *id;
-- struct sockaddr *sa;
-- int ret;
--
-- sa = (struct sockaddr *)&np->np_sockaddr;
-- pr_debug("ksockaddr: %p, sa: %p\n", &np->np_sockaddr, sa);
--
-- id = rdma_create_id(isert_cma_handler, isert_np,
-- RDMA_PS_TCP, IB_QPT_RC);
-- if (IS_ERR(id)) {
-- pr_err("rdma_create_id() failed: %ld\n", PTR_ERR(id));
-- ret = PTR_ERR(id);
-- goto out;
-- }
-- pr_debug("id %p context %p\n", id, id->context);
--
-- ret = rdma_bind_addr(id, sa);
-- if (ret) {
-- pr_err("rdma_bind_addr() failed: %d\n", ret);
-- goto out_id;
-- }
--
-- ret = rdma_listen(id, ISERT_RDMA_LISTEN_BACKLOG);
-- if (ret) {
-- pr_err("rdma_listen() failed: %d\n", ret);
-- goto out_id;
-- }
--
-- return id;
--out_id:
-- rdma_destroy_id(id);
--out:
-- return ERR_PTR(ret);
--}
--
- static int
- isert_setup_np(struct iscsi_np *np,
- struct __kernel_sockaddr_storage *ksockaddr)
- {
- struct isert_np *isert_np;
- struct rdma_cm_id *isert_lid;
-+ struct sockaddr *sa;
- int ret;
-
- isert_np = kzalloc(sizeof(struct isert_np), GFP_KERNEL);
-@@ -2632,8 +2504,9 @@
- mutex_init(&isert_np->np_accept_mutex);
- INIT_LIST_HEAD(&isert_np->np_accept_list);
- init_completion(&isert_np->np_login_comp);
-- isert_np->np = np;
-
-+ sa = (struct sockaddr *)ksockaddr;
-+ pr_debug("ksockaddr: %p, sa: %p\n", ksockaddr, sa);
- /*
- * Setup the np->np_sockaddr from the passed sockaddr setup
- * in iscsi_target_configfs.c code..
-@@ -2641,20 +2514,37 @@
- memcpy(&np->np_sockaddr, ksockaddr,
- sizeof(struct __kernel_sockaddr_storage));
-
-- isert_lid = isert_setup_id(isert_np);
-+ isert_lid = rdma_create_id(isert_cma_handler, np, RDMA_PS_TCP,
-+ IB_QPT_RC);
- if (IS_ERR(isert_lid)) {
-+ pr_err("rdma_create_id() for isert_listen_handler failed: %ld\n",
-+ PTR_ERR(isert_lid));
- ret = PTR_ERR(isert_lid);
- goto out;
- }
-
-+ ret = rdma_bind_addr(isert_lid, sa);
-+ if (ret) {
-+ pr_err("rdma_bind_addr() for isert_lid failed: %d\n", ret);
-+ goto out_lid;
-+ }
-+
-+ ret = rdma_listen(isert_lid, ISERT_RDMA_LISTEN_BACKLOG);
-+ if (ret) {
-+ pr_err("rdma_listen() for isert_lid failed: %d\n", ret);
-+ goto out_lid;
-+ }
-+
- isert_np->np_cm_id = isert_lid;
- np->np_context = isert_np;
-+ pr_debug("Setup isert_lid->context: %p\n", isert_lid->context);
-
- return 0;
-
-+out_lid:
-+ rdma_destroy_id(isert_lid);
- out:
- kfree(isert_np);
--
- return ret;
- }
-
-@@ -2690,15 +2580,7 @@
- struct isert_conn *isert_conn = (struct isert_conn *)conn->context;
- int ret;
-
-- pr_info("before login_req comp conn: %p\n", isert_conn);
-- ret = wait_for_completion_interruptible(&isert_conn->login_req_comp);
-- if (ret) {
-- pr_err("isert_conn %p interrupted before got login req\n",
-- isert_conn);
-- return ret;
-- }
-- INIT_COMPLETION(isert_conn->login_req_comp);
--
-+ pr_debug("isert_get_login_rx before conn_login_comp conn: %p\n", conn);
- /*
- * For login requests after the first PDU, isert_rx_login_req() will
- * kick schedule_delayed_work(&conn->login_work) as the packet is
-@@ -2708,15 +2590,11 @@
- if (!login->first_request)
- return 0;
-
-- isert_rx_login_req(isert_conn);
--
-- pr_info("before conn_login_comp conn: %p\n", conn);
- ret = wait_for_completion_interruptible(&isert_conn->conn_login_comp);
- if (ret)
- return ret;
-
-- pr_info("processing login->req: %p\n", login->req);
--
-+ pr_debug("isert_get_login_rx processing login->req: %p\n", login->req);
- return 0;
- }
-
-@@ -2794,10 +2672,17 @@
- isert_conn->conn = conn;
- max_accept = 0;
-
-- isert_set_conn_info(np, conn, isert_conn);
-+ ret = isert_rdma_post_recvl(isert_conn);
-+ if (ret)
-+ return ret;
-+
-+ ret = isert_rdma_accept(isert_conn);
-+ if (ret)
-+ return ret;
-
-- pr_debug("Processing isert_conn: %p\n", isert_conn);
-+ isert_set_conn_info(np, conn, isert_conn);
-
-+ pr_debug("Processing isert_accept_np: isert_conn: %p\n", isert_conn);
- return 0;
- }
-
-@@ -2813,24 +2698,6 @@
- kfree(isert_np);
- }
-
--static void isert_release_work(struct work_struct *work)
--{
-- struct isert_conn *isert_conn = container_of(work,
-- struct isert_conn,
-- release_work);
--
-- pr_info("Starting release conn %p\n", isert_conn);
--
-- wait_for_completion(&isert_conn->conn_wait);
--
-- mutex_lock(&isert_conn->conn_mutex);
-- isert_conn->state = ISER_CONN_DOWN;
-- mutex_unlock(&isert_conn->conn_mutex);
--
-- pr_info("Destroying conn %p\n", isert_conn);
-- isert_put_conn(isert_conn);
--}
--
- static void isert_wait_conn(struct iscsi_conn *conn)
- {
- struct isert_conn *isert_conn = conn->context;
-@@ -2838,6 +2705,10 @@
- pr_debug("isert_wait_conn: Starting \n");
-
- mutex_lock(&isert_conn->conn_mutex);
-+ if (isert_conn->conn_cm_id) {
-+ pr_debug("Calling rdma_disconnect from isert_wait_conn\n");
-+ rdma_disconnect(isert_conn->conn_cm_id);
-+ }
- /*
- * Only wait for conn_wait_comp_err if the isert_conn made it
- * into full feature phase..
-@@ -2846,13 +2717,14 @@
- mutex_unlock(&isert_conn->conn_mutex);
- return;
- }
-- isert_conn_terminate(isert_conn);
-+ if (isert_conn->state == ISER_CONN_UP)
-+ isert_conn->state = ISER_CONN_TERMINATING;
- mutex_unlock(&isert_conn->conn_mutex);
-
- wait_for_completion(&isert_conn->conn_wait_comp_err);
-
-- INIT_WORK(&isert_conn->release_work, isert_release_work);
-- queue_work(isert_release_wq, &isert_conn->release_work);
-+ wait_for_completion(&isert_conn->conn_wait);
-+ isert_put_conn(isert_conn);
- }
-
- static void isert_free_conn(struct iscsi_conn *conn)
-@@ -2898,21 +2770,10 @@
- goto destroy_rx_wq;
- }
-
-- isert_release_wq = alloc_workqueue("isert_release_wq", WQ_UNBOUND,
-- WQ_UNBOUND_MAX_ACTIVE);
-- if (!isert_release_wq) {
-- pr_err("Unable to allocate isert_release_wq\n");
-- ret = -ENOMEM;
-- goto destroy_comp_wq;
-- }
--
- iscsit_register_transport(&iser_target_transport);
-- pr_info("iSER_TARGET[0] - Loaded iser_target_transport\n");
--
-+ pr_debug("iSER_TARGET[0] - Loaded iser_target_transport\n");
- return 0;
-
--destroy_comp_wq:
-- destroy_workqueue(isert_comp_wq);
- destroy_rx_wq:
- destroy_workqueue(isert_rx_wq);
- return ret;
-@@ -2921,7 +2782,6 @@
- static void __exit isert_exit(void)
- {
- flush_scheduled_work();
-- destroy_workqueue(isert_release_wq);
- destroy_workqueue(isert_comp_wq);
- destroy_workqueue(isert_rx_wq);
- iscsit_unregister_transport(&iser_target_transport);
-diff -Nur linux-3.12.38/drivers/infiniband/ulp/isert/ib_isert.h linux-rpi/drivers/infiniband/ulp/isert/ib_isert.h
---- linux-3.12.38/drivers/infiniband/ulp/isert/ib_isert.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/infiniband/ulp/isert/ib_isert.h 2015-03-10 17:26:50.374216693 +0100
-@@ -23,7 +23,6 @@
- enum iser_conn_state {
- ISER_CONN_INIT,
- ISER_CONN_UP,
-- ISER_CONN_FULL_FEATURE,
- ISER_CONN_TERMINATING,
- ISER_CONN_DOWN,
- };
-@@ -100,7 +99,6 @@
- char *login_req_buf;
- char *login_rsp_buf;
- u64 login_req_dma;
-- int login_req_len;
- u64 login_rsp_dma;
- unsigned int conn_rx_desc_head;
- struct iser_rx_desc *conn_rx_descs;
-@@ -108,13 +106,13 @@
- struct iscsi_conn *conn;
- struct list_head conn_accept_node;
- struct completion conn_login_comp;
-- struct completion login_req_comp;
- struct iser_tx_desc conn_login_tx_desc;
- struct rdma_cm_id *conn_cm_id;
- struct ib_pd *conn_pd;
- struct ib_mr *conn_mr;
- struct ib_qp *conn_qp;
- struct isert_device *conn_device;
-+ struct work_struct conn_logout_work;
- struct mutex conn_mutex;
- struct completion conn_wait;
- struct completion conn_wait_comp_err;
-@@ -123,7 +121,7 @@
- int conn_frwr_pool_size;
- /* lock to protect frwr_pool */
- spinlock_t conn_lock;
-- struct work_struct release_work;
-+ bool disconnect;
- };
-
- #define ISERT_MAX_CQ 64
-@@ -156,7 +154,6 @@
- };
-
- struct isert_np {
-- struct iscsi_np *np;
- struct semaphore np_sem;
- struct rdma_cm_id *np_cm_id;
- struct mutex np_accept_mutex;
-diff -Nur linux-3.12.38/drivers/input/mouse/synaptics.c linux-rpi/drivers/input/mouse/synaptics.c
---- linux-3.12.38/drivers/input/mouse/synaptics.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/input/mouse/synaptics.c 2015-03-10 17:26:50.386216693 +0100
-@@ -132,9 +132,8 @@
- 1232, 5710, 1156, 4696
- },
- {
-- (const char * const []){"LEN0034", "LEN0036", "LEN0037",
-- "LEN0039", "LEN2002", "LEN2004",
-- NULL},
-+ (const char * const []){"LEN0034", "LEN0036", "LEN0039",
-+ "LEN2002", "LEN2004", NULL},
- 1024, 5112, 2024, 4832
- },
- {
-@@ -163,7 +162,7 @@
- "LEN0034", /* T431s, L440, L540, T540, W540, X1 Carbon 2nd */
- "LEN0035", /* X240 */
- "LEN0036", /* T440 */
-- "LEN0037", /* X1 Carbon 2nd */
-+ "LEN0037",
- "LEN0038",
- "LEN0039", /* T440s */
- "LEN0041",
-diff -Nur linux-3.12.38/drivers/input/serio/i8042.c linux-rpi/drivers/input/serio/i8042.c
---- linux-3.12.38/drivers/input/serio/i8042.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/input/serio/i8042.c 2015-03-10 17:26:50.386216693 +0100
-@@ -67,10 +67,6 @@
- module_param_named(notimeout, i8042_notimeout, bool, 0);
- MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
-
--static bool i8042_kbdreset;
--module_param_named(kbdreset, i8042_kbdreset, bool, 0);
--MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
--
- #ifdef CONFIG_X86
- static bool i8042_dritek;
- module_param_named(dritek, i8042_dritek, bool, 0);
-@@ -794,16 +790,6 @@
- return -1;
-
- /*
-- * Reset keyboard (needed on some laptops to successfully detect
-- * touchpad, e.g., some Gigabyte laptop models with Elantech
-- * touchpads).
-- */
-- if (i8042_kbdreset) {
-- pr_warn("Attempting to reset device connected to KBD port\n");
-- i8042_kbd_write(NULL, (unsigned char) 0xff);
-- }
--
--/*
- * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
- * used it for a PCI card or somethig else.
- */
-diff -Nur linux-3.12.38/drivers/input/serio/i8042-x86ia64io.h linux-rpi/drivers/input/serio/i8042-x86ia64io.h
---- linux-3.12.38/drivers/input/serio/i8042-x86ia64io.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/input/serio/i8042-x86ia64io.h 2015-03-10 17:26:50.386216693 +0100
-@@ -152,14 +152,6 @@
- },
- },
- {
-- /* Medion Akoya E7225 */
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "Medion"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "Akoya E7225"),
-- DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
-- },
-- },
-- {
- /* Blue FB5601 */
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "blue"),
-@@ -423,13 +415,6 @@
- },
- },
- {
-- /* Acer Aspire 7738 */
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 7738"),
-- },
-- },
-- {
- /* Gericom Bellagio */
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "Gericom"),
-@@ -743,35 +728,6 @@
- { }
- };
-
--/*
-- * Some laptops need keyboard reset before probing for the trackpad to get
-- * it detected, initialised & finally work.
-- */
--static const struct dmi_system_id __initconst i8042_dmi_kbdreset_table[] = {
-- {
-- /* Gigabyte P35 v2 - Elantech touchpad */
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "P35V2"),
-- },
-- },
-- {
-- /* Aorus branded Gigabyte X3 Plus - Elantech touchpad */
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X3"),
-- },
-- },
-- {
-- /* Gigabyte P34 - Elantech touchpad */
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "GIGABYTE"),
-- DMI_MATCH(DMI_PRODUCT_NAME, "P34"),
-- },
-- },
-- { }
--};
--
- #endif /* CONFIG_X86 */
-
- #ifdef CONFIG_PNP
-@@ -1067,9 +1023,6 @@
- if (dmi_check_system(i8042_dmi_dritek_table))
- i8042_dritek = true;
-
-- if (dmi_check_system(i8042_dmi_kbdreset_table))
-- i8042_kbdreset = true;
--
- /*
- * A20 was already enabled during early kernel init. But some buggy
- * BIOSes (in MSI Laptops) require A20 to be enabled using 8042 to
-diff -Nur linux-3.12.38/drivers/iommu/intel-iommu.c linux-rpi/drivers/iommu/intel-iommu.c
---- linux-3.12.38/drivers/iommu/intel-iommu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/iommu/intel-iommu.c 2015-03-10 17:26:50.398216693 +0100
-@@ -1796,7 +1796,7 @@
- struct dma_pte *first_pte = NULL, *pte = NULL;
- phys_addr_t uninitialized_var(pteval);
- int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
-- unsigned long sg_res = 0;
-+ unsigned long sg_res;
- unsigned int largepage_lvl = 0;
- unsigned long lvl_pages = 0;
-
-@@ -1807,8 +1807,10 @@
-
- prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
-
-- if (!sg) {
-- sg_res = nr_pages;
-+ if (sg)
-+ sg_res = 0;
-+ else {
-+ sg_res = nr_pages + 1;
- pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
- }
-
-diff -Nur linux-3.12.38/drivers/md/bcache/btree.c linux-rpi/drivers/md/bcache/btree.c
---- linux-3.12.38/drivers/md/bcache/btree.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/md/bcache/btree.c 2015-03-10 17:26:50.414216693 +0100
-@@ -141,7 +141,7 @@
- struct bset *i = b->sets[0].data;
- struct btree_iter *iter;
-
-- iter = mempool_alloc(b->c->fill_iter, GFP_NOIO);
-+ iter = mempool_alloc(b->c->fill_iter, GFP_NOWAIT);
- iter->size = b->c->sb.bucket_size / b->c->sb.block_size;
- iter->used = 0;
-
-diff -Nur linux-3.12.38/drivers/md/dm.c linux-rpi/drivers/md/dm.c
---- linux-3.12.38/drivers/md/dm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/md/dm.c 2015-03-10 17:26:50.422216693 +0100
-@@ -2253,8 +2253,7 @@
- set_bit(DMF_MERGE_IS_OPTIONAL, &md->flags);
- else
- clear_bit(DMF_MERGE_IS_OPTIONAL, &md->flags);
-- if (old_map)
-- dm_sync_table(md);
-+ dm_sync_table(md);
-
- return old_map;
- }
-@@ -2695,8 +2694,7 @@
- * flush_workqueue(md->wq).
- */
- set_bit(DMF_BLOCK_IO_FOR_SUSPEND, &md->flags);
-- if (map)
-- synchronize_srcu(&md->io_barrier);
-+ synchronize_srcu(&md->io_barrier);
-
- /*
- * Stop md->queue before flushing md->wq in case request-based
-@@ -2716,8 +2714,7 @@
-
- if (noflush)
- clear_bit(DMF_NOFLUSH_SUSPENDING, &md->flags);
-- if (map)
-- synchronize_srcu(&md->io_barrier);
-+ synchronize_srcu(&md->io_barrier);
-
- /* were we interrupted ? */
- if (r < 0) {
-diff -Nur linux-3.12.38/drivers/md/dm-cache-metadata.c linux-rpi/drivers/md/dm-cache-metadata.c
---- linux-3.12.38/drivers/md/dm-cache-metadata.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/md/dm-cache-metadata.c 2015-03-10 17:26:50.418216693 +0100
-@@ -88,9 +88,6 @@
- } __packed;
-
- struct dm_cache_metadata {
-- atomic_t ref_count;
-- struct list_head list;
--
- struct block_device *bdev;
- struct dm_block_manager *bm;
- struct dm_space_map *metadata_sm;
-@@ -653,10 +650,10 @@
-
- /*----------------------------------------------------------------*/
-
--static struct dm_cache_metadata *metadata_open(struct block_device *bdev,
-- sector_t data_block_size,
-- bool may_format_device,
-- size_t policy_hint_size)
-+struct dm_cache_metadata *dm_cache_metadata_open(struct block_device *bdev,
-+ sector_t data_block_size,
-+ bool may_format_device,
-+ size_t policy_hint_size)
- {
- int r;
- struct dm_cache_metadata *cmd;
-@@ -664,10 +661,9 @@
- cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
- if (!cmd) {
- DMERR("could not allocate metadata struct");
-- return ERR_PTR(-ENOMEM);
-+ return NULL;
- }
-
-- atomic_set(&cmd->ref_count, 1);
- init_rwsem(&cmd->root_lock);
- cmd->bdev = bdev;
- cmd->data_block_size = data_block_size;
-@@ -690,96 +686,10 @@
- return cmd;
- }
-
--/*
-- * We keep a little list of ref counted metadata objects to prevent two
-- * different target instances creating separate bufio instances. This is
-- * an issue if a table is reloaded before the suspend.
-- */
--static DEFINE_MUTEX(table_lock);
--static LIST_HEAD(table);
--
--static struct dm_cache_metadata *lookup(struct block_device *bdev)
--{
-- struct dm_cache_metadata *cmd;
--
-- list_for_each_entry(cmd, &table, list)
-- if (cmd->bdev == bdev) {
-- atomic_inc(&cmd->ref_count);
-- return cmd;
-- }
--
-- return NULL;
--}
--
--static struct dm_cache_metadata *lookup_or_open(struct block_device *bdev,
-- sector_t data_block_size,
-- bool may_format_device,
-- size_t policy_hint_size)
--{
-- struct dm_cache_metadata *cmd, *cmd2;
--
-- mutex_lock(&table_lock);
-- cmd = lookup(bdev);
-- mutex_unlock(&table_lock);
--
-- if (cmd)
-- return cmd;
--
-- cmd = metadata_open(bdev, data_block_size, may_format_device, policy_hint_size);
-- if (!IS_ERR(cmd)) {
-- mutex_lock(&table_lock);
-- cmd2 = lookup(bdev);
-- if (cmd2) {
-- mutex_unlock(&table_lock);
-- __destroy_persistent_data_objects(cmd);
-- kfree(cmd);
-- return cmd2;
-- }
-- list_add(&cmd->list, &table);
-- mutex_unlock(&table_lock);
-- }
--
-- return cmd;
--}
--
--static bool same_params(struct dm_cache_metadata *cmd, sector_t data_block_size)
--{
-- if (cmd->data_block_size != data_block_size) {
-- DMERR("data_block_size (%llu) different from that in metadata (%llu)\n",
-- (unsigned long long) data_block_size,
-- (unsigned long long) cmd->data_block_size);
-- return false;
-- }
--
-- return true;
--}
--
--struct dm_cache_metadata *dm_cache_metadata_open(struct block_device *bdev,
-- sector_t data_block_size,
-- bool may_format_device,
-- size_t policy_hint_size)
--{
-- struct dm_cache_metadata *cmd = lookup_or_open(bdev, data_block_size,
-- may_format_device, policy_hint_size);
--
-- if (!IS_ERR(cmd) && !same_params(cmd, data_block_size)) {
-- dm_cache_metadata_close(cmd);
-- return ERR_PTR(-EINVAL);
-- }
--
-- return cmd;
--}
--
- void dm_cache_metadata_close(struct dm_cache_metadata *cmd)
- {
-- if (atomic_dec_and_test(&cmd->ref_count)) {
-- mutex_lock(&table_lock);
-- list_del(&cmd->list);
-- mutex_unlock(&table_lock);
--
-- __destroy_persistent_data_objects(cmd);
-- kfree(cmd);
-- }
-+ __destroy_persistent_data_objects(cmd);
-+ kfree(cmd);
- }
-
- int dm_cache_resize(struct dm_cache_metadata *cmd, dm_cblock_t new_cache_size)
-diff -Nur linux-3.12.38/drivers/md/dm-cache-target.c linux-rpi/drivers/md/dm-cache-target.c
---- linux-3.12.38/drivers/md/dm-cache-target.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/md/dm-cache-target.c 2015-03-10 17:26:50.418216693 +0100
-@@ -146,13 +146,7 @@
- struct list_head need_commit_migrations;
- sector_t migration_threshold;
- wait_queue_head_t migration_wait;
-- atomic_t nr_allocated_migrations;
--
-- /*
-- * The number of in flight migrations that are performing
-- * background io. eg, promotion, writeback.
-- */
-- atomic_t nr_io_migrations;
-+ atomic_t nr_migrations;
-
- wait_queue_head_t quiescing_wait;
- atomic_t quiescing_ack;
-@@ -188,6 +182,7 @@
- struct dm_deferred_set *all_io_ds;
-
- mempool_t *migration_pool;
-+ struct dm_cache_migration *next_migration;
-
- struct dm_cache_policy *policy;
- unsigned policy_nr_args;
-@@ -270,31 +265,10 @@
- dm_bio_prison_free_cell(cache->prison, cell);
- }
-
--static struct dm_cache_migration *alloc_migration(struct cache *cache)
--{
-- struct dm_cache_migration *mg;
--
-- mg = mempool_alloc(cache->migration_pool, GFP_NOWAIT);
-- if (mg) {
-- mg->cache = cache;
-- atomic_inc(&mg->cache->nr_allocated_migrations);
-- }
--
-- return mg;
--}
--
--static void free_migration(struct dm_cache_migration *mg)
--{
-- if (atomic_dec_and_test(&mg->cache->nr_allocated_migrations))
-- wake_up(&mg->cache->migration_wait);
--
-- mempool_free(mg, mg->cache->migration_pool);
--}
--
- static int prealloc_data_structs(struct cache *cache, struct prealloc *p)
- {
- if (!p->mg) {
-- p->mg = alloc_migration(cache);
-+ p->mg = mempool_alloc(cache->migration_pool, GFP_NOWAIT);
- if (!p->mg)
- return -ENOMEM;
- }
-@@ -323,7 +297,7 @@
- free_prison_cell(cache, p->cell1);
-
- if (p->mg)
-- free_migration(p->mg);
-+ mempool_free(p->mg, cache->migration_pool);
- }
-
- static struct dm_cache_migration *prealloc_get_migration(struct prealloc *p)
-@@ -734,14 +708,24 @@
- * Migration covers moving data from the origin device to the cache, or
- * vice versa.
- *--------------------------------------------------------------*/
--static void inc_io_migrations(struct cache *cache)
-+static void free_migration(struct dm_cache_migration *mg)
-+{
-+ mempool_free(mg, mg->cache->migration_pool);
-+}
-+
-+static void inc_nr_migrations(struct cache *cache)
- {
-- atomic_inc(&cache->nr_io_migrations);
-+ atomic_inc(&cache->nr_migrations);
- }
-
--static void dec_io_migrations(struct cache *cache)
-+static void dec_nr_migrations(struct cache *cache)
- {
-- atomic_dec(&cache->nr_io_migrations);
-+ atomic_dec(&cache->nr_migrations);
-+
-+ /*
-+ * Wake the worker in case we're suspending the target.
-+ */
-+ wake_up(&cache->migration_wait);
- }
-
- static void __cell_defer(struct cache *cache, struct dm_bio_prison_cell *cell,
-@@ -764,10 +748,11 @@
- wake_worker(cache);
- }
-
--static void free_io_migration(struct dm_cache_migration *mg)
-+static void cleanup_migration(struct dm_cache_migration *mg)
- {
-- dec_io_migrations(mg->cache);
-+ struct cache *cache = mg->cache;
- free_migration(mg);
-+ dec_nr_migrations(cache);
- }
-
- static void migration_failure(struct dm_cache_migration *mg)
-@@ -792,7 +777,7 @@
- cell_defer(cache, mg->new_ocell, 1);
- }
-
-- free_io_migration(mg);
-+ cleanup_migration(mg);
- }
-
- static void migration_success_pre_commit(struct dm_cache_migration *mg)
-@@ -803,7 +788,7 @@
- if (mg->writeback) {
- clear_dirty(cache, mg->old_oblock, mg->cblock);
- cell_defer(cache, mg->old_ocell, false);
-- free_io_migration(mg);
-+ cleanup_migration(mg);
- return;
-
- } else if (mg->demote) {
-@@ -813,14 +798,14 @@
- mg->old_oblock);
- if (mg->promote)
- cell_defer(cache, mg->new_ocell, true);
-- free_io_migration(mg);
-+ cleanup_migration(mg);
- return;
- }
- } else {
- if (dm_cache_insert_mapping(cache->cmd, mg->cblock, mg->new_oblock)) {
- DMWARN_LIMIT("promotion failed; couldn't update on disk metadata");
- policy_remove_mapping(cache->policy, mg->new_oblock);
-- free_io_migration(mg);
-+ cleanup_migration(mg);
- return;
- }
- }
-@@ -851,12 +836,12 @@
- spin_unlock_irqrestore(&cache->lock, flags);
-
- } else
-- free_io_migration(mg);
-+ cleanup_migration(mg);
-
- } else {
- clear_dirty(cache, mg->new_oblock, mg->cblock);
- cell_defer(cache, mg->new_ocell, true);
-- free_io_migration(mg);
-+ cleanup_migration(mg);
- }
- }
-
-@@ -1017,7 +1002,7 @@
- mg->new_ocell = cell;
- mg->start_jiffies = jiffies;
-
-- inc_io_migrations(cache);
-+ inc_nr_migrations(cache);
- quiesce_migration(mg);
- }
-
-@@ -1038,7 +1023,7 @@
- mg->new_ocell = NULL;
- mg->start_jiffies = jiffies;
-
-- inc_io_migrations(cache);
-+ inc_nr_migrations(cache);
- quiesce_migration(mg);
- }
-
-@@ -1062,7 +1047,7 @@
- mg->new_ocell = new_ocell;
- mg->start_jiffies = jiffies;
-
-- inc_io_migrations(cache);
-+ inc_nr_migrations(cache);
- quiesce_migration(mg);
- }
-
-@@ -1123,7 +1108,7 @@
-
- static bool spare_migration_bandwidth(struct cache *cache)
- {
-- sector_t current_volume = (atomic_read(&cache->nr_io_migrations) + 1) *
-+ sector_t current_volume = (atomic_read(&cache->nr_migrations) + 1) *
- cache->sectors_per_block;
- return current_volume < cache->migration_threshold;
- }
-@@ -1414,7 +1399,7 @@
-
- static void wait_for_migrations(struct cache *cache)
- {
-- wait_event(cache->migration_wait, !atomic_read(&cache->nr_allocated_migrations));
-+ wait_event(cache->migration_wait, !atomic_read(&cache->nr_migrations));
- }
-
- static void stop_worker(struct cache *cache)
-@@ -1523,6 +1508,9 @@
- {
- unsigned i;
-
-+ if (cache->next_migration)
-+ mempool_free(cache->next_migration, cache->migration_pool);
-+
- if (cache->migration_pool)
- mempool_destroy(cache->migration_pool);
-
-@@ -2010,8 +1998,7 @@
- INIT_LIST_HEAD(&cache->quiesced_migrations);
- INIT_LIST_HEAD(&cache->completed_migrations);
- INIT_LIST_HEAD(&cache->need_commit_migrations);
-- atomic_set(&cache->nr_allocated_migrations, 0);
-- atomic_set(&cache->nr_io_migrations, 0);
-+ atomic_set(&cache->nr_migrations, 0);
- init_waitqueue_head(&cache->migration_wait);
-
- init_waitqueue_head(&cache->quiescing_wait);
-@@ -2070,6 +2057,8 @@
- goto bad;
- }
-
-+ cache->next_migration = NULL;
-+
- cache->need_tick_bio = true;
- cache->sized = false;
- cache->quiescing = false;
-diff -Nur linux-3.12.38/drivers/md/dm-thin.c linux-rpi/drivers/md/dm-thin.c
---- linux-3.12.38/drivers/md/dm-thin.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/md/dm-thin.c 2015-03-10 17:26:50.422216693 +0100
-@@ -2507,12 +2507,6 @@
- struct pool_c *pt = ti->private;
- struct pool *pool = pt->pool;
-
-- if (get_pool_mode(pool) >= PM_READ_ONLY) {
-- DMERR("%s: unable to service pool target messages in READ_ONLY or FAIL mode",
-- dm_device_name(pool->pool_md));
-- return -EINVAL;
-- }
--
- if (!strcasecmp(argv[0], "create_thin"))
- r = process_create_thin_mesg(argc, argv, pool);
-
-diff -Nur linux-3.12.38/drivers/md/raid5.c linux-rpi/drivers/md/raid5.c
---- linux-3.12.38/drivers/md/raid5.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/md/raid5.c 2015-03-10 17:26:50.426216693 +0100
-@@ -2789,8 +2789,7 @@
- (s->failed >= 2 && fdev[1]->toread) ||
- (sh->raid_conf->level <= 5 && s->failed && fdev[0]->towrite &&
- !test_bit(R5_OVERWRITE, &fdev[0]->flags)) ||
-- ((sh->raid_conf->level == 6 || sh->sector >= sh->raid_conf->mddev->recovery_cp)
-- && s->failed && s->to_write))) {
-+ (sh->raid_conf->level == 6 && s->failed && s->to_write))) {
- /* we would like to get this block, possibly by computing it,
- * otherwise read it if the backing disk is insync
- */
-diff -Nur linux-3.12.38/drivers/media/i2c/smiapp/smiapp-core.c linux-rpi/drivers/media/i2c/smiapp/smiapp-core.c
---- linux-3.12.38/drivers/media/i2c/smiapp/smiapp-core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/i2c/smiapp/smiapp-core.c 2015-03-10 17:26:50.446216693 +0100
-@@ -2625,9 +2625,7 @@
- pll->flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
- pll->scale_n = sensor->limits[SMIAPP_LIMIT_SCALER_N_MIN];
-
-- mutex_lock(&sensor->mutex);
- rval = smiapp_update_mode(sensor);
-- mutex_unlock(&sensor->mutex);
- if (rval) {
- dev_err(&client->dev, "update mode failed\n");
- goto out_nvm_release;
-diff -Nur linux-3.12.38/drivers/media/i2c/smiapp-pll.c linux-rpi/drivers/media/i2c/smiapp-pll.c
---- linux-3.12.38/drivers/media/i2c/smiapp-pll.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/i2c/smiapp-pll.c 2015-03-10 17:26:50.442216693 +0100
-@@ -67,7 +67,7 @@
- {
- dev_dbg(dev, "pre_pll_clk_div\t%d\n", pll->pre_pll_clk_div);
- dev_dbg(dev, "pll_multiplier \t%d\n", pll->pll_multiplier);
-- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
-+ if (pll->flags != SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
- dev_dbg(dev, "op_sys_clk_div \t%d\n", pll->op_sys_clk_div);
- dev_dbg(dev, "op_pix_clk_div \t%d\n", pll->op_pix_clk_div);
- }
-@@ -77,7 +77,7 @@
- dev_dbg(dev, "ext_clk_freq_hz \t%d\n", pll->ext_clk_freq_hz);
- dev_dbg(dev, "pll_ip_clk_freq_hz \t%d\n", pll->pll_ip_clk_freq_hz);
- dev_dbg(dev, "pll_op_clk_freq_hz \t%d\n", pll->pll_op_clk_freq_hz);
-- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
-+ if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
- dev_dbg(dev, "op_sys_clk_freq_hz \t%d\n",
- pll->op_sys_clk_freq_hz);
- dev_dbg(dev, "op_pix_clk_freq_hz \t%d\n",
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/bcm2835-camera.c linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c
---- linux-3.12.38/drivers/media/platform/bcm2835/bcm2835-camera.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c 2015-03-10 17:26:50.466216693 +0100
-@@ -0,0 +1,1827 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <media/videobuf2-vmalloc.h>
-+#include <media/videobuf2-dma-contig.h>
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-ioctl.h>
-+#include <media/v4l2-ctrls.h>
-+#include <media/v4l2-fh.h>
-+#include <media/v4l2-event.h>
-+#include <media/v4l2-common.h>
-+#include <linux/delay.h>
-+
-+#include "mmal-common.h"
-+#include "mmal-encodings.h"
-+#include "mmal-vchiq.h"
-+#include "mmal-msg.h"
-+#include "mmal-parameters.h"
-+#include "bcm2835-camera.h"
-+
-+#define BM2835_MMAL_VERSION "0.0.2"
-+#define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2"
-+#define MIN_WIDTH 16
-+#define MIN_HEIGHT 16
-+#define MAX_WIDTH 2592
-+#define MAX_HEIGHT 1944
-+#define MIN_BUFFER_SIZE (80*1024)
-+
-+#define MAX_VIDEO_MODE_WIDTH 1280
-+#define MAX_VIDEO_MODE_HEIGHT 720
-+
-+MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture");
-+MODULE_AUTHOR("Vincent Sanders");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(BM2835_MMAL_VERSION);
-+
-+int bcm2835_v4l2_debug;
-+module_param_named(debug, bcm2835_v4l2_debug, int, 0644);
-+MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2");
-+
-+int max_video_width = MAX_VIDEO_MODE_WIDTH;
-+int max_video_height = MAX_VIDEO_MODE_HEIGHT;
-+module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
-+MODULE_PARM_DESC(max_video_width, "Threshold for video mode");
-+module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
-+MODULE_PARM_DESC(max_video_height, "Threshold for video mode");
-+
-+/* Gstreamer bug https://bugzilla.gnome.org/show_bug.cgi?id=726521
-+ * v4l2src does bad (and actually wrong) things when the vidioc_enum_framesizes
-+ * function says type V4L2_FRMSIZE_TYPE_STEPWISE, which we do by default.
-+ * It's happier if we just don't say anything at all, when it then
-+ * sets up a load of defaults that it thinks might work.
-+ * If gst_v4l2src_is_broken is non-zero, then we remove the function from
-+ * our function table list (actually switch to an alternate set, but same
-+ * result).
-+ */
-+int gst_v4l2src_is_broken = 0;
-+module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
-+MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer");
-+
-+static struct bm2835_mmal_dev *gdev; /* global device data */
-+
-+#define FPS_MIN 1
-+#define FPS_MAX 90
-+
-+/* timeperframe: min/max and default */
-+static const struct v4l2_fract
-+ tpf_min = {.numerator = 1, .denominator = FPS_MAX},
-+ tpf_max = {.numerator = 1, .denominator = FPS_MIN},
-+ tpf_default = {.numerator = 1000, .denominator = 30000};
-+
-+/* video formats */
-+static struct mmal_fmt formats[] = {
-+ {
-+ .name = "4:2:0, packed YUV",
-+ .fourcc = V4L2_PIX_FMT_YUV420,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_I420,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:2, packed, YUYV",
-+ .fourcc = V4L2_PIX_FMT_YUYV,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_YUYV,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "RGB24 (LE)",
-+ .fourcc = V4L2_PIX_FMT_RGB24,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_BGR24,
-+ .depth = 24,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "JPEG",
-+ .fourcc = V4L2_PIX_FMT_JPEG,
-+ .flags = V4L2_FMT_FLAG_COMPRESSED,
-+ .mmal = MMAL_ENCODING_JPEG,
-+ .depth = 8,
-+ .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
-+ },
-+ {
-+ .name = "H264",
-+ .fourcc = V4L2_PIX_FMT_H264,
-+ .flags = V4L2_FMT_FLAG_COMPRESSED,
-+ .mmal = MMAL_ENCODING_H264,
-+ .depth = 8,
-+ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+ },
-+ {
-+ .name = "MJPEG",
-+ .fourcc = V4L2_PIX_FMT_MJPEG,
-+ .flags = V4L2_FMT_FLAG_COMPRESSED,
-+ .mmal = MMAL_ENCODING_MJPEG,
-+ .depth = 8,
-+ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+ },
-+ {
-+ .name = "4:2:2, packed, YVYU",
-+ .fourcc = V4L2_PIX_FMT_YVYU,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_YVYU,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:2, packed, VYUY",
-+ .fourcc = V4L2_PIX_FMT_VYUY,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_VYUY,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:2, packed, UYVY",
-+ .fourcc = V4L2_PIX_FMT_UYVY,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_UYVY,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:0, packed, NV12",
-+ .fourcc = V4L2_PIX_FMT_NV12,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_NV12,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "RGB24 (BE)",
-+ .fourcc = V4L2_PIX_FMT_BGR24,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_RGB24,
-+ .depth = 24,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:0, packed YVU",
-+ .fourcc = V4L2_PIX_FMT_YVU420,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_YV12,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:0, packed, NV21",
-+ .fourcc = V4L2_PIX_FMT_NV21,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_NV21,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "RGB32 (BE)",
-+ .fourcc = V4L2_PIX_FMT_BGR32,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_BGRA,
-+ .depth = 32,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+};
-+
-+static struct mmal_fmt *get_format(struct v4l2_format *f)
-+{
-+ struct mmal_fmt *fmt;
-+ unsigned int k;
-+
-+ for (k = 0; k < ARRAY_SIZE(formats); k++) {
-+ fmt = &formats[k];
-+ if (fmt->fourcc == f->fmt.pix.pixelformat)
-+ break;
-+ }
-+
-+ if (k == ARRAY_SIZE(formats))
-+ return NULL;
-+
-+ return &formats[k];
-+}
-+
-+/* ------------------------------------------------------------------
-+ Videobuf queue operations
-+ ------------------------------------------------------------------*/
-+
-+static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
-+ unsigned int *nbuffers, unsigned int *nplanes,
-+ unsigned int sizes[], void *alloc_ctxs[])
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ unsigned long size;
-+
-+ /* refuse queue setup if port is not configured */
-+ if (dev->capture.port == NULL) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: capture port not configured\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ size = dev->capture.port->current_buffer.size;
-+ if (size == 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: capture port buffer size is zero\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ if (*nbuffers < (dev->capture.port->current_buffer.num + 2))
-+ *nbuffers = (dev->capture.port->current_buffer.num + 2);
-+
-+ *nplanes = 1;
-+
-+ sizes[0] = size;
-+
-+ /*
-+ * videobuf2-vmalloc allocator is context-less so no need to set
-+ * alloc_ctxs array.
-+ */
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ return 0;
-+}
-+
-+static int buffer_prepare(struct vb2_buffer *vb)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-+ unsigned long size;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ BUG_ON(dev->capture.port == NULL);
-+ BUG_ON(dev->capture.fmt == NULL);
-+
-+ size = dev->capture.stride * dev->capture.height;
-+ if (vb2_plane_size(vb, 0) < size) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s data will not fit into plane (%lu < %lu)\n",
-+ __func__, vb2_plane_size(vb, 0), size);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static inline bool is_capturing(struct bm2835_mmal_dev *dev)
-+{
-+ return dev->capture.camera_port ==
-+ &dev->
-+ component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE];
-+}
-+
-+static void buffer_cb(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ int status,
-+ struct mmal_buffer *buf,
-+ unsigned long length, u32 mmal_flags, s64 dts, s64 pts)
-+{
-+ struct bm2835_mmal_dev *dev = port->cb_ctx;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\n",
-+ __func__, status, buf, length, mmal_flags, pts);
-+
-+ if (status != 0) {
-+ /* error in transfer */
-+ if (buf != NULL) {
-+ /* there was a buffer with the error so return it */
-+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
-+ }
-+ return;
-+ } else if (length == 0) {
-+ /* stream ended */
-+ if (buf != NULL) {
-+ /* this should only ever happen if the port is
-+ * disabled and there are buffers still queued
-+ */
-+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
-+ pr_debug("Empty buffer");
-+ } else if (dev->capture.frame_count) {
-+ /* grab another frame */
-+ if (is_capturing(dev)) {
-+ pr_debug("Grab another frame");
-+ vchiq_mmal_port_parameter_set(
-+ instance,
-+ dev->capture.
-+ camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.
-+ frame_count,
-+ sizeof(dev->capture.frame_count));
-+ }
-+ } else {
-+ /* signal frame completion */
-+ complete(&dev->capture.frame_cmplt);
-+ }
-+ } else {
-+ if (dev->capture.frame_count) {
-+ if (dev->capture.vc_start_timestamp != -1 &&
-+ pts != 0) {
-+ s64 runtime_us = pts -
-+ dev->capture.vc_start_timestamp;
-+ u32 div = 0;
-+ u32 rem = 0;
-+
-+ div =
-+ div_u64_rem(runtime_us, USEC_PER_SEC, &rem);
-+ buf->vb.v4l2_buf.timestamp.tv_sec =
-+ dev->capture.kernel_start_ts.tv_sec - 1 +
-+ div;
-+ buf->vb.v4l2_buf.timestamp.tv_usec =
-+ dev->capture.kernel_start_ts.tv_usec + rem;
-+
-+ if (buf->vb.v4l2_buf.timestamp.tv_usec >=
-+ USEC_PER_SEC) {
-+ buf->vb.v4l2_buf.timestamp.tv_sec++;
-+ buf->vb.v4l2_buf.timestamp.tv_usec -=
-+ USEC_PER_SEC;
-+ }
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Convert start time %d.%06d and %llu "
-+ "with offset %llu to %d.%06d\n",
-+ (int)dev->capture.kernel_start_ts.
-+ tv_sec,
-+ (int)dev->capture.kernel_start_ts.
-+ tv_usec,
-+ dev->capture.vc_start_timestamp, pts,
-+ (int)buf->vb.v4l2_buf.timestamp.tv_sec,
-+ (int)buf->vb.v4l2_buf.timestamp.
-+ tv_usec);
-+ } else {
-+ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp);
-+ }
-+
-+ vb2_set_plane_payload(&buf->vb, 0, length);
-+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE);
-+
-+ if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
-+ is_capturing(dev)) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Grab another frame as buffer has EOS");
-+ vchiq_mmal_port_parameter_set(
-+ instance,
-+ dev->capture.
-+ camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.
-+ frame_count,
-+ sizeof(dev->capture.frame_count));
-+ }
-+ } else {
-+ /* signal frame completion */
-+ complete(&dev->capture.frame_cmplt);
-+ }
-+ }
-+}
-+
-+static int enable_camera(struct bm2835_mmal_dev *dev)
-+{
-+ int ret;
-+ if (!dev->camera_use_count) {
-+ ret = vchiq_mmal_component_enable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed enabling camera, ret %d\n", ret);
-+ return -EINVAL;
-+ }
-+ }
-+ dev->camera_use_count++;
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev, "enabled camera (refcount %d)\n",
-+ dev->camera_use_count);
-+ return 0;
-+}
-+
-+static int disable_camera(struct bm2835_mmal_dev *dev)
-+{
-+ int ret;
-+ if (!dev->camera_use_count) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Disabled the camera when already disabled\n");
-+ return -EINVAL;
-+ }
-+ dev->camera_use_count--;
-+ if (!dev->camera_use_count) {
-+ unsigned int i = 0xFFFFFFFF;
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Disabling camera\n");
-+ ret =
-+ vchiq_mmal_component_disable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed disabling camera, ret %d\n", ret);
-+ return -EINVAL;
-+ }
-+ vchiq_mmal_port_parameter_set(
-+ dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->control,
-+ MMAL_PARAMETER_CAMERA_NUM, &i,
-+ sizeof(i));
-+ }
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Camera refcount now %d\n", dev->camera_use_count);
-+ return 0;
-+}
-+
-+static void buffer_queue(struct vb2_buffer *vb)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-+ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb);
-+ int ret;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: dev:%p buf:%p\n", __func__, dev, buf);
-+
-+ buf->buffer = vb2_plane_vaddr(&buf->vb, 0);
-+ buf->buffer_size = vb2_plane_size(&buf->vb, 0);
-+
-+ ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf);
-+ if (ret < 0)
-+ v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n",
-+ __func__);
-+}
-+
-+static int start_streaming(struct vb2_queue *vq, unsigned int count)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ int ret;
-+ int parameter_size;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ /* ensure a format has actually been set */
-+ if (dev->capture.port == NULL)
-+ return -EINVAL;
-+
-+ if (enable_camera(dev) < 0) {
-+ v4l2_err(&dev->v4l2_dev, "Failed to enable camera\n");
-+ return -EINVAL;
-+ }
-+
-+ /*init_completion(&dev->capture.frame_cmplt); */
-+
-+ /* enable frame capture */
-+ dev->capture.frame_count = 1;
-+
-+ /* if the preview is not already running, wait for a few frames for AGC
-+ * to settle down.
-+ */
-+ if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled)
-+ msleep(300);
-+
-+ /* enable the connection from camera to encoder (if applicable) */
-+ if (dev->capture.camera_port != dev->capture.port
-+ && dev->capture.camera_port) {
-+ ret = vchiq_mmal_port_enable(dev->instance,
-+ dev->capture.camera_port, NULL);
-+ if (ret) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to enable encode tunnel - error %d\n",
-+ ret);
-+ return -1;
-+ }
-+ }
-+
-+ /* Get VC timestamp at this point in time */
-+ parameter_size = sizeof(dev->capture.vc_start_timestamp);
-+ if (vchiq_mmal_port_parameter_get(dev->instance,
-+ dev->capture.camera_port,
-+ MMAL_PARAMETER_SYSTEM_TIME,
-+ &dev->capture.vc_start_timestamp,
-+ &parameter_size)) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to get VC start time - update your VC f/w\n");
-+
-+ /* Flag to indicate just to rely on kernel timestamps */
-+ dev->capture.vc_start_timestamp = -1;
-+ } else
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Start time %lld size %d\n",
-+ dev->capture.vc_start_timestamp, parameter_size);
-+
-+ v4l2_get_timestamp(&dev->capture.kernel_start_ts);
-+
-+ /* enable the camera port */
-+ dev->capture.port->cb_ctx = dev;
-+ ret =
-+ vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb);
-+ if (ret) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to enable capture port - error %d. "
-+ "Disabling camera port again\n", ret);
-+
-+ vchiq_mmal_port_disable(dev->instance,
-+ dev->capture.camera_port);
-+ if (disable_camera(dev) < 0) {
-+ v4l2_err(&dev->v4l2_dev, "Failed to disable camera");
-+ return -EINVAL;
-+ }
-+ return -1;
-+ }
-+
-+ /* capture the first frame */
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ dev->capture.camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.frame_count,
-+ sizeof(dev->capture.frame_count));
-+ return 0;
-+}
-+
-+/* abort streaming and wait for last buffer */
-+static int stop_streaming(struct vb2_queue *vq)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ init_completion(&dev->capture.frame_cmplt);
-+ dev->capture.frame_count = 0;
-+
-+ /* ensure a format has actually been set */
-+ if (dev->capture.port == NULL)
-+ return -EINVAL;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "stopping capturing\n");
-+
-+ /* stop capturing frames */
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ dev->capture.camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.frame_count,
-+ sizeof(dev->capture.frame_count));
-+
-+ /* wait for last frame to complete */
-+ ret = wait_for_completion_timeout(&dev->capture.frame_cmplt, HZ);
-+ if (ret <= 0)
-+ v4l2_err(&dev->v4l2_dev,
-+ "error %d waiting for frame completion\n", ret);
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "disabling connection\n");
-+
-+ /* disable the connection from camera to encoder */
-+ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.camera_port);
-+ if (!ret && dev->capture.camera_port != dev->capture.port) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "disabling port\n");
-+ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.port);
-+ } else if (dev->capture.camera_port != dev->capture.port) {
-+ v4l2_err(&dev->v4l2_dev, "port_disable failed, error %d\n",
-+ ret);
-+ }
-+
-+ if (disable_camera(dev) < 0) {
-+ v4l2_err(&dev->v4l2_dev, "Failed to disable camera");
-+ return -EINVAL;
-+ }
-+
-+ return ret;
-+}
-+
-+static void bm2835_mmal_lock(struct vb2_queue *vq)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ mutex_lock(&dev->mutex);
-+}
-+
-+static void bm2835_mmal_unlock(struct vb2_queue *vq)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ mutex_unlock(&dev->mutex);
-+}
-+
-+static struct vb2_ops bm2835_mmal_video_qops = {
-+ .queue_setup = queue_setup,
-+ .buf_prepare = buffer_prepare,
-+ .buf_queue = buffer_queue,
-+ .start_streaming = start_streaming,
-+ .stop_streaming = stop_streaming,
-+ .wait_prepare = bm2835_mmal_unlock,
-+ .wait_finish = bm2835_mmal_lock,
-+};
-+
-+/* ------------------------------------------------------------------
-+ IOCTL operations
-+ ------------------------------------------------------------------*/
-+
-+/* overlay ioctl */
-+static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_fmtdesc *f)
-+{
-+ struct mmal_fmt *fmt;
-+
-+ if (f->index >= ARRAY_SIZE(formats))
-+ return -EINVAL;
-+
-+ fmt = &formats[f->index];
-+
-+ strlcpy(f->description, fmt->name, sizeof(f->description));
-+ f->pixelformat = fmt->fourcc;
-+ f->flags = fmt->flags;
-+
-+ return 0;
-+}
-+
-+static int vidioc_g_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ f->fmt.win = dev->overlay;
-+
-+ return 0;
-+}
-+
-+static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ /* Only support one format so get the current one. */
-+ vidioc_g_fmt_vid_overlay(file, priv, f);
-+
-+ /* todo: allow the size and/or offset to be changed. */
-+ return 0;
-+}
-+
-+static int vidioc_s_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ vidioc_try_fmt_vid_overlay(file, priv, f);
-+
-+ dev->overlay = f->fmt.win;
-+
-+ /* todo: program the preview port parameters */
-+ return 0;
-+}
-+
-+static int vidioc_overlay(struct file *file, void *f, unsigned int on)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct vchiq_mmal_port *src;
-+ struct vchiq_mmal_port *dst;
-+ struct mmal_parameter_displayregion prev_config = {
-+ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA |
-+ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN,
-+ .layer = PREVIEW_LAYER,
-+ .alpha = 255,
-+ .fullscreen = 0,
-+ .dest_rect = {
-+ .x = dev->overlay.w.left,
-+ .y = dev->overlay.w.top,
-+ .width = dev->overlay.w.width,
-+ .height = dev->overlay.w.height,
-+ },
-+ };
-+
-+ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ||
-+ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled))
-+ return 0; /* already in requested state */
-+
-+ src =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW];
-+
-+ if (!on) {
-+ /* disconnect preview ports and disable component */
-+ ret = vchiq_mmal_port_disable(dev->instance, src);
-+ if (!ret)
-+ ret =
-+ vchiq_mmal_port_connect_tunnel(dev->instance, src,
-+ NULL);
-+ if (ret >= 0)
-+ ret = vchiq_mmal_component_disable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_PREVIEW]);
-+
-+ disable_camera(dev);
-+ return ret;
-+ }
-+
-+ /* set preview port format and connect it to output */
-+ dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0];
-+
-+ ret = vchiq_mmal_port_set_format(dev->instance, src);
-+ if (ret < 0)
-+ goto error;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, dst,
-+ MMAL_PARAMETER_DISPLAYREGION,
-+ &prev_config, sizeof(prev_config));
-+ if (ret < 0)
-+ goto error;
-+
-+ if (enable_camera(dev) < 0)
-+ goto error;
-+
-+ ret = vchiq_mmal_component_enable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_PREVIEW]);
-+ if (ret < 0)
-+ goto error;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n",
-+ src, dst);
-+ ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst);
-+ if (!ret)
-+ ret = vchiq_mmal_port_enable(dev->instance, src, NULL);
-+error:
-+ return ret;
-+}
-+
-+static int vidioc_g_fbuf(struct file *file, void *fh,
-+ struct v4l2_framebuffer *a)
-+{
-+ /* The video overlay must stay within the framebuffer and can't be
-+ positioned independently. */
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct vchiq_mmal_port *preview_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW];
-+ a->flags = V4L2_FBUF_FLAG_OVERLAY;
-+ a->fmt.width = preview_port->es.video.width;
-+ a->fmt.height = preview_port->es.video.height;
-+ a->fmt.pixelformat = V4L2_PIX_FMT_YUV420;
-+ a->fmt.bytesperline = (preview_port->es.video.width * 3)>>1;
-+ a->fmt.sizeimage = (preview_port->es.video.width *
-+ preview_port->es.video.height * 3)>>1;
-+ a->fmt.colorspace = V4L2_COLORSPACE_JPEG;
-+
-+ return 0;
-+}
-+
-+/* input ioctls */
-+static int vidioc_enum_input(struct file *file, void *priv,
-+ struct v4l2_input *inp)
-+{
-+ /* only a single camera input */
-+ if (inp->index != 0)
-+ return -EINVAL;
-+
-+ inp->type = V4L2_INPUT_TYPE_CAMERA;
-+ sprintf(inp->name, "Camera %u", inp->index);
-+ return 0;
-+}
-+
-+static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
-+{
-+ *i = 0;
-+ return 0;
-+}
-+
-+static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
-+{
-+ if (i != 0)
-+ return -EINVAL;
-+
-+ return 0;
-+}
-+
-+/* capture ioctls */
-+static int vidioc_querycap(struct file *file, void *priv,
-+ struct v4l2_capability *cap)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ u32 major;
-+ u32 minor;
-+
-+ vchiq_mmal_version(dev->instance, &major, &minor);
-+
-+ strcpy(cap->driver, "bm2835 mmal");
-+ snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d",
-+ major, minor);
-+
-+ snprintf(cap->bus_info, sizeof(cap->bus_info),
-+ "platform:%s", dev->v4l2_dev.name);
-+ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY |
-+ V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
-+ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
-+
-+ return 0;
-+}
-+
-+static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_fmtdesc *f)
-+{
-+ struct mmal_fmt *fmt;
-+
-+ if (f->index >= ARRAY_SIZE(formats))
-+ return -EINVAL;
-+
-+ fmt = &formats[f->index];
-+
-+ strlcpy(f->description, fmt->name, sizeof(f->description));
-+ f->pixelformat = fmt->fourcc;
-+ f->flags = fmt->flags;
-+
-+ return 0;
-+}
-+
-+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ f->fmt.pix.width = dev->capture.width;
-+ f->fmt.pix.height = dev->capture.height;
-+ f->fmt.pix.field = V4L2_FIELD_NONE;
-+ f->fmt.pix.pixelformat = dev->capture.fmt->fourcc;
-+ f->fmt.pix.bytesperline = dev->capture.stride;
-+ f->fmt.pix.sizeimage = dev->capture.buffersize;
-+
-+ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24)
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
-+ else
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
-+ f->fmt.pix.priv = 0;
-+
-+ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix,
-+ __func__);
-+ return 0;
-+}
-+
-+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct mmal_fmt *mfmt;
-+
-+ mfmt = get_format(f);
-+ if (!mfmt) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Fourcc format (0x%08x) unknown.\n",
-+ f->fmt.pix.pixelformat);
-+ f->fmt.pix.pixelformat = formats[0].fourcc;
-+ mfmt = get_format(f);
-+ }
-+
-+ f->fmt.pix.field = V4L2_FIELD_NONE;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Clipping/aligning %dx%d format %08X\n",
-+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
-+
-+ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1,
-+ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0);
-+ f->fmt.pix.bytesperline = (f->fmt.pix.width * mfmt->depth)>>3;
-+
-+ /* Image buffer has to be padded to allow for alignment, even though
-+ * we then remove that padding before delivering the buffer.
-+ */
-+ f->fmt.pix.sizeimage = ((f->fmt.pix.height+15)&~15) *
-+ (((f->fmt.pix.width+31)&~31) * mfmt->depth) >> 3;
-+
-+ if ((mfmt->flags & V4L2_FMT_FLAG_COMPRESSED) &&
-+ f->fmt.pix.sizeimage < MIN_BUFFER_SIZE)
-+ f->fmt.pix.sizeimage = MIN_BUFFER_SIZE;
-+
-+ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24)
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
-+ else
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
-+ f->fmt.pix.priv = 0;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Now %dx%d format %08X\n",
-+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
-+
-+ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix,
-+ __func__);
-+ return 0;
-+}
-+
-+static int mmal_setup_components(struct bm2835_mmal_dev *dev,
-+ struct v4l2_format *f)
-+{
-+ int ret;
-+ struct vchiq_mmal_port *port = NULL, *camera_port = NULL;
-+ struct vchiq_mmal_component *encode_component = NULL;
-+ struct mmal_fmt *mfmt = get_format(f);
-+
-+ BUG_ON(!mfmt);
-+
-+ if (dev->capture.encode_component) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "vid_cap - disconnect previous tunnel\n");
-+
-+ /* Disconnect any previous connection */
-+ vchiq_mmal_port_connect_tunnel(dev->instance,
-+ dev->capture.camera_port, NULL);
-+ dev->capture.camera_port = NULL;
-+ ret = vchiq_mmal_component_disable(dev->instance,
-+ dev->capture.
-+ encode_component);
-+ if (ret)
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to disable encode component %d\n",
-+ ret);
-+
-+ dev->capture.encode_component = NULL;
-+ }
-+ /* format dependant port setup */
-+ switch (mfmt->mmal_component) {
-+ case MMAL_COMPONENT_CAMERA:
-+ /* Make a further decision on port based on resolution */
-+ if (f->fmt.pix.width <= max_video_width
-+ && f->fmt.pix.height <= max_video_height)
-+ camera_port = port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO];
-+ else
-+ camera_port = port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE];
-+ break;
-+ case MMAL_COMPONENT_IMAGE_ENCODE:
-+ encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE];
-+ port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
-+ camera_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE];
-+ break;
-+ case MMAL_COMPONENT_VIDEO_ENCODE:
-+ encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE];
-+ port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+ camera_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO];
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (!port)
-+ return -EINVAL;
-+
-+ if (encode_component)
-+ camera_port->format.encoding = MMAL_ENCODING_OPAQUE;
-+ else
-+ camera_port->format.encoding = mfmt->mmal;
-+
-+ camera_port->format.encoding_variant = 0;
-+ camera_port->es.video.width = f->fmt.pix.width;
-+ camera_port->es.video.height = f->fmt.pix.height;
-+ camera_port->es.video.crop.x = 0;
-+ camera_port->es.video.crop.y = 0;
-+ camera_port->es.video.crop.width = f->fmt.pix.width;
-+ camera_port->es.video.crop.height = f->fmt.pix.height;
-+ camera_port->es.video.frame_rate.num = 0;
-+ camera_port->es.video.frame_rate.den = 1;
-+ camera_port->es.video.color_space = MMAL_COLOR_SPACE_JPEG_JFIF;
-+
-+ ret = vchiq_mmal_port_set_format(dev->instance, camera_port);
-+
-+ if (!ret
-+ && camera_port ==
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO]) {
-+ bool overlay_enabled =
-+ !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled;
-+ struct vchiq_mmal_port *preview_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW];
-+ /* Preview and encode ports need to match on resolution */
-+ if (overlay_enabled) {
-+ /* Need to disable the overlay before we can update
-+ * the resolution
-+ */
-+ ret =
-+ vchiq_mmal_port_disable(dev->instance,
-+ preview_port);
-+ if (!ret)
-+ ret =
-+ vchiq_mmal_port_connect_tunnel(
-+ dev->instance,
-+ preview_port,
-+ NULL);
-+ }
-+ preview_port->es.video.width = f->fmt.pix.width;
-+ preview_port->es.video.height = f->fmt.pix.height;
-+ preview_port->es.video.crop.x = 0;
-+ preview_port->es.video.crop.y = 0;
-+ preview_port->es.video.crop.width = f->fmt.pix.width;
-+ preview_port->es.video.crop.height = f->fmt.pix.height;
-+ preview_port->es.video.frame_rate.num =
-+ dev->capture.timeperframe.denominator;
-+ preview_port->es.video.frame_rate.den =
-+ dev->capture.timeperframe.numerator;
-+ ret = vchiq_mmal_port_set_format(dev->instance, preview_port);
-+ if (overlay_enabled) {
-+ ret = vchiq_mmal_port_connect_tunnel(
-+ dev->instance,
-+ preview_port,
-+ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]);
-+ if (!ret)
-+ ret = vchiq_mmal_port_enable(dev->instance,
-+ preview_port,
-+ NULL);
-+ }
-+ }
-+
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s failed to set format %dx%d %08X\n", __func__,
-+ f->fmt.pix.width, f->fmt.pix.height,
-+ f->fmt.pix.pixelformat);
-+ /* ensure capture is not going to be tried */
-+ dev->capture.port = NULL;
-+ } else {
-+ if (encode_component) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "vid_cap - set up encode comp\n");
-+
-+ /* configure buffering */
-+ camera_port->current_buffer.size =
-+ camera_port->recommended_buffer.size;
-+ camera_port->current_buffer.num =
-+ camera_port->recommended_buffer.num;
-+
-+ ret =
-+ vchiq_mmal_port_connect_tunnel(
-+ dev->instance,
-+ camera_port,
-+ &encode_component->input[0]);
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "%s failed to create connection\n",
-+ __func__);
-+ /* ensure capture is not going to be tried */
-+ dev->capture.port = NULL;
-+ } else {
-+ port->es.video.width = f->fmt.pix.width;
-+ port->es.video.height = f->fmt.pix.height;
-+ port->es.video.crop.x = 0;
-+ port->es.video.crop.y = 0;
-+ port->es.video.crop.width = f->fmt.pix.width;
-+ port->es.video.crop.height = f->fmt.pix.height;
-+ port->es.video.frame_rate.num =
-+ dev->capture.timeperframe.denominator;
-+ port->es.video.frame_rate.den =
-+ dev->capture.timeperframe.numerator;
-+
-+ port->format.encoding = mfmt->mmal;
-+ port->format.encoding_variant = 0;
-+ /* Set any encoding specific parameters */
-+ switch (mfmt->mmal_component) {
-+ case MMAL_COMPONENT_VIDEO_ENCODE:
-+ port->format.bitrate =
-+ dev->capture.encode_bitrate;
-+ break;
-+ case MMAL_COMPONENT_IMAGE_ENCODE:
-+ /* Could set EXIF parameters here */
-+ break;
-+ default:
-+ break;
-+ }
-+ ret = vchiq_mmal_port_set_format(dev->instance,
-+ port);
-+ if (ret)
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "%s failed to set format %dx%d fmt %08X\n",
-+ __func__,
-+ f->fmt.pix.width,
-+ f->fmt.pix.height,
-+ f->fmt.pix.pixelformat
-+ );
-+ }
-+
-+ if (!ret) {
-+ ret = vchiq_mmal_component_enable(
-+ dev->instance,
-+ encode_component);
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "%s Failed to enable encode components\n",
-+ __func__);
-+ }
-+ }
-+ if (!ret) {
-+ /* configure buffering */
-+ port->current_buffer.num = 1;
-+ port->current_buffer.size =
-+ f->fmt.pix.sizeimage;
-+ if (port->format.encoding ==
-+ MMAL_ENCODING_JPEG) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "JPG - buf size now %d was %d\n",
-+ f->fmt.pix.sizeimage,
-+ port->current_buffer.size);
-+ port->current_buffer.size =
-+ (f->fmt.pix.sizeimage <
-+ (100 << 10))
-+ ? (100 << 10) : f->fmt.pix.
-+ sizeimage;
-+ }
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "vid_cap - cur_buf.size set to %d\n",
-+ f->fmt.pix.sizeimage);
-+ port->current_buffer.alignment = 0;
-+ }
-+ } else {
-+ /* configure buffering */
-+ camera_port->current_buffer.num = 1;
-+ camera_port->current_buffer.size = f->fmt.pix.sizeimage;
-+ camera_port->current_buffer.alignment = 0;
-+ }
-+
-+ if (!ret) {
-+ dev->capture.fmt = mfmt;
-+ dev->capture.stride = f->fmt.pix.bytesperline;
-+ dev->capture.width = camera_port->es.video.crop.width;
-+ dev->capture.height = camera_port->es.video.crop.height;
-+ dev->capture.buffersize = port->current_buffer.size;
-+
-+ /* select port for capture */
-+ dev->capture.port = port;
-+ dev->capture.camera_port = camera_port;
-+ dev->capture.encode_component = encode_component;
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d",
-+ port->format.encoding,
-+ dev->capture.width, dev->capture.height,
-+ dev->capture.stride, dev->capture.buffersize);
-+ }
-+ }
-+
-+ /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */
-+ return ret;
-+}
-+
-+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct mmal_fmt *mfmt;
-+
-+ /* try the format to set valid parameters */
-+ ret = vidioc_try_fmt_vid_cap(file, priv, f);
-+ if (ret) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "vid_cap - vidioc_try_fmt_vid_cap failed\n");
-+ return ret;
-+ }
-+
-+ /* if a capture is running refuse to set format */
-+ if (vb2_is_busy(&dev->capture.vb_vidq)) {
-+ v4l2_info(&dev->v4l2_dev, "%s device busy\n", __func__);
-+ return -EBUSY;
-+ }
-+
-+ /* If the format is unsupported v4l2 says we should switch to
-+ * a supported one and not return an error. */
-+ mfmt = get_format(f);
-+ if (!mfmt) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Fourcc format (0x%08x) unknown.\n",
-+ f->fmt.pix.pixelformat);
-+ f->fmt.pix.pixelformat = formats[0].fourcc;
-+ mfmt = get_format(f);
-+ }
-+
-+ ret = mmal_setup_components(dev, f);
-+ if (ret != 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: failed to setup mmal components: %d\n",
-+ __func__, ret);
-+ ret = -EINVAL;
-+ }
-+
-+ return ret;
-+}
-+
-+int vidioc_enum_framesizes(struct file *file, void *fh,
-+ struct v4l2_frmsizeenum *fsize)
-+{
-+ static const struct v4l2_frmsize_stepwise sizes = {
-+ MIN_WIDTH, MAX_WIDTH, 2,
-+ MIN_HEIGHT, MAX_HEIGHT, 2
-+ };
-+ int i;
-+
-+ if (fsize->index)
-+ return -EINVAL;
-+ for (i = 0; i < ARRAY_SIZE(formats); i++)
-+ if (formats[i].fourcc == fsize->pixel_format)
-+ break;
-+ if (i == ARRAY_SIZE(formats))
-+ return -EINVAL;
-+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
-+ fsize->stepwise = sizes;
-+ return 0;
-+}
-+
-+/* timeperframe is arbitrary and continous */
-+static int vidioc_enum_frameintervals(struct file *file, void *priv,
-+ struct v4l2_frmivalenum *fival)
-+{
-+ int i;
-+
-+ if (fival->index)
-+ return -EINVAL;
-+
-+ for (i = 0; i < ARRAY_SIZE(formats); i++)
-+ if (formats[i].fourcc == fival->pixel_format)
-+ break;
-+ if (i == ARRAY_SIZE(formats))
-+ return -EINVAL;
-+
-+ /* regarding width & height - we support any within range */
-+ if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH ||
-+ fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT)
-+ return -EINVAL;
-+
-+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
-+
-+ /* fill in stepwise (step=1.0 is requred by V4L2 spec) */
-+ fival->stepwise.min = tpf_min;
-+ fival->stepwise.max = tpf_max;
-+ fival->stepwise.step = (struct v4l2_fract) {1, 1};
-+
-+ return 0;
-+}
-+
-+static int vidioc_g_parm(struct file *file, void *priv,
-+ struct v4l2_streamparm *parm)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
-+ return -EINVAL;
-+
-+ parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
-+ parm->parm.capture.timeperframe = dev->capture.timeperframe;
-+ parm->parm.capture.readbuffers = 1;
-+ return 0;
-+}
-+
-+#define FRACT_CMP(a, OP, b) \
-+ ((u64)(a).numerator * (b).denominator OP \
-+ (u64)(b).numerator * (a).denominator)
-+
-+static int vidioc_s_parm(struct file *file, void *priv,
-+ struct v4l2_streamparm *parm)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct v4l2_fract tpf;
-+ struct mmal_parameter_rational fps_param;
-+
-+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
-+ return -EINVAL;
-+
-+ tpf = parm->parm.capture.timeperframe;
-+
-+ /* tpf: {*, 0} resets timing; clip to [min, max]*/
-+ tpf = tpf.denominator ? tpf : tpf_default;
-+ tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf;
-+ tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf;
-+
-+ dev->capture.timeperframe = tpf;
-+ parm->parm.capture.timeperframe = tpf;
-+ parm->parm.capture.readbuffers = 1;
-+
-+ fps_param.num = 0; /* Select variable fps, and then use
-+ * FPS_RANGE to select the actual limits.
-+ */
-+ fps_param.den = 1;
-+ set_framerate_params(dev);
-+
-+ return 0;
-+}
-+
-+static const struct v4l2_ioctl_ops camera0_ioctl_ops = {
-+ /* overlay */
-+ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay,
-+ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay,
-+ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay,
-+ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay,
-+ .vidioc_overlay = vidioc_overlay,
-+ .vidioc_g_fbuf = vidioc_g_fbuf,
-+
-+ /* inputs */
-+ .vidioc_enum_input = vidioc_enum_input,
-+ .vidioc_g_input = vidioc_g_input,
-+ .vidioc_s_input = vidioc_s_input,
-+
-+ /* capture */
-+ .vidioc_querycap = vidioc_querycap,
-+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
-+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
-+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
-+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
-+
-+ /* buffer management */
-+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
-+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
-+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
-+ .vidioc_querybuf = vb2_ioctl_querybuf,
-+ .vidioc_qbuf = vb2_ioctl_qbuf,
-+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
-+ .vidioc_enum_framesizes = vidioc_enum_framesizes,
-+ .vidioc_enum_frameintervals = vidioc_enum_frameintervals,
-+ .vidioc_g_parm = vidioc_g_parm,
-+ .vidioc_s_parm = vidioc_s_parm,
-+ .vidioc_streamon = vb2_ioctl_streamon,
-+ .vidioc_streamoff = vb2_ioctl_streamoff,
-+
-+ .vidioc_log_status = v4l2_ctrl_log_status,
-+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
-+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
-+};
-+
-+static const struct v4l2_ioctl_ops camera0_ioctl_ops_gstreamer = {
-+ /* overlay */
-+ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay,
-+ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay,
-+ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay,
-+ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay,
-+ .vidioc_overlay = vidioc_overlay,
-+ .vidioc_g_fbuf = vidioc_g_fbuf,
-+
-+ /* inputs */
-+ .vidioc_enum_input = vidioc_enum_input,
-+ .vidioc_g_input = vidioc_g_input,
-+ .vidioc_s_input = vidioc_s_input,
-+
-+ /* capture */
-+ .vidioc_querycap = vidioc_querycap,
-+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
-+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
-+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
-+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
-+
-+ /* buffer management */
-+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
-+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
-+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
-+ .vidioc_querybuf = vb2_ioctl_querybuf,
-+ .vidioc_qbuf = vb2_ioctl_qbuf,
-+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
-+ /* Remove this function ptr to fix gstreamer bug
-+ .vidioc_enum_framesizes = vidioc_enum_framesizes, */
-+ .vidioc_enum_frameintervals = vidioc_enum_frameintervals,
-+ .vidioc_g_parm = vidioc_g_parm,
-+ .vidioc_s_parm = vidioc_s_parm,
-+ .vidioc_streamon = vb2_ioctl_streamon,
-+ .vidioc_streamoff = vb2_ioctl_streamoff,
-+
-+ .vidioc_log_status = v4l2_ctrl_log_status,
-+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
-+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
-+};
-+
-+/* ------------------------------------------------------------------
-+ Driver init/finalise
-+ ------------------------------------------------------------------*/
-+
-+static const struct v4l2_file_operations camera0_fops = {
-+ .owner = THIS_MODULE,
-+ .open = v4l2_fh_open,
-+ .release = vb2_fop_release,
-+ .read = vb2_fop_read,
-+ .poll = vb2_fop_poll,
-+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
-+ .mmap = vb2_fop_mmap,
-+};
-+
-+static struct video_device vdev_template = {
-+ .name = "camera0",
-+ .fops = &camera0_fops,
-+ .ioctl_ops = &camera0_ioctl_ops,
-+ .release = video_device_release_empty,
-+};
-+
-+static int set_camera_parameters(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *camera)
-+{
-+ int ret;
-+ struct mmal_parameter_camera_config cam_config = {
-+ .max_stills_w = MAX_WIDTH,
-+ .max_stills_h = MAX_HEIGHT,
-+ .stills_yuv422 = 1,
-+ .one_shot_stills = 1,
-+ .max_preview_video_w = (max_video_width > 1920) ?
-+ max_video_width : 1920,
-+ .max_preview_video_h = (max_video_height > 1088) ?
-+ max_video_height : 1088,
-+ .num_preview_video_frames = 3,
-+ .stills_capture_circular_buffer_height = 0,
-+ .fast_preview_resume = 0,
-+ .use_stc_timestamp = MMAL_PARAM_TIMESTAMP_MODE_RAW_STC
-+ };
-+
-+ ret = vchiq_mmal_port_parameter_set(instance, &camera->control,
-+ MMAL_PARAMETER_CAMERA_CONFIG,
-+ &cam_config, sizeof(cam_config));
-+ return ret;
-+}
-+
-+/* MMAL instance and component init */
-+static int __init mmal_init(struct bm2835_mmal_dev *dev)
-+{
-+ int ret;
-+ struct mmal_es_format *format;
-+ u32 bool_true = 1;
-+
-+ ret = vchiq_mmal_init(&dev->instance);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* get the camera component ready */
-+ ret = vchiq_mmal_component_init(dev->instance, "ril.camera",
-+ &dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0)
-+ goto unreg_mmal;
-+
-+ if (dev->component[MMAL_COMPONENT_CAMERA]->outputs <
-+ MMAL_CAMERA_PORT_COUNT) {
-+ ret = -EINVAL;
-+ goto unreg_camera;
-+ }
-+
-+ ret = set_camera_parameters(dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0)
-+ goto unreg_camera;
-+
-+ format =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW].format;
-+
-+ format->encoding = MMAL_ENCODING_OPAQUE;
-+ format->encoding_variant = MMAL_ENCODING_I420;
-+
-+ format->es->video.width = 1024;
-+ format->es->video.height = 768;
-+ format->es->video.crop.x = 0;
-+ format->es->video.crop.y = 0;
-+ format->es->video.crop.width = 1024;
-+ format->es->video.crop.height = 768;
-+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
-+ format->es->video.frame_rate.den = 1;
-+
-+ format =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO].format;
-+
-+ format->encoding = MMAL_ENCODING_OPAQUE;
-+ format->encoding_variant = MMAL_ENCODING_I420;
-+
-+ format->es->video.width = 1024;
-+ format->es->video.height = 768;
-+ format->es->video.crop.x = 0;
-+ format->es->video.crop.y = 0;
-+ format->es->video.crop.width = 1024;
-+ format->es->video.crop.height = 768;
-+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
-+ format->es->video.frame_rate.den = 1;
-+
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO],
-+ MMAL_PARAMETER_NO_IMAGE_PADDING,
-+ &bool_true, sizeof(bool_true));
-+
-+ format =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE].format;
-+
-+ format->encoding = MMAL_ENCODING_OPAQUE;
-+
-+ format->es->video.width = 2592;
-+ format->es->video.height = 1944;
-+ format->es->video.crop.x = 0;
-+ format->es->video.crop.y = 0;
-+ format->es->video.crop.width = 2592;
-+ format->es->video.crop.height = 1944;
-+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
-+ format->es->video.frame_rate.den = 1;
-+
-+ dev->capture.width = format->es->video.width;
-+ dev->capture.height = format->es->video.height;
-+ dev->capture.fmt = &formats[0];
-+ dev->capture.encode_component = NULL;
-+ dev->capture.timeperframe = tpf_default;
-+ dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
-+ dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
-+
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE],
-+ MMAL_PARAMETER_NO_IMAGE_PADDING,
-+ &bool_true, sizeof(bool_true));
-+
-+ /* get the preview component ready */
-+ ret = vchiq_mmal_component_init(
-+ dev->instance, "ril.video_render",
-+ &dev->component[MMAL_COMPONENT_PREVIEW]);
-+ if (ret < 0)
-+ goto unreg_camera;
-+
-+ if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) {
-+ ret = -EINVAL;
-+ pr_debug("too few input ports %d needed %d\n",
-+ dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1);
-+ goto unreg_preview;
-+ }
-+
-+ /* get the image encoder component ready */
-+ ret = vchiq_mmal_component_init(
-+ dev->instance, "ril.image_encode",
-+ &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+ if (ret < 0)
-+ goto unreg_preview;
-+
-+ if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) {
-+ ret = -EINVAL;
-+ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
-+ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs,
-+ 1);
-+ goto unreg_image_encoder;
-+ }
-+
-+ /* get the video encoder component ready */
-+ ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode",
-+ &dev->
-+ component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+ if (ret < 0)
-+ goto unreg_image_encoder;
-+
-+ if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) {
-+ ret = -EINVAL;
-+ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
-+ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs,
-+ 1);
-+ goto unreg_vid_encoder;
-+ }
-+
-+ {
-+ struct vchiq_mmal_port *encoder_port =
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+ encoder_port->format.encoding = MMAL_ENCODING_H264;
-+ ret = vchiq_mmal_port_set_format(dev->instance,
-+ encoder_port);
-+ }
-+
-+ {
-+ unsigned int enable = 1;
-+ vchiq_mmal_port_parameter_set(
-+ dev->instance,
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
-+ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
-+ &enable, sizeof(enable));
-+
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
-+ MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
-+ &enable,
-+ sizeof(enable));
-+ }
-+ ret = bm2835_mmal_set_all_camera_controls(dev);
-+ if (ret < 0)
-+ goto unreg_vid_encoder;
-+
-+ return 0;
-+
-+unreg_vid_encoder:
-+ pr_err("Cleanup: Destroy video encoder\n");
-+ vchiq_mmal_component_finalise(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+
-+unreg_image_encoder:
-+ pr_err("Cleanup: Destroy image encoder\n");
-+ vchiq_mmal_component_finalise(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+
-+unreg_preview:
-+ pr_err("Cleanup: Destroy video render\n");
-+ vchiq_mmal_component_finalise(dev->instance,
-+ dev->component[MMAL_COMPONENT_PREVIEW]);
-+
-+unreg_camera:
-+ pr_err("Cleanup: Destroy camera\n");
-+ vchiq_mmal_component_finalise(dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+
-+unreg_mmal:
-+ vchiq_mmal_finalise(dev->instance);
-+ return ret;
-+}
-+
-+static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev,
-+ struct video_device *vfd)
-+{
-+ int ret;
-+
-+ *vfd = vdev_template;
-+ if (gst_v4l2src_is_broken) {
-+ v4l2_info(&dev->v4l2_dev,
-+ "Work-around for gstreamer issue is active.\n");
-+ vfd->ioctl_ops = &camera0_ioctl_ops_gstreamer;
-+ }
-+
-+ vfd->v4l2_dev = &dev->v4l2_dev;
-+
-+ vfd->lock = &dev->mutex;
-+
-+ vfd->queue = &dev->capture.vb_vidq;
-+
-+ set_bit(V4L2_FL_USE_FH_PRIO, &vfd->flags);
-+
-+ /* video device needs to be able to access instance data */
-+ video_set_drvdata(vfd, dev);
-+
-+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
-+ if (ret < 0)
-+ return ret;
-+
-+ v4l2_info(vfd->v4l2_dev,
-+ "V4L2 device registered as %s - stills mode > %dx%d\n",
-+ video_device_node_name(vfd), max_video_width, max_video_height);
-+
-+ return 0;
-+}
-+
-+static struct v4l2_format default_v4l2_format = {
-+ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG,
-+ .fmt.pix.width = 1024,
-+ .fmt.pix.bytesperline = 1024,
-+ .fmt.pix.height = 768,
-+ .fmt.pix.sizeimage = 1024*768,
-+};
-+
-+static int __init bm2835_mmal_init(void)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev;
-+ struct vb2_queue *q;
-+
-+ dev = kzalloc(sizeof(*gdev), GFP_KERNEL);
-+ if (!dev)
-+ return -ENOMEM;
-+
-+ /* setup device defaults */
-+ dev->overlay.w.left = 150;
-+ dev->overlay.w.top = 50;
-+ dev->overlay.w.width = 1024;
-+ dev->overlay.w.height = 768;
-+ dev->overlay.clipcount = 0;
-+ dev->overlay.field = V4L2_FIELD_NONE;
-+
-+ dev->capture.fmt = &formats[3]; /* JPEG */
-+
-+ /* v4l device registration */
-+ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
-+ "%s", BM2835_MMAL_MODULE_NAME);
-+ ret = v4l2_device_register(NULL, &dev->v4l2_dev);
-+ if (ret)
-+ goto free_dev;
-+
-+ /* setup v4l controls */
-+ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler);
-+ if (ret < 0)
-+ goto unreg_dev;
-+ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler;
-+
-+ /* mmal init */
-+ ret = mmal_init(dev);
-+ if (ret < 0)
-+ goto unreg_dev;
-+
-+ /* initialize queue */
-+ q = &dev->capture.vb_vidq;
-+ memset(q, 0, sizeof(*q));
-+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
-+ q->drv_priv = dev;
-+ q->buf_struct_size = sizeof(struct mmal_buffer);
-+ q->ops = &bm2835_mmal_video_qops;
-+ q->mem_ops = &vb2_vmalloc_memops;
-+ q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
-+ ret = vb2_queue_init(q);
-+ if (ret < 0)
-+ goto unreg_dev;
-+
-+ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */
-+ mutex_init(&dev->mutex);
-+
-+ /* initialise video devices */
-+ ret = bm2835_mmal_init_device(dev, &dev->vdev);
-+ if (ret < 0)
-+ goto unreg_dev;
-+
-+ /* Really want to call vidioc_s_fmt_vid_cap with the default
-+ * format, but currently the APIs don't join up.
-+ */
-+ ret = mmal_setup_components(dev, &default_v4l2_format);
-+ if (ret < 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: could not setup components\n", __func__);
-+ goto unreg_dev;
-+ }
-+
-+ v4l2_info(&dev->v4l2_dev,
-+ "Broadcom 2835 MMAL video capture ver %s loaded.\n",
-+ BM2835_MMAL_VERSION);
-+
-+ gdev = dev;
-+ return 0;
-+
-+unreg_dev:
-+ v4l2_ctrl_handler_free(&dev->ctrl_handler);
-+ v4l2_device_unregister(&dev->v4l2_dev);
-+
-+free_dev:
-+ kfree(dev);
-+
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: error %d while loading driver\n",
-+ BM2835_MMAL_MODULE_NAME, ret);
-+
-+ return ret;
-+}
-+
-+static void __exit bm2835_mmal_exit(void)
-+{
-+ if (!gdev)
-+ return;
-+
-+ v4l2_info(&gdev->v4l2_dev, "unregistering %s\n",
-+ video_device_node_name(&gdev->vdev));
-+
-+ video_unregister_device(&gdev->vdev);
-+
-+ if (gdev->capture.encode_component) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev,
-+ "mmal_exit - disconnect tunnel\n");
-+ vchiq_mmal_port_connect_tunnel(gdev->instance,
-+ gdev->capture.camera_port, NULL);
-+ vchiq_mmal_component_disable(gdev->instance,
-+ gdev->capture.encode_component);
-+ }
-+ vchiq_mmal_component_disable(gdev->instance,
-+ gdev->component[MMAL_COMPONENT_CAMERA]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->
-+ component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->
-+ component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->component[MMAL_COMPONENT_PREVIEW]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->component[MMAL_COMPONENT_CAMERA]);
-+
-+ vchiq_mmal_finalise(gdev->instance);
-+
-+ v4l2_ctrl_handler_free(&gdev->ctrl_handler);
-+
-+ v4l2_device_unregister(&gdev->v4l2_dev);
-+
-+ kfree(gdev);
-+}
-+
-+module_init(bm2835_mmal_init);
-+module_exit(bm2835_mmal_exit);
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/bcm2835-camera.h linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h
---- linux-3.12.38/drivers/media/platform/bcm2835/bcm2835-camera.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,126 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * core driver device
-+ */
-+
-+#define V4L2_CTRL_COUNT 28 /* number of v4l controls */
-+
-+enum {
-+ MMAL_COMPONENT_CAMERA = 0,
-+ MMAL_COMPONENT_PREVIEW,
-+ MMAL_COMPONENT_IMAGE_ENCODE,
-+ MMAL_COMPONENT_VIDEO_ENCODE,
-+ MMAL_COMPONENT_COUNT
-+};
-+
-+enum {
-+ MMAL_CAMERA_PORT_PREVIEW = 0,
-+ MMAL_CAMERA_PORT_VIDEO,
-+ MMAL_CAMERA_PORT_CAPTURE,
-+ MMAL_CAMERA_PORT_COUNT
-+};
-+
-+#define PREVIEW_LAYER 2
-+
-+extern int bcm2835_v4l2_debug;
-+
-+struct bm2835_mmal_dev {
-+ /* v4l2 devices */
-+ struct v4l2_device v4l2_dev;
-+ struct video_device vdev;
-+ struct mutex mutex;
-+
-+ /* controls */
-+ struct v4l2_ctrl_handler ctrl_handler;
-+ struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT];
-+ enum v4l2_scene_mode scene_mode;
-+ struct mmal_colourfx colourfx;
-+ int hflip;
-+ int vflip;
-+ int red_gain;
-+ int blue_gain;
-+ enum mmal_parameter_exposuremode exposure_mode_user;
-+ enum v4l2_exposure_auto_type exposure_mode_v4l2_user;
-+ /* active exposure mode may differ if selected via a scene mode */
-+ enum mmal_parameter_exposuremode exposure_mode_active;
-+ enum mmal_parameter_exposuremeteringmode metering_mode;
-+ unsigned int manual_shutter_speed;
-+ bool exp_auto_priority;
-+
-+ /* allocated mmal instance and components */
-+ struct vchiq_mmal_instance *instance;
-+ struct vchiq_mmal_component *component[MMAL_COMPONENT_COUNT];
-+ int camera_use_count;
-+
-+ struct v4l2_window overlay;
-+
-+ struct {
-+ unsigned int width; /* width */
-+ unsigned int height; /* height */
-+ unsigned int stride; /* stride */
-+ unsigned int buffersize; /* buffer size with padding */
-+ struct mmal_fmt *fmt;
-+ struct v4l2_fract timeperframe;
-+
-+ /* H264 encode bitrate */
-+ int encode_bitrate;
-+ /* H264 bitrate mode. CBR/VBR */
-+ int encode_bitrate_mode;
-+ /* H264 profile */
-+ enum v4l2_mpeg_video_h264_profile enc_profile;
-+ /* H264 level */
-+ enum v4l2_mpeg_video_h264_level enc_level;
-+ /* JPEG Q-factor */
-+ int q_factor;
-+
-+ struct vb2_queue vb_vidq;
-+
-+ /* VC start timestamp for streaming */
-+ s64 vc_start_timestamp;
-+ /* Kernel start timestamp for streaming */
-+ struct timeval kernel_start_ts;
-+
-+ struct vchiq_mmal_port *port; /* port being used for capture */
-+ /* camera port being used for capture */
-+ struct vchiq_mmal_port *camera_port;
-+ /* component being used for encode */
-+ struct vchiq_mmal_component *encode_component;
-+ /* number of frames remaining which driver should capture */
-+ unsigned int frame_count;
-+ /* last frame completion */
-+ struct completion frame_cmplt;
-+
-+ } capture;
-+
-+};
-+
-+int bm2835_mmal_init_controls(
-+ struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl_handler *hdl);
-+
-+int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev);
-+int set_framerate_params(struct bm2835_mmal_dev *dev);
-+
-+/* Debug helpers */
-+
-+#define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \
-+{ \
-+ v4l2_dbg(level, debug, dev, \
-+"%s: w %u h %u field %u pfmt 0x%x bpl %u sz_img %u colorspace 0x%x priv %u\n", \
-+ desc == NULL ? "" : desc, \
-+ (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \
-+ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
-+ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
-+}
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/controls.c linux-rpi/drivers/media/platform/bcm2835/controls.c
---- linux-3.12.38/drivers/media/platform/bcm2835/controls.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/controls.c 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,1322 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <media/videobuf2-vmalloc.h>
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-ioctl.h>
-+#include <media/v4l2-ctrls.h>
-+#include <media/v4l2-fh.h>
-+#include <media/v4l2-event.h>
-+#include <media/v4l2-common.h>
-+
-+#include "mmal-common.h"
-+#include "mmal-vchiq.h"
-+#include "mmal-parameters.h"
-+#include "bcm2835-camera.h"
-+
-+/* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0.
-+ * MMAL values are in 1/6th increments so the MMAL range is -24 to +24.
-+ * V4L2 docs say value "is expressed in terms of EV, drivers should interpret
-+ * the values as 0.001 EV units, where the value 1000 stands for +1 EV."
-+ * V4L2 is limited to a max of 32 values in a menu, so count in 1/3rds from
-+ * -4 to +4
-+ */
-+static const s64 ev_bias_qmenu[] = {
-+ -4000, -3667, -3333,
-+ -3000, -2667, -2333,
-+ -2000, -1667, -1333,
-+ -1000, -667, -333,
-+ 0, 333, 667,
-+ 1000, 1333, 1667,
-+ 2000, 2333, 2667,
-+ 3000, 3333, 3667,
-+ 4000
-+};
-+
-+/* Supported ISO values
-+ * ISOO = auto ISO
-+ */
-+static const s64 iso_qmenu[] = {
-+ 0, 100, 200, 400, 800,
-+};
-+
-+static const s64 mains_freq_qmenu[] = {
-+ V4L2_CID_POWER_LINE_FREQUENCY_DISABLED,
-+ V4L2_CID_POWER_LINE_FREQUENCY_50HZ,
-+ V4L2_CID_POWER_LINE_FREQUENCY_60HZ,
-+ V4L2_CID_POWER_LINE_FREQUENCY_AUTO
-+};
-+
-+/* Supported video encode modes */
-+static const s64 bitrate_mode_qmenu[] = {
-+ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
-+ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
-+};
-+
-+enum bm2835_mmal_ctrl_type {
-+ MMAL_CONTROL_TYPE_STD,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ MMAL_CONTROL_TYPE_INT_MENU,
-+ MMAL_CONTROL_TYPE_CLUSTER, /* special cluster entry */
-+};
-+
-+struct bm2835_mmal_v4l2_ctrl;
-+
-+typedef int(bm2835_mmal_v4l2_ctrl_cb)(
-+ struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl);
-+
-+struct bm2835_mmal_v4l2_ctrl {
-+ u32 id; /* v4l2 control identifier */
-+ enum bm2835_mmal_ctrl_type type;
-+ /* control minimum value or
-+ * mask for MMAL_CONTROL_TYPE_STD_MENU */
-+ s32 min;
-+ s32 max; /* maximum value of control */
-+ s32 def; /* default value of control */
-+ s32 step; /* step size of the control */
-+ const s64 *imenu; /* integer menu array */
-+ u32 mmal_id; /* mmal parameter id */
-+ bm2835_mmal_v4l2_ctrl_cb *setter;
-+ bool ignore_errors;
-+};
-+
-+struct v4l2_to_mmal_effects_setting {
-+ u32 v4l2_effect;
-+ u32 mmal_effect;
-+ s32 col_fx_enable;
-+ s32 col_fx_fixed_cbcr;
-+ u32 u;
-+ u32 v;
-+ u32 num_effect_params;
-+ u32 effect_params[MMAL_MAX_IMAGEFX_PARAMETERS];
-+};
-+
-+static const struct v4l2_to_mmal_effects_setting
-+ v4l2_to_mmal_effects_values[] = {
-+ { V4L2_COLORFX_NONE, MMAL_PARAM_IMAGEFX_NONE,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_BW, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 0, 128, 128, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SEPIA, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 0, 87, 151, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_NEGATIVE, MMAL_PARAM_IMAGEFX_NEGATIVE,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_EMBOSS, MMAL_PARAM_IMAGEFX_EMBOSS,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SKETCH, MMAL_PARAM_IMAGEFX_SKETCH,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SKY_BLUE, MMAL_PARAM_IMAGEFX_PASTEL,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_GRASS_GREEN, MMAL_PARAM_IMAGEFX_WATERCOLOUR,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SKIN_WHITEN, MMAL_PARAM_IMAGEFX_WASHEDOUT,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_VIVID, MMAL_PARAM_IMAGEFX_SATURATION,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_AQUA, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 0, 171, 121, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_ART_FREEZE, MMAL_PARAM_IMAGEFX_HATCH,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SILHOUETTE, MMAL_PARAM_IMAGEFX_FILM,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SOLARIZATION, MMAL_PARAM_IMAGEFX_SOLARIZE,
-+ 0, 0, 0, 0, 5, {1, 128, 160, 160, 48} },
-+ { V4L2_COLORFX_ANTIQUE, MMAL_PARAM_IMAGEFX_COLOURBALANCE,
-+ 0, 0, 0, 0, 3, {108, 274, 238, 0, 0} },
-+ { V4L2_COLORFX_SET_CBCR, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 1, 0, 0, 0, {0, 0, 0, 0, 0} }
-+};
-+
-+struct v4l2_mmal_scene_config {
-+ enum v4l2_scene_mode v4l2_scene;
-+ enum mmal_parameter_exposuremode exposure_mode;
-+ enum mmal_parameter_exposuremeteringmode metering_mode;
-+};
-+
-+static const struct v4l2_mmal_scene_config scene_configs[] = {
-+ /* V4L2_SCENE_MODE_NONE automatically added */
-+ {
-+ V4L2_SCENE_MODE_NIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_NIGHT,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE
-+ },
-+ {
-+ V4L2_SCENE_MODE_SPORTS,
-+ MMAL_PARAM_EXPOSUREMODE_SPORTS,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE
-+ },
-+};
-+
-+/* control handlers*/
-+
-+static int ctrl_set_rational(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ struct mmal_parameter_rational rational_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ rational_value.num = ctrl->val;
-+ rational_value.den = 100;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &rational_value,
-+ sizeof(rational_value));
-+}
-+
-+static int ctrl_set_value(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ u32_value = ctrl->val;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min)
-+ return 1;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ u32_value = mmal_ctrl->imenu[ctrl->val];
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_value_ev(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ s32 s32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ s32_value = (ctrl->val-12)*2; /* Convert from index to 1/6ths */
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &s32_value, sizeof(s32_value));
-+}
-+
-+static int ctrl_set_rotate(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret;
-+ u32 u32_value;
-+ struct vchiq_mmal_component *camera;
-+
-+ camera = dev->component[MMAL_COMPONENT_CAMERA];
-+
-+ u32_value = ((ctrl->val % 360) / 90) * 90;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+
-+ return ret;
-+}
-+
-+static int ctrl_set_flip(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret;
-+ u32 u32_value;
-+ struct vchiq_mmal_component *camera;
-+
-+ if (ctrl->id == V4L2_CID_HFLIP)
-+ dev->hflip = ctrl->val;
-+ else
-+ dev->vflip = ctrl->val;
-+
-+ camera = dev->component[MMAL_COMPONENT_CAMERA];
-+
-+ if (dev->hflip && dev->vflip)
-+ u32_value = MMAL_PARAM_MIRROR_BOTH;
-+ else if (dev->hflip)
-+ u32_value = MMAL_PARAM_MIRROR_HORIZONTAL;
-+ else if (dev->vflip)
-+ u32_value = MMAL_PARAM_MIRROR_VERTICAL;
-+ else
-+ u32_value = MMAL_PARAM_MIRROR_NONE;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+
-+ return ret;
-+
-+}
-+
-+static int ctrl_set_exposure(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ enum mmal_parameter_exposuremode exp_mode = dev->exposure_mode_user;
-+ u32 shutter_speed = 0;
-+ struct vchiq_mmal_port *control;
-+ int ret = 0;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED) {
-+ /* V4L2 is in 100usec increments.
-+ * MMAL is 1usec.
-+ */
-+ dev->manual_shutter_speed = ctrl->val * 100;
-+ } else if (mmal_ctrl->mmal_id == MMAL_PARAMETER_EXPOSURE_MODE) {
-+ switch (ctrl->val) {
-+ case V4L2_EXPOSURE_AUTO:
-+ exp_mode = MMAL_PARAM_EXPOSUREMODE_AUTO;
-+ break;
-+
-+ case V4L2_EXPOSURE_MANUAL:
-+ exp_mode = MMAL_PARAM_EXPOSUREMODE_OFF;
-+ break;
-+ }
-+ dev->exposure_mode_user = exp_mode;
-+ dev->exposure_mode_v4l2_user = ctrl->val;
-+ } else if (mmal_ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {
-+ dev->exp_auto_priority = ctrl->val;
-+ }
-+
-+ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) {
-+ if (exp_mode == MMAL_PARAM_EXPOSUREMODE_OFF)
-+ shutter_speed = dev->manual_shutter_speed;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &shutter_speed,
-+ sizeof(shutter_speed));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &exp_mode,
-+ sizeof(u32));
-+ dev->exposure_mode_active = exp_mode;
-+ }
-+ /* exposure_dynamic_framerate (V4L2_CID_EXPOSURE_AUTO_PRIORITY) should
-+ * always apply irrespective of scene mode.
-+ */
-+ ret += set_framerate_params(dev);
-+
-+ return ret;
-+}
-+
-+static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ switch (ctrl->val) {
-+ case V4L2_EXPOSURE_METERING_AVERAGE:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE;
-+ break;
-+
-+ case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT;
-+ break;
-+
-+ case V4L2_EXPOSURE_METERING_SPOT:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT;
-+ break;
-+
-+ /* todo matrix weighting not added to Linux API till 3.9
-+ case V4L2_EXPOSURE_METERING_MATRIX:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX;
-+ break;
-+ */
-+
-+ }
-+
-+ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) {
-+ struct vchiq_mmal_port *control;
-+ u32 u32_value = dev->metering_mode;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ } else
-+ return 0;
-+}
-+
-+static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ switch (ctrl->val) {
-+ case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_OFF;
-+ break;
-+ case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_50HZ;
-+ break;
-+ case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_60HZ;
-+ break;
-+ case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_AUTO;
-+ break;
-+ }
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_awb_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ switch (ctrl->val) {
-+ case V4L2_WHITE_BALANCE_MANUAL:
-+ u32_value = MMAL_PARAM_AWBMODE_OFF;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_AUTO:
-+ u32_value = MMAL_PARAM_AWBMODE_AUTO;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_INCANDESCENT:
-+ u32_value = MMAL_PARAM_AWBMODE_INCANDESCENT;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_FLUORESCENT:
-+ u32_value = MMAL_PARAM_AWBMODE_FLUORESCENT;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_FLUORESCENT_H:
-+ u32_value = MMAL_PARAM_AWBMODE_TUNGSTEN;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_HORIZON:
-+ u32_value = MMAL_PARAM_AWBMODE_HORIZON;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_DAYLIGHT:
-+ u32_value = MMAL_PARAM_AWBMODE_SUNLIGHT;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_FLASH:
-+ u32_value = MMAL_PARAM_AWBMODE_FLASH;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_CLOUDY:
-+ u32_value = MMAL_PARAM_AWBMODE_CLOUDY;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_SHADE:
-+ u32_value = MMAL_PARAM_AWBMODE_SHADE;
-+ break;
-+
-+ }
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_awb_gains(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ struct vchiq_mmal_port *control;
-+ struct mmal_parameter_awbgains gains;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ if (ctrl->id == V4L2_CID_RED_BALANCE)
-+ dev->red_gain = ctrl->val;
-+ else if (ctrl->id == V4L2_CID_BLUE_BALANCE)
-+ dev->blue_gain = ctrl->val;
-+
-+ gains.r_gain.num = dev->red_gain;
-+ gains.b_gain.num = dev->blue_gain;
-+ gains.r_gain.den = gains.b_gain.den = 1000;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &gains, sizeof(gains));
-+}
-+
-+static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret = -EINVAL;
-+ int i, j;
-+ struct vchiq_mmal_port *control;
-+ struct mmal_parameter_imagefx_parameters imagefx;
-+
-+ for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) {
-+ if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) {
-+
-+ imagefx.effect =
-+ v4l2_to_mmal_effects_values[i].mmal_effect;
-+ imagefx.num_effect_params =
-+ v4l2_to_mmal_effects_values[i].num_effect_params;
-+
-+ if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS)
-+ imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS;
-+
-+ for (j = 0; j < imagefx.num_effect_params; j++)
-+ imagefx.effect_parameter[j] =
-+ v4l2_to_mmal_effects_values[i].effect_params[j];
-+
-+ dev->colourfx.enable =
-+ v4l2_to_mmal_effects_values[i].col_fx_enable;
-+ if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) {
-+ dev->colourfx.u =
-+ v4l2_to_mmal_effects_values[i].u;
-+ dev->colourfx.v =
-+ v4l2_to_mmal_effects_values[i].v;
-+ }
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ ret = vchiq_mmal_port_parameter_set(
-+ dev->instance, control,
-+ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
-+ &imagefx, sizeof(imagefx));
-+ if (ret)
-+ goto exit;
-+
-+ ret = vchiq_mmal_port_parameter_set(
-+ dev->instance, control,
-+ MMAL_PARAMETER_COLOUR_EFFECT,
-+ &dev->colourfx, sizeof(dev->colourfx));
-+ }
-+ }
-+
-+exit:
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "mmal_ctrl:%p ctrl id:0x%x ctrl val:%d imagefx:0x%x color_effect:%s u:%d v:%d ret %d(%d)\n",
-+ mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect,
-+ dev->colourfx.enable ? "true" : "false",
-+ dev->colourfx.u, dev->colourfx.v,
-+ ret, (ret == 0 ? 0 : -EINVAL));
-+ return (ret == 0 ? 0 : EINVAL);
-+}
-+
-+static int ctrl_set_colfx(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret = -EINVAL;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ dev->colourfx.enable = (ctrl->val & 0xff00) >> 8;
-+ dev->colourfx.enable = ctrl->val & 0xff;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_COLOUR_EFFECT,
-+ &dev->colourfx, sizeof(dev->colourfx));
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n",
-+ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret,
-+ (ret == 0 ? 0 : -EINVAL));
-+ return (ret == 0 ? 0 : EINVAL);
-+}
-+
-+static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret;
-+ struct vchiq_mmal_port *encoder_out;
-+
-+ dev->capture.encode_bitrate = ctrl->val;
-+
-+ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
-+ mmal_ctrl->mmal_id,
-+ &ctrl->val, sizeof(ctrl->val));
-+ ret = 0;
-+ return ret;
-+}
-+
-+static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 bitrate_mode;
-+ struct vchiq_mmal_port *encoder_out;
-+
-+ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+
-+ dev->capture.encode_bitrate_mode = ctrl->val;
-+ switch (ctrl->val) {
-+ default:
-+ case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
-+ bitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE;
-+ break;
-+ case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
-+ bitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT;
-+ break;
-+ }
-+
-+ vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
-+ mmal_ctrl->mmal_id,
-+ &bitrate_mode,
-+ sizeof(bitrate_mode));
-+ return 0;
-+}
-+
-+static int ctrl_set_image_encode_output(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *jpeg_out;
-+
-+ jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
-+
-+ u32_value = ctrl->val;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, jpeg_out,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_video_encode_param_output(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *vid_enc_ctl;
-+
-+ vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+
-+ u32_value = ctrl->val;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, vid_enc_ctl,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_video_encode_profile_level(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ struct mmal_parameter_video_profile param;
-+ int ret = 0;
-+
-+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) {
-+ switch (ctrl->val) {
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
-+ dev->capture.enc_profile = ctrl->val;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) {
-+ switch (ctrl->val) {
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
-+ dev->capture.enc_level = ctrl->val;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+ }
-+
-+ if (!ret) {
-+ switch (dev->capture.enc_profile) {
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
-+ param.profile = MMAL_VIDEO_PROFILE_H264_BASELINE;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
-+ param.profile =
-+ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
-+ param.profile = MMAL_VIDEO_PROFILE_H264_MAIN;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
-+ param.profile = MMAL_VIDEO_PROFILE_H264_HIGH;
-+ break;
-+ default:
-+ /* Should never get here */
-+ break;
-+ }
-+
-+ switch (dev->capture.enc_level) {
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_1;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
-+ param.level = MMAL_VIDEO_LEVEL_H264_1b;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
-+ param.level = MMAL_VIDEO_LEVEL_H264_11;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
-+ param.level = MMAL_VIDEO_LEVEL_H264_12;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
-+ param.level = MMAL_VIDEO_LEVEL_H264_13;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_2;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
-+ param.level = MMAL_VIDEO_LEVEL_H264_21;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
-+ param.level = MMAL_VIDEO_LEVEL_H264_22;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_3;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
-+ param.level = MMAL_VIDEO_LEVEL_H264_31;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
-+ param.level = MMAL_VIDEO_LEVEL_H264_32;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_4;
-+ break;
-+ default:
-+ /* Should never get here */
-+ break;
-+ }
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0],
-+ mmal_ctrl->mmal_id,
-+ &param, sizeof(param));
-+ }
-+ return ret;
-+}
-+
-+static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret = 0;
-+ int shutter_speed;
-+ struct vchiq_mmal_port *control;
-+
-+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "scene mode selected %d, was %d\n", ctrl->val,
-+ dev->scene_mode);
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ if (ctrl->val == dev->scene_mode)
-+ return 0;
-+
-+ if (ctrl->val == V4L2_SCENE_MODE_NONE) {
-+ /* Restore all user selections */
-+ dev->scene_mode = V4L2_SCENE_MODE_NONE;
-+
-+ if (dev->exposure_mode_user == MMAL_PARAM_EXPOSUREMODE_OFF)
-+ shutter_speed = dev->manual_shutter_speed;
-+ else
-+ shutter_speed = 0;
-+
-+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n",
-+ __func__, shutter_speed, dev->exposure_mode_user,
-+ dev->metering_mode);
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &shutter_speed,
-+ sizeof(shutter_speed));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &dev->exposure_mode_user,
-+ sizeof(u32));
-+ dev->exposure_mode_active = dev->exposure_mode_user;
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXP_METERING_MODE,
-+ &dev->metering_mode,
-+ sizeof(u32));
-+ ret += set_framerate_params(dev);
-+ } else {
-+ /* Set up scene mode */
-+ int i;
-+ const struct v4l2_mmal_scene_config *scene = NULL;
-+ int shutter_speed;
-+ enum mmal_parameter_exposuremode exposure_mode;
-+ enum mmal_parameter_exposuremeteringmode metering_mode;
-+
-+ for (i = 0; i < ARRAY_SIZE(scene_configs); i++) {
-+ if (scene_configs[i].v4l2_scene ==
-+ ctrl->val) {
-+ scene = &scene_configs[i];
-+ break;
-+ }
-+ }
-+ if (i >= ARRAY_SIZE(scene_configs))
-+ return -EINVAL;
-+
-+ /* Set all the values */
-+ dev->scene_mode = ctrl->val;
-+
-+ if (scene->exposure_mode == MMAL_PARAM_EXPOSUREMODE_OFF)
-+ shutter_speed = dev->manual_shutter_speed;
-+ else
-+ shutter_speed = 0;
-+ exposure_mode = scene->exposure_mode;
-+ metering_mode = scene->metering_mode;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n",
-+ __func__, shutter_speed, exposure_mode, metering_mode);
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &shutter_speed,
-+ sizeof(shutter_speed));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &exposure_mode,
-+ sizeof(u32));
-+ dev->exposure_mode_active = exposure_mode;
-+ ret += vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &exposure_mode,
-+ sizeof(u32));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_EXP_METERING_MODE,
-+ &metering_mode,
-+ sizeof(u32));
-+ ret += set_framerate_params(dev);
-+ }
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: Setting scene to %d, ret=%d\n",
-+ __func__, ctrl->val, ret);
-+ ret = -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+static int bm2835_mmal_s_ctrl(struct v4l2_ctrl *ctrl)
-+{
-+ struct bm2835_mmal_dev *dev =
-+ container_of(ctrl->handler, struct bm2835_mmal_dev,
-+ ctrl_handler);
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl = ctrl->priv;
-+ int ret;
-+
-+ if ((mmal_ctrl == NULL) ||
-+ (mmal_ctrl->id != ctrl->id) ||
-+ (mmal_ctrl->setter == NULL)) {
-+ pr_warn("mmal_ctrl:%p ctrl id:%d\n", mmal_ctrl, ctrl->id);
-+ return -EINVAL;
-+ }
-+
-+ ret = mmal_ctrl->setter(dev, ctrl, mmal_ctrl);
-+ if (ret)
-+ pr_warn("ctrl id:%d/MMAL param %08X- returned ret %d\n",
-+ ctrl->id, mmal_ctrl->mmal_id, ret);
-+ if (mmal_ctrl->ignore_errors)
-+ ret = 0;
-+ return ret;
-+}
-+
-+static const struct v4l2_ctrl_ops bm2835_mmal_ctrl_ops = {
-+ .s_ctrl = bm2835_mmal_s_ctrl,
-+};
-+
-+
-+
-+static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = {
-+ {
-+ V4L2_CID_SATURATION, MMAL_CONTROL_TYPE_STD,
-+ -100, 100, 0, 1, NULL,
-+ MMAL_PARAMETER_SATURATION,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_SHARPNESS, MMAL_CONTROL_TYPE_STD,
-+ -100, 100, 0, 1, NULL,
-+ MMAL_PARAMETER_SHARPNESS,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_CONTRAST, MMAL_CONTROL_TYPE_STD,
-+ -100, 100, 0, 1, NULL,
-+ MMAL_PARAMETER_CONTRAST,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_BRIGHTNESS, MMAL_CONTROL_TYPE_STD,
-+ 0, 100, 50, 1, NULL,
-+ MMAL_PARAMETER_BRIGHTNESS,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU,
-+ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu,
-+ MMAL_PARAMETER_ISO,
-+ &ctrl_set_value_menu,
-+ false
-+ },
-+ {
-+ V4L2_CID_IMAGE_STABILIZATION, MMAL_CONTROL_TYPE_STD,
-+ 0, 1, 0, 1, NULL,
-+ MMAL_PARAMETER_VIDEO_STABILISATION,
-+ &ctrl_set_value,
-+ false
-+ },
-+/* {
-+ 0, MMAL_CONTROL_TYPE_CLUSTER, 3, 1, 0, NULL, 0, NULL
-+ }, */
-+ {
-+ V4L2_CID_EXPOSURE_AUTO, MMAL_CONTROL_TYPE_STD_MENU,
-+ ~0x03, 3, V4L2_EXPOSURE_AUTO, 0, NULL,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &ctrl_set_exposure,
-+ false
-+ },
-+/* todo this needs mixing in with set exposure
-+ {
-+ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
-+ },
-+ */
-+ {
-+ V4L2_CID_EXPOSURE_ABSOLUTE, MMAL_CONTROL_TYPE_STD,
-+ /* Units of 100usecs */
-+ 1, 1*1000*10, 100*10, 1, NULL,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &ctrl_set_exposure,
-+ false
-+ },
-+ {
-+ V4L2_CID_AUTO_EXPOSURE_BIAS, MMAL_CONTROL_TYPE_INT_MENU,
-+ 0, ARRAY_SIZE(ev_bias_qmenu) - 1,
-+ (ARRAY_SIZE(ev_bias_qmenu)+1)/2 - 1, 0, ev_bias_qmenu,
-+ MMAL_PARAMETER_EXPOSURE_COMP,
-+ &ctrl_set_value_ev,
-+ false
-+ },
-+ {
-+ V4L2_CID_EXPOSURE_AUTO_PRIORITY, MMAL_CONTROL_TYPE_STD,
-+ 0, 1,
-+ 0, 1, NULL,
-+ 0, /* Dummy MMAL ID as it gets mapped into FPS range*/
-+ &ctrl_set_exposure,
-+ false
-+ },
-+ {
-+ V4L2_CID_EXPOSURE_METERING,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ ~0x7, 2, V4L2_EXPOSURE_METERING_AVERAGE, 0, NULL,
-+ MMAL_PARAMETER_EXP_METERING_MODE,
-+ &ctrl_set_metering_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ ~0x3ff, 9, V4L2_WHITE_BALANCE_AUTO, 0, NULL,
-+ MMAL_PARAMETER_AWB_MODE,
-+ &ctrl_set_awb_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_RED_BALANCE, MMAL_CONTROL_TYPE_STD,
-+ 1, 7999, 1000, 1, NULL,
-+ MMAL_PARAMETER_CUSTOM_AWB_GAINS,
-+ &ctrl_set_awb_gains,
-+ false
-+ },
-+ {
-+ V4L2_CID_BLUE_BALANCE, MMAL_CONTROL_TYPE_STD,
-+ 1, 7999, 1000, 1, NULL,
-+ MMAL_PARAMETER_CUSTOM_AWB_GAINS,
-+ &ctrl_set_awb_gains,
-+ false
-+ },
-+ {
-+ V4L2_CID_COLORFX, MMAL_CONTROL_TYPE_STD_MENU,
-+ 0, 15, V4L2_COLORFX_NONE, 0, NULL,
-+ MMAL_PARAMETER_IMAGE_EFFECT,
-+ &ctrl_set_image_effect,
-+ false
-+ },
-+ {
-+ V4L2_CID_COLORFX_CBCR, MMAL_CONTROL_TYPE_STD,
-+ 0, 0xffff, 0x8080, 1, NULL,
-+ MMAL_PARAMETER_COLOUR_EFFECT,
-+ &ctrl_set_colfx,
-+ false
-+ },
-+ {
-+ V4L2_CID_ROTATE, MMAL_CONTROL_TYPE_STD,
-+ 0, 360, 0, 90, NULL,
-+ MMAL_PARAMETER_ROTATION,
-+ &ctrl_set_rotate,
-+ false
-+ },
-+ {
-+ V4L2_CID_HFLIP, MMAL_CONTROL_TYPE_STD,
-+ 0, 1, 0, 1, NULL,
-+ MMAL_PARAMETER_MIRROR,
-+ &ctrl_set_flip,
-+ false
-+ },
-+ {
-+ V4L2_CID_VFLIP, MMAL_CONTROL_TYPE_STD,
-+ 0, 1, 0, 1, NULL,
-+ MMAL_PARAMETER_MIRROR,
-+ &ctrl_set_flip,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_BITRATE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
-+ 0, ARRAY_SIZE(bitrate_mode_qmenu) - 1,
-+ 0, 0, bitrate_mode_qmenu,
-+ MMAL_PARAMETER_RATECONTROL,
-+ &ctrl_set_bitrate_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_BITRATE, MMAL_CONTROL_TYPE_STD,
-+ 25*1000, 25*1000*1000, 10*1000*1000, 25*1000, NULL,
-+ MMAL_PARAMETER_VIDEO_BIT_RATE,
-+ &ctrl_set_bitrate,
-+ false
-+ },
-+ {
-+ V4L2_CID_JPEG_COMPRESSION_QUALITY, MMAL_CONTROL_TYPE_STD,
-+ 1, 100,
-+ 30, 1, NULL,
-+ MMAL_PARAMETER_JPEG_Q_FACTOR,
-+ &ctrl_set_image_encode_output,
-+ false
-+ },
-+ {
-+ V4L2_CID_POWER_LINE_FREQUENCY, MMAL_CONTROL_TYPE_STD_MENU,
-+ 0, ARRAY_SIZE(mains_freq_qmenu) - 1,
-+ 1, 1, NULL,
-+ MMAL_PARAMETER_FLICKER_AVOID,
-+ &ctrl_set_flicker_avoidance,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER, MMAL_CONTROL_TYPE_STD,
-+ 0, 1,
-+ 0, 1, NULL,
-+ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER,
-+ &ctrl_set_video_encode_param_output,
-+ true /* Errors ignored as requires latest firmware to work */
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_H264_PROFILE,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ ~((1<<V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
-+ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
-+ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
-+ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
-+ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
-+ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 1, NULL,
-+ MMAL_PARAMETER_PROFILE,
-+ &ctrl_set_video_encode_profile_level,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_H264_LEVEL, MMAL_CONTROL_TYPE_STD_MENU,
-+ ~((1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_4_0)),
-+ V4L2_MPEG_VIDEO_H264_LEVEL_4_0,
-+ V4L2_MPEG_VIDEO_H264_LEVEL_4_0, 1, NULL,
-+ MMAL_PARAMETER_PROFILE,
-+ &ctrl_set_video_encode_profile_level,
-+ false
-+ },
-+ {
-+ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
-+ -1, /* Min is computed at runtime */
-+ V4L2_SCENE_MODE_TEXT,
-+ V4L2_SCENE_MODE_NONE, 1, NULL,
-+ MMAL_PARAMETER_PROFILE,
-+ &ctrl_set_scene_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, MMAL_CONTROL_TYPE_STD,
-+ 0, 0x7FFFFFFF, 60, 1, NULL,
-+ MMAL_PARAMETER_INTRAPERIOD,
-+ &ctrl_set_video_encode_param_output,
-+ false
-+ },
-+};
-+
-+int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev)
-+{
-+ int c;
-+ int ret = 0;
-+
-+ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
-+ if ((dev->ctrls[c]) && (v4l2_ctrls[c].setter)) {
-+ ret = v4l2_ctrls[c].setter(dev, dev->ctrls[c],
-+ &v4l2_ctrls[c]);
-+ if (!v4l2_ctrls[c].ignore_errors && ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Failed when setting default values for ctrl %d\n",
-+ c);
-+ break;
-+ }
-+ }
-+ }
-+ return ret;
-+}
-+
-+int set_framerate_params(struct bm2835_mmal_dev *dev)
-+{
-+ struct mmal_parameter_fps_range fps_range;
-+ int ret;
-+
-+ if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) &&
-+ (dev->exp_auto_priority)) {
-+ /* Variable FPS. Define min FPS as 1fps.
-+ * Max as max defined FPS.
-+ */
-+ fps_range.fps_low.num = 1;
-+ fps_range.fps_low.den = 1;
-+ fps_range.fps_high.num = dev->capture.timeperframe.denominator;
-+ fps_range.fps_high.den = dev->capture.timeperframe.numerator;
-+ } else {
-+ /* Fixed FPS - set min and max to be the same */
-+ fps_range.fps_low.num = fps_range.fps_high.num =
-+ dev->capture.timeperframe.denominator;
-+ fps_range.fps_low.den = fps_range.fps_high.den =
-+ dev->capture.timeperframe.numerator;
-+ }
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Set fps range to %d/%d to %d/%d\n",
-+ fps_range.fps_low.num,
-+ fps_range.fps_low.den,
-+ fps_range.fps_high.num,
-+ fps_range.fps_high.den
-+ );
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW],
-+ MMAL_PARAMETER_FPS_RANGE,
-+ &fps_range, sizeof(fps_range));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO],
-+ MMAL_PARAMETER_FPS_RANGE,
-+ &fps_range, sizeof(fps_range));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE],
-+ MMAL_PARAMETER_FPS_RANGE,
-+ &fps_range, sizeof(fps_range));
-+ if (ret)
-+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Failed to set fps ret %d\n",
-+ ret);
-+
-+ return ret;
-+
-+}
-+
-+int bm2835_mmal_init_controls(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl_handler *hdl)
-+{
-+ int c;
-+ const struct bm2835_mmal_v4l2_ctrl *ctrl;
-+
-+ v4l2_ctrl_handler_init(hdl, V4L2_CTRL_COUNT);
-+
-+ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
-+ ctrl = &v4l2_ctrls[c];
-+
-+ switch (ctrl->type) {
-+ case MMAL_CONTROL_TYPE_STD:
-+ dev->ctrls[c] = v4l2_ctrl_new_std(hdl,
-+ &bm2835_mmal_ctrl_ops, ctrl->id,
-+ ctrl->min, ctrl->max, ctrl->step, ctrl->def);
-+ break;
-+
-+ case MMAL_CONTROL_TYPE_STD_MENU:
-+ {
-+ int mask = ctrl->min;
-+
-+ if (ctrl->id == V4L2_CID_SCENE_MODE) {
-+ /* Special handling to work out the mask
-+ * value based on the scene_configs array
-+ * at runtime. Reduces the chance of
-+ * mismatches.
-+ */
-+ int i;
-+ mask = 1<<V4L2_SCENE_MODE_NONE;
-+ for (i = 0;
-+ i < ARRAY_SIZE(scene_configs);
-+ i++) {
-+ mask |= 1<<scene_configs[i].v4l2_scene;
-+ }
-+ mask = ~mask;
-+ }
-+
-+ dev->ctrls[c] = v4l2_ctrl_new_std_menu(hdl,
-+ &bm2835_mmal_ctrl_ops, ctrl->id,
-+ ctrl->max, mask, ctrl->def);
-+ break;
-+ }
-+
-+ case MMAL_CONTROL_TYPE_INT_MENU:
-+ dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl,
-+ &bm2835_mmal_ctrl_ops, ctrl->id,
-+ ctrl->max, ctrl->def, ctrl->imenu);
-+ break;
-+
-+ case MMAL_CONTROL_TYPE_CLUSTER:
-+ /* skip this entry when constructing controls */
-+ continue;
-+ }
-+
-+ if (hdl->error)
-+ break;
-+
-+ dev->ctrls[c]->priv = (void *)ctrl;
-+ }
-+
-+ if (hdl->error) {
-+ pr_err("error adding control %d/%d id 0x%x\n", c,
-+ V4L2_CTRL_COUNT, ctrl->id);
-+ return hdl->error;
-+ }
-+
-+ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
-+ ctrl = &v4l2_ctrls[c];
-+
-+ switch (ctrl->type) {
-+ case MMAL_CONTROL_TYPE_CLUSTER:
-+ v4l2_ctrl_auto_cluster(ctrl->min,
-+ &dev->ctrls[c+1],
-+ ctrl->max,
-+ ctrl->def);
-+ break;
-+
-+ case MMAL_CONTROL_TYPE_STD:
-+ case MMAL_CONTROL_TYPE_STD_MENU:
-+ case MMAL_CONTROL_TYPE_INT_MENU:
-+ break;
-+ }
-+
-+ }
-+
-+ return 0;
-+}
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/Kconfig linux-rpi/drivers/media/platform/bcm2835/Kconfig
---- linux-3.12.38/drivers/media/platform/bcm2835/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/Kconfig 2015-03-10 17:26:50.466216693 +0100
-@@ -0,0 +1,25 @@
-+# Broadcom VideoCore IV v4l2 camera support
-+
-+config VIDEO_BCM2835
-+ bool "Broadcom BCM2835 camera interface driver"
-+ depends on VIDEO_V4L2 && ARCH_BCM2708
-+ ---help---
-+ Say Y here to enable camera host interface devices for
-+ Broadcom BCM2835 SoC. This operates over the VCHIQ interface
-+ to a service running on VideoCore.
-+
-+
-+if VIDEO_BCM2835
-+
-+config VIDEO_BCM2835_MMAL
-+ tristate "Broadcom BM2835 MMAL camera interface driver"
-+ depends on BCM2708_VCHIQ
-+ select VIDEOBUF2_VMALLOC
-+ ---help---
-+ This is a V4L2 driver for the Broadcom BCM2835 MMAL camera host interface
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called bcm2835-v4l2.o
-+
-+
-+endif # VIDEO_BM2835
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/Makefile linux-rpi/drivers/media/platform/bcm2835/Makefile
---- linux-3.12.38/drivers/media/platform/bcm2835/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/Makefile 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,5 @@
-+bcm2835-v4l2-objs := bcm2835-camera.o controls.o mmal-vchiq.o
-+
-+obj-$(CONFIG_VIDEO_BCM2835_MMAL) += bcm2835-v4l2.o
-+
-+ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-common.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-common.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-common.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,53 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * MMAL structures
-+ *
-+ */
-+
-+#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24))
-+#define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l')
-+
-+/** Special value signalling that time is not known */
-+#define MMAL_TIME_UNKNOWN (1LL<<63)
-+
-+/* mapping between v4l and mmal video modes */
-+struct mmal_fmt {
-+ char *name;
-+ u32 fourcc; /* v4l2 format id */
-+ int flags; /* v4l2 flags field */
-+ u32 mmal;
-+ int depth;
-+ u32 mmal_component; /* MMAL component index to be used to encode */
-+};
-+
-+/* buffer for one video frame */
-+struct mmal_buffer {
-+ /* v4l buffer data -- must be first */
-+ struct vb2_buffer vb;
-+
-+ /* list of buffers available */
-+ struct list_head list;
-+
-+ void *buffer; /* buffer pointer */
-+ unsigned long buffer_size; /* size of allocated buffer */
-+};
-+
-+/* */
-+struct mmal_colourfx {
-+ s32 enable;
-+ u32 u;
-+ u32 v;
-+};
-+
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-encodings.h linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-encodings.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,127 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+#ifndef MMAL_ENCODINGS_H
-+#define MMAL_ENCODINGS_H
-+
-+#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4')
-+#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3')
-+#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V')
-+#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V')
-+#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V')
-+#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3')
-+#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2')
-+#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1')
-+#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1')
-+#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ')
-+#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ')
-+#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ')
-+#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O')
-+#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K')
-+#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G')
-+
-+#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G')
-+#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ')
-+#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ')
-+#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ')
-+#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ')
-+#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ')
-+
-+#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0')
-+#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0')
-+#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2')
-+#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2')
-+#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2')
-+#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V')
-+#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U')
-+#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y')
-+#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y')
-+#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2')
-+#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1')
-+#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B')
-+#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A')
-+#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R')
-+#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A')
-+#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2')
-+#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3')
-+#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4')
-+#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2')
-+#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3')
-+#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4')
-+
-+/** SAND Video (YUVUV128) format, native format understood by VideoCore.
-+ * This format is *not* opaque - if requested you will receive full frames
-+ * of YUV_UV video.
-+ */
-+#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D')
-+
-+/** VideoCore opaque image format, image handles are returned to
-+ * the host but not the actual image data.
-+ */
-+#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V')
-+
-+/** An EGL image handle
-+ */
-+#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I')
-+
-+/* }@ */
-+
-+/** \name Pre-defined audio encodings */
-+/* @{ */
-+#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U')
-+#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u')
-+#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S')
-+#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's')
-+#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F')
-+#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f')
-+
-+/* Pre-defined H264 encoding variants */
-+
-+/** ISO 14496-10 Annex B byte stream format */
-+#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0
-+/** ISO 14496-15 AVC stream format */
-+#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1')
-+/** Implicitly delineated NAL units without emulation prevention */
-+#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ')
-+
-+
-+/** \defgroup MmalColorSpace List of pre-defined video color spaces
-+ * This defines a list of common color spaces. This list isn't exhaustive and
-+ * is only provided as a convenience to avoid clients having to use FourCC
-+ * codes directly. However components are allowed to define and use their own
-+ * FourCC codes.
-+ */
-+/* @{ */
-+
-+/** Unknown color space */
-+#define MMAL_COLOR_SPACE_UNKNOWN 0
-+/** ITU-R BT.601-5 [SDTV] */
-+#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1')
-+/** ITU-R BT.709-3 [HDTV] */
-+#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9')
-+/** JPEG JFIF */
-+#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I')
-+/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */
-+#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C')
-+/** Society of Motion Picture and Television Engineers 240M (1999) */
-+#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0')
-+/** ITU-R BT.470-2 System M */
-+#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M')
-+/** ITU-R BT.470-2 System BG */
-+#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G')
-+/** JPEG JFIF, but with 16..255 luma */
-+#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6')
-+/* @} MmalColorSpace List */
-+
-+#endif /* MMAL_ENCODINGS_H */
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg-common.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,50 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#ifndef MMAL_MSG_COMMON_H
-+#define MMAL_MSG_COMMON_H
-+
-+enum mmal_msg_status {
-+ MMAL_MSG_STATUS_SUCCESS = 0, /**< Success */
-+ MMAL_MSG_STATUS_ENOMEM, /**< Out of memory */
-+ MMAL_MSG_STATUS_ENOSPC, /**< Out of resources other than memory */
-+ MMAL_MSG_STATUS_EINVAL, /**< Argument is invalid */
-+ MMAL_MSG_STATUS_ENOSYS, /**< Function not implemented */
-+ MMAL_MSG_STATUS_ENOENT, /**< No such file or directory */
-+ MMAL_MSG_STATUS_ENXIO, /**< No such device or address */
-+ MMAL_MSG_STATUS_EIO, /**< I/O error */
-+ MMAL_MSG_STATUS_ESPIPE, /**< Illegal seek */
-+ MMAL_MSG_STATUS_ECORRUPT, /**< Data is corrupt \attention */
-+ MMAL_MSG_STATUS_ENOTREADY, /**< Component is not ready */
-+ MMAL_MSG_STATUS_ECONFIG, /**< Component is not configured */
-+ MMAL_MSG_STATUS_EISCONN, /**< Port is already connected */
-+ MMAL_MSG_STATUS_ENOTCONN, /**< Port is disconnected */
-+ MMAL_MSG_STATUS_EAGAIN, /**< Resource temporarily unavailable. */
-+ MMAL_MSG_STATUS_EFAULT, /**< Bad address */
-+};
-+
-+struct mmal_rect {
-+ s32 x; /**< x coordinate (from left) */
-+ s32 y; /**< y coordinate (from top) */
-+ s32 width; /**< width */
-+ s32 height; /**< height */
-+};
-+
-+struct mmal_rational {
-+ s32 num; /**< Numerator */
-+ s32 den; /**< Denominator */
-+};
-+
-+#endif /* MMAL_MSG_COMMON_H */
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg-format.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg-format.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,81 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#ifndef MMAL_MSG_FORMAT_H
-+#define MMAL_MSG_FORMAT_H
-+
-+#include "mmal-msg-common.h"
-+
-+/* MMAL_ES_FORMAT_T */
-+
-+
-+struct mmal_audio_format {
-+ u32 channels; /**< Number of audio channels */
-+ u32 sample_rate; /**< Sample rate */
-+
-+ u32 bits_per_sample; /**< Bits per sample */
-+ u32 block_align; /**< Size of a block of data */
-+};
-+
-+struct mmal_video_format {
-+ u32 width; /**< Width of frame in pixels */
-+ u32 height; /**< Height of frame in rows of pixels */
-+ struct mmal_rect crop; /**< Visible region of the frame */
-+ struct mmal_rational frame_rate; /**< Frame rate */
-+ struct mmal_rational par; /**< Pixel aspect ratio */
-+
-+ /* FourCC specifying the color space of the video stream. See the
-+ * \ref MmalColorSpace "pre-defined color spaces" for some examples.
-+ */
-+ u32 color_space;
-+};
-+
-+struct mmal_subpicture_format {
-+ u32 x_offset;
-+ u32 y_offset;
-+};
-+
-+union mmal_es_specific_format {
-+ struct mmal_audio_format audio;
-+ struct mmal_video_format video;
-+ struct mmal_subpicture_format subpicture;
-+};
-+
-+/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
-+struct mmal_es_format {
-+ u32 type; /* enum mmal_es_type */
-+
-+ u32 encoding; /* FourCC specifying encoding of the elementary stream.*/
-+ u32 encoding_variant; /* FourCC specifying the specific
-+ * encoding variant of the elementary
-+ * stream.
-+ */
-+
-+ union mmal_es_specific_format *es; /* TODO: pointers in
-+ * message serialisation?!?
-+ */
-+ /* Type specific
-+ * information for the
-+ * elementary stream
-+ */
-+
-+ u32 bitrate; /**< Bitrate in bits per second */
-+ u32 flags; /**< Flags describing properties of the elementary stream. */
-+
-+ u32 extradata_size; /**< Size of the codec specific data */
-+ u8 *extradata; /**< Codec specific data */
-+};
-+
-+#endif /* MMAL_MSG_FORMAT_H */
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,404 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+/* all the data structures which serialise the MMAL protocol. note
-+ * these are directly mapped onto the recived message data.
-+ *
-+ * BEWARE: They seem to *assume* pointers are u32 and that there is no
-+ * structure padding!
-+ *
-+ * NOTE: this implementation uses kernel types to ensure sizes. Rather
-+ * than assigning values to enums to force their size the
-+ * implementation uses fixed size types and not the enums (though the
-+ * comments have the actual enum type
-+ */
-+
-+#define VC_MMAL_VER 15
-+#define VC_MMAL_MIN_VER 10
-+#define VC_MMAL_SERVER_NAME MAKE_FOURCC("mmal")
-+
-+/* max total message size is 512 bytes */
-+#define MMAL_MSG_MAX_SIZE 512
-+/* with six 32bit header elements max payload is therefore 488 bytes */
-+#define MMAL_MSG_MAX_PAYLOAD 488
-+
-+#include "mmal-msg-common.h"
-+#include "mmal-msg-format.h"
-+#include "mmal-msg-port.h"
-+
-+enum mmal_msg_type {
-+ MMAL_MSG_TYPE_QUIT = 1,
-+ MMAL_MSG_TYPE_SERVICE_CLOSED,
-+ MMAL_MSG_TYPE_GET_VERSION,
-+ MMAL_MSG_TYPE_COMPONENT_CREATE,
-+ MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */
-+ MMAL_MSG_TYPE_COMPONENT_ENABLE,
-+ MMAL_MSG_TYPE_COMPONENT_DISABLE,
-+ MMAL_MSG_TYPE_PORT_INFO_GET,
-+ MMAL_MSG_TYPE_PORT_INFO_SET,
-+ MMAL_MSG_TYPE_PORT_ACTION, /* 10 */
-+ MMAL_MSG_TYPE_BUFFER_FROM_HOST,
-+ MMAL_MSG_TYPE_BUFFER_TO_HOST,
-+ MMAL_MSG_TYPE_GET_STATS,
-+ MMAL_MSG_TYPE_PORT_PARAMETER_SET,
-+ MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */
-+ MMAL_MSG_TYPE_EVENT_TO_HOST,
-+ MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT,
-+ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR,
-+ MMAL_MSG_TYPE_CONSUME_MEM,
-+ MMAL_MSG_TYPE_LMK, /* 20 */
-+ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC,
-+ MMAL_MSG_TYPE_DRM_GET_LHS32,
-+ MMAL_MSG_TYPE_DRM_GET_TIME,
-+ MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN,
-+ MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */
-+ MMAL_MSG_TYPE_HOST_LOG,
-+ MMAL_MSG_TYPE_MSG_LAST
-+};
-+
-+/* port action request messages differ depending on the action type */
-+enum mmal_msg_port_action_type {
-+ MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0, /* Unkown action */
-+ MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */
-+ MMAL_MSG_PORT_ACTION_TYPE_DISABLE, /* Disable a port */
-+ MMAL_MSG_PORT_ACTION_TYPE_FLUSH, /* Flush a port */
-+ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, /* Connect ports */
-+ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, /* Disconnect ports */
-+ MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/
-+};
-+
-+struct mmal_msg_header {
-+ u32 magic;
-+ u32 type; /** enum mmal_msg_type */
-+
-+ /* Opaque handle to the control service */
-+ struct mmal_control_service *control_service;
-+
-+ struct mmal_msg_context *context; /** a u32 per message context */
-+ u32 status; /** The status of the vchiq operation */
-+ u32 padding;
-+};
-+
-+/* Send from VC to host to report version */
-+struct mmal_msg_version {
-+ u32 flags;
-+ u32 major;
-+ u32 minor;
-+ u32 minimum;
-+};
-+
-+/* request to VC to create component */
-+struct mmal_msg_component_create {
-+ void *client_component; /* component context */
-+ char name[128];
-+ u32 pid; /* For debug */
-+};
-+
-+/* reply from VC to component creation request */
-+struct mmal_msg_component_create_reply {
-+ u32 status; /** enum mmal_msg_status - how does this differ to
-+ * the one in the header?
-+ */
-+ u32 component_handle; /* VideoCore handle for component */
-+ u32 input_num; /* Number of input ports */
-+ u32 output_num; /* Number of output ports */
-+ u32 clock_num; /* Number of clock ports */
-+};
-+
-+/* request to VC to destroy a component */
-+struct mmal_msg_component_destroy {
-+ u32 component_handle;
-+};
-+
-+struct mmal_msg_component_destroy_reply {
-+ u32 status; /** The component destruction status */
-+};
-+
-+
-+/* request and reply to VC to enable a component */
-+struct mmal_msg_component_enable {
-+ u32 component_handle;
-+};
-+
-+struct mmal_msg_component_enable_reply {
-+ u32 status; /** The component enable status */
-+};
-+
-+
-+/* request and reply to VC to disable a component */
-+struct mmal_msg_component_disable {
-+ u32 component_handle;
-+};
-+
-+struct mmal_msg_component_disable_reply {
-+ u32 status; /** The component disable status */
-+};
-+
-+/* request to VC to get port information */
-+struct mmal_msg_port_info_get {
-+ u32 component_handle; /* component handle port is associated with */
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 index; /* port index to query */
-+};
-+
-+/* reply from VC to get port info request */
-+struct mmal_msg_port_info_get_reply {
-+ u32 status; /** enum mmal_msg_status */
-+ u32 component_handle; /* component handle port is associated with */
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 port_index; /* port indexed in query */
-+ s32 found; /* unused */
-+ u32 port_handle; /**< Handle to use for this port */
-+ struct mmal_port port;
-+ struct mmal_es_format format; /* elementry stream format */
-+ union mmal_es_specific_format es; /* es type specific data */
-+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; /* es extra data */
-+};
-+
-+/* request to VC to set port information */
-+struct mmal_msg_port_info_set {
-+ u32 component_handle;
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 port_index; /* port indexed in query */
-+ struct mmal_port port;
-+ struct mmal_es_format format;
-+ union mmal_es_specific_format es;
-+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];
-+};
-+
-+/* reply from VC to port info set request */
-+struct mmal_msg_port_info_set_reply {
-+ u32 status;
-+ u32 component_handle; /* component handle port is associated with */
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 index; /* port indexed in query */
-+ s32 found; /* unused */
-+ u32 port_handle; /**< Handle to use for this port */
-+ struct mmal_port port;
-+ struct mmal_es_format format;
-+ union mmal_es_specific_format es;
-+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];
-+};
-+
-+
-+/* port action requests that take a mmal_port as a parameter */
-+struct mmal_msg_port_action_port {
-+ u32 component_handle;
-+ u32 port_handle;
-+ u32 action; /* enum mmal_msg_port_action_type */
-+ struct mmal_port port;
-+};
-+
-+/* port action requests that take handles as a parameter */
-+struct mmal_msg_port_action_handle {
-+ u32 component_handle;
-+ u32 port_handle;
-+ u32 action; /* enum mmal_msg_port_action_type */
-+ u32 connect_component_handle;
-+ u32 connect_port_handle;
-+};
-+
-+struct mmal_msg_port_action_reply {
-+ u32 status; /** The port action operation status */
-+};
-+
-+
-+
-+
-+/* MMAL buffer transfer */
-+
-+/** Size of space reserved in a buffer message for short messages. */
-+#define MMAL_VC_SHORT_DATA 128
-+
-+/** Signals that the current payload is the end of the stream of data */
-+#define MMAL_BUFFER_HEADER_FLAG_EOS (1<<0)
-+/** Signals that the start of the current payload starts a frame */
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME_START (1<<1)
-+/** Signals that the end of the current payload ends a frame */
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME_END (1<<2)
-+/** Signals that the current payload contains only complete frames (>1) */
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME \
-+ (MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END)
-+/** Signals that the current payload is a keyframe (i.e. self decodable) */
-+#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME (1<<3)
-+/** Signals a discontinuity in the stream of data (e.g. after a seek).
-+ * Can be used for instance by a decoder to reset its state */
-+#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY (1<<4)
-+/** Signals a buffer containing some kind of config data for the component
-+ * (e.g. codec config data) */
-+#define MMAL_BUFFER_HEADER_FLAG_CONFIG (1<<5)
-+/** Signals an encrypted payload */
-+#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED (1<<6)
-+/** Signals a buffer containing side information */
-+#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO (1<<7)
-+/** Signals a buffer which is the snapshot/postview image from a stills
-+ * capture
-+ */
-+#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT (1<<8)
-+/** Signals a buffer which contains data known to be corrupted */
-+#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED (1<<9)
-+/** Signals that a buffer failed to be transmitted */
-+#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED (1<<10)
-+
-+struct mmal_driver_buffer {
-+ u32 magic;
-+ u32 component_handle;
-+ u32 port_handle;
-+ void *client_context;
-+};
-+
-+/* buffer header */
-+struct mmal_buffer_header {
-+ struct mmal_buffer_header *next; /* next header */
-+ void *priv; /* framework private data */
-+ u32 cmd;
-+ void *data;
-+ u32 alloc_size;
-+ u32 length;
-+ u32 offset;
-+ u32 flags;
-+ s64 pts;
-+ s64 dts;
-+ void *type;
-+ void *user_data;
-+};
-+
-+struct mmal_buffer_header_type_specific {
-+ union {
-+ struct {
-+ u32 planes;
-+ u32 offset[4];
-+ u32 pitch[4];
-+ u32 flags;
-+ } video;
-+ } u;
-+};
-+
-+struct mmal_msg_buffer_from_host {
-+ /* The front 32 bytes of the buffer header are copied
-+ * back to us in the reply to allow for context. This
-+ * area is used to store two mmal_driver_buffer structures to
-+ * allow for multiple concurrent service users.
-+ */
-+ /* control data */
-+ struct mmal_driver_buffer drvbuf;
-+
-+ /* referenced control data for passthrough buffer management */
-+ struct mmal_driver_buffer drvbuf_ref;
-+ struct mmal_buffer_header buffer_header; /* buffer header itself */
-+ struct mmal_buffer_header_type_specific buffer_header_type_specific;
-+ s32 is_zero_copy;
-+ s32 has_reference;
-+
-+ /** allows short data to be xfered in control message */
-+ u32 payload_in_message;
-+ u8 short_data[MMAL_VC_SHORT_DATA];
-+};
-+
-+
-+/* port parameter setting */
-+
-+#define MMAL_WORKER_PORT_PARAMETER_SPACE 96
-+
-+struct mmal_msg_port_parameter_set {
-+ u32 component_handle; /* component */
-+ u32 port_handle; /* port */
-+ u32 id; /* Parameter ID */
-+ u32 size; /* Parameter size */
-+ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
-+};
-+
-+struct mmal_msg_port_parameter_set_reply {
-+ u32 status; /** enum mmal_msg_status todo: how does this
-+ * differ to the one in the header?
-+ */
-+};
-+
-+/* port parameter getting */
-+
-+struct mmal_msg_port_parameter_get {
-+ u32 component_handle; /* component */
-+ u32 port_handle; /* port */
-+ u32 id; /* Parameter ID */
-+ u32 size; /* Parameter size */
-+};
-+
-+struct mmal_msg_port_parameter_get_reply {
-+ u32 status; /* Status of mmal_port_parameter_get call */
-+ u32 id; /* Parameter ID */
-+ u32 size; /* Parameter size */
-+ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
-+};
-+
-+/* event messages */
-+#define MMAL_WORKER_EVENT_SPACE 256
-+
-+struct mmal_msg_event_to_host {
-+ void *client_component; /* component context */
-+
-+ u32 port_type;
-+ u32 port_num;
-+
-+ u32 cmd;
-+ u32 length;
-+ u8 data[MMAL_WORKER_EVENT_SPACE];
-+ struct mmal_buffer_header *delayed_buffer;
-+};
-+
-+/* all mmal messages are serialised through this structure */
-+struct mmal_msg {
-+ /* header */
-+ struct mmal_msg_header h;
-+ /* payload */
-+ union {
-+ struct mmal_msg_version version;
-+
-+ struct mmal_msg_component_create component_create;
-+ struct mmal_msg_component_create_reply component_create_reply;
-+
-+ struct mmal_msg_component_destroy component_destroy;
-+ struct mmal_msg_component_destroy_reply component_destroy_reply;
-+
-+ struct mmal_msg_component_enable component_enable;
-+ struct mmal_msg_component_enable_reply component_enable_reply;
-+
-+ struct mmal_msg_component_disable component_disable;
-+ struct mmal_msg_component_disable_reply component_disable_reply;
-+
-+ struct mmal_msg_port_info_get port_info_get;
-+ struct mmal_msg_port_info_get_reply port_info_get_reply;
-+
-+ struct mmal_msg_port_info_set port_info_set;
-+ struct mmal_msg_port_info_set_reply port_info_set_reply;
-+
-+ struct mmal_msg_port_action_port port_action_port;
-+ struct mmal_msg_port_action_handle port_action_handle;
-+ struct mmal_msg_port_action_reply port_action_reply;
-+
-+ struct mmal_msg_buffer_from_host buffer_from_host;
-+
-+ struct mmal_msg_port_parameter_set port_parameter_set;
-+ struct mmal_msg_port_parameter_set_reply
-+ port_parameter_set_reply;
-+ struct mmal_msg_port_parameter_get
-+ port_parameter_get;
-+ struct mmal_msg_port_parameter_get_reply
-+ port_parameter_get_reply;
-+
-+ struct mmal_msg_event_to_host event_to_host;
-+
-+ u8 payload[MMAL_MSG_MAX_PAYLOAD];
-+ } u;
-+};
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg-port.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-msg-port.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,107 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+/* MMAL_PORT_TYPE_T */
-+enum mmal_port_type {
-+ MMAL_PORT_TYPE_UNKNOWN = 0, /**< Unknown port type */
-+ MMAL_PORT_TYPE_CONTROL, /**< Control port */
-+ MMAL_PORT_TYPE_INPUT, /**< Input port */
-+ MMAL_PORT_TYPE_OUTPUT, /**< Output port */
-+ MMAL_PORT_TYPE_CLOCK, /**< Clock port */
-+};
-+
-+/** The port is pass-through and doesn't need buffer headers allocated */
-+#define MMAL_PORT_CAPABILITY_PASSTHROUGH 0x01
-+/** The port wants to allocate the buffer payloads.
-+ * This signals a preference that payload allocation should be done
-+ * on this port for efficiency reasons. */
-+#define MMAL_PORT_CAPABILITY_ALLOCATION 0x02
-+/** The port supports format change events.
-+ * This applies to input ports and is used to let the client know
-+ * whether the port supports being reconfigured via a format
-+ * change event (i.e. without having to disable the port). */
-+#define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE 0x04
-+
-+/* mmal port structure (MMAL_PORT_T)
-+ *
-+ * most elements are informational only, the pointer values for
-+ * interogation messages are generally provided as additional
-+ * strucures within the message. When used to set values only teh
-+ * buffer_num, buffer_size and userdata parameters are writable.
-+ */
-+struct mmal_port {
-+ void *priv; /* Private member used by the framework */
-+ const char *name; /* Port name. Used for debugging purposes (RO) */
-+
-+ u32 type; /* Type of the port (RO) enum mmal_port_type */
-+ u16 index; /* Index of the port in its type list (RO) */
-+ u16 index_all; /* Index of the port in the list of all ports (RO) */
-+
-+ u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */
-+ struct mmal_es_format *format; /* Format of the elementary stream */
-+
-+ u32 buffer_num_min; /* Minimum number of buffers the port
-+ * requires (RO). This is set by the
-+ * component.
-+ */
-+
-+ u32 buffer_size_min; /* Minimum size of buffers the port
-+ * requires (RO). This is set by the
-+ * component.
-+ */
-+
-+ u32 buffer_alignment_min; /* Minimum alignment requirement for
-+ * the buffers (RO). A value of
-+ * zero means no special alignment
-+ * requirements. This is set by the
-+ * component.
-+ */
-+
-+ u32 buffer_num_recommended; /* Number of buffers the port
-+ * recommends for optimal
-+ * performance (RO). A value of
-+ * zero means no special
-+ * recommendation. This is set
-+ * by the component.
-+ */
-+
-+ u32 buffer_size_recommended; /* Size of buffers the port
-+ * recommends for optimal
-+ * performance (RO). A value of
-+ * zero means no special
-+ * recommendation. This is set
-+ * by the component.
-+ */
-+
-+ u32 buffer_num; /* Actual number of buffers the port will use.
-+ * This is set by the client.
-+ */
-+
-+ u32 buffer_size; /* Actual maximum size of the buffers that
-+ * will be sent to the port. This is set by
-+ * the client.
-+ */
-+
-+ void *component; /* Component this port belongs to (Read Only) */
-+
-+ void *userdata; /* Field reserved for use by the client */
-+
-+ u32 capabilities; /* Flags describing the capabilities of a
-+ * port (RO). Bitwise combination of \ref
-+ * portcapabilities "Port capabilities"
-+ * values.
-+ */
-+
-+};
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-parameters.h linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-parameters.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,656 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+/* common parameters */
-+
-+/** @name Parameter groups
-+ * Parameters are divided into groups, and then allocated sequentially within
-+ * a group using an enum.
-+ * @{
-+ */
-+
-+/** Common parameter ID group, used with many types of component. */
-+#define MMAL_PARAMETER_GROUP_COMMON (0<<16)
-+/** Camera-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_CAMERA (1<<16)
-+/** Video-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_VIDEO (2<<16)
-+/** Audio-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_AUDIO (3<<16)
-+/** Clock-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_CLOCK (4<<16)
-+/** Miracast-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_MIRACAST (5<<16)
-+
-+/* Common parameters */
-+enum mmal_parameter_common_type {
-+ MMAL_PARAMETER_UNUSED /**< Never a valid parameter ID */
-+ = MMAL_PARAMETER_GROUP_COMMON,
-+ MMAL_PARAMETER_SUPPORTED_ENCODINGS, /**< MMAL_PARAMETER_ENCODING_T */
-+ MMAL_PARAMETER_URI, /**< MMAL_PARAMETER_URI_T */
-+
-+ /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */
-+ MMAL_PARAMETER_CHANGE_EVENT_REQUEST,
-+
-+ /** MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_ZERO_COPY,
-+
-+ /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */
-+ MMAL_PARAMETER_BUFFER_REQUIREMENTS,
-+
-+ MMAL_PARAMETER_STATISTICS, /**< MMAL_PARAMETER_STATISTICS_T */
-+ MMAL_PARAMETER_CORE_STATISTICS, /**< MMAL_PARAMETER_CORE_STATISTICS_T */
-+ MMAL_PARAMETER_MEM_USAGE, /**< MMAL_PARAMETER_MEM_USAGE_T */
-+ MMAL_PARAMETER_BUFFER_FLAG_FILTER, /**< MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_SEEK, /**< MMAL_PARAMETER_SEEK_T */
-+ MMAL_PARAMETER_POWERMON_ENABLE, /**< MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_LOGGING, /**< MMAL_PARAMETER_LOGGING_T */
-+ MMAL_PARAMETER_SYSTEM_TIME, /**< MMAL_PARAMETER_UINT64_T */
-+ MMAL_PARAMETER_NO_IMAGE_PADDING /**< MMAL_PARAMETER_BOOLEAN_T */
-+};
-+
-+/* camera parameters */
-+
-+enum mmal_parameter_camera_type {
-+ /* 0 */
-+ /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */
-+ MMAL_PARAMETER_THUMBNAIL_CONFIGURATION
-+ = MMAL_PARAMETER_GROUP_CAMERA,
-+ MMAL_PARAMETER_CAPTURE_QUALITY, /**< Unused? */
-+ MMAL_PARAMETER_ROTATION, /**< @ref MMAL_PARAMETER_INT32_T */
-+ MMAL_PARAMETER_EXIF_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_EXIF, /**< @ref MMAL_PARAMETER_EXIF_T */
-+ MMAL_PARAMETER_AWB_MODE, /**< @ref MMAL_PARAM_AWBMODE_T */
-+ MMAL_PARAMETER_IMAGE_EFFECT, /**< @ref MMAL_PARAMETER_IMAGEFX_T */
-+ MMAL_PARAMETER_COLOUR_EFFECT, /**< @ref MMAL_PARAMETER_COLOURFX_T */
-+ MMAL_PARAMETER_FLICKER_AVOID, /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */
-+ MMAL_PARAMETER_FLASH, /**< @ref MMAL_PARAMETER_FLASH_T */
-+ MMAL_PARAMETER_REDEYE, /**< @ref MMAL_PARAMETER_REDEYE_T */
-+ MMAL_PARAMETER_FOCUS, /**< @ref MMAL_PARAMETER_FOCUS_T */
-+ MMAL_PARAMETER_FOCAL_LENGTHS, /**< Unused? */
-+ MMAL_PARAMETER_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */
-+ MMAL_PARAMETER_ZOOM, /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */
-+ MMAL_PARAMETER_MIRROR, /**< @ref MMAL_PARAMETER_MIRROR_T */
-+
-+ /* 0x10 */
-+ MMAL_PARAMETER_CAMERA_NUM, /**< @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_EXPOSURE_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */
-+ MMAL_PARAMETER_EXP_METERING_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */
-+ MMAL_PARAMETER_FOCUS_STATUS, /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */
-+ MMAL_PARAMETER_CAMERA_CONFIG, /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */
-+ MMAL_PARAMETER_CAPTURE_STATUS, /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */
-+ MMAL_PARAMETER_FACE_TRACK, /**< @ref MMAL_PARAMETER_FACE_TRACK_T */
-+ MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_JPEG_Q_FACTOR, /**< @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_FRAME_RATE, /**< @ref MMAL_PARAMETER_FRAME_RATE_T */
-+ MMAL_PARAMETER_USE_STC, /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */
-+ MMAL_PARAMETER_CAMERA_INFO, /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */
-+ MMAL_PARAMETER_VIDEO_STABILISATION, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_FACE_TRACK_RESULTS, /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */
-+ MMAL_PARAMETER_ENABLE_RAW_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+
-+ /* 0x20 */
-+ MMAL_PARAMETER_DPF_FILE, /**< @ref MMAL_PARAMETER_URI_T */
-+ MMAL_PARAMETER_ENABLE_DPF_FILE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_DPF_FAIL_IS_FATAL, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_CAPTURE_MODE, /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */
-+ MMAL_PARAMETER_FOCUS_REGIONS, /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */
-+ MMAL_PARAMETER_INPUT_CROP, /**< @ref MMAL_PARAMETER_INPUT_CROP_T */
-+ MMAL_PARAMETER_SENSOR_INFORMATION, /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */
-+ MMAL_PARAMETER_FLASH_SELECT, /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */
-+ MMAL_PARAMETER_FIELD_OF_VIEW, /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */
-+ MMAL_PARAMETER_HIGH_DYNAMIC_RANGE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION, /**< @ref MMAL_PARAMETER_DRC_T */
-+ MMAL_PARAMETER_ALGORITHM_CONTROL, /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */
-+ MMAL_PARAMETER_SHARPNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+ MMAL_PARAMETER_CONTRAST, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+ MMAL_PARAMETER_BRIGHTNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+ MMAL_PARAMETER_SATURATION, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+
-+ /* 0x30 */
-+ MMAL_PARAMETER_ISO, /**< @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_ANTISHAKE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+
-+ /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */
-+ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_CAMERA_BURST_CAPTURE,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CAMERA_MIN_ISO,
-+
-+ /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */
-+ MMAL_PARAMETER_CAMERA_USE_CASE,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_CAPTURE_STATS_PASS,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_ENABLE_REGISTER_FILE,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL,
-+
-+ /** @ref MMAL_PARAMETER_CONFIGFILE_T */
-+ MMAL_PARAMETER_CONFIGFILE_REGISTERS,
-+
-+ /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */
-+ MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS,
-+ MMAL_PARAMETER_JPEG_ATTACH_LOG, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_ZERO_SHUTTER_LAG, /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */
-+ MMAL_PARAMETER_FPS_RANGE, /**< @ref MMAL_PARAMETER_FPS_RANGE_T */
-+ MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */
-+
-+ /* 0x40 */
-+ MMAL_PARAMETER_SW_SHARPEN_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_FLASH_REQUIRED, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_SW_SATURATION_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_SHUTTER_SPEED, /**< Takes a @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CUSTOM_AWB_GAINS, /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */
-+};
-+
-+struct mmal_parameter_rational {
-+ s32 num; /**< Numerator */
-+ s32 den; /**< Denominator */
-+};
-+
-+enum mmal_parameter_camera_config_timestamp_mode {
-+ MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */
-+ MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value
-+ * for the frame timestamp
-+ */
-+ MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp
-+ * but subtract the
-+ * timestamp of the first
-+ * frame sent to give a
-+ * zero based timestamp.
-+ */
-+};
-+
-+struct mmal_parameter_fps_range {
-+ /**< Low end of the permitted framerate range */
-+ struct mmal_parameter_rational fps_low;
-+ /**< High end of the permitted framerate range */
-+ struct mmal_parameter_rational fps_high;
-+};
-+
-+
-+/* camera configuration parameter */
-+struct mmal_parameter_camera_config {
-+ /* Parameters for setting up the image pools */
-+ u32 max_stills_w; /* Max size of stills capture */
-+ u32 max_stills_h;
-+ u32 stills_yuv422; /* Allow YUV422 stills capture */
-+ u32 one_shot_stills; /* Continuous or one shot stills captures. */
-+
-+ u32 max_preview_video_w; /* Max size of the preview or video
-+ * capture frames
-+ */
-+ u32 max_preview_video_h;
-+ u32 num_preview_video_frames;
-+
-+ /** Sets the height of the circular buffer for stills capture. */
-+ u32 stills_capture_circular_buffer_height;
-+
-+ /** Allows preview/encode to resume as fast as possible after the stills
-+ * input frame has been received, and then processes the still frame in
-+ * the background whilst preview/encode has resumed.
-+ * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE.
-+ */
-+ u32 fast_preview_resume;
-+
-+ /** Selects algorithm for timestamping frames if
-+ * there is no clock component connected.
-+ * enum mmal_parameter_camera_config_timestamp_mode
-+ */
-+ s32 use_stc_timestamp;
-+};
-+
-+
-+enum mmal_parameter_exposuremode {
-+ MMAL_PARAM_EXPOSUREMODE_OFF,
-+ MMAL_PARAM_EXPOSUREMODE_AUTO,
-+ MMAL_PARAM_EXPOSUREMODE_NIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW,
-+ MMAL_PARAM_EXPOSUREMODE_BACKLIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_SPORTS,
-+ MMAL_PARAM_EXPOSUREMODE_SNOW,
-+ MMAL_PARAM_EXPOSUREMODE_BEACH,
-+ MMAL_PARAM_EXPOSUREMODE_VERYLONG,
-+ MMAL_PARAM_EXPOSUREMODE_FIXEDFPS,
-+ MMAL_PARAM_EXPOSUREMODE_ANTISHAKE,
-+ MMAL_PARAM_EXPOSUREMODE_FIREWORKS,
-+};
-+
-+enum mmal_parameter_exposuremeteringmode {
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX,
-+};
-+
-+enum mmal_parameter_awbmode {
-+ MMAL_PARAM_AWBMODE_OFF,
-+ MMAL_PARAM_AWBMODE_AUTO,
-+ MMAL_PARAM_AWBMODE_SUNLIGHT,
-+ MMAL_PARAM_AWBMODE_CLOUDY,
-+ MMAL_PARAM_AWBMODE_SHADE,
-+ MMAL_PARAM_AWBMODE_TUNGSTEN,
-+ MMAL_PARAM_AWBMODE_FLUORESCENT,
-+ MMAL_PARAM_AWBMODE_INCANDESCENT,
-+ MMAL_PARAM_AWBMODE_FLASH,
-+ MMAL_PARAM_AWBMODE_HORIZON,
-+};
-+
-+enum mmal_parameter_imagefx {
-+ MMAL_PARAM_IMAGEFX_NONE,
-+ MMAL_PARAM_IMAGEFX_NEGATIVE,
-+ MMAL_PARAM_IMAGEFX_SOLARIZE,
-+ MMAL_PARAM_IMAGEFX_POSTERIZE,
-+ MMAL_PARAM_IMAGEFX_WHITEBOARD,
-+ MMAL_PARAM_IMAGEFX_BLACKBOARD,
-+ MMAL_PARAM_IMAGEFX_SKETCH,
-+ MMAL_PARAM_IMAGEFX_DENOISE,
-+ MMAL_PARAM_IMAGEFX_EMBOSS,
-+ MMAL_PARAM_IMAGEFX_OILPAINT,
-+ MMAL_PARAM_IMAGEFX_HATCH,
-+ MMAL_PARAM_IMAGEFX_GPEN,
-+ MMAL_PARAM_IMAGEFX_PASTEL,
-+ MMAL_PARAM_IMAGEFX_WATERCOLOUR,
-+ MMAL_PARAM_IMAGEFX_FILM,
-+ MMAL_PARAM_IMAGEFX_BLUR,
-+ MMAL_PARAM_IMAGEFX_SATURATION,
-+ MMAL_PARAM_IMAGEFX_COLOURSWAP,
-+ MMAL_PARAM_IMAGEFX_WASHEDOUT,
-+ MMAL_PARAM_IMAGEFX_POSTERISE,
-+ MMAL_PARAM_IMAGEFX_COLOURPOINT,
-+ MMAL_PARAM_IMAGEFX_COLOURBALANCE,
-+ MMAL_PARAM_IMAGEFX_CARTOON,
-+};
-+
-+enum MMAL_PARAM_FLICKERAVOID_T {
-+ MMAL_PARAM_FLICKERAVOID_OFF,
-+ MMAL_PARAM_FLICKERAVOID_AUTO,
-+ MMAL_PARAM_FLICKERAVOID_50HZ,
-+ MMAL_PARAM_FLICKERAVOID_60HZ,
-+ MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF
-+};
-+
-+struct mmal_parameter_awbgains {
-+ struct mmal_parameter_rational r_gain; /**< Red gain */
-+ struct mmal_parameter_rational b_gain; /**< Blue gain */
-+};
-+
-+/** Manner of video rate control */
-+enum mmal_parameter_rate_control_mode {
-+ MMAL_VIDEO_RATECONTROL_DEFAULT,
-+ MMAL_VIDEO_RATECONTROL_VARIABLE,
-+ MMAL_VIDEO_RATECONTROL_CONSTANT,
-+ MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES,
-+ MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES
-+};
-+
-+enum mmal_video_profile {
-+ MMAL_VIDEO_PROFILE_H263_BASELINE,
-+ MMAL_VIDEO_PROFILE_H263_H320CODING,
-+ MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE,
-+ MMAL_VIDEO_PROFILE_H263_ISWV2,
-+ MMAL_VIDEO_PROFILE_H263_ISWV3,
-+ MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION,
-+ MMAL_VIDEO_PROFILE_H263_INTERNET,
-+ MMAL_VIDEO_PROFILE_H263_INTERLACE,
-+ MMAL_VIDEO_PROFILE_H263_HIGHLATENCY,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLE,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE,
-+ MMAL_VIDEO_PROFILE_MP4V_CORE,
-+ MMAL_VIDEO_PROFILE_MP4V_MAIN,
-+ MMAL_VIDEO_PROFILE_MP4V_NBIT,
-+ MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA,
-+ MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED,
-+ MMAL_VIDEO_PROFILE_MP4V_HYBRID,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME,
-+ MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE,
-+ MMAL_VIDEO_PROFILE_H264_BASELINE,
-+ MMAL_VIDEO_PROFILE_H264_MAIN,
-+ MMAL_VIDEO_PROFILE_H264_EXTENDED,
-+ MMAL_VIDEO_PROFILE_H264_HIGH,
-+ MMAL_VIDEO_PROFILE_H264_HIGH10,
-+ MMAL_VIDEO_PROFILE_H264_HIGH422,
-+ MMAL_VIDEO_PROFILE_H264_HIGH444,
-+ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE,
-+ MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF
-+};
-+
-+enum mmal_video_level {
-+ MMAL_VIDEO_LEVEL_H263_10,
-+ MMAL_VIDEO_LEVEL_H263_20,
-+ MMAL_VIDEO_LEVEL_H263_30,
-+ MMAL_VIDEO_LEVEL_H263_40,
-+ MMAL_VIDEO_LEVEL_H263_45,
-+ MMAL_VIDEO_LEVEL_H263_50,
-+ MMAL_VIDEO_LEVEL_H263_60,
-+ MMAL_VIDEO_LEVEL_H263_70,
-+ MMAL_VIDEO_LEVEL_MP4V_0,
-+ MMAL_VIDEO_LEVEL_MP4V_0b,
-+ MMAL_VIDEO_LEVEL_MP4V_1,
-+ MMAL_VIDEO_LEVEL_MP4V_2,
-+ MMAL_VIDEO_LEVEL_MP4V_3,
-+ MMAL_VIDEO_LEVEL_MP4V_4,
-+ MMAL_VIDEO_LEVEL_MP4V_4a,
-+ MMAL_VIDEO_LEVEL_MP4V_5,
-+ MMAL_VIDEO_LEVEL_MP4V_6,
-+ MMAL_VIDEO_LEVEL_H264_1,
-+ MMAL_VIDEO_LEVEL_H264_1b,
-+ MMAL_VIDEO_LEVEL_H264_11,
-+ MMAL_VIDEO_LEVEL_H264_12,
-+ MMAL_VIDEO_LEVEL_H264_13,
-+ MMAL_VIDEO_LEVEL_H264_2,
-+ MMAL_VIDEO_LEVEL_H264_21,
-+ MMAL_VIDEO_LEVEL_H264_22,
-+ MMAL_VIDEO_LEVEL_H264_3,
-+ MMAL_VIDEO_LEVEL_H264_31,
-+ MMAL_VIDEO_LEVEL_H264_32,
-+ MMAL_VIDEO_LEVEL_H264_4,
-+ MMAL_VIDEO_LEVEL_H264_41,
-+ MMAL_VIDEO_LEVEL_H264_42,
-+ MMAL_VIDEO_LEVEL_H264_5,
-+ MMAL_VIDEO_LEVEL_H264_51,
-+ MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF
-+};
-+
-+struct mmal_parameter_video_profile {
-+ enum mmal_video_profile profile;
-+ enum mmal_video_level level;
-+};
-+
-+/* video parameters */
-+
-+enum mmal_parameter_video_type {
-+ /** @ref MMAL_DISPLAYREGION_T */
-+ MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
-+ MMAL_PARAMETER_SUPPORTED_PROFILES,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
-+ MMAL_PARAMETER_PROFILE,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_INTRAPERIOD,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */
-+ MMAL_PARAMETER_RATECONTROL,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */
-+ MMAL_PARAMETER_NALUNITFORMAT,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T.
-+ * Setting the value to zero resets to the default (one slice per frame).
-+ */
-+ MMAL_PARAMETER_MB_ROWS_PER_SLICE,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */
-+ MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */
-+ MMAL_PARAMETER_VIDEO_EEDE_ENABLE,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */
-+ MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */
-+ MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME,
-+ /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */
-+ MMAL_PARAMETER_VIDEO_INTRA_REFRESH,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */
-+ MMAL_PARAMETER_VIDEO_BIT_RATE,
-+
-+ /** @ref MMAL_PARAMETER_FRAME_RATE_T */
-+ MMAL_PARAMETER_VIDEO_FRAME_RATE,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL,
-+
-+ MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */
-+ /** @ref MMAL_PARAMETER_UINT32_T.
-+ * Changing this parameter from the default can reduce frame rate
-+ * because image buffers need to be re-pitched.
-+ */
-+ MMAL_PARAMETER_VIDEO_ALIGN_HORIZ,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T.
-+ * Changing this parameter from the default can reduce frame rate
-+ * because image buffers need to be re-pitched.
-+ */
-+ MMAL_PARAMETER_VIDEO_ALIGN_VERT,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT,
-+
-+ /**< @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_QP_P,
-+
-+ /**< @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE,
-+
-+ /* H264 specific parameters */
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */
-+ MMAL_PARAMETER_VIDEO_DRM_INIT_INFO,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */
-+ MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER,
-+
-+ /** @ref MMAL_PARAMETER_BYTES_T */
-+ MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER
-+};
-+
-+/** Valid mirror modes */
-+enum mmal_parameter_mirror {
-+ MMAL_PARAM_MIRROR_NONE,
-+ MMAL_PARAM_MIRROR_VERTICAL,
-+ MMAL_PARAM_MIRROR_HORIZONTAL,
-+ MMAL_PARAM_MIRROR_BOTH,
-+};
-+
-+enum mmal_parameter_displaytransform {
-+ MMAL_DISPLAY_ROT0 = 0,
-+ MMAL_DISPLAY_MIRROR_ROT0 = 1,
-+ MMAL_DISPLAY_MIRROR_ROT180 = 2,
-+ MMAL_DISPLAY_ROT180 = 3,
-+ MMAL_DISPLAY_MIRROR_ROT90 = 4,
-+ MMAL_DISPLAY_ROT270 = 5,
-+ MMAL_DISPLAY_ROT90 = 6,
-+ MMAL_DISPLAY_MIRROR_ROT270 = 7,
-+};
-+
-+enum mmal_parameter_displaymode {
-+ MMAL_DISPLAY_MODE_FILL = 0,
-+ MMAL_DISPLAY_MODE_LETTERBOX = 1,
-+};
-+
-+enum mmal_parameter_displayset {
-+ MMAL_DISPLAY_SET_NONE = 0,
-+ MMAL_DISPLAY_SET_NUM = 1,
-+ MMAL_DISPLAY_SET_FULLSCREEN = 2,
-+ MMAL_DISPLAY_SET_TRANSFORM = 4,
-+ MMAL_DISPLAY_SET_DEST_RECT = 8,
-+ MMAL_DISPLAY_SET_SRC_RECT = 0x10,
-+ MMAL_DISPLAY_SET_MODE = 0x20,
-+ MMAL_DISPLAY_SET_PIXEL = 0x40,
-+ MMAL_DISPLAY_SET_NOASPECT = 0x80,
-+ MMAL_DISPLAY_SET_LAYER = 0x100,
-+ MMAL_DISPLAY_SET_COPYPROTECT = 0x200,
-+ MMAL_DISPLAY_SET_ALPHA = 0x400,
-+};
-+
-+struct mmal_parameter_displayregion {
-+ /** Bitfield that indicates which fields are set and should be
-+ * used. All other fields will maintain their current value.
-+ * \ref MMAL_DISPLAYSET_T defines the bits that can be
-+ * combined.
-+ */
-+ u32 set;
-+
-+ /** Describes the display output device, with 0 typically
-+ * being a directly connected LCD display. The actual values
-+ * will depend on the hardware. Code using hard-wired numbers
-+ * (e.g. 2) is certain to fail.
-+ */
-+
-+ u32 display_num;
-+ /** Indicates that we are using the full device screen area,
-+ * rather than a window of the display. If zero, then
-+ * dest_rect is used to specify a region of the display to
-+ * use.
-+ */
-+
-+ s32 fullscreen;
-+ /** Indicates any rotation or flipping used to map frames onto
-+ * the natural display orientation.
-+ */
-+ u32 transform; /* enum mmal_parameter_displaytransform */
-+
-+ /** Where to display the frame within the screen, if
-+ * fullscreen is zero.
-+ */
-+ struct vchiq_mmal_rect dest_rect;
-+
-+ /** Indicates which area of the frame to display. If all
-+ * values are zero, the whole frame will be used.
-+ */
-+ struct vchiq_mmal_rect src_rect;
-+
-+ /** If set to non-zero, indicates that any display scaling
-+ * should disregard the aspect ratio of the frame region being
-+ * displayed.
-+ */
-+ s32 noaspect;
-+
-+ /** Indicates how the image should be scaled to fit the
-+ * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates
-+ * that the image should fill the screen by potentially
-+ * cropping the frames. Setting \code mode \endcode to \code
-+ * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the
-+ * source region should be displayed and black bars added if
-+ * necessary.
-+ */
-+ u32 mode; /* enum mmal_parameter_displaymode */
-+
-+ /** If non-zero, defines the width of a source pixel relative
-+ * to \code pixel_y \endcode. If zero, then pixels default to
-+ * being square.
-+ */
-+ u32 pixel_x;
-+
-+ /** If non-zero, defines the height of a source pixel relative
-+ * to \code pixel_x \endcode. If zero, then pixels default to
-+ * being square.
-+ */
-+ u32 pixel_y;
-+
-+ /** Sets the relative depth of the images, with greater values
-+ * being in front of smaller values.
-+ */
-+ u32 layer;
-+
-+ /** Set to non-zero to ensure copy protection is used on
-+ * output.
-+ */
-+ s32 copyprotect_required;
-+
-+ /** Level of opacity of the layer, where zero is fully
-+ * transparent and 255 is fully opaque.
-+ */
-+ u32 alpha;
-+};
-+
-+#define MMAL_MAX_IMAGEFX_PARAMETERS 5
-+
-+struct mmal_parameter_imagefx_parameters {
-+ enum mmal_parameter_imagefx effect;
-+ u32 num_effect_params;
-+ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS];
-+};
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-vchiq.c linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-vchiq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,1916 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * V4L2 driver MMAL vchiq interface code
-+ */
-+
-+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/mutex.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/completion.h>
-+#include <linux/vmalloc.h>
-+#include <asm/cacheflush.h>
-+#include <media/videobuf2-vmalloc.h>
-+
-+#include "mmal-common.h"
-+#include "mmal-vchiq.h"
-+#include "mmal-msg.h"
-+
-+#define USE_VCHIQ_ARM
-+#include "interface/vchi/vchi.h"
-+
-+/* maximum number of components supported */
-+#define VCHIQ_MMAL_MAX_COMPONENTS 4
-+
-+/*#define FULL_MSG_DUMP 1*/
-+
-+#ifdef DEBUG
-+static const char *const msg_type_names[] = {
-+ "UNKNOWN",
-+ "QUIT",
-+ "SERVICE_CLOSED",
-+ "GET_VERSION",
-+ "COMPONENT_CREATE",
-+ "COMPONENT_DESTROY",
-+ "COMPONENT_ENABLE",
-+ "COMPONENT_DISABLE",
-+ "PORT_INFO_GET",
-+ "PORT_INFO_SET",
-+ "PORT_ACTION",
-+ "BUFFER_FROM_HOST",
-+ "BUFFER_TO_HOST",
-+ "GET_STATS",
-+ "PORT_PARAMETER_SET",
-+ "PORT_PARAMETER_GET",
-+ "EVENT_TO_HOST",
-+ "GET_CORE_STATS_FOR_PORT",
-+ "OPAQUE_ALLOCATOR",
-+ "CONSUME_MEM",
-+ "LMK",
-+ "OPAQUE_ALLOCATOR_DESC",
-+ "DRM_GET_LHS32",
-+ "DRM_GET_TIME",
-+ "BUFFER_FROM_HOST_ZEROLEN",
-+ "PORT_FLUSH",
-+ "HOST_LOG",
-+};
-+#endif
-+
-+static const char *const port_action_type_names[] = {
-+ "UNKNOWN",
-+ "ENABLE",
-+ "DISABLE",
-+ "FLUSH",
-+ "CONNECT",
-+ "DISCONNECT",
-+ "SET_REQUIREMENTS",
-+};
-+
-+#if defined(DEBUG)
-+#if defined(FULL_MSG_DUMP)
-+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \
-+ do { \
-+ pr_debug(TITLE" type:%s(%d) length:%d\n", \
-+ msg_type_names[(MSG)->h.type], \
-+ (MSG)->h.type, (MSG_LEN)); \
-+ print_hex_dump(KERN_DEBUG, "<<h: ", DUMP_PREFIX_OFFSET, \
-+ 16, 4, (MSG), \
-+ sizeof(struct mmal_msg_header), 1); \
-+ print_hex_dump(KERN_DEBUG, "<<p: ", DUMP_PREFIX_OFFSET, \
-+ 16, 4, \
-+ ((u8 *)(MSG)) + sizeof(struct mmal_msg_header),\
-+ (MSG_LEN) - sizeof(struct mmal_msg_header), 1); \
-+ } while (0)
-+#else
-+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \
-+ { \
-+ pr_debug(TITLE" type:%s(%d) length:%d\n", \
-+ msg_type_names[(MSG)->h.type], \
-+ (MSG)->h.type, (MSG_LEN)); \
-+ }
-+#endif
-+#else
-+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE)
-+#endif
-+
-+/* normal message context */
-+struct mmal_msg_context {
-+ union {
-+ struct {
-+ /* work struct for defered callback - must come first */
-+ struct work_struct work;
-+ /* mmal instance */
-+ struct vchiq_mmal_instance *instance;
-+ /* mmal port */
-+ struct vchiq_mmal_port *port;
-+ /* actual buffer used to store bulk reply */
-+ struct mmal_buffer *buffer;
-+ /* amount of buffer used */
-+ unsigned long buffer_used;
-+ /* MMAL buffer flags */
-+ u32 mmal_flags;
-+ /* Presentation and Decode timestamps */
-+ s64 pts;
-+ s64 dts;
-+
-+ int status; /* context status */
-+
-+ } bulk; /* bulk data */
-+
-+ struct {
-+ /* message handle to release */
-+ VCHI_HELD_MSG_T msg_handle;
-+ /* pointer to received message */
-+ struct mmal_msg *msg;
-+ /* received message length */
-+ u32 msg_len;
-+ /* completion upon reply */
-+ struct completion cmplt;
-+ } sync; /* synchronous response */
-+ } u;
-+
-+};
-+
-+struct vchiq_mmal_instance {
-+ VCHI_SERVICE_HANDLE_T handle;
-+
-+ /* ensure serialised access to service */
-+ struct mutex vchiq_mutex;
-+
-+ /* ensure serialised access to bulk operations */
-+ struct mutex bulk_mutex;
-+
-+ /* vmalloc page to receive scratch bulk xfers into */
-+ void *bulk_scratch;
-+
-+ /* component to use next */
-+ int component_idx;
-+ struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS];
-+};
-+
-+static struct mmal_msg_context *get_msg_context(struct vchiq_mmal_instance
-+ *instance)
-+{
-+ struct mmal_msg_context *msg_context;
-+
-+ /* todo: should this be allocated from a pool to avoid kmalloc */
-+ msg_context = kmalloc(sizeof(*msg_context), GFP_KERNEL);
-+ memset(msg_context, 0, sizeof(*msg_context));
-+
-+ return msg_context;
-+}
-+
-+static void release_msg_context(struct mmal_msg_context *msg_context)
-+{
-+ kfree(msg_context);
-+}
-+
-+/* deals with receipt of event to host message */
-+static void event_to_host_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg, u32 msg_len)
-+{
-+ pr_debug("unhandled event\n");
-+ pr_debug("component:%p port type:%d num:%d cmd:0x%x length:%d\n",
-+ msg->u.event_to_host.client_component,
-+ msg->u.event_to_host.port_type,
-+ msg->u.event_to_host.port_num,
-+ msg->u.event_to_host.cmd, msg->u.event_to_host.length);
-+}
-+
-+/* workqueue scheduled callback
-+ *
-+ * we do this because it is important we do not call any other vchiq
-+ * sync calls from witin the message delivery thread
-+ */
-+static void buffer_work_cb(struct work_struct *work)
-+{
-+ struct mmal_msg_context *msg_context = (struct mmal_msg_context *)work;
-+
-+ msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance,
-+ msg_context->u.bulk.port,
-+ msg_context->u.bulk.status,
-+ msg_context->u.bulk.buffer,
-+ msg_context->u.bulk.buffer_used,
-+ msg_context->u.bulk.mmal_flags,
-+ msg_context->u.bulk.dts,
-+ msg_context->u.bulk.pts);
-+
-+ /* release message context */
-+ release_msg_context(msg_context);
-+}
-+
-+/* enqueue a bulk receive for a given message context */
-+static int bulk_receive(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg,
-+ struct mmal_msg_context *msg_context)
-+{
-+ unsigned long rd_len;
-+ unsigned long flags = 0;
-+ int ret;
-+
-+ /* bulk mutex stops other bulk operations while we have a
-+ * receive in progress - released in callback
-+ */
-+ ret = mutex_lock_interruptible(&instance->bulk_mutex);
-+ if (ret != 0)
-+ return ret;
-+
-+ rd_len = msg->u.buffer_from_host.buffer_header.length;
-+
-+ /* take buffer from queue */
-+ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
-+ if (list_empty(&msg_context->u.bulk.port->buffers)) {
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+ pr_err("buffer list empty trying to submit bulk receive\n");
-+
-+ /* todo: this is a serious error, we should never have
-+ * commited a buffer_to_host operation to the mmal
-+ * port without the buffer to back it up (underflow
-+ * handling) and there is no obvious way to deal with
-+ * this - how is the mmal servie going to react when
-+ * we fail to do the xfer and reschedule a buffer when
-+ * it arrives? perhaps a starved flag to indicate a
-+ * waiting bulk receive?
-+ */
-+
-+ mutex_unlock(&instance->bulk_mutex);
-+
-+ return -EINVAL;
-+ }
-+
-+ msg_context->u.bulk.buffer =
-+ list_entry(msg_context->u.bulk.port->buffers.next,
-+ struct mmal_buffer, list);
-+ list_del(&msg_context->u.bulk.buffer->list);
-+
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+
-+ /* ensure we do not overrun the available buffer */
-+ if (rd_len > msg_context->u.bulk.buffer->buffer_size) {
-+ rd_len = msg_context->u.bulk.buffer->buffer_size;
-+ pr_warn("short read as not enough receive buffer space\n");
-+ /* todo: is this the correct response, what happens to
-+ * the rest of the message data?
-+ */
-+ }
-+
-+ /* store length */
-+ msg_context->u.bulk.buffer_used = rd_len;
-+ msg_context->u.bulk.mmal_flags =
-+ msg->u.buffer_from_host.buffer_header.flags;
-+ msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts;
-+ msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts;
-+
-+ // only need to flush L1 cache here, as VCHIQ takes care of the L2
-+ // cache.
-+ __cpuc_flush_dcache_area(msg_context->u.bulk.buffer->buffer, rd_len);
-+
-+ /* queue the bulk submission */
-+ vchi_service_use(instance->handle);
-+ ret = vchi_bulk_queue_receive(instance->handle,
-+ msg_context->u.bulk.buffer->buffer,
-+ /* Actual receive needs to be a multiple
-+ * of 4 bytes
-+ */
-+ (rd_len + 3) & ~3,
-+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
-+ msg_context);
-+
-+ vchi_service_release(instance->handle);
-+
-+ if (ret != 0) {
-+ /* callback will not be clearing the mutex */
-+ mutex_unlock(&instance->bulk_mutex);
-+ }
-+
-+ return ret;
-+}
-+
-+/* enque a dummy bulk receive for a given message context */
-+static int dummy_bulk_receive(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg_context *msg_context)
-+{
-+ int ret;
-+
-+ /* bulk mutex stops other bulk operations while we have a
-+ * receive in progress - released in callback
-+ */
-+ ret = mutex_lock_interruptible(&instance->bulk_mutex);
-+ if (ret != 0)
-+ return ret;
-+
-+ /* zero length indicates this was a dummy transfer */
-+ msg_context->u.bulk.buffer_used = 0;
-+
-+ /* queue the bulk submission */
-+ vchi_service_use(instance->handle);
-+
-+ ret = vchi_bulk_queue_receive(instance->handle,
-+ instance->bulk_scratch,
-+ 8,
-+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
-+ msg_context);
-+
-+ vchi_service_release(instance->handle);
-+
-+ if (ret != 0) {
-+ /* callback will not be clearing the mutex */
-+ mutex_unlock(&instance->bulk_mutex);
-+ }
-+
-+ return ret;
-+}
-+
-+/* data in message, memcpy from packet into output buffer */
-+static int inline_receive(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg,
-+ struct mmal_msg_context *msg_context)
-+{
-+ unsigned long flags = 0;
-+
-+ /* take buffer from queue */
-+ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
-+ if (list_empty(&msg_context->u.bulk.port->buffers)) {
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+ pr_err("buffer list empty trying to receive inline\n");
-+
-+ /* todo: this is a serious error, we should never have
-+ * commited a buffer_to_host operation to the mmal
-+ * port without the buffer to back it up (with
-+ * underflow handling) and there is no obvious way to
-+ * deal with this. Less bad than the bulk case as we
-+ * can just drop this on the floor but...unhelpful
-+ */
-+ return -EINVAL;
-+ }
-+
-+ msg_context->u.bulk.buffer =
-+ list_entry(msg_context->u.bulk.port->buffers.next,
-+ struct mmal_buffer, list);
-+ list_del(&msg_context->u.bulk.buffer->list);
-+
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+
-+ memcpy(msg_context->u.bulk.buffer->buffer,
-+ msg->u.buffer_from_host.short_data,
-+ msg->u.buffer_from_host.payload_in_message);
-+
-+ msg_context->u.bulk.buffer_used =
-+ msg->u.buffer_from_host.payload_in_message;
-+
-+ return 0;
-+}
-+
-+/* queue the buffer availability with MMAL_MSG_TYPE_BUFFER_FROM_HOST */
-+static int
-+buffer_from_host(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port, struct mmal_buffer *buf)
-+{
-+ struct mmal_msg_context *msg_context;
-+ struct mmal_msg m;
-+ int ret;
-+
-+ pr_debug("instance:%p buffer:%p\n", instance->handle, buf);
-+
-+ /* bulk mutex stops other bulk operations while we
-+ * have a receive in progress
-+ */
-+ if (mutex_lock_interruptible(&instance->bulk_mutex))
-+ return -EINTR;
-+
-+ /* get context */
-+ msg_context = get_msg_context(instance);
-+ if (msg_context == NULL)
-+ return -ENOMEM;
-+
-+ /* store bulk message context for when data arrives */
-+ msg_context->u.bulk.instance = instance;
-+ msg_context->u.bulk.port = port;
-+ msg_context->u.bulk.buffer = NULL; /* not valid until bulk xfer */
-+ msg_context->u.bulk.buffer_used = 0;
-+
-+ /* initialise work structure ready to schedule callback */
-+ INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb);
-+
-+ /* prep the buffer from host message */
-+ memset(&m, 0xbc, sizeof(m)); /* just to make debug clearer */
-+
-+ m.h.type = MMAL_MSG_TYPE_BUFFER_FROM_HOST;
-+ m.h.magic = MMAL_MAGIC;
-+ m.h.context = msg_context;
-+ m.h.status = 0;
-+
-+ /* drvbuf is our private data passed back */
-+ m.u.buffer_from_host.drvbuf.magic = MMAL_MAGIC;
-+ m.u.buffer_from_host.drvbuf.component_handle = port->component->handle;
-+ m.u.buffer_from_host.drvbuf.port_handle = port->handle;
-+ m.u.buffer_from_host.drvbuf.client_context = msg_context;
-+
-+ /* buffer header */
-+ m.u.buffer_from_host.buffer_header.cmd = 0;
-+ m.u.buffer_from_host.buffer_header.data = buf->buffer;
-+ m.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size;
-+ m.u.buffer_from_host.buffer_header.length = 0; /* nothing used yet */
-+ m.u.buffer_from_host.buffer_header.offset = 0; /* no offset */
-+ m.u.buffer_from_host.buffer_header.flags = 0; /* no flags */
-+ m.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN;
-+ m.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN;
-+
-+ /* clear buffer type sepecific data */
-+ memset(&m.u.buffer_from_host.buffer_header_type_specific, 0,
-+ sizeof(m.u.buffer_from_host.buffer_header_type_specific));
-+
-+ /* no payload in message */
-+ m.u.buffer_from_host.payload_in_message = 0;
-+
-+ vchi_service_use(instance->handle);
-+
-+ ret = vchi_msg_queue(instance->handle, &m,
-+ sizeof(struct mmal_msg_header) +
-+ sizeof(m.u.buffer_from_host),
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (ret != 0) {
-+ release_msg_context(msg_context);
-+ /* todo: is this correct error value? */
-+ }
-+
-+ vchi_service_release(instance->handle);
-+
-+ mutex_unlock(&instance->bulk_mutex);
-+
-+ return ret;
-+}
-+
-+/* submit a buffer to the mmal sevice
-+ *
-+ * the buffer_from_host uses size data from the ports next available
-+ * mmal_buffer and deals with there being no buffer available by
-+ * incrementing the underflow for later
-+ */
-+static int port_buffer_from_host(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct mmal_buffer *buf;
-+ unsigned long flags = 0;
-+
-+ if (!port->enabled)
-+ return -EINVAL;
-+
-+ /* peek buffer from queue */
-+ spin_lock_irqsave(&port->slock, flags);
-+ if (list_empty(&port->buffers)) {
-+ port->buffer_underflow++;
-+ spin_unlock_irqrestore(&port->slock, flags);
-+ return -ENOSPC;
-+ }
-+
-+ buf = list_entry(port->buffers.next, struct mmal_buffer, list);
-+
-+ spin_unlock_irqrestore(&port->slock, flags);
-+
-+ /* issue buffer to mmal service */
-+ ret = buffer_from_host(instance, port, buf);
-+ if (ret) {
-+ pr_err("adding buffer header failed\n");
-+ /* todo: how should this be dealt with */
-+ }
-+
-+ return ret;
-+}
-+
-+/* deals with receipt of buffer to host message */
-+static void buffer_to_host_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg, u32 msg_len)
-+{
-+ struct mmal_msg_context *msg_context;
-+
-+ pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n",
-+ instance, msg, msg_len);
-+
-+ if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) {
-+ msg_context = msg->u.buffer_from_host.drvbuf.client_context;
-+ } else {
-+ pr_err("MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\n");
-+ return;
-+ }
-+
-+ if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) {
-+ /* message reception had an error */
-+ pr_warn("error %d in reply\n", msg->h.status);
-+
-+ msg_context->u.bulk.status = msg->h.status;
-+
-+ } else if (msg->u.buffer_from_host.buffer_header.length == 0) {
-+ /* empty buffer */
-+ if (msg->u.buffer_from_host.buffer_header.flags &
-+ MMAL_BUFFER_HEADER_FLAG_EOS) {
-+ msg_context->u.bulk.status =
-+ dummy_bulk_receive(instance, msg_context);
-+ if (msg_context->u.bulk.status == 0)
-+ return; /* successful bulk submission, bulk
-+ * completion will trigger callback
-+ */
-+ } else {
-+ /* do callback with empty buffer - not EOS though */
-+ msg_context->u.bulk.status = 0;
-+ msg_context->u.bulk.buffer_used = 0;
-+ }
-+ } else if (msg->u.buffer_from_host.payload_in_message == 0) {
-+ /* data is not in message, queue a bulk receive */
-+ msg_context->u.bulk.status =
-+ bulk_receive(instance, msg, msg_context);
-+ if (msg_context->u.bulk.status == 0)
-+ return; /* successful bulk submission, bulk
-+ * completion will trigger callback
-+ */
-+
-+ /* failed to submit buffer, this will end badly */
-+ pr_err("error %d on bulk submission\n",
-+ msg_context->u.bulk.status);
-+
-+ } else if (msg->u.buffer_from_host.payload_in_message <=
-+ MMAL_VC_SHORT_DATA) {
-+ /* data payload within message */
-+ msg_context->u.bulk.status = inline_receive(instance, msg,
-+ msg_context);
-+ } else {
-+ pr_err("message with invalid short payload\n");
-+
-+ /* signal error */
-+ msg_context->u.bulk.status = -EINVAL;
-+ msg_context->u.bulk.buffer_used =
-+ msg->u.buffer_from_host.payload_in_message;
-+ }
-+
-+ /* replace the buffer header */
-+ port_buffer_from_host(instance, msg_context->u.bulk.port);
-+
-+ /* schedule the port callback */
-+ schedule_work(&msg_context->u.bulk.work);
-+}
-+
-+static void bulk_receive_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg_context *msg_context)
-+{
-+ /* bulk receive operation complete */
-+ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
-+
-+ /* replace the buffer header */
-+ port_buffer_from_host(msg_context->u.bulk.instance,
-+ msg_context->u.bulk.port);
-+
-+ msg_context->u.bulk.status = 0;
-+
-+ /* schedule the port callback */
-+ schedule_work(&msg_context->u.bulk.work);
-+}
-+
-+static void bulk_abort_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg_context *msg_context)
-+{
-+ pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context);
-+
-+ /* bulk receive operation complete */
-+ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
-+
-+ /* replace the buffer header */
-+ port_buffer_from_host(msg_context->u.bulk.instance,
-+ msg_context->u.bulk.port);
-+
-+ msg_context->u.bulk.status = -EINTR;
-+
-+ schedule_work(&msg_context->u.bulk.work);
-+}
-+
-+/* incoming event service callback */
-+static void service_callback(void *param,
-+ const VCHI_CALLBACK_REASON_T reason,
-+ void *bulk_ctx)
-+{
-+ struct vchiq_mmal_instance *instance = param;
-+ int status;
-+ u32 msg_len;
-+ struct mmal_msg *msg;
-+ VCHI_HELD_MSG_T msg_handle;
-+
-+ if (!instance) {
-+ pr_err("Message callback passed NULL instance\n");
-+ return;
-+ }
-+
-+ switch (reason) {
-+ case VCHI_CALLBACK_MSG_AVAILABLE:
-+ status = vchi_msg_hold(instance->handle, (void **)&msg,
-+ &msg_len, VCHI_FLAGS_NONE, &msg_handle);
-+ if (status) {
-+ pr_err("Unable to dequeue a message (%d)\n", status);
-+ break;
-+ }
-+
-+ DBG_DUMP_MSG(msg, msg_len, "<<< reply message");
-+
-+ /* handling is different for buffer messages */
-+ switch (msg->h.type) {
-+
-+ case MMAL_MSG_TYPE_BUFFER_FROM_HOST:
-+ vchi_held_msg_release(&msg_handle);
-+ break;
-+
-+ case MMAL_MSG_TYPE_EVENT_TO_HOST:
-+ event_to_host_cb(instance, msg, msg_len);
-+ vchi_held_msg_release(&msg_handle);
-+
-+ break;
-+
-+ case MMAL_MSG_TYPE_BUFFER_TO_HOST:
-+ buffer_to_host_cb(instance, msg, msg_len);
-+ vchi_held_msg_release(&msg_handle);
-+ break;
-+
-+ default:
-+ /* messages dependant on header context to complete */
-+
-+ /* todo: the msg.context really ought to be sanity
-+ * checked before we just use it, afaict it comes back
-+ * and is used raw from the videocore. Perhaps it
-+ * should be verified the address lies in the kernel
-+ * address space.
-+ */
-+ if (msg->h.context == NULL) {
-+ pr_err("received message context was null!\n");
-+ vchi_held_msg_release(&msg_handle);
-+ break;
-+ }
-+
-+ /* fill in context values */
-+ msg->h.context->u.sync.msg_handle = msg_handle;
-+ msg->h.context->u.sync.msg = msg;
-+ msg->h.context->u.sync.msg_len = msg_len;
-+
-+ /* todo: should this check (completion_done()
-+ * == 1) for no one waiting? or do we need a
-+ * flag to tell us the completion has been
-+ * interrupted so we can free the message and
-+ * its context. This probably also solves the
-+ * message arriving after interruption todo
-+ * below
-+ */
-+
-+ /* complete message so caller knows it happened */
-+ complete(&msg->h.context->u.sync.cmplt);
-+ break;
-+ }
-+
-+ break;
-+
-+ case VCHI_CALLBACK_BULK_RECEIVED:
-+ bulk_receive_cb(instance, bulk_ctx);
-+ break;
-+
-+ case VCHI_CALLBACK_BULK_RECEIVE_ABORTED:
-+ bulk_abort_cb(instance, bulk_ctx);
-+ break;
-+
-+ case VCHI_CALLBACK_SERVICE_CLOSED:
-+ /* TODO: consider if this requires action if received when
-+ * driver is not explicitly closing the service
-+ */
-+ break;
-+
-+ default:
-+ pr_err("Received unhandled message reason %d\n", reason);
-+ break;
-+ }
-+}
-+
-+static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg,
-+ unsigned int payload_len,
-+ struct mmal_msg **msg_out,
-+ VCHI_HELD_MSG_T *msg_handle_out)
-+{
-+ struct mmal_msg_context msg_context;
-+ int ret;
-+
-+ /* payload size must not cause message to exceed max size */
-+ if (payload_len >
-+ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) {
-+ pr_err("payload length %d exceeds max:%d\n", payload_len,
-+ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header)));
-+ return -EINVAL;
-+ }
-+
-+ init_completion(&msg_context.u.sync.cmplt);
-+
-+ msg->h.magic = MMAL_MAGIC;
-+ msg->h.context = &msg_context;
-+ msg->h.status = 0;
-+
-+ DBG_DUMP_MSG(msg, (sizeof(struct mmal_msg_header) + payload_len),
-+ ">>> sync message");
-+
-+ vchi_service_use(instance->handle);
-+
-+ ret = vchi_msg_queue(instance->handle,
-+ msg,
-+ sizeof(struct mmal_msg_header) + payload_len,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ vchi_service_release(instance->handle);
-+
-+ if (ret) {
-+ pr_err("error %d queuing message\n", ret);
-+ return ret;
-+ }
-+
-+ ret = wait_for_completion_timeout(&msg_context.u.sync.cmplt, 3*HZ);
-+ if (ret <= 0) {
-+ pr_err("error %d waiting for sync completion\n", ret);
-+ if (ret == 0)
-+ ret = -ETIME;
-+ /* todo: what happens if the message arrives after aborting */
-+ return ret;
-+ }
-+
-+ *msg_out = msg_context.u.sync.msg;
-+ *msg_handle_out = msg_context.u.sync.msg_handle;
-+
-+ return 0;
-+}
-+
-+static void dump_port_info(struct vchiq_mmal_port *port)
-+{
-+ pr_debug("port handle:0x%x enabled:%d\n", port->handle, port->enabled);
-+
-+ pr_debug("buffer minimum num:%d size:%d align:%d\n",
-+ port->minimum_buffer.num,
-+ port->minimum_buffer.size, port->minimum_buffer.alignment);
-+
-+ pr_debug("buffer recommended num:%d size:%d align:%d\n",
-+ port->recommended_buffer.num,
-+ port->recommended_buffer.size,
-+ port->recommended_buffer.alignment);
-+
-+ pr_debug("buffer current values num:%d size:%d align:%d\n",
-+ port->current_buffer.num,
-+ port->current_buffer.size, port->current_buffer.alignment);
-+
-+ pr_debug("elementry stream: type:%d encoding:0x%x varient:0x%x\n",
-+ port->format.type,
-+ port->format.encoding, port->format.encoding_variant);
-+
-+ pr_debug(" bitrate:%d flags:0x%x\n",
-+ port->format.bitrate, port->format.flags);
-+
-+ if (port->format.type == MMAL_ES_TYPE_VIDEO) {
-+ pr_debug
-+ ("es video format: width:%d height:%d colourspace:0x%x\n",
-+ port->es.video.width, port->es.video.height,
-+ port->es.video.color_space);
-+
-+ pr_debug(" : crop xywh %d,%d,%d,%d\n",
-+ port->es.video.crop.x,
-+ port->es.video.crop.y,
-+ port->es.video.crop.width, port->es.video.crop.height);
-+ pr_debug(" : framerate %d/%d aspect %d/%d\n",
-+ port->es.video.frame_rate.num,
-+ port->es.video.frame_rate.den,
-+ port->es.video.par.num, port->es.video.par.den);
-+ }
-+}
-+
-+static void port_to_mmal_msg(struct vchiq_mmal_port *port, struct mmal_port *p)
-+{
-+
-+ /* todo do readonly fields need setting at all? */
-+ p->type = port->type;
-+ p->index = port->index;
-+ p->index_all = 0;
-+ p->is_enabled = port->enabled;
-+ p->buffer_num_min = port->minimum_buffer.num;
-+ p->buffer_size_min = port->minimum_buffer.size;
-+ p->buffer_alignment_min = port->minimum_buffer.alignment;
-+ p->buffer_num_recommended = port->recommended_buffer.num;
-+ p->buffer_size_recommended = port->recommended_buffer.size;
-+
-+ /* only three writable fields in a port */
-+ p->buffer_num = port->current_buffer.num;
-+ p->buffer_size = port->current_buffer.size;
-+ p->userdata = port;
-+}
-+
-+static int port_info_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ pr_debug("setting port info port %p\n", port);
-+ if (!port)
-+ return -1;
-+ dump_port_info(port);
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_INFO_SET;
-+
-+ m.u.port_info_set.component_handle = port->component->handle;
-+ m.u.port_info_set.port_type = port->type;
-+ m.u.port_info_set.port_index = port->index;
-+
-+ port_to_mmal_msg(port, &m.u.port_info_set.port);
-+
-+ /* elementry stream format setup */
-+ m.u.port_info_set.format.type = port->format.type;
-+ m.u.port_info_set.format.encoding = port->format.encoding;
-+ m.u.port_info_set.format.encoding_variant =
-+ port->format.encoding_variant;
-+ m.u.port_info_set.format.bitrate = port->format.bitrate;
-+ m.u.port_info_set.format.flags = port->format.flags;
-+
-+ memcpy(&m.u.port_info_set.es, &port->es,
-+ sizeof(union mmal_es_specific_format));
-+
-+ m.u.port_info_set.format.extradata_size = port->format.extradata_size;
-+ memcpy(rmsg->u.port_info_set.extradata, port->format.extradata,
-+ port->format.extradata_size);
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_info_set),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_SET) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ /* return operation status */
-+ ret = -rmsg->u.port_info_get_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d\n", __func__, ret,
-+ port->component->handle, port->handle);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+
-+}
-+
-+/* use port info get message to retrive port information */
-+static int port_info_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ /* port info time */
-+ m.h.type = MMAL_MSG_TYPE_PORT_INFO_GET;
-+ m.u.port_info_get.component_handle = port->component->handle;
-+ m.u.port_info_get.port_type = port->type;
-+ m.u.port_info_get.index = port->index;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_info_get),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_GET) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ /* return operation status */
-+ ret = -rmsg->u.port_info_get_reply.status;
-+ if (ret != MMAL_MSG_STATUS_SUCCESS)
-+ goto release_msg;
-+
-+ if (rmsg->u.port_info_get_reply.port.is_enabled == 0)
-+ port->enabled = false;
-+ else
-+ port->enabled = true;
-+
-+ /* copy the values out of the message */
-+ port->handle = rmsg->u.port_info_get_reply.port_handle;
-+
-+ /* port type and index cached to use on port info set becuase
-+ * it does not use a port handle
-+ */
-+ port->type = rmsg->u.port_info_get_reply.port_type;
-+ port->index = rmsg->u.port_info_get_reply.port_index;
-+
-+ port->minimum_buffer.num =
-+ rmsg->u.port_info_get_reply.port.buffer_num_min;
-+ port->minimum_buffer.size =
-+ rmsg->u.port_info_get_reply.port.buffer_size_min;
-+ port->minimum_buffer.alignment =
-+ rmsg->u.port_info_get_reply.port.buffer_alignment_min;
-+
-+ port->recommended_buffer.alignment =
-+ rmsg->u.port_info_get_reply.port.buffer_alignment_min;
-+ port->recommended_buffer.num =
-+ rmsg->u.port_info_get_reply.port.buffer_num_recommended;
-+
-+ port->current_buffer.num = rmsg->u.port_info_get_reply.port.buffer_num;
-+ port->current_buffer.size =
-+ rmsg->u.port_info_get_reply.port.buffer_size;
-+
-+ /* stream format */
-+ port->format.type = rmsg->u.port_info_get_reply.format.type;
-+ port->format.encoding = rmsg->u.port_info_get_reply.format.encoding;
-+ port->format.encoding_variant =
-+ rmsg->u.port_info_get_reply.format.encoding_variant;
-+ port->format.bitrate = rmsg->u.port_info_get_reply.format.bitrate;
-+ port->format.flags = rmsg->u.port_info_get_reply.format.flags;
-+
-+ /* elementry stream format */
-+ memcpy(&port->es,
-+ &rmsg->u.port_info_get_reply.es,
-+ sizeof(union mmal_es_specific_format));
-+ port->format.es = &port->es;
-+
-+ port->format.extradata_size =
-+ rmsg->u.port_info_get_reply.format.extradata_size;
-+ memcpy(port->format.extradata,
-+ rmsg->u.port_info_get_reply.extradata,
-+ port->format.extradata_size);
-+
-+ pr_debug("received port info\n");
-+ dump_port_info(port);
-+
-+release_msg:
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d\n",
-+ __func__, ret, port->component->handle, port->handle);
-+
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* create comonent on vc */
-+static int create_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component,
-+ const char *name)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ /* build component create message */
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_CREATE;
-+ m.u.component_create.client_component = component;
-+ strncpy(m.u.component_create.name, name,
-+ sizeof(m.u.component_create.name));
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_create),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_create_reply.status;
-+ if (ret != MMAL_MSG_STATUS_SUCCESS)
-+ goto release_msg;
-+
-+ /* a valid component response received */
-+ component->handle = rmsg->u.component_create_reply.component_handle;
-+ component->inputs = rmsg->u.component_create_reply.input_num;
-+ component->outputs = rmsg->u.component_create_reply.output_num;
-+ component->clocks = rmsg->u.component_create_reply.clock_num;
-+
-+ pr_debug("Component handle:0x%x in:%d out:%d clock:%d\n",
-+ component->handle,
-+ component->inputs, component->outputs, component->clocks);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* destroys a component on vc */
-+static int destroy_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_DESTROY;
-+ m.u.component_destroy.component_handle = component->handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_destroy),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_destroy_reply.status;
-+
-+release_msg:
-+
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* enable a component on vc */
-+static int enable_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_ENABLE;
-+ m.u.component_enable.component_handle = component->handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_enable),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_enable_reply.status;
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* disable a component on vc */
-+static int disable_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_DISABLE;
-+ m.u.component_disable.component_handle = component->handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_disable),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_disable_reply.status;
-+
-+release_msg:
-+
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* get version of mmal implementation */
-+static int get_version(struct vchiq_mmal_instance *instance,
-+ u32 *major_out, u32 *minor_out)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_GET_VERSION;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.version),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ *major_out = rmsg->u.version.major;
-+ *minor_out = rmsg->u.version.minor;
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* do a port action with a port as a parameter */
-+static int port_action_port(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ enum mmal_msg_port_action_type action_type)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_ACTION;
-+ m.u.port_action_port.component_handle = port->component->handle;
-+ m.u.port_action_port.port_handle = port->handle;
-+ m.u.port_action_port.action = action_type;
-+
-+ port_to_mmal_msg(port, &m.u.port_action_port.port);
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_action_port),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_action_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)\n",
-+ __func__,
-+ ret, port->component->handle, port->handle,
-+ port_action_type_names[action_type], action_type);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* do a port action with handles as parameters */
-+static int port_action_handle(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ enum mmal_msg_port_action_type action_type,
-+ u32 connect_component_handle,
-+ u32 connect_port_handle)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_ACTION;
-+
-+ m.u.port_action_handle.component_handle = port->component->handle;
-+ m.u.port_action_handle.port_handle = port->handle;
-+ m.u.port_action_handle.action = action_type;
-+
-+ m.u.port_action_handle.connect_component_handle =
-+ connect_component_handle;
-+ m.u.port_action_handle.connect_port_handle = connect_port_handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_action_handle),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_action_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \
-+ " connect component:0x%x connect port:%d\n",
-+ __func__,
-+ ret, port->component->handle, port->handle,
-+ port_action_type_names[action_type],
-+ action_type, connect_component_handle, connect_port_handle);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+static int port_parameter_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter_id, void *value, u32 value_size)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_SET;
-+
-+ m.u.port_parameter_set.component_handle = port->component->handle;
-+ m.u.port_parameter_set.port_handle = port->handle;
-+ m.u.port_parameter_set.id = parameter_id;
-+ m.u.port_parameter_set.size = (2 * sizeof(u32)) + value_size;
-+ memcpy(&m.u.port_parameter_set.value, value, value_size);
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ (4 * sizeof(u32)) + value_size,
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_SET) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_parameter_set_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n",
-+ __func__,
-+ ret, port->component->handle, port->handle, parameter_id);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+static int port_parameter_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter_id, void *value, u32 *value_size)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_GET;
-+
-+ m.u.port_parameter_get.component_handle = port->component->handle;
-+ m.u.port_parameter_get.port_handle = port->handle;
-+ m.u.port_parameter_get.id = parameter_id;
-+ m.u.port_parameter_get.size = (2 * sizeof(u32)) + *value_size;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(struct
-+ mmal_msg_port_parameter_get),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_GET) {
-+ /* got an unexpected message type in reply */
-+ pr_err("Incorrect reply type %d\n", rmsg->h.type);
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_parameter_get_reply.status;
-+ if (ret) {
-+ /* Copy only as much as we have space for
-+ * but report true size of parameter
-+ */
-+ memcpy(value, &rmsg->u.port_parameter_get_reply.value,
-+ *value_size);
-+ *value_size = rmsg->u.port_parameter_get_reply.size;
-+ } else
-+ memcpy(value, &rmsg->u.port_parameter_get_reply.value,
-+ rmsg->u.port_parameter_get_reply.size);
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__,
-+ ret, port->component->handle, port->handle, parameter_id);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* disables a port and drains buffers from it */
-+static int port_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct list_head *q, *buf_head;
-+ unsigned long flags = 0;
-+
-+ if (!port->enabled)
-+ return 0;
-+
-+ port->enabled = false;
-+
-+ ret = port_action_port(instance, port,
-+ MMAL_MSG_PORT_ACTION_TYPE_DISABLE);
-+ if (ret == 0) {
-+
-+ /* drain all queued buffers on port */
-+ spin_lock_irqsave(&port->slock, flags);
-+
-+ list_for_each_safe(buf_head, q, &port->buffers) {
-+ struct mmal_buffer *mmalbuf;
-+ mmalbuf = list_entry(buf_head, struct mmal_buffer,
-+ list);
-+ list_del(buf_head);
-+ if (port->buffer_cb)
-+ port->buffer_cb(instance,
-+ port, 0, mmalbuf, 0, 0,
-+ MMAL_TIME_UNKNOWN,
-+ MMAL_TIME_UNKNOWN);
-+ }
-+
-+ spin_unlock_irqrestore(&port->slock, flags);
-+
-+ ret = port_info_get(instance, port);
-+ }
-+
-+ return ret;
-+}
-+
-+/* enable a port */
-+static int port_enable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ unsigned int hdr_count;
-+ struct list_head *buf_head;
-+ int ret;
-+
-+ if (port->enabled)
-+ return 0;
-+
-+ /* ensure there are enough buffers queued to cover the buffer headers */
-+ if (port->buffer_cb != NULL) {
-+ hdr_count = 0;
-+ list_for_each(buf_head, &port->buffers) {
-+ hdr_count++;
-+ }
-+ if (hdr_count < port->current_buffer.num)
-+ return -ENOSPC;
-+ }
-+
-+ ret = port_action_port(instance, port,
-+ MMAL_MSG_PORT_ACTION_TYPE_ENABLE);
-+ if (ret)
-+ goto done;
-+
-+ port->enabled = true;
-+
-+ if (port->buffer_cb) {
-+ /* send buffer headers to videocore */
-+ hdr_count = 1;
-+ list_for_each(buf_head, &port->buffers) {
-+ struct mmal_buffer *mmalbuf;
-+ mmalbuf = list_entry(buf_head, struct mmal_buffer,
-+ list);
-+ ret = buffer_from_host(instance, port, mmalbuf);
-+ if (ret)
-+ goto done;
-+
-+ hdr_count++;
-+ if (hdr_count > port->current_buffer.num)
-+ break;
-+ }
-+ }
-+
-+ ret = port_info_get(instance, port);
-+
-+done:
-+ return ret;
-+}
-+
-+/* ------------------------------------------------------------------
-+ * Exported API
-+ *------------------------------------------------------------------*/
-+
-+int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = port_info_set(instance, port);
-+ if (ret)
-+ goto release_unlock;
-+
-+ /* read what has actually been set */
-+ ret = port_info_get(instance, port);
-+
-+release_unlock:
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+
-+}
-+
-+int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter, void *value, u32 value_size)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = port_parameter_set(instance, port, parameter, value, value_size);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter, void *value, u32 *value_size)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = port_parameter_get(instance, port, parameter, value, value_size);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/* enable a port
-+ *
-+ * enables a port and queues buffers for satisfying callbacks if we
-+ * provide a callback handler
-+ */
-+int vchiq_mmal_port_enable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ vchiq_mmal_buffer_cb buffer_cb)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ /* already enabled - noop */
-+ if (port->enabled) {
-+ ret = 0;
-+ goto unlock;
-+ }
-+
-+ port->buffer_cb = buffer_cb;
-+
-+ ret = port_enable(instance, port);
-+
-+unlock:
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (!port->enabled) {
-+ mutex_unlock(&instance->vchiq_mutex);
-+ return 0;
-+ }
-+
-+ ret = port_disable(instance, port);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/* ports will be connected in a tunneled manner so data buffers
-+ * are not handled by client.
-+ */
-+int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *src,
-+ struct vchiq_mmal_port *dst)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ /* disconnect ports if connected */
-+ if (src->connected != NULL) {
-+ ret = port_disable(instance, src);
-+ if (ret) {
-+ pr_err("failed disabling src port(%d)\n", ret);
-+ goto release_unlock;
-+ }
-+
-+ /* do not need to disable the destination port as they
-+ * are connected and it is done automatically
-+ */
-+
-+ ret = port_action_handle(instance, src,
-+ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT,
-+ src->connected->component->handle,
-+ src->connected->handle);
-+ if (ret < 0) {
-+ pr_err("failed disconnecting src port\n");
-+ goto release_unlock;
-+ }
-+ src->connected->enabled = false;
-+ src->connected = NULL;
-+ }
-+
-+ if (dst == NULL) {
-+ /* do not make new connection */
-+ ret = 0;
-+ pr_debug("not making new connection\n");
-+ goto release_unlock;
-+ }
-+
-+ /* copy src port format to dst */
-+ dst->format.encoding = src->format.encoding;
-+ dst->es.video.width = src->es.video.width;
-+ dst->es.video.height = src->es.video.height;
-+ dst->es.video.crop.x = src->es.video.crop.x;
-+ dst->es.video.crop.y = src->es.video.crop.y;
-+ dst->es.video.crop.width = src->es.video.crop.width;
-+ dst->es.video.crop.height = src->es.video.crop.height;
-+ dst->es.video.frame_rate.num = src->es.video.frame_rate.num;
-+ dst->es.video.frame_rate.den = src->es.video.frame_rate.den;
-+
-+ /* set new format */
-+ ret = port_info_set(instance, dst);
-+ if (ret) {
-+ pr_debug("setting port info failed\n");
-+ goto release_unlock;
-+ }
-+
-+ /* read what has actually been set */
-+ ret = port_info_get(instance, dst);
-+ if (ret) {
-+ pr_debug("read back port info failed\n");
-+ goto release_unlock;
-+ }
-+
-+ /* connect two ports together */
-+ ret = port_action_handle(instance, src,
-+ MMAL_MSG_PORT_ACTION_TYPE_CONNECT,
-+ dst->component->handle, dst->handle);
-+ if (ret < 0) {
-+ pr_debug("connecting port %d:%d to %d:%d failed\n",
-+ src->component->handle, src->handle,
-+ dst->component->handle, dst->handle);
-+ goto release_unlock;
-+ }
-+ src->connected = dst;
-+
-+release_unlock:
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ struct mmal_buffer *buffer)
-+{
-+ unsigned long flags = 0;
-+
-+ spin_lock_irqsave(&port->slock, flags);
-+ list_add_tail(&buffer->list, &port->buffers);
-+ spin_unlock_irqrestore(&port->slock, flags);
-+
-+ /* the port previously underflowed because it was missing a
-+ * mmal_buffer which has just been added, submit that buffer
-+ * to the mmal service.
-+ */
-+ if (port->buffer_underflow) {
-+ port_buffer_from_host(instance, port);
-+ port->buffer_underflow--;
-+ }
-+
-+ return 0;
-+}
-+
-+/* Initialise a mmal component and its ports
-+ *
-+ */
-+int vchiq_mmal_component_init(struct vchiq_mmal_instance *instance,
-+ const char *name,
-+ struct vchiq_mmal_component **component_out)
-+{
-+ int ret;
-+ int idx; /* port index */
-+ struct vchiq_mmal_component *component;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (instance->component_idx == VCHIQ_MMAL_MAX_COMPONENTS) {
-+ ret = -EINVAL; /* todo is this correct error? */
-+ goto unlock;
-+ }
-+
-+ component = &instance->component[instance->component_idx];
-+
-+ ret = create_component(instance, component, name);
-+ if (ret < 0)
-+ goto unlock;
-+
-+ /* ports info needs gathering */
-+ component->control.type = MMAL_PORT_TYPE_CONTROL;
-+ component->control.index = 0;
-+ component->control.component = component;
-+ spin_lock_init(&component->control.slock);
-+ INIT_LIST_HEAD(&component->control.buffers);
-+ ret = port_info_get(instance, &component->control);
-+ if (ret < 0)
-+ goto release_component;
-+
-+ for (idx = 0; idx < component->inputs; idx++) {
-+ component->input[idx].type = MMAL_PORT_TYPE_INPUT;
-+ component->input[idx].index = idx;
-+ component->input[idx].component = component;
-+ spin_lock_init(&component->input[idx].slock);
-+ INIT_LIST_HEAD(&component->input[idx].buffers);
-+ ret = port_info_get(instance, &component->input[idx]);
-+ if (ret < 0)
-+ goto release_component;
-+ }
-+
-+ for (idx = 0; idx < component->outputs; idx++) {
-+ component->output[idx].type = MMAL_PORT_TYPE_OUTPUT;
-+ component->output[idx].index = idx;
-+ component->output[idx].component = component;
-+ spin_lock_init(&component->output[idx].slock);
-+ INIT_LIST_HEAD(&component->output[idx].buffers);
-+ ret = port_info_get(instance, &component->output[idx]);
-+ if (ret < 0)
-+ goto release_component;
-+ }
-+
-+ for (idx = 0; idx < component->clocks; idx++) {
-+ component->clock[idx].type = MMAL_PORT_TYPE_CLOCK;
-+ component->clock[idx].index = idx;
-+ component->clock[idx].component = component;
-+ spin_lock_init(&component->clock[idx].slock);
-+ INIT_LIST_HEAD(&component->clock[idx].buffers);
-+ ret = port_info_get(instance, &component->clock[idx]);
-+ if (ret < 0)
-+ goto release_component;
-+ }
-+
-+ instance->component_idx++;
-+
-+ *component_out = component;
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return 0;
-+
-+release_component:
-+ destroy_component(instance, component);
-+unlock:
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/*
-+ * cause a mmal component to be destroyed
-+ */
-+int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (component->enabled)
-+ ret = disable_component(instance, component);
-+
-+ ret = destroy_component(instance, component);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/*
-+ * cause a mmal component to be enabled
-+ */
-+int vchiq_mmal_component_enable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (component->enabled) {
-+ mutex_unlock(&instance->vchiq_mutex);
-+ return 0;
-+ }
-+
-+ ret = enable_component(instance, component);
-+ if (ret == 0)
-+ component->enabled = true;
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/*
-+ * cause a mmal component to be enabled
-+ */
-+int vchiq_mmal_component_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (!component->enabled) {
-+ mutex_unlock(&instance->vchiq_mutex);
-+ return 0;
-+ }
-+
-+ ret = disable_component(instance, component);
-+ if (ret == 0)
-+ component->enabled = false;
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
-+ u32 *major_out, u32 *minor_out)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = get_version(instance, major_out, minor_out);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance)
-+{
-+ int status = 0;
-+
-+ if (instance == NULL)
-+ return -EINVAL;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ vchi_service_use(instance->handle);
-+
-+ status = vchi_service_close(instance->handle);
-+ if (status != 0)
-+ pr_err("mmal-vchiq: VCHIQ close failed");
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ vfree(instance->bulk_scratch);
-+
-+ kfree(instance);
-+
-+ return status;
-+}
-+
-+int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance)
-+{
-+ int status;
-+ struct vchiq_mmal_instance *instance;
-+ static VCHI_CONNECTION_T *vchi_connection;
-+ static VCHI_INSTANCE_T vchi_instance;
-+ SERVICE_CREATION_T params = {
-+ VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER),
-+ VC_MMAL_SERVER_NAME,
-+ vchi_connection,
-+ 0, /* rx fifo size (unused) */
-+ 0, /* tx fifo size (unused) */
-+ service_callback,
-+ NULL, /* service callback parameter */
-+ 1, /* unaligned bulk receives */
-+ 1, /* unaligned bulk transmits */
-+ 0 /* want crc check on bulk transfers */
-+ };
-+
-+ /* compile time checks to ensure structure size as they are
-+ * directly (de)serialised from memory.
-+ */
-+
-+ /* ensure the header structure has packed to the correct size */
-+ BUILD_BUG_ON(sizeof(struct mmal_msg_header) != 24);
-+
-+ /* ensure message structure does not exceed maximum length */
-+ BUILD_BUG_ON(sizeof(struct mmal_msg) > MMAL_MSG_MAX_SIZE);
-+
-+ /* mmal port struct is correct size */
-+ BUILD_BUG_ON(sizeof(struct mmal_port) != 64);
-+
-+ /* create a vchi instance */
-+ status = vchi_initialise(&vchi_instance);
-+ if (status) {
-+ pr_err("Failed to initialise VCHI instance (status=%d)\n",
-+ status);
-+ return -EIO;
-+ }
-+
-+ status = vchi_connect(NULL, 0, vchi_instance);
-+ if (status) {
-+ pr_err("Failed to connect VCHI instance (status=%d)\n", status);
-+ return -EIO;
-+ }
-+
-+ instance = kmalloc(sizeof(*instance), GFP_KERNEL);
-+ memset(instance, 0, sizeof(*instance));
-+
-+ mutex_init(&instance->vchiq_mutex);
-+ mutex_init(&instance->bulk_mutex);
-+
-+ instance->bulk_scratch = vmalloc(PAGE_SIZE);
-+
-+ params.callback_param = instance;
-+
-+ status = vchi_service_open(vchi_instance, &params, &instance->handle);
-+ if (status) {
-+ pr_err("Failed to open VCHI service connection (status=%d)\n",
-+ status);
-+ goto err_close_services;
-+ }
-+
-+ vchi_service_release(instance->handle);
-+
-+ *out_instance = instance;
-+
-+ return 0;
-+
-+err_close_services:
-+
-+ vchi_service_close(instance->handle);
-+ vfree(instance->bulk_scratch);
-+ kfree(instance);
-+ return -ENODEV;
-+}
-diff -Nur linux-3.12.38/drivers/media/platform/bcm2835/mmal-vchiq.h linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h
---- linux-3.12.38/drivers/media/platform/bcm2835/mmal-vchiq.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h 2015-03-09 10:39:30.594893734 +0100
-@@ -0,0 +1,178 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * MMAL interface to VCHIQ message passing
-+ */
-+
-+#ifndef MMAL_VCHIQ_H
-+#define MMAL_VCHIQ_H
-+
-+#include "mmal-msg-format.h"
-+
-+#define MAX_PORT_COUNT 4
-+
-+/* Maximum size of the format extradata. */
-+#define MMAL_FORMAT_EXTRADATA_MAX_SIZE 128
-+
-+struct vchiq_mmal_instance;
-+
-+enum vchiq_mmal_es_type {
-+ MMAL_ES_TYPE_UNKNOWN, /**< Unknown elementary stream type */
-+ MMAL_ES_TYPE_CONTROL, /**< Elementary stream of control commands */
-+ MMAL_ES_TYPE_AUDIO, /**< Audio elementary stream */
-+ MMAL_ES_TYPE_VIDEO, /**< Video elementary stream */
-+ MMAL_ES_TYPE_SUBPICTURE /**< Sub-picture elementary stream */
-+};
-+
-+/* rectangle, used lots so it gets its own struct */
-+struct vchiq_mmal_rect {
-+ s32 x;
-+ s32 y;
-+ s32 width;
-+ s32 height;
-+};
-+
-+struct vchiq_mmal_port_buffer {
-+ unsigned int num; /* number of buffers */
-+ u32 size; /* size of buffers */
-+ u32 alignment; /* alignment of buffers */
-+};
-+
-+struct vchiq_mmal_port;
-+
-+typedef void (*vchiq_mmal_buffer_cb)(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ int status, struct mmal_buffer *buffer,
-+ unsigned long length, u32 mmal_flags, s64 dts, s64 pts);
-+
-+struct vchiq_mmal_port {
-+ bool enabled;
-+ u32 handle;
-+ u32 type; /* port type, cached to use on port info set */
-+ u32 index; /* port index, cached to use on port info set */
-+
-+ /* component port belongs to, allows simple deref */
-+ struct vchiq_mmal_component *component;
-+
-+ struct vchiq_mmal_port *connected; /* port conencted to */
-+
-+ /* buffer info */
-+ struct vchiq_mmal_port_buffer minimum_buffer;
-+ struct vchiq_mmal_port_buffer recommended_buffer;
-+ struct vchiq_mmal_port_buffer current_buffer;
-+
-+ /* stream format */
-+ struct mmal_es_format format;
-+ /* elementry stream format */
-+ union mmal_es_specific_format es;
-+
-+ /* data buffers to fill */
-+ struct list_head buffers;
-+ /* lock to serialise adding and removing buffers from list */
-+ spinlock_t slock;
-+ /* count of how many buffer header refils have failed because
-+ * there was no buffer to satisfy them
-+ */
-+ int buffer_underflow;
-+ /* callback on buffer completion */
-+ vchiq_mmal_buffer_cb buffer_cb;
-+ /* callback context */
-+ void *cb_ctx;
-+};
-+
-+struct vchiq_mmal_component {
-+ bool enabled;
-+ u32 handle; /* VideoCore handle for component */
-+ u32 inputs; /* Number of input ports */
-+ u32 outputs; /* Number of output ports */
-+ u32 clocks; /* Number of clock ports */
-+ struct vchiq_mmal_port control; /* control port */
-+ struct vchiq_mmal_port input[MAX_PORT_COUNT]; /* input ports */
-+ struct vchiq_mmal_port output[MAX_PORT_COUNT]; /* output ports */
-+ struct vchiq_mmal_port clock[MAX_PORT_COUNT]; /* clock ports */
-+};
-+
-+
-+int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance);
-+int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance);
-+
-+/* Initialise a mmal component and its ports
-+*
-+*/
-+int vchiq_mmal_component_init(
-+ struct vchiq_mmal_instance *instance,
-+ const char *name,
-+ struct vchiq_mmal_component **component_out);
-+
-+int vchiq_mmal_component_finalise(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component);
-+
-+int vchiq_mmal_component_enable(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component);
-+
-+int vchiq_mmal_component_disable(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component);
-+
-+
-+
-+/* enable a mmal port
-+ *
-+ * enables a port and if a buffer callback provided enque buffer
-+ * headers as apropriate for the port.
-+ */
-+int vchiq_mmal_port_enable(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ vchiq_mmal_buffer_cb buffer_cb);
-+
-+/* disable a port
-+ *
-+ * disable a port will dequeue any pending buffers
-+ */
-+int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port);
-+
-+
-+int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter,
-+ void *value,
-+ u32 value_size);
-+
-+int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter,
-+ void *value,
-+ u32 *value_size);
-+
-+int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port);
-+
-+int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *src,
-+ struct vchiq_mmal_port *dst);
-+
-+int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
-+ u32 *major_out,
-+ u32 *minor_out);
-+
-+int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ struct mmal_buffer *buf);
-+
-+#endif /* MMAL_VCHIQ_H */
-diff -Nur linux-3.12.38/drivers/media/platform/Kconfig linux-rpi/drivers/media/platform/Kconfig
---- linux-3.12.38/drivers/media/platform/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/platform/Kconfig 2015-03-10 17:26:50.466216693 +0100
-@@ -124,6 +124,7 @@
- source "drivers/media/platform/soc_camera/Kconfig"
- source "drivers/media/platform/exynos4-is/Kconfig"
- source "drivers/media/platform/s5p-tv/Kconfig"
-+source "drivers/media/platform/bcm2835/Kconfig"
-
- endif # V4L_PLATFORM_DRIVERS
-
-diff -Nur linux-3.12.38/drivers/media/platform/Makefile linux-rpi/drivers/media/platform/Makefile
---- linux-3.12.38/drivers/media/platform/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/platform/Makefile 2015-03-10 17:26:50.466216693 +0100
-@@ -52,4 +52,6 @@
-
- obj-$(CONFIG_ARCH_OMAP) += omap/
-
-+obj-$(CONFIG_VIDEO_BCM2835) += bcm2835/
-+
- ccflags-y += -I$(srctree)/drivers/media/i2c
-diff -Nur linux-3.12.38/drivers/media/rc/ir-lirc-codec.c linux-rpi/drivers/media/rc/ir-lirc-codec.c
---- linux-3.12.38/drivers/media/rc/ir-lirc-codec.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/rc/ir-lirc-codec.c 2015-03-10 17:26:50.490216692 +0100
-@@ -42,17 +42,11 @@
- return -EINVAL;
-
- /* Packet start */
-- if (ev.reset) {
-- /* Userspace expects a long space event before the start of
-- * the signal to use as a sync. This may be done with repeat
-- * packets and normal samples. But if a reset has been sent
-- * then we assume that a long time has passed, so we send a
-- * space with the maximum time value. */
-- sample = LIRC_SPACE(LIRC_VALUE_MASK);
-- IR_dprintk(2, "delivering reset sync space to lirc_dev\n");
-+ if (ev.reset)
-+ return 0;
-
- /* Carrier reports */
-- } else if (ev.carrier_report) {
-+ if (ev.carrier_report) {
- sample = LIRC_FREQUENCY(ev.carrier);
- IR_dprintk(2, "carrier report (freq: %d)\n", sample);
-
-diff -Nur linux-3.12.38/drivers/media/usb/au0828/au0828-cards.c linux-rpi/drivers/media/usb/au0828/au0828-cards.c
---- linux-3.12.38/drivers/media/usb/au0828/au0828-cards.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/usb/au0828/au0828-cards.c 2015-03-10 17:26:50.498216692 +0100
-@@ -36,11 +36,6 @@
- au0828_clear(dev, REG_000, 0x10);
- }
-
--/*
-- * WARNING: There's a quirks table at sound/usb/quirks-table.h
-- * that should also be updated every time a new device with V4L2 support
-- * is added here.
-- */
- struct au0828_board au0828_boards[] = {
- [AU0828_BOARD_UNKNOWN] = {
- .name = "Unknown board",
-diff -Nur linux-3.12.38/drivers/media/usb/dvb-usb/af9005.c linux-rpi/drivers/media/usb/dvb-usb/af9005.c
---- linux-3.12.38/drivers/media/usb/dvb-usb/af9005.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/usb/dvb-usb/af9005.c 2015-03-10 17:26:50.506216692 +0100
-@@ -1081,12 +1081,9 @@
- err("usb_register failed. (%d)", result);
- return result;
- }
--#if IS_MODULE(CONFIG_DVB_USB_AF9005) || defined(CONFIG_DVB_USB_AF9005_REMOTE)
-- /* FIXME: convert to todays kernel IR infrastructure */
- rc_decode = symbol_request(af9005_rc_decode);
- rc_keys = symbol_request(rc_map_af9005_table);
- rc_keys_size = symbol_request(rc_map_af9005_table_size);
--#endif
- if (rc_decode == NULL || rc_keys == NULL || rc_keys_size == NULL) {
- err("af9005_rc_decode function not found, disabling remote");
- af9005_properties.rc.legacy.rc_query = NULL;
-diff -Nur linux-3.12.38/drivers/media/usb/dvb-usb-v2/rtl28xxu.c linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
---- linux-3.12.38/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-03-10 17:26:50.502216692 +0100
-@@ -1390,6 +1390,10 @@
- &rtl2832u_props, "Compro VideoMate U620F", NULL) },
- { DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394,
- &rtl2832u_props, "MaxMedia HU394-T", NULL) },
-+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/,
-+ &rtl2832u_props, "August DVB-T 205", NULL) },
-+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/,
-+ &rtl2832u_props, "August DVB-T 205", NULL) },
- { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03,
- &rtl2832u_props, "Leadtek WinFast DTV Dongle mini", NULL) },
- { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A,
-diff -Nur linux-3.12.38/drivers/media/usb/usbtv/usbtv.c linux-rpi/drivers/media/usb/usbtv/usbtv.c
---- linux-3.12.38/drivers/media/usb/usbtv/usbtv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/usb/usbtv/usbtv.c 2015-03-10 17:26:50.522216692 +0100
-@@ -50,13 +50,8 @@
- #define USBTV_ISOC_TRANSFERS 16
- #define USBTV_ISOC_PACKETS 8
-
--#define USBTV_WIDTH 720
--#define USBTV_HEIGHT 480
--
- #define USBTV_CHUNK_SIZE 256
- #define USBTV_CHUNK 240
--#define USBTV_CHUNKS (USBTV_WIDTH * USBTV_HEIGHT \
-- / 4 / USBTV_CHUNK)
-
- /* Chunk header. */
- #define USBTV_MAGIC_OK(chunk) ((be32_to_cpu(chunk[0]) & 0xff000000) \
-@@ -65,6 +60,27 @@
- #define USBTV_ODD(chunk) ((be32_to_cpu(chunk[0]) & 0x0000f000) >> 15)
- #define USBTV_CHUNK_NO(chunk) (be32_to_cpu(chunk[0]) & 0x00000fff)
-
-+#define USBTV_TV_STD (V4L2_STD_525_60 | V4L2_STD_PAL)
-+
-+/* parameters for supported TV norms */
-+struct usbtv_norm_params {
-+ v4l2_std_id norm;
-+ int cap_width, cap_height;
-+};
-+
-+static struct usbtv_norm_params norm_params[] = {
-+ {
-+ .norm = V4L2_STD_525_60,
-+ .cap_width = 720,
-+ .cap_height = 480,
-+ },
-+ {
-+ .norm = V4L2_STD_PAL,
-+ .cap_width = 720,
-+ .cap_height = 576,
-+ }
-+};
-+
- /* A single videobuf2 frame buffer. */
- struct usbtv_buf {
- struct vb2_buffer vb;
-@@ -94,11 +110,38 @@
- USBTV_COMPOSITE_INPUT,
- USBTV_SVIDEO_INPUT,
- } input;
-+ v4l2_std_id norm;
-+ int width, height;
-+ int n_chunks;
- int iso_size;
- unsigned int sequence;
- struct urb *isoc_urbs[USBTV_ISOC_TRANSFERS];
- };
-
-+static int usbtv_configure_for_norm(struct usbtv *usbtv, v4l2_std_id norm)
-+{
-+ int i, ret = 0;
-+ struct usbtv_norm_params *params = NULL;
-+
-+ for (i = 0; i < ARRAY_SIZE(norm_params); i++) {
-+ if (norm_params[i].norm & norm) {
-+ params = &norm_params[i];
-+ break;
-+ }
-+ }
-+
-+ if (params) {
-+ usbtv->width = params->cap_width;
-+ usbtv->height = params->cap_height;
-+ usbtv->n_chunks = usbtv->width * usbtv->height
-+ / 4 / USBTV_CHUNK;
-+ usbtv->norm = params->norm;
-+ } else
-+ ret = -EINVAL;
-+
-+ return ret;
-+}
-+
- static int usbtv_set_regs(struct usbtv *usbtv, const u16 regs[][2], int size)
- {
- int ret;
-@@ -158,6 +201,57 @@
- return ret;
- }
-
-+static int usbtv_select_norm(struct usbtv *usbtv, v4l2_std_id norm)
-+{
-+ int ret;
-+ static const u16 pal[][2] = {
-+ { USBTV_BASE + 0x001a, 0x0068 },
-+ { USBTV_BASE + 0x010e, 0x0072 },
-+ { USBTV_BASE + 0x010f, 0x00a2 },
-+ { USBTV_BASE + 0x0112, 0x00b0 },
-+ { USBTV_BASE + 0x0117, 0x0001 },
-+ { USBTV_BASE + 0x0118, 0x002c },
-+ { USBTV_BASE + 0x012d, 0x0010 },
-+ { USBTV_BASE + 0x012f, 0x0020 },
-+ { USBTV_BASE + 0x024f, 0x0002 },
-+ { USBTV_BASE + 0x0254, 0x0059 },
-+ { USBTV_BASE + 0x025a, 0x0016 },
-+ { USBTV_BASE + 0x025b, 0x0035 },
-+ { USBTV_BASE + 0x0263, 0x0017 },
-+ { USBTV_BASE + 0x0266, 0x0016 },
-+ { USBTV_BASE + 0x0267, 0x0036 }
-+ };
-+
-+ static const u16 ntsc[][2] = {
-+ { USBTV_BASE + 0x001a, 0x0079 },
-+ { USBTV_BASE + 0x010e, 0x0068 },
-+ { USBTV_BASE + 0x010f, 0x009c },
-+ { USBTV_BASE + 0x0112, 0x00f0 },
-+ { USBTV_BASE + 0x0117, 0x0000 },
-+ { USBTV_BASE + 0x0118, 0x00fc },
-+ { USBTV_BASE + 0x012d, 0x0004 },
-+ { USBTV_BASE + 0x012f, 0x0008 },
-+ { USBTV_BASE + 0x024f, 0x0001 },
-+ { USBTV_BASE + 0x0254, 0x005f },
-+ { USBTV_BASE + 0x025a, 0x0012 },
-+ { USBTV_BASE + 0x025b, 0x0001 },
-+ { USBTV_BASE + 0x0263, 0x001c },
-+ { USBTV_BASE + 0x0266, 0x0011 },
-+ { USBTV_BASE + 0x0267, 0x0005 }
-+ };
-+
-+ ret = usbtv_configure_for_norm(usbtv, norm);
-+
-+ if (!ret) {
-+ if (norm & V4L2_STD_525_60)
-+ ret = usbtv_set_regs(usbtv, ntsc, ARRAY_SIZE(ntsc));
-+ else if (norm & V4L2_STD_PAL)
-+ ret = usbtv_set_regs(usbtv, pal, ARRAY_SIZE(pal));
-+ }
-+
-+ return ret;
-+}
-+
- static int usbtv_setup_capture(struct usbtv *usbtv)
- {
- int ret;
-@@ -225,26 +319,11 @@
-
- { USBTV_BASE + 0x0284, 0x0088 },
- { USBTV_BASE + 0x0003, 0x0004 },
-- { USBTV_BASE + 0x001a, 0x0079 },
- { USBTV_BASE + 0x0100, 0x00d3 },
-- { USBTV_BASE + 0x010e, 0x0068 },
-- { USBTV_BASE + 0x010f, 0x009c },
-- { USBTV_BASE + 0x0112, 0x00f0 },
- { USBTV_BASE + 0x0115, 0x0015 },
-- { USBTV_BASE + 0x0117, 0x0000 },
-- { USBTV_BASE + 0x0118, 0x00fc },
-- { USBTV_BASE + 0x012d, 0x0004 },
-- { USBTV_BASE + 0x012f, 0x0008 },
- { USBTV_BASE + 0x0220, 0x002e },
- { USBTV_BASE + 0x0225, 0x0008 },
- { USBTV_BASE + 0x024e, 0x0002 },
-- { USBTV_BASE + 0x024f, 0x0001 },
-- { USBTV_BASE + 0x0254, 0x005f },
-- { USBTV_BASE + 0x025a, 0x0012 },
-- { USBTV_BASE + 0x025b, 0x0001 },
-- { USBTV_BASE + 0x0263, 0x001c },
-- { USBTV_BASE + 0x0266, 0x0011 },
-- { USBTV_BASE + 0x0267, 0x0005 },
- { USBTV_BASE + 0x024e, 0x0002 },
- { USBTV_BASE + 0x024f, 0x0002 },
- };
-@@ -253,6 +332,10 @@
- if (ret)
- return ret;
-
-+ ret = usbtv_select_norm(usbtv, usbtv->norm);
-+ if (ret)
-+ return ret;
-+
- ret = usbtv_select_input(usbtv, usbtv->input);
- if (ret)
- return ret;
-@@ -296,7 +379,7 @@
- frame_id = USBTV_FRAME_ID(chunk);
- odd = USBTV_ODD(chunk);
- chunk_no = USBTV_CHUNK_NO(chunk);
-- if (chunk_no >= USBTV_CHUNKS)
-+ if (chunk_no >= usbtv->n_chunks)
- return;
-
- /* Beginning of a frame. */
-@@ -324,10 +407,10 @@
- usbtv->chunks_done++;
-
- /* Last chunk in a frame, signalling an end */
-- if (odd && chunk_no == USBTV_CHUNKS-1) {
-+ if (odd && chunk_no == usbtv->n_chunks-1) {
- int size = vb2_plane_size(&buf->vb, 0);
- enum vb2_buffer_state state = usbtv->chunks_done ==
-- USBTV_CHUNKS ?
-+ usbtv->n_chunks ?
- VB2_BUF_STATE_DONE :
- VB2_BUF_STATE_ERROR;
-
-@@ -500,6 +583,8 @@
- static int usbtv_enum_input(struct file *file, void *priv,
- struct v4l2_input *i)
- {
-+ struct usbtv *dev = video_drvdata(file);
-+
- switch (i->index) {
- case USBTV_COMPOSITE_INPUT:
- strlcpy(i->name, "Composite", sizeof(i->name));
-@@ -512,7 +597,7 @@
- }
-
- i->type = V4L2_INPUT_TYPE_CAMERA;
-- i->std = V4L2_STD_525_60;
-+ i->std = dev->vdev.tvnorms;
- return 0;
- }
-
-@@ -531,23 +616,37 @@
- static int usbtv_fmt_vid_cap(struct file *file, void *priv,
- struct v4l2_format *f)
- {
-- f->fmt.pix.width = USBTV_WIDTH;
-- f->fmt.pix.height = USBTV_HEIGHT;
-+ struct usbtv *usbtv = video_drvdata(file);
-+
-+ f->fmt.pix.width = usbtv->width;
-+ f->fmt.pix.height = usbtv->height;
- f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUYV;
- f->fmt.pix.field = V4L2_FIELD_INTERLACED;
-- f->fmt.pix.bytesperline = USBTV_WIDTH * 2;
-+ f->fmt.pix.bytesperline = usbtv->width * 2;
- f->fmt.pix.sizeimage = (f->fmt.pix.bytesperline * f->fmt.pix.height);
- f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
-- f->fmt.pix.priv = 0;
-+
- return 0;
- }
-
- static int usbtv_g_std(struct file *file, void *priv, v4l2_std_id *norm)
- {
-- *norm = V4L2_STD_525_60;
-+ struct usbtv *usbtv = video_drvdata(file);
-+ *norm = usbtv->norm;
- return 0;
- }
-
-+static int usbtv_s_std(struct file *file, void *priv, v4l2_std_id norm)
-+{
-+ int ret = -EINVAL;
-+ struct usbtv *usbtv = video_drvdata(file);
-+
-+ if ((norm & V4L2_STD_525_60) || (norm & V4L2_STD_PAL))
-+ ret = usbtv_select_norm(usbtv, norm);
-+
-+ return ret;
-+}
-+
- static int usbtv_g_input(struct file *file, void *priv, unsigned int *i)
- {
- struct usbtv *usbtv = video_drvdata(file);
-@@ -561,13 +660,6 @@
- return usbtv_select_input(usbtv, i);
- }
-
--static int usbtv_s_std(struct file *file, void *priv, v4l2_std_id norm)
--{
-- if (norm & V4L2_STD_525_60)
-- return 0;
-- return -EINVAL;
--}
--
- struct v4l2_ioctl_ops usbtv_ioctl_ops = {
- .vidioc_querycap = usbtv_querycap,
- .vidioc_enum_input = usbtv_enum_input,
-@@ -604,10 +696,12 @@
- const struct v4l2_format *v4l_fmt, unsigned int *nbuffers,
- unsigned int *nplanes, unsigned int sizes[], void *alloc_ctxs[])
- {
-+ struct usbtv *usbtv = vb2_get_drv_priv(vq);
-+
- if (*nbuffers < 2)
- *nbuffers = 2;
- *nplanes = 1;
-- sizes[0] = USBTV_WIDTH * USBTV_HEIGHT / 2 * sizeof(u32);
-+ sizes[0] = USBTV_CHUNK * usbtv->n_chunks * 2 * sizeof(u32);
-
- return 0;
- }
-@@ -690,7 +784,11 @@
- return -ENOMEM;
- usbtv->dev = dev;
- usbtv->udev = usb_get_dev(interface_to_usbdev(intf));
-+
- usbtv->iso_size = size;
-+
-+ (void)usbtv_configure_for_norm(usbtv, V4L2_STD_525_60);
-+
- spin_lock_init(&usbtv->buflock);
- mutex_init(&usbtv->v4l2_lock);
- mutex_init(&usbtv->vb2q_lock);
-@@ -727,7 +825,7 @@
- usbtv->vdev.release = video_device_release_empty;
- usbtv->vdev.fops = &usbtv_fops;
- usbtv->vdev.ioctl_ops = &usbtv_ioctl_ops;
-- usbtv->vdev.tvnorms = V4L2_STD_525_60;
-+ usbtv->vdev.tvnorms = USBTV_TV_STD;
- usbtv->vdev.queue = &usbtv->vb2q;
- usbtv->vdev.lock = &usbtv->v4l2_lock;
- set_bit(V4L2_FL_USE_FH_PRIO, &usbtv->vdev.flags);
-diff -Nur linux-3.12.38/drivers/media/usb/uvc/uvc_driver.c linux-rpi/drivers/media/usb/uvc/uvc_driver.c
---- linux-3.12.38/drivers/media/usb/uvc/uvc_driver.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/media/usb/uvc/uvc_driver.c 2015-03-10 17:26:50.526216692 +0100
-@@ -1603,12 +1603,12 @@
- {
- struct list_head *p, *n;
-
-- uvc_status_cleanup(dev);
-- uvc_ctrl_cleanup_device(dev);
--
- usb_put_intf(dev->intf);
- usb_put_dev(dev->udev);
-
-+ uvc_status_cleanup(dev);
-+ uvc_ctrl_cleanup_device(dev);
-+
- if (dev->vdev.dev)
- v4l2_device_unregister(&dev->vdev);
- #ifdef CONFIG_MEDIA_CONTROLLER
-diff -Nur linux-3.12.38/drivers/misc/Kconfig linux-rpi/drivers/misc/Kconfig
---- linux-3.12.38/drivers/misc/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/misc/Kconfig 2015-03-10 17:26:50.546216692 +0100
-@@ -537,4 +537,5 @@
- source "drivers/misc/altera-stapl/Kconfig"
- source "drivers/misc/mei/Kconfig"
- source "drivers/misc/vmw_vmci/Kconfig"
-+source "drivers/misc/vc04_services/Kconfig"
- endmenu
-diff -Nur linux-3.12.38/drivers/misc/Makefile linux-rpi/drivers/misc/Makefile
---- linux-3.12.38/drivers/misc/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/misc/Makefile 2015-03-10 17:26:50.546216692 +0100
-@@ -53,3 +53,4 @@
- obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/
- obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o
- obj-$(CONFIG_SRAM) += sram.o
-+obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/connections/connection.h linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/connections/connection.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,328 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef CONNECTION_H_
-+#define CONNECTION_H_
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/semaphore.h>
-+
-+#include "interface/vchi/vchi_cfg_internal.h"
-+#include "interface/vchi/vchi_common.h"
-+#include "interface/vchi/message_drivers/message.h"
-+
-+/******************************************************************************
-+ Global defs
-+ *****************************************************************************/
-+
-+// Opaque handle for a connection / service pair
-+typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T;
-+
-+// opaque handle to the connection state information
-+typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T;
-+
-+typedef struct vchi_connection_t VCHI_CONNECTION_T;
-+
-+
-+/******************************************************************************
-+ API
-+ *****************************************************************************/
-+
-+// Routine to init a connection with a particular low level driver
-+typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection,
-+ const VCHI_MESSAGE_DRIVER_T * driver );
-+
-+// Routine to control CRC enabling at a connection level
-+typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle,
-+ VCHI_CRC_CONTROL_T control );
-+
-+// Routine to create a service
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle,
-+ int32_t service_id,
-+ uint32_t rx_fifo_size,
-+ uint32_t tx_fifo_size,
-+ int server,
-+ VCHI_CALLBACK_T callback,
-+ void *callback_param,
-+ int32_t want_crc,
-+ int32_t want_unaligned_bulk_rx,
-+ int32_t want_unaligned_bulk_tx,
-+ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle );
-+
-+// Routine to close a service
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle );
-+
-+// Routine to queue a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ const void *data,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// scatter-gather (vector) message queueing
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ VCHI_MSG_VECTOR_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// Routine to dequeue a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *data,
-+ uint32_t max_data_size_to_read,
-+ uint32_t *actual_msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to peek at a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to hold a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags,
-+ void **message_handle );
-+
-+// Routine to initialise a received message iterator
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ VCHI_MSG_ITER_T *iter,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to release a held message
-+typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *message_handle );
-+
-+// Routine to get info on a held message
-+typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *message_handle,
-+ void **data,
-+ int32_t *msg_size,
-+ uint32_t *tx_timestamp,
-+ uint32_t *rx_timestamp );
-+
-+// Routine to check whether the iterator has a next message
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ const VCHI_MSG_ITER_T *iter );
-+
-+// Routine to advance the iterator
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ VCHI_MSG_ITER_T *iter,
-+ void **data,
-+ uint32_t *msg_size );
-+
-+// Routine to remove the last message returned by the iterator
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ VCHI_MSG_ITER_T *iter );
-+
-+// Routine to hold the last message returned by the iterator
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ VCHI_MSG_ITER_T *iter,
-+ void **msg_handle );
-+
-+// Routine to transmit bulk data
-+typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ const void *data_src,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle );
-+
-+// Routine to receive data
-+typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *data_dst,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle );
-+
-+// Routine to report if a server is available
-+typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags );
-+
-+// Routine to report the number of RX slots available
-+typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state );
-+
-+// Routine to report the RX slot size
-+typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state );
-+
-+// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO
-+typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state,
-+ int32_t service,
-+ uint32_t length,
-+ MESSAGE_TX_CHANNEL_T channel,
-+ uint32_t channel_params,
-+ uint32_t data_length,
-+ uint32_t data_offset);
-+
-+// Callback to inform a service that a Xon or Xoff message has been received
-+typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff);
-+
-+// Callback to inform a service that a server available reply message has been received
-+typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags);
-+
-+// Callback to indicate that bulk auxiliary messages have arrived
-+typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state);
-+
-+// Callback to indicate that bulk auxiliary messages have arrived
-+typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle);
-+
-+// Callback with all the connection info you require
-+typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size);
-+
-+// Callback to inform of a disconnect
-+typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags);
-+
-+// Callback to inform of a power control request
-+typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable);
-+
-+// allocate memory suitably aligned for this connection
-+typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length);
-+
-+// free memory allocated by buffer_allocate
-+typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address);
-+
-+
-+/******************************************************************************
-+ System driver struct
-+ *****************************************************************************/
-+
-+struct opaque_vchi_connection_api_t
-+{
-+ // Routine to init the connection
-+ VCHI_CONNECTION_INIT_T init;
-+
-+ // Connection-level CRC control
-+ VCHI_CONNECTION_CRC_CONTROL_T crc_control;
-+
-+ // Routine to connect to or create service
-+ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect;
-+
-+ // Routine to disconnect from a service
-+ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect;
-+
-+ // Routine to queue a message
-+ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg;
-+
-+ // scatter-gather (vector) message queue
-+ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv;
-+
-+ // Routine to dequeue a message
-+ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg;
-+
-+ // Routine to peek at a message
-+ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg;
-+
-+ // Routine to hold a message
-+ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg;
-+
-+ // Routine to initialise a received message iterator
-+ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg;
-+
-+ // Routine to release a message
-+ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release;
-+
-+ // Routine to get information on a held message
-+ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info;
-+
-+ // Routine to check for next message on iterator
-+ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next;
-+
-+ // Routine to get next message on iterator
-+ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next;
-+
-+ // Routine to remove the last message returned by iterator
-+ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove;
-+
-+ // Routine to hold the last message returned by iterator
-+ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold;
-+
-+ // Routine to transmit bulk data
-+ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit;
-+
-+ // Routine to receive data
-+ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive;
-+
-+ // Routine to report the available servers
-+ VCHI_CONNECTION_SERVER_PRESENT server_present;
-+
-+ // Routine to report the number of RX slots available
-+ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available;
-+
-+ // Routine to report the RX slot size
-+ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size;
-+
-+ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO
-+ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added;
-+
-+ // Callback to inform a service that a Xon or Xoff message has been received
-+ VCHI_CONNECTION_FLOW_CONTROL flow_control;
-+
-+ // Callback to inform a service that a server available reply message has been received
-+ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply;
-+
-+ // Callback to indicate that bulk auxiliary messages have arrived
-+ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received;
-+
-+ // Callback to indicate that a bulk auxiliary message has been transmitted
-+ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted;
-+
-+ // Callback to provide information about the connection
-+ VCHI_CONNECTION_INFO connection_info;
-+
-+ // Callback to notify that peer has requested disconnect
-+ VCHI_CONNECTION_DISCONNECT disconnect;
-+
-+ // Callback to notify that peer has requested power change
-+ VCHI_CONNECTION_POWER_CONTROL power_control;
-+
-+ // allocate memory suitably aligned for this connection
-+ VCHI_BUFFER_ALLOCATE buffer_allocate;
-+
-+ // free memory allocated by buffer_allocate
-+ VCHI_BUFFER_FREE buffer_free;
-+
-+};
-+
-+struct vchi_connection_t {
-+ const VCHI_CONNECTION_API_T *api;
-+ VCHI_CONNECTION_STATE_T *state;
-+#ifdef VCHI_COARSE_LOCKING
-+ struct semaphore sem;
-+#endif
-+};
-+
-+
-+#endif /* CONNECTION_H_ */
-+
-+/****************************** End of file **********************************/
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,204 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef _VCHI_MESSAGE_H_
-+#define _VCHI_MESSAGE_H_
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/semaphore.h>
-+
-+#include "interface/vchi/vchi_cfg_internal.h"
-+#include "interface/vchi/vchi_common.h"
-+
-+
-+typedef enum message_event_type {
-+ MESSAGE_EVENT_NONE,
-+ MESSAGE_EVENT_NOP,
-+ MESSAGE_EVENT_MESSAGE,
-+ MESSAGE_EVENT_SLOT_COMPLETE,
-+ MESSAGE_EVENT_RX_BULK_PAUSED,
-+ MESSAGE_EVENT_RX_BULK_COMPLETE,
-+ MESSAGE_EVENT_TX_COMPLETE,
-+ MESSAGE_EVENT_MSG_DISCARDED
-+} MESSAGE_EVENT_TYPE_T;
-+
-+typedef enum vchi_msg_flags
-+{
-+ VCHI_MSG_FLAGS_NONE = 0x0,
-+ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1
-+} VCHI_MSG_FLAGS_T;
-+
-+typedef enum message_tx_channel
-+{
-+ MESSAGE_TX_CHANNEL_MESSAGE = 0,
-+ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards
-+} MESSAGE_TX_CHANNEL_T;
-+
-+// Macros used for cycling through bulk channels
-+#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION)
-+#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION)
-+
-+typedef enum message_rx_channel
-+{
-+ MESSAGE_RX_CHANNEL_MESSAGE = 0,
-+ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards
-+} MESSAGE_RX_CHANNEL_T;
-+
-+// Message receive slot information
-+typedef struct rx_msg_slot_info {
-+
-+ struct rx_msg_slot_info *next;
-+ //struct slot_info *prev;
-+#if !defined VCHI_COARSE_LOCKING
-+ struct semaphore sem;
-+#endif
-+
-+ uint8_t *addr; // base address of slot
-+ uint32_t len; // length of slot in bytes
-+
-+ uint32_t write_ptr; // hardware causes this to advance
-+ uint32_t read_ptr; // this module does the reading
-+ int active; // is this slot in the hardware dma fifo?
-+ uint32_t msgs_parsed; // count how many messages are in this slot
-+ uint32_t msgs_released; // how many messages have been released
-+ void *state; // connection state information
-+ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services
-+} RX_MSG_SLOTINFO_T;
-+
-+// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out.
-+// In particular, it mustn't use addr and len - they're the client buffer, but the message
-+// driver will be tasked with sending the aligned core section.
-+typedef struct rx_bulk_slotinfo_t {
-+ struct rx_bulk_slotinfo_t *next;
-+
-+ struct semaphore *blocking;
-+
-+ // needed by DMA
-+ void *addr;
-+ uint32_t len;
-+
-+ // needed for the callback
-+ void *service;
-+ void *handle;
-+ VCHI_FLAGS_T flags;
-+} RX_BULK_SLOTINFO_T;
-+
-+
-+/* ----------------------------------------------------------------------
-+ * each connection driver will have a pool of the following struct.
-+ *
-+ * the pool will be managed by vchi_qman_*
-+ * this means there will be multiple queues (single linked lists)
-+ * a given struct message_info will be on exactly one of these queues
-+ * at any one time
-+ * -------------------------------------------------------------------- */
-+typedef struct rx_message_info {
-+
-+ struct message_info *next;
-+ //struct message_info *prev;
-+
-+ uint8_t *addr;
-+ uint32_t len;
-+ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message
-+ uint32_t tx_timestamp;
-+ uint32_t rx_timestamp;
-+
-+} RX_MESSAGE_INFO_T;
-+
-+typedef struct {
-+ MESSAGE_EVENT_TYPE_T type;
-+
-+ struct {
-+ // for messages
-+ void *addr; // address of message
-+ uint16_t slot_delta; // whether this message indicated slot delta
-+ uint32_t len; // length of message
-+ RX_MSG_SLOTINFO_T *slot; // slot this message is in
-+ int32_t service; // service id this message is destined for
-+ uint32_t tx_timestamp; // timestamp from the header
-+ uint32_t rx_timestamp; // timestamp when we parsed it
-+ } message;
-+
-+ // FIXME: cleanup slot reporting...
-+ RX_MSG_SLOTINFO_T *rx_msg;
-+ RX_BULK_SLOTINFO_T *rx_bulk;
-+ void *tx_handle;
-+ MESSAGE_TX_CHANNEL_T tx_channel;
-+
-+} MESSAGE_EVENT_T;
-+
-+
-+// callbacks
-+typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state );
-+
-+typedef struct {
-+ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback;
-+} VCHI_MESSAGE_DRIVER_OPEN_T;
-+
-+
-+// handle to this instance of message driver (as returned by ->open)
-+typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T;
-+
-+struct opaque_vchi_message_driver_t {
-+ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state );
-+ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle );
-+ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle );
-+ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable );
-+ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message
-+ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk)
-+ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk)
-+ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver
-+ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle );
-+ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void
-+ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial );
-+
-+ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count );
-+ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length );
-+ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length );
-+ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address );
-+ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size );
-+ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size );
-+
-+ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
-+ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
-+ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
-+ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel );
-+ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len );
-+ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle );
-+};
-+
-+
-+#endif // _VCHI_MESSAGE_H_
-+
-+/****************************** End of file ***********************************/
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,224 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_CFG_H_
-+#define VCHI_CFG_H_
-+
-+/****************************************************************************************
-+ * Defines in this first section are part of the VCHI API and may be examined by VCHI
-+ * services.
-+ ***************************************************************************************/
-+
-+/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */
-+/* Really determined by the message driver, and should be available from a run-time call. */
-+#ifndef VCHI_BULK_ALIGN
-+# if __VCCOREVER__ >= 0x04000000
-+# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans
-+# else
-+# define VCHI_BULK_ALIGN 16
-+# endif
-+#endif
-+
-+/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */
-+/* May be less than or greater than VCHI_BULK_ALIGN */
-+/* Really determined by the message driver, and should be available from a run-time call. */
-+#ifndef VCHI_BULK_GRANULARITY
-+# if __VCCOREVER__ >= 0x04000000
-+# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans
-+# else
-+# define VCHI_BULK_GRANULARITY 16
-+# endif
-+#endif
-+
-+/* The largest possible message to be queued with vchi_msg_queue. */
-+#ifndef VCHI_MAX_MSG_SIZE
-+# if defined VCHI_LOCAL_HOST_PORT
-+# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk?
-+# else
-+# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!!
-+# endif
-+#endif
-+
-+/******************************************************************************************
-+ * Defines below are system configuration options, and should not be used by VCHI services.
-+ *****************************************************************************************/
-+
-+/* How many connections can we support? A localhost implementation uses 2 connections,
-+ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW
-+ * driver. */
-+#ifndef VCHI_MAX_NUM_CONNECTIONS
-+# define VCHI_MAX_NUM_CONNECTIONS 3
-+#endif
-+
-+/* How many services can we open per connection? Extending this doesn't cost processing time, just a small
-+ * amount of static memory. */
-+#ifndef VCHI_MAX_SERVICES_PER_CONNECTION
-+# define VCHI_MAX_SERVICES_PER_CONNECTION 36
-+#endif
-+
-+/* Adjust if using a message driver that supports more logical TX channels */
-+#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION
-+# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels
-+#endif
-+
-+/* Adjust if using a message driver that supports more logical RX channels */
-+#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION
-+# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI
-+#endif
-+
-+/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective
-+ * receive queue space, less message headers. */
-+#ifndef VCHI_NUM_READ_SLOTS
-+# if defined(VCHI_LOCAL_HOST_PORT)
-+# define VCHI_NUM_READ_SLOTS 4
-+# else
-+# define VCHI_NUM_READ_SLOTS 48
-+# endif
-+#endif
-+
-+/* Do we utilise overrun facility for receive message slots? Can aid peer transmit
-+ * performance. Only define on VideoCore end, talking to host.
-+ */
-+//#define VCHI_MSG_RX_OVERRUN
-+
-+/* How many transmit slots do we use. Generally don't need many, as the hardware driver
-+ * underneath VCHI will usually have its own buffering. */
-+#ifndef VCHI_NUM_WRITE_SLOTS
-+# define VCHI_NUM_WRITE_SLOTS 4
-+#endif
-+
-+/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots,
-+ * then it's taking up too much buffer space, and the peer service will be told to stop
-+ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS
-+ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency
-+ * is too high. */
-+#ifndef VCHI_XOFF_THRESHOLD
-+# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2)
-+#endif
-+
-+/* After we've sent an XOFF, the peer will be told to resume transmission once the local
-+ * service has dequeued/released enough messages that it's now occupying
-+ * VCHI_XON_THRESHOLD slots or fewer. */
-+#ifndef VCHI_XON_THRESHOLD
-+# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4)
-+#endif
-+
-+/* A size below which a bulk transfer omits the handshake completely and always goes
-+ * via the message channel, if bulk auxiliary is being sent on that service. (The user
-+ * can guarantee this by enabling unaligned transmits).
-+ * Not API. */
-+#ifndef VCHI_MIN_BULK_SIZE
-+# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 )
-+#endif
-+
-+/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between
-+ * speed and latency; the smaller the chunk size the better change of messages and other
-+ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not
-+ * break transmissions into chunks.
-+ */
-+#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI
-+# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024)
-+#endif
-+
-+/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode
-+ * with multiple-line frames. Only use if the receiver can cope. */
-+#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2
-+# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0
-+#endif
-+
-+/* How many TX messages can we have pending in our transmit slots. Once exhausted,
-+ * vchi_msg_queue will be blocked. */
-+#ifndef VCHI_TX_MSG_QUEUE_SIZE
-+# define VCHI_TX_MSG_QUEUE_SIZE 256
-+#endif
-+
-+/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing
-+ * will be suspended until older messages are dequeued/released. */
-+#ifndef VCHI_RX_MSG_QUEUE_SIZE
-+# define VCHI_RX_MSG_QUEUE_SIZE 256
-+#endif
-+
-+/* Really should be able to cope if we run out of received message descriptors, by
-+ * suspending parsing as the comment above says, but we don't. This sweeps the issue
-+ * under the carpet. */
-+#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS
-+# undef VCHI_RX_MSG_QUEUE_SIZE
-+# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS
-+#endif
-+
-+/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit
-+ * will be blocked. */
-+#ifndef VCHI_TX_BULK_QUEUE_SIZE
-+# define VCHI_TX_BULK_QUEUE_SIZE 64
-+#endif
-+
-+/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive
-+ * will be blocked. */
-+#ifndef VCHI_RX_BULK_QUEUE_SIZE
-+# define VCHI_RX_BULK_QUEUE_SIZE 64
-+#endif
-+
-+/* A limit on how many outstanding bulk requests we expect the peer to give us. If
-+ * the peer asks for more than this, VCHI will fail and assert. The number is determined
-+ * by the peer's hardware - it's the number of outstanding requests that can be queued
-+ * on all bulk channels. VC3's MPHI peripheral allows 16. */
-+#ifndef VCHI_MAX_PEER_BULK_REQUESTS
-+# define VCHI_MAX_PEER_BULK_REQUESTS 32
-+#endif
-+
-+/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2
-+ * transmitter on and off.
-+ */
-+/*#define VCHI_CCP2TX_MANUAL_POWER*/
-+
-+#ifndef VCHI_CCP2TX_MANUAL_POWER
-+
-+/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set
-+ * negative for no IDLE.
-+ */
-+# ifndef VCHI_CCP2TX_IDLE_TIMEOUT
-+# define VCHI_CCP2TX_IDLE_TIMEOUT 5
-+# endif
-+
-+/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set
-+ * negative for no OFF.
-+ */
-+# ifndef VCHI_CCP2TX_OFF_TIMEOUT
-+# define VCHI_CCP2TX_OFF_TIMEOUT 1000
-+# endif
-+
-+#endif /* VCHI_CCP2TX_MANUAL_POWER */
-+
-+#endif /* VCHI_CFG_H_ */
-+
-+/****************************** End of file **********************************/
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,71 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_CFG_INTERNAL_H_
-+#define VCHI_CFG_INTERNAL_H_
-+
-+/****************************************************************************************
-+ * Control optimisation attempts.
-+ ***************************************************************************************/
-+
-+// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second
-+#define VCHI_COARSE_LOCKING
-+
-+// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx)
-+// (only relevant if VCHI_COARSE_LOCKING)
-+#define VCHI_ELIDE_BLOCK_EXIT_LOCK
-+
-+// Avoid lock on non-blocking peek
-+// (only relevant if VCHI_COARSE_LOCKING)
-+#define VCHI_AVOID_PEEK_LOCK
-+
-+// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation.
-+#define VCHI_MULTIPLE_HANDLER_THREADS
-+
-+// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash
-+// our way through the pool of descriptors.
-+#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD
-+
-+// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING.
-+#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS
-+
-+// Don't use message descriptors for TX messages that don't need them
-+#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS
-+
-+// Nano-locks for multiqueue
-+//#define VCHI_MQUEUE_NANOLOCKS
-+
-+// Lock-free(er) dequeuing
-+//#define VCHI_RX_NANOLOCKS
-+
-+#endif /*VCHI_CFG_INTERNAL_H_*/
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_common.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_common.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,174 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_COMMON_H_
-+#define VCHI_COMMON_H_
-+
-+
-+//flags used when sending messages (must be bitmapped)
-+typedef enum
-+{
-+ VCHI_FLAGS_NONE = 0x0,
-+ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side)
-+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go
-+ VCHI_FLAGS_ALLOW_PARTIAL = 0x8,
-+ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10,
-+ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20,
-+
-+ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only
-+ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only
-+ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only
-+ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only
-+ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only
-+ VCHI_FLAGS_INTERNAL = 0xFF0000
-+} VCHI_FLAGS_T;
-+
-+// constants for vchi_crc_control()
-+typedef enum {
-+ VCHI_CRC_NOTHING = -1,
-+ VCHI_CRC_PER_SERVICE = 0,
-+ VCHI_CRC_EVERYTHING = 1,
-+} VCHI_CRC_CONTROL_T;
-+
-+//callback reasons when an event occurs on a service
-+typedef enum
-+{
-+ VCHI_CALLBACK_REASON_MIN,
-+
-+ //This indicates that there is data available
-+ //handle is the msg id that was transmitted with the data
-+ // When a message is received and there was no FULL message available previously, send callback
-+ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails
-+ VCHI_CALLBACK_MSG_AVAILABLE,
-+ VCHI_CALLBACK_MSG_SENT,
-+ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented
-+
-+ // This indicates that a transfer from the other side has completed
-+ VCHI_CALLBACK_BULK_RECEIVED,
-+ //This indicates that data queued up to be sent has now gone
-+ //handle is the msg id that was used when sending the data
-+ VCHI_CALLBACK_BULK_SENT,
-+ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented
-+ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented
-+
-+ VCHI_CALLBACK_SERVICE_CLOSED,
-+
-+ // this side has sent XOFF to peer due to lack of data consumption by service
-+ // (suggests the service may need to take some recovery action if it has
-+ // been deliberately holding off consuming data)
-+ VCHI_CALLBACK_SENT_XOFF,
-+ VCHI_CALLBACK_SENT_XON,
-+
-+ // indicates that a bulk transfer has finished reading the source buffer
-+ VCHI_CALLBACK_BULK_DATA_READ,
-+
-+ // power notification events (currently host side only)
-+ VCHI_CALLBACK_PEER_OFF,
-+ VCHI_CALLBACK_PEER_SUSPENDED,
-+ VCHI_CALLBACK_PEER_ON,
-+ VCHI_CALLBACK_PEER_RESUMED,
-+ VCHI_CALLBACK_FORCED_POWER_OFF,
-+
-+#ifdef USE_VCHIQ_ARM
-+ // some extra notifications provided by vchiq_arm
-+ VCHI_CALLBACK_SERVICE_OPENED,
-+ VCHI_CALLBACK_BULK_RECEIVE_ABORTED,
-+ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED,
-+#endif
-+
-+ VCHI_CALLBACK_REASON_MAX
-+} VCHI_CALLBACK_REASON_T;
-+
-+// service control options
-+typedef enum
-+{
-+ VCHI_SERVICE_OPTION_MIN,
-+
-+ VCHI_SERVICE_OPTION_TRACE,
-+
-+ VCHI_SERVICE_OPTION_MAX
-+} VCHI_SERVICE_OPTION_T;
-+
-+
-+//Callback used by all services / bulk transfers
-+typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param
-+ VCHI_CALLBACK_REASON_T reason,
-+ void *handle ); //for transmitting msg's only
-+
-+
-+
-+/*
-+ * Define vector struct for scatter-gather (vector) operations
-+ * Vectors can be nested - if a vector element has negative length, then
-+ * the data pointer is treated as pointing to another vector array, with
-+ * '-vec_len' elements. Thus to append a header onto an existing vector,
-+ * you can do this:
-+ *
-+ * void foo(const VCHI_MSG_VECTOR_T *v, int n)
-+ * {
-+ * VCHI_MSG_VECTOR_T nv[2];
-+ * nv[0].vec_base = my_header;
-+ * nv[0].vec_len = sizeof my_header;
-+ * nv[1].vec_base = v;
-+ * nv[1].vec_len = -n;
-+ * ...
-+ *
-+ */
-+typedef struct vchi_msg_vector {
-+ const void *vec_base;
-+ int32_t vec_len;
-+} VCHI_MSG_VECTOR_T;
-+
-+// Opaque type for a connection API
-+typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T;
-+
-+// Opaque type for a message driver
-+typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T;
-+
-+
-+// Iterator structure for reading ahead through received message queue. Allocated by client,
-+// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only.
-+// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead -
-+// will not proceed to messages received since. Behaviour is undefined if an iterator
-+// is used again after messages for that service are removed/dequeued by any
-+// means other than vchi_msg_iter_... calls on the iterator itself.
-+typedef struct {
-+ struct opaque_vchi_service_t *service;
-+ void *last;
-+ void *next;
-+ void *remove;
-+} VCHI_MSG_ITER_T;
-+
-+
-+#endif // VCHI_COMMON_H_
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,378 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_H_
-+#define VCHI_H_
-+
-+#include "interface/vchi/vchi_cfg.h"
-+#include "interface/vchi/vchi_common.h"
-+#include "interface/vchi/connections/connection.h"
-+#include "vchi_mh.h"
-+
-+
-+/******************************************************************************
-+ Global defs
-+ *****************************************************************************/
-+
-+#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1))
-+#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1))
-+#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1))))
-+
-+#ifdef USE_VCHIQ_ARM
-+#define VCHI_BULK_ALIGNED(x) 1
-+#else
-+#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0)
-+#endif
-+
-+struct vchi_version {
-+ uint32_t version;
-+ uint32_t version_min;
-+};
-+#define VCHI_VERSION(v_) { v_, v_ }
-+#define VCHI_VERSION_EX(v_, m_) { v_, m_ }
-+
-+typedef enum
-+{
-+ VCHI_VEC_POINTER,
-+ VCHI_VEC_HANDLE,
-+ VCHI_VEC_LIST
-+} VCHI_MSG_VECTOR_TYPE_T;
-+
-+typedef struct vchi_msg_vector_ex {
-+
-+ VCHI_MSG_VECTOR_TYPE_T type;
-+ union
-+ {
-+ // a memory handle
-+ struct
-+ {
-+ VCHI_MEM_HANDLE_T handle;
-+ uint32_t offset;
-+ int32_t vec_len;
-+ } handle;
-+
-+ // an ordinary data pointer
-+ struct
-+ {
-+ const void *vec_base;
-+ int32_t vec_len;
-+ } ptr;
-+
-+ // a nested vector list
-+ struct
-+ {
-+ struct vchi_msg_vector_ex *vec;
-+ uint32_t vec_len;
-+ } list;
-+ } u;
-+} VCHI_MSG_VECTOR_EX_T;
-+
-+
-+// Construct an entry in a msg vector for a pointer (p) of length (l)
-+#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } }
-+
-+// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l)
-+#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } }
-+
-+// Macros to manipulate 'FOURCC' values
-+#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] ))
-+#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF
-+
-+
-+// Opaque service information
-+struct opaque_vchi_service_t;
-+
-+// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold,
-+// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only.
-+typedef struct
-+{
-+ struct opaque_vchi_service_t *service;
-+ void *message;
-+} VCHI_HELD_MSG_T;
-+
-+
-+
-+// structure used to provide the information needed to open a server or a client
-+typedef struct {
-+ struct vchi_version version;
-+ int32_t service_id;
-+ VCHI_CONNECTION_T *connection;
-+ uint32_t rx_fifo_size;
-+ uint32_t tx_fifo_size;
-+ VCHI_CALLBACK_T callback;
-+ void *callback_param;
-+ /* client intends to receive bulk transfers of
-+ odd lengths or into unaligned buffers */
-+ int32_t want_unaligned_bulk_rx;
-+ /* client intends to transmit bulk transfers of
-+ odd lengths or out of unaligned buffers */
-+ int32_t want_unaligned_bulk_tx;
-+ /* client wants to check CRCs on (bulk) xfers.
-+ Only needs to be set at 1 end - will do both directions. */
-+ int32_t want_crc;
-+} SERVICE_CREATION_T;
-+
-+// Opaque handle for a VCHI instance
-+typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T;
-+
-+// Opaque handle for a server or client
-+typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T;
-+
-+// Service registration & startup
-+typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections);
-+
-+typedef struct service_info_tag {
-+ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */
-+ VCHI_SERVICE_INIT init; /* Service initialisation function */
-+ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */
-+} SERVICE_INFO_T;
-+
-+/******************************************************************************
-+ Global funcs - implementation is specific to which side you are on (local / remote)
-+ *****************************************************************************/
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table,
-+ const VCHI_MESSAGE_DRIVER_T * low_level);
-+
-+
-+// Routine used to initialise the vchi on both local + remote connections
-+extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle );
-+
-+extern int32_t vchi_exit( void );
-+
-+extern int32_t vchi_connect( VCHI_CONNECTION_T **connections,
-+ const uint32_t num_connections,
-+ VCHI_INSTANCE_T instance_handle );
-+
-+//When this is called, ensure that all services have no data pending.
-+//Bulk transfers can remain 'queued'
-+extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle );
-+
-+// Global control over bulk CRC checking
-+extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection,
-+ VCHI_CRC_CONTROL_T control );
-+
-+// helper functions
-+extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length);
-+extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address);
-+extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle);
-+
-+
-+/******************************************************************************
-+ Global service API
-+ *****************************************************************************/
-+// Routine to create a named service
-+extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle );
-+
-+// Routine to destory a service
-+extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to open a named service
-+extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle);
-+
-+extern int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle,
-+ short *peer_version );
-+
-+// Routine to close a named service
-+extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to increment ref count on a named service
-+extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to decrement ref count on a named service
-+extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to set a control option for a named service
-+extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_SERVICE_OPTION_T option,
-+ int value);
-+
-+// Routine to send a message across a service
-+extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle,
-+ const void *data,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// scatter-gather (vector) and send message
-+int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_VECTOR_EX_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// legacy scatter-gather (vector) and send message, only handles pointers
-+int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_VECTOR_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// Routine to receive a msg from a service
-+// Dequeue is equivalent to hold, copy into client buffer, release
-+extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle,
-+ void *data,
-+ uint32_t max_data_size_to_read,
-+ uint32_t *actual_msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to look at a message in place.
-+// The message is not dequeued, so a subsequent call to peek or dequeue
-+// will return the same message.
-+extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to remove a message after it has been read in place with peek
-+// The first message on the queue is dequeued.
-+extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to look at a message in place.
-+// The message is dequeued, so the caller is left holding it; the descriptor is
-+// filled in and must be released when the user has finished with the message.
-+extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle,
-+ void **data, // } may be NULL, as info can be
-+ uint32_t *msg_size, // } obtained from HELD_MSG_T
-+ VCHI_FLAGS_T flags,
-+ VCHI_HELD_MSG_T *message_descriptor );
-+
-+// Initialise an iterator to look through messages in place
-+extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_ITER_T *iter,
-+ VCHI_FLAGS_T flags );
-+
-+/******************************************************************************
-+ Global service support API - operations on held messages and message iterators
-+ *****************************************************************************/
-+
-+// Routine to get the address of a held message
-+extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to get the size of a held message
-+extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to get the transmit timestamp as written into the header by the peer
-+extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to get the reception timestamp, written as we parsed the header
-+extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to release a held message after it has been processed
-+extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message );
-+
-+// Indicates whether the iterator has a next message.
-+extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter );
-+
-+// Return the pointer and length for the next message and advance the iterator.
-+extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter,
-+ void **data,
-+ uint32_t *msg_size );
-+
-+// Remove the last message returned by vchi_msg_iter_next.
-+// Can only be called once after each call to vchi_msg_iter_next.
-+extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter );
-+
-+// Hold the last message returned by vchi_msg_iter_next.
-+// Can only be called once after each call to vchi_msg_iter_next.
-+extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter,
-+ VCHI_HELD_MSG_T *message );
-+
-+// Return information for the next message, and hold it, advancing the iterator.
-+extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter,
-+ void **data, // } may be NULL
-+ uint32_t *msg_size, // }
-+ VCHI_HELD_MSG_T *message );
-+
-+
-+/******************************************************************************
-+ Global bulk API
-+ *****************************************************************************/
-+
-+// Routine to prepare interface for a transfer from the other side
-+extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle,
-+ void *data_dst,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *transfer_handle );
-+
-+
-+// Prepare interface for a transfer from the other side into relocatable memory.
-+int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T h_dst,
-+ uint32_t offset,
-+ uint32_t data_size,
-+ const VCHI_FLAGS_T flags,
-+ void * const bulk_handle );
-+
-+// Routine to queue up data ready for transfer to the other (once they have signalled they are ready)
-+extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle,
-+ const void *data_src,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *transfer_handle );
-+
-+
-+/******************************************************************************
-+ Configuration plumbing
-+ *****************************************************************************/
-+
-+// function prototypes for the different mid layers (the state info gives the different physical connections)
-+extern const VCHI_CONNECTION_API_T *single_get_func_table( void );
-+//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void );
-+//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void );
-+
-+// declare all message drivers here
-+const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void );
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T h_src,
-+ uint32_t offset,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *transfer_handle );
-+#endif /* VCHI_H_ */
-+
-+/****************************** End of file **********************************/
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_mh.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,42 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_MH_H_
-+#define VCHI_MH_H_
-+
-+#include <linux/types.h>
-+
-+typedef int32_t VCHI_MEM_HANDLE_T;
-+#define VCHI_MEM_HANDLE_INVALID 0
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,562 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/pagemap.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/version.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <asm/pgtable.h>
-+
-+#include <mach/irqs.h>
-+
-+#include <mach/platform.h>
-+#include <mach/vcio.h>
-+
-+#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32)
-+
-+#define VCHIQ_DOORBELL_IRQ IRQ_ARM_DOORBELL_0
-+#define VCHIQ_ARM_ADDRESS(x) ((void *)__virt_to_bus((unsigned)x))
-+
-+#include "vchiq_arm.h"
-+#include "vchiq_2835.h"
-+#include "vchiq_connected.h"
-+#include "vchiq_killable.h"
-+
-+#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2)
-+
-+typedef struct vchiq_2835_state_struct {
-+ int inited;
-+ VCHIQ_ARM_STATE_T arm_state;
-+} VCHIQ_2835_ARM_STATE_T;
-+
-+static char *g_slot_mem;
-+static int g_slot_mem_size;
-+dma_addr_t g_slot_phys;
-+static FRAGMENTS_T *g_fragments_base;
-+static FRAGMENTS_T *g_free_fragments;
-+struct semaphore g_free_fragments_sema;
-+
-+extern int vchiq_arm_log_level;
-+
-+static DEFINE_SEMAPHORE(g_free_fragments_mutex);
-+
-+static irqreturn_t
-+vchiq_doorbell_irq(int irq, void *dev_id);
-+
-+static int
-+create_pagelist(char __user *buf, size_t count, unsigned short type,
-+ struct task_struct *task, PAGELIST_T ** ppagelist);
-+
-+static void
-+free_pagelist(PAGELIST_T *pagelist, int actual);
-+
-+int __init
-+vchiq_platform_init(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero;
-+ int frag_mem_size;
-+ int err;
-+ int i;
-+
-+ /* Allocate space for the channels in coherent memory */
-+ g_slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE);
-+ frag_mem_size = PAGE_ALIGN(sizeof(FRAGMENTS_T) * MAX_FRAGMENTS);
-+
-+ g_slot_mem = dma_alloc_coherent(NULL, g_slot_mem_size + frag_mem_size,
-+ &g_slot_phys, GFP_ATOMIC);
-+
-+ if (!g_slot_mem) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to allocate channel memory");
-+ err = -ENOMEM;
-+ goto failed_alloc;
-+ }
-+
-+ WARN_ON(((int)g_slot_mem & (PAGE_SIZE - 1)) != 0);
-+
-+ vchiq_slot_zero = vchiq_init_slots(g_slot_mem, g_slot_mem_size);
-+ if (!vchiq_slot_zero) {
-+ err = -EINVAL;
-+ goto failed_init_slots;
-+ }
-+
-+ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] =
-+ (int)g_slot_phys + g_slot_mem_size;
-+ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] =
-+ MAX_FRAGMENTS;
-+
-+ g_fragments_base = (FRAGMENTS_T *)(g_slot_mem + g_slot_mem_size);
-+ g_slot_mem_size += frag_mem_size;
-+
-+ g_free_fragments = g_fragments_base;
-+ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) {
-+ *(FRAGMENTS_T **)&g_fragments_base[i] =
-+ &g_fragments_base[i + 1];
-+ }
-+ *(FRAGMENTS_T **)&g_fragments_base[i] = NULL;
-+ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS);
-+
-+ if (vchiq_init_state(state, vchiq_slot_zero, 0/*slave*/) !=
-+ VCHIQ_SUCCESS) {
-+ err = -EINVAL;
-+ goto failed_vchiq_init;
-+ }
-+
-+ err = request_irq(VCHIQ_DOORBELL_IRQ, vchiq_doorbell_irq,
-+ IRQF_IRQPOLL, "VCHIQ doorbell",
-+ state);
-+ if (err < 0) {
-+ vchiq_log_error(vchiq_arm_log_level, "%s: failed to register "
-+ "irq=%d err=%d", __func__,
-+ VCHIQ_DOORBELL_IRQ, err);
-+ goto failed_request_irq;
-+ }
-+
-+ /* Send the base address of the slots to VideoCore */
-+
-+ dsb(); /* Ensure all writes have completed */
-+
-+ bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)g_slot_phys);
-+
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "vchiq_init - done (slots %x, phys %x)",
-+ (unsigned int)vchiq_slot_zero, g_slot_phys);
-+
-+ vchiq_call_connected_callbacks();
-+
-+ return 0;
-+
-+failed_request_irq:
-+failed_vchiq_init:
-+failed_init_slots:
-+ dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys);
-+
-+failed_alloc:
-+ return err;
-+}
-+
-+void __exit
-+vchiq_platform_exit(VCHIQ_STATE_T *state)
-+{
-+ free_irq(VCHIQ_DOORBELL_IRQ, state);
-+ dma_free_coherent(NULL, g_slot_mem_size,
-+ g_slot_mem, g_slot_phys);
-+}
-+
-+
-+VCHIQ_STATUS_T
-+vchiq_platform_init_state(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL);
-+ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1;
-+ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state);
-+ if(status != VCHIQ_SUCCESS)
-+ {
-+ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0;
-+ }
-+ return status;
-+}
-+
-+VCHIQ_ARM_STATE_T*
-+vchiq_platform_get_arm_state(VCHIQ_STATE_T *state)
-+{
-+ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited)
-+ {
-+ BUG();
-+ }
-+ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state;
-+}
-+
-+void
-+remote_event_signal(REMOTE_EVENT_T *event)
-+{
-+ wmb();
-+
-+ event->fired = 1;
-+
-+ dsb(); /* data barrier operation */
-+
-+ if (event->armed) {
-+ /* trigger vc interrupt */
-+
-+ writel(0, __io_address(ARM_0_BELL2));
-+ }
-+}
-+
-+int
-+vchiq_copy_from_user(void *dst, const void *src, int size)
-+{
-+ if ((uint32_t)src < TASK_SIZE) {
-+ return copy_from_user(dst, src, size);
-+ } else {
-+ memcpy(dst, src, size);
-+ return 0;
-+ }
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle,
-+ void *offset, int size, int dir)
-+{
-+ PAGELIST_T *pagelist;
-+ int ret;
-+
-+ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID);
-+
-+ ret = create_pagelist((char __user *)offset, size,
-+ (dir == VCHIQ_BULK_RECEIVE)
-+ ? PAGELIST_READ
-+ : PAGELIST_WRITE,
-+ current,
-+ &pagelist);
-+ if (ret != 0)
-+ return VCHIQ_ERROR;
-+
-+ bulk->handle = memhandle;
-+ bulk->data = VCHIQ_ARM_ADDRESS(pagelist);
-+
-+ /* Store the pagelist address in remote_data, which isn't used by the
-+ slave. */
-+ bulk->remote_data = pagelist;
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+void
-+vchiq_complete_bulk(VCHIQ_BULK_T *bulk)
-+{
-+ if (bulk && bulk->remote_data && bulk->actual)
-+ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual);
-+}
-+
-+void
-+vchiq_transfer_bulk(VCHIQ_BULK_T *bulk)
-+{
-+ /*
-+ * This should only be called on the master (VideoCore) side, but
-+ * provide an implementation to avoid the need for ifdefery.
-+ */
-+ BUG();
-+}
-+
-+void
-+vchiq_dump_platform_state(void *dump_context)
-+{
-+ char buf[80];
-+ int len;
-+ len = snprintf(buf, sizeof(buf),
-+ " Platform: 2835 (VC master)");
-+ vchiq_dump(dump_context, buf, len + 1);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_platform_suspend(VCHIQ_STATE_T *state)
-+{
-+ return VCHIQ_ERROR;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_platform_resume(VCHIQ_STATE_T *state)
-+{
-+ return VCHIQ_SUCCESS;
-+}
-+
-+void
-+vchiq_platform_paused(VCHIQ_STATE_T *state)
-+{
-+}
-+
-+void
-+vchiq_platform_resumed(VCHIQ_STATE_T *state)
-+{
-+}
-+
-+int
-+vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state)
-+{
-+ return 1; // autosuspend not supported - videocore always wanted
-+}
-+
-+int
-+vchiq_platform_use_suspend_timer(void)
-+{
-+ return 0;
-+}
-+void
-+vchiq_dump_platform_use_state(VCHIQ_STATE_T *state)
-+{
-+ vchiq_log_info((vchiq_arm_log_level>=VCHIQ_LOG_INFO),"Suspend timer not in use");
-+}
-+void
-+vchiq_platform_handle_timeout(VCHIQ_STATE_T *state)
-+{
-+ (void)state;
-+}
-+/*
-+ * Local functions
-+ */
-+
-+static irqreturn_t
-+vchiq_doorbell_irq(int irq, void *dev_id)
-+{
-+ VCHIQ_STATE_T *state = dev_id;
-+ irqreturn_t ret = IRQ_NONE;
-+ unsigned int status;
-+
-+ /* Read (and clear) the doorbell */
-+ status = readl(__io_address(ARM_0_BELL0));
-+
-+ if (status & 0x4) { /* Was the doorbell rung? */
-+ remote_event_pollall(state);
-+ ret = IRQ_HANDLED;
-+ }
-+
-+ return ret;
-+}
-+
-+/* There is a potential problem with partial cache lines (pages?)
-+** at the ends of the block when reading. If the CPU accessed anything in
-+** the same line (page?) then it may have pulled old data into the cache,
-+** obscuring the new data underneath. We can solve this by transferring the
-+** partial cache lines separately, and allowing the ARM to copy into the
-+** cached area.
-+
-+** N.B. This implementation plays slightly fast and loose with the Linux
-+** driver programming rules, e.g. its use of __virt_to_bus instead of
-+** dma_map_single, but it isn't a multi-platform driver and it benefits
-+** from increased speed as a result.
-+*/
-+
-+static int
-+create_pagelist(char __user *buf, size_t count, unsigned short type,
-+ struct task_struct *task, PAGELIST_T ** ppagelist)
-+{
-+ PAGELIST_T *pagelist;
-+ struct page **pages;
-+ struct page *page;
-+ unsigned long *addrs;
-+ unsigned int num_pages, offset, i;
-+ char *addr, *base_addr, *next_addr;
-+ int run, addridx, actual_pages;
-+ unsigned long *need_release;
-+
-+ offset = (unsigned int)buf & (PAGE_SIZE - 1);
-+ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE;
-+
-+ *ppagelist = NULL;
-+
-+ /* Allocate enough storage to hold the page pointers and the page
-+ ** list
-+ */
-+ pagelist = kmalloc(sizeof(PAGELIST_T) +
-+ (num_pages * sizeof(unsigned long)) +
-+ sizeof(unsigned long) +
-+ (num_pages * sizeof(pages[0])),
-+ GFP_KERNEL);
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "create_pagelist - %x", (unsigned int)pagelist);
-+ if (!pagelist)
-+ return -ENOMEM;
-+
-+ addrs = pagelist->addrs;
-+ need_release = (unsigned long *)(addrs + num_pages);
-+ pages = (struct page **)(addrs + num_pages + 1);
-+
-+ if (is_vmalloc_addr(buf)) {
-+ for (actual_pages = 0; actual_pages < num_pages; actual_pages++) {
-+ pages[actual_pages] = vmalloc_to_page(buf + (actual_pages * PAGE_SIZE));
-+ }
-+ *need_release = 0; /* do not try and release vmalloc pages */
-+ } else {
-+ down_read(&task->mm->mmap_sem);
-+ actual_pages = get_user_pages(task, task->mm,
-+ (unsigned long)buf & ~(PAGE_SIZE - 1),
-+ num_pages,
-+ (type == PAGELIST_READ) /*Write */ ,
-+ 0 /*Force */ ,
-+ pages,
-+ NULL /*vmas */);
-+ up_read(&task->mm->mmap_sem);
-+
-+ if (actual_pages != num_pages) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "create_pagelist - only %d/%d pages locked",
-+ actual_pages,
-+ num_pages);
-+
-+ /* This is probably due to the process being killed */
-+ while (actual_pages > 0)
-+ {
-+ actual_pages--;
-+ page_cache_release(pages[actual_pages]);
-+ }
-+ kfree(pagelist);
-+ if (actual_pages == 0)
-+ actual_pages = -ENOMEM;
-+ return actual_pages;
-+ }
-+ *need_release = 1; /* release user pages */
-+ }
-+
-+ pagelist->length = count;
-+ pagelist->type = type;
-+ pagelist->offset = offset;
-+
-+ /* Group the pages into runs of contiguous pages */
-+
-+ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0]));
-+ next_addr = base_addr + PAGE_SIZE;
-+ addridx = 0;
-+ run = 0;
-+
-+ for (i = 1; i < num_pages; i++) {
-+ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i]));
-+ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) {
-+ next_addr += PAGE_SIZE;
-+ run++;
-+ } else {
-+ addrs[addridx] = (unsigned long)base_addr + run;
-+ addridx++;
-+ base_addr = addr;
-+ next_addr = addr + PAGE_SIZE;
-+ run = 0;
-+ }
-+ }
-+
-+ addrs[addridx] = (unsigned long)base_addr + run;
-+ addridx++;
-+
-+ /* Partial cache lines (fragments) require special measures */
-+ if ((type == PAGELIST_READ) &&
-+ ((pagelist->offset & (CACHE_LINE_SIZE - 1)) ||
-+ ((pagelist->offset + pagelist->length) &
-+ (CACHE_LINE_SIZE - 1)))) {
-+ FRAGMENTS_T *fragments;
-+
-+ if (down_interruptible(&g_free_fragments_sema) != 0) {
-+ kfree(pagelist);
-+ return -EINTR;
-+ }
-+
-+ WARN_ON(g_free_fragments == NULL);
-+
-+ down(&g_free_fragments_mutex);
-+ fragments = (FRAGMENTS_T *) g_free_fragments;
-+ WARN_ON(fragments == NULL);
-+ g_free_fragments = *(FRAGMENTS_T **) g_free_fragments;
-+ up(&g_free_fragments_mutex);
-+ pagelist->type =
-+ PAGELIST_READ_WITH_FRAGMENTS + (fragments -
-+ g_fragments_base);
-+ }
-+
-+ for (page = virt_to_page(pagelist);
-+ page <= virt_to_page(addrs + num_pages - 1); page++) {
-+ flush_dcache_page(page);
-+ }
-+
-+ *ppagelist = pagelist;
-+
-+ return 0;
-+}
-+
-+static void
-+free_pagelist(PAGELIST_T *pagelist, int actual)
-+{
-+ unsigned long *need_release;
-+ struct page **pages;
-+ unsigned int num_pages, i;
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "free_pagelist - %x, %d", (unsigned int)pagelist, actual);
-+
-+ num_pages =
-+ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) /
-+ PAGE_SIZE;
-+
-+ need_release = (unsigned long *)(pagelist->addrs + num_pages);
-+ pages = (struct page **)(pagelist->addrs + num_pages + 1);
-+
-+ /* Deal with any partial cache lines (fragments) */
-+ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) {
-+ FRAGMENTS_T *fragments = g_fragments_base +
-+ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS);
-+ int head_bytes, tail_bytes;
-+ head_bytes = (CACHE_LINE_SIZE - pagelist->offset) &
-+ (CACHE_LINE_SIZE - 1);
-+ tail_bytes = (pagelist->offset + actual) &
-+ (CACHE_LINE_SIZE - 1);
-+
-+ if ((actual >= 0) && (head_bytes != 0)) {
-+ if (head_bytes > actual)
-+ head_bytes = actual;
-+
-+ memcpy((char *)page_address(pages[0]) +
-+ pagelist->offset,
-+ fragments->headbuf,
-+ head_bytes);
-+ }
-+ if ((actual >= 0) && (head_bytes < actual) &&
-+ (tail_bytes != 0)) {
-+ memcpy((char *)page_address(pages[num_pages - 1]) +
-+ ((pagelist->offset + actual) &
-+ (PAGE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1)),
-+ fragments->tailbuf, tail_bytes);
-+ }
-+
-+ down(&g_free_fragments_mutex);
-+ *(FRAGMENTS_T **) fragments = g_free_fragments;
-+ g_free_fragments = fragments;
-+ up(&g_free_fragments_mutex);
-+ up(&g_free_fragments_sema);
-+ }
-+
-+ if (*need_release) {
-+ for (i = 0; i < num_pages; i++) {
-+ if (pagelist->type != PAGELIST_WRITE)
-+ set_page_dirty(pages[i]);
-+
-+ page_cache_release(pages[i]);
-+ }
-+ }
-+
-+ kfree(pagelist);
-+}
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,42 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_2835_H
-+#define VCHIQ_2835_H
-+
-+#include "vchiq_pagelist.h"
-+
-+#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0
-+#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1
-+
-+#endif /* VCHIQ_2835_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,2884 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/cdev.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/mm.h>
-+#include <linux/highmem.h>
-+#include <linux/pagemap.h>
-+#include <linux/bug.h>
-+#include <linux/semaphore.h>
-+#include <linux/list.h>
-+
-+#include "vchiq_core.h"
-+#include "vchiq_ioctl.h"
-+#include "vchiq_arm.h"
-+#include "vchiq_killable.h"
-+#include "vchiq_debugfs.h"
-+
-+#define DEVICE_NAME "vchiq"
-+
-+/* Override the default prefix, which would be vchiq_arm (from the filename) */
-+#undef MODULE_PARAM_PREFIX
-+#define MODULE_PARAM_PREFIX DEVICE_NAME "."
-+
-+#define VCHIQ_MINOR 0
-+
-+/* Some per-instance constants */
-+#define MAX_COMPLETIONS 16
-+#define MAX_SERVICES 64
-+#define MAX_ELEMENTS 8
-+#define MSG_QUEUE_SIZE 64
-+
-+#define KEEPALIVE_VER 1
-+#define KEEPALIVE_VER_MIN KEEPALIVE_VER
-+
-+/* Run time control of log level, based on KERN_XXX level. */
-+int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT;
-+int vchiq_susp_log_level = VCHIQ_LOG_ERROR;
-+
-+#define SUSPEND_TIMER_TIMEOUT_MS 100
-+#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000
-+
-+#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */
-+static const char *const suspend_state_names[] = {
-+ "VC_SUSPEND_FORCE_CANCELED",
-+ "VC_SUSPEND_REJECTED",
-+ "VC_SUSPEND_FAILED",
-+ "VC_SUSPEND_IDLE",
-+ "VC_SUSPEND_REQUESTED",
-+ "VC_SUSPEND_IN_PROGRESS",
-+ "VC_SUSPEND_SUSPENDED"
-+};
-+#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */
-+static const char *const resume_state_names[] = {
-+ "VC_RESUME_FAILED",
-+ "VC_RESUME_IDLE",
-+ "VC_RESUME_REQUESTED",
-+ "VC_RESUME_IN_PROGRESS",
-+ "VC_RESUME_RESUMED"
-+};
-+/* The number of times we allow force suspend to timeout before actually
-+** _forcing_ suspend. This is to cater for SW which fails to release vchiq
-+** correctly - we don't want to prevent ARM suspend indefinitely in this case.
-+*/
-+#define FORCE_SUSPEND_FAIL_MAX 8
-+
-+/* The time in ms allowed for videocore to go idle when force suspend has been
-+ * requested */
-+#define FORCE_SUSPEND_TIMEOUT_MS 200
-+
-+
-+static void suspend_timer_callback(unsigned long context);
-+
-+
-+typedef struct user_service_struct {
-+ VCHIQ_SERVICE_T *service;
-+ void *userdata;
-+ VCHIQ_INSTANCE_T instance;
-+ char is_vchi;
-+ char dequeue_pending;
-+ char close_pending;
-+ int message_available_pos;
-+ int msg_insert;
-+ int msg_remove;
-+ struct semaphore insert_event;
-+ struct semaphore remove_event;
-+ struct semaphore close_event;
-+ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE];
-+} USER_SERVICE_T;
-+
-+struct bulk_waiter_node {
-+ struct bulk_waiter bulk_waiter;
-+ int pid;
-+ struct list_head list;
-+};
-+
-+struct vchiq_instance_struct {
-+ VCHIQ_STATE_T *state;
-+ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS];
-+ int completion_insert;
-+ int completion_remove;
-+ struct semaphore insert_event;
-+ struct semaphore remove_event;
-+ struct mutex completion_mutex;
-+
-+ int connected;
-+ int closing;
-+ int pid;
-+ int mark;
-+ int use_close_delivered;
-+ int trace;
-+
-+ struct list_head bulk_waiter_list;
-+ struct mutex bulk_waiter_list_mutex;
-+
-+ VCHIQ_DEBUGFS_NODE_T debugfs_node;
-+};
-+
-+typedef struct dump_context_struct {
-+ char __user *buf;
-+ size_t actual;
-+ size_t space;
-+ loff_t offset;
-+} DUMP_CONTEXT_T;
-+
-+static struct cdev vchiq_cdev;
-+static dev_t vchiq_devid;
-+static VCHIQ_STATE_T g_state;
-+static struct class *vchiq_class;
-+static struct device *vchiq_dev;
-+static DEFINE_SPINLOCK(msg_queue_spinlock);
-+
-+static const char *const ioctl_names[] = {
-+ "CONNECT",
-+ "SHUTDOWN",
-+ "CREATE_SERVICE",
-+ "REMOVE_SERVICE",
-+ "QUEUE_MESSAGE",
-+ "QUEUE_BULK_TRANSMIT",
-+ "QUEUE_BULK_RECEIVE",
-+ "AWAIT_COMPLETION",
-+ "DEQUEUE_MESSAGE",
-+ "GET_CLIENT_ID",
-+ "GET_CONFIG",
-+ "CLOSE_SERVICE",
-+ "USE_SERVICE",
-+ "RELEASE_SERVICE",
-+ "SET_SERVICE_OPTION",
-+ "DUMP_PHYS_MEM",
-+ "LIB_VERSION",
-+ "CLOSE_DELIVERED"
-+};
-+
-+vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) ==
-+ (VCHIQ_IOC_MAX + 1));
-+
-+static void
-+dump_phys_mem(void *virt_addr, uint32_t num_bytes);
-+
-+/****************************************************************************
-+*
-+* add_completion
-+*
-+***************************************************************************/
-+
-+static VCHIQ_STATUS_T
-+add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service,
-+ void *bulk_userdata)
-+{
-+ VCHIQ_COMPLETION_DATA_T *completion;
-+ DEBUG_INITIALISE(g_state.local)
-+
-+ while (instance->completion_insert ==
-+ (instance->completion_remove + MAX_COMPLETIONS)) {
-+ /* Out of space - wait for the client */
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "add_completion - completion queue full");
-+ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT);
-+ if (down_interruptible(&instance->remove_event) != 0) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback interrupted");
-+ return VCHIQ_RETRY;
-+ } else if (instance->closing) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback closing");
-+ return VCHIQ_ERROR;
-+ }
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ }
-+
-+ completion =
-+ &instance->completions[instance->completion_insert &
-+ (MAX_COMPLETIONS - 1)];
-+
-+ completion->header = header;
-+ completion->reason = reason;
-+ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */
-+ completion->service_userdata = user_service->service;
-+ completion->bulk_userdata = bulk_userdata;
-+
-+ if (reason == VCHIQ_SERVICE_CLOSED) {
-+ /* Take an extra reference, to be held until
-+ this CLOSED notification is delivered. */
-+ lock_service(user_service->service);
-+ if (instance->use_close_delivered)
-+ user_service->close_pending = 1;
-+ }
-+
-+ /* A write barrier is needed here to ensure that the entire completion
-+ record is written out before the insert point. */
-+ wmb();
-+
-+ if (reason == VCHIQ_MESSAGE_AVAILABLE)
-+ user_service->message_available_pos =
-+ instance->completion_insert;
-+ instance->completion_insert++;
-+
-+ up(&instance->insert_event);
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+/****************************************************************************
-+*
-+* service_callback
-+*
-+***************************************************************************/
-+
-+static VCHIQ_STATUS_T
-+service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header,
-+ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata)
-+{
-+ /* How do we ensure the callback goes to the right client?
-+ ** The service_user data points to a USER_SERVICE_T record containing
-+ ** the original callback and the user state structure, which contains a
-+ ** circular buffer for completion records.
-+ */
-+ USER_SERVICE_T *user_service;
-+ VCHIQ_SERVICE_T *service;
-+ VCHIQ_INSTANCE_T instance;
-+ DEBUG_INITIALISE(g_state.local)
-+
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+
-+ service = handle_to_service(handle);
-+ BUG_ON(!service);
-+ user_service = (USER_SERVICE_T *)service->base.userdata;
-+ instance = user_service->instance;
-+
-+ if (!instance || instance->closing)
-+ return VCHIQ_SUCCESS;
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "service_callback - service %lx(%d,%p), reason %d, header %lx, "
-+ "instance %lx, bulk_userdata %lx",
-+ (unsigned long)user_service,
-+ service->localport, user_service->userdata,
-+ reason, (unsigned long)header,
-+ (unsigned long)instance, (unsigned long)bulk_userdata);
-+
-+ if (header && user_service->is_vchi) {
-+ spin_lock(&msg_queue_spinlock);
-+ while (user_service->msg_insert ==
-+ (user_service->msg_remove + MSG_QUEUE_SIZE)) {
-+ spin_unlock(&msg_queue_spinlock);
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT);
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "service_callback - msg queue full");
-+ /* If there is no MESSAGE_AVAILABLE in the completion
-+ ** queue, add one
-+ */
-+ if ((user_service->message_available_pos -
-+ instance->completion_remove) < 0) {
-+ VCHIQ_STATUS_T status;
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "Inserting extra MESSAGE_AVAILABLE");
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ status = add_completion(instance, reason,
-+ NULL, user_service, bulk_userdata);
-+ if (status != VCHIQ_SUCCESS) {
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ return status;
-+ }
-+ }
-+
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ if (down_interruptible(&user_service->remove_event)
-+ != 0) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback interrupted");
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ return VCHIQ_RETRY;
-+ } else if (instance->closing) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback closing");
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ return VCHIQ_ERROR;
-+ }
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ spin_lock(&msg_queue_spinlock);
-+ }
-+
-+ user_service->msg_queue[user_service->msg_insert &
-+ (MSG_QUEUE_SIZE - 1)] = header;
-+ user_service->msg_insert++;
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ up(&user_service->insert_event);
-+
-+ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if
-+ ** there is a MESSAGE_AVAILABLE in the completion queue then
-+ ** bypass the completion queue.
-+ */
-+ if (((user_service->message_available_pos -
-+ instance->completion_remove) >= 0) ||
-+ user_service->dequeue_pending) {
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ user_service->dequeue_pending = 0;
-+ return VCHIQ_SUCCESS;
-+ }
-+
-+ header = NULL;
-+ }
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+
-+ return add_completion(instance, reason, header, user_service,
-+ bulk_userdata);
-+}
-+
-+/****************************************************************************
-+*
-+* user_service_free
-+*
-+***************************************************************************/
-+static void
-+user_service_free(void *userdata)
-+{
-+ kfree(userdata);
-+}
-+
-+/****************************************************************************
-+*
-+* close_delivered
-+*
-+***************************************************************************/
-+static void close_delivered(USER_SERVICE_T *user_service)
-+{
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "close_delivered(handle=%x)",
-+ user_service->service->handle);
-+
-+ if (user_service->close_pending) {
-+ /* Allow the underlying service to be culled */
-+ unlock_service(user_service->service);
-+
-+ /* Wake the user-thread blocked in close_ or remove_service */
-+ up(&user_service->close_event);
-+
-+ user_service->close_pending = 0;
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_ioctl
-+*
-+***************************************************************************/
-+static long
-+vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ VCHIQ_INSTANCE_T instance = file->private_data;
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ VCHIQ_SERVICE_T *service = NULL;
-+ long ret = 0;
-+ int i, rc;
-+ DEBUG_INITIALISE(g_state.local)
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "vchiq_ioctl - instance %x, cmd %s, arg %lx",
-+ (unsigned int)instance,
-+ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) &&
-+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ?
-+ ioctl_names[_IOC_NR(cmd)] : "<invalid>", arg);
-+
-+ switch (cmd) {
-+ case VCHIQ_IOC_SHUTDOWN:
-+ if (!instance->connected)
-+ break;
-+
-+ /* Remove all services */
-+ i = 0;
-+ while ((service = next_service_by_instance(instance->state,
-+ instance, &i)) != NULL) {
-+ status = vchiq_remove_service(service->handle);
-+ unlock_service(service);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+ service = NULL;
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ /* Wake the completion thread and ask it to exit */
-+ instance->closing = 1;
-+ up(&instance->insert_event);
-+ }
-+
-+ break;
-+
-+ case VCHIQ_IOC_CONNECT:
-+ if (instance->connected) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+ rc = mutex_lock_interruptible(&instance->state->mutex);
-+ if (rc != 0) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "vchiq: connect: could not lock mutex for "
-+ "state %d: %d",
-+ instance->state->id, rc);
-+ ret = -EINTR;
-+ break;
-+ }
-+ status = vchiq_connect_internal(instance->state, instance);
-+ mutex_unlock(&instance->state->mutex);
-+
-+ if (status == VCHIQ_SUCCESS)
-+ instance->connected = 1;
-+ else
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "vchiq: could not connect: %d", status);
-+ break;
-+
-+ case VCHIQ_IOC_CREATE_SERVICE: {
-+ VCHIQ_CREATE_SERVICE_T args;
-+ USER_SERVICE_T *user_service = NULL;
-+ void *userdata;
-+ int srvstate;
-+
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL);
-+ if (!user_service) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+
-+ if (args.is_open) {
-+ if (!instance->connected) {
-+ ret = -ENOTCONN;
-+ kfree(user_service);
-+ break;
-+ }
-+ srvstate = VCHIQ_SRVSTATE_OPENING;
-+ } else {
-+ srvstate =
-+ instance->connected ?
-+ VCHIQ_SRVSTATE_LISTENING :
-+ VCHIQ_SRVSTATE_HIDDEN;
-+ }
-+
-+ userdata = args.params.userdata;
-+ args.params.callback = service_callback;
-+ args.params.userdata = user_service;
-+ service = vchiq_add_service_internal(
-+ instance->state,
-+ &args.params, srvstate,
-+ instance, user_service_free);
-+
-+ if (service != NULL) {
-+ user_service->service = service;
-+ user_service->userdata = userdata;
-+ user_service->instance = instance;
-+ user_service->is_vchi = (args.is_vchi != 0);
-+ user_service->dequeue_pending = 0;
-+ user_service->close_pending = 0;
-+ user_service->message_available_pos =
-+ instance->completion_remove - 1;
-+ user_service->msg_insert = 0;
-+ user_service->msg_remove = 0;
-+ sema_init(&user_service->insert_event, 0);
-+ sema_init(&user_service->remove_event, 0);
-+ sema_init(&user_service->close_event, 0);
-+
-+ if (args.is_open) {
-+ status = vchiq_open_service_internal
-+ (service, instance->pid);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_remove_service(service->handle);
-+ service = NULL;
-+ ret = (status == VCHIQ_RETRY) ?
-+ -EINTR : -EIO;
-+ break;
-+ }
-+ }
-+
-+ if (copy_to_user((void __user *)
-+ &(((VCHIQ_CREATE_SERVICE_T __user *)
-+ arg)->handle),
-+ (const void *)&service->handle,
-+ sizeof(service->handle)) != 0) {
-+ ret = -EFAULT;
-+ vchiq_remove_service(service->handle);
-+ }
-+
-+ service = NULL;
-+ } else {
-+ ret = -EEXIST;
-+ kfree(user_service);
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_CLOSE_SERVICE: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ USER_SERVICE_T *user_service =
-+ (USER_SERVICE_T *)service->base.userdata;
-+ /* close_pending is false on first entry, and when the
-+ wait in vchiq_close_service has been interrupted. */
-+ if (!user_service->close_pending) {
-+ status = vchiq_close_service(service->handle);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+
-+ /* close_pending is true once the underlying service
-+ has been closed until the client library calls the
-+ CLOSE_DELIVERED ioctl, signalling close_event. */
-+ if (user_service->close_pending &&
-+ down_interruptible(&user_service->close_event))
-+ status = VCHIQ_RETRY;
-+ }
-+ else
-+ ret = -EINVAL;
-+ } break;
-+
-+ case VCHIQ_IOC_REMOVE_SERVICE: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ USER_SERVICE_T *user_service =
-+ (USER_SERVICE_T *)service->base.userdata;
-+ /* close_pending is false on first entry, and when the
-+ wait in vchiq_close_service has been interrupted. */
-+ if (!user_service->close_pending) {
-+ status = vchiq_remove_service(service->handle);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+
-+ /* close_pending is true once the underlying service
-+ has been closed until the client library calls the
-+ CLOSE_DELIVERED ioctl, signalling close_event. */
-+ if (user_service->close_pending &&
-+ down_interruptible(&user_service->close_event))
-+ status = VCHIQ_RETRY;
-+ }
-+ else
-+ ret = -EINVAL;
-+ } break;
-+
-+ case VCHIQ_IOC_USE_SERVICE:
-+ case VCHIQ_IOC_RELEASE_SERVICE: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ status = (cmd == VCHIQ_IOC_USE_SERVICE) ?
-+ vchiq_use_service_internal(service) :
-+ vchiq_release_service_internal(service);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s: cmd %s returned error %d for "
-+ "service %c%c%c%c:%03d",
-+ __func__,
-+ (cmd == VCHIQ_IOC_USE_SERVICE) ?
-+ "VCHIQ_IOC_USE_SERVICE" :
-+ "VCHIQ_IOC_RELEASE_SERVICE",
-+ status,
-+ VCHIQ_FOURCC_AS_4CHARS(
-+ service->base.fourcc),
-+ service->client_id);
-+ ret = -EINVAL;
-+ }
-+ } else
-+ ret = -EINVAL;
-+ } break;
-+
-+ case VCHIQ_IOC_QUEUE_MESSAGE: {
-+ VCHIQ_QUEUE_MESSAGE_T args;
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ service = find_service_for_instance(instance, args.handle);
-+
-+ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) {
-+ /* Copy elements into kernel space */
-+ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS];
-+ if (copy_from_user(elements, args.elements,
-+ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0)
-+ status = vchiq_queue_message
-+ (args.handle,
-+ elements, args.count);
-+ else
-+ ret = -EFAULT;
-+ } else {
-+ ret = -EINVAL;
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT:
-+ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: {
-+ VCHIQ_QUEUE_BULK_TRANSFER_T args;
-+ struct bulk_waiter_node *waiter = NULL;
-+ VCHIQ_BULK_DIR_T dir =
-+ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ?
-+ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE;
-+
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ service = find_service_for_instance(instance, args.handle);
-+ if (!service) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) {
-+ waiter = kzalloc(sizeof(struct bulk_waiter_node),
-+ GFP_KERNEL);
-+ if (!waiter) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+ args.userdata = &waiter->bulk_waiter;
-+ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) {
-+ struct list_head *pos;
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_for_each(pos, &instance->bulk_waiter_list) {
-+ if (list_entry(pos, struct bulk_waiter_node,
-+ list)->pid == current->pid) {
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ break;
-+ }
-+
-+ }
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+ if (!waiter) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "no bulk_waiter found for pid %d",
-+ current->pid);
-+ ret = -ESRCH;
-+ break;
-+ }
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "found bulk_waiter %x for pid %d",
-+ (unsigned int)waiter, current->pid);
-+ args.userdata = &waiter->bulk_waiter;
-+ }
-+ status = vchiq_bulk_transfer
-+ (args.handle,
-+ VCHI_MEM_HANDLE_INVALID,
-+ args.data, args.size,
-+ args.userdata, args.mode,
-+ dir);
-+ if (!waiter)
-+ break;
-+ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) ||
-+ !waiter->bulk_waiter.bulk) {
-+ if (waiter->bulk_waiter.bulk) {
-+ /* Cancel the signal when the transfer
-+ ** completes. */
-+ spin_lock(&bulk_waiter_spinlock);
-+ waiter->bulk_waiter.bulk->userdata = NULL;
-+ spin_unlock(&bulk_waiter_spinlock);
-+ }
-+ kfree(waiter);
-+ } else {
-+ const VCHIQ_BULK_MODE_T mode_waiting =
-+ VCHIQ_BULK_MODE_WAITING;
-+ waiter->pid = current->pid;
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_add(&waiter->list, &instance->bulk_waiter_list);
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "saved bulk_waiter %x for pid %d",
-+ (unsigned int)waiter, current->pid);
-+
-+ if (copy_to_user((void __user *)
-+ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *)
-+ arg)->mode),
-+ (const void *)&mode_waiting,
-+ sizeof(mode_waiting)) != 0)
-+ ret = -EFAULT;
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_AWAIT_COMPLETION: {
-+ VCHIQ_AWAIT_COMPLETION_T args;
-+
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ if (!instance->connected) {
-+ ret = -ENOTCONN;
-+ break;
-+ }
-+
-+ if (copy_from_user(&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ mutex_lock(&instance->completion_mutex);
-+
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ while ((instance->completion_remove ==
-+ instance->completion_insert)
-+ && !instance->closing) {
-+ int rc;
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ mutex_unlock(&instance->completion_mutex);
-+ rc = down_interruptible(&instance->insert_event);
-+ mutex_lock(&instance->completion_mutex);
-+ if (rc != 0) {
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "AWAIT_COMPLETION interrupted");
-+ ret = -EINTR;
-+ break;
-+ }
-+ }
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+
-+ /* A read memory barrier is needed to stop prefetch of a stale
-+ ** completion record
-+ */
-+ rmb();
-+
-+ if (ret == 0) {
-+ int msgbufcount = args.msgbufcount;
-+ for (ret = 0; ret < args.count; ret++) {
-+ VCHIQ_COMPLETION_DATA_T *completion;
-+ VCHIQ_SERVICE_T *service;
-+ USER_SERVICE_T *user_service;
-+ VCHIQ_HEADER_T *header;
-+ if (instance->completion_remove ==
-+ instance->completion_insert)
-+ break;
-+ completion = &instance->completions[
-+ instance->completion_remove &
-+ (MAX_COMPLETIONS - 1)];
-+
-+ service = completion->service_userdata;
-+ user_service = service->base.userdata;
-+ completion->service_userdata =
-+ user_service->userdata;
-+
-+ header = completion->header;
-+ if (header) {
-+ void __user *msgbuf;
-+ int msglen;
-+
-+ msglen = header->size +
-+ sizeof(VCHIQ_HEADER_T);
-+ /* This must be a VCHIQ-style service */
-+ if (args.msgbufsize < msglen) {
-+ vchiq_log_error(
-+ vchiq_arm_log_level,
-+ "header %x: msgbufsize"
-+ " %x < msglen %x",
-+ (unsigned int)header,
-+ args.msgbufsize,
-+ msglen);
-+ WARN(1, "invalid message "
-+ "size\n");
-+ if (ret == 0)
-+ ret = -EMSGSIZE;
-+ break;
-+ }
-+ if (msgbufcount <= 0)
-+ /* Stall here for lack of a
-+ ** buffer for the message. */
-+ break;
-+ /* Get the pointer from user space */
-+ msgbufcount--;
-+ if (copy_from_user(&msgbuf,
-+ (const void __user *)
-+ &args.msgbufs[msgbufcount],
-+ sizeof(msgbuf)) != 0) {
-+ if (ret == 0)
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ /* Copy the message to user space */
-+ if (copy_to_user(msgbuf, header,
-+ msglen) != 0) {
-+ if (ret == 0)
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ /* Now it has been copied, the message
-+ ** can be released. */
-+ vchiq_release_message(service->handle,
-+ header);
-+
-+ /* The completion must point to the
-+ ** msgbuf. */
-+ completion->header = msgbuf;
-+ }
-+
-+ if ((completion->reason ==
-+ VCHIQ_SERVICE_CLOSED) &&
-+ !instance->use_close_delivered)
-+ unlock_service(service);
-+
-+ if (copy_to_user((void __user *)(
-+ (size_t)args.buf +
-+ ret * sizeof(VCHIQ_COMPLETION_DATA_T)),
-+ completion,
-+ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) {
-+ if (ret == 0)
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ instance->completion_remove++;
-+ }
-+
-+ if (msgbufcount != args.msgbufcount) {
-+ if (copy_to_user((void __user *)
-+ &((VCHIQ_AWAIT_COMPLETION_T *)arg)->
-+ msgbufcount,
-+ &msgbufcount,
-+ sizeof(msgbufcount)) != 0) {
-+ ret = -EFAULT;
-+ }
-+ }
-+ }
-+
-+ if (ret != 0)
-+ up(&instance->remove_event);
-+ mutex_unlock(&instance->completion_mutex);
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ } break;
-+
-+ case VCHIQ_IOC_DEQUEUE_MESSAGE: {
-+ VCHIQ_DEQUEUE_MESSAGE_T args;
-+ USER_SERVICE_T *user_service;
-+ VCHIQ_HEADER_T *header;
-+
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ service = find_service_for_instance(instance, args.handle);
-+ if (!service) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+ user_service = (USER_SERVICE_T *)service->base.userdata;
-+ if (user_service->is_vchi == 0) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ spin_lock(&msg_queue_spinlock);
-+ if (user_service->msg_remove == user_service->msg_insert) {
-+ if (!args.blocking) {
-+ spin_unlock(&msg_queue_spinlock);
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ ret = -EWOULDBLOCK;
-+ break;
-+ }
-+ user_service->dequeue_pending = 1;
-+ do {
-+ spin_unlock(&msg_queue_spinlock);
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ if (down_interruptible(
-+ &user_service->insert_event) != 0) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "DEQUEUE_MESSAGE interrupted");
-+ ret = -EINTR;
-+ break;
-+ }
-+ spin_lock(&msg_queue_spinlock);
-+ } while (user_service->msg_remove ==
-+ user_service->msg_insert);
-+
-+ if (ret)
-+ break;
-+ }
-+
-+ BUG_ON((int)(user_service->msg_insert -
-+ user_service->msg_remove) < 0);
-+
-+ header = user_service->msg_queue[user_service->msg_remove &
-+ (MSG_QUEUE_SIZE - 1)];
-+ user_service->msg_remove++;
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ up(&user_service->remove_event);
-+ if (header == NULL)
-+ ret = -ENOTCONN;
-+ else if (header->size <= args.bufsize) {
-+ /* Copy to user space if msgbuf is not NULL */
-+ if ((args.buf == NULL) ||
-+ (copy_to_user((void __user *)args.buf,
-+ header->data,
-+ header->size) == 0)) {
-+ ret = header->size;
-+ vchiq_release_message(
-+ service->handle,
-+ header);
-+ } else
-+ ret = -EFAULT;
-+ } else {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "header %x: bufsize %x < size %x",
-+ (unsigned int)header, args.bufsize,
-+ header->size);
-+ WARN(1, "invalid size\n");
-+ ret = -EMSGSIZE;
-+ }
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ } break;
-+
-+ case VCHIQ_IOC_GET_CLIENT_ID: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ ret = vchiq_get_client_id(handle);
-+ } break;
-+
-+ case VCHIQ_IOC_GET_CONFIG: {
-+ VCHIQ_GET_CONFIG_T args;
-+ VCHIQ_CONFIG_T config;
-+
-+ if (copy_from_user(&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ if (args.config_size > sizeof(config)) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+ status = vchiq_get_config(instance, args.config_size, &config);
-+ if (status == VCHIQ_SUCCESS) {
-+ if (copy_to_user((void __user *)args.pconfig,
-+ &config, args.config_size) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_SET_SERVICE_OPTION: {
-+ VCHIQ_SET_SERVICE_OPTION_T args;
-+
-+ if (copy_from_user(
-+ &args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ service = find_service_for_instance(instance, args.handle);
-+ if (!service) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ status = vchiq_set_service_option(
-+ args.handle, args.option, args.value);
-+ } break;
-+
-+ case VCHIQ_IOC_DUMP_PHYS_MEM: {
-+ VCHIQ_DUMP_MEM_T args;
-+
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ dump_phys_mem(args.virt_addr, args.num_bytes);
-+ } break;
-+
-+ case VCHIQ_IOC_LIB_VERSION: {
-+ unsigned int lib_version = (unsigned int)arg;
-+
-+ if (lib_version < VCHIQ_VERSION_MIN)
-+ ret = -EINVAL;
-+ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED)
-+ instance->use_close_delivered = 1;
-+ } break;
-+
-+ case VCHIQ_IOC_CLOSE_DELIVERED: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_closed_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ USER_SERVICE_T *user_service =
-+ (USER_SERVICE_T *)service->base.userdata;
-+ close_delivered(user_service);
-+ }
-+ else
-+ ret = -EINVAL;
-+ } break;
-+
-+ default:
-+ ret = -ENOTTY;
-+ break;
-+ }
-+
-+ if (service)
-+ unlock_service(service);
-+
-+ if (ret == 0) {
-+ if (status == VCHIQ_ERROR)
-+ ret = -EIO;
-+ else if (status == VCHIQ_RETRY)
-+ ret = -EINTR;
-+ }
-+
-+ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) &&
-+ (ret != -EWOULDBLOCK))
-+ vchiq_log_info(vchiq_arm_log_level,
-+ " ioctl instance %lx, cmd %s -> status %d, %ld",
-+ (unsigned long)instance,
-+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ?
-+ ioctl_names[_IOC_NR(cmd)] :
-+ "<invalid>",
-+ status, ret);
-+ else
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ " ioctl instance %lx, cmd %s -> status %d, %ld",
-+ (unsigned long)instance,
-+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ?
-+ ioctl_names[_IOC_NR(cmd)] :
-+ "<invalid>",
-+ status, ret);
-+
-+ return ret;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_open
-+*
-+***************************************************************************/
-+
-+static int
-+vchiq_open(struct inode *inode, struct file *file)
-+{
-+ int dev = iminor(inode) & 0x0f;
-+ vchiq_log_info(vchiq_arm_log_level, "vchiq_open");
-+ switch (dev) {
-+ case VCHIQ_MINOR: {
-+ int ret;
-+ VCHIQ_STATE_T *state = vchiq_get_state();
-+ VCHIQ_INSTANCE_T instance;
-+
-+ if (!state) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "vchiq has no connection to VideoCore");
-+ return -ENOTCONN;
-+ }
-+
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+ if (!instance)
-+ return -ENOMEM;
-+
-+ instance->state = state;
-+ instance->pid = current->tgid;
-+
-+ ret = vchiq_debugfs_add_instance(instance);
-+ if (ret != 0) {
-+ kfree(instance);
-+ return ret;
-+ }
-+
-+ sema_init(&instance->insert_event, 0);
-+ sema_init(&instance->remove_event, 0);
-+ mutex_init(&instance->completion_mutex);
-+ mutex_init(&instance->bulk_waiter_list_mutex);
-+ INIT_LIST_HEAD(&instance->bulk_waiter_list);
-+
-+ file->private_data = instance;
-+ } break;
-+
-+ default:
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unknown minor device: %d", dev);
-+ return -ENXIO;
-+ }
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_release
-+*
-+***************************************************************************/
-+
-+static int
-+vchiq_release(struct inode *inode, struct file *file)
-+{
-+ int dev = iminor(inode) & 0x0f;
-+ int ret = 0;
-+ switch (dev) {
-+ case VCHIQ_MINOR: {
-+ VCHIQ_INSTANCE_T instance = file->private_data;
-+ VCHIQ_STATE_T *state = vchiq_get_state();
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "vchiq_release: instance=%lx",
-+ (unsigned long)instance);
-+
-+ if (!state) {
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ /* Ensure videocore is awake to allow termination. */
-+ vchiq_use_internal(instance->state, NULL,
-+ USE_TYPE_VCHIQ);
-+
-+ mutex_lock(&instance->completion_mutex);
-+
-+ /* Wake the completion thread and ask it to exit */
-+ instance->closing = 1;
-+ up(&instance->insert_event);
-+
-+ mutex_unlock(&instance->completion_mutex);
-+
-+ /* Wake the slot handler if the completion queue is full. */
-+ up(&instance->remove_event);
-+
-+ /* Mark all services for termination... */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance,
-+ &i)) != NULL) {
-+ USER_SERVICE_T *user_service = service->base.userdata;
-+
-+ /* Wake the slot handler if the msg queue is full. */
-+ up(&user_service->remove_event);
-+
-+ vchiq_terminate_service_internal(service);
-+ unlock_service(service);
-+ }
-+
-+ /* ...and wait for them to die */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance, &i))
-+ != NULL) {
-+ USER_SERVICE_T *user_service = service->base.userdata;
-+
-+ down(&service->remove_event);
-+
-+ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE);
-+
-+ spin_lock(&msg_queue_spinlock);
-+
-+ while (user_service->msg_remove !=
-+ user_service->msg_insert) {
-+ VCHIQ_HEADER_T *header = user_service->
-+ msg_queue[user_service->msg_remove &
-+ (MSG_QUEUE_SIZE - 1)];
-+ user_service->msg_remove++;
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ if (header)
-+ vchiq_release_message(
-+ service->handle,
-+ header);
-+ spin_lock(&msg_queue_spinlock);
-+ }
-+
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ unlock_service(service);
-+ }
-+
-+ /* Release any closed services */
-+ while (instance->completion_remove !=
-+ instance->completion_insert) {
-+ VCHIQ_COMPLETION_DATA_T *completion;
-+ VCHIQ_SERVICE_T *service;
-+ completion = &instance->completions[
-+ instance->completion_remove &
-+ (MAX_COMPLETIONS - 1)];
-+ service = completion->service_userdata;
-+ if (completion->reason == VCHIQ_SERVICE_CLOSED)
-+ {
-+ USER_SERVICE_T *user_service =
-+ service->base.userdata;
-+
-+ /* Wake any blocked user-thread */
-+ if (instance->use_close_delivered)
-+ up(&user_service->close_event);
-+ unlock_service(service);
-+ }
-+ instance->completion_remove++;
-+ }
-+
-+ /* Release the PEER service count. */
-+ vchiq_release_internal(instance->state, NULL);
-+
-+ {
-+ struct list_head *pos, *next;
-+ list_for_each_safe(pos, next,
-+ &instance->bulk_waiter_list) {
-+ struct bulk_waiter_node *waiter;
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "bulk_waiter - cleaned up %x "
-+ "for pid %d",
-+ (unsigned int)waiter, waiter->pid);
-+ kfree(waiter);
-+ }
-+ }
-+
-+ vchiq_debugfs_remove_instance(instance);
-+
-+ kfree(instance);
-+ file->private_data = NULL;
-+ } break;
-+
-+ default:
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unknown minor device: %d", dev);
-+ ret = -ENXIO;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_dump
-+*
-+***************************************************************************/
-+
-+void
-+vchiq_dump(void *dump_context, const char *str, int len)
-+{
-+ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context;
-+
-+ if (context->actual < context->space) {
-+ int copy_bytes;
-+ if (context->offset > 0) {
-+ int skip_bytes = min(len, (int)context->offset);
-+ str += skip_bytes;
-+ len -= skip_bytes;
-+ context->offset -= skip_bytes;
-+ if (context->offset > 0)
-+ return;
-+ }
-+ copy_bytes = min(len, (int)(context->space - context->actual));
-+ if (copy_bytes == 0)
-+ return;
-+ if (copy_to_user(context->buf + context->actual, str,
-+ copy_bytes))
-+ context->actual = -EFAULT;
-+ context->actual += copy_bytes;
-+ len -= copy_bytes;
-+
-+ /* If tne terminating NUL is included in the length, then it
-+ ** marks the end of a line and should be replaced with a
-+ ** carriage return. */
-+ if ((len == 0) && (str[copy_bytes - 1] == '\0')) {
-+ char cr = '\n';
-+ if (copy_to_user(context->buf + context->actual - 1,
-+ &cr, 1))
-+ context->actual = -EFAULT;
-+ }
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_dump_platform_instance_state
-+*
-+***************************************************************************/
-+
-+void
-+vchiq_dump_platform_instances(void *dump_context)
-+{
-+ VCHIQ_STATE_T *state = vchiq_get_state();
-+ char buf[80];
-+ int len;
-+ int i;
-+
-+ /* There is no list of instances, so instead scan all services,
-+ marking those that have been dumped. */
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ VCHIQ_INSTANCE_T instance;
-+
-+ if (service && (service->base.callback == service_callback)) {
-+ instance = service->instance;
-+ if (instance)
-+ instance->mark = 0;
-+ }
-+ }
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ VCHIQ_INSTANCE_T instance;
-+
-+ if (service && (service->base.callback == service_callback)) {
-+ instance = service->instance;
-+ if (instance && !instance->mark) {
-+ len = snprintf(buf, sizeof(buf),
-+ "Instance %x: pid %d,%s completions "
-+ "%d/%d",
-+ (unsigned int)instance, instance->pid,
-+ instance->connected ? " connected, " :
-+ "",
-+ instance->completion_insert -
-+ instance->completion_remove,
-+ MAX_COMPLETIONS);
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ instance->mark = 1;
-+ }
-+ }
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_dump_platform_service_state
-+*
-+***************************************************************************/
-+
-+void
-+vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service)
-+{
-+ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata;
-+ char buf[80];
-+ int len;
-+
-+ len = snprintf(buf, sizeof(buf), " instance %x",
-+ (unsigned int)service->instance);
-+
-+ if ((service->base.callback == service_callback) &&
-+ user_service->is_vchi) {
-+ len += snprintf(buf + len, sizeof(buf) - len,
-+ ", %d/%d messages",
-+ user_service->msg_insert - user_service->msg_remove,
-+ MSG_QUEUE_SIZE);
-+
-+ if (user_service->dequeue_pending)
-+ len += snprintf(buf + len, sizeof(buf) - len,
-+ " (dequeue pending)");
-+ }
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+}
-+
-+/****************************************************************************
-+*
-+* dump_user_mem
-+*
-+***************************************************************************/
-+
-+static void
-+dump_phys_mem(void *virt_addr, uint32_t num_bytes)
-+{
-+ int rc;
-+ uint8_t *end_virt_addr = virt_addr + num_bytes;
-+ int num_pages;
-+ int offset;
-+ int end_offset;
-+ int page_idx;
-+ int prev_idx;
-+ struct page *page;
-+ struct page **pages;
-+ uint8_t *kmapped_virt_ptr;
-+
-+ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */
-+
-+ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL);
-+ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) &
-+ ~0x0fuL);
-+
-+ offset = (int)(long)virt_addr & (PAGE_SIZE - 1);
-+ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1);
-+
-+ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
-+
-+ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL);
-+ if (pages == NULL) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to allocation memory for %d pages\n",
-+ num_pages);
-+ return;
-+ }
-+
-+ down_read(&current->mm->mmap_sem);
-+ rc = get_user_pages(current, /* task */
-+ current->mm, /* mm */
-+ (unsigned long)virt_addr, /* start */
-+ num_pages, /* len */
-+ 0, /* write */
-+ 0, /* force */
-+ pages, /* pages (array of page pointers) */
-+ NULL); /* vmas */
-+ up_read(&current->mm->mmap_sem);
-+
-+ prev_idx = -1;
-+ page = NULL;
-+
-+ while (offset < end_offset) {
-+
-+ int page_offset = offset % PAGE_SIZE;
-+ page_idx = offset / PAGE_SIZE;
-+
-+ if (page_idx != prev_idx) {
-+
-+ if (page != NULL)
-+ kunmap(page);
-+ page = pages[page_idx];
-+ kmapped_virt_ptr = kmap(page);
-+
-+ prev_idx = page_idx;
-+ }
-+
-+ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE)
-+ vchiq_log_dump_mem("ph",
-+ (uint32_t)(unsigned long)&kmapped_virt_ptr[
-+ page_offset],
-+ &kmapped_virt_ptr[page_offset], 16);
-+
-+ offset += 16;
-+ }
-+ if (page != NULL)
-+ kunmap(page);
-+
-+ for (page_idx = 0; page_idx < num_pages; page_idx++)
-+ page_cache_release(pages[page_idx]);
-+
-+ kfree(pages);
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_read
-+*
-+***************************************************************************/
-+
-+static ssize_t
-+vchiq_read(struct file *file, char __user *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ DUMP_CONTEXT_T context;
-+ context.buf = buf;
-+ context.actual = 0;
-+ context.space = count;
-+ context.offset = *ppos;
-+
-+ vchiq_dump_state(&context, &g_state);
-+
-+ *ppos += context.actual;
-+
-+ return context.actual;
-+}
-+
-+VCHIQ_STATE_T *
-+vchiq_get_state(void)
-+{
-+
-+ if (g_state.remote == NULL)
-+ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__);
-+ else if (g_state.remote->initialised != 1)
-+ printk(KERN_NOTICE "%s: g_state.remote->initialised != 1 (%d)\n",
-+ __func__, g_state.remote->initialised);
-+
-+ return ((g_state.remote != NULL) &&
-+ (g_state.remote->initialised == 1)) ? &g_state : NULL;
-+}
-+
-+static const struct file_operations
-+vchiq_fops = {
-+ .owner = THIS_MODULE,
-+ .unlocked_ioctl = vchiq_ioctl,
-+ .open = vchiq_open,
-+ .release = vchiq_release,
-+ .read = vchiq_read
-+};
-+
-+/*
-+ * Autosuspend related functionality
-+ */
-+
-+int
-+vchiq_videocore_wanted(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ if (!arm_state)
-+ /* autosuspend not supported - always return wanted */
-+ return 1;
-+ else if (arm_state->blocked_count)
-+ return 1;
-+ else if (!arm_state->videocore_use_count)
-+ /* usage count zero - check for override unless we're forcing */
-+ if (arm_state->resume_blocked)
-+ return 0;
-+ else
-+ return vchiq_platform_videocore_wanted(state);
-+ else
-+ /* non-zero usage count - videocore still required */
-+ return 1;
-+}
-+
-+static VCHIQ_STATUS_T
-+vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header,
-+ VCHIQ_SERVICE_HANDLE_T service_user,
-+ void *bulk_user)
-+{
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s callback reason %d", __func__, reason);
-+ return 0;
-+}
-+
-+static int
-+vchiq_keepalive_thread_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_INSTANCE_T instance;
-+ VCHIQ_SERVICE_HANDLE_T ka_handle;
-+
-+ VCHIQ_SERVICE_PARAMS_T params = {
-+ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'),
-+ .callback = vchiq_keepalive_vchiq_callback,
-+ .version = KEEPALIVE_VER,
-+ .version_min = KEEPALIVE_VER_MIN
-+ };
-+
-+ status = vchiq_initialise(&instance);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_initialise failed %d", __func__, status);
-+ goto exit;
-+ }
-+
-+ status = vchiq_connect(instance);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_connect failed %d", __func__, status);
-+ goto shutdown;
-+ }
-+
-+ status = vchiq_add_service(instance, &params, &ka_handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_open_service failed %d", __func__, status);
-+ goto shutdown;
-+ }
-+
-+ while (1) {
-+ long rc = 0, uc = 0;
-+ if (wait_for_completion_interruptible(&arm_state->ka_evt)
-+ != 0) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s interrupted", __func__);
-+ flush_signals(current);
-+ continue;
-+ }
-+
-+ /* read and clear counters. Do release_count then use_count to
-+ * prevent getting more releases than uses */
-+ rc = atomic_xchg(&arm_state->ka_release_count, 0);
-+ uc = atomic_xchg(&arm_state->ka_use_count, 0);
-+
-+ /* Call use/release service the requisite number of times.
-+ * Process use before release so use counts don't go negative */
-+ while (uc--) {
-+ atomic_inc(&arm_state->ka_use_ack_count);
-+ status = vchiq_use_service(ka_handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_use_service error %d",
-+ __func__, status);
-+ }
-+ }
-+ while (rc--) {
-+ status = vchiq_release_service(ka_handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_release_service error %d",
-+ __func__, status);
-+ }
-+ }
-+ }
-+
-+shutdown:
-+ vchiq_shutdown(instance);
-+exit:
-+ return 0;
-+}
-+
-+
-+
-+VCHIQ_STATUS_T
-+vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (arm_state) {
-+ rwlock_init(&arm_state->susp_res_lock);
-+
-+ init_completion(&arm_state->ka_evt);
-+ atomic_set(&arm_state->ka_use_count, 0);
-+ atomic_set(&arm_state->ka_use_ack_count, 0);
-+ atomic_set(&arm_state->ka_release_count, 0);
-+
-+ init_completion(&arm_state->vc_suspend_complete);
-+
-+ init_completion(&arm_state->vc_resume_complete);
-+ /* Initialise to 'done' state. We only want to block on resume
-+ * completion while videocore is suspended. */
-+ set_resume_state(arm_state, VC_RESUME_RESUMED);
-+
-+ init_completion(&arm_state->resume_blocker);
-+ /* Initialise to 'done' state. We only want to block on this
-+ * completion while resume is blocked */
-+ complete_all(&arm_state->resume_blocker);
-+
-+ init_completion(&arm_state->blocked_blocker);
-+ /* Initialise to 'done' state. We only want to block on this
-+ * completion while things are waiting on the resume blocker */
-+ complete_all(&arm_state->blocked_blocker);
-+
-+ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS;
-+ arm_state->suspend_timer_running = 0;
-+ init_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer.data = (unsigned long)(state);
-+ arm_state->suspend_timer.function = suspend_timer_callback;
-+
-+ arm_state->first_connect = 0;
-+
-+ }
-+ return status;
-+}
-+
-+/*
-+** Functions to modify the state variables;
-+** set_suspend_state
-+** set_resume_state
-+**
-+** There are more state variables than we might like, so ensure they remain in
-+** step. Suspend and resume state are maintained separately, since most of
-+** these state machines can operate independently. However, there are a few
-+** states where state transitions in one state machine cause a reset to the
-+** other state machine. In addition, there are some completion events which
-+** need to occur on state machine reset and end-state(s), so these are also
-+** dealt with in these functions.
-+**
-+** In all states we set the state variable according to the input, but in some
-+** cases we perform additional steps outlined below;
-+**
-+** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time.
-+** The suspend completion is completed after any suspend
-+** attempt. When we reset the state machine we also reset
-+** the completion. This reset occurs when videocore is
-+** resumed, and also if we initiate suspend after a suspend
-+** failure.
-+**
-+** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for
-+** suspend - ie from this point on we must try to suspend
-+** before resuming can occur. We therefore also reset the
-+** resume state machine to VC_RESUME_IDLE in this state.
-+**
-+** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call
-+** complete_all on the suspend completion to notify
-+** anything waiting for suspend to happen.
-+**
-+** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also
-+** initiate resume, so no need to alter resume state.
-+** We call complete_all on the suspend completion to notify
-+** of suspend rejection.
-+**
-+** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the
-+** suspend completion and reset the resume state machine.
-+**
-+** VC_RESUME_IDLE - Initialise the resume completion at the same time. The
-+** resume completion is in it's 'done' state whenever
-+** videcore is running. Therfore, the VC_RESUME_IDLE state
-+** implies that videocore is suspended.
-+** Hence, any thread which needs to wait until videocore is
-+** running can wait on this completion - it will only block
-+** if videocore is suspended.
-+**
-+** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running.
-+** Call complete_all on the resume completion to unblock
-+** any threads waiting for resume. Also reset the suspend
-+** state machine to it's idle state.
-+**
-+** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists.
-+*/
-+
-+inline void
-+set_suspend_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_suspend_status new_state)
-+{
-+ /* set the state in all cases */
-+ arm_state->vc_suspend_state = new_state;
-+
-+ /* state specific additional actions */
-+ switch (new_state) {
-+ case VC_SUSPEND_FORCE_CANCELED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ break;
-+ case VC_SUSPEND_REJECTED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ break;
-+ case VC_SUSPEND_FAILED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ arm_state->vc_resume_state = VC_RESUME_RESUMED;
-+ complete_all(&arm_state->vc_resume_complete);
-+ break;
-+ case VC_SUSPEND_IDLE:
-+ INIT_COMPLETION(arm_state->vc_suspend_complete);
-+ break;
-+ case VC_SUSPEND_REQUESTED:
-+ break;
-+ case VC_SUSPEND_IN_PROGRESS:
-+ set_resume_state(arm_state, VC_RESUME_IDLE);
-+ break;
-+ case VC_SUSPEND_SUSPENDED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ break;
-+ default:
-+ BUG();
-+ break;
-+ }
-+}
-+
-+inline void
-+set_resume_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_resume_status new_state)
-+{
-+ /* set the state in all cases */
-+ arm_state->vc_resume_state = new_state;
-+
-+ /* state specific additional actions */
-+ switch (new_state) {
-+ case VC_RESUME_FAILED:
-+ break;
-+ case VC_RESUME_IDLE:
-+ INIT_COMPLETION(arm_state->vc_resume_complete);
-+ break;
-+ case VC_RESUME_REQUESTED:
-+ break;
-+ case VC_RESUME_IN_PROGRESS:
-+ break;
-+ case VC_RESUME_RESUMED:
-+ complete_all(&arm_state->vc_resume_complete);
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+ break;
-+ default:
-+ BUG();
-+ break;
-+ }
-+}
-+
-+
-+/* should be called with the write lock held */
-+inline void
-+start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ del_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer.expires = jiffies +
-+ msecs_to_jiffies(arm_state->
-+ suspend_timer_timeout);
-+ add_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer_running = 1;
-+}
-+
-+/* should be called with the write lock held */
-+static inline void
-+stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ if (arm_state->suspend_timer_running) {
-+ del_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer_running = 0;
-+ }
-+}
-+
-+static inline int
-+need_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) &&
-+ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) &&
-+ vchiq_videocore_wanted(state);
-+}
-+
-+static int
-+block_resume(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ int status = VCHIQ_SUCCESS;
-+ const unsigned long timeout_val =
-+ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS);
-+ int resume_count = 0;
-+
-+ /* Allow any threads which were blocked by the last force suspend to
-+ * complete if they haven't already. Only give this one shot; if
-+ * blocked_count is incremented after blocked_blocker is completed
-+ * (which only happens when blocked_count hits 0) then those threads
-+ * will have to wait until next time around */
-+ if (arm_state->blocked_count) {
-+ INIT_COMPLETION(arm_state->blocked_blocker);
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously "
-+ "blocked clients", __func__);
-+ if (wait_for_completion_interruptible_timeout(
-+ &arm_state->blocked_blocker, timeout_val)
-+ <= 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s wait for "
-+ "previously blocked clients failed" , __func__);
-+ status = VCHIQ_ERROR;
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked "
-+ "clients resumed", __func__);
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ }
-+
-+ /* We need to wait for resume to complete if it's in process */
-+ while (arm_state->vc_resume_state != VC_RESUME_RESUMED &&
-+ arm_state->vc_resume_state > VC_RESUME_IDLE) {
-+ if (resume_count > 1) {
-+ status = VCHIQ_ERROR;
-+ vchiq_log_error(vchiq_susp_log_level, "%s waited too "
-+ "many times for resume" , __func__);
-+ goto out;
-+ }
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ vchiq_log_info(vchiq_susp_log_level, "%s wait for resume",
-+ __func__);
-+ if (wait_for_completion_interruptible_timeout(
-+ &arm_state->vc_resume_complete, timeout_val)
-+ <= 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s wait for "
-+ "resume failed (%s)", __func__,
-+ resume_state_names[arm_state->vc_resume_state +
-+ VC_RESUME_NUM_OFFSET]);
-+ status = VCHIQ_ERROR;
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s resumed", __func__);
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ resume_count++;
-+ }
-+ INIT_COMPLETION(arm_state->resume_blocker);
-+ arm_state->resume_blocked = 1;
-+
-+out:
-+ return status;
-+}
-+
-+static inline void
-+unblock_resume(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ complete_all(&arm_state->resume_blocker);
-+ arm_state->resume_blocked = 0;
-+}
-+
-+/* Initiate suspend via slot handler. Should be called with the write lock
-+ * held */
-+VCHIQ_STATUS_T
-+vchiq_arm_vcsuspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+ status = VCHIQ_SUCCESS;
-+
-+
-+ switch (arm_state->vc_suspend_state) {
-+ case VC_SUSPEND_REQUESTED:
-+ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already "
-+ "requested", __func__);
-+ break;
-+ case VC_SUSPEND_IN_PROGRESS:
-+ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in "
-+ "progress", __func__);
-+ break;
-+
-+ default:
-+ /* We don't expect to be in other states, so log but continue
-+ * anyway */
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s unexpected suspend state %s", __func__,
-+ suspend_state_names[arm_state->vc_suspend_state +
-+ VC_SUSPEND_NUM_OFFSET]);
-+ /* fall through */
-+ case VC_SUSPEND_REJECTED:
-+ case VC_SUSPEND_FAILED:
-+ /* Ensure any idle state actions have been run */
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+ /* fall through */
-+ case VC_SUSPEND_IDLE:
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: suspending", __func__);
-+ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED);
-+ /* kick the slot handler thread to initiate suspend */
-+ request_poll(state, NULL, 0);
-+ break;
-+ }
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status);
-+ return status;
-+}
-+
-+void
-+vchiq_platform_check_suspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int susp = 0;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED &&
-+ arm_state->vc_resume_state == VC_RESUME_RESUMED) {
-+ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS);
-+ susp = 1;
-+ }
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (susp)
-+ vchiq_platform_suspend(state);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return;
-+}
-+
-+
-+static void
-+output_timeout_error(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ char service_err[50] = "";
-+ int vc_use_count = arm_state->videocore_use_count;
-+ int active_services = state->unused_service;
-+ int i;
-+
-+ if (!arm_state->videocore_use_count) {
-+ snprintf(service_err, 50, " Videocore usecount is 0");
-+ goto output_msg;
-+ }
-+ for (i = 0; i < active_services; i++) {
-+ VCHIQ_SERVICE_T *service_ptr = state->services[i];
-+ if (service_ptr && service_ptr->service_use_count &&
-+ (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) {
-+ snprintf(service_err, 50, " %c%c%c%c(%d) service has "
-+ "use count %d%s", VCHIQ_FOURCC_AS_4CHARS(
-+ service_ptr->base.fourcc),
-+ service_ptr->client_id,
-+ service_ptr->service_use_count,
-+ service_ptr->service_use_count ==
-+ vc_use_count ? "" : " (+ more)");
-+ break;
-+ }
-+ }
-+
-+output_msg:
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "timed out waiting for vc suspend (%d).%s",
-+ arm_state->autosuspend_override, service_err);
-+
-+}
-+
-+/* Try to get videocore into suspended state, regardless of autosuspend state.
-+** We don't actually force suspend, since videocore may get into a bad state
-+** if we force suspend at a bad time. Instead, we wait for autosuspend to
-+** determine a good point to suspend. If this doesn't happen within 100ms we
-+** report failure.
-+**
-+** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if
-+** videocore failed to suspend in time or VCHIQ_ERROR if interrupted.
-+*/
-+VCHIQ_STATUS_T
-+vchiq_arm_force_suspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ long rc = 0;
-+ int repeat = -1;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+
-+ status = block_resume(arm_state);
-+ if (status != VCHIQ_SUCCESS)
-+ goto unlock;
-+ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) {
-+ /* Already suspended - just block resume and exit */
-+ vchiq_log_info(vchiq_susp_log_level, "%s already suspended",
-+ __func__);
-+ status = VCHIQ_SUCCESS;
-+ goto unlock;
-+ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) {
-+ /* initiate suspend immediately in the case that we're waiting
-+ * for the timeout */
-+ stop_suspend_timer(arm_state);
-+ if (!vchiq_videocore_wanted(state)) {
-+ vchiq_log_info(vchiq_susp_log_level, "%s videocore "
-+ "idle, initiating suspend", __func__);
-+ status = vchiq_arm_vcsuspend(state);
-+ } else if (arm_state->autosuspend_override <
-+ FORCE_SUSPEND_FAIL_MAX) {
-+ vchiq_log_info(vchiq_susp_log_level, "%s letting "
-+ "videocore go idle", __func__);
-+ status = VCHIQ_SUCCESS;
-+ } else {
-+ vchiq_log_warning(vchiq_susp_log_level, "%s failed too "
-+ "many times - attempting suspend", __func__);
-+ status = vchiq_arm_vcsuspend(state);
-+ }
-+ } else {
-+ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend "
-+ "in progress - wait for completion", __func__);
-+ status = VCHIQ_SUCCESS;
-+ }
-+
-+ /* Wait for suspend to happen due to system idle (not forced..) */
-+ if (status != VCHIQ_SUCCESS)
-+ goto unblock_resume;
-+
-+ do {
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ rc = wait_for_completion_interruptible_timeout(
-+ &arm_state->vc_suspend_complete,
-+ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS));
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (rc < 0) {
-+ vchiq_log_warning(vchiq_susp_log_level, "%s "
-+ "interrupted waiting for suspend", __func__);
-+ status = VCHIQ_ERROR;
-+ goto unblock_resume;
-+ } else if (rc == 0) {
-+ if (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) {
-+ /* Repeat timeout once if in progress */
-+ if (repeat < 0) {
-+ repeat = 1;
-+ continue;
-+ }
-+ }
-+ arm_state->autosuspend_override++;
-+ output_timeout_error(state);
-+
-+ status = VCHIQ_RETRY;
-+ goto unblock_resume;
-+ }
-+ } while (0 < (repeat--));
-+
-+ /* Check and report state in case we need to abort ARM suspend */
-+ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) {
-+ status = VCHIQ_RETRY;
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s videocore suspend failed (state %s)", __func__,
-+ suspend_state_names[arm_state->vc_suspend_state +
-+ VC_SUSPEND_NUM_OFFSET]);
-+ /* Reset the state only if it's still in an error state.
-+ * Something could have already initiated another suspend. */
-+ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE)
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+
-+ goto unblock_resume;
-+ }
-+
-+ /* successfully suspended - unlock and exit */
-+ goto unlock;
-+
-+unblock_resume:
-+ /* all error states need to unblock resume before exit */
-+ unblock_resume(arm_state);
-+
-+unlock:
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status);
-+ return status;
-+}
-+
-+void
-+vchiq_check_suspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED &&
-+ arm_state->first_connect &&
-+ !vchiq_videocore_wanted(state)) {
-+ vchiq_arm_vcsuspend(state);
-+ }
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return;
-+}
-+
-+
-+int
-+vchiq_arm_allow_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int resume = 0;
-+ int ret = -1;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ unblock_resume(arm_state);
-+ resume = vchiq_check_resume(state);
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (resume) {
-+ if (wait_for_completion_interruptible(
-+ &arm_state->vc_resume_complete) < 0) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s interrupted", __func__);
-+ /* failed, cannot accurately derive suspend
-+ * state, so exit early. */
-+ goto out;
-+ }
-+ }
-+
-+ read_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: Videocore remains suspended", __func__);
-+ } else {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: Videocore resumed", __func__);
-+ ret = 0;
-+ }
-+ read_unlock_bh(&arm_state->susp_res_lock);
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
-+ return ret;
-+}
-+
-+/* This function should be called with the write lock held */
-+int
-+vchiq_check_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int resume = 0;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ if (need_resume(state)) {
-+ set_resume_state(arm_state, VC_RESUME_REQUESTED);
-+ request_poll(state, NULL, 0);
-+ resume = 1;
-+ }
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return resume;
-+}
-+
-+void
-+vchiq_platform_check_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int res = 0;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->wake_address == 0) {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: already awake", __func__);
-+ goto unlock;
-+ }
-+ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: already resuming", __func__);
-+ goto unlock;
-+ }
-+
-+ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) {
-+ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS);
-+ res = 1;
-+ } else
-+ vchiq_log_trace(vchiq_susp_log_level,
-+ "%s: not resuming (resume state %s)", __func__,
-+ resume_state_names[arm_state->vc_resume_state +
-+ VC_RESUME_NUM_OFFSET]);
-+
-+unlock:
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (res)
-+ vchiq_platform_resume(state);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return;
-+
-+}
-+
-+
-+
-+VCHIQ_STATUS_T
-+vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ enum USE_TYPE_E use_type)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS;
-+ char entity[16];
-+ int *entity_uc;
-+ int local_uc, local_entity_uc;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ if (use_type == USE_TYPE_VCHIQ) {
-+ sprintf(entity, "VCHIQ: ");
-+ entity_uc = &arm_state->peer_use_count;
-+ } else if (service) {
-+ sprintf(entity, "%c%c%c%c:%03d",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->client_id);
-+ entity_uc = &service->service_use_count;
-+ } else {
-+ vchiq_log_error(vchiq_susp_log_level, "%s null service "
-+ "ptr", __func__);
-+ ret = VCHIQ_ERROR;
-+ goto out;
-+ }
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ while (arm_state->resume_blocked) {
-+ /* If we call 'use' while force suspend is waiting for suspend,
-+ * then we're about to block the thread which the force is
-+ * waiting to complete, so we're bound to just time out. In this
-+ * case, set the suspend state such that the wait will be
-+ * canceled, so we can complete as quickly as possible. */
-+ if (arm_state->resume_blocked && arm_state->vc_suspend_state ==
-+ VC_SUSPEND_IDLE) {
-+ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED);
-+ break;
-+ }
-+ /* If suspend is already in progress then we need to block */
-+ if (!try_wait_for_completion(&arm_state->resume_blocker)) {
-+ /* Indicate that there are threads waiting on the resume
-+ * blocker. These need to be allowed to complete before
-+ * a _second_ call to force suspend can complete,
-+ * otherwise low priority threads might never actually
-+ * continue */
-+ arm_state->blocked_count++;
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s resume "
-+ "blocked - waiting...", __func__, entity);
-+ if (wait_for_completion_killable(
-+ &arm_state->resume_blocker) != 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s %s "
-+ "wait for resume blocker interrupted",
-+ __func__, entity);
-+ ret = VCHIQ_ERROR;
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ arm_state->blocked_count--;
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s resume "
-+ "unblocked", __func__, entity);
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (--arm_state->blocked_count == 0)
-+ complete_all(&arm_state->blocked_blocker);
-+ }
-+ }
-+
-+ stop_suspend_timer(arm_state);
-+
-+ local_uc = ++arm_state->videocore_use_count;
-+ local_entity_uc = ++(*entity_uc);
-+
-+ /* If there's a pending request which hasn't yet been serviced then
-+ * just clear it. If we're past VC_SUSPEND_REQUESTED state then
-+ * vc_resume_complete will block until we either resume or fail to
-+ * suspend */
-+ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED)
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+
-+ if ((use_type != USE_TYPE_SERVICE_NO_RESUME) && need_resume(state)) {
-+ set_resume_state(arm_state, VC_RESUME_REQUESTED);
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d",
-+ __func__, entity, local_entity_uc, local_uc);
-+ request_poll(state, NULL, 0);
-+ } else
-+ vchiq_log_trace(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d",
-+ __func__, entity, *entity_uc, local_uc);
-+
-+
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ /* Completion is in a done state when we're not suspended, so this won't
-+ * block for the non-suspended case. */
-+ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) {
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume",
-+ __func__, entity);
-+ if (wait_for_completion_killable(
-+ &arm_state->vc_resume_complete) != 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for "
-+ "resume interrupted", __func__, entity);
-+ ret = VCHIQ_ERROR;
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__,
-+ entity);
-+ }
-+
-+ if (ret == VCHIQ_SUCCESS) {
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0);
-+ while (ack_cnt && (status == VCHIQ_SUCCESS)) {
-+ /* Send the use notify to videocore */
-+ status = vchiq_send_remote_use_active(state);
-+ if (status == VCHIQ_SUCCESS)
-+ ack_cnt--;
-+ else
-+ atomic_add(ack_cnt,
-+ &arm_state->ka_use_ack_count);
-+ }
-+ }
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
-+ return ret;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS;
-+ char entity[16];
-+ int *entity_uc;
-+ int local_uc, local_entity_uc;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ if (service) {
-+ sprintf(entity, "%c%c%c%c:%03d",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->client_id);
-+ entity_uc = &service->service_use_count;
-+ } else {
-+ sprintf(entity, "PEER: ");
-+ entity_uc = &arm_state->peer_use_count;
-+ }
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (!arm_state->videocore_use_count || !(*entity_uc)) {
-+ /* Don't use BUG_ON - don't allow user thread to crash kernel */
-+ WARN_ON(!arm_state->videocore_use_count);
-+ WARN_ON(!(*entity_uc));
-+ ret = VCHIQ_ERROR;
-+ goto unlock;
-+ }
-+ local_uc = --arm_state->videocore_use_count;
-+ local_entity_uc = --(*entity_uc);
-+
-+ if (!vchiq_videocore_wanted(state)) {
-+ if (vchiq_platform_use_suspend_timer() &&
-+ !arm_state->resume_blocked) {
-+ /* Only use the timer if we're not trying to force
-+ * suspend (=> resume_blocked) */
-+ start_suspend_timer(arm_state);
-+ } else {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d - suspending",
-+ __func__, entity, *entity_uc,
-+ arm_state->videocore_use_count);
-+ vchiq_arm_vcsuspend(state);
-+ }
-+ } else
-+ vchiq_log_trace(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d",
-+ __func__, entity, *entity_uc,
-+ arm_state->videocore_use_count);
-+
-+unlock:
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
-+ return ret;
-+}
-+
-+void
-+vchiq_on_remote_use(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+ atomic_inc(&arm_state->ka_use_count);
-+ complete(&arm_state->ka_evt);
-+}
-+
-+void
-+vchiq_on_remote_release(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+ atomic_inc(&arm_state->ka_release_count);
-+ complete(&arm_state->ka_evt);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_use_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_release_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ return vchiq_release_internal(service->state, service);
-+}
-+
-+VCHIQ_DEBUGFS_NODE_T *
-+vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance)
-+{
-+ return &instance->debugfs_node;
-+}
-+
-+int
-+vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int use_count = 0, i;
-+ i = 0;
-+ while ((service = next_service_by_instance(instance->state,
-+ instance, &i)) != NULL) {
-+ use_count += service->service_use_count;
-+ unlock_service(service);
-+ }
-+ return use_count;
-+}
-+
-+int
-+vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance)
-+{
-+ return instance->pid;
-+}
-+
-+int
-+vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance)
-+{
-+ return instance->trace;
-+}
-+
-+void
-+vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+ i = 0;
-+ while ((service = next_service_by_instance(instance->state,
-+ instance, &i)) != NULL) {
-+ service->trace = trace;
-+ unlock_service(service);
-+ }
-+ instance->trace = (trace != 0);
-+}
-+
-+static void suspend_timer_callback(unsigned long context)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context;
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ if (!arm_state)
-+ goto out;
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s - suspend timer expired - check suspend", __func__);
-+ vchiq_check_suspend(state);
-+out:
-+ return;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_use_service_no_resume(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ if (service) {
-+ ret = vchiq_use_internal(service->state, service,
-+ USE_TYPE_SERVICE_NO_RESUME);
-+ unlock_service(service);
-+ }
-+ return ret;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ if (service) {
-+ ret = vchiq_use_internal(service->state, service,
-+ USE_TYPE_SERVICE);
-+ unlock_service(service);
-+ }
-+ return ret;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ if (service) {
-+ ret = vchiq_release_internal(service->state, service);
-+ unlock_service(service);
-+ }
-+ return ret;
-+}
-+
-+void
-+vchiq_dump_service_use_state(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int i, j = 0;
-+ /* Only dump 64 services */
-+ static const int local_max_services = 64;
-+ /* If there's more than 64 services, only dump ones with
-+ * non-zero counts */
-+ int only_nonzero = 0;
-+ static const char *nz = "<-- preventing suspend";
-+
-+ enum vc_suspend_status vc_suspend_state;
-+ enum vc_resume_status vc_resume_state;
-+ int peer_count;
-+ int vc_use_count;
-+ int active_services;
-+ struct service_data_struct {
-+ int fourcc;
-+ int clientid;
-+ int use_count;
-+ } service_data[local_max_services];
-+
-+ if (!arm_state)
-+ return;
-+
-+ read_lock_bh(&arm_state->susp_res_lock);
-+ vc_suspend_state = arm_state->vc_suspend_state;
-+ vc_resume_state = arm_state->vc_resume_state;
-+ peer_count = arm_state->peer_use_count;
-+ vc_use_count = arm_state->videocore_use_count;
-+ active_services = state->unused_service;
-+ if (active_services > local_max_services)
-+ only_nonzero = 1;
-+
-+ for (i = 0; (i < active_services) && (j < local_max_services); i++) {
-+ VCHIQ_SERVICE_T *service_ptr = state->services[i];
-+ if (!service_ptr)
-+ continue;
-+
-+ if (only_nonzero && !service_ptr->service_use_count)
-+ continue;
-+
-+ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) {
-+ service_data[j].fourcc = service_ptr->base.fourcc;
-+ service_data[j].clientid = service_ptr->client_id;
-+ service_data[j++].use_count = service_ptr->
-+ service_use_count;
-+ }
-+ }
-+
-+ read_unlock_bh(&arm_state->susp_res_lock);
-+
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "-- Videcore suspend state: %s --",
-+ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]);
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "-- Videcore resume state: %s --",
-+ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]);
-+
-+ if (only_nonzero)
-+ vchiq_log_warning(vchiq_susp_log_level, "Too many active "
-+ "services (%d). Only dumping up to first %d services "
-+ "with non-zero use-count", active_services,
-+ local_max_services);
-+
-+ for (i = 0; i < j; i++) {
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "----- %c%c%c%c:%d service count %d %s",
-+ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc),
-+ service_data[i].clientid,
-+ service_data[i].use_count,
-+ service_data[i].use_count ? nz : "");
-+ }
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "----- VCHIQ use count count %d", peer_count);
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "--- Overall vchiq instance use count %d", vc_use_count);
-+
-+ vchiq_dump_platform_use_state(state);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_check_service(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state;
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+
-+ if (!service || !service->state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ arm_state = vchiq_platform_get_arm_state(service->state);
-+
-+ read_lock_bh(&arm_state->susp_res_lock);
-+ if (service->service_use_count)
-+ ret = VCHIQ_SUCCESS;
-+ read_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (ret == VCHIQ_ERROR) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s ERROR - %c%c%c%c:%d service count %d, "
-+ "state count %d, videocore suspend state %s", __func__,
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->client_id, service->service_use_count,
-+ arm_state->videocore_use_count,
-+ suspend_state_names[arm_state->vc_suspend_state +
-+ VC_SUSPEND_NUM_OFFSET]);
-+ vchiq_dump_service_use_state(service->state);
-+ }
-+out:
-+ return ret;
-+}
-+
-+/* stub functions */
-+void vchiq_on_remote_use_active(VCHIQ_STATE_T *state)
-+{
-+ (void)state;
-+}
-+
-+void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state,
-+ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id,
-+ get_conn_state_name(oldstate), get_conn_state_name(newstate));
-+ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) {
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (!arm_state->first_connect) {
-+ char threadname[10];
-+ arm_state->first_connect = 1;
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ snprintf(threadname, sizeof(threadname), "VCHIQka-%d",
-+ state->id);
-+ arm_state->ka_thread = kthread_create(
-+ &vchiq_keepalive_thread_func,
-+ (void *)state,
-+ threadname);
-+ if (arm_state->ka_thread == NULL) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "vchiq: FATAL: couldn't create thread %s",
-+ threadname);
-+ } else {
-+ wake_up_process(arm_state->ka_thread);
-+ }
-+ } else
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ }
-+}
-+
-+
-+/****************************************************************************
-+*
-+* vchiq_init - called when the module is loaded.
-+*
-+***************************************************************************/
-+
-+static int __init
-+vchiq_init(void)
-+{
-+ int err;
-+ void *ptr_err;
-+
-+ /* create debugfs entries */
-+ err = vchiq_debugfs_init();
-+ if (err != 0)
-+ goto failed_debugfs_init;
-+
-+ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME);
-+ if (err != 0) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to allocate device number");
-+ goto failed_alloc_chrdev;
-+ }
-+ cdev_init(&vchiq_cdev, &vchiq_fops);
-+ vchiq_cdev.owner = THIS_MODULE;
-+ err = cdev_add(&vchiq_cdev, vchiq_devid, 1);
-+ if (err != 0) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to register device");
-+ goto failed_cdev_add;
-+ }
-+
-+ /* create sysfs entries */
-+ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME);
-+ ptr_err = vchiq_class;
-+ if (IS_ERR(ptr_err))
-+ goto failed_class_create;
-+
-+ vchiq_dev = device_create(vchiq_class, NULL,
-+ vchiq_devid, NULL, "vchiq");
-+ ptr_err = vchiq_dev;
-+ if (IS_ERR(ptr_err))
-+ goto failed_device_create;
-+
-+ err = vchiq_platform_init(&g_state);
-+ if (err != 0)
-+ goto failed_platform_init;
-+
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "vchiq: initialised - version %d (min %d), device %d.%d",
-+ VCHIQ_VERSION, VCHIQ_VERSION_MIN,
-+ MAJOR(vchiq_devid), MINOR(vchiq_devid));
-+
-+ return 0;
-+
-+failed_platform_init:
-+ device_destroy(vchiq_class, vchiq_devid);
-+failed_device_create:
-+ class_destroy(vchiq_class);
-+failed_class_create:
-+ cdev_del(&vchiq_cdev);
-+ err = PTR_ERR(ptr_err);
-+failed_cdev_add:
-+ unregister_chrdev_region(vchiq_devid, 1);
-+failed_alloc_chrdev:
-+ vchiq_debugfs_deinit();
-+failed_debugfs_init:
-+ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq");
-+ return err;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_exit - called when the module is unloaded.
-+*
-+***************************************************************************/
-+
-+static void __exit
-+vchiq_exit(void)
-+{
-+ vchiq_platform_exit(&g_state);
-+ device_destroy(vchiq_class, vchiq_devid);
-+ class_destroy(vchiq_class);
-+ cdev_del(&vchiq_cdev);
-+ unregister_chrdev_region(vchiq_devid, 1);
-+}
-+
-+module_init(vchiq_init);
-+module_exit(vchiq_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,223 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_ARM_H
-+#define VCHIQ_ARM_H
-+
-+#include <linux/mutex.h>
-+#include <linux/semaphore.h>
-+#include <linux/atomic.h>
-+#include "vchiq_core.h"
-+#include "vchiq_debugfs.h"
-+
-+
-+enum vc_suspend_status {
-+ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */
-+ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */
-+ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */
-+ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */
-+ VC_SUSPEND_REQUESTED, /* User has requested suspend */
-+ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */
-+ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */
-+};
-+
-+enum vc_resume_status {
-+ VC_RESUME_FAILED = -1, /* Videocore resume failed */
-+ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */
-+ VC_RESUME_REQUESTED, /* User has requested resume */
-+ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */
-+ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */
-+};
-+
-+
-+enum USE_TYPE_E {
-+ USE_TYPE_SERVICE,
-+ USE_TYPE_SERVICE_NO_RESUME,
-+ USE_TYPE_VCHIQ
-+};
-+
-+
-+
-+typedef struct vchiq_arm_state_struct {
-+ /* Keepalive-related data */
-+ struct task_struct *ka_thread;
-+ struct completion ka_evt;
-+ atomic_t ka_use_count;
-+ atomic_t ka_use_ack_count;
-+ atomic_t ka_release_count;
-+
-+ struct completion vc_suspend_complete;
-+ struct completion vc_resume_complete;
-+
-+ rwlock_t susp_res_lock;
-+ enum vc_suspend_status vc_suspend_state;
-+ enum vc_resume_status vc_resume_state;
-+
-+ unsigned int wake_address;
-+
-+ struct timer_list suspend_timer;
-+ int suspend_timer_timeout;
-+ int suspend_timer_running;
-+
-+ /* Global use count for videocore.
-+ ** This is equal to the sum of the use counts for all services. When
-+ ** this hits zero the videocore suspend procedure will be initiated.
-+ */
-+ int videocore_use_count;
-+
-+ /* Use count to track requests from videocore peer.
-+ ** This use count is not associated with a service, so needs to be
-+ ** tracked separately with the state.
-+ */
-+ int peer_use_count;
-+
-+ /* Flag to indicate whether resume is blocked. This happens when the
-+ ** ARM is suspending
-+ */
-+ struct completion resume_blocker;
-+ int resume_blocked;
-+ struct completion blocked_blocker;
-+ int blocked_count;
-+
-+ int autosuspend_override;
-+
-+ /* Flag to indicate that the first vchiq connect has made it through.
-+ ** This means that both sides should be fully ready, and we should
-+ ** be able to suspend after this point.
-+ */
-+ int first_connect;
-+
-+ unsigned long long suspend_start_time;
-+ unsigned long long sleep_start_time;
-+ unsigned long long resume_start_time;
-+ unsigned long long last_wake_time;
-+
-+} VCHIQ_ARM_STATE_T;
-+
-+extern int vchiq_arm_log_level;
-+extern int vchiq_susp_log_level;
-+
-+extern int __init
-+vchiq_platform_init(VCHIQ_STATE_T *state);
-+
-+extern void __exit
-+vchiq_platform_exit(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATE_T *
-+vchiq_get_state(void);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_vcsuspend(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_force_suspend(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_arm_allow_resume(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_vcresume(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state);
-+
-+extern int
-+vchiq_check_resume(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_check_suspend(VCHIQ_STATE_T *state);
-+ VCHIQ_STATUS_T
-+vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_check_service(VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_platform_suspend(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_platform_use_suspend_timer(void);
-+
-+extern void
-+vchiq_dump_platform_use_state(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_dump_service_use_state(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_ARM_STATE_T*
-+vchiq_platform_get_arm_state(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_videocore_wanted(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ enum USE_TYPE_E use_type);
-+extern VCHIQ_STATUS_T
-+vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_DEBUGFS_NODE_T *
-+vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance);
-+
-+extern int
-+vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance);
-+
-+extern int
-+vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance);
-+
-+extern int
-+vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance);
-+
-+extern void
-+vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace);
-+
-+extern void
-+set_suspend_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_suspend_status new_state);
-+
-+extern void
-+set_resume_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_resume_status new_state);
-+
-+extern void
-+start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state);
-+
-+
-+#endif /* VCHIQ_ARM_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,37 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+const char *vchiq_get_build_hostname(void);
-+const char *vchiq_get_build_version(void);
-+const char *vchiq_get_build_time(void);
-+const char *vchiq_get_build_date(void);
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,66 @@
-+/**
-+ * Copyright (c) 2010-2014 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_CFG_H
-+#define VCHIQ_CFG_H
-+
-+#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I')
-+/* The version of VCHIQ - change with any non-trivial change */
-+#define VCHIQ_VERSION 7
-+/* The minimum compatible version - update to match VCHIQ_VERSION with any
-+** incompatible change */
-+#define VCHIQ_VERSION_MIN 3
-+
-+/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */
-+#define VCHIQ_VERSION_LIB_VERSION 7
-+
-+/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */
-+#define VCHIQ_VERSION_CLOSE_DELIVERED 7
-+
-+#define VCHIQ_MAX_STATES 1
-+#define VCHIQ_MAX_SERVICES 4096
-+#define VCHIQ_MAX_SLOTS 128
-+#define VCHIQ_MAX_SLOTS_PER_SIDE 64
-+
-+#define VCHIQ_NUM_CURRENT_BULKS 32
-+#define VCHIQ_NUM_SERVICE_BULKS 4
-+
-+#ifndef VCHIQ_ENABLE_DEBUG
-+#define VCHIQ_ENABLE_DEBUG 1
-+#endif
-+
-+#ifndef VCHIQ_ENABLE_STATS
-+#define VCHIQ_ENABLE_STATS 1
-+#endif
-+
-+#endif /* VCHIQ_CFG_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,120 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "vchiq_connected.h"
-+#include "vchiq_core.h"
-+#include "vchiq_killable.h"
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+
-+#define MAX_CALLBACKS 10
-+
-+static int g_connected;
-+static int g_num_deferred_callbacks;
-+static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS];
-+static int g_once_init;
-+static struct mutex g_connected_mutex;
-+
-+/****************************************************************************
-+*
-+* Function to initialize our lock.
-+*
-+***************************************************************************/
-+
-+static void connected_init(void)
-+{
-+ if (!g_once_init) {
-+ mutex_init(&g_connected_mutex);
-+ g_once_init = 1;
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* This function is used to defer initialization until the vchiq stack is
-+* initialized. If the stack is already initialized, then the callback will
-+* be made immediately, otherwise it will be deferred until
-+* vchiq_call_connected_callbacks is called.
-+*
-+***************************************************************************/
-+
-+void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback)
-+{
-+ connected_init();
-+
-+ if (mutex_lock_interruptible(&g_connected_mutex) != 0)
-+ return;
-+
-+ if (g_connected)
-+ /* We're already connected. Call the callback immediately. */
-+
-+ callback();
-+ else {
-+ if (g_num_deferred_callbacks >= MAX_CALLBACKS)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "There already %d callback registered - "
-+ "please increase MAX_CALLBACKS",
-+ g_num_deferred_callbacks);
-+ else {
-+ g_deferred_callback[g_num_deferred_callbacks] =
-+ callback;
-+ g_num_deferred_callbacks++;
-+ }
-+ }
-+ mutex_unlock(&g_connected_mutex);
-+}
-+
-+/****************************************************************************
-+*
-+* This function is called by the vchiq stack once it has been connected to
-+* the videocore and clients can start to use the stack.
-+*
-+***************************************************************************/
-+
-+void vchiq_call_connected_callbacks(void)
-+{
-+ int i;
-+
-+ connected_init();
-+
-+ if (mutex_lock_interruptible(&g_connected_mutex) != 0)
-+ return;
-+
-+ for (i = 0; i < g_num_deferred_callbacks; i++)
-+ g_deferred_callback[i]();
-+
-+ g_num_deferred_callbacks = 0;
-+ g_connected = 1;
-+ mutex_unlock(&g_connected_mutex);
-+}
-+EXPORT_SYMBOL(vchiq_add_connected_callback);
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,50 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_CONNECTED_H
-+#define VCHIQ_CONNECTED_H
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void);
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback);
-+void vchiq_call_connected_callbacks(void);
-+
-+#endif /* VCHIQ_CONNECTED_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,3862 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "vchiq_core.h"
-+#include "vchiq_killable.h"
-+
-+#define VCHIQ_SLOT_HANDLER_STACK 8192
-+
-+#define HANDLE_STATE_SHIFT 12
-+
-+#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index))
-+#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index))
-+#define SLOT_INDEX_FROM_DATA(state, data) \
-+ (((unsigned int)((char *)data - (char *)state->slot_data)) / \
-+ VCHIQ_SLOT_SIZE)
-+#define SLOT_INDEX_FROM_INFO(state, info) \
-+ ((unsigned int)(info - state->slot_info))
-+#define SLOT_QUEUE_INDEX_FROM_POS(pos) \
-+ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE))
-+
-+#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1))
-+
-+#define SRVTRACE_LEVEL(srv) \
-+ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level)
-+#define SRVTRACE_ENABLED(srv, lev) \
-+ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev)))
-+
-+struct vchiq_open_payload {
-+ int fourcc;
-+ int client_id;
-+ short version;
-+ short version_min;
-+};
-+
-+struct vchiq_openack_payload {
-+ short version;
-+};
-+
-+/* we require this for consistency between endpoints */
-+vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8);
-+vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T)));
-+vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS));
-+vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS));
-+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES));
-+vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN);
-+
-+/* Run time control of log level, based on KERN_XXX level. */
-+int vchiq_core_log_level = VCHIQ_LOG_DEFAULT;
-+int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT;
-+int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT;
-+
-+static atomic_t pause_bulks_count = ATOMIC_INIT(0);
-+
-+static DEFINE_SPINLOCK(service_spinlock);
-+DEFINE_SPINLOCK(bulk_waiter_spinlock);
-+DEFINE_SPINLOCK(quota_spinlock);
-+
-+VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES];
-+static unsigned int handle_seq;
-+
-+static const char *const srvstate_names[] = {
-+ "FREE",
-+ "HIDDEN",
-+ "LISTENING",
-+ "OPENING",
-+ "OPEN",
-+ "OPENSYNC",
-+ "CLOSESENT",
-+ "CLOSERECVD",
-+ "CLOSEWAIT",
-+ "CLOSED"
-+};
-+
-+static const char *const reason_names[] = {
-+ "SERVICE_OPENED",
-+ "SERVICE_CLOSED",
-+ "MESSAGE_AVAILABLE",
-+ "BULK_TRANSMIT_DONE",
-+ "BULK_RECEIVE_DONE",
-+ "BULK_TRANSMIT_ABORTED",
-+ "BULK_RECEIVE_ABORTED"
-+};
-+
-+static const char *const conn_state_names[] = {
-+ "DISCONNECTED",
-+ "CONNECTING",
-+ "CONNECTED",
-+ "PAUSING",
-+ "PAUSE_SENT",
-+ "PAUSED",
-+ "RESUMING",
-+ "PAUSE_TIMEOUT",
-+ "RESUME_TIMEOUT"
-+};
-+
-+
-+static void
-+release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header);
-+
-+static const char *msg_type_str(unsigned int msg_type)
-+{
-+ switch (msg_type) {
-+ case VCHIQ_MSG_PADDING: return "PADDING";
-+ case VCHIQ_MSG_CONNECT: return "CONNECT";
-+ case VCHIQ_MSG_OPEN: return "OPEN";
-+ case VCHIQ_MSG_OPENACK: return "OPENACK";
-+ case VCHIQ_MSG_CLOSE: return "CLOSE";
-+ case VCHIQ_MSG_DATA: return "DATA";
-+ case VCHIQ_MSG_BULK_RX: return "BULK_RX";
-+ case VCHIQ_MSG_BULK_TX: return "BULK_TX";
-+ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE";
-+ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE";
-+ case VCHIQ_MSG_PAUSE: return "PAUSE";
-+ case VCHIQ_MSG_RESUME: return "RESUME";
-+ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE";
-+ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE";
-+ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE";
-+ }
-+ return "???";
-+}
-+
-+static inline void
-+vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate)
-+{
-+ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s",
-+ service->state->id, service->localport,
-+ srvstate_names[service->srvstate],
-+ srvstate_names[newstate]);
-+ service->srvstate = newstate;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service;
-+
-+ spin_lock(&service_spinlock);
-+ service = handle_to_service(handle);
-+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (service->handle == handle)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid service handle 0x%x", handle);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_service_by_port(VCHIQ_STATE_T *state, int localport)
-+{
-+ VCHIQ_SERVICE_T *service = NULL;
-+ if ((unsigned int)localport <= VCHIQ_PORT_MAX) {
-+ spin_lock(&service_spinlock);
-+ service = state->services[localport];
-+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+ }
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid port %d", localport);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle) {
-+ VCHIQ_SERVICE_T *service;
-+
-+ spin_lock(&service_spinlock);
-+ service = handle_to_service(handle);
-+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (service->handle == handle) &&
-+ (service->instance == instance)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid service handle 0x%x", handle);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle) {
-+ VCHIQ_SERVICE_T *service;
-+
-+ spin_lock(&service_spinlock);
-+ service = handle_to_service(handle);
-+ if (service &&
-+ ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) &&
-+ (service->handle == handle) &&
-+ (service->instance == instance)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid service handle 0x%x", handle);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance,
-+ int *pidx)
-+{
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int idx = *pidx;
-+
-+ spin_lock(&service_spinlock);
-+ while (idx < state->unused_service) {
-+ VCHIQ_SERVICE_T *srv = state->services[idx++];
-+ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (srv->instance == instance)) {
-+ service = srv;
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ break;
-+ }
-+ }
-+ spin_unlock(&service_spinlock);
-+
-+ *pidx = idx;
-+
-+ return service;
-+}
-+
-+void
-+lock_service(VCHIQ_SERVICE_T *service)
-+{
-+ spin_lock(&service_spinlock);
-+ BUG_ON(!service || (service->ref_count == 0));
-+ if (service)
-+ service->ref_count++;
-+ spin_unlock(&service_spinlock);
-+}
-+
-+void
-+unlock_service(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ spin_lock(&service_spinlock);
-+ BUG_ON(!service || (service->ref_count == 0));
-+ if (service && service->ref_count) {
-+ service->ref_count--;
-+ if (!service->ref_count) {
-+ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE);
-+ state->services[service->localport] = NULL;
-+ } else
-+ service = NULL;
-+ }
-+ spin_unlock(&service_spinlock);
-+
-+ if (service && service->userdata_term)
-+ service->userdata_term(service->base.userdata);
-+
-+ kfree(service);
-+}
-+
-+int
-+vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ int id;
-+
-+ id = service ? service->client_id : 0;
-+ if (service)
-+ unlock_service(service);
-+
-+ return id;
-+}
-+
-+void *
-+vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service = handle_to_service(handle);
-+
-+ return service ? service->base.userdata : NULL;
-+}
-+
-+int
-+vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service = handle_to_service(handle);
-+
-+ return service ? service->base.fourcc : 0;
-+}
-+
-+static void
-+mark_service_closing_internal(VCHIQ_SERVICE_T *service, int sh_thread)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ VCHIQ_SERVICE_QUOTA_T *service_quota;
-+
-+ service->closing = 1;
-+
-+ /* Synchronise with other threads. */
-+ mutex_lock(&state->recycle_mutex);
-+ mutex_unlock(&state->recycle_mutex);
-+ if (!sh_thread || (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT)) {
-+ /* If we're pausing then the slot_mutex is held until resume
-+ * by the slot handler. Therefore don't try to acquire this
-+ * mutex if we're the slot handler and in the pause sent state.
-+ * We don't need to in this case anyway. */
-+ mutex_lock(&state->slot_mutex);
-+ mutex_unlock(&state->slot_mutex);
-+ }
-+
-+ /* Unblock any sending thread. */
-+ service_quota = &state->service_quotas[service->localport];
-+ up(&service_quota->quota_event);
-+}
-+
-+static void
-+mark_service_closing(VCHIQ_SERVICE_T *service)
-+{
-+ mark_service_closing_internal(service, 0);
-+}
-+
-+static inline VCHIQ_STATUS_T
-+make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header, void *bulk_userdata)
-+{
-+ VCHIQ_STATUS_T status;
-+ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)",
-+ service->state->id, service->localport, reason_names[reason],
-+ (unsigned int)header, (unsigned int)bulk_userdata);
-+ status = service->base.callback(reason, header, service->handle,
-+ bulk_userdata);
-+ if (status == VCHIQ_ERROR) {
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: ignoring ERROR from callback to service %x",
-+ service->state->id, service->handle);
-+ status = VCHIQ_SUCCESS;
-+ }
-+ return status;
-+}
-+
-+inline void
-+vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate)
-+{
-+ VCHIQ_CONNSTATE_T oldstate = state->conn_state;
-+ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id,
-+ conn_state_names[oldstate],
-+ conn_state_names[newstate]);
-+ state->conn_state = newstate;
-+ vchiq_platform_conn_state_changed(state, oldstate, newstate);
-+}
-+
-+static inline void
-+remote_event_create(REMOTE_EVENT_T *event)
-+{
-+ event->armed = 0;
-+ /* Don't clear the 'fired' flag because it may already have been set
-+ ** by the other side. */
-+ sema_init(event->event, 0);
-+}
-+
-+static inline void
-+remote_event_destroy(REMOTE_EVENT_T *event)
-+{
-+ (void)event;
-+}
-+
-+static inline int
-+remote_event_wait(REMOTE_EVENT_T *event)
-+{
-+ if (!event->fired) {
-+ event->armed = 1;
-+ dsb();
-+ if (!event->fired) {
-+ if (down_interruptible(event->event) != 0) {
-+ event->armed = 0;
-+ return 0;
-+ }
-+ }
-+ event->armed = 0;
-+ wmb();
-+ }
-+
-+ event->fired = 0;
-+ return 1;
-+}
-+
-+static inline void
-+remote_event_signal_local(REMOTE_EVENT_T *event)
-+{
-+ event->armed = 0;
-+ up(event->event);
-+}
-+
-+static inline void
-+remote_event_poll(REMOTE_EVENT_T *event)
-+{
-+ if (event->fired && event->armed)
-+ remote_event_signal_local(event);
-+}
-+
-+void
-+remote_event_pollall(VCHIQ_STATE_T *state)
-+{
-+ remote_event_poll(&state->local->sync_trigger);
-+ remote_event_poll(&state->local->sync_release);
-+ remote_event_poll(&state->local->trigger);
-+ remote_event_poll(&state->local->recycle);
-+}
-+
-+/* Round up message sizes so that any space at the end of a slot is always big
-+** enough for a header. This relies on header size being a power of two, which
-+** has been verified earlier by a static assertion. */
-+
-+static inline unsigned int
-+calc_stride(unsigned int size)
-+{
-+ /* Allow room for the header */
-+ size += sizeof(VCHIQ_HEADER_T);
-+
-+ /* Round up */
-+ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T)
-+ - 1);
-+}
-+
-+/* Called by the slot handler thread */
-+static VCHIQ_SERVICE_T *
-+get_listening_service(VCHIQ_STATE_T *state, int fourcc)
-+{
-+ int i;
-+
-+ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID);
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ if (service &&
-+ (service->public_fourcc == fourcc) &&
-+ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
-+ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) &&
-+ (service->remoteport == VCHIQ_PORT_FREE)))) {
-+ lock_service(service);
-+ return service;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+/* Called by the slot handler thread */
-+static VCHIQ_SERVICE_T *
-+get_connected_service(VCHIQ_STATE_T *state, unsigned int port)
-+{
-+ int i;
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN)
-+ && (service->remoteport == port)) {
-+ lock_service(service);
-+ return service;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+inline void
-+request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type)
-+{
-+ uint32_t value;
-+
-+ if (service) {
-+ do {
-+ value = atomic_read(&service->poll_flags);
-+ } while (atomic_cmpxchg(&service->poll_flags, value,
-+ value | (1 << poll_type)) != value);
-+
-+ do {
-+ value = atomic_read(&state->poll_services[
-+ service->localport>>5]);
-+ } while (atomic_cmpxchg(
-+ &state->poll_services[service->localport>>5],
-+ value, value | (1 << (service->localport & 0x1f)))
-+ != value);
-+ }
-+
-+ state->poll_needed = 1;
-+ wmb();
-+
-+ /* ... and ensure the slot handler runs. */
-+ remote_event_signal_local(&state->local->trigger);
-+}
-+
-+/* Called from queue_message, by the slot handler and application threads,
-+** with slot_mutex held */
-+static VCHIQ_HEADER_T *
-+reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking)
-+{
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ int tx_pos = state->local_tx_pos;
-+ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK);
-+
-+ if (space > slot_space) {
-+ VCHIQ_HEADER_T *header;
-+ /* Fill the remaining space with padding */
-+ WARN_ON(state->tx_data == NULL);
-+ header = (VCHIQ_HEADER_T *)
-+ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK));
-+ header->msgid = VCHIQ_MSGID_PADDING;
-+ header->size = slot_space - sizeof(VCHIQ_HEADER_T);
-+
-+ tx_pos += slot_space;
-+ }
-+
-+ /* If necessary, get the next slot. */
-+ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) {
-+ int slot_index;
-+
-+ /* If there is no free slot... */
-+
-+ if (down_trylock(&state->slot_available_event) != 0) {
-+ /* ...wait for one. */
-+
-+ VCHIQ_STATS_INC(state, slot_stalls);
-+
-+ /* But first, flush through the last slot. */
-+ state->local_tx_pos = tx_pos;
-+ local->tx_pos = tx_pos;
-+ remote_event_signal(&state->remote->trigger);
-+
-+ if (!is_blocking ||
-+ (down_interruptible(
-+ &state->slot_available_event) != 0))
-+ return NULL; /* No space available */
-+ }
-+
-+ BUG_ON(tx_pos ==
-+ (state->slot_queue_available * VCHIQ_SLOT_SIZE));
-+
-+ slot_index = local->slot_queue[
-+ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) &
-+ VCHIQ_SLOT_QUEUE_MASK];
-+ state->tx_data =
-+ (char *)SLOT_DATA_FROM_INDEX(state, slot_index);
-+ }
-+
-+ state->local_tx_pos = tx_pos + space;
-+
-+ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK));
-+}
-+
-+/* Called by the recycle thread. */
-+static void
-+process_free_queue(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)];
-+ int slot_queue_available;
-+
-+ /* Use a read memory barrier to ensure that any state that may have
-+ ** been modified by another thread is not masked by stale prefetched
-+ ** values. */
-+ rmb();
-+
-+ /* Find slots which have been freed by the other side, and return them
-+ ** to the available queue. */
-+ slot_queue_available = state->slot_queue_available;
-+
-+ while (slot_queue_available != local->slot_queue_recycle) {
-+ unsigned int pos;
-+ int slot_index = local->slot_queue[slot_queue_available++ &
-+ VCHIQ_SLOT_QUEUE_MASK];
-+ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index);
-+ int data_found = 0;
-+
-+ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x",
-+ state->id, slot_index, (unsigned int)data,
-+ local->slot_queue_recycle, slot_queue_available);
-+
-+ /* Initialise the bitmask for services which have used this
-+ ** slot */
-+ BITSET_ZERO(service_found);
-+
-+ pos = 0;
-+
-+ while (pos < VCHIQ_SLOT_SIZE) {
-+ VCHIQ_HEADER_T *header =
-+ (VCHIQ_HEADER_T *)(data + pos);
-+ int msgid = header->msgid;
-+ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) {
-+ int port = VCHIQ_MSG_SRCPORT(msgid);
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &state->service_quotas[port];
-+ int count;
-+ spin_lock(&quota_spinlock);
-+ count = service_quota->message_use_count;
-+ if (count > 0)
-+ service_quota->message_use_count =
-+ count - 1;
-+ spin_unlock(&quota_spinlock);
-+
-+ if (count == service_quota->message_quota)
-+ /* Signal the service that it
-+ ** has dropped below its quota
-+ */
-+ up(&service_quota->quota_event);
-+ else if (count == 0) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "service %d "
-+ "message_use_count=%d "
-+ "(header %x, msgid %x, "
-+ "header->msgid %x, "
-+ "header->size %x)",
-+ port,
-+ service_quota->
-+ message_use_count,
-+ (unsigned int)header, msgid,
-+ header->msgid,
-+ header->size);
-+ WARN(1, "invalid message use count\n");
-+ }
-+ if (!BITSET_IS_SET(service_found, port)) {
-+ /* Set the found bit for this service */
-+ BITSET_SET(service_found, port);
-+
-+ spin_lock(&quota_spinlock);
-+ count = service_quota->slot_use_count;
-+ if (count > 0)
-+ service_quota->slot_use_count =
-+ count - 1;
-+ spin_unlock(&quota_spinlock);
-+
-+ if (count > 0) {
-+ /* Signal the service in case
-+ ** it has dropped below its
-+ ** quota */
-+ up(&service_quota->quota_event);
-+ vchiq_log_trace(
-+ vchiq_core_log_level,
-+ "%d: pfq:%d %x@%x - "
-+ "slot_use->%d",
-+ state->id, port,
-+ header->size,
-+ (unsigned int)header,
-+ count - 1);
-+ } else {
-+ vchiq_log_error(
-+ vchiq_core_log_level,
-+ "service %d "
-+ "slot_use_count"
-+ "=%d (header %x"
-+ ", msgid %x, "
-+ "header->msgid"
-+ " %x, header->"
-+ "size %x)",
-+ port, count,
-+ (unsigned int)header,
-+ msgid,
-+ header->msgid,
-+ header->size);
-+ WARN(1, "bad slot use count\n");
-+ }
-+ }
-+
-+ data_found = 1;
-+ }
-+
-+ pos += calc_stride(header->size);
-+ if (pos > VCHIQ_SLOT_SIZE) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "pfq - pos %x: header %x, msgid %x, "
-+ "header->msgid %x, header->size %x",
-+ pos, (unsigned int)header, msgid,
-+ header->msgid, header->size);
-+ WARN(1, "invalid slot position\n");
-+ }
-+ }
-+
-+ if (data_found) {
-+ int count;
-+ spin_lock(&quota_spinlock);
-+ count = state->data_use_count;
-+ if (count > 0)
-+ state->data_use_count =
-+ count - 1;
-+ spin_unlock(&quota_spinlock);
-+ if (count == state->data_quota)
-+ up(&state->data_quota_event);
-+ }
-+
-+ state->slot_queue_available = slot_queue_available;
-+ up(&state->slot_available_event);
-+ }
-+}
-+
-+/* Called by the slot handler and application threads */
-+static VCHIQ_STATUS_T
-+queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ int msgid, const VCHIQ_ELEMENT_T *elements,
-+ int count, int size, int is_blocking)
-+{
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL;
-+ VCHIQ_HEADER_T *header;
-+ int type = VCHIQ_MSG_TYPE(msgid);
-+
-+ unsigned int stride;
-+
-+ local = state->local;
-+
-+ stride = calc_stride(size);
-+
-+ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE));
-+
-+ if ((type != VCHIQ_MSG_RESUME) &&
-+ (mutex_lock_interruptible(&state->slot_mutex) != 0))
-+ return VCHIQ_RETRY;
-+
-+ if (type == VCHIQ_MSG_DATA) {
-+ int tx_end_index;
-+
-+ BUG_ON(!service);
-+
-+ if (service->closing) {
-+ /* The service has been closed */
-+ mutex_unlock(&state->slot_mutex);
-+ return VCHIQ_ERROR;
-+ }
-+
-+ service_quota = &state->service_quotas[service->localport];
-+
-+ spin_lock(&quota_spinlock);
-+
-+ /* Ensure this service doesn't use more than its quota of
-+ ** messages or slots */
-+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
-+ state->local_tx_pos + stride - 1);
-+
-+ /* Ensure data messages don't use more than their quota of
-+ ** slots */
-+ while ((tx_end_index != state->previous_data_index) &&
-+ (state->data_use_count == state->data_quota)) {
-+ VCHIQ_STATS_INC(state, data_stalls);
-+ spin_unlock(&quota_spinlock);
-+ mutex_unlock(&state->slot_mutex);
-+
-+ if (down_interruptible(&state->data_quota_event)
-+ != 0)
-+ return VCHIQ_RETRY;
-+
-+ mutex_lock(&state->slot_mutex);
-+ spin_lock(&quota_spinlock);
-+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
-+ state->local_tx_pos + stride - 1);
-+ if ((tx_end_index == state->previous_data_index) ||
-+ (state->data_use_count < state->data_quota)) {
-+ /* Pass the signal on to other waiters */
-+ up(&state->data_quota_event);
-+ break;
-+ }
-+ }
-+
-+ while ((service_quota->message_use_count ==
-+ service_quota->message_quota) ||
-+ ((tx_end_index != service_quota->previous_tx_index) &&
-+ (service_quota->slot_use_count ==
-+ service_quota->slot_quota))) {
-+ spin_unlock(&quota_spinlock);
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: qm:%d %s,%x - quota stall "
-+ "(msg %d, slot %d)",
-+ state->id, service->localport,
-+ msg_type_str(type), size,
-+ service_quota->message_use_count,
-+ service_quota->slot_use_count);
-+ VCHIQ_SERVICE_STATS_INC(service, quota_stalls);
-+ mutex_unlock(&state->slot_mutex);
-+ if (down_interruptible(&service_quota->quota_event)
-+ != 0)
-+ return VCHIQ_RETRY;
-+ if (service->closing)
-+ return VCHIQ_ERROR;
-+ if (mutex_lock_interruptible(&state->slot_mutex) != 0)
-+ return VCHIQ_RETRY;
-+ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) {
-+ /* The service has been closed */
-+ mutex_unlock(&state->slot_mutex);
-+ return VCHIQ_ERROR;
-+ }
-+ spin_lock(&quota_spinlock);
-+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
-+ state->local_tx_pos + stride - 1);
-+ }
-+
-+ spin_unlock(&quota_spinlock);
-+ }
-+
-+ header = reserve_space(state, stride, is_blocking);
-+
-+ if (!header) {
-+ if (service)
-+ VCHIQ_SERVICE_STATS_INC(service, slot_stalls);
-+ mutex_unlock(&state->slot_mutex);
-+ return VCHIQ_RETRY;
-+ }
-+
-+ if (type == VCHIQ_MSG_DATA) {
-+ int i, pos;
-+ int tx_end_index;
-+ int slot_use_count;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: qm %s@%x,%x (%d->%d)",
-+ state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+
-+ BUG_ON(!service);
-+
-+ for (i = 0, pos = 0; i < (unsigned int)count;
-+ pos += elements[i++].size)
-+ if (elements[i].size) {
-+ if (vchiq_copy_from_user
-+ (header->data + pos, elements[i].data,
-+ (size_t) elements[i].size) !=
-+ VCHIQ_SUCCESS) {
-+ mutex_unlock(&state->slot_mutex);
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ error_count);
-+ return VCHIQ_ERROR;
-+ }
-+ if (i == 0) {
-+ if (SRVTRACE_ENABLED(service,
-+ VCHIQ_LOG_INFO))
-+ vchiq_log_dump_mem("Sent", 0,
-+ header->data + pos,
-+ min(64u,
-+ elements[0].size));
-+ }
-+ }
-+
-+ spin_lock(&quota_spinlock);
-+ service_quota->message_use_count++;
-+
-+ tx_end_index =
-+ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1);
-+
-+ /* If this transmission can't fit in the last slot used by any
-+ ** service, the data_use_count must be increased. */
-+ if (tx_end_index != state->previous_data_index) {
-+ state->previous_data_index = tx_end_index;
-+ state->data_use_count++;
-+ }
-+
-+ /* If this isn't the same slot last used by this service,
-+ ** the service's slot_use_count must be increased. */
-+ if (tx_end_index != service_quota->previous_tx_index) {
-+ service_quota->previous_tx_index = tx_end_index;
-+ slot_use_count = ++service_quota->slot_use_count;
-+ } else {
-+ slot_use_count = 0;
-+ }
-+
-+ spin_unlock(&quota_spinlock);
-+
-+ if (slot_use_count)
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)",
-+ state->id, service->localport,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size,
-+ slot_use_count, header);
-+
-+ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
-+ } else {
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: qm %s@%x,%x (%d->%d)", state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+ if (size != 0) {
-+ WARN_ON(!((count == 1) && (size == elements[0].size)));
-+ memcpy(header->data, elements[0].data,
-+ elements[0].size);
-+ }
-+ VCHIQ_STATS_INC(state, ctrl_tx_count);
-+ }
-+
-+ header->msgid = msgid;
-+ header->size = size;
-+
-+ {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d",
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ VCHIQ_MSG_TYPE(msgid),
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid),
-+ size);
-+ }
-+
-+ /* Make sure the new header is visible to the peer. */
-+ wmb();
-+
-+ /* Make the new tx_pos visible to the peer. */
-+ local->tx_pos = state->local_tx_pos;
-+ wmb();
-+
-+ if (service && (type == VCHIQ_MSG_CLOSE))
-+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT);
-+
-+ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE)
-+ mutex_unlock(&state->slot_mutex);
-+
-+ remote_event_signal(&state->remote->trigger);
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+/* Called by the slot handler and application threads */
-+static VCHIQ_STATUS_T
-+queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ int msgid, const VCHIQ_ELEMENT_T *elements,
-+ int count, int size, int is_blocking)
-+{
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_HEADER_T *header;
-+
-+ local = state->local;
-+
-+ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) &&
-+ (mutex_lock_interruptible(&state->sync_mutex) != 0))
-+ return VCHIQ_RETRY;
-+
-+ remote_event_wait(&local->sync_release);
-+
-+ rmb();
-+
-+ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
-+ local->slot_sync);
-+
-+ {
-+ int oldmsgid = header->msgid;
-+ if (oldmsgid != VCHIQ_MSGID_PADDING)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: qms - msgid %x, not PADDING",
-+ state->id, oldmsgid);
-+ }
-+
-+ if (service) {
-+ int i, pos;
-+
-+ vchiq_log_info(vchiq_sync_log_level,
-+ "%d: qms %s@%x,%x (%d->%d)", state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+
-+ for (i = 0, pos = 0; i < (unsigned int)count;
-+ pos += elements[i++].size)
-+ if (elements[i].size) {
-+ if (vchiq_copy_from_user
-+ (header->data + pos, elements[i].data,
-+ (size_t) elements[i].size) !=
-+ VCHIQ_SUCCESS) {
-+ mutex_unlock(&state->sync_mutex);
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ error_count);
-+ return VCHIQ_ERROR;
-+ }
-+ if (i == 0) {
-+ if (vchiq_sync_log_level >=
-+ VCHIQ_LOG_TRACE)
-+ vchiq_log_dump_mem("Sent Sync",
-+ 0, header->data + pos,
-+ min(64u,
-+ elements[0].size));
-+ }
-+ }
-+
-+ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
-+ } else {
-+ vchiq_log_info(vchiq_sync_log_level,
-+ "%d: qms %s@%x,%x (%d->%d)", state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+ if (size != 0) {
-+ WARN_ON(!((count == 1) && (size == elements[0].size)));
-+ memcpy(header->data, elements[0].data,
-+ elements[0].size);
-+ }
-+ VCHIQ_STATS_INC(state, ctrl_tx_count);
-+ }
-+
-+ header->size = size;
-+ header->msgid = msgid;
-+
-+ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+
-+ vchiq_log_trace(vchiq_sync_log_level,
-+ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d",
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ VCHIQ_MSG_TYPE(msgid),
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid),
-+ size);
-+ }
-+
-+ /* Make sure the new header is visible to the peer. */
-+ wmb();
-+
-+ remote_event_signal(&state->remote->sync_trigger);
-+
-+ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE)
-+ mutex_unlock(&state->sync_mutex);
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+static inline void
-+claim_slot(VCHIQ_SLOT_INFO_T *slot)
-+{
-+ slot->use_count++;
-+}
-+
-+static void
-+release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info,
-+ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service)
-+{
-+ int release_count;
-+
-+ mutex_lock(&state->recycle_mutex);
-+
-+ if (header) {
-+ int msgid = header->msgid;
-+ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) ||
-+ (service && service->closing)) {
-+ mutex_unlock(&state->recycle_mutex);
-+ return;
-+ }
-+
-+ /* Rewrite the message header to prevent a double
-+ ** release */
-+ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED;
-+ }
-+
-+ release_count = slot_info->release_count;
-+ slot_info->release_count = ++release_count;
-+
-+ if (release_count == slot_info->use_count) {
-+ int slot_queue_recycle;
-+ /* Add to the freed queue */
-+
-+ /* A read barrier is necessary here to prevent speculative
-+ ** fetches of remote->slot_queue_recycle from overtaking the
-+ ** mutex. */
-+ rmb();
-+
-+ slot_queue_recycle = state->remote->slot_queue_recycle;
-+ state->remote->slot_queue[slot_queue_recycle &
-+ VCHIQ_SLOT_QUEUE_MASK] =
-+ SLOT_INDEX_FROM_INFO(state, slot_info);
-+ state->remote->slot_queue_recycle = slot_queue_recycle + 1;
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: release_slot %d - recycle->%x",
-+ state->id, SLOT_INDEX_FROM_INFO(state, slot_info),
-+ state->remote->slot_queue_recycle);
-+
-+ /* A write barrier is necessary, but remote_event_signal
-+ ** contains one. */
-+ remote_event_signal(&state->remote->recycle);
-+ }
-+
-+ mutex_unlock(&state->recycle_mutex);
-+}
-+
-+/* Called by the slot handler - don't hold the bulk mutex */
-+static VCHIQ_STATUS_T
-+notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue,
-+ int retry_poll)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: nb:%d %cx - p=%x rn=%x r=%x",
-+ service->state->id, service->localport,
-+ (queue == &service->bulk_tx) ? 't' : 'r',
-+ queue->process, queue->remote_notify, queue->remove);
-+
-+ if (service->state->is_master) {
-+ while (queue->remote_notify != queue->process) {
-+ VCHIQ_BULK_T *bulk =
-+ &queue->bulks[BULK_INDEX(queue->remote_notify)];
-+ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ?
-+ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE;
-+ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport,
-+ service->remoteport);
-+ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 };
-+ /* Only reply to non-dummy bulk requests */
-+ if (bulk->remote_data) {
-+ status = queue_message(service->state, NULL,
-+ msgid, &element, 1, 4, 0);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+ queue->remote_notify++;
-+ }
-+ } else {
-+ queue->remote_notify = queue->process;
-+ }
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ while (queue->remove != queue->remote_notify) {
-+ VCHIQ_BULK_T *bulk =
-+ &queue->bulks[BULK_INDEX(queue->remove)];
-+
-+ /* Only generate callbacks for non-dummy bulk
-+ ** requests, and non-terminated services */
-+ if (bulk->data && service->instance) {
-+ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) {
-+ if (bulk->dir == VCHIQ_BULK_TRANSMIT) {
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ bulk_tx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service,
-+ bulk_tx_bytes,
-+ bulk->actual);
-+ } else {
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ bulk_rx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service,
-+ bulk_rx_bytes,
-+ bulk->actual);
-+ }
-+ } else {
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ bulk_aborted_count);
-+ }
-+ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) {
-+ struct bulk_waiter *waiter;
-+ spin_lock(&bulk_waiter_spinlock);
-+ waiter = bulk->userdata;
-+ if (waiter) {
-+ waiter->actual = bulk->actual;
-+ up(&waiter->event);
-+ }
-+ spin_unlock(&bulk_waiter_spinlock);
-+ } else if (bulk->mode ==
-+ VCHIQ_BULK_MODE_CALLBACK) {
-+ VCHIQ_REASON_T reason = (bulk->dir ==
-+ VCHIQ_BULK_TRANSMIT) ?
-+ ((bulk->actual ==
-+ VCHIQ_BULK_ACTUAL_ABORTED) ?
-+ VCHIQ_BULK_TRANSMIT_ABORTED :
-+ VCHIQ_BULK_TRANSMIT_DONE) :
-+ ((bulk->actual ==
-+ VCHIQ_BULK_ACTUAL_ABORTED) ?
-+ VCHIQ_BULK_RECEIVE_ABORTED :
-+ VCHIQ_BULK_RECEIVE_DONE);
-+ status = make_service_callback(service,
-+ reason, NULL, bulk->userdata);
-+ if (status == VCHIQ_RETRY)
-+ break;
-+ }
-+ }
-+
-+ queue->remove++;
-+ up(&service->bulk_remove_event);
-+ }
-+ if (!retry_poll)
-+ status = VCHIQ_SUCCESS;
-+ }
-+
-+ if (status == VCHIQ_RETRY)
-+ request_poll(service->state, service,
-+ (queue == &service->bulk_tx) ?
-+ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
-+
-+ return status;
-+}
-+
-+/* Called by the slot handler thread */
-+static void
-+poll_services(VCHIQ_STATE_T *state)
-+{
-+ int group, i;
-+
-+ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) {
-+ uint32_t flags;
-+ flags = atomic_xchg(&state->poll_services[group], 0);
-+ for (i = 0; flags; i++) {
-+ if (flags & (1 << i)) {
-+ VCHIQ_SERVICE_T *service =
-+ find_service_by_port(state,
-+ (group<<5) + i);
-+ uint32_t service_flags;
-+ flags &= ~(1 << i);
-+ if (!service)
-+ continue;
-+ service_flags =
-+ atomic_xchg(&service->poll_flags, 0);
-+ if (service_flags &
-+ (1 << VCHIQ_POLL_REMOVE)) {
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: ps - remove %d<->%d",
-+ state->id, service->localport,
-+ service->remoteport);
-+
-+ /* Make it look like a client, because
-+ it must be removed and not left in
-+ the LISTENING state. */
-+ service->public_fourcc =
-+ VCHIQ_FOURCC_INVALID;
-+
-+ if (vchiq_close_service_internal(
-+ service, 0/*!close_recvd*/) !=
-+ VCHIQ_SUCCESS)
-+ request_poll(state, service,
-+ VCHIQ_POLL_REMOVE);
-+ } else if (service_flags &
-+ (1 << VCHIQ_POLL_TERMINATE)) {
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: ps - terminate %d<->%d",
-+ state->id, service->localport,
-+ service->remoteport);
-+ if (vchiq_close_service_internal(
-+ service, 0/*!close_recvd*/) !=
-+ VCHIQ_SUCCESS)
-+ request_poll(state, service,
-+ VCHIQ_POLL_TERMINATE);
-+ }
-+ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY))
-+ notify_bulks(service,
-+ &service->bulk_tx,
-+ 1/*retry_poll*/);
-+ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY))
-+ notify_bulks(service,
-+ &service->bulk_rx,
-+ 1/*retry_poll*/);
-+ unlock_service(service);
-+ }
-+ }
-+ }
-+}
-+
-+/* Called by the slot handler or application threads, holding the bulk mutex. */
-+static int
-+resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ int resolved = 0;
-+ int rc;
-+
-+ while ((queue->process != queue->local_insert) &&
-+ (queue->process != queue->remote_insert)) {
-+ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)];
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: rb:%d %cx - li=%x ri=%x p=%x",
-+ state->id, service->localport,
-+ (queue == &service->bulk_tx) ? 't' : 'r',
-+ queue->local_insert, queue->remote_insert,
-+ queue->process);
-+
-+ WARN_ON(!((int)(queue->local_insert - queue->process) > 0));
-+ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0));
-+
-+ rc = mutex_lock_interruptible(&state->bulk_transfer_mutex);
-+ if (rc != 0)
-+ break;
-+
-+ vchiq_transfer_bulk(bulk);
-+ mutex_unlock(&state->bulk_transfer_mutex);
-+
-+ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) {
-+ const char *header = (queue == &service->bulk_tx) ?
-+ "Send Bulk to" : "Recv Bulk from";
-+ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED)
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "%s %c%c%c%c d:%d len:%d %x<->%x",
-+ header,
-+ VCHIQ_FOURCC_AS_4CHARS(
-+ service->base.fourcc),
-+ service->remoteport,
-+ bulk->size,
-+ (unsigned int)bulk->data,
-+ (unsigned int)bulk->remote_data);
-+ else
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "%s %c%c%c%c d:%d ABORTED - tx len:%d,"
-+ " rx len:%d %x<->%x",
-+ header,
-+ VCHIQ_FOURCC_AS_4CHARS(
-+ service->base.fourcc),
-+ service->remoteport,
-+ bulk->size,
-+ bulk->remote_size,
-+ (unsigned int)bulk->data,
-+ (unsigned int)bulk->remote_data);
-+ }
-+
-+ vchiq_complete_bulk(bulk);
-+ queue->process++;
-+ resolved++;
-+ }
-+ return resolved;
-+}
-+
-+/* Called with the bulk_mutex held */
-+static void
-+abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue)
-+{
-+ int is_tx = (queue == &service->bulk_tx);
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: aob:%d %cx - li=%x ri=%x p=%x",
-+ service->state->id, service->localport, is_tx ? 't' : 'r',
-+ queue->local_insert, queue->remote_insert, queue->process);
-+
-+ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0));
-+ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0));
-+
-+ while ((queue->process != queue->local_insert) ||
-+ (queue->process != queue->remote_insert)) {
-+ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)];
-+
-+ if (queue->process == queue->remote_insert) {
-+ /* fabricate a matching dummy bulk */
-+ bulk->remote_data = NULL;
-+ bulk->remote_size = 0;
-+ queue->remote_insert++;
-+ }
-+
-+ if (queue->process != queue->local_insert) {
-+ vchiq_complete_bulk(bulk);
-+
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "%s %c%c%c%c d:%d ABORTED - tx len:%d, "
-+ "rx len:%d",
-+ is_tx ? "Send Bulk to" : "Recv Bulk from",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->remoteport,
-+ bulk->size,
-+ bulk->remote_size);
-+ } else {
-+ /* fabricate a matching dummy bulk */
-+ bulk->data = NULL;
-+ bulk->size = 0;
-+ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED;
-+ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT :
-+ VCHIQ_BULK_RECEIVE;
-+ queue->local_insert++;
-+ }
-+
-+ queue->process++;
-+ }
-+}
-+
-+/* Called from the slot handler thread */
-+static void
-+pause_bulks(VCHIQ_STATE_T *state)
-+{
-+ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) {
-+ WARN_ON_ONCE(1);
-+ atomic_set(&pause_bulks_count, 1);
-+ return;
-+ }
-+
-+ /* Block bulk transfers from all services */
-+ mutex_lock(&state->bulk_transfer_mutex);
-+}
-+
-+/* Called from the slot handler thread */
-+static void
-+resume_bulks(VCHIQ_STATE_T *state)
-+{
-+ int i;
-+ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) {
-+ WARN_ON_ONCE(1);
-+ atomic_set(&pause_bulks_count, 0);
-+ return;
-+ }
-+
-+ /* Allow bulk transfers from all services */
-+ mutex_unlock(&state->bulk_transfer_mutex);
-+
-+ if (state->deferred_bulks == 0)
-+ return;
-+
-+ /* Deal with any bulks which had to be deferred due to being in
-+ * paused state. Don't try to match up to number of deferred bulks
-+ * in case we've had something come and close the service in the
-+ * interim - just process all bulk queues for all services */
-+ vchiq_log_info(vchiq_core_log_level, "%s: processing %d deferred bulks",
-+ __func__, state->deferred_bulks);
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ int resolved_rx = 0;
-+ int resolved_tx = 0;
-+ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN))
-+ continue;
-+
-+ mutex_lock(&service->bulk_mutex);
-+ resolved_rx = resolve_bulks(service, &service->bulk_rx);
-+ resolved_tx = resolve_bulks(service, &service->bulk_tx);
-+ mutex_unlock(&service->bulk_mutex);
-+ if (resolved_rx)
-+ notify_bulks(service, &service->bulk_rx, 1);
-+ if (resolved_tx)
-+ notify_bulks(service, &service->bulk_tx, 1);
-+ }
-+ state->deferred_bulks = 0;
-+}
-+
-+static int
-+parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
-+{
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int msgid, size;
-+ int type;
-+ unsigned int localport, remoteport;
-+
-+ msgid = header->msgid;
-+ size = header->size;
-+ type = VCHIQ_MSG_TYPE(msgid);
-+ localport = VCHIQ_MSG_DSTPORT(msgid);
-+ remoteport = VCHIQ_MSG_SRCPORT(msgid);
-+ if (size >= sizeof(struct vchiq_open_payload)) {
-+ const struct vchiq_open_payload *payload =
-+ (struct vchiq_open_payload *)header->data;
-+ unsigned int fourcc;
-+
-+ fourcc = payload->fourcc;
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs OPEN@%x (%d->'%c%c%c%c')",
-+ state->id, (unsigned int)header,
-+ localport,
-+ VCHIQ_FOURCC_AS_4CHARS(fourcc));
-+
-+ service = get_listening_service(state, fourcc);
-+
-+ if (service) {
-+ /* A matching service exists */
-+ short version = payload->version;
-+ short version_min = payload->version_min;
-+ if ((service->version < version_min) ||
-+ (version < service->version_min)) {
-+ /* Version mismatch */
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("%d: service %d (%c%c%c%c) "
-+ "version mismatch - local (%d, min %d)"
-+ " vs. remote (%d, min %d)",
-+ state->id, service->localport,
-+ VCHIQ_FOURCC_AS_4CHARS(fourcc),
-+ service->version, service->version_min,
-+ version, version_min);
-+ vchiq_loud_error_footer();
-+ unlock_service(service);
-+ service = NULL;
-+ goto fail_open;
-+ }
-+ service->peer_version = version;
-+
-+ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) {
-+ struct vchiq_openack_payload ack_payload = {
-+ service->version
-+ };
-+ VCHIQ_ELEMENT_T body = {
-+ &ack_payload,
-+ sizeof(ack_payload)
-+ };
-+
-+ /* Acknowledge the OPEN */
-+ if (service->sync) {
-+ if (queue_message_sync(state, NULL,
-+ VCHIQ_MAKE_MSG(
-+ VCHIQ_MSG_OPENACK,
-+ service->localport,
-+ remoteport),
-+ &body, 1, sizeof(ack_payload),
-+ 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+ } else {
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(
-+ VCHIQ_MSG_OPENACK,
-+ service->localport,
-+ remoteport),
-+ &body, 1, sizeof(ack_payload),
-+ 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+ }
-+
-+ /* The service is now open */
-+ vchiq_set_service_state(service,
-+ service->sync ? VCHIQ_SRVSTATE_OPENSYNC
-+ : VCHIQ_SRVSTATE_OPEN);
-+ }
-+
-+ service->remoteport = remoteport;
-+ service->client_id = ((int *)header->data)[1];
-+ if (make_service_callback(service, VCHIQ_SERVICE_OPENED,
-+ NULL, NULL) == VCHIQ_RETRY) {
-+ /* Bail out if not ready */
-+ service->remoteport = VCHIQ_PORT_FREE;
-+ goto bail_not_ready;
-+ }
-+
-+ /* Success - the message has been dealt with */
-+ unlock_service(service);
-+ return 1;
-+ }
-+ }
-+
-+fail_open:
-+ /* No available service, or an invalid request - send a CLOSE */
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)),
-+ NULL, 0, 0, 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+
-+ return 1;
-+
-+bail_not_ready:
-+ if (service)
-+ unlock_service(service);
-+
-+ return 0;
-+}
-+
-+/* Called by the slot handler thread */
-+static void
-+parse_rx_slots(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_SHARED_STATE_T *remote = state->remote;
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int tx_pos;
-+ DEBUG_INITIALISE(state->local)
-+
-+ tx_pos = remote->tx_pos;
-+
-+ while (state->rx_pos != tx_pos) {
-+ VCHIQ_HEADER_T *header;
-+ int msgid, size;
-+ int type;
-+ unsigned int localport, remoteport;
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (!state->rx_data) {
-+ int rx_index;
-+ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0));
-+ rx_index = remote->slot_queue[
-+ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) &
-+ VCHIQ_SLOT_QUEUE_MASK];
-+ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state,
-+ rx_index);
-+ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index);
-+
-+ /* Initialise use_count to one, and increment
-+ ** release_count at the end of the slot to avoid
-+ ** releasing the slot prematurely. */
-+ state->rx_info->use_count = 1;
-+ state->rx_info->release_count = 0;
-+ }
-+
-+ header = (VCHIQ_HEADER_T *)(state->rx_data +
-+ (state->rx_pos & VCHIQ_SLOT_MASK));
-+ DEBUG_VALUE(PARSE_HEADER, (int)header);
-+ msgid = header->msgid;
-+ DEBUG_VALUE(PARSE_MSGID, msgid);
-+ size = header->size;
-+ type = VCHIQ_MSG_TYPE(msgid);
-+ localport = VCHIQ_MSG_DSTPORT(msgid);
-+ remoteport = VCHIQ_MSG_SRCPORT(msgid);
-+
-+ if (type != VCHIQ_MSG_DATA)
-+ VCHIQ_STATS_INC(state, ctrl_rx_count);
-+
-+ switch (type) {
-+ case VCHIQ_MSG_OPENACK:
-+ case VCHIQ_MSG_CLOSE:
-+ case VCHIQ_MSG_DATA:
-+ case VCHIQ_MSG_BULK_RX:
-+ case VCHIQ_MSG_BULK_TX:
-+ case VCHIQ_MSG_BULK_RX_DONE:
-+ case VCHIQ_MSG_BULK_TX_DONE:
-+ service = find_service_by_port(state, localport);
-+ if ((!service ||
-+ ((service->remoteport != remoteport) &&
-+ (service->remoteport != VCHIQ_PORT_FREE))) &&
-+ (localport == 0) &&
-+ (type == VCHIQ_MSG_CLOSE)) {
-+ /* This could be a CLOSE from a client which
-+ hadn't yet received the OPENACK - look for
-+ the connected service */
-+ if (service)
-+ unlock_service(service);
-+ service = get_connected_service(state,
-+ remoteport);
-+ if (service)
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) - "
-+ "found connected service %d",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ service->localport);
-+ }
-+
-+ if (!service) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) - "
-+ "invalid/closed service %d",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport, localport);
-+ goto skip_message;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d "
-+ "len:%d",
-+ msg_type_str(type), type,
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ remoteport, localport, size);
-+ if (size > 0)
-+ vchiq_log_dump_mem("Rcvd", 0, header->data,
-+ min(64, size));
-+ }
-+
-+ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size)
-+ > VCHIQ_SLOT_SIZE) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "header %x (msgid %x) - size %x too big for "
-+ "slot",
-+ (unsigned int)header, (unsigned int)msgid,
-+ (unsigned int)size);
-+ WARN(1, "oversized for slot\n");
-+ }
-+
-+ switch (type) {
-+ case VCHIQ_MSG_OPEN:
-+ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0));
-+ if (!parse_open(state, header))
-+ goto bail_not_ready;
-+ break;
-+ case VCHIQ_MSG_OPENACK:
-+ if (size >= sizeof(struct vchiq_openack_payload)) {
-+ const struct vchiq_openack_payload *payload =
-+ (struct vchiq_openack_payload *)
-+ header->data;
-+ service->peer_version = payload->version;
-+ }
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs OPENACK@%x,%x (%d->%d) v:%d",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport, service->peer_version);
-+ if (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPENING) {
-+ service->remoteport = remoteport;
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_OPEN);
-+ up(&service->remove_event);
-+ } else
-+ vchiq_log_error(vchiq_core_log_level,
-+ "OPENACK received in state %s",
-+ srvstate_names[service->srvstate]);
-+ break;
-+ case VCHIQ_MSG_CLOSE:
-+ WARN_ON(size != 0); /* There should be no data */
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs CLOSE@%x (%d->%d)",
-+ state->id, (unsigned int)header,
-+ remoteport, localport);
-+
-+ mark_service_closing_internal(service, 1);
-+
-+ if (vchiq_close_service_internal(service,
-+ 1/*close_recvd*/) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Close Service %c%c%c%c s:%u d:%d",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->localport,
-+ service->remoteport);
-+ break;
-+ case VCHIQ_MSG_DATA:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs DATA@%x,%x (%d->%d)",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport);
-+
-+ if ((service->remoteport == remoteport)
-+ && (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPEN)) {
-+ header->msgid = msgid | VCHIQ_MSGID_CLAIMED;
-+ claim_slot(state->rx_info);
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (make_service_callback(service,
-+ VCHIQ_MESSAGE_AVAILABLE, header,
-+ NULL) == VCHIQ_RETRY) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ goto bail_not_ready;
-+ }
-+ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes,
-+ size);
-+ } else {
-+ VCHIQ_STATS_INC(state, error_count);
-+ }
-+ break;
-+ case VCHIQ_MSG_CONNECT:
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs CONNECT@%x",
-+ state->id, (unsigned int)header);
-+ up(&state->connect);
-+ break;
-+ case VCHIQ_MSG_BULK_RX:
-+ case VCHIQ_MSG_BULK_TX: {
-+ VCHIQ_BULK_QUEUE_T *queue;
-+ WARN_ON(!state->is_master);
-+ queue = (type == VCHIQ_MSG_BULK_RX) ?
-+ &service->bulk_tx : &service->bulk_rx;
-+ if ((service->remoteport == remoteport)
-+ && (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPEN)) {
-+ VCHIQ_BULK_T *bulk;
-+ int resolved = 0;
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (mutex_lock_interruptible(
-+ &service->bulk_mutex) != 0) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ goto bail_not_ready;
-+ }
-+
-+ WARN_ON(!(queue->remote_insert < queue->remove +
-+ VCHIQ_NUM_SERVICE_BULKS));
-+ bulk = &queue->bulks[
-+ BULK_INDEX(queue->remote_insert)];
-+ bulk->remote_data =
-+ (void *)((int *)header->data)[0];
-+ bulk->remote_size = ((int *)header->data)[1];
-+ wmb();
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) %x@%x",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ bulk->remote_size,
-+ (unsigned int)bulk->remote_data);
-+
-+ queue->remote_insert++;
-+
-+ if (atomic_read(&pause_bulks_count)) {
-+ state->deferred_bulks++;
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%s: deferring bulk (%d)",
-+ __func__,
-+ state->deferred_bulks);
-+ if (state->conn_state !=
-+ VCHIQ_CONNSTATE_PAUSE_SENT)
-+ vchiq_log_error(
-+ vchiq_core_log_level,
-+ "%s: bulks paused in "
-+ "unexpected state %s",
-+ __func__,
-+ conn_state_names[
-+ state->conn_state]);
-+ } else if (state->conn_state ==
-+ VCHIQ_CONNSTATE_CONNECTED) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ resolved = resolve_bulks(service,
-+ queue);
-+ }
-+
-+ mutex_unlock(&service->bulk_mutex);
-+ if (resolved)
-+ notify_bulks(service, queue,
-+ 1/*retry_poll*/);
-+ }
-+ } break;
-+ case VCHIQ_MSG_BULK_RX_DONE:
-+ case VCHIQ_MSG_BULK_TX_DONE:
-+ WARN_ON(state->is_master);
-+ if ((service->remoteport == remoteport)
-+ && (service->srvstate !=
-+ VCHIQ_SRVSTATE_FREE)) {
-+ VCHIQ_BULK_QUEUE_T *queue;
-+ VCHIQ_BULK_T *bulk;
-+
-+ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ?
-+ &service->bulk_rx : &service->bulk_tx;
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (mutex_lock_interruptible(
-+ &service->bulk_mutex) != 0) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ goto bail_not_ready;
-+ }
-+ if ((int)(queue->remote_insert -
-+ queue->local_insert) >= 0) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) "
-+ "unexpected (ri=%d,li=%d)",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ queue->remote_insert,
-+ queue->local_insert);
-+ mutex_unlock(&service->bulk_mutex);
-+ break;
-+ }
-+
-+ BUG_ON(queue->process == queue->local_insert);
-+ BUG_ON(queue->process != queue->remote_insert);
-+
-+ bulk = &queue->bulks[
-+ BULK_INDEX(queue->remote_insert)];
-+ bulk->actual = *(int *)header->data;
-+ queue->remote_insert++;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) %x@%x",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ bulk->actual, (unsigned int)bulk->data);
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs:%d %cx li=%x ri=%x p=%x",
-+ state->id, localport,
-+ (type == VCHIQ_MSG_BULK_RX_DONE) ?
-+ 'r' : 't',
-+ queue->local_insert,
-+ queue->remote_insert, queue->process);
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ WARN_ON(queue->process == queue->local_insert);
-+ vchiq_complete_bulk(bulk);
-+ queue->process++;
-+ mutex_unlock(&service->bulk_mutex);
-+ DEBUG_TRACE(PARSE_LINE);
-+ notify_bulks(service, queue, 1/*retry_poll*/);
-+ DEBUG_TRACE(PARSE_LINE);
-+ }
-+ break;
-+ case VCHIQ_MSG_PADDING:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs PADDING@%x,%x",
-+ state->id, (unsigned int)header, size);
-+ break;
-+ case VCHIQ_MSG_PAUSE:
-+ /* If initiated, signal the application thread */
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs PAUSE@%x,%x",
-+ state->id, (unsigned int)header, size);
-+ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: PAUSE received in state PAUSED",
-+ state->id);
-+ break;
-+ }
-+ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) {
-+ /* Send a PAUSE in response */
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0),
-+ NULL, 0, 0, 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+ if (state->is_master)
-+ pause_bulks(state);
-+ }
-+ /* At this point slot_mutex is held */
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED);
-+ vchiq_platform_paused(state);
-+ break;
-+ case VCHIQ_MSG_RESUME:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs RESUME@%x,%x",
-+ state->id, (unsigned int)header, size);
-+ /* Release the slot mutex */
-+ mutex_unlock(&state->slot_mutex);
-+ if (state->is_master)
-+ resume_bulks(state);
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED);
-+ vchiq_platform_resumed(state);
-+ break;
-+
-+ case VCHIQ_MSG_REMOTE_USE:
-+ vchiq_on_remote_use(state);
-+ break;
-+ case VCHIQ_MSG_REMOTE_RELEASE:
-+ vchiq_on_remote_release(state);
-+ break;
-+ case VCHIQ_MSG_REMOTE_USE_ACTIVE:
-+ vchiq_on_remote_use_active(state);
-+ break;
-+
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: prs invalid msgid %x@%x,%x",
-+ state->id, msgid, (unsigned int)header, size);
-+ WARN(1, "invalid message\n");
-+ break;
-+ }
-+
-+skip_message:
-+ if (service) {
-+ unlock_service(service);
-+ service = NULL;
-+ }
-+
-+ state->rx_pos += calc_stride(size);
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ /* Perform some housekeeping when the end of the slot is
-+ ** reached. */
-+ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) {
-+ /* Remove the extra reference count. */
-+ release_slot(state, state->rx_info, NULL, NULL);
-+ state->rx_data = NULL;
-+ }
-+ }
-+
-+bail_not_ready:
-+ if (service)
-+ unlock_service(service);
-+}
-+
-+/* Called by the slot handler thread */
-+static int
-+slot_handler_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ DEBUG_INITIALISE(local)
-+
-+ while (1) {
-+ DEBUG_COUNT(SLOT_HANDLER_COUNT);
-+ DEBUG_TRACE(SLOT_HANDLER_LINE);
-+ remote_event_wait(&local->trigger);
-+
-+ rmb();
-+
-+ DEBUG_TRACE(SLOT_HANDLER_LINE);
-+ if (state->poll_needed) {
-+ /* Check if we need to suspend - may change our
-+ * conn_state */
-+ vchiq_platform_check_suspend(state);
-+
-+ state->poll_needed = 0;
-+
-+ /* Handle service polling and other rare conditions here
-+ ** out of the mainline code */
-+ switch (state->conn_state) {
-+ case VCHIQ_CONNSTATE_CONNECTED:
-+ /* Poll the services as requested */
-+ poll_services(state);
-+ break;
-+
-+ case VCHIQ_CONNSTATE_PAUSING:
-+ if (state->is_master)
-+ pause_bulks(state);
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0),
-+ NULL, 0, 0, 0) != VCHIQ_RETRY) {
-+ vchiq_set_conn_state(state,
-+ VCHIQ_CONNSTATE_PAUSE_SENT);
-+ } else {
-+ if (state->is_master)
-+ resume_bulks(state);
-+ /* Retry later */
-+ state->poll_needed = 1;
-+ }
-+ break;
-+
-+ case VCHIQ_CONNSTATE_PAUSED:
-+ vchiq_platform_resume(state);
-+ break;
-+
-+ case VCHIQ_CONNSTATE_RESUMING:
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0),
-+ NULL, 0, 0, 0) != VCHIQ_RETRY) {
-+ if (state->is_master)
-+ resume_bulks(state);
-+ vchiq_set_conn_state(state,
-+ VCHIQ_CONNSTATE_CONNECTED);
-+ vchiq_platform_resumed(state);
-+ } else {
-+ /* This should really be impossible,
-+ ** since the PAUSE should have flushed
-+ ** through outstanding messages. */
-+ vchiq_log_error(vchiq_core_log_level,
-+ "Failed to send RESUME "
-+ "message");
-+ BUG();
-+ }
-+ break;
-+
-+ case VCHIQ_CONNSTATE_PAUSE_TIMEOUT:
-+ case VCHIQ_CONNSTATE_RESUME_TIMEOUT:
-+ vchiq_platform_handle_timeout(state);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+
-+ }
-+
-+ DEBUG_TRACE(SLOT_HANDLER_LINE);
-+ parse_rx_slots(state);
-+ }
-+ return 0;
-+}
-+
-+
-+/* Called by the recycle thread */
-+static int
-+recycle_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+
-+ while (1) {
-+ remote_event_wait(&local->recycle);
-+
-+ process_free_queue(state);
-+ }
-+ return 0;
-+}
-+
-+
-+/* Called by the sync thread */
-+static int
-+sync_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
-+ state->remote->slot_sync);
-+
-+ while (1) {
-+ VCHIQ_SERVICE_T *service;
-+ int msgid, size;
-+ int type;
-+ unsigned int localport, remoteport;
-+
-+ remote_event_wait(&local->sync_trigger);
-+
-+ rmb();
-+
-+ msgid = header->msgid;
-+ size = header->size;
-+ type = VCHIQ_MSG_TYPE(msgid);
-+ localport = VCHIQ_MSG_DSTPORT(msgid);
-+ remoteport = VCHIQ_MSG_SRCPORT(msgid);
-+
-+ service = find_service_by_port(state, localport);
-+
-+ if (!service) {
-+ vchiq_log_error(vchiq_sync_log_level,
-+ "%d: sf %s@%x (%d->%d) - "
-+ "invalid/closed service %d",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport, localport);
-+ release_message_sync(state, header);
-+ continue;
-+ }
-+
-+ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+ vchiq_log_trace(vchiq_sync_log_level,
-+ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d",
-+ msg_type_str(type),
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ remoteport, localport, size);
-+ if (size > 0)
-+ vchiq_log_dump_mem("Rcvd", 0, header->data,
-+ min(64, size));
-+ }
-+
-+ switch (type) {
-+ case VCHIQ_MSG_OPENACK:
-+ if (size >= sizeof(struct vchiq_openack_payload)) {
-+ const struct vchiq_openack_payload *payload =
-+ (struct vchiq_openack_payload *)
-+ header->data;
-+ service->peer_version = payload->version;
-+ }
-+ vchiq_log_info(vchiq_sync_log_level,
-+ "%d: sf OPENACK@%x,%x (%d->%d) v:%d",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport, service->peer_version);
-+ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) {
-+ service->remoteport = remoteport;
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_OPENSYNC);
-+ up(&service->remove_event);
-+ }
-+ release_message_sync(state, header);
-+ break;
-+
-+ case VCHIQ_MSG_DATA:
-+ vchiq_log_trace(vchiq_sync_log_level,
-+ "%d: sf DATA@%x,%x (%d->%d)",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport);
-+
-+ if ((service->remoteport == remoteport) &&
-+ (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPENSYNC)) {
-+ if (make_service_callback(service,
-+ VCHIQ_MESSAGE_AVAILABLE, header,
-+ NULL) == VCHIQ_RETRY)
-+ vchiq_log_error(vchiq_sync_log_level,
-+ "synchronous callback to "
-+ "service %d returns "
-+ "VCHIQ_RETRY",
-+ localport);
-+ }
-+ break;
-+
-+ default:
-+ vchiq_log_error(vchiq_sync_log_level,
-+ "%d: sf unexpected msgid %x@%x,%x",
-+ state->id, msgid, (unsigned int)header, size);
-+ release_message_sync(state, header);
-+ break;
-+ }
-+
-+ unlock_service(service);
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static void
-+init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue)
-+{
-+ queue->local_insert = 0;
-+ queue->remote_insert = 0;
-+ queue->process = 0;
-+ queue->remote_notify = 0;
-+ queue->remove = 0;
-+}
-+
-+
-+inline const char *
-+get_conn_state_name(VCHIQ_CONNSTATE_T conn_state)
-+{
-+ return conn_state_names[conn_state];
-+}
-+
-+
-+VCHIQ_SLOT_ZERO_T *
-+vchiq_init_slots(void *mem_base, int mem_size)
-+{
-+ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK;
-+ VCHIQ_SLOT_ZERO_T *slot_zero =
-+ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align);
-+ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE;
-+ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS;
-+
-+ /* Ensure there is enough memory to run an absolutely minimum system */
-+ num_slots -= first_data_slot;
-+
-+ if (num_slots < 4) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_init_slots - insufficient memory %x bytes",
-+ mem_size);
-+ return NULL;
-+ }
-+
-+ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T));
-+
-+ slot_zero->magic = VCHIQ_MAGIC;
-+ slot_zero->version = VCHIQ_VERSION;
-+ slot_zero->version_min = VCHIQ_VERSION_MIN;
-+ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T);
-+ slot_zero->slot_size = VCHIQ_SLOT_SIZE;
-+ slot_zero->max_slots = VCHIQ_MAX_SLOTS;
-+ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE;
-+
-+ slot_zero->master.slot_sync = first_data_slot;
-+ slot_zero->master.slot_first = first_data_slot + 1;
-+ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1;
-+ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2);
-+ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1;
-+ slot_zero->slave.slot_last = first_data_slot + num_slots - 1;
-+
-+ return slot_zero;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero,
-+ int is_master)
-+{
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_SHARED_STATE_T *remote;
-+ VCHIQ_STATUS_T status;
-+ char threadname[10];
-+ static int id;
-+ int i;
-+
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%s: slot_zero = 0x%08lx, is_master = %d",
-+ __func__, (unsigned long)slot_zero, is_master);
-+
-+ /* Check the input configuration */
-+
-+ if (slot_zero->magic != VCHIQ_MAGIC) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("Invalid VCHIQ magic value found.");
-+ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)",
-+ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if (slot_zero->version < VCHIQ_VERSION_MIN) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("Incompatible VCHIQ versions found.");
-+ vchiq_loud_error("slot_zero=%x: VideoCore version=%d "
-+ "(minimum %d)",
-+ (unsigned int)slot_zero, slot_zero->version,
-+ VCHIQ_VERSION_MIN);
-+ vchiq_loud_error("Restart with a newer VideoCore image.");
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if (VCHIQ_VERSION < slot_zero->version_min) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("Incompatible VCHIQ versions found.");
-+ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore "
-+ "minimum %d)",
-+ (unsigned int)slot_zero, VCHIQ_VERSION,
-+ slot_zero->version_min);
-+ vchiq_loud_error("Restart with a newer kernel.");
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ||
-+ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ||
-+ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ||
-+ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) {
-+ vchiq_loud_error_header();
-+ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T))
-+ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x "
-+ "(expected %x)",
-+ (unsigned int)slot_zero,
-+ slot_zero->slot_zero_size,
-+ sizeof(VCHIQ_SLOT_ZERO_T));
-+ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE)
-+ vchiq_loud_error("slot_zero=%x: slot_size=%d "
-+ "(expected %d",
-+ (unsigned int)slot_zero, slot_zero->slot_size,
-+ VCHIQ_SLOT_SIZE);
-+ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS)
-+ vchiq_loud_error("slot_zero=%x: max_slots=%d "
-+ "(expected %d)",
-+ (unsigned int)slot_zero, slot_zero->max_slots,
-+ VCHIQ_MAX_SLOTS);
-+ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)
-+ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d "
-+ "(expected %d)",
-+ (unsigned int)slot_zero,
-+ slot_zero->max_slots_per_side,
-+ VCHIQ_MAX_SLOTS_PER_SIDE);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if (is_master) {
-+ local = &slot_zero->master;
-+ remote = &slot_zero->slave;
-+ } else {
-+ local = &slot_zero->slave;
-+ remote = &slot_zero->master;
-+ }
-+
-+ if (local->initialised) {
-+ vchiq_loud_error_header();
-+ if (remote->initialised)
-+ vchiq_loud_error("local state has already been "
-+ "initialised");
-+ else
-+ vchiq_loud_error("master/slave mismatch - two %ss",
-+ is_master ? "master" : "slave");
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ memset(state, 0, sizeof(VCHIQ_STATE_T));
-+
-+ state->id = id++;
-+ state->is_master = is_master;
-+
-+ /*
-+ initialize shared state pointers
-+ */
-+
-+ state->local = local;
-+ state->remote = remote;
-+ state->slot_data = (VCHIQ_SLOT_T *)slot_zero;
-+
-+ /*
-+ initialize events and mutexes
-+ */
-+
-+ sema_init(&state->connect, 0);
-+ mutex_init(&state->mutex);
-+ sema_init(&state->trigger_event, 0);
-+ sema_init(&state->recycle_event, 0);
-+ sema_init(&state->sync_trigger_event, 0);
-+ sema_init(&state->sync_release_event, 0);
-+
-+ mutex_init(&state->slot_mutex);
-+ mutex_init(&state->recycle_mutex);
-+ mutex_init(&state->sync_mutex);
-+ mutex_init(&state->bulk_transfer_mutex);
-+
-+ sema_init(&state->slot_available_event, 0);
-+ sema_init(&state->slot_remove_event, 0);
-+ sema_init(&state->data_quota_event, 0);
-+
-+ state->slot_queue_available = 0;
-+
-+ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &state->service_quotas[i];
-+ sema_init(&service_quota->quota_event, 0);
-+ }
-+
-+ for (i = local->slot_first; i <= local->slot_last; i++) {
-+ local->slot_queue[state->slot_queue_available++] = i;
-+ up(&state->slot_available_event);
-+ }
-+
-+ state->default_slot_quota = state->slot_queue_available/2;
-+ state->default_message_quota =
-+ min((unsigned short)(state->default_slot_quota * 256),
-+ (unsigned short)~0);
-+
-+ state->previous_data_index = -1;
-+ state->data_use_count = 0;
-+ state->data_quota = state->slot_queue_available - 1;
-+
-+ local->trigger.event = &state->trigger_event;
-+ remote_event_create(&local->trigger);
-+ local->tx_pos = 0;
-+
-+ local->recycle.event = &state->recycle_event;
-+ remote_event_create(&local->recycle);
-+ local->slot_queue_recycle = state->slot_queue_available;
-+
-+ local->sync_trigger.event = &state->sync_trigger_event;
-+ remote_event_create(&local->sync_trigger);
-+
-+ local->sync_release.event = &state->sync_release_event;
-+ remote_event_create(&local->sync_release);
-+
-+ /* At start-of-day, the slot is empty and available */
-+ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid
-+ = VCHIQ_MSGID_PADDING;
-+ remote_event_signal_local(&local->sync_release);
-+
-+ local->debug[DEBUG_ENTRIES] = DEBUG_MAX;
-+
-+ status = vchiq_platform_init_state(state);
-+
-+ /*
-+ bring up slot handler thread
-+ */
-+ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id);
-+ state->slot_handler_thread = kthread_create(&slot_handler_func,
-+ (void *)state,
-+ threadname);
-+
-+ if (state->slot_handler_thread == NULL) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("couldn't create thread %s", threadname);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+ set_user_nice(state->slot_handler_thread, -19);
-+ wake_up_process(state->slot_handler_thread);
-+
-+ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id);
-+ state->recycle_thread = kthread_create(&recycle_func,
-+ (void *)state,
-+ threadname);
-+ if (state->recycle_thread == NULL) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("couldn't create thread %s", threadname);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+ set_user_nice(state->recycle_thread, -19);
-+ wake_up_process(state->recycle_thread);
-+
-+ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id);
-+ state->sync_thread = kthread_create(&sync_func,
-+ (void *)state,
-+ threadname);
-+ if (state->sync_thread == NULL) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("couldn't create thread %s", threadname);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+ set_user_nice(state->sync_thread, -20);
-+ wake_up_process(state->sync_thread);
-+
-+ BUG_ON(state->id >= VCHIQ_MAX_STATES);
-+ vchiq_states[state->id] = state;
-+
-+ /* Indicate readiness to the other side */
-+ local->initialised = 1;
-+
-+ return status;
-+}
-+
-+/* Called from application thread when a client or server service is created. */
-+VCHIQ_SERVICE_T *
-+vchiq_add_service_internal(VCHIQ_STATE_T *state,
-+ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate,
-+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term)
-+{
-+ VCHIQ_SERVICE_T *service;
-+
-+ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL);
-+ if (service) {
-+ service->base.fourcc = params->fourcc;
-+ service->base.callback = params->callback;
-+ service->base.userdata = params->userdata;
-+ service->handle = VCHIQ_SERVICE_HANDLE_INVALID;
-+ service->ref_count = 1;
-+ service->srvstate = VCHIQ_SRVSTATE_FREE;
-+ service->userdata_term = userdata_term;
-+ service->localport = VCHIQ_PORT_FREE;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+
-+ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ?
-+ VCHIQ_FOURCC_INVALID : params->fourcc;
-+ service->client_id = 0;
-+ service->auto_close = 1;
-+ service->sync = 0;
-+ service->closing = 0;
-+ service->trace = 0;
-+ atomic_set(&service->poll_flags, 0);
-+ service->version = params->version;
-+ service->version_min = params->version_min;
-+ service->state = state;
-+ service->instance = instance;
-+ service->service_use_count = 0;
-+ init_bulk_queue(&service->bulk_tx);
-+ init_bulk_queue(&service->bulk_rx);
-+ sema_init(&service->remove_event, 0);
-+ sema_init(&service->bulk_remove_event, 0);
-+ mutex_init(&service->bulk_mutex);
-+ memset(&service->stats, 0, sizeof(service->stats));
-+ } else {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "Out of memory");
-+ }
-+
-+ if (service) {
-+ VCHIQ_SERVICE_T **pservice = NULL;
-+ int i;
-+
-+ /* Although it is perfectly possible to use service_spinlock
-+ ** to protect the creation of services, it is overkill as it
-+ ** disables interrupts while the array is searched.
-+ ** The only danger is of another thread trying to create a
-+ ** service - service deletion is safe.
-+ ** Therefore it is preferable to use state->mutex which,
-+ ** although slower to claim, doesn't block interrupts while
-+ ** it is held.
-+ */
-+
-+ mutex_lock(&state->mutex);
-+
-+ /* Prepare to use a previously unused service */
-+ if (state->unused_service < VCHIQ_MAX_SERVICES)
-+ pservice = &state->services[state->unused_service];
-+
-+ if (srvstate == VCHIQ_SRVSTATE_OPENING) {
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *srv = state->services[i];
-+ if (!srv) {
-+ pservice = &state->services[i];
-+ break;
-+ }
-+ }
-+ } else {
-+ for (i = (state->unused_service - 1); i >= 0; i--) {
-+ VCHIQ_SERVICE_T *srv = state->services[i];
-+ if (!srv)
-+ pservice = &state->services[i];
-+ else if ((srv->public_fourcc == params->fourcc)
-+ && ((srv->instance != instance) ||
-+ (srv->base.callback !=
-+ params->callback))) {
-+ /* There is another server using this
-+ ** fourcc which doesn't match. */
-+ pservice = NULL;
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (pservice) {
-+ service->localport = (pservice - state->services);
-+ if (!handle_seq)
-+ handle_seq = VCHIQ_MAX_STATES *
-+ VCHIQ_MAX_SERVICES;
-+ service->handle = handle_seq |
-+ (state->id * VCHIQ_MAX_SERVICES) |
-+ service->localport;
-+ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES;
-+ *pservice = service;
-+ if (pservice == &state->services[state->unused_service])
-+ state->unused_service++;
-+ }
-+
-+ mutex_unlock(&state->mutex);
-+
-+ if (!pservice) {
-+ kfree(service);
-+ service = NULL;
-+ }
-+ }
-+
-+ if (service) {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &state->service_quotas[service->localport];
-+ service_quota->slot_quota = state->default_slot_quota;
-+ service_quota->message_quota = state->default_message_quota;
-+ if (service_quota->slot_use_count == 0)
-+ service_quota->previous_tx_index =
-+ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos)
-+ - 1;
-+
-+ /* Bring this service online */
-+ vchiq_set_service_state(service, srvstate);
-+
-+ vchiq_log_info(vchiq_core_msg_log_level,
-+ "%s Service %c%c%c%c SrcPort:%d",
-+ (srvstate == VCHIQ_SRVSTATE_OPENING)
-+ ? "Open" : "Add",
-+ VCHIQ_FOURCC_AS_4CHARS(params->fourcc),
-+ service->localport);
-+ }
-+
-+ /* Don't unlock the service - leave it with a ref_count of 1. */
-+
-+ return service;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id)
-+{
-+ struct vchiq_open_payload payload = {
-+ service->base.fourcc,
-+ client_id,
-+ service->version,
-+ service->version_min
-+ };
-+ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) };
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ service->client_id = client_id;
-+ vchiq_use_service_internal(service);
-+ status = queue_message(service->state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0),
-+ &body, 1, sizeof(payload), 1);
-+ if (status == VCHIQ_SUCCESS) {
-+ /* Wait for the ACK/NAK */
-+ if (down_interruptible(&service->remove_event) != 0) {
-+ status = VCHIQ_RETRY;
-+ vchiq_release_service_internal(service);
-+ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) {
-+ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: osi - srvstate = %s (ref %d)",
-+ service->state->id,
-+ srvstate_names[service->srvstate],
-+ service->ref_count);
-+ status = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_STATS_INC(service, error_count);
-+ vchiq_release_service_internal(service);
-+ }
-+ }
-+ return status;
-+}
-+
-+static void
-+release_service_messages(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ int slot_last = state->remote->slot_last;
-+ int i;
-+
-+ /* Release any claimed messages */
-+ for (i = state->remote->slot_first; i <= slot_last; i++) {
-+ VCHIQ_SLOT_INFO_T *slot_info =
-+ SLOT_INFO_FROM_INDEX(state, i);
-+ if (slot_info->release_count != slot_info->use_count) {
-+ char *data =
-+ (char *)SLOT_DATA_FROM_INDEX(state, i);
-+ unsigned int pos, end;
-+
-+ end = VCHIQ_SLOT_SIZE;
-+ if (data == state->rx_data)
-+ /* This buffer is still being read from - stop
-+ ** at the current read position */
-+ end = state->rx_pos & VCHIQ_SLOT_MASK;
-+
-+ pos = 0;
-+
-+ while (pos < end) {
-+ VCHIQ_HEADER_T *header =
-+ (VCHIQ_HEADER_T *)(data + pos);
-+ int msgid = header->msgid;
-+ int port = VCHIQ_MSG_DSTPORT(msgid);
-+ if ((port == service->localport) &&
-+ (msgid & VCHIQ_MSGID_CLAIMED)) {
-+ vchiq_log_info(vchiq_core_log_level,
-+ " fsi - hdr %x",
-+ (unsigned int)header);
-+ release_slot(state, slot_info, header,
-+ NULL);
-+ }
-+ pos += calc_stride(header->size);
-+ if (pos > VCHIQ_SLOT_SIZE) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "fsi - pos %x: header %x, "
-+ "msgid %x, header->msgid %x, "
-+ "header->size %x",
-+ pos, (unsigned int)header,
-+ msgid, header->msgid,
-+ header->size);
-+ WARN(1, "invalid slot position\n");
-+ }
-+ }
-+ }
-+ }
-+}
-+
-+static int
-+do_abort_bulks(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATUS_T status;
-+
-+ /* Abort any outstanding bulk transfers */
-+ if (mutex_lock_interruptible(&service->bulk_mutex) != 0)
-+ return 0;
-+ abort_outstanding_bulks(service, &service->bulk_tx);
-+ abort_outstanding_bulks(service, &service->bulk_rx);
-+ mutex_unlock(&service->bulk_mutex);
-+
-+ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/);
-+ if (status == VCHIQ_SUCCESS)
-+ status = notify_bulks(service, &service->bulk_rx,
-+ 0/*!retry_poll*/);
-+ return (status == VCHIQ_SUCCESS);
-+}
-+
-+static VCHIQ_STATUS_T
-+close_service_complete(VCHIQ_SERVICE_T *service, int failstate)
-+{
-+ VCHIQ_STATUS_T status;
-+ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID);
-+ int newstate;
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_OPEN:
-+ case VCHIQ_SRVSTATE_CLOSESENT:
-+ case VCHIQ_SRVSTATE_CLOSERECVD:
-+ if (is_server) {
-+ if (service->auto_close) {
-+ service->client_id = 0;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+ newstate = VCHIQ_SRVSTATE_LISTENING;
-+ } else
-+ newstate = VCHIQ_SRVSTATE_CLOSEWAIT;
-+ } else
-+ newstate = VCHIQ_SRVSTATE_CLOSED;
-+ vchiq_set_service_state(service, newstate);
-+ break;
-+ case VCHIQ_SRVSTATE_LISTENING:
-+ break;
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "close_service_complete(%x) called in state %s",
-+ service->handle, srvstate_names[service->srvstate]);
-+ WARN(1, "close_service_complete in unexpected state\n");
-+ return VCHIQ_ERROR;
-+ }
-+
-+ status = make_service_callback(service,
-+ VCHIQ_SERVICE_CLOSED, NULL, NULL);
-+
-+ if (status != VCHIQ_RETRY) {
-+ int uc = service->service_use_count;
-+ int i;
-+ /* Complete the close process */
-+ for (i = 0; i < uc; i++)
-+ /* cater for cases where close is forced and the
-+ ** client may not close all it's handles */
-+ vchiq_release_service_internal(service);
-+
-+ service->client_id = 0;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+
-+ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED)
-+ vchiq_free_service_internal(service);
-+ else if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) {
-+ if (is_server)
-+ service->closing = 0;
-+
-+ up(&service->remove_event);
-+ }
-+ } else
-+ vchiq_set_service_state(service, failstate);
-+
-+ return status;
-+}
-+
-+/* Called by the slot handler */
-+VCHIQ_STATUS_T
-+vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID);
-+
-+ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)",
-+ service->state->id, service->localport, close_recvd,
-+ srvstate_names[service->srvstate]);
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_CLOSED:
-+ case VCHIQ_SRVSTATE_HIDDEN:
-+ case VCHIQ_SRVSTATE_LISTENING:
-+ case VCHIQ_SRVSTATE_CLOSEWAIT:
-+ if (close_recvd)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_close_service_internal(1) called "
-+ "in state %s",
-+ srvstate_names[service->srvstate]);
-+ else if (is_server) {
-+ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) {
-+ status = VCHIQ_ERROR;
-+ } else {
-+ service->client_id = 0;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+ if (service->srvstate ==
-+ VCHIQ_SRVSTATE_CLOSEWAIT)
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_LISTENING);
-+ }
-+ up(&service->remove_event);
-+ } else
-+ vchiq_free_service_internal(service);
-+ break;
-+ case VCHIQ_SRVSTATE_OPENING:
-+ if (close_recvd) {
-+ /* The open was rejected - tell the user */
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_CLOSEWAIT);
-+ up(&service->remove_event);
-+ } else {
-+ /* Shutdown mid-open - let the other side know */
-+ status = queue_message(state, service,
-+ VCHIQ_MAKE_MSG
-+ (VCHIQ_MSG_CLOSE,
-+ service->localport,
-+ VCHIQ_MSG_DSTPORT(service->remoteport)),
-+ NULL, 0, 0, 0);
-+ }
-+ break;
-+
-+ case VCHIQ_SRVSTATE_OPENSYNC:
-+ mutex_lock(&state->sync_mutex);
-+ /* Drop through */
-+
-+ case VCHIQ_SRVSTATE_OPEN:
-+ if (state->is_master || close_recvd) {
-+ if (!do_abort_bulks(service))
-+ status = VCHIQ_RETRY;
-+ }
-+
-+ release_service_messages(service);
-+
-+ if (status == VCHIQ_SUCCESS)
-+ status = queue_message(state, service,
-+ VCHIQ_MAKE_MSG
-+ (VCHIQ_MSG_CLOSE,
-+ service->localport,
-+ VCHIQ_MSG_DSTPORT(service->remoteport)),
-+ NULL, 0, 0, 0);
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ if (!close_recvd)
-+ break;
-+ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) {
-+ mutex_unlock(&state->sync_mutex);
-+ break;
-+ } else
-+ break;
-+
-+ status = close_service_complete(service,
-+ VCHIQ_SRVSTATE_CLOSERECVD);
-+ break;
-+
-+ case VCHIQ_SRVSTATE_CLOSESENT:
-+ if (!close_recvd)
-+ /* This happens when a process is killed mid-close */
-+ break;
-+
-+ if (!state->is_master) {
-+ if (!do_abort_bulks(service)) {
-+ status = VCHIQ_RETRY;
-+ break;
-+ }
-+ }
-+
-+ if (status == VCHIQ_SUCCESS)
-+ status = close_service_complete(service,
-+ VCHIQ_SRVSTATE_CLOSERECVD);
-+ break;
-+
-+ case VCHIQ_SRVSTATE_CLOSERECVD:
-+ if (!close_recvd && is_server)
-+ /* Force into LISTENING mode */
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_LISTENING);
-+ status = close_service_complete(service,
-+ VCHIQ_SRVSTATE_CLOSERECVD);
-+ break;
-+
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_close_service_internal(%d) called in state %s",
-+ close_recvd, srvstate_names[service->srvstate]);
-+ break;
-+ }
-+
-+ return status;
-+}
-+
-+/* Called from the application process upon process death */
-+void
-+vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+
-+ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)",
-+ state->id, service->localport, service->remoteport);
-+
-+ mark_service_closing(service);
-+
-+ /* Mark the service for removal by the slot handler */
-+ request_poll(state, service, VCHIQ_POLL_REMOVE);
-+}
-+
-+/* Called from the slot handler */
-+void
-+vchiq_free_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+
-+ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)",
-+ state->id, service->localport);
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_OPENING:
-+ case VCHIQ_SRVSTATE_CLOSED:
-+ case VCHIQ_SRVSTATE_HIDDEN:
-+ case VCHIQ_SRVSTATE_LISTENING:
-+ case VCHIQ_SRVSTATE_CLOSEWAIT:
-+ break;
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: fsi - (%d) in state %s",
-+ state->id, service->localport,
-+ srvstate_names[service->srvstate]);
-+ return;
-+ }
-+
-+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE);
-+
-+ up(&service->remove_event);
-+
-+ /* Release the initial lock */
-+ unlock_service(service);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+
-+ /* Find all services registered to this client and enable them. */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance,
-+ &i)) != NULL) {
-+ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_LISTENING);
-+ unlock_service(service);
-+ }
-+
-+ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) {
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0,
-+ 0, 1) == VCHIQ_RETRY)
-+ return VCHIQ_RETRY;
-+
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING);
-+ }
-+
-+ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) {
-+ if (down_interruptible(&state->connect) != 0)
-+ return VCHIQ_RETRY;
-+
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED);
-+ up(&state->connect);
-+ }
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+
-+ /* Find all services registered to this client and enable them. */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance,
-+ &i)) != NULL) {
-+ (void)vchiq_remove_service(service->handle);
-+ unlock_service(service);
-+ }
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_pause_internal(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ switch (state->conn_state) {
-+ case VCHIQ_CONNSTATE_CONNECTED:
-+ /* Request a pause */
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING);
-+ request_poll(state, NULL, 0);
-+ break;
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_pause_internal in state %s\n",
-+ conn_state_names[state->conn_state]);
-+ status = VCHIQ_ERROR;
-+ VCHIQ_STATS_INC(state, error_count);
-+ break;
-+ }
-+
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_resume_internal(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) {
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING);
-+ request_poll(state, NULL, 0);
-+ } else {
-+ status = VCHIQ_ERROR;
-+ VCHIQ_STATS_INC(state, error_count);
-+ }
-+
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ /* Unregister the service */
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (!service)
-+ return VCHIQ_ERROR;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: close_service:%d",
-+ service->state->id, service->localport);
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) {
-+ unlock_service(service);
-+ return VCHIQ_ERROR;
-+ }
-+
-+ mark_service_closing(service);
-+
-+ if (current == service->state->slot_handler_thread) {
-+ status = vchiq_close_service_internal(service,
-+ 0/*!close_recvd*/);
-+ BUG_ON(status == VCHIQ_RETRY);
-+ } else {
-+ /* Mark the service for termination by the slot handler */
-+ request_poll(service->state, service, VCHIQ_POLL_TERMINATE);
-+ }
-+
-+ while (1) {
-+ if (down_interruptible(&service->remove_event) != 0) {
-+ status = VCHIQ_RETRY;
-+ break;
-+ }
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_OPEN))
-+ break;
-+
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: close_service:%d - waiting in state %s",
-+ service->state->id, service->localport,
-+ srvstate_names[service->srvstate]);
-+ }
-+
-+ if ((status == VCHIQ_SUCCESS) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_LISTENING))
-+ status = VCHIQ_ERROR;
-+
-+ unlock_service(service);
-+
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ /* Unregister the service */
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (!service)
-+ return VCHIQ_ERROR;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: remove_service:%d",
-+ service->state->id, service->localport);
-+
-+ if (service->srvstate == VCHIQ_SRVSTATE_FREE) {
-+ unlock_service(service);
-+ return VCHIQ_ERROR;
-+ }
-+
-+ mark_service_closing(service);
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ||
-+ (current == service->state->slot_handler_thread)) {
-+ /* Make it look like a client, because it must be removed and
-+ not left in the LISTENING state. */
-+ service->public_fourcc = VCHIQ_FOURCC_INVALID;
-+
-+ status = vchiq_close_service_internal(service,
-+ 0/*!close_recvd*/);
-+ BUG_ON(status == VCHIQ_RETRY);
-+ } else {
-+ /* Mark the service for removal by the slot handler */
-+ request_poll(service->state, service, VCHIQ_POLL_REMOVE);
-+ }
-+ while (1) {
-+ if (down_interruptible(&service->remove_event) != 0) {
-+ status = VCHIQ_RETRY;
-+ break;
-+ }
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_OPEN))
-+ break;
-+
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: remove_service:%d - waiting in state %s",
-+ service->state->id, service->localport,
-+ srvstate_names[service->srvstate]);
-+ }
-+
-+ if ((status == VCHIQ_SUCCESS) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_FREE))
-+ status = VCHIQ_ERROR;
-+
-+ unlock_service(service);
-+
-+ return status;
-+}
-+
-+
-+/* This function may be called by kernel threads or user threads.
-+ * User threads may receive VCHIQ_RETRY to indicate that a signal has been
-+ * received and the call should be retried after being returned to user
-+ * context.
-+ * When called in blocking mode, the userdata field points to a bulk_waiter
-+ * structure.
-+ */
-+VCHIQ_STATUS_T
-+vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_BULK_QUEUE_T *queue;
-+ VCHIQ_BULK_T *bulk;
-+ VCHIQ_STATE_T *state;
-+ struct bulk_waiter *bulk_waiter = NULL;
-+ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r';
-+ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ?
-+ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX;
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+
-+ if (!service ||
-+ (service->srvstate != VCHIQ_SRVSTATE_OPEN) ||
-+ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) ||
-+ (vchiq_check_service(service) != VCHIQ_SUCCESS))
-+ goto error_exit;
-+
-+ switch (mode) {
-+ case VCHIQ_BULK_MODE_NOCALLBACK:
-+ case VCHIQ_BULK_MODE_CALLBACK:
-+ break;
-+ case VCHIQ_BULK_MODE_BLOCKING:
-+ bulk_waiter = (struct bulk_waiter *)userdata;
-+ sema_init(&bulk_waiter->event, 0);
-+ bulk_waiter->actual = 0;
-+ bulk_waiter->bulk = NULL;
-+ break;
-+ case VCHIQ_BULK_MODE_WAITING:
-+ bulk_waiter = (struct bulk_waiter *)userdata;
-+ bulk = bulk_waiter->bulk;
-+ goto waiting;
-+ default:
-+ goto error_exit;
-+ }
-+
-+ state = service->state;
-+
-+ queue = (dir == VCHIQ_BULK_TRANSMIT) ?
-+ &service->bulk_tx : &service->bulk_rx;
-+
-+ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) {
-+ status = VCHIQ_RETRY;
-+ goto error_exit;
-+ }
-+
-+ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) {
-+ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls);
-+ do {
-+ mutex_unlock(&service->bulk_mutex);
-+ if (down_interruptible(&service->bulk_remove_event)
-+ != 0) {
-+ status = VCHIQ_RETRY;
-+ goto error_exit;
-+ }
-+ if (mutex_lock_interruptible(&service->bulk_mutex)
-+ != 0) {
-+ status = VCHIQ_RETRY;
-+ goto error_exit;
-+ }
-+ } while (queue->local_insert == queue->remove +
-+ VCHIQ_NUM_SERVICE_BULKS);
-+ }
-+
-+ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)];
-+
-+ bulk->mode = mode;
-+ bulk->dir = dir;
-+ bulk->userdata = userdata;
-+ bulk->size = size;
-+ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED;
-+
-+ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) !=
-+ VCHIQ_SUCCESS)
-+ goto unlock_error_exit;
-+
-+ wmb();
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: bt (%d->%d) %cx %x@%x %x",
-+ state->id,
-+ service->localport, service->remoteport, dir_char,
-+ size, (unsigned int)bulk->data, (unsigned int)userdata);
-+
-+ if (state->is_master) {
-+ queue->local_insert++;
-+ if (resolve_bulks(service, queue))
-+ request_poll(state, service,
-+ (dir == VCHIQ_BULK_TRANSMIT) ?
-+ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
-+ } else {
-+ int payload[2] = { (int)bulk->data, bulk->size };
-+ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) };
-+
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(dir_msgtype,
-+ service->localport, service->remoteport),
-+ &element, 1, sizeof(payload), 1);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_complete_bulk(bulk);
-+ goto unlock_error_exit;
-+ }
-+ queue->local_insert++;
-+ }
-+
-+ mutex_unlock(&service->bulk_mutex);
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: bt:%d %cx li=%x ri=%x p=%x",
-+ state->id,
-+ service->localport, dir_char,
-+ queue->local_insert, queue->remote_insert, queue->process);
-+
-+waiting:
-+ unlock_service(service);
-+
-+ status = VCHIQ_SUCCESS;
-+
-+ if (bulk_waiter) {
-+ bulk_waiter->bulk = bulk;
-+ if (down_interruptible(&bulk_waiter->event) != 0)
-+ status = VCHIQ_RETRY;
-+ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED)
-+ status = VCHIQ_ERROR;
-+ }
-+
-+ return status;
-+
-+unlock_error_exit:
-+ mutex_unlock(&service->bulk_mutex);
-+
-+error_exit:
-+ if (service)
-+ unlock_service(service);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
-+ const VCHIQ_ELEMENT_T *elements, unsigned int count)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+
-+ unsigned int size = 0;
-+ unsigned int i;
-+
-+ if (!service ||
-+ (vchiq_check_service(service) != VCHIQ_SUCCESS))
-+ goto error_exit;
-+
-+ for (i = 0; i < (unsigned int)count; i++) {
-+ if (elements[i].size) {
-+ if (elements[i].data == NULL) {
-+ VCHIQ_SERVICE_STATS_INC(service, error_count);
-+ goto error_exit;
-+ }
-+ size += elements[i].size;
-+ }
-+ }
-+
-+ if (size > VCHIQ_MAX_MSG_SIZE) {
-+ VCHIQ_SERVICE_STATS_INC(service, error_count);
-+ goto error_exit;
-+ }
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_OPEN:
-+ status = queue_message(service->state, service,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
-+ service->localport,
-+ service->remoteport),
-+ elements, count, size, 1);
-+ break;
-+ case VCHIQ_SRVSTATE_OPENSYNC:
-+ status = queue_message_sync(service->state, service,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
-+ service->localport,
-+ service->remoteport),
-+ elements, count, size, 1);
-+ break;
-+ default:
-+ status = VCHIQ_ERROR;
-+ break;
-+ }
-+
-+error_exit:
-+ if (service)
-+ unlock_service(service);
-+
-+ return status;
-+}
-+
-+void
-+vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_SHARED_STATE_T *remote;
-+ VCHIQ_STATE_T *state;
-+ int slot_index;
-+
-+ if (!service)
-+ return;
-+
-+ state = service->state;
-+ remote = state->remote;
-+
-+ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header);
-+
-+ if ((slot_index >= remote->slot_first) &&
-+ (slot_index <= remote->slot_last)) {
-+ int msgid = header->msgid;
-+ if (msgid & VCHIQ_MSGID_CLAIMED) {
-+ VCHIQ_SLOT_INFO_T *slot_info =
-+ SLOT_INFO_FROM_INDEX(state, slot_index);
-+
-+ release_slot(state, slot_info, header, service);
-+ }
-+ } else if (slot_index == remote->slot_sync)
-+ release_message_sync(state, header);
-+
-+ unlock_service(service);
-+}
-+
-+static void
-+release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
-+{
-+ header->msgid = VCHIQ_MSGID_PADDING;
-+ wmb();
-+ remote_event_signal(&state->remote->sync_release);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, short *peer_version)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+
-+ if (!service ||
-+ (vchiq_check_service(service) != VCHIQ_SUCCESS) ||
-+ !peer_version)
-+ goto exit;
-+ *peer_version = service->peer_version;
-+ status = VCHIQ_SUCCESS;
-+
-+exit:
-+ if (service)
-+ unlock_service(service);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_get_config(VCHIQ_INSTANCE_T instance,
-+ int config_size, VCHIQ_CONFIG_T *pconfig)
-+{
-+ VCHIQ_CONFIG_T config;
-+
-+ (void)instance;
-+
-+ config.max_msg_size = VCHIQ_MAX_MSG_SIZE;
-+ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE;
-+ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS;
-+ config.max_services = VCHIQ_MAX_SERVICES;
-+ config.version = VCHIQ_VERSION;
-+ config.version_min = VCHIQ_VERSION_MIN;
-+
-+ if (config_size > sizeof(VCHIQ_CONFIG_T))
-+ return VCHIQ_ERROR;
-+
-+ memcpy(pconfig, &config,
-+ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T))));
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle,
-+ VCHIQ_SERVICE_OPTION_T option, int value)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+
-+ if (service) {
-+ switch (option) {
-+ case VCHIQ_SERVICE_OPTION_AUTOCLOSE:
-+ service->auto_close = value;
-+ status = VCHIQ_SUCCESS;
-+ break;
-+
-+ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &service->state->service_quotas[
-+ service->localport];
-+ if (value == 0)
-+ value = service->state->default_slot_quota;
-+ if ((value >= service_quota->slot_use_count) &&
-+ (value < (unsigned short)~0)) {
-+ service_quota->slot_quota = value;
-+ if ((value >= service_quota->slot_use_count) &&
-+ (service_quota->message_quota >=
-+ service_quota->message_use_count)) {
-+ /* Signal the service that it may have
-+ ** dropped below its quota */
-+ up(&service_quota->quota_event);
-+ }
-+ status = VCHIQ_SUCCESS;
-+ }
-+ } break;
-+
-+ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &service->state->service_quotas[
-+ service->localport];
-+ if (value == 0)
-+ value = service->state->default_message_quota;
-+ if ((value >= service_quota->message_use_count) &&
-+ (value < (unsigned short)~0)) {
-+ service_quota->message_quota = value;
-+ if ((value >=
-+ service_quota->message_use_count) &&
-+ (service_quota->slot_quota >=
-+ service_quota->slot_use_count))
-+ /* Signal the service that it may have
-+ ** dropped below its quota */
-+ up(&service_quota->quota_event);
-+ status = VCHIQ_SUCCESS;
-+ }
-+ } break;
-+
-+ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS:
-+ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ||
-+ (service->srvstate ==
-+ VCHIQ_SRVSTATE_LISTENING)) {
-+ service->sync = value;
-+ status = VCHIQ_SUCCESS;
-+ }
-+ break;
-+
-+ case VCHIQ_SERVICE_OPTION_TRACE:
-+ service->trace = value;
-+ status = VCHIQ_SUCCESS;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ unlock_service(service);
-+ }
-+
-+ return status;
-+}
-+
-+void
-+vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state,
-+ VCHIQ_SHARED_STATE_T *shared, const char *label)
-+{
-+ static const char *const debug_names[] = {
-+ "<entries>",
-+ "SLOT_HANDLER_COUNT",
-+ "SLOT_HANDLER_LINE",
-+ "PARSE_LINE",
-+ "PARSE_HEADER",
-+ "PARSE_MSGID",
-+ "AWAIT_COMPLETION_LINE",
-+ "DEQUEUE_MESSAGE_LINE",
-+ "SERVICE_CALLBACK_LINE",
-+ "MSG_QUEUE_FULL_COUNT",
-+ "COMPLETION_QUEUE_FULL_COUNT"
-+ };
-+ int i;
-+
-+ char buf[80];
-+ int len;
-+ len = snprintf(buf, sizeof(buf),
-+ " %s: slots %d-%d tx_pos=%x recycle=%x",
-+ label, shared->slot_first, shared->slot_last,
-+ shared->tx_pos, shared->slot_queue_recycle);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Slots claimed:");
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ for (i = shared->slot_first; i <= shared->slot_last; i++) {
-+ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i);
-+ if (slot_info.use_count != slot_info.release_count) {
-+ len = snprintf(buf, sizeof(buf),
-+ " %d: %d/%d", i, slot_info.use_count,
-+ slot_info.release_count);
-+ vchiq_dump(dump_context, buf, len + 1);
-+ }
-+ }
-+
-+ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) {
-+ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)",
-+ debug_names[i], shared->debug[i], shared->debug[i]);
-+ vchiq_dump(dump_context, buf, len + 1);
-+ }
-+}
-+
-+void
-+vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state)
-+{
-+ char buf[80];
-+ int len;
-+ int i;
-+
-+ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id,
-+ conn_state_names[state->conn_state]);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " tx_pos=%x(@%x), rx_pos=%x(@%x)",
-+ state->local->tx_pos,
-+ (uint32_t)state->tx_data +
-+ (state->local_tx_pos & VCHIQ_SLOT_MASK),
-+ state->rx_pos,
-+ (uint32_t)state->rx_data +
-+ (state->rx_pos & VCHIQ_SLOT_MASK));
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Version: %d (min %d)",
-+ VCHIQ_VERSION, VCHIQ_VERSION_MIN);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ if (VCHIQ_ENABLE_STATS) {
-+ len = snprintf(buf, sizeof(buf),
-+ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, "
-+ "error_count=%d",
-+ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count,
-+ state->stats.error_count);
-+ vchiq_dump(dump_context, buf, len + 1);
-+ }
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Slots: %d available (%d data), %d recyclable, %d stalls "
-+ "(%d data)",
-+ ((state->slot_queue_available * VCHIQ_SLOT_SIZE) -
-+ state->local_tx_pos) / VCHIQ_SLOT_SIZE,
-+ state->data_quota - state->data_use_count,
-+ state->local->slot_queue_recycle - state->slot_queue_available,
-+ state->stats.slot_stalls, state->stats.data_stalls);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ vchiq_dump_platform_state(dump_context);
-+
-+ vchiq_dump_shared_state(dump_context, state, state->local, "Local");
-+ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote");
-+
-+ vchiq_dump_platform_instances(dump_context);
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = find_service_by_port(state, i);
-+
-+ if (service) {
-+ vchiq_dump_service_state(dump_context, service);
-+ unlock_service(service);
-+ }
-+ }
-+}
-+
-+void
-+vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service)
-+{
-+ char buf[80];
-+ int len;
-+
-+ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)",
-+ service->localport, srvstate_names[service->srvstate],
-+ service->ref_count - 1); /*Don't include the lock just taken*/
-+
-+ if (service->srvstate != VCHIQ_SRVSTATE_FREE) {
-+ char remoteport[30];
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &service->state->service_quotas[service->localport];
-+ int fourcc = service->base.fourcc;
-+ int tx_pending, rx_pending;
-+ if (service->remoteport != VCHIQ_PORT_FREE) {
-+ int len2 = snprintf(remoteport, sizeof(remoteport),
-+ "%d", service->remoteport);
-+ if (service->public_fourcc != VCHIQ_FOURCC_INVALID)
-+ snprintf(remoteport + len2,
-+ sizeof(remoteport) - len2,
-+ " (client %x)", service->client_id);
-+ } else
-+ strcpy(remoteport, "n/a");
-+
-+ len += snprintf(buf + len, sizeof(buf) - len,
-+ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)",
-+ VCHIQ_FOURCC_AS_4CHARS(fourcc),
-+ remoteport,
-+ service_quota->message_use_count,
-+ service_quota->message_quota,
-+ service_quota->slot_use_count,
-+ service_quota->slot_quota);
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ tx_pending = service->bulk_tx.local_insert -
-+ service->bulk_tx.remote_insert;
-+
-+ rx_pending = service->bulk_rx.local_insert -
-+ service->bulk_rx.remote_insert;
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Bulk: tx_pending=%d (size %d),"
-+ " rx_pending=%d (size %d)",
-+ tx_pending,
-+ tx_pending ? service->bulk_tx.bulks[
-+ BULK_INDEX(service->bulk_tx.remove)].size : 0,
-+ rx_pending,
-+ rx_pending ? service->bulk_rx.bulks[
-+ BULK_INDEX(service->bulk_rx.remove)].size : 0);
-+
-+ if (VCHIQ_ENABLE_STATS) {
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Ctrl: tx_count=%d, tx_bytes=%llu, "
-+ "rx_count=%d, rx_bytes=%llu",
-+ service->stats.ctrl_tx_count,
-+ service->stats.ctrl_tx_bytes,
-+ service->stats.ctrl_rx_count,
-+ service->stats.ctrl_rx_bytes);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Bulk: tx_count=%d, tx_bytes=%llu, "
-+ "rx_count=%d, rx_bytes=%llu",
-+ service->stats.bulk_tx_count,
-+ service->stats.bulk_tx_bytes,
-+ service->stats.bulk_rx_count,
-+ service->stats.bulk_rx_bytes);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " %d quota stalls, %d slot stalls, "
-+ "%d bulk stalls, %d aborted, %d errors",
-+ service->stats.quota_stalls,
-+ service->stats.slot_stalls,
-+ service->stats.bulk_stalls,
-+ service->stats.bulk_aborted_count,
-+ service->stats.error_count);
-+ }
-+ }
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ if (service->srvstate != VCHIQ_SRVSTATE_FREE)
-+ vchiq_dump_platform_service_state(dump_context, service);
-+}
-+
-+
-+void
-+vchiq_loud_error_header(void)
-+{
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+ vchiq_log_error(vchiq_core_log_level, "=====");
-+}
-+
-+void
-+vchiq_loud_error_footer(void)
-+{
-+ vchiq_log_error(vchiq_core_log_level, "=====");
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+}
-+
-+
-+VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_RETRY;
-+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0),
-+ NULL, 0, 0, 0);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_RETRY;
-+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0),
-+ NULL, 0, 0, 0);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_RETRY;
-+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0),
-+ NULL, 0, 0, 0);
-+ return status;
-+}
-+
-+void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem,
-+ size_t numBytes)
-+{
-+ const uint8_t *mem = (const uint8_t *)voidMem;
-+ size_t offset;
-+ char lineBuf[100];
-+ char *s;
-+
-+ while (numBytes > 0) {
-+ s = lineBuf;
-+
-+ for (offset = 0; offset < 16; offset++) {
-+ if (offset < numBytes)
-+ s += snprintf(s, 4, "%02x ", mem[offset]);
-+ else
-+ s += snprintf(s, 4, " ");
-+ }
-+
-+ for (offset = 0; offset < 16; offset++) {
-+ if (offset < numBytes) {
-+ uint8_t ch = mem[offset];
-+
-+ if ((ch < ' ') || (ch > '~'))
-+ ch = '.';
-+ *s++ = (char)ch;
-+ }
-+ }
-+ *s++ = '\0';
-+
-+ if ((label != NULL) && (*label != '\0'))
-+ vchiq_log_trace(VCHIQ_LOG_TRACE,
-+ "%s: %08x: %s", label, addr, lineBuf);
-+ else
-+ vchiq_log_trace(VCHIQ_LOG_TRACE,
-+ "%08x: %s", addr, lineBuf);
-+
-+ addr += 16;
-+ mem += 16;
-+ if (numBytes > 16)
-+ numBytes -= 16;
-+ else
-+ numBytes = 0;
-+ }
-+}
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,711 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_CORE_H
-+#define VCHIQ_CORE_H
-+
-+#include <linux/mutex.h>
-+#include <linux/semaphore.h>
-+#include <linux/kthread.h>
-+
-+#include "vchiq_cfg.h"
-+
-+#include "vchiq.h"
-+
-+/* Run time control of log level, based on KERN_XXX level. */
-+#define VCHIQ_LOG_DEFAULT 4
-+#define VCHIQ_LOG_ERROR 3
-+#define VCHIQ_LOG_WARNING 4
-+#define VCHIQ_LOG_INFO 6
-+#define VCHIQ_LOG_TRACE 7
-+
-+#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: "
-+
-+#ifndef vchiq_log_error
-+#define vchiq_log_error(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_ERROR) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+#ifndef vchiq_log_warning
-+#define vchiq_log_warning(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_WARNING) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+#ifndef vchiq_log_info
-+#define vchiq_log_info(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_INFO) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+#ifndef vchiq_log_trace
-+#define vchiq_log_trace(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_TRACE) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+
-+#define vchiq_loud_error(...) \
-+ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__)
-+
-+#ifndef vchiq_static_assert
-+#define vchiq_static_assert(cond) __attribute__((unused)) \
-+ extern int vchiq_static_assert[(cond) ? 1 : -1]
-+#endif
-+
-+#define IS_POW2(x) (x && ((x & (x - 1)) == 0))
-+
-+/* Ensure that the slot size and maximum number of slots are powers of 2 */
-+vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE));
-+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS));
-+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE));
-+
-+#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1)
-+#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1)
-+#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \
-+ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE)
-+
-+#define VCHIQ_MSG_PADDING 0 /* - */
-+#define VCHIQ_MSG_CONNECT 1 /* - */
-+#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */
-+#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */
-+#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */
-+#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */
-+#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */
-+#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */
-+#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */
-+#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */
-+#define VCHIQ_MSG_PAUSE 10 /* - */
-+#define VCHIQ_MSG_RESUME 11 /* - */
-+#define VCHIQ_MSG_REMOTE_USE 12 /* - */
-+#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */
-+#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */
-+
-+#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1)
-+#define VCHIQ_PORT_FREE 0x1000
-+#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE)
-+#define VCHIQ_MAKE_MSG(type, srcport, dstport) \
-+ ((type<<24) | (srcport<<12) | (dstport<<0))
-+#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24)
-+#define VCHIQ_MSG_SRCPORT(msgid) \
-+ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff)
-+#define VCHIQ_MSG_DSTPORT(msgid) \
-+ ((unsigned short)msgid & 0xfff)
-+
-+#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \
-+ ((fourcc) >> 24) & 0xff, \
-+ ((fourcc) >> 16) & 0xff, \
-+ ((fourcc) >> 8) & 0xff, \
-+ (fourcc) & 0xff
-+
-+/* Ensure the fields are wide enough */
-+vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX))
-+ == 0);
-+vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0);
-+vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX <
-+ (unsigned int)VCHIQ_PORT_FREE);
-+
-+#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0)
-+#define VCHIQ_MSGID_CLAIMED 0x40000000
-+
-+#define VCHIQ_FOURCC_INVALID 0x00000000
-+#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID)
-+
-+#define VCHIQ_BULK_ACTUAL_ABORTED -1
-+
-+typedef uint32_t BITSET_T;
-+
-+vchiq_static_assert((sizeof(BITSET_T) * 8) == 32);
-+
-+#define BITSET_SIZE(b) ((b + 31) >> 5)
-+#define BITSET_WORD(b) (b >> 5)
-+#define BITSET_BIT(b) (1 << (b & 31))
-+#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs))
-+#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b))
-+#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b))
-+#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b))
-+
-+#if VCHIQ_ENABLE_STATS
-+#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++)
-+#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++)
-+#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \
-+ (service->stats. stat += addend)
-+#else
-+#define VCHIQ_STATS_INC(state, stat) ((void)0)
-+#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0)
-+#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0)
-+#endif
-+
-+enum {
-+ DEBUG_ENTRIES,
-+#if VCHIQ_ENABLE_DEBUG
-+ DEBUG_SLOT_HANDLER_COUNT,
-+ DEBUG_SLOT_HANDLER_LINE,
-+ DEBUG_PARSE_LINE,
-+ DEBUG_PARSE_HEADER,
-+ DEBUG_PARSE_MSGID,
-+ DEBUG_AWAIT_COMPLETION_LINE,
-+ DEBUG_DEQUEUE_MESSAGE_LINE,
-+ DEBUG_SERVICE_CALLBACK_LINE,
-+ DEBUG_MSG_QUEUE_FULL_COUNT,
-+ DEBUG_COMPLETION_QUEUE_FULL_COUNT,
-+#endif
-+ DEBUG_MAX
-+};
-+
-+#if VCHIQ_ENABLE_DEBUG
-+
-+#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug;
-+#define DEBUG_TRACE(d) \
-+ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0)
-+#define DEBUG_VALUE(d, v) \
-+ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0)
-+#define DEBUG_COUNT(d) \
-+ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0)
-+
-+#else /* VCHIQ_ENABLE_DEBUG */
-+
-+#define DEBUG_INITIALISE(local)
-+#define DEBUG_TRACE(d)
-+#define DEBUG_VALUE(d, v)
-+#define DEBUG_COUNT(d)
-+
-+#endif /* VCHIQ_ENABLE_DEBUG */
-+
-+typedef enum {
-+ VCHIQ_CONNSTATE_DISCONNECTED,
-+ VCHIQ_CONNSTATE_CONNECTING,
-+ VCHIQ_CONNSTATE_CONNECTED,
-+ VCHIQ_CONNSTATE_PAUSING,
-+ VCHIQ_CONNSTATE_PAUSE_SENT,
-+ VCHIQ_CONNSTATE_PAUSED,
-+ VCHIQ_CONNSTATE_RESUMING,
-+ VCHIQ_CONNSTATE_PAUSE_TIMEOUT,
-+ VCHIQ_CONNSTATE_RESUME_TIMEOUT
-+} VCHIQ_CONNSTATE_T;
-+
-+enum {
-+ VCHIQ_SRVSTATE_FREE,
-+ VCHIQ_SRVSTATE_HIDDEN,
-+ VCHIQ_SRVSTATE_LISTENING,
-+ VCHIQ_SRVSTATE_OPENING,
-+ VCHIQ_SRVSTATE_OPEN,
-+ VCHIQ_SRVSTATE_OPENSYNC,
-+ VCHIQ_SRVSTATE_CLOSESENT,
-+ VCHIQ_SRVSTATE_CLOSERECVD,
-+ VCHIQ_SRVSTATE_CLOSEWAIT,
-+ VCHIQ_SRVSTATE_CLOSED
-+};
-+
-+enum {
-+ VCHIQ_POLL_TERMINATE,
-+ VCHIQ_POLL_REMOVE,
-+ VCHIQ_POLL_TXNOTIFY,
-+ VCHIQ_POLL_RXNOTIFY,
-+ VCHIQ_POLL_COUNT
-+};
-+
-+typedef enum {
-+ VCHIQ_BULK_TRANSMIT,
-+ VCHIQ_BULK_RECEIVE
-+} VCHIQ_BULK_DIR_T;
-+
-+typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata);
-+
-+typedef struct vchiq_bulk_struct {
-+ short mode;
-+ short dir;
-+ void *userdata;
-+ VCHI_MEM_HANDLE_T handle;
-+ void *data;
-+ int size;
-+ void *remote_data;
-+ int remote_size;
-+ int actual;
-+} VCHIQ_BULK_T;
-+
-+typedef struct vchiq_bulk_queue_struct {
-+ int local_insert; /* Where to insert the next local bulk */
-+ int remote_insert; /* Where to insert the next remote bulk (master) */
-+ int process; /* Bulk to transfer next */
-+ int remote_notify; /* Bulk to notify the remote client of next (mstr) */
-+ int remove; /* Bulk to notify the local client of, and remove,
-+ ** next */
-+ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS];
-+} VCHIQ_BULK_QUEUE_T;
-+
-+typedef struct remote_event_struct {
-+ int armed;
-+ int fired;
-+ struct semaphore *event;
-+} REMOTE_EVENT_T;
-+
-+typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T;
-+
-+typedef struct vchiq_state_struct VCHIQ_STATE_T;
-+
-+typedef struct vchiq_slot_struct {
-+ char data[VCHIQ_SLOT_SIZE];
-+} VCHIQ_SLOT_T;
-+
-+typedef struct vchiq_slot_info_struct {
-+ /* Use two counters rather than one to avoid the need for a mutex. */
-+ short use_count;
-+ short release_count;
-+} VCHIQ_SLOT_INFO_T;
-+
-+typedef struct vchiq_service_struct {
-+ VCHIQ_SERVICE_BASE_T base;
-+ VCHIQ_SERVICE_HANDLE_T handle;
-+ unsigned int ref_count;
-+ int srvstate;
-+ VCHIQ_USERDATA_TERM_T userdata_term;
-+ unsigned int localport;
-+ unsigned int remoteport;
-+ int public_fourcc;
-+ int client_id;
-+ char auto_close;
-+ char sync;
-+ char closing;
-+ char trace;
-+ atomic_t poll_flags;
-+ short version;
-+ short version_min;
-+ short peer_version;
-+
-+ VCHIQ_STATE_T *state;
-+ VCHIQ_INSTANCE_T instance;
-+
-+ int service_use_count;
-+
-+ VCHIQ_BULK_QUEUE_T bulk_tx;
-+ VCHIQ_BULK_QUEUE_T bulk_rx;
-+
-+ struct semaphore remove_event;
-+ struct semaphore bulk_remove_event;
-+ struct mutex bulk_mutex;
-+
-+ struct service_stats_struct {
-+ int quota_stalls;
-+ int slot_stalls;
-+ int bulk_stalls;
-+ int error_count;
-+ int ctrl_tx_count;
-+ int ctrl_rx_count;
-+ int bulk_tx_count;
-+ int bulk_rx_count;
-+ int bulk_aborted_count;
-+ uint64_t ctrl_tx_bytes;
-+ uint64_t ctrl_rx_bytes;
-+ uint64_t bulk_tx_bytes;
-+ uint64_t bulk_rx_bytes;
-+ } stats;
-+} VCHIQ_SERVICE_T;
-+
-+/* The quota information is outside VCHIQ_SERVICE_T so that it can be
-+ statically allocated, since for accounting reasons a service's slot
-+ usage is carried over between users of the same port number.
-+ */
-+typedef struct vchiq_service_quota_struct {
-+ unsigned short slot_quota;
-+ unsigned short slot_use_count;
-+ unsigned short message_quota;
-+ unsigned short message_use_count;
-+ struct semaphore quota_event;
-+ int previous_tx_index;
-+} VCHIQ_SERVICE_QUOTA_T;
-+
-+typedef struct vchiq_shared_state_struct {
-+
-+ /* A non-zero value here indicates that the content is valid. */
-+ int initialised;
-+
-+ /* The first and last (inclusive) slots allocated to the owner. */
-+ int slot_first;
-+ int slot_last;
-+
-+ /* The slot allocated to synchronous messages from the owner. */
-+ int slot_sync;
-+
-+ /* Signalling this event indicates that owner's slot handler thread
-+ ** should run. */
-+ REMOTE_EVENT_T trigger;
-+
-+ /* Indicates the byte position within the stream where the next message
-+ ** will be written. The least significant bits are an index into the
-+ ** slot. The next bits are the index of the slot in slot_queue. */
-+ int tx_pos;
-+
-+ /* This event should be signalled when a slot is recycled. */
-+ REMOTE_EVENT_T recycle;
-+
-+ /* The slot_queue index where the next recycled slot will be written. */
-+ int slot_queue_recycle;
-+
-+ /* This event should be signalled when a synchronous message is sent. */
-+ REMOTE_EVENT_T sync_trigger;
-+
-+ /* This event should be signalled when a synchronous message has been
-+ ** released. */
-+ REMOTE_EVENT_T sync_release;
-+
-+ /* A circular buffer of slot indexes. */
-+ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE];
-+
-+ /* Debugging state */
-+ int debug[DEBUG_MAX];
-+} VCHIQ_SHARED_STATE_T;
-+
-+typedef struct vchiq_slot_zero_struct {
-+ int magic;
-+ short version;
-+ short version_min;
-+ int slot_zero_size;
-+ int slot_size;
-+ int max_slots;
-+ int max_slots_per_side;
-+ int platform_data[2];
-+ VCHIQ_SHARED_STATE_T master;
-+ VCHIQ_SHARED_STATE_T slave;
-+ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS];
-+} VCHIQ_SLOT_ZERO_T;
-+
-+struct vchiq_state_struct {
-+ int id;
-+ int initialised;
-+ VCHIQ_CONNSTATE_T conn_state;
-+ int is_master;
-+
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_SHARED_STATE_T *remote;
-+ VCHIQ_SLOT_T *slot_data;
-+
-+ unsigned short default_slot_quota;
-+ unsigned short default_message_quota;
-+
-+ /* Event indicating connect message received */
-+ struct semaphore connect;
-+
-+ /* Mutex protecting services */
-+ struct mutex mutex;
-+ VCHIQ_INSTANCE_T *instance;
-+
-+ /* Processes incoming messages */
-+ struct task_struct *slot_handler_thread;
-+
-+ /* Processes recycled slots */
-+ struct task_struct *recycle_thread;
-+
-+ /* Processes synchronous messages */
-+ struct task_struct *sync_thread;
-+
-+ /* Local implementation of the trigger remote event */
-+ struct semaphore trigger_event;
-+
-+ /* Local implementation of the recycle remote event */
-+ struct semaphore recycle_event;
-+
-+ /* Local implementation of the sync trigger remote event */
-+ struct semaphore sync_trigger_event;
-+
-+ /* Local implementation of the sync release remote event */
-+ struct semaphore sync_release_event;
-+
-+ char *tx_data;
-+ char *rx_data;
-+ VCHIQ_SLOT_INFO_T *rx_info;
-+
-+ struct mutex slot_mutex;
-+
-+ struct mutex recycle_mutex;
-+
-+ struct mutex sync_mutex;
-+
-+ struct mutex bulk_transfer_mutex;
-+
-+ /* Indicates the byte position within the stream from where the next
-+ ** message will be read. The least significant bits are an index into
-+ ** the slot.The next bits are the index of the slot in
-+ ** remote->slot_queue. */
-+ int rx_pos;
-+
-+ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read
-+ from remote->tx_pos. */
-+ int local_tx_pos;
-+
-+ /* The slot_queue index of the slot to become available next. */
-+ int slot_queue_available;
-+
-+ /* A flag to indicate if any poll has been requested */
-+ int poll_needed;
-+
-+ /* Ths index of the previous slot used for data messages. */
-+ int previous_data_index;
-+
-+ /* The number of slots occupied by data messages. */
-+ unsigned short data_use_count;
-+
-+ /* The maximum number of slots to be occupied by data messages. */
-+ unsigned short data_quota;
-+
-+ /* An array of bit sets indicating which services must be polled. */
-+ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)];
-+
-+ /* The number of the first unused service */
-+ int unused_service;
-+
-+ /* Signalled when a free slot becomes available. */
-+ struct semaphore slot_available_event;
-+
-+ struct semaphore slot_remove_event;
-+
-+ /* Signalled when a free data slot becomes available. */
-+ struct semaphore data_quota_event;
-+
-+ /* Incremented when there are bulk transfers which cannot be processed
-+ * whilst paused and must be processed on resume */
-+ int deferred_bulks;
-+
-+ struct state_stats_struct {
-+ int slot_stalls;
-+ int data_stalls;
-+ int ctrl_tx_count;
-+ int ctrl_rx_count;
-+ int error_count;
-+ } stats;
-+
-+ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES];
-+ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES];
-+ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS];
-+
-+ VCHIQ_PLATFORM_STATE_T platform_state;
-+};
-+
-+struct bulk_waiter {
-+ VCHIQ_BULK_T *bulk;
-+ struct semaphore event;
-+ int actual;
-+};
-+
-+extern spinlock_t bulk_waiter_spinlock;
-+
-+extern int vchiq_core_log_level;
-+extern int vchiq_core_msg_log_level;
-+extern int vchiq_sync_log_level;
-+
-+extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES];
-+
-+extern const char *
-+get_conn_state_name(VCHIQ_CONNSTATE_T conn_state);
-+
-+extern VCHIQ_SLOT_ZERO_T *
-+vchiq_init_slots(void *mem_base, int mem_size);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero,
-+ int is_master);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance);
-+
-+extern VCHIQ_SERVICE_T *
-+vchiq_add_service_internal(VCHIQ_STATE_T *state,
-+ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate,
-+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd);
-+
-+extern void
-+vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_free_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_pause_internal(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_resume_internal(VCHIQ_STATE_T *state);
-+
-+extern void
-+remote_event_pollall(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir);
-+
-+extern void
-+vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_loud_error_header(void);
-+
-+extern void
-+vchiq_loud_error_footer(void);
-+
-+extern void
-+request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type);
-+
-+static inline VCHIQ_SERVICE_T *
-+handle_to_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) &
-+ (VCHIQ_MAX_STATES - 1)];
-+ if (!state)
-+ return NULL;
-+
-+ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)];
-+}
-+
-+extern VCHIQ_SERVICE_T *
-+find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_SERVICE_T *
-+find_service_by_port(VCHIQ_STATE_T *state, int localport);
-+
-+extern VCHIQ_SERVICE_T *
-+find_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_SERVICE_T *
-+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_SERVICE_T *
-+next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance,
-+ int *pidx);
-+
-+extern void
-+lock_service(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+unlock_service(VCHIQ_SERVICE_T *service);
-+
-+/* The following functions are called from vchiq_core, and external
-+** implementations must be provided. */
-+
-+extern VCHIQ_STATUS_T
-+vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk,
-+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir);
-+
-+extern void
-+vchiq_transfer_bulk(VCHIQ_BULK_T *bulk);
-+
-+extern void
-+vchiq_complete_bulk(VCHIQ_BULK_T *bulk);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_copy_from_user(void *dst, const void *src, int size);
-+
-+extern void
-+remote_event_signal(REMOTE_EVENT_T *event);
-+
-+void
-+vchiq_platform_check_suspend(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_platform_paused(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_platform_resume(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_platform_resumed(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_dump(void *dump_context, const char *str, int len);
-+
-+extern void
-+vchiq_dump_platform_state(void *dump_context);
-+
-+extern void
-+vchiq_dump_platform_instances(void *dump_context);
-+
-+extern void
-+vchiq_dump_platform_service_state(void *dump_context,
-+ VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_use_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_release_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_on_remote_use(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_on_remote_release(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_platform_init_state(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_check_service(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_on_remote_use_active(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_send_remote_use(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_send_remote_release(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_send_remote_use_active(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state,
-+ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate);
-+
-+extern void
-+vchiq_platform_handle_timeout(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate);
-+
-+
-+extern void
-+vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem,
-+ size_t numBytes);
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,383 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+#include <linux/debugfs.h>
-+#include "vchiq_core.h"
-+#include "vchiq_arm.h"
-+#include "vchiq_debugfs.h"
-+
-+#ifdef CONFIG_DEBUG_FS
-+
-+/****************************************************************************
-+*
-+* log category entries
-+*
-+***************************************************************************/
-+#define DEBUGFS_WRITE_BUF_SIZE 256
-+
-+#define VCHIQ_LOG_ERROR_STR "error"
-+#define VCHIQ_LOG_WARNING_STR "warning"
-+#define VCHIQ_LOG_INFO_STR "info"
-+#define VCHIQ_LOG_TRACE_STR "trace"
-+
-+
-+/* Top-level debug info */
-+struct vchiq_debugfs_info {
-+ /* Global 'vchiq' debugfs entry used by all instances */
-+ struct dentry *vchiq_cfg_dir;
-+
-+ /* one entry per client process */
-+ struct dentry *clients;
-+
-+ /* log categories */
-+ struct dentry *log_categories;
-+};
-+
-+static struct vchiq_debugfs_info debugfs_info;
-+
-+/* Log category debugfs entries */
-+struct vchiq_debugfs_log_entry {
-+ const char *name;
-+ int *plevel;
-+ struct dentry *dir;
-+};
-+
-+static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = {
-+ { "core", &vchiq_core_log_level },
-+ { "msg", &vchiq_core_msg_log_level },
-+ { "sync", &vchiq_sync_log_level },
-+ { "susp", &vchiq_susp_log_level },
-+ { "arm", &vchiq_arm_log_level },
-+};
-+static int n_log_entries =
-+ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]);
-+
-+
-+static struct dentry *vchiq_clients_top(void);
-+static struct dentry *vchiq_debugfs_top(void);
-+
-+static int debugfs_log_show(struct seq_file *f, void *offset)
-+{
-+ int *levp = f->private;
-+ char *log_value = NULL;
-+
-+ switch (*levp) {
-+ case VCHIQ_LOG_ERROR:
-+ log_value = VCHIQ_LOG_ERROR_STR;
-+ break;
-+ case VCHIQ_LOG_WARNING:
-+ log_value = VCHIQ_LOG_WARNING_STR;
-+ break;
-+ case VCHIQ_LOG_INFO:
-+ log_value = VCHIQ_LOG_INFO_STR;
-+ break;
-+ case VCHIQ_LOG_TRACE:
-+ log_value = VCHIQ_LOG_TRACE_STR;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ seq_printf(f, "%s\n", log_value ? log_value : "(null)");
-+
-+ return 0;
-+}
-+
-+static int debugfs_log_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, debugfs_log_show, inode->i_private);
-+}
-+
-+static int debugfs_log_write(struct file *file,
-+ const char __user *buffer,
-+ size_t count, loff_t *ppos)
-+{
-+ struct seq_file *f = (struct seq_file *)file->private_data;
-+ int *levp = f->private;
-+ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1];
-+
-+ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1);
-+ if (count >= DEBUGFS_WRITE_BUF_SIZE)
-+ count = DEBUGFS_WRITE_BUF_SIZE;
-+
-+ if (copy_from_user(kbuf, buffer, count) != 0)
-+ return -EFAULT;
-+ kbuf[count - 1] = 0;
-+
-+ if (strncmp("error", kbuf, strlen("error")) == 0)
-+ *levp = VCHIQ_LOG_ERROR;
-+ else if (strncmp("warning", kbuf, strlen("warning")) == 0)
-+ *levp = VCHIQ_LOG_WARNING;
-+ else if (strncmp("info", kbuf, strlen("info")) == 0)
-+ *levp = VCHIQ_LOG_INFO;
-+ else if (strncmp("trace", kbuf, strlen("trace")) == 0)
-+ *levp = VCHIQ_LOG_TRACE;
-+ else
-+ *levp = VCHIQ_LOG_DEFAULT;
-+
-+ *ppos += count;
-+
-+ return count;
-+}
-+
-+static const struct file_operations debugfs_log_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debugfs_log_open,
-+ .write = debugfs_log_write,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+/* create an entry under <debugfs>/vchiq/log for each log category */
-+static int vchiq_debugfs_create_log_entries(struct dentry *top)
-+{
-+ struct dentry *dir;
-+ size_t i;
-+ int ret = 0;
-+ dir = debugfs_create_dir("log", vchiq_debugfs_top());
-+ if (!dir)
-+ return -ENOMEM;
-+ debugfs_info.log_categories = dir;
-+
-+ for (i = 0; i < n_log_entries; i++) {
-+ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel;
-+ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name,
-+ 0644,
-+ debugfs_info.log_categories,
-+ levp,
-+ &debugfs_log_fops);
-+ if (!dir) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+
-+ vchiq_debugfs_log_entries[i].dir = dir;
-+ }
-+ return ret;
-+}
-+
-+static int debugfs_usecount_show(struct seq_file *f, void *offset)
-+{
-+ VCHIQ_INSTANCE_T instance = f->private;
-+ int use_count;
-+
-+ use_count = vchiq_instance_get_use_count(instance);
-+ seq_printf(f, "%d\n", use_count);
-+
-+ return 0;
-+}
-+
-+static int debugfs_usecount_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, debugfs_usecount_show, inode->i_private);
-+}
-+
-+static const struct file_operations debugfs_usecount_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debugfs_usecount_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+static int debugfs_trace_show(struct seq_file *f, void *offset)
-+{
-+ VCHIQ_INSTANCE_T instance = f->private;
-+ int trace;
-+
-+ trace = vchiq_instance_get_trace(instance);
-+ seq_printf(f, "%s\n", trace ? "Y" : "N");
-+
-+ return 0;
-+}
-+
-+static int debugfs_trace_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, debugfs_trace_show, inode->i_private);
-+}
-+
-+static int debugfs_trace_write(struct file *file,
-+ const char __user *buffer,
-+ size_t count, loff_t *ppos)
-+{
-+ struct seq_file *f = (struct seq_file *)file->private_data;
-+ VCHIQ_INSTANCE_T instance = f->private;
-+ char firstchar;
-+
-+ if (copy_from_user(&firstchar, buffer, 1) != 0)
-+ return -EFAULT;
-+
-+ switch (firstchar) {
-+ case 'Y':
-+ case 'y':
-+ case '1':
-+ vchiq_instance_set_trace(instance, 1);
-+ break;
-+ case 'N':
-+ case 'n':
-+ case '0':
-+ vchiq_instance_set_trace(instance, 0);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ *ppos += count;
-+
-+ return count;
-+}
-+
-+static const struct file_operations debugfs_trace_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debugfs_trace_open,
-+ .write = debugfs_trace_write,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+/* add an instance (process) to the debugfs entries */
-+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
-+{
-+ char pidstr[16];
-+ struct dentry *top, *use_count, *trace;
-+ struct dentry *clients = vchiq_clients_top();
-+
-+ snprintf(pidstr, sizeof(pidstr), "%d",
-+ vchiq_instance_get_pid(instance));
-+
-+ top = debugfs_create_dir(pidstr, clients);
-+ if (!top)
-+ goto fail_top;
-+
-+ use_count = debugfs_create_file("use_count",
-+ 0444, top,
-+ instance,
-+ &debugfs_usecount_fops);
-+ if (!use_count)
-+ goto fail_use_count;
-+
-+ trace = debugfs_create_file("trace",
-+ 0644, top,
-+ instance,
-+ &debugfs_trace_fops);
-+ if (!trace)
-+ goto fail_trace;
-+
-+ vchiq_instance_get_debugfs_node(instance)->dentry = top;
-+
-+ return 0;
-+
-+fail_trace:
-+ debugfs_remove(use_count);
-+fail_use_count:
-+ debugfs_remove(top);
-+fail_top:
-+ return -ENOMEM;
-+}
-+
-+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance);
-+ debugfs_remove_recursive(node->dentry);
-+}
-+
-+
-+int vchiq_debugfs_init(void)
-+{
-+ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL);
-+
-+ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL);
-+ if (debugfs_info.vchiq_cfg_dir == NULL)
-+ goto fail;
-+
-+ debugfs_info.clients = debugfs_create_dir("clients",
-+ vchiq_debugfs_top());
-+ if (!debugfs_info.clients)
-+ goto fail;
-+
-+ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0)
-+ goto fail;
-+
-+ return 0;
-+
-+fail:
-+ vchiq_debugfs_deinit();
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "%s: failed to create debugfs directory",
-+ __func__);
-+
-+ return -ENOMEM;
-+}
-+
-+/* remove all the debugfs entries */
-+void vchiq_debugfs_deinit(void)
-+{
-+ debugfs_remove_recursive(vchiq_debugfs_top());
-+}
-+
-+static struct dentry *vchiq_clients_top(void)
-+{
-+ return debugfs_info.clients;
-+}
-+
-+static struct dentry *vchiq_debugfs_top(void)
-+{
-+ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL);
-+ return debugfs_info.vchiq_cfg_dir;
-+}
-+
-+#else /* CONFIG_DEBUG_FS */
-+
-+int vchiq_debugfs_init(void)
-+{
-+ return 0;
-+}
-+
-+void vchiq_debugfs_deinit(void)
-+{
-+}
-+
-+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
-+{
-+ return 0;
-+}
-+
-+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
-+{
-+}
-+
-+#endif /* CONFIG_DEBUG_FS */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,52 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_DEBUGFS_H
-+#define VCHIQ_DEBUGFS_H
-+
-+#include "vchiq_core.h"
-+
-+typedef struct vchiq_debugfs_node_struct
-+{
-+ struct dentry *dentry;
-+} VCHIQ_DEBUGFS_NODE_T;
-+
-+int vchiq_debugfs_init(void);
-+
-+void vchiq_debugfs_deinit(void);
-+
-+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance);
-+
-+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance);
-+
-+#endif /* VCHIQ_DEBUGFS_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,87 @@
-+#!/usr/bin/perl -w
-+
-+use strict;
-+
-+#
-+# Generate a version from available information
-+#
-+
-+my $prefix = shift @ARGV;
-+my $root = shift @ARGV;
-+
-+
-+if ( not defined $root ) {
-+ die "usage: $0 prefix root-dir\n";
-+}
-+
-+if ( ! -d $root ) {
-+ die "root directory $root not found\n";
-+}
-+
-+my $version = "unknown";
-+my $tainted = "";
-+
-+if ( -d "$root/.git" ) {
-+ # attempt to work out git version. only do so
-+ # on a linux build host, as cygwin builds are
-+ # already slow enough
-+
-+ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) {
-+ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) {
-+ $version = "no git version";
-+ }
-+ else {
-+ $version = <F>;
-+ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
-+ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
-+ }
-+
-+ if (open(G, "git --git-dir $root/.git status --porcelain|")) {
-+ $tainted = <G>;
-+ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
-+ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
-+ if (length $tainted) {
-+ $version = join ' ', $version, "(tainted)";
-+ }
-+ else {
-+ $version = join ' ', $version, "(clean)";
-+ }
-+ }
-+ }
-+}
-+
-+my $hostname = `hostname`;
-+$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
-+$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
-+
-+
-+print STDERR "Version $version\n";
-+print <<EOF;
-+#include "${prefix}_build_info.h"
-+#include <linux/broadcom/vc_debug_sym.h>
-+
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" );
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" );
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ );
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ );
-+
-+const char *vchiq_get_build_hostname( void )
-+{
-+ return vchiq_build_hostname;
-+}
-+
-+const char *vchiq_get_build_version( void )
-+{
-+ return vchiq_build_version;
-+}
-+
-+const char *vchiq_get_build_date( void )
-+{
-+ return vchiq_build_date;
-+}
-+
-+const char *vchiq_get_build_time( void )
-+{
-+ return vchiq_build_time;
-+}
-+EOF
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2015-03-09 10:39:30.718893733 +0100
-@@ -0,0 +1,40 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_VCHIQ_H
-+#define VCHIQ_VCHIQ_H
-+
-+#include "vchiq_if.h"
-+#include "vchiq_util.h"
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,189 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_IF_H
-+#define VCHIQ_IF_H
-+
-+#include "interface/vchi/vchi_mh.h"
-+
-+#define VCHIQ_SERVICE_HANDLE_INVALID 0
-+
-+#define VCHIQ_SLOT_SIZE 4096
-+#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T))
-+#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */
-+
-+#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \
-+ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3))
-+#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service)
-+#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service)
-+
-+typedef enum {
-+ VCHIQ_SERVICE_OPENED, /* service, -, - */
-+ VCHIQ_SERVICE_CLOSED, /* service, -, - */
-+ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */
-+ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */
-+ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */
-+ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */
-+ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */
-+} VCHIQ_REASON_T;
-+
-+typedef enum {
-+ VCHIQ_ERROR = -1,
-+ VCHIQ_SUCCESS = 0,
-+ VCHIQ_RETRY = 1
-+} VCHIQ_STATUS_T;
-+
-+typedef enum {
-+ VCHIQ_BULK_MODE_CALLBACK,
-+ VCHIQ_BULK_MODE_BLOCKING,
-+ VCHIQ_BULK_MODE_NOCALLBACK,
-+ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */
-+} VCHIQ_BULK_MODE_T;
-+
-+typedef enum {
-+ VCHIQ_SERVICE_OPTION_AUTOCLOSE,
-+ VCHIQ_SERVICE_OPTION_SLOT_QUOTA,
-+ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA,
-+ VCHIQ_SERVICE_OPTION_SYNCHRONOUS,
-+ VCHIQ_SERVICE_OPTION_TRACE
-+} VCHIQ_SERVICE_OPTION_T;
-+
-+typedef struct vchiq_header_struct {
-+ /* The message identifier - opaque to applications. */
-+ int msgid;
-+
-+ /* Size of message data. */
-+ unsigned int size;
-+
-+ char data[0]; /* message */
-+} VCHIQ_HEADER_T;
-+
-+typedef struct {
-+ const void *data;
-+ unsigned int size;
-+} VCHIQ_ELEMENT_T;
-+
-+typedef unsigned int VCHIQ_SERVICE_HANDLE_T;
-+
-+typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *,
-+ VCHIQ_SERVICE_HANDLE_T, void *);
-+
-+typedef struct vchiq_service_base_struct {
-+ int fourcc;
-+ VCHIQ_CALLBACK_T callback;
-+ void *userdata;
-+} VCHIQ_SERVICE_BASE_T;
-+
-+typedef struct vchiq_service_params_struct {
-+ int fourcc;
-+ VCHIQ_CALLBACK_T callback;
-+ void *userdata;
-+ short version; /* Increment for non-trivial changes */
-+ short version_min; /* Update for incompatible changes */
-+} VCHIQ_SERVICE_PARAMS_T;
-+
-+typedef struct vchiq_config_struct {
-+ unsigned int max_msg_size;
-+ unsigned int bulk_threshold; /* The message size above which it
-+ is better to use a bulk transfer
-+ (<= max_msg_size) */
-+ unsigned int max_outstanding_bulks;
-+ unsigned int max_services;
-+ short version; /* The version of VCHIQ */
-+ short version_min; /* The minimum compatible version of VCHIQ */
-+} VCHIQ_CONFIG_T;
-+
-+typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T;
-+typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg);
-+
-+extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance);
-+extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance);
-+extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance);
-+extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *pservice);
-+extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *pservice);
-+extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_use_service_no_resume(
-+ VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service);
-+
-+extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service,
-+ const VCHIQ_ELEMENT_T *elements, unsigned int count);
-+extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHIQ_HEADER_T *header);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
-+ const void *data, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service,
-+ void *data, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle(
-+ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle,
-+ const void *offset, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle(
-+ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle,
-+ void *offset, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
-+ const void *data, unsigned int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode);
-+extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service,
-+ void *data, unsigned int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode);
-+extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHI_MEM_HANDLE_T handle, const void *offset, unsigned int size,
-+ void *userdata, VCHIQ_BULK_MODE_T mode);
-+extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHI_MEM_HANDLE_T handle, void *offset, unsigned int size,
-+ void *userdata, VCHIQ_BULK_MODE_T mode);
-+extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service);
-+extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service);
-+extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance,
-+ int config_size, VCHIQ_CONFIG_T *pconfig);
-+extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHIQ_SERVICE_OPTION_T option, int value);
-+
-+extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg);
-+extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance);
-+
-+extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service,
-+ void *ptr, size_t num_bytes);
-+
-+extern VCHIQ_STATUS_T vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle,
-+ short *peer_version);
-+
-+#endif /* VCHIQ_IF_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,131 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_IOCTLS_H
-+#define VCHIQ_IOCTLS_H
-+
-+#include <linux/ioctl.h>
-+#include "vchiq_if.h"
-+
-+#define VCHIQ_IOC_MAGIC 0xc4
-+#define VCHIQ_INVALID_HANDLE (~0)
-+
-+typedef struct {
-+ VCHIQ_SERVICE_PARAMS_T params;
-+ int is_open;
-+ int is_vchi;
-+ unsigned int handle; /* OUT */
-+} VCHIQ_CREATE_SERVICE_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ unsigned int count;
-+ const VCHIQ_ELEMENT_T *elements;
-+} VCHIQ_QUEUE_MESSAGE_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ void *data;
-+ unsigned int size;
-+ void *userdata;
-+ VCHIQ_BULK_MODE_T mode;
-+} VCHIQ_QUEUE_BULK_TRANSFER_T;
-+
-+typedef struct {
-+ VCHIQ_REASON_T reason;
-+ VCHIQ_HEADER_T *header;
-+ void *service_userdata;
-+ void *bulk_userdata;
-+} VCHIQ_COMPLETION_DATA_T;
-+
-+typedef struct {
-+ unsigned int count;
-+ VCHIQ_COMPLETION_DATA_T *buf;
-+ unsigned int msgbufsize;
-+ unsigned int msgbufcount; /* IN/OUT */
-+ void **msgbufs;
-+} VCHIQ_AWAIT_COMPLETION_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ int blocking;
-+ unsigned int bufsize;
-+ void *buf;
-+} VCHIQ_DEQUEUE_MESSAGE_T;
-+
-+typedef struct {
-+ unsigned int config_size;
-+ VCHIQ_CONFIG_T *pconfig;
-+} VCHIQ_GET_CONFIG_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ VCHIQ_SERVICE_OPTION_T option;
-+ int value;
-+} VCHIQ_SET_SERVICE_OPTION_T;
-+
-+typedef struct {
-+ void *virt_addr;
-+ size_t num_bytes;
-+} VCHIQ_DUMP_MEM_T;
-+
-+#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0)
-+#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1)
-+#define VCHIQ_IOC_CREATE_SERVICE \
-+ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T)
-+#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3)
-+#define VCHIQ_IOC_QUEUE_MESSAGE \
-+ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T)
-+#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \
-+ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T)
-+#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \
-+ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T)
-+#define VCHIQ_IOC_AWAIT_COMPLETION \
-+ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T)
-+#define VCHIQ_IOC_DEQUEUE_MESSAGE \
-+ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T)
-+#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9)
-+#define VCHIQ_IOC_GET_CONFIG \
-+ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T)
-+#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11)
-+#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12)
-+#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13)
-+#define VCHIQ_IOC_SET_SERVICE_OPTION \
-+ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T)
-+#define VCHIQ_IOC_DUMP_PHYS_MEM \
-+ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T)
-+#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16)
-+#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17)
-+#define VCHIQ_IOC_MAX 17
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,458 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+/* ---- Include Files ---------------------------------------------------- */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+
-+#include "vchiq_core.h"
-+#include "vchiq_arm.h"
-+#include "vchiq_killable.h"
-+
-+/* ---- Public Variables ------------------------------------------------- */
-+
-+/* ---- Private Constants and Types -------------------------------------- */
-+
-+struct bulk_waiter_node {
-+ struct bulk_waiter bulk_waiter;
-+ int pid;
-+ struct list_head list;
-+};
-+
-+struct vchiq_instance_struct {
-+ VCHIQ_STATE_T *state;
-+
-+ int connected;
-+
-+ struct list_head bulk_waiter_list;
-+ struct mutex bulk_waiter_list_mutex;
-+};
-+
-+static VCHIQ_STATUS_T
-+vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, VCHIQ_BULK_DIR_T dir);
-+
-+/****************************************************************************
-+*
-+* vchiq_initialise
-+*
-+***************************************************************************/
-+#define VCHIQ_INIT_RETRIES 10
-+VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_STATE_T *state;
-+ VCHIQ_INSTANCE_T instance = NULL;
-+ int i;
-+
-+ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__);
-+
-+ /* VideoCore may not be ready due to boot up timing.
-+ It may never be ready if kernel and firmware are mismatched, so don't block forever. */
-+ for (i=0; i<VCHIQ_INIT_RETRIES; i++) {
-+ state = vchiq_get_state();
-+ if (state)
-+ break;
-+ udelay(500);
-+ }
-+ if (i==VCHIQ_INIT_RETRIES) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%s: videocore not initialized\n", __func__);
-+ goto failed;
-+ } else if (i>0) {
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%s: videocore initialized after %d retries\n", __func__, i);
-+ }
-+
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+ if (!instance) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%s: error allocating vchiq instance\n", __func__);
-+ goto failed;
-+ }
-+
-+ instance->connected = 0;
-+ instance->state = state;
-+ mutex_init(&instance->bulk_waiter_list_mutex);
-+ INIT_LIST_HEAD(&instance->bulk_waiter_list);
-+
-+ *instanceOut = instance;
-+
-+ status = VCHIQ_SUCCESS;
-+
-+failed:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_initialise);
-+
-+/****************************************************************************
-+*
-+* vchiq_shutdown
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_STATE_T *state = instance->state;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ if (mutex_lock_interruptible(&state->mutex) != 0)
-+ return VCHIQ_RETRY;
-+
-+ /* Remove all services */
-+ status = vchiq_shutdown_internal(state, instance);
-+
-+ mutex_unlock(&state->mutex);
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ struct list_head *pos, *next;
-+ list_for_each_safe(pos, next,
-+ &instance->bulk_waiter_list) {
-+ struct bulk_waiter_node *waiter;
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "bulk_waiter - cleaned up %x "
-+ "for pid %d",
-+ (unsigned int)waiter, waiter->pid);
-+ kfree(waiter);
-+ }
-+ kfree(instance);
-+ }
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_shutdown);
-+
-+/****************************************************************************
-+*
-+* vchiq_is_connected
-+*
-+***************************************************************************/
-+
-+int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
-+{
-+ return instance->connected;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_connect
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_STATE_T *state = instance->state;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ if (mutex_lock_interruptible(&state->mutex) != 0) {
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s: call to mutex_lock failed", __func__);
-+ status = VCHIQ_RETRY;
-+ goto failed;
-+ }
-+ status = vchiq_connect_internal(state, instance);
-+
-+ if (status == VCHIQ_SUCCESS)
-+ instance->connected = 1;
-+
-+ mutex_unlock(&state->mutex);
-+
-+failed:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_connect);
-+
-+/****************************************************************************
-+*
-+* vchiq_add_service
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_add_service(
-+ VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *phandle)
-+{
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_STATE_T *state = instance->state;
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int srvstate;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
-+
-+ srvstate = vchiq_is_connected(instance)
-+ ? VCHIQ_SRVSTATE_LISTENING
-+ : VCHIQ_SRVSTATE_HIDDEN;
-+
-+ service = vchiq_add_service_internal(
-+ state,
-+ params,
-+ srvstate,
-+ instance,
-+ NULL);
-+
-+ if (service) {
-+ *phandle = service->handle;
-+ status = VCHIQ_SUCCESS;
-+ } else
-+ status = VCHIQ_ERROR;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_add_service);
-+
-+/****************************************************************************
-+*
-+* vchiq_open_service
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_open_service(
-+ VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *phandle)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_STATE_T *state = instance->state;
-+ VCHIQ_SERVICE_T *service = NULL;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
-+
-+ if (!vchiq_is_connected(instance))
-+ goto failed;
-+
-+ service = vchiq_add_service_internal(state,
-+ params,
-+ VCHIQ_SRVSTATE_OPENING,
-+ instance,
-+ NULL);
-+
-+ if (service) {
-+ *phandle = service->handle;
-+ status = vchiq_open_service_internal(service, current->pid);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_remove_service(service->handle);
-+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
-+ }
-+ }
-+
-+failed:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_open_service);
-+
-+VCHIQ_STATUS_T
-+vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle,
-+ const void *data, unsigned int size, void *userdata)
-+{
-+ return vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata,
-+ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT);
-+}
-+EXPORT_SYMBOL(vchiq_queue_bulk_transmit);
-+
-+VCHIQ_STATUS_T
-+vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, void *userdata)
-+{
-+ return vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, data, size, userdata,
-+ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE);
-+}
-+EXPORT_SYMBOL(vchiq_queue_bulk_receive);
-+
-+VCHIQ_STATUS_T
-+vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data,
-+ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode)
-+{
-+ VCHIQ_STATUS_T status;
-+
-+ switch (mode) {
-+ case VCHIQ_BULK_MODE_NOCALLBACK:
-+ case VCHIQ_BULK_MODE_CALLBACK:
-+ status = vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata,
-+ mode, VCHIQ_BULK_TRANSMIT);
-+ break;
-+ case VCHIQ_BULK_MODE_BLOCKING:
-+ status = vchiq_blocking_bulk_transfer(handle,
-+ (void *)data, size, VCHIQ_BULK_TRANSMIT);
-+ break;
-+ default:
-+ return VCHIQ_ERROR;
-+ }
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_bulk_transmit);
-+
-+VCHIQ_STATUS_T
-+vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode)
-+{
-+ VCHIQ_STATUS_T status;
-+
-+ switch (mode) {
-+ case VCHIQ_BULK_MODE_NOCALLBACK:
-+ case VCHIQ_BULK_MODE_CALLBACK:
-+ status = vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, data, size, userdata,
-+ mode, VCHIQ_BULK_RECEIVE);
-+ break;
-+ case VCHIQ_BULK_MODE_BLOCKING:
-+ status = vchiq_blocking_bulk_transfer(handle,
-+ (void *)data, size, VCHIQ_BULK_RECEIVE);
-+ break;
-+ default:
-+ return VCHIQ_ERROR;
-+ }
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_bulk_receive);
-+
-+static VCHIQ_STATUS_T
-+vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, VCHIQ_BULK_DIR_T dir)
-+{
-+ VCHIQ_INSTANCE_T instance;
-+ VCHIQ_SERVICE_T *service;
-+ VCHIQ_STATUS_T status;
-+ struct bulk_waiter_node *waiter = NULL;
-+ struct list_head *pos;
-+
-+ service = find_service_by_handle(handle);
-+ if (!service)
-+ return VCHIQ_ERROR;
-+
-+ instance = service->instance;
-+
-+ unlock_service(service);
-+
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_for_each(pos, &instance->bulk_waiter_list) {
-+ if (list_entry(pos, struct bulk_waiter_node,
-+ list)->pid == current->pid) {
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ break;
-+ }
-+ }
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+
-+ if (waiter) {
-+ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk;
-+ if (bulk) {
-+ /* This thread has an outstanding bulk transfer. */
-+ if ((bulk->data != data) ||
-+ (bulk->size != size)) {
-+ /* This is not a retry of the previous one.
-+ ** Cancel the signal when the transfer
-+ ** completes. */
-+ spin_lock(&bulk_waiter_spinlock);
-+ bulk->userdata = NULL;
-+ spin_unlock(&bulk_waiter_spinlock);
-+ }
-+ }
-+ }
-+
-+ if (!waiter) {
-+ waiter = kzalloc(sizeof(struct bulk_waiter_node), GFP_KERNEL);
-+ if (!waiter) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%s - out of memory", __func__);
-+ return VCHIQ_ERROR;
-+ }
-+ }
-+
-+ status = vchiq_bulk_transfer(handle, VCHI_MEM_HANDLE_INVALID,
-+ data, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING,
-+ dir);
-+ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) ||
-+ !waiter->bulk_waiter.bulk) {
-+ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk;
-+ if (bulk) {
-+ /* Cancel the signal when the transfer
-+ ** completes. */
-+ spin_lock(&bulk_waiter_spinlock);
-+ bulk->userdata = NULL;
-+ spin_unlock(&bulk_waiter_spinlock);
-+ }
-+ kfree(waiter);
-+ } else {
-+ waiter->pid = current->pid;
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_add(&waiter->list, &instance->bulk_waiter_list);
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "saved bulk_waiter %x for pid %d",
-+ (unsigned int)waiter, current->pid);
-+ }
-+
-+ return status;
-+}
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,69 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_KILLABLE_H
-+#define VCHIQ_KILLABLE_H
-+
-+#include <linux/mutex.h>
-+#include <linux/semaphore.h>
-+
-+#define SHUTDOWN_SIGS (sigmask(SIGKILL) | sigmask(SIGINT) | sigmask(SIGQUIT) | sigmask(SIGTRAP) | sigmask(SIGSTOP) | sigmask(SIGCONT))
-+
-+static inline int __must_check down_interruptible_killable(struct semaphore *sem)
-+{
-+ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */
-+ int ret;
-+ sigset_t blocked, oldset;
-+ siginitsetinv(&blocked, SHUTDOWN_SIGS);
-+ sigprocmask(SIG_SETMASK, &blocked, &oldset);
-+ ret = down_interruptible(sem);
-+ sigprocmask(SIG_SETMASK, &oldset, NULL);
-+ return ret;
-+}
-+#define down_interruptible down_interruptible_killable
-+
-+
-+static inline int __must_check mutex_lock_interruptible_killable(struct mutex *lock)
-+{
-+ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */
-+ int ret;
-+ sigset_t blocked, oldset;
-+ siginitsetinv(&blocked, SHUTDOWN_SIGS);
-+ sigprocmask(SIG_SETMASK, &blocked, &oldset);
-+ ret = mutex_lock_interruptible(lock);
-+ sigprocmask(SIG_SETMASK, &oldset, NULL);
-+ return ret;
-+}
-+#define mutex_lock_interruptible mutex_lock_interruptible_killable
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,71 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_MEMDRV_H
-+#define VCHIQ_MEMDRV_H
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+#include <linux/kernel.h>
-+#include "vchiq_if.h"
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+typedef struct {
-+ void *armSharedMemVirt;
-+ dma_addr_t armSharedMemPhys;
-+ size_t armSharedMemSize;
-+
-+ void *vcSharedMemVirt;
-+ dma_addr_t vcSharedMemPhys;
-+ size_t vcSharedMemSize;
-+} VCHIQ_SHARED_MEM_INFO_T;
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info);
-+
-+VCHIQ_STATUS_T vchiq_memdrv_initialise(void);
-+
-+VCHIQ_STATUS_T vchiq_userdrv_create_instance(
-+ const VCHIQ_PLATFORM_DATA_T * platform_data);
-+
-+VCHIQ_STATUS_T vchiq_userdrv_suspend(
-+ const VCHIQ_PLATFORM_DATA_T * platform_data);
-+
-+VCHIQ_STATUS_T vchiq_userdrv_resume(
-+ const VCHIQ_PLATFORM_DATA_T * platform_data);
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,58 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_PAGELIST_H
-+#define VCHIQ_PAGELIST_H
-+
-+#ifndef PAGE_SIZE
-+#define PAGE_SIZE 4096
-+#endif
-+#define CACHE_LINE_SIZE 32
-+#define PAGELIST_WRITE 0
-+#define PAGELIST_READ 1
-+#define PAGELIST_READ_WITH_FRAGMENTS 2
-+
-+typedef struct pagelist_struct {
-+ unsigned long length;
-+ unsigned short type;
-+ unsigned short offset;
-+ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following
-+ pages at consecutive addresses. */
-+} PAGELIST_T;
-+
-+typedef struct fragments_struct {
-+ char headbuf[CACHE_LINE_SIZE];
-+ char tailbuf[CACHE_LINE_SIZE];
-+} FRAGMENTS_T;
-+
-+#endif /* VCHIQ_PAGELIST_H */
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,857 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include <linux/module.h>
-+#include <linux/types.h>
-+
-+#include "interface/vchi/vchi.h"
-+#include "vchiq.h"
-+#include "vchiq_core.h"
-+
-+#include "vchiq_util.h"
-+
-+#include <stddef.h>
-+
-+#define vchiq_status_to_vchi(status) ((int32_t)status)
-+
-+typedef struct {
-+ VCHIQ_SERVICE_HANDLE_T handle;
-+
-+ VCHIU_QUEUE_T queue;
-+
-+ VCHI_CALLBACK_T callback;
-+ void *callback_param;
-+} SHIM_SERVICE_T;
-+
-+/* ----------------------------------------------------------------------
-+ * return pointer to the mphi message driver function table
-+ * -------------------------------------------------------------------- */
-+const VCHI_MESSAGE_DRIVER_T *
-+vchi_mphi_message_driver_func_table(void)
-+{
-+ return NULL;
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * return a pointer to the 'single' connection driver fops
-+ * -------------------------------------------------------------------- */
-+const VCHI_CONNECTION_API_T *
-+single_get_func_table(void)
-+{
-+ return NULL;
-+}
-+
-+VCHI_CONNECTION_T *vchi_create_connection(
-+ const VCHI_CONNECTION_API_T *function_table,
-+ const VCHI_MESSAGE_DRIVER_T *low_level)
-+{
-+ (void)function_table;
-+ (void)low_level;
-+ return NULL;
-+}
-+
-+/***********************************************************
-+ * Name: vchi_msg_peek
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle,
-+ * void **data,
-+ * uint32_t *msg_size,
-+
-+
-+ * VCHI_FLAGS_T flags
-+ *
-+ * Description: Routine to return a pointer to the current message (to allow in
-+ * place processing). The message can be removed using
-+ * vchi_msg_remove when you're finished
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ WARN_ON((flags != VCHI_FLAGS_NONE) &&
-+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
-+
-+ if (flags == VCHI_FLAGS_NONE)
-+ if (vchiu_queue_is_empty(&service->queue))
-+ return -1;
-+
-+ header = vchiu_queue_peek(&service->queue);
-+
-+ *data = header->data;
-+ *msg_size = header->size;
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_peek);
-+
-+/***********************************************************
-+ * Name: vchi_msg_remove
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle,
-+ *
-+ * Description: Routine to remove a message (after it has been read with
-+ * vchi_msg_peek)
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ header = vchiu_queue_pop(&service->queue);
-+
-+ vchiq_release_message(service->handle, header);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_remove);
-+
-+/***********************************************************
-+ * Name: vchi_msg_queue
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * const void *data,
-+ * uint32_t data_size,
-+ * VCHI_FLAGS_T flags,
-+ * void *msg_handle,
-+ *
-+ * Description: Thin wrapper to queue a message onto a connection
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
-+ const void *data,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_ELEMENT_T element = {data, data_size};
-+ VCHIQ_STATUS_T status;
-+
-+ (void)msg_handle;
-+
-+ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
-+
-+ status = vchiq_queue_message(service->handle, &element, 1);
-+
-+ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to
-+ ** implement a retry mechanism since this function is supposed
-+ ** to block until queued
-+ */
-+ while (status == VCHIQ_RETRY) {
-+ msleep(1);
-+ status = vchiq_queue_message(service->handle, &element, 1);
-+ }
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_msg_queue);
-+
-+/***********************************************************
-+ * Name: vchi_bulk_queue_receive
-+ *
-+ * Arguments: VCHI_BULK_HANDLE_T handle,
-+ * void *data_dst,
-+ * const uint32_t data_size,
-+ * VCHI_FLAGS_T flags
-+ * void *bulk_handle
-+ *
-+ * Description: Routine to setup a rcv buffer
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle,
-+ void *data_dst,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_BULK_MODE_T mode;
-+ VCHIQ_STATUS_T status;
-+
-+ switch ((int)flags) {
-+ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
-+ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ WARN_ON(!service->callback);
-+ mode = VCHIQ_BULK_MODE_CALLBACK;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE:
-+ mode = VCHIQ_BULK_MODE_BLOCKING;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ case VCHI_FLAGS_NONE:
-+ mode = VCHIQ_BULK_MODE_NOCALLBACK;
-+ break;
-+ default:
-+ WARN(1, "unsupported message\n");
-+ return vchiq_status_to_vchi(VCHIQ_ERROR);
-+ }
-+
-+ status = vchiq_bulk_receive(service->handle, data_dst, data_size,
-+ bulk_handle, mode);
-+
-+ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to
-+ ** implement a retry mechanism since this function is supposed
-+ ** to block until queued
-+ */
-+ while (status == VCHIQ_RETRY) {
-+ msleep(1);
-+ status = vchiq_bulk_receive(service->handle, data_dst,
-+ data_size, bulk_handle, mode);
-+ }
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_bulk_queue_receive);
-+
-+/***********************************************************
-+ * Name: vchi_bulk_queue_transmit
-+ *
-+ * Arguments: VCHI_BULK_HANDLE_T handle,
-+ * const void *data_src,
-+ * uint32_t data_size,
-+ * VCHI_FLAGS_T flags,
-+ * void *bulk_handle
-+ *
-+ * Description: Routine to transmit some data
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle,
-+ const void *data_src,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_BULK_MODE_T mode;
-+ VCHIQ_STATUS_T status;
-+
-+ switch ((int)flags) {
-+ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
-+ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ WARN_ON(!service->callback);
-+ mode = VCHIQ_BULK_MODE_CALLBACK;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ:
-+ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE:
-+ mode = VCHIQ_BULK_MODE_BLOCKING;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ case VCHI_FLAGS_NONE:
-+ mode = VCHIQ_BULK_MODE_NOCALLBACK;
-+ break;
-+ default:
-+ WARN(1, "unsupported message\n");
-+ return vchiq_status_to_vchi(VCHIQ_ERROR);
-+ }
-+
-+ status = vchiq_bulk_transmit(service->handle, data_src, data_size,
-+ bulk_handle, mode);
-+
-+ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to
-+ ** implement a retry mechanism since this function is supposed
-+ ** to block until queued
-+ */
-+ while (status == VCHIQ_RETRY) {
-+ msleep(1);
-+ status = vchiq_bulk_transmit(service->handle, data_src,
-+ data_size, bulk_handle, mode);
-+ }
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_bulk_queue_transmit);
-+
-+/***********************************************************
-+ * Name: vchi_msg_dequeue
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * void *data,
-+ * uint32_t max_data_size_to_read,
-+ * uint32_t *actual_msg_size
-+ * VCHI_FLAGS_T flags
-+ *
-+ * Description: Routine to dequeue a message into the supplied buffer
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle,
-+ void *data,
-+ uint32_t max_data_size_to_read,
-+ uint32_t *actual_msg_size,
-+ VCHI_FLAGS_T flags)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ WARN_ON((flags != VCHI_FLAGS_NONE) &&
-+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
-+
-+ if (flags == VCHI_FLAGS_NONE)
-+ if (vchiu_queue_is_empty(&service->queue))
-+ return -1;
-+
-+ header = vchiu_queue_pop(&service->queue);
-+
-+ memcpy(data, header->data, header->size < max_data_size_to_read ?
-+ header->size : max_data_size_to_read);
-+
-+ *actual_msg_size = header->size;
-+
-+ vchiq_release_message(service->handle, header);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_dequeue);
-+
-+/***********************************************************
-+ * Name: vchi_msg_queuev
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * VCHI_MSG_VECTOR_T *vector,
-+ * uint32_t count,
-+ * VCHI_FLAGS_T flags,
-+ * void *msg_handle
-+ *
-+ * Description: Thin wrapper to queue a message onto a connection
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+
-+vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T));
-+vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) ==
-+ offsetof(VCHIQ_ELEMENT_T, data));
-+vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) ==
-+ offsetof(VCHIQ_ELEMENT_T, size));
-+
-+int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_VECTOR_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+
-+ (void)msg_handle;
-+
-+ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
-+
-+ return vchiq_status_to_vchi(vchiq_queue_message(service->handle,
-+ (const VCHIQ_ELEMENT_T *)vector, count));
-+}
-+EXPORT_SYMBOL(vchi_msg_queuev);
-+
-+/***********************************************************
-+ * Name: vchi_held_msg_release
-+ *
-+ * Arguments: VCHI_HELD_MSG_T *message
-+ *
-+ * Description: Routine to release a held message (after it has been read with
-+ * vchi_msg_hold)
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message)
-+{
-+ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service,
-+ (VCHIQ_HEADER_T *)message->message);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_held_msg_release);
-+
-+/***********************************************************
-+ * Name: vchi_msg_hold
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * void **data,
-+ * uint32_t *msg_size,
-+ * VCHI_FLAGS_T flags,
-+ * VCHI_HELD_MSG_T *message_handle
-+ *
-+ * Description: Routine to return a pointer to the current message (to allow
-+ * in place processing). The message is dequeued - don't forget
-+ * to release the message using vchi_held_msg_release when you're
-+ * finished.
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags,
-+ VCHI_HELD_MSG_T *message_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ WARN_ON((flags != VCHI_FLAGS_NONE) &&
-+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
-+
-+ if (flags == VCHI_FLAGS_NONE)
-+ if (vchiu_queue_is_empty(&service->queue))
-+ return -1;
-+
-+ header = vchiu_queue_pop(&service->queue);
-+
-+ *data = header->data;
-+ *msg_size = header->size;
-+
-+ message_handle->service =
-+ (struct opaque_vchi_service_t *)service->handle;
-+ message_handle->message = header;
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_hold);
-+
-+/***********************************************************
-+ * Name: vchi_initialise
-+ *
-+ * Arguments: VCHI_INSTANCE_T *instance_handle
-+ *
-+ * Description: Initialises the hardware but does not transmit anything
-+ * When run as a Host App this will be called twice hence the need
-+ * to malloc the state information
-+ *
-+ * Returns: 0 if successful, failure otherwise
-+ *
-+ ***********************************************************/
-+
-+int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle)
-+{
-+ VCHIQ_INSTANCE_T instance;
-+ VCHIQ_STATUS_T status;
-+
-+ status = vchiq_initialise(&instance);
-+
-+ *instance_handle = (VCHI_INSTANCE_T)instance;
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_initialise);
-+
-+/***********************************************************
-+ * Name: vchi_connect
-+ *
-+ * Arguments: VCHI_CONNECTION_T **connections
-+ * const uint32_t num_connections
-+ * VCHI_INSTANCE_T instance_handle)
-+ *
-+ * Description: Starts the command service on each connection,
-+ * causing INIT messages to be pinged back and forth
-+ *
-+ * Returns: 0 if successful, failure otherwise
-+ *
-+ ***********************************************************/
-+int32_t vchi_connect(VCHI_CONNECTION_T **connections,
-+ const uint32_t num_connections,
-+ VCHI_INSTANCE_T instance_handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+
-+ (void)connections;
-+ (void)num_connections;
-+
-+ return vchiq_connect(instance);
-+}
-+EXPORT_SYMBOL(vchi_connect);
-+
-+
-+/***********************************************************
-+ * Name: vchi_disconnect
-+ *
-+ * Arguments: VCHI_INSTANCE_T instance_handle
-+ *
-+ * Description: Stops the command service on each connection,
-+ * causing DE-INIT messages to be pinged back and forth
-+ *
-+ * Returns: 0 if successful, failure otherwise
-+ *
-+ ***********************************************************/
-+int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+ return vchiq_status_to_vchi(vchiq_shutdown(instance));
-+}
-+EXPORT_SYMBOL(vchi_disconnect);
-+
-+
-+/***********************************************************
-+ * Name: vchi_service_open
-+ * Name: vchi_service_create
-+ *
-+ * Arguments: VCHI_INSTANCE_T *instance_handle
-+ * SERVICE_CREATION_T *setup,
-+ * VCHI_SERVICE_HANDLE_T *handle
-+ *
-+ * Description: Routine to open a service
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+
-+static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user)
-+{
-+ SHIM_SERVICE_T *service =
-+ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle);
-+
-+ if (!service->callback)
-+ goto release;
-+
-+ switch (reason) {
-+ case VCHIQ_MESSAGE_AVAILABLE:
-+ vchiu_queue_push(&service->queue, header);
-+
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_MSG_AVAILABLE, NULL);
-+
-+ goto done;
-+ break;
-+
-+ case VCHIQ_BULK_TRANSMIT_DONE:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_SENT, bulk_user);
-+ break;
-+
-+ case VCHIQ_BULK_RECEIVE_DONE:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_RECEIVED, bulk_user);
-+ break;
-+
-+ case VCHIQ_SERVICE_CLOSED:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_SERVICE_CLOSED, NULL);
-+ break;
-+
-+ case VCHIQ_SERVICE_OPENED:
-+ /* No equivalent VCHI reason */
-+ break;
-+
-+ case VCHIQ_BULK_TRANSMIT_ABORTED:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED,
-+ bulk_user);
-+ break;
-+
-+ case VCHIQ_BULK_RECEIVE_ABORTED:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_RECEIVE_ABORTED,
-+ bulk_user);
-+ break;
-+
-+ default:
-+ WARN(1, "not supported\n");
-+ break;
-+ }
-+
-+release:
-+ vchiq_release_message(service->handle, header);
-+done:
-+ return VCHIQ_SUCCESS;
-+}
-+
-+static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance,
-+ SERVICE_CREATION_T *setup)
-+{
-+ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL);
-+
-+ (void)instance;
-+
-+ if (service) {
-+ if (vchiu_queue_init(&service->queue, 64)) {
-+ service->callback = setup->callback;
-+ service->callback_param = setup->callback_param;
-+ } else {
-+ kfree(service);
-+ service = NULL;
-+ }
-+ }
-+
-+ return service;
-+}
-+
-+static void service_free(SHIM_SERVICE_T *service)
-+{
-+ if (service) {
-+ vchiu_queue_delete(&service->queue);
-+ kfree(service);
-+ }
-+}
-+
-+int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+ SHIM_SERVICE_T *service = service_alloc(instance, setup);
-+
-+ *handle = (VCHI_SERVICE_HANDLE_T)service;
-+
-+ if (service) {
-+ VCHIQ_SERVICE_PARAMS_T params;
-+ VCHIQ_STATUS_T status;
-+
-+ memset(&params, 0, sizeof(params));
-+ params.fourcc = setup->service_id;
-+ params.callback = shim_callback;
-+ params.userdata = service;
-+ params.version = setup->version.version;
-+ params.version_min = setup->version.version_min;
-+
-+ status = vchiq_open_service(instance, &params,
-+ &service->handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ *handle = NULL;
-+ }
-+ }
-+
-+ return (service != NULL) ? 0 : -1;
-+}
-+EXPORT_SYMBOL(vchi_service_open);
-+
-+int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+ SHIM_SERVICE_T *service = service_alloc(instance, setup);
-+
-+ *handle = (VCHI_SERVICE_HANDLE_T)service;
-+
-+ if (service) {
-+ VCHIQ_SERVICE_PARAMS_T params;
-+ VCHIQ_STATUS_T status;
-+
-+ memset(&params, 0, sizeof(params));
-+ params.fourcc = setup->service_id;
-+ params.callback = shim_callback;
-+ params.userdata = service;
-+ params.version = setup->version.version;
-+ params.version_min = setup->version.version_min;
-+ status = vchiq_add_service(instance, &params, &service->handle);
-+
-+ if (status != VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ *handle = NULL;
-+ }
-+ }
-+
-+ return (service != NULL) ? 0 : -1;
-+}
-+EXPORT_SYMBOL(vchi_service_create);
-+
-+int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service) {
-+ VCHIQ_STATUS_T status = vchiq_close_service(service->handle);
-+ if (status == VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ }
-+
-+ ret = vchiq_status_to_vchi(status);
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_close);
-+
-+int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service) {
-+ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle);
-+ if (status == VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ }
-+
-+ ret = vchiq_status_to_vchi(status);
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_destroy);
-+
-+int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_SERVICE_OPTION_T option,
-+ int value)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_SERVICE_OPTION_T vchiq_option;
-+ switch (option) {
-+ case VCHI_SERVICE_OPTION_TRACE:
-+ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE;
-+ break;
-+ default:
-+ service = NULL;
-+ break;
-+ }
-+ if (service) {
-+ VCHIQ_STATUS_T status =
-+ vchiq_set_service_option(service->handle,
-+ vchiq_option,
-+ value);
-+
-+ ret = vchiq_status_to_vchi(status);
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_set_option);
-+
-+int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version )
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if(service)
-+ {
-+ VCHIQ_STATUS_T status = vchiq_get_peer_version(service->handle, peer_version);
-+ ret = vchiq_status_to_vchi( status );
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_get_peer_version);
-+
-+/* ----------------------------------------------------------------------
-+ * read a uint32_t from buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+uint32_t
-+vchi_readbuf_uint32(const void *_ptr)
-+{
-+ const unsigned char *ptr = _ptr;
-+ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * write a uint32_t to buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+void
-+vchi_writebuf_uint32(void *_ptr, uint32_t value)
-+{
-+ unsigned char *ptr = _ptr;
-+ ptr[0] = (unsigned char)((value >> 0) & 0xFF);
-+ ptr[1] = (unsigned char)((value >> 8) & 0xFF);
-+ ptr[2] = (unsigned char)((value >> 16) & 0xFF);
-+ ptr[3] = (unsigned char)((value >> 24) & 0xFF);
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * read a uint16_t from buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+uint16_t
-+vchi_readbuf_uint16(const void *_ptr)
-+{
-+ const unsigned char *ptr = _ptr;
-+ return ptr[0] | (ptr[1] << 8);
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * write a uint16_t into the buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+void
-+vchi_writebuf_uint16(void *_ptr, uint16_t value)
-+{
-+ unsigned char *ptr = _ptr;
-+ ptr[0] = (value >> 0) & 0xFF;
-+ ptr[1] = (value >> 8) & 0xFF;
-+}
-+
-+/***********************************************************
-+ * Name: vchi_service_use
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle
-+ *
-+ * Description: Routine to increment refcount on a service
-+ *
-+ * Returns: void
-+ *
-+ ***********************************************************/
-+int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service)
-+ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle));
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_use);
-+
-+/***********************************************************
-+ * Name: vchi_service_release
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle
-+ *
-+ * Description: Routine to decrement refcount on a service
-+ *
-+ * Returns: void
-+ *
-+ ***********************************************************/
-+int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service)
-+ ret = vchiq_status_to_vchi(
-+ vchiq_release_service(service->handle));
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_release);
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,152 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "vchiq_util.h"
-+#include "vchiq_killable.h"
-+
-+static inline int is_pow2(int i)
-+{
-+ return i && !(i & (i - 1));
-+}
-+
-+int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size)
-+{
-+ WARN_ON(!is_pow2(size));
-+
-+ queue->size = size;
-+ queue->read = 0;
-+ queue->write = 0;
-+
-+ sema_init(&queue->pop, 0);
-+ sema_init(&queue->push, 0);
-+
-+ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL);
-+ if (queue->storage == NULL) {
-+ vchiu_queue_delete(queue);
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+void vchiu_queue_delete(VCHIU_QUEUE_T *queue)
-+{
-+ if (queue->storage != NULL)
-+ kfree(queue->storage);
-+}
-+
-+int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue)
-+{
-+ return queue->read == queue->write;
-+}
-+
-+int vchiu_queue_is_full(VCHIU_QUEUE_T *queue)
-+{
-+ return queue->write == queue->read + queue->size;
-+}
-+
-+void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header)
-+{
-+ while (queue->write == queue->read + queue->size) {
-+ if (down_interruptible(&queue->pop) != 0) {
-+ flush_signals(current);
-+ }
-+ }
-+
-+ /*
-+ * Write to queue->storage must be visible after read from
-+ * queue->read
-+ */
-+ smp_mb();
-+
-+ queue->storage[queue->write & (queue->size - 1)] = header;
-+
-+ /*
-+ * Write to queue->storage must be visible before write to
-+ * queue->write
-+ */
-+ smp_wmb();
-+
-+ queue->write++;
-+
-+ up(&queue->push);
-+}
-+
-+VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue)
-+{
-+ while (queue->write == queue->read) {
-+ if (down_interruptible(&queue->push) != 0) {
-+ flush_signals(current);
-+ }
-+ }
-+
-+ up(&queue->push); // We haven't removed anything from the queue.
-+
-+ /*
-+ * Read from queue->storage must be visible after read from
-+ * queue->write
-+ */
-+ smp_rmb();
-+
-+ return queue->storage[queue->read & (queue->size - 1)];
-+}
-+
-+VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue)
-+{
-+ VCHIQ_HEADER_T *header;
-+
-+ while (queue->write == queue->read) {
-+ if (down_interruptible(&queue->push) != 0) {
-+ flush_signals(current);
-+ }
-+ }
-+
-+ /*
-+ * Read from queue->storage must be visible after read from
-+ * queue->write
-+ */
-+ smp_rmb();
-+
-+ header = queue->storage[queue->read & (queue->size - 1)];
-+
-+ /*
-+ * Read from queue->storage must be visible before write to
-+ * queue->read
-+ */
-+ smp_mb();
-+
-+ queue->read++;
-+
-+ up(&queue->pop);
-+
-+ return header;
-+}
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,81 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_UTIL_H
-+#define VCHIQ_UTIL_H
-+
-+#include <linux/types.h>
-+#include <linux/semaphore.h>
-+#include <linux/mutex.h>
-+#include <linux/bitops.h>
-+#include <linux/kthread.h>
-+#include <linux/wait.h>
-+#include <linux/vmalloc.h>
-+#include <linux/jiffies.h>
-+#include <linux/delay.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/random.h>
-+#include <linux/sched.h>
-+#include <linux/ctype.h>
-+#include <linux/uaccess.h>
-+#include <linux/time.h> /* for time_t */
-+#include <linux/slab.h>
-+#include <linux/vmalloc.h>
-+
-+#include "vchiq_if.h"
-+
-+typedef struct {
-+ int size;
-+ int read;
-+ int write;
-+
-+ struct semaphore pop;
-+ struct semaphore push;
-+
-+ VCHIQ_HEADER_T **storage;
-+} VCHIU_QUEUE_T;
-+
-+extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size);
-+extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue);
-+
-+extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue);
-+extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue);
-+
-+extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header);
-+
-+extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue);
-+extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue);
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c
---- linux-3.12.38/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2015-03-09 10:39:30.722893733 +0100
-@@ -0,0 +1,59 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include "vchiq_build_info.h"
-+#include <linux/broadcom/vc_debug_sym.h>
-+
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" );
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" );
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ );
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ );
-+
-+const char *vchiq_get_build_hostname( void )
-+{
-+ return vchiq_build_hostname;
-+}
-+
-+const char *vchiq_get_build_version( void )
-+{
-+ return vchiq_build_version;
-+}
-+
-+const char *vchiq_get_build_date( void )
-+{
-+ return vchiq_build_date;
-+}
-+
-+const char *vchiq_get_build_time( void )
-+{
-+ return vchiq_build_time;
-+}
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/Kconfig linux-rpi/drivers/misc/vc04_services/Kconfig
---- linux-3.12.38/drivers/misc/vc04_services/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/Kconfig 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,9 @@
-+config BCM2708_VCHIQ
-+ tristate "Videocore VCHIQ"
-+ depends on MACH_BCM2708
-+ default y
-+ help
-+ Kernel to VideoCore communication interface for the
-+ BCM2708 family of products.
-+ Defaults to Y when the Broadcom Videocore services
-+ are included in the build, N otherwise.
-diff -Nur linux-3.12.38/drivers/misc/vc04_services/Makefile linux-rpi/drivers/misc/vc04_services/Makefile
---- linux-3.12.38/drivers/misc/vc04_services/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/misc/vc04_services/Makefile 2015-03-10 17:26:50.554216692 +0100
-@@ -0,0 +1,17 @@
-+ifeq ($(CONFIG_MACH_BCM2708),y)
-+
-+obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o
-+
-+vchiq-objs := \
-+ interface/vchiq_arm/vchiq_core.o \
-+ interface/vchiq_arm/vchiq_arm.o \
-+ interface/vchiq_arm/vchiq_kern_lib.o \
-+ interface/vchiq_arm/vchiq_2835_arm.o \
-+ interface/vchiq_arm/vchiq_debugfs.o \
-+ interface/vchiq_arm/vchiq_shim.o \
-+ interface/vchiq_arm/vchiq_util.o \
-+ interface/vchiq_arm/vchiq_connected.o \
-+
-+ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000
-+
-+endif
-diff -Nur linux-3.12.38/drivers/mmc/card/block.c linux-rpi/drivers/mmc/card/block.c
---- linux-3.12.38/drivers/mmc/card/block.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/card/block.c 2015-03-10 17:26:50.554216692 +0100
-@@ -1361,7 +1361,7 @@
- brq->data.blocks = 1;
- }
-
-- if (brq->data.blocks > 1 || do_rel_wr) {
-+ if (brq->data.blocks > 1 || do_rel_wr || card->host->caps2 & MMC_CAP2_FORCE_MULTIBLOCK) {
- /* SPI multiblock writes terminate using a special
- * token, not a STOP_TRANSMISSION request.
- */
-diff -Nur linux-3.12.38/drivers/mmc/core/sd.c linux-rpi/drivers/mmc/core/sd.c
---- linux-3.12.38/drivers/mmc/core/sd.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/core/sd.c 2015-03-10 17:26:50.554216692 +0100
-@@ -14,6 +14,8 @@
- #include <linux/sizes.h>
- #include <linux/slab.h>
- #include <linux/stat.h>
-+#include <linux/jiffies.h>
-+#include <linux/nmi.h>
-
- #include <linux/mmc/host.h>
- #include <linux/mmc/card.h>
-@@ -66,6 +68,15 @@
- __res & __mask; \
- })
-
-+// timeout for tries
-+static const unsigned long retry_timeout_ms= 10*1000;
-+
-+// try at least 10 times, even if timeout is reached
-+static const int retry_min_tries= 10;
-+
-+// delay between tries
-+static const unsigned long retry_delay_ms= 10;
-+
- /*
- * Given the decoded CSD structure, decode the raw CID to our CID structure.
- */
-@@ -218,12 +229,63 @@
- }
-
- /*
-- * Fetch and process SD Status register.
-+ * Fetch and process SD Configuration Register.
-+ */
-+static int mmc_read_scr(struct mmc_card *card)
-+{
-+ unsigned long timeout_at;
-+ int err, tries;
-+
-+ timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms );
-+ tries= 0;
-+
-+ while( tries < retry_min_tries || time_before( jiffies, timeout_at ) )
-+ {
-+ unsigned long delay_at;
-+ tries++;
-+
-+ err = mmc_app_send_scr(card, card->raw_scr);
-+ if( !err )
-+ break; // success!!!
-+
-+ touch_nmi_watchdog(); // we are still alive!
-+
-+ // delay
-+ delay_at= jiffies + msecs_to_jiffies( retry_delay_ms );
-+ while( time_before( jiffies, delay_at ) )
-+ {
-+ mdelay( 1 );
-+ touch_nmi_watchdog(); // we are still alive!
-+ }
-+ }
-+
-+ if( err)
-+ {
-+ pr_err("%s: failed to read SD Configuration register (SCR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err );
-+ return err;
-+ }
-+
-+ if( tries > 1 )
-+ {
-+ pr_info("%s: could read SD Configuration register (SCR) at the %dth attempt\n", mmc_hostname(card->host), tries );
-+ }
-+
-+ err = mmc_decode_scr(card);
-+ if (err)
-+ return err;
-+
-+ return err;
-+}
-+
-+/*
-+ * Fetch and process SD Status Register.
- */
- static int mmc_read_ssr(struct mmc_card *card)
- {
-+ unsigned long timeout_at;
- unsigned int au, es, et, eo;
- int err, i;
-+ int tries;
- u32 *ssr;
-
- if (!(card->csd.cmdclass & CCC_APP_SPEC)) {
-@@ -236,14 +298,40 @@
- if (!ssr)
- return -ENOMEM;
-
-- err = mmc_app_sd_status(card, ssr);
-- if (err) {
-- pr_warning("%s: problem reading SD Status "
-- "register.\n", mmc_hostname(card->host));
-- err = 0;
-+ timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms );
-+ tries= 0;
-+
-+ while( tries < retry_min_tries || time_before( jiffies, timeout_at ) )
-+ {
-+ unsigned long delay_at;
-+ tries++;
-+
-+ err= mmc_app_sd_status(card, ssr);
-+ if( !err )
-+ break; // sucess!!!
-+
-+ touch_nmi_watchdog(); // we are still alive!
-+
-+ // delay
-+ delay_at= jiffies + msecs_to_jiffies( retry_delay_ms );
-+ while( time_before( jiffies, delay_at ) )
-+ {
-+ mdelay( 1 );
-+ touch_nmi_watchdog(); // we are still alive!
-+ }
-+ }
-+
-+ if( err)
-+ {
-+ pr_err("%s: failed to read SD Status register (SSR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err );
- goto out;
- }
-
-+ if( tries > 1 )
-+ {
-+ pr_info("%s: read SD Status register (SSR) after %d attempts\n", mmc_hostname(card->host), tries );
-+ }
-+
- for (i = 0; i < 16; i++)
- ssr[i] = be32_to_cpu(ssr[i]);
-
-@@ -823,14 +911,10 @@
-
- if (!reinit) {
- /*
-- * Fetch SCR from card.
-+ * Fetch and decode SD Configuration register.
- */
-- err = mmc_app_send_scr(card, card->raw_scr);
-- if (err)
-- return err;
--
-- err = mmc_decode_scr(card);
-- if (err)
-+ err = mmc_read_scr(card);
-+ if( err )
- return err;
-
- /*
-diff -Nur linux-3.12.38/drivers/mmc/host/bcm2835-mmc.c linux-rpi/drivers/mmc/host/bcm2835-mmc.c
---- linux-3.12.38/drivers/mmc/host/bcm2835-mmc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/bcm2835-mmc.c 2015-03-10 17:26:50.558216692 +0100
-@@ -0,0 +1,1547 @@
-+/*
-+ * BCM2835 MMC host driver.
-+ *
-+ * Author: Gellert Weisz <gellert@raspberrypi.org>
-+ * Copyright 2014
-+ *
-+ * Based on
-+ * sdhci-bcm2708.c by Broadcom
-+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
-+ * sdhci.c and sdhci-pci.c by Pierre Ossman
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/scatterlist.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/blkdev.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of_dma.h>
-+
-+#include "sdhci.h"
-+
-+
-+#ifndef CONFIG_OF
-+ #define BCM2835_CLOCK_FREQ 250000000
-+#endif
-+
-+#define DRIVER_NAME "mmc-bcm2835"
-+
-+#define DBG(f, x...) \
-+pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
-+
-+#ifndef CONFIG_MMC_BCM2835_DMA
-+ #define FORCE_PIO
-+#endif
-+
-+
-+/* the inclusive limit in bytes under which PIO will be used instead of DMA */
-+#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
-+#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
-+#else
-+#define PIO_DMA_BARRIER 00
-+#endif
-+
-+#define MIN_FREQ 400000
-+#define TIMEOUT_VAL 0xE
-+#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
-+
-+#ifndef BCM2708_PERI_BASE
-+ #define BCM2708_PERI_BASE 0x20000000
-+#endif
-+
-+/* FIXME: Needs IOMMU support */
-+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE)
-+
-+
-+struct bcm2835_host {
-+ spinlock_t lock;
-+
-+ void __iomem *ioaddr;
-+ u32 phys_addr;
-+
-+ struct mmc_host *mmc;
-+
-+ u32 timeout;
-+
-+ int clock; /* Current clock speed */
-+ u8 pwr; /* Current voltage */
-+
-+ unsigned int max_clk; /* Max possible freq */
-+ unsigned int timeout_clk; /* Timeout freq (KHz) */
-+ unsigned int clk_mul; /* Clock Muliplier value */
-+
-+ struct tasklet_struct finish_tasklet; /* Tasklet structures */
-+
-+ struct timer_list timer; /* Timer for timeouts */
-+
-+ struct sg_mapping_iter sg_miter; /* SG state for PIO */
-+ unsigned int blocks; /* remaining PIO blocks */
-+
-+ int irq; /* Device IRQ */
-+
-+
-+ u32 ier; /* cached registers */
-+
-+ struct mmc_request *mrq; /* Current request */
-+ struct mmc_command *cmd; /* Current command */
-+ struct mmc_data *data; /* Current data request */
-+ unsigned int data_early:1; /* Data finished before cmd */
-+
-+ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
-+
-+ u32 thread_isr;
-+
-+ u32 shadow;
-+
-+ /*DMA part*/
-+ struct dma_chan *dma_chan_rx; /* DMA channel for reads */
-+ struct dma_chan *dma_chan_tx; /* DMA channel for writes */
-+ struct dma_async_tx_descriptor *tx_desc; /* descriptor */
-+
-+ bool have_dma;
-+ bool use_dma;
-+ /*end of DMA part*/
-+
-+ int max_delay; /* maximum length of time spent waiting */
-+
-+ int flags; /* Host attributes */
-+#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
-+#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
-+#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
-+#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
-+#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
-+#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
-+#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
-+#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
-+#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
-+};
-+
-+
-+static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg)
-+{
-+ writel(val, host->ioaddr + reg);
-+ udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
-+}
-+
-+static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
-+{
-+ writel(val, host->ioaddr + reg);
-+}
-+
-+static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
-+{
-+ return readl(host->ioaddr + reg);
-+}
-+
-+static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
-+{
-+ u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
-+ bcm2835_mmc_readl(host, reg & ~3);
-+ u32 word_num = (reg >> 1) & 1;
-+ u32 word_shift = word_num * 16;
-+ u32 mask = 0xffff << word_shift;
-+ u32 newval = (oldval & ~mask) | (val << word_shift);
-+
-+ if (reg == SDHCI_TRANSFER_MODE)
-+ host->shadow = newval;
-+ else
-+ bcm2835_mmc_writel(host, newval, reg & ~3);
-+
-+}
-+
-+static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
-+{
-+ u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
-+ u32 byte_num = reg & 3;
-+ u32 byte_shift = byte_num * 8;
-+ u32 mask = 0xff << byte_shift;
-+ u32 newval = (oldval & ~mask) | (val << byte_shift);
-+
-+ bcm2835_mmc_writel(host, newval, reg & ~3);
-+}
-+
-+
-+static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
-+{
-+ u32 val = bcm2835_mmc_readl(host, (reg & ~3));
-+ u32 word_num = (reg >> 1) & 1;
-+ u32 word_shift = word_num * 16;
-+ u32 word = (val >> word_shift) & 0xffff;
-+
-+ return word;
-+}
-+
-+static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
-+{
-+ u32 val = bcm2835_mmc_readl(host, (reg & ~3));
-+ u32 byte_num = reg & 3;
-+ u32 byte_shift = byte_num * 8;
-+ u32 byte = (val >> byte_shift) & 0xff;
-+
-+ return byte;
-+}
-+
-+static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
-+{
-+ u32 ier;
-+
-+ ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
-+ ier &= ~clear;
-+ /* change which requests generate IRQs - makes no difference to
-+ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
-+ bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE);
-+}
-+
-+
-+static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
-+{
-+ pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
-+ mmc_hostname(host->mmc));
-+
-+ pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
-+ bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
-+ pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
-+ bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
-+ pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
-+ bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
-+ pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
-+ bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
-+ pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
-+ bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
-+ bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
-+ pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
-+ bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
-+ bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
-+ pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
-+ bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
-+ bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
-+ pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
-+ bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
-+ pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
-+ bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
-+ pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
-+ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
-+ pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_COMMAND),
-+ bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
-+ pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
-+
-+ pr_debug(DRIVER_NAME ": ===========================================\n");
-+}
-+
-+
-+static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
-+{
-+ unsigned long timeout;
-+
-+ bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
-+
-+ if (mask & SDHCI_RESET_ALL)
-+ host->clock = 0;
-+
-+ /* Wait max 100 ms */
-+ timeout = 100;
-+
-+ /* hw clears the bit when it's done */
-+ while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
-+ if (timeout == 0) {
-+ pr_err("%s: Reset 0x%x never completed.\n",
-+ mmc_hostname(host->mmc), (int)mask);
-+ bcm2835_mmc_dumpregs(host);
-+ return;
-+ }
-+ timeout--;
-+ mdelay(1);
-+ }
-+
-+ if (100-timeout > 10 && 100-timeout > host->max_delay) {
-+ host->max_delay = 100-timeout;
-+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+ }
-+}
-+
-+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
-+
-+static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
-+{
-+ if (soft)
-+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
-+ else
-+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
-+ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
-+ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
-+ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
-+ SDHCI_INT_RESPONSE;
-+
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-+
-+ if (soft) {
-+ /* force clock reconfiguration */
-+ host->clock = 0;
-+ bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
-+ }
-+}
-+
-+
-+
-+static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
-+
-+static void bcm2835_mmc_dma_complete(void *param)
-+{
-+ struct bcm2835_host *host = param;
-+ struct dma_chan *dma_chan;
-+ unsigned long flags;
-+ u32 dir_data;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
-+ /* otherwise handled in SDHCI IRQ */
-+ dma_chan = host->dma_chan_rx;
-+ dir_data = DMA_FROM_DEVICE;
-+
-+ dma_unmap_sg(dma_chan->device->dev,
-+ host->data->sg, host->data->sg_len,
-+ dir_data);
-+
-+ bcm2835_mmc_finish_data(host);
-+ }
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
-+{
-+ unsigned long flags;
-+ size_t blksize, len, chunk;
-+
-+ u32 uninitialized_var(scratch);
-+ u8 *buf;
-+
-+ blksize = host->data->blksz;
-+ chunk = 0;
-+
-+ local_irq_save(flags);
-+
-+ while (blksize) {
-+ if (!sg_miter_next(&host->sg_miter))
-+ BUG();
-+
-+ len = min(host->sg_miter.length, blksize);
-+
-+ blksize -= len;
-+ host->sg_miter.consumed = len;
-+
-+ buf = host->sg_miter.addr;
-+
-+ while (len) {
-+ if (chunk == 0) {
-+ scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
-+ chunk = 4;
-+ }
-+
-+ *buf = scratch & 0xFF;
-+
-+ buf++;
-+ scratch >>= 8;
-+ chunk--;
-+ len--;
-+ }
-+ }
-+
-+ sg_miter_stop(&host->sg_miter);
-+
-+ local_irq_restore(flags);
-+}
-+
-+static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
-+{
-+ unsigned long flags;
-+ size_t blksize, len, chunk;
-+ u32 scratch;
-+ u8 *buf;
-+
-+ blksize = host->data->blksz;
-+ chunk = 0;
-+ chunk = 0;
-+ scratch = 0;
-+
-+ local_irq_save(flags);
-+
-+ while (blksize) {
-+ if (!sg_miter_next(&host->sg_miter))
-+ BUG();
-+
-+ len = min(host->sg_miter.length, blksize);
-+
-+ blksize -= len;
-+ host->sg_miter.consumed = len;
-+
-+ buf = host->sg_miter.addr;
-+
-+ while (len) {
-+ scratch |= (u32)*buf << (chunk * 8);
-+
-+ buf++;
-+ chunk++;
-+ len--;
-+
-+ if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
-+ mmc_raw_writel(host, scratch, SDHCI_BUFFER);
-+ chunk = 0;
-+ scratch = 0;
-+ }
-+ }
-+ }
-+
-+ sg_miter_stop(&host->sg_miter);
-+
-+ local_irq_restore(flags);
-+}
-+
-+
-+static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
-+{
-+ u32 mask;
-+
-+ BUG_ON(!host->data);
-+
-+ if (host->blocks == 0)
-+ return;
-+
-+ if (host->data->flags & MMC_DATA_READ)
-+ mask = SDHCI_DATA_AVAILABLE;
-+ else
-+ mask = SDHCI_SPACE_AVAILABLE;
-+
-+ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+
-+ if (host->data->flags & MMC_DATA_READ)
-+ bcm2835_bcm2835_mmc_read_block_pio(host);
-+ else
-+ bcm2835_bcm2835_mmc_write_block_pio(host);
-+
-+ host->blocks--;
-+
-+ /* QUIRK used in sdhci.c removes the 'if' */
-+ /* but it seems this is unnecessary */
-+ if (host->blocks == 0)
-+ break;
-+
-+
-+ }
-+}
-+
-+
-+static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
-+{
-+ u32 len, dir_data, dir_slave;
-+ struct dma_async_tx_descriptor *desc = NULL;
-+ struct dma_chan *dma_chan;
-+
-+
-+ WARN_ON(!host->data);
-+
-+ if (!host->data)
-+ return;
-+
-+ if (host->blocks == 0)
-+ return;
-+
-+ if (host->data->flags & MMC_DATA_READ) {
-+ dma_chan = host->dma_chan_rx;
-+ dir_data = DMA_FROM_DEVICE;
-+ dir_slave = DMA_DEV_TO_MEM;
-+ } else {
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ dir_slave = DMA_MEM_TO_DEV;
-+ }
-+
-+ BUG_ON(!dma_chan->device);
-+ BUG_ON(!dma_chan->device->dev);
-+ BUG_ON(!host->data->sg);
-+
-+ len = dma_map_sg(dma_chan->device->dev, host->data->sg,
-+ host->data->sg_len, dir_data);
-+ if (len > 0) {
-+ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
-+ len, dir_slave,
-+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+ } else {
-+ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
-+ }
-+ if (desc) {
-+ bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+ SDHCI_INT_SPACE_AVAIL);
-+ host->tx_desc = desc;
-+ desc->callback = bcm2835_mmc_dma_complete;
-+ desc->callback_param = host;
-+ dmaengine_submit(desc);
-+ dma_async_issue_pending(dma_chan);
-+ }
-+
-+}
-+
-+
-+
-+static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
-+{
-+ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
-+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
-+
-+ if (host->use_dma)
-+ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
-+ else
-+ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
-+
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-+}
-+
-+
-+static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+ u8 count;
-+ struct mmc_data *data = cmd->data;
-+
-+ WARN_ON(host->data);
-+
-+ if (data || (cmd->flags & MMC_RSP_BUSY)) {
-+ count = TIMEOUT_VAL;
-+ bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
-+ }
-+
-+ if (!data)
-+ return;
-+
-+ /* Sanity checks */
-+ BUG_ON(data->blksz * data->blocks > 524288);
-+ BUG_ON(data->blksz > host->mmc->max_blk_size);
-+ BUG_ON(data->blocks > 65535);
-+
-+ host->data = data;
-+ host->data_early = 0;
-+ host->data->bytes_xfered = 0;
-+
-+
-+ if (!(host->flags & SDHCI_REQ_USE_DMA)) {
-+ int flags;
-+
-+ flags = SG_MITER_ATOMIC;
-+ if (host->data->flags & MMC_DATA_READ)
-+ flags |= SG_MITER_TO_SG;
-+ else
-+ flags |= SG_MITER_FROM_SG;
-+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
-+ host->blocks = data->blocks;
-+ }
-+
-+ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
-+
-+ bcm2835_mmc_set_transfer_irqs(host);
-+
-+ /* Set the DMA boundary value and block size */
-+ bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
-+ data->blksz), SDHCI_BLOCK_SIZE);
-+ bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
-+
-+ BUG_ON(!host->data);
-+}
-+
-+static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
-+ struct mmc_command *cmd)
-+{
-+ u16 mode;
-+ struct mmc_data *data = cmd->data;
-+
-+ if (data == NULL) {
-+ /* clear Auto CMD settings for no data CMDs */
-+ mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
-+ bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
-+ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
-+ return;
-+ }
-+
-+ WARN_ON(!host->data);
-+
-+ mode = SDHCI_TRNS_BLK_CNT_EN;
-+
-+ if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
-+ mode |= SDHCI_TRNS_MULTI;
-+
-+ /*
-+ * If we are sending CMD23, CMD12 never gets sent
-+ * on successful completion (so no Auto-CMD12).
-+ */
-+ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
-+ mode |= SDHCI_TRNS_AUTO_CMD12;
-+ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
-+ mode |= SDHCI_TRNS_AUTO_CMD23;
-+ bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
-+ }
-+ }
-+
-+ if (data->flags & MMC_DATA_READ)
-+ mode |= SDHCI_TRNS_READ;
-+ if (host->flags & SDHCI_REQ_USE_DMA)
-+ mode |= SDHCI_TRNS_DMA;
-+
-+ bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
-+}
-+
-+void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+ int flags;
-+ u32 mask;
-+ unsigned long timeout;
-+
-+ WARN_ON(host->cmd);
-+
-+ /* Wait max 10 ms */
-+ timeout = 1000;
-+
-+ mask = SDHCI_CMD_INHIBIT;
-+ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
-+ mask |= SDHCI_DATA_INHIBIT;
-+
-+ /* We shouldn't wait for data inihibit for stop commands, even
-+ though they might use busy signaling */
-+ if (host->mrq->data && (cmd == host->mrq->data->stop))
-+ mask &= ~SDHCI_DATA_INHIBIT;
-+
-+ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+ if (timeout == 0) {
-+ pr_err("%s: Controller never released inhibit bit(s).\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_mmc_dumpregs(host);
-+ cmd->error = -EIO;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+ timeout--;
-+ udelay(10);
-+ }
-+
-+ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
-+ host->max_delay = (1000-timeout)/100;
-+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+ }
-+
-+ timeout = jiffies;
-+#ifdef CONFIG_OF
-+ if (!cmd->data && cmd->busy_timeout > 9000)
-+ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
-+ else
-+#endif
-+ timeout += 10 * HZ;
-+ mod_timer(&host->timer, timeout);
-+
-+ host->cmd = cmd;
-+
-+ bcm2835_mmc_prepare_data(host, cmd);
-+
-+ bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT);
-+
-+ bcm2835_mmc_set_transfer_mode(host, cmd);
-+
-+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
-+ pr_err("%s: Unsupported response type!\n",
-+ mmc_hostname(host->mmc));
-+ cmd->error = -EINVAL;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ if (!(cmd->flags & MMC_RSP_PRESENT))
-+ flags = SDHCI_CMD_RESP_NONE;
-+ else if (cmd->flags & MMC_RSP_136)
-+ flags = SDHCI_CMD_RESP_LONG;
-+ else if (cmd->flags & MMC_RSP_BUSY)
-+ flags = SDHCI_CMD_RESP_SHORT_BUSY;
-+ else
-+ flags = SDHCI_CMD_RESP_SHORT;
-+
-+ if (cmd->flags & MMC_RSP_CRC)
-+ flags |= SDHCI_CMD_CRC;
-+ if (cmd->flags & MMC_RSP_OPCODE)
-+ flags |= SDHCI_CMD_INDEX;
-+
-+ if (cmd->data)
-+ flags |= SDHCI_CMD_DATA;
-+
-+ bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
-+}
-+
-+
-+static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
-+{
-+ struct mmc_data *data;
-+
-+ BUG_ON(!host->data);
-+
-+ data = host->data;
-+ host->data = NULL;
-+
-+ if (data->error)
-+ data->bytes_xfered = 0;
-+ else
-+ data->bytes_xfered = data->blksz * data->blocks;
-+
-+ /*
-+ * Need to send CMD12 if -
-+ * a) open-ended multiblock transfer (no CMD23)
-+ * b) error in multiblock transfer
-+ */
-+ if (data->stop &&
-+ (data->error ||
-+ !host->mrq->sbc)) {
-+
-+ /*
-+ * The controller needs a reset of internal state machines
-+ * upon error conditions.
-+ */
-+ if (data->error) {
-+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
-+ bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
-+ }
-+
-+ bcm2835_mmc_send_command(host, data->stop);
-+ } else
-+ tasklet_schedule(&host->finish_tasklet);
-+}
-+
-+static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
-+{
-+ int i;
-+
-+ BUG_ON(host->cmd == NULL);
-+
-+ if (host->cmd->flags & MMC_RSP_PRESENT) {
-+ if (host->cmd->flags & MMC_RSP_136) {
-+ /* CRC is stripped so we need to do some shifting. */
-+ for (i = 0; i < 4; i++) {
-+ host->cmd->resp[i] = bcm2835_mmc_readl(host,
-+ SDHCI_RESPONSE + (3-i)*4) << 8;
-+ if (i != 3)
-+ host->cmd->resp[i] |=
-+ bcm2835_mmc_readb(host,
-+ SDHCI_RESPONSE + (3-i)*4-1);
-+ }
-+ } else {
-+ host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
-+ }
-+ }
-+
-+ host->cmd->error = 0;
-+
-+ /* Finished CMD23, now send actual command. */
-+ if (host->cmd == host->mrq->sbc) {
-+ host->cmd = NULL;
-+ bcm2835_mmc_send_command(host, host->mrq->cmd);
-+ } else {
-+
-+ /* Processed actual command. */
-+ if (host->data && host->data_early)
-+ bcm2835_mmc_finish_data(host);
-+
-+ if (!host->cmd->data)
-+ tasklet_schedule(&host->finish_tasklet);
-+
-+ host->cmd = NULL;
-+ }
-+}
-+
-+
-+static void bcm2835_mmc_timeout_timer(unsigned long data)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+
-+ host = (struct bcm2835_host *)data;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host->mrq) {
-+ pr_err("%s: Timeout waiting for hardware interrupt.\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_mmc_dumpregs(host);
-+
-+ if (host->data) {
-+ host->data->error = -ETIMEDOUT;
-+ bcm2835_mmc_finish_data(host);
-+ } else {
-+ if (host->cmd)
-+ host->cmd->error = -ETIMEDOUT;
-+ else
-+ host->mrq->cmd->error = -ETIMEDOUT;
-+
-+ tasklet_schedule(&host->finish_tasklet);
-+ }
-+ }
-+
-+ mmiowb();
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
-+{
-+ if (!(host->flags & SDHCI_DEVICE_DEAD)) {
-+ if (enable)
-+ host->ier |= SDHCI_INT_CARD_INT;
-+ else
-+ host->ier &= ~SDHCI_INT_CARD_INT;
-+
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
-+ mmiowb();
-+ }
-+}
-+
-+static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+ struct bcm2835_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ if (enable)
-+ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
-+ else
-+ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
-+
-+ bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+
-+ BUG_ON(intmask == 0);
-+
-+ if (!host->cmd) {
-+ pr_err("%s: Got command interrupt 0x%08x even "
-+ "though no command operation was in progress.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_mmc_dumpregs(host);
-+ return;
-+ }
-+
-+ if (intmask & SDHCI_INT_TIMEOUT)
-+ host->cmd->error = -ETIMEDOUT;
-+ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
-+ SDHCI_INT_INDEX)) {
-+ host->cmd->error = -EILSEQ;
-+ }
-+
-+ if (host->cmd->error) {
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ if (intmask & SDHCI_INT_RESPONSE)
-+ bcm2835_mmc_finish_command(host);
-+
-+}
-+
-+static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+ struct dma_chan *dma_chan;
-+ u32 dir_data;
-+
-+ BUG_ON(intmask == 0);
-+
-+ if (!host->data) {
-+ /*
-+ * The "data complete" interrupt is also used to
-+ * indicate that a busy state has ended. See comment
-+ * above in sdhci_cmd_irq().
-+ */
-+ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
-+ if (intmask & SDHCI_INT_DATA_END) {
-+ bcm2835_mmc_finish_command(host);
-+ return;
-+ }
-+ }
-+
-+ pr_debug("%s: Got data interrupt 0x%08x even "
-+ "though no data operation was in progress.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_mmc_dumpregs(host);
-+
-+ return;
-+ }
-+
-+ if (intmask & SDHCI_INT_DATA_TIMEOUT)
-+ host->data->error = -ETIMEDOUT;
-+ else if (intmask & SDHCI_INT_DATA_END_BIT)
-+ host->data->error = -EILSEQ;
-+ else if ((intmask & SDHCI_INT_DATA_CRC) &&
-+ SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
-+ != MMC_BUS_TEST_R)
-+ host->data->error = -EILSEQ;
-+
-+ if (host->use_dma) {
-+ if (host->data->flags & MMC_DATA_WRITE) {
-+ /* IRQ handled here */
-+
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ dma_unmap_sg(dma_chan->device->dev,
-+ host->data->sg, host->data->sg_len,
-+ dir_data);
-+
-+ bcm2835_mmc_finish_data(host);
-+ }
-+
-+ } else {
-+ if (host->data->error)
-+ bcm2835_mmc_finish_data(host);
-+ else {
-+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
-+ bcm2835_mmc_transfer_pio(host);
-+
-+ if (intmask & SDHCI_INT_DATA_END) {
-+ if (host->cmd) {
-+ /*
-+ * Data managed to finish before the
-+ * command completed. Make sure we do
-+ * things in the proper order.
-+ */
-+ host->data_early = 1;
-+ } else {
-+ bcm2835_mmc_finish_data(host);
-+ }
-+ }
-+ }
-+ }
-+}
-+
-+
-+static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
-+{
-+ irqreturn_t result = IRQ_NONE;
-+ struct bcm2835_host *host = dev_id;
-+ u32 intmask, mask, unexpected = 0;
-+ int max_loops = 16;
-+#ifndef CONFIG_OF
-+ int cardint = 0;
-+#endif
-+
-+ spin_lock(&host->lock);
-+
-+ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+
-+ if (!intmask || intmask == 0xffffffff) {
-+ result = IRQ_NONE;
-+ goto out;
-+ }
-+
-+ do {
-+ /* Clear selected interrupts. */
-+ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
-+ SDHCI_INT_BUS_POWER);
-+ bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS);
-+
-+
-+ if (intmask & SDHCI_INT_CMD_MASK)
-+ bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
-+
-+ if (intmask & SDHCI_INT_DATA_MASK)
-+ bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
-+
-+ if (intmask & SDHCI_INT_BUS_POWER)
-+ pr_err("%s: Card is consuming too much power!\n",
-+ mmc_hostname(host->mmc));
-+
-+ if (intmask & SDHCI_INT_CARD_INT) {
-+#ifndef CONFIG_OF
-+ cardint = 1;
-+#else
-+ bcm2835_mmc_enable_sdio_irq_nolock(host, false);
-+ host->thread_isr |= SDHCI_INT_CARD_INT;
-+ result = IRQ_WAKE_THREAD;
-+#endif
-+ }
-+
-+ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
-+ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
-+ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
-+ SDHCI_INT_CARD_INT);
-+
-+ if (intmask) {
-+ unexpected |= intmask;
-+ bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS);
-+ }
-+
-+ if (result == IRQ_NONE)
-+ result = IRQ_HANDLED;
-+
-+ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+ } while (intmask && --max_loops);
-+out:
-+ spin_unlock(&host->lock);
-+
-+ if (unexpected) {
-+ pr_err("%s: Unexpected interrupt 0x%08x.\n",
-+ mmc_hostname(host->mmc), unexpected);
-+ bcm2835_mmc_dumpregs(host);
-+ }
-+
-+#ifndef CONFIG_OF
-+ if (cardint)
-+ mmc_signal_sdio_irq(host->mmc);
-+#endif
-+
-+ return result;
-+}
-+
-+#ifdef CONFIG_OF
-+static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
-+{
-+ struct bcm2835_host *host = dev_id;
-+ unsigned long flags;
-+ u32 isr;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ isr = host->thread_isr;
-+ host->thread_isr = 0;
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (isr & SDHCI_INT_CARD_INT) {
-+ sdio_run_irqs(host->mmc);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
-+ bcm2835_mmc_enable_sdio_irq_nolock(host, true);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ }
-+
-+ return isr ? IRQ_HANDLED : IRQ_NONE;
-+}
-+#endif
-+
-+
-+
-+void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
-+{
-+ int div = 0; /* Initialized for compiler warning */
-+ int real_div = div, clk_mul = 1;
-+ u16 clk = 0;
-+ unsigned long timeout;
-+
-+
-+ host->mmc->actual_clock = 0;
-+
-+ bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
-+
-+ if (clock == 0)
-+ return;
-+
-+ /* Version 3.00 divisors must be a multiple of 2. */
-+ if (host->max_clk <= clock)
-+ div = 1;
-+ else {
-+ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
-+ div += 2) {
-+ if ((host->max_clk / div) <= clock)
-+ break;
-+ }
-+ }
-+
-+ real_div = div;
-+ div >>= 1;
-+
-+ if (real_div)
-+ host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
-+
-+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
-+ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
-+ << SDHCI_DIVIDER_HI_SHIFT;
-+ clk |= SDHCI_CLOCK_INT_EN;
-+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+
-+ /* Wait max 20 ms */
-+ timeout = 20;
-+ while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
-+ & SDHCI_CLOCK_INT_STABLE)) {
-+ if (timeout == 0) {
-+ pr_err("%s: Internal clock never "
-+ "stabilised.\n", mmc_hostname(host->mmc));
-+ bcm2835_mmc_dumpregs(host);
-+ return;
-+ }
-+ timeout--;
-+ mdelay(1);
-+ }
-+
-+ if (20-timeout > 10 && 20-timeout > host->max_delay) {
-+ host->max_delay = 20-timeout;
-+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+ }
-+
-+ clk |= SDHCI_CLOCK_CARD_EN;
-+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+}
-+
-+static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+
-+ host = mmc_priv(mmc);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ WARN_ON(host->mrq != NULL);
-+
-+ host->mrq = mrq;
-+ bcm2835_mmc_send_command(host, mrq->cmd);
-+ mmiowb();
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (mrq->cmd->data && host->use_dma) {
-+ /* DMA transfer starts now, PIO starts after interrupt */
-+ bcm2835_mmc_transfer_dma(host);
-+ }
-+}
-+
-+
-+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+
-+ struct bcm2835_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+ u8 ctrl;
-+ u16 clk, ctrl_2;
-+
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (!ios->clock || ios->clock != host->clock) {
-+ bcm2835_mmc_set_clock(host, ios->clock);
-+ host->clock = ios->clock;
-+ }
-+
-+ if (host->pwr != SDHCI_POWER_330) {
-+ host->pwr = SDHCI_POWER_330;
-+ bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
-+ }
-+
-+ ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
-+
-+ /* set bus width */
-+ ctrl &= ~SDHCI_CTRL_8BITBUS;
-+ if (ios->bus_width == MMC_BUS_WIDTH_4)
-+ ctrl |= SDHCI_CTRL_4BITBUS;
-+ else
-+ ctrl &= ~SDHCI_CTRL_4BITBUS;
-+
-+ ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
-+
-+
-+ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-+ /*
-+ * We only need to set Driver Strength if the
-+ * preset value enable is not set.
-+ */
-+ ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
-+ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
-+ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
-+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
-+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
-+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
-+
-+ bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
-+
-+ /* Reset SD Clock Enable */
-+ clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
-+ clk &= ~SDHCI_CLOCK_CARD_EN;
-+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+
-+ /* Re-enable SD Clock */
-+ bcm2835_mmc_set_clock(host, host->clock);
-+ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-+
-+ mmiowb();
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static struct mmc_host_ops bcm2835_ops = {
-+ .request = bcm2835_mmc_request,
-+ .set_ios = bcm2835_mmc_set_ios,
-+ .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
-+};
-+
-+
-+static void bcm2835_mmc_tasklet_finish(unsigned long param)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+ struct mmc_request *mrq;
-+
-+ host = (struct bcm2835_host *)param;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ /*
-+ * If this tasklet gets rescheduled while running, it will
-+ * be run again afterwards but without any active request.
-+ */
-+ if (!host->mrq) {
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ return;
-+ }
-+
-+ del_timer(&host->timer);
-+
-+ mrq = host->mrq;
-+
-+ /*
-+ * The controller needs a reset of internal state machines
-+ * upon error conditions.
-+ */
-+ if (!(host->flags & SDHCI_DEVICE_DEAD) &&
-+ ((mrq->cmd && mrq->cmd->error) ||
-+ (mrq->data && (mrq->data->error ||
-+ (mrq->data->stop && mrq->data->stop->error))))) {
-+
-+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
-+ bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
-+ }
-+
-+ host->mrq = NULL;
-+ host->cmd = NULL;
-+ host->data = NULL;
-+
-+ mmiowb();
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ mmc_request_done(host->mmc, mrq);
-+}
-+
-+
-+
-+int bcm2835_mmc_add_host(struct bcm2835_host *host)
-+{
-+ struct mmc_host *mmc;
-+#ifndef FORCE_PIO
-+ struct dma_slave_config cfg;
-+#endif
-+ int ret;
-+
-+ mmc = host->mmc;
-+
-+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+ host->clk_mul = 0;
-+
-+ mmc->ops = &bcm2835_ops;
-+ mmc->f_max = host->max_clk;
-+ mmc->f_max = host->max_clk;
-+ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
-+
-+ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
-+ host->timeout_clk = mmc->f_max / 1000;
-+#ifdef CONFIG_OF
-+ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
-+#endif
-+ /* host controller capabilities */
-+ mmc->caps = MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ |
-+ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA;
-+
-+ host->flags = SDHCI_AUTO_CMD23;
-+
-+ spin_lock_init(&host->lock);
-+
-+
-+#ifdef FORCE_PIO
-+ pr_info("Forcing PIO mode\n");
-+ host->have_dma = false;
-+#else
-+ if (!host->dma_chan_tx || !host->dma_chan_rx ||
-+ IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
-+ pr_err("%s: Unable to initialise DMA channels. Falling back to PIO\n", DRIVER_NAME);
-+ host->have_dma = false;
-+ } else {
-+ pr_info("DMA channels allocated for the MMC driver");
-+ host->have_dma = true;
-+
-+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.slave_id = 11; /* DREQ channel */
-+
-+ cfg.direction = DMA_MEM_TO_DEV;
-+ cfg.src_addr = 0;
-+ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER;
-+ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
-+
-+ cfg.direction = DMA_DEV_TO_MEM;
-+ cfg.src_addr = host->phys_addr + SDHCI_BUFFER;
-+ cfg.dst_addr = 0;
-+ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
-+ }
-+#endif
-+
-+
-+ mmc->max_segs = 128;
-+ mmc->max_req_size = 524288;
-+ mmc->max_seg_size = mmc->max_req_size;
-+ mmc->max_blk_size = 512;
-+ mmc->max_blk_count = 65535;
-+
-+ /* report supported voltage ranges */
-+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+ tasklet_init(&host->finish_tasklet,
-+ bcm2835_mmc_tasklet_finish, (unsigned long)host);
-+
-+ setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
-+ init_waitqueue_head(&host->buf_ready_int);
-+
-+ bcm2835_mmc_init(host, 0);
-+#ifndef CONFIG_OF
-+ ret = request_irq(host->irq, bcm2835_mmc_irq, 0 /*IRQF_SHARED*/,
-+ mmc_hostname(mmc), host);
-+#else
-+ ret = request_threaded_irq(host->irq, bcm2835_mmc_irq, bcm2835_mmc_thread_irq,
-+ IRQF_SHARED, mmc_hostname(mmc), host);
-+#endif
-+ if (ret) {
-+ pr_err("%s: Failed to request IRQ %d: %d\n",
-+ mmc_hostname(mmc), host->irq, ret);
-+ goto untasklet;
-+ }
-+
-+ mmiowb();
-+ mmc_add_host(mmc);
-+
-+ pr_info("Load BCM2835 MMC driver\n");
-+
-+ return 0;
-+
-+untasklet:
-+ tasklet_kill(&host->finish_tasklet);
-+
-+ return ret;
-+}
-+
-+static int bcm2835_mmc_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+#ifdef CONFIG_OF
-+ struct device_node *node = dev->of_node;
-+ struct clk *clk;
-+#endif
-+ struct resource *iomem;
-+ struct bcm2835_host *host = NULL;
-+
-+ int ret;
-+ struct mmc_host *mmc;
-+#if !defined(CONFIG_OF) && !defined(FORCE_PIO)
-+ dma_cap_mask_t mask;
-+#endif
-+
-+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!iomem) {
-+ ret = -ENOMEM;
-+ goto err;
-+ }
-+
-+ if (resource_size(iomem) < 0x100)
-+ dev_err(&pdev->dev, "Invalid iomem size!\n");
-+
-+ mmc = mmc_alloc_host(sizeof(struct bcm2835_host), dev);
-+ host = mmc_priv(mmc);
-+ host->mmc = mmc;
-+
-+
-+ if (IS_ERR(host)) {
-+ ret = PTR_ERR(host);
-+ goto err;
-+ }
-+
-+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT;
-+
-+#ifndef CONFIG_OF
-+#ifndef FORCE_PIO
-+ dma_cap_zero(mask);
-+ /* we don't care about the channel, any would work */
-+ dma_cap_set(DMA_SLAVE, mask);
-+
-+ host->dma_chan_tx = dma_request_channel(mask, NULL, NULL);
-+ host->dma_chan_rx = dma_request_channel(mask, NULL, NULL);
-+#endif
-+ host->max_clk = BCM2835_CLOCK_FREQ;
-+
-+#else
-+#ifndef FORCE_PIO
-+ host->dma_chan_tx = of_dma_request_slave_channel(node, "tx");
-+ host->dma_chan_rx = of_dma_request_slave_channel(node, "rx");
-+#endif
-+ clk = of_clk_get(node, 0);
-+ if (IS_ERR(clk)) {
-+ dev_err(dev, "get CLOCK failed\n");
-+ ret = PTR_ERR(clk);
-+ goto out;
-+ }
-+ host->max_clk = (clk_get_rate(clk));
-+#endif
-+ host->irq = platform_get_irq(pdev, 0);
-+
-+ if (!request_mem_region(iomem->start, resource_size(iomem),
-+ mmc_hostname(host->mmc))) {
-+ dev_err(&pdev->dev, "cannot request region\n");
-+ ret = -EBUSY;
-+ goto err_request;
-+ }
-+
-+ host->ioaddr = ioremap(iomem->start, resource_size(iomem));
-+ if (!host->ioaddr) {
-+ dev_err(&pdev->dev, "failed to remap registers\n");
-+ ret = -ENOMEM;
-+ goto err_remap;
-+ }
-+
-+ platform_set_drvdata(pdev, host);
-+
-+
-+ if (host->irq <= 0) {
-+ dev_err(dev, "get IRQ failed\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+
-+#ifndef CONFIG_OF
-+ mmc->caps |= MMC_CAP_4_BIT_DATA;
-+#else
-+ mmc_of_parse(mmc);
-+#endif
-+ host->timeout = msecs_to_jiffies(1000);
-+ spin_lock_init(&host->lock);
-+ mmc->ops = &bcm2835_ops;
-+ return bcm2835_mmc_add_host(host);
-+
-+
-+err_remap:
-+ release_mem_region(iomem->start, resource_size(iomem));
-+err_request:
-+ mmc_free_host(host->mmc);
-+err:
-+ dev_err(&pdev->dev, "%s failed %d\n", __func__, ret);
-+ return ret;
-+out:
-+ if (mmc)
-+ mmc_free_host(mmc);
-+ return ret;
-+}
-+
-+static int bcm2835_mmc_remove(struct platform_device *pdev)
-+{
-+ struct bcm2835_host *host = platform_get_drvdata(pdev);
-+ struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ unsigned long flags;
-+ int dead;
-+ u32 scratch;
-+
-+ dead = 0;
-+ scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+ if (scratch == (u32)-1)
-+ dead = 1;
-+
-+
-+ if (dead) {
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ host->flags |= SDHCI_DEVICE_DEAD;
-+
-+ if (host->mrq) {
-+ pr_err("%s: Controller removed during "
-+ " transfer!\n", mmc_hostname(host->mmc));
-+
-+ host->mrq->cmd->error = -ENOMEDIUM;
-+ tasklet_schedule(&host->finish_tasklet);
-+ }
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ }
-+
-+ mmc_remove_host(host->mmc);
-+
-+ if (!dead)
-+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+ free_irq(host->irq, host);
-+
-+ del_timer_sync(&host->timer);
-+
-+ tasklet_kill(&host->finish_tasklet);
-+
-+ iounmap(host->ioaddr);
-+ release_mem_region(iomem->start, resource_size(iomem));
-+ mmc_free_host(host->mmc);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+
-+static const struct of_device_id bcm2835_mmc_match[] = {
-+ { .compatible = "brcm,bcm2835-mmc" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
-+
-+
-+
-+static struct platform_driver bcm2835_mmc_driver = {
-+ .probe = bcm2835_mmc_probe,
-+ .remove = bcm2835_mmc_remove,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcm2835_mmc_match,
-+ },
-+};
-+module_platform_driver(bcm2835_mmc_driver);
-+
-+MODULE_ALIAS("platform:mmc-bcm2835");
-+MODULE_DESCRIPTION("BCM2835 SDHCI driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Gellert Weisz");
-diff -Nur linux-3.12.38/drivers/mmc/host/Kconfig linux-rpi/drivers/mmc/host/Kconfig
---- linux-3.12.38/drivers/mmc/host/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/Kconfig 2015-03-10 17:26:50.558216692 +0100
-@@ -260,6 +260,27 @@
-
- If you have a controller with this interface, say Y or M here.
-
-+config MMC_SDHCI_BCM2708
-+ tristate "SDHCI support on BCM2708"
-+ depends on MMC_SDHCI && MACH_BCM2708
-+ select MMC_SDHCI_IO_ACCESSORS
-+ help
-+ This selects the Secure Digital Host Controller Interface (SDHCI)
-+ often referrered to as the eMMC block.
-+
-+ If you have a controller with this interface, say Y or M here.
-+
-+ If unsure, say N.
-+
-+config MMC_SDHCI_BCM2708_DMA
-+ bool "DMA support on BCM2708 Arasan controller"
-+ depends on MMC_SDHCI_BCM2708
-+ help
-+ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
-+ based chips.
-+
-+ If unsure, say N.
-+
- config MMC_SDHCI_BCM2835
- tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
- depends on ARCH_BCM2835
-@@ -271,6 +292,35 @@
-
- If unsure, say N.
-
-+config MMC_BCM2835
-+ tristate "MMC support on BCM2835"
-+ depends on MACH_BCM2708
-+ help
-+ This selects the MMC Interface on BCM2835.
-+
-+ If you have a controller with this interface, say Y or M here.
-+
-+ If unsure, say N.
-+
-+config MMC_BCM2835_DMA
-+ bool "DMA support on BCM2835 Arasan controller"
-+ depends on MMC_BCM2835
-+ help
-+ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
-+ based chips.
-+
-+ If unsure, say N.
-+
-+config MMC_BCM2835_PIO_DMA_BARRIER
-+ int "Block count limit for PIO transfers"
-+ depends on MMC_BCM2835 && MMC_BCM2835_DMA
-+ range 0 256
-+ default 2
-+ help
-+ The inclusive limit in bytes under which PIO will be used instead of DMA
-+
-+ If unsure, say 2 here.
-+
- config MMC_OMAP
- tristate "TI OMAP Multimedia Card Interface support"
- depends on ARCH_OMAP
-diff -Nur linux-3.12.38/drivers/mmc/host/Makefile linux-rpi/drivers/mmc/host/Makefile
---- linux-3.12.38/drivers/mmc/host/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/Makefile 2015-03-10 17:26:50.558216692 +0100
-@@ -15,6 +15,8 @@
- obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
- obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
- obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
-+obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o
-+obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
- obj-$(CONFIG_MMC_WBSD) += wbsd.o
- obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
- obj-$(CONFIG_MMC_OMAP) += omap.o
-diff -Nur linux-3.12.38/drivers/mmc/host/sdhci-acpi.c linux-rpi/drivers/mmc/host/sdhci-acpi.c
---- linux-3.12.38/drivers/mmc/host/sdhci-acpi.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/sdhci-acpi.c 2015-03-10 17:26:50.562216692 +0100
-@@ -119,11 +119,9 @@
- .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | MMC_CAP_HW_RESET,
- .caps2 = MMC_CAP2_HC_ERASE_SZ,
- .flags = SDHCI_ACPI_RUNTIME_PM,
-- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
- };
-
- static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
-- .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
- .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
- .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD,
- .flags = SDHCI_ACPI_RUNTIME_PM,
-@@ -144,23 +142,16 @@
- static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
- { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
- { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
-- { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
- { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
-- { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
- { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
-- { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
-- { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
- { "PNP0D40" },
- { },
- };
-
- static const struct acpi_device_id sdhci_acpi_ids[] = {
- { "80860F14" },
-- { "80860F16" },
- { "INT33BB" },
- { "INT33C6" },
-- { "INT3436" },
-- { "INT344D" },
- { "PNP0D40" },
- { },
- };
-diff -Nur linux-3.12.38/drivers/mmc/host/sdhci-bcm2708.c linux-rpi/drivers/mmc/host/sdhci-bcm2708.c
---- linux-3.12.38/drivers/mmc/host/sdhci-bcm2708.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/sdhci-bcm2708.c 2015-03-10 17:26:50.562216692 +0100
-@@ -0,0 +1,1433 @@
-+/*
-+ * sdhci-bcm2708.c Support for SDHCI device on BCM2708
-+ * Copyright (c) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+/* Supports:
-+ * SDHCI platform device - Arasan SD controller in BCM2708
-+ *
-+ * Inspired by sdhci-pci.c, by Pierre Ossman
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/highmem.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+
-+#include <linux/io.h>
-+#include <linux/dma-mapping.h>
-+#include <mach/dma.h>
-+
-+#include "sdhci.h"
-+
-+/*****************************************************************************\
-+ * *
-+ * Configuration *
-+ * *
-+\*****************************************************************************/
-+
-+#define DRIVER_NAME "bcm2708_sdhci"
-+
-+/* for the time being insist on DMA mode - PIO seems not to work */
-+#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA
-+#warning Non-DMA (PIO) version of this driver currently unavailable
-+#endif
-+#undef CONFIG_MMC_SDHCI_BCM2708_DMA
-+#define CONFIG_MMC_SDHCI_BCM2708_DMA y
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+/* #define CHECK_DMA_USE */
-+#endif
-+//#define LOG_REGISTERS
-+
-+#define USE_SCHED_TIME
-+#define USE_SPACED_WRITES_2CLK 1 /* space consecutive register writes */
-+#define USE_SOFTWARE_TIMEOUTS 1 /* not hardware timeouts */
-+#define SOFTWARE_ERASE_TIMEOUT_SEC 30
-+
-+#define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */
-+#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
-+/* We are worried that SD card DMA use may be blocking the AXI bus for others */
-+
-+/*! TODO: obtain these from the physical address */
-+#define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */
-+#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER)
-+
-+#define MAX_LITE_TRANSFER 32768
-+#define MAX_NORMAL_TRANSFER 1073741824
-+
-+#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */
-+
-+/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */
-+#define BCM2708_EMMC_CLOCK_FREQ 50000000
-+
-+#define REG_EXRDFIFO_EN 0x80
-+#define REG_EXRDFIFO_CFG 0x84
-+
-+int cycle_delay=2;
-+
-+/*****************************************************************************\
-+ * *
-+ * Debug *
-+ * *
-+\*****************************************************************************/
-+
-+
-+
-+#define DBG(f, x...) \
-+ pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
-+// printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG
-+
-+
-+/*****************************************************************************\
-+ * *
-+ * High Precision Time *
-+ * *
-+\*****************************************************************************/
-+
-+#ifdef USE_SCHED_TIME
-+
-+#include <mach/frc.h>
-+
-+typedef unsigned long hptime_t;
-+
-+#define FMT_HPT "lu"
-+
-+static inline hptime_t hptime(void)
-+{
-+ return frc_clock_ticks32();
-+}
-+
-+#define HPTIME_CLK_NS 1000ul
-+
-+#else
-+
-+typedef unsigned long hptime_t;
-+
-+#define FMT_HPT "lu"
-+
-+static inline hptime_t hptime(void)
-+{
-+ return jiffies;
-+}
-+
-+#define HPTIME_CLK_NS (1000000000ul/HZ)
-+
-+#endif
-+
-+static inline unsigned long int since_ns(hptime_t t)
-+{
-+ return (unsigned long)((hptime() - t) * HPTIME_CLK_NS);
-+}
-+
-+static bool allow_highspeed = 1;
-+static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ;
-+static bool sync_after_dma = 1;
-+static bool missing_status = 1;
-+static bool spurious_crc_acmd51 = 0;
-+bool enable_llm = 1;
-+bool extra_messages = 0;
-+
-+#if 0
-+static void hptime_test(void)
-+{
-+ hptime_t now;
-+ hptime_t later;
-+
-+ now = hptime();
-+ msleep(10);
-+ later = hptime();
-+
-+ printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks "
-+ "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
-+ later-now, now, later,
-+ (unsigned long)(HPTIME_CLK_NS * (later - now)));
-+
-+ now = hptime();
-+ msleep(1000);
-+ later = hptime();
-+
-+ printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks "
-+ "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
-+ later-now, now, later,
-+ (unsigned long)(HPTIME_CLK_NS * (later - now)));
-+}
-+#endif
-+
-+/*****************************************************************************\
-+ * *
-+ * SDHCI core callbacks *
-+ * *
-+\*****************************************************************************/
-+
-+
-+#ifdef CHECK_DMA_USE
-+/*#define CHECK_DMA_REG_USE*/
-+#endif
-+
-+#ifdef CHECK_DMA_REG_USE
-+/* we don't expect anything to be using these registers during a
-+ DMA (except the IRQ status) - so check */
-+static void check_dma_reg_use(struct sdhci_host *host, int reg);
-+#else
-+#define check_dma_reg_use(host, reg)
-+#endif
-+
-+
-+static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg)
-+{
-+ return readl(host->ioaddr + reg);
-+}
-+
-+u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg)
-+{
-+ u32 l = sdhci_bcm2708_raw_readl(host, reg);
-+
-+#ifdef LOG_REGISTERS
-+ printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n",
-+ mmc_hostname(host->mmc), reg, l);
-+#endif
-+ check_dma_reg_use(host, reg);
-+
-+ return l;
-+}
-+
-+u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg)
-+{
-+ u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
-+ u32 w = l >> (reg << 3 & 0x18) & 0xffff;
-+
-+#ifdef LOG_REGISTERS
-+ printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n",
-+ mmc_hostname(host->mmc), reg, w);
-+#endif
-+ check_dma_reg_use(host, reg);
-+
-+ return (u16)w;
-+}
-+
-+u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg)
-+{
-+ u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
-+ u32 b = l >> (reg << 3 & 0x18) & 0xff;
-+
-+#ifdef LOG_REGISTERS
-+ printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n",
-+ mmc_hostname(host->mmc), reg, b);
-+#endif
-+ check_dma_reg_use(host, reg);
-+
-+ return (u8)b;
-+}
-+
-+
-+static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg)
-+{
-+ u32 ier;
-+
-+#if USE_SPACED_WRITES_2CLK
-+ static bool timeout_disabled = false;
-+ unsigned int ns_2clk = 0;
-+
-+ /* The Arasan has a bugette whereby it may lose the content of
-+ * successive writes to registers that are within two SD-card clock
-+ * cycles of each other (a clock domain crossing problem).
-+ * It seems, however, that the data register does not have this problem.
-+ * (Which is just as well - otherwise we'd have to nobble the DMA engine
-+ * too)
-+ */
-+ if (reg != SDHCI_BUFFER && host->clock != 0) {
-+ /* host->clock is the clock freq in Hz */
-+ static hptime_t last_write_hpt;
-+ hptime_t now = hptime();
-+ ns_2clk = cycle_delay*1000000/(host->clock/1000);
-+
-+ if (now == last_write_hpt || now == last_write_hpt+1) {
-+ /* we can't guarantee any significant time has
-+ * passed - we'll have to wait anyway ! */
-+ ndelay(ns_2clk);
-+ } else
-+ {
-+ /* we must have waited at least this many ns: */
-+ unsigned int ns_wait = HPTIME_CLK_NS *
-+ (now - last_write_hpt - 1);
-+ if (ns_wait < ns_2clk)
-+ ndelay(ns_2clk - ns_wait);
-+ }
-+ last_write_hpt = now;
-+ }
-+#if USE_SOFTWARE_TIMEOUTS
-+ /* The Arasan is clocked for timeouts using the SD clock which is too
-+ * fast for ERASE commands and causes issues. So we disable timeouts
-+ * for ERASE */
-+ if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE &&
-+ reg == (SDHCI_COMMAND & ~3)) {
-+ mod_timer(&host->timer,
-+ jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ);
-+ ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
-+ ier &= ~SDHCI_INT_DATA_TIMEOUT;
-+ writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
-+ timeout_disabled = true;
-+ ndelay(ns_2clk);
-+ } else if (timeout_disabled) {
-+ ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
-+ ier |= SDHCI_INT_DATA_TIMEOUT;
-+ writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
-+ timeout_disabled = false;
-+ ndelay(ns_2clk);
-+ }
-+#endif
-+ writel(val, host->ioaddr + reg);
-+#else
-+ void __iomem * regaddr = host->ioaddr + reg;
-+
-+ writel(val, regaddr);
-+
-+ if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0)
-+ {
-+ int timeout = 100000;
-+ while (val != readl(regaddr) && --timeout > 0)
-+ continue;
-+
-+ if (timeout <= 0)
-+ printk(KERN_ERR "%s: writing 0x%X to reg 0x%X "
-+ "always gives 0x%X\n",
-+ mmc_hostname(host->mmc),
-+ val, reg, readl(regaddr));
-+ BUG_ON(timeout <= 0);
-+ }
-+#endif
-+}
-+
-+
-+void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg)
-+{
-+#ifdef LOG_REGISTERS
-+ printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n",
-+ mmc_hostname(host->mmc), reg, val);
-+#endif
-+ check_dma_reg_use(host, reg);
-+
-+ sdhci_bcm2708_raw_writel(host, val, reg);
-+}
-+
-+void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg)
-+{
-+ static u32 shadow = 0;
-+
-+ u32 p = reg == SDHCI_COMMAND ? shadow :
-+ sdhci_bcm2708_raw_readl(host, reg & ~3);
-+ u32 s = reg << 3 & 0x18;
-+ u32 l = val << s;
-+ u32 m = 0xffff << s;
-+
-+#ifdef LOG_REGISTERS
-+ printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n",
-+ mmc_hostname(host->mmc), reg, val);
-+#endif
-+
-+ if (reg == SDHCI_TRANSFER_MODE)
-+ shadow = (p & ~m) | l;
-+ else {
-+ check_dma_reg_use(host, reg);
-+ sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
-+ }
-+}
-+
-+void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg)
-+{
-+ u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3);
-+ u32 s = reg << 3 & 0x18;
-+ u32 l = val << s;
-+ u32 m = 0xff << s;
-+
-+#ifdef LOG_REGISTERS
-+ printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n",
-+ mmc_hostname(host->mmc), reg, val);
-+#endif
-+
-+ check_dma_reg_use(host, reg);
-+ sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
-+}
-+
-+static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host)
-+{
-+ return emmc_clock_freq;
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Operation *
-+ * *
-+\*****************************************************************************/
-+
-+struct sdhci_bcm2708_priv {
-+ int dma_chan;
-+ int dma_irq;
-+ void __iomem *dma_chan_base;
-+ struct bcm2708_dma_cb *cb_base; /* DMA control blocks */
-+ dma_addr_t cb_handle;
-+ /* tracking scatter gather progress */
-+ unsigned sg_ix; /* scatter gather list index */
-+ unsigned sg_done; /* bytes in current sg_ix done */
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ unsigned char dma_wanted; /* DMA transfer requested */
-+ unsigned char dma_waits; /* wait states in DMAs */
-+#ifdef CHECK_DMA_USE
-+ unsigned char dmas_pending; /* no of unfinished DMAs */
-+ hptime_t when_started;
-+ hptime_t when_reset;
-+ hptime_t when_stopped;
-+#endif
-+#endif
-+ /* signalling the end of a transfer */
-+ void (*complete)(struct sdhci_host *);
-+};
-+
-+#define SDHCI_HOST_PRIV(host) \
-+ (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1)
-+
-+
-+
-+#ifdef CHECK_DMA_REG_USE
-+static void check_dma_reg_use(struct sdhci_host *host, int reg)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) {
-+ printk(KERN_INFO"%s: accessing register 0x%x during DMA\n",
-+ mmc_hostname(host->mmc), reg);
-+ }
-+}
-+#endif
-+
-+
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+
-+static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set)
-+{
-+ u32 ier;
-+
-+ ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE);
-+ ier &= ~clear;
-+ ier |= set;
-+ /* change which requests generate IRQs - makes no difference to
-+ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
-+ sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE);
-+}
-+
-+static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs)
-+{
-+ sdhci_clear_set_irqgen(host, 0, irqs);
-+}
-+
-+static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs)
-+{
-+ sdhci_clear_set_irqgen(host, irqs, 0);
-+}
-+
-+
-+
-+static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host,
-+ int ix,
-+ dma_addr_t dma_addr, unsigned len,
-+ int /*bool*/ is_last)
-+{
-+ struct bcm2708_dma_cb *cb;
-+ unsigned char dmawaits = host->dma_waits;
-+ unsigned i, max_size;
-+
-+ if (host->dma_chan >= 8) /* we have a LITE channel */
-+ max_size = MAX_LITE_TRANSFER;
-+ else
-+ max_size = MAX_NORMAL_TRANSFER;
-+
-+ for (i = 0; i < len; i += max_size) {
-+ cb = &host->cb_base[ix+i/max_size];
-+
-+ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
-+ BCM2708_DMA_WAITS(dmawaits) |
-+ BCM2708_DMA_WAIT_RESP |
-+ BCM2708_DMA_S_DREQ |
-+ BCM2708_DMA_D_WIDTH |
-+ BCM2708_DMA_D_INC;
-+ cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */
-+ cb->dst = dma_addr + (dma_addr_t)i;
-+ cb->length = min(len-i, max_size);
-+ cb->stride = 0;
-+
-+ if (is_last && len-i <= max_size) {
-+ cb->info |= BCM2708_DMA_INT_EN;
-+ cb->next = 0;
-+ } else
-+ cb->next = host->cb_handle +
-+ (ix+1 + i/max_size)*sizeof(struct bcm2708_dma_cb);
-+
-+ cb->pad[0] = 0;
-+ cb->pad[1] = 0;
-+ }
-+}
-+
-+static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host,
-+ int ix,
-+ dma_addr_t dma_addr, unsigned len,
-+ int /*bool*/ is_last)
-+{
-+ struct bcm2708_dma_cb *cb = &host->cb_base[ix];
-+ unsigned char dmawaits = host->dma_waits;
-+ unsigned i, max_size;
-+
-+ if (host->dma_chan >= 8) /* we have a LITE channel */
-+ max_size = MAX_LITE_TRANSFER;
-+ else
-+ max_size = MAX_NORMAL_TRANSFER;
-+
-+ /* We can make arbitrarily large writes as long as we specify DREQ to
-+ pace the delivery of bytes to the Arasan hardware. However we need
-+ to take care when using LITE channels */
-+
-+ for (i = 0; i < len; i += max_size) {
-+ cb = &host->cb_base[ix+i/max_size];
-+
-+ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
-+ BCM2708_DMA_WAITS(dmawaits) |
-+ BCM2708_DMA_WAIT_RESP |
-+ BCM2708_DMA_D_DREQ |
-+ BCM2708_DMA_S_WIDTH |
-+ BCM2708_DMA_S_INC;
-+ cb->src = dma_addr + (dma_addr_t)i;
-+ cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */
-+ cb->length = min(len-i, max_size);
-+ cb->stride = 0;
-+
-+ if (is_last && len-i <= max_size) {
-+ cb->info |= BCM2708_DMA_INT_EN;
-+ cb->next = 0;
-+ } else
-+ cb->next = host->cb_handle +
-+ (ix+1 + i/max_size)*sizeof(struct bcm2708_dma_cb);
-+
-+ cb->pad[0] = 0;
-+ cb->pad[1] = 0;
-+ }
-+}
-+
-+
-+static void schci_bcm2708_dma_go(struct sdhci_host *host)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ void __iomem *dma_chan_base = host_priv->dma_chan_base;
-+
-+ BUG_ON(host_priv->dma_wanted);
-+#ifdef CHECK_DMA_USE
-+ if (host_priv->dma_wanted)
-+ printk(KERN_ERR "%s: DMA already in progress - "
-+ "now %"FMT_HPT", last started %lu "
-+ "reset %lu stopped %lu\n",
-+ mmc_hostname(host->mmc),
-+ hptime(), since_ns(host_priv->when_started),
-+ since_ns(host_priv->when_reset),
-+ since_ns(host_priv->when_stopped));
-+ else if (host_priv->dmas_pending > 0)
-+ printk(KERN_INFO "%s: note - new DMA when %d reset DMAs "
-+ "already in progress - "
-+ "now %"FMT_HPT", started %lu reset %lu stopped %lu\n",
-+ mmc_hostname(host->mmc),
-+ host_priv->dmas_pending,
-+ hptime(), since_ns(host_priv->when_started),
-+ since_ns(host_priv->when_reset),
-+ since_ns(host_priv->when_stopped));
-+ host_priv->dmas_pending += 1;
-+ host_priv->when_started = hptime();
-+#endif
-+ host_priv->dma_wanted = 1;
-+ DBG("PDMA go - base %p handle %08X\n", dma_chan_base,
-+ host_priv->cb_handle);
-+ bcm_dma_start(dma_chan_base, host_priv->cb_handle);
-+}
-+
-+
-+static void
-+sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+
-+ DBG("PDMA to read %d bytes\n", len);
-+ host_priv->sg_done += len;
-+ schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/);
-+ schci_bcm2708_dma_go(host);
-+}
-+
-+
-+static void
-+sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+
-+ DBG("PDMA to write %d bytes\n", len);
-+ //BUG_ON(0 != (len & 0x1ff));
-+
-+ host_priv->sg_done += len;
-+ schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/);
-+ schci_bcm2708_dma_go(host);
-+}
-+
-+/*! space is avaiable to receive into or data is available to write
-+ Platform DMA exported function
-+*/
-+void
-+sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
-+ void(*completion_callback)(struct sdhci_host *host))
-+{
-+ struct mmc_data *data = host->data;
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ int sg_ix;
-+ size_t bytes;
-+ dma_addr_t addr;
-+
-+ BUG_ON(NULL == data);
-+ BUG_ON(0 == data->blksz);
-+
-+ host_priv->complete = completion_callback;
-+
-+ sg_ix = host_priv->sg_ix;
-+ BUG_ON(sg_ix >= data->sg_len);
-+
-+ /* we can DMA blocks larger than blksz - it may hang the DMA
-+ channel but we are its only user */
-+ bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done;
-+ addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done;
-+
-+ if (bytes > 0) {
-+ /* We're going to poll for read/write available state until
-+ we finish this DMA
-+ */
-+
-+ if (data->flags & MMC_DATA_READ) {
-+ if (*ref_intmask & SDHCI_INT_DATA_AVAIL) {
-+ sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+ SDHCI_INT_SPACE_AVAIL);
-+ sdhci_platdma_read(host, addr, bytes);
-+ }
-+ } else {
-+ if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) {
-+ sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+ SDHCI_INT_SPACE_AVAIL);
-+ sdhci_platdma_write(host, addr, bytes);
-+ }
-+ }
-+ }
-+ /* else:
-+ we have run out of bytes that need transferring (e.g. we may be in
-+ the middle of the last DMA transfer), or
-+ it is also possible that we've been called when another IRQ is
-+ signalled, even though we've turned off signalling of our own IRQ */
-+
-+ *ref_intmask &= ~SDHCI_INT_DATA_END;
-+ /* don't let the main sdhci driver act on this .. we'll deal with it
-+ when we respond to the DMA - if one is currently in progress */
-+}
-+
-+/* is it possible to DMA the given mmc_data structure?
-+ Platform DMA exported function
-+*/
-+int /*bool*/
-+sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len);
-+
-+ if (!ok)
-+ DBG("Reverting to PIO - bad cache alignment\n");
-+
-+ else {
-+ host_priv->sg_ix = 0; /* first SG index */
-+ host_priv->sg_done = 0; /* no bytes done */
-+ }
-+
-+ return ok;
-+}
-+
-+#include <mach/arm_control.h> //GRAYG
-+/*! the current SD transacton has been abandonned
-+ We need to tidy up if we were in the middle of a DMA
-+ Platform DMA exported function
-+*/
-+void
-+sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+// unsigned long flags;
-+
-+ BUG_ON(NULL == host);
-+
-+// spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host_priv->dma_wanted) {
-+ if (NULL == data) {
-+ printk(KERN_ERR "%s: ongoing DMA reset - no data!\n",
-+ mmc_hostname(host->mmc));
-+ BUG_ON(NULL == data);
-+ } else {
-+ struct scatterlist *sg;
-+ int sg_len;
-+ int sg_todo;
-+ int rc;
-+ unsigned long cs;
-+
-+ sg = data->sg;
-+ sg_len = data->sg_len;
-+ sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
-+
-+ cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (!(BCM2708_DMA_ACTIVE & cs))
-+ {
-+ if (extra_messages)
-+ printk(KERN_INFO "%s: missed completion of "
-+ "cmd %d DMA (%d/%d [%d]/[%d]) - "
-+ "ignoring it\n",
-+ mmc_hostname(host->mmc),
-+ host->last_cmdop,
-+ host_priv->sg_done, sg_todo,
-+ host_priv->sg_ix+1, sg_len);
-+ }
-+ else
-+ printk(KERN_INFO "%s: resetting ongoing cmd %d"
-+ "DMA before %d/%d [%d]/[%d] complete\n",
-+ mmc_hostname(host->mmc),
-+ host->last_cmdop,
-+ host_priv->sg_done, sg_todo,
-+ host_priv->sg_ix+1, sg_len);
-+#ifdef CHECK_DMA_USE
-+ printk(KERN_INFO "%s: now %"FMT_HPT" started %lu "
-+ "last reset %lu last stopped %lu\n",
-+ mmc_hostname(host->mmc),
-+ hptime(), since_ns(host_priv->when_started),
-+ since_ns(host_priv->when_reset),
-+ since_ns(host_priv->when_stopped));
-+ { unsigned long info, debug;
-+ void __iomem *base;
-+ unsigned long pend0, pend1, pend2;
-+
-+ base = host_priv->dma_chan_base;
-+ cs = readl(base + BCM2708_DMA_CS);
-+ info = readl(base + BCM2708_DMA_INFO);
-+ debug = readl(base + BCM2708_DMA_DEBUG);
-+ printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX "
-+ "DEBUG=%08lX\n",
-+ mmc_hostname(host->mmc),
-+ host_priv->dma_chan,
-+ cs, info, debug);
-+ pend0 = readl(__io_address(ARM_IRQ_PEND0));
-+ pend1 = readl(__io_address(ARM_IRQ_PEND1));
-+ pend2 = readl(__io_address(ARM_IRQ_PEND2));
-+
-+ printk(KERN_INFO "%s: PEND0=%08lX "
-+ "PEND1=%08lX PEND2=%08lX\n",
-+ mmc_hostname(host->mmc),
-+ pend0, pend1, pend2);
-+
-+ //gintsts = readl(__io_address(GINTSTS));
-+ //gintmsk = readl(__io_address(GINTMSK));
-+ //printk(KERN_INFO "%s: USB GINTSTS=%08lX"
-+ // "GINTMSK=%08lX\n",
-+ // mmc_hostname(host->mmc), gintsts, gintmsk);
-+ }
-+#endif
-+ rc = bcm_dma_abort(host_priv->dma_chan_base);
-+ BUG_ON(rc != 0);
-+ }
-+ host_priv->dma_wanted = 0;
-+#ifdef CHECK_DMA_USE
-+ host_priv->when_reset = hptime();
-+#endif
-+ }
-+
-+// spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host,
-+ u32 dma_cs)
-+{
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ struct mmc_data *data;
-+ struct scatterlist *sg;
-+ int sg_len;
-+ int sg_ix;
-+ int sg_todo;
-+// unsigned long flags;
-+
-+ BUG_ON(NULL == host);
-+
-+// spin_lock_irqsave(&host->lock, flags);
-+ data = host->data;
-+
-+#ifdef CHECK_DMA_USE
-+ if (host_priv->dmas_pending <= 0)
-+ DBG("on completion no DMA in progress - "
-+ "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
-+ hptime(), since_ns(host_priv->when_started),
-+ since_ns(host_priv->when_reset),
-+ since_ns(host_priv->when_stopped));
-+ else if (host_priv->dmas_pending > 1)
-+ DBG("still %d DMA in progress after completion - "
-+ "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
-+ host_priv->dmas_pending - 1,
-+ hptime(), since_ns(host_priv->when_started),
-+ since_ns(host_priv->when_reset),
-+ since_ns(host_priv->when_stopped));
-+ BUG_ON(host_priv->dmas_pending <= 0);
-+ host_priv->dmas_pending -= 1;
-+ host_priv->when_stopped = hptime();
-+#endif
-+ host_priv->dma_wanted = 0;
-+
-+ if (NULL == data) {
-+ DBG("PDMA unused completion - status 0x%X\n", dma_cs);
-+// spin_unlock_irqrestore(&host->lock, flags);
-+ return;
-+ }
-+ sg = data->sg;
-+ sg_len = data->sg_len;
-+ sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
-+
-+ DBG("PDMA complete %d/%d [%d]/[%d]..\n",
-+ host_priv->sg_done, sg_todo,
-+ host_priv->sg_ix+1, sg_len);
-+
-+ BUG_ON(host_priv->sg_done > sg_todo);
-+
-+ if (host_priv->sg_done >= sg_todo) {
-+ host_priv->sg_ix++;
-+ host_priv->sg_done = 0;
-+ }
-+
-+ sg_ix = host_priv->sg_ix;
-+ if (sg_ix < sg_len) {
-+ u32 irq_mask;
-+ /* Set off next DMA if we've got the capacity */
-+
-+ if (data->flags & MMC_DATA_READ)
-+ irq_mask = SDHCI_INT_DATA_AVAIL;
-+ else
-+ irq_mask = SDHCI_INT_SPACE_AVAIL;
-+
-+ /* We have to use the interrupt status register on the BCM2708
-+ rather than the SDHCI_PRESENT_STATE register because latency
-+ in the glue logic means that the information retrieved from
-+ the latter is not always up-to-date w.r.t the DMA engine -
-+ it may not indicate that a read or a write is ready yet */
-+ if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) &
-+ irq_mask) {
-+ size_t bytes = sg_dma_len(&sg[sg_ix]) -
-+ host_priv->sg_done;
-+ dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) +
-+ host_priv->sg_done;
-+
-+ /* acknowledge interrupt */
-+ sdhci_bcm2708_raw_writel(host, irq_mask,
-+ SDHCI_INT_STATUS);
-+
-+ BUG_ON(0 == bytes);
-+
-+ if (data->flags & MMC_DATA_READ)
-+ sdhci_platdma_read(host, addr, bytes);
-+ else
-+ sdhci_platdma_write(host, addr, bytes);
-+ } else {
-+ DBG("PDMA - wait avail\n");
-+ /* may generate an IRQ if already present */
-+ sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+ SDHCI_INT_SPACE_AVAIL);
-+ }
-+ } else {
-+ if (sync_after_dma) {
-+ /* On the Arasan controller the stop command (which will be
-+ scheduled after this completes) does not seem to work
-+ properly if we allow it to be issued when we are
-+ transferring data to/from the SD card.
-+ We get CRC and DEND errors unless we wait for
-+ the SD controller to finish reading/writing to the card. */
-+ u32 state_mask;
-+ int timeout=3*1000*1000;
-+
-+ DBG("PDMA over - sync card\n");
-+ if (data->flags & MMC_DATA_READ)
-+ state_mask = SDHCI_DOING_READ;
-+ else
-+ state_mask = SDHCI_DOING_WRITE;
-+
-+ while (0 != (sdhci_bcm2708_raw_readl(host, SDHCI_PRESENT_STATE)
-+ & state_mask) && --timeout > 0)
-+ {
-+ udelay(1);
-+ continue;
-+ }
-+ if (timeout <= 0)
-+ printk(KERN_ERR"%s: final %s to SD card still "
-+ "running\n",
-+ mmc_hostname(host->mmc),
-+ data->flags & MMC_DATA_READ? "read": "write");
-+ }
-+ if (host_priv->complete) {
-+ (*host_priv->complete)(host);
-+ DBG("PDMA %s complete\n",
-+ data->flags & MMC_DATA_READ?"read":"write");
-+ sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+ SDHCI_INT_SPACE_AVAIL);
-+ }
-+ }
-+// spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id)
-+{
-+ irqreturn_t result = IRQ_NONE;
-+ struct sdhci_host *host = dev_id;
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ u32 dma_cs; /* control and status register */
-+
-+ BUG_ON(NULL == dev_id);
-+ BUG_ON(NULL == host_priv->dma_chan_base);
-+
-+ sdhci_spin_lock(host);
-+
-+ dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (dma_cs & BCM2708_DMA_ERR) {
-+ unsigned long debug;
-+ debug = readl(host_priv->dma_chan_base +
-+ BCM2708_DMA_DEBUG);
-+ printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n",
-+ mmc_hostname(host->mmc), (unsigned long)dma_cs,
-+ (unsigned long)debug);
-+ /* reset error */
-+ writel(debug, host_priv->dma_chan_base +
-+ BCM2708_DMA_DEBUG);
-+ }
-+ if (dma_cs & BCM2708_DMA_INT) {
-+ /* acknowledge interrupt */
-+ writel(BCM2708_DMA_INT,
-+ host_priv->dma_chan_base + BCM2708_DMA_CS);
-+
-+ dsb(); /* ARM data synchronization (push) operation */
-+
-+ if (!host_priv->dma_wanted) {
-+ /* ignore this interrupt - it was reset */
-+ if (extra_messages)
-+ printk(KERN_INFO "%s: DMA IRQ %X ignored - "
-+ "results were reset\n",
-+ mmc_hostname(host->mmc), dma_cs);
-+#ifdef CHECK_DMA_USE
-+ printk(KERN_INFO "%s: now %"FMT_HPT
-+ " started %lu reset %lu stopped %lu\n",
-+ mmc_hostname(host->mmc), hptime(),
-+ since_ns(host_priv->when_started),
-+ since_ns(host_priv->when_reset),
-+ since_ns(host_priv->when_stopped));
-+ host_priv->dmas_pending--;
-+#endif
-+ } else
-+ sdhci_bcm2708_dma_complete_irq(host, dma_cs);
-+
-+ result = IRQ_HANDLED;
-+ }
-+ sdhci_spin_unlock(host);
-+
-+ return result;
-+}
-+#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * Device Attributes *
-+ * *
-+\*****************************************************************************/
-+
-+
-+/**
-+ * Show the DMA-using status
-+ */
-+static ssize_t attr_dma_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
-+
-+ if (host) {
-+ int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0);
-+ return sprintf(buf, "%d\n", use_dma);
-+ } else
-+ return -EINVAL;
-+}
-+
-+/**
-+ * Set the DMA-using status
-+ */
-+static ssize_t attr_dma_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
-+
-+ if (host) {
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ int on = simple_strtol(buf, NULL, 0);
-+ if (on) {
-+ host->flags |= SDHCI_USE_PLATDMA;
-+ sdhci_bcm2708_writel(host, 1, REG_EXRDFIFO_EN);
-+ printk(KERN_INFO "%s: DMA enabled\n",
-+ mmc_hostname(host->mmc));
-+ } else {
-+ host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA);
-+ sdhci_bcm2708_writel(host, 0, REG_EXRDFIFO_EN);
-+ printk(KERN_INFO "%s: DMA disabled\n",
-+ mmc_hostname(host->mmc));
-+ }
-+#endif
-+ return count;
-+ } else
-+ return -EINVAL;
-+}
-+
-+static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store);
-+
-+
-+/**
-+ * Show the DMA wait states used
-+ */
-+static ssize_t attr_dmawait_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
-+
-+ if (host) {
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ int dmawait = host_priv->dma_waits;
-+ return sprintf(buf, "%d\n", dmawait);
-+ } else
-+ return -EINVAL;
-+}
-+
-+/**
-+ * Set the DMA wait state used
-+ */
-+static ssize_t attr_dmawait_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
-+
-+ if (host) {
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ int dma_waits = simple_strtol(buf, NULL, 0);
-+ if (dma_waits >= 0 && dma_waits < 32)
-+ host_priv->dma_waits = dma_waits;
-+ else
-+ printk(KERN_ERR "%s: illegal dma_waits value - %d",
-+ mmc_hostname(host->mmc), dma_waits);
-+#endif
-+ return count;
-+ } else
-+ return -EINVAL;
-+}
-+
-+static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO,
-+ attr_dmawait_show, attr_dmawait_store);
-+
-+
-+/**
-+ * Show the DMA-using status
-+ */
-+static ssize_t attr_status_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
-+
-+ if (host) {
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ return sprintf(buf,
-+ "present: yes\n"
-+ "power: %s\n"
-+ "clock: %u Hz\n"
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ "dma: %s (%d waits)\n",
-+#else
-+ "dma: unconfigured\n",
-+#endif
-+ "always on",
-+ host->clock
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ , (host->flags & SDHCI_USE_PLATDMA)? "on": "off"
-+ , host_priv->dma_waits
-+#endif
-+ );
-+ } else
-+ return -EINVAL;
-+}
-+
-+static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL);
-+
-+/***************************************************************************** \
-+ * *
-+ * Power Management *
-+ * *
-+\*****************************************************************************/
-+
-+
-+#ifdef CONFIG_PM
-+static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)
-+ platform_get_drvdata(dev);
-+ int ret = 0;
-+
-+ if (host->mmc) {
-+ //ret = mmc_suspend_host(host->mmc);
-+ }
-+
-+ return ret;
-+}
-+
-+static int sdhci_bcm2708_resume(struct platform_device *dev)
-+{
-+ struct sdhci_host *host = (struct sdhci_host *)
-+ platform_get_drvdata(dev);
-+ int ret = 0;
-+
-+ if (host->mmc) {
-+ //ret = mmc_resume_host(host->mmc);
-+ }
-+
-+ return ret;
-+}
-+#endif
-+
-+
-+/*****************************************************************************\
-+ * *
-+ * Device quirk functions. Implemented as local ops because the flags *
-+ * field is out of space with newer kernels. This implementation can be *
-+ * back ported to older kernels as well. *
-+\****************************************************************************/
-+static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
-+{
-+ return 1;
-+}
-+
-+static unsigned int sdhci_bcm2708_quirk_spurious_crc_acmd51(struct sdhci_host *host)
-+{
-+ return 1;
-+}
-+
-+static unsigned int sdhci_bcm2708_missing_status(struct sdhci_host *host)
-+{
-+ return 1;
-+}
-+
-+/***************************************************************************** \
-+ * *
-+ * Device ops *
-+ * *
-+\*****************************************************************************/
-+
-+static struct sdhci_ops sdhci_bcm2708_ops = {
-+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
-+ .read_l = sdhci_bcm2708_readl,
-+ .read_w = sdhci_bcm2708_readw,
-+ .read_b = sdhci_bcm2708_readb,
-+ .write_l = sdhci_bcm2708_writel,
-+ .write_w = sdhci_bcm2708_writew,
-+ .write_b = sdhci_bcm2708_writeb,
-+#else
-+#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set
-+#endif
-+ .get_max_clock = sdhci_bcm2708_get_max_clock,
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ // Platform DMA operations
-+ .pdma_able = sdhci_bcm2708_platdma_dmaable,
-+ .pdma_avail = sdhci_bcm2708_platdma_avail,
-+ .pdma_reset = sdhci_bcm2708_platdma_reset,
-+#endif
-+ .extra_ints = sdhci_bcm2708_quirk_extra_ints,
-+};
-+
-+/*****************************************************************************\
-+ * *
-+ * Device probing/removal *
-+ * *
-+\*****************************************************************************/
-+
-+static int sdhci_bcm2708_probe(struct platform_device *pdev)
-+{
-+ struct sdhci_host *host;
-+ struct resource *iomem;
-+ struct sdhci_bcm2708_priv *host_priv;
-+ int ret;
-+
-+ BUG_ON(pdev == NULL);
-+
-+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!iomem) {
-+ ret = -ENOMEM;
-+ goto err;
-+ }
-+
-+ if (resource_size(iomem) != 0x100)
-+ dev_err(&pdev->dev, "Invalid iomem size. You may "
-+ "experience problems.\n");
-+
-+ if (pdev->dev.parent)
-+ host = sdhci_alloc_host(pdev->dev.parent,
-+ sizeof(struct sdhci_bcm2708_priv));
-+ else
-+ host = sdhci_alloc_host(&pdev->dev,
-+ sizeof(struct sdhci_bcm2708_priv));
-+
-+ if (IS_ERR(host)) {
-+ ret = PTR_ERR(host);
-+ goto err;
-+ }
-+ if (missing_status) {
-+ sdhci_bcm2708_ops.missing_status = sdhci_bcm2708_missing_status;
-+ }
-+
-+ if( spurious_crc_acmd51 ) {
-+ sdhci_bcm2708_ops.spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc_acmd51;
-+ }
-+
-+
-+ printk("sdhci: %s low-latency mode\n",enable_llm?"Enable":"Disable");
-+
-+ host->hw_name = "BCM2708_Arasan";
-+ host->ops = &sdhci_bcm2708_ops;
-+ host->irq = platform_get_irq(pdev, 0);
-+ host->second_irq = 0;
-+
-+ host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
-+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
-+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
-+ SDHCI_QUIRK_MISSING_CAPS |
-+ SDHCI_QUIRK_NO_HISPD_BIT |
-+ (sync_after_dma ? 0:SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12);
-+
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ host->flags = SDHCI_USE_PLATDMA;
-+#endif
-+
-+ if (!request_mem_region(iomem->start, resource_size(iomem),
-+ mmc_hostname(host->mmc))) {
-+ dev_err(&pdev->dev, "cannot request region\n");
-+ ret = -EBUSY;
-+ goto err_request;
-+ }
-+
-+ host->ioaddr = ioremap(iomem->start, resource_size(iomem));
-+ if (!host->ioaddr) {
-+ dev_err(&pdev->dev, "failed to remap registers\n");
-+ ret = -ENOMEM;
-+ goto err_remap;
-+ }
-+
-+ host_priv = SDHCI_HOST_PRIV(host);
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ host_priv->dma_wanted = 0;
-+#ifdef CHECK_DMA_USE
-+ host_priv->dmas_pending = 0;
-+ host_priv->when_started = 0;
-+ host_priv->when_reset = 0;
-+ host_priv->when_stopped = 0;
-+#endif
-+ host_priv->sg_ix = 0;
-+ host_priv->sg_done = 0;
-+ host_priv->complete = NULL;
-+ host_priv->dma_waits = SDHCI_BCM_DMA_WAITS;
-+
-+ host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K,
-+ &host_priv->cb_handle,
-+ GFP_KERNEL);
-+ if (!host_priv->cb_base) {
-+ dev_err(&pdev->dev, "cannot allocate DMA CBs\n");
-+ ret = -ENOMEM;
-+ goto err_alloc_cb;
-+ }
-+
-+ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
-+ &host_priv->dma_chan_base,
-+ &host_priv->dma_irq);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "couldn't allocate a DMA channel\n");
-+ goto err_add_dma;
-+ }
-+ host_priv->dma_chan = ret;
-+
-+ ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,
-+ 0 /*IRQF_SHARED*/, DRIVER_NAME " (dma)", host);
-+ if (ret) {
-+ dev_err(&pdev->dev, "cannot set DMA IRQ\n");
-+ goto err_add_dma_irq;
-+ }
-+ host->second_irq = host_priv->dma_irq;
-+ DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n",
-+ host_priv->cb_base, (unsigned)host_priv->cb_handle,
-+ host_priv->dma_chan, host_priv->dma_chan_base,
-+ host_priv->dma_irq);
-+
-+ // we support 3.3V
-+ host->caps |= SDHCI_CAN_VDD_330;
-+ if (allow_highspeed)
-+ host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
-+
-+ /* single block writes cause data loss with some SD cards! */
-+ host->mmc->caps2 |= MMC_CAP2_FORCE_MULTIBLOCK;
-+#endif
-+
-+ ret = sdhci_add_host(host);
-+ if (ret)
-+ goto err_add_host;
-+
-+ platform_set_drvdata(pdev, host);
-+ ret = device_create_file(&pdev->dev, &dev_attr_use_dma);
-+ ret = device_create_file(&pdev->dev, &dev_attr_dma_wait);
-+ ret = device_create_file(&pdev->dev, &dev_attr_status);
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ /* enable extension fifo for paced DMA transfers */
-+ sdhci_bcm2708_writel(host, 1, REG_EXRDFIFO_EN);
-+ sdhci_bcm2708_writel(host, 4, REG_EXRDFIFO_CFG);
-+#endif
-+
-+ printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n",
-+ mmc_hostname(host->mmc), (unsigned long long)iomem->start,
-+ host_priv->dma_chan, host_priv->dma_irq);
-+
-+ return 0;
-+
-+err_add_host:
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ free_irq(host_priv->dma_irq, host);
-+err_add_dma_irq:
-+ bcm_dma_chan_free(host_priv->dma_chan);
-+err_add_dma:
-+ dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
-+ host_priv->cb_handle);
-+err_alloc_cb:
-+#endif
-+ iounmap(host->ioaddr);
-+err_remap:
-+ release_mem_region(iomem->start, resource_size(iomem));
-+err_request:
-+ sdhci_free_host(host);
-+err:
-+ dev_err(&pdev->dev, "probe failed, err %d\n", ret);
-+ return ret;
-+}
-+
-+static int sdhci_bcm2708_remove(struct platform_device *pdev)
-+{
-+ struct sdhci_host *host = platform_get_drvdata(pdev);
-+ struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
-+ int dead;
-+ u32 scratch;
-+
-+ dead = 0;
-+ scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS);
-+ if (scratch == (u32)-1)
-+ dead = 1;
-+
-+ device_remove_file(&pdev->dev, &dev_attr_status);
-+ device_remove_file(&pdev->dev, &dev_attr_dma_wait);
-+ device_remove_file(&pdev->dev, &dev_attr_use_dma);
-+
-+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
-+ free_irq(host_priv->dma_irq, host);
-+ dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
-+ host_priv->cb_handle);
-+#endif
-+ sdhci_remove_host(host, dead);
-+ iounmap(host->ioaddr);
-+ release_mem_region(iomem->start, resource_size(iomem));
-+ sdhci_free_host(host);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sdhci_bcm2708_driver = {
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = sdhci_bcm2708_probe,
-+ .remove = sdhci_bcm2708_remove,
-+
-+#ifdef CONFIG_PM
-+ .suspend = sdhci_bcm2708_suspend,
-+ .resume = sdhci_bcm2708_resume,
-+#endif
-+
-+};
-+
-+/*****************************************************************************\
-+ * *
-+ * Driver init/exit *
-+ * *
-+\*****************************************************************************/
-+
-+static int __init sdhci_drv_init(void)
-+{
-+ return platform_driver_register(&sdhci_bcm2708_driver);
-+}
-+
-+static void __exit sdhci_drv_exit(void)
-+{
-+ platform_driver_unregister(&sdhci_bcm2708_driver);
-+}
-+
-+module_init(sdhci_drv_init);
-+module_exit(sdhci_drv_exit);
-+
-+module_param(allow_highspeed, bool, 0444);
-+module_param(emmc_clock_freq, int, 0444);
-+module_param(sync_after_dma, bool, 0444);
-+module_param(missing_status, bool, 0444);
-+module_param(spurious_crc_acmd51, bool, 0444);
-+module_param(enable_llm, bool, 0444);
-+module_param(cycle_delay, int, 0444);
-+module_param(extra_messages, bool, 0444);
-+
-+MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
-+MODULE_AUTHOR("Broadcom <info@broadcom.com>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:"DRIVER_NAME);
-+
-+MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes");
-+MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock");
-+MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete");
-+MODULE_PARM_DESC(missing_status, "Use the missing status quirk");
-+MODULE_PARM_DESC(spurious_crc_acmd51, "Use the spurious crc quirk for reading SCR (ACMD51)");
-+MODULE_PARM_DESC(enable_llm, "Enable low-latency mode");
-+MODULE_PARM_DESC(extra_messages, "Enable more sdcard warning messages");
-diff -Nur linux-3.12.38/drivers/mmc/host/sdhci.c linux-rpi/drivers/mmc/host/sdhci.c
---- linux-3.12.38/drivers/mmc/host/sdhci.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/sdhci.c 2015-03-11 10:46:10.585835779 +0100
-@@ -28,6 +28,7 @@
- #include <linux/mmc/mmc.h>
- #include <linux/mmc/host.h>
- #include <linux/mmc/card.h>
-+#include <linux/mmc/sd.h>
- #include <linux/mmc/slot-gpio.h>
-
- #include "sdhci.h"
-@@ -131,6 +132,42 @@
- * Low level functions *
- * *
- \*****************************************************************************/
-+static int sdhci_locked=0;
-+void sdhci_spin_lock(struct sdhci_host *host)
-+{
-+ spin_lock(&host->lock);
-+}
-+
-+void sdhci_spin_unlock(struct sdhci_host *host)
-+{
-+ spin_unlock(&host->lock);
-+}
-+
-+void sdhci_spin_lock_irqsave(struct sdhci_host *host,unsigned long *flags)
-+{
-+ spin_lock_irqsave(&host->lock,*flags);
-+}
-+
-+void sdhci_spin_unlock_irqrestore(struct sdhci_host *host,unsigned long flags)
-+{
-+ spin_unlock_irqrestore(&host->lock,flags);
-+}
-+
-+static void sdhci_spin_enable_schedule(struct sdhci_host *host)
-+{
-+}
-+
-+static void sdhci_spin_disable_schedule(struct sdhci_host *host)
-+{
-+}
-+
-+
-+#undef spin_lock_irqsave
-+#define spin_lock_irqsave(host_lock, flags) sdhci_spin_lock_irqsave(container_of(host_lock, struct sdhci_host, lock), &flags)
-+#define spin_unlock_irqrestore(host_lock, flags) sdhci_spin_unlock_irqrestore(container_of(host_lock, struct sdhci_host, lock), flags)
-+
-+#define spin_lock(host_lock) sdhci_spin_lock(container_of(host_lock, struct sdhci_host, lock))
-+#define spin_unlock(host_lock) sdhci_spin_unlock(container_of(host_lock, struct sdhci_host, lock))
-
- static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
- {
-@@ -300,7 +337,7 @@
- struct sdhci_host *host = container_of(led, struct sdhci_host, led);
- unsigned long flags;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- if (host->runtime_suspended)
- goto out;
-@@ -310,7 +347,7 @@
- else
- sdhci_activate_led(host);
- out:
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
- #endif
-
-@@ -327,7 +364,7 @@
- u32 uninitialized_var(scratch);
- u8 *buf;
-
-- DBG("PIO reading\n");
-+ DBG("PIO reading %db\n", host->data->blksz);
-
- blksize = host->data->blksz;
- chunk = 0;
-@@ -372,7 +409,7 @@
- u32 scratch;
- u8 *buf;
-
-- DBG("PIO writing\n");
-+ DBG("PIO writing %db\n", host->data->blksz);
-
- blksize = host->data->blksz;
- chunk = 0;
-@@ -411,19 +448,28 @@
- local_irq_restore(flags);
- }
-
--static void sdhci_transfer_pio(struct sdhci_host *host)
-+static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate)
- {
- u32 mask;
-+ u32 state = 0;
-+ u32 intmask;
-+ int available;
-
- BUG_ON(!host->data);
-
- if (host->blocks == 0)
- return;
-
-- if (host->data->flags & MMC_DATA_READ)
-+ if (host->data->flags & MMC_DATA_READ) {
- mask = SDHCI_DATA_AVAILABLE;
-- else
-+ intmask = SDHCI_INT_DATA_AVAIL;
-+ } else {
- mask = SDHCI_SPACE_AVAILABLE;
-+ intmask = SDHCI_INT_SPACE_AVAIL;
-+ }
-+
-+ /* initially we can see whether we can procede using intstate */
-+ available = (intstate & intmask);
-
- /*
- * Some controllers (JMicron JMB38x) mess up the buffer bits
-@@ -434,7 +480,7 @@
- (host->data->blocks == 1))
- mask = ~0;
-
-- while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+ while (available) {
- if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
- udelay(100);
-
-@@ -446,9 +492,12 @@
- host->blocks--;
- if (host->blocks == 0)
- break;
-+ state = sdhci_readl(host, SDHCI_PRESENT_STATE);
-+ available = state & mask;
-+ break;
- }
-
-- DBG("PIO transfer complete.\n");
-+ DBG("PIO transfer complete - %d blocks left.\n", host->blocks);
- }
-
- static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
-@@ -721,7 +770,9 @@
- u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
- u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
-
-- if (host->flags & SDHCI_REQ_USE_DMA)
-+ /* platform DMA will begin on receipt of PIO irqs */
-+ if ((host->flags & SDHCI_REQ_USE_DMA) &&
-+ !(host->flags & SDHCI_USE_PLATDMA))
- sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
- else
- sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
-@@ -753,44 +804,25 @@
- host->data_early = 0;
- host->data->bytes_xfered = 0;
-
-- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
-+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA))
- host->flags |= SDHCI_REQ_USE_DMA;
-
- /*
- * FIXME: This doesn't account for merging when mapping the
- * scatterlist.
- */
-- if (host->flags & SDHCI_REQ_USE_DMA) {
-- int broken, i;
-- struct scatterlist *sg;
--
-- broken = 0;
-- if (host->flags & SDHCI_USE_ADMA) {
-- if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
-- broken = 1;
-- } else {
-- if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
-- broken = 1;
-- }
--
-- if (unlikely(broken)) {
-- for_each_sg(data->sg, sg, data->sg_len, i) {
-- if (sg->length & 0x3) {
-- DBG("Reverting to PIO because of "
-- "transfer size (%d)\n",
-- sg->length);
-- host->flags &= ~SDHCI_REQ_USE_DMA;
-- break;
-- }
-- }
-- }
-- }
-
- /*
- * The assumption here being that alignment is the same after
- * translation to device address space.
- */
-- if (host->flags & SDHCI_REQ_USE_DMA) {
-+ if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) ==
-+ (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) {
-+
-+ if (! sdhci_platdma_dmaable(host, data))
-+ host->flags &= ~SDHCI_REQ_USE_DMA;
-+
-+ } else if (host->flags & SDHCI_REQ_USE_DMA) {
- int broken, i;
- struct scatterlist *sg;
-
-@@ -849,7 +881,8 @@
- */
- WARN_ON(1);
- host->flags &= ~SDHCI_REQ_USE_DMA;
-- } else {
-+ } else
-+ if (!(host->flags & SDHCI_USE_PLATDMA)) {
- WARN_ON(sg_cnt != 1);
- sdhci_writel(host, sg_dma_address(data->sg),
- SDHCI_DMA_ADDRESS);
-@@ -865,11 +898,13 @@
- if (host->version >= SDHCI_SPEC_200) {
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl &= ~SDHCI_CTRL_DMA_MASK;
-+ if (! (host->flags & SDHCI_USE_PLATDMA)) {
- if ((host->flags & SDHCI_REQ_USE_DMA) &&
- (host->flags & SDHCI_USE_ADMA))
- ctrl |= SDHCI_CTRL_ADMA32;
- else
- ctrl |= SDHCI_CTRL_SDMA;
-+ }
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
- }
-
-@@ -921,7 +956,8 @@
-
- if (data->flags & MMC_DATA_READ)
- mode |= SDHCI_TRNS_READ;
-- if (host->flags & SDHCI_REQ_USE_DMA)
-+ if ((host->flags & SDHCI_REQ_USE_DMA) &&
-+ !(host->flags & SDHCI_USE_PLATDMA))
- mode |= SDHCI_TRNS_DMA;
-
- sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
-@@ -937,13 +973,16 @@
- host->data = NULL;
-
- if (host->flags & SDHCI_REQ_USE_DMA) {
-- if (host->flags & SDHCI_USE_ADMA)
-- sdhci_adma_table_post(host, data);
-- else {
-+ /* we may have to abandon an ongoing platform DMA */
-+ if (host->flags & SDHCI_USE_PLATDMA)
-+ sdhci_platdma_reset(host, data);
-+
-+ if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) {
- dma_unmap_sg(mmc_dev(host->mmc), data->sg,
- data->sg_len, (data->flags & MMC_DATA_READ) ?
- DMA_FROM_DEVICE : DMA_TO_DEVICE);
-- }
-+ } else if (host->flags & SDHCI_USE_ADMA)
-+ sdhci_adma_table_post(host, data);
- }
-
- /*
-@@ -996,6 +1035,12 @@
- if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
- mask |= SDHCI_DATA_INHIBIT;
-
-+ if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) {
-+ timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller
-+ // which might cause the STATUS command to get stuck when a data operation is in flow
-+ mask |= SDHCI_DATA_INHIBIT;
-+ }
-+
- /* We shouldn't wait for data inihibit for stop commands, even
- though they might use busy signaling */
- if (host->mrq->data && (cmd == host->mrq->data->stop))
-@@ -1011,12 +1056,20 @@
- return;
- }
- timeout--;
-+ sdhci_spin_enable_schedule(host);
- mdelay(1);
-+ sdhci_spin_disable_schedule(host);
- }
-+ DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask,
-+ sdhci_readl(host, SDHCI_INT_STATUS));
-
- mod_timer(&host->timer, jiffies + 10 * HZ);
-
- host->cmd = cmd;
-+ if (host->last_cmdop == MMC_APP_CMD)
-+ host->last_cmdop = -cmd->opcode;
-+ else
-+ host->last_cmdop = cmd->opcode;
-
- sdhci_prepare_data(host, cmd);
-
-@@ -1232,7 +1285,9 @@
- return;
- }
- timeout--;
-+ sdhci_spin_enable_schedule(host);
- mdelay(1);
-+ sdhci_spin_disable_schedule(host);
- }
-
- clk |= SDHCI_CLOCK_CARD_EN;
-@@ -1333,9 +1388,7 @@
-
- sdhci_runtime_pm_get(host);
-
-- present = mmc_gpio_get_cd(host->mmc);
--
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- WARN_ON(host->mrq != NULL);
-
-@@ -1363,6 +1416,7 @@
- * zero: cd-gpio is used, and card is removed
- * one: cd-gpio is used, and card is present
- */
-+ present = mmc_gpio_get_cd(host->mmc);
- if (present < 0) {
- /* If polling, assume that the card is always present. */
- if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
-@@ -1392,9 +1446,9 @@
- mmc->card->type == MMC_TYPE_MMC ?
- MMC_SEND_TUNING_BLOCK_HS200 :
- MMC_SEND_TUNING_BLOCK;
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- sdhci_execute_tuning(mmc, tuning_opcode);
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- /* Restore original mmc_request structure */
- host->mrq = mrq;
-@@ -1408,7 +1462,7 @@
- }
-
- mmiowb();
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
-@@ -1417,10 +1471,10 @@
- int vdd_bit = -1;
- u8 ctrl;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- if (host->flags & SDHCI_DEVICE_DEAD) {
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
- mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
- return;
-@@ -1447,9 +1501,9 @@
- vdd_bit = sdhci_set_power(host, ios->vdd);
-
- if (host->vmmc && vdd_bit != -1) {
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
- }
-
- if (host->ops->platform_send_init_74_clocks)
-@@ -1586,7 +1640,7 @@
- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
-
- mmiowb();
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-@@ -1634,7 +1688,7 @@
- unsigned long flags;
- int is_readonly;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- if (host->flags & SDHCI_DEVICE_DEAD)
- is_readonly = 0;
-@@ -1644,7 +1698,7 @@
- is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
- & SDHCI_WRITE_PROTECT);
-
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
-
- /* This quirk needs to be replaced by a callback-function later */
- return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
-@@ -1717,9 +1771,9 @@
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
- sdhci_enable_sdio_irq_nolock(host, enable);
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
-@@ -2062,18 +2116,15 @@
- {
- struct sdhci_host *host = mmc_priv(mmc);
- unsigned long flags;
-- int present;
-
- /* First check if client has provided their own card event */
- if (host->ops->card_event)
- host->ops->card_event(host);
-
-- present = sdhci_do_get_cd(host);
--
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- /* Check host->mrq first in case we are runtime suspended */
-- if (host->mrq && !present) {
-+ if (host->mrq && !sdhci_do_get_cd(host)) {
- pr_err("%s: Card removed during transfer!\n",
- mmc_hostname(host->mmc));
- pr_err("%s: Resetting controller.\n",
-@@ -2086,7 +2137,7 @@
- tasklet_schedule(&host->finish_tasklet);
- }
-
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- static const struct mmc_host_ops sdhci_ops = {
-@@ -2125,14 +2176,14 @@
-
- host = (struct sdhci_host*)param;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- /*
- * If this tasklet gets rescheduled while running, it will
- * be run again afterwards but without any active request.
- */
- if (!host->mrq) {
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- return;
- }
-
-@@ -2170,7 +2221,7 @@
- #endif
-
- mmiowb();
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
-
- mmc_request_done(host->mmc, mrq);
- sdhci_runtime_pm_put(host);
-@@ -2183,11 +2234,11 @@
-
- host = (struct sdhci_host*)data;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- if (host->mrq) {
- pr_err("%s: Timeout waiting for hardware "
-- "interrupt.\n", mmc_hostname(host->mmc));
-+ "interrupt - cmd%d.\n", mmc_hostname(host->mmc), host->last_cmdop);
- sdhci_dumpregs(host);
-
- if (host->data) {
-@@ -2204,7 +2255,7 @@
- }
-
- mmiowb();
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- static void sdhci_tuning_timer(unsigned long data)
-@@ -2214,11 +2265,11 @@
-
- host = (struct sdhci_host *)data;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- host->flags |= SDHCI_NEEDS_RETUNING;
-
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- /*****************************************************************************\
-@@ -2232,10 +2283,13 @@
- BUG_ON(intmask == 0);
-
- if (!host->cmd) {
-+ if (!(host->ops->extra_ints)) {
- pr_err("%s: Got command interrupt 0x%08x even "
- "though no command operation was in progress.\n",
- mmc_hostname(host->mmc), (unsigned)intmask);
- sdhci_dumpregs(host);
-+ } else
-+ DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask);
- return;
- }
-
-@@ -2305,6 +2359,19 @@
- static void sdhci_show_adma_error(struct sdhci_host *host) { }
- #endif
-
-+static void sdhci_data_end(struct sdhci_host *host)
-+{
-+ if (host->cmd) {
-+ /*
-+ * Data managed to finish before the
-+ * command completed. Make sure we do
-+ * things in the proper order.
-+ */
-+ host->data_early = 1;
-+ } else
-+ sdhci_finish_data(host);
-+}
-+
- static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
- {
- u32 command;
-@@ -2334,23 +2401,39 @@
- }
- }
-
-+ if (!(host->ops->extra_ints)) {
- pr_err("%s: Got data interrupt 0x%08x even "
- "though no data operation was in progress.\n",
- mmc_hostname(host->mmc), (unsigned)intmask);
- sdhci_dumpregs(host);
-+ } else
-+ DBG("data irq 0x%08x but no data\n", (unsigned)intmask);
-
- return;
- }
-
- if (intmask & SDHCI_INT_DATA_TIMEOUT)
- host->data->error = -ETIMEDOUT;
-- else if (intmask & SDHCI_INT_DATA_END_BIT)
-+ else if (intmask & SDHCI_INT_DATA_END_BIT) {
-+ DBG("end error in cmd %d\n", host->last_cmdop);
-+ if (host->ops->spurious_crc_acmd51 &&
-+ host->last_cmdop == -SD_APP_SEND_SCR) {
-+ DBG("ignoring spurious data_end_bit error\n");
-+ intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
-+ } else
- host->data->error = -EILSEQ;
-- else if ((intmask & SDHCI_INT_DATA_CRC) &&
-+ } else if ((intmask & SDHCI_INT_DATA_CRC) &&
- SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
-- != MMC_BUS_TEST_R)
-+ != MMC_BUS_TEST_R) {
-+ DBG("crc error in cmd %d\n", host->last_cmdop);
-+ if (host->ops->spurious_crc_acmd51 &&
-+ host->last_cmdop == -SD_APP_SEND_SCR) {
-+ DBG("ignoring spurious data_crc_bit error\n");
-+ intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
-+ } else {
- host->data->error = -EILSEQ;
-- else if (intmask & SDHCI_INT_ADMA_ERROR) {
-+ }
-+ } else if (intmask & SDHCI_INT_ADMA_ERROR) {
- pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
- sdhci_show_adma_error(host);
- host->data->error = -EIO;
-@@ -2358,11 +2441,18 @@
- host->ops->adma_workaround(host, intmask);
- }
-
-- if (host->data->error)
-+ if (host->data->error) {
-+ DBG("finish request early on error %d\n", host->data->error);
- sdhci_finish_data(host);
-- else {
-- if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
-- sdhci_transfer_pio(host);
-+ } else {
-+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
-+ if (host->flags & SDHCI_REQ_USE_DMA) {
-+ /* possible only in PLATDMA mode */
-+ sdhci_platdma_avail(host, &intmask,
-+ &sdhci_data_end);
-+ } else
-+ sdhci_transfer_pio(host, intmask);
-+ }
-
- /*
- * We currently don't do anything fancy with DMA
-@@ -2391,18 +2481,8 @@
- sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
- }
-
-- if (intmask & SDHCI_INT_DATA_END) {
-- if (host->cmd) {
-- /*
-- * Data managed to finish before the
-- * command completed. Make sure we do
-- * things in the proper order.
-- */
-- host->data_early = 1;
-- } else {
-- sdhci_finish_data(host);
-- }
-- }
-+ if (intmask & SDHCI_INT_DATA_END)
-+ sdhci_data_end(host);
- }
- }
-
-@@ -2413,10 +2493,10 @@
- u32 intmask, unexpected = 0;
- int cardint = 0, max_loops = 16;
-
-- spin_lock(&host->lock);
-+ sdhci_spin_lock(host);
-
- if (host->runtime_suspended) {
-- spin_unlock(&host->lock);
-+ sdhci_spin_unlock(host);
- pr_warning("%s: got irq while runtime suspended\n",
- mmc_hostname(host->mmc));
- return IRQ_HANDLED;
-@@ -2458,6 +2538,22 @@
- tasklet_schedule(&host->card_tasklet);
- }
-
-+ if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR)
-+ DBG("controller reports error 0x%x -"
-+ "%s%s%s%s%s%s%s%s%s%s",
-+ intmask,
-+ intmask & SDHCI_INT_TIMEOUT? " timeout": "",
-+ intmask & SDHCI_INT_CRC ? " crc": "",
-+ intmask & SDHCI_INT_END_BIT? " endbit": "",
-+ intmask & SDHCI_INT_INDEX? " index": "",
-+ intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "",
-+ intmask & SDHCI_INT_DATA_CRC? " data_crc": "",
-+ intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "",
-+ intmask & SDHCI_INT_BUS_POWER? " buspower": "",
-+ intmask & SDHCI_INT_ACMD12ERR? " acmd12": "",
-+ intmask & SDHCI_INT_ADMA_ERROR? " adma": ""
-+ );
-+
- if (intmask & SDHCI_INT_CMD_MASK) {
- sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
- SDHCI_INT_STATUS);
-@@ -2472,7 +2568,13 @@
-
- intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
-
-- intmask &= ~SDHCI_INT_ERROR;
-+ if (intmask & SDHCI_INT_ERROR_MASK) {
-+ /* collect any uncovered errors */
-+ sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK,
-+ SDHCI_INT_STATUS);
-+ }
-+
-+ intmask &= ~SDHCI_INT_ERROR_MASK;
-
- if (intmask & SDHCI_INT_BUS_POWER) {
- pr_err("%s: Card is consuming too much power!\n",
-@@ -2498,7 +2600,7 @@
- if (intmask && --max_loops)
- goto again;
- out:
-- spin_unlock(&host->lock);
-+ sdhci_spin_unlock(host);
-
- if (unexpected) {
- pr_err("%s: Unexpected interrupt 0x%08x.\n",
-@@ -2508,7 +2610,7 @@
- /*
- * We have to delay this as it calls back into the driver.
- */
-- if (cardint && host->mmc->sdio_irqs)
-+ if (cardint)
- mmc_signal_sdio_irq(host->mmc);
-
- return result;
-@@ -2592,13 +2694,14 @@
- {
- int ret;
-
-- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
-+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
-+ SDHCI_USE_PLATDMA)) {
- if (host->ops->enable_dma)
- host->ops->enable_dma(host);
- }
-
- if (!device_may_wakeup(mmc_dev(host->mmc))) {
-- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
-+ ret = request_irq(host->irq, sdhci_irq, 0 /*IRQF_SHARED*/,
- mmc_hostname(host->mmc), host);
- if (ret)
- return ret;
-@@ -2675,15 +2778,15 @@
- host->flags &= ~SDHCI_NEEDS_RETUNING;
- }
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
-
- synchronize_irq(host->irq);
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
- host->runtime_suspended = true;
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
-
- return ret;
- }
-@@ -2709,16 +2812,16 @@
- sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
- if ((host_flags & SDHCI_PV_ENABLED) &&
- !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
- sdhci_enable_preset_value(host, true);
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- /* Set the re-tuning expiration flag */
- if (host->flags & SDHCI_USING_RETUNING_TIMER)
- host->flags |= SDHCI_NEEDS_RETUNING;
-
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- host->runtime_suspended = false;
-
-@@ -2729,7 +2832,7 @@
- /* Enable Card Detection */
- sdhci_enable_card_detection(host);
-
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
-
- return ret;
- }
-@@ -2824,14 +2927,16 @@
- host->flags &= ~SDHCI_USE_ADMA;
- }
-
-- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
-+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
-+ SDHCI_USE_PLATDMA)) {
- if (host->ops->enable_dma) {
- if (host->ops->enable_dma(host)) {
- pr_warning("%s: No suitable DMA "
- "available. Falling back to PIO.\n",
- mmc_hostname(mmc));
- host->flags &=
-- ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
-+ ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA |
-+ SDHCI_USE_PLATDMA);
- }
- }
- }
-@@ -3006,13 +3111,11 @@
- /* SD3.0: SDR104 is supported so (for eMMC) the caps2
- * field can be promoted to support HS200.
- */
-- if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
-- mmc->caps2 |= MMC_CAP2_HS200;
-+ mmc->caps2 |= MMC_CAP2_HS200;
- } else if (caps[1] & SDHCI_SUPPORT_SDR50)
- mmc->caps |= MMC_CAP_UHS_SDR50;
-
-- if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
-- !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
-+ if (caps[1] & SDHCI_SUPPORT_DDR50)
- mmc->caps |= MMC_CAP_UHS_DDR50;
-
- /* Does the host need tuning for SDR50? */
-@@ -3224,8 +3327,8 @@
-
- sdhci_init(host, 0);
-
-- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
-- mmc_hostname(mmc), host);
-+ ret = request_irq(host->irq, sdhci_irq, 0 /*IRQF_SHARED*/,
-+ mmc_hostname(mmc), host);
- if (ret) {
- pr_err("%s: Failed to request IRQ %d: %d\n",
- mmc_hostname(mmc), host->irq, ret);
-@@ -3258,6 +3361,7 @@
-
- pr_info("%s: SDHCI controller on %s [%s] using %s\n",
- mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
-+ (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" :
- (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
- (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
-
-@@ -3285,7 +3389,7 @@
- unsigned long flags;
-
- if (dead) {
-- spin_lock_irqsave(&host->lock, flags);
-+ sdhci_spin_lock_irqsave(host, &flags);
-
- host->flags |= SDHCI_DEVICE_DEAD;
-
-@@ -3297,7 +3401,7 @@
- tasklet_schedule(&host->finish_tasklet);
- }
-
-- spin_unlock_irqrestore(&host->lock, flags);
-+ sdhci_spin_unlock_irqrestore(host, flags);
- }
-
- sdhci_disable_card_detection(host);
-diff -Nur linux-3.12.38/drivers/mmc/host/sdhci.h linux-rpi/drivers/mmc/host/sdhci.h
---- linux-3.12.38/drivers/mmc/host/sdhci.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/sdhci.h 2015-03-10 17:26:50.562216692 +0100
-@@ -289,6 +289,18 @@
- void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
- void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
- int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
-+
-+ int (*pdma_able)(struct sdhci_host *host,
-+ struct mmc_data *data);
-+ void (*pdma_avail)(struct sdhci_host *host,
-+ unsigned int *ref_intmask,
-+ void(*complete)(struct sdhci_host *));
-+ void (*pdma_reset)(struct sdhci_host *host,
-+ struct mmc_data *data);
-+ unsigned int (*extra_ints)(struct sdhci_host *host);
-+ unsigned int (*spurious_crc_acmd51)(struct sdhci_host *host);
-+ unsigned int (*missing_status)(struct sdhci_host *host);
-+
- void (*hw_reset)(struct sdhci_host *host);
- void (*platform_suspend)(struct sdhci_host *host);
- void (*platform_resume)(struct sdhci_host *host);
-@@ -400,9 +412,38 @@
- extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
- #endif
-
-+static inline int /*bool*/
-+sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
-+{
-+ if (host->ops->pdma_able)
-+ return host->ops->pdma_able(host, data);
-+ else
-+ return 1;
-+}
-+static inline void
-+sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
-+ void(*completion_callback)(struct sdhci_host *))
-+{
-+ if (host->ops->pdma_avail)
-+ host->ops->pdma_avail(host, ref_intmask, completion_callback);
-+}
-+
-+static inline void
-+sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
-+{
-+ if (host->ops->pdma_reset)
-+ host->ops->pdma_reset(host, data);
-+}
-+
- #ifdef CONFIG_PM_RUNTIME
- extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
- extern int sdhci_runtime_resume_host(struct sdhci_host *host);
- #endif
-
-+extern void sdhci_spin_lock_irqsave(struct sdhci_host *host,unsigned long *flags);
-+extern void sdhci_spin_unlock_irqrestore(struct sdhci_host *host,unsigned long flags);
-+extern void sdhci_spin_lock(struct sdhci_host *host);
-+extern void sdhci_spin_unlock(struct sdhci_host *host);
-+
-+
- #endif /* __SDHCI_HW_H */
-diff -Nur linux-3.12.38/drivers/mmc/host/sdhci-pci.c linux-rpi/drivers/mmc/host/sdhci-pci.c
---- linux-3.12.38/drivers/mmc/host/sdhci-pci.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/sdhci-pci.c 2015-03-10 17:26:50.562216692 +0100
-@@ -27,7 +27,81 @@
- #include <linux/mmc/sdhci-pci-data.h>
-
- #include "sdhci.h"
--#include "sdhci-pci.h"
-+
-+/*
-+ * PCI device IDs
-+ */
-+#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
-+#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
-+#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
-+#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
-+#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
-+#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
-+#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
-+#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
-+#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
-+#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
-+#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
-+#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
-+#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
-+
-+/*
-+ * PCI registers
-+ */
-+
-+#define PCI_SDHCI_IFPIO 0x00
-+#define PCI_SDHCI_IFDMA 0x01
-+#define PCI_SDHCI_IFVENDOR 0x02
-+
-+#define PCI_SLOT_INFO 0x40 /* 8 bits */
-+#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
-+#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
-+
-+#define MAX_SLOTS 8
-+
-+struct sdhci_pci_chip;
-+struct sdhci_pci_slot;
-+
-+struct sdhci_pci_fixes {
-+ unsigned int quirks;
-+ unsigned int quirks2;
-+ bool allow_runtime_pm;
-+ bool own_cd_for_runtime_pm;
-+
-+ int (*probe) (struct sdhci_pci_chip *);
-+
-+ int (*probe_slot) (struct sdhci_pci_slot *);
-+ void (*remove_slot) (struct sdhci_pci_slot *, int);
-+
-+ int (*suspend) (struct sdhci_pci_chip *);
-+ int (*resume) (struct sdhci_pci_chip *);
-+};
-+
-+struct sdhci_pci_slot {
-+ struct sdhci_pci_chip *chip;
-+ struct sdhci_host *host;
-+ struct sdhci_pci_data *data;
-+
-+ int pci_bar;
-+ int rst_n_gpio;
-+ int cd_gpio;
-+ int cd_irq;
-+
-+ void (*hw_reset)(struct sdhci_host *host);
-+};
-+
-+struct sdhci_pci_chip {
-+ struct pci_dev *pdev;
-+
-+ unsigned int quirks;
-+ unsigned int quirks2;
-+ bool allow_runtime_pm;
-+ const struct sdhci_pci_fixes *fixes;
-+
-+ int num_slots; /* Slots on controller */
-+ struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
-+};
-+
-
- /*****************************************************************************\
- * *
-@@ -270,8 +344,6 @@
- MMC_CAP_HW_RESET;
- slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
- slot->hw_reset = sdhci_pci_int_hw_reset;
-- if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
-- slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
- return 0;
- }
-
-@@ -284,7 +356,6 @@
- static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
- .allow_runtime_pm = true,
- .probe_slot = byt_emmc_probe_slot,
-- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
- };
-
- static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
-@@ -318,7 +389,6 @@
-
- static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
- .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
-- .quirks2 = SDHCI_QUIRK2_BROKEN_HS200,
- .probe_slot = intel_mrfl_mmc_probe_slot,
- };
-
-@@ -672,18 +742,6 @@
- .probe = via_probe,
- };
-
--static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
--{
-- slot->host->mmc->caps2 |= MMC_CAP2_HS200;
-- return 0;
--}
--
--static const struct sdhci_pci_fixes sdhci_rtsx = {
-- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
-- SDHCI_QUIRK2_BROKEN_DDR50,
-- .probe_slot = rtsx_probe_slot,
--};
--
- static const struct pci_device_id pci_ids[] = {
- {
- .vendor = PCI_VENDOR_ID_RICOH,
-@@ -806,14 +864,6 @@
- },
-
- {
-- .vendor = PCI_VENDOR_ID_REALTEK,
-- .device = 0x5250,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_rtsx,
-- },
--
-- {
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_QRK_SD,
- .subvendor = PCI_ANY_ID,
-@@ -933,29 +983,6 @@
- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
- },
-
-- {
-- .vendor = PCI_VENDOR_ID_INTEL,
-- .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
-- },
--
-- {
-- .vendor = PCI_VENDOR_ID_INTEL,
-- .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
-- },
--
-- {
-- .vendor = PCI_VENDOR_ID_INTEL,
-- .device = PCI_DEVICE_ID_INTEL_BSW_SD,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
-- },
-
- {
- .vendor = PCI_VENDOR_ID_INTEL,
-@@ -1004,31 +1031,6 @@
- .subdevice = PCI_ANY_ID,
- .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
- },
--
-- {
-- .vendor = PCI_VENDOR_ID_INTEL,
-- .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
-- },
--
-- {
-- .vendor = PCI_VENDOR_ID_INTEL,
-- .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
-- },
--
-- {
-- .vendor = PCI_VENDOR_ID_INTEL,
-- .device = PCI_DEVICE_ID_INTEL_SPT_SD,
-- .subvendor = PCI_ANY_ID,
-- .subdevice = PCI_ANY_ID,
-- .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
-- },
--
- {
- .vendor = PCI_VENDOR_ID_O2,
- .device = PCI_DEVICE_ID_O2_8120,
-diff -Nur linux-3.12.38/drivers/mmc/host/sdhci-pci.h linux-rpi/drivers/mmc/host/sdhci-pci.h
---- linux-3.12.38/drivers/mmc/host/sdhci-pci.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mmc/host/sdhci-pci.h 1970-01-01 01:00:00.000000000 +0100
-@@ -1,85 +0,0 @@
--#ifndef __SDHCI_PCI_H
--#define __SDHCI_PCI_H
--
--/*
-- * PCI device IDs
-- */
--
--#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
--#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
--#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
--#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
--#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
--#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
--#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
--#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
--#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
--#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
--#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
--#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
--#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
--#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
--#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
--#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
--#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
--#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
--#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
--
--/*
-- * PCI registers
-- */
--
--#define PCI_SDHCI_IFPIO 0x00
--#define PCI_SDHCI_IFDMA 0x01
--#define PCI_SDHCI_IFVENDOR 0x02
--
--#define PCI_SLOT_INFO 0x40 /* 8 bits */
--#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
--#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
--
--#define MAX_SLOTS 8
--
--struct sdhci_pci_chip;
--struct sdhci_pci_slot;
--
--struct sdhci_pci_fixes {
-- unsigned int quirks;
-- unsigned int quirks2;
-- bool allow_runtime_pm;
-- bool own_cd_for_runtime_pm;
--
-- int (*probe) (struct sdhci_pci_chip *);
--
-- int (*probe_slot) (struct sdhci_pci_slot *);
-- void (*remove_slot) (struct sdhci_pci_slot *, int);
--
-- int (*suspend) (struct sdhci_pci_chip *);
-- int (*resume) (struct sdhci_pci_chip *);
--};
--
--struct sdhci_pci_slot {
-- struct sdhci_pci_chip *chip;
-- struct sdhci_host *host;
-- struct sdhci_pci_data *data;
--
-- int pci_bar;
-- int rst_n_gpio;
-- int cd_gpio;
-- int cd_irq;
--
-- void (*hw_reset)(struct sdhci_host *host);
--};
--
--struct sdhci_pci_chip {
-- struct pci_dev *pdev;
--
-- unsigned int quirks;
-- unsigned int quirks2;
-- bool allow_runtime_pm;
-- const struct sdhci_pci_fixes *fixes;
--
-- int num_slots; /* Slots on controller */
-- struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
--};
--
--#endif /* __SDHCI_PCI_H */
-diff -Nur linux-3.12.38/drivers/mtd/tests/torturetest.c linux-rpi/drivers/mtd/tests/torturetest.c
---- linux-3.12.38/drivers/mtd/tests/torturetest.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mtd/tests/torturetest.c 2015-03-10 17:26:50.582216692 +0100
-@@ -264,9 +264,7 @@
- int i;
- void *patt;
-
-- err = mtdtest_erase_good_eraseblocks(mtd, bad_ebs, eb, ebcnt);
-- if (err)
-- goto out;
-+ mtdtest_erase_good_eraseblocks(mtd, bad_ebs, eb, ebcnt);
-
- /* Check if the eraseblocks contain only 0xFF bytes */
- if (check) {
-diff -Nur linux-3.12.38/drivers/mtd/ubi/upd.c linux-rpi/drivers/mtd/ubi/upd.c
---- linux-3.12.38/drivers/mtd/ubi/upd.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mtd/ubi/upd.c 2015-03-10 17:26:50.582216692 +0100
-@@ -133,10 +133,6 @@
- ubi_assert(!vol->updating && !vol->changing_leb);
- vol->updating = 1;
-
-- vol->upd_buf = vmalloc(ubi->leb_size);
-- if (!vol->upd_buf)
-- return -ENOMEM;
--
- err = set_update_marker(ubi, vol);
- if (err)
- return err;
-@@ -156,12 +152,14 @@
- err = clear_update_marker(ubi, vol, 0);
- if (err)
- return err;
--
-- vfree(vol->upd_buf);
- vol->updating = 0;
- return 0;
- }
-
-+ vol->upd_buf = vmalloc(ubi->leb_size);
-+ if (!vol->upd_buf)
-+ return -ENOMEM;
-+
- vol->upd_ebs = div_u64(bytes + vol->usable_leb_size - 1,
- vol->usable_leb_size);
- vol->upd_bytes = bytes;
-diff -Nur linux-3.12.38/drivers/mtd/ubi/wl.c linux-rpi/drivers/mtd/ubi/wl.c
---- linux-3.12.38/drivers/mtd/ubi/wl.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/mtd/ubi/wl.c 2015-03-10 17:26:50.582216692 +0100
-@@ -1209,6 +1209,7 @@
-
- err = do_sync_erase(ubi, e1, vol_id, lnum, 0);
- if (err) {
-+ kmem_cache_free(ubi_wl_entry_slab, e1);
- if (e2)
- kmem_cache_free(ubi_wl_entry_slab, e2);
- goto out_ro;
-@@ -1222,8 +1223,10 @@
- dbg_wl("PEB %d (LEB %d:%d) was put meanwhile, erase",
- e2->pnum, vol_id, lnum);
- err = do_sync_erase(ubi, e2, vol_id, lnum, 0);
-- if (err)
-+ if (err) {
-+ kmem_cache_free(ubi_wl_entry_slab, e2);
- goto out_ro;
-+ }
- }
-
- dbg_wl("done");
-@@ -1259,9 +1262,10 @@
-
- ubi_free_vid_hdr(ubi, vid_hdr);
- err = do_sync_erase(ubi, e2, vol_id, lnum, torture);
-- if (err)
-+ if (err) {
-+ kmem_cache_free(ubi_wl_entry_slab, e2);
- goto out_ro;
--
-+ }
- mutex_unlock(&ubi->move_mutex);
- return 0;
-
-diff -Nur linux-3.12.38/drivers/net/can/dev.c linux-rpi/drivers/net/can/dev.c
---- linux-3.12.38/drivers/net/can/dev.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/can/dev.c 2015-03-10 17:26:50.586216692 +0100
-@@ -643,14 +643,10 @@
- if (dev->flags & IFF_UP)
- return -EBUSY;
- cm = nla_data(data[IFLA_CAN_CTRLMODE]);
--
-- /* check whether changed bits are allowed to be modified */
-- if (cm->mask & ~priv->ctrlmode_supported)
-+ if (cm->flags & ~priv->ctrlmode_supported)
- return -EOPNOTSUPP;
--
-- /* clear bits to be modified and copy the flag values */
- priv->ctrlmode &= ~cm->mask;
-- priv->ctrlmode |= (cm->flags & cm->mask);
-+ priv->ctrlmode |= cm->flags;
- }
-
- if (data[IFLA_CAN_BITTIMING]) {
-diff -Nur linux-3.12.38/drivers/net/can/usb/kvaser_usb.c linux-rpi/drivers/net/can/usb/kvaser_usb.c
---- linux-3.12.38/drivers/net/can/usb/kvaser_usb.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/can/usb/kvaser_usb.c 2015-03-10 17:26:50.590216692 +0100
-@@ -579,7 +579,7 @@
- usb_sndbulkpipe(dev->udev,
- dev->bulk_out->bEndpointAddress),
- buf, msg->len,
-- kvaser_usb_simple_msg_callback, netdev);
-+ kvaser_usb_simple_msg_callback, priv);
- usb_anchor_urb(urb, &priv->tx_submitted);
-
- err = usb_submit_urb(urb, GFP_ATOMIC);
-@@ -654,6 +654,11 @@
- priv = dev->nets[channel];
- stats = &priv->netdev->stats;
-
-+ if (status & M16C_STATE_BUS_RESET) {
-+ kvaser_usb_unlink_tx_urbs(priv);
-+ return;
-+ }
-+
- skb = alloc_can_err_skb(priv->netdev, &cf);
- if (!skb) {
- stats->rx_dropped++;
-@@ -664,7 +669,7 @@
-
- netdev_dbg(priv->netdev, "Error status: 0x%02x\n", status);
-
-- if (status & (M16C_STATE_BUS_OFF | M16C_STATE_BUS_RESET)) {
-+ if (status & M16C_STATE_BUS_OFF) {
- cf->can_id |= CAN_ERR_BUSOFF;
-
- priv->can.can_stats.bus_off++;
-@@ -690,7 +695,9 @@
- }
-
- new_state = CAN_STATE_ERROR_PASSIVE;
-- } else if (status & M16C_STATE_BUS_ERROR) {
-+ }
-+
-+ if (status == M16C_STATE_BUS_ERROR) {
- if ((priv->can.state < CAN_STATE_ERROR_WARNING) &&
- ((txerr >= 96) || (rxerr >= 96))) {
- cf->can_id |= CAN_ERR_CRTL;
-@@ -700,8 +707,7 @@
-
- priv->can.can_stats.error_warning++;
- new_state = CAN_STATE_ERROR_WARNING;
-- } else if ((priv->can.state > CAN_STATE_ERROR_ACTIVE) &&
-- ((txerr < 96) && (rxerr < 96))) {
-+ } else if (priv->can.state > CAN_STATE_ERROR_ACTIVE) {
- cf->can_id |= CAN_ERR_PROT;
- cf->data[2] = CAN_ERR_PROT_ACTIVE;
-
-@@ -1232,9 +1238,6 @@
- if (err)
- netdev_warn(netdev, "Cannot stop device, error %d\n", err);
-
-- /* reset tx contexts */
-- kvaser_usb_unlink_tx_urbs(priv);
--
- priv->can.state = CAN_STATE_STOPPED;
- close_candev(priv->netdev);
-
-@@ -1283,14 +1286,12 @@
- if (!urb) {
- netdev_err(netdev, "No memory left for URBs\n");
- stats->tx_dropped++;
-- dev_kfree_skb(skb);
-- return NETDEV_TX_OK;
-+ goto nourbmem;
- }
-
- buf = kmalloc(sizeof(struct kvaser_msg), GFP_ATOMIC);
- if (!buf) {
- stats->tx_dropped++;
-- dev_kfree_skb(skb);
- goto nobufmem;
- }
-
-@@ -1325,7 +1326,6 @@
- }
- }
-
-- /* This should never happen; it implies a flow control bug */
- if (!context) {
- netdev_warn(netdev, "cannot find free context\n");
- ret = NETDEV_TX_BUSY;
-@@ -1356,6 +1356,9 @@
- if (unlikely(err)) {
- can_free_echo_skb(netdev, context->echo_index);
-
-+ skb = NULL; /* set to NULL to avoid double free in
-+ * dev_kfree_skb(skb) */
-+
- atomic_dec(&priv->active_tx_urbs);
- usb_unanchor_urb(urb);
-
-@@ -1377,6 +1380,8 @@
- kfree(buf);
- nobufmem:
- usb_free_urb(urb);
-+nourbmem:
-+ dev_kfree_skb(skb);
- return ret;
- }
-
-@@ -1488,10 +1493,6 @@
- struct kvaser_usb_net_priv *priv;
- int i, err;
-
-- err = kvaser_usb_send_simple_msg(dev, CMD_RESET_CHIP, channel);
-- if (err)
-- return err;
--
- netdev = alloc_candev(sizeof(*priv), MAX_TX_URBS);
- if (!netdev) {
- dev_err(&intf->dev, "Cannot alloc candev\n");
-@@ -1577,7 +1578,7 @@
- {
- struct kvaser_usb *dev;
- int err = -ENOMEM;
-- int i, retry = 3;
-+ int i;
-
- dev = devm_kzalloc(&intf->dev, sizeof(*dev), GFP_KERNEL);
- if (!dev)
-@@ -1595,15 +1596,10 @@
-
- usb_set_intfdata(intf, dev);
-
-- /* On some x86 laptops, plugging a Kvaser device again after
-- * an unplug makes the firmware always ignore the very first
-- * command. For such a case, provide some room for retries
-- * instead of completely exiting the driver.
-- */
-- do {
-- err = kvaser_usb_get_software_info(dev);
-- } while (--retry && err == -ETIMEDOUT);
-+ for (i = 0; i < MAX_NET_DEVICES; i++)
-+ kvaser_usb_send_simple_msg(dev, CMD_RESET_CHIP, i);
-
-+ err = kvaser_usb_get_software_info(dev);
- if (err) {
- dev_err(&intf->dev,
- "Cannot get software infos, error %d\n", err);
-diff -Nur linux-3.12.38/drivers/net/can/usb/peak_usb/pcan_usb_core.c linux-rpi/drivers/net/can/usb/peak_usb/pcan_usb_core.c
---- linux-3.12.38/drivers/net/can/usb/peak_usb/pcan_usb_core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/can/usb/peak_usb/pcan_usb_core.c 2015-03-10 17:26:50.590216692 +0100
-@@ -734,7 +734,7 @@
- dev->cmd_buf = kmalloc(PCAN_USB_MAX_CMD_LEN, GFP_KERNEL);
- if (!dev->cmd_buf) {
- err = -ENOMEM;
-- goto lbl_free_candev;
-+ goto lbl_set_intf_data;
- }
-
- dev->udev = usb_dev;
-@@ -773,7 +773,7 @@
- err = register_candev(netdev);
- if (err) {
- dev_err(&intf->dev, "couldn't register CAN device: %d\n", err);
-- goto lbl_restore_intf_data;
-+ goto lbl_free_cmd_buf;
- }
-
- if (dev->prev_siblings)
-@@ -786,14 +786,14 @@
- if (dev->adapter->dev_init) {
- err = dev->adapter->dev_init(dev);
- if (err)
-- goto lbl_unregister_candev;
-+ goto lbl_free_cmd_buf;
- }
-
- /* set bus off */
- if (dev->adapter->dev_set_bus) {
- err = dev->adapter->dev_set_bus(dev, 0);
- if (err)
-- goto lbl_unregister_candev;
-+ goto lbl_free_cmd_buf;
- }
-
- /* get device number early */
-@@ -805,14 +805,11 @@
-
- return 0;
-
--lbl_unregister_candev:
-- unregister_candev(netdev);
--
--lbl_restore_intf_data:
-- usb_set_intfdata(intf, dev->prev_siblings);
-+lbl_free_cmd_buf:
- kfree(dev->cmd_buf);
-
--lbl_free_candev:
-+lbl_set_intf_data:
-+ usb_set_intfdata(intf, dev->prev_siblings);
- free_candev(netdev);
-
- return err;
-diff -Nur linux-3.12.38/drivers/net/can/usb/peak_usb/pcan_usb_pro.c linux-rpi/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
---- linux-3.12.38/drivers/net/can/usb/peak_usb/pcan_usb_pro.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/can/usb/peak_usb/pcan_usb_pro.c 2015-03-10 17:26:50.590216692 +0100
-@@ -333,6 +333,8 @@
- if (!(dev->state & PCAN_USB_STATE_CONNECTED))
- return 0;
-
-+ memset(req_addr, '\0', req_size);
-+
- req_type = USB_TYPE_VENDOR | USB_RECIP_OTHER;
-
- switch (req_id) {
-@@ -343,7 +345,6 @@
- default:
- p = usb_rcvctrlpipe(dev->udev, 0);
- req_type |= USB_DIR_IN;
-- memset(req_addr, '\0', req_size);
- break;
- }
-
-diff -Nur linux-3.12.38/drivers/net/ethernet/atheros/alx/main.c linux-rpi/drivers/net/ethernet/atheros/alx/main.c
---- linux-3.12.38/drivers/net/ethernet/atheros/alx/main.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/atheros/alx/main.c 2015-03-10 17:26:50.602216692 +0100
-@@ -184,16 +184,15 @@
- schedule_work(&alx->reset_wk);
- }
-
--static int alx_clean_rx_irq(struct alx_priv *alx, int budget)
-+static bool alx_clean_rx_irq(struct alx_priv *alx, int budget)
- {
- struct alx_rx_queue *rxq = &alx->rxq;
- struct alx_rrd *rrd;
- struct alx_buffer *rxb;
- struct sk_buff *skb;
- u16 length, rfd_cleaned = 0;
-- int work = 0;
-
-- while (work < budget) {
-+ while (budget > 0) {
- rrd = &rxq->rrd[rxq->rrd_read_idx];
- if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
- break;
-@@ -204,7 +203,7 @@
- ALX_GET_FIELD(le32_to_cpu(rrd->word0),
- RRD_NOR) != 1) {
- alx_schedule_reset(alx);
-- return work;
-+ return 0;
- }
-
- rxb = &rxq->bufs[rxq->read_idx];
-@@ -244,7 +243,7 @@
- }
-
- napi_gro_receive(&alx->napi, skb);
-- work++;
-+ budget--;
-
- next_pkt:
- if (++rxq->read_idx == alx->rx_ringsz)
-@@ -259,22 +258,21 @@
- if (rfd_cleaned)
- alx_refill_rx_ring(alx, GFP_ATOMIC);
-
-- return work;
-+ return budget > 0;
- }
-
- static int alx_poll(struct napi_struct *napi, int budget)
- {
- struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
- struct alx_hw *hw = &alx->hw;
-+ bool complete = true;
- unsigned long flags;
-- bool tx_complete;
-- int work;
-
-- tx_complete = alx_clean_tx_irq(alx);
-- work = alx_clean_rx_irq(alx, budget);
-+ complete = alx_clean_tx_irq(alx) &&
-+ alx_clean_rx_irq(alx, budget);
-
-- if (!tx_complete || work == budget)
-- return budget;
-+ if (!complete)
-+ return 1;
-
- napi_complete(&alx->napi);
-
-@@ -286,7 +284,7 @@
-
- alx_post_write(hw);
-
-- return work;
-+ return 0;
- }
-
- static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
-diff -Nur linux-3.12.38/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c linux-rpi/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
---- linux-3.12.38/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c 2015-03-10 17:26:50.606216692 +0100
-@@ -3087,7 +3087,7 @@
- }
- #endif
- if (!bnx2x_fp_lock_napi(fp))
-- return budget;
-+ return work_done;
-
- for_each_cos_in_tx_queue(fp, cos)
- if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
-diff -Nur linux-3.12.38/drivers/net/ethernet/broadcom/tg3.c linux-rpi/drivers/net/ethernet/broadcom/tg3.c
---- linux-3.12.38/drivers/net/ethernet/broadcom/tg3.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/broadcom/tg3.c 2015-03-10 17:26:50.622216692 +0100
-@@ -17572,6 +17572,23 @@
- goto err_out_apeunmap;
- }
-
-+ /*
-+ * Reset chip in case UNDI or EFI driver did not shutdown
-+ * DMA self test will enable WDMAC and we'll see (spurious)
-+ * pending DMA on the PCI bus at that point.
-+ */
-+ if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
-+ (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
-+ tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
-+ tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
-+ }
-+
-+ err = tg3_test_dma(tp);
-+ if (err) {
-+ dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
-+ goto err_out_apeunmap;
-+ }
-+
- intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
- rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
- sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
-@@ -17616,23 +17633,6 @@
- sndmbx += 0xc;
- }
-
-- /*
-- * Reset chip in case UNDI or EFI driver did not shutdown
-- * DMA self test will enable WDMAC and we'll see (spurious)
-- * pending DMA on the PCI bus at that point.
-- */
-- if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
-- (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
-- tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
-- tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
-- }
--
-- err = tg3_test_dma(tp);
-- if (err) {
-- dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
-- goto err_out_apeunmap;
-- }
--
- tg3_init_coal(tp);
-
- pci_set_drvdata(pdev, dev);
-diff -Nur linux-3.12.38/drivers/net/ethernet/cisco/enic/enic_main.c linux-rpi/drivers/net/ethernet/cisco/enic/enic_main.c
---- linux-3.12.38/drivers/net/ethernet/cisco/enic/enic_main.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/cisco/enic/enic_main.c 2015-03-10 17:26:50.634216691 +0100
-@@ -1043,14 +1043,10 @@
- skb->l4_rxhash = true;
- }
-
-- /* Hardware does not provide whole packet checksum. It only
-- * provides pseudo checksum. Since hw validates the packet
-- * checksum but not provide us the checksum value. use
-- * CHECSUM_UNNECESSARY.
-- */
-- if ((netdev->features & NETIF_F_RXCSUM) && tcp_udp_csum_ok &&
-- ipv4_csum_ok)
-- skb->ip_summed = CHECKSUM_UNNECESSARY;
-+ if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) {
-+ skb->csum = htons(checksum);
-+ skb->ip_summed = CHECKSUM_COMPLETE;
-+ }
-
- if (vlan_stripped)
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci);
-diff -Nur linux-3.12.38/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c linux-rpi/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
---- linux-3.12.38/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c 2015-03-10 17:26:50.690216691 +0100
-@@ -2366,10 +2366,7 @@
-
- work_done = netxen_process_rcv_ring(sds_ring, budget);
-
-- if (!tx_complete)
-- work_done = budget;
--
-- if (work_done < budget) {
-+ if ((work_done < budget) && tx_complete) {
- napi_complete(&sds_ring->napi);
- if (test_bit(__NX_DEV_UP, &adapter->state))
- netxen_nic_enable_int(sds_ring);
-diff -Nur linux-3.12.38/drivers/net/ethernet/ti/cpsw_ale.c linux-rpi/drivers/net/ethernet/ti/cpsw_ale.c
---- linux-3.12.38/drivers/net/ethernet/ti/cpsw_ale.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/ti/cpsw_ale.c 2015-03-10 17:26:50.714216691 +0100
-@@ -236,7 +236,7 @@
- cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
- }
-
--int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
-+int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask)
- {
- u32 ale_entry[ALE_ENTRY_WORDS];
- int ret, idx;
-@@ -247,14 +247,6 @@
- if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
- continue;
-
-- /* if vid passed is -1 then remove all multicast entry from
-- * the table irrespective of vlan id, if a valid vlan id is
-- * passed then remove only multicast added to that vlan id.
-- * if vlan id doesn't match then move on to next entry.
-- */
-- if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
-- continue;
--
- if (cpsw_ale_get_mcast(ale_entry)) {
- u8 addr[6];
-
-diff -Nur linux-3.12.38/drivers/net/ethernet/ti/cpsw_ale.h linux-rpi/drivers/net/ethernet/ti/cpsw_ale.h
---- linux-3.12.38/drivers/net/ethernet/ti/cpsw_ale.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/ti/cpsw_ale.h 2015-03-10 17:26:50.714216691 +0100
-@@ -86,7 +86,7 @@
-
- int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout);
- int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask);
--int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid);
-+int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask);
- int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port,
- int flags, u16 vid);
- int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port,
-diff -Nur linux-3.12.38/drivers/net/ethernet/ti/cpsw.c linux-rpi/drivers/net/ethernet/ti/cpsw.c
---- linux-3.12.38/drivers/net/ethernet/ti/cpsw.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ethernet/ti/cpsw.c 2015-03-10 17:26:50.714216691 +0100
-@@ -546,12 +546,6 @@
- static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
- {
- struct cpsw_priv *priv = netdev_priv(ndev);
-- int vid;
--
-- if (priv->data.dual_emac)
-- vid = priv->slaves[priv->emac_port].port_vlan;
-- else
-- vid = priv->data.default_vlan;
-
- if (ndev->flags & IFF_PROMISC) {
- /* Enable promiscuous mode */
-@@ -560,8 +554,7 @@
- }
-
- /* Clear all mcast from ALE */
-- cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
-- vid);
-+ cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
-
- if (!netdev_mc_empty(ndev)) {
- struct netdev_hw_addr *ha;
-@@ -646,14 +639,6 @@
- static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
- {
- struct cpsw_priv *priv = dev_id;
-- int value = irq - priv->irqs_table[0];
--
-- /* NOTICE: Ending IRQ here. The trick with the 'value' variable above
-- * is to make sure we will always write the correct value to the EOI
-- * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
-- * for TX Interrupt and 3 for MISC Interrupt.
-- */
-- cpdma_ctlr_eoi(priv->dma, value);
-
- cpsw_intr_disable(priv);
- if (priv->irq_enabled == true) {
-@@ -683,6 +668,8 @@
- int num_tx, num_rx;
-
- num_tx = cpdma_chan_process(priv->txch, 128);
-+ if (num_tx)
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
-
- num_rx = cpdma_chan_process(priv->rxch, budget);
- if (num_rx < budget) {
-@@ -690,6 +677,7 @@
-
- napi_complete(napi);
- cpsw_intr_enable(priv);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
- prim_cpsw = cpsw_get_slave_priv(priv, 0);
- if (prim_cpsw->irq_enabled == false) {
- prim_cpsw->irq_enabled = true;
-@@ -1177,6 +1165,8 @@
- napi_enable(&priv->napi);
- cpdma_ctlr_start(priv->dma);
- cpsw_intr_enable(priv);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
-
- if (priv->data.dual_emac)
- priv->slaves[priv->emac_port].open_stat = true;
-@@ -1426,6 +1416,9 @@
- cpdma_chan_start(priv->txch);
- cpdma_ctlr_int_ctrl(priv->dma, true);
- cpsw_intr_enable(priv);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
-+
- }
-
- static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
-@@ -1471,6 +1464,9 @@
- cpsw_interrupt(ndev->irq, priv);
- cpdma_ctlr_int_ctrl(priv->dma, true);
- cpsw_intr_enable(priv);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
-+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
-+
- }
- #endif
-
-@@ -1514,19 +1510,6 @@
- if (vid == priv->data.default_vlan)
- return 0;
-
-- if (priv->data.dual_emac) {
-- /* In dual EMAC, reserved VLAN id should not be used for
-- * creating VLAN interfaces as this can break the dual
-- * EMAC port separation
-- */
-- int i;
--
-- for (i = 0; i < priv->data.slaves; i++) {
-- if (vid == priv->slaves[i].port_vlan)
-- return -EINVAL;
-- }
-- }
--
- dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
- return cpsw_add_vlan_ale_entry(priv, vid);
- }
-@@ -1540,15 +1523,6 @@
- if (vid == priv->data.default_vlan)
- return 0;
-
-- if (priv->data.dual_emac) {
-- int i;
--
-- for (i = 0; i < priv->data.slaves; i++) {
-- if (vid == priv->slaves[i].port_vlan)
-- return -EINVAL;
-- }
-- }
--
- dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
- ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
- if (ret != 0)
-diff -Nur linux-3.12.38/drivers/net/ppp/ppp_deflate.c linux-rpi/drivers/net/ppp/ppp_deflate.c
---- linux-3.12.38/drivers/net/ppp/ppp_deflate.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/ppp/ppp_deflate.c 2015-03-10 17:26:50.734216691 +0100
-@@ -246,7 +246,7 @@
- /*
- * See if we managed to reduce the size of the packet.
- */
-- if (olen < isize && olen <= osize) {
-+ if (olen < isize) {
- state->stats.comp_bytes += olen;
- state->stats.comp_packets++;
- } else {
-diff -Nur linux-3.12.38/drivers/net/team/team.c linux-rpi/drivers/net/team/team.c
---- linux-3.12.38/drivers/net/team/team.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/team/team.c 2015-03-10 17:26:50.734216691 +0100
-@@ -629,7 +629,6 @@
- static void team_notify_peers_work(struct work_struct *work)
- {
- struct team *team;
-- int val;
-
- team = container_of(work, struct team, notify_peers.dw.work);
-
-@@ -637,14 +636,9 @@
- schedule_delayed_work(&team->notify_peers.dw, 0);
- return;
- }
-- val = atomic_dec_if_positive(&team->notify_peers.count_pending);
-- if (val < 0) {
-- rtnl_unlock();
-- return;
-- }
- call_netdevice_notifiers(NETDEV_NOTIFY_PEERS, team->dev);
- rtnl_unlock();
-- if (val)
-+ if (!atomic_dec_and_test(&team->notify_peers.count_pending))
- schedule_delayed_work(&team->notify_peers.dw,
- msecs_to_jiffies(team->notify_peers.interval));
- }
-@@ -675,7 +669,6 @@
- static void team_mcast_rejoin_work(struct work_struct *work)
- {
- struct team *team;
-- int val;
-
- team = container_of(work, struct team, mcast_rejoin.dw.work);
-
-@@ -683,14 +676,9 @@
- schedule_delayed_work(&team->mcast_rejoin.dw, 0);
- return;
- }
-- val = atomic_dec_if_positive(&team->mcast_rejoin.count_pending);
-- if (val < 0) {
-- rtnl_unlock();
-- return;
-- }
- call_netdevice_notifiers(NETDEV_RESEND_IGMP, team->dev);
- rtnl_unlock();
-- if (val)
-+ if (!atomic_dec_and_test(&team->mcast_rejoin.count_pending))
- schedule_delayed_work(&team->mcast_rejoin.dw,
- msecs_to_jiffies(team->mcast_rejoin.interval));
- }
-diff -Nur linux-3.12.38/drivers/net/usb/smsc95xx.c linux-rpi/drivers/net/usb/smsc95xx.c
---- linux-3.12.38/drivers/net/usb/smsc95xx.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/usb/smsc95xx.c 2015-03-10 17:26:50.738216691 +0100
-@@ -61,6 +61,7 @@
- #define SUSPEND_SUSPEND3 (0x08)
- #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
- SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
-+#define MAC_ADDR_LEN (6)
-
- struct smsc95xx_priv {
- u32 mac_cr;
-@@ -76,6 +77,10 @@
- module_param(turbo_mode, bool, 0644);
- MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
-
-+static char *macaddr = ":";
-+module_param(macaddr, charp, 0);
-+MODULE_PARM_DESC(macaddr, "MAC address");
-+
- static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
- u32 *data, int in_pm)
- {
-@@ -765,8 +770,59 @@
- return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
- }
-
-+/* Check the macaddr module parameter for a MAC address */
-+static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac)
-+{
-+ int i, j, got_num, num;
-+ u8 mtbl[MAC_ADDR_LEN];
-+
-+ if (macaddr[0] == ':')
-+ return 0;
-+
-+ i = 0;
-+ j = 0;
-+ num = 0;
-+ got_num = 0;
-+ while (j < MAC_ADDR_LEN) {
-+ if (macaddr[i] && macaddr[i] != ':') {
-+ got_num++;
-+ if ('0' <= macaddr[i] && macaddr[i] <= '9')
-+ num = num * 16 + macaddr[i] - '0';
-+ else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
-+ num = num * 16 + 10 + macaddr[i] - 'A';
-+ else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
-+ num = num * 16 + 10 + macaddr[i] - 'a';
-+ else
-+ break;
-+ i++;
-+ } else if (got_num == 2) {
-+ mtbl[j++] = (u8) num;
-+ num = 0;
-+ got_num = 0;
-+ i++;
-+ } else {
-+ break;
-+ }
-+ }
-+
-+ if (j == MAC_ADDR_LEN) {
-+ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: "
-+ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2],
-+ mtbl[3], mtbl[4], mtbl[5]);
-+ for (i = 0; i < MAC_ADDR_LEN; i++)
-+ dev_mac[i] = mtbl[i];
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+}
-+
- static void smsc95xx_init_mac_address(struct usbnet *dev)
- {
-+ /* Check module parameters */
-+ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr))
-+ return;
-+
- /* try reading mac address from EEPROM */
- if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
- dev->net->dev_addr) == 0) {
-diff -Nur linux-3.12.38/drivers/net/wireless/ath/ath5k/qcu.c linux-rpi/drivers/net/wireless/ath/ath5k/qcu.c
---- linux-3.12.38/drivers/net/wireless/ath/ath5k/qcu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/wireless/ath/ath5k/qcu.c 2015-03-10 17:26:50.754216691 +0100
-@@ -225,7 +225,13 @@
- } else {
- switch (queue_type) {
- case AR5K_TX_QUEUE_DATA:
-- queue = queue_info->tqi_subtype;
-+ for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
-+ ah->ah_txq[queue].tqi_type !=
-+ AR5K_TX_QUEUE_INACTIVE; queue++) {
-+
-+ if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
-+ return -EINVAL;
-+ }
- break;
- case AR5K_TX_QUEUE_UAPSD:
- queue = AR5K_TX_QUEUE_ID_UAPSD;
-diff -Nur linux-3.12.38/drivers/net/wireless/ath/ath9k/hw.h linux-rpi/drivers/net/wireless/ath/ath9k/hw.h
---- linux-3.12.38/drivers/net/wireless/ath/ath9k/hw.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/wireless/ath/ath9k/hw.h 2015-03-10 17:26:50.766216691 +0100
-@@ -215,8 +215,8 @@
- #define AH_WOW_BEACON_MISS BIT(3)
-
- enum ath_hw_txq_subtype {
-- ATH_TXQ_AC_BK = 0,
-- ATH_TXQ_AC_BE = 1,
-+ ATH_TXQ_AC_BE = 0,
-+ ATH_TXQ_AC_BK = 1,
- ATH_TXQ_AC_VI = 2,
- ATH_TXQ_AC_VO = 3,
- };
-diff -Nur linux-3.12.38/drivers/net/wireless/ath/ath9k/mac.c linux-rpi/drivers/net/wireless/ath/ath9k/mac.c
---- linux-3.12.38/drivers/net/wireless/ath/ath9k/mac.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/net/wireless/ath/ath9k/mac.c 2015-03-10 17:26:50.766216691 +0100
-@@ -311,7 +311,14 @@
- q = ATH9K_NUM_TX_QUEUES - 3;
- break;
- case ATH9K_TX_QUEUE_DATA:
-- q = qinfo->tqi_subtype;
-+ for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
-+ if (ah->txq[q].tqi_type ==
-+ ATH9K_TX_QUEUE_INACTIVE)
-+ break;
-+ if (q == ATH9K_NUM_TX_QUEUES) {
-+ ath_err(common, "No available TX queue\n");
-+ return -1;
-+ }
- break;
- default:
- ath_err(common, "Invalid TX queue type: %u\n", type);
-diff -Nur linux-3.12.38/drivers/parport/parport_pc.c linux-rpi/drivers/parport/parport_pc.c
---- linux-3.12.38/drivers/parport/parport_pc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/parport/parport_pc.c 2015-03-10 17:26:50.866216690 +0100
-@@ -3312,14 +3312,13 @@
- while (!list_empty(&ports_list)) {
- struct parport_pc_private *priv;
- struct parport *port;
-- struct device *dev;
- priv = list_entry(ports_list.next,
- struct parport_pc_private, list);
- port = priv->port;
-- dev = port->dev;
-+ if (port->dev && port->dev->bus == &platform_bus_type)
-+ platform_device_unregister(
-+ to_platform_device(port->dev));
- parport_pc_unregister_port(port);
-- if (dev && dev->bus == &platform_bus_type)
-- platform_device_unregister(to_platform_device(dev));
- }
- }
-
-diff -Nur linux-3.12.38/drivers/pci/probe.c linux-rpi/drivers/pci/probe.c
---- linux-3.12.38/drivers/pci/probe.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/pci/probe.c 2015-03-10 17:26:50.878216690 +0100
-@@ -214,17 +214,14 @@
- res->flags |= IORESOURCE_SIZEALIGN;
- if (res->flags & IORESOURCE_IO) {
- l &= PCI_BASE_ADDRESS_IO_MASK;
-- sz &= PCI_BASE_ADDRESS_IO_MASK;
- mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
- } else {
- l &= PCI_BASE_ADDRESS_MEM_MASK;
-- sz &= PCI_BASE_ADDRESS_MEM_MASK;
- mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
- }
- } else {
- res->flags |= (l & IORESOURCE_ROM_ENABLE);
- l &= PCI_ROM_ADDRESS_MASK;
-- sz &= PCI_ROM_ADDRESS_MASK;
- mask = (u32)PCI_ROM_ADDRESS_MASK;
- }
-
-diff -Nur linux-3.12.38/drivers/pinctrl/core.c linux-rpi/drivers/pinctrl/core.c
---- linux-3.12.38/drivers/pinctrl/core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/pinctrl/core.c 2015-03-10 17:26:50.878216690 +0100
-@@ -1796,15 +1796,14 @@
- if (pctldev == NULL)
- return;
-
-+ mutex_lock(&pinctrldev_list_mutex);
- mutex_lock(&pctldev->mutex);
-+
- pinctrl_remove_device_debugfs(pctldev);
-- mutex_unlock(&pctldev->mutex);
-
- if (!IS_ERR(pctldev->p))
- pinctrl_put(pctldev->p);
-
-- mutex_lock(&pinctrldev_list_mutex);
-- mutex_lock(&pctldev->mutex);
- /* TODO: check that no pinmuxes are still active? */
- list_del(&pctldev->node);
- /* Destroy descriptor tree */
-diff -Nur linux-3.12.38/drivers/platform/x86/asus-nb-wmi.c linux-rpi/drivers/platform/x86/asus-nb-wmi.c
---- linux-3.12.38/drivers/platform/x86/asus-nb-wmi.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/platform/x86/asus-nb-wmi.c 2015-03-10 17:26:50.898216690 +0100
-@@ -70,14 +70,10 @@
- .no_display_toggle = true,
- };
-
--static struct quirk_entry quirk_asus_wapf4 = {
-+static struct quirk_entry quirk_asus_x401u = {
- .wapf = 4,
- };
-
--static struct quirk_entry quirk_asus_x200ca = {
-- .wapf = 2,
--};
--
- static int dmi_matched(const struct dmi_system_id *dmi)
- {
- quirks = dmi->driver_data;
-@@ -87,20 +83,6 @@
- static struct dmi_system_id asus_quirks[] = {
- {
- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. U32U",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "U32U"),
-- },
-- /*
-- * Note this machine has a Brazos APU, and most Brazos Asus
-- * machines need quirk_asus_x55u / wmi_backlight_power but
-- * here acpi-video seems to work fine for backlight control.
-- */
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
- .ident = "ASUSTeK COMPUTER INC. X401U",
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-@@ -115,7 +97,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X401A"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -124,7 +106,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X401A1"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -142,7 +124,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X501A"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -151,52 +133,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X501A1"),
- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X550CA",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X550CA"),
-- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X550CC",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X550CC"),
-- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X550CL",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X550CL"),
-- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X550VB",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X550VB"),
-- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X551CA",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X551CA"),
-- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -205,7 +142,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X55A"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -214,7 +151,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X55C"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -232,7 +169,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X55VD"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -241,16 +178,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "X75A"),
- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X75VBP",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X75VBP"),
-- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -259,7 +187,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "1015E"),
- },
-- .driver_data = &quirk_asus_wapf4,
-+ .driver_data = &quirk_asus_x401u,
- },
- {
- .callback = dmi_matched,
-@@ -268,16 +196,7 @@
- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
- DMI_MATCH(DMI_PRODUCT_NAME, "1015U"),
- },
-- .driver_data = &quirk_asus_wapf4,
-- },
-- {
-- .callback = dmi_matched,
-- .ident = "ASUSTeK COMPUTER INC. X200CA",
-- .matches = {
-- DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
-- DMI_MATCH(DMI_PRODUCT_NAME, "X200CA"),
-- },
-- .driver_data = &quirk_asus_x200ca,
-+ .driver_data = &quirk_asus_x401u,
- },
- {},
- };
-diff -Nur linux-3.12.38/drivers/platform/x86/hp_accel.c linux-rpi/drivers/platform/x86/hp_accel.c
---- linux-3.12.38/drivers/platform/x86/hp_accel.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/platform/x86/hp_accel.c 2015-03-10 17:26:50.898216690 +0100
-@@ -237,7 +237,6 @@
- AXIS_DMI_MATCH("HPB64xx", "HP ProBook 64", xy_swap),
- AXIS_DMI_MATCH("HPB64xx", "HP EliteBook 84", xy_swap),
- AXIS_DMI_MATCH("HPB65xx", "HP ProBook 65", x_inverted),
-- AXIS_DMI_MATCH("HPZBook15", "HP ZBook 15", x_inverted),
- { NULL, }
- /* Laptop models without axis info (yet):
- * "NC6910" "HP Compaq 6910"
-diff -Nur linux-3.12.38/drivers/regulator/core.c linux-rpi/drivers/regulator/core.c
---- linux-3.12.38/drivers/regulator/core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/regulator/core.c 2015-03-10 17:26:50.910216690 +0100
-@@ -1474,7 +1474,7 @@
- }
- EXPORT_SYMBOL_GPL(devm_regulator_get_optional);
-
--/* regulator_list_mutex lock held by regulator_put() */
-+/* Locks held by regulator_put() */
- static void _regulator_put(struct regulator *regulator)
- {
- struct regulator_dev *rdev;
-@@ -1489,14 +1489,12 @@
- /* remove any sysfs entries */
- if (regulator->dev)
- sysfs_remove_link(&rdev->dev.kobj, regulator->supply_name);
-- mutex_lock(&rdev->mutex);
- kfree(regulator->supply_name);
- list_del(&regulator->list);
- kfree(regulator);
-
- rdev->open_count--;
- rdev->exclusive = 0;
-- mutex_unlock(&rdev->mutex);
-
- module_put(rdev->owner);
- }
-diff -Nur linux-3.12.38/drivers/rtc/rtc-sirfsoc.c linux-rpi/drivers/rtc/rtc-sirfsoc.c
---- linux-3.12.38/drivers/rtc/rtc-sirfsoc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/rtc/rtc-sirfsoc.c 2015-03-10 17:26:50.922216690 +0100
-@@ -290,6 +290,14 @@
- rtc_div = ((32768 / RTC_HZ) / 2) - 1;
- sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
-
-+ rtcdrv->rtc = rtc_device_register(pdev->name, &(pdev->dev),
-+ &sirfsoc_rtc_ops, THIS_MODULE);
-+ if (IS_ERR(rtcdrv->rtc)) {
-+ err = PTR_ERR(rtcdrv->rtc);
-+ dev_err(&pdev->dev, "can't register RTC device\n");
-+ return err;
-+ }
-+
- /* 0x3 -> RTC_CLK */
- sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
- rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
-@@ -304,14 +312,6 @@
- rtcdrv->overflow_rtc =
- sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
-
-- rtcdrv->rtc = rtc_device_register(pdev->name, &(pdev->dev),
-- &sirfsoc_rtc_ops, THIS_MODULE);
-- if (IS_ERR(rtcdrv->rtc)) {
-- err = PTR_ERR(rtcdrv->rtc);
-- dev_err(&pdev->dev, "can't register RTC device\n");
-- return err;
-- }
--
- rtcdrv->irq = platform_get_irq(pdev, 0);
- err = devm_request_irq(
- &pdev->dev,
-diff -Nur linux-3.12.38/drivers/s390/crypto/ap_bus.c linux-rpi/drivers/s390/crypto/ap_bus.c
---- linux-3.12.38/drivers/s390/crypto/ap_bus.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/s390/crypto/ap_bus.c 2015-03-10 17:26:50.930216690 +0100
-@@ -44,7 +44,6 @@
- #include <linux/hrtimer.h>
- #include <linux/ktime.h>
- #include <asm/facility.h>
--#include <linux/crypto.h>
-
- #include "ap_bus.h"
-
-@@ -72,7 +71,7 @@
- MODULE_DESCRIPTION("Adjunct Processor Bus driver, " \
- "Copyright IBM Corp. 2006, 2012");
- MODULE_LICENSE("GPL");
--MODULE_ALIAS_CRYPTO("z90crypt");
-+MODULE_ALIAS("z90crypt");
-
- /*
- * Module parameter
-diff -Nur linux-3.12.38/drivers/scsi/ipr.c linux-rpi/drivers/scsi/ipr.c
---- linux-3.12.38/drivers/scsi/ipr.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/ipr.c 2015-03-10 17:26:50.974216689 +0100
-@@ -683,7 +683,6 @@
- ipr_reinit_ipr_cmnd(ipr_cmd);
- ipr_cmd->u.scratch = 0;
- ipr_cmd->sibling = NULL;
-- ipr_cmd->eh_comp = NULL;
- ipr_cmd->fast_done = fast_done;
- init_timer(&ipr_cmd->timer);
- }
-@@ -849,8 +848,6 @@
-
- scsi_dma_unmap(ipr_cmd->scsi_cmd);
- scsi_cmd->scsi_done(scsi_cmd);
-- if (ipr_cmd->eh_comp)
-- complete(ipr_cmd->eh_comp);
- list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
- }
-
-@@ -4808,84 +4805,6 @@
- return rc;
- }
-
--/**
-- * ipr_match_lun - Match function for specified LUN
-- * @ipr_cmd: ipr command struct
-- * @device: device to match (sdev)
-- *
-- * Returns:
-- * 1 if command matches sdev / 0 if command does not match sdev
-- **/
--static int ipr_match_lun(struct ipr_cmnd *ipr_cmd, void *device)
--{
-- if (ipr_cmd->scsi_cmd && ipr_cmd->scsi_cmd->device == device)
-- return 1;
-- return 0;
--}
--
--/**
-- * ipr_wait_for_ops - Wait for matching commands to complete
-- * @ipr_cmd: ipr command struct
-- * @device: device to match (sdev)
-- * @match: match function to use
-- *
-- * Returns:
-- * SUCCESS / FAILED
-- **/
--static int ipr_wait_for_ops(struct ipr_ioa_cfg *ioa_cfg, void *device,
-- int (*match)(struct ipr_cmnd *, void *))
--{
-- struct ipr_cmnd *ipr_cmd;
-- int wait;
-- unsigned long flags;
-- struct ipr_hrr_queue *hrrq;
-- signed long timeout = IPR_ABORT_TASK_TIMEOUT;
-- DECLARE_COMPLETION_ONSTACK(comp);
--
-- ENTER;
-- do {
-- wait = 0;
--
-- for_each_hrrq(hrrq, ioa_cfg) {
-- spin_lock_irqsave(hrrq->lock, flags);
-- list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
-- if (match(ipr_cmd, device)) {
-- ipr_cmd->eh_comp = &comp;
-- wait++;
-- }
-- }
-- spin_unlock_irqrestore(hrrq->lock, flags);
-- }
--
-- if (wait) {
-- timeout = wait_for_completion_timeout(&comp, timeout);
--
-- if (!timeout) {
-- wait = 0;
--
-- for_each_hrrq(hrrq, ioa_cfg) {
-- spin_lock_irqsave(hrrq->lock, flags);
-- list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
-- if (match(ipr_cmd, device)) {
-- ipr_cmd->eh_comp = NULL;
-- wait++;
-- }
-- }
-- spin_unlock_irqrestore(hrrq->lock, flags);
-- }
--
-- if (wait)
-- dev_err(&ioa_cfg->pdev->dev, "Timed out waiting for aborted commands\n");
-- LEAVE;
-- return wait ? FAILED : SUCCESS;
-- }
-- }
-- } while (wait);
--
-- LEAVE;
-- return SUCCESS;
--}
--
- static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
- {
- struct ipr_ioa_cfg *ioa_cfg;
-@@ -5104,17 +5023,11 @@
- static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
- {
- int rc;
-- struct ipr_ioa_cfg *ioa_cfg;
--
-- ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
-
- spin_lock_irq(cmd->device->host->host_lock);
- rc = __ipr_eh_dev_reset(cmd);
- spin_unlock_irq(cmd->device->host->host_lock);
-
-- if (rc == SUCCESS)
-- rc = ipr_wait_for_ops(ioa_cfg, cmd->device, ipr_match_lun);
--
- return rc;
- }
-
-@@ -5292,18 +5205,13 @@
- {
- unsigned long flags;
- int rc;
-- struct ipr_ioa_cfg *ioa_cfg;
-
- ENTER;
-
-- ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
--
- spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
- rc = ipr_cancel_op(scsi_cmd);
- spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
-
-- if (rc == SUCCESS)
-- rc = ipr_wait_for_ops(ioa_cfg, scsi_cmd->device, ipr_match_lun);
- LEAVE;
- return rc;
- }
-diff -Nur linux-3.12.38/drivers/scsi/ipr.h linux-rpi/drivers/scsi/ipr.h
---- linux-3.12.38/drivers/scsi/ipr.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/ipr.h 2015-03-10 17:26:50.974216689 +0100
-@@ -1588,7 +1588,6 @@
- struct scsi_device *sdev;
- } u;
-
-- struct completion *eh_comp;
- struct ipr_hrr_queue *hrrq;
- struct ipr_ioa_cfg *ioa_cfg;
- };
-diff -Nur linux-3.12.38/drivers/scsi/mpt2sas/mpt2sas_transport.c linux-rpi/drivers/scsi/mpt2sas/mpt2sas_transport.c
---- linux-3.12.38/drivers/scsi/mpt2sas/mpt2sas_transport.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/mpt2sas/mpt2sas_transport.c 2015-03-10 17:26:50.994216689 +0100
-@@ -1006,9 +1006,12 @@
- &mpt2sas_phy->remote_identify);
- _transport_add_phy_to_an_existing_port(ioc, sas_node,
- mpt2sas_phy, mpt2sas_phy->remote_identify.sas_address);
-- } else
-+ } else {
- memset(&mpt2sas_phy->remote_identify, 0 , sizeof(struct
- sas_identify));
-+ _transport_del_phy_from_an_existing_port(ioc, sas_node,
-+ mpt2sas_phy);
-+ }
-
- if (mpt2sas_phy->phy)
- mpt2sas_phy->phy->negotiated_linkrate =
-diff -Nur linux-3.12.38/drivers/scsi/mpt3sas/mpt3sas_transport.c linux-rpi/drivers/scsi/mpt3sas/mpt3sas_transport.c
---- linux-3.12.38/drivers/scsi/mpt3sas/mpt3sas_transport.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/mpt3sas/mpt3sas_transport.c 2015-03-10 17:26:50.998216689 +0100
-@@ -1003,9 +1003,12 @@
- &mpt3sas_phy->remote_identify);
- _transport_add_phy_to_an_existing_port(ioc, sas_node,
- mpt3sas_phy, mpt3sas_phy->remote_identify.sas_address);
-- } else
-+ } else {
- memset(&mpt3sas_phy->remote_identify, 0 , sizeof(struct
- sas_identify));
-+ _transport_del_phy_from_an_existing_port(ioc, sas_node,
-+ mpt3sas_phy);
-+ }
-
- if (mpt3sas_phy->phy)
- mpt3sas_phy->phy->negotiated_linkrate =
-diff -Nur linux-3.12.38/drivers/scsi/scsi_devinfo.c linux-rpi/drivers/scsi/scsi_devinfo.c
---- linux-3.12.38/drivers/scsi/scsi_devinfo.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/scsi_devinfo.c 2015-03-10 17:26:51.018216689 +0100
-@@ -211,7 +211,6 @@
- {"Medion", "Flash XL MMC/SD", "2.6D", BLIST_FORCELUN},
- {"MegaRAID", "LD", NULL, BLIST_FORCELUN},
- {"MICROP", "4110", NULL, BLIST_NOTQ},
-- {"MSFT", "Virtual HD", NULL, BLIST_NO_RSOC},
- {"MYLEX", "DACARMRB", "*", BLIST_REPORTLUN2},
- {"nCipher", "Fastness Crypto", NULL, BLIST_FORCELUN},
- {"NAKAMICH", "MJ-4.8S", NULL, BLIST_FORCELUN | BLIST_SINGLELUN},
-diff -Nur linux-3.12.38/drivers/scsi/scsi_lib.c linux-rpi/drivers/scsi/scsi_lib.c
---- linux-3.12.38/drivers/scsi/scsi_lib.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/scsi_lib.c 2015-03-10 17:26:51.018216689 +0100
-@@ -831,14 +831,6 @@
- scsi_next_command(cmd);
- return;
- }
-- } else if (blk_rq_bytes(req) == 0 && result && !sense_deferred) {
-- /*
-- * Certain non BLOCK_PC requests are commands that don't
-- * actually transfer anything (FLUSH), so cannot use
-- * good_bytes != blk_rq_bytes(req) as the signal for an error.
-- * This sets the error explicitly for the problem case.
-- */
-- error = __scsi_error_from_host_byte(cmd, result);
- }
-
- /* no bidi support for !REQ_TYPE_BLOCK_PC yet */
-diff -Nur linux-3.12.38/drivers/scsi/storvsc_drv.c linux-rpi/drivers/scsi/storvsc_drv.c
---- linux-3.12.38/drivers/scsi/storvsc_drv.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/scsi/storvsc_drv.c 2015-03-10 17:26:51.022216689 +0100
-@@ -1690,12 +1690,13 @@
- if (ret == -EAGAIN) {
- /* no more space */
-
-- if (cmd_request->bounce_sgl_count)
-+ if (cmd_request->bounce_sgl_count) {
- destroy_bounce_buffer(cmd_request->bounce_sgl,
- cmd_request->bounce_sgl_count);
-
-- ret = SCSI_MLQUEUE_DEVICE_BUSY;
-- goto queue_error;
-+ ret = SCSI_MLQUEUE_DEVICE_BUSY;
-+ goto queue_error;
-+ }
- }
-
- return 0;
-diff -Nur linux-3.12.38/drivers/spi/Kconfig linux-rpi/drivers/spi/Kconfig
---- linux-3.12.38/drivers/spi/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/spi/Kconfig 2015-03-10 17:26:51.030216689 +0100
-@@ -85,6 +85,14 @@
- is for the regular SPI controller. Slave mode operation is not also
- not supported.
-
-+config SPI_BCM2708
-+ tristate "BCM2708 SPI controller driver (SPI0)"
-+ depends on MACH_BCM2708
-+ help
-+ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
-+ driver is not compatible with the "Universal SPI Master" or the SPI slave
-+ device.
-+
- config SPI_BFIN5XX
- tristate "SPI controller driver for ADI Blackfin5xx"
- depends on BLACKFIN && !BF60x
-diff -Nur linux-3.12.38/drivers/spi/Makefile linux-rpi/drivers/spi/Makefile
---- linux-3.12.38/drivers/spi/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/spi/Makefile 2015-03-10 17:26:51.030216689 +0100
-@@ -18,6 +18,7 @@
- obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
- obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
- obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o
-+obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o
- obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
- obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
- obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
-diff -Nur linux-3.12.38/drivers/spi/spi-bcm2708.c linux-rpi/drivers/spi/spi-bcm2708.c
---- linux-3.12.38/drivers/spi/spi-bcm2708.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/spi/spi-bcm2708.c 2015-03-10 17:26:51.030216689 +0100
-@@ -0,0 +1,626 @@
-+/*
-+ * Driver for Broadcom BCM2708 SPI Controllers
-+ *
-+ * Copyright (C) 2012 Chris Boot
-+ *
-+ * This driver is inspired by:
-+ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/spi/spi.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/log2.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+
-+/* SPI register offsets */
-+#define SPI_CS 0x00
-+#define SPI_FIFO 0x04
-+#define SPI_CLK 0x08
-+#define SPI_DLEN 0x0c
-+#define SPI_LTOH 0x10
-+#define SPI_DC 0x14
-+
-+/* Bitfields in CS */
-+#define SPI_CS_LEN_LONG 0x02000000
-+#define SPI_CS_DMA_LEN 0x01000000
-+#define SPI_CS_CSPOL2 0x00800000
-+#define SPI_CS_CSPOL1 0x00400000
-+#define SPI_CS_CSPOL0 0x00200000
-+#define SPI_CS_RXF 0x00100000
-+#define SPI_CS_RXR 0x00080000
-+#define SPI_CS_TXD 0x00040000
-+#define SPI_CS_RXD 0x00020000
-+#define SPI_CS_DONE 0x00010000
-+#define SPI_CS_LEN 0x00002000
-+#define SPI_CS_REN 0x00001000
-+#define SPI_CS_ADCS 0x00000800
-+#define SPI_CS_INTR 0x00000400
-+#define SPI_CS_INTD 0x00000200
-+#define SPI_CS_DMAEN 0x00000100
-+#define SPI_CS_TA 0x00000080
-+#define SPI_CS_CSPOL 0x00000040
-+#define SPI_CS_CLEAR_RX 0x00000020
-+#define SPI_CS_CLEAR_TX 0x00000010
-+#define SPI_CS_CPOL 0x00000008
-+#define SPI_CS_CPHA 0x00000004
-+#define SPI_CS_CS_10 0x00000002
-+#define SPI_CS_CS_01 0x00000001
-+
-+#define SPI_TIMEOUT_MS 150
-+
-+#define DRV_NAME "bcm2708_spi"
-+
-+struct bcm2708_spi {
-+ spinlock_t lock;
-+ void __iomem *base;
-+ int irq;
-+ struct clk *clk;
-+ bool stopping;
-+
-+ struct list_head queue;
-+ struct workqueue_struct *workq;
-+ struct work_struct work;
-+ struct completion done;
-+
-+ const u8 *tx_buf;
-+ u8 *rx_buf;
-+ int len;
-+};
-+
-+struct bcm2708_spi_state {
-+ u32 cs;
-+ u16 cdiv;
-+};
-+
-+/*
-+ * This function sets the ALT mode on the SPI pins so that we can use them with
-+ * the SPI hardware.
-+ *
-+ * FIXME: This is a hack. Use pinmux / pinctrl.
-+ */
-+static void bcm2708_init_pinmode(void)
-+{
-+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
-+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
-+
-+ int pin;
-+ u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
-+
-+ /* SPI is on GPIO 7..11 */
-+ for (pin = 7; pin <= 11; pin++) {
-+ INP_GPIO(pin); /* set mode to GPIO input first */
-+ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
-+ }
-+
-+ iounmap(gpio);
-+
-+#undef INP_GPIO
-+#undef SET_GPIO_ALT
-+}
-+
-+static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg)
-+{
-+ return readl(bs->base + reg);
-+}
-+
-+static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val)
-+{
-+ writel(val, bs->base + reg);
-+}
-+
-+static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len)
-+{
-+ u8 byte;
-+
-+ while (len--) {
-+ byte = bcm2708_rd(bs, SPI_FIFO);
-+ if (bs->rx_buf)
-+ *bs->rx_buf++ = byte;
-+ }
-+}
-+
-+static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len)
-+{
-+ u8 byte;
-+ u16 val;
-+
-+ if (len > bs->len)
-+ len = bs->len;
-+
-+ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) {
-+ /* LoSSI mode */
-+ if (unlikely(len % 2)) {
-+ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n");
-+ bs->len = 0;
-+ return;
-+ }
-+ while (len) {
-+ if (bs->tx_buf) {
-+ val = *(const u16 *)bs->tx_buf;
-+ bs->tx_buf += 2;
-+ } else
-+ val = 0;
-+ bcm2708_wr(bs, SPI_FIFO, val);
-+ bs->len -= 2;
-+ len -= 2;
-+ }
-+ return;
-+ }
-+
-+ while (len--) {
-+ byte = bs->tx_buf ? *bs->tx_buf++ : 0;
-+ bcm2708_wr(bs, SPI_FIFO, byte);
-+ bs->len--;
-+ }
-+}
-+
-+static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id)
-+{
-+ struct spi_master *master = dev_id;
-+ struct bcm2708_spi *bs = spi_master_get_devdata(master);
-+ u32 cs;
-+
-+ spin_lock(&bs->lock);
-+
-+ cs = bcm2708_rd(bs, SPI_CS);
-+
-+ if (cs & SPI_CS_DONE) {
-+ if (bs->len) { /* first interrupt in a transfer */
-+ /* fill the TX fifo with up to 16 bytes */
-+ bcm2708_wr_fifo(bs, 16);
-+ } else { /* transfer complete */
-+ /* disable interrupts */
-+ cs &= ~(SPI_CS_INTR | SPI_CS_INTD);
-+ bcm2708_wr(bs, SPI_CS, cs);
-+
-+ /* drain RX FIFO */
-+ while (cs & SPI_CS_RXD) {
-+ bcm2708_rd_fifo(bs, 1);
-+ cs = bcm2708_rd(bs, SPI_CS);
-+ }
-+
-+ /* wake up our bh */
-+ complete(&bs->done);
-+ }
-+ } else if (cs & SPI_CS_RXR) {
-+ /* read 12 bytes of data */
-+ bcm2708_rd_fifo(bs, 12);
-+
-+ /* write up to 12 bytes */
-+ bcm2708_wr_fifo(bs, 12);
-+ }
-+
-+ spin_unlock(&bs->lock);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int bcm2708_setup_state(struct spi_master *master,
-+ struct device *dev, struct bcm2708_spi_state *state,
-+ u32 hz, u8 csel, u8 mode, u8 bpw)
-+{
-+ struct bcm2708_spi *bs = spi_master_get_devdata(master);
-+ int cdiv;
-+ unsigned long bus_hz;
-+ u32 cs = 0;
-+
-+ bus_hz = clk_get_rate(bs->clk);
-+
-+ if (hz >= bus_hz) {
-+ cdiv = 2; /* bus_hz / 2 is as fast as we can go */
-+ } else if (hz) {
-+ cdiv = DIV_ROUND_UP(bus_hz, hz);
-+
-+ /* CDIV must be a power of 2, so round up */
-+ cdiv = roundup_pow_of_two(cdiv);
-+
-+ if (cdiv > 65536) {
-+ dev_dbg(dev,
-+ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n",
-+ hz, cdiv, bus_hz / 65536);
-+ return -EINVAL;
-+ } else if (cdiv == 65536) {
-+ cdiv = 0;
-+ } else if (cdiv == 1) {
-+ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */
-+ }
-+ } else {
-+ cdiv = 0;
-+ }
-+
-+ switch (bpw) {
-+ case 8:
-+ break;
-+ case 9:
-+ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */
-+ cs |= SPI_CS_LEN;
-+ break;
-+ default:
-+ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n",
-+ bpw);
-+ return -EINVAL;
-+ }
-+
-+ if (mode & SPI_CPOL)
-+ cs |= SPI_CS_CPOL;
-+ if (mode & SPI_CPHA)
-+ cs |= SPI_CS_CPHA;
-+
-+ if (!(mode & SPI_NO_CS)) {
-+ if (mode & SPI_CS_HIGH) {
-+ cs |= SPI_CS_CSPOL;
-+ cs |= SPI_CS_CSPOL0 << csel;
-+ }
-+
-+ cs |= csel;
-+ } else {
-+ cs |= SPI_CS_CS_10 | SPI_CS_CS_01;
-+ }
-+
-+ if (state) {
-+ state->cs = cs;
-+ state->cdiv = cdiv;
-+ dev_dbg(dev, "setup: want %d Hz; "
-+ "bus_hz=%lu / cdiv=%u == %lu Hz; "
-+ "mode %u: cs 0x%08X\n",
-+ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs);
-+ }
-+
-+ return 0;
-+}
-+
-+static int bcm2708_process_transfer(struct bcm2708_spi *bs,
-+ struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+ struct spi_device *spi = msg->spi;
-+ struct bcm2708_spi_state state, *stp;
-+ int ret;
-+ u32 cs;
-+
-+ if (bs->stopping)
-+ return -ESHUTDOWN;
-+
-+ if (xfer->bits_per_word || xfer->speed_hz) {
-+ ret = bcm2708_setup_state(spi->master, &spi->dev, &state,
-+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
-+ spi->chip_select, spi->mode,
-+ xfer->bits_per_word ? xfer->bits_per_word :
-+ spi->bits_per_word);
-+ if (ret)
-+ return ret;
-+
-+ stp = &state;
-+ } else {
-+ stp = spi->controller_state;
-+ }
-+
-+ INIT_COMPLETION(bs->done);
-+ bs->tx_buf = xfer->tx_buf;
-+ bs->rx_buf = xfer->rx_buf;
-+ bs->len = xfer->len;
-+
-+ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA;
-+
-+ bcm2708_wr(bs, SPI_CLK, stp->cdiv);
-+ bcm2708_wr(bs, SPI_CS, cs);
-+
-+ ret = wait_for_completion_timeout(&bs->done,
-+ msecs_to_jiffies(SPI_TIMEOUT_MS));
-+ if (ret == 0) {
-+ dev_err(&spi->dev, "transfer timed out\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ if (xfer->delay_usecs)
-+ udelay(xfer->delay_usecs);
-+
-+ if (list_is_last(&xfer->transfer_list, &msg->transfers) ||
-+ xfer->cs_change) {
-+ /* clear TA and interrupt flags */
-+ bcm2708_wr(bs, SPI_CS, stp->cs);
-+ }
-+
-+ msg->actual_length += (xfer->len - bs->len);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_work(struct work_struct *work)
-+{
-+ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work);
-+ unsigned long flags;
-+ struct spi_message *msg;
-+ struct spi_transfer *xfer;
-+ int status = 0;
-+
-+ spin_lock_irqsave(&bs->lock, flags);
-+ while (!list_empty(&bs->queue)) {
-+ msg = list_first_entry(&bs->queue, struct spi_message, queue);
-+ list_del_init(&msg->queue);
-+ spin_unlock_irqrestore(&bs->lock, flags);
-+
-+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+ status = bcm2708_process_transfer(bs, msg, xfer);
-+ if (status)
-+ break;
-+ }
-+
-+ msg->status = status;
-+ msg->complete(msg->context);
-+
-+ spin_lock_irqsave(&bs->lock, flags);
-+ }
-+ spin_unlock_irqrestore(&bs->lock, flags);
-+}
-+
-+static int bcm2708_spi_setup(struct spi_device *spi)
-+{
-+ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
-+ struct bcm2708_spi_state *state;
-+ int ret;
-+
-+ if (bs->stopping)
-+ return -ESHUTDOWN;
-+
-+ if (!(spi->mode & SPI_NO_CS) &&
-+ (spi->chip_select > spi->master->num_chipselect)) {
-+ dev_dbg(&spi->dev,
-+ "setup: invalid chipselect %u (%u defined)\n",
-+ spi->chip_select, spi->master->num_chipselect);
-+ return -EINVAL;
-+ }
-+
-+ state = spi->controller_state;
-+ if (!state) {
-+ state = kzalloc(sizeof(*state), GFP_KERNEL);
-+ if (!state)
-+ return -ENOMEM;
-+
-+ spi->controller_state = state;
-+ }
-+
-+ ret = bcm2708_setup_state(spi->master, &spi->dev, state,
-+ spi->max_speed_hz, spi->chip_select, spi->mode,
-+ spi->bits_per_word);
-+ if (ret < 0) {
-+ kfree(state);
-+ spi->controller_state = NULL;
-+ return ret;
-+ }
-+
-+ dev_dbg(&spi->dev,
-+ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n",
-+ spi->chip_select, spi->max_speed_hz, spi->bits_per_word,
-+ spi->mode, state->cs, state->cdiv);
-+
-+ return 0;
-+}
-+
-+static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg)
-+{
-+ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
-+ struct spi_transfer *xfer;
-+ int ret;
-+ unsigned long flags;
-+
-+ if (unlikely(list_empty(&msg->transfers)))
-+ return -EINVAL;
-+
-+ if (bs->stopping)
-+ return -ESHUTDOWN;
-+
-+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
-+ dev_dbg(&spi->dev, "missing rx or tx buf\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!xfer->bits_per_word || xfer->speed_hz)
-+ continue;
-+
-+ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL,
-+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
-+ spi->chip_select, spi->mode,
-+ xfer->bits_per_word ? xfer->bits_per_word :
-+ spi->bits_per_word);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ msg->status = -EINPROGRESS;
-+ msg->actual_length = 0;
-+
-+ spin_lock_irqsave(&bs->lock, flags);
-+ list_add_tail(&msg->queue, &bs->queue);
-+ queue_work(bs->workq, &bs->work);
-+ spin_unlock_irqrestore(&bs->lock, flags);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_spi_cleanup(struct spi_device *spi)
-+{
-+ if (spi->controller_state) {
-+ kfree(spi->controller_state);
-+ spi->controller_state = NULL;
-+ }
-+}
-+
-+static int bcm2708_spi_probe(struct platform_device *pdev)
-+{
-+ struct resource *regs;
-+ int irq, err = -ENOMEM;
-+ struct clk *clk;
-+ struct spi_master *master;
-+ struct bcm2708_spi *bs;
-+
-+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!regs) {
-+ dev_err(&pdev->dev, "could not get IO memory\n");
-+ return -ENXIO;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "could not get IRQ\n");
-+ return irq;
-+ }
-+
-+ clk = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
-+ return PTR_ERR(clk);
-+ }
-+
-+ bcm2708_init_pinmode();
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(*bs));
-+ if (!master) {
-+ dev_err(&pdev->dev, "spi_alloc_master() failed\n");
-+ goto out_clk_put;
-+ }
-+
-+ /* the spi->mode bits understood by this driver: */
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS;
-+
-+ master->bus_num = pdev->id;
-+ master->num_chipselect = 3;
-+ master->setup = bcm2708_spi_setup;
-+ master->transfer = bcm2708_spi_transfer;
-+ master->cleanup = bcm2708_spi_cleanup;
-+ platform_set_drvdata(pdev, master);
-+
-+ bs = spi_master_get_devdata(master);
-+
-+ spin_lock_init(&bs->lock);
-+ INIT_LIST_HEAD(&bs->queue);
-+ init_completion(&bs->done);
-+ INIT_WORK(&bs->work, bcm2708_work);
-+
-+ bs->base = ioremap(regs->start, resource_size(regs));
-+ if (!bs->base) {
-+ dev_err(&pdev->dev, "could not remap memory\n");
-+ goto out_master_put;
-+ }
-+
-+ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev));
-+ if (!bs->workq) {
-+ dev_err(&pdev->dev, "could not create workqueue\n");
-+ goto out_iounmap;
-+ }
-+
-+ bs->irq = irq;
-+ bs->clk = clk;
-+ bs->stopping = false;
-+
-+ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev),
-+ master);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
-+ goto out_workqueue;
-+ }
-+
-+ /* initialise the hardware */
-+ clk_enable(clk);
-+ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
-+
-+ err = spi_register_master(master);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
-+ goto out_free_irq;
-+ }
-+
-+ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n",
-+ (unsigned long)regs->start, irq);
-+
-+ return 0;
-+
-+out_free_irq:
-+ free_irq(bs->irq, master);
-+out_workqueue:
-+ destroy_workqueue(bs->workq);
-+out_iounmap:
-+ iounmap(bs->base);
-+out_master_put:
-+ spi_master_put(master);
-+out_clk_put:
-+ clk_put(clk);
-+ return err;
-+}
-+
-+static int bcm2708_spi_remove(struct platform_device *pdev)
-+{
-+ struct spi_master *master = platform_get_drvdata(pdev);
-+ struct bcm2708_spi *bs = spi_master_get_devdata(master);
-+
-+ /* reset the hardware and block queue progress */
-+ spin_lock_irq(&bs->lock);
-+ bs->stopping = true;
-+ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
-+ spin_unlock_irq(&bs->lock);
-+
-+ flush_work_sync(&bs->work);
-+
-+ clk_disable(bs->clk);
-+ clk_put(bs->clk);
-+ free_irq(bs->irq, master);
-+ iounmap(bs->base);
-+
-+ spi_unregister_master(master);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm2708_spi_driver = {
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = bcm2708_spi_probe,
-+ .remove = bcm2708_spi_remove,
-+};
-+
-+
-+static int __init bcm2708_spi_init(void)
-+{
-+ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe);
-+}
-+module_init(bcm2708_spi_init);
-+
-+static void __exit bcm2708_spi_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_spi_driver);
-+}
-+module_exit(bcm2708_spi_exit);
-+
-+
-+//module_platform_driver(bcm2708_spi_driver);
-+
-+MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708");
-+MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRV_NAME);
-diff -Nur linux-3.12.38/drivers/spi/spi-dw-mid.c linux-rpi/drivers/spi/spi-dw-mid.c
---- linux-3.12.38/drivers/spi/spi-dw-mid.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/spi/spi-dw-mid.c 2015-03-10 17:26:51.030216689 +0100
-@@ -222,6 +222,7 @@
- iounmap(clk_reg);
-
- dws->num_cs = 16;
-+ dws->fifo_len = 40; /* FIFO has 40 words buffer */
-
- #ifdef CONFIG_SPI_DW_MID_DMA
- dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
-diff -Nur linux-3.12.38/drivers/spi/spi-fsl-spi.c linux-rpi/drivers/spi/spi-fsl-spi.c
---- linux-3.12.38/drivers/spi/spi-fsl-spi.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/spi/spi-fsl-spi.c 2015-03-10 17:26:51.030216689 +0100
-@@ -362,28 +362,18 @@
- static void fsl_spi_do_one_msg(struct spi_message *m)
- {
- struct spi_device *spi = m->spi;
-- struct spi_transfer *t, *first;
-+ struct spi_transfer *t;
- unsigned int cs_change;
- const int nsecs = 50;
- int status;
-
-- /* Don't allow changes if CS is active */
-- first = list_first_entry(&m->transfers, struct spi_transfer,
-- transfer_list);
-- list_for_each_entry(t, &m->transfers, transfer_list) {
-- if ((first->bits_per_word != t->bits_per_word) ||
-- (first->speed_hz != t->speed_hz)) {
-- status = -EINVAL;
-- dev_err(&spi->dev,
-- "bits_per_word/speed_hz should be same for the same SPI transfer\n");
-- return;
-- }
-- }
--
- cs_change = 1;
-- status = -EINVAL;
-+ status = 0;
- list_for_each_entry(t, &m->transfers, transfer_list) {
- if (t->bits_per_word || t->speed_hz) {
-+ /* Don't allow changes if CS is active */
-+ status = -EINVAL;
-+
- if (cs_change)
- status = fsl_spi_setup_transfer(spi, t);
- if (status < 0)
-diff -Nur linux-3.12.38/drivers/spi/spi-pxa2xx.c linux-rpi/drivers/spi/spi-pxa2xx.c
---- linux-3.12.38/drivers/spi/spi-pxa2xx.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/spi/spi-pxa2xx.c 2015-03-10 17:26:51.034216689 +0100
-@@ -400,8 +400,8 @@
- cs_deassert(drv_data);
- }
-
-- drv_data->cur_chip = NULL;
- spi_finalize_current_message(drv_data->master);
-+ drv_data->cur_chip = NULL;
- }
-
- static void reset_sccr1(struct driver_data *drv_data)
-diff -Nur linux-3.12.38/drivers/staging/lustre/lustre/llite/dcache.c linux-rpi/drivers/staging/lustre/lustre/llite/dcache.c
---- linux-3.12.38/drivers/staging/lustre/lustre/llite/dcache.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/staging/lustre/lustre/llite/dcache.c 2015-03-10 17:26:51.118216689 +0100
-@@ -278,7 +278,7 @@
- inode->i_ino, inode->i_generation, inode);
-
- ll_lock_dcache(inode);
-- ll_d_hlist_for_each_entry(dentry, p, &inode->i_dentry, d_u.d_alias) {
-+ ll_d_hlist_for_each_entry(dentry, p, &inode->i_dentry, d_alias) {
- CDEBUG(D_DENTRY, "dentry in drop %.*s (%p) parent %p "
- "inode %p flags %d\n", dentry->d_name.len,
- dentry->d_name.name, dentry, dentry->d_parent,
-diff -Nur linux-3.12.38/drivers/staging/lustre/lustre/llite/llite_lib.c linux-rpi/drivers/staging/lustre/lustre/llite/llite_lib.c
---- linux-3.12.38/drivers/staging/lustre/lustre/llite/llite_lib.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/staging/lustre/lustre/llite/llite_lib.c 2015-03-10 17:26:51.118216689 +0100
-@@ -665,7 +665,7 @@
- return;
-
- list_for_each(tmp, &dentry->d_subdirs) {
-- struct dentry *d = list_entry(tmp, struct dentry, d_child);
-+ struct dentry *d = list_entry(tmp, struct dentry, d_u.d_child);
- lustre_dump_dentry(d, recur - 1);
- }
- }
-diff -Nur linux-3.12.38/drivers/staging/lustre/lustre/llite/namei.c linux-rpi/drivers/staging/lustre/lustre/llite/namei.c
---- linux-3.12.38/drivers/staging/lustre/lustre/llite/namei.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/staging/lustre/lustre/llite/namei.c 2015-03-10 17:26:51.122216688 +0100
-@@ -175,14 +175,14 @@
- struct ll_d_hlist_node *p;
-
- ll_lock_dcache(dir);
-- ll_d_hlist_for_each_entry(dentry, p, &dir->i_dentry, d_u.d_alias) {
-+ ll_d_hlist_for_each_entry(dentry, p, &dir->i_dentry, d_alias) {
- spin_lock(&dentry->d_lock);
- if (!list_empty(&dentry->d_subdirs)) {
- struct dentry *child;
-
- list_for_each_entry_safe(child, tmp_subdir,
- &dentry->d_subdirs,
-- d_child) {
-+ d_u.d_child) {
- if (child->d_inode == NULL)
- d_lustre_invalidate(child, 1);
- }
-@@ -363,7 +363,7 @@
- discon_alias = invalid_alias = NULL;
-
- ll_lock_dcache(inode);
-- ll_d_hlist_for_each_entry(alias, p, &inode->i_dentry, d_u.d_alias) {
-+ ll_d_hlist_for_each_entry(alias, p, &inode->i_dentry, d_alias) {
- LASSERT(alias != dentry);
-
- spin_lock(&alias->d_lock);
-@@ -953,7 +953,7 @@
- {
- struct dentry *parent, *child;
-
-- parent = ll_d_hlist_entry(dir->i_dentry, struct dentry, d_u.d_alias);
-+ parent = ll_d_hlist_entry(dir->i_dentry, struct dentry, d_alias);
- child = d_lookup(parent, name);
- if (child) {
- if (child->d_inode)
-diff -Nur linux-3.12.38/drivers/staging/media/lirc/Kconfig linux-rpi/drivers/staging/media/lirc/Kconfig
---- linux-3.12.38/drivers/staging/media/lirc/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/staging/media/lirc/Kconfig 2015-03-09 10:39:32.818893720 +0100
-@@ -38,6 +38,12 @@
- help
- Driver for Homebrew Parallel Port Receivers
-
-+config LIRC_RPI
-+ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi"
-+ depends on LIRC
-+ help
-+ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi
-+
- config LIRC_SASEM
- tristate "Sasem USB IR Remote"
- depends on LIRC && USB
-diff -Nur linux-3.12.38/drivers/staging/media/lirc/lirc_rpi.c linux-rpi/drivers/staging/media/lirc/lirc_rpi.c
---- linux-3.12.38/drivers/staging/media/lirc/lirc_rpi.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/staging/media/lirc/lirc_rpi.c 2015-03-10 17:26:51.146216688 +0100
-@@ -0,0 +1,689 @@
-+/*
-+ * lirc_rpi.c
-+ *
-+ * lirc_rpi - Device driver that records pulse- and pause-lengths
-+ * (space-lengths) (just like the lirc_serial driver does)
-+ * between GPIO interrupt events on the Raspberry Pi.
-+ * Lots of code has been taken from the lirc_serial module,
-+ * so I would like say thanks to the authors.
-+ *
-+ * Copyright (C) 2012 Aron Robert Szabo <aron@reon.hu>,
-+ * Michael Bishop <cleverca22@gmail.com>
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/time.h>
-+#include <linux/timex.h>
-+#include <linux/string.h>
-+#include <linux/delay.h>
-+#include <linux/platform_device.h>
-+#include <linux/irq.h>
-+#include <linux/spinlock.h>
-+#include <media/lirc.h>
-+#include <media/lirc_dev.h>
-+#include <mach/gpio.h>
-+#include <linux/gpio.h>
-+
-+#include <linux/platform_data/bcm2708.h>
-+
-+#define LIRC_DRIVER_NAME "lirc_rpi"
-+#define RBUF_LEN 256
-+#define LIRC_TRANSMITTER_LATENCY 50
-+
-+#ifndef MAX_UDELAY_MS
-+#define MAX_UDELAY_US 5000
-+#else
-+#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
-+#endif
-+
-+#define dprintk(fmt, args...) \
-+ do { \
-+ if (debug) \
-+ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
-+ fmt, ## args); \
-+ } while (0)
-+
-+/* module parameters */
-+
-+/* set the default GPIO input pin */
-+static int gpio_in_pin = 18;
-+/* set the default pull behaviour for input pin */
-+static int gpio_in_pull = BCM2708_PULL_DOWN;
-+/* set the default GPIO output pin */
-+static int gpio_out_pin = 17;
-+/* enable debugging messages */
-+static bool debug;
-+/* -1 = auto, 0 = active high, 1 = active low */
-+static int sense = -1;
-+/* use softcarrier by default */
-+static bool softcarrier = 1;
-+/* 0 = do not invert output, 1 = invert output */
-+static bool invert = 0;
-+
-+struct gpio_chip *gpiochip;
-+struct irq_chip *irqchip;
-+struct irq_data *irqdata;
-+
-+/* forward declarations */
-+static long send_pulse(unsigned long length);
-+static void send_space(long length);
-+static void lirc_rpi_exit(void);
-+
-+static struct platform_device *lirc_rpi_dev;
-+static struct timeval lasttv = { 0, 0 };
-+static struct lirc_buffer rbuf;
-+static spinlock_t lock;
-+
-+/* initialized/set in init_timing_params() */
-+static unsigned int freq = 38000;
-+static unsigned int duty_cycle = 50;
-+static unsigned long period;
-+static unsigned long pulse_width;
-+static unsigned long space_width;
-+
-+static void safe_udelay(unsigned long usecs)
-+{
-+ while (usecs > MAX_UDELAY_US) {
-+ udelay(MAX_UDELAY_US);
-+ usecs -= MAX_UDELAY_US;
-+ }
-+ udelay(usecs);
-+}
-+
-+static int init_timing_params(unsigned int new_duty_cycle,
-+ unsigned int new_freq)
-+{
-+ if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <=
-+ LIRC_TRANSMITTER_LATENCY)
-+ return -EINVAL;
-+ if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <=
-+ LIRC_TRANSMITTER_LATENCY)
-+ return -EINVAL;
-+ duty_cycle = new_duty_cycle;
-+ freq = new_freq;
-+ period = 1000 * 1000000L / freq;
-+ pulse_width = period * duty_cycle / 100;
-+ space_width = period - pulse_width;
-+ dprintk("in init_timing_params, freq=%d pulse=%ld, "
-+ "space=%ld\n", freq, pulse_width, space_width);
-+ return 0;
-+}
-+
-+static long send_pulse_softcarrier(unsigned long length)
-+{
-+ int flag;
-+ unsigned long actual, target;
-+ unsigned long actual_us, initial_us, target_us;
-+
-+ length *= 1000;
-+
-+ actual = 0; target = 0; flag = 0;
-+ read_current_timer(&actual_us);
-+
-+ while (actual < length) {
-+ if (flag) {
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+ target += space_width;
-+ } else {
-+ gpiochip->set(gpiochip, gpio_out_pin, !invert);
-+ target += pulse_width;
-+ }
-+ initial_us = actual_us;
-+ target_us = actual_us + (target - actual) / 1000;
-+ /*
-+ * Note - we've checked in ioctl that the pulse/space
-+ * widths are big enough so that d is > 0
-+ */
-+ if ((int)(target_us - actual_us) > 0)
-+ udelay(target_us - actual_us);
-+ read_current_timer(&actual_us);
-+ actual += (actual_us - initial_us) * 1000;
-+ flag = !flag;
-+ }
-+ return (actual-length) / 1000;
-+}
-+
-+static long send_pulse(unsigned long length)
-+{
-+ if (length <= 0)
-+ return 0;
-+
-+ if (softcarrier) {
-+ return send_pulse_softcarrier(length);
-+ } else {
-+ gpiochip->set(gpiochip, gpio_out_pin, !invert);
-+ safe_udelay(length);
-+ return 0;
-+ }
-+}
-+
-+static void send_space(long length)
-+{
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+ if (length <= 0)
-+ return;
-+ safe_udelay(length);
-+}
-+
-+static void rbwrite(int l)
-+{
-+ if (lirc_buffer_full(&rbuf)) {
-+ /* no new signals will be accepted */
-+ dprintk("Buffer overrun\n");
-+ return;
-+ }
-+ lirc_buffer_write(&rbuf, (void *)&l);
-+}
-+
-+static void frbwrite(int l)
-+{
-+ /* simple noise filter */
-+ static int pulse, space;
-+ static unsigned int ptr;
-+
-+ if (ptr > 0 && (l & PULSE_BIT)) {
-+ pulse += l & PULSE_MASK;
-+ if (pulse > 250) {
-+ rbwrite(space);
-+ rbwrite(pulse | PULSE_BIT);
-+ ptr = 0;
-+ pulse = 0;
-+ }
-+ return;
-+ }
-+ if (!(l & PULSE_BIT)) {
-+ if (ptr == 0) {
-+ if (l > 20000) {
-+ space = l;
-+ ptr++;
-+ return;
-+ }
-+ } else {
-+ if (l > 20000) {
-+ space += pulse;
-+ if (space > PULSE_MASK)
-+ space = PULSE_MASK;
-+ space += l;
-+ if (space > PULSE_MASK)
-+ space = PULSE_MASK;
-+ pulse = 0;
-+ return;
-+ }
-+ rbwrite(space);
-+ rbwrite(pulse | PULSE_BIT);
-+ ptr = 0;
-+ pulse = 0;
-+ }
-+ }
-+ rbwrite(l);
-+}
-+
-+static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs)
-+{
-+ struct timeval tv;
-+ long deltv;
-+ int data;
-+ int signal;
-+
-+ /* use the GPIO signal level */
-+ signal = gpiochip->get(gpiochip, gpio_in_pin);
-+
-+ /* unmask the irq */
-+ irqchip->irq_unmask(irqdata);
-+
-+ if (sense != -1) {
-+ /* get current time */
-+ do_gettimeofday(&tv);
-+
-+ /* calc time since last interrupt in microseconds */
-+ deltv = tv.tv_sec-lasttv.tv_sec;
-+ if (tv.tv_sec < lasttv.tv_sec ||
-+ (tv.tv_sec == lasttv.tv_sec &&
-+ tv.tv_usec < lasttv.tv_usec)) {
-+ printk(KERN_WARNING LIRC_DRIVER_NAME
-+ ": AIEEEE: your clock just jumped backwards\n");
-+ printk(KERN_WARNING LIRC_DRIVER_NAME
-+ ": %d %d %lx %lx %lx %lx\n", signal, sense,
-+ tv.tv_sec, lasttv.tv_sec,
-+ tv.tv_usec, lasttv.tv_usec);
-+ data = PULSE_MASK;
-+ } else if (deltv > 15) {
-+ data = PULSE_MASK; /* really long time */
-+ if (!(signal^sense)) {
-+ /* sanity check */
-+ printk(KERN_WARNING LIRC_DRIVER_NAME
-+ ": AIEEEE: %d %d %lx %lx %lx %lx\n",
-+ signal, sense, tv.tv_sec, lasttv.tv_sec,
-+ tv.tv_usec, lasttv.tv_usec);
-+ /*
-+ * detecting pulse while this
-+ * MUST be a space!
-+ */
-+ sense = sense ? 0 : 1;
-+ }
-+ } else {
-+ data = (int) (deltv*1000000 +
-+ (tv.tv_usec - lasttv.tv_usec));
-+ }
-+ frbwrite(signal^sense ? data : (data|PULSE_BIT));
-+ lasttv = tv;
-+ wake_up_interruptible(&rbuf.wait_poll);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int is_right_chip(struct gpio_chip *chip, void *data)
-+{
-+ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label));
-+
-+ if (strcmp(data, chip->label) == 0)
-+ return 1;
-+ return 0;
-+}
-+
-+static int init_port(void)
-+{
-+ int i, nlow, nhigh, ret, irq;
-+
-+ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip);
-+
-+ if (!gpiochip)
-+ return -ENODEV;
-+
-+ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) {
-+ printk(KERN_ALERT LIRC_DRIVER_NAME
-+ ": cant claim gpio pin %d\n", gpio_out_pin);
-+ ret = -ENODEV;
-+ goto exit_init_port;
-+ }
-+
-+ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) {
-+ printk(KERN_ALERT LIRC_DRIVER_NAME
-+ ": cant claim gpio pin %d\n", gpio_in_pin);
-+ ret = -ENODEV;
-+ goto exit_gpio_free_out_pin;
-+ }
-+
-+ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull);
-+ gpiochip->direction_input(gpiochip, gpio_in_pin);
-+ gpiochip->direction_output(gpiochip, gpio_out_pin, 1);
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+
-+ irq = gpiochip->to_irq(gpiochip, gpio_in_pin);
-+ dprintk("to_irq %d\n", irq);
-+ irqdata = irq_get_irq_data(irq);
-+
-+ if (irqdata && irqdata->chip) {
-+ irqchip = irqdata->chip;
-+ } else {
-+ ret = -ENODEV;
-+ goto exit_gpio_free_in_pin;
-+ }
-+
-+ /* if pin is high, then this must be an active low receiver. */
-+ if (sense == -1) {
-+ /* wait 1/2 sec for the power supply */
-+ msleep(500);
-+
-+ /*
-+ * probe 9 times every 0.04s, collect "votes" for
-+ * active high/low
-+ */
-+ nlow = 0;
-+ nhigh = 0;
-+ for (i = 0; i < 9; i++) {
-+ if (gpiochip->get(gpiochip, gpio_in_pin))
-+ nlow++;
-+ else
-+ nhigh++;
-+ msleep(40);
-+ }
-+ sense = (nlow >= nhigh ? 1 : 0);
-+ printk(KERN_INFO LIRC_DRIVER_NAME
-+ ": auto-detected active %s receiver on GPIO pin %d\n",
-+ sense ? "low" : "high", gpio_in_pin);
-+ } else {
-+ printk(KERN_INFO LIRC_DRIVER_NAME
-+ ": manually using active %s receiver on GPIO pin %d\n",
-+ sense ? "low" : "high", gpio_in_pin);
-+ }
-+
-+ return 0;
-+
-+ exit_gpio_free_in_pin:
-+ gpio_free(gpio_in_pin);
-+
-+ exit_gpio_free_out_pin:
-+ gpio_free(gpio_out_pin);
-+
-+ exit_init_port:
-+ return ret;
-+}
-+
-+// called when the character device is opened
-+static int set_use_inc(void *data)
-+{
-+ int result;
-+ unsigned long flags;
-+
-+ /* initialize timestamp */
-+ do_gettimeofday(&lasttv);
-+
-+ result = request_irq(gpiochip->to_irq(gpiochip, gpio_in_pin),
-+ (irq_handler_t) irq_handler, 0,
-+ LIRC_DRIVER_NAME, (void*) 0);
-+
-+ switch (result) {
-+ case -EBUSY:
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": IRQ %d is busy\n",
-+ gpiochip->to_irq(gpiochip, gpio_in_pin));
-+ return -EBUSY;
-+ case -EINVAL:
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": Bad irq number or handler\n");
-+ return -EINVAL;
-+ default:
-+ dprintk("Interrupt %d obtained\n",
-+ gpiochip->to_irq(gpiochip, gpio_in_pin));
-+ break;
-+ };
-+
-+ /* initialize pulse/space widths */
-+ init_timing_params(duty_cycle, freq);
-+
-+ spin_lock_irqsave(&lock, flags);
-+
-+ /* GPIO Pin Falling/Rising Edge Detect Enable */
-+ irqchip->irq_set_type(irqdata,
-+ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING);
-+
-+ /* unmask the irq */
-+ irqchip->irq_unmask(irqdata);
-+
-+ spin_unlock_irqrestore(&lock, flags);
-+
-+ return 0;
-+}
-+
-+static void set_use_dec(void *data)
-+{
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&lock, flags);
-+
-+ /* GPIO Pin Falling/Rising Edge Detect Disable */
-+ irqchip->irq_set_type(irqdata, 0);
-+ irqchip->irq_mask(irqdata);
-+
-+ spin_unlock_irqrestore(&lock, flags);
-+
-+ free_irq(gpiochip->to_irq(gpiochip, gpio_in_pin), (void *) 0);
-+
-+ dprintk(KERN_INFO LIRC_DRIVER_NAME
-+ ": freed IRQ %d\n", gpiochip->to_irq(gpiochip, gpio_in_pin));
-+}
-+
-+static ssize_t lirc_write(struct file *file, const char *buf,
-+ size_t n, loff_t *ppos)
-+{
-+ int i, count;
-+ unsigned long flags;
-+ long delta = 0;
-+ int *wbuf;
-+
-+ count = n / sizeof(int);
-+ if (n % sizeof(int) || count % 2 == 0)
-+ return -EINVAL;
-+ wbuf = memdup_user(buf, n);
-+ if (IS_ERR(wbuf))
-+ return PTR_ERR(wbuf);
-+ spin_lock_irqsave(&lock, flags);
-+
-+ for (i = 0; i < count; i++) {
-+ if (i%2)
-+ send_space(wbuf[i] - delta);
-+ else
-+ delta = send_pulse(wbuf[i]);
-+ }
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+
-+ spin_unlock_irqrestore(&lock, flags);
-+ kfree(wbuf);
-+ return n;
-+}
-+
-+static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
-+{
-+ int result;
-+ __u32 value;
-+
-+ switch (cmd) {
-+ case LIRC_GET_SEND_MODE:
-+ return -ENOIOCTLCMD;
-+ break;
-+
-+ case LIRC_SET_SEND_MODE:
-+ result = get_user(value, (__u32 *) arg);
-+ if (result)
-+ return result;
-+ /* only LIRC_MODE_PULSE supported */
-+ if (value != LIRC_MODE_PULSE)
-+ return -ENOSYS;
-+ break;
-+
-+ case LIRC_GET_LENGTH:
-+ return -ENOSYS;
-+ break;
-+
-+ case LIRC_SET_SEND_DUTY_CYCLE:
-+ dprintk("SET_SEND_DUTY_CYCLE\n");
-+ result = get_user(value, (__u32 *) arg);
-+ if (result)
-+ return result;
-+ if (value <= 0 || value > 100)
-+ return -EINVAL;
-+ return init_timing_params(value, freq);
-+ break;
-+
-+ case LIRC_SET_SEND_CARRIER:
-+ dprintk("SET_SEND_CARRIER\n");
-+ result = get_user(value, (__u32 *) arg);
-+ if (result)
-+ return result;
-+ if (value > 500000 || value < 20000)
-+ return -EINVAL;
-+ return init_timing_params(duty_cycle, value);
-+ break;
-+
-+ default:
-+ return lirc_dev_fop_ioctl(filep, cmd, arg);
-+ }
-+ return 0;
-+}
-+
-+static const struct file_operations lirc_fops = {
-+ .owner = THIS_MODULE,
-+ .write = lirc_write,
-+ .unlocked_ioctl = lirc_ioctl,
-+ .read = lirc_dev_fop_read,
-+ .poll = lirc_dev_fop_poll,
-+ .open = lirc_dev_fop_open,
-+ .release = lirc_dev_fop_close,
-+ .llseek = no_llseek,
-+};
-+
-+static struct lirc_driver driver = {
-+ .name = LIRC_DRIVER_NAME,
-+ .minor = -1,
-+ .code_length = 1,
-+ .sample_rate = 0,
-+ .data = NULL,
-+ .add_to_buf = NULL,
-+ .rbuf = &rbuf,
-+ .set_use_inc = set_use_inc,
-+ .set_use_dec = set_use_dec,
-+ .fops = &lirc_fops,
-+ .dev = NULL,
-+ .owner = THIS_MODULE,
-+};
-+
-+static struct platform_driver lirc_rpi_driver = {
-+ .driver = {
-+ .name = LIRC_DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init lirc_rpi_init(void)
-+{
-+ int result;
-+
-+ /* Init read buffer. */
-+ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN);
-+ if (result < 0)
-+ return -ENOMEM;
-+
-+ result = platform_driver_register(&lirc_rpi_driver);
-+ if (result) {
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": lirc register returned %d\n", result);
-+ goto exit_buffer_free;
-+ }
-+
-+ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0);
-+ if (!lirc_rpi_dev) {
-+ result = -ENOMEM;
-+ goto exit_driver_unregister;
-+ }
-+
-+ result = platform_device_add(lirc_rpi_dev);
-+ if (result)
-+ goto exit_device_put;
-+
-+ return 0;
-+
-+ exit_device_put:
-+ platform_device_put(lirc_rpi_dev);
-+
-+ exit_driver_unregister:
-+ platform_driver_unregister(&lirc_rpi_driver);
-+
-+ exit_buffer_free:
-+ lirc_buffer_free(&rbuf);
-+
-+ return result;
-+}
-+
-+static void lirc_rpi_exit(void)
-+{
-+ platform_device_unregister(lirc_rpi_dev);
-+ platform_driver_unregister(&lirc_rpi_driver);
-+ lirc_buffer_free(&rbuf);
-+}
-+
-+static int __init lirc_rpi_init_module(void)
-+{
-+ int result;
-+
-+ result = lirc_rpi_init();
-+ if (result)
-+ return result;
-+
-+ if (gpio_in_pin >= BCM2708_NR_GPIOS || gpio_out_pin >= BCM2708_NR_GPIOS) {
-+ result = -EINVAL;
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": invalid GPIO pin(s) specified!\n");
-+ goto exit_rpi;
-+ }
-+
-+ result = init_port();
-+ if (result < 0)
-+ goto exit_rpi;
-+
-+ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE |
-+ LIRC_CAN_SET_SEND_CARRIER |
-+ LIRC_CAN_SEND_PULSE |
-+ LIRC_CAN_REC_MODE2;
-+
-+ driver.dev = &lirc_rpi_dev->dev;
-+ driver.minor = lirc_register_driver(&driver);
-+
-+ if (driver.minor < 0) {
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": device registration failed with %d\n", result);
-+ result = -EIO;
-+ goto exit_rpi;
-+ }
-+
-+ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n");
-+
-+ return 0;
-+
-+ exit_rpi:
-+ lirc_rpi_exit();
-+
-+ return result;
-+}
-+
-+static void __exit lirc_rpi_exit_module(void)
-+{
-+ gpio_free(gpio_out_pin);
-+ gpio_free(gpio_in_pin);
-+
-+ lirc_rpi_exit();
-+
-+ lirc_unregister_driver(driver.minor);
-+ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n");
-+}
-+
-+module_init(lirc_rpi_init_module);
-+module_exit(lirc_rpi_exit_module);
-+
-+MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO.");
-+MODULE_AUTHOR("Aron Robert Szabo <aron@reon.hu>");
-+MODULE_AUTHOR("Michael Bishop <cleverca22@gmail.com>");
-+MODULE_LICENSE("GPL");
-+
-+module_param(gpio_out_pin, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM"
-+ " processor. (default 17");
-+
-+module_param(gpio_in_pin, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor."
-+ " (default 18");
-+
-+module_param(gpio_in_pull, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration."
-+ " (0 = off, 1 = up, 2 = down, default down)");
-+
-+module_param(sense, int, S_IRUGO);
-+MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit"
-+ " (0 = active high, 1 = active low )");
-+
-+module_param(softcarrier, bool, S_IRUGO);
-+MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)");
-+
-+module_param(invert, bool, S_IRUGO);
-+MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off");
-+
-+module_param(debug, bool, S_IRUGO | S_IWUSR);
-+MODULE_PARM_DESC(debug, "Enable debugging messages");
-diff -Nur linux-3.12.38/drivers/staging/media/lirc/Makefile linux-rpi/drivers/staging/media/lirc/Makefile
---- linux-3.12.38/drivers/staging/media/lirc/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/staging/media/lirc/Makefile 2015-03-09 10:39:32.818893720 +0100
-@@ -7,6 +7,7 @@
- obj-$(CONFIG_LIRC_IGORPLUGUSB) += lirc_igorplugusb.o
- obj-$(CONFIG_LIRC_IMON) += lirc_imon.o
- obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o
-+obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o
- obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o
- obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o
- obj-$(CONFIG_LIRC_SIR) += lirc_sir.o
-diff -Nur linux-3.12.38/drivers/target/iscsi/iscsi_target_login.c linux-rpi/drivers/target/iscsi/iscsi_target_login.c
---- linux-3.12.38/drivers/target/iscsi/iscsi_target_login.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/iscsi/iscsi_target_login.c 2015-03-10 17:26:51.246216688 +0100
-@@ -1188,9 +1188,6 @@
- conn->sock = NULL;
- }
-
-- if (conn->conn_transport->iscsit_wait_conn)
-- conn->conn_transport->iscsit_wait_conn(conn);
--
- if (conn->conn_transport->iscsit_free_conn)
- conn->conn_transport->iscsit_free_conn(conn);
-
-diff -Nur linux-3.12.38/drivers/target/iscsi/iscsi_target_util.c linux-rpi/drivers/target/iscsi/iscsi_target_util.c
---- linux-3.12.38/drivers/target/iscsi/iscsi_target_util.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/iscsi/iscsi_target_util.c 2015-03-10 17:26:51.246216688 +0100
-@@ -1355,15 +1355,15 @@
- struct iscsi_conn *conn,
- struct iscsi_data_count *count)
- {
-- int ret, iov_len;
-+ int data = count->data_length, total_tx = 0, tx_loop = 0, iov_len;
- struct kvec *iov_p;
- struct msghdr msg;
-
- if (!conn || !conn->sock || !conn->conn_ops)
- return -1;
-
-- if (count->data_length <= 0) {
-- pr_err("Data length is: %d\n", count->data_length);
-+ if (data <= 0) {
-+ pr_err("Data length is: %d\n", data);
- return -1;
- }
-
-@@ -1372,16 +1372,20 @@
- iov_p = count->iov;
- iov_len = count->iov_count;
-
-- ret = kernel_sendmsg(conn->sock, &msg, iov_p, iov_len,
-- count->data_length);
-- if (ret != count->data_length) {
-- pr_err("Unexpected ret: %d send data %d\n",
-- ret, count->data_length);
-- return -EPIPE;
-+ while (total_tx < data) {
-+ tx_loop = kernel_sendmsg(conn->sock, &msg, iov_p, iov_len,
-+ (data - total_tx));
-+ if (tx_loop <= 0) {
-+ pr_debug("tx_loop: %d total_tx %d\n",
-+ tx_loop, total_tx);
-+ return tx_loop;
-+ }
-+ total_tx += tx_loop;
-+ pr_debug("tx_loop: %d, total_tx: %d, data: %d\n",
-+ tx_loop, total_tx, data);
- }
-- pr_debug("ret: %d, sent data: %d\n", ret, count->data_length);
-
-- return ret;
-+ return total_tx;
- }
-
- int rx_data(
-diff -Nur linux-3.12.38/drivers/target/loopback/tcm_loop.c linux-rpi/drivers/target/loopback/tcm_loop.c
---- linux-3.12.38/drivers/target/loopback/tcm_loop.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/loopback/tcm_loop.c 2015-03-10 17:26:51.246216688 +0100
-@@ -179,7 +179,7 @@
- goto out_done;
- }
-
-- tl_nexus = tl_tpg->tl_nexus;
-+ tl_nexus = tl_hba->tl_nexus;
- if (!tl_nexus) {
- scmd_printk(KERN_ERR, sc, "TCM_Loop I_T Nexus"
- " does not exist\n");
-@@ -258,20 +258,20 @@
- */
- tl_hba = *(struct tcm_loop_hba **)shost_priv(sc->device->host);
- /*
-- * Locate the tl_tpg and se_tpg pointers from TargetID in sc->device->id
-- */
-- tl_tpg = &tl_hba->tl_hba_tpgs[sc->device->id];
-- se_tpg = &tl_tpg->tl_se_tpg;
-- /*
- * Locate the tl_nexus and se_sess pointers
- */
-- tl_nexus = tl_tpg->tl_nexus;
-+ tl_nexus = tl_hba->tl_nexus;
- if (!tl_nexus) {
- pr_err("Unable to perform device reset without"
- " active I_T Nexus\n");
- return FAILED;
- }
- se_sess = tl_nexus->se_sess;
-+ /*
-+ * Locate the tl_tpg and se_tpg pointers from TargetID in sc->device->id
-+ */
-+ tl_tpg = &tl_hba->tl_hba_tpgs[sc->device->id];
-+ se_tpg = &tl_tpg->tl_se_tpg;
-
- tl_cmd = kmem_cache_zalloc(tcm_loop_cmd_cache, GFP_KERNEL);
- if (!tl_cmd) {
-@@ -878,8 +878,8 @@
- struct tcm_loop_nexus *tl_nexus;
- int ret = -ENOMEM;
-
-- if (tl_tpg->tl_nexus) {
-- pr_debug("tl_tpg->tl_nexus already exists\n");
-+ if (tl_tpg->tl_hba->tl_nexus) {
-+ pr_debug("tl_tpg->tl_hba->tl_nexus already exists\n");
- return -EEXIST;
- }
- se_tpg = &tl_tpg->tl_se_tpg;
-@@ -914,7 +914,7 @@
- */
- __transport_register_session(se_tpg, tl_nexus->se_sess->se_node_acl,
- tl_nexus->se_sess, tl_nexus);
-- tl_tpg->tl_nexus = tl_nexus;
-+ tl_tpg->tl_hba->tl_nexus = tl_nexus;
- pr_debug("TCM_Loop_ConfigFS: Established I_T Nexus to emulated"
- " %s Initiator Port: %s\n", tcm_loop_dump_proto_id(tl_hba),
- name);
-@@ -930,8 +930,9 @@
- {
- struct se_session *se_sess;
- struct tcm_loop_nexus *tl_nexus;
-+ struct tcm_loop_hba *tl_hba = tpg->tl_hba;
-
-- tl_nexus = tpg->tl_nexus;
-+ tl_nexus = tpg->tl_hba->tl_nexus;
- if (!tl_nexus)
- return -ENODEV;
-
-@@ -947,13 +948,13 @@
- }
-
- pr_debug("TCM_Loop_ConfigFS: Removing I_T Nexus to emulated"
-- " %s Initiator Port: %s\n", tcm_loop_dump_proto_id(tpg->tl_hba),
-+ " %s Initiator Port: %s\n", tcm_loop_dump_proto_id(tl_hba),
- tl_nexus->se_sess->se_node_acl->initiatorname);
- /*
- * Release the SCSI I_T Nexus to the emulated SAS Target Port
- */
- transport_deregister_session(tl_nexus->se_sess);
-- tpg->tl_nexus = NULL;
-+ tpg->tl_hba->tl_nexus = NULL;
- kfree(tl_nexus);
- return 0;
- }
-@@ -969,7 +970,7 @@
- struct tcm_loop_nexus *tl_nexus;
- ssize_t ret;
-
-- tl_nexus = tl_tpg->tl_nexus;
-+ tl_nexus = tl_tpg->tl_hba->tl_nexus;
- if (!tl_nexus)
- return -ENODEV;
-
-diff -Nur linux-3.12.38/drivers/target/loopback/tcm_loop.h linux-rpi/drivers/target/loopback/tcm_loop.h
---- linux-3.12.38/drivers/target/loopback/tcm_loop.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/loopback/tcm_loop.h 2015-03-10 17:26:51.250216688 +0100
-@@ -25,6 +25,11 @@
- };
-
- struct tcm_loop_nexus {
-+ int it_nexus_active;
-+ /*
-+ * Pointer to Linux/SCSI HBA from linux/include/scsi_host.h
-+ */
-+ struct scsi_host *sh;
- /*
- * Pointer to TCM session for I_T Nexus
- */
-@@ -40,7 +45,6 @@
- atomic_t tl_tpg_port_count;
- struct se_portal_group tl_se_tpg;
- struct tcm_loop_hba *tl_hba;
-- struct tcm_loop_nexus *tl_nexus;
- };
-
- struct tcm_loop_hba {
-@@ -49,6 +53,7 @@
- struct se_hba_s *se_hba;
- struct se_lun *tl_hba_lun;
- struct se_port *tl_hba_lun_sep;
-+ struct tcm_loop_nexus *tl_nexus;
- struct device dev;
- struct Scsi_Host *sh;
- struct tcm_loop_tpg tl_hba_tpgs[TL_TPGS_PER_HBA];
-diff -Nur linux-3.12.38/drivers/target/target_core_device.c linux-rpi/drivers/target/target_core_device.c
---- linux-3.12.38/drivers/target/target_core_device.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/target_core_device.c 2015-03-10 17:26:51.250216688 +0100
-@@ -1066,10 +1066,10 @@
- " changed for TCM/pSCSI\n", dev);
- return -EINVAL;
- }
-- if (optimal_sectors > dev->dev_attrib.hw_max_sectors) {
-+ if (optimal_sectors > dev->dev_attrib.fabric_max_sectors) {
- pr_err("dev[%p]: Passed optimal_sectors %u cannot be"
-- " greater than hw_max_sectors: %u\n", dev,
-- optimal_sectors, dev->dev_attrib.hw_max_sectors);
-+ " greater than fabric_max_sectors: %u\n", dev,
-+ optimal_sectors, dev->dev_attrib.fabric_max_sectors);
- return -EINVAL;
- }
-
-@@ -1474,6 +1474,7 @@
- DA_UNMAP_GRANULARITY_ALIGNMENT_DEFAULT;
- dev->dev_attrib.max_write_same_len = DA_MAX_WRITE_SAME_LEN;
- dev->dev_attrib.fabric_max_sectors = DA_FABRIC_MAX_SECTORS;
-+ dev->dev_attrib.optimal_sectors = DA_FABRIC_MAX_SECTORS;
-
- return dev;
- }
-@@ -1506,7 +1507,6 @@
- dev->dev_attrib.hw_max_sectors =
- se_dev_align_max_sectors(dev->dev_attrib.hw_max_sectors,
- dev->dev_attrib.hw_block_size);
-- dev->dev_attrib.optimal_sectors = dev->dev_attrib.hw_max_sectors;
-
- dev->dev_index = scsi_get_new_index(SCSI_DEVICE_INDEX);
- dev->creation_time = get_jiffies_64();
-diff -Nur linux-3.12.38/drivers/target/target_core_file.c linux-rpi/drivers/target/target_core_file.c
---- linux-3.12.38/drivers/target/target_core_file.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/target_core_file.c 2015-03-10 17:26:51.250216688 +0100
-@@ -552,16 +552,7 @@
- {
- struct se_device *dev = cmd->se_dev;
- int ret = 0;
-- /*
-- * We are currently limited by the number of iovecs (2048) per
-- * single vfs_[writev,readv] call.
-- */
-- if (cmd->data_length > FD_MAX_BYTES) {
-- pr_err("FILEIO: Not able to process I/O of %u bytes due to"
-- "FD_MAX_BYTES: %u iovec count limitiation\n",
-- cmd->data_length, FD_MAX_BYTES);
-- return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
-- }
-+
- /*
- * Call vectorized fileio functions to map struct scatterlist
- * physical memory addresses to struct iovec virtual memory.
-diff -Nur linux-3.12.38/drivers/target/target_core_iblock.c linux-rpi/drivers/target/target_core_iblock.c
---- linux-3.12.38/drivers/target/target_core_iblock.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/target_core_iblock.c 2015-03-10 17:26:51.250216688 +0100
-@@ -122,7 +122,7 @@
- q = bdev_get_queue(bd);
-
- dev->dev_attrib.hw_block_size = bdev_logical_block_size(bd);
-- dev->dev_attrib.hw_max_sectors = queue_max_hw_sectors(q);
-+ dev->dev_attrib.hw_max_sectors = UINT_MAX;
- dev->dev_attrib.hw_queue_depth = q->nr_requests;
-
- /*
-diff -Nur linux-3.12.38/drivers/target/target_core_sbc.c linux-rpi/drivers/target/target_core_sbc.c
---- linux-3.12.38/drivers/target/target_core_sbc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/target_core_sbc.c 2015-03-10 17:26:51.250216688 +0100
-@@ -829,6 +829,21 @@
- if (cmd->se_cmd_flags & SCF_SCSI_DATA_CDB) {
- unsigned long long end_lba;
-
-+ if (sectors > dev->dev_attrib.fabric_max_sectors) {
-+ printk_ratelimited(KERN_ERR "SCSI OP %02xh with too"
-+ " big sectors %u exceeds fabric_max_sectors:"
-+ " %u\n", cdb[0], sectors,
-+ dev->dev_attrib.fabric_max_sectors);
-+ return TCM_INVALID_CDB_FIELD;
-+ }
-+ if (sectors > dev->dev_attrib.hw_max_sectors) {
-+ printk_ratelimited(KERN_ERR "SCSI OP %02xh with too"
-+ " big sectors %u exceeds backend hw_max_sectors:"
-+ " %u\n", cdb[0], sectors,
-+ dev->dev_attrib.hw_max_sectors);
-+ return TCM_INVALID_CDB_FIELD;
-+ }
-+
- end_lba = dev->transport->get_blocks(dev) + 1;
- if (cmd->t_task_lba + sectors > end_lba) {
- pr_err("cmd exceeds last lba %llu "
-diff -Nur linux-3.12.38/drivers/target/target_core_spc.c linux-rpi/drivers/target/target_core_spc.c
---- linux-3.12.38/drivers/target/target_core_spc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/target/target_core_spc.c 2015-03-10 17:26:51.250216688 +0100
-@@ -450,6 +450,7 @@
- spc_emulate_evpd_b0(struct se_cmd *cmd, unsigned char *buf)
- {
- struct se_device *dev = cmd->se_dev;
-+ u32 max_sectors;
- int have_tp = 0;
-
- /*
-@@ -479,7 +480,9 @@
- /*
- * Set MAXIMUM TRANSFER LENGTH
- */
-- put_unaligned_be32(dev->dev_attrib.hw_max_sectors, &buf[8]);
-+ max_sectors = min(dev->dev_attrib.fabric_max_sectors,
-+ dev->dev_attrib.hw_max_sectors);
-+ put_unaligned_be32(max_sectors, &buf[8]);
-
- /*
- * Set OPTIMAL TRANSFER LENGTH
-diff -Nur linux-3.12.38/drivers/thermal/bcm2835-thermal.c linux-rpi/drivers/thermal/bcm2835-thermal.c
---- linux-3.12.38/drivers/thermal/bcm2835-thermal.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/thermal/bcm2835-thermal.c 2015-03-09 10:39:33.042893719 +0100
-@@ -0,0 +1,184 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/sysfs.h>
-+#include <mach/vcio.h>
-+#include <linux/thermal.h>
-+
-+
-+/* --- DEFINITIONS --- */
-+#define MODULE_NAME "bcm2835_thermal"
-+
-+/*#define THERMAL_DEBUG_ENABLE*/
-+
-+#ifdef THERMAL_DEBUG_ENABLE
-+#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+
-+#define VC_TAG_GET_TEMP 0x00030006
-+#define VC_TAG_GET_MAX_TEMP 0x0003000A
-+
-+typedef enum {
-+ TEMP,
-+ MAX_TEMP,
-+} temp_type;
-+
-+/* --- STRUCTS --- */
-+/* tag part of the message */
-+struct vc_msg_tag {
-+ uint32_t tag_id; /* the tag ID for the temperature */
-+ uint32_t buffer_size; /* size of the buffer (should be 8) */
-+ uint32_t request_code; /* identifies message as a request (should be 0) */
-+ uint32_t id; /* extra ID field (should be 0) */
-+ uint32_t val; /* returned value of the temperature */
-+};
-+
-+/* message structure to be sent to videocore */
-+struct vc_msg {
-+ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */
-+ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */
-+ struct vc_msg_tag tag; /* the tag structure above to make */
-+ uint32_t end_tag; /* an end identifier, should be set to NULL */
-+};
-+
-+struct bcm2835_thermal_data {
-+ struct thermal_zone_device *thermal_dev;
-+ struct vc_msg msg;
-+};
-+
-+/* --- GLOBALS --- */
-+static struct bcm2835_thermal_data bcm2835_data;
-+
-+/* Thermal Device Operations */
-+static struct thermal_zone_device_ops ops;
-+
-+/* --- FUNCTIONS --- */
-+
-+static int bcm2835_get_temp_or_max(struct thermal_zone_device *thermal_dev, unsigned long *temp, unsigned tag_id)
-+{
-+ int result = -1, retry = 3;
-+ print_debug("IN");
-+
-+ *temp = 0;
-+ while (result != 0 && retry-- > 0) {
-+ /* wipe all previous message data */
-+ memset(&bcm2835_data.msg, 0, sizeof bcm2835_data.msg);
-+
-+ /* prepare message */
-+ bcm2835_data.msg.msg_size = sizeof bcm2835_data.msg;
-+ bcm2835_data.msg.tag.buffer_size = 8;
-+ bcm2835_data.msg.tag.tag_id = tag_id;
-+
-+ /* send the message */
-+ result = bcm_mailbox_property(&bcm2835_data.msg, sizeof bcm2835_data.msg);
-+ print_debug("Got %stemperature as %u (%d,%x)\n", tag_id==VC_TAG_GET_MAX_TEMP ? "max ":"", (uint)bcm2835_data.msg.tag.val, result, bcm2835_data.msg.request_code);
-+ if (!(bcm2835_data.msg.request_code & 0x80000000))
-+ result = -1;
-+ }
-+
-+ /* check if it was all ok and return the rate in milli degrees C */
-+ if (result == 0)
-+ *temp = (uint)bcm2835_data.msg.tag.val;
-+ else
-+ print_err("Failed to get temperature! (%x:%d)\n", tag_id, result);
-+ print_debug("OUT");
-+ return result;
-+}
-+
-+static int bcm2835_get_temp(struct thermal_zone_device *thermal_dev, unsigned long *temp)
-+{
-+ return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_TEMP);
-+}
-+
-+static int bcm2835_get_max_temp(struct thermal_zone_device *thermal_dev, int trip_num, unsigned long *temp)
-+{
-+ return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_MAX_TEMP);
-+}
-+
-+static int bcm2835_get_trip_type(struct thermal_zone_device * thermal_dev, int trip_num, enum thermal_trip_type *trip_type)
-+{
-+ *trip_type = THERMAL_TRIP_HOT;
-+ return 0;
-+}
-+
-+
-+static int bcm2835_get_mode(struct thermal_zone_device *thermal_dev, enum thermal_device_mode *dev_mode)
-+{
-+ *dev_mode = THERMAL_DEVICE_ENABLED;
-+ return 0;
-+}
-+
-+
-+static int bcm2835_thermal_probe(struct platform_device *pdev)
-+{
-+ print_debug("IN");
-+ print_debug("THERMAL Driver has been probed!");
-+
-+ /* check that the device isn't null!*/
-+ if(pdev == NULL)
-+ {
-+ print_debug("Platform device is empty!");
-+ return -ENODEV;
-+ }
-+
-+ if(!(bcm2835_data.thermal_dev = thermal_zone_device_register("bcm2835_thermal", 1, 0, NULL, &ops, NULL, 0, 0)))
-+ {
-+ print_debug("Unable to register the thermal device!");
-+ return -EFAULT;
-+ }
-+ return 0;
-+}
-+
-+
-+static int bcm2835_thermal_remove(struct platform_device *pdev)
-+{
-+ print_debug("IN");
-+
-+ thermal_zone_device_unregister(bcm2835_data.thermal_dev);
-+
-+ print_debug("OUT");
-+
-+ return 0;
-+}
-+
-+static struct thermal_zone_device_ops ops = {
-+ .get_temp = bcm2835_get_temp,
-+ .get_trip_temp = bcm2835_get_max_temp,
-+ .get_trip_type = bcm2835_get_trip_type,
-+ .get_mode = bcm2835_get_mode,
-+};
-+
-+/* Thermal Driver */
-+static struct platform_driver bcm2835_thermal_driver = {
-+ .probe = bcm2835_thermal_probe,
-+ .remove = bcm2835_thermal_remove,
-+ .driver = {
-+ .name = "bcm2835_thermal",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Dorian Peake");
-+MODULE_DESCRIPTION("Thermal driver for bcm2835 chip");
-+
-+module_platform_driver(bcm2835_thermal_driver);
-diff -Nur linux-3.12.38/drivers/thermal/intel_powerclamp.c linux-rpi/drivers/thermal/intel_powerclamp.c
---- linux-3.12.38/drivers/thermal/intel_powerclamp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/thermal/intel_powerclamp.c 2015-03-10 17:26:51.254216688 +0100
-@@ -426,6 +426,7 @@
- * allowed. thus jiffies are updated properly.
- */
- preempt_disable();
-+ tick_nohz_idle_enter();
- /* mwait until target jiffies is reached */
- while (time_before(jiffies, target_jiffies)) {
- unsigned long ecx = 1;
-@@ -443,6 +444,7 @@
- start_critical_timings();
- atomic_inc(&idle_wakeup_counter);
- }
-+ tick_nohz_idle_exit();
- preempt_enable_no_resched();
- }
- del_timer_sync(&wakeup_timer);
-diff -Nur linux-3.12.38/drivers/thermal/Kconfig linux-rpi/drivers/thermal/Kconfig
---- linux-3.12.38/drivers/thermal/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/thermal/Kconfig 2015-03-10 17:26:51.254216688 +0100
-@@ -181,6 +181,12 @@
- enforce idle time which results in more package C-state residency. The
- user interface is exposed via generic thermal framework.
-
-+config THERMAL_BCM2835
-+ tristate "BCM2835 Thermal Driver"
-+ help
-+ This will enable temperature monitoring for the Broadcom BCM2835
-+ chip. If built as a module, it will be called 'bcm2835-thermal'.
-+
- config X86_PKG_TEMP_THERMAL
- tristate "X86 package temperature thermal driver"
- depends on X86_THERMAL_VECTOR
-diff -Nur linux-3.12.38/drivers/thermal/Makefile linux-rpi/drivers/thermal/Makefile
---- linux-3.12.38/drivers/thermal/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/thermal/Makefile 2015-03-10 17:26:51.254216688 +0100
-@@ -27,5 +27,6 @@
- obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
- obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
- obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
-+obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o
- obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
- obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
-diff -Nur linux-3.12.38/drivers/tty/n_tty.c linux-rpi/drivers/tty/n_tty.c
---- linux-3.12.38/drivers/tty/n_tty.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/tty/n_tty.c 2015-03-10 17:26:51.258216688 +0100
-@@ -319,8 +319,7 @@
-
- static inline void put_tty_queue(unsigned char c, struct n_tty_data *ldata)
- {
-- *read_buf_addr(ldata, ldata->read_head) = c;
-- ldata->read_head++;
-+ *read_buf_addr(ldata, ldata->read_head++) = c;
- }
-
- /**
-diff -Nur linux-3.12.38/drivers/tty/serial/amba-pl011.c linux-rpi/drivers/tty/serial/amba-pl011.c
---- linux-3.12.38/drivers/tty/serial/amba-pl011.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/tty/serial/amba-pl011.c 2015-03-10 17:26:51.262216688 +0100
-@@ -84,7 +84,7 @@
-
- static unsigned int get_fifosize_arm(struct amba_device *dev)
- {
-- return amba_rev(dev) < 3 ? 16 : 32;
-+ return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
- }
-
- static struct vendor_data vendor_arm = {
-diff -Nur linux-3.12.38/drivers/tty/serial/samsung.c linux-rpi/drivers/tty/serial/samsung.c
---- linux-3.12.38/drivers/tty/serial/samsung.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/tty/serial/samsung.c 2015-03-10 17:26:51.270216688 +0100
-@@ -537,15 +537,11 @@
- unsigned int old)
- {
- struct s3c24xx_uart_port *ourport = to_ourport(port);
-- int timeout = 10000;
-
- ourport->pm_level = level;
-
- switch (level) {
- case 3:
-- while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
-- udelay(100);
--
- if (!IS_ERR(ourport->baudclk))
- clk_disable_unprepare(ourport->baudclk);
-
-diff -Nur linux-3.12.38/drivers/usb/class/cdc-acm.c linux-rpi/drivers/usb/class/cdc-acm.c
---- linux-3.12.38/drivers/usb/class/cdc-acm.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/class/cdc-acm.c 2015-03-10 17:26:51.282216688 +0100
-@@ -1079,11 +1079,10 @@
- } else {
- control_interface = usb_ifnum_to_if(usb_dev, union_header->bMasterInterface0);
- data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = union_header->bSlaveInterface0));
-- }
--
-- if (!control_interface || !data_interface) {
-- dev_dbg(&intf->dev, "no interfaces\n");
-- return -ENODEV;
-+ if (!control_interface || !data_interface) {
-+ dev_dbg(&intf->dev, "no interfaces\n");
-+ return -ENODEV;
-+ }
- }
-
- if (data_interface_num != call_interface_num)
-@@ -1358,7 +1357,6 @@
- &dev_attr_wCountryCodes);
- device_remove_file(&acm->control->dev,
- &dev_attr_iCountryCodeRelDate);
-- kfree(acm->country_codes);
- }
- device_remove_file(&acm->control->dev, &dev_attr_bmCapabilities);
- alloc_fail7:
-diff -Nur linux-3.12.38/drivers/usb/core/generic.c linux-rpi/drivers/usb/core/generic.c
---- linux-3.12.38/drivers/usb/core/generic.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/core/generic.c 2015-03-10 17:26:51.282216688 +0100
-@@ -152,6 +152,7 @@
- dev_warn(&udev->dev,
- "no configuration chosen from %d choice%s\n",
- num_configs, plural(num_configs));
-+ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
- }
- return i;
- }
-diff -Nur linux-3.12.38/drivers/usb/core/hub.c linux-rpi/drivers/usb/core/hub.c
---- linux-3.12.38/drivers/usb/core/hub.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/core/hub.c 2015-03-10 17:26:51.282216688 +0100
-@@ -4845,7 +4845,7 @@
- u16 status = 0;
- u16 unused;
-
-- dev_dbg(hub_dev, "over-current change on port "
-+ dev_notice(hub_dev, "over-current change on port "
- "%d\n", i);
- usb_clear_port_feature(hdev, i,
- USB_PORT_FEAT_C_OVER_CURRENT);
-diff -Nur linux-3.12.38/drivers/usb/core/message.c linux-rpi/drivers/usb/core/message.c
---- linux-3.12.38/drivers/usb/core/message.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/core/message.c 2015-03-10 17:26:51.282216688 +0100
-@@ -1885,6 +1885,85 @@
- if (cp->string == NULL &&
- !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
- cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
-+/* Uncomment this define to enable the HS Electrical Test support */
-+#define DWC_HS_ELECT_TST 1
-+#ifdef DWC_HS_ELECT_TST
-+ /* Here we implement the HS Electrical Test support. The
-+ * tester uses a vendor ID of 0x1A0A to indicate we should
-+ * run a special test sequence. The product ID tells us
-+ * which sequence to run. We invoke the test sequence by
-+ * sending a non-standard SetFeature command to our root
-+ * hub port. Our dwc_otg_hcd_hub_control() routine will
-+ * recognize the command and perform the desired test
-+ * sequence.
-+ */
-+ if (dev->descriptor.idVendor == 0x1A0A) {
-+ /* HSOTG Electrical Test */
-+ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
-+
-+ if (dev->bus && dev->bus->root_hub) {
-+ struct usb_device *hdev = dev->bus->root_hub;
-+ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
-+
-+ switch (dev->descriptor.idProduct) {
-+ case 0x0101: /* TEST_SE0_NAK */
-+ dev_warn(&dev->dev, "TEST_SE0_NAK\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0102: /* TEST_J */
-+ dev_warn(&dev->dev, "TEST_J\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0103: /* TEST_K */
-+ dev_warn(&dev->dev, "TEST_K\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0104: /* TEST_PACKET */
-+ dev_warn(&dev->dev, "TEST_PACKET\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0105: /* TEST_FORCE_ENABLE */
-+ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */
-+ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
-+ break;
-+
-+ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
-+ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
-+ break;
-+
-+ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
-+ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
-+ }
-+ }
-+ }
-+#endif /* DWC_HS_ELECT_TST */
-
- /* Now that the interfaces are installed, re-enable LPM. */
- usb_unlocked_enable_lpm(dev);
-diff -Nur linux-3.12.38/drivers/usb/core/otg_whitelist.h linux-rpi/drivers/usb/core/otg_whitelist.h
---- linux-3.12.38/drivers/usb/core/otg_whitelist.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/core/otg_whitelist.h 2015-03-10 17:26:51.282216688 +0100
-@@ -19,33 +19,82 @@
- static struct usb_device_id whitelist_table [] = {
-
- /* hubs are optional in OTG, but very handy ... */
-+#define CERT_WITHOUT_HUBS
-+#if defined(CERT_WITHOUT_HUBS)
-+{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
-+#else
- { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
- { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
-+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
-+#endif
-
- #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
- /* FIXME actually, printers are NOT supposed to use device classes;
- * they're supposed to use interface classes...
- */
--{ USB_DEVICE_INFO(7, 1, 1) },
--{ USB_DEVICE_INFO(7, 1, 2) },
--{ USB_DEVICE_INFO(7, 1, 3) },
-+//{ USB_DEVICE_INFO(7, 1, 1) },
-+//{ USB_DEVICE_INFO(7, 1, 2) },
-+//{ USB_DEVICE_INFO(7, 1, 3) },
- #endif
-
- #ifdef CONFIG_USB_NET_CDCETHER
- /* Linux-USB CDC Ethernet gadget */
--{ USB_DEVICE(0x0525, 0xa4a1), },
-+//{ USB_DEVICE(0x0525, 0xa4a1), },
- /* Linux-USB CDC Ethernet + RNDIS gadget */
--{ USB_DEVICE(0x0525, 0xa4a2), },
-+//{ USB_DEVICE(0x0525, 0xa4a2), },
- #endif
-
- #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
- /* gadget zero, for testing */
--{ USB_DEVICE(0x0525, 0xa4a0), },
-+//{ USB_DEVICE(0x0525, 0xa4a0), },
- #endif
-
-+/* OPT Tester */
-+{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
-+{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
-+{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
-+{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
-+{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
-+{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */
-+{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
-+{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
-+
-+/* Sony cameras */
-+{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
-+
-+/* Memory Devices */
-+//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
-+//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
-+//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
-+//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */
-+{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
-+//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
-+
-+/* HP Printers */
-+//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
-+//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
-+
-+/* Speakers */
-+//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
-+//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
-+
- { } /* Terminating entry */
- };
-
-+static inline void report_errors(struct usb_device *dev)
-+{
-+ /* OTG MESSAGE: report errors here, customize to match your product */
-+ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
-+ le16_to_cpu(dev->descriptor.idVendor),
-+ le16_to_cpu(dev->descriptor.idProduct));
-+ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
-+ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
-+ } else {
-+ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
-+ }
-+}
-+
-+
- static int is_targeted(struct usb_device *dev)
- {
- struct usb_device_id *id = whitelist_table;
-@@ -55,58 +104,83 @@
- return 1;
-
- /* HNP test device is _never_ targeted (see OTG spec 6.6.6) */
-- if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a &&
-- le16_to_cpu(dev->descriptor.idProduct) == 0xbadd))
-- return 0;
-+ if (dev->descriptor.idVendor == 0x1a0a &&
-+ dev->descriptor.idProduct == 0xbadd) {
-+ return 0;
-+ } else if (!enable_whitelist) {
-+ return 1;
-+ } else {
-
-- /* NOTE: can't use usb_match_id() since interface caches
-- * aren't set up yet. this is cut/paste from that code.
-- */
-- for (id = whitelist_table; id->match_flags; id++) {
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
-- id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
-- continue;
--
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
-- id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
-- continue;
--
-- /* No need to test id->bcdDevice_lo != 0, since 0 is never
-- greater than any unsigned number. */
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
-- (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
-- continue;
--
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
-- (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
-- continue;
--
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
-- (id->bDeviceClass != dev->descriptor.bDeviceClass))
-- continue;
--
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
-- (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
-- continue;
--
-- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
-- (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
-- continue;
-+#ifdef DEBUG
-+ dev_dbg(&dev->dev, "device V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
-+ dev->descriptor.idVendor,
-+ dev->descriptor.idProduct,
-+ dev->descriptor.bDeviceClass,
-+ dev->descriptor.bDeviceSubClass,
-+ dev->descriptor.bDeviceProtocol);
-+#endif
-
- return 1;
-+ /* NOTE: can't use usb_match_id() since interface caches
-+ * aren't set up yet. this is cut/paste from that code.
-+ */
-+ for (id = whitelist_table; id->match_flags; id++) {
-+#ifdef DEBUG
-+ dev_dbg(&dev->dev,
-+ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
-+ id->idVendor,
-+ id->idProduct,
-+ id->bDeviceClass,
-+ id->bDeviceSubClass,
-+ id->bDeviceProtocol);
-+#endif
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
-+ id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
-+ id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
-+ continue;
-+
-+ /* No need to test id->bcdDevice_lo != 0, since 0 is never
-+ greater than any unsigned number. */
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
-+ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
-+ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
-+ (id->bDeviceClass != dev->descriptor.bDeviceClass))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
-+ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
-+ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
-+ continue;
-+
-+ return 1;
-+ }
- }
-
- /* add other match criteria here ... */
-
--
-- /* OTG MESSAGE: report errors here, customize to match your product */
-- dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
-- le16_to_cpu(dev->descriptor.idVendor),
-- le16_to_cpu(dev->descriptor.idProduct));
- #ifdef CONFIG_USB_OTG_WHITELIST
-+ report_errors(dev);
- return 0;
- #else
-- return 1;
-+ if (enable_whitelist) {
-+ report_errors(dev);
-+ return 0;
-+ } else {
-+ return 1;
-+ }
- #endif
- }
-
-diff -Nur linux-3.12.38/drivers/usb/dwc3/gadget.c linux-rpi/drivers/usb/dwc3/gadget.c
---- linux-3.12.38/drivers/usb/dwc3/gadget.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/dwc3/gadget.c 2015-03-10 17:26:51.286216687 +0100
-@@ -887,7 +887,8 @@
-
- if (i == (request->num_mapped_sgs - 1) ||
- sg_is_last(s)) {
-- if (list_empty(&dep->request_list))
-+ if (list_is_last(&req->list,
-+ &dep->request_list))
- last_one = true;
- chain = false;
- }
-@@ -905,9 +906,6 @@
- if (last_one)
- break;
- }
--
-- if (last_one)
-- break;
- } else {
- dma = req->request.dma;
- length = req->request.length;
-diff -Nur linux-3.12.38/drivers/usb/gadget/file_storage.c linux-rpi/drivers/usb/gadget/file_storage.c
---- linux-3.12.38/drivers/usb/gadget/file_storage.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/gadget/file_storage.c 2015-03-09 10:39:33.198893718 +0100
-@@ -0,0 +1,3676 @@
-+/*
-+ * file_storage.c -- File-backed USB Storage Gadget, for USB development
-+ *
-+ * Copyright (C) 2003-2008 Alan Stern
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * The File-backed Storage Gadget acts as a USB Mass Storage device,
-+ * appearing to the host as a disk drive or as a CD-ROM drive. In addition
-+ * to providing an example of a genuinely useful gadget driver for a USB
-+ * device, it also illustrates a technique of double-buffering for increased
-+ * throughput. Last but not least, it gives an easy way to probe the
-+ * behavior of the Mass Storage drivers in a USB host.
-+ *
-+ * Backing storage is provided by a regular file or a block device, specified
-+ * by the "file" module parameter. Access can be limited to read-only by
-+ * setting the optional "ro" module parameter. (For CD-ROM emulation,
-+ * access is always read-only.) The gadget will indicate that it has
-+ * removable media if the optional "removable" module parameter is set.
-+ *
-+ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
-+ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
-+ * by the optional "transport" module parameter. It also supports the
-+ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
-+ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
-+ * the optional "protocol" module parameter. In addition, the default
-+ * Vendor ID, Product ID, release number and serial number can be overridden.
-+ *
-+ * There is support for multiple logical units (LUNs), each of which has
-+ * its own backing file. The number of LUNs can be set using the optional
-+ * "luns" module parameter (anywhere from 1 to 8), and the corresponding
-+ * files are specified using comma-separated lists for "file" and "ro".
-+ * The default number of LUNs is taken from the number of "file" elements;
-+ * it is 1 if "file" is not given. If "removable" is not set then a backing
-+ * file must be specified for each LUN. If it is set, then an unspecified
-+ * or empty backing filename means the LUN's medium is not loaded. Ideally
-+ * each LUN would be settable independently as a disk drive or a CD-ROM
-+ * drive, but currently all LUNs have to be the same type. The CD-ROM
-+ * emulation includes a single data track and no audio tracks; hence there
-+ * need be only one backing file per LUN.
-+ *
-+ * Requirements are modest; only a bulk-in and a bulk-out endpoint are
-+ * needed (an interrupt-out endpoint is also needed for CBI). The memory
-+ * requirement amounts to two 16K buffers, size configurable by a parameter.
-+ * Support is included for both full-speed and high-speed operation.
-+ *
-+ * Note that the driver is slightly non-portable in that it assumes a
-+ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
-+ * interrupt-in endpoints. With most device controllers this isn't an
-+ * issue, but there may be some with hardware restrictions that prevent
-+ * a buffer from being used by more than one endpoint.
-+ *
-+ * Module options:
-+ *
-+ * file=filename[,filename...]
-+ * Required if "removable" is not set, names of
-+ * the files or block devices used for
-+ * backing storage
-+ * serial=HHHH... Required serial number (string of hex chars)
-+ * ro=b[,b...] Default false, booleans for read-only access
-+ * removable Default false, boolean for removable media
-+ * luns=N Default N = number of filenames, number of
-+ * LUNs to support
-+ * nofua=b[,b...] Default false, booleans for ignore FUA flag
-+ * in SCSI WRITE(10,12) commands
-+ * stall Default determined according to the type of
-+ * USB device controller (usually true),
-+ * boolean to permit the driver to halt
-+ * bulk endpoints
-+ * cdrom Default false, boolean for whether to emulate
-+ * a CD-ROM drive
-+ * transport=XXX Default BBB, transport name (CB, CBI, or BBB)
-+ * protocol=YYY Default SCSI, protocol name (RBC, 8020 or
-+ * ATAPI, QIC, UFI, 8070, or SCSI;
-+ * also 1 - 6)
-+ * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID
-+ * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID
-+ * release=0xRRRR Override the USB release number (bcdDevice)
-+ * buflen=N Default N=16384, buffer size used (will be
-+ * rounded down to a multiple of
-+ * PAGE_CACHE_SIZE)
-+ *
-+ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
-+ * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
-+ * default values are used for everything else.
-+ *
-+ * The pathnames of the backing files and the ro settings are available in
-+ * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
-+ * the gadget's sysfs directory. If the "removable" option is set, writing to
-+ * these files will simulate ejecting/loading the medium (writing an empty
-+ * line means eject) and adjusting a write-enable tab. Changes to the ro
-+ * setting are not allowed when the medium is loaded or if CD-ROM emulation
-+ * is being used.
-+ *
-+ * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
-+ * The driver's SCSI command interface was based on the "Information
-+ * technology - Small Computer System Interface - 2" document from
-+ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
-+ * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. The single exception
-+ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
-+ * "Universal Serial Bus Mass Storage Class UFI Command Specification"
-+ * document, Revision 1.0, December 14, 1998, available at
-+ * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
-+ */
-+
-+
-+/*
-+ * Driver Design
-+ *
-+ * The FSG driver is fairly straightforward. There is a main kernel
-+ * thread that handles most of the work. Interrupt routines field
-+ * callbacks from the controller driver: bulk- and interrupt-request
-+ * completion notifications, endpoint-0 events, and disconnect events.
-+ * Completion events are passed to the main thread by wakeup calls. Many
-+ * ep0 requests are handled at interrupt time, but SetInterface,
-+ * SetConfiguration, and device reset requests are forwarded to the
-+ * thread in the form of "exceptions" using SIGUSR1 signals (since they
-+ * should interrupt any ongoing file I/O operations).
-+ *
-+ * The thread's main routine implements the standard command/data/status
-+ * parts of a SCSI interaction. It and its subroutines are full of tests
-+ * for pending signals/exceptions -- all this polling is necessary since
-+ * the kernel has no setjmp/longjmp equivalents. (Maybe this is an
-+ * indication that the driver really wants to be running in userspace.)
-+ * An important point is that so long as the thread is alive it keeps an
-+ * open reference to the backing file. This will prevent unmounting
-+ * the backing file's underlying filesystem and could cause problems
-+ * during system shutdown, for example. To prevent such problems, the
-+ * thread catches INT, TERM, and KILL signals and converts them into
-+ * an EXIT exception.
-+ *
-+ * In normal operation the main thread is started during the gadget's
-+ * fsg_bind() callback and stopped during fsg_unbind(). But it can also
-+ * exit when it receives a signal, and there's no point leaving the
-+ * gadget running when the thread is dead. So just before the thread
-+ * exits, it deregisters the gadget driver. This makes things a little
-+ * tricky: The driver is deregistered at two places, and the exiting
-+ * thread can indirectly call fsg_unbind() which in turn can tell the
-+ * thread to exit. The first problem is resolved through the use of the
-+ * REGISTERED atomic bitflag; the driver will only be deregistered once.
-+ * The second problem is resolved by having fsg_unbind() check
-+ * fsg->state; it won't try to stop the thread if the state is already
-+ * FSG_STATE_TERMINATED.
-+ *
-+ * To provide maximum throughput, the driver uses a circular pipeline of
-+ * buffer heads (struct fsg_buffhd). In principle the pipeline can be
-+ * arbitrarily long; in practice the benefits don't justify having more
-+ * than 2 stages (i.e., double buffering). But it helps to think of the
-+ * pipeline as being a long one. Each buffer head contains a bulk-in and
-+ * a bulk-out request pointer (since the buffer can be used for both
-+ * output and input -- directions always are given from the host's
-+ * point of view) as well as a pointer to the buffer and various state
-+ * variables.
-+ *
-+ * Use of the pipeline follows a simple protocol. There is a variable
-+ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
-+ * At any time that buffer head may still be in use from an earlier
-+ * request, so each buffer head has a state variable indicating whether
-+ * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the
-+ * buffer head to be EMPTY, filling the buffer either by file I/O or by
-+ * USB I/O (during which the buffer head is BUSY), and marking the buffer
-+ * head FULL when the I/O is complete. Then the buffer will be emptied
-+ * (again possibly by USB I/O, during which it is marked BUSY) and
-+ * finally marked EMPTY again (possibly by a completion routine).
-+ *
-+ * A module parameter tells the driver to avoid stalling the bulk
-+ * endpoints wherever the transport specification allows. This is
-+ * necessary for some UDCs like the SuperH, which cannot reliably clear a
-+ * halt on a bulk endpoint. However, under certain circumstances the
-+ * Bulk-only specification requires a stall. In such cases the driver
-+ * will halt the endpoint and set a flag indicating that it should clear
-+ * the halt in software during the next device reset. Hopefully this
-+ * will permit everything to work correctly. Furthermore, although the
-+ * specification allows the bulk-out endpoint to halt when the host sends
-+ * too much data, implementing this would cause an unavoidable race.
-+ * The driver will always use the "no-stall" approach for OUT transfers.
-+ *
-+ * One subtle point concerns sending status-stage responses for ep0
-+ * requests. Some of these requests, such as device reset, can involve
-+ * interrupting an ongoing file I/O operation, which might take an
-+ * arbitrarily long time. During that delay the host might give up on
-+ * the original ep0 request and issue a new one. When that happens the
-+ * driver should not notify the host about completion of the original
-+ * request, as the host will no longer be waiting for it. So the driver
-+ * assigns to each ep0 request a unique tag, and it keeps track of the
-+ * tag value of the request associated with a long-running exception
-+ * (device-reset, interface-change, or configuration-change). When the
-+ * exception handler is finished, the status-stage response is submitted
-+ * only if the current ep0 request tag is equal to the exception request
-+ * tag. Thus only the most recently received ep0 request will get a
-+ * status-stage response.
-+ *
-+ * Warning: This driver source file is too long. It ought to be split up
-+ * into a header file plus about 3 separate .c files, to handle the details
-+ * of the Gadget, USB Mass Storage, and SCSI protocols.
-+ */
-+
-+
-+/* #define VERBOSE_DEBUG */
-+/* #define DUMP_MSGS */
-+
-+
-+#include <linux/blkdev.h>
-+#include <linux/completion.h>
-+#include <linux/dcache.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/fcntl.h>
-+#include <linux/file.h>
-+#include <linux/fs.h>
-+#include <linux/kref.h>
-+#include <linux/kthread.h>
-+#include <linux/limits.h>
-+#include <linux/module.h>
-+#include <linux/rwsem.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/string.h>
-+#include <linux/freezer.h>
-+#include <linux/utsname.h>
-+
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+
-+#include "gadget_chips.h"
-+
-+
-+
-+/*
-+ * Kbuild is not very cooperative with respect to linking separately
-+ * compiled library objects into one module. So for now we won't use
-+ * separate compilation ... ensuring init/exit sections work to shrink
-+ * the runtime footprint, and giving us at least some parts of what
-+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
-+ */
-+#include "usbstring.c"
-+#include "config.c"
-+#include "epautoconf.c"
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_DESC "File-backed Storage Gadget"
-+#define DRIVER_NAME "g_file_storage"
-+#define DRIVER_VERSION "1 September 2010"
-+
-+static char fsg_string_manufacturer[64];
-+static const char fsg_string_product[] = DRIVER_DESC;
-+static const char fsg_string_config[] = "Self-powered";
-+static const char fsg_string_interface[] = "Mass Storage";
-+
-+
-+#include "storage_common.c"
-+
-+
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_AUTHOR("Alan Stern");
-+MODULE_LICENSE("Dual BSD/GPL");
-+
-+/*
-+ * This driver assumes self-powered hardware and has no way for users to
-+ * trigger remote wakeup. It uses autoconfiguration to select endpoints
-+ * and endpoint addresses.
-+ */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/* Encapsulate the module parameter settings */
-+
-+static struct {
-+ char *file[FSG_MAX_LUNS];
-+ char *serial;
-+ bool ro[FSG_MAX_LUNS];
-+ bool nofua[FSG_MAX_LUNS];
-+ unsigned int num_filenames;
-+ unsigned int num_ros;
-+ unsigned int num_nofuas;
-+ unsigned int nluns;
-+
-+ bool removable;
-+ bool can_stall;
-+ bool cdrom;
-+
-+ char *transport_parm;
-+ char *protocol_parm;
-+ unsigned short vendor;
-+ unsigned short product;
-+ unsigned short release;
-+ unsigned int buflen;
-+
-+ int transport_type;
-+ char *transport_name;
-+ int protocol_type;
-+ char *protocol_name;
-+
-+} mod_data = { // Default values
-+ .transport_parm = "BBB",
-+ .protocol_parm = "SCSI",
-+ .removable = 0,
-+ .can_stall = 1,
-+ .cdrom = 0,
-+ .vendor = FSG_VENDOR_ID,
-+ .product = FSG_PRODUCT_ID,
-+ .release = 0xffff, // Use controller chip type
-+ .buflen = 16384,
-+ };
-+
-+
-+module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
-+ S_IRUGO);
-+MODULE_PARM_DESC(file, "names of backing files or devices");
-+
-+module_param_named(serial, mod_data.serial, charp, S_IRUGO);
-+MODULE_PARM_DESC(serial, "USB serial number");
-+
-+module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
-+MODULE_PARM_DESC(ro, "true to force read-only");
-+
-+module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
-+ S_IRUGO);
-+MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
-+
-+module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
-+MODULE_PARM_DESC(luns, "number of LUNs");
-+
-+module_param_named(removable, mod_data.removable, bool, S_IRUGO);
-+MODULE_PARM_DESC(removable, "true to simulate removable media");
-+
-+module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
-+MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
-+
-+module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
-+MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
-+
-+/* In the non-TEST version, only the module parameters listed above
-+ * are available. */
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+
-+module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
-+MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
-+
-+module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
-+MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
-+ "8070, or SCSI)");
-+
-+module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
-+MODULE_PARM_DESC(vendor, "USB Vendor ID");
-+
-+module_param_named(product, mod_data.product, ushort, S_IRUGO);
-+MODULE_PARM_DESC(product, "USB Product ID");
-+
-+module_param_named(release, mod_data.release, ushort, S_IRUGO);
-+MODULE_PARM_DESC(release, "USB release number");
-+
-+module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
-+MODULE_PARM_DESC(buflen, "I/O buffer size");
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*
-+ * These definitions will permit the compiler to avoid generating code for
-+ * parts of the driver that aren't used in the non-TEST version. Even gcc
-+ * can recognize when a test of a constant expression yields a dead code
-+ * path.
-+ */
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+
-+#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK)
-+#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI)
-+#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI)
-+
-+#else
-+
-+#define transport_is_bbb() 1
-+#define transport_is_cbi() 0
-+#define protocol_is_scsi() 1
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+struct fsg_dev {
-+ /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
-+ spinlock_t lock;
-+ struct usb_gadget *gadget;
-+
-+ /* filesem protects: backing files in use */
-+ struct rw_semaphore filesem;
-+
-+ /* reference counting: wait until all LUNs are released */
-+ struct kref ref;
-+
-+ struct usb_ep *ep0; // Handy copy of gadget->ep0
-+ struct usb_request *ep0req; // For control responses
-+ unsigned int ep0_req_tag;
-+ const char *ep0req_name;
-+
-+ struct usb_request *intreq; // For interrupt responses
-+ int intreq_busy;
-+ struct fsg_buffhd *intr_buffhd;
-+
-+ unsigned int bulk_out_maxpacket;
-+ enum fsg_state state; // For exception handling
-+ unsigned int exception_req_tag;
-+
-+ u8 config, new_config;
-+
-+ unsigned int running : 1;
-+ unsigned int bulk_in_enabled : 1;
-+ unsigned int bulk_out_enabled : 1;
-+ unsigned int intr_in_enabled : 1;
-+ unsigned int phase_error : 1;
-+ unsigned int short_packet_received : 1;
-+ unsigned int bad_lun_okay : 1;
-+
-+ unsigned long atomic_bitflags;
-+#define REGISTERED 0
-+#define IGNORE_BULK_OUT 1
-+#define SUSPENDED 2
-+
-+ struct usb_ep *bulk_in;
-+ struct usb_ep *bulk_out;
-+ struct usb_ep *intr_in;
-+
-+ struct fsg_buffhd *next_buffhd_to_fill;
-+ struct fsg_buffhd *next_buffhd_to_drain;
-+
-+ int thread_wakeup_needed;
-+ struct completion thread_notifier;
-+ struct task_struct *thread_task;
-+
-+ int cmnd_size;
-+ u8 cmnd[MAX_COMMAND_SIZE];
-+ enum data_direction data_dir;
-+ u32 data_size;
-+ u32 data_size_from_cmnd;
-+ u32 tag;
-+ unsigned int lun;
-+ u32 residue;
-+ u32 usb_amount_left;
-+
-+ /* The CB protocol offers no way for a host to know when a command
-+ * has completed. As a result the next command may arrive early,
-+ * and we will still have to handle it. For that reason we need
-+ * a buffer to store new commands when using CB (or CBI, which
-+ * does not oblige a host to wait for command completion either). */
-+ int cbbuf_cmnd_size;
-+ u8 cbbuf_cmnd[MAX_COMMAND_SIZE];
-+
-+ unsigned int nluns;
-+ struct fsg_lun *luns;
-+ struct fsg_lun *curlun;
-+ /* Must be the last entry */
-+ struct fsg_buffhd buffhds[];
-+};
-+
-+typedef void (*fsg_routine_t)(struct fsg_dev *);
-+
-+static int exception_in_progress(struct fsg_dev *fsg)
-+{
-+ return (fsg->state > FSG_STATE_IDLE);
-+}
-+
-+/* Make bulk-out requests be divisible by the maxpacket size */
-+static void set_bulk_out_req_length(struct fsg_dev *fsg,
-+ struct fsg_buffhd *bh, unsigned int length)
-+{
-+ unsigned int rem;
-+
-+ bh->bulk_out_intended_length = length;
-+ rem = length % fsg->bulk_out_maxpacket;
-+ if (rem > 0)
-+ length += fsg->bulk_out_maxpacket - rem;
-+ bh->outreq->length = length;
-+}
-+
-+static struct fsg_dev *the_fsg;
-+static struct usb_gadget_driver fsg_driver;
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
-+{
-+ const char *name;
-+
-+ if (ep == fsg->bulk_in)
-+ name = "bulk-in";
-+ else if (ep == fsg->bulk_out)
-+ name = "bulk-out";
-+ else
-+ name = ep->name;
-+ DBG(fsg, "%s set halt\n", name);
-+ return usb_ep_set_halt(ep);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full) configuration
-+ * descriptors are built on demand. Also the (static) config and interface
-+ * descriptors are adjusted during fsg_bind().
-+ */
-+
-+/* There is only one configuration. */
-+#define CONFIG_VALUE 1
-+
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+
-+ .bcdUSB = cpu_to_le16(0x0200),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+
-+ /* The next three values can be overridden by module parameters */
-+ .idVendor = cpu_to_le16(FSG_VENDOR_ID),
-+ .idProduct = cpu_to_le16(FSG_PRODUCT_ID),
-+ .bcdDevice = cpu_to_le16(0xffff),
-+
-+ .iManufacturer = FSG_STRING_MANUFACTURER,
-+ .iProduct = FSG_STRING_PRODUCT,
-+ .iSerialNumber = FSG_STRING_SERIAL,
-+ .bNumConfigurations = 1,
-+};
-+
-+static struct usb_config_descriptor
-+config_desc = {
-+ .bLength = sizeof config_desc,
-+ .bDescriptorType = USB_DT_CONFIG,
-+
-+ /* wTotalLength computed by usb_gadget_config_buf() */
-+ .bNumInterfaces = 1,
-+ .bConfigurationValue = CONFIG_VALUE,
-+ .iConfiguration = FSG_STRING_CONFIG,
-+ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
-+ .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2,
-+};
-+
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+ .bLength = sizeof dev_qualifier,
-+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
-+
-+ .bcdUSB = cpu_to_le16(0x0200),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+
-+ .bNumConfigurations = 1,
-+};
-+
-+static int populate_bos(struct fsg_dev *fsg, u8 *buf)
-+{
-+ memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
-+ buf += USB_DT_BOS_SIZE;
-+
-+ memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
-+ buf += USB_DT_USB_EXT_CAP_SIZE;
-+
-+ memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
-+
-+ return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
-+ + USB_DT_USB_EXT_CAP_SIZE;
-+}
-+
-+/*
-+ * Config descriptors must agree with the code that sets configurations
-+ * and with code managing interfaces and their altsettings. They must
-+ * also handle different speeds and other-speed requests.
-+ */
-+static int populate_config_buf(struct usb_gadget *gadget,
-+ u8 *buf, u8 type, unsigned index)
-+{
-+ enum usb_device_speed speed = gadget->speed;
-+ int len;
-+ const struct usb_descriptor_header **function;
-+
-+ if (index > 0)
-+ return -EINVAL;
-+
-+ if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
-+ speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
-+ function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
-+ ? (const struct usb_descriptor_header **)fsg_hs_function
-+ : (const struct usb_descriptor_header **)fsg_fs_function;
-+
-+ /* for now, don't advertise srp-only devices */
-+ if (!gadget_is_otg(gadget))
-+ function++;
-+
-+ len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
-+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+ return len;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* These routines may be called in process context or in_irq */
-+
-+/* Caller must hold fsg->lock */
-+static void wakeup_thread(struct fsg_dev *fsg)
-+{
-+ /* Tell the main thread that something has happened */
-+ fsg->thread_wakeup_needed = 1;
-+ if (fsg->thread_task)
-+ wake_up_process(fsg->thread_task);
-+}
-+
-+
-+static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
-+{
-+ unsigned long flags;
-+
-+ /* Do nothing if a higher-priority exception is already in progress.
-+ * If a lower-or-equal priority exception is in progress, preempt it
-+ * and notify the main thread by sending it a signal. */
-+ spin_lock_irqsave(&fsg->lock, flags);
-+ if (fsg->state <= new_state) {
-+ fsg->exception_req_tag = fsg->ep0_req_tag;
-+ fsg->state = new_state;
-+ if (fsg->thread_task)
-+ send_sig_info(SIGUSR1, SEND_SIG_FORCED,
-+ fsg->thread_task);
-+ }
-+ spin_unlock_irqrestore(&fsg->lock, flags);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* The disconnect callback and ep0 routines. These always run in_irq,
-+ * except that ep0_queue() is called in the main thread to acknowledge
-+ * completion of various requests: set config, set interface, and
-+ * Bulk-only device reset. */
-+
-+static void fsg_disconnect(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+
-+ DBG(fsg, "disconnect or port reset\n");
-+ raise_exception(fsg, FSG_STATE_DISCONNECT);
-+}
-+
-+
-+static int ep0_queue(struct fsg_dev *fsg)
-+{
-+ int rc;
-+
-+ rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
-+ if (rc != 0 && rc != -ESHUTDOWN) {
-+
-+ /* We can't do much more than wait for a reset */
-+ WARNING(fsg, "error in submission: %s --> %d\n",
-+ fsg->ep0->name, rc);
-+ }
-+ return rc;
-+}
-+
-+static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+
-+ if (req->actual > 0)
-+ dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
-+ if (req->status || req->actual != req->length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual, req->length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ if (req->status == 0 && req->context)
-+ ((fsg_routine_t) (req->context))(fsg);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Bulk and interrupt endpoint completion handlers.
-+ * These always run in_irq. */
-+
-+static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+ struct fsg_buffhd *bh = req->context;
-+
-+ if (req->status || req->actual != req->length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual, req->length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ /* Hold the lock while we update the request and buffer states */
-+ smp_wmb();
-+ spin_lock(&fsg->lock);
-+ bh->inreq_busy = 0;
-+ bh->state = BUF_STATE_EMPTY;
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+ struct fsg_buffhd *bh = req->context;
-+
-+ dump_msg(fsg, "bulk-out", req->buf, req->actual);
-+ if (req->status || req->actual != bh->bulk_out_intended_length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual,
-+ bh->bulk_out_intended_length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ /* Hold the lock while we update the request and buffer states */
-+ smp_wmb();
-+ spin_lock(&fsg->lock);
-+ bh->outreq_busy = 0;
-+ bh->state = BUF_STATE_FULL;
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+ struct fsg_buffhd *bh = req->context;
-+
-+ if (req->status || req->actual != req->length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual, req->length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ /* Hold the lock while we update the request and buffer states */
-+ smp_wmb();
-+ spin_lock(&fsg->lock);
-+ fsg->intreq_busy = 0;
-+ bh->state = BUF_STATE_EMPTY;
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+#else
-+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{}
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Ep0 class-specific handlers. These always run in_irq. */
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct usb_request *req = fsg->ep0req;
-+ static u8 cbi_reset_cmnd[6] = {
-+ SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
-+
-+ /* Error in command transfer? */
-+ if (req->status || req->length != req->actual ||
-+ req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
-+
-+ /* Not all controllers allow a protocol stall after
-+ * receiving control-out data, but we'll try anyway. */
-+ fsg_set_halt(fsg, fsg->ep0);
-+ return; // Wait for reset
-+ }
-+
-+ /* Is it the special reset command? */
-+ if (req->actual >= sizeof cbi_reset_cmnd &&
-+ memcmp(req->buf, cbi_reset_cmnd,
-+ sizeof cbi_reset_cmnd) == 0) {
-+
-+ /* Raise an exception to stop the current operation
-+ * and reinitialize our state. */
-+ DBG(fsg, "cbi reset request\n");
-+ raise_exception(fsg, FSG_STATE_RESET);
-+ return;
-+ }
-+
-+ VDBG(fsg, "CB[I] accept device-specific command\n");
-+ spin_lock(&fsg->lock);
-+
-+ /* Save the command for later */
-+ if (fsg->cbbuf_cmnd_size)
-+ WARNING(fsg, "CB[I] overwriting previous command\n");
-+ fsg->cbbuf_cmnd_size = req->actual;
-+ memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
-+
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+#else
-+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{}
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+static int class_setup_req(struct fsg_dev *fsg,
-+ const struct usb_ctrlrequest *ctrl)
-+{
-+ struct usb_request *req = fsg->ep0req;
-+ int value = -EOPNOTSUPP;
-+ u16 w_index = le16_to_cpu(ctrl->wIndex);
-+ u16 w_value = le16_to_cpu(ctrl->wValue);
-+ u16 w_length = le16_to_cpu(ctrl->wLength);
-+
-+ if (!fsg->config)
-+ return value;
-+
-+ /* Handle Bulk-only class-specific requests */
-+ if (transport_is_bbb()) {
-+ switch (ctrl->bRequest) {
-+
-+ case US_BULK_RESET_REQUEST:
-+ if (ctrl->bRequestType != (USB_DIR_OUT |
-+ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+ break;
-+ if (w_index != 0 || w_value != 0 || w_length != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+
-+ /* Raise an exception to stop the current operation
-+ * and reinitialize our state. */
-+ DBG(fsg, "bulk reset request\n");
-+ raise_exception(fsg, FSG_STATE_RESET);
-+ value = DELAYED_STATUS;
-+ break;
-+
-+ case US_BULK_GET_MAX_LUN:
-+ if (ctrl->bRequestType != (USB_DIR_IN |
-+ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+ break;
-+ if (w_index != 0 || w_value != 0 || w_length != 1) {
-+ value = -EDOM;
-+ break;
-+ }
-+ VDBG(fsg, "get max LUN\n");
-+ *(u8 *) req->buf = fsg->nluns - 1;
-+ value = 1;
-+ break;
-+ }
-+ }
-+
-+ /* Handle CBI class-specific requests */
-+ else {
-+ switch (ctrl->bRequest) {
-+
-+ case USB_CBI_ADSC_REQUEST:
-+ if (ctrl->bRequestType != (USB_DIR_OUT |
-+ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+ break;
-+ if (w_index != 0 || w_value != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ if (w_length > MAX_COMMAND_SIZE) {
-+ value = -EOVERFLOW;
-+ break;
-+ }
-+ value = w_length;
-+ fsg->ep0req->context = received_cbi_adsc;
-+ break;
-+ }
-+ }
-+
-+ if (value == -EOPNOTSUPP)
-+ VDBG(fsg,
-+ "unknown class-specific control req "
-+ "%02x.%02x v%04x i%04x l%u\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ le16_to_cpu(ctrl->wValue), w_index, w_length);
-+ return value;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Ep0 standard request handlers. These always run in_irq. */
-+
-+static int standard_setup_req(struct fsg_dev *fsg,
-+ const struct usb_ctrlrequest *ctrl)
-+{
-+ struct usb_request *req = fsg->ep0req;
-+ int value = -EOPNOTSUPP;
-+ u16 w_index = le16_to_cpu(ctrl->wIndex);
-+ u16 w_value = le16_to_cpu(ctrl->wValue);
-+
-+ /* Usually this just stores reply data in the pre-allocated ep0 buffer,
-+ * but config change events will also reconfigure hardware. */
-+ switch (ctrl->bRequest) {
-+
-+ case USB_REQ_GET_DESCRIPTOR:
-+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+ USB_RECIP_DEVICE))
-+ break;
-+ switch (w_value >> 8) {
-+
-+ case USB_DT_DEVICE:
-+ VDBG(fsg, "get device descriptor\n");
-+ device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
-+ value = sizeof device_desc;
-+ memcpy(req->buf, &device_desc, value);
-+ break;
-+ case USB_DT_DEVICE_QUALIFIER:
-+ VDBG(fsg, "get device qualifier\n");
-+ if (!gadget_is_dualspeed(fsg->gadget) ||
-+ fsg->gadget->speed == USB_SPEED_SUPER)
-+ break;
-+ /*
-+ * Assume ep0 uses the same maxpacket value for both
-+ * speeds
-+ */
-+ dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
-+ value = sizeof dev_qualifier;
-+ memcpy(req->buf, &dev_qualifier, value);
-+ break;
-+
-+ case USB_DT_OTHER_SPEED_CONFIG:
-+ VDBG(fsg, "get other-speed config descriptor\n");
-+ if (!gadget_is_dualspeed(fsg->gadget) ||
-+ fsg->gadget->speed == USB_SPEED_SUPER)
-+ break;
-+ goto get_config;
-+ case USB_DT_CONFIG:
-+ VDBG(fsg, "get configuration descriptor\n");
-+get_config:
-+ value = populate_config_buf(fsg->gadget,
-+ req->buf,
-+ w_value >> 8,
-+ w_value & 0xff);
-+ break;
-+
-+ case USB_DT_STRING:
-+ VDBG(fsg, "get string descriptor\n");
-+
-+ /* wIndex == language code */
-+ value = usb_gadget_get_string(&fsg_stringtab,
-+ w_value & 0xff, req->buf);
-+ break;
-+
-+ case USB_DT_BOS:
-+ VDBG(fsg, "get bos descriptor\n");
-+
-+ if (gadget_is_superspeed(fsg->gadget))
-+ value = populate_bos(fsg, req->buf);
-+ break;
-+ }
-+
-+ break;
-+
-+ /* One config, two speeds */
-+ case USB_REQ_SET_CONFIGURATION:
-+ if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
-+ USB_RECIP_DEVICE))
-+ break;
-+ VDBG(fsg, "set configuration\n");
-+ if (w_value == CONFIG_VALUE || w_value == 0) {
-+ fsg->new_config = w_value;
-+
-+ /* Raise an exception to wipe out previous transaction
-+ * state (queued bufs, etc) and set the new config. */
-+ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
-+ value = DELAYED_STATUS;
-+ }
-+ break;
-+ case USB_REQ_GET_CONFIGURATION:
-+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+ USB_RECIP_DEVICE))
-+ break;
-+ VDBG(fsg, "get configuration\n");
-+ *(u8 *) req->buf = fsg->config;
-+ value = 1;
-+ break;
-+
-+ case USB_REQ_SET_INTERFACE:
-+ if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
-+ USB_RECIP_INTERFACE))
-+ break;
-+ if (fsg->config && w_index == 0) {
-+
-+ /* Raise an exception to wipe out previous transaction
-+ * state (queued bufs, etc) and install the new
-+ * interface altsetting. */
-+ raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
-+ value = DELAYED_STATUS;
-+ }
-+ break;
-+ case USB_REQ_GET_INTERFACE:
-+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+ USB_RECIP_INTERFACE))
-+ break;
-+ if (!fsg->config)
-+ break;
-+ if (w_index != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ VDBG(fsg, "get interface\n");
-+ *(u8 *) req->buf = 0;
-+ value = 1;
-+ break;
-+
-+ default:
-+ VDBG(fsg,
-+ "unknown control req %02x.%02x v%04x i%04x l%u\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ w_value, w_index, le16_to_cpu(ctrl->wLength));
-+ }
-+
-+ return value;
-+}
-+
-+
-+static int fsg_setup(struct usb_gadget *gadget,
-+ const struct usb_ctrlrequest *ctrl)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+ int rc;
-+ int w_length = le16_to_cpu(ctrl->wLength);
-+
-+ ++fsg->ep0_req_tag; // Record arrival of a new request
-+ fsg->ep0req->context = NULL;
-+ fsg->ep0req->length = 0;
-+ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
-+
-+ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
-+ rc = class_setup_req(fsg, ctrl);
-+ else
-+ rc = standard_setup_req(fsg, ctrl);
-+
-+ /* Respond with data/status or defer until later? */
-+ if (rc >= 0 && rc != DELAYED_STATUS) {
-+ rc = min(rc, w_length);
-+ fsg->ep0req->length = rc;
-+ fsg->ep0req->zero = rc < w_length;
-+ fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
-+ "ep0-in" : "ep0-out");
-+ rc = ep0_queue(fsg);
-+ }
-+
-+ /* Device either stalls (rc < 0) or reports success */
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* All the following routines run in process context */
-+
-+
-+/* Use this for bulk or interrupt transfers, not ep0 */
-+static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
-+ struct usb_request *req, int *pbusy,
-+ enum fsg_buffer_state *state)
-+{
-+ int rc;
-+
-+ if (ep == fsg->bulk_in)
-+ dump_msg(fsg, "bulk-in", req->buf, req->length);
-+ else if (ep == fsg->intr_in)
-+ dump_msg(fsg, "intr-in", req->buf, req->length);
-+
-+ spin_lock_irq(&fsg->lock);
-+ *pbusy = 1;
-+ *state = BUF_STATE_BUSY;
-+ spin_unlock_irq(&fsg->lock);
-+ rc = usb_ep_queue(ep, req, GFP_KERNEL);
-+ if (rc != 0) {
-+ *pbusy = 0;
-+ *state = BUF_STATE_EMPTY;
-+
-+ /* We can't do much more than wait for a reset */
-+
-+ /* Note: currently the net2280 driver fails zero-length
-+ * submissions if DMA is enabled. */
-+ if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
-+ req->length == 0))
-+ WARNING(fsg, "error in submission: %s --> %d\n",
-+ ep->name, rc);
-+ }
-+}
-+
-+
-+static int sleep_thread(struct fsg_dev *fsg)
-+{
-+ int rc = 0;
-+
-+ /* Wait until a signal arrives or we are woken up */
-+ for (;;) {
-+ try_to_freeze();
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ if (signal_pending(current)) {
-+ rc = -EINTR;
-+ break;
-+ }
-+ if (fsg->thread_wakeup_needed)
-+ break;
-+ schedule();
-+ }
-+ __set_current_state(TASK_RUNNING);
-+ fsg->thread_wakeup_needed = 0;
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_read(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba;
-+ struct fsg_buffhd *bh;
-+ int rc;
-+ u32 amount_left;
-+ loff_t file_offset, file_offset_tmp;
-+ unsigned int amount;
-+ ssize_t nread;
-+
-+ /* Get the starting Logical Block Address and check that it's
-+ * not too big */
-+ if (fsg->cmnd[0] == READ_6)
-+ lba = get_unaligned_be24(&fsg->cmnd[1]);
-+ else {
-+ lba = get_unaligned_be32(&fsg->cmnd[2]);
-+
-+ /* We allow DPO (Disable Page Out = don't save data in the
-+ * cache) and FUA (Force Unit Access = don't read from the
-+ * cache), but we don't implement them. */
-+ if ((fsg->cmnd[1] & ~0x18) != 0) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ }
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+ file_offset = ((loff_t) lba) << curlun->blkbits;
-+
-+ /* Carry out the file reads */
-+ amount_left = fsg->data_size_from_cmnd;
-+ if (unlikely(amount_left == 0))
-+ return -EIO; // No default reply
-+
-+ for (;;) {
-+
-+ /* Figure out how much we need to read:
-+ * Try to read the remaining amount.
-+ * But don't read more than the buffer size.
-+ * And don't try to read past the end of the file.
-+ */
-+ amount = min((unsigned int) amount_left, mod_data.buflen);
-+ amount = min((loff_t) amount,
-+ curlun->file_length - file_offset);
-+
-+ /* Wait for the next buffer to become available */
-+ bh = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ /* If we were asked to read past the end of file,
-+ * end with an empty buffer. */
-+ if (amount == 0) {
-+ curlun->sense_data =
-+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ bh->inreq->length = 0;
-+ bh->state = BUF_STATE_FULL;
-+ break;
-+ }
-+
-+ /* Perform the read */
-+ file_offset_tmp = file_offset;
-+ nread = vfs_read(curlun->filp,
-+ (char __user *) bh->buf,
-+ amount, &file_offset_tmp);
-+ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
-+ (unsigned long long) file_offset,
-+ (int) nread);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ if (nread < 0) {
-+ LDBG(curlun, "error in file read: %d\n",
-+ (int) nread);
-+ nread = 0;
-+ } else if (nread < amount) {
-+ LDBG(curlun, "partial file read: %d/%u\n",
-+ (int) nread, amount);
-+ nread = round_down(nread, curlun->blksize);
-+ }
-+ file_offset += nread;
-+ amount_left -= nread;
-+ fsg->residue -= nread;
-+
-+ /* Except at the end of the transfer, nread will be
-+ * equal to the buffer size, which is divisible by the
-+ * bulk-in maxpacket size.
-+ */
-+ bh->inreq->length = nread;
-+ bh->state = BUF_STATE_FULL;
-+
-+ /* If an error occurred, report it and its position */
-+ if (nread < amount) {
-+ curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ if (amount_left == 0)
-+ break; // No more left to read
-+
-+ /* Send this buffer and go read some more */
-+ bh->inreq->zero = 0;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ }
-+
-+ return -EIO; // No default reply
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_write(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba;
-+ struct fsg_buffhd *bh;
-+ int get_some_more;
-+ u32 amount_left_to_req, amount_left_to_write;
-+ loff_t usb_offset, file_offset, file_offset_tmp;
-+ unsigned int amount;
-+ ssize_t nwritten;
-+ int rc;
-+
-+ if (curlun->ro) {
-+ curlun->sense_data = SS_WRITE_PROTECTED;
-+ return -EINVAL;
-+ }
-+ spin_lock(&curlun->filp->f_lock);
-+ curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait
-+ spin_unlock(&curlun->filp->f_lock);
-+
-+ /* Get the starting Logical Block Address and check that it's
-+ * not too big */
-+ if (fsg->cmnd[0] == WRITE_6)
-+ lba = get_unaligned_be24(&fsg->cmnd[1]);
-+ else {
-+ lba = get_unaligned_be32(&fsg->cmnd[2]);
-+
-+ /* We allow DPO (Disable Page Out = don't save data in the
-+ * cache) and FUA (Force Unit Access = write directly to the
-+ * medium). We don't implement DPO; we implement FUA by
-+ * performing synchronous output. */
-+ if ((fsg->cmnd[1] & ~0x18) != 0) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ /* FUA */
-+ if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
-+ spin_lock(&curlun->filp->f_lock);
-+ curlun->filp->f_flags |= O_DSYNC;
-+ spin_unlock(&curlun->filp->f_lock);
-+ }
-+ }
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+
-+ /* Carry out the file writes */
-+ get_some_more = 1;
-+ file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
-+ amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
-+
-+ while (amount_left_to_write > 0) {
-+
-+ /* Queue a request for more data from the host */
-+ bh = fsg->next_buffhd_to_fill;
-+ if (bh->state == BUF_STATE_EMPTY && get_some_more) {
-+
-+ /* Figure out how much we want to get:
-+ * Try to get the remaining amount,
-+ * but not more than the buffer size.
-+ */
-+ amount = min(amount_left_to_req, mod_data.buflen);
-+
-+ /* Beyond the end of the backing file? */
-+ if (usb_offset >= curlun->file_length) {
-+ get_some_more = 0;
-+ curlun->sense_data =
-+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ curlun->sense_data_info = usb_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ continue;
-+ }
-+
-+ /* Get the next buffer */
-+ usb_offset += amount;
-+ fsg->usb_amount_left -= amount;
-+ amount_left_to_req -= amount;
-+ if (amount_left_to_req == 0)
-+ get_some_more = 0;
-+
-+ /* Except at the end of the transfer, amount will be
-+ * equal to the buffer size, which is divisible by
-+ * the bulk-out maxpacket size.
-+ */
-+ set_bulk_out_req_length(fsg, bh, amount);
-+ start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+ &bh->outreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ continue;
-+ }
-+
-+ /* Write the received data to the backing file */
-+ bh = fsg->next_buffhd_to_drain;
-+ if (bh->state == BUF_STATE_EMPTY && !get_some_more)
-+ break; // We stopped early
-+ if (bh->state == BUF_STATE_FULL) {
-+ smp_rmb();
-+ fsg->next_buffhd_to_drain = bh->next;
-+ bh->state = BUF_STATE_EMPTY;
-+
-+ /* Did something go wrong with the transfer? */
-+ if (bh->outreq->status != 0) {
-+ curlun->sense_data = SS_COMMUNICATION_FAILURE;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ amount = bh->outreq->actual;
-+ if (curlun->file_length - file_offset < amount) {
-+ LERROR(curlun,
-+ "write %u @ %llu beyond end %llu\n",
-+ amount, (unsigned long long) file_offset,
-+ (unsigned long long) curlun->file_length);
-+ amount = curlun->file_length - file_offset;
-+ }
-+
-+ /* Don't accept excess data. The spec doesn't say
-+ * what to do in this case. We'll ignore the error.
-+ */
-+ amount = min(amount, bh->bulk_out_intended_length);
-+
-+ /* Don't write a partial block */
-+ amount = round_down(amount, curlun->blksize);
-+ if (amount == 0)
-+ goto empty_write;
-+
-+ /* Perform the write */
-+ file_offset_tmp = file_offset;
-+ nwritten = vfs_write(curlun->filp,
-+ (char __user *) bh->buf,
-+ amount, &file_offset_tmp);
-+ VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
-+ (unsigned long long) file_offset,
-+ (int) nwritten);
-+ if (signal_pending(current))
-+ return -EINTR; // Interrupted!
-+
-+ if (nwritten < 0) {
-+ LDBG(curlun, "error in file write: %d\n",
-+ (int) nwritten);
-+ nwritten = 0;
-+ } else if (nwritten < amount) {
-+ LDBG(curlun, "partial file write: %d/%u\n",
-+ (int) nwritten, amount);
-+ nwritten = round_down(nwritten, curlun->blksize);
-+ }
-+ file_offset += nwritten;
-+ amount_left_to_write -= nwritten;
-+ fsg->residue -= nwritten;
-+
-+ /* If an error occurred, report it and its position */
-+ if (nwritten < amount) {
-+ curlun->sense_data = SS_WRITE_ERROR;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ empty_write:
-+ /* Did the host decide to stop early? */
-+ if (bh->outreq->actual < bh->bulk_out_intended_length) {
-+ fsg->short_packet_received = 1;
-+ break;
-+ }
-+ continue;
-+ }
-+
-+ /* Wait for something to happen */
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ return -EIO; // No default reply
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_synchronize_cache(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int rc;
-+
-+ /* We ignore the requested LBA and write out all file's
-+ * dirty data buffers. */
-+ rc = fsg_lun_fsync_sub(curlun);
-+ if (rc)
-+ curlun->sense_data = SS_WRITE_ERROR;
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void invalidate_sub(struct fsg_lun *curlun)
-+{
-+ struct file *filp = curlun->filp;
-+ struct inode *inode = filp->f_path.dentry->d_inode;
-+ unsigned long rc;
-+
-+ rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
-+ VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
-+}
-+
-+static int do_verify(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba;
-+ u32 verification_length;
-+ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
-+ loff_t file_offset, file_offset_tmp;
-+ u32 amount_left;
-+ unsigned int amount;
-+ ssize_t nread;
-+
-+ /* Get the starting Logical Block Address and check that it's
-+ * not too big */
-+ lba = get_unaligned_be32(&fsg->cmnd[2]);
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+
-+ /* We allow DPO (Disable Page Out = don't save data in the
-+ * cache) but we don't implement it. */
-+ if ((fsg->cmnd[1] & ~0x10) != 0) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ verification_length = get_unaligned_be16(&fsg->cmnd[7]);
-+ if (unlikely(verification_length == 0))
-+ return -EIO; // No default reply
-+
-+ /* Prepare to carry out the file verify */
-+ amount_left = verification_length << curlun->blkbits;
-+ file_offset = ((loff_t) lba) << curlun->blkbits;
-+
-+ /* Write out all the dirty buffers before invalidating them */
-+ fsg_lun_fsync_sub(curlun);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ invalidate_sub(curlun);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ /* Just try to read the requested blocks */
-+ while (amount_left > 0) {
-+
-+ /* Figure out how much we need to read:
-+ * Try to read the remaining amount, but not more than
-+ * the buffer size.
-+ * And don't try to read past the end of the file.
-+ */
-+ amount = min((unsigned int) amount_left, mod_data.buflen);
-+ amount = min((loff_t) amount,
-+ curlun->file_length - file_offset);
-+ if (amount == 0) {
-+ curlun->sense_data =
-+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ /* Perform the read */
-+ file_offset_tmp = file_offset;
-+ nread = vfs_read(curlun->filp,
-+ (char __user *) bh->buf,
-+ amount, &file_offset_tmp);
-+ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
-+ (unsigned long long) file_offset,
-+ (int) nread);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ if (nread < 0) {
-+ LDBG(curlun, "error in file verify: %d\n",
-+ (int) nread);
-+ nread = 0;
-+ } else if (nread < amount) {
-+ LDBG(curlun, "partial file verify: %d/%u\n",
-+ (int) nread, amount);
-+ nread = round_down(nread, curlun->blksize);
-+ }
-+ if (nread == 0) {
-+ curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+ file_offset += nread;
-+ amount_left -= nread;
-+ }
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ static char vendor_id[] = "Linux ";
-+ static char product_disk_id[] = "File-Stor Gadget";
-+ static char product_cdrom_id[] = "File-CD Gadget ";
-+
-+ if (!fsg->curlun) { // Unsupported LUNs are okay
-+ fsg->bad_lun_okay = 1;
-+ memset(buf, 0, 36);
-+ buf[0] = 0x7f; // Unsupported, no device-type
-+ buf[4] = 31; // Additional length
-+ return 36;
-+ }
-+
-+ memset(buf, 0, 8);
-+ buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
-+ if (mod_data.removable)
-+ buf[1] = 0x80;
-+ buf[2] = 2; // ANSI SCSI level 2
-+ buf[3] = 2; // SCSI-2 INQUIRY data format
-+ buf[4] = 31; // Additional length
-+ // No special options
-+ sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
-+ (mod_data.cdrom ? product_cdrom_id :
-+ product_disk_id),
-+ mod_data.release);
-+ return 36;
-+}
-+
-+
-+static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u8 *buf = (u8 *) bh->buf;
-+ u32 sd, sdinfo;
-+ int valid;
-+
-+ /*
-+ * From the SCSI-2 spec., section 7.9 (Unit attention condition):
-+ *
-+ * If a REQUEST SENSE command is received from an initiator
-+ * with a pending unit attention condition (before the target
-+ * generates the contingent allegiance condition), then the
-+ * target shall either:
-+ * a) report any pending sense data and preserve the unit
-+ * attention condition on the logical unit, or,
-+ * b) report the unit attention condition, may discard any
-+ * pending sense data, and clear the unit attention
-+ * condition on the logical unit for that initiator.
-+ *
-+ * FSG normally uses option a); enable this code to use option b).
-+ */
-+#if 0
-+ if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
-+ curlun->sense_data = curlun->unit_attention_data;
-+ curlun->unit_attention_data = SS_NO_SENSE;
-+ }
-+#endif
-+
-+ if (!curlun) { // Unsupported LUNs are okay
-+ fsg->bad_lun_okay = 1;
-+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-+ sdinfo = 0;
-+ valid = 0;
-+ } else {
-+ sd = curlun->sense_data;
-+ sdinfo = curlun->sense_data_info;
-+ valid = curlun->info_valid << 7;
-+ curlun->sense_data = SS_NO_SENSE;
-+ curlun->sense_data_info = 0;
-+ curlun->info_valid = 0;
-+ }
-+
-+ memset(buf, 0, 18);
-+ buf[0] = valid | 0x70; // Valid, current error
-+ buf[2] = SK(sd);
-+ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
-+ buf[7] = 18 - 8; // Additional sense length
-+ buf[12] = ASC(sd);
-+ buf[13] = ASCQ(sd);
-+ return 18;
-+}
-+
-+
-+static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
-+ int pmi = fsg->cmnd[8];
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ /* Check the PMI and LBA fields */
-+ if (pmi > 1 || (pmi == 0 && lba != 0)) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
-+ /* Max logical block */
-+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
-+ return 8;
-+}
-+
-+
-+static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int msf = fsg->cmnd[1] & 0x02;
-+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+
-+ memset(buf, 0, 8);
-+ buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */
-+ store_cdrom_address(&buf[4], msf, lba);
-+ return 8;
-+}
-+
-+
-+static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int msf = fsg->cmnd[1] & 0x02;
-+ int start_track = fsg->cmnd[6];
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */
-+ start_track > 1) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ memset(buf, 0, 20);
-+ buf[1] = (20-2); /* TOC data length */
-+ buf[2] = 1; /* First track number */
-+ buf[3] = 1; /* Last track number */
-+ buf[5] = 0x16; /* Data track, copying allowed */
-+ buf[6] = 0x01; /* Only track is number 1 */
-+ store_cdrom_address(&buf[8], msf, 0);
-+
-+ buf[13] = 0x16; /* Lead-out track is data */
-+ buf[14] = 0xAA; /* Lead-out track number */
-+ store_cdrom_address(&buf[16], msf, curlun->num_sectors);
-+ return 20;
-+}
-+
-+
-+static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int mscmnd = fsg->cmnd[0];
-+ u8 *buf = (u8 *) bh->buf;
-+ u8 *buf0 = buf;
-+ int pc, page_code;
-+ int changeable_values, all_pages;
-+ int valid_page = 0;
-+ int len, limit;
-+
-+ if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ pc = fsg->cmnd[2] >> 6;
-+ page_code = fsg->cmnd[2] & 0x3f;
-+ if (pc == 3) {
-+ curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
-+ return -EINVAL;
-+ }
-+ changeable_values = (pc == 1);
-+ all_pages = (page_code == 0x3f);
-+
-+ /* Write the mode parameter header. Fixed values are: default
-+ * medium type, no cache control (DPOFUA), and no block descriptors.
-+ * The only variable value is the WriteProtect bit. We will fill in
-+ * the mode data length later. */
-+ memset(buf, 0, 8);
-+ if (mscmnd == MODE_SENSE) {
-+ buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
-+ buf += 4;
-+ limit = 255;
-+ } else { // MODE_SENSE_10
-+ buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
-+ buf += 8;
-+ limit = 65535; // Should really be mod_data.buflen
-+ }
-+
-+ /* No block descriptors */
-+
-+ /* The mode pages, in numerical order. The only page we support
-+ * is the Caching page. */
-+ if (page_code == 0x08 || all_pages) {
-+ valid_page = 1;
-+ buf[0] = 0x08; // Page code
-+ buf[1] = 10; // Page length
-+ memset(buf+2, 0, 10); // None of the fields are changeable
-+
-+ if (!changeable_values) {
-+ buf[2] = 0x04; // Write cache enable,
-+ // Read cache not disabled
-+ // No cache retention priorities
-+ put_unaligned_be16(0xffff, &buf[4]);
-+ /* Don't disable prefetch */
-+ /* Minimum prefetch = 0 */
-+ put_unaligned_be16(0xffff, &buf[8]);
-+ /* Maximum prefetch */
-+ put_unaligned_be16(0xffff, &buf[10]);
-+ /* Maximum prefetch ceiling */
-+ }
-+ buf += 12;
-+ }
-+
-+ /* Check that a valid page was requested and the mode data length
-+ * isn't too long. */
-+ len = buf - buf0;
-+ if (!valid_page || len > limit) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ /* Store the mode data length */
-+ if (mscmnd == MODE_SENSE)
-+ buf0[0] = len - 1;
-+ else
-+ put_unaligned_be16(len - 2, buf0);
-+ return len;
-+}
-+
-+
-+static int do_start_stop(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int loej, start;
-+
-+ if (!mod_data.removable) {
-+ curlun->sense_data = SS_INVALID_COMMAND;
-+ return -EINVAL;
-+ }
-+
-+ // int immed = fsg->cmnd[1] & 0x01;
-+ loej = fsg->cmnd[4] & 0x02;
-+ start = fsg->cmnd[4] & 0x01;
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+ if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed
-+ (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ if (!start) {
-+
-+ /* Are we allowed to unload the media? */
-+ if (curlun->prevent_medium_removal) {
-+ LDBG(curlun, "unload attempt prevented\n");
-+ curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
-+ return -EINVAL;
-+ }
-+ if (loej) { // Simulate an unload/eject
-+ up_read(&fsg->filesem);
-+ down_write(&fsg->filesem);
-+ fsg_lun_close(curlun);
-+ up_write(&fsg->filesem);
-+ down_read(&fsg->filesem);
-+ }
-+ } else {
-+
-+ /* Our emulation doesn't support mounting; the medium is
-+ * available for use as soon as it is loaded. */
-+ if (!fsg_lun_is_open(curlun)) {
-+ curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
-+ return -EINVAL;
-+ }
-+ }
-+#endif
-+ return 0;
-+}
-+
-+
-+static int do_prevent_allow(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int prevent;
-+
-+ if (!mod_data.removable) {
-+ curlun->sense_data = SS_INVALID_COMMAND;
-+ return -EINVAL;
-+ }
-+
-+ prevent = fsg->cmnd[4] & 0x01;
-+ if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ if (curlun->prevent_medium_removal && !prevent)
-+ fsg_lun_fsync_sub(curlun);
-+ curlun->prevent_medium_removal = prevent;
-+ return 0;
-+}
-+
-+
-+static int do_read_format_capacities(struct fsg_dev *fsg,
-+ struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ buf[0] = buf[1] = buf[2] = 0;
-+ buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
-+ buf += 4;
-+
-+ put_unaligned_be32(curlun->num_sectors, &buf[0]);
-+ /* Number of blocks */
-+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
-+ buf[4] = 0x02; /* Current capacity */
-+ return 12;
-+}
-+
-+
-+static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+
-+ /* We don't support MODE SELECT */
-+ curlun->sense_data = SS_INVALID_COMMAND;
-+ return -EINVAL;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
-+{
-+ int rc;
-+
-+ rc = fsg_set_halt(fsg, fsg->bulk_in);
-+ if (rc == -EAGAIN)
-+ VDBG(fsg, "delayed bulk-in endpoint halt\n");
-+ while (rc != 0) {
-+ if (rc != -EAGAIN) {
-+ WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
-+ rc = 0;
-+ break;
-+ }
-+
-+ /* Wait for a short time and then try again */
-+ if (msleep_interruptible(100) != 0)
-+ return -EINTR;
-+ rc = usb_ep_set_halt(fsg->bulk_in);
-+ }
-+ return rc;
-+}
-+
-+static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
-+{
-+ int rc;
-+
-+ DBG(fsg, "bulk-in set wedge\n");
-+ rc = usb_ep_set_wedge(fsg->bulk_in);
-+ if (rc == -EAGAIN)
-+ VDBG(fsg, "delayed bulk-in endpoint wedge\n");
-+ while (rc != 0) {
-+ if (rc != -EAGAIN) {
-+ WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
-+ rc = 0;
-+ break;
-+ }
-+
-+ /* Wait for a short time and then try again */
-+ if (msleep_interruptible(100) != 0)
-+ return -EINTR;
-+ rc = usb_ep_set_wedge(fsg->bulk_in);
-+ }
-+ return rc;
-+}
-+
-+static int throw_away_data(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh;
-+ u32 amount;
-+ int rc;
-+
-+ while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
-+ fsg->usb_amount_left > 0) {
-+
-+ /* Throw away the data in a filled buffer */
-+ if (bh->state == BUF_STATE_FULL) {
-+ smp_rmb();
-+ bh->state = BUF_STATE_EMPTY;
-+ fsg->next_buffhd_to_drain = bh->next;
-+
-+ /* A short packet or an error ends everything */
-+ if (bh->outreq->actual < bh->bulk_out_intended_length ||
-+ bh->outreq->status != 0) {
-+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+ return -EINTR;
-+ }
-+ continue;
-+ }
-+
-+ /* Try to submit another request if we need one */
-+ bh = fsg->next_buffhd_to_fill;
-+ if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
-+ amount = min(fsg->usb_amount_left,
-+ (u32) mod_data.buflen);
-+
-+ /* Except at the end of the transfer, amount will be
-+ * equal to the buffer size, which is divisible by
-+ * the bulk-out maxpacket size.
-+ */
-+ set_bulk_out_req_length(fsg, bh, amount);
-+ start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+ &bh->outreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ fsg->usb_amount_left -= amount;
-+ continue;
-+ }
-+
-+ /* Otherwise wait for something to happen */
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+ return 0;
-+}
-+
-+
-+static int finish_reply(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
-+ int rc = 0;
-+
-+ switch (fsg->data_dir) {
-+ case DATA_DIR_NONE:
-+ break; // Nothing to send
-+
-+ /* If we don't know whether the host wants to read or write,
-+ * this must be CB or CBI with an unknown command. We mustn't
-+ * try to send or receive any data. So stall both bulk pipes
-+ * if we can and wait for a reset. */
-+ case DATA_DIR_UNKNOWN:
-+ if (mod_data.can_stall) {
-+ fsg_set_halt(fsg, fsg->bulk_out);
-+ rc = halt_bulk_in_endpoint(fsg);
-+ }
-+ break;
-+
-+ /* All but the last buffer of data must have already been sent */
-+ case DATA_DIR_TO_HOST:
-+ if (fsg->data_size == 0)
-+ ; // Nothing to send
-+
-+ /* If there's no residue, simply send the last buffer */
-+ else if (fsg->residue == 0) {
-+ bh->inreq->zero = 0;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ }
-+
-+ /* There is a residue. For CB and CBI, simply mark the end
-+ * of the data with a short packet. However, if we are
-+ * allowed to stall, there was no data at all (residue ==
-+ * data_size), and the command failed (invalid LUN or
-+ * sense data is set), then halt the bulk-in endpoint
-+ * instead. */
-+ else if (!transport_is_bbb()) {
-+ if (mod_data.can_stall &&
-+ fsg->residue == fsg->data_size &&
-+ (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
-+ bh->state = BUF_STATE_EMPTY;
-+ rc = halt_bulk_in_endpoint(fsg);
-+ } else {
-+ bh->inreq->zero = 1;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ }
-+ }
-+
-+ /*
-+ * For Bulk-only, mark the end of the data with a short
-+ * packet. If we are allowed to stall, halt the bulk-in
-+ * endpoint. (Note: This violates the Bulk-Only Transport
-+ * specification, which requires us to pad the data if we
-+ * don't halt the endpoint. Presumably nobody will mind.)
-+ */
-+ else {
-+ bh->inreq->zero = 1;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ if (mod_data.can_stall)
-+ rc = halt_bulk_in_endpoint(fsg);
-+ }
-+ break;
-+
-+ /* We have processed all we want from the data the host has sent.
-+ * There may still be outstanding bulk-out requests. */
-+ case DATA_DIR_FROM_HOST:
-+ if (fsg->residue == 0)
-+ ; // Nothing to receive
-+
-+ /* Did the host stop sending unexpectedly early? */
-+ else if (fsg->short_packet_received) {
-+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+ rc = -EINTR;
-+ }
-+
-+ /* We haven't processed all the incoming data. Even though
-+ * we may be allowed to stall, doing so would cause a race.
-+ * The controller may already have ACK'ed all the remaining
-+ * bulk-out packets, in which case the host wouldn't see a
-+ * STALL. Not realizing the endpoint was halted, it wouldn't
-+ * clear the halt -- leading to problems later on. */
-+#if 0
-+ else if (mod_data.can_stall) {
-+ fsg_set_halt(fsg, fsg->bulk_out);
-+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+ rc = -EINTR;
-+ }
-+#endif
-+
-+ /* We can't stall. Read in the excess data and throw it
-+ * all away. */
-+ else
-+ rc = throw_away_data(fsg);
-+ break;
-+ }
-+ return rc;
-+}
-+
-+
-+static int send_status(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ struct fsg_buffhd *bh;
-+ int rc;
-+ u8 status = US_BULK_STAT_OK;
-+ u32 sd, sdinfo = 0;
-+
-+ /* Wait for the next buffer to become available */
-+ bh = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ if (curlun) {
-+ sd = curlun->sense_data;
-+ sdinfo = curlun->sense_data_info;
-+ } else if (fsg->bad_lun_okay)
-+ sd = SS_NO_SENSE;
-+ else
-+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-+
-+ if (fsg->phase_error) {
-+ DBG(fsg, "sending phase-error status\n");
-+ status = US_BULK_STAT_PHASE;
-+ sd = SS_INVALID_COMMAND;
-+ } else if (sd != SS_NO_SENSE) {
-+ DBG(fsg, "sending command-failure status\n");
-+ status = US_BULK_STAT_FAIL;
-+ VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
-+ " info x%x\n",
-+ SK(sd), ASC(sd), ASCQ(sd), sdinfo);
-+ }
-+
-+ if (transport_is_bbb()) {
-+ struct bulk_cs_wrap *csw = bh->buf;
-+
-+ /* Store and send the Bulk-only CSW */
-+ csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
-+ csw->Tag = fsg->tag;
-+ csw->Residue = cpu_to_le32(fsg->residue);
-+ csw->Status = status;
-+
-+ bh->inreq->length = US_BULK_CS_WRAP_LEN;
-+ bh->inreq->zero = 0;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+
-+ } else if (mod_data.transport_type == USB_PR_CB) {
-+
-+ /* Control-Bulk transport has no status phase! */
-+ return 0;
-+
-+ } else { // USB_PR_CBI
-+ struct interrupt_data *buf = bh->buf;
-+
-+ /* Store and send the Interrupt data. UFI sends the ASC
-+ * and ASCQ bytes. Everything else sends a Type (which
-+ * is always 0) and the status Value. */
-+ if (mod_data.protocol_type == USB_SC_UFI) {
-+ buf->bType = ASC(sd);
-+ buf->bValue = ASCQ(sd);
-+ } else {
-+ buf->bType = 0;
-+ buf->bValue = status;
-+ }
-+ fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
-+
-+ fsg->intr_buffhd = bh; // Point to the right buffhd
-+ fsg->intreq->buf = bh->inreq->buf;
-+ fsg->intreq->context = bh;
-+ start_transfer(fsg, fsg->intr_in, fsg->intreq,
-+ &fsg->intreq_busy, &bh->state);
-+ }
-+
-+ fsg->next_buffhd_to_fill = bh->next;
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Check whether the command is properly formed and whether its data size
-+ * and direction agree with the values we already have. */
-+static int check_command(struct fsg_dev *fsg, int cmnd_size,
-+ enum data_direction data_dir, unsigned int mask,
-+ int needs_medium, const char *name)
-+{
-+ int i;
-+ int lun = fsg->cmnd[1] >> 5;
-+ static const char dirletter[4] = {'u', 'o', 'i', 'n'};
-+ char hdlen[20];
-+ struct fsg_lun *curlun;
-+
-+ /* Adjust the expected cmnd_size for protocol encapsulation padding.
-+ * Transparent SCSI doesn't pad. */
-+ if (protocol_is_scsi())
-+ ;
-+
-+ /* There's some disagreement as to whether RBC pads commands or not.
-+ * We'll play it safe and accept either form. */
-+ else if (mod_data.protocol_type == USB_SC_RBC) {
-+ if (fsg->cmnd_size == 12)
-+ cmnd_size = 12;
-+
-+ /* All the other protocols pad to 12 bytes */
-+ } else
-+ cmnd_size = 12;
-+
-+ hdlen[0] = 0;
-+ if (fsg->data_dir != DATA_DIR_UNKNOWN)
-+ sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
-+ fsg->data_size);
-+ VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n",
-+ name, cmnd_size, dirletter[(int) data_dir],
-+ fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
-+
-+ /* We can't reply at all until we know the correct data direction
-+ * and size. */
-+ if (fsg->data_size_from_cmnd == 0)
-+ data_dir = DATA_DIR_NONE;
-+ if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI
-+ fsg->data_dir = data_dir;
-+ fsg->data_size = fsg->data_size_from_cmnd;
-+
-+ } else { // Bulk-only
-+ if (fsg->data_size < fsg->data_size_from_cmnd) {
-+
-+ /* Host data size < Device data size is a phase error.
-+ * Carry out the command, but only transfer as much
-+ * as we are allowed. */
-+ fsg->data_size_from_cmnd = fsg->data_size;
-+ fsg->phase_error = 1;
-+ }
-+ }
-+ fsg->residue = fsg->usb_amount_left = fsg->data_size;
-+
-+ /* Conflicting data directions is a phase error */
-+ if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
-+ fsg->phase_error = 1;
-+ return -EINVAL;
-+ }
-+
-+ /* Verify the length of the command itself */
-+ if (cmnd_size != fsg->cmnd_size) {
-+
-+ /* Special case workaround: There are plenty of buggy SCSI
-+ * implementations. Many have issues with cbw->Length
-+ * field passing a wrong command size. For those cases we
-+ * always try to work around the problem by using the length
-+ * sent by the host side provided it is at least as large
-+ * as the correct command length.
-+ * Examples of such cases would be MS-Windows, which issues
-+ * REQUEST SENSE with cbw->Length == 12 where it should
-+ * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
-+ * REQUEST SENSE with cbw->Length == 10 where it should
-+ * be 6 as well.
-+ */
-+ if (cmnd_size <= fsg->cmnd_size) {
-+ DBG(fsg, "%s is buggy! Expected length %d "
-+ "but we got %d\n", name,
-+ cmnd_size, fsg->cmnd_size);
-+ cmnd_size = fsg->cmnd_size;
-+ } else {
-+ fsg->phase_error = 1;
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* Check that the LUN values are consistent */
-+ if (transport_is_bbb()) {
-+ if (fsg->lun != lun)
-+ DBG(fsg, "using LUN %d from CBW, "
-+ "not LUN %d from CDB\n",
-+ fsg->lun, lun);
-+ }
-+
-+ /* Check the LUN */
-+ curlun = fsg->curlun;
-+ if (curlun) {
-+ if (fsg->cmnd[0] != REQUEST_SENSE) {
-+ curlun->sense_data = SS_NO_SENSE;
-+ curlun->sense_data_info = 0;
-+ curlun->info_valid = 0;
-+ }
-+ } else {
-+ fsg->bad_lun_okay = 0;
-+
-+ /* INQUIRY and REQUEST SENSE commands are explicitly allowed
-+ * to use unsupported LUNs; all others may not. */
-+ if (fsg->cmnd[0] != INQUIRY &&
-+ fsg->cmnd[0] != REQUEST_SENSE) {
-+ DBG(fsg, "unsupported LUN %d\n", fsg->lun);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* If a unit attention condition exists, only INQUIRY and
-+ * REQUEST SENSE commands are allowed; anything else must fail. */
-+ if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
-+ fsg->cmnd[0] != INQUIRY &&
-+ fsg->cmnd[0] != REQUEST_SENSE) {
-+ curlun->sense_data = curlun->unit_attention_data;
-+ curlun->unit_attention_data = SS_NO_SENSE;
-+ return -EINVAL;
-+ }
-+
-+ /* Check that only command bytes listed in the mask are non-zero */
-+ fsg->cmnd[1] &= 0x1f; // Mask away the LUN
-+ for (i = 1; i < cmnd_size; ++i) {
-+ if (fsg->cmnd[i] && !(mask & (1 << i))) {
-+ if (curlun)
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* If the medium isn't mounted and the command needs to access
-+ * it, return an error. */
-+ if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
-+ curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/* wrapper of check_command for data size in blocks handling */
-+static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
-+ enum data_direction data_dir, unsigned int mask,
-+ int needs_medium, const char *name)
-+{
-+ if (fsg->curlun)
-+ fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
-+ return check_command(fsg, cmnd_size, data_dir,
-+ mask, needs_medium, name);
-+}
-+
-+static int do_scsi_command(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh;
-+ int rc;
-+ int reply = -EINVAL;
-+ int i;
-+ static char unknown[16];
-+
-+ dump_cdb(fsg);
-+
-+ /* Wait for the next buffer to become available for data or status */
-+ bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+ fsg->phase_error = 0;
-+ fsg->short_packet_received = 0;
-+
-+ down_read(&fsg->filesem); // We're using the backing file
-+ switch (fsg->cmnd[0]) {
-+
-+ case INQUIRY:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+ (1<<4), 0,
-+ "INQUIRY")) == 0)
-+ reply = do_inquiry(fsg, bh);
-+ break;
-+
-+ case MODE_SELECT:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
-+ (1<<1) | (1<<4), 0,
-+ "MODE SELECT(6)")) == 0)
-+ reply = do_mode_select(fsg, bh);
-+ break;
-+
-+ case MODE_SELECT_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
-+ (1<<1) | (3<<7), 0,
-+ "MODE SELECT(10)")) == 0)
-+ reply = do_mode_select(fsg, bh);
-+ break;
-+
-+ case MODE_SENSE:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+ (1<<1) | (1<<2) | (1<<4), 0,
-+ "MODE SENSE(6)")) == 0)
-+ reply = do_mode_sense(fsg, bh);
-+ break;
-+
-+ case MODE_SENSE_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (1<<1) | (1<<2) | (3<<7), 0,
-+ "MODE SENSE(10)")) == 0)
-+ reply = do_mode_sense(fsg, bh);
-+ break;
-+
-+ case ALLOW_MEDIUM_REMOVAL:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
-+ (1<<4), 0,
-+ "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
-+ reply = do_prevent_allow(fsg);
-+ break;
-+
-+ case READ_6:
-+ i = fsg->cmnd[4];
-+ fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
-+ if ((reply = check_command_size_in_blocks(fsg, 6,
-+ DATA_DIR_TO_HOST,
-+ (7<<1) | (1<<4), 1,
-+ "READ(6)")) == 0)
-+ reply = do_read(fsg);
-+ break;
-+
-+ case READ_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command_size_in_blocks(fsg, 10,
-+ DATA_DIR_TO_HOST,
-+ (1<<1) | (0xf<<2) | (3<<7), 1,
-+ "READ(10)")) == 0)
-+ reply = do_read(fsg);
-+ break;
-+
-+ case READ_12:
-+ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
-+ if ((reply = check_command_size_in_blocks(fsg, 12,
-+ DATA_DIR_TO_HOST,
-+ (1<<1) | (0xf<<2) | (0xf<<6), 1,
-+ "READ(12)")) == 0)
-+ reply = do_read(fsg);
-+ break;
-+
-+ case READ_CAPACITY:
-+ fsg->data_size_from_cmnd = 8;
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (0xf<<2) | (1<<8), 1,
-+ "READ CAPACITY")) == 0)
-+ reply = do_read_capacity(fsg, bh);
-+ break;
-+
-+ case READ_HEADER:
-+ if (!mod_data.cdrom)
-+ goto unknown_cmnd;
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (3<<7) | (0x1f<<1), 1,
-+ "READ HEADER")) == 0)
-+ reply = do_read_header(fsg, bh);
-+ break;
-+
-+ case READ_TOC:
-+ if (!mod_data.cdrom)
-+ goto unknown_cmnd;
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (7<<6) | (1<<1), 1,
-+ "READ TOC")) == 0)
-+ reply = do_read_toc(fsg, bh);
-+ break;
-+
-+ case READ_FORMAT_CAPACITIES:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (3<<7), 1,
-+ "READ FORMAT CAPACITIES")) == 0)
-+ reply = do_read_format_capacities(fsg, bh);
-+ break;
-+
-+ case REQUEST_SENSE:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+ (1<<4), 0,
-+ "REQUEST SENSE")) == 0)
-+ reply = do_request_sense(fsg, bh);
-+ break;
-+
-+ case START_STOP:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
-+ (1<<1) | (1<<4), 0,
-+ "START-STOP UNIT")) == 0)
-+ reply = do_start_stop(fsg);
-+ break;
-+
-+ case SYNCHRONIZE_CACHE:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
-+ (0xf<<2) | (3<<7), 1,
-+ "SYNCHRONIZE CACHE")) == 0)
-+ reply = do_synchronize_cache(fsg);
-+ break;
-+
-+ case TEST_UNIT_READY:
-+ fsg->data_size_from_cmnd = 0;
-+ reply = check_command(fsg, 6, DATA_DIR_NONE,
-+ 0, 1,
-+ "TEST UNIT READY");
-+ break;
-+
-+ /* Although optional, this command is used by MS-Windows. We
-+ * support a minimal version: BytChk must be 0. */
-+ case VERIFY:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
-+ (1<<1) | (0xf<<2) | (3<<7), 1,
-+ "VERIFY")) == 0)
-+ reply = do_verify(fsg);
-+ break;
-+
-+ case WRITE_6:
-+ i = fsg->cmnd[4];
-+ fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
-+ if ((reply = check_command_size_in_blocks(fsg, 6,
-+ DATA_DIR_FROM_HOST,
-+ (7<<1) | (1<<4), 1,
-+ "WRITE(6)")) == 0)
-+ reply = do_write(fsg);
-+ break;
-+
-+ case WRITE_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command_size_in_blocks(fsg, 10,
-+ DATA_DIR_FROM_HOST,
-+ (1<<1) | (0xf<<2) | (3<<7), 1,
-+ "WRITE(10)")) == 0)
-+ reply = do_write(fsg);
-+ break;
-+
-+ case WRITE_12:
-+ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
-+ if ((reply = check_command_size_in_blocks(fsg, 12,
-+ DATA_DIR_FROM_HOST,
-+ (1<<1) | (0xf<<2) | (0xf<<6), 1,
-+ "WRITE(12)")) == 0)
-+ reply = do_write(fsg);
-+ break;
-+
-+ /* Some mandatory commands that we recognize but don't implement.
-+ * They don't mean much in this setting. It's left as an exercise
-+ * for anyone interested to implement RESERVE and RELEASE in terms
-+ * of Posix locks. */
-+ case FORMAT_UNIT:
-+ case RELEASE:
-+ case RESERVE:
-+ case SEND_DIAGNOSTIC:
-+ // Fall through
-+
-+ default:
-+ unknown_cmnd:
-+ fsg->data_size_from_cmnd = 0;
-+ sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
-+ if ((reply = check_command(fsg, fsg->cmnd_size,
-+ DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
-+ fsg->curlun->sense_data = SS_INVALID_COMMAND;
-+ reply = -EINVAL;
-+ }
-+ break;
-+ }
-+ up_read(&fsg->filesem);
-+
-+ if (reply == -EINTR || signal_pending(current))
-+ return -EINTR;
-+
-+ /* Set up the single reply buffer for finish_reply() */
-+ if (reply == -EINVAL)
-+ reply = 0; // Error reply length
-+ if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
-+ reply = min((u32) reply, fsg->data_size_from_cmnd);
-+ bh->inreq->length = reply;
-+ bh->state = BUF_STATE_FULL;
-+ fsg->residue -= reply;
-+ } // Otherwise it's already set
-+
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct usb_request *req = bh->outreq;
-+ struct bulk_cb_wrap *cbw = req->buf;
-+
-+ /* Was this a real packet? Should it be ignored? */
-+ if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-+ return -EINVAL;
-+
-+ /* Is the CBW valid? */
-+ if (req->actual != US_BULK_CB_WRAP_LEN ||
-+ cbw->Signature != cpu_to_le32(
-+ US_BULK_CB_SIGN)) {
-+ DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
-+ req->actual,
-+ le32_to_cpu(cbw->Signature));
-+
-+ /* The Bulk-only spec says we MUST stall the IN endpoint
-+ * (6.6.1), so it's unavoidable. It also says we must
-+ * retain this state until the next reset, but there's
-+ * no way to tell the controller driver it should ignore
-+ * Clear-Feature(HALT) requests.
-+ *
-+ * We aren't required to halt the OUT endpoint; instead
-+ * we can simply accept and discard any data received
-+ * until the next reset. */
-+ wedge_bulk_in_endpoint(fsg);
-+ set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
-+ return -EINVAL;
-+ }
-+
-+ /* Is the CBW meaningful? */
-+ if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
-+ cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
-+ DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
-+ "cmdlen %u\n",
-+ cbw->Lun, cbw->Flags, cbw->Length);
-+
-+ /* We can do anything we want here, so let's stall the
-+ * bulk pipes if we are allowed to. */
-+ if (mod_data.can_stall) {
-+ fsg_set_halt(fsg, fsg->bulk_out);
-+ halt_bulk_in_endpoint(fsg);
-+ }
-+ return -EINVAL;
-+ }
-+
-+ /* Save the command for later */
-+ fsg->cmnd_size = cbw->Length;
-+ memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
-+ if (cbw->Flags & US_BULK_FLAG_IN)
-+ fsg->data_dir = DATA_DIR_TO_HOST;
-+ else
-+ fsg->data_dir = DATA_DIR_FROM_HOST;
-+ fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
-+ if (fsg->data_size == 0)
-+ fsg->data_dir = DATA_DIR_NONE;
-+ fsg->lun = cbw->Lun;
-+ fsg->tag = cbw->Tag;
-+ return 0;
-+}
-+
-+
-+static int get_next_command(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh;
-+ int rc = 0;
-+
-+ if (transport_is_bbb()) {
-+
-+ /* Wait for the next buffer to become available */
-+ bh = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ /* Queue a request to read a Bulk-only CBW */
-+ set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
-+ start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+ &bh->outreq_busy, &bh->state);
-+
-+ /* We will drain the buffer in software, which means we
-+ * can reuse it for the next filling. No need to advance
-+ * next_buffhd_to_fill. */
-+
-+ /* Wait for the CBW to arrive */
-+ while (bh->state != BUF_STATE_FULL) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+ smp_rmb();
-+ rc = received_cbw(fsg, bh);
-+ bh->state = BUF_STATE_EMPTY;
-+
-+ } else { // USB_PR_CB or USB_PR_CBI
-+
-+ /* Wait for the next command to arrive */
-+ while (fsg->cbbuf_cmnd_size == 0) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ /* Is the previous status interrupt request still busy?
-+ * The host is allowed to skip reading the status,
-+ * so we must cancel it. */
-+ if (fsg->intreq_busy)
-+ usb_ep_dequeue(fsg->intr_in, fsg->intreq);
-+
-+ /* Copy the command and mark the buffer empty */
-+ fsg->data_dir = DATA_DIR_UNKNOWN;
-+ spin_lock_irq(&fsg->lock);
-+ fsg->cmnd_size = fsg->cbbuf_cmnd_size;
-+ memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
-+ fsg->cbbuf_cmnd_size = 0;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ /* Use LUN from the command */
-+ fsg->lun = fsg->cmnd[1] >> 5;
-+ }
-+
-+ /* Update current lun */
-+ if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
-+ fsg->curlun = &fsg->luns[fsg->lun];
-+ else
-+ fsg->curlun = NULL;
-+
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
-+ const struct usb_endpoint_descriptor *d)
-+{
-+ int rc;
-+
-+ ep->driver_data = fsg;
-+ ep->desc = d;
-+ rc = usb_ep_enable(ep);
-+ if (rc)
-+ ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
-+ return rc;
-+}
-+
-+static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
-+ struct usb_request **preq)
-+{
-+ *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
-+ if (*preq)
-+ return 0;
-+ ERROR(fsg, "can't allocate request for %s\n", ep->name);
-+ return -ENOMEM;
-+}
-+
-+/*
-+ * Reset interface setting and re-init endpoint state (toggle etc).
-+ * Call with altsetting < 0 to disable the interface. The only other
-+ * available altsetting is 0, which enables the interface.
-+ */
-+static int do_set_interface(struct fsg_dev *fsg, int altsetting)
-+{
-+ int rc = 0;
-+ int i;
-+ const struct usb_endpoint_descriptor *d;
-+
-+ if (fsg->running)
-+ DBG(fsg, "reset interface\n");
-+
-+reset:
-+ /* Deallocate the requests */
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+ if (bh->inreq) {
-+ usb_ep_free_request(fsg->bulk_in, bh->inreq);
-+ bh->inreq = NULL;
-+ }
-+ if (bh->outreq) {
-+ usb_ep_free_request(fsg->bulk_out, bh->outreq);
-+ bh->outreq = NULL;
-+ }
-+ }
-+ if (fsg->intreq) {
-+ usb_ep_free_request(fsg->intr_in, fsg->intreq);
-+ fsg->intreq = NULL;
-+ }
-+
-+ /* Disable the endpoints */
-+ if (fsg->bulk_in_enabled) {
-+ usb_ep_disable(fsg->bulk_in);
-+ fsg->bulk_in_enabled = 0;
-+ }
-+ if (fsg->bulk_out_enabled) {
-+ usb_ep_disable(fsg->bulk_out);
-+ fsg->bulk_out_enabled = 0;
-+ }
-+ if (fsg->intr_in_enabled) {
-+ usb_ep_disable(fsg->intr_in);
-+ fsg->intr_in_enabled = 0;
-+ }
-+
-+ fsg->running = 0;
-+ if (altsetting < 0 || rc != 0)
-+ return rc;
-+
-+ DBG(fsg, "set interface %d\n", altsetting);
-+
-+ /* Enable the endpoints */
-+ d = fsg_ep_desc(fsg->gadget,
-+ &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
-+ &fsg_ss_bulk_in_desc);
-+ if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
-+ goto reset;
-+ fsg->bulk_in_enabled = 1;
-+
-+ d = fsg_ep_desc(fsg->gadget,
-+ &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
-+ &fsg_ss_bulk_out_desc);
-+ if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
-+ goto reset;
-+ fsg->bulk_out_enabled = 1;
-+ fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
-+ clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
-+
-+ if (transport_is_cbi()) {
-+ d = fsg_ep_desc(fsg->gadget,
-+ &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
-+ &fsg_ss_intr_in_desc);
-+ if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
-+ goto reset;
-+ fsg->intr_in_enabled = 1;
-+ }
-+
-+ /* Allocate the requests */
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+ if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
-+ goto reset;
-+ if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
-+ goto reset;
-+ bh->inreq->buf = bh->outreq->buf = bh->buf;
-+ bh->inreq->context = bh->outreq->context = bh;
-+ bh->inreq->complete = bulk_in_complete;
-+ bh->outreq->complete = bulk_out_complete;
-+ }
-+ if (transport_is_cbi()) {
-+ if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
-+ goto reset;
-+ fsg->intreq->complete = intr_in_complete;
-+ }
-+
-+ fsg->running = 1;
-+ for (i = 0; i < fsg->nluns; ++i)
-+ fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
-+ return rc;
-+}
-+
-+
-+/*
-+ * Change our operational configuration. This code must agree with the code
-+ * that returns config descriptors, and with interface altsetting code.
-+ *
-+ * It's also responsible for power management interactions. Some
-+ * configurations might not work with our current power sources.
-+ * For now we just assume the gadget is always self-powered.
-+ */
-+static int do_set_config(struct fsg_dev *fsg, u8 new_config)
-+{
-+ int rc = 0;
-+
-+ /* Disable the single interface */
-+ if (fsg->config != 0) {
-+ DBG(fsg, "reset config\n");
-+ fsg->config = 0;
-+ rc = do_set_interface(fsg, -1);
-+ }
-+
-+ /* Enable the interface */
-+ if (new_config != 0) {
-+ fsg->config = new_config;
-+ if ((rc = do_set_interface(fsg, 0)) != 0)
-+ fsg->config = 0; // Reset on errors
-+ else
-+ INFO(fsg, "%s config #%d\n",
-+ usb_speed_string(fsg->gadget->speed),
-+ fsg->config);
-+ }
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void handle_exception(struct fsg_dev *fsg)
-+{
-+ siginfo_t info;
-+ int sig;
-+ int i;
-+ int num_active;
-+ struct fsg_buffhd *bh;
-+ enum fsg_state old_state;
-+ u8 new_config;
-+ struct fsg_lun *curlun;
-+ unsigned int exception_req_tag;
-+ int rc;
-+
-+ /* Clear the existing signals. Anything but SIGUSR1 is converted
-+ * into a high-priority EXIT exception. */
-+ for (;;) {
-+ sig = dequeue_signal_lock(current, &current->blocked, &info);
-+ if (!sig)
-+ break;
-+ if (sig != SIGUSR1) {
-+ if (fsg->state < FSG_STATE_EXIT)
-+ DBG(fsg, "Main thread exiting on signal\n");
-+ raise_exception(fsg, FSG_STATE_EXIT);
-+ }
-+ }
-+
-+ /* Cancel all the pending transfers */
-+ if (fsg->intreq_busy)
-+ usb_ep_dequeue(fsg->intr_in, fsg->intreq);
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ bh = &fsg->buffhds[i];
-+ if (bh->inreq_busy)
-+ usb_ep_dequeue(fsg->bulk_in, bh->inreq);
-+ if (bh->outreq_busy)
-+ usb_ep_dequeue(fsg->bulk_out, bh->outreq);
-+ }
-+
-+ /* Wait until everything is idle */
-+ for (;;) {
-+ num_active = fsg->intreq_busy;
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ bh = &fsg->buffhds[i];
-+ num_active += bh->inreq_busy + bh->outreq_busy;
-+ }
-+ if (num_active == 0)
-+ break;
-+ if (sleep_thread(fsg))
-+ return;
-+ }
-+
-+ /* Clear out the controller's fifos */
-+ if (fsg->bulk_in_enabled)
-+ usb_ep_fifo_flush(fsg->bulk_in);
-+ if (fsg->bulk_out_enabled)
-+ usb_ep_fifo_flush(fsg->bulk_out);
-+ if (fsg->intr_in_enabled)
-+ usb_ep_fifo_flush(fsg->intr_in);
-+
-+ /* Reset the I/O buffer states and pointers, the SCSI
-+ * state, and the exception. Then invoke the handler. */
-+ spin_lock_irq(&fsg->lock);
-+
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ bh = &fsg->buffhds[i];
-+ bh->state = BUF_STATE_EMPTY;
-+ }
-+ fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
-+ &fsg->buffhds[0];
-+
-+ exception_req_tag = fsg->exception_req_tag;
-+ new_config = fsg->new_config;
-+ old_state = fsg->state;
-+
-+ if (old_state == FSG_STATE_ABORT_BULK_OUT)
-+ fsg->state = FSG_STATE_STATUS_PHASE;
-+ else {
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ curlun->prevent_medium_removal = 0;
-+ curlun->sense_data = curlun->unit_attention_data =
-+ SS_NO_SENSE;
-+ curlun->sense_data_info = 0;
-+ curlun->info_valid = 0;
-+ }
-+ fsg->state = FSG_STATE_IDLE;
-+ }
-+ spin_unlock_irq(&fsg->lock);
-+
-+ /* Carry out any extra actions required for the exception */
-+ switch (old_state) {
-+ default:
-+ break;
-+
-+ case FSG_STATE_ABORT_BULK_OUT:
-+ send_status(fsg);
-+ spin_lock_irq(&fsg->lock);
-+ if (fsg->state == FSG_STATE_STATUS_PHASE)
-+ fsg->state = FSG_STATE_IDLE;
-+ spin_unlock_irq(&fsg->lock);
-+ break;
-+
-+ case FSG_STATE_RESET:
-+ /* In case we were forced against our will to halt a
-+ * bulk endpoint, clear the halt now. (The SuperH UDC
-+ * requires this.) */
-+ if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-+ usb_ep_clear_halt(fsg->bulk_in);
-+
-+ if (transport_is_bbb()) {
-+ if (fsg->ep0_req_tag == exception_req_tag)
-+ ep0_queue(fsg); // Complete the status stage
-+
-+ } else if (transport_is_cbi())
-+ send_status(fsg); // Status by interrupt pipe
-+
-+ /* Technically this should go here, but it would only be
-+ * a waste of time. Ditto for the INTERFACE_CHANGE and
-+ * CONFIG_CHANGE cases. */
-+ // for (i = 0; i < fsg->nluns; ++i)
-+ // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
-+ break;
-+
-+ case FSG_STATE_INTERFACE_CHANGE:
-+ rc = do_set_interface(fsg, 0);
-+ if (fsg->ep0_req_tag != exception_req_tag)
-+ break;
-+ if (rc != 0) // STALL on errors
-+ fsg_set_halt(fsg, fsg->ep0);
-+ else // Complete the status stage
-+ ep0_queue(fsg);
-+ break;
-+
-+ case FSG_STATE_CONFIG_CHANGE:
-+ rc = do_set_config(fsg, new_config);
-+ if (fsg->ep0_req_tag != exception_req_tag)
-+ break;
-+ if (rc != 0) // STALL on errors
-+ fsg_set_halt(fsg, fsg->ep0);
-+ else // Complete the status stage
-+ ep0_queue(fsg);
-+ break;
-+
-+ case FSG_STATE_DISCONNECT:
-+ for (i = 0; i < fsg->nluns; ++i)
-+ fsg_lun_fsync_sub(fsg->luns + i);
-+ do_set_config(fsg, 0); // Unconfigured state
-+ break;
-+
-+ case FSG_STATE_EXIT:
-+ case FSG_STATE_TERMINATED:
-+ do_set_config(fsg, 0); // Free resources
-+ spin_lock_irq(&fsg->lock);
-+ fsg->state = FSG_STATE_TERMINATED; // Stop the thread
-+ spin_unlock_irq(&fsg->lock);
-+ break;
-+ }
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int fsg_main_thread(void *fsg_)
-+{
-+ struct fsg_dev *fsg = fsg_;
-+
-+ /* Allow the thread to be killed by a signal, but set the signal mask
-+ * to block everything but INT, TERM, KILL, and USR1. */
-+ allow_signal(SIGINT);
-+ allow_signal(SIGTERM);
-+ allow_signal(SIGKILL);
-+ allow_signal(SIGUSR1);
-+
-+ /* Allow the thread to be frozen */
-+ set_freezable();
-+
-+ /* Arrange for userspace references to be interpreted as kernel
-+ * pointers. That way we can pass a kernel pointer to a routine
-+ * that expects a __user pointer and it will work okay. */
-+ set_fs(get_ds());
-+
-+ /* The main loop */
-+ while (fsg->state != FSG_STATE_TERMINATED) {
-+ if (exception_in_progress(fsg) || signal_pending(current)) {
-+ handle_exception(fsg);
-+ continue;
-+ }
-+
-+ if (!fsg->running) {
-+ sleep_thread(fsg);
-+ continue;
-+ }
-+
-+ if (get_next_command(fsg))
-+ continue;
-+
-+ spin_lock_irq(&fsg->lock);
-+ if (!exception_in_progress(fsg))
-+ fsg->state = FSG_STATE_DATA_PHASE;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ if (do_scsi_command(fsg) || finish_reply(fsg))
-+ continue;
-+
-+ spin_lock_irq(&fsg->lock);
-+ if (!exception_in_progress(fsg))
-+ fsg->state = FSG_STATE_STATUS_PHASE;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ if (send_status(fsg))
-+ continue;
-+
-+ spin_lock_irq(&fsg->lock);
-+ if (!exception_in_progress(fsg))
-+ fsg->state = FSG_STATE_IDLE;
-+ spin_unlock_irq(&fsg->lock);
-+ }
-+
-+ spin_lock_irq(&fsg->lock);
-+ fsg->thread_task = NULL;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ /* If we are exiting because of a signal, unregister the
-+ * gadget driver. */
-+ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
-+ usb_gadget_unregister_driver(&fsg_driver);
-+
-+ /* Let the unbind and cleanup routines know the thread has exited */
-+ complete_and_exit(&fsg->thread_notifier, 0);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/* The write permissions and store_xxx pointers are set in fsg_bind() */
-+static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
-+static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
-+static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void fsg_release(struct kref *ref)
-+{
-+ struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref);
-+
-+ kfree(fsg->luns);
-+ kfree(fsg);
-+}
-+
-+static void lun_release(struct device *dev)
-+{
-+ struct rw_semaphore *filesem = dev_get_drvdata(dev);
-+ struct fsg_dev *fsg =
-+ container_of(filesem, struct fsg_dev, filesem);
-+
-+ kref_put(&fsg->ref, fsg_release);
-+}
-+
-+static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+ int i;
-+ struct fsg_lun *curlun;
-+ struct usb_request *req = fsg->ep0req;
-+
-+ DBG(fsg, "unbind\n");
-+ clear_bit(REGISTERED, &fsg->atomic_bitflags);
-+
-+ /* If the thread isn't already dead, tell it to exit now */
-+ if (fsg->state != FSG_STATE_TERMINATED) {
-+ raise_exception(fsg, FSG_STATE_EXIT);
-+ wait_for_completion(&fsg->thread_notifier);
-+
-+ /* The cleanup routine waits for this completion also */
-+ complete(&fsg->thread_notifier);
-+ }
-+
-+ /* Unregister the sysfs attribute files and the LUNs */
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ if (curlun->registered) {
-+ device_remove_file(&curlun->dev, &dev_attr_nofua);
-+ device_remove_file(&curlun->dev, &dev_attr_ro);
-+ device_remove_file(&curlun->dev, &dev_attr_file);
-+ fsg_lun_close(curlun);
-+ device_unregister(&curlun->dev);
-+ curlun->registered = 0;
-+ }
-+ }
-+
-+ /* Free the data buffers */
-+ for (i = 0; i < fsg_num_buffers; ++i)
-+ kfree(fsg->buffhds[i].buf);
-+
-+ /* Free the request and buffer for endpoint 0 */
-+ if (req) {
-+ kfree(req->buf);
-+ usb_ep_free_request(fsg->ep0, req);
-+ }
-+
-+ set_gadget_data(gadget, NULL);
-+}
-+
-+
-+static int __init check_parameters(struct fsg_dev *fsg)
-+{
-+ int prot;
-+ int gcnum;
-+
-+ /* Store the default values */
-+ mod_data.transport_type = USB_PR_BULK;
-+ mod_data.transport_name = "Bulk-only";
-+ mod_data.protocol_type = USB_SC_SCSI;
-+ mod_data.protocol_name = "Transparent SCSI";
-+
-+ /* Some peripheral controllers are known not to be able to
-+ * halt bulk endpoints correctly. If one of them is present,
-+ * disable stalls.
-+ */
-+ if (gadget_is_at91(fsg->gadget))
-+ mod_data.can_stall = 0;
-+
-+ if (mod_data.release == 0xffff) { // Parameter wasn't set
-+ gcnum = usb_gadget_controller_number(fsg->gadget);
-+ if (gcnum >= 0)
-+ mod_data.release = 0x0300 + gcnum;
-+ else {
-+ WARNING(fsg, "controller '%s' not recognized\n",
-+ fsg->gadget->name);
-+ mod_data.release = 0x0399;
-+ }
-+ }
-+
-+ prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+ if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
-+ ; // Use default setting
-+ } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
-+ mod_data.transport_type = USB_PR_CB;
-+ mod_data.transport_name = "Control-Bulk";
-+ } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
-+ mod_data.transport_type = USB_PR_CBI;
-+ mod_data.transport_name = "Control-Bulk-Interrupt";
-+ } else {
-+ ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
-+ return -EINVAL;
-+ }
-+
-+ if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
-+ prot == USB_SC_SCSI) {
-+ ; // Use default setting
-+ } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
-+ prot == USB_SC_RBC) {
-+ mod_data.protocol_type = USB_SC_RBC;
-+ mod_data.protocol_name = "RBC";
-+ } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
-+ strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
-+ prot == USB_SC_8020) {
-+ mod_data.protocol_type = USB_SC_8020;
-+ mod_data.protocol_name = "8020i (ATAPI)";
-+ } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
-+ prot == USB_SC_QIC) {
-+ mod_data.protocol_type = USB_SC_QIC;
-+ mod_data.protocol_name = "QIC-157";
-+ } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
-+ prot == USB_SC_UFI) {
-+ mod_data.protocol_type = USB_SC_UFI;
-+ mod_data.protocol_name = "UFI";
-+ } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
-+ prot == USB_SC_8070) {
-+ mod_data.protocol_type = USB_SC_8070;
-+ mod_data.protocol_name = "8070i";
-+ } else {
-+ ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
-+ return -EINVAL;
-+ }
-+
-+ mod_data.buflen &= PAGE_CACHE_MASK;
-+ if (mod_data.buflen <= 0) {
-+ ERROR(fsg, "invalid buflen\n");
-+ return -ETOOSMALL;
-+ }
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+ /* Serial string handling.
-+ * On a real device, the serial string would be loaded
-+ * from permanent storage. */
-+ if (mod_data.serial) {
-+ const char *ch;
-+ unsigned len = 0;
-+
-+ /* Sanity check :
-+ * The CB[I] specification limits the serial string to
-+ * 12 uppercase hexadecimal characters.
-+ * BBB need at least 12 uppercase hexadecimal characters,
-+ * with a maximum of 126. */
-+ for (ch = mod_data.serial; *ch; ++ch) {
-+ ++len;
-+ if ((*ch < '0' || *ch > '9') &&
-+ (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
-+ WARNING(fsg,
-+ "Invalid serial string character: %c\n",
-+ *ch);
-+ goto no_serial;
-+ }
-+ }
-+ if (len > 126 ||
-+ (mod_data.transport_type == USB_PR_BULK && len < 12) ||
-+ (mod_data.transport_type != USB_PR_BULK && len > 12)) {
-+ WARNING(fsg, "Invalid serial string length!\n");
-+ goto no_serial;
-+ }
-+ fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
-+ } else {
-+ WARNING(fsg, "No serial-number string provided!\n");
-+ no_serial:
-+ device_desc.iSerialNumber = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static int __init fsg_bind(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = the_fsg;
-+ int rc;
-+ int i;
-+ struct fsg_lun *curlun;
-+ struct usb_ep *ep;
-+ struct usb_request *req;
-+ char *pathbuf, *p;
-+
-+ fsg->gadget = gadget;
-+ set_gadget_data(gadget, fsg);
-+ fsg->ep0 = gadget->ep0;
-+ fsg->ep0->driver_data = fsg;
-+
-+ if ((rc = check_parameters(fsg)) != 0)
-+ goto out;
-+
-+ if (mod_data.removable) { // Enable the store_xxx attributes
-+ dev_attr_file.attr.mode = 0644;
-+ dev_attr_file.store = fsg_store_file;
-+ if (!mod_data.cdrom) {
-+ dev_attr_ro.attr.mode = 0644;
-+ dev_attr_ro.store = fsg_store_ro;
-+ }
-+ }
-+
-+ /* Only for removable media? */
-+ dev_attr_nofua.attr.mode = 0644;
-+ dev_attr_nofua.store = fsg_store_nofua;
-+
-+ /* Find out how many LUNs there should be */
-+ i = mod_data.nluns;
-+ if (i == 0)
-+ i = max(mod_data.num_filenames, 1u);
-+ if (i > FSG_MAX_LUNS) {
-+ ERROR(fsg, "invalid number of LUNs: %d\n", i);
-+ rc = -EINVAL;
-+ goto out;
-+ }
-+
-+ /* Create the LUNs, open their backing files, and register the
-+ * LUN devices in sysfs. */
-+ fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
-+ if (!fsg->luns) {
-+ rc = -ENOMEM;
-+ goto out;
-+ }
-+ fsg->nluns = i;
-+
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ curlun->cdrom = !!mod_data.cdrom;
-+ curlun->ro = mod_data.cdrom || mod_data.ro[i];
-+ curlun->initially_ro = curlun->ro;
-+ curlun->removable = mod_data.removable;
-+ curlun->nofua = mod_data.nofua[i];
-+ curlun->dev.release = lun_release;
-+ curlun->dev.parent = &gadget->dev;
-+ curlun->dev.driver = &fsg_driver.driver;
-+ dev_set_drvdata(&curlun->dev, &fsg->filesem);
-+ dev_set_name(&curlun->dev,"%s-lun%d",
-+ dev_name(&gadget->dev), i);
-+
-+ kref_get(&fsg->ref);
-+ rc = device_register(&curlun->dev);
-+ if (rc) {
-+ INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
-+ put_device(&curlun->dev);
-+ goto out;
-+ }
-+ curlun->registered = 1;
-+
-+ rc = device_create_file(&curlun->dev, &dev_attr_ro);
-+ if (rc)
-+ goto out;
-+ rc = device_create_file(&curlun->dev, &dev_attr_nofua);
-+ if (rc)
-+ goto out;
-+ rc = device_create_file(&curlun->dev, &dev_attr_file);
-+ if (rc)
-+ goto out;
-+
-+ if (mod_data.file[i] && *mod_data.file[i]) {
-+ rc = fsg_lun_open(curlun, mod_data.file[i]);
-+ if (rc)
-+ goto out;
-+ } else if (!mod_data.removable) {
-+ ERROR(fsg, "no file given for LUN%d\n", i);
-+ rc = -EINVAL;
-+ goto out;
-+ }
-+ }
-+
-+ /* Find all the endpoints we will use */
-+ usb_ep_autoconfig_reset(gadget);
-+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
-+ if (!ep)
-+ goto autoconf_fail;
-+ ep->driver_data = fsg; // claim the endpoint
-+ fsg->bulk_in = ep;
-+
-+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
-+ if (!ep)
-+ goto autoconf_fail;
-+ ep->driver_data = fsg; // claim the endpoint
-+ fsg->bulk_out = ep;
-+
-+ if (transport_is_cbi()) {
-+ ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
-+ if (!ep)
-+ goto autoconf_fail;
-+ ep->driver_data = fsg; // claim the endpoint
-+ fsg->intr_in = ep;
-+ }
-+
-+ /* Fix up the descriptors */
-+ device_desc.idVendor = cpu_to_le16(mod_data.vendor);
-+ device_desc.idProduct = cpu_to_le16(mod_data.product);
-+ device_desc.bcdDevice = cpu_to_le16(mod_data.release);
-+
-+ i = (transport_is_cbi() ? 3 : 2); // Number of endpoints
-+ fsg_intf_desc.bNumEndpoints = i;
-+ fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
-+ fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
-+ fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+ if (gadget_is_dualspeed(gadget)) {
-+ fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+ /* Assume endpoint addresses are the same for both speeds */
-+ fsg_hs_bulk_in_desc.bEndpointAddress =
-+ fsg_fs_bulk_in_desc.bEndpointAddress;
-+ fsg_hs_bulk_out_desc.bEndpointAddress =
-+ fsg_fs_bulk_out_desc.bEndpointAddress;
-+ fsg_hs_intr_in_desc.bEndpointAddress =
-+ fsg_fs_intr_in_desc.bEndpointAddress;
-+ }
-+
-+ if (gadget_is_superspeed(gadget)) {
-+ unsigned max_burst;
-+
-+ fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+ /* Calculate bMaxBurst, we know packet size is 1024 */
-+ max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
-+
-+ /* Assume endpoint addresses are the same for both speeds */
-+ fsg_ss_bulk_in_desc.bEndpointAddress =
-+ fsg_fs_bulk_in_desc.bEndpointAddress;
-+ fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
-+
-+ fsg_ss_bulk_out_desc.bEndpointAddress =
-+ fsg_fs_bulk_out_desc.bEndpointAddress;
-+ fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
-+ }
-+
-+ if (gadget_is_otg(gadget))
-+ fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
-+
-+ rc = -ENOMEM;
-+
-+ /* Allocate the request and buffer for endpoint 0 */
-+ fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
-+ if (!req)
-+ goto out;
-+ req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
-+ if (!req->buf)
-+ goto out;
-+ req->complete = ep0_complete;
-+
-+ /* Allocate the data buffers */
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+ /* Allocate for the bulk-in endpoint. We assume that
-+ * the buffer will also work with the bulk-out (and
-+ * interrupt-in) endpoint. */
-+ bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
-+ if (!bh->buf)
-+ goto out;
-+ bh->next = bh + 1;
-+ }
-+ fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
-+
-+ /* This should reflect the actual gadget power source */
-+ usb_gadget_set_selfpowered(gadget);
-+
-+ snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
-+ "%s %s with %s",
-+ init_utsname()->sysname, init_utsname()->release,
-+ gadget->name);
-+
-+ fsg->thread_task = kthread_create(fsg_main_thread, fsg,
-+ "file-storage-gadget");
-+ if (IS_ERR(fsg->thread_task)) {
-+ rc = PTR_ERR(fsg->thread_task);
-+ goto out;
-+ }
-+
-+ INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
-+ INFO(fsg, "NOTE: This driver is deprecated. "
-+ "Consider using g_mass_storage instead.\n");
-+ INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
-+
-+ pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ if (fsg_lun_is_open(curlun)) {
-+ p = NULL;
-+ if (pathbuf) {
-+ p = d_path(&curlun->filp->f_path,
-+ pathbuf, PATH_MAX);
-+ if (IS_ERR(p))
-+ p = NULL;
-+ }
-+ LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
-+ curlun->ro, curlun->nofua, (p ? p : "(error)"));
-+ }
-+ }
-+ kfree(pathbuf);
-+
-+ DBG(fsg, "transport=%s (x%02x)\n",
-+ mod_data.transport_name, mod_data.transport_type);
-+ DBG(fsg, "protocol=%s (x%02x)\n",
-+ mod_data.protocol_name, mod_data.protocol_type);
-+ DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
-+ mod_data.vendor, mod_data.product, mod_data.release);
-+ DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
-+ mod_data.removable, mod_data.can_stall,
-+ mod_data.cdrom, mod_data.buflen);
-+ DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
-+
-+ set_bit(REGISTERED, &fsg->atomic_bitflags);
-+
-+ /* Tell the thread to start working */
-+ wake_up_process(fsg->thread_task);
-+ return 0;
-+
-+autoconf_fail:
-+ ERROR(fsg, "unable to autoconfigure all endpoints\n");
-+ rc = -ENOTSUPP;
-+
-+out:
-+ fsg->state = FSG_STATE_TERMINATED; // The thread is dead
-+ fsg_unbind(gadget);
-+ complete(&fsg->thread_notifier);
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void fsg_suspend(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+
-+ DBG(fsg, "suspend\n");
-+ set_bit(SUSPENDED, &fsg->atomic_bitflags);
-+}
-+
-+static void fsg_resume(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+
-+ DBG(fsg, "resume\n");
-+ clear_bit(SUSPENDED, &fsg->atomic_bitflags);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver fsg_driver = {
-+ .max_speed = USB_SPEED_SUPER,
-+ .function = (char *) fsg_string_product,
-+ .unbind = fsg_unbind,
-+ .disconnect = fsg_disconnect,
-+ .setup = fsg_setup,
-+ .suspend = fsg_suspend,
-+ .resume = fsg_resume,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ // .release = ...
-+ // .suspend = ...
-+ // .resume = ...
-+ },
-+};
-+
-+
-+static int __init fsg_alloc(void)
-+{
-+ struct fsg_dev *fsg;
-+
-+ fsg = kzalloc(sizeof *fsg +
-+ fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
-+
-+ if (!fsg)
-+ return -ENOMEM;
-+ spin_lock_init(&fsg->lock);
-+ init_rwsem(&fsg->filesem);
-+ kref_init(&fsg->ref);
-+ init_completion(&fsg->thread_notifier);
-+
-+ the_fsg = fsg;
-+ return 0;
-+}
-+
-+
-+static int __init fsg_init(void)
-+{
-+ int rc;
-+ struct fsg_dev *fsg;
-+
-+ rc = fsg_num_buffers_validate();
-+ if (rc != 0)
-+ return rc;
-+
-+ if ((rc = fsg_alloc()) != 0)
-+ return rc;
-+ fsg = the_fsg;
-+ if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
-+ kref_put(&fsg->ref, fsg_release);
-+ return rc;
-+}
-+module_init(fsg_init);
-+
-+
-+static void __exit fsg_cleanup(void)
-+{
-+ struct fsg_dev *fsg = the_fsg;
-+
-+ /* Unregister the driver iff the thread hasn't already done so */
-+ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
-+ usb_gadget_unregister_driver(&fsg_driver);
-+
-+ /* Wait for the thread to finish up */
-+ wait_for_completion(&fsg->thread_notifier);
-+
-+ kref_put(&fsg->ref, fsg_release);
-+}
-+module_exit(fsg_cleanup);
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/changes.txt linux-rpi/drivers/usb/host/dwc_common_port/changes.txt
---- linux-3.12.38/drivers/usb/host/dwc_common_port/changes.txt 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/changes.txt 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,174 @@
-+
-+dwc_read_reg32() and friends now take an additional parameter, a pointer to an
-+IO context struct. The IO context struct should live in an os-dependent struct
-+in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
-+named 'os_dep' embedded in the main device struct. So there these calls look
-+like this:
-+
-+ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
-+
-+ dwc_write_reg32(&usb3_dev->os_dep.ioctx,
-+ &pcd->dev_global_regs->dcfg, 0);
-+
-+Note that for the existing Linux driver ports, it is not necessary to actually
-+define the 'ioctx' member in the os-dependent struct. Since Linux does not
-+require an IO context, its macros for dwc_read_reg32() and friends do not
-+use the context pointer, so it is optimized away by the compiler. But it is
-+necessary to add the pointer parameter to all of the call sites, to be ready
-+for any future ports (such as FreeBSD) which do require an IO context.
-+
-+
-+Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
-+take an additional parameter, a pointer to a memory context. Examples:
-+
-+ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
-+
-+ dwc_free(&usb3_dev->os_dep.memctx, addr);
-+
-+Again, for the Linux ports, it is not necessary to actually define the memctx
-+member, but it is necessary to add the pointer parameter to all of the call
-+sites.
-+
-+
-+Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
-+
-+ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
-+
-+ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
-+
-+
-+Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
-+
-+ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
-+
-+ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
-+
-+
-+Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
-+
-+ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
-+
-+ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
-+
-+
-+Same for dwc_timer_alloc(). Example:
-+
-+ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
-+ cb_func, cb_data);
-+
-+
-+Same for dwc_waitq_alloc(). Example:
-+
-+ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
-+
-+
-+Same for dwc_thread_run(). Example:
-+
-+ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
-+ "dwc_usb3_thd1", data);
-+
-+
-+Same for dwc_workq_alloc(). Example:
-+
-+ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
-+
-+
-+Same for dwc_task_alloc(). Example:
-+
-+ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
-+ cb_func, cb_data);
-+
-+
-+In addition to the context pointer additions, a few core functions have had
-+other changes made to their parameters:
-+
-+The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
-+has been changed from a uint64_t to a dwc_irqflags_t.
-+
-+dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
-+FreeBSD equivalent of that function requires it.
-+
-+And, in addition to the context pointer, dwc_task_alloc() also adds a
-+'char *name' parameter, to be consistent with dwc_thread_run() and
-+dwc_workq_alloc(), and because the FreeBSD equivalent of that function
-+requires a unique name.
-+
-+
-+Here is a complete list of the core functions that now take a pointer to a
-+context as their first parameter:
-+
-+ dwc_read_reg32
-+ dwc_read_reg64
-+ dwc_write_reg32
-+ dwc_write_reg64
-+ dwc_modify_reg32
-+ dwc_modify_reg64
-+ dwc_alloc
-+ dwc_alloc_atomic
-+ dwc_strdup
-+ dwc_free
-+ dwc_dma_alloc
-+ dwc_dma_free
-+ dwc_mutex_alloc
-+ dwc_mutex_free
-+ dwc_spinlock_alloc
-+ dwc_spinlock_free
-+ dwc_timer_alloc
-+ dwc_waitq_alloc
-+ dwc_thread_run
-+ dwc_workq_alloc
-+ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter
-+
-+And here are the core functions that have other changes to their parameters:
-+
-+ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *'
-+ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
-+ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter
-+
-+
-+
-+The changes to the core functions also require some of the other library
-+functions to change:
-+
-+ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
-+ (for memory allocation) as the 1st param and a 'void *mtxctx'
-+ (for mutex allocation) as the 2nd param.
-+
-+ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
-+ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
-+ 'void *memctx' as the 1st param.
-+
-+ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
-+ 'void *memctx' as the 1st param.
-+
-+ dwc_modpow() now takes a 'void *memctx' as the 1st param.
-+
-+ dwc_alloc_notification_manager() now takes a 'void *memctx' as the
-+ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
-+ param, and also now returns an integer value that is non-zero if
-+ allocation of its data structures or work queue fails.
-+
-+ dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
-+
-+ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
-+ param, and also now returns an integer value that is non-zero if
-+ allocation of its data structures fails.
-+
-+
-+
-+Other miscellaneous changes:
-+
-+The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
-+DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
-+
-+The following #define's have been added to allow selectively compiling library
-+features:
-+
-+ DWC_CCLIB
-+ DWC_CRYPTOLIB
-+ DWC_NOTIFYLIB
-+ DWC_UTFLIB
-+
-+A DWC_LIBMODULE #define has also been added. If this is not defined, then the
-+module code in dwc_common_linux.c is not compiled in. This allows linking the
-+library code directly into a driver module, instead of as a standalone module.
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
---- linux-3.12.38/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,270 @@
-+# Doxyfile 1.4.5
-+
-+#---------------------------------------------------------------------------
-+# Project related configuration options
-+#---------------------------------------------------------------------------
-+PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB"
-+PROJECT_NUMBER =
-+OUTPUT_DIRECTORY = doc
-+CREATE_SUBDIRS = NO
-+OUTPUT_LANGUAGE = English
-+BRIEF_MEMBER_DESC = YES
-+REPEAT_BRIEF = YES
-+ABBREVIATE_BRIEF = "The $name class" \
-+ "The $name widget" \
-+ "The $name file" \
-+ is \
-+ provides \
-+ specifies \
-+ contains \
-+ represents \
-+ a \
-+ an \
-+ the
-+ALWAYS_DETAILED_SEC = YES
-+INLINE_INHERITED_MEMB = NO
-+FULL_PATH_NAMES = NO
-+STRIP_FROM_PATH = ..
-+STRIP_FROM_INC_PATH =
-+SHORT_NAMES = NO
-+JAVADOC_AUTOBRIEF = YES
-+MULTILINE_CPP_IS_BRIEF = NO
-+DETAILS_AT_TOP = YES
-+INHERIT_DOCS = YES
-+SEPARATE_MEMBER_PAGES = NO
-+TAB_SIZE = 8
-+ALIASES =
-+OPTIMIZE_OUTPUT_FOR_C = YES
-+OPTIMIZE_OUTPUT_JAVA = NO
-+BUILTIN_STL_SUPPORT = NO
-+DISTRIBUTE_GROUP_DOC = NO
-+SUBGROUPING = NO
-+#---------------------------------------------------------------------------
-+# Build related configuration options
-+#---------------------------------------------------------------------------
-+EXTRACT_ALL = NO
-+EXTRACT_PRIVATE = NO
-+EXTRACT_STATIC = YES
-+EXTRACT_LOCAL_CLASSES = NO
-+EXTRACT_LOCAL_METHODS = NO
-+HIDE_UNDOC_MEMBERS = NO
-+HIDE_UNDOC_CLASSES = NO
-+HIDE_FRIEND_COMPOUNDS = NO
-+HIDE_IN_BODY_DOCS = NO
-+INTERNAL_DOCS = NO
-+CASE_SENSE_NAMES = YES
-+HIDE_SCOPE_NAMES = NO
-+SHOW_INCLUDE_FILES = NO
-+INLINE_INFO = YES
-+SORT_MEMBER_DOCS = NO
-+SORT_BRIEF_DOCS = NO
-+SORT_BY_SCOPE_NAME = NO
-+GENERATE_TODOLIST = YES
-+GENERATE_TESTLIST = YES
-+GENERATE_BUGLIST = YES
-+GENERATE_DEPRECATEDLIST= YES
-+ENABLED_SECTIONS =
-+MAX_INITIALIZER_LINES = 30
-+SHOW_USED_FILES = YES
-+SHOW_DIRECTORIES = YES
-+FILE_VERSION_FILTER =
-+#---------------------------------------------------------------------------
-+# configuration options related to warning and progress messages
-+#---------------------------------------------------------------------------
-+QUIET = YES
-+WARNINGS = YES
-+WARN_IF_UNDOCUMENTED = NO
-+WARN_IF_DOC_ERROR = YES
-+WARN_NO_PARAMDOC = YES
-+WARN_FORMAT = "$file:$line: $text"
-+WARN_LOGFILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the input files
-+#---------------------------------------------------------------------------
-+INPUT = .
-+FILE_PATTERNS = *.c \
-+ *.cc \
-+ *.cxx \
-+ *.cpp \
-+ *.c++ \
-+ *.d \
-+ *.java \
-+ *.ii \
-+ *.ixx \
-+ *.ipp \
-+ *.i++ \
-+ *.inl \
-+ *.h \
-+ *.hh \
-+ *.hxx \
-+ *.hpp \
-+ *.h++ \
-+ *.idl \
-+ *.odl \
-+ *.cs \
-+ *.php \
-+ *.php3 \
-+ *.inc \
-+ *.m \
-+ *.mm \
-+ *.dox \
-+ *.py \
-+ *.C \
-+ *.CC \
-+ *.C++ \
-+ *.II \
-+ *.I++ \
-+ *.H \
-+ *.HH \
-+ *.H++ \
-+ *.CS \
-+ *.PHP \
-+ *.PHP3 \
-+ *.M \
-+ *.MM \
-+ *.PY
-+RECURSIVE = NO
-+EXCLUDE =
-+EXCLUDE_SYMLINKS = NO
-+EXCLUDE_PATTERNS =
-+EXAMPLE_PATH =
-+EXAMPLE_PATTERNS = *
-+EXAMPLE_RECURSIVE = NO
-+IMAGE_PATH =
-+INPUT_FILTER =
-+FILTER_PATTERNS =
-+FILTER_SOURCE_FILES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to source browsing
-+#---------------------------------------------------------------------------
-+SOURCE_BROWSER = NO
-+INLINE_SOURCES = NO
-+STRIP_CODE_COMMENTS = YES
-+REFERENCED_BY_RELATION = YES
-+REFERENCES_RELATION = YES
-+USE_HTAGS = NO
-+VERBATIM_HEADERS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the alphabetical class index
-+#---------------------------------------------------------------------------
-+ALPHABETICAL_INDEX = NO
-+COLS_IN_ALPHA_INDEX = 5
-+IGNORE_PREFIX =
-+#---------------------------------------------------------------------------
-+# configuration options related to the HTML output
-+#---------------------------------------------------------------------------
-+GENERATE_HTML = YES
-+HTML_OUTPUT = html
-+HTML_FILE_EXTENSION = .html
-+HTML_HEADER =
-+HTML_FOOTER =
-+HTML_STYLESHEET =
-+HTML_ALIGN_MEMBERS = YES
-+GENERATE_HTMLHELP = NO
-+CHM_FILE =
-+HHC_LOCATION =
-+GENERATE_CHI = NO
-+BINARY_TOC = NO
-+TOC_EXPAND = NO
-+DISABLE_INDEX = NO
-+ENUM_VALUES_PER_LINE = 4
-+GENERATE_TREEVIEW = YES
-+TREEVIEW_WIDTH = 250
-+#---------------------------------------------------------------------------
-+# configuration options related to the LaTeX output
-+#---------------------------------------------------------------------------
-+GENERATE_LATEX = NO
-+LATEX_OUTPUT = latex
-+LATEX_CMD_NAME = latex
-+MAKEINDEX_CMD_NAME = makeindex
-+COMPACT_LATEX = NO
-+PAPER_TYPE = a4wide
-+EXTRA_PACKAGES =
-+LATEX_HEADER =
-+PDF_HYPERLINKS = NO
-+USE_PDFLATEX = NO
-+LATEX_BATCHMODE = NO
-+LATEX_HIDE_INDICES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the RTF output
-+#---------------------------------------------------------------------------
-+GENERATE_RTF = NO
-+RTF_OUTPUT = rtf
-+COMPACT_RTF = NO
-+RTF_HYPERLINKS = NO
-+RTF_STYLESHEET_FILE =
-+RTF_EXTENSIONS_FILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the man page output
-+#---------------------------------------------------------------------------
-+GENERATE_MAN = NO
-+MAN_OUTPUT = man
-+MAN_EXTENSION = .3
-+MAN_LINKS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the XML output
-+#---------------------------------------------------------------------------
-+GENERATE_XML = NO
-+XML_OUTPUT = xml
-+XML_SCHEMA =
-+XML_DTD =
-+XML_PROGRAMLISTING = YES
-+#---------------------------------------------------------------------------
-+# configuration options for the AutoGen Definitions output
-+#---------------------------------------------------------------------------
-+GENERATE_AUTOGEN_DEF = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the Perl module output
-+#---------------------------------------------------------------------------
-+GENERATE_PERLMOD = NO
-+PERLMOD_LATEX = NO
-+PERLMOD_PRETTY = YES
-+PERLMOD_MAKEVAR_PREFIX =
-+#---------------------------------------------------------------------------
-+# Configuration options related to the preprocessor
-+#---------------------------------------------------------------------------
-+ENABLE_PREPROCESSING = YES
-+MACRO_EXPANSION = NO
-+EXPAND_ONLY_PREDEF = NO
-+SEARCH_INCLUDES = YES
-+INCLUDE_PATH =
-+INCLUDE_FILE_PATTERNS =
-+PREDEFINED = DEBUG DEBUG_MEMORY
-+EXPAND_AS_DEFINED =
-+SKIP_FUNCTION_MACROS = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to external references
-+#---------------------------------------------------------------------------
-+TAGFILES =
-+GENERATE_TAGFILE =
-+ALLEXTERNALS = NO
-+EXTERNAL_GROUPS = YES
-+PERL_PATH = /usr/bin/perl
-+#---------------------------------------------------------------------------
-+# Configuration options related to the dot tool
-+#---------------------------------------------------------------------------
-+CLASS_DIAGRAMS = YES
-+HIDE_UNDOC_RELATIONS = YES
-+HAVE_DOT = NO
-+CLASS_GRAPH = YES
-+COLLABORATION_GRAPH = YES
-+GROUP_GRAPHS = YES
-+UML_LOOK = NO
-+TEMPLATE_RELATIONS = NO
-+INCLUDE_GRAPH = NO
-+INCLUDED_BY_GRAPH = YES
-+CALL_GRAPH = NO
-+GRAPHICAL_HIERARCHY = YES
-+DIRECTORY_GRAPH = YES
-+DOT_IMAGE_FORMAT = png
-+DOT_PATH =
-+DOTFILE_DIRS =
-+MAX_DOT_GRAPH_DEPTH = 1000
-+DOT_TRANSPARENT = NO
-+DOT_MULTI_TARGETS = NO
-+GENERATE_LEGEND = YES
-+DOT_CLEANUP = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to the search engine
-+#---------------------------------------------------------------------------
-+SEARCHENGINE = NO
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_cc.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_cc.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,532 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
-+ * $Revision: #4 $
-+ * $Date: 2010/11/04 $
-+ * $Change: 1621692 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifdef DWC_CCLIB
-+
-+#include "dwc_cc.h"
-+
-+typedef struct dwc_cc
-+{
-+ uint32_t uid;
-+ uint8_t chid[16];
-+ uint8_t cdid[16];
-+ uint8_t ck[16];
-+ uint8_t *name;
-+ uint8_t length;
-+ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
-+} dwc_cc_t;
-+
-+DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
-+
-+/** The main structure for CC management. */
-+struct dwc_cc_if
-+{
-+ dwc_mutex_t *mutex;
-+ char *filename;
-+
-+ unsigned is_host:1;
-+
-+ dwc_notifier_t *notifier;
-+
-+ struct context_list list;
-+};
-+
-+#ifdef DEBUG
-+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
-+{
-+ int i;
-+ DWC_PRINTF("%s: ", name);
-+ for (i=0; i<len; i++) {
-+ DWC_PRINTF("%02x ", bytes[i]);
-+ }
-+ DWC_PRINTF("\n");
-+}
-+#else
-+#define dump_bytes(x...)
-+#endif
-+
-+static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
-+{
-+ dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
-+ if (!cc) {
-+ return NULL;
-+ }
-+ DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
-+
-+ if (name) {
-+ cc->length = length;
-+ cc->name = dwc_alloc(mem_ctx, length);
-+ if (!cc->name) {
-+ dwc_free(mem_ctx, cc);
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(cc->name, name, length);
-+ }
-+
-+ return cc;
-+}
-+
-+static void free_cc(void *mem_ctx, dwc_cc_t *cc)
-+{
-+ if (cc->name) {
-+ dwc_free(mem_ctx, cc->name);
-+ }
-+ dwc_free(mem_ctx, cc);
-+}
-+
-+static uint32_t next_uid(dwc_cc_if_t *cc_if)
-+{
-+ uint32_t uid = 0;
-+ dwc_cc_t *cc;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (cc->uid > uid) {
-+ uid = cc->uid;
-+ }
-+ }
-+
-+ if (uid == 0) {
-+ uid = 255;
-+ }
-+
-+ return uid + 1;
-+}
-+
-+static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
-+{
-+ dwc_cc_t *cc;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (cc->uid == uid) {
-+ return cc;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
-+{
-+ unsigned int size = 0;
-+ dwc_cc_t *cc;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ size += (48 + 1);
-+ if (cc->name) {
-+ size += cc->length;
-+ }
-+ }
-+ return size;
-+}
-+
-+static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
-+{
-+ uint32_t uid = 0;
-+ dwc_cc_t *cc;
-+
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
-+ uid = cc->uid;
-+ break;
-+ }
-+ }
-+ return uid;
-+}
-+static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
-+{
-+ uint32_t uid = 0;
-+ dwc_cc_t *cc;
-+
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
-+ uid = cc->uid;
-+ break;
-+ }
-+ }
-+ return uid;
-+}
-+
-+/* Internal cc_add */
-+static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+ dwc_cc_t *cc;
-+ uint32_t uid;
-+
-+ if (cc_if->is_host) {
-+ uid = cc_match_cdid(cc_if, cdid);
-+ }
-+ else {
-+ uid = cc_match_chid(cc_if, chid);
-+ }
-+
-+ if (uid) {
-+ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
-+ cc = cc_find(cc_if, uid);
-+ }
-+ else {
-+ cc = alloc_cc(mem_ctx, name, length);
-+ cc->uid = next_uid(cc_if);
-+ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
-+ }
-+
-+ DWC_MEMCPY(&(cc->chid[0]), chid, 16);
-+ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
-+ DWC_MEMCPY(&(cc->ck[0]), ck, 16);
-+
-+ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
-+ dump_bytes("CHID", cc->chid, 16);
-+ dump_bytes("CDID", cc->cdid, 16);
-+ dump_bytes("CK", cc->ck, 16);
-+ return cc->uid;
-+}
-+
-+/* Internal cc_clear */
-+static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
-+{
-+ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
-+ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
-+ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
-+ free_cc(mem_ctx, cc);
-+ }
-+}
-+
-+dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
-+ dwc_notifier_t *notifier, unsigned is_host)
-+{
-+ dwc_cc_if_t *cc_if = NULL;
-+
-+ /* Allocate a common_cc_if structure */
-+ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
-+
-+ if (!cc_if)
-+ return NULL;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
-+#else
-+ cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
-+#endif
-+ if (!cc_if->mutex) {
-+ dwc_free(mem_ctx, cc_if);
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&cc_if->list);
-+ cc_if->is_host = is_host;
-+ cc_if->notifier = notifier;
-+ return cc_if;
-+}
-+
-+void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
-+{
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+ DWC_MUTEX_FREE(cc_if->mutex);
-+#else
-+ dwc_mutex_free(mtx_ctx, cc_if->mutex);
-+#endif
-+ cc_clear(mem_ctx, cc_if);
-+ dwc_free(mem_ctx, cc_if);
-+}
-+
-+static void cc_changed(dwc_cc_if_t *cc_if)
-+{
-+ if (cc_if->notifier) {
-+ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
-+ }
-+}
-+
-+void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
-+{
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc_clear(mem_ctx, cc_if);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ cc_changed(cc_if);
-+}
-+
-+int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+ uint32_t uid;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ cc_changed(cc_if);
-+
-+ return uid;
-+}
-+
-+void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+ dwc_cc_t* cc;
-+
-+ DWC_DEBUGC("Change connection context %d", id);
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (!cc) {
-+ DWC_ERROR("Uid %d not found in cc list\n", id);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return;
-+ }
-+
-+ if (chid) {
-+ DWC_MEMCPY(&(cc->chid[0]), chid, 16);
-+ }
-+ if (cdid) {
-+ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
-+ }
-+ if (ck) {
-+ DWC_MEMCPY(&(cc->ck[0]), ck, 16);
-+ }
-+
-+ if (name) {
-+ if (cc->name) {
-+ dwc_free(mem_ctx, cc->name);
-+ }
-+ cc->name = dwc_alloc(mem_ctx, length);
-+ if (!cc->name) {
-+ DWC_ERROR("Out of memory in dwc_cc_change()\n");
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return;
-+ }
-+ cc->length = length;
-+ DWC_MEMCPY(cc->name, name, length);
-+ }
-+
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ cc_changed(cc_if);
-+
-+ DWC_DEBUGC("Changed connection context id=%d\n", id);
-+ dump_bytes("New CHID", cc->chid, 16);
-+ dump_bytes("New CDID", cc->cdid, 16);
-+ dump_bytes("New CK", cc->ck, 16);
-+}
-+
-+void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ dwc_cc_t *cc;
-+
-+ DWC_DEBUGC("Removing connection context %d", id);
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (!cc) {
-+ DWC_ERROR("Uid %d not found in cc list\n", id);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ free_cc(mem_ctx, cc);
-+
-+ cc_changed(cc_if);
-+}
-+
-+uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
-+{
-+ uint8_t *buf, *x;
-+ uint8_t zero = 0;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ *length = cc_data_size(cc_if);
-+ if (!(*length)) {
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return NULL;
-+ }
-+
-+ DWC_DEBUGC("Creating data for saving (length=%d)", *length);
-+
-+ buf = dwc_alloc(mem_ctx, *length);
-+ if (!buf) {
-+ *length = 0;
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return NULL;
-+ }
-+
-+ x = buf;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ DWC_MEMCPY(x, cc->chid, 16);
-+ x += 16;
-+ DWC_MEMCPY(x, cc->cdid, 16);
-+ x += 16;
-+ DWC_MEMCPY(x, cc->ck, 16);
-+ x += 16;
-+ if (cc->name) {
-+ DWC_MEMCPY(x, &cc->length, 1);
-+ x += 1;
-+ DWC_MEMCPY(x, cc->name, cc->length);
-+ x += cc->length;
-+ }
-+ else {
-+ DWC_MEMCPY(x, &zero, 1);
-+ x += 1;
-+ }
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return buf;
-+}
-+
-+void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
-+{
-+ uint8_t name_length;
-+ uint8_t *name;
-+ uint8_t *chid;
-+ uint8_t *cdid;
-+ uint8_t *ck;
-+ uint32_t i = 0;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc_clear(mem_ctx, cc_if);
-+
-+ while (i < length) {
-+ chid = &data[i];
-+ i += 16;
-+ cdid = &data[i];
-+ i += 16;
-+ ck = &data[i];
-+ i += 16;
-+
-+ name_length = data[i];
-+ i ++;
-+
-+ if (name_length) {
-+ name = &data[i];
-+ i += name_length;
-+ }
-+ else {
-+ name = NULL;
-+ }
-+
-+ /* check to see if we haven't overflown the buffer */
-+ if (i > length) {
-+ DWC_ERROR("Data format error while attempting to load CCs "
-+ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
-+ break;
-+ }
-+
-+ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ cc_changed(cc_if);
-+}
-+
-+uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
-+{
-+ uint32_t uid = 0;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ uid = cc_match_chid(cc_if, chid);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return uid;
-+}
-+uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
-+{
-+ uint32_t uid = 0;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ uid = cc_match_cdid(cc_if, cdid);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return uid;
-+}
-+
-+uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ uint8_t *ck = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ ck = cc->ck;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return ck;
-+
-+}
-+
-+uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ uint8_t *retval = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ retval = cc->chid;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return retval;
-+}
-+
-+uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ uint8_t *retval = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ retval = cc->cdid;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return retval;
-+}
-+
-+uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
-+{
-+ uint8_t *retval = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ *length = 0;
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ *length = cc->length;
-+ retval = cc->name;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return retval;
-+}
-+
-+#endif /* DWC_CCLIB */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_cc.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_cc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,224 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
-+ * $Revision: #4 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_CC_H_
-+#define _DWC_CC_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file defines the Context Context library.
-+ *
-+ * The main data structure is dwc_cc_if_t which is returned by either the
-+ * dwc_cc_if_alloc function or returned by the module to the user via a provided
-+ * function. The data structure is opaque and should only be manipulated via the
-+ * functions provied in this API.
-+ *
-+ * It manages a list of connection contexts and operations can be performed to
-+ * add, remove, query, search, and change, those contexts. Additionally,
-+ * a dwc_notifier_t object can be requested from the manager so that
-+ * the user can be notified whenever the context list has changed.
-+ */
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+#include "dwc_notifier.h"
-+
-+
-+/* Notifications */
-+#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
-+
-+struct dwc_cc_if;
-+typedef struct dwc_cc_if dwc_cc_if_t;
-+
-+
-+/** @name Connection Context Operations */
-+/** @{ */
-+
-+/** This function allocates memory for a dwc_cc_if_t structure, initializes
-+ * fields to default values, and returns a pointer to the structure or NULL on
-+ * error. */
-+extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
-+ dwc_notifier_t *notifier, unsigned is_host);
-+
-+/** Frees the memory for the specified CC structure allocated from
-+ * dwc_cc_if_alloc(). */
-+extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
-+
-+/** Removes all contexts from the connection context list */
-+extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
-+
-+/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
-+ * If a CHID already exists, the CK and name are overwritten. Statistics are
-+ * not overwritten.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param chid A pointer to the 16-byte CHID. This value will be copied.
-+ * @param ck A pointer to the 16-byte CK. This value will be copied.
-+ * @param cdid A pointer to the 16-byte CDID. This value will be copied.
-+ * @param name An optional host friendly name as defined in the association model
-+ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
-+ * @param length The length othe unicode string.
-+ * @return A unique identifier used to refer to this context that is valid for
-+ * as long as this context is still in the list. */
-+extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name,
-+ uint8_t length);
-+
-+/** Changes the CHID, CK, CDID, or Name values of a connection context in the
-+ * list, preserving any accumulated statistics. This would typically be called
-+ * if the host decideds to change the context with a SET_CONNECTION request.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL
-+ * indicates no change.
-+ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL
-+ * indicates no change.
-+ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL
-+ * indicates no change.
-+ * @param name Host friendly name UTF16-LE. NULL indicates no change.
-+ * @param length Length of name. */
-+extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
-+ uint8_t *chid, uint8_t *cdid, uint8_t *ck,
-+ uint8_t *name, uint8_t length);
-+
-+/** Remove the specified connection context.
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context to remove. */
-+extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Get a binary block of data for the connection context list and attributes.
-+ * This data can be used by the OS specific driver to save the connection
-+ * context list into non-volatile memory.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param length Return the length of the data buffer.
-+ * @return A pointer to the data buffer. The memory for this buffer should be
-+ * freed with DWC_FREE() after use. */
-+extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
-+ unsigned int *length);
-+
-+/** Restore the connection context list from the binary data that was previously
-+ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific
-+ * driver to load a connection context list from non-volatile memory.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param data The data bytes as returned from dwc_cc_data_for_save.
-+ * @param length The length of the data. */
-+extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
-+ uint8_t *data, unsigned int length);
-+
-+/** Find the connection context from the specified CHID.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param chid A pointer to the CHID data.
-+ * @return A non-zero identifier of the connection context if the CHID matches.
-+ * Otherwise returns 0. */
-+extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
-+
-+/** Find the connection context from the specified CDID.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param cdid A pointer to the CDID data.
-+ * @return A non-zero identifier of the connection context if the CHID matches.
-+ * Otherwise returns 0. */
-+extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
-+
-+/** Retrieve the CK from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CK data. The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Retrieve the CHID from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CHID data. The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Retrieve the CDID from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CDID data. The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
-+
-+extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
-+
-+/** Checks a buffer for non-zero.
-+ * @param id A pointer to a 16 byte buffer.
-+ * @return true if the 16 byte value is non-zero. */
-+static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
-+ int i;
-+ for (i=0; i<16; i++) {
-+ if (id[i]) return 1;
-+ }
-+ return 0;
-+}
-+
-+/** Checks a buffer for zero.
-+ * @param id A pointer to a 16 byte buffer.
-+ * @return true if the 16 byte value is zero. */
-+static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
-+ return !dwc_assoc_is_not_zero_id(id);
-+}
-+
-+/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
-+ * buffer. */
-+static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
-+ char *ptr = buffer;
-+ int i;
-+ for (i=0; i<16; i++) {
-+ ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
-+ if (i < 15) {
-+ ptr += DWC_SPRINTF(ptr, " ");
-+ }
-+ }
-+ return ptr - buffer;
-+}
-+
-+/** @} */
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_CC_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,1308 @@
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+ return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+ return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+ bcopy(src, dest, size);
-+ return dest;
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+ return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+ return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+ return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+ return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+ return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+ int len = DWC_STRLEN(str) + 1;
-+ char *new = DWC_ALLOC_ATOMIC(len);
-+
-+ if (!new) {
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(new, str, len);
-+ return new;
-+}
-+
-+int DWC_ATOI(char *str, int32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = strtol(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+int DWC_ATOUI(char *str, uint32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+#endif /* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+// return in_irq();
-+ return 0;
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+// return in_softirq();
-+ return 0;
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+ vprintf(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+ return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsprintf(buffer, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsnprintf(buffer, size, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+// BUG_ON(1); ???
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+ uint32_t align,
-+ uint32_t alloc)
-+{
-+ struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+ size, align, alloc);
-+ return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+ dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+ memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+ dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
-+{
-+ if (error)
-+ return;
-+ *(bus_addr_t *)arg = segs[0].ds_addr;
-+}
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+ int error;
-+
-+ error = bus_dma_tag_create(
-+#if __FreeBSD_version >= 700000
-+ bus_get_dma_tag(dma->dev), /* parent */
-+#else
-+ NULL, /* parent */
-+#endif
-+ 4, 0, /* alignment, bounds */
-+ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
-+ BUS_SPACE_MAXADDR, /* highaddr */
-+ NULL, NULL, /* filter, filterarg */
-+ size, /* maxsize */
-+ 1, /* nsegments */
-+ size, /* maxsegsize */
-+ 0, /* flags */
-+ NULL, /* lockfunc */
-+ NULL, /* lockarg */
-+ &dma->dma_tag);
-+ if (error) {
-+ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
-+ __func__, error);
-+ goto fail_0;
-+ }
-+
-+ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
-+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
-+ if (error) {
-+ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
-+ __func__, (uintmax_t)size, error);
-+ goto fail_1;
-+ }
-+
-+ dma->dma_paddr = 0;
-+ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
-+ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
-+ if (error || dma->dma_paddr == 0) {
-+ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
-+ __func__, error);
-+ goto fail_2;
-+ }
-+
-+ *dma_addr = dma->dma_paddr;
-+ return dma->dma_vaddr;
-+
-+fail_2:
-+ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+fail_1:
-+ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
-+ bus_dma_tag_destroy(dma->dma_tag);
-+fail_0:
-+ dma->dma_map = NULL;
-+ dma->dma_tag = NULL;
-+
-+ return NULL;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+
-+ if (dma->dma_tag == NULL)
-+ return;
-+ if (dma->dma_map != NULL) {
-+ bus_dmamap_sync(dma->dma_tag, dma->dma_map,
-+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-+ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
-+ dma->dma_map = NULL;
-+ }
-+
-+ bus_dma_tag_destroy(dma->dma_tag);
-+ dma->dma_tag = NULL;
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+ free(addr, M_DEVBUF);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+ get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+ struct crypto_blkcipher *tfm;
-+ struct blkcipher_desc desc;
-+ struct scatterlist sgd;
-+ struct scatterlist sgs;
-+
-+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+ if (tfm == NULL) {
-+ printk("failed to load transform for aes CBC\n");
-+ return -1;
-+ }
-+
-+ crypto_blkcipher_setkey(tfm, key, keylen);
-+ crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+ sg_init_one(&sgd, out, messagelen);
-+ sg_init_one(&sgs, message, messagelen);
-+
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+ crypto_free_blkcipher(tfm);
-+ DWC_ERROR("AES CBC encryption failed");
-+ return -1;
-+ }
-+
-+ crypto_free_blkcipher(tfm);
-+ return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, len);
-+ crypto_hash_digest(&desc, &sg, len, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, messagelen);
-+ crypto_hash_setkey(tfm, key, keylen);
-+ crypto_hash_digest(&desc, &sg, messagelen, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_4(io->iot, io->ioh, ior);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_8(io->iot, io->ioh, ior);
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior, value);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior, value);
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
-+ uint32_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior,
-+ (bus_space_read_4(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
-+ uint64_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior,
-+ (bus_space_read_8(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+ struct mtx *sl = DWC_ALLOC(sizeof(*sl));
-+
-+ if (!sl) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ return NULL;
-+ }
-+
-+ mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
-+ return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+ struct mtx *sl = (struct mtx *)lock;
-+
-+ mtx_destroy(sl);
-+ DWC_FREE(sl);
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+ mtx_lock_spin((struct mtx *)lock); // ???
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+ mtx_unlock_spin((struct mtx *)lock); // ???
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+ mtx_lock_spin((struct mtx *)lock);
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+ mtx_unlock_spin((struct mtx *)lock);
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+ struct mtx *m;
-+ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
-+
-+ if (!mutex) {
-+ DWC_ERROR("Cannot allocate memory for mutex");
-+ return NULL;
-+ }
-+
-+ m = (struct mtx *)mutex;
-+ mtx_init(m, "dw3mtx", NULL, MTX_DEF);
-+ return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+ mtx_destroy((struct mtx *)mutex);
-+ DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+ struct mtx *m = (struct mtx *)mutex;
-+
-+ mtx_lock(m);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mtx *m = (struct mtx *)mutex;
-+
-+ return mtx_trylock(m);
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mtx *m = (struct mtx *)mutex;
-+
-+ mtx_unlock(m);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+ DELAY(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+ do {
-+ DELAY(1000);
-+ } while (--msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+ pause("dw3slp", tvtohz(&tv));
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+ struct timeval tv;
-+
-+ microuptime(&tv); // or getmicrouptime? (less precise, but faster)
-+ return tv.tv_sec * 1000 + tv.tv_usec / 1000;
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+ struct callout t;
-+ char *name;
-+ dwc_spinlock_t *lock;
-+ dwc_timer_callback_t cb;
-+ void *data;
-+};
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (!t) {
-+ DWC_ERROR("Cannot allocate memory for timer");
-+ return NULL;
-+ }
-+
-+ callout_init(&t->t, 1);
-+
-+ t->name = DWC_STRDUP(name);
-+ if (!t->name) {
-+ DWC_ERROR("Cannot allocate memory for timer->name");
-+ goto no_name;
-+ }
-+
-+ t->lock = DWC_SPINLOCK_ALLOC();
-+ if (!t->lock) {
-+ DWC_ERROR("Cannot allocate memory for lock");
-+ goto no_lock;
-+ }
-+
-+ t->cb = cb;
-+ t->data = data;
-+
-+ return t;
-+
-+ no_lock:
-+ DWC_FREE(t->name);
-+ no_name:
-+ DWC_FREE(t);
-+
-+ return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+ DWC_SPINLOCK_FREE(timer->lock);
-+ DWC_FREE(timer->name);
-+ DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+ struct mtx lock;
-+ int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ return NULL;
-+ }
-+
-+ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
-+ wq->abort = 0;
-+
-+ return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+ mtx_destroy(&wq->lock);
-+ DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+// intrmask_t ipl;
-+ int result = 0;
-+
-+ mtx_lock(&wq->lock);
-+// ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+// splx(ipl);
-+ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
-+// ipl = splbio();
-+ }
-+
-+ if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+
-+ } else if (result == EINTR) { // signaled - interrupt
-+ result = -DWC_E_ABORT;
-+
-+ } else if (wq->abort) {
-+ result = -DWC_E_ABORT;
-+
-+ } else {
-+ result = 0;
-+ }
-+
-+ wq->abort = 0;
-+// splx(ipl);
-+ mtx_unlock(&wq->lock);
-+ return result;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs)
-+{
-+ struct timeval tv, tv1, tv2;
-+// intrmask_t ipl;
-+ int result = 0;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+
-+ mtx_lock(&wq->lock);
-+// ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+// splx(ipl);
-+ getmicrouptime(&tv1);
-+ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
-+ getmicrouptime(&tv2);
-+// ipl = splbio();
-+ }
-+
-+ if (result == 0) { // awoken
-+ if (wq->abort) {
-+ result = -DWC_E_ABORT;
-+ } else {
-+ tv2.tv_usec -= tv1.tv_usec;
-+ if (tv2.tv_usec < 0) {
-+ tv2.tv_usec += 1000000;
-+ tv2.tv_sec--;
-+ }
-+
-+ tv2.tv_sec -= tv1.tv_sec;
-+ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
-+ result = msecs - result;
-+ if (result <= 0)
-+ result = 1;
-+ }
-+ } else if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+
-+ } else if (result == EINTR) { // signaled - interrupt
-+ result = -DWC_E_ABORT;
-+
-+ } else { // timed out
-+ result = -DWC_E_TIMEOUT;
-+ }
-+
-+ wq->abort = 0;
-+// splx(ipl);
-+ mtx_unlock(&wq->lock);
-+ return result;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+ wakeup(wq);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+// intrmask_t ipl;
-+
-+ mtx_lock(&wq->lock);
-+// ipl = splbio();
-+ wq->abort = 1;
-+ wakeup(wq);
-+// splx(ipl);
-+ mtx_unlock(&wq->lock);
-+}
-+
-+
-+/* Threading */
-+
-+struct dwc_thread {
-+ struct proc *proc;
-+ int abort;
-+};
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+ int retval;
-+ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
-+
-+ if (!thread) {
-+ return NULL;
-+ }
-+
-+ thread->abort = 0;
-+ retval = kthread_create((void (*)(void *))func, data, &thread->proc,
-+ RFPROC | RFNOWAIT, 0, "%s", name);
-+ if (retval) {
-+ DWC_FREE(thread);
-+ return NULL;
-+ }
-+
-+ return thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+ int retval;
-+
-+ thread->abort = 1;
-+ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
-+
-+ if (retval == 0) {
-+ /* DWC_THREAD_EXIT() will free the thread struct */
-+ return 0;
-+ }
-+
-+ /* NOTE: We leak the thread struct if thread doesn't die */
-+
-+ if (retval == EWOULDBLOCK) {
-+ return -DWC_E_TIMEOUT;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
-+{
-+ return thread->abort;
-+}
-+
-+void DWC_THREAD_EXIT(dwc_thread_t *thread)
-+{
-+ wakeup(&thread->abort);
-+ DWC_FREE(thread);
-+ kthread_exit(0);
-+}
-+
-+
-+/* tasklets
-+ - Runs in interrupt context (cannot sleep)
-+ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
-+ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
-+ */
-+struct dwc_tasklet {
-+ struct task t;
-+ dwc_tasklet_callback_t cb;
-+ void *data;
-+};
-+
-+static void tasklet_callback(void *data, int pending) // what to do with pending ???
-+{
-+ dwc_tasklet_t *task = (dwc_tasklet_t *)data;
-+
-+ task->cb(task->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
-+
-+ if (task) {
-+ task->cb = cb;
-+ task->data = data;
-+ TASK_INIT(&task->t, 0, tasklet_callback, task);
-+ } else {
-+ DWC_ERROR("Cannot allocate memory for tasklet");
-+ }
-+
-+ return task;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+ taskqueue_drain(taskqueue_fast, &task->t); // ???
-+ DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ /* Uses predefined system queue */
-+ taskqueue_enqueue_fast(taskqueue_fast, &task->t);
-+}
-+
-+
-+/* workqueues
-+ - Runs in process context (can sleep)
-+ */
-+typedef struct work_container {
-+ dwc_work_callback_t cb;
-+ void *data;
-+ dwc_workq_t *wq;
-+ char *name;
-+ int hz;
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_ENTRY(work_container) entry;
-+#endif
-+ struct task task;
-+} work_container_t;
-+
-+#ifdef DEBUG
-+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
-+#endif
-+
-+struct dwc_workq {
-+ struct taskqueue *taskq;
-+ dwc_spinlock_t *lock;
-+ dwc_waitq_t *waitq;
-+ int pending;
-+
-+#ifdef DEBUG
-+ struct work_container_queue entries;
-+#endif
-+};
-+
-+static void do_work(void *data, int pending) // what to do with pending ???
-+{
-+ work_container_t *container = (work_container_t *)data;
-+ dwc_workq_t *wq = container->wq;
-+ dwc_irqflags_t flags;
-+
-+ if (container->hz) {
-+ pause("dw3wrk", container->hz);
-+ }
-+
-+ container->cb(container->data);
-+ DWC_DEBUG("Work done: %s, container=%p", container->name, container);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
-+#endif
-+ if (container->name)
-+ DWC_FREE(container->name);
-+ DWC_FREE(container);
-+ wq->pending--;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+ dwc_workq_t *workq = (dwc_workq_t *)data;
-+
-+ return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for workqueue");
-+ return NULL;
-+ }
-+
-+ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
-+ if (!wq->taskq) {
-+ DWC_ERROR("Cannot allocate memory for taskqueue");
-+ goto no_taskq;
-+ }
-+
-+ wq->pending = 0;
-+
-+ wq->lock = DWC_SPINLOCK_ALLOC();
-+ if (!wq->lock) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ goto no_lock;
-+ }
-+
-+ wq->waitq = DWC_WAITQ_ALLOC();
-+ if (!wq->waitq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ goto no_waitq;
-+ }
-+
-+ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INIT(&wq->entries);
-+#endif
-+ return wq;
-+
-+ no_waitq:
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+ taskqueue_free(wq->taskq);
-+ no_taskq:
-+ DWC_FREE(wq);
-+
-+ return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+ if (wq->pending != 0) {
-+ struct work_container *container;
-+
-+ DWC_ERROR("Destroying work queue with pending work");
-+
-+ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
-+ DWC_ERROR("Work %s still pending", container->name);
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+#endif
-+ DWC_WAITQ_FREE(wq->waitq);
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ taskqueue_free(wq->taskq);
-+ DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+ char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ container->hz = 0;
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+
-+ TASK_INIT(&container->task, 0, do_work, container);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ taskqueue_enqueue_fast(wq->taskq, &container->task);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ struct timeval tv;
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ container->hz = tvtohz(&tv);
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+
-+ TASK_INIT(&container->task, 0, do_work, container);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ taskqueue_enqueue_fast(wq->taskq, &container->task);
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+ return wq->pending;
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_common_linux.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_common_linux.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,1432 @@
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kthread.h>
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the Linux kernel implementation of the DWC platform library. */
-+#include <linux/moduleparam.h>
-+#include <linux/ctype.h>
-+#include <linux/crypto.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/cdev.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/jiffies.h>
-+#include <linux/list.h>
-+#include <linux/pci.h>
-+#include <linux/random.h>
-+#include <linux/scatterlist.h>
-+#include <linux/slab.h>
-+#include <linux/stat.h>
-+#include <linux/string.h>
-+#include <linux/timer.h>
-+#include <linux/usb.h>
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+# include <linux/usb/gadget.h>
-+#else
-+# include <linux/usb_gadget.h>
-+#endif
-+
-+#include <asm/io.h>
-+#include <asm/page.h>
-+#include <asm/uaccess.h>
-+#include <asm/unaligned.h>
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+ return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+ return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+ return memmove(dest, src, size);
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+ return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+ return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+ return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+ return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+ return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+ int len = DWC_STRLEN(str) + 1;
-+ char *new = DWC_ALLOC_ATOMIC(len);
-+
-+ if (!new) {
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(new, str, len);
-+ return new;
-+}
-+
-+int DWC_ATOI(const char *str, int32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = simple_strtol(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+int DWC_ATOUI(const char *str, uint32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = simple_strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+#endif /* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+ return in_irq();
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+ return in_softirq();
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+ vprintk(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+ return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsprintf(buffer, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsnprintf(buffer, size, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_WARNING);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_ERR);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_ERR);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+ BUG_ON(1);
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_DEBUG);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+ uint32_t align,
-+ uint32_t alloc)
-+{
-+ struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+ size, align, alloc);
-+ return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+ dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+ memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+ dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+#ifdef xxCOSIM /* Only works for 32-bit cosim */
-+ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL);
-+#else
-+ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32);
-+#endif
-+ if (!buf) {
-+ return NULL;
-+ }
-+
-+ memset(buf, 0, (size_t)size);
-+ return buf;
-+}
-+
-+void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
-+ if (!buf) {
-+ return NULL;
-+ }
-+ memset(buf, 0, (size_t)size);
-+ return buf;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+ return kzalloc(size, GFP_KERNEL);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+ return kzalloc(size, GFP_ATOMIC);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+ kfree(addr);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+ get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+ struct crypto_blkcipher *tfm;
-+ struct blkcipher_desc desc;
-+ struct scatterlist sgd;
-+ struct scatterlist sgs;
-+
-+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+ if (tfm == NULL) {
-+ printk("failed to load transform for aes CBC\n");
-+ return -1;
-+ }
-+
-+ crypto_blkcipher_setkey(tfm, key, keylen);
-+ crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+ sg_init_one(&sgd, out, messagelen);
-+ sg_init_one(&sgs, message, messagelen);
-+
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+ crypto_free_blkcipher(tfm);
-+ DWC_ERROR("AES CBC encryption failed");
-+ return -1;
-+ }
-+
-+ crypto_free_blkcipher(tfm);
-+ return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, len);
-+ crypto_hash_digest(&desc, &sg, len, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, messagelen);
-+ crypto_hash_setkey(tfm, key, keylen);
-+ crypto_hash_digest(&desc, &sg, messagelen, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(uint32_t volatile *reg)
-+{
-+ return readl(reg);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(uint64_t volatile *reg)
-+{
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
-+{
-+ writel(value, reg);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
-+{
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
-+{
-+ unsigned long flags;
-+
-+ local_irq_save(flags);
-+ local_fiq_disable();
-+ writel((readl(reg) & ~clear_mask) | set_mask, reg);
-+ local_fiq_enable();
-+ local_irq_restore(flags);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
-+{
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+ spinlock_t *sl = (spinlock_t *)1;
-+
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ sl = DWC_ALLOC(sizeof(*sl));
-+ if (!sl) {
-+ DWC_ERROR("Cannot allocate memory for spinlock\n");
-+ return NULL;
-+ }
-+
-+ spin_lock_init(sl);
-+#endif
-+ return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ DWC_FREE(lock);
-+#endif
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_lock((spinlock_t *)lock);
-+#endif
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_unlock((spinlock_t *)lock);
-+#endif
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+ dwc_irqflags_t f;
-+
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_lock_irqsave((spinlock_t *)lock, f);
-+#else
-+ local_irq_save(f);
-+#endif
-+ *flags = f;
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_unlock_irqrestore((spinlock_t *)lock, flags);
-+#else
-+ local_irq_restore(flags);
-+#endif
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+ struct mutex *m;
-+ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
-+
-+ if (!mutex) {
-+ DWC_ERROR("Cannot allocate memory for mutex\n");
-+ return NULL;
-+ }
-+
-+ m = (struct mutex *)mutex;
-+ mutex_init(m);
-+ return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+ mutex_destroy((struct mutex *)mutex);
-+ DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+ struct mutex *m = (struct mutex *)mutex;
-+ mutex_lock(m);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mutex *m = (struct mutex *)mutex;
-+ return mutex_trylock(m);
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mutex *m = (struct mutex *)mutex;
-+ mutex_unlock(m);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+ udelay(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+ mdelay(msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+ msleep(msecs);
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+ return jiffies_to_msecs(jiffies);
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+ struct timer_list *t;
-+ char *name;
-+ dwc_timer_callback_t cb;
-+ void *data;
-+ uint8_t scheduled;
-+ dwc_spinlock_t *lock;
-+};
-+
-+static void timer_callback(unsigned long data)
-+{
-+ dwc_timer_t *timer = (dwc_timer_t *)data;
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+ timer->scheduled = 0;
-+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+ DWC_DEBUGC("Timer %s callback", timer->name);
-+ timer->cb(timer->data);
-+}
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (!t) {
-+ DWC_ERROR("Cannot allocate memory for timer");
-+ return NULL;
-+ }
-+
-+ t->t = DWC_ALLOC(sizeof(*t->t));
-+ if (!t->t) {
-+ DWC_ERROR("Cannot allocate memory for timer->t");
-+ goto no_timer;
-+ }
-+
-+ t->name = DWC_STRDUP(name);
-+ if (!t->name) {
-+ DWC_ERROR("Cannot allocate memory for timer->name");
-+ goto no_name;
-+ }
-+
-+ t->lock = DWC_SPINLOCK_ALLOC();
-+ if (!t->lock) {
-+ DWC_ERROR("Cannot allocate memory for lock");
-+ goto no_lock;
-+ }
-+
-+ t->scheduled = 0;
-+ t->t->base = &boot_tvec_bases;
-+ t->t->expires = jiffies;
-+ setup_timer(t->t, timer_callback, (unsigned long)t);
-+
-+ t->cb = cb;
-+ t->data = data;
-+
-+ return t;
-+
-+ no_lock:
-+ DWC_FREE(t->name);
-+ no_name:
-+ DWC_FREE(t->t);
-+ no_timer:
-+ DWC_FREE(t);
-+ return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+
-+ if (timer->scheduled) {
-+ del_timer(timer->t);
-+ timer->scheduled = 0;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+ DWC_SPINLOCK_FREE(timer->lock);
-+ DWC_FREE(timer->t);
-+ DWC_FREE(timer->name);
-+ DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+
-+ if (!timer->scheduled) {
-+ timer->scheduled = 1;
-+ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
-+ timer->t->expires = jiffies + msecs_to_jiffies(time);
-+ add_timer(timer->t);
-+ } else {
-+ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
-+ mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+ del_timer(timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+ wait_queue_head_t queue;
-+ int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue\n");
-+ return NULL;
-+ }
-+
-+ init_waitqueue_head(&wq->queue);
-+ wq->abort = 0;
-+ return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+ DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+ int result = wait_event_interruptible(wq->queue,
-+ cond(data) || wq->abort);
-+ if (result == -ERESTARTSYS) {
-+ wq->abort = 0;
-+ return -DWC_E_RESTART;
-+ }
-+
-+ if (wq->abort == 1) {
-+ wq->abort = 0;
-+ return -DWC_E_ABORT;
-+ }
-+
-+ wq->abort = 0;
-+
-+ if (result == 0) {
-+ return 0;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs)
-+{
-+ int32_t tmsecs;
-+ int result = wait_event_interruptible_timeout(wq->queue,
-+ cond(data) || wq->abort,
-+ msecs_to_jiffies(msecs));
-+ if (result == -ERESTARTSYS) {
-+ wq->abort = 0;
-+ return -DWC_E_RESTART;
-+ }
-+
-+ if (wq->abort == 1) {
-+ wq->abort = 0;
-+ return -DWC_E_ABORT;
-+ }
-+
-+ wq->abort = 0;
-+
-+ if (result > 0) {
-+ tmsecs = jiffies_to_msecs(result);
-+ if (!tmsecs) {
-+ return 1;
-+ }
-+
-+ return tmsecs;
-+ }
-+
-+ if (result == 0) {
-+ return -DWC_E_TIMEOUT;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+ wq->abort = 0;
-+ wake_up_interruptible(&wq->queue);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+ wq->abort = 1;
-+ wake_up_interruptible(&wq->queue);
-+}
-+
-+
-+/* Threading */
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+ struct task_struct *thread = kthread_run(func, data, name);
-+
-+ if (thread == ERR_PTR(-ENOMEM)) {
-+ return NULL;
-+ }
-+
-+ return (dwc_thread_t *)thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+ return kthread_stop((struct task_struct *)thread);
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
-+{
-+ return kthread_should_stop();
-+}
-+
-+
-+/* tasklets
-+ - run in interrupt context (cannot sleep)
-+ - each tasklet runs on a single CPU
-+ - different tasklets can be running simultaneously on different CPUs
-+ */
-+struct dwc_tasklet {
-+ struct tasklet_struct t;
-+ dwc_tasklet_callback_t cb;
-+ void *data;
-+};
-+
-+static void tasklet_callback(unsigned long data)
-+{
-+ dwc_tasklet_t *t = (dwc_tasklet_t *)data;
-+ t->cb(t->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (t) {
-+ t->cb = cb;
-+ t->data = data;
-+ tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
-+ } else {
-+ DWC_ERROR("Cannot allocate memory for tasklet\n");
-+ }
-+
-+ return t;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+ DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ tasklet_schedule(&task->t);
-+}
-+
-+void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ tasklet_hi_schedule(&task->t);
-+}
-+
-+
-+/* workqueues
-+ - run in process context (can sleep)
-+ */
-+typedef struct work_container {
-+ dwc_work_callback_t cb;
-+ void *data;
-+ dwc_workq_t *wq;
-+ char *name;
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_ENTRY(work_container) entry;
-+#endif
-+ struct delayed_work work;
-+} work_container_t;
-+
-+#ifdef DEBUG
-+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
-+#endif
-+
-+struct dwc_workq {
-+ struct workqueue_struct *wq;
-+ dwc_spinlock_t *lock;
-+ dwc_waitq_t *waitq;
-+ int pending;
-+
-+#ifdef DEBUG
-+ struct work_container_queue entries;
-+#endif
-+};
-+
-+static void do_work(struct work_struct *work)
-+{
-+ dwc_irqflags_t flags;
-+ struct delayed_work *dw = container_of(work, struct delayed_work, work);
-+ work_container_t *container = container_of(dw, struct work_container, work);
-+ dwc_workq_t *wq = container->wq;
-+
-+ container->cb(container->data);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
-+#endif
-+ DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
-+ if (container->name) {
-+ DWC_FREE(container->name);
-+ }
-+ DWC_FREE(container);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending--;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+ dwc_workq_t *workq = (dwc_workq_t *)data;
-+ return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ return NULL;
-+ }
-+
-+ wq->wq = create_singlethread_workqueue(name);
-+ if (!wq->wq) {
-+ goto no_wq;
-+ }
-+
-+ wq->pending = 0;
-+
-+ wq->lock = DWC_SPINLOCK_ALLOC();
-+ if (!wq->lock) {
-+ goto no_lock;
-+ }
-+
-+ wq->waitq = DWC_WAITQ_ALLOC();
-+ if (!wq->waitq) {
-+ goto no_waitq;
-+ }
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INIT(&wq->entries);
-+#endif
-+ return wq;
-+
-+ no_waitq:
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+ destroy_workqueue(wq->wq);
-+ no_wq:
-+ DWC_FREE(wq);
-+
-+ return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+ if (wq->pending != 0) {
-+ struct work_container *wc;
-+ DWC_ERROR("Destroying work queue with pending work");
-+ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
-+ DWC_ERROR("Work %s still pending", wc->name);
-+ }
-+ }
-+#endif
-+ destroy_workqueue(wq->wq);
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ DWC_WAITQ_FREE(wq->waitq);
-+ DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+ char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container\n");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name\n");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
-+ INIT_WORK(&container->work.work, do_work);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ queue_work(wq->wq, &container->work.work);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container\n");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name\n");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
-+ INIT_DELAYED_WORK(&container->work, do_work);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+ return wq->pending;
-+}
-+
-+
-+#ifdef DWC_LIBMODULE
-+
-+#ifdef DWC_CCLIB
-+/* CC */
-+EXPORT_SYMBOL(dwc_cc_if_alloc);
-+EXPORT_SYMBOL(dwc_cc_if_free);
-+EXPORT_SYMBOL(dwc_cc_clear);
-+EXPORT_SYMBOL(dwc_cc_add);
-+EXPORT_SYMBOL(dwc_cc_remove);
-+EXPORT_SYMBOL(dwc_cc_change);
-+EXPORT_SYMBOL(dwc_cc_data_for_save);
-+EXPORT_SYMBOL(dwc_cc_restore_from_data);
-+EXPORT_SYMBOL(dwc_cc_match_chid);
-+EXPORT_SYMBOL(dwc_cc_match_cdid);
-+EXPORT_SYMBOL(dwc_cc_ck);
-+EXPORT_SYMBOL(dwc_cc_chid);
-+EXPORT_SYMBOL(dwc_cc_cdid);
-+EXPORT_SYMBOL(dwc_cc_name);
-+#endif /* DWC_CCLIB */
-+
-+#ifdef DWC_CRYPTOLIB
-+# ifndef CONFIG_MACH_IPMATE
-+/* Modpow */
-+EXPORT_SYMBOL(dwc_modpow);
-+
-+/* DH */
-+EXPORT_SYMBOL(dwc_dh_modpow);
-+EXPORT_SYMBOL(dwc_dh_derive_keys);
-+EXPORT_SYMBOL(dwc_dh_pk);
-+# endif /* CONFIG_MACH_IPMATE */
-+
-+/* Crypto */
-+EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
-+EXPORT_SYMBOL(dwc_wusb_cmf);
-+EXPORT_SYMBOL(dwc_wusb_prf);
-+EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
-+EXPORT_SYMBOL(dwc_wusb_gen_nonce);
-+EXPORT_SYMBOL(dwc_wusb_gen_key);
-+EXPORT_SYMBOL(dwc_wusb_gen_mic);
-+#endif /* DWC_CRYPTOLIB */
-+
-+/* Notification */
-+#ifdef DWC_NOTIFYLIB
-+EXPORT_SYMBOL(dwc_alloc_notification_manager);
-+EXPORT_SYMBOL(dwc_free_notification_manager);
-+EXPORT_SYMBOL(dwc_register_notifier);
-+EXPORT_SYMBOL(dwc_unregister_notifier);
-+EXPORT_SYMBOL(dwc_add_observer);
-+EXPORT_SYMBOL(dwc_remove_observer);
-+EXPORT_SYMBOL(dwc_notify);
-+#endif
-+
-+/* Memory Debugging Routines */
-+#ifdef DWC_DEBUG_MEMORY
-+EXPORT_SYMBOL(dwc_alloc_debug);
-+EXPORT_SYMBOL(dwc_alloc_atomic_debug);
-+EXPORT_SYMBOL(dwc_free_debug);
-+EXPORT_SYMBOL(dwc_dma_alloc_debug);
-+EXPORT_SYMBOL(dwc_dma_free_debug);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_MEMSET);
-+EXPORT_SYMBOL(DWC_MEMCPY);
-+EXPORT_SYMBOL(DWC_MEMMOVE);
-+EXPORT_SYMBOL(DWC_MEMCMP);
-+EXPORT_SYMBOL(DWC_STRNCMP);
-+EXPORT_SYMBOL(DWC_STRCMP);
-+EXPORT_SYMBOL(DWC_STRLEN);
-+EXPORT_SYMBOL(DWC_STRCPY);
-+EXPORT_SYMBOL(DWC_STRDUP);
-+EXPORT_SYMBOL(DWC_ATOI);
-+EXPORT_SYMBOL(DWC_ATOUI);
-+
-+#ifdef DWC_UTFLIB
-+EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
-+#endif /* DWC_UTFLIB */
-+
-+EXPORT_SYMBOL(DWC_IN_IRQ);
-+EXPORT_SYMBOL(DWC_IN_BH);
-+EXPORT_SYMBOL(DWC_VPRINTF);
-+EXPORT_SYMBOL(DWC_VSNPRINTF);
-+EXPORT_SYMBOL(DWC_PRINTF);
-+EXPORT_SYMBOL(DWC_SPRINTF);
-+EXPORT_SYMBOL(DWC_SNPRINTF);
-+EXPORT_SYMBOL(__DWC_WARN);
-+EXPORT_SYMBOL(__DWC_ERROR);
-+EXPORT_SYMBOL(DWC_EXCEPTION);
-+
-+#ifdef DEBUG
-+EXPORT_SYMBOL(__DWC_DEBUG);
-+#endif
-+
-+EXPORT_SYMBOL(__DWC_DMA_ALLOC);
-+EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
-+EXPORT_SYMBOL(__DWC_DMA_FREE);
-+EXPORT_SYMBOL(__DWC_ALLOC);
-+EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
-+EXPORT_SYMBOL(__DWC_FREE);
-+
-+#ifdef DWC_CRYPTOLIB
-+EXPORT_SYMBOL(DWC_RANDOM_BYTES);
-+EXPORT_SYMBOL(DWC_AES_CBC);
-+EXPORT_SYMBOL(DWC_SHA256);
-+EXPORT_SYMBOL(DWC_HMAC_SHA256);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_CPU_TO_LE32);
-+EXPORT_SYMBOL(DWC_CPU_TO_BE32);
-+EXPORT_SYMBOL(DWC_LE32_TO_CPU);
-+EXPORT_SYMBOL(DWC_BE32_TO_CPU);
-+EXPORT_SYMBOL(DWC_CPU_TO_LE16);
-+EXPORT_SYMBOL(DWC_CPU_TO_BE16);
-+EXPORT_SYMBOL(DWC_LE16_TO_CPU);
-+EXPORT_SYMBOL(DWC_BE16_TO_CPU);
-+EXPORT_SYMBOL(DWC_READ_REG32);
-+EXPORT_SYMBOL(DWC_WRITE_REG32);
-+EXPORT_SYMBOL(DWC_MODIFY_REG32);
-+
-+#if 0
-+EXPORT_SYMBOL(DWC_READ_REG64);
-+EXPORT_SYMBOL(DWC_WRITE_REG64);
-+EXPORT_SYMBOL(DWC_MODIFY_REG64);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
-+EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
-+EXPORT_SYMBOL(DWC_SPINLOCK);
-+EXPORT_SYMBOL(DWC_SPINUNLOCK);
-+EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
-+EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
-+EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
-+
-+#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
-+EXPORT_SYMBOL(DWC_MUTEX_FREE);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_MUTEX_LOCK);
-+EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
-+EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
-+EXPORT_SYMBOL(DWC_UDELAY);
-+EXPORT_SYMBOL(DWC_MDELAY);
-+EXPORT_SYMBOL(DWC_MSLEEP);
-+EXPORT_SYMBOL(DWC_TIME);
-+EXPORT_SYMBOL(DWC_TIMER_ALLOC);
-+EXPORT_SYMBOL(DWC_TIMER_FREE);
-+EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
-+EXPORT_SYMBOL(DWC_TIMER_CANCEL);
-+EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
-+EXPORT_SYMBOL(DWC_WAITQ_FREE);
-+EXPORT_SYMBOL(DWC_WAITQ_WAIT);
-+EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
-+EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
-+EXPORT_SYMBOL(DWC_WAITQ_ABORT);
-+EXPORT_SYMBOL(DWC_THREAD_RUN);
-+EXPORT_SYMBOL(DWC_THREAD_STOP);
-+EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
-+EXPORT_SYMBOL(DWC_TASK_ALLOC);
-+EXPORT_SYMBOL(DWC_TASK_FREE);
-+EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
-+EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
-+EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
-+EXPORT_SYMBOL(DWC_WORKQ_FREE);
-+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
-+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
-+EXPORT_SYMBOL(DWC_WORKQ_PENDING);
-+
-+static int dwc_common_port_init_module(void)
-+{
-+ int result = 0;
-+
-+ printk(KERN_DEBUG "Module dwc_common_port init\n" );
-+
-+#ifdef DWC_DEBUG_MEMORY
-+ result = dwc_memory_debug_start(NULL);
-+ if (result) {
-+ printk(KERN_ERR
-+ "dwc_memory_debug_start() failed with error %d\n",
-+ result);
-+ return result;
-+ }
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+ result = dwc_alloc_notification_manager(NULL, NULL);
-+ if (result) {
-+ printk(KERN_ERR
-+ "dwc_alloc_notification_manager() failed with error %d\n",
-+ result);
-+ return result;
-+ }
-+#endif
-+ return result;
-+}
-+
-+static void dwc_common_port_exit_module(void)
-+{
-+ printk(KERN_DEBUG "Module dwc_common_port exit\n" );
-+
-+#ifdef DWC_NOTIFYLIB
-+ dwc_free_notification_manager();
-+#endif
-+
-+#ifdef DWC_DEBUG_MEMORY
-+ dwc_memory_debug_stop();
-+#endif
-+}
-+
-+module_init(dwc_common_port_init_module);
-+module_exit(dwc_common_port_exit_module);
-+
-+MODULE_DESCRIPTION("DWC Common Library - Portable version");
-+MODULE_AUTHOR("Synopsys Inc.");
-+MODULE_LICENSE ("GPL");
-+
-+#endif /* DWC_LIBMODULE */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,1275 @@
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+ return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+ return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+ bcopy(src, dest, size);
-+ return dest;
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+ return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+ return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+ return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+ return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+ return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+ int len = DWC_STRLEN(str) + 1;
-+ char *new = DWC_ALLOC_ATOMIC(len);
-+
-+ if (!new) {
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(new, str, len);
-+ return new;
-+}
-+
-+int DWC_ATOI(char *str, int32_t *value)
-+{
-+ char *end = NULL;
-+
-+ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
-+ * should be equivalent on 2's complement machines
-+ */
-+ *value = strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+int DWC_ATOUI(char *str, uint32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+#endif /* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+// return in_irq();
-+ return 0;
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+// return in_softirq();
-+ return 0;
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+ vprintf(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+ return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsprintf(buffer, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsnprintf(buffer, size, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+// BUG_ON(1); ???
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+ uint32_t align,
-+ uint32_t alloc)
-+{
-+ struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+ size, align, alloc);
-+ return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+ dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+ memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+ dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+ int error;
-+
-+ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
-+ sizeof(dma->segs) / sizeof(dma->segs[0]),
-+ &dma->nsegs, BUS_DMA_NOWAIT);
-+ if (error) {
-+ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
-+ (uintmax_t)size, error);
-+ goto fail_0;
-+ }
-+
-+ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
-+ (caddr_t *)&dma->dma_vaddr,
-+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
-+ if (error) {
-+ printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
-+ goto fail_1;
-+ }
-+
-+ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
-+ BUS_DMA_NOWAIT, &dma->dma_map);
-+ if (error) {
-+ printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
-+ goto fail_2;
-+ }
-+
-+ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
-+ size, NULL, BUS_DMA_NOWAIT);
-+ if (error) {
-+ printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
-+ goto fail_3;
-+ }
-+
-+ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
-+ *dma_addr = dma->dma_paddr;
-+ return dma->dma_vaddr;
-+
-+fail_3:
-+ bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
-+fail_2:
-+ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
-+fail_1:
-+ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
-+fail_0:
-+ dma->dma_map = NULL;
-+ dma->dma_vaddr = NULL;
-+ dma->nsegs = 0;
-+
-+ return NULL;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+
-+ if (dma->dma_map != NULL) {
-+ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
-+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-+ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+ bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
-+ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
-+ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
-+ dma->dma_paddr = 0;
-+ dma->dma_map = NULL;
-+ dma->dma_vaddr = NULL;
-+ dma->nsegs = 0;
-+ }
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+ free(addr, M_DEVBUF);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+ get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+ struct crypto_blkcipher *tfm;
-+ struct blkcipher_desc desc;
-+ struct scatterlist sgd;
-+ struct scatterlist sgs;
-+
-+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+ if (tfm == NULL) {
-+ printk("failed to load transform for aes CBC\n");
-+ return -1;
-+ }
-+
-+ crypto_blkcipher_setkey(tfm, key, keylen);
-+ crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+ sg_init_one(&sgd, out, messagelen);
-+ sg_init_one(&sgs, message, messagelen);
-+
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+ crypto_free_blkcipher(tfm);
-+ DWC_ERROR("AES CBC encryption failed");
-+ return -1;
-+ }
-+
-+ crypto_free_blkcipher(tfm);
-+ return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, len);
-+ crypto_hash_digest(&desc, &sg, len, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, messagelen);
-+ crypto_hash_setkey(tfm, key, keylen);
-+ crypto_hash_digest(&desc, &sg, messagelen, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_4(io->iot, io->ioh, ior);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_8(io->iot, io->ioh, ior);
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior, value);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior, value);
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
-+ uint32_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior,
-+ (bus_space_read_4(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
-+ uint64_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior,
-+ (bus_space_read_8(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+ struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
-+
-+ if (!sl) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ return NULL;
-+ }
-+
-+ simple_lock_init(sl);
-+ return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+ struct simplelock *sl = (struct simplelock *)lock;
-+
-+ DWC_FREE(sl);
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+ simple_lock((struct simplelock *)lock);
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+ simple_unlock((struct simplelock *)lock);
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+ simple_lock((struct simplelock *)lock);
-+ *flags = splbio();
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+ splx(flags);
-+ simple_unlock((struct simplelock *)lock);
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
-+
-+ if (!mutex) {
-+ DWC_ERROR("Cannot allocate memory for mutex");
-+ return NULL;
-+ }
-+
-+ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
-+ return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+ DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+ int status;
-+
-+ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
-+ return status == 0;
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+ lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+ DELAY(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+ do {
-+ DELAY(1000);
-+ } while (--msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+ tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+ struct timeval tv;
-+
-+ microuptime(&tv); // or getmicrouptime? (less precise, but faster)
-+ return tv.tv_sec * 1000 + tv.tv_usec / 1000;
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+ struct callout t;
-+ char *name;
-+ dwc_spinlock_t *lock;
-+ dwc_timer_callback_t cb;
-+ void *data;
-+};
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (!t) {
-+ DWC_ERROR("Cannot allocate memory for timer");
-+ return NULL;
-+ }
-+
-+ callout_init(&t->t);
-+
-+ t->name = DWC_STRDUP(name);
-+ if (!t->name) {
-+ DWC_ERROR("Cannot allocate memory for timer->name");
-+ goto no_name;
-+ }
-+
-+ t->lock = DWC_SPINLOCK_ALLOC();
-+ if (!t->lock) {
-+ DWC_ERROR("Cannot allocate memory for timer->lock");
-+ goto no_lock;
-+ }
-+
-+ t->cb = cb;
-+ t->data = data;
-+
-+ return t;
-+
-+ no_lock:
-+ DWC_FREE(t->name);
-+ no_name:
-+ DWC_FREE(t);
-+
-+ return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+ DWC_SPINLOCK_FREE(timer->lock);
-+ DWC_FREE(timer->name);
-+ DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+ struct simplelock lock;
-+ int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ return NULL;
-+ }
-+
-+ simple_lock_init(&wq->lock);
-+ wq->abort = 0;
-+
-+ return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+ DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+ int ipl;
-+ int result = 0;
-+
-+ simple_lock(&wq->lock);
-+ ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+ splx(ipl);
-+ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
-+ ipl = splbio();
-+ }
-+
-+ if (result == 0) { // awoken
-+ if (wq->abort) {
-+ wq->abort = 0;
-+ result = -DWC_E_ABORT;
-+ } else {
-+ result = 0;
-+ }
-+
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+ } else {
-+ wq->abort = 0;
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+
-+ if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+ } else { // signaled - must be EINTR
-+ result = -DWC_E_ABORT;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs)
-+{
-+ struct timeval tv, tv1, tv2;
-+ int ipl;
-+ int result = 0;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+
-+ simple_lock(&wq->lock);
-+ ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+ splx(ipl);
-+ getmicrouptime(&tv1);
-+ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
-+ getmicrouptime(&tv2);
-+ ipl = splbio();
-+ }
-+
-+ if (result == 0) { // awoken
-+ if (wq->abort) {
-+ wq->abort = 0;
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+ result = -DWC_E_ABORT;
-+ } else {
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+
-+ tv2.tv_usec -= tv1.tv_usec;
-+ if (tv2.tv_usec < 0) {
-+ tv2.tv_usec += 1000000;
-+ tv2.tv_sec--;
-+ }
-+
-+ tv2.tv_sec -= tv1.tv_sec;
-+ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
-+ result = msecs - result;
-+ if (result <= 0)
-+ result = 1;
-+ }
-+ } else {
-+ wq->abort = 0;
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+
-+ if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+
-+ } else if (result == EINTR) { // signaled - interrupt
-+ result = -DWC_E_ABORT;
-+
-+ } else { // timed out
-+ result = -DWC_E_TIMEOUT;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+ wakeup(wq);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+ int ipl;
-+
-+ simple_lock(&wq->lock);
-+ ipl = splbio();
-+ wq->abort = 1;
-+ wakeup(wq);
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+}
-+
-+
-+/* Threading */
-+
-+struct dwc_thread {
-+ struct proc *proc;
-+ int abort;
-+};
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+ int retval;
-+ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
-+
-+ if (!thread) {
-+ return NULL;
-+ }
-+
-+ thread->abort = 0;
-+ retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
-+ "%s", name);
-+ if (retval) {
-+ DWC_FREE(thread);
-+ return NULL;
-+ }
-+
-+ return thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+ int retval;
-+
-+ thread->abort = 1;
-+ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
-+
-+ if (retval == 0) {
-+ /* DWC_THREAD_EXIT() will free the thread struct */
-+ return 0;
-+ }
-+
-+ /* NOTE: We leak the thread struct if thread doesn't die */
-+
-+ if (retval == EWOULDBLOCK) {
-+ return -DWC_E_TIMEOUT;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
-+{
-+ return thread->abort;
-+}
-+
-+void DWC_THREAD_EXIT(dwc_thread_t *thread)
-+{
-+ wakeup(&thread->abort);
-+ DWC_FREE(thread);
-+ kthread_exit(0);
-+}
-+
-+/* tasklets
-+ - Runs in interrupt context (cannot sleep)
-+ - Each tasklet runs on a single CPU
-+ - Different tasklets can be running simultaneously on different CPUs
-+ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
-+ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
-+ */
-+struct dwc_tasklet {
-+ dwc_tasklet_callback_t cb;
-+ void *data;
-+};
-+
-+static void tasklet_callback(void *data)
-+{
-+ dwc_tasklet_t *task = (dwc_tasklet_t *)data;
-+
-+ task->cb(task->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
-+
-+ if (task) {
-+ task->cb = cb;
-+ task->data = data;
-+ } else {
-+ DWC_ERROR("Cannot allocate memory for tasklet");
-+ }
-+
-+ return task;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+ DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ tasklet_callback(task);
-+}
-+
-+
-+/* workqueues
-+ - Runs in process context (can sleep)
-+ */
-+typedef struct work_container {
-+ dwc_work_callback_t cb;
-+ void *data;
-+ dwc_workq_t *wq;
-+ char *name;
-+ int hz;
-+ struct work task;
-+} work_container_t;
-+
-+struct dwc_workq {
-+ struct workqueue *taskq;
-+ dwc_spinlock_t *lock;
-+ dwc_waitq_t *waitq;
-+ int pending;
-+ struct work_container *container;
-+};
-+
-+static void do_work(struct work *task, void *data)
-+{
-+ dwc_workq_t *wq = (dwc_workq_t *)data;
-+ work_container_t *container = wq->container;
-+ dwc_irqflags_t flags;
-+
-+ if (container->hz) {
-+ tsleep(container, 0, "dw3wrk", container->hz);
-+ }
-+
-+ container->cb(container->data);
-+ DWC_DEBUG("Work done: %s, container=%p", container->name, container);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ if (container->name)
-+ DWC_FREE(container->name);
-+ DWC_FREE(container);
-+ wq->pending--;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+ dwc_workq_t *workq = (dwc_workq_t *)data;
-+
-+ return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+ int result;
-+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for workqueue");
-+ return NULL;
-+ }
-+
-+ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
-+ IPL_BIO, 0);
-+ if (result) {
-+ DWC_ERROR("Cannot create workqueue");
-+ goto no_taskq;
-+ }
-+
-+ wq->pending = 0;
-+
-+ wq->lock = DWC_SPINLOCK_ALLOC();
-+ if (!wq->lock) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ goto no_lock;
-+ }
-+
-+ wq->waitq = DWC_WAITQ_ALLOC();
-+ if (!wq->waitq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ goto no_waitq;
-+ }
-+
-+ return wq;
-+
-+ no_waitq:
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+ workqueue_destroy(wq->taskq);
-+ no_taskq:
-+ DWC_FREE(wq);
-+
-+ return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+ if (wq->pending != 0) {
-+ struct work_container *container = wq->container;
-+
-+ DWC_ERROR("Destroying work queue with pending work");
-+
-+ if (container && container->name) {
-+ DWC_ERROR("Work %s still pending", container->name);
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+#endif
-+ DWC_WAITQ_FREE(wq->waitq);
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ workqueue_destroy(wq->taskq);
-+ DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+ char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ container->hz = 0;
-+ wq->container = container;
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+ workqueue_enqueue(wq->taskq, &container->task);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ struct timeval tv;
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ container->hz = tvtohz(&tv);
-+ wq->container = container;
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+ workqueue_enqueue(wq->taskq, &container->task);
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+ return wq->pending;
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_crypto.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_crypto.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,308 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
-+ * $Revision: #5 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+
-+/** @file
-+ * This file contains the WUSB cryptographic routines.
-+ */
-+
-+#ifdef DWC_CRYPTOLIB
-+
-+#include "dwc_crypto.h"
-+#include "usb.h"
-+
-+#ifdef DEBUG
-+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
-+{
-+ int i;
-+ DWC_PRINTF("%s: ", name);
-+ for (i=0; i<len; i++) {
-+ DWC_PRINTF("%02x ", bytes[i]);
-+ }
-+ DWC_PRINTF("\n");
-+}
-+#else
-+#define dump_bytes(x...)
-+#endif
-+
-+/* Display a block */
-+void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
-+{
-+#ifdef DWC_DEBUG_CRYPTO
-+ int i, blksize = 16;
-+
-+ DWC_DEBUG("%s", prefix);
-+
-+ if (suffix == NULL) {
-+ suffix = "\n";
-+ blksize = a;
-+ }
-+
-+ for (i = 0; i < blksize; i++)
-+ DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? " " : " ");
-+ DWC_PRINT(suffix);
-+#endif
-+}
-+
-+/**
-+ * Encrypts an array of bytes using the AES encryption engine.
-+ * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
-+ * in-place.
-+ *
-+ * @return 0 on success, negative error code on error.
-+ */
-+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
-+{
-+ u8 block_t[16];
-+ DWC_MEMSET(block_t, 0, 16);
-+
-+ return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
-+}
-+
-+/**
-+ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
-+ * This function takes a data string and returns the encrypted CBC
-+ * Counter-mode MIC.
-+ *
-+ * @param key The 128-bit symmetric key.
-+ * @param nonce The CCM nonce.
-+ * @param label The unique 14-byte ASCII text label.
-+ * @param bytes The byte array to be encrypted.
-+ * @param len Length of the byte array.
-+ * @param result Byte array to receive the 8-byte encrypted MIC.
-+ */
-+void dwc_wusb_cmf(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ u8 block_m[16];
-+ u8 block_x[16];
-+ u8 block_t[8];
-+ int idx, blkNum;
-+ u16 la = (u16)(len + 14);
-+
-+ /* Set the AES-128 key */
-+ //dwc_aes_setkey(tfm, key, 16);
-+
-+ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
-+ block_m[0] = 0x59;
-+ for (idx = 0; idx < 13; idx++)
-+ block_m[idx + 1] = nonce[idx];
-+ block_m[14] = 0;
-+ block_m[15] = 0;
-+
-+ /* Produce the CBC IV */
-+ dwc_wusb_aes_encrypt(block_m, key, block_x);
-+ show_block(block_m, "CBC IV in: ", "\n", 0);
-+ show_block(block_x, "CBC IV out:", "\n", 0);
-+
-+ /* Fill block B1 from l(a) = Blen + 14, and A */
-+ block_x[0] ^= (u8)(la >> 8);
-+ block_x[1] ^= (u8)la;
-+ for (idx = 0; idx < 14; idx++)
-+ block_x[idx + 2] ^= label[idx];
-+ show_block(block_x, "After xor: ", "b1\n", 16);
-+
-+ dwc_wusb_aes_encrypt(block_x, key, block_x);
-+ show_block(block_x, "After AES: ", "b1\n", 16);
-+
-+ idx = 0;
-+ blkNum = 0;
-+
-+ /* Fill remaining blocks with B */
-+ while (len-- > 0) {
-+ block_x[idx] ^= *bytes++;
-+ if (++idx >= 16) {
-+ idx = 0;
-+ show_block(block_x, "After xor: ", "\n", blkNum);
-+ dwc_wusb_aes_encrypt(block_x, key, block_x);
-+ show_block(block_x, "After AES: ", "\n", blkNum);
-+ blkNum++;
-+ }
-+ }
-+
-+ /* Handle partial last block */
-+ if (idx > 0) {
-+ show_block(block_x, "After xor: ", "\n", blkNum);
-+ dwc_wusb_aes_encrypt(block_x, key, block_x);
-+ show_block(block_x, "After AES: ", "\n", blkNum);
-+ }
-+
-+ /* Save the MIC tag */
-+ DWC_MEMCPY(block_t, block_x, 8);
-+ show_block(block_t, "MIC tag : ", NULL, 8);
-+
-+ /* Fill block A0 from flags = 0x01, N, and counter = 0 */
-+ block_m[0] = 0x01;
-+ block_m[14] = 0;
-+ block_m[15] = 0;
-+
-+ /* Encrypt the counter */
-+ dwc_wusb_aes_encrypt(block_m, key, block_x);
-+ show_block(block_x, "CTR[MIC] : ", NULL, 8);
-+
-+ /* XOR with MIC tag */
-+ for (idx = 0; idx < 8; idx++) {
-+ block_t[idx] ^= block_x[idx];
-+ }
-+
-+ /* Return result to caller */
-+ DWC_MEMCPY(result, block_t, 8);
-+ show_block(result, "CCM-MIC : ", NULL, 8);
-+
-+}
-+
-+/**
-+ * The PRF function described in section 6.5 of the WUSB spec. This function
-+ * concatenates MIC values returned from dwc_cmf() to create a value of
-+ * the requested length.
-+ *
-+ * @param prf_len Length of the PRF function in bits (64, 128, or 256).
-+ * @param key, nonce, label, bytes, len Same as for dwc_cmf().
-+ * @param result Byte array to receive the result.
-+ */
-+void dwc_wusb_prf(int prf_len, u8 *key,
-+ u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
-+{
-+ int i;
-+
-+ nonce[0] = 0;
-+ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
-+ dwc_wusb_cmf(key, nonce, label, bytes, len, result);
-+ result += 8;
-+ }
-+}
-+
-+/**
-+ * Fills in CCM Nonce per the WUSB spec.
-+ *
-+ * @param[in] haddr Host address.
-+ * @param[in] daddr Device address.
-+ * @param[in] tkid Session Key(PTK) identifier.
-+ * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
-+ */
-+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
-+ uint8_t *nonce)
-+{
-+
-+ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
-+
-+ DWC_MEMSET(&nonce[0], 0, 16);
-+
-+ DWC_MEMCPY(&nonce[6], tkid, 3);
-+ nonce[9] = daddr & 0xFF;
-+ nonce[10] = (daddr >> 8) & 0xFF;
-+ nonce[11] = haddr & 0xFF;
-+ nonce[12] = (haddr >> 8) & 0xFF;
-+
-+ dump_bytes("CCM nonce", nonce, 16);
-+}
-+
-+/**
-+ * Generates a 16-byte cryptographic-grade random number for the Host/Device
-+ * Nonce.
-+ */
-+void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
-+{
-+ uint8_t inonce[16];
-+ uint32_t temp[4];
-+
-+ /* Fill in the Nonce */
-+ DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
-+ inonce[9] = addr & 0xFF;
-+ inonce[10] = (addr >> 8) & 0xFF;
-+ inonce[11] = inonce[9];
-+ inonce[12] = inonce[10];
-+
-+ /* Collect "randomness samples" */
-+ DWC_RANDOM_BYTES((uint8_t *)temp, 16);
-+
-+ dwc_wusb_prf_128((uint8_t *)temp, nonce,
-+ "Random Numbers", (uint8_t *)temp, sizeof(temp),
-+ nonce);
-+}
-+
-+/**
-+ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
-+ * WUSB spec.
-+ *
-+ * @param[in] ccm_nonce Pointer to CCM Nonce.
-+ * @param[in] mk Master Key to derive the session from
-+ * @param[in] hnonce Pointer to Host Nonce.
-+ * @param[in] dnonce Pointer to Device Nonce.
-+ * @param[out] kck Pointer to where the KCK output is to be written.
-+ * @param[out] ptk Pointer to where the PTK output is to be written.
-+ */
-+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
-+ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
-+{
-+ uint8_t idata[32];
-+ uint8_t odata[32];
-+
-+ dump_bytes("ck", mk, 16);
-+ dump_bytes("hnonce", hnonce, 16);
-+ dump_bytes("dnonce", dnonce, 16);
-+
-+ /* The data is the HNonce and DNonce concatenated */
-+ DWC_MEMCPY(&idata[0], hnonce, 16);
-+ DWC_MEMCPY(&idata[16], dnonce, 16);
-+
-+ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
-+
-+ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
-+ DWC_MEMCPY(kck, &odata[0], 16);
-+ DWC_MEMCPY(ptk, &odata[16], 16);
-+
-+ dump_bytes("kck", kck, 16);
-+ dump_bytes("ptk", ptk, 16);
-+}
-+
-+/**
-+ * Generates the Message Integrity Code over the Handshake data per the
-+ * WUSB spec.
-+ *
-+ * @param ccm_nonce Pointer to CCM Nonce.
-+ * @param kck Pointer to Key Confirmation Key.
-+ * @param data Pointer to Handshake data to be checked.
-+ * @param mic Pointer to where the MIC output is to be written.
-+ */
-+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
-+ uint8_t *data, uint8_t *mic)
-+{
-+
-+ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
-+ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
-+}
-+
-+#endif /* DWC_CRYPTOLIB */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_crypto.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_crypto.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,111 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
-+ * $Revision: #3 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+
-+#ifndef _DWC_CRYPTO_H_
-+#define _DWC_CRYPTO_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file contains declarations for the WUSB Cryptographic routines as
-+ * defined in the WUSB spec. They are only to be used internally by the DWC UWB
-+ * modules.
-+ */
-+
-+#include "dwc_os.h"
-+
-+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
-+
-+void dwc_wusb_cmf(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result);
-+void dwc_wusb_prf(int prf_len, u8 *key,
-+ u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
-+
-+/**
-+ * The PRF-64 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
-+}
-+
-+/**
-+ * The PRF-128 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
-+}
-+
-+/**
-+ * The PRF-256 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
-+}
-+
-+
-+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
-+ uint8_t *nonce);
-+void dwc_wusb_gen_nonce(uint16_t addr,
-+ uint8_t *nonce);
-+
-+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
-+ uint8_t *hnonce, uint8_t *dnonce,
-+ uint8_t *kck, uint8_t *ptk);
-+
-+
-+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
-+ *kck, uint8_t *data, uint8_t *mic);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_CRYPTO_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_dh.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_dh.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,291 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
-+ * $Revision: #3 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifdef DWC_CRYPTOLIB
-+
-+#ifndef CONFIG_MACH_IPMATE
-+
-+#include "dwc_dh.h"
-+#include "dwc_modpow.h"
-+
-+#ifdef DEBUG
-+/* This function prints out a buffer in the format described in the Association
-+ * Model specification. */
-+static void dh_dump(char *str, void *_num, int len)
-+{
-+ uint8_t *num = _num;
-+ int i;
-+ DWC_PRINTF("%s\n", str);
-+ for (i = 0; i < len; i ++) {
-+ DWC_PRINTF("%02x", num[i]);
-+ if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
-+ if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
-+ }
-+
-+ DWC_PRINTF("\n");
-+}
-+#else
-+#define dh_dump(_x...) do {; } while(0)
-+#endif
-+
-+/* Constant g value */
-+static __u32 dh_g[] = {
-+ 0x02000000,
-+};
-+
-+/* Constant p value */
-+static __u32 dh_p[] = {
-+ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
-+ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
-+ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
-+ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
-+ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
-+ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
-+ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
-+ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
-+ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
-+ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
-+ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
-+ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
-+};
-+
-+static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
-+{
-+ uint8_t *in = _in;
-+ uint8_t *out = _out;
-+ int i;
-+ for (i=0; i<len; i++) {
-+ out[i] = in[len-1-i];
-+ }
-+}
-+
-+/* Computes the modular exponentiation (num^exp % mod). num, exp, and mod are
-+ * big endian numbers of size len, in bytes. Each len value must be a multiple
-+ * of 4. */
-+int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
-+ void *exp, uint32_t exp_len,
-+ void *mod, uint32_t mod_len,
-+ void *out)
-+{
-+ /* modpow() takes little endian numbers. AM uses big-endian. This
-+ * function swaps bytes of numbers before passing onto modpow. */
-+
-+ int retval = 0;
-+ uint32_t *result;
-+
-+ uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
-+ uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
-+ uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
-+
-+ dh_swap_bytes(num, &bignum_num[1], num_len);
-+ bignum_num[0] = num_len / 4;
-+
-+ dh_swap_bytes(exp, &bignum_exp[1], exp_len);
-+ bignum_exp[0] = exp_len / 4;
-+
-+ dh_swap_bytes(mod, &bignum_mod[1], mod_len);
-+ bignum_mod[0] = mod_len / 4;
-+
-+ result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
-+ if (!result) {
-+ retval = -1;
-+ goto dh_modpow_nomem;
-+ }
-+
-+ dh_swap_bytes(&result[1], out, result[0] * 4);
-+ dwc_free(mem_ctx, result);
-+
-+ dh_modpow_nomem:
-+ dwc_free(mem_ctx, bignum_num);
-+ dwc_free(mem_ctx, bignum_exp);
-+ dwc_free(mem_ctx, bignum_mod);
-+ return retval;
-+}
-+
-+
-+int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
-+{
-+ int retval;
-+ uint8_t m3[385];
-+
-+#ifndef DH_TEST_VECTORS
-+ DWC_RANDOM_BYTES(exp, 32);
-+#endif
-+
-+ /* Compute the pkd */
-+ if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
-+ exp, 32,
-+ dh_p, 384, pk))) {
-+ return retval;
-+ }
-+
-+ m3[384] = nd;
-+ DWC_MEMCPY(&m3[0], pk, 384);
-+ DWC_SHA256(m3, 385, hash);
-+
-+ dh_dump("PK", pk, 384);
-+ dh_dump("SHA-256(M3)", hash, 32);
-+ return 0;
-+}
-+
-+int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
-+ uint8_t *exp, int is_host,
-+ char *dd, uint8_t *ck, uint8_t *kdk)
-+{
-+ int retval;
-+ uint8_t mv[784];
-+ uint8_t sha_result[32];
-+ uint8_t dhkey[384];
-+ uint8_t shared_secret[384];
-+ char *message;
-+ uint32_t vd;
-+
-+ uint8_t *pk;
-+
-+ if (is_host) {
-+ pk = pkd;
-+ }
-+ else {
-+ pk = pkh;
-+ }
-+
-+ if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
-+ exp, 32,
-+ dh_p, 384, shared_secret))) {
-+ return retval;
-+ }
-+ dh_dump("Shared Secret", shared_secret, 384);
-+
-+ DWC_SHA256(shared_secret, 384, dhkey);
-+ dh_dump("DHKEY", dhkey, 384);
-+
-+ DWC_MEMCPY(&mv[0], pkd, 384);
-+ DWC_MEMCPY(&mv[384], pkh, 384);
-+ DWC_MEMCPY(&mv[768], "displayed digest", 16);
-+ dh_dump("MV", mv, 784);
-+
-+ DWC_SHA256(mv, 784, sha_result);
-+ dh_dump("SHA-256(MV)", sha_result, 32);
-+ dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
-+
-+ dh_swap_bytes(sha_result, &vd, 4);
-+#ifdef DEBUG
-+ DWC_PRINTF("Vd (decimal) = %d\n", vd);
-+#endif
-+
-+ switch (nd) {
-+ case 2:
-+ vd = vd % 100;
-+ DWC_SPRINTF(dd, "%02d", vd);
-+ break;
-+ case 3:
-+ vd = vd % 1000;
-+ DWC_SPRINTF(dd, "%03d", vd);
-+ break;
-+ case 4:
-+ vd = vd % 10000;
-+ DWC_SPRINTF(dd, "%04d", vd);
-+ break;
-+ }
-+#ifdef DEBUG
-+ DWC_PRINTF("Display Digits: %s\n", dd);
-+#endif
-+
-+ message = "connection key";
-+ DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
-+ dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
-+ DWC_MEMCPY(ck, sha_result, 16);
-+
-+ message = "key derivation key";
-+ DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
-+ dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
-+ DWC_MEMCPY(kdk, sha_result, 32);
-+
-+ return 0;
-+}
-+
-+
-+#ifdef DH_TEST_VECTORS
-+
-+static __u8 dh_a[] = {
-+ 0x44, 0x00, 0x51, 0xd6,
-+ 0xf0, 0xb5, 0x5e, 0xa9,
-+ 0x67, 0xab, 0x31, 0xc6,
-+ 0x8a, 0x8b, 0x5e, 0x37,
-+ 0xd9, 0x10, 0xda, 0xe0,
-+ 0xe2, 0xd4, 0x59, 0xa4,
-+ 0x86, 0x45, 0x9c, 0xaa,
-+ 0xdf, 0x36, 0x75, 0x16,
-+};
-+
-+static __u8 dh_b[] = {
-+ 0x5d, 0xae, 0xc7, 0x86,
-+ 0x79, 0x80, 0xa3, 0x24,
-+ 0x8c, 0xe3, 0x57, 0x8f,
-+ 0xc7, 0x5f, 0x1b, 0x0f,
-+ 0x2d, 0xf8, 0x9d, 0x30,
-+ 0x6f, 0xa4, 0x52, 0xcd,
-+ 0xe0, 0x7a, 0x04, 0x8a,
-+ 0xde, 0xd9, 0x26, 0x56,
-+};
-+
-+void dwc_run_dh_test_vectors(void *mem_ctx)
-+{
-+ uint8_t pkd[384];
-+ uint8_t pkh[384];
-+ uint8_t hashd[32];
-+ uint8_t hashh[32];
-+ uint8_t ck[16];
-+ uint8_t kdk[32];
-+ char dd[5];
-+
-+ DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
-+
-+ /* compute the PKd and SHA-256(PKd || Nd) */
-+ DWC_PRINTF("Computing PKd\n");
-+ dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
-+
-+ /* compute the PKd and SHA-256(PKh || Nd) */
-+ DWC_PRINTF("Computing PKh\n");
-+ dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
-+
-+ /* compute the dhkey */
-+ dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
-+}
-+#endif /* DH_TEST_VECTORS */
-+
-+#endif /* !CONFIG_MACH_IPMATE */
-+
-+#endif /* DWC_CRYPTOLIB */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_dh.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_dh.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,106 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
-+ * $Revision: #4 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_DH_H_
-+#define _DWC_DH_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * This file defines the common functions on device and host for performing
-+ * numeric association as defined in the WUSB spec. They are only to be
-+ * used internally by the DWC UWB modules. */
-+
-+extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
-+extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen,
-+ uint8_t *out);
-+extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
-+ void *exp, uint32_t exp_len,
-+ void *mod, uint32_t mod_len,
-+ void *out);
-+
-+/** Computes PKD or PKH, and SHA-256(PKd || Nd)
-+ *
-+ * PK = g^exp mod p.
-+ *
-+ * Input:
-+ * Nd = Number of digits on the device.
-+ *
-+ * Output:
-+ * exp = A 32-byte buffer to be filled with a randomly generated number.
-+ * used as either A or B.
-+ * pk = A 384-byte buffer to be filled with the PKH or PKD.
-+ * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
-+ */
-+extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
-+
-+/** Computes the DHKEY, and VD.
-+ *
-+ * If called from host, then it will comput DHKEY=PKD^exp % p.
-+ * If called from device, then it will comput DHKEY=PKH^exp % p.
-+ *
-+ * Input:
-+ * pkd = The PKD value.
-+ * pkh = The PKH value.
-+ * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
-+ * is_host = Set to non zero if a WUSB host is calling this function.
-+ *
-+ * Output:
-+
-+ * dd = A pointer to an buffer to be set to the displayed digits string to be shown
-+ * to the user. This buffer should be at 5 bytes long to hold 4 digits plus a
-+ * null termination character. This buffer can be used directly for display.
-+ * ck = A 16-byte buffer to be filled with the CK.
-+ * kdk = A 32-byte buffer to be filled with the KDK.
-+ */
-+extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
-+ uint8_t *exp, int is_host,
-+ char *dd, uint8_t *ck, uint8_t *kdk);
-+
-+#ifdef DH_TEST_VECTORS
-+extern void dwc_run_dh_test_vectors(void);
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_DH_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_list.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_list.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_list.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_list.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,594 @@
-+/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
-+/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
-+
-+/*
-+ * Copyright (c) 1991, 1993
-+ * The Regents of the University of California. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. Neither the name of the University nor the names of its contributors
-+ * may be used to endorse or promote products derived from this software
-+ * without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
-+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-+ * SUCH DAMAGE.
-+ *
-+ * @(#)queue.h 8.5 (Berkeley) 8/20/94
-+ */
-+
-+#ifndef _DWC_LIST_H_
-+#define _DWC_LIST_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file defines linked list operations. It is derived from BSD with
-+ * only the MACRO names being prefixed with DWC_. This is because a few of
-+ * these names conflict with those on Linux. For documentation on use, see the
-+ * inline comments in the source code. The original license for this source
-+ * code applies and is preserved in the dwc_list.h source file.
-+ */
-+
-+/*
-+ * This file defines five types of data structures: singly-linked lists,
-+ * lists, simple queues, tail queues, and circular queues.
-+ *
-+ *
-+ * A singly-linked list is headed by a single forward pointer. The elements
-+ * are singly linked for minimum space and pointer manipulation overhead at
-+ * the expense of O(n) removal for arbitrary elements. New elements can be
-+ * added to the list after an existing element or at the head of the list.
-+ * Elements being removed from the head of the list should use the explicit
-+ * macro for this purpose for optimum efficiency. A singly-linked list may
-+ * only be traversed in the forward direction. Singly-linked lists are ideal
-+ * for applications with large datasets and few or no removals or for
-+ * implementing a LIFO queue.
-+ *
-+ * A list is headed by a single forward pointer (or an array of forward
-+ * pointers for a hash table header). The elements are doubly linked
-+ * so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before
-+ * or after an existing element or at the head of the list. A list
-+ * may only be traversed in the forward direction.
-+ *
-+ * A simple queue is headed by a pair of pointers, one the head of the
-+ * list and the other to the tail of the list. The elements are singly
-+ * linked to save space, so elements can only be removed from the
-+ * head of the list. New elements can be added to the list before or after
-+ * an existing element, at the head of the list, or at the end of the
-+ * list. A simple queue may only be traversed in the forward direction.
-+ *
-+ * A tail queue is headed by a pair of pointers, one to the head of the
-+ * list and the other to the tail of the list. The elements are doubly
-+ * linked so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before or
-+ * after an existing element, at the head of the list, or at the end of
-+ * the list. A tail queue may be traversed in either direction.
-+ *
-+ * A circle queue is headed by a pair of pointers, one to the head of the
-+ * list and the other to the tail of the list. The elements are doubly
-+ * linked so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before or after
-+ * an existing element, at the head of the list, or at the end of the list.
-+ * A circle queue may be traversed in either direction, but has a more
-+ * complex end of list detection.
-+ *
-+ * For details on the use of these macros, see the queue(3) manual page.
-+ */
-+
-+/*
-+ * Double-linked List.
-+ */
-+
-+typedef struct dwc_list_link {
-+ struct dwc_list_link *next;
-+ struct dwc_list_link *prev;
-+} dwc_list_link_t;
-+
-+#define DWC_LIST_INIT(link) do { \
-+ (link)->next = (link); \
-+ (link)->prev = (link); \
-+} while (0)
-+
-+#define DWC_LIST_FIRST(link) ((link)->next)
-+#define DWC_LIST_LAST(link) ((link)->prev)
-+#define DWC_LIST_END(link) (link)
-+#define DWC_LIST_NEXT(link) ((link)->next)
-+#define DWC_LIST_PREV(link) ((link)->prev)
-+#define DWC_LIST_EMPTY(link) \
-+ (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
-+#define DWC_LIST_ENTRY(link, type, field) \
-+ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
-+
-+#if 0
-+#define DWC_LIST_INSERT_HEAD(list, link) do { \
-+ (link)->next = (list)->next; \
-+ (link)->prev = (list); \
-+ (list)->next->prev = (link); \
-+ (list)->next = (link); \
-+} while (0)
-+
-+#define DWC_LIST_INSERT_TAIL(list, link) do { \
-+ (link)->next = (list); \
-+ (link)->prev = (list)->prev; \
-+ (list)->prev->next = (link); \
-+ (list)->prev = (link); \
-+} while (0)
-+#else
-+#define DWC_LIST_INSERT_HEAD(list, link) do { \
-+ dwc_list_link_t *__next__ = (list)->next; \
-+ __next__->prev = (link); \
-+ (link)->next = __next__; \
-+ (link)->prev = (list); \
-+ (list)->next = (link); \
-+} while (0)
-+
-+#define DWC_LIST_INSERT_TAIL(list, link) do { \
-+ dwc_list_link_t *__prev__ = (list)->prev; \
-+ (list)->prev = (link); \
-+ (link)->next = (list); \
-+ (link)->prev = __prev__; \
-+ __prev__->next = (link); \
-+} while (0)
-+#endif
-+
-+#if 0
-+static inline void __list_add(struct list_head *new,
-+ struct list_head *prev,
-+ struct list_head *next)
-+{
-+ next->prev = new;
-+ new->next = next;
-+ new->prev = prev;
-+ prev->next = new;
-+}
-+
-+static inline void list_add(struct list_head *new, struct list_head *head)
-+{
-+ __list_add(new, head, head->next);
-+}
-+
-+static inline void list_add_tail(struct list_head *new, struct list_head *head)
-+{
-+ __list_add(new, head->prev, head);
-+}
-+
-+static inline void __list_del(struct list_head * prev, struct list_head * next)
-+{
-+ next->prev = prev;
-+ prev->next = next;
-+}
-+
-+static inline void list_del(struct list_head *entry)
-+{
-+ __list_del(entry->prev, entry->next);
-+ entry->next = LIST_POISON1;
-+ entry->prev = LIST_POISON2;
-+}
-+#endif
-+
-+#define DWC_LIST_REMOVE(link) do { \
-+ (link)->next->prev = (link)->prev; \
-+ (link)->prev->next = (link)->next; \
-+} while (0)
-+
-+#define DWC_LIST_REMOVE_INIT(link) do { \
-+ DWC_LIST_REMOVE(link); \
-+ DWC_LIST_INIT(link); \
-+} while (0)
-+
-+#define DWC_LIST_MOVE_HEAD(list, link) do { \
-+ DWC_LIST_REMOVE(link); \
-+ DWC_LIST_INSERT_HEAD(list, link); \
-+} while (0)
-+
-+#define DWC_LIST_MOVE_TAIL(list, link) do { \
-+ DWC_LIST_REMOVE(link); \
-+ DWC_LIST_INSERT_TAIL(list, link); \
-+} while (0)
-+
-+#define DWC_LIST_FOREACH(var, list) \
-+ for((var) = DWC_LIST_FIRST(list); \
-+ (var) != DWC_LIST_END(list); \
-+ (var) = DWC_LIST_NEXT(var))
-+
-+#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
-+ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
-+ (var) != DWC_LIST_END(list); \
-+ (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
-+
-+#define DWC_LIST_FOREACH_REVERSE(var, list) \
-+ for((var) = DWC_LIST_LAST(list); \
-+ (var) != DWC_LIST_END(list); \
-+ (var) = DWC_LIST_PREV(var))
-+
-+/*
-+ * Singly-linked List definitions.
-+ */
-+#define DWC_SLIST_HEAD(name, type) \
-+struct name { \
-+ struct type *slh_first; /* first element */ \
-+}
-+
-+#define DWC_SLIST_HEAD_INITIALIZER(head) \
-+ { NULL }
-+
-+#define DWC_SLIST_ENTRY(type) \
-+struct { \
-+ struct type *sle_next; /* next element */ \
-+}
-+
-+/*
-+ * Singly-linked List access methods.
-+ */
-+#define DWC_SLIST_FIRST(head) ((head)->slh_first)
-+#define DWC_SLIST_END(head) NULL
-+#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
-+#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
-+
-+#define DWC_SLIST_FOREACH(var, head, field) \
-+ for((var) = SLIST_FIRST(head); \
-+ (var) != SLIST_END(head); \
-+ (var) = SLIST_NEXT(var, field))
-+
-+#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
-+ for((varp) = &SLIST_FIRST((head)); \
-+ ((var) = *(varp)) != SLIST_END(head); \
-+ (varp) = &SLIST_NEXT((var), field))
-+
-+/*
-+ * Singly-linked List functions.
-+ */
-+#define DWC_SLIST_INIT(head) { \
-+ SLIST_FIRST(head) = SLIST_END(head); \
-+}
-+
-+#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
-+ (elm)->field.sle_next = (slistelm)->field.sle_next; \
-+ (slistelm)->field.sle_next = (elm); \
-+} while (0)
-+
-+#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
-+ (elm)->field.sle_next = (head)->slh_first; \
-+ (head)->slh_first = (elm); \
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
-+ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
-+ (head)->slh_first = (head)->slh_first->field.sle_next; \
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
-+ if ((head)->slh_first == (elm)) { \
-+ SLIST_REMOVE_HEAD((head), field); \
-+ } \
-+ else { \
-+ struct type *curelm = (head)->slh_first; \
-+ while( curelm->field.sle_next != (elm) ) \
-+ curelm = curelm->field.sle_next; \
-+ curelm->field.sle_next = \
-+ curelm->field.sle_next->field.sle_next; \
-+ } \
-+} while (0)
-+
-+/*
-+ * Simple queue definitions.
-+ */
-+#define DWC_SIMPLEQ_HEAD(name, type) \
-+struct name { \
-+ struct type *sqh_first; /* first element */ \
-+ struct type **sqh_last; /* addr of last next element */ \
-+}
-+
-+#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
-+ { NULL, &(head).sqh_first }
-+
-+#define DWC_SIMPLEQ_ENTRY(type) \
-+struct { \
-+ struct type *sqe_next; /* next element */ \
-+}
-+
-+/*
-+ * Simple queue access methods.
-+ */
-+#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
-+#define DWC_SIMPLEQ_END(head) NULL
-+#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
-+#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
-+
-+#define DWC_SIMPLEQ_FOREACH(var, head, field) \
-+ for((var) = SIMPLEQ_FIRST(head); \
-+ (var) != SIMPLEQ_END(head); \
-+ (var) = SIMPLEQ_NEXT(var, field))
-+
-+/*
-+ * Simple queue functions.
-+ */
-+#define DWC_SIMPLEQ_INIT(head) do { \
-+ (head)->sqh_first = NULL; \
-+ (head)->sqh_last = &(head)->sqh_first; \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
-+ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
-+ (head)->sqh_last = &(elm)->field.sqe_next; \
-+ (head)->sqh_first = (elm); \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
-+ (elm)->field.sqe_next = NULL; \
-+ *(head)->sqh_last = (elm); \
-+ (head)->sqh_last = &(elm)->field.sqe_next; \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
-+ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
-+ (head)->sqh_last = &(elm)->field.sqe_next; \
-+ (listelm)->field.sqe_next = (elm); \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
-+ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
-+ (head)->sqh_last = &(head)->sqh_first; \
-+} while (0)
-+
-+/*
-+ * Tail queue definitions.
-+ */
-+#define DWC_TAILQ_HEAD(name, type) \
-+struct name { \
-+ struct type *tqh_first; /* first element */ \
-+ struct type **tqh_last; /* addr of last next element */ \
-+}
-+
-+#define DWC_TAILQ_HEAD_INITIALIZER(head) \
-+ { NULL, &(head).tqh_first }
-+
-+#define DWC_TAILQ_ENTRY(type) \
-+struct { \
-+ struct type *tqe_next; /* next element */ \
-+ struct type **tqe_prev; /* address of previous next element */ \
-+}
-+
-+/*
-+ * tail queue access methods
-+ */
-+#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
-+#define DWC_TAILQ_END(head) NULL
-+#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-+#define DWC_TAILQ_LAST(head, headname) \
-+ (*(((struct headname *)((head)->tqh_last))->tqh_last))
-+/* XXX */
-+#define DWC_TAILQ_PREV(elm, headname, field) \
-+ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-+#define DWC_TAILQ_EMPTY(head) \
-+ (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
-+
-+#define DWC_TAILQ_FOREACH(var, head, field) \
-+ for ((var) = DWC_TAILQ_FIRST(head); \
-+ (var) != DWC_TAILQ_END(head); \
-+ (var) = DWC_TAILQ_NEXT(var, field))
-+
-+#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
-+ for ((var) = DWC_TAILQ_LAST(head, headname); \
-+ (var) != DWC_TAILQ_END(head); \
-+ (var) = DWC_TAILQ_PREV(var, headname, field))
-+
-+/*
-+ * Tail queue functions.
-+ */
-+#define DWC_TAILQ_INIT(head) do { \
-+ (head)->tqh_first = NULL; \
-+ (head)->tqh_last = &(head)->tqh_first; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
-+ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
-+ (head)->tqh_first->field.tqe_prev = \
-+ &(elm)->field.tqe_next; \
-+ else \
-+ (head)->tqh_last = &(elm)->field.tqe_next; \
-+ (head)->tqh_first = (elm); \
-+ (elm)->field.tqe_prev = &(head)->tqh_first; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
-+ (elm)->field.tqe_next = NULL; \
-+ (elm)->field.tqe_prev = (head)->tqh_last; \
-+ *(head)->tqh_last = (elm); \
-+ (head)->tqh_last = &(elm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
-+ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
-+ (elm)->field.tqe_next->field.tqe_prev = \
-+ &(elm)->field.tqe_next; \
-+ else \
-+ (head)->tqh_last = &(elm)->field.tqe_next; \
-+ (listelm)->field.tqe_next = (elm); \
-+ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
-+ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
-+ (elm)->field.tqe_next = (listelm); \
-+ *(listelm)->field.tqe_prev = (elm); \
-+ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_REMOVE(head, elm, field) do { \
-+ if (((elm)->field.tqe_next) != NULL) \
-+ (elm)->field.tqe_next->field.tqe_prev = \
-+ (elm)->field.tqe_prev; \
-+ else \
-+ (head)->tqh_last = (elm)->field.tqe_prev; \
-+ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
-+ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
-+ (elm2)->field.tqe_next->field.tqe_prev = \
-+ &(elm2)->field.tqe_next; \
-+ else \
-+ (head)->tqh_last = &(elm2)->field.tqe_next; \
-+ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
-+ *(elm2)->field.tqe_prev = (elm2); \
-+} while (0)
-+
-+/*
-+ * Circular queue definitions.
-+ */
-+#define DWC_CIRCLEQ_HEAD(name, type) \
-+struct name { \
-+ struct type *cqh_first; /* first element */ \
-+ struct type *cqh_last; /* last element */ \
-+}
-+
-+#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
-+ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
-+
-+#define DWC_CIRCLEQ_ENTRY(type) \
-+struct { \
-+ struct type *cqe_next; /* next element */ \
-+ struct type *cqe_prev; /* previous element */ \
-+}
-+
-+/*
-+ * Circular queue access methods
-+ */
-+#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
-+#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
-+#define DWC_CIRCLEQ_END(head) ((void *)(head))
-+#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
-+#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
-+#define DWC_CIRCLEQ_EMPTY(head) \
-+ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
-+
-+#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
-+
-+#define DWC_CIRCLEQ_FOREACH(var, head, field) \
-+ for((var) = DWC_CIRCLEQ_FIRST(head); \
-+ (var) != DWC_CIRCLEQ_END(head); \
-+ (var) = DWC_CIRCLEQ_NEXT(var, field))
-+
-+#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
-+ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
-+ (var) != DWC_CIRCLEQ_END(head); \
-+ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
-+
-+#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
-+ for((var) = DWC_CIRCLEQ_LAST(head); \
-+ (var) != DWC_CIRCLEQ_END(head); \
-+ (var) = DWC_CIRCLEQ_PREV(var, field))
-+
-+/*
-+ * Circular queue functions.
-+ */
-+#define DWC_CIRCLEQ_INIT(head) do { \
-+ (head)->cqh_first = DWC_CIRCLEQ_END(head); \
-+ (head)->cqh_last = DWC_CIRCLEQ_END(head); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
-+ (elm)->field.cqe_next = NULL; \
-+ (elm)->field.cqe_prev = NULL; \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
-+ (elm)->field.cqe_next = (listelm)->field.cqe_next; \
-+ (elm)->field.cqe_prev = (listelm); \
-+ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_last = (elm); \
-+ else \
-+ (listelm)->field.cqe_next->field.cqe_prev = (elm); \
-+ (listelm)->field.cqe_next = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
-+ (elm)->field.cqe_next = (listelm); \
-+ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
-+ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_first = (elm); \
-+ else \
-+ (listelm)->field.cqe_prev->field.cqe_next = (elm); \
-+ (listelm)->field.cqe_prev = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
-+ (elm)->field.cqe_next = (head)->cqh_first; \
-+ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
-+ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_last = (elm); \
-+ else \
-+ (head)->cqh_first->field.cqe_prev = (elm); \
-+ (head)->cqh_first = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
-+ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
-+ (elm)->field.cqe_prev = (head)->cqh_last; \
-+ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_first = (elm); \
-+ else \
-+ (head)->cqh_last->field.cqe_next = (elm); \
-+ (head)->cqh_last = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
-+ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_last = (elm)->field.cqe_prev; \
-+ else \
-+ (elm)->field.cqe_next->field.cqe_prev = \
-+ (elm)->field.cqe_prev; \
-+ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_first = (elm)->field.cqe_next; \
-+ else \
-+ (elm)->field.cqe_prev->field.cqe_next = \
-+ (elm)->field.cqe_next; \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
-+ DWC_CIRCLEQ_REMOVE(head, elm, field); \
-+ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
-+ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
-+ DWC_CIRCLEQ_END(head)) \
-+ (head).cqh_last = (elm2); \
-+ else \
-+ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \
-+ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
-+ DWC_CIRCLEQ_END(head)) \
-+ (head).cqh_first = (elm2); \
-+ else \
-+ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \
-+} while (0)
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_LIST_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_mem.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_mem.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,245 @@
-+/* Memory Debugging */
-+#ifdef DWC_DEBUG_MEMORY
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+struct allocation {
-+ void *addr;
-+ void *ctx;
-+ char *func;
-+ int line;
-+ uint32_t size;
-+ int dma;
-+ DWC_CIRCLEQ_ENTRY(allocation) entry;
-+};
-+
-+DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
-+
-+struct allocation_manager {
-+ void *mem_ctx;
-+ struct allocation_queue allocations;
-+
-+ /* statistics */
-+ int num;
-+ int num_freed;
-+ int num_active;
-+ uint32_t total;
-+ uint32_t cur;
-+ uint32_t max;
-+};
-+
-+static struct allocation_manager *manager = NULL;
-+
-+static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
-+ int dma)
-+{
-+ struct allocation *a;
-+
-+ DWC_ASSERT(manager != NULL, "manager not allocated");
-+
-+ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
-+ if (!a) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
-+ if (!a->func) {
-+ __DWC_FREE(manager->mem_ctx, a);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
-+ a->addr = addr;
-+ a->ctx = ctx;
-+ a->line = line;
-+ a->size = size;
-+ a->dma = dma;
-+ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
-+
-+ /* Update stats */
-+ manager->num++;
-+ manager->num_active++;
-+ manager->total += size;
-+ manager->cur += size;
-+
-+ if (manager->max < manager->cur) {
-+ manager->max = manager->cur;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct allocation *find_allocation(void *ctx, void *addr)
-+{
-+ struct allocation *a;
-+
-+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+ if (a->ctx == ctx && a->addr == addr) {
-+ return a;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+static void free_allocation(void *ctx, void *addr, char const *func, int line)
-+{
-+ struct allocation *a = find_allocation(ctx, addr);
-+
-+ if (!a) {
-+ DWC_ASSERT(0,
-+ "Free of address %p that was never allocated or already freed %s:%d",
-+ addr, func, line);
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
-+
-+ manager->num_active--;
-+ manager->num_freed++;
-+ manager->cur -= a->size;
-+ __DWC_FREE(manager->mem_ctx, a->func);
-+ __DWC_FREE(manager->mem_ctx, a);
-+}
-+
-+int dwc_memory_debug_start(void *mem_ctx)
-+{
-+ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
-+
-+ if (manager) {
-+ return -DWC_E_BUSY;
-+ }
-+
-+ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
-+ if (!manager) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&manager->allocations);
-+ manager->mem_ctx = mem_ctx;
-+ manager->num = 0;
-+ manager->num_freed = 0;
-+ manager->num_active = 0;
-+ manager->total = 0;
-+ manager->cur = 0;
-+ manager->max = 0;
-+
-+ return 0;
-+}
-+
-+void dwc_memory_debug_stop(void)
-+{
-+ struct allocation *a;
-+
-+ dwc_memory_debug_report();
-+
-+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
-+ free_allocation(a->ctx, a->addr, NULL, -1);
-+ }
-+
-+ __DWC_FREE(manager->mem_ctx, manager);
-+}
-+
-+void dwc_memory_debug_report(void)
-+{
-+ struct allocation *a;
-+
-+ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
-+ DWC_PRINTF("Num Allocations = %d\n", manager->num);
-+ DWC_PRINTF("Freed = %d\n", manager->num_freed);
-+ DWC_PRINTF("Active = %d\n", manager->num_active);
-+ DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
-+ DWC_PRINTF("Total Memory Used = %d\n", manager->total);
-+ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
-+ DWC_PRINTF("Unfreed allocations:\n");
-+
-+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n",
-+ a->addr, a->size, a->func, a->line, a->dma);
-+ }
-+}
-+
-+/* The replacement functions */
-+void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
-+{
-+ void *addr = __DWC_ALLOC(mem_ctx, size);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
-+ __DWC_FREE(mem_ctx, addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
-+ int line)
-+{
-+ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
-+ __DWC_FREE(mem_ctx, addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
-+{
-+ free_allocation(mem_ctx, addr, func, line);
-+ __DWC_FREE(mem_ctx, addr);
-+}
-+
-+void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+ char const *func, int line)
-+{
-+ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
-+ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
-+ dwc_dma_t *dma_addr, char const *func, int line)
-+{
-+ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
-+ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
-+ dwc_dma_t dma_addr, char const *func, int line)
-+{
-+ free_allocation(dma_ctx, virt_addr, func, line);
-+ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
-+}
-+
-+#endif /* DWC_DEBUG_MEMORY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_modpow.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_modpow.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,636 @@
-+/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows.
-+ *
-+ * PuTTY is copyright 1997-2007 Simon Tatham.
-+ *
-+ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
-+ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
-+ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
-+ * Kuhn, and CORE SDI S.A.
-+ *
-+ * Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation files
-+ * (the "Software"), to deal in the Software without restriction,
-+ * including without limitation the rights to use, copy, modify, merge,
-+ * publish, distribute, sublicense, and/or sell copies of the Software,
-+ * and to permit persons to whom the Software is furnished to do so,
-+ * subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
-+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
-+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifdef DWC_CRYPTOLIB
-+
-+#ifndef CONFIG_MACH_IPMATE
-+
-+#include "dwc_modpow.h"
-+
-+#define BIGNUM_INT_MASK 0xFFFFFFFFUL
-+#define BIGNUM_TOP_BIT 0x80000000UL
-+#define BIGNUM_INT_BITS 32
-+
-+
-+static void *snmalloc(void *mem_ctx, size_t n, size_t size)
-+{
-+ void *p;
-+ size *= n;
-+ if (size == 0) size = 1;
-+ p = dwc_alloc(mem_ctx, size);
-+ return p;
-+}
-+
-+#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
-+#define sfree dwc_free
-+
-+/*
-+ * Usage notes:
-+ * * Do not call the DIVMOD_WORD macro with expressions such as array
-+ * subscripts, as some implementations object to this (see below).
-+ * * Note that none of the division methods below will cope if the
-+ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
-+ * to avoid this case.
-+ * If this condition occurs, in the case of the x86 DIV instruction,
-+ * an overflow exception will occur, which (according to a correspondent)
-+ * will manifest on Windows as something like
-+ * 0xC0000095: Integer overflow
-+ * The C variant won't give the right answer, either.
-+ */
-+
-+#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
-+
-+#if defined __GNUC__ && defined __i386__
-+#define DIVMOD_WORD(q, r, hi, lo, w) \
-+ __asm__("div %2" : \
-+ "=d" (r), "=a" (q) : \
-+ "r" (w), "d" (hi), "a" (lo))
-+#else
-+#define DIVMOD_WORD(q, r, hi, lo, w) do { \
-+ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
-+ q = n / w; \
-+ r = n % w; \
-+} while (0)
-+#endif
-+
-+// q = n / w;
-+// r = n % w;
-+
-+#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
-+
-+#define BIGNUM_INTERNAL
-+
-+static Bignum newbn(void *mem_ctx, int length)
-+{
-+ Bignum b = snewn(mem_ctx, length + 1, BignumInt);
-+ //if (!b)
-+ //abort(); /* FIXME */
-+ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
-+ b[0] = length;
-+ return b;
-+}
-+
-+void freebn(void *mem_ctx, Bignum b)
-+{
-+ /*
-+ * Burn the evidence, just in case.
-+ */
-+ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
-+ sfree(mem_ctx, b);
-+}
-+
-+/*
-+ * Compute c = a * b.
-+ * Input is in the first len words of a and b.
-+ * Result is returned in the first 2*len words of c.
-+ */
-+static void internal_mul(BignumInt *a, BignumInt *b,
-+ BignumInt *c, int len)
-+{
-+ int i, j;
-+ BignumDblInt t;
-+
-+ for (j = 0; j < 2 * len; j++)
-+ c[j] = 0;
-+
-+ for (i = len - 1; i >= 0; i--) {
-+ t = 0;
-+ for (j = len - 1; j >= 0; j--) {
-+ t += MUL_WORD(a[i], (BignumDblInt) b[j]);
-+ t += (BignumDblInt) c[i + j + 1];
-+ c[i + j + 1] = (BignumInt) t;
-+ t = t >> BIGNUM_INT_BITS;
-+ }
-+ c[i] = (BignumInt) t;
-+ }
-+}
-+
-+static void internal_add_shifted(BignumInt *number,
-+ unsigned n, int shift)
-+{
-+ int word = 1 + (shift / BIGNUM_INT_BITS);
-+ int bshift = shift % BIGNUM_INT_BITS;
-+ BignumDblInt addend;
-+
-+ addend = (BignumDblInt)n << bshift;
-+
-+ while (addend) {
-+ addend += number[word];
-+ number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
-+ addend >>= BIGNUM_INT_BITS;
-+ word++;
-+ }
-+}
-+
-+/*
-+ * Compute a = a % m.
-+ * Input in first alen words of a and first mlen words of m.
-+ * Output in first alen words of a
-+ * (of which first alen-mlen words will be zero).
-+ * The MSW of m MUST have its high bit set.
-+ * Quotient is accumulated in the `quotient' array, which is a Bignum
-+ * rather than the internal bigendian format. Quotient parts are shifted
-+ * left by `qshift' before adding into quot.
-+ */
-+static void internal_mod(BignumInt *a, int alen,
-+ BignumInt *m, int mlen,
-+ BignumInt *quot, int qshift)
-+{
-+ BignumInt m0, m1;
-+ unsigned int h;
-+ int i, k;
-+
-+ m0 = m[0];
-+ if (mlen > 1)
-+ m1 = m[1];
-+ else
-+ m1 = 0;
-+
-+ for (i = 0; i <= alen - mlen; i++) {
-+ BignumDblInt t;
-+ unsigned int q, r, c, ai1;
-+
-+ if (i == 0) {
-+ h = 0;
-+ } else {
-+ h = a[i - 1];
-+ a[i - 1] = 0;
-+ }
-+
-+ if (i == alen - 1)
-+ ai1 = 0;
-+ else
-+ ai1 = a[i + 1];
-+
-+ /* Find q = h:a[i] / m0 */
-+ if (h >= m0) {
-+ /*
-+ * Special case.
-+ *
-+ * To illustrate it, suppose a BignumInt is 8 bits, and
-+ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
-+ * our initial division will be 0xA123 / 0xA1, which
-+ * will give a quotient of 0x100 and a divide overflow.
-+ * However, the invariants in this division algorithm
-+ * are not violated, since the full number A1:23:... is
-+ * _less_ than the quotient prefix A1:B2:... and so the
-+ * following correction loop would have sorted it out.
-+ *
-+ * In this situation we set q to be the largest
-+ * quotient we _can_ stomach (0xFF, of course).
-+ */
-+ q = BIGNUM_INT_MASK;
-+ } else {
-+ /* Macro doesn't want an array subscript expression passed
-+ * into it (see definition), so use a temporary. */
-+ BignumInt tmplo = a[i];
-+ DIVMOD_WORD(q, r, h, tmplo, m0);
-+
-+ /* Refine our estimate of q by looking at
-+ h:a[i]:a[i+1] / m0:m1 */
-+ t = MUL_WORD(m1, q);
-+ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
-+ q--;
-+ t -= m1;
-+ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */
-+ if (r >= (BignumDblInt) m0 &&
-+ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
-+ }
-+ }
-+
-+ /* Subtract q * m from a[i...] */
-+ c = 0;
-+ for (k = mlen - 1; k >= 0; k--) {
-+ t = MUL_WORD(q, m[k]);
-+ t += c;
-+ c = (unsigned)(t >> BIGNUM_INT_BITS);
-+ if ((BignumInt) t > a[i + k])
-+ c++;
-+ a[i + k] -= (BignumInt) t;
-+ }
-+
-+ /* Add back m in case of borrow */
-+ if (c != h) {
-+ t = 0;
-+ for (k = mlen - 1; k >= 0; k--) {
-+ t += m[k];
-+ t += a[i + k];
-+ a[i + k] = (BignumInt) t;
-+ t = t >> BIGNUM_INT_BITS;
-+ }
-+ q--;
-+ }
-+ if (quot)
-+ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
-+ }
-+}
-+
-+/*
-+ * Compute p % mod.
-+ * The most significant word of mod MUST be non-zero.
-+ * We assume that the result array is the same size as the mod array.
-+ * We optionally write out a quotient if `quotient' is non-NULL.
-+ * We can avoid writing out the result if `result' is NULL.
-+ */
-+void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
-+{
-+ BignumInt *n, *m;
-+ int mshift;
-+ int plen, mlen, i, j;
-+
-+ /* Allocate m of size mlen, copy mod to m */
-+ /* We use big endian internally */
-+ mlen = mod[0];
-+ m = snewn(mem_ctx, mlen, BignumInt);
-+ //if (!m)
-+ //abort(); /* FIXME */
-+ for (j = 0; j < mlen; j++)
-+ m[j] = mod[mod[0] - j];
-+
-+ /* Shift m left to make msb bit set */
-+ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
-+ if ((m[0] << mshift) & BIGNUM_TOP_BIT)
-+ break;
-+ if (mshift) {
-+ for (i = 0; i < mlen - 1; i++)
-+ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
-+ m[mlen - 1] = m[mlen - 1] << mshift;
-+ }
-+
-+ plen = p[0];
-+ /* Ensure plen > mlen */
-+ if (plen <= mlen)
-+ plen = mlen + 1;
-+
-+ /* Allocate n of size plen, copy p to n */
-+ n = snewn(mem_ctx, plen, BignumInt);
-+ //if (!n)
-+ //abort(); /* FIXME */
-+ for (j = 0; j < plen; j++)
-+ n[j] = 0;
-+ for (j = 1; j <= (int)p[0]; j++)
-+ n[plen - j] = p[j];
-+
-+ /* Main computation */
-+ internal_mod(n, plen, m, mlen, quotient, mshift);
-+
-+ /* Fixup result in case the modulus was shifted */
-+ if (mshift) {
-+ for (i = plen - mlen - 1; i < plen - 1; i++)
-+ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
-+ n[plen - 1] = n[plen - 1] << mshift;
-+ internal_mod(n, plen, m, mlen, quotient, 0);
-+ for (i = plen - 1; i >= plen - mlen; i--)
-+ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
-+ }
-+
-+ /* Copy result to buffer */
-+ if (result) {
-+ for (i = 1; i <= (int)result[0]; i++) {
-+ int j = plen - i;
-+ result[i] = j >= 0 ? n[j] : 0;
-+ }
-+ }
-+
-+ /* Free temporary arrays */
-+ for (i = 0; i < mlen; i++)
-+ m[i] = 0;
-+ sfree(mem_ctx, m);
-+ for (i = 0; i < plen; i++)
-+ n[i] = 0;
-+ sfree(mem_ctx, n);
-+}
-+
-+/*
-+ * Simple remainder.
-+ */
-+Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
-+{
-+ Bignum r = newbn(mem_ctx, b[0]);
-+ bigdivmod(mem_ctx, a, b, r, NULL);
-+ return r;
-+}
-+
-+/*
-+ * Compute (base ^ exp) % mod.
-+ */
-+Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
-+{
-+ BignumInt *a, *b, *n, *m;
-+ int mshift;
-+ int mlen, i, j;
-+ Bignum base, result;
-+
-+ /*
-+ * The most significant word of mod needs to be non-zero. It
-+ * should already be, but let's make sure.
-+ */
-+ //assert(mod[mod[0]] != 0);
-+
-+ /*
-+ * Make sure the base is smaller than the modulus, by reducing
-+ * it modulo the modulus if not.
-+ */
-+ base = bigmod(mem_ctx, base_in, mod);
-+
-+ /* Allocate m of size mlen, copy mod to m */
-+ /* We use big endian internally */
-+ mlen = mod[0];
-+ m = snewn(mem_ctx, mlen, BignumInt);
-+ //if (!m)
-+ //abort(); /* FIXME */
-+ for (j = 0; j < mlen; j++)
-+ m[j] = mod[mod[0] - j];
-+
-+ /* Shift m left to make msb bit set */
-+ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
-+ if ((m[0] << mshift) & BIGNUM_TOP_BIT)
-+ break;
-+ if (mshift) {
-+ for (i = 0; i < mlen - 1; i++)
-+ m[i] =
-+ (m[i] << mshift) | (m[i + 1] >>
-+ (BIGNUM_INT_BITS - mshift));
-+ m[mlen - 1] = m[mlen - 1] << mshift;
-+ }
-+
-+ /* Allocate n of size mlen, copy base to n */
-+ n = snewn(mem_ctx, mlen, BignumInt);
-+ //if (!n)
-+ //abort(); /* FIXME */
-+ i = mlen - base[0];
-+ for (j = 0; j < i; j++)
-+ n[j] = 0;
-+ for (j = 0; j < base[0]; j++)
-+ n[i + j] = base[base[0] - j];
-+
-+ /* Allocate a and b of size 2*mlen. Set a = 1 */
-+ a = snewn(mem_ctx, 2 * mlen, BignumInt);
-+ //if (!a)
-+ //abort(); /* FIXME */
-+ b = snewn(mem_ctx, 2 * mlen, BignumInt);
-+ //if (!b)
-+ //abort(); /* FIXME */
-+ for (i = 0; i < 2 * mlen; i++)
-+ a[i] = 0;
-+ a[2 * mlen - 1] = 1;
-+
-+ /* Skip leading zero bits of exp. */
-+ i = 0;
-+ j = BIGNUM_INT_BITS - 1;
-+ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
-+ j--;
-+ if (j < 0) {
-+ i++;
-+ j = BIGNUM_INT_BITS - 1;
-+ }
-+ }
-+
-+ /* Main computation */
-+ while (i < exp[0]) {
-+ while (j >= 0) {
-+ internal_mul(a + mlen, a + mlen, b, mlen);
-+ internal_mod(b, mlen * 2, m, mlen, NULL, 0);
-+ if ((exp[exp[0] - i] & (1 << j)) != 0) {
-+ internal_mul(b + mlen, n, a, mlen);
-+ internal_mod(a, mlen * 2, m, mlen, NULL, 0);
-+ } else {
-+ BignumInt *t;
-+ t = a;
-+ a = b;
-+ b = t;
-+ }
-+ j--;
-+ }
-+ i++;
-+ j = BIGNUM_INT_BITS - 1;
-+ }
-+
-+ /* Fixup result in case the modulus was shifted */
-+ if (mshift) {
-+ for (i = mlen - 1; i < 2 * mlen - 1; i++)
-+ a[i] =
-+ (a[i] << mshift) | (a[i + 1] >>
-+ (BIGNUM_INT_BITS - mshift));
-+ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
-+ internal_mod(a, mlen * 2, m, mlen, NULL, 0);
-+ for (i = 2 * mlen - 1; i >= mlen; i--)
-+ a[i] =
-+ (a[i] >> mshift) | (a[i - 1] <<
-+ (BIGNUM_INT_BITS - mshift));
-+ }
-+
-+ /* Copy result to buffer */
-+ result = newbn(mem_ctx, mod[0]);
-+ for (i = 0; i < mlen; i++)
-+ result[result[0] - i] = a[i + mlen];
-+ while (result[0] > 1 && result[result[0]] == 0)
-+ result[0]--;
-+
-+ /* Free temporary arrays */
-+ for (i = 0; i < 2 * mlen; i++)
-+ a[i] = 0;
-+ sfree(mem_ctx, a);
-+ for (i = 0; i < 2 * mlen; i++)
-+ b[i] = 0;
-+ sfree(mem_ctx, b);
-+ for (i = 0; i < mlen; i++)
-+ m[i] = 0;
-+ sfree(mem_ctx, m);
-+ for (i = 0; i < mlen; i++)
-+ n[i] = 0;
-+ sfree(mem_ctx, n);
-+
-+ freebn(mem_ctx, base);
-+
-+ return result;
-+}
-+
-+
-+#ifdef UNITTEST
-+
-+static __u32 dh_p[] = {
-+ 96,
-+ 0xFFFFFFFF,
-+ 0xFFFFFFFF,
-+ 0xA93AD2CA,
-+ 0x4B82D120,
-+ 0xE0FD108E,
-+ 0x43DB5BFC,
-+ 0x74E5AB31,
-+ 0x08E24FA0,
-+ 0xBAD946E2,
-+ 0x770988C0,
-+ 0x7A615D6C,
-+ 0xBBE11757,
-+ 0x177B200C,
-+ 0x521F2B18,
-+ 0x3EC86A64,
-+ 0xD8760273,
-+ 0xD98A0864,
-+ 0xF12FFA06,
-+ 0x1AD2EE6B,
-+ 0xCEE3D226,
-+ 0x4A25619D,
-+ 0x1E8C94E0,
-+ 0xDB0933D7,
-+ 0xABF5AE8C,
-+ 0xA6E1E4C7,
-+ 0xB3970F85,
-+ 0x5D060C7D,
-+ 0x8AEA7157,
-+ 0x58DBEF0A,
-+ 0xECFB8504,
-+ 0xDF1CBA64,
-+ 0xA85521AB,
-+ 0x04507A33,
-+ 0xAD33170D,
-+ 0x8AAAC42D,
-+ 0x15728E5A,
-+ 0x98FA0510,
-+ 0x15D22618,
-+ 0xEA956AE5,
-+ 0x3995497C,
-+ 0x95581718,
-+ 0xDE2BCBF6,
-+ 0x6F4C52C9,
-+ 0xB5C55DF0,
-+ 0xEC07A28F,
-+ 0x9B2783A2,
-+ 0x180E8603,
-+ 0xE39E772C,
-+ 0x2E36CE3B,
-+ 0x32905E46,
-+ 0xCA18217C,
-+ 0xF1746C08,
-+ 0x4ABC9804,
-+ 0x670C354E,
-+ 0x7096966D,
-+ 0x9ED52907,
-+ 0x208552BB,
-+ 0x1C62F356,
-+ 0xDCA3AD96,
-+ 0x83655D23,
-+ 0xFD24CF5F,
-+ 0x69163FA8,
-+ 0x1C55D39A,
-+ 0x98DA4836,
-+ 0xA163BF05,
-+ 0xC2007CB8,
-+ 0xECE45B3D,
-+ 0x49286651,
-+ 0x7C4B1FE6,
-+ 0xAE9F2411,
-+ 0x5A899FA5,
-+ 0xEE386BFB,
-+ 0xF406B7ED,
-+ 0x0BFF5CB6,
-+ 0xA637ED6B,
-+ 0xF44C42E9,
-+ 0x625E7EC6,
-+ 0xE485B576,
-+ 0x6D51C245,
-+ 0x4FE1356D,
-+ 0xF25F1437,
-+ 0x302B0A6D,
-+ 0xCD3A431B,
-+ 0xEF9519B3,
-+ 0x8E3404DD,
-+ 0x514A0879,
-+ 0x3B139B22,
-+ 0x020BBEA6,
-+ 0x8A67CC74,
-+ 0x29024E08,
-+ 0x80DC1CD1,
-+ 0xC4C6628B,
-+ 0x2168C234,
-+ 0xC90FDAA2,
-+ 0xFFFFFFFF,
-+ 0xFFFFFFFF,
-+};
-+
-+static __u32 dh_a[] = {
-+ 8,
-+ 0xdf367516,
-+ 0x86459caa,
-+ 0xe2d459a4,
-+ 0xd910dae0,
-+ 0x8a8b5e37,
-+ 0x67ab31c6,
-+ 0xf0b55ea9,
-+ 0x440051d6,
-+};
-+
-+static __u32 dh_b[] = {
-+ 8,
-+ 0xded92656,
-+ 0xe07a048a,
-+ 0x6fa452cd,
-+ 0x2df89d30,
-+ 0xc75f1b0f,
-+ 0x8ce3578f,
-+ 0x7980a324,
-+ 0x5daec786,
-+};
-+
-+static __u32 dh_g[] = {
-+ 1,
-+ 2,
-+};
-+
-+int main(void)
-+{
-+ int i;
-+ __u32 *k;
-+ k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
-+
-+ printf("\n\n");
-+ for (i=0; i<k[0]; i++) {
-+ __u32 word32 = k[k[0] - i];
-+ __u16 l = word32 & 0xffff;
-+ __u16 m = (word32 & 0xffff0000) >> 16;
-+ printf("%04x %04x ", m, l);
-+ if (!((i + 1)%13)) printf("\n");
-+ }
-+ printf("\n\n");
-+
-+ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
-+ printf("PASS\n\n");
-+ }
-+ else {
-+ printf("FAIL\n\n");
-+ }
-+
-+}
-+
-+#endif /* UNITTEST */
-+
-+#endif /* CONFIG_MACH_IPMATE */
-+
-+#endif /*DWC_CRYPTOLIB */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_modpow.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_modpow.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * dwc_modpow.h
-+ * See dwc_modpow.c for license and changes
-+ */
-+#ifndef _DWC_MODPOW_H
-+#define _DWC_MODPOW_H
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * This file defines the module exponentiation function which is only used
-+ * internally by the DWC UWB modules for calculation of PKs during numeric
-+ * association. The routine is taken from the PUTTY, an open source terminal
-+ * emulator. The PUTTY License is preserved in the dwc_modpow.c file.
-+ *
-+ */
-+
-+typedef uint32_t BignumInt;
-+typedef uint64_t BignumDblInt;
-+typedef BignumInt *Bignum;
-+
-+/* Compute modular exponentiaion */
-+extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _LINUX_BIGNUM_H */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_notifier.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_notifier.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,319 @@
-+#ifdef DWC_NOTIFYLIB
-+
-+#include "dwc_notifier.h"
-+#include "dwc_list.h"
-+
-+typedef struct dwc_observer {
-+ void *observer;
-+ dwc_notifier_callback_t callback;
-+ void *data;
-+ char *notification;
-+ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
-+} observer_t;
-+
-+DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
-+
-+typedef struct dwc_notifier {
-+ void *mem_ctx;
-+ void *object;
-+ struct observer_queue observers;
-+ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
-+} notifier_t;
-+
-+DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
-+
-+typedef struct manager {
-+ void *mem_ctx;
-+ void *wkq_ctx;
-+ dwc_workq_t *wq;
-+// dwc_mutex_t *mutex;
-+ struct notifier_queue notifiers;
-+} manager_t;
-+
-+static manager_t *manager = NULL;
-+
-+static int create_manager(void *mem_ctx, void *wkq_ctx)
-+{
-+ manager = dwc_alloc(mem_ctx, sizeof(manager_t));
-+ if (!manager) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&manager->notifiers);
-+
-+ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
-+ if (!manager->wq) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ return 0;
-+}
-+
-+static void free_manager(void)
-+{
-+ dwc_workq_free(manager->wq);
-+
-+ /* All notifiers must have unregistered themselves before this module
-+ * can be removed. Hitting this assertion indicates a programmer
-+ * error. */
-+ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
-+ "Notification manager being freed before all notifiers have been removed");
-+ dwc_free(manager->mem_ctx, manager);
-+}
-+
-+#ifdef DEBUG
-+static void dump_manager(void)
-+{
-+ notifier_t *n;
-+ observer_t *o;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ DWC_DEBUG("List of all notifiers and observers:\n");
-+ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
-+ DWC_DEBUG("Notifier %p has observers:\n", n->object);
-+ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
-+ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification);
-+ }
-+ }
-+}
-+#else
-+#define dump_manager(...)
-+#endif
-+
-+static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
-+ dwc_notifier_callback_t callback, void *data)
-+{
-+ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
-+
-+ if (!new_observer) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
-+ new_observer->observer = observer;
-+ new_observer->notification = notification;
-+ new_observer->callback = callback;
-+ new_observer->data = data;
-+ return new_observer;
-+}
-+
-+static void free_observer(void *mem_ctx, observer_t *observer)
-+{
-+ dwc_free(mem_ctx, observer);
-+}
-+
-+static notifier_t *alloc_notifier(void *mem_ctx, void *object)
-+{
-+ notifier_t *notifier;
-+
-+ if (!object) {
-+ return NULL;
-+ }
-+
-+ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
-+ if (!notifier) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&notifier->observers);
-+ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
-+
-+ notifier->mem_ctx = mem_ctx;
-+ notifier->object = object;
-+ return notifier;
-+}
-+
-+static void free_notifier(notifier_t *notifier)
-+{
-+ observer_t *observer;
-+
-+ DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
-+ free_observer(notifier->mem_ctx, observer);
-+ }
-+
-+ dwc_free(notifier->mem_ctx, notifier);
-+}
-+
-+static notifier_t *find_notifier(void *object)
-+{
-+ notifier_t *notifier;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ if (!object) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
-+ if (notifier->object == object) {
-+ return notifier;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
-+{
-+ return create_manager(mem_ctx, wkq_ctx);
-+}
-+
-+void dwc_free_notification_manager(void)
-+{
-+ free_manager();
-+}
-+
-+dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
-+{
-+ notifier_t *notifier;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ notifier = find_notifier(object);
-+ if (notifier) {
-+ DWC_ERROR("Notifier %p is already registered\n", object);
-+ return NULL;
-+ }
-+
-+ notifier = alloc_notifier(mem_ctx, object);
-+ if (!notifier) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
-+
-+ DWC_INFO("Notifier %p registered", object);
-+ dump_manager();
-+
-+ return notifier;
-+}
-+
-+void dwc_unregister_notifier(dwc_notifier_t *notifier)
-+{
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
-+ observer_t *o;
-+
-+ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
-+ DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
-+ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification);
-+ }
-+
-+ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),
-+ "Notifier %p has active observers when removing", notifier);
-+ }
-+
-+ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
-+ free_notifier(notifier);
-+
-+ DWC_INFO("Notifier unregistered");
-+ dump_manager();
-+}
-+
-+/* Add an observer to observe the notifier for a particular state, event, or notification. */
-+int dwc_add_observer(void *observer, void *object, char *notification,
-+ dwc_notifier_callback_t callback, void *data)
-+{
-+ notifier_t *notifier = find_notifier(object);
-+ observer_t *new_observer;
-+
-+ if (!notifier) {
-+ DWC_ERROR("Notifier %p is not found when adding observer\n", object);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
-+ if (!new_observer) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
-+
-+ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
-+ observer, object, notification, callback, data);
-+
-+ dump_manager();
-+ return 0;
-+}
-+
-+int dwc_remove_observer(void *observer)
-+{
-+ notifier_t *n;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
-+ observer_t *o;
-+ observer_t *o2;
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
-+ if (o->observer == observer) {
-+ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
-+ DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
-+ o->observer, n->object, o->notification);
-+ free_observer(n->mem_ctx, o);
-+ }
-+ }
-+ }
-+
-+ dump_manager();
-+ return 0;
-+}
-+
-+typedef struct callback_data {
-+ void *mem_ctx;
-+ dwc_notifier_callback_t cb;
-+ void *observer;
-+ void *data;
-+ void *object;
-+ char *notification;
-+ void *notification_data;
-+} cb_data_t;
-+
-+static void cb_task(void *data)
-+{
-+ cb_data_t *cb = (cb_data_t *)data;
-+
-+ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
-+ dwc_free(cb->mem_ctx, cb);
-+}
-+
-+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
-+{
-+ observer_t *o;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
-+ int len = DWC_STRLEN(notification);
-+
-+ if (DWC_STRLEN(o->notification) != len) {
-+ continue;
-+ }
-+
-+ if (DWC_STRNCMP(o->notification, notification, len) == 0) {
-+ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
-+
-+ if (!cb_data) {
-+ DWC_ERROR("Failed to allocate callback data\n");
-+ return;
-+ }
-+
-+ cb_data->mem_ctx = notifier->mem_ctx;
-+ cb_data->cb = o->callback;
-+ cb_data->observer = o->observer;
-+ cb_data->data = o->data;
-+ cb_data->object = notifier->object;
-+ cb_data->notification = notification;
-+ cb_data->notification_data = notification_data;
-+ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
-+ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
-+ "Notify callback from %p for Notification %s, to observer %p",
-+ cb_data->object, notification, cb_data->observer);
-+ }
-+ }
-+}
-+
-+#endif /* DWC_NOTIFYLIB */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_notifier.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_notifier.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,122 @@
-+
-+#ifndef __DWC_NOTIFIER_H__
-+#define __DWC_NOTIFIER_H__
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * A simple implementation of the Observer pattern. Any "module" can
-+ * register as an observer or notifier. The notion of "module" is abstract and
-+ * can mean anything used to identify either an observer or notifier. Usually
-+ * it will be a pointer to a data structure which contains some state, ie an
-+ * object.
-+ *
-+ * Before any notifiers can be added, the global notification manager must be
-+ * brought up with dwc_alloc_notification_manager().
-+ * dwc_free_notification_manager() will bring it down and free all resources.
-+ * These would typically be called upon module load and unload. The
-+ * notification manager is a single global instance that handles all registered
-+ * observable modules and observers so this should be done only once.
-+ *
-+ * A module can be observable by using Notifications to publicize some general
-+ * information about it's state or operation. It does not care who listens, or
-+ * even if anyone listens, or what they do with the information. The observable
-+ * modules do not need to know any information about it's observers or their
-+ * interface, or their state or data.
-+ *
-+ * Any module can register to emit Notifications. It should publish a list of
-+ * notifications that it can emit and their behavior, such as when they will get
-+ * triggered, and what information will be provided to the observer. Then it
-+ * should register itself as an observable module. See dwc_register_notifier().
-+ *
-+ * Any module can observe any observable, registered module, provided it has a
-+ * handle to the other module and knows what notifications to observe. See
-+ * dwc_add_observer().
-+ *
-+ * A function of type dwc_notifier_callback_t is called whenever a notification
-+ * is triggered with one or more observers observing it. This function is
-+ * called in it's own process so it may sleep or block if needed. It is
-+ * guaranteed to be called sometime after the notification has occurred and will
-+ * be called once per each time the notification is triggered. It will NOT be
-+ * called in the same process context used to trigger the notification.
-+ *
-+ * @section Limitiations
-+ *
-+ * Keep in mind that Notifications that can be triggered in rapid sucession may
-+ * schedule too many processes too handle. Be aware of this limitation when
-+ * designing to use notifications, and only add notifications for appropriate
-+ * observable information.
-+ *
-+ * Also Notification callbacks are not synchronous. If you need to synchronize
-+ * the behavior between module/observer you must use other means. And perhaps
-+ * that will mean Notifications are not the proper solution.
-+ */
-+
-+struct dwc_notifier;
-+typedef struct dwc_notifier dwc_notifier_t;
-+
-+/** The callback function must be of this type.
-+ *
-+ * @param object This is the object that is being observed.
-+ * @param notification This is the notification that was triggered.
-+ * @param observer This is the observer
-+ * @param notification_data This is notification-specific data that the notifier
-+ * has included in this notification. The value of this should be published in
-+ * the documentation of the observable module with the notifications.
-+ * @param user_data This is any custom data that the observer provided when
-+ * adding itself as an observer to the notification. */
-+typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
-+ void *notification_data, void *user_data);
-+
-+/** Brings up the notification manager. */
-+extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
-+/** Brings down the notification manager. */
-+extern void dwc_free_notification_manager(void);
-+
-+/** This function registers an observable module. A dwc_notifier_t object is
-+ * returned to the observable module. This is an opaque object that is used by
-+ * the observable module to trigger notifications. This object should only be
-+ * accessible to functions that are authorized to trigger notifications for this
-+ * module. Observers do not need this object. */
-+extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
-+
-+/** This function unregisters an observable module. All observers have to be
-+ * removed prior to unregistration. */
-+extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
-+
-+/** Add a module as an observer to the observable module. The observable module
-+ * needs to have previously registered with the notification manager.
-+ *
-+ * @param observer The observer module
-+ * @param object The module to observe
-+ * @param notification The notification to observe
-+ * @param callback The callback function to call
-+ * @param user_data Any additional user data to pass into the callback function */
-+extern int dwc_add_observer(void *observer, void *object, char *notification,
-+ dwc_notifier_callback_t callback, void *user_data);
-+
-+/** Removes the specified observer from all notifications that it is currently
-+ * observing. */
-+extern int dwc_remove_observer(void *observer);
-+
-+/** This function triggers a Notification. It should be called by the
-+ * observable module, or any module or library which the observable module
-+ * allows to trigger notification on it's behalf. Such as the dwc_cc_t.
-+ *
-+ * dwc_notify is a non-blocking function. Callbacks are scheduled called in
-+ * their own process context for each trigger. Callbacks can be blocking.
-+ * dwc_notify can be called from interrupt context if needed.
-+ *
-+ */
-+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* __DWC_NOTIFIER_H__ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_os.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/dwc_os.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,1262 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
-+ * $Revision: #14 $
-+ * $Date: 2010/11/04 $
-+ * $Change: 1621695 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_OS_H_
-+#define _DWC_OS_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * DWC portability library, low level os-wrapper functions
-+ *
-+ */
-+
-+/* These basic types need to be defined by some OS header file or custom header
-+ * file for your specific target architecture.
-+ *
-+ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
-+ *
-+ * Any custom or alternate header file must be added and enabled here.
-+ */
-+
-+#ifdef DWC_LINUX
-+# include <linux/types.h>
-+# ifdef CONFIG_DEBUG_MUTEXES
-+# include <linux/mutex.h>
-+# endif
-+# include <linux/errno.h>
-+# include <stdarg.h>
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+# include <os_dep.h>
-+#endif
-+
-+
-+/** @name Primitive Types and Values */
-+
-+/** We define a boolean type for consistency. Can be either YES or NO */
-+typedef uint8_t dwc_bool_t;
-+#define YES 1
-+#define NO 0
-+
-+#ifdef DWC_LINUX
-+
-+/** @name Error Codes */
-+#define DWC_E_INVALID EINVAL
-+#define DWC_E_NO_MEMORY ENOMEM
-+#define DWC_E_NO_DEVICE ENODEV
-+#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
-+#define DWC_E_TIMEOUT ETIMEDOUT
-+#define DWC_E_BUSY EBUSY
-+#define DWC_E_AGAIN EAGAIN
-+#define DWC_E_RESTART ERESTART
-+#define DWC_E_ABORT ECONNABORTED
-+#define DWC_E_SHUTDOWN ESHUTDOWN
-+#define DWC_E_NO_DATA ENODATA
-+#define DWC_E_DISCONNECT ECONNRESET
-+#define DWC_E_UNKNOWN EINVAL
-+#define DWC_E_NO_STREAM_RES ENOSR
-+#define DWC_E_COMMUNICATION ECOMM
-+#define DWC_E_OVERFLOW EOVERFLOW
-+#define DWC_E_PROTOCOL EPROTO
-+#define DWC_E_IN_PROGRESS EINPROGRESS
-+#define DWC_E_PIPE EPIPE
-+#define DWC_E_IO EIO
-+#define DWC_E_NO_SPACE ENOSPC
-+
-+#else
-+
-+/** @name Error Codes */
-+#define DWC_E_INVALID 1001
-+#define DWC_E_NO_MEMORY 1002
-+#define DWC_E_NO_DEVICE 1003
-+#define DWC_E_NOT_SUPPORTED 1004
-+#define DWC_E_TIMEOUT 1005
-+#define DWC_E_BUSY 1006
-+#define DWC_E_AGAIN 1007
-+#define DWC_E_RESTART 1008
-+#define DWC_E_ABORT 1009
-+#define DWC_E_SHUTDOWN 1010
-+#define DWC_E_NO_DATA 1011
-+#define DWC_E_DISCONNECT 2000
-+#define DWC_E_UNKNOWN 3000
-+#define DWC_E_NO_STREAM_RES 4001
-+#define DWC_E_COMMUNICATION 4002
-+#define DWC_E_OVERFLOW 4003
-+#define DWC_E_PROTOCOL 4004
-+#define DWC_E_IN_PROGRESS 4005
-+#define DWC_E_PIPE 4006
-+#define DWC_E_IO 4007
-+#define DWC_E_NO_SPACE 4008
-+
-+#endif
-+
-+
-+/** @name Tracing/Logging Functions
-+ *
-+ * These function provide the capability to add tracing, debugging, and error
-+ * messages, as well exceptions as assertions. The WUDEV uses these
-+ * extensively. These could be logged to the main console, the serial port, an
-+ * internal buffer, etc. These functions could also be no-op if they are too
-+ * expensive on your system. By default undefining the DEBUG macro already
-+ * no-ops some of these functions. */
-+
-+/** Returns non-zero if in interrupt context. */
-+extern dwc_bool_t DWC_IN_IRQ(void);
-+#define dwc_in_irq DWC_IN_IRQ
-+
-+/** Returns "IRQ" if DWC_IN_IRQ is true. */
-+static inline char *dwc_irq(void) {
-+ return DWC_IN_IRQ() ? "IRQ" : "";
-+}
-+
-+/** Returns non-zero if in bottom-half context. */
-+extern dwc_bool_t DWC_IN_BH(void);
-+#define dwc_in_bh DWC_IN_BH
-+
-+/** Returns "BH" if DWC_IN_BH is true. */
-+static inline char *dwc_bh(void) {
-+ return DWC_IN_BH() ? "BH" : "";
-+}
-+
-+/**
-+ * A vprintf() clone. Just call vprintf if you've got it.
-+ */
-+extern void DWC_VPRINTF(char *format, va_list args);
-+#define dwc_vprintf DWC_VPRINTF
-+
-+/**
-+ * A vsnprintf() clone. Just call vprintf if you've got it.
-+ */
-+extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
-+#define dwc_vsnprintf DWC_VSNPRINTF
-+
-+/**
-+ * printf() clone. Just call printf if you've go it.
-+ */
-+extern void DWC_PRINTF(char *format, ...)
-+/* This provides compiler level static checking of the parameters if you're
-+ * using GCC. */
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+#define dwc_printf DWC_PRINTF
-+
-+/**
-+ * sprintf() clone. Just call sprintf if you've got it.
-+ */
-+extern int DWC_SPRINTF(char *string, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 2, 3)));
-+#else
-+ ;
-+#endif
-+#define dwc_sprintf DWC_SPRINTF
-+
-+/**
-+ * snprintf() clone. Just call snprintf if you've got it.
-+ */
-+extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 3, 4)));
-+#else
-+ ;
-+#endif
-+#define dwc_snprintf DWC_SNPRINTF
-+
-+/**
-+ * Prints a WARNING message. On systems that don't differentiate between
-+ * warnings and regular log messages, just print it. Indicates that something
-+ * may be wrong with the driver. Works like printf().
-+ *
-+ * Use the DWC_WARN macro to call this function.
-+ */
-+extern void __DWC_WARN(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+
-+/**
-+ * Prints an error message. On systems that don't differentiate between errors
-+ * and regular log messages, just print it. Indicates that something went wrong
-+ * with the driver. Works like printf().
-+ *
-+ * Use the DWC_ERROR macro to call this function.
-+ */
-+extern void __DWC_ERROR(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+
-+/**
-+ * Prints an exception error message and takes some user-defined action such as
-+ * print out a backtrace or trigger a breakpoint. Indicates that something went
-+ * abnormally wrong with the driver such as programmer error, or other
-+ * exceptional condition. It should not be ignored so even on systems without
-+ * printing capability, some action should be taken to notify the developer of
-+ * it. Works like printf().
-+ */
-+extern void DWC_EXCEPTION(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+#define dwc_exception DWC_EXCEPTION
-+
-+#ifndef DWC_OTG_DEBUG_LEV
-+#define DWC_OTG_DEBUG_LEV 0
-+#endif
-+
-+#ifdef DEBUG
-+/**
-+ * Prints out a debug message. Used for logging/trace messages.
-+ *
-+ * Use the DWC_DEBUG macro to call this function
-+ */
-+extern void __DWC_DEBUG(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+#else
-+#define __DWC_DEBUG printk
-+#endif
-+
-+/**
-+ * Prints out a Debug message.
-+ */
-+#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
-+ __func__, dwc_irq(), ## _args)
-+#define dwc_debug DWC_DEBUG
-+/**
-+ * Prints out a Debug message if enabled at compile time.
-+ */
-+#if DWC_OTG_DEBUG_LEV > 0
-+#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
-+#else
-+#define DWC_DEBUGC(_format, _args...)
-+#endif
-+#define dwc_debugc DWC_DEBUGC
-+/**
-+ * Prints out an informative message.
-+ */
-+#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
-+ dwc_irq(), ## _args)
-+#define dwc_info DWC_INFO
-+/**
-+ * Prints out an informative message if enabled at compile time.
-+ */
-+#if DWC_OTG_DEBUG_LEV > 1
-+#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
-+#else
-+#define DWC_INFOC(_format, _args...)
-+#endif
-+#define dwc_infoc DWC_INFOC
-+/**
-+ * Prints out a warning message.
-+ */
-+#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
-+ dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_warn DWC_WARN
-+/**
-+ * Prints out an error message.
-+ */
-+#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
-+ dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_error DWC_ERROR
-+
-+#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
-+ dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_proto_error DWC_PROTO_ERROR
-+
-+#ifdef DEBUG
-+/** Prints out a exception error message if the _expr expression fails. Disabled
-+ * if DEBUG is not enabled. */
-+#define DWC_ASSERT(_expr, _format, _args...) do { \
-+ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
-+ __FILE__, __LINE__, ## _args); } \
-+ } while (0)
-+#else
-+#define DWC_ASSERT(_x...)
-+#endif
-+#define dwc_assert DWC_ASSERT
-+
-+
-+/** @name Byte Ordering
-+ * The following functions are for conversions between processor's byte ordering
-+ * and specific ordering you want.
-+ */
-+
-+/** Converts 32 bit data in CPU byte ordering to little endian. */
-+extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
-+#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
-+
-+/** Converts 32 bit data in CPU byte orderint to big endian. */
-+extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
-+#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
-+
-+/** Converts 32 bit little endian data to CPU byte ordering. */
-+extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
-+#define dwc_le32_to_cpu DWC_LE32_TO_CPU
-+
-+/** Converts 32 bit big endian data to CPU byte ordering. */
-+extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
-+#define dwc_be32_to_cpu DWC_BE32_TO_CPU
-+
-+/** Converts 16 bit data in CPU byte ordering to little endian. */
-+extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
-+#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
-+
-+/** Converts 16 bit data in CPU byte orderint to big endian. */
-+extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
-+#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
-+
-+/** Converts 16 bit little endian data to CPU byte ordering. */
-+extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
-+#define dwc_le16_to_cpu DWC_LE16_TO_CPU
-+
-+/** Converts 16 bit bi endian data to CPU byte ordering. */
-+extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
-+#define dwc_be16_to_cpu DWC_BE16_TO_CPU
-+
-+
-+/** @name Register Read/Write
-+ *
-+ * The following six functions should be implemented to read/write registers of
-+ * 32-bit and 64-bit sizes. All modules use this to read/write register values.
-+ * The reg value is a pointer to the register calculated from the void *base
-+ * variable passed into the driver when it is started. */
-+
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any extra parameters for register read/write, so we
-+ * just throw away the IO context parameter.
-+ */
-+/** Reads the content of a 32-bit register. */
-+extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
-+#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
-+
-+/** Reads the content of a 64-bit register. */
-+extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
-+#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
-+
-+/** Writes to a 32-bit register. */
-+extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
-+#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
-+
-+/** Writes to a 64-bit register. */
-+extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
-+#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
-+
-+/**
-+ * Modify bit values in a register. Using the
-+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
-+ */
-+extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
-+#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
-+extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
-+#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
-+
-+#endif /* DWC_LINUX */
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+typedef struct dwc_ioctx {
-+ struct device *dev;
-+ bus_space_tag_t iot;
-+ bus_space_handle_t ioh;
-+} dwc_ioctx_t;
-+
-+/** BSD needs two extra parameters for register read/write, so we pass
-+ * them in using the IO context parameter.
-+ */
-+/** Reads the content of a 32-bit register. */
-+extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
-+#define dwc_read_reg32 DWC_READ_REG32
-+
-+/** Reads the content of a 64-bit register. */
-+extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
-+#define dwc_read_reg64 DWC_READ_REG64
-+
-+/** Writes to a 32-bit register. */
-+extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
-+#define dwc_write_reg32 DWC_WRITE_REG32
-+
-+/** Writes to a 64-bit register. */
-+extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
-+#define dwc_write_reg64 DWC_WRITE_REG64
-+
-+/**
-+ * Modify bit values in a register. Using the
-+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
-+ */
-+extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
-+#define dwc_modify_reg32 DWC_MODIFY_REG32
-+extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
-+#define dwc_modify_reg64 DWC_MODIFY_REG64
-+
-+#endif /* DWC_FREEBSD || DWC_NETBSD */
-+
-+/** @cond */
-+
-+/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
-+ * register writes. */
-+
-+#ifdef DWC_LINUX
-+
-+# ifdef DWC_DEBUG_REGS
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
-+ return DWC_READ_REG32(&container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
-+ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
-+ &(((uint32_t*)container->regs->_reg)[num]), data); \
-+ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
-+ return DWC_READ_REG32(&container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
-+ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
-+ DWC_WRITE_REG32(&container->regs->_reg, data); \
-+}
-+
-+# else /* DWC_DEBUG_REGS */
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
-+ return DWC_READ_REG32(&container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
-+ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
-+ return DWC_READ_REG32(&container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
-+ DWC_WRITE_REG32(&container->regs->_reg, data); \
-+}
-+
-+# endif /* DWC_DEBUG_REGS */
-+
-+#endif /* DWC_LINUX */
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+
-+# ifdef DWC_DEBUG_REGS
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
-+ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
-+ &(((uint32_t*)container->regs->_reg)[num]), data); \
-+ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
-+ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
-+ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
-+}
-+
-+# else /* DWC_DEBUG_REGS */
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
-+ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
-+ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
-+}
-+
-+# endif /* DWC_DEBUG_REGS */
-+
-+#endif /* DWC_FREEBSD || DWC_NETBSD */
-+
-+/** @endcond */
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/** @name Crypto Functions
-+ *
-+ * These are the low-level cryptographic functions used by the driver. */
-+
-+/** Perform AES CBC */
-+extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
-+#define dwc_aes_cbc DWC_AES_CBC
-+
-+/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
-+extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
-+#define dwc_random_bytes DWC_RANDOM_BYTES
-+
-+/** Perform the SHA-256 hash function */
-+extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
-+#define dwc_sha256 DWC_SHA256
-+
-+/** Calculated the HMAC-SHA256 */
-+extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
-+#define dwc_hmac_sha256 DWC_HMAC_SHA256
-+
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/** @name Memory Allocation
-+ *
-+ * These function provide access to memory allocation. There are only 2 DMA
-+ * functions and 3 Regular memory functions that need to be implemented. None
-+ * of the memory debugging routines need to be implemented. The allocation
-+ * routines all ZERO the contents of the memory.
-+ *
-+ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
-+ * This checks for memory leaks, keeping track of alloc/free pairs. It also
-+ * keeps track of how much memory the driver is using at any given time. */
-+
-+#define DWC_PAGE_SIZE 4096
-+#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
-+#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
-+
-+#define DWC_INVALID_DMA_ADDR 0x0
-+
-+#ifdef DWC_LINUX
-+/** Type for a DMA address */
-+typedef dma_addr_t dwc_dma_t;
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+typedef bus_addr_t dwc_dma_t;
-+#endif
-+
-+#ifdef DWC_FREEBSD
-+typedef struct dwc_dmactx {
-+ struct device *dev;
-+ bus_dma_tag_t dma_tag;
-+ bus_dmamap_t dma_map;
-+ bus_addr_t dma_paddr;
-+ void *dma_vaddr;
-+} dwc_dmactx_t;
-+#endif
-+
-+#ifdef DWC_NETBSD
-+typedef struct dwc_dmactx {
-+ struct device *dev;
-+ bus_dma_tag_t dma_tag;
-+ bus_dmamap_t dma_map;
-+ bus_dma_segment_t segs[1];
-+ int nsegs;
-+ bus_addr_t dma_paddr;
-+ void *dma_vaddr;
-+} dwc_dmactx_t;
-+#endif
-+
-+/* @todo these functions will be added in the future */
-+#if 0
-+/**
-+ * Creates a DMA pool from which you can allocate DMA buffers. Buffers
-+ * allocated from this pool will be guaranteed to meet the size, alignment, and
-+ * boundary requirements specified.
-+ *
-+ * @param[in] size Specifies the size of the buffers that will be allocated from
-+ * this pool.
-+ * @param[in] align Specifies the byte alignment requirements of the buffers
-+ * allocated from this pool. Must be a power of 2.
-+ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
-+ * this pool must not cross.
-+ *
-+ * @returns A pointer to an internal opaque structure which is not to be
-+ * accessed outside of these library functions. Use this handle to specify
-+ * which pools to allocate/free DMA buffers from and also to destroy the pool,
-+ * when you are done with it.
-+ */
-+extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
-+
-+/**
-+ * Destroy a DMA pool. All buffers allocated from that pool must be freed first.
-+ */
-+extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
-+
-+/**
-+ * Allocate a buffer from the specified DMA pool and zeros its contents.
-+ */
-+extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
-+
-+/**
-+ * Free a previously allocated buffer from the DMA pool.
-+ */
-+extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
-+#endif
-+
-+/** Allocates a DMA capable buffer and zeroes its contents. */
-+extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
-+
-+/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
-+extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
-+
-+/** Frees a previously allocated buffer. */
-+extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
-+
-+/** Allocates a block of memory and zeroes its contents. */
-+extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
-+
-+/** Allocates a block of memory and zeroes its contents, in an atomic manner
-+ * which can be used inside interrupt context. The size should be sufficiently
-+ * small, a few KB at most, such that failures are not likely to occur. Can just call
-+ * __DWC_ALLOC if it is atomic. */
-+extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
-+
-+/** Frees a previously allocated buffer. */
-+extern void __DWC_FREE(void *mem_ctx, void *addr);
-+
-+#ifndef DWC_DEBUG_MEMORY
-+
-+#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
-+#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
-+#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
-+
-+# ifdef DWC_LINUX
-+#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
-+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
-+#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
-+# endif
-+
-+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
-+#define DWC_DMA_FREE __DWC_DMA_FREE
-+# endif
-+extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
-+
-+#else /* DWC_DEBUG_MEMORY */
-+
-+extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
-+extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
-+extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
-+extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+ char const *func, int line);
-+extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+ char const *func, int line);
-+extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
-+ dwc_dma_t dma_addr, char const *func, int line);
-+
-+extern int dwc_memory_debug_start(void *mem_ctx);
-+extern void dwc_memory_debug_stop(void);
-+extern void dwc_memory_debug_report(void);
-+
-+#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
-+#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
-+ __func__, __LINE__)
-+#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
-+
-+# ifdef DWC_LINUX
-+#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \
-+ _dma_, __func__, __LINE__)
-+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \
-+ _dma_, __func__, __LINE__)
-+#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \
-+ _virt_, _dma_, __func__, __LINE__)
-+# endif
-+
-+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
-+ _dma_, __func__, __LINE__)
-+#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
-+ _virt_, _dma_, __func__, __LINE__)
-+# endif
-+
-+#endif /* DWC_DEBUG_MEMORY */
-+
-+#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
-+#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
-+#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
-+
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
-+ * just throw away the DMA context parameter.
-+ */
-+#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
-+#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
-+#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+/** BSD needs several extra parameters for DMA buffer allocation, so we pass
-+ * them in using the DMA context parameter.
-+ */
-+#define dwc_dma_alloc DWC_DMA_ALLOC
-+#define dwc_dma_free DWC_DMA_FREE
-+#endif
-+
-+
-+/** @name Memory and String Processing */
-+
-+/** memset() clone */
-+extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
-+#define dwc_memset DWC_MEMSET
-+
-+/** memcpy() clone */
-+extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
-+#define dwc_memcpy DWC_MEMCPY
-+
-+/** memmove() clone */
-+extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
-+#define dwc_memmove DWC_MEMMOVE
-+
-+/** memcmp() clone */
-+extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
-+#define dwc_memcmp DWC_MEMCMP
-+
-+/** strcmp() clone */
-+extern int DWC_STRCMP(void *s1, void *s2);
-+#define dwc_strcmp DWC_STRCMP
-+
-+/** strncmp() clone */
-+extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
-+#define dwc_strncmp DWC_STRNCMP
-+
-+/** strlen() clone, for NULL terminated ASCII strings */
-+extern int DWC_STRLEN(char const *str);
-+#define dwc_strlen DWC_STRLEN
-+
-+/** strcpy() clone, for NULL terminated ASCII strings */
-+extern char *DWC_STRCPY(char *to, const char *from);
-+#define dwc_strcpy DWC_STRCPY
-+
-+/** strdup() clone. If you wish to use memory allocation debugging, this
-+ * implementation of strdup should use the DWC_* memory routines instead of
-+ * calling a predefined strdup. Otherwise the memory allocated by this routine
-+ * will not be seen by the debugging routines. */
-+extern char *DWC_STRDUP(char const *str);
-+#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
-+
-+/** NOT an atoi() clone. Read the description carefully. Returns an integer
-+ * converted from the string str in base 10 unless the string begins with a "0x"
-+ * in which case it is base 16. String must be a NULL terminated sequence of
-+ * ASCII characters and may optionally begin with whitespace, a + or -, and a
-+ * "0x" prefix if base 16. The remaining characters must be valid digits for
-+ * the number and end with a NULL character. If any invalid characters are
-+ * encountered or it returns with a negative error code and the results of the
-+ * conversion are undefined. On sucess it returns 0. Overflow conditions are
-+ * undefined. An example implementation using atoi() can be referenced from the
-+ * Linux implementation. */
-+extern int DWC_ATOI(const char *str, int32_t *value);
-+#define dwc_atoi DWC_ATOI
-+
-+/** Same as above but for unsigned. */
-+extern int DWC_ATOUI(const char *str, uint32_t *value);
-+#define dwc_atoui DWC_ATOUI
-+
-+#ifdef DWC_UTFLIB
-+/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
-+extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
-+#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
-+#endif
-+
-+
-+/** @name Wait queues
-+ *
-+ * Wait queues provide a means of synchronizing between threads or processes. A
-+ * process can block on a waitq if some condition is not true, waiting for it to
-+ * become true. When the waitq is triggered all waiting process will get
-+ * unblocked and the condition will be check again. Waitqs should be triggered
-+ * every time a condition can potentially change.*/
-+struct dwc_waitq;
-+
-+/** Type for a waitq */
-+typedef struct dwc_waitq dwc_waitq_t;
-+
-+/** The type of waitq condition callback function. This is called every time
-+ * condition is evaluated. */
-+typedef int (*dwc_waitq_condition_t)(void *data);
-+
-+/** Allocate a waitq */
-+extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
-+#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
-+
-+/** Free a waitq */
-+extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
-+#define dwc_waitq_free DWC_WAITQ_FREE
-+
-+/** Check the condition and if it is false, block on the waitq. When unblocked, check the
-+ * condition again. The function returns when the condition becomes true. The return value
-+ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
-+extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
-+#define dwc_waitq_wait DWC_WAITQ_WAIT
-+
-+/** Check the condition and if it is false, block on the waitq. When unblocked,
-+ * check the condition again. The function returns when the condition become
-+ * true or the timeout has passed. The return value is 0 on condition true or
-+ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
-+ * error. */
-+extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs);
-+#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
-+
-+/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
-+ * has potentially changed. */
-+extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
-+#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
-+
-+/** Unblock all processes waiting on the waitq with an ABORTED result. */
-+extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
-+#define dwc_waitq_abort DWC_WAITQ_ABORT
-+
-+
-+/** @name Threads
-+ *
-+ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
-+ * whenever it is woken up, and then return. The DWC_THREAD_STOP function
-+ * returns the value from the thread.
-+ */
-+
-+struct dwc_thread;
-+
-+/** Type for a thread */
-+typedef struct dwc_thread dwc_thread_t;
-+
-+/** The thread function */
-+typedef int (*dwc_thread_function_t)(void *data);
-+
-+/** Create a thread and start it running the thread_function. Returns a handle
-+ * to the thread */
-+extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
-+#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
-+
-+/** Stops a thread. Return the value returned by the thread. Or will return
-+ * DWC_ABORT if the thread never started. */
-+extern int DWC_THREAD_STOP(dwc_thread_t *thread);
-+#define dwc_thread_stop DWC_THREAD_STOP
-+
-+/** Signifies to the thread that it must stop. */
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any parameters for kthread_should_stop() */
-+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
-+#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
-+
-+/* No thread_exit function in Linux */
-+#define dwc_thread_exit(_thrd_)
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+/** BSD needs the thread pointer for kthread_suspend_check() */
-+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
-+#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
-+
-+/** The thread must call this to exit. */
-+extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
-+#define dwc_thread_exit DWC_THREAD_EXIT
-+#endif
-+
-+
-+/** @name Work queues
-+ *
-+ * Workqs are used to queue a callback function to be called at some later time,
-+ * in another thread. */
-+struct dwc_workq;
-+
-+/** Type for a workq */
-+typedef struct dwc_workq dwc_workq_t;
-+
-+/** The type of the callback function to be called. */
-+typedef void (*dwc_work_callback_t)(void *data);
-+
-+/** Allocate a workq */
-+extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
-+#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
-+
-+/** Free a workq. All work must be completed before being freed. */
-+extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
-+#define dwc_workq_free DWC_WORKQ_FREE
-+
-+/** Schedule a callback on the workq, passing in data. The function will be
-+ * scheduled at some later time. */
-+extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
-+ void *data, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 4, 5)));
-+#else
-+ ;
-+#endif
-+#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
-+
-+/** Schedule a callback on the workq, that will be called until at least
-+ * given number miliseconds have passed. */
-+extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 5, 6)));
-+#else
-+ ;
-+#endif
-+#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
-+
-+/** The number of processes in the workq */
-+extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
-+#define dwc_workq_pending DWC_WORKQ_PENDING
-+
-+/** Blocks until all the work in the workq is complete or timed out. Returns <
-+ * 0 on timeout. */
-+extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
-+#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
-+
-+
-+/** @name Tasklets
-+ *
-+ */
-+struct dwc_tasklet;
-+
-+/** Type for a tasklet */
-+typedef struct dwc_tasklet dwc_tasklet_t;
-+
-+/** The type of the callback function to be called */
-+typedef void (*dwc_tasklet_callback_t)(void *data);
-+
-+/** Allocates a tasklet */
-+extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
-+#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
-+
-+/** Frees a tasklet */
-+extern void DWC_TASK_FREE(dwc_tasklet_t *task);
-+#define dwc_task_free DWC_TASK_FREE
-+
-+/** Schedules a tasklet to run */
-+extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
-+#define dwc_task_schedule DWC_TASK_SCHEDULE
-+
-+extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
-+#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
-+
-+/** @name Timer
-+ *
-+ * Callbacks must be small and atomic.
-+ */
-+struct dwc_timer;
-+
-+/** Type for a timer */
-+typedef struct dwc_timer dwc_timer_t;
-+
-+/** The type of the callback function to be called */
-+typedef void (*dwc_timer_callback_t)(void *data);
-+
-+/** Allocates a timer */
-+extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
-+#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
-+
-+/** Frees a timer */
-+extern void DWC_TIMER_FREE(dwc_timer_t *timer);
-+#define dwc_timer_free DWC_TIMER_FREE
-+
-+/** Schedules the timer to run at time ms from now. And will repeat at every
-+ * repeat_interval msec therafter
-+ *
-+ * Modifies a timer that is still awaiting execution to a new expiration time.
-+ * The mod_time is added to the old time. */
-+extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
-+#define dwc_timer_schedule DWC_TIMER_SCHEDULE
-+
-+/** Disables the timer from execution. */
-+extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
-+#define dwc_timer_cancel DWC_TIMER_CANCEL
-+
-+
-+/** @name Spinlocks
-+ *
-+ * These locks are used when the work between the lock/unlock is atomic and
-+ * short. Interrupts are also disabled during the lock/unlock and thus they are
-+ * suitable to lock between interrupt/non-interrupt context. They also lock
-+ * between processes if you have multiple CPUs or Preemption. If you don't have
-+ * multiple CPUS or Preemption, then the you can simply implement the
-+ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
-+ * the work between the lock/unlock is atomic, the process context will never
-+ * change, and so you never have to lock between processes. */
-+
-+struct dwc_spinlock;
-+
-+/** Type for a spinlock */
-+typedef struct dwc_spinlock dwc_spinlock_t;
-+
-+/** Type for the 'flags' argument to spinlock funtions */
-+typedef unsigned long dwc_irqflags_t;
-+
-+/** Returns an initialized lock variable. This function should allocate and
-+ * initialize the OS-specific data structure used for locking. This data
-+ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
-+ * be freed by the DWC_FREE_LOCK when it is no longer used. */
-+extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
-+#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
-+
-+/** Frees an initialized lock variable. */
-+extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
-+#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
-+
-+/** Disables interrupts and blocks until it acquires the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ * @param flags Unsigned long for irq flags storage.
-+ */
-+extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
-+#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
-+
-+/** Re-enables the interrupt and releases the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ * @param flags Unsigned long for irq flags storage. Must be the same as was
-+ * passed into DWC_LOCK.
-+ */
-+extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
-+#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
-+
-+/** Blocks until it acquires the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ */
-+extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
-+#define dwc_spinlock DWC_SPINLOCK
-+
-+/** Releases the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ */
-+extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
-+#define dwc_spinunlock DWC_SPINUNLOCK
-+
-+
-+/** @name Mutexes
-+ *
-+ * Unlike spinlocks Mutexes lock only between processes and the work between the
-+ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
-+ */
-+
-+struct dwc_mutex;
-+
-+/** Type for a mutex */
-+typedef struct dwc_mutex dwc_mutex_t;
-+
-+/* For Linux Mutex Debugging make it inline because the debugging routines use
-+ * the symbol to determine recursive locking. This makes it falsely think
-+ * recursive locking occurs. */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
-+#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
-+ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
-+ mutex_init((struct mutex *)__mutexp); \
-+})
-+#endif
-+
-+/** Allocate a mutex */
-+extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
-+#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
-+
-+/* For memory leak debugging when using Linux Mutex Debugging */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
-+#define DWC_MUTEX_FREE(__mutexp) do { \
-+ mutex_destroy((struct mutex *)__mutexp); \
-+ DWC_FREE(__mutexp); \
-+} while(0)
-+#else
-+/** Free a mutex */
-+extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
-+#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
-+#endif
-+
-+/** Lock a mutex */
-+extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_lock DWC_MUTEX_LOCK
-+
-+/** Non-blocking lock returns 1 on successful lock. */
-+extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
-+
-+/** Unlock a mutex */
-+extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
-+
-+
-+/** @name Time */
-+
-+/** Microsecond delay.
-+ *
-+ * @param usecs Microseconds to delay.
-+ */
-+extern void DWC_UDELAY(uint32_t usecs);
-+#define dwc_udelay DWC_UDELAY
-+
-+/** Millisecond delay.
-+ *
-+ * @param msecs Milliseconds to delay.
-+ */
-+extern void DWC_MDELAY(uint32_t msecs);
-+#define dwc_mdelay DWC_MDELAY
-+
-+/** Non-busy waiting.
-+ * Sleeps for specified number of milliseconds.
-+ *
-+ * @param msecs Milliseconds to sleep.
-+ */
-+extern void DWC_MSLEEP(uint32_t msecs);
-+#define dwc_msleep DWC_MSLEEP
-+
-+/**
-+ * Returns number of milliseconds since boot.
-+ */
-+extern uint32_t DWC_TIME(void);
-+#define dwc_time DWC_TIME
-+
-+
-+
-+
-+/* @mainpage DWC Portability and Common Library
-+ *
-+ * This is the documentation for the DWC Portability and Common Library.
-+ *
-+ * @section intro Introduction
-+ *
-+ * The DWC Portability library consists of wrapper calls and data structures to
-+ * all low-level functions which are typically provided by the OS. The WUDEV
-+ * driver uses only these functions. In order to port the WUDEV driver, only
-+ * the functions in this library need to be re-implemented, with the same
-+ * behavior as documented here.
-+ *
-+ * The Common library consists of higher level functions, which rely only on
-+ * calling the functions from the DWC Portability library. These common
-+ * routines are shared across modules. Some of the common libraries need to be
-+ * used directly by the driver programmer when porting WUDEV. Such as the
-+ * parameter and notification libraries.
-+ *
-+ * @section low Portability Library OS Wrapper Functions
-+ *
-+ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
-+ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
-+ * these functions are included in the dwc_os.h file.
-+ *
-+ * There are many functions here covering a wide array of OS services. Please
-+ * see dwc_os.h for details, and implementation notes for each function.
-+ *
-+ * @section common Common Library Functions
-+ *
-+ * Any function starting with dwc and in all lowercase is a common library
-+ * routine. These functions have a portable implementation and do not need to
-+ * be reimplemented when porting. The common routines can be used by any
-+ * driver, and some must be used by the end user to control the drivers. For
-+ * example, you must use the Parameter common library in order to set the
-+ * parameters in the WUDEV module.
-+ *
-+ * The common libraries consist of the following:
-+ *
-+ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
-+ * - Parameters - Used internally and can be used by end-user. See dwc_params.h
-+ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
-+ * - Lists - Used internally and can be used by end-user. See dwc_list.h
-+ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
-+ * - Modpow - Used internally only. See dwc_modpow.h
-+ * - DH - Used internally only. See dwc_dh.h
-+ * - Crypto - Used internally only. See dwc_crypto.h
-+ *
-+ *
-+ * @section prereq Prerequistes For dwc_os.h
-+ * @subsection types Data Types
-+ *
-+ * The dwc_os.h file assumes that several low-level data types are pre defined for the
-+ * compilation environment. These data types are:
-+ *
-+ * - uint8_t - unsigned 8-bit data type
-+ * - int8_t - signed 8-bit data type
-+ * - uint16_t - unsigned 16-bit data type
-+ * - int16_t - signed 16-bit data type
-+ * - uint32_t - unsigned 32-bit data type
-+ * - int32_t - signed 32-bit data type
-+ * - uint64_t - unsigned 64-bit data type
-+ * - int64_t - signed 64-bit data type
-+ *
-+ * Ensure that these are defined before using dwc_os.h. The easiest way to do
-+ * that is to modify the top of the file to include the appropriate header.
-+ * This is already done for the Linux environment. If the DWC_LINUX macro is
-+ * defined, the correct header will be added. A standard header <stdint.h> is
-+ * also used for environments where standard C headers are available.
-+ *
-+ * @subsection stdarg Variable Arguments
-+ *
-+ * Variable arguments are provided by a standard C header <stdarg.h>. it is
-+ * available in Both the Linux and ANSI C enviornment. An equivalent must be
-+ * provided in your enviornment in order to use dwc_os.h with the debug and
-+ * tracing message functionality.
-+ *
-+ * @subsection thread Threading
-+ *
-+ * WUDEV Core must be run on an operating system that provides for multiple
-+ * threads/processes. Threading can be implemented in many ways, even in
-+ * embedded systems without an operating system. At the bare minimum, the
-+ * system should be able to start any number of processes at any time to handle
-+ * special work. It need not be a pre-emptive system. Process context can
-+ * change upon a call to a blocking function. The hardware interrupt context
-+ * that calls the module's ISR() function must be differentiable from process
-+ * context, even if your processes are impemented via a hardware interrupt.
-+ * Further locking mechanism between process must exist (or be implemented), and
-+ * process context must have a way to disable interrupts for a period of time to
-+ * lock them out. If all of this exists, the functions in dwc_os.h related to
-+ * threading should be able to be implemented with the defined behavior.
-+ *
-+ */
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_OS_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/Makefile linux-rpi/drivers/usb/host/dwc_common_port/Makefile
---- linux-3.12.38/drivers/usb/host/dwc_common_port/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,58 @@
-+#
-+# Makefile for DWC_common library
-+#
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+ccflags-y += -DDWC_LINUX
-+#ccflags-y += -DDEBUG
-+#ccflags-y += -DDWC_DEBUG_REGS
-+#ccflags-y += -DDWC_DEBUG_MEMORY
-+
-+ccflags-y += -DDWC_LIBMODULE
-+ccflags-y += -DDWC_CCLIB
-+#ccflags-y += -DDWC_CRYPTOLIB
-+ccflags-y += -DDWC_NOTIFYLIB
-+ccflags-y += -DDWC_UTFLIB
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o
-+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
-+ dwc_crypto.o dwc_notifier.o \
-+ dwc_common_linux.o dwc_mem.o
-+
-+kernrelwd := $(subst ., ,$(KERNELRELEASE))
-+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
-+
-+ifneq ($(kernrel3),2.6.20)
-+# grayg - I only know that we use ccflags-y in 2.6.31 actually
-+ccflags-y += $(CPPFLAGS)
-+endif
-+
-+else
-+
-+#ifeq ($(KDIR),)
-+#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
-+#endif
-+
-+ifeq ($(ARCH),)
-+$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
-+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
-+endif
-+
-+ifeq ($(DOXYGEN),)
-+DOXYGEN := doxygen
-+endif
-+
-+default:
-+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+docs: $(wildcard *.[hc]) doc/doxygen.cfg
-+ $(DOXYGEN) doc/doxygen.cfg
-+
-+tags: $(wildcard *.[hc])
-+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+endif
-+
-+clean:
-+ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/Makefile.fbsd linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd
---- linux-3.12.38/drivers/usb/host/dwc_common_port/Makefile.fbsd 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,17 @@
-+CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
-+CFLAGS += -DDWC_FREEBSD
-+CFLAGS += -DDEBUG
-+#CFLAGS += -DDWC_DEBUG_REGS
-+#CFLAGS += -DDWC_DEBUG_MEMORY
-+
-+#CFLAGS += -DDWC_LIBMODULE
-+#CFLAGS += -DDWC_CCLIB
-+#CFLAGS += -DDWC_CRYPTOLIB
-+#CFLAGS += -DDWC_NOTIFYLIB
-+#CFLAGS += -DDWC_UTFLIB
-+
-+KMOD = dwc_common_port_lib
-+SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
-+ dwc_common_fbsd.c dwc_mem.c
-+
-+.include <bsd.kmod.mk>
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/Makefile.linux linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux
---- linux-3.12.38/drivers/usb/host/dwc_common_port/Makefile.linux 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,49 @@
-+#
-+# Makefile for DWC_common library
-+#
-+ifneq ($(KERNELRELEASE),)
-+
-+ccflags-y += -DDWC_LINUX
-+#ccflags-y += -DDEBUG
-+#ccflags-y += -DDWC_DEBUG_REGS
-+#ccflags-y += -DDWC_DEBUG_MEMORY
-+
-+ccflags-y += -DDWC_LIBMODULE
-+ccflags-y += -DDWC_CCLIB
-+ccflags-y += -DDWC_CRYPTOLIB
-+ccflags-y += -DDWC_NOTIFYLIB
-+ccflags-y += -DDWC_UTFLIB
-+
-+obj-m := dwc_common_port_lib.o
-+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
-+ dwc_crypto.o dwc_notifier.o \
-+ dwc_common_linux.o dwc_mem.o
-+
-+else
-+
-+ifeq ($(KDIR),)
-+$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
-+endif
-+
-+ifeq ($(ARCH),)
-+$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
-+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
-+endif
-+
-+ifeq ($(DOXYGEN),)
-+DOXYGEN := doxygen
-+endif
-+
-+default:
-+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+docs: $(wildcard *.[hc]) doc/doxygen.cfg
-+ $(DOXYGEN) doc/doxygen.cfg
-+
-+tags: $(wildcard *.[hc])
-+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+endif
-+
-+clean:
-+ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_common_port/usb.h linux-rpi/drivers/usb/host/dwc_common_port/usb.h
---- linux-3.12.38/drivers/usb/host/dwc_common_port/usb.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_common_port/usb.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,946 @@
-+/*
-+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
-+ * All rights reserved.
-+ *
-+ * This code is derived from software contributed to The NetBSD Foundation
-+ * by Lennart Augustsson (lennart@augustsson.net) at
-+ * Carlstedt Research & Technology.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. All advertising materials mentioning features or use of this software
-+ * must display the following acknowledgement:
-+ * This product includes software developed by the NetBSD
-+ * Foundation, Inc. and its contributors.
-+ * 4. Neither the name of The NetBSD Foundation nor the names of its
-+ * contributors may be used to endorse or promote products derived
-+ * from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
-+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
-+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+/* Modified by Synopsys, Inc, 12/12/2007 */
-+
-+
-+#ifndef _USB_H_
-+#define _USB_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/*
-+ * The USB records contain some unaligned little-endian word
-+ * components. The U[SG]ETW macros take care of both the alignment
-+ * and endian problem and should always be used to access non-byte
-+ * values.
-+ */
-+typedef u_int8_t uByte;
-+typedef u_int8_t uWord[2];
-+typedef u_int8_t uDWord[4];
-+
-+#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
-+#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff }
-+#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \
-+ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
-+
-+#if 1
-+#define UGETW(w) ((w)[0] | ((w)[1] << 8))
-+#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
-+#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
-+#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
-+ (w)[1] = (u_int8_t)((v) >> 8), \
-+ (w)[2] = (u_int8_t)((v) >> 16), \
-+ (w)[3] = (u_int8_t)((v) >> 24))
-+#else
-+/*
-+ * On little-endian machines that can handle unanliged accesses
-+ * (e.g. i386) these macros can be replaced by the following.
-+ */
-+#define UGETW(w) (*(u_int16_t *)(w))
-+#define USETW(w,v) (*(u_int16_t *)(w) = (v))
-+#define UGETDW(w) (*(u_int32_t *)(w))
-+#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
-+#endif
-+
-+/*
-+ * Macros for accessing UAS IU fields, which are big-endian
-+ */
-+#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
-+#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff }
-+#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
-+ ((x) >> 8) & 0xff, (x) & 0xff }
-+#define IUGETW(w) (((w)[0] << 8) | (w)[1])
-+#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
-+#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
-+#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
-+ (w)[1] = (u_int8_t)((v) >> 16), \
-+ (w)[2] = (u_int8_t)((v) >> 8), \
-+ (w)[3] = (u_int8_t)(v))
-+
-+#define UPACKED __attribute__((__packed__))
-+
-+typedef struct {
-+ uByte bmRequestType;
-+ uByte bRequest;
-+ uWord wValue;
-+ uWord wIndex;
-+ uWord wLength;
-+} UPACKED usb_device_request_t;
-+
-+#define UT_GET_DIR(a) ((a) & 0x80)
-+#define UT_WRITE 0x00
-+#define UT_READ 0x80
-+
-+#define UT_GET_TYPE(a) ((a) & 0x60)
-+#define UT_STANDARD 0x00
-+#define UT_CLASS 0x20
-+#define UT_VENDOR 0x40
-+
-+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
-+#define UT_DEVICE 0x00
-+#define UT_INTERFACE 0x01
-+#define UT_ENDPOINT 0x02
-+#define UT_OTHER 0x03
-+
-+#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE)
-+#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE)
-+#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT)
-+#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE)
-+#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE)
-+#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
-+#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE)
-+#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE)
-+#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER)
-+#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT)
-+#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE)
-+#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
-+#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER)
-+#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT)
-+#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE)
-+#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE)
-+#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER)
-+#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT)
-+#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
-+#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
-+#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER)
-+#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
-+
-+/* Requests */
-+#define UR_GET_STATUS 0x00
-+#define USTAT_STANDARD_STATUS 0x00
-+#define WUSTAT_WUSB_FEATURE 0x01
-+#define WUSTAT_CHANNEL_INFO 0x02
-+#define WUSTAT_RECEIVED_DATA 0x03
-+#define WUSTAT_MAS_AVAILABILITY 0x04
-+#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05
-+#define UR_CLEAR_FEATURE 0x01
-+#define UR_SET_FEATURE 0x03
-+#define UR_SET_AND_TEST_FEATURE 0x0c
-+#define UR_SET_ADDRESS 0x05
-+#define UR_GET_DESCRIPTOR 0x06
-+#define UDESC_DEVICE 0x01
-+#define UDESC_CONFIG 0x02
-+#define UDESC_STRING 0x03
-+#define UDESC_INTERFACE 0x04
-+#define UDESC_ENDPOINT 0x05
-+#define UDESC_SS_USB_COMPANION 0x30
-+#define UDESC_DEVICE_QUALIFIER 0x06
-+#define UDESC_OTHER_SPEED_CONFIGURATION 0x07
-+#define UDESC_INTERFACE_POWER 0x08
-+#define UDESC_OTG 0x09
-+#define WUDESC_SECURITY 0x0c
-+#define WUDESC_KEY 0x0d
-+#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
-+#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
-+#define WUD_KEY_TYPE_ASSOC 0x01
-+#define WUD_KEY_TYPE_GTK 0x02
-+#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
-+#define WUD_KEY_ORIGIN_HOST 0x00
-+#define WUD_KEY_ORIGIN_DEVICE 0x01
-+#define WUDESC_ENCRYPTION_TYPE 0x0e
-+#define WUDESC_BOS 0x0f
-+#define WUDESC_DEVICE_CAPABILITY 0x10
-+#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
-+#define UDESC_BOS 0x0f
-+#define UDESC_DEVICE_CAPABILITY 0x10
-+#define UDESC_CS_DEVICE 0x21 /* class specific */
-+#define UDESC_CS_CONFIG 0x22
-+#define UDESC_CS_STRING 0x23
-+#define UDESC_CS_INTERFACE 0x24
-+#define UDESC_CS_ENDPOINT 0x25
-+#define UDESC_HUB 0x29
-+#define UR_SET_DESCRIPTOR 0x07
-+#define UR_GET_CONFIG 0x08
-+#define UR_SET_CONFIG 0x09
-+#define UR_GET_INTERFACE 0x0a
-+#define UR_SET_INTERFACE 0x0b
-+#define UR_SYNCH_FRAME 0x0c
-+#define WUR_SET_ENCRYPTION 0x0d
-+#define WUR_GET_ENCRYPTION 0x0e
-+#define WUR_SET_HANDSHAKE 0x0f
-+#define WUR_GET_HANDSHAKE 0x10
-+#define WUR_SET_CONNECTION 0x11
-+#define WUR_SET_SECURITY_DATA 0x12
-+#define WUR_GET_SECURITY_DATA 0x13
-+#define WUR_SET_WUSB_DATA 0x14
-+#define WUDATA_DRPIE_INFO 0x01
-+#define WUDATA_TRANSMIT_DATA 0x02
-+#define WUDATA_TRANSMIT_PARAMS 0x03
-+#define WUDATA_RECEIVE_PARAMS 0x04
-+#define WUDATA_TRANSMIT_POWER 0x05
-+#define WUR_LOOPBACK_DATA_WRITE 0x15
-+#define WUR_LOOPBACK_DATA_READ 0x16
-+#define WUR_SET_INTERFACE_DS 0x17
-+
-+/* Feature numbers */
-+#define UF_ENDPOINT_HALT 0
-+#define UF_DEVICE_REMOTE_WAKEUP 1
-+#define UF_TEST_MODE 2
-+#define UF_DEVICE_B_HNP_ENABLE 3
-+#define UF_DEVICE_A_HNP_SUPPORT 4
-+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
-+#define WUF_WUSB 3
-+#define WUF_TX_DRPIE 0x0
-+#define WUF_DEV_XMIT_PACKET 0x1
-+#define WUF_COUNT_PACKETS 0x2
-+#define WUF_CAPTURE_PACKETS 0x3
-+#define UF_FUNCTION_SUSPEND 0
-+#define UF_U1_ENABLE 48
-+#define UF_U2_ENABLE 49
-+#define UF_LTM_ENABLE 50
-+
-+/* Class requests from the USB 2.0 hub spec, table 11-15 */
-+#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE)
-+#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE)
-+#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR)
-+#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS)
-+#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS)
-+#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE)
-+#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE)
-+#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE)
-+
-+#ifdef _MSC_VER
-+#include <pshpack1.h>
-+#endif
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDescriptorSubtype;
-+} UPACKED usb_descriptor_t;
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+} UPACKED usb_descriptor_header_t;
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord bcdUSB;
-+#define UD_USB_2_0 0x0200
-+#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
-+ uByte bDeviceClass;
-+ uByte bDeviceSubClass;
-+ uByte bDeviceProtocol;
-+ uByte bMaxPacketSize;
-+ /* The fields below are not part of the initial descriptor. */
-+ uWord idVendor;
-+ uWord idProduct;
-+ uWord bcdDevice;
-+ uByte iManufacturer;
-+ uByte iProduct;
-+ uByte iSerialNumber;
-+ uByte bNumConfigurations;
-+} UPACKED usb_device_descriptor_t;
-+#define USB_DEVICE_DESCRIPTOR_SIZE 18
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord wTotalLength;
-+ uByte bNumInterface;
-+ uByte bConfigurationValue;
-+ uByte iConfiguration;
-+#define UC_ATT_ONE (1 << 7) /* must be set */
-+#define UC_ATT_SELFPOWER (1 << 6) /* self powered */
-+#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */
-+#define UC_ATT_BATTERY (1 << 4) /* battery powered */
-+ uByte bmAttributes;
-+#define UC_BUS_POWERED 0x80
-+#define UC_SELF_POWERED 0x40
-+#define UC_REMOTE_WAKEUP 0x20
-+ uByte bMaxPower; /* max current in 2 mA units */
-+#define UC_POWER_FACTOR 2
-+} UPACKED usb_config_descriptor_t;
-+#define USB_CONFIG_DESCRIPTOR_SIZE 9
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bInterfaceNumber;
-+ uByte bAlternateSetting;
-+ uByte bNumEndpoints;
-+ uByte bInterfaceClass;
-+ uByte bInterfaceSubClass;
-+ uByte bInterfaceProtocol;
-+ uByte iInterface;
-+} UPACKED usb_interface_descriptor_t;
-+#define USB_INTERFACE_DESCRIPTOR_SIZE 9
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bEndpointAddress;
-+#define UE_GET_DIR(a) ((a) & 0x80)
-+#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
-+#define UE_DIR_IN 0x80
-+#define UE_DIR_OUT 0x00
-+#define UE_ADDR 0x0f
-+#define UE_GET_ADDR(a) ((a) & UE_ADDR)
-+ uByte bmAttributes;
-+#define UE_XFERTYPE 0x03
-+#define UE_CONTROL 0x00
-+#define UE_ISOCHRONOUS 0x01
-+#define UE_BULK 0x02
-+#define UE_INTERRUPT 0x03
-+#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE)
-+#define UE_ISO_TYPE 0x0c
-+#define UE_ISO_ASYNC 0x04
-+#define UE_ISO_ADAPT 0x08
-+#define UE_ISO_SYNC 0x0c
-+#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE)
-+ uWord wMaxPacketSize;
-+ uByte bInterval;
-+} UPACKED usb_endpoint_descriptor_t;
-+#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
-+
-+typedef struct ss_endpoint_companion_descriptor {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bMaxBurst;
-+#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f)
-+#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f))
-+#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03)
-+#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03))
-+ uByte bmAttributes;
-+ uWord wBytesPerInterval;
-+} UPACKED ss_endpoint_companion_descriptor_t;
-+#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord bString[127];
-+} UPACKED usb_string_descriptor_t;
-+#define USB_MAX_STRING_LEN 128
-+#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
-+
-+/* Hub specific request */
-+#define UR_GET_BUS_STATE 0x02
-+#define UR_CLEAR_TT_BUFFER 0x08
-+#define UR_RESET_TT 0x09
-+#define UR_GET_TT_STATE 0x0a
-+#define UR_STOP_TT 0x0b
-+
-+/* Hub features */
-+#define UHF_C_HUB_LOCAL_POWER 0
-+#define UHF_C_HUB_OVER_CURRENT 1
-+#define UHF_PORT_CONNECTION 0
-+#define UHF_PORT_ENABLE 1
-+#define UHF_PORT_SUSPEND 2
-+#define UHF_PORT_OVER_CURRENT 3
-+#define UHF_PORT_RESET 4
-+#define UHF_PORT_L1 5
-+#define UHF_PORT_POWER 8
-+#define UHF_PORT_LOW_SPEED 9
-+#define UHF_PORT_HIGH_SPEED 10
-+#define UHF_C_PORT_CONNECTION 16
-+#define UHF_C_PORT_ENABLE 17
-+#define UHF_C_PORT_SUSPEND 18
-+#define UHF_C_PORT_OVER_CURRENT 19
-+#define UHF_C_PORT_RESET 20
-+#define UHF_C_PORT_L1 23
-+#define UHF_PORT_TEST 21
-+#define UHF_PORT_INDICATOR 22
-+
-+typedef struct {
-+ uByte bDescLength;
-+ uByte bDescriptorType;
-+ uByte bNbrPorts;
-+ uWord wHubCharacteristics;
-+#define UHD_PWR 0x0003
-+#define UHD_PWR_GANGED 0x0000
-+#define UHD_PWR_INDIVIDUAL 0x0001
-+#define UHD_PWR_NO_SWITCH 0x0002
-+#define UHD_COMPOUND 0x0004
-+#define UHD_OC 0x0018
-+#define UHD_OC_GLOBAL 0x0000
-+#define UHD_OC_INDIVIDUAL 0x0008
-+#define UHD_OC_NONE 0x0010
-+#define UHD_TT_THINK 0x0060
-+#define UHD_TT_THINK_8 0x0000
-+#define UHD_TT_THINK_16 0x0020
-+#define UHD_TT_THINK_24 0x0040
-+#define UHD_TT_THINK_32 0x0060
-+#define UHD_PORT_IND 0x0080
-+ uByte bPwrOn2PwrGood; /* delay in 2 ms units */
-+#define UHD_PWRON_FACTOR 2
-+ uByte bHubContrCurrent;
-+ uByte DeviceRemovable[32]; /* max 255 ports */
-+#define UHD_NOT_REMOV(desc, i) \
-+ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
-+ /* deprecated */ uByte PortPowerCtrlMask[1];
-+} UPACKED usb_hub_descriptor_t;
-+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord bcdUSB;
-+ uByte bDeviceClass;
-+ uByte bDeviceSubClass;
-+ uByte bDeviceProtocol;
-+ uByte bMaxPacketSize0;
-+ uByte bNumConfigurations;
-+ uByte bReserved;
-+} UPACKED usb_device_qualifier_t;
-+#define USB_DEVICE_QUALIFIER_SIZE 10
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bmAttributes;
-+#define UOTG_SRP 0x01
-+#define UOTG_HNP 0x02
-+} UPACKED usb_otg_descriptor_t;
-+
-+/* OTG feature selectors */
-+#define UOTG_B_HNP_ENABLE 3
-+#define UOTG_A_HNP_SUPPORT 4
-+#define UOTG_A_ALT_HNP_SUPPORT 5
-+
-+typedef struct {
-+ uWord wStatus;
-+/* Device status flags */
-+#define UDS_SELF_POWERED 0x0001
-+#define UDS_REMOTE_WAKEUP 0x0002
-+/* Endpoint status flags */
-+#define UES_HALT 0x0001
-+} UPACKED usb_status_t;
-+
-+typedef struct {
-+ uWord wHubStatus;
-+#define UHS_LOCAL_POWER 0x0001
-+#define UHS_OVER_CURRENT 0x0002
-+ uWord wHubChange;
-+} UPACKED usb_hub_status_t;
-+
-+typedef struct {
-+ uWord wPortStatus;
-+#define UPS_CURRENT_CONNECT_STATUS 0x0001
-+#define UPS_PORT_ENABLED 0x0002
-+#define UPS_SUSPEND 0x0004
-+#define UPS_OVERCURRENT_INDICATOR 0x0008
-+#define UPS_RESET 0x0010
-+#define UPS_PORT_POWER 0x0100
-+#define UPS_LOW_SPEED 0x0200
-+#define UPS_HIGH_SPEED 0x0400
-+#define UPS_PORT_TEST 0x0800
-+#define UPS_PORT_INDICATOR 0x1000
-+ uWord wPortChange;
-+#define UPS_C_CONNECT_STATUS 0x0001
-+#define UPS_C_PORT_ENABLED 0x0002
-+#define UPS_C_SUSPEND 0x0004
-+#define UPS_C_OVERCURRENT_INDICATOR 0x0008
-+#define UPS_C_PORT_RESET 0x0010
-+} UPACKED usb_port_status_t;
-+
-+#ifdef _MSC_VER
-+#include <poppack.h>
-+#endif
-+
-+/* Device class codes */
-+#define UDCLASS_IN_INTERFACE 0x00
-+#define UDCLASS_COMM 0x02
-+#define UDCLASS_HUB 0x09
-+#define UDSUBCLASS_HUB 0x00
-+#define UDPROTO_FSHUB 0x00
-+#define UDPROTO_HSHUBSTT 0x01
-+#define UDPROTO_HSHUBMTT 0x02
-+#define UDCLASS_DIAGNOSTIC 0xdc
-+#define UDCLASS_WIRELESS 0xe0
-+#define UDSUBCLASS_RF 0x01
-+#define UDPROTO_BLUETOOTH 0x01
-+#define UDCLASS_VENDOR 0xff
-+
-+/* Interface class codes */
-+#define UICLASS_UNSPEC 0x00
-+
-+#define UICLASS_AUDIO 0x01
-+#define UISUBCLASS_AUDIOCONTROL 1
-+#define UISUBCLASS_AUDIOSTREAM 2
-+#define UISUBCLASS_MIDISTREAM 3
-+
-+#define UICLASS_CDC 0x02 /* communication */
-+#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
-+#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
-+#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
-+#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
-+#define UISUBCLASS_CAPI_CONTROLMODEL 5
-+#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
-+#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
-+#define UIPROTO_CDC_AT 1
-+
-+#define UICLASS_HID 0x03
-+#define UISUBCLASS_BOOT 1
-+#define UIPROTO_BOOT_KEYBOARD 1
-+
-+#define UICLASS_PHYSICAL 0x05
-+
-+#define UICLASS_IMAGE 0x06
-+
-+#define UICLASS_PRINTER 0x07
-+#define UISUBCLASS_PRINTER 1
-+#define UIPROTO_PRINTER_UNI 1
-+#define UIPROTO_PRINTER_BI 2
-+#define UIPROTO_PRINTER_1284 3
-+
-+#define UICLASS_MASS 0x08
-+#define UISUBCLASS_RBC 1
-+#define UISUBCLASS_SFF8020I 2
-+#define UISUBCLASS_QIC157 3
-+#define UISUBCLASS_UFI 4
-+#define UISUBCLASS_SFF8070I 5
-+#define UISUBCLASS_SCSI 6
-+#define UIPROTO_MASS_CBI_I 0
-+#define UIPROTO_MASS_CBI 1
-+#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
-+#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
-+
-+#define UICLASS_HUB 0x09
-+#define UISUBCLASS_HUB 0
-+#define UIPROTO_FSHUB 0
-+#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
-+#define UIPROTO_HSHUBMTT 1
-+
-+#define UICLASS_CDC_DATA 0x0a
-+#define UISUBCLASS_DATA 0
-+#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
-+#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
-+#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
-+#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
-+#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
-+#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
-+#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
-+#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
-+#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
-+#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
-+#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
-+#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
-+#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
-+
-+#define UICLASS_SMARTCARD 0x0b
-+
-+/*#define UICLASS_FIRM_UPD 0x0c*/
-+
-+#define UICLASS_SECURITY 0x0d
-+
-+#define UICLASS_DIAGNOSTIC 0xdc
-+
-+#define UICLASS_WIRELESS 0xe0
-+#define UISUBCLASS_RF 0x01
-+#define UIPROTO_BLUETOOTH 0x01
-+
-+#define UICLASS_APPL_SPEC 0xfe
-+#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
-+#define UISUBCLASS_IRDA 2
-+#define UIPROTO_IRDA 0
-+
-+#define UICLASS_VENDOR 0xff
-+
-+#define USB_HUB_MAX_DEPTH 5
-+
-+/*
-+ * Minimum time a device needs to be powered down to go through
-+ * a power cycle. XXX Are these time in the spec?
-+ */
-+#define USB_POWER_DOWN_TIME 200 /* ms */
-+#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
-+
-+#if 0
-+/* These are the values from the spec. */
-+#define USB_PORT_RESET_DELAY 10 /* ms */
-+#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */
-+#define USB_PORT_RESET_RECOVERY 10 /* ms */
-+#define USB_PORT_POWERUP_DELAY 100 /* ms */
-+#define USB_SET_ADDRESS_SETTLE 2 /* ms */
-+#define USB_RESUME_DELAY (20*5) /* ms */
-+#define USB_RESUME_WAIT 10 /* ms */
-+#define USB_RESUME_RECOVERY 10 /* ms */
-+#define USB_EXTRA_POWER_UP_TIME 0 /* ms */
-+#else
-+/* Allow for marginal (i.e. non-conforming) devices. */
-+#define USB_PORT_RESET_DELAY 50 /* ms */
-+#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
-+#define USB_PORT_RESET_RECOVERY 250 /* ms */
-+#define USB_PORT_POWERUP_DELAY 300 /* ms */
-+#define USB_SET_ADDRESS_SETTLE 10 /* ms */
-+#define USB_RESUME_DELAY (50*5) /* ms */
-+#define USB_RESUME_WAIT 50 /* ms */
-+#define USB_RESUME_RECOVERY 50 /* ms */
-+#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
-+#endif
-+
-+#define USB_MIN_POWER 100 /* mA */
-+#define USB_MAX_POWER 500 /* mA */
-+
-+#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
-+
-+#define USB_UNCONFIG_NO 0
-+#define USB_UNCONFIG_INDEX (-1)
-+
-+/*** ioctl() related stuff ***/
-+
-+struct usb_ctl_request {
-+ int ucr_addr;
-+ usb_device_request_t ucr_request;
-+ void *ucr_data;
-+ int ucr_flags;
-+#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
-+ int ucr_actlen; /* actual length transferred */
-+};
-+
-+struct usb_alt_interface {
-+ int uai_config_index;
-+ int uai_interface_index;
-+ int uai_alt_no;
-+};
-+
-+#define USB_CURRENT_CONFIG_INDEX (-1)
-+#define USB_CURRENT_ALT_INDEX (-1)
-+
-+struct usb_config_desc {
-+ int ucd_config_index;
-+ usb_config_descriptor_t ucd_desc;
-+};
-+
-+struct usb_interface_desc {
-+ int uid_config_index;
-+ int uid_interface_index;
-+ int uid_alt_index;
-+ usb_interface_descriptor_t uid_desc;
-+};
-+
-+struct usb_endpoint_desc {
-+ int ued_config_index;
-+ int ued_interface_index;
-+ int ued_alt_index;
-+ int ued_endpoint_index;
-+ usb_endpoint_descriptor_t ued_desc;
-+};
-+
-+struct usb_full_desc {
-+ int ufd_config_index;
-+ u_int ufd_size;
-+ u_char *ufd_data;
-+};
-+
-+struct usb_string_desc {
-+ int usd_string_index;
-+ int usd_language_id;
-+ usb_string_descriptor_t usd_desc;
-+};
-+
-+struct usb_ctl_report_desc {
-+ int ucrd_size;
-+ u_char ucrd_data[1024]; /* filled data size will vary */
-+};
-+
-+typedef struct { u_int32_t cookie; } usb_event_cookie_t;
-+
-+#define USB_MAX_DEVNAMES 4
-+#define USB_MAX_DEVNAMELEN 16
-+struct usb_device_info {
-+ u_int8_t udi_bus;
-+ u_int8_t udi_addr; /* device address */
-+ usb_event_cookie_t udi_cookie;
-+ char udi_product[USB_MAX_STRING_LEN];
-+ char udi_vendor[USB_MAX_STRING_LEN];
-+ char udi_release[8];
-+ u_int16_t udi_productNo;
-+ u_int16_t udi_vendorNo;
-+ u_int16_t udi_releaseNo;
-+ u_int8_t udi_class;
-+ u_int8_t udi_subclass;
-+ u_int8_t udi_protocol;
-+ u_int8_t udi_config;
-+ u_int8_t udi_speed;
-+#define USB_SPEED_UNKNOWN 0
-+#define USB_SPEED_LOW 1
-+#define USB_SPEED_FULL 2
-+#define USB_SPEED_HIGH 3
-+#define USB_SPEED_VARIABLE 4
-+#define USB_SPEED_SUPER 5
-+ int udi_power; /* power consumption in mA, 0 if selfpowered */
-+ int udi_nports;
-+ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
-+ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */
-+#define USB_PORT_ENABLED 0xff
-+#define USB_PORT_SUSPENDED 0xfe
-+#define USB_PORT_POWERED 0xfd
-+#define USB_PORT_DISABLED 0xfc
-+};
-+
-+struct usb_ctl_report {
-+ int ucr_report;
-+ u_char ucr_data[1024]; /* filled data size will vary */
-+};
-+
-+struct usb_device_stats {
-+ u_long uds_requests[4]; /* indexed by transfer type UE_* */
-+};
-+
-+#define WUSB_MIN_IE 0x80
-+#define WUSB_WCTA_IE 0x80
-+#define WUSB_WCONNECTACK_IE 0x81
-+#define WUSB_WHOSTINFO_IE 0x82
-+#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
-+#define WUHI_CA_RECONN 0x00
-+#define WUHI_CA_LIMITED 0x01
-+#define WUHI_CA_ALL 0x03
-+#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
-+#define WUSB_WCHCHANGEANNOUNCE_IE 0x83
-+#define WUSB_WDEV_DISCONNECT_IE 0x84
-+#define WUSB_WHOST_DISCONNECT_IE 0x85
-+#define WUSB_WRELEASE_CHANNEL_IE 0x86
-+#define WUSB_WWORK_IE 0x87
-+#define WUSB_WCHANNEL_STOP_IE 0x88
-+#define WUSB_WDEV_KEEPALIVE_IE 0x89
-+#define WUSB_WISOCH_DISCARD_IE 0x8A
-+#define WUSB_WRESETDEVICE_IE 0x8B
-+#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C
-+#define WUSB_MAX_IE 0x8C
-+
-+/* Device Notification Types */
-+
-+#define WUSB_DN_MIN 0x01
-+#define WUSB_DN_CONNECT 0x01
-+# define WUSB_DA_OLDCONN 0x00
-+# define WUSB_DA_NEWCONN 0x01
-+# define WUSB_DA_SELF_BEACON 0x02
-+# define WUSB_DA_DIR_BEACON 0x04
-+# define WUSB_DA_NO_BEACON 0x06
-+#define WUSB_DN_DISCONNECT 0x02
-+#define WUSB_DN_EPRDY 0x03
-+#define WUSB_DN_MASAVAILCHANGED 0x04
-+#define WUSB_DN_REMOTEWAKEUP 0x05
-+#define WUSB_DN_SLEEP 0x06
-+#define WUSB_DN_ALIVE 0x07
-+#define WUSB_DN_MAX 0x07
-+
-+#ifdef _MSC_VER
-+#include <pshpack1.h>
-+#endif
-+
-+/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */
-+typedef struct wusb_hndshk_data {
-+ uByte bMessageNumber;
-+ uByte bStatus;
-+ uByte tTKID[3];
-+ uByte bReserved;
-+ uByte CDID[16];
-+ uByte Nonce[16];
-+ uByte MIC[8];
-+} UPACKED wusb_hndshk_data_t;
-+#define WUSB_HANDSHAKE_LEN_FOR_MIC 38
-+
-+/* WUSB Connection Context */
-+typedef struct wusb_conn_context {
-+ uByte CHID [16];
-+ uByte CDID [16];
-+ uByte CK [16];
-+} UPACKED wusb_conn_context_t;
-+
-+/* WUSB Security Descriptor */
-+typedef struct wusb_security_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord wTotalLength;
-+ uByte bNumEncryptionTypes;
-+} UPACKED wusb_security_desc_t;
-+
-+/* WUSB Encryption Type Descriptor */
-+typedef struct wusb_encrypt_type_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+
-+ uByte bEncryptionType;
-+#define WUETD_UNSECURE 0
-+#define WUETD_WIRED 1
-+#define WUETD_CCM_1 2
-+#define WUETD_RSA_1 3
-+
-+ uByte bEncryptionValue;
-+ uByte bAuthKeyIndex;
-+} UPACKED wusb_encrypt_type_desc_t;
-+
-+/* WUSB Key Descriptor */
-+typedef struct wusb_key_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte tTKID[3];
-+ uByte bReserved;
-+ uByte KeyData[1]; /* variable length */
-+} UPACKED wusb_key_desc_t;
-+
-+/* WUSB BOS Descriptor (Binary device Object Store) */
-+typedef struct wusb_bos_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord wTotalLength;
-+ uByte bNumDeviceCaps;
-+} UPACKED wusb_bos_desc_t;
-+
-+#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02
-+typedef struct usb_dev_cap_20_ext_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+#define USB_20_EXT_LPM 0x02
-+ uDWord bmAttributes;
-+} UPACKED usb_dev_cap_20_ext_desc_t;
-+
-+#define USB_DEVICE_CAPABILITY_SS_USB 0x03
-+typedef struct usb_dev_cap_ss_usb {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+#define USB_DC_SS_USB_LTM_CAPABLE 0x02
-+ uByte bmAttributes;
-+#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01
-+#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02
-+#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04
-+#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08
-+ uWord wSpeedsSupported;
-+ uByte bFunctionalitySupport;
-+ uByte bU1DevExitLat;
-+ uWord wU2DevExitLat;
-+} UPACKED usb_dev_cap_ss_usb_t;
-+
-+#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04
-+typedef struct usb_dev_cap_container_id {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+ uByte bReserved;
-+ uByte containerID[16];
-+} UPACKED usb_dev_cap_container_id_t;
-+
-+/* Device Capability Type Codes */
-+#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
-+
-+/* Device Capability Descriptor */
-+typedef struct wusb_dev_cap_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+ uByte caps[1]; /* Variable length */
-+} UPACKED wusb_dev_cap_desc_t;
-+
-+/* Device Capability Descriptor */
-+typedef struct wusb_dev_cap_uwb_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+ uByte bmAttributes;
-+ uWord wPHYRates; /* Bitmap */
-+ uByte bmTFITXPowerInfo;
-+ uByte bmFFITXPowerInfo;
-+ uWord bmBandGroup;
-+ uByte bReserved;
-+} UPACKED wusb_dev_cap_uwb_desc_t;
-+
-+/* Wireless USB Endpoint Companion Descriptor */
-+typedef struct wusb_endpoint_companion_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bMaxBurst;
-+ uByte bMaxSequence;
-+ uWord wMaxStreamDelay;
-+ uWord wOverTheAirPacketSize;
-+ uByte bOverTheAirInterval;
-+ uByte bmCompAttributes;
-+} UPACKED wusb_endpoint_companion_desc_t;
-+
-+/* Wireless USB Numeric Association M1 Data Structure */
-+typedef struct wusb_m1_data {
-+ uByte version;
-+ uWord langId;
-+ uByte deviceFriendlyNameLength;
-+ uByte sha_256_m3[32];
-+ uByte deviceFriendlyName[256];
-+} UPACKED wusb_m1_data_t;
-+
-+typedef struct wusb_m2_data {
-+ uByte version;
-+ uWord langId;
-+ uByte hostFriendlyNameLength;
-+ uByte pkh[384];
-+ uByte hostFriendlyName[256];
-+} UPACKED wusb_m2_data_t;
-+
-+typedef struct wusb_m3_data {
-+ uByte pkd[384];
-+ uByte nd;
-+} UPACKED wusb_m3_data_t;
-+
-+typedef struct wusb_m4_data {
-+ uDWord _attributeTypeIdAndLength_1;
-+ uWord associationTypeId;
-+
-+ uDWord _attributeTypeIdAndLength_2;
-+ uWord associationSubTypeId;
-+
-+ uDWord _attributeTypeIdAndLength_3;
-+ uDWord length;
-+
-+ uDWord _attributeTypeIdAndLength_4;
-+ uDWord associationStatus;
-+
-+ uDWord _attributeTypeIdAndLength_5;
-+ uByte chid[16];
-+
-+ uDWord _attributeTypeIdAndLength_6;
-+ uByte cdid[16];
-+
-+ uDWord _attributeTypeIdAndLength_7;
-+ uByte bandGroups[2];
-+} UPACKED wusb_m4_data_t;
-+
-+#ifdef _MSC_VER
-+#include <poppack.h>
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _USB_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg
---- linux-3.12.38/drivers/usb/host/dwc_otg/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,224 @@
-+# Doxyfile 1.3.9.1
-+
-+#---------------------------------------------------------------------------
-+# Project related configuration options
-+#---------------------------------------------------------------------------
-+PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
-+PROJECT_NUMBER = v3.00a
-+OUTPUT_DIRECTORY = ./doc/
-+CREATE_SUBDIRS = NO
-+OUTPUT_LANGUAGE = English
-+BRIEF_MEMBER_DESC = YES
-+REPEAT_BRIEF = YES
-+ABBREVIATE_BRIEF = "The $name class" \
-+ "The $name widget" \
-+ "The $name file" \
-+ is \
-+ provides \
-+ specifies \
-+ contains \
-+ represents \
-+ a \
-+ an \
-+ the
-+ALWAYS_DETAILED_SEC = NO
-+INLINE_INHERITED_MEMB = NO
-+FULL_PATH_NAMES = NO
-+STRIP_FROM_PATH =
-+STRIP_FROM_INC_PATH =
-+SHORT_NAMES = NO
-+JAVADOC_AUTOBRIEF = YES
-+MULTILINE_CPP_IS_BRIEF = NO
-+INHERIT_DOCS = YES
-+DISTRIBUTE_GROUP_DOC = NO
-+TAB_SIZE = 8
-+ALIASES =
-+OPTIMIZE_OUTPUT_FOR_C = YES
-+OPTIMIZE_OUTPUT_JAVA = NO
-+SUBGROUPING = YES
-+#---------------------------------------------------------------------------
-+# Build related configuration options
-+#---------------------------------------------------------------------------
-+EXTRACT_ALL = NO
-+EXTRACT_PRIVATE = YES
-+EXTRACT_STATIC = YES
-+EXTRACT_LOCAL_CLASSES = YES
-+EXTRACT_LOCAL_METHODS = NO
-+HIDE_UNDOC_MEMBERS = NO
-+HIDE_UNDOC_CLASSES = NO
-+HIDE_FRIEND_COMPOUNDS = NO
-+HIDE_IN_BODY_DOCS = NO
-+INTERNAL_DOCS = NO
-+CASE_SENSE_NAMES = NO
-+HIDE_SCOPE_NAMES = NO
-+SHOW_INCLUDE_FILES = YES
-+INLINE_INFO = YES
-+SORT_MEMBER_DOCS = NO
-+SORT_BRIEF_DOCS = NO
-+SORT_BY_SCOPE_NAME = NO
-+GENERATE_TODOLIST = YES
-+GENERATE_TESTLIST = YES
-+GENERATE_BUGLIST = YES
-+GENERATE_DEPRECATEDLIST= YES
-+ENABLED_SECTIONS =
-+MAX_INITIALIZER_LINES = 30
-+SHOW_USED_FILES = YES
-+SHOW_DIRECTORIES = YES
-+#---------------------------------------------------------------------------
-+# configuration options related to warning and progress messages
-+#---------------------------------------------------------------------------
-+QUIET = YES
-+WARNINGS = YES
-+WARN_IF_UNDOCUMENTED = NO
-+WARN_IF_DOC_ERROR = YES
-+WARN_FORMAT = "$file:$line: $text"
-+WARN_LOGFILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the input files
-+#---------------------------------------------------------------------------
-+INPUT = .
-+FILE_PATTERNS = *.c \
-+ *.h \
-+ ./linux/*.c \
-+ ./linux/*.h
-+RECURSIVE = NO
-+EXCLUDE = ./test/ \
-+ ./dwc_otg/.AppleDouble/
-+EXCLUDE_SYMLINKS = YES
-+EXCLUDE_PATTERNS = *.mod.*
-+EXAMPLE_PATH =
-+EXAMPLE_PATTERNS = *
-+EXAMPLE_RECURSIVE = NO
-+IMAGE_PATH =
-+INPUT_FILTER =
-+FILTER_PATTERNS =
-+FILTER_SOURCE_FILES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to source browsing
-+#---------------------------------------------------------------------------
-+SOURCE_BROWSER = YES
-+INLINE_SOURCES = NO
-+STRIP_CODE_COMMENTS = YES
-+REFERENCED_BY_RELATION = NO
-+REFERENCES_RELATION = NO
-+VERBATIM_HEADERS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the alphabetical class index
-+#---------------------------------------------------------------------------
-+ALPHABETICAL_INDEX = NO
-+COLS_IN_ALPHA_INDEX = 5
-+IGNORE_PREFIX =
-+#---------------------------------------------------------------------------
-+# configuration options related to the HTML output
-+#---------------------------------------------------------------------------
-+GENERATE_HTML = YES
-+HTML_OUTPUT = html
-+HTML_FILE_EXTENSION = .html
-+HTML_HEADER =
-+HTML_FOOTER =
-+HTML_STYLESHEET =
-+HTML_ALIGN_MEMBERS = YES
-+GENERATE_HTMLHELP = NO
-+CHM_FILE =
-+HHC_LOCATION =
-+GENERATE_CHI = NO
-+BINARY_TOC = NO
-+TOC_EXPAND = NO
-+DISABLE_INDEX = NO
-+ENUM_VALUES_PER_LINE = 4
-+GENERATE_TREEVIEW = YES
-+TREEVIEW_WIDTH = 250
-+#---------------------------------------------------------------------------
-+# configuration options related to the LaTeX output
-+#---------------------------------------------------------------------------
-+GENERATE_LATEX = NO
-+LATEX_OUTPUT = latex
-+LATEX_CMD_NAME = latex
-+MAKEINDEX_CMD_NAME = makeindex
-+COMPACT_LATEX = NO
-+PAPER_TYPE = a4wide
-+EXTRA_PACKAGES =
-+LATEX_HEADER =
-+PDF_HYPERLINKS = NO
-+USE_PDFLATEX = NO
-+LATEX_BATCHMODE = NO
-+LATEX_HIDE_INDICES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the RTF output
-+#---------------------------------------------------------------------------
-+GENERATE_RTF = NO
-+RTF_OUTPUT = rtf
-+COMPACT_RTF = NO
-+RTF_HYPERLINKS = NO
-+RTF_STYLESHEET_FILE =
-+RTF_EXTENSIONS_FILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the man page output
-+#---------------------------------------------------------------------------
-+GENERATE_MAN = NO
-+MAN_OUTPUT = man
-+MAN_EXTENSION = .3
-+MAN_LINKS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the XML output
-+#---------------------------------------------------------------------------
-+GENERATE_XML = NO
-+XML_OUTPUT = xml
-+XML_SCHEMA =
-+XML_DTD =
-+XML_PROGRAMLISTING = YES
-+#---------------------------------------------------------------------------
-+# configuration options for the AutoGen Definitions output
-+#---------------------------------------------------------------------------
-+GENERATE_AUTOGEN_DEF = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the Perl module output
-+#---------------------------------------------------------------------------
-+GENERATE_PERLMOD = NO
-+PERLMOD_LATEX = NO
-+PERLMOD_PRETTY = YES
-+PERLMOD_MAKEVAR_PREFIX =
-+#---------------------------------------------------------------------------
-+# Configuration options related to the preprocessor
-+#---------------------------------------------------------------------------
-+ENABLE_PREPROCESSING = YES
-+MACRO_EXPANSION = YES
-+EXPAND_ONLY_PREDEF = YES
-+SEARCH_INCLUDES = YES
-+INCLUDE_PATH =
-+INCLUDE_FILE_PATTERNS =
-+PREDEFINED = DEVICE_ATTR DWC_EN_ISOC
-+EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
-+SKIP_FUNCTION_MACROS = NO
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to external references
-+#---------------------------------------------------------------------------
-+TAGFILES =
-+GENERATE_TAGFILE =
-+ALLEXTERNALS = NO
-+EXTERNAL_GROUPS = YES
-+PERL_PATH = /usr/bin/perl
-+#---------------------------------------------------------------------------
-+# Configuration options related to the dot tool
-+#---------------------------------------------------------------------------
-+CLASS_DIAGRAMS = YES
-+HIDE_UNDOC_RELATIONS = YES
-+HAVE_DOT = NO
-+CLASS_GRAPH = YES
-+COLLABORATION_GRAPH = YES
-+UML_LOOK = NO
-+TEMPLATE_RELATIONS = NO
-+INCLUDE_GRAPH = YES
-+INCLUDED_BY_GRAPH = YES
-+CALL_GRAPH = NO
-+GRAPHICAL_HIERARCHY = YES
-+DOT_IMAGE_FORMAT = png
-+DOT_PATH =
-+DOTFILE_DIRS =
-+MAX_DOT_GRAPH_DEPTH = 1000
-+GENERATE_LEGEND = YES
-+DOT_CLEANUP = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to the search engine
-+#---------------------------------------------------------------------------
-+SEARCHENGINE = NO
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dummy_audio.c linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dummy_audio.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,1575 @@
-+/*
-+ * zero.c -- Gadget Zero, for USB development
-+ *
-+ * Copyright (C) 2003-2004 David Brownell
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * Gadget Zero only needs two bulk endpoints, and is an example of how you
-+ * can write a hardware-agnostic gadget driver running inside a USB device.
-+ *
-+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
-+ * affect most of the driver.
-+ *
-+ * Use it with the Linux host/master side "usbtest" driver to get a basic
-+ * functional test of your device-side usb stack, or with "usb-skeleton".
-+ *
-+ * It supports two similar configurations. One sinks whatever the usb host
-+ * writes, and in return sources zeroes. The other loops whatever the host
-+ * writes back, so the host can read it. Module options include:
-+ *
-+ * buflen=N default N=4096, buffer size used
-+ * qlen=N default N=32, how many buffers in the loopback queue
-+ * loopdefault default false, list loopback config first
-+ *
-+ * Many drivers will only have one configuration, letting them be much
-+ * simpler if they also don't support high speed operation (like this
-+ * driver does).
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/delay.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/smp_lock.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/timer.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/uts.h>
-+#include <linux/version.h>
-+#include <linux/device.h>
-+#include <linux/moduleparam.h>
-+#include <linux/proc_fs.h>
-+
-+#include <asm/byteorder.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/system.h>
-+#include <asm/unaligned.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#include <linux/usb_gadget.h>
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+
-+/**
-+ * usb_gadget_get_string - fill out a string descriptor
-+ * @table: of c strings encoded using UTF-8
-+ * @id: string id, from low byte of wValue in get string descriptor
-+ * @buf: at least 256 bytes
-+ *
-+ * Finds the UTF-8 string matching the ID, and converts it into a
-+ * string descriptor in utf16-le.
-+ * Returns length of descriptor (always even) or negative errno
-+ *
-+ * If your driver needs stings in multiple languages, you'll probably
-+ * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
-+ * using this routine after choosing which set of UTF-8 strings to use.
-+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
-+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
-+ * characters (which are also widely used in C strings).
-+ */
-+int
-+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
-+{
-+ struct usb_string *s;
-+ int len;
-+
-+ /* descriptor 0 has the language id */
-+ if (id == 0) {
-+ buf [0] = 4;
-+ buf [1] = USB_DT_STRING;
-+ buf [2] = (u8) table->language;
-+ buf [3] = (u8) (table->language >> 8);
-+ return 4;
-+ }
-+ for (s = table->strings; s && s->s; s++)
-+ if (s->id == id)
-+ break;
-+
-+ /* unrecognized: stall. */
-+ if (!s || !s->s)
-+ return -EINVAL;
-+
-+ /* string descriptors have length, tag, then UTF16-LE text */
-+ len = min ((size_t) 126, strlen (s->s));
-+ memset (buf + 2, 0, 2 * len); /* zero all the bytes */
-+ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
-+ if (len < 0)
-+ return -EINVAL;
-+ buf [0] = (len + 1) * 2;
-+ buf [1] = USB_DT_STRING;
-+ return buf [0];
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/**
-+ * usb_descriptor_fillbuf - fill buffer with descriptors
-+ * @buf: Buffer to be filled
-+ * @buflen: Size of buf
-+ * @src: Array of descriptor pointers, terminated by null pointer.
-+ *
-+ * Copies descriptors into the buffer, returning the length or a
-+ * negative error code if they can't all be copied. Useful when
-+ * assembling descriptors for an associated set of interfaces used
-+ * as part of configuring a composite device; or in other cases where
-+ * sets of descriptors need to be marshaled.
-+ */
-+int
-+usb_descriptor_fillbuf(void *buf, unsigned buflen,
-+ const struct usb_descriptor_header **src)
-+{
-+ u8 *dest = buf;
-+
-+ if (!src)
-+ return -EINVAL;
-+
-+ /* fill buffer from src[] until null descriptor ptr */
-+ for (; 0 != *src; src++) {
-+ unsigned len = (*src)->bLength;
-+
-+ if (len > buflen)
-+ return -EINVAL;
-+ memcpy(dest, *src, len);
-+ buflen -= len;
-+ dest += len;
-+ }
-+ return dest - (u8 *)buf;
-+}
-+
-+
-+/**
-+ * usb_gadget_config_buf - builts a complete configuration descriptor
-+ * @config: Header for the descriptor, including characteristics such
-+ * as power requirements and number of interfaces.
-+ * @desc: Null-terminated vector of pointers to the descriptors (interface,
-+ * endpoint, etc) defining all functions in this device configuration.
-+ * @buf: Buffer for the resulting configuration descriptor.
-+ * @length: Length of buffer. If this is not big enough to hold the
-+ * entire configuration descriptor, an error code will be returned.
-+ *
-+ * This copies descriptors into the response buffer, building a descriptor
-+ * for that configuration. It returns the buffer length or a negative
-+ * status code. The config.wTotalLength field is set to match the length
-+ * of the result, but other descriptor fields (including power usage and
-+ * interface count) must be set by the caller.
-+ *
-+ * Gadget drivers could use this when constructing a config descriptor
-+ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
-+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
-+ */
-+int usb_gadget_config_buf(
-+ const struct usb_config_descriptor *config,
-+ void *buf,
-+ unsigned length,
-+ const struct usb_descriptor_header **desc
-+)
-+{
-+ struct usb_config_descriptor *cp = buf;
-+ int len;
-+
-+ /* config descriptor first */
-+ if (length < USB_DT_CONFIG_SIZE || !desc)
-+ return -EINVAL;
-+ *cp = *config;
-+
-+ /* then interface/endpoint/class/vendor/... */
-+ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
-+ length - USB_DT_CONFIG_SIZE, desc);
-+ if (len < 0)
-+ return len;
-+ len += USB_DT_CONFIG_SIZE;
-+ if (len > 0xffff)
-+ return -EINVAL;
-+
-+ /* patch up the config descriptor */
-+ cp->bLength = USB_DT_CONFIG_SIZE;
-+ cp->bDescriptorType = USB_DT_CONFIG;
-+ cp->wTotalLength = cpu_to_le16(len);
-+ cp->bmAttributes |= USB_CONFIG_ATT_ONE;
-+ return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+#define RBUF_LEN (1024*1024)
-+static int rbuf_start;
-+static int rbuf_len;
-+static __u8 rbuf[RBUF_LEN];
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_VERSION "St Patrick's Day 2004"
-+
-+static const char shortname [] = "zero";
-+static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
-+
-+static const char source_sink [] = "source and sink data";
-+static const char loopback [] = "loop input to output";
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * driver assumes self-powered hardware, and
-+ * has no way for users to trigger remote wakeup.
-+ *
-+ * this version autoconfigures as much as possible,
-+ * which is reasonable for most "bulk-only" drivers.
-+ */
-+static const char *EP_IN_NAME; /* source */
-+static const char *EP_OUT_NAME; /* sink */
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* big enough to hold our biggest descriptor */
-+#define USB_BUFSIZ 512
-+
-+struct zero_dev {
-+ spinlock_t lock;
-+ struct usb_gadget *gadget;
-+ struct usb_request *req; /* for control responses */
-+
-+ /* when configured, we have one of two configs:
-+ * - source data (in to host) and sink it (out from host)
-+ * - or loop it back (out from host back in to host)
-+ */
-+ u8 config;
-+ struct usb_ep *in_ep, *out_ep;
-+
-+ /* autoresume timer */
-+ struct timer_list resume;
-+};
-+
-+#define xprintk(d,level,fmt,args...) \
-+ dev_printk(level , &(d)->gadget->dev , fmt , ## args)
-+
-+#ifdef DEBUG
-+#define DBG(dev,fmt,args...) \
-+ xprintk(dev , KERN_DEBUG , fmt , ## args)
-+#else
-+#define DBG(dev,fmt,args...) \
-+ do { } while (0)
-+#endif /* DEBUG */
-+
-+#ifdef VERBOSE
-+#define VDBG DBG
-+#else
-+#define VDBG(dev,fmt,args...) \
-+ do { } while (0)
-+#endif /* VERBOSE */
-+
-+#define ERROR(dev,fmt,args...) \
-+ xprintk(dev , KERN_ERR , fmt , ## args)
-+#define WARN(dev,fmt,args...) \
-+ xprintk(dev , KERN_WARNING , fmt , ## args)
-+#define INFO(dev,fmt,args...) \
-+ xprintk(dev , KERN_INFO , fmt , ## args)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static unsigned buflen = 4096;
-+static unsigned qlen = 32;
-+static unsigned pattern = 0;
-+
-+module_param (buflen, uint, S_IRUGO|S_IWUSR);
-+module_param (qlen, uint, S_IRUGO|S_IWUSR);
-+module_param (pattern, uint, S_IRUGO|S_IWUSR);
-+
-+/*
-+ * if it's nonzero, autoresume says how many seconds to wait
-+ * before trying to wake up the host after suspend.
-+ */
-+static unsigned autoresume = 0;
-+module_param (autoresume, uint, 0);
-+
-+/*
-+ * Normally the "loopback" configuration is second (index 1) so
-+ * it's not the default. Here's where to change that order, to
-+ * work better with hosts where config changes are problematic.
-+ * Or controllers (like superh) that only support one config.
-+ */
-+static int loopdefault = 0;
-+
-+module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Thanks to NetChip Technologies for donating this product ID.
-+ *
-+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
-+ * Instead: allocate your own, using normal USB-IF procedures.
-+ */
-+#ifndef CONFIG_USB_ZERO_HNPTEST
-+#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
-+#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
-+#else
-+#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
-+#define DRIVER_PRODUCT_NUM 0xbadd
-+#endif
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full)
-+ * configuration descriptors are built on demand.
-+ */
-+
-+/*
-+#define STRING_MANUFACTURER 25
-+#define STRING_PRODUCT 42
-+#define STRING_SERIAL 101
-+*/
-+#define STRING_MANUFACTURER 1
-+#define STRING_PRODUCT 2
-+#define STRING_SERIAL 3
-+
-+#define STRING_SOURCE_SINK 250
-+#define STRING_LOOPBACK 251
-+
-+/*
-+ * This device advertises two configurations; these numbers work
-+ * on a pxa250 as well as more flexible hardware.
-+ */
-+#define CONFIG_SOURCE_SINK 3
-+#define CONFIG_LOOPBACK 2
-+
-+/*
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+
-+ .bcdUSB = __constant_cpu_to_le16 (0x0200),
-+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-+
-+ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
-+ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
-+ .iManufacturer = STRING_MANUFACTURER,
-+ .iProduct = STRING_PRODUCT,
-+ .iSerialNumber = STRING_SERIAL,
-+ .bNumConfigurations = 2,
-+};
-+*/
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+ .bcdUSB = __constant_cpu_to_le16 (0x0100),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+ .bDeviceSubClass = 0,
-+ .bDeviceProtocol = 0,
-+ .bMaxPacketSize0 = 64,
-+ .bcdDevice = __constant_cpu_to_le16 (0x0100),
-+ .idVendor = __constant_cpu_to_le16 (0x0499),
-+ .idProduct = __constant_cpu_to_le16 (0x3002),
-+ .iManufacturer = STRING_MANUFACTURER,
-+ .iProduct = STRING_PRODUCT,
-+ .iSerialNumber = STRING_SERIAL,
-+ .bNumConfigurations = 1,
-+};
-+
-+static struct usb_config_descriptor
-+z_config = {
-+ .bLength = sizeof z_config,
-+ .bDescriptorType = USB_DT_CONFIG,
-+
-+ /* compute wTotalLength on the fly */
-+ .bNumInterfaces = 2,
-+ .bConfigurationValue = 1,
-+ .iConfiguration = 0,
-+ .bmAttributes = 0x40,
-+ .bMaxPower = 0, /* self-powered */
-+};
-+
-+
-+static struct usb_otg_descriptor
-+otg_descriptor = {
-+ .bLength = sizeof otg_descriptor,
-+ .bDescriptorType = USB_DT_OTG,
-+
-+ .bmAttributes = USB_OTG_SRP,
-+};
-+
-+/* one interface in each configuration */
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+
-+/*
-+ * usb 2.0 devices need to expose both high speed and full speed
-+ * descriptors, unless they only run at full speed.
-+ *
-+ * that means alternate endpoint descriptors (bigger packets)
-+ * and a "device qualifier" ... plus more construction options
-+ * for the config descriptor.
-+ */
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+ .bLength = sizeof dev_qualifier,
-+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
-+
-+ .bcdUSB = __constant_cpu_to_le16 (0x0200),
-+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-+
-+ .bNumConfigurations = 2,
-+};
-+
-+
-+struct usb_cs_as_general_descriptor {
-+ __u8 bLength;
-+ __u8 bDescriptorType;
-+
-+ __u8 bDescriptorSubType;
-+ __u8 bTerminalLink;
-+ __u8 bDelay;
-+ __u16 wFormatTag;
-+} __attribute__ ((packed));
-+
-+struct usb_cs_as_format_descriptor {
-+ __u8 bLength;
-+ __u8 bDescriptorType;
-+
-+ __u8 bDescriptorSubType;
-+ __u8 bFormatType;
-+ __u8 bNrChannels;
-+ __u8 bSubframeSize;
-+ __u8 bBitResolution;
-+ __u8 bSamfreqType;
-+ __u8 tLowerSamFreq[3];
-+ __u8 tUpperSamFreq[3];
-+} __attribute__ ((packed));
-+
-+static const struct usb_interface_descriptor
-+z_audio_control_if_desc = {
-+ .bLength = sizeof z_audio_control_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 0,
-+ .bAlternateSetting = 0,
-+ .bNumEndpoints = 0,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x1,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc = {
-+ .bLength = sizeof z_audio_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 1,
-+ .bAlternateSetting = 0,
-+ .bNumEndpoints = 0,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x2,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc2 = {
-+ .bLength = sizeof z_audio_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 1,
-+ .bAlternateSetting = 1,
-+ .bNumEndpoints = 1,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x2,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_cs_as_general_descriptor
-+z_audio_cs_as_if_desc = {
-+ .bLength = 7,
-+ .bDescriptorType = 0x24,
-+
-+ .bDescriptorSubType = 0x01,
-+ .bTerminalLink = 0x01,
-+ .bDelay = 0x0,
-+ .wFormatTag = __constant_cpu_to_le16 (0x0001)
-+};
-+
-+
-+static const struct usb_cs_as_format_descriptor
-+z_audio_cs_as_format_desc = {
-+ .bLength = 0xe,
-+ .bDescriptorType = 0x24,
-+
-+ .bDescriptorSubType = 2,
-+ .bFormatType = 1,
-+ .bNrChannels = 1,
-+ .bSubframeSize = 1,
-+ .bBitResolution = 8,
-+ .bSamfreqType = 0,
-+ .tLowerSamFreq = {0x7e, 0x13, 0x00},
-+ .tUpperSamFreq = {0xe2, 0xd6, 0x00},
-+};
-+
-+static const struct usb_endpoint_descriptor
-+z_iso_ep = {
-+ .bLength = 0x09,
-+ .bDescriptorType = 0x05,
-+ .bEndpointAddress = 0x04,
-+ .bmAttributes = 0x09,
-+ .wMaxPacketSize = 0x0038,
-+ .bInterval = 0x01,
-+ .bRefresh = 0x00,
-+ .bSynchAddress = 0x00,
-+};
-+
-+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+// 9 bytes
-+static char z_ac_interface_header_desc[] =
-+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
-+
-+// 12 bytes
-+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
-+ 0x03, 0x00, 0x00, 0x00};
-+// 13 bytes
-+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
-+ 0x02, 0x00, 0x02, 0x00, 0x00};
-+// 9 bytes
-+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
-+ 0x00};
-+
-+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
-+ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+
-+
-+static const struct usb_descriptor_header *z_function [] = {
-+ (struct usb_descriptor_header *) &z_audio_control_if_desc,
-+ (struct usb_descriptor_header *) &z_ac_interface_header_desc,
-+ (struct usb_descriptor_header *) &z_0,
-+ (struct usb_descriptor_header *) &z_1,
-+ (struct usb_descriptor_header *) &z_2,
-+ (struct usb_descriptor_header *) &z_audio_if_desc,
-+ (struct usb_descriptor_header *) &z_audio_if_desc2,
-+ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
-+ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
-+ (struct usb_descriptor_header *) &z_iso_ep,
-+ (struct usb_descriptor_header *) &z_iso_ep2,
-+ (struct usb_descriptor_header *) &za_0,
-+ (struct usb_descriptor_header *) &za_1,
-+ (struct usb_descriptor_header *) &za_2,
-+ (struct usb_descriptor_header *) &za_3,
-+ (struct usb_descriptor_header *) &za_4,
-+ (struct usb_descriptor_header *) &za_5,
-+ (struct usb_descriptor_header *) &za_6,
-+ (struct usb_descriptor_header *) &za_7,
-+ (struct usb_descriptor_header *) &za_8,
-+ (struct usb_descriptor_header *) &za_9,
-+ (struct usb_descriptor_header *) &za_10,
-+ (struct usb_descriptor_header *) &za_11,
-+ (struct usb_descriptor_header *) &za_12,
-+ (struct usb_descriptor_header *) &za_13,
-+ (struct usb_descriptor_header *) &za_14,
-+ (struct usb_descriptor_header *) &za_15,
-+ (struct usb_descriptor_header *) &za_16,
-+ (struct usb_descriptor_header *) &za_17,
-+ (struct usb_descriptor_header *) &za_18,
-+ (struct usb_descriptor_header *) &za_19,
-+ (struct usb_descriptor_header *) &za_20,
-+ (struct usb_descriptor_header *) &za_21,
-+ (struct usb_descriptor_header *) &za_22,
-+ (struct usb_descriptor_header *) &za_23,
-+ (struct usb_descriptor_header *) &za_24,
-+ NULL,
-+};
-+
-+/* maxpacket and other transfer characteristics vary by speed. */
-+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
-+
-+#else
-+
-+/* if there's no high speed support, maxpacket doesn't change. */
-+#define ep_desc(g,hs,fs) fs
-+
-+#endif /* !CONFIG_USB_GADGET_DUALSPEED */
-+
-+static char manufacturer [40];
-+//static char serial [40];
-+static char serial [] = "Ser 00 em";
-+
-+/* static strings, in UTF-8 */
-+static struct usb_string strings [] = {
-+ { STRING_MANUFACTURER, manufacturer, },
-+ { STRING_PRODUCT, longname, },
-+ { STRING_SERIAL, serial, },
-+ { STRING_LOOPBACK, loopback, },
-+ { STRING_SOURCE_SINK, source_sink, },
-+ { } /* end of list */
-+};
-+
-+static struct usb_gadget_strings stringtab = {
-+ .language = 0x0409, /* en-us */
-+ .strings = strings,
-+};
-+
-+/*
-+ * config descriptors are also handcrafted. these must agree with code
-+ * that sets configurations, and with code managing interfaces and their
-+ * altsettings. other complexity may come from:
-+ *
-+ * - high speed support, including "other speed config" rules
-+ * - multiple configurations
-+ * - interfaces with alternate settings
-+ * - embedded class or vendor-specific descriptors
-+ *
-+ * this handles high speed, and has a second config that could as easily
-+ * have been an alternate interface setting (on most hardware).
-+ *
-+ * NOTE: to demonstrate (and test) more USB capabilities, this driver
-+ * should include an altsetting to test interrupt transfers, including
-+ * high bandwidth modes at high speed. (Maybe work like Intel's test
-+ * device?)
-+ */
-+static int
-+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
-+{
-+ int len;
-+ const struct usb_descriptor_header **function;
-+
-+ function = z_function;
-+ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
-+ if (len < 0)
-+ return len;
-+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+ return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_request *
-+alloc_ep_req (struct usb_ep *ep, unsigned length)
-+{
-+ struct usb_request *req;
-+
-+ req = usb_ep_alloc_request (ep, GFP_ATOMIC);
-+ if (req) {
-+ req->length = length;
-+ req->buf = usb_ep_alloc_buffer (ep, length,
-+ &req->dma, GFP_ATOMIC);
-+ if (!req->buf) {
-+ usb_ep_free_request (ep, req);
-+ req = NULL;
-+ }
-+ }
-+ return req;
-+}
-+
-+static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
-+{
-+ if (req->buf)
-+ usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
-+ usb_ep_free_request (ep, req);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* optionally require specific source/sink data patterns */
-+
-+static int
-+check_read_data (
-+ struct zero_dev *dev,
-+ struct usb_ep *ep,
-+ struct usb_request *req
-+)
-+{
-+ unsigned i;
-+ u8 *buf = req->buf;
-+
-+ for (i = 0; i < req->actual; i++, buf++) {
-+ switch (pattern) {
-+ /* all-zeroes has no synchronization issues */
-+ case 0:
-+ if (*buf == 0)
-+ continue;
-+ break;
-+ /* mod63 stays in sync with short-terminated transfers,
-+ * or otherwise when host and gadget agree on how large
-+ * each usb transfer request should be. resync is done
-+ * with set_interface or set_config.
-+ */
-+ case 1:
-+ if (*buf == (u8)(i % 63))
-+ continue;
-+ break;
-+ }
-+ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
-+ usb_ep_set_halt (ep);
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_reset_config (struct zero_dev *dev)
-+{
-+ if (dev->config == 0)
-+ return;
-+
-+ DBG (dev, "reset config\n");
-+
-+ /* just disable endpoints, forcing completion of pending i/o.
-+ * all our completion handlers free their requests in this case.
-+ */
-+ if (dev->in_ep) {
-+ usb_ep_disable (dev->in_ep);
-+ dev->in_ep = NULL;
-+ }
-+ if (dev->out_ep) {
-+ usb_ep_disable (dev->out_ep);
-+ dev->out_ep = NULL;
-+ }
-+ dev->config = 0;
-+ del_timer (&dev->resume);
-+}
-+
-+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
-+
-+static void
-+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct zero_dev *dev = ep->driver_data;
-+ int status = req->status;
-+ int i, j;
-+
-+ switch (status) {
-+
-+ case 0: /* normal completion? */
-+ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
-+ for (i=0, j=rbuf_start; i<req->actual; i++) {
-+ //printk ("%02x ", ((__u8*)req->buf)[i]);
-+ rbuf[j] = ((__u8*)req->buf)[i];
-+ j++;
-+ if (j >= RBUF_LEN) j=0;
-+ }
-+ rbuf_start = j;
-+ //printk ("\n\n");
-+
-+ if (rbuf_len < RBUF_LEN) {
-+ rbuf_len += req->actual;
-+ if (rbuf_len > RBUF_LEN) {
-+ rbuf_len = RBUF_LEN;
-+ }
-+ }
-+
-+ break;
-+
-+ /* this endpoint is normally active while we're configured */
-+ case -ECONNABORTED: /* hardware forced ep reset */
-+ case -ECONNRESET: /* request dequeued */
-+ case -ESHUTDOWN: /* disconnect from host */
-+ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
-+ req->actual, req->length);
-+ if (ep == dev->out_ep)
-+ check_read_data (dev, ep, req);
-+ free_ep_req (ep, req);
-+ return;
-+
-+ case -EOVERFLOW: /* buffer overrun on read means that
-+ * we didn't provide a big enough
-+ * buffer.
-+ */
-+ default:
-+#if 1
-+ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
-+ status, req->actual, req->length);
-+#endif
-+ case -EREMOTEIO: /* short read */
-+ break;
-+ }
-+
-+ status = usb_ep_queue (ep, req, GFP_ATOMIC);
-+ if (status) {
-+ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
-+ ep->name, req->length, status);
-+ usb_ep_set_halt (ep);
-+ /* FIXME recover later ... somehow */
-+ }
-+}
-+
-+static struct usb_request *
-+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
-+{
-+ struct usb_request *req;
-+ int status;
-+
-+ req = alloc_ep_req (ep, 512);
-+ if (!req)
-+ return NULL;
-+
-+ req->complete = zero_isoc_complete;
-+
-+ status = usb_ep_queue (ep, req, gfp_flags);
-+ if (status) {
-+ struct zero_dev *dev = ep->driver_data;
-+
-+ ERROR (dev, "start %s --> %d\n", ep->name, status);
-+ free_ep_req (ep, req);
-+ req = NULL;
-+ }
-+
-+ return req;
-+}
-+
-+/* change our operational config. this code must agree with the code
-+ * that returns config descriptors, and altsetting code.
-+ *
-+ * it's also responsible for power management interactions. some
-+ * configurations might not work with our current power sources.
-+ *
-+ * note that some device controller hardware will constrain what this
-+ * code can do, perhaps by disallowing more than one configuration or
-+ * by limiting configuration choices (like the pxa2xx).
-+ */
-+static int
-+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
-+{
-+ int result = 0;
-+ struct usb_gadget *gadget = dev->gadget;
-+ const struct usb_endpoint_descriptor *d;
-+ struct usb_ep *ep;
-+
-+ if (number == dev->config)
-+ return 0;
-+
-+ zero_reset_config (dev);
-+
-+ gadget_for_each_ep (ep, gadget) {
-+
-+ if (strcmp (ep->name, "ep4") == 0) {
-+
-+ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
-+ result = usb_ep_enable (ep, d);
-+
-+ if (result == 0) {
-+ ep->driver_data = dev;
-+ dev->in_ep = ep;
-+
-+ if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
-+
-+ dev->in_ep = ep;
-+ continue;
-+ }
-+
-+ usb_ep_disable (ep);
-+ result = -EIO;
-+ }
-+ }
-+
-+ }
-+
-+ dev->config = number;
-+ return result;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+ if (req->status || req->actual != req->length)
-+ DBG ((struct zero_dev *) ep->driver_data,
-+ "setup complete --> %d, %d/%d\n",
-+ req->status, req->actual, req->length);
-+}
-+
-+/*
-+ * The setup() callback implements all the ep0 functionality that's
-+ * not handled lower down, in hardware or the hardware driver (like
-+ * device and endpoint feature flags, and their status). It's all
-+ * housekeeping for the gadget function we're implementing. Most of
-+ * the work is in config-specific setup.
-+ */
-+static int
-+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+ struct usb_request *req = dev->req;
-+ int value = -EOPNOTSUPP;
-+
-+ /* usually this stores reply data in the pre-allocated ep0 buffer,
-+ * but config change events will reconfigure hardware.
-+ */
-+ req->zero = 0;
-+ switch (ctrl->bRequest) {
-+
-+ case USB_REQ_GET_DESCRIPTOR:
-+
-+ switch (ctrl->wValue >> 8) {
-+
-+ case USB_DT_DEVICE:
-+ value = min (ctrl->wLength, (u16) sizeof device_desc);
-+ memcpy (req->buf, &device_desc, value);
-+ break;
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ case USB_DT_DEVICE_QUALIFIER:
-+ if (!gadget->is_dualspeed)
-+ break;
-+ value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
-+ memcpy (req->buf, &dev_qualifier, value);
-+ break;
-+
-+ case USB_DT_OTHER_SPEED_CONFIG:
-+ if (!gadget->is_dualspeed)
-+ break;
-+ // FALLTHROUGH
-+#endif /* CONFIG_USB_GADGET_DUALSPEED */
-+ case USB_DT_CONFIG:
-+ value = config_buf (gadget, req->buf,
-+ ctrl->wValue >> 8,
-+ ctrl->wValue & 0xff);
-+ if (value >= 0)
-+ value = min (ctrl->wLength, (u16) value);
-+ break;
-+
-+ case USB_DT_STRING:
-+ /* wIndex == language code.
-+ * this driver only handles one language, you can
-+ * add string tables for other languages, using
-+ * any UTF-8 characters
-+ */
-+ value = usb_gadget_get_string (&stringtab,
-+ ctrl->wValue & 0xff, req->buf);
-+ if (value >= 0) {
-+ value = min (ctrl->wLength, (u16) value);
-+ }
-+ break;
-+ }
-+ break;
-+
-+ /* currently two configs, two speeds */
-+ case USB_REQ_SET_CONFIGURATION:
-+ if (ctrl->bRequestType != 0)
-+ goto unknown;
-+
-+ spin_lock (&dev->lock);
-+ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
-+ spin_unlock (&dev->lock);
-+ break;
-+ case USB_REQ_GET_CONFIGURATION:
-+ if (ctrl->bRequestType != USB_DIR_IN)
-+ goto unknown;
-+ *(u8 *)req->buf = dev->config;
-+ value = min (ctrl->wLength, (u16) 1);
-+ break;
-+
-+ /* until we add altsetting support, or other interfaces,
-+ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
-+ * and already killed pending endpoint I/O.
-+ */
-+ case USB_REQ_SET_INTERFACE:
-+
-+ if (ctrl->bRequestType != USB_RECIP_INTERFACE)
-+ goto unknown;
-+ spin_lock (&dev->lock);
-+ if (dev->config) {
-+ u8 config = dev->config;
-+
-+ /* resets interface configuration, forgets about
-+ * previous transaction state (queued bufs, etc)
-+ * and re-inits endpoint state (toggle etc)
-+ * no response queued, just zero status == success.
-+ * if we had more than one interface we couldn't
-+ * use this "reset the config" shortcut.
-+ */
-+ zero_reset_config (dev);
-+ zero_set_config (dev, config, GFP_ATOMIC);
-+ value = 0;
-+ }
-+ spin_unlock (&dev->lock);
-+ break;
-+ case USB_REQ_GET_INTERFACE:
-+ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
-+ value = ctrl->wLength;
-+ break;
-+ }
-+ else {
-+ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
-+ goto unknown;
-+ if (!dev->config)
-+ break;
-+ if (ctrl->wIndex != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ *(u8 *)req->buf = 0;
-+ value = min (ctrl->wLength, (u16) 1);
-+ }
-+ break;
-+
-+ /*
-+ * These are the same vendor-specific requests supported by
-+ * Intel's USB 2.0 compliance test devices. We exceed that
-+ * device spec by allowing multiple-packet requests.
-+ */
-+ case 0x5b: /* control WRITE test -- fill the buffer */
-+ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
-+ goto unknown;
-+ if (ctrl->wValue || ctrl->wIndex)
-+ break;
-+ /* just read that many bytes into the buffer */
-+ if (ctrl->wLength > USB_BUFSIZ)
-+ break;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x5c: /* control READ test -- return the buffer */
-+ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
-+ goto unknown;
-+ if (ctrl->wValue || ctrl->wIndex)
-+ break;
-+ /* expect those bytes are still in the buffer; send back */
-+ if (ctrl->wLength > USB_BUFSIZ
-+ || ctrl->wLength != req->length)
-+ break;
-+ value = ctrl->wLength;
-+ break;
-+
-+ case 0x01: // SET_CUR
-+ case 0x02:
-+ case 0x03:
-+ case 0x04:
-+ case 0x05:
-+ value = ctrl->wLength;
-+ break;
-+ case 0x81:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0xe3;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x00;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x81;
-+ //((u8*)req->buf)[1] = 0x81;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x82:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0xc3;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x00;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x82;
-+ //((u8*)req->buf)[1] = 0x82;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x83:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0x00;
-+ break;
-+ case 0x0300:
-+ ((u8*)req->buf)[0] = 0x60;
-+ break;
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x18;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x83;
-+ //((u8*)req->buf)[1] = 0x83;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x84:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0x01;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x08;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x84;
-+ //((u8*)req->buf)[1] = 0x84;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x85:
-+ ((u8*)req->buf)[0] = 0x85;
-+ ((u8*)req->buf)[1] = 0x85;
-+ value = ctrl->wLength;
-+ break;
-+
-+
-+ default:
-+unknown:
-+ printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ ctrl->wValue, ctrl->wIndex, ctrl->wLength);
-+ }
-+
-+ /* respond with data transfer before status phase? */
-+ if (value >= 0) {
-+ req->length = value;
-+ req->zero = value < ctrl->wLength
-+ && (value % gadget->ep0->maxpacket) == 0;
-+ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
-+ if (value < 0) {
-+ DBG (dev, "ep_queue < 0 --> %d\n", value);
-+ req->status = 0;
-+ zero_setup_complete (gadget->ep0, req);
-+ }
-+ }
-+
-+ /* device either stalls (value < 0) or reports success */
-+ return value;
-+}
-+
-+static void
-+zero_disconnect (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave (&dev->lock, flags);
-+ zero_reset_config (dev);
-+
-+ /* a more significant application might have some non-usb
-+ * activities to quiesce here, saving resources like power
-+ * or pushing the notification up a network stack.
-+ */
-+ spin_unlock_irqrestore (&dev->lock, flags);
-+
-+ /* next we may get setup() calls to enumerate new connections;
-+ * or an unbind() during shutdown (including removing module).
-+ */
-+}
-+
-+static void
-+zero_autoresume (unsigned long _dev)
-+{
-+ struct zero_dev *dev = (struct zero_dev *) _dev;
-+ int status;
-+
-+ /* normally the host would be woken up for something
-+ * more significant than just a timer firing...
-+ */
-+ if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
-+ status = usb_gadget_wakeup (dev->gadget);
-+ DBG (dev, "wakeup --> %d\n", status);
-+ }
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_unbind (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ DBG (dev, "unbind\n");
-+
-+ /* we've already been disconnected ... no i/o is active */
-+ if (dev->req)
-+ free_ep_req (gadget->ep0, dev->req);
-+ del_timer_sync (&dev->resume);
-+ kfree (dev);
-+ set_gadget_data (gadget, NULL);
-+}
-+
-+static int
-+zero_bind (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev;
-+ //struct usb_ep *ep;
-+
-+ printk("binding\n");
-+ /*
-+ * DRIVER POLICY CHOICE: you may want to do this differently.
-+ * One thing to avoid is reusing a bcdDevice revision code
-+ * with different host-visible configurations or behavior
-+ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
-+ */
-+ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
-+
-+
-+ /* ok, we made sense of the hardware ... */
-+ dev = kmalloc (sizeof *dev, SLAB_KERNEL);
-+ if (!dev)
-+ return -ENOMEM;
-+ memset (dev, 0, sizeof *dev);
-+ spin_lock_init (&dev->lock);
-+ dev->gadget = gadget;
-+ set_gadget_data (gadget, dev);
-+
-+ /* preallocate control response and buffer */
-+ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
-+ if (!dev->req)
-+ goto enomem;
-+ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
-+ &dev->req->dma, GFP_KERNEL);
-+ if (!dev->req->buf)
-+ goto enomem;
-+
-+ dev->req->complete = zero_setup_complete;
-+
-+ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
-+
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ /* assume ep0 uses the same value for both speeds ... */
-+ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
-+
-+ /* and that all endpoints are dual-speed */
-+ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
-+ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
-+#endif
-+
-+ usb_gadget_set_selfpowered (gadget);
-+
-+ init_timer (&dev->resume);
-+ dev->resume.function = zero_autoresume;
-+ dev->resume.data = (unsigned long) dev;
-+
-+ gadget->ep0->driver_data = dev;
-+
-+ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
-+ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
-+ EP_OUT_NAME, EP_IN_NAME);
-+
-+ snprintf (manufacturer, sizeof manufacturer,
-+ UTS_SYSNAME " " UTS_RELEASE " with %s",
-+ gadget->name);
-+
-+ return 0;
-+
-+enomem:
-+ zero_unbind (gadget);
-+ return -ENOMEM;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_suspend (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ if (gadget->speed == USB_SPEED_UNKNOWN)
-+ return;
-+
-+ if (autoresume) {
-+ mod_timer (&dev->resume, jiffies + (HZ * autoresume));
-+ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
-+ } else
-+ DBG (dev, "suspend\n");
-+}
-+
-+static void
-+zero_resume (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ DBG (dev, "resume\n");
-+ del_timer (&dev->resume);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver zero_driver = {
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ .speed = USB_SPEED_HIGH,
-+#else
-+ .speed = USB_SPEED_FULL,
-+#endif
-+ .function = (char *) longname,
-+ .bind = zero_bind,
-+ .unbind = zero_unbind,
-+
-+ .setup = zero_setup,
-+ .disconnect = zero_disconnect,
-+
-+ .suspend = zero_suspend,
-+ .resume = zero_resume,
-+
-+ .driver = {
-+ .name = (char *) shortname,
-+ // .shutdown = ...
-+ // .suspend = ...
-+ // .resume = ...
-+ },
-+};
-+
-+MODULE_AUTHOR ("David Brownell");
-+MODULE_LICENSE ("Dual BSD/GPL");
-+
-+static struct proc_dir_entry *pdir, *pfile;
-+
-+static int isoc_read_data (char *page, char **start,
-+ off_t off, int count,
-+ int *eof, void *data)
-+{
-+ int i;
-+ static int c = 0;
-+ static int done = 0;
-+ static int s = 0;
-+
-+/*
-+ printk ("\ncount: %d\n", count);
-+ printk ("rbuf_start: %d\n", rbuf_start);
-+ printk ("rbuf_len: %d\n", rbuf_len);
-+ printk ("off: %d\n", off);
-+ printk ("start: %p\n\n", *start);
-+*/
-+ if (done) {
-+ c = 0;
-+ done = 0;
-+ *eof = 1;
-+ return 0;
-+ }
-+
-+ if (c == 0) {
-+ if (rbuf_len == RBUF_LEN)
-+ s = rbuf_start;
-+ else s = 0;
-+ }
-+
-+ for (i=0; i<count && c<rbuf_len; i++, c++) {
-+ page[i] = rbuf[(c+s) % RBUF_LEN];
-+ }
-+ *start = page;
-+
-+ if (c >= rbuf_len) {
-+ *eof = 1;
-+ done = 1;
-+ }
-+
-+
-+ return i;
-+}
-+
-+static int __init init (void)
-+{
-+
-+ int retval = 0;
-+
-+ pdir = proc_mkdir("isoc_test", NULL);
-+ if(pdir == NULL) {
-+ retval = -ENOMEM;
-+ printk("Error creating dir\n");
-+ goto done;
-+ }
-+ pdir->owner = THIS_MODULE;
-+
-+ pfile = create_proc_read_entry("isoc_data",
-+ 0444, pdir,
-+ isoc_read_data,
-+ NULL);
-+ if (pfile == NULL) {
-+ retval = -ENOMEM;
-+ printk("Error creating file\n");
-+ goto no_file;
-+ }
-+ pfile->owner = THIS_MODULE;
-+
-+ return usb_gadget_register_driver (&zero_driver);
-+
-+ no_file:
-+ remove_proc_entry("isoc_data", NULL);
-+ done:
-+ return retval;
-+}
-+module_init (init);
-+
-+static void __exit cleanup (void)
-+{
-+
-+ usb_gadget_unregister_driver (&zero_driver);
-+
-+ remove_proc_entry("isoc_data", pdir);
-+ remove_proc_entry("isoc_test", NULL);
-+}
-+module_exit (cleanup);
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_cfi_common.h linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_cfi_common.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,142 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CFI_COMMON_H__)
-+#define __DWC_CFI_COMMON_H__
-+
-+//#include <linux/types.h>
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the CFI specific common constants, interfaces
-+ * (functions and macros) and structures for Linux. No PCD specific
-+ * data structure or definition is to be included in this file.
-+ *
-+ */
-+
-+/** This is a request for all Core Features */
-+#define VEN_CORE_GET_FEATURES 0xB1
-+
-+/** This is a request to get the value of a specific Core Feature */
-+#define VEN_CORE_GET_FEATURE 0xB2
-+
-+/** This command allows the host to set the value of a specific Core Feature */
-+#define VEN_CORE_SET_FEATURE 0xB3
-+
-+/** This command allows the host to set the default values of
-+ * either all or any specific Core Feature
-+ */
-+#define VEN_CORE_RESET_FEATURES 0xB4
-+
-+/** This command forces the PCD to write the deferred values of a Core Features */
-+#define VEN_CORE_ACTIVATE_FEATURES 0xB5
-+
-+/** This request reads a DWORD value from a register at the specified offset */
-+#define VEN_CORE_READ_REGISTER 0xB6
-+
-+/** This request writes a DWORD value into a register at the specified offset */
-+#define VEN_CORE_WRITE_REGISTER 0xB7
-+
-+/** This structure is the header of the Core Features dataset returned to
-+ * the Host
-+ */
-+struct cfi_all_features_header {
-+/** The features header structure length is */
-+#define CFI_ALL_FEATURES_HDR_LEN 8
-+ /**
-+ * The total length of the features dataset returned to the Host
-+ */
-+ uint16_t wTotalLen;
-+
-+ /**
-+ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
-+ * This field identifies the version of the CFI Specification with which
-+ * the device is compliant.
-+ */
-+ uint16_t wVersion;
-+
-+ /** The ID of the Core */
-+ uint16_t wCoreID;
-+#define CFI_CORE_ID_UDC 1
-+#define CFI_CORE_ID_OTG 2
-+#define CFI_CORE_ID_WUDEV 3
-+
-+ /** Number of features returned by VEN_CORE_GET_FEATURES request */
-+ uint16_t wNumFeatures;
-+} UPACKED;
-+
-+typedef struct cfi_all_features_header cfi_all_features_header_t;
-+
-+/** This structure is a header of the Core Feature descriptor dataset returned to
-+ * the Host after the VEN_CORE_GET_FEATURES request
-+ */
-+struct cfi_feature_desc_header {
-+#define CFI_FEATURE_DESC_HDR_LEN 8
-+
-+ /** The feature ID */
-+ uint16_t wFeatureID;
-+
-+ /** Length of this feature descriptor in bytes - including the
-+ * length of the feature name string
-+ */
-+ uint16_t wLength;
-+
-+ /** The data length of this feature in bytes */
-+ uint16_t wDataLength;
-+
-+ /**
-+ * Attributes of this features
-+ * D0: Access rights
-+ * 0 - Read/Write
-+ * 1 - Read only
-+ */
-+ uint8_t bmAttributes;
-+#define CFI_FEATURE_ATTR_RO 1
-+#define CFI_FEATURE_ATTR_RW 0
-+
-+ /** Length of the feature name in bytes */
-+ uint8_t bNameLen;
-+
-+ /** The feature name buffer */
-+ //uint8_t *name;
-+} UPACKED;
-+
-+typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
-+
-+/**
-+ * This structure describes a NULL terminated string referenced by its id field.
-+ * It is very similar to usb_string structure but has the id field type set to 16-bit.
-+ */
-+struct cfi_string {
-+ uint16_t id;
-+ const uint8_t *s;
-+};
-+typedef struct cfi_string cfi_string_t;
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_adp.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_adp.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,854 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
-+ * $Revision: #12 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_adp.h"
-+
-+/** @file
-+ *
-+ * This file contains the most of the Attach Detect Protocol implementation for
-+ * the driver to support OTG Rev2.0.
-+ *
-+ */
-+
-+void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
-+{
-+ adpctl_data_t adpctl;
-+
-+ adpctl.d32 = value;
-+ adpctl.b.ar = 0x2;
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
-+
-+ while (adpctl.b.ar) {
-+ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
-+ }
-+
-+}
-+
-+/**
-+ * Function is called to read ADP registers
-+ */
-+uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ adpctl.d32 = 0;
-+ adpctl.b.ar = 0x1;
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
-+
-+ while (adpctl.b.ar) {
-+ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
-+ }
-+
-+ return adpctl.d32;
-+}
-+
-+/**
-+ * Function is called to read ADPCTL register and filter Write-clear bits
-+ */
-+uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_tmout_int = 0;
-+ adpctl.b.adp_prb_int = 0;
-+ adpctl.b.adp_tmout_int = 0;
-+
-+ return adpctl.d32;
-+}
-+
-+/**
-+ * Function is called to write ADP registers
-+ */
-+void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
-+ uint32_t set)
-+{
-+ dwc_otg_adp_write_reg(core_if,
-+ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
-+}
-+
-+static void adp_sense_timeout(void *ptr)
-+{
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+ core_if->adp.sense_timer_started = 0;
-+ DWC_PRINTF("ADP SENSE TIMEOUT\n");
-+ if (core_if->adp_enable) {
-+ dwc_otg_adp_sense_stop(core_if);
-+ dwc_otg_adp_probe_start(core_if);
-+ }
-+}
-+
-+/**
-+ * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
-+ */
-+static void adp_vbuson_timeout(void *ptr)
-+{
-+ gpwrdn_data_t gpwrdn;
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
-+ if (core_if) {
-+ core_if->adp.vbuson_timer_started = 0;
-+ /* Turn off vbus */
-+ hprt0.b.prtpwr = 1;
-+ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
-+ gpwrdn.d32 = 0;
-+
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ /* Enable Wakeup Logic */
-+// gpwrdn.b.wkupactiv = 1;
-+ gpwrdn.b.pmuactv = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+
-+ /* Suspend the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ /* Switch on VDD */
-+// gpwrdn.b.wkupactiv = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+ } else {
-+ /* Enable Power Down Logic */
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+ }
-+
-+ /* Unmask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+
-+ dwc_otg_adp_probe_start(core_if);
-+ dwc_otg_dump_global_registers(core_if);
-+ dwc_otg_dump_host_registers(core_if);
-+ }
-+
-+}
-+
-+/**
-+ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
-+ * not asserted within 1.1 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->adp.vbuson_timer_started = 1;
-+ if (core_if->adp.vbuson_timer)
-+ {
-+ DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
-+ /* 1.1 secs + 60ms necessary for cil_hcd_start*/
-+ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
-+ } else {
-+ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
-+ }
-+}
-+
-+#if 0
-+/**
-+ * Masks all DWC OTG core interrupts
-+ *
-+ */
-+static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+
-+ /* Mask Host Interrupts */
-+
-+ /* Clear and disable HCINTs */
-+ for (i = 0; i < core_if->core_params->host_channels; i++) {
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
-+
-+ }
-+
-+ /* Clear and disable HAINT */
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
-+
-+ /* Mask Device Interrupts */
-+ if (!core_if->multiproc_int_enable) {
-+ /* Clear and disable IN Endpoint interrupts */
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
-+ diepint, 0xFFFFFFFF);
-+ }
-+
-+ /* Clear and disable OUT Endpoint interrupts */
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
-+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
-+ doepint, 0xFFFFFFFF);
-+ }
-+
-+ /* Clear and disable DAINT */
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
-+ 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
-+ } else {
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ diepeachintmsk[i], 0);
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
-+ diepint, 0xFFFFFFFF);
-+ }
-+
-+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[i], 0);
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
-+ doepint, 0xFFFFFFFF);
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+ 0);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
-+ 0xFFFFFFFF);
-+
-+ }
-+
-+ /* Disable interrupts */
-+ ahbcfg.b.glblintrmsk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+
-+ /* Disable all interrupts. */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Clear any pending OTG Interrupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
-+}
-+
-+/**
-+ * Unmask Port Connection Detected interrupt
-+ *
-+ */
-+static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
-+}
-+#endif
-+
-+/**
-+ * Starts the ADP Probing
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ */
-+uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
-+{
-+
-+ adpctl_data_t adpctl = {.d32 = 0};
-+ gpwrdn_data_t gpwrdn;
-+#if 0
-+ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
-+ .b.adp_sns_int = 1, b.adp_tmout_int};
-+#endif
-+ dwc_otg_disable_global_interrupts(core_if);
-+ DWC_PRINTF("ADP Probe Start\n");
-+ core_if->adp.probe_enabled = 1;
-+
-+ adpctl.b.adpres = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ while (adpctl.b.adpres) {
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ }
-+
-+ adpctl.d32 = 0;
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ /* In Host mode unmask SRP detected interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.sts_chngint_msk = 1;
-+ if (!gpwrdn.b.idsts) {
-+ gpwrdn.b.srp_det_msk = 1;
-+ }
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+
-+ adpctl.b.adp_tmout_int_msk = 1;
-+ adpctl.b.adp_prb_int_msk = 1;
-+ adpctl.b.prb_dschg = 1;
-+ adpctl.b.prb_delta = 1;
-+ adpctl.b.prb_per = 1;
-+ adpctl.b.adpen = 1;
-+ adpctl.b.enaprb = 1;
-+
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+ DWC_PRINTF("ADP Probe Finish\n");
-+ return 0;
-+}
-+
-+/**
-+ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
-+ * within 3 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->adp.sense_timer_started = 1;
-+ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
-+}
-+
-+/**
-+ * Starts the ADP Sense
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ DWC_PRINTF("ADP Sense Start\n");
-+
-+ /* Unmask ADP sense interrupt and mask all other from the core */
-+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+ adpctl.b.adp_sns_int_msk = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+ dwc_otg_disable_global_interrupts(core_if); // vahrama
-+
-+ /* Set ADP reset bit*/
-+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+ adpctl.b.adpres = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ while (adpctl.b.adpres) {
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ }
-+
-+ adpctl.b.adpres = 0;
-+ adpctl.b.adpen = 1;
-+ adpctl.b.enasns = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ dwc_otg_adp_sense_timer_start(core_if);
-+
-+ return 0;
-+}
-+
-+/**
-+ * Stops the ADP Probing
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
-+{
-+
-+ adpctl_data_t adpctl;
-+ DWC_PRINTF("Stop ADP probe\n");
-+ core_if->adp.probe_enabled = 0;
-+ core_if->adp.probe_counter = 0;
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+
-+ adpctl.b.adpen = 0;
-+ adpctl.b.adp_prb_int = 1;
-+ adpctl.b.adp_tmout_int = 1;
-+ adpctl.b.adp_sns_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * Stops the ADP Sensing
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ core_if->adp.sense_enabled = 0;
-+
-+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+ adpctl.b.enasns = 0;
-+ adpctl.b.adp_sns_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * Called to turn on the VBUS after initial ADP probe in host mode.
-+ * If port power was already enabled in cil_hcd_start function then
-+ * only schedule a timer.
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ */
-+void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
-+
-+ if (hprt0.b.prtpwr == 0) {
-+ hprt0.b.prtpwr = 1;
-+ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+
-+ dwc_otg_adp_vbuson_timer_start(core_if);
-+}
-+
-+/**
-+ * Called right after driver is loaded
-+ * to perform initial actions for ADP
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
-+ */
-+void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
-+{
-+ gpwrdn_data_t gpwrdn;
-+
-+ DWC_PRINTF("ADP Initial Start\n");
-+ core_if->adp.adp_started = 1;
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+ dwc_otg_disable_global_interrupts(core_if);
-+ if (is_host) {
-+ DWC_PRINTF("HOST MODE\n");
-+ /* Enable Power Down Logic Interrupt*/
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ /* Initialize first ADP probe to obtain Ramp Time value */
-+ core_if->adp.initial_probe = 1;
-+ dwc_otg_adp_probe_start(core_if);
-+ } else {
-+ gotgctl_data_t gotgctl;
-+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ DWC_PRINTF("DEVICE MODE\n");
-+ if (gotgctl.b.bsesvld == 0) {
-+ /* Enable Power Down Logic Interrupt*/
-+ gpwrdn.d32 = 0;
-+ DWC_PRINTF("VBUS is not valid - start ADP probe\n");
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ core_if->adp.initial_probe = 1;
-+ dwc_otg_adp_probe_start(core_if);
-+ } else {
-+ DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ dwc_otg_dump_global_registers(core_if);
-+ dwc_otg_dump_dev_registers(core_if);
-+ }
-+ }
-+}
-+
-+void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->adp.adp_started = 0;
-+ core_if->adp.initial_probe = 0;
-+ core_if->adp.probe_timer_values[0] = -1;
-+ core_if->adp.probe_timer_values[1] = -1;
-+ core_if->adp.probe_enabled = 0;
-+ core_if->adp.sense_enabled = 0;
-+ core_if->adp.sense_timer_started = 0;
-+ core_if->adp.vbuson_timer_started = 0;
-+ core_if->adp.probe_counter = 0;
-+ core_if->adp.gpwrdn = 0;
-+ core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
-+ /* Initialize timers */
-+ core_if->adp.sense_timer =
-+ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
-+ core_if->adp.vbuson_timer =
-+ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
-+ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
-+ {
-+ DWC_ERROR("Could not allocate memory for ADP timers\n");
-+ }
-+}
-+
-+void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ if (core_if->adp.probe_enabled)
-+ dwc_otg_adp_probe_stop(core_if);
-+ if (core_if->adp.sense_enabled)
-+ dwc_otg_adp_sense_stop(core_if);
-+ if (core_if->adp.sense_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+ if (core_if->adp.vbuson_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
-+ DWC_TIMER_FREE(core_if->adp.sense_timer);
-+ DWC_TIMER_FREE(core_if->adp.vbuson_timer);
-+}
-+
-+/////////////////////////////////////////////////////////////////////
-+////////////// ADP Interrupt Handlers ///////////////////////////////
-+/////////////////////////////////////////////////////////////////////
-+/**
-+ * This function sets Ramp Timer values
-+ */
-+static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ if (core_if->adp.probe_timer_values[0] == -1) {
-+ core_if->adp.probe_timer_values[0] = val;
-+ core_if->adp.probe_timer_values[1] = -1;
-+ return 1;
-+ } else {
-+ core_if->adp.probe_timer_values[1] =
-+ core_if->adp.probe_timer_values[0];
-+ core_if->adp.probe_timer_values[0] = val;
-+ return 0;
-+ }
-+}
-+
-+/**
-+ * This function compares Ramp Timer values
-+ */
-+static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t diff;
-+ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
-+ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
-+ else
-+ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
-+ if(diff < 2) {
-+ return 0;
-+ } else {
-+ return 1;
-+ }
-+}
-+
-+/**
-+ * This function handles ADP Probe Interrupts
-+ */
-+static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
-+ uint32_t val)
-+{
-+ adpctl_data_t adpctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn, temp;
-+ adpctl.d32 = val;
-+
-+ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ core_if->adp.probe_counter++;
-+ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (adpctl.b.rtim == 0 && !temp.b.idsts){
-+ DWC_PRINTF("RTIM value is 0\n");
-+ goto exit;
-+ }
-+ if (set_timer_value(core_if, adpctl.b.rtim) &&
-+ core_if->adp.initial_probe) {
-+ core_if->adp.initial_probe = 0;
-+ dwc_otg_adp_probe_stop(core_if);
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* check which value is for device mode and which for Host mode */
-+ if (!temp.b.idsts) { /* considered host mode value is 0 */
-+ /*
-+ * Turn on VBUS after initial ADP probe.
-+ */
-+ core_if->op_state = A_HOST;
-+ dwc_otg_enable_global_interrupts(core_if);
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_start(core_if);
-+ dwc_otg_adp_turnon_vbus(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ } else {
-+ /*
-+ * Initiate SRP after initial ADP probe.
-+ */
-+ dwc_otg_enable_global_interrupts(core_if);
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+ } else if (core_if->adp.probe_counter > 2){
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (compare_timer_values(core_if)) {
-+ DWC_PRINTF("Difference in timer values !!! \n");
-+// core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Power on the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ /* check which value is for device mode and which for Host mode */
-+ if (!temp.b.idsts) { /* considered host mode value is 0 */
-+ /* Disable Interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ } else {
-+ gotgctl_data_t gotgctl;
-+ /* Mask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Disable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Device mode.
-+ */
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+
-+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ if (!gotgctl.b.bsesvld) {
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+ }
-+ }
-+ if (core_if->power_down == 2) {
-+ if (gpwrdn.b.bsessvld) {
-+ /* Mask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Disable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Device mode.
-+ */
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ }
-+ }
-+ }
-+exit:
-+ /* Clear interrupt */
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_prb_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function hadles ADP Sense Interrupt
-+ */
-+static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+ /* Stop ADP Sense timer */
-+ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+
-+ /* Restart ADP Sense timer */
-+ dwc_otg_adp_sense_timer_start(core_if);
-+
-+ /* Clear interrupt */
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_sns_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function handles ADP Probe Interrupts
-+ */
-+static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
-+ uint32_t val)
-+{
-+ adpctl_data_t adpctl = {.d32 = 0 };
-+ adpctl.d32 = val;
-+ set_timer_value(core_if, adpctl.b.rtim);
-+
-+ /* Clear interrupt */
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_tmout_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * ADP Interrupt handler.
-+ *
-+ */
-+int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
-+{
-+ int retval = 0;
-+ adpctl_data_t adpctl = {.d32 = 0};
-+
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
-+
-+ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
-+ DWC_PRINTF("ADP Sense interrupt\n");
-+ retval |= dwc_otg_adp_handle_sns_intr(core_if);
-+ }
-+ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
-+ DWC_PRINTF("ADP timeout interrupt\n");
-+ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
-+ }
-+ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
-+ DWC_PRINTF("ADP Probe interrupt\n");
-+ adpctl.b.adp_prb_int = 1;
-+ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
-+ }
-+
-+// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
-+ //dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+ DWC_PRINTF("RETURN FROM ADP ISR\n");
-+
-+ return retval;
-+}
-+
-+/**
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
-+{
-+
-+#ifndef DWC_HOST_ONLY
-+ hprt0_data_t hprt0;
-+ gpwrdn_data_t gpwrdn;
-+ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ /* check which value is for device mode and which for Host mode */
-+ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */
-+ DWC_PRINTF("SRP: Host mode\n");
-+
-+ if (core_if->adp_enable) {
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Power on the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+
-+ /* Turn on the port power bit. */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Start the Connection timer. So a message can be displayed
-+ * if connect does not occur within 10 seconds. */
-+ cil_hcd_session_start(core_if);
-+ } else {
-+ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
-+ if (core_if->adp_enable) {
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Power on the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 0;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ }
-+ }
-+#endif
-+ return 1;
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_adp.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_adp.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,80 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
-+ * $Revision: #7 $
-+ * $Date: 2011/10/24 $
-+ * $Change: 1871159 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_ADP_H__
-+#define __DWC_OTG_ADP_H__
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the Attach Detect Protocol interfaces and defines
-+ * (functions) and structures for Linux.
-+ *
-+ */
-+
-+#define DWC_OTG_ADP_UNATTACHED 0
-+#define DWC_OTG_ADP_ATTACHED 1
-+#define DWC_OTG_ADP_UNKOWN 2
-+
-+typedef struct dwc_otg_adp {
-+ uint32_t adp_started;
-+ uint32_t initial_probe;
-+ int32_t probe_timer_values[2];
-+ uint32_t probe_enabled;
-+ uint32_t sense_enabled;
-+ dwc_timer_t *sense_timer;
-+ uint32_t sense_timer_started;
-+ dwc_timer_t *vbuson_timer;
-+ uint32_t vbuson_timer_started;
-+ uint32_t attached;
-+ uint32_t probe_counter;
-+ uint32_t gpwrdn;
-+} dwc_otg_adp_t;
-+
-+/**
-+ * Attach Detect Protocol functions
-+ */
-+
-+extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
-+extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
-+extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
-+extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
-+extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
-+
-+#endif //__DWC_OTG_ADP_H__
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_attr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_attr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,1210 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
-+ * $Revision: #44 $
-+ * $Date: 2010/11/29 $
-+ * $Change: 1636033 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing. The Linux driver attributes
-+ * feature will be used to provide the Linux Diagnostic
-+ * Interface. These attributes are accessed through sysfs.
-+ */
-+
-+/** @page "Linux Module Attributes"
-+ *
-+ * The Linux module attributes feature is used to provide the Linux
-+ * Diagnostic Interface. These attributes are accessed through sysfs.
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing.
-+
-+ The following table shows the attributes.
-+ <table>
-+ <tr>
-+ <td><b> Name</b></td>
-+ <td><b> Description</b></td>
-+ <td><b> Access</b></td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode </td>
-+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnpcapable </td>
-+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srpcapable </td>
-+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hsic_connect </td>
-+ <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> inv_sel_hsic </td>
-+ <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnp </td>
-+ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srp </td>
-+ <td> Initiates the Session Request Protocol. Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> buspower </td>
-+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> bussuspend </td>
-+ <td> Suspends the USB bus.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> busconnected </td>
-+ <td> Gets the connection status of the bus</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gotgctl </td>
-+ <td> Gets or sets the Core Control Status Register.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gusbcfg </td>
-+ <td> Gets or sets the Core USB Configuration Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> grxfsiz </td>
-+ <td> Gets or sets the Receive FIFO Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gnptxfsiz </td>
-+ <td> Gets or sets the non-periodic Transmit Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gpvndctl </td>
-+ <td> Gets or sets the PHY Vendor Control Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> ggpio </td>
-+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
-+ or sets the upper 16 bits.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> guid </td>
-+ <td> Gets or sets the value of the User ID Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gsnpsid </td>
-+ <td> Gets the value of the Synopsys ID Regester</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> devspeed </td>
-+ <td> Gets or sets the device speed setting in the DCFG register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> enumspeed </td>
-+ <td> Gets the device enumeration Speed.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hptxfsiz </td>
-+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hprt0 </td>
-+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regoffset </td>
-+ <td> Sets the register offset for the next Register Access</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regvalue </td>
-+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> remote_wakeup </td>
-+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
-+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
-+ Wakeup signalling bit in the Device Control Register is set for 1
-+ milli-second.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rem_wakeup_pwrdn </td>
-+ <td> On read, shows the status core - hibernated or not. On write, initiates
-+ a remote wakeup of the device from Hibernation. </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode_ch_tim_en </td>
-+ <td> This bit is used to enable or disable the host core to wait for 200 PHY
-+ clock cycles at the end of Resume to change the opmode signal to the PHY to 00
-+ after Suspend or LPM. </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> fr_interval </td>
-+ <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
-+ reload HFIR register during runtime. The application can write a value to this
-+ register only after the Port Enable bit of the Host Port Control and Status
-+ register (HPRT.PrtEnaPort) has been set </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> disconnect_us </td>
-+ <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
-+ which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> spramdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcddump </td>
-+ <td> Dumps the current HCD state.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcd_frrem </td>
-+ <td> Shows the average value of the Frame Remaining
-+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
-+ occurs. This can be used to determine the average interrupt latency. Also
-+ shows the average Frame Remaining value for start_transfer and the "a" and
-+ "b" sample points. The "a" and "b" sample points may be used during debugging
-+ bto determine how long it takes to execute a section of the HCD code.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rd_reg_test </td>
-+ <td> Displays the time required to read the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is read).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> wr_reg_test </td>
-+ <td> Displays the time required to write the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is written).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> lpm_response </td>
-+ <td> Gets or sets lpm_response mode. Applicable only in device mode.
-+ <td> Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> sleep_status </td>
-+ <td> Shows sleep status of device.
-+ <td> Read</td>
-+ </tr>
-+
-+ </table>
-+
-+ Example usage:
-+ To get the current mode:
-+ cat /sys/devices/lm0/mode
-+
-+ To power down the USB:
-+ echo 0 > /sys/devices/lm0/buspower
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_os.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_hcd_if.h"
-+
-+/*
-+ * MACROs for defining sysfs attribute
-+ */
-+#ifdef LM_INTERFACE
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+ return count; \
-+}
-+
-+#elif defined(PCI_INTERFACE)
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+ return count; \
-+}
-+
-+#elif defined(PLATFORM_INTERFACE)
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct platform_device *platform_dev = \
-+ container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t val; \
-+ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
-+ __func__, _dev, platform_dev, otg_dev); \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+ return count; \
-+}
-+#endif
-+
-+/*
-+ * MACROs for defining sysfs attribute for 32-bit registers
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+ return count; \
-+}
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+ return count; \
-+}
-+
-+#elif defined(PLATFORM_INTERFACE)
-+#include "dwc_otg_dbg.h"
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t val; \
-+ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
-+ __func__, _dev, platform_dev, otg_dev); \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+ return count; \
-+}
-+
-+#endif
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+/** @name Functions for Show/Store of Attributes */
-+/**@{*/
-+
-+/**
-+ * Helper function returning the otg_device structure of the given device
-+ */
-+static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
-+{
-+ dwc_otg_device_t *otg_dev;
-+ DWC_OTG_GETDRVDEV(otg_dev, _dev);
-+ return otg_dev;
-+}
-+
-+/**
-+ * Show the register offset of the Register Access.
-+ */
-+static ssize_t regoffset_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
-+ otg_dev->os_dep.reg_offset);
-+}
-+
-+/**
-+ * Set the register offset for the next Register Access Read/Write
-+ */
-+static ssize_t regoffset_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t offset = simple_strtoul(buf, NULL, 16);
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+ if (offset < SZ_256K) {
-+#elif defined(PCI_INTERFACE)
-+ if (offset < 0x00040000) {
-+#endif
-+ otg_dev->os_dep.reg_offset = offset;
-+ } else {
-+ dev_err(_dev, "invalid offset\n");
-+ }
-+
-+ return count;
-+}
-+
-+DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
-+
-+/**
-+ * Show the value of the register at the offset in the reg_offset
-+ * attribute.
-+ */
-+static ssize_t regvalue_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val;
-+ volatile uint32_t *addr;
-+
-+ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
-+ /* Calculate the address */
-+ addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
-+ (uint8_t *) otg_dev->os_dep.base);
-+ val = DWC_READ_REG32(addr);
-+ return snprintf(buf,
-+ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
-+ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
-+ val);
-+ } else {
-+ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
-+ return sprintf(buf, "invalid offset\n");
-+ }
-+}
-+
-+/**
-+ * Store the value in the register at the offset in the reg_offset
-+ * attribute.
-+ *
-+ */
-+static ssize_t regvalue_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ volatile uint32_t *addr;
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
-+ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
-+ /* Calculate the address */
-+ addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
-+ (uint8_t *) otg_dev->os_dep.base);
-+ DWC_WRITE_REG32(addr, val);
-+ } else {
-+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
-+ otg_dev->os_dep.reg_offset);
-+ }
-+ return count;
-+}
-+
-+DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
-+
-+/*
-+ * Attributes
-+ */
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
-+
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
-+ &(otg_dev->core_if->core_global_regs->gusbcfg),
-+ "GUSBCFG");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
-+ &(otg_dev->core_if->core_global_regs->grxfsiz),
-+ "GRXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
-+ &(otg_dev->core_if->core_global_regs->gnptxfsiz),
-+ "GNPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
-+ &(otg_dev->core_if->core_global_regs->gpvndctl),
-+ "GPVNDCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
-+ &(otg_dev->core_if->core_global_regs->ggpio),
-+ "GGPIO");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
-+ "GUID");
-+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
-+ &(otg_dev->core_if->core_global_regs->gsnpsid),
-+ "GSNPSID");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
-+ &(otg_dev->core_if->core_global_regs->hptxfsiz),
-+ "HPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
-+
-+/**
-+ * @todo Add code to initiate the HNP.
-+ */
-+/**
-+ * Show the HNP status bit
-+ */
-+static ssize_t hnp_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "HstNegScs = 0x%x\n",
-+ dwc_otg_get_hnpstatus(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the HNP Request bit
-+ */
-+static ssize_t hnp_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_hnpreq(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
-+
-+/**
-+ * @todo Add code to initiate the SRP.
-+ */
-+/**
-+ * Show the SRP status bit
-+ */
-+static ssize_t srp_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "SesReqScs = 0x%x\n",
-+ dwc_otg_get_srpstatus(otg_dev->core_if));
-+#else
-+ return sprintf(buf, "Host Only Mode!\n");
-+#endif
-+}
-+
-+/**
-+ * Set the SRP Request bit
-+ */
-+static ssize_t srp_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_pcd_initiate_srp(otg_dev->pcd);
-+#endif
-+ return count;
-+}
-+
-+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
-+
-+/**
-+ * @todo Need to do more for power on/off?
-+ */
-+/**
-+ * Show the Bus Power status
-+ */
-+static ssize_t buspower_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Bus Power = 0x%x\n",
-+ dwc_otg_get_prtpower(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Bus Power status
-+ */
-+static ssize_t buspower_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t on = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_prtpower(otg_dev->core_if, on);
-+ return count;
-+}
-+
-+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
-+
-+/**
-+ * @todo Need to do more for suspend?
-+ */
-+/**
-+ * Show the Bus Suspend status
-+ */
-+static ssize_t bussuspend_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Bus Suspend = 0x%x\n",
-+ dwc_otg_get_prtsuspend(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Bus Suspend status
-+ */
-+static ssize_t bussuspend_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_prtsuspend(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
-+
-+/**
-+ * Show the Mode Change Ready Timer status
-+ */
-+static ssize_t mode_ch_tim_en_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
-+ dwc_otg_get_mode_ch_tim(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Mode Change Ready Timer status
-+ */
-+static ssize_t mode_ch_tim_en_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
-+
-+/**
-+ * Show the value of HFIR Frame Interval bitfield
-+ */
-+static ssize_t fr_interval_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Frame Interval = 0x%x\n",
-+ dwc_otg_get_fr_interval(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the HFIR Frame Interval value
-+ */
-+static ssize_t fr_interval_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 10);
-+ dwc_otg_set_fr_interval(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
-+
-+/**
-+ * Show the status of Remote Wakeup.
-+ */
-+static ssize_t remote_wakeup_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ return sprintf(buf,
-+ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
-+ dwc_otg_get_remotewakesig(otg_dev->core_if),
-+ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
-+ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
-+#else
-+ return sprintf(buf, "Host Only Mode!\n");
-+#endif /* DWC_HOST_ONLY */
-+}
-+
-+/**
-+ * Initiate a remote wakeup of the host. The Device control register
-+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
-+ * flag is set.
-+ *
-+ */
-+static ssize_t remote_wakeup_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+
-+ if (val & 1) {
-+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
-+ } else {
-+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
-+ }
-+#endif /* DWC_HOST_ONLY */
-+ return count;
-+}
-+
-+DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
-+ remote_wakeup_store);
-+
-+/**
-+ * Show the whether core is hibernated or not.
-+ */
-+static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ if (dwc_otg_get_core_state(otg_dev->core_if)) {
-+ DWC_PRINTF("Core is in hibernation\n");
-+ } else {
-+ DWC_PRINTF("Core is not in hibernation\n");
-+ }
-+#endif /* DWC_HOST_ONLY */
-+ return 0;
-+}
-+
-+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset);
-+
-+/**
-+ * Initiate a remote wakeup of the device to exit from hibernation.
-+ */
-+static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
-+#endif
-+ return count;
-+}
-+
-+DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
-+ rem_wakeup_pwrdn_store);
-+
-+static ssize_t disconnect_us(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+ DWC_PRINTF("The Passed value is %04x\n", val);
-+
-+ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
-+
-+#endif /* DWC_HOST_ONLY */
-+ return count;
-+}
-+
-+DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t regdump_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ dwc_otg_dump_global_registers(otg_dev->core_if);
-+ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
-+ dwc_otg_dump_host_registers(otg_dev->core_if);
-+ } else {
-+ dwc_otg_dump_dev_registers(otg_dev->core_if);
-+
-+ }
-+ return sprintf(buf, "Register Dump\n");
-+}
-+
-+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t spramdump_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ //dwc_otg_dump_spram(otg_dev->core_if);
-+
-+ return sprintf(buf, "SPRAM Dump\n");
-+}
-+
-+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
-+
-+/**
-+ * Dump the current hcd state.
-+ */
-+static ssize_t hcddump_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_hcd_dump_state(otg_dev->hcd);
-+#endif /* DWC_DEVICE_ONLY */
-+ return sprintf(buf, "HCD Dump\n");
-+}
-+
-+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ */
-+static ssize_t hcd_frrem_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ dwc_otg_hcd_dump_frrem(otg_dev->hcd);
-+#endif /* DWC_DEVICE_ONLY */
-+ return sprintf(buf, "HCD Dump Frame Remaining\n");
-+}
-+
-+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
-+
-+/**
-+ * Displays the time required to read the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is read).
-+ */
-+#define RW_REG_COUNT 10000000
-+#define MSEC_PER_JIFFIE 1000/HZ
-+static ssize_t rd_reg_test_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ int i;
-+ int time;
-+ int start_jiffies;
-+
-+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+ start_jiffies = jiffies;
-+ for (i = 0; i < RW_REG_COUNT; i++) {
-+ dwc_otg_get_gnptxfsiz(otg_dev->core_if);
-+ }
-+ time = jiffies - start_jiffies;
-+ return sprintf(buf,
-+ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
-+
-+/**
-+ * Displays the time required to write the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is written).
-+ */
-+static ssize_t wr_reg_test_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t reg_val;
-+ int i;
-+ int time;
-+ int start_jiffies;
-+
-+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
-+ start_jiffies = jiffies;
-+ for (i = 0; i < RW_REG_COUNT; i++) {
-+ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
-+ }
-+ time = jiffies - start_jiffies;
-+ return sprintf(buf,
-+ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+
-+/**
-+* Show the lpm_response attribute.
-+*/
-+static ssize_t lpmresp_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
-+ return sprintf(buf, "** LPM is DISABLED **\n");
-+
-+ if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
-+ return sprintf(buf, "** Current mode is not device mode\n");
-+ }
-+ return sprintf(buf, "lpm_response = %d\n",
-+ dwc_otg_get_lpmresponse(otg_dev->core_if));
-+}
-+
-+/**
-+* Store the lpm_response attribute.
-+*/
-+static ssize_t lpmresp_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+
-+ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
-+ return 0;
-+ }
-+
-+ if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
-+ return 0;
-+ }
-+
-+ dwc_otg_set_lpmresponse(otg_dev->core_if, val);
-+ return count;
-+}
-+
-+DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
-+
-+/**
-+* Show the sleep_status attribute.
-+*/
-+static ssize_t sleepstatus_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Sleep Status = %d\n",
-+ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
-+}
-+
-+/**
-+ * Store the sleep_status attribure.
-+ */
-+static ssize_t sleepstatus_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
-+ if (dwc_otg_is_host_mode(core_if)) {
-+
-+ DWC_PRINTF("Host initiated resume\n");
-+ dwc_otg_set_prtresume(otg_dev->core_if, 1);
-+ }
-+ }
-+
-+ return count;
-+}
-+
-+DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
-+ sleepstatus_store);
-+
-+#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
-+
-+/**@}*/
-+
-+/**
-+ * Create the device files
-+ */
-+void dwc_otg_attr_create(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ )
-+{
-+ int error;
-+
-+ error = device_create_file(&dev->dev, &dev_attr_regoffset);
-+ error = device_create_file(&dev->dev, &dev_attr_regvalue);
-+ error = device_create_file(&dev->dev, &dev_attr_mode);
-+ error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
-+ error = device_create_file(&dev->dev, &dev_attr_srpcapable);
-+ error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
-+ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
-+ error = device_create_file(&dev->dev, &dev_attr_hnp);
-+ error = device_create_file(&dev->dev, &dev_attr_srp);
-+ error = device_create_file(&dev->dev, &dev_attr_buspower);
-+ error = device_create_file(&dev->dev, &dev_attr_bussuspend);
-+ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
-+ error = device_create_file(&dev->dev, &dev_attr_fr_interval);
-+ error = device_create_file(&dev->dev, &dev_attr_busconnected);
-+ error = device_create_file(&dev->dev, &dev_attr_gotgctl);
-+ error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
-+ error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
-+ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
-+ error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
-+ error = device_create_file(&dev->dev, &dev_attr_ggpio);
-+ error = device_create_file(&dev->dev, &dev_attr_guid);
-+ error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
-+ error = device_create_file(&dev->dev, &dev_attr_devspeed);
-+ error = device_create_file(&dev->dev, &dev_attr_enumspeed);
-+ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
-+ error = device_create_file(&dev->dev, &dev_attr_hprt0);
-+ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
-+ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
-+ error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
-+ error = device_create_file(&dev->dev, &dev_attr_regdump);
-+ error = device_create_file(&dev->dev, &dev_attr_spramdump);
-+ error = device_create_file(&dev->dev, &dev_attr_hcddump);
-+ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
-+ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
-+ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ error = device_create_file(&dev->dev, &dev_attr_lpm_response);
-+ error = device_create_file(&dev->dev, &dev_attr_sleep_status);
-+#endif
-+}
-+
-+/**
-+ * Remove the device files
-+ */
-+void dwc_otg_attr_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ )
-+{
-+ device_remove_file(&dev->dev, &dev_attr_regoffset);
-+ device_remove_file(&dev->dev, &dev_attr_regvalue);
-+ device_remove_file(&dev->dev, &dev_attr_mode);
-+ device_remove_file(&dev->dev, &dev_attr_hnpcapable);
-+ device_remove_file(&dev->dev, &dev_attr_srpcapable);
-+ device_remove_file(&dev->dev, &dev_attr_hsic_connect);
-+ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
-+ device_remove_file(&dev->dev, &dev_attr_hnp);
-+ device_remove_file(&dev->dev, &dev_attr_srp);
-+ device_remove_file(&dev->dev, &dev_attr_buspower);
-+ device_remove_file(&dev->dev, &dev_attr_bussuspend);
-+ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
-+ device_remove_file(&dev->dev, &dev_attr_fr_interval);
-+ device_remove_file(&dev->dev, &dev_attr_busconnected);
-+ device_remove_file(&dev->dev, &dev_attr_gotgctl);
-+ device_remove_file(&dev->dev, &dev_attr_gusbcfg);
-+ device_remove_file(&dev->dev, &dev_attr_grxfsiz);
-+ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
-+ device_remove_file(&dev->dev, &dev_attr_gpvndctl);
-+ device_remove_file(&dev->dev, &dev_attr_ggpio);
-+ device_remove_file(&dev->dev, &dev_attr_guid);
-+ device_remove_file(&dev->dev, &dev_attr_gsnpsid);
-+ device_remove_file(&dev->dev, &dev_attr_devspeed);
-+ device_remove_file(&dev->dev, &dev_attr_enumspeed);
-+ device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
-+ device_remove_file(&dev->dev, &dev_attr_hprt0);
-+ device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
-+ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
-+ device_remove_file(&dev->dev, &dev_attr_disconnect_us);
-+ device_remove_file(&dev->dev, &dev_attr_regdump);
-+ device_remove_file(&dev->dev, &dev_attr_spramdump);
-+ device_remove_file(&dev->dev, &dev_attr_hcddump);
-+ device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
-+ device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
-+ device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ device_remove_file(&dev->dev, &dev_attr_lpm_response);
-+ device_remove_file(&dev->dev, &dev_attr_sleep_status);
-+#endif
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_attr.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_attr.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,89 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
-+ * $Revision: #13 $
-+ * $Date: 2010/06/21 $
-+ * $Change: 1532021 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_ATTR_H__)
-+#define __DWC_OTG_ATTR_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux device attributes.
-+ */
-+extern struct device_attribute dev_attr_regoffset;
-+extern struct device_attribute dev_attr_regvalue;
-+
-+extern struct device_attribute dev_attr_mode;
-+extern struct device_attribute dev_attr_hnpcapable;
-+extern struct device_attribute dev_attr_srpcapable;
-+extern struct device_attribute dev_attr_hnp;
-+extern struct device_attribute dev_attr_srp;
-+extern struct device_attribute dev_attr_buspower;
-+extern struct device_attribute dev_attr_bussuspend;
-+extern struct device_attribute dev_attr_mode_ch_tim_en;
-+extern struct device_attribute dev_attr_fr_interval;
-+extern struct device_attribute dev_attr_busconnected;
-+extern struct device_attribute dev_attr_gotgctl;
-+extern struct device_attribute dev_attr_gusbcfg;
-+extern struct device_attribute dev_attr_grxfsiz;
-+extern struct device_attribute dev_attr_gnptxfsiz;
-+extern struct device_attribute dev_attr_gpvndctl;
-+extern struct device_attribute dev_attr_ggpio;
-+extern struct device_attribute dev_attr_guid;
-+extern struct device_attribute dev_attr_gsnpsid;
-+extern struct device_attribute dev_attr_devspeed;
-+extern struct device_attribute dev_attr_enumspeed;
-+extern struct device_attribute dev_attr_hptxfsiz;
-+extern struct device_attribute dev_attr_hprt0;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+extern struct device_attribute dev_attr_lpm_response;
-+extern struct device_attribute devi_attr_sleep_status;
-+#endif
-+
-+void dwc_otg_attr_create(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+
-+void dwc_otg_attr_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+#endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cfi.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,1876 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * This file contains the most of the CFI(Core Feature Interface)
-+ * implementation for the OTG.
-+ */
-+
-+#ifdef DWC_UTE_CFI
-+
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_cfi.h"
-+
-+/** This definition should actually migrate to the Portability Library */
-+#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
-+
-+extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
-+
-+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
-+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
-+ struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *ctrl_req);
-+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
-+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
-+
-+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
-+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
-+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
-+
-+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
-+
-+/** This is the header of the all features descriptor */
-+static cfi_all_features_header_t all_props_desc_header = {
-+ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
-+ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
-+ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
-+};
-+
-+/** This is an array of statically allocated feature descriptors */
-+static cfi_feature_desc_header_t prop_descs[] = {
-+
-+ /* FT_ID_DMA_MODE */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
-+ },
-+
-+ /* FT_ID_DMA_BUFFER_SETUP */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_DMA_BUFF_ALIGN */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ },
-+
-+ /* FT_ID_DMA_CONCAT_SETUP */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_DMA_CIRCULAR */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_THRESHOLD_SETUP */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_DFIFO_DEPTH */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
-+ .bmAttributes = CFI_FEATURE_ATTR_RO,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ },
-+
-+ /* FT_ID_TX_FIFO_DEPTH */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ },
-+
-+ /* FT_ID_RX_FIFO_DEPTH */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ }
-+};
-+
-+/** The table of feature names */
-+cfi_string_t prop_name_table[] = {
-+ {FT_ID_DMA_MODE, "dma_mode"},
-+ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
-+ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
-+ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
-+ {FT_ID_DMA_CIRCULAR, "buffer_circular"},
-+ {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
-+ {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
-+ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
-+ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
-+ {}
-+};
-+
-+/************************************************************************/
-+
-+/**
-+ * Returns the name of the feature by its ID
-+ * or NULL if no featute ID matches.
-+ *
-+ */
-+const uint8_t *get_prop_name(uint16_t prop_id, int *len)
-+{
-+ cfi_string_t *pstr;
-+ *len = 0;
-+
-+ for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
-+ if (pstr->id == prop_id) {
-+ *len = DWC_STRLEN(pstr->s);
-+ return pstr->s;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+/**
-+ * This function handles all CFI specific control requests.
-+ *
-+ * Return a negative value to stall the DCE.
-+ */
-+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
-+{
-+ int retval = 0;
-+ dwc_otg_pcd_ep_t *ep = NULL;
-+ cfiobject_t *cfi = pcd->cfi;
-+ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
-+ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
-+ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
-+ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
-+ uint32_t regaddr = 0;
-+ uint32_t regval = 0;
-+
-+ /* Save this Control Request in the CFI object.
-+ * The data field will be assigned in the data stage completion CB function.
-+ */
-+ cfi->ctrl_req = *ctrl;
-+ cfi->ctrl_req.data = NULL;
-+
-+ cfi->need_gadget_att = 0;
-+ cfi->need_status_in_complete = 0;
-+
-+ switch (ctrl->bRequest) {
-+ case VEN_CORE_GET_FEATURES:
-+ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
-+ if (retval >= 0) {
-+ //dump_msg(cfi->buf_in.buf, retval);
-+ ep = &pcd->ep0;
-+
-+ retval = min((uint16_t) retval, wLen);
-+ /* Transfer this buffer to the host through the EP0-IN EP */
-+ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_len = retval;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ }
-+ retval = 0;
-+ break;
-+
-+ case VEN_CORE_GET_FEATURE:
-+ CFI_INFO("VEN_CORE_GET_FEATURE\n");
-+ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
-+ pcd, ctrl);
-+ if (retval >= 0) {
-+ ep = &pcd->ep0;
-+
-+ retval = min((uint16_t) retval, wLen);
-+ /* Transfer this buffer to the host through the EP0-IN EP */
-+ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_len = retval;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ }
-+ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
-+ dump_msg(cfi->buf_in.buf, retval);
-+ break;
-+
-+ case VEN_CORE_SET_FEATURE:
-+ CFI_INFO("VEN_CORE_SET_FEATURE\n");
-+ /* Set up an XFER to get the data stage of the control request,
-+ * which is the new value of the feature to be modified.
-+ */
-+ ep = &pcd->ep0;
-+ ep->dwc_ep.is_in = 0;
-+ ep->dwc_ep.dma_addr = cfi->buf_out.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_len = wLen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ /* Read the control write's data stage */
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ retval = 0;
-+ break;
-+
-+ case VEN_CORE_RESET_FEATURES:
-+ CFI_INFO("VEN_CORE_RESET_FEATURES\n");
-+ cfi->need_gadget_att = 1;
-+ cfi->need_status_in_complete = 1;
-+ retval = cfi_preproc_reset(pcd, ctrl);
-+ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
-+ break;
-+
-+ case VEN_CORE_ACTIVATE_FEATURES:
-+ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
-+ break;
-+
-+ case VEN_CORE_READ_REGISTER:
-+ CFI_INFO("VEN_CORE_READ_REGISTER\n");
-+ /* wValue optionally contains the HI WORD of the register offset and
-+ * wIndex contains the LOW WORD of the register offset
-+ */
-+ if (wValue == 0) {
-+ /* @TODO - MAS - fix the access to the base field */
-+ regaddr = 0;
-+ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
-+ //GET_CORE_IF(pcd)->co
-+ regaddr |= wIndex;
-+ } else {
-+ regaddr = (wValue << 16) | wIndex;
-+ }
-+
-+ /* Read a 32-bit value of the memory at the regaddr */
-+ regval = DWC_READ_REG32((uint32_t *) regaddr);
-+
-+ ep = &pcd->ep0;
-+ dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
-+ ep->dwc_ep.is_in = 1;
-+ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_len = wLen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ cfi->need_gadget_att = 0;
-+ retval = 0;
-+ break;
-+
-+ case VEN_CORE_WRITE_REGISTER:
-+ CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
-+ /* Set up an XFER to get the data stage of the control request,
-+ * which is the new value of the register to be modified.
-+ */
-+ ep = &pcd->ep0;
-+ ep->dwc_ep.is_in = 0;
-+ ep->dwc_ep.dma_addr = cfi->buf_out.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_len = wLen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ /* Read the control write's data stage */
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ retval = 0;
-+ break;
-+
-+ default:
-+ retval = -DWC_E_NOT_SUPPORTED;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function prepares the core features descriptors and copies its
-+ * raw representation into the buffer <buf>.
-+ *
-+ * The buffer structure is as follows:
-+ * all_features_header (8 bytes)
-+ * features_#1 (8 bytes + feature name string length)
-+ * features_#2 (8 bytes + feature name string length)
-+ * .....
-+ * features_#n - where n=the total count of feature descriptors
-+ */
-+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
-+{
-+ cfi_feature_desc_header_t *prop_hdr = prop_descs;
-+ cfi_feature_desc_header_t *prop;
-+ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
-+ cfi_all_features_header_t *tmp;
-+ uint8_t *tmpbuf = buf;
-+ const uint8_t *pname = NULL;
-+ int i, j, namelen = 0, totlen;
-+
-+ /* Prepare and copy the core features into the buffer */
-+ CFI_INFO("%s:\n", __func__);
-+
-+ tmp = (cfi_all_features_header_t *) tmpbuf;
-+ *tmp = *all_props_hdr;
-+ tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
-+
-+ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
-+ for (i = 0; i < j; i++, prop_hdr++) {
-+ pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
-+ prop = (cfi_feature_desc_header_t *) tmpbuf;
-+ *prop = *prop_hdr;
-+
-+ prop->bNameLen = namelen;
-+ prop->wLength =
-+ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
-+ namelen);
-+
-+ tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
-+ dwc_memcpy(tmpbuf, pname, namelen);
-+ tmpbuf += namelen;
-+ }
-+
-+ totlen = tmpbuf - buf;
-+
-+ if (totlen > 0) {
-+ tmp = (cfi_all_features_header_t *) buf;
-+ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
-+ }
-+
-+ return totlen;
-+}
-+
-+/**
-+ * This function releases all the dynamic memory in the CFI object.
-+ */
-+static void cfi_release(cfiobject_t * cfiobj)
-+{
-+ cfi_ep_t *cfiep;
-+ dwc_list_link_t *tmp;
-+
-+ CFI_INFO("%s\n", __func__);
-+
-+ if (cfiobj->buf_in.buf) {
-+ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
-+ cfiobj->buf_in.addr);
-+ cfiobj->buf_in.buf = NULL;
-+ }
-+
-+ if (cfiobj->buf_out.buf) {
-+ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
-+ cfiobj->buf_out.addr);
-+ cfiobj->buf_out.buf = NULL;
-+ }
-+
-+ /* Free the Buffer Setup values for each EP */
-+ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ cfi_free_ep_bs_dyn_data(cfiep);
-+ }
-+}
-+
-+/**
-+ * This function frees the dynamically allocated EP buffer setup data.
-+ */
-+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
-+{
-+ if (cfiep->bm_sg) {
-+ DWC_FREE(cfiep->bm_sg);
-+ cfiep->bm_sg = NULL;
-+ }
-+
-+ if (cfiep->bm_align) {
-+ DWC_FREE(cfiep->bm_align);
-+ cfiep->bm_align = NULL;
-+ }
-+
-+ if (cfiep->bm_concat) {
-+ if (NULL != cfiep->bm_concat->wTxBytes) {
-+ DWC_FREE(cfiep->bm_concat->wTxBytes);
-+ cfiep->bm_concat->wTxBytes = NULL;
-+ }
-+ DWC_FREE(cfiep->bm_concat);
-+ cfiep->bm_concat = NULL;
-+ }
-+}
-+
-+/**
-+ * This function initializes the default values of the features
-+ * for a specific endpoint and should be called only once when
-+ * the EP is enabled first time.
-+ */
-+static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
-+{
-+ int retval = 0;
-+
-+ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
-+ if (NULL == cfiep->bm_sg) {
-+ CFI_INFO("Failed to allocate memory for SG feature value\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+
-+ /* For the Concatenation feature's default value we do not allocate
-+ * memory for the wTxBytes field - it will be done in the set_feature_value
-+ * request handler.
-+ */
-+ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
-+ if (NULL == cfiep->bm_concat) {
-+ CFI_INFO
-+ ("Failed to allocate memory for CONCATENATION feature value\n");
-+ DWC_FREE(cfiep->bm_sg);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
-+
-+ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
-+ if (NULL == cfiep->bm_align) {
-+ CFI_INFO
-+ ("Failed to allocate memory for Alignment feature value\n");
-+ DWC_FREE(cfiep->bm_sg);
-+ DWC_FREE(cfiep->bm_concat);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
-+
-+ return retval;
-+}
-+
-+/**
-+ * The callback function that notifies the CFI on the activation of
-+ * an endpoint in the PCD. The following steps are done in this function:
-+ *
-+ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
-+ * active endpoint)
-+ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
-+ * Set the Buffer Mode to standard
-+ * Initialize the default values for all EP modes (SG, Circular, Concat, Align)
-+ * Add the cfi_ep_t object to the list of active endpoints in the CFI object
-+ */
-+static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
-+ struct dwc_otg_pcd_ep *ep)
-+{
-+ cfi_ep_t *cfiep;
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+
-+ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
-+ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
-+ /* MAS - Check whether this endpoint already is in the list */
-+ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
-+
-+ if (NULL == cfiep) {
-+ /* Allocate a cfi_ep_t object */
-+ cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
-+ if (NULL == cfiep) {
-+ CFI_INFO
-+ ("Unable to allocate memory for <cfiep> in function %s\n",
-+ __func__);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
-+
-+ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
-+ cfiep->ep = ep;
-+
-+ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
-+ ep->dwc_ep.descs =
-+ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
-+ sizeof(dwc_otg_dma_desc_t),
-+ &ep->dwc_ep.descs_dma_addr);
-+
-+ if (NULL == ep->dwc_ep.descs) {
-+ DWC_FREE(cfiep);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_LIST_INIT(&cfiep->lh);
-+
-+ /* Set the buffer mode to BM_STANDARD. It will be modified
-+ * when building descriptors for a specific buffer mode */
-+ ep->dwc_ep.buff_mode = BM_STANDARD;
-+
-+ /* Create and initialize the default values for this EP's Buffer modes */
-+ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
-+ return retval;
-+
-+ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
-+ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
-+ retval = 0;
-+ } else { /* The sought EP already is in the list */
-+ CFI_INFO("%s: The sought EP already is in the list\n",
-+ __func__);
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function is called when the data stage of a 3-stage Control Write request
-+ * is complete.
-+ *
-+ */
-+static int cfi_ctrl_write_complete(struct cfiobject *cfi,
-+ struct dwc_otg_pcd *pcd)
-+{
-+ uint32_t addr, reg_value;
-+ uint16_t wIndex, wValue;
-+ uint8_t bRequest;
-+ uint8_t *buf = cfi->buf_out.buf;
-+ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
-+ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+
-+ CFI_INFO("%s\n", __func__);
-+
-+ bRequest = ctrl_req->bRequest;
-+ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
-+ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
-+
-+ /*
-+ * Save the pointer to the data stage in the ctrl_req's <data> field.
-+ * The request should be already saved in the command stage by now.
-+ */
-+ ctrl_req->data = cfi->buf_out.buf;
-+ cfi->need_status_in_complete = 0;
-+ cfi->need_gadget_att = 0;
-+
-+ switch (bRequest) {
-+ case VEN_CORE_WRITE_REGISTER:
-+ /* The buffer contains raw data of the new value for the register */
-+ reg_value = *((uint32_t *) buf);
-+ if (wValue == 0) {
-+ addr = 0;
-+ //addr = (uint32_t) pcd->otg_dev->os_dep.base;
-+ addr += wIndex;
-+ } else {
-+ addr = (wValue << 16) | wIndex;
-+ }
-+
-+ //writel(reg_value, addr);
-+
-+ retval = 0;
-+ cfi->need_status_in_complete = 1;
-+ break;
-+
-+ case VEN_CORE_SET_FEATURE:
-+ /* The buffer contains raw data of the new value of the feature */
-+ retval = cfi_set_feature_value(pcd);
-+ if (retval < 0)
-+ return retval;
-+
-+ cfi->need_status_in_complete = 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the SG buffer mode.
-+ */
-+static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
-+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
-+ dma_addr_t buff_addr = req->dma;
-+ int i;
-+ uint32_t txsize, off;
-+
-+ txsize = sgval->wSize;
-+ off = sgval->bOffset;
-+
-+// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
-+// __func__, cfiep->ep->ep.name, txsize, off);
-+
-+ for (i = 0; i < sgval->bCount; i++) {
-+ desc->status.b.bs = BS_HOST_BUSY;
-+ desc->buf = buff_addr;
-+ desc->status.b.l = 0;
-+ desc->status.b.ioc = 0;
-+ desc->status.b.sp = 0;
-+ desc->status.b.bytes = txsize;
-+ desc->status.b.bs = BS_HOST_READY;
-+
-+ /* Set the next address of the buffer */
-+ buff_addr += txsize + off;
-+ desc_last = desc;
-+ desc++;
-+ }
-+
-+ /* Set the last, ioc and sp bits on the Last DMA Descriptor */
-+ desc_last->status.b.l = 1;
-+ desc_last->status.b.ioc = 1;
-+ desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
-+ /* Save the last DMA descriptor pointer */
-+ cfiep->dma_desc_last = desc_last;
-+ cfiep->desc_count = sgval->bCount;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Concatenation buffer mode.
-+ */
-+static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
-+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
-+ dma_addr_t buff_addr = req->dma;
-+ int i;
-+ uint16_t *txsize;
-+
-+ txsize = concatval->wTxBytes;
-+
-+ for (i = 0; i < concatval->hdr.bDescCount; i++) {
-+ desc->buf = buff_addr;
-+ desc->status.b.bs = BS_HOST_BUSY;
-+ desc->status.b.l = 0;
-+ desc->status.b.ioc = 0;
-+ desc->status.b.sp = 0;
-+ desc->status.b.bytes = *txsize;
-+ desc->status.b.bs = BS_HOST_READY;
-+
-+ txsize++;
-+ /* Set the next address of the buffer */
-+ buff_addr += UGETW(ep->desc->wMaxPacketSize);
-+ desc_last = desc;
-+ desc++;
-+ }
-+
-+ /* Set the last, ioc and sp bits on the Last DMA Descriptor */
-+ desc_last->status.b.l = 1;
-+ desc_last->status.b.ioc = 1;
-+ desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
-+ cfiep->dma_desc_last = desc_last;
-+ cfiep->desc_count = concatval->hdr.bDescCount;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Circular buffer mode
-+ */
-+static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ /* @todo: MAS - add implementation when this feature needs to be tested */
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Alignment buffer mode
-+ */
-+static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+ ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
-+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+ dma_addr_t buff_addr = req->dma;
-+
-+ desc->status.b.bs = BS_HOST_BUSY;
-+ desc->status.b.l = 1;
-+ desc->status.b.ioc = 1;
-+ desc->status.b.sp = ep->dwc_ep.sent_zlp;
-+ desc->status.b.bytes = req->length;
-+ /* Adjust the buffer alignment */
-+ desc->buf = (buff_addr + alignval->bAlign);
-+ desc->status.b.bs = BS_HOST_READY;
-+ cfiep->dma_desc_last = desc;
-+ cfiep->desc_count = 1;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors chain for different modes of the
-+ * buffer setup of an endpoint.
-+ */
-+static void cfi_build_descriptors(struct cfiobject *cfi,
-+ struct dwc_otg_pcd *pcd,
-+ struct dwc_otg_pcd_ep *ep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ cfi_ep_t *cfiep;
-+
-+ /* Get the cfiep by the dwc_otg_pcd_ep */
-+ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Unable to find a matching active endpoint\n",
-+ __func__);
-+ return;
-+ }
-+
-+ cfiep->xfer_len = req->length;
-+
-+ /* Iterate through all the DMA descriptors */
-+ switch (cfiep->ep->dwc_ep.buff_mode) {
-+ case BM_SG:
-+ cfi_build_sg_descs(cfi, cfiep, req);
-+ break;
-+
-+ case BM_CONCAT:
-+ cfi_build_concat_descs(cfi, cfiep, req);
-+ break;
-+
-+ case BM_CIRCULAR:
-+ cfi_build_circ_descs(cfi, cfiep, req);
-+ break;
-+
-+ case BM_ALIGN:
-+ cfi_build_align_descs(cfi, cfiep, req);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+}
-+
-+/**
-+ * Allocate DMA buffer for different Buffer modes.
-+ */
-+static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
-+ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
-+ unsigned size, gfp_t flags)
-+{
-+ return DWC_DMA_ALLOC(size, dma);
-+}
-+
-+/**
-+ * This function initializes the CFI object.
-+ */
-+int init_cfi(cfiobject_t * cfiobj)
-+{
-+ CFI_INFO("%s\n", __func__);
-+
-+ /* Allocate a buffer for IN XFERs */
-+ cfiobj->buf_in.buf =
-+ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
-+ if (NULL == cfiobj->buf_in.buf) {
-+ CFI_INFO("Unable to allocate buffer for INs\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Allocate a buffer for OUT XFERs */
-+ cfiobj->buf_out.buf =
-+ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
-+ if (NULL == cfiobj->buf_out.buf) {
-+ CFI_INFO("Unable to allocate buffer for OUT\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Initialize the callback function pointers */
-+ cfiobj->ops.release = cfi_release;
-+ cfiobj->ops.ep_enable = cfi_ep_enable;
-+ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
-+ cfiobj->ops.build_descriptors = cfi_build_descriptors;
-+ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
-+
-+ /* Initialize the list of active endpoints in the CFI object */
-+ DWC_LIST_INIT(&cfiobj->active_eps);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function reads the required feature's current value into the buffer
-+ *
-+ * @retval: Returns negative as error, or the data length of the feature
-+ */
-+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
-+ struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *ctrl_req)
-+{
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
-+ uint16_t dfifo, rxfifo, txfifo;
-+
-+ switch (ctrl_req->wIndex) {
-+ /* Whether the DDMA is enabled or not */
-+ case FT_ID_DMA_MODE:
-+ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
-+ retval = 1;
-+ break;
-+
-+ case FT_ID_DMA_BUFFER_SETUP:
-+ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
-+ break;
-+
-+ case FT_ID_DMA_BUFF_ALIGN:
-+ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
-+ break;
-+
-+ case FT_ID_DMA_CONCAT_SETUP:
-+ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
-+ break;
-+
-+ case FT_ID_DMA_CIRCULAR:
-+ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
-+ break;
-+
-+ case FT_ID_THRESHOLD_SETUP:
-+ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
-+ break;
-+
-+ case FT_ID_DFIFO_DEPTH:
-+ dfifo = get_dfifo_size(coreif);
-+ *((uint16_t *) buf) = dfifo;
-+ retval = sizeof(uint16_t);
-+ break;
-+
-+ case FT_ID_TX_FIFO_DEPTH:
-+ retval = get_txfifo_size(pcd, ctrl_req->wValue);
-+ if (retval >= 0) {
-+ txfifo = retval;
-+ *((uint16_t *) buf) = txfifo;
-+ retval = sizeof(uint16_t);
-+ }
-+ break;
-+
-+ case FT_ID_RX_FIFO_DEPTH:
-+ retval = get_rxfifo_size(coreif, ctrl_req->wValue);
-+ if (retval >= 0) {
-+ rxfifo = retval;
-+ *((uint16_t *) buf) = rxfifo;
-+ retval = sizeof(uint16_t);
-+ }
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function resets the SG for the specified EP to its default value
-+ */
-+static int cfi_reset_sg_val(cfi_ep_t * cfiep)
-+{
-+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+ return 0;
-+}
-+
-+/**
-+ * This function resets the Alignment for the specified EP to its default value
-+ */
-+static int cfi_reset_align_val(cfi_ep_t * cfiep)
-+{
-+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+ return 0;
-+}
-+
-+/**
-+ * This function resets the Concatenation for the specified EP to its default value
-+ * This function will also set the value of the wTxBytes field to NULL after
-+ * freeing the memory previously allocated for this field.
-+ */
-+static int cfi_reset_concat_val(cfi_ep_t * cfiep)
-+{
-+ /* First we need to free the wTxBytes field */
-+ if (cfiep->bm_concat->wTxBytes) {
-+ DWC_FREE(cfiep->bm_concat->wTxBytes);
-+ cfiep->bm_concat->wTxBytes = NULL;
-+ }
-+
-+ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
-+ return 0;
-+}
-+
-+/**
-+ * This function resets all the buffer setups of the specified endpoint
-+ */
-+static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
-+{
-+ cfi_reset_sg_val(cfiep);
-+ cfi_reset_align_val(cfiep);
-+ cfi_reset_concat_val(cfiep);
-+ return 0;
-+}
-+
-+static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
-+ uint8_t rx_rst, uint8_t tx_rst)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint16_t tx_siz[15];
-+ uint16_t rx_siz = 0;
-+ dwc_otg_pcd_ep_t *ep = NULL;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+
-+ if (rx_rst) {
-+ rx_siz = params->dev_rx_fifo_size;
-+ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
-+ }
-+
-+ if (tx_rst) {
-+ if (ep_addr == 0) {
-+ int i;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ tx_siz[i] =
-+ core_if->core_params->dev_tx_fifo_size[i];
-+ core_if->core_params->dev_tx_fifo_size[i] =
-+ core_if->init_txfsiz[i];
-+ }
-+ } else {
-+
-+ ep = get_ep_by_addr(pcd, ep_addr);
-+
-+ if (NULL == ep) {
-+ CFI_INFO
-+ ("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, ep_addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ tx_siz[0] =
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
-+ 1];
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
-+ GET_CORE_IF(pcd)->init_txfsiz[ep->
-+ dwc_ep.tx_fifo_num -
-+ 1];
-+ }
-+ }
-+
-+ if (resize_fifos(GET_CORE_IF(pcd))) {
-+ retval = 0;
-+ } else {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Reset All(FIFO size)\n",
-+ __func__);
-+ if (rx_rst) {
-+ params->dev_rx_fifo_size = rx_siz;
-+ }
-+
-+ if (tx_rst) {
-+ if (ep_addr == 0) {
-+ int i;
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
-+ i++) {
-+ core_if->
-+ core_params->dev_tx_fifo_size[i] =
-+ tx_siz[i];
-+ }
-+ } else {
-+ params->dev_tx_fifo_size[ep->
-+ dwc_ep.tx_fifo_num -
-+ 1] = tx_siz[0];
-+ }
-+ }
-+ retval = -DWC_E_INVALID;
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
-+ if (retval < 0) {
-+ return retval;
-+ }
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_ep_reset_all_setup_vals(cfiep);
-+ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_ep_reset_all_setup_vals(cfiep);
-+ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Reset All\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
-+ uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_reset_sg_val(cfiep);
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_reset_sg_val(cfiep);
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Buffer Setup\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_reset_concat_val(cfiep);
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_reset_concat_val(cfiep);
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Concatenation Value\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_reset_align_val(cfiep);
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_reset_align_val(cfiep);
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Aliignment Value\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+
-+}
-+
-+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = 0;
-+
-+ switch (req->wIndex) {
-+ case 0:
-+ /* Reset all features */
-+ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_DMA_BUFFER_SETUP:
-+ /* Reset the SG buffer setup */
-+ retval =
-+ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_DMA_CONCAT_SETUP:
-+ /* Reset the Concatenation buffer setup */
-+ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_DMA_BUFF_ALIGN:
-+ /* Reset the Alignment buffer setup */
-+ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_TX_FIFO_DEPTH:
-+ retval =
-+ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
-+ pcd->cfi->need_gadget_att = 0;
-+ break;
-+
-+ case FT_ID_RX_FIFO_DEPTH:
-+ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
-+ pcd->cfi->need_gadget_att = 0;
-+ break;
-+ default:
-+ break;
-+ }
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the SG buffer setup.
-+ */
-+static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+ uint8_t inaddr, outaddr;
-+ cfi_ep_t *epin, *epout;
-+ ddma_sg_buffer_setup_t *psgval;
-+ uint32_t desccount, size;
-+
-+ CFI_INFO("%s\n", __func__);
-+
-+ psgval = (ddma_sg_buffer_setup_t *) buf;
-+ desccount = (uint32_t) psgval->bCount;
-+ size = (uint32_t) psgval->wSize;
-+
-+ /* Check the DMA descriptor count */
-+ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
-+ CFI_INFO
-+ ("%s: The count of DMA Descriptors should be between 1 and %d\n",
-+ __func__, MAX_DMA_DESCS_PER_EP);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ /* Check the DMA descriptor count */
-+
-+ if (size == 0) {
-+
-+ CFI_INFO("%s: The transfer size should be at least 1 byte\n",
-+ __func__);
-+
-+ return -DWC_E_INVALID;
-+
-+ }
-+
-+ inaddr = psgval->bInEndpointAddress;
-+ outaddr = psgval->bOutEndpointAddress;
-+
-+ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
-+ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
-+
-+ if (NULL == epin || NULL == epout) {
-+ CFI_INFO
-+ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
-+ __func__, inaddr, outaddr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ epin->ep->dwc_ep.buff_mode = BM_SG;
-+ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
-+
-+ epout->ep->dwc_ep.buff_mode = BM_SG;
-+ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+ cfi_ep_t *ep;
-+ uint8_t addr;
-+ ddma_align_buffer_setup_t *palignval;
-+
-+ palignval = (ddma_align_buffer_setup_t *) buf;
-+ addr = palignval->bEndpointAddress;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ ep->ep->dwc_ep.buff_mode = BM_ALIGN;
-+ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function sets a new value for the Concatenation buffer setup.
-+ */
-+static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
-+ uint16_t *pVals;
-+ uint32_t desccount;
-+ int i;
-+ uint16_t mps;
-+
-+ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
-+ desccount = (uint32_t) pConcatValHdr->bDescCount;
-+ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
-+
-+ /* Check the DMA descriptor count */
-+ if (desccount > MAX_DMA_DESCS_PER_EP) {
-+ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
-+ __func__, MAX_DMA_DESCS_PER_EP);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ addr = pConcatValHdr->bEndpointAddress;
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ mps = UGETW(ep->ep->desc->wMaxPacketSize);
-+
-+#if 0
-+ for (i = 0; i < desccount; i++) {
-+ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
-+ }
-+ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
-+#endif
-+
-+ /* Check the wTxSizes to be less than or equal to the mps */
-+ for (i = 0; i < desccount; i++) {
-+ if (pVals[i] > mps) {
-+ CFI_INFO
-+ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
-+ __func__, i, pVals[i]);
-+ return -DWC_E_INVALID;
-+ }
-+ }
-+
-+ ep->ep->dwc_ep.buff_mode = BM_CONCAT;
-+ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
-+
-+ /* Free the previously allocated storage for the wTxBytes */
-+ if (ep->bm_concat->wTxBytes) {
-+ DWC_FREE(ep->bm_concat->wTxBytes);
-+ }
-+
-+ /* Allocate a new storage for the wTxBytes field */
-+ ep->bm_concat->wTxBytes =
-+ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
-+ if (NULL == ep->bm_concat->wTxBytes) {
-+ CFI_INFO("%s: Unable to allocate memory\n", __func__);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Copy the new values into the wTxBytes filed */
-+ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
-+ sizeof(uint16_t) * pConcatValHdr->bDescCount);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function calculates the total of all FIFO sizes
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ uint16_t dfifo_total = 0;
-+ int i;
-+
-+ /* The shared RxFIFO size */
-+ dfifo_total =
-+ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
-+
-+ /* Add up each TxFIFO size to the total */
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ dfifo_total += params->dev_tx_fifo_size[i];
-+ }
-+
-+ return dfifo_total;
-+}
-+
-+/**
-+ * This function returns Rx FIFO size
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
-+{
-+ switch (wValue >> 8) {
-+ case 0:
-+ return (core_if->pwron_rxfsiz <
-+ 32768) ? core_if->pwron_rxfsiz : 32768;
-+ break;
-+ case 1:
-+ return core_if->core_params->dev_rx_fifo_size;
-+ break;
-+ default:
-+ return -DWC_E_INVALID;
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function returns Tx FIFO size for IN EP
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ ep = get_ep_by_addr(pcd, wValue & 0xff);
-+
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, wValue & 0xff);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (!ep->dwc_ep.is_in) {
-+ CFI_INFO
-+ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
-+ __func__, wValue & 0xff);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ switch (wValue >> 8) {
-+ case 0:
-+ return (GET_CORE_IF(pcd)->pwron_txfsiz
-+ [ep->dwc_ep.tx_fifo_num - 1] <
-+ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
-+ dwc_ep.tx_fifo_num
-+ - 1] : 32768;
-+ break;
-+ case 1:
-+ return GET_CORE_IF(pcd)->core_params->
-+ dev_tx_fifo_size[ep->dwc_ep.num - 1];
-+ break;
-+ default:
-+ return -DWC_E_INVALID;
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function checks if the submitted combination of
-+ * device mode FIFO sizes is possible or not.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return 1 if possible, 0 otherwise.
-+ *
-+ */
-+static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
-+{
-+ uint16_t dfifo_actual = 0;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ uint16_t start_addr = 0;
-+ int i;
-+
-+ dfifo_actual =
-+ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ dfifo_actual += params->dev_tx_fifo_size[i];
-+ }
-+
-+ if (dfifo_actual > core_if->total_fifo_size) {
-+ return 0;
-+ }
-+
-+ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
-+ return 0;
-+
-+ if (params->dev_nperio_tx_fifo_size > 32768
-+ || params->dev_nperio_tx_fifo_size < 16)
-+ return 0;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+ if (params->dev_tx_fifo_size[i] > 768
-+ || params->dev_tx_fifo_size[i] < 4)
-+ return 0;
-+ }
-+
-+ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
-+ return 0;
-+ start_addr = params->dev_rx_fifo_size;
-+
-+ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
-+ return 0;
-+ start_addr += params->dev_nperio_tx_fifo_size;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
-+ return 0;
-+ start_addr += params->dev_tx_fifo_size[i];
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function resizes Device mode FIFOs
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return 1 if successful, 0 otherwise
-+ *
-+ */
-+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
-+{
-+ int i = 0;
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ uint32_t rx_fifo_size;
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t txfifosize[15];
-+
-+ uint32_t rx_fsz_bak;
-+ uint32_t nptxfsz_bak;
-+ uint32_t txfsz_bak[15];
-+
-+ uint16_t start_address;
-+ uint8_t retval = 1;
-+
-+ if (!check_fifo_sizes(core_if)) {
-+ return 0;
-+ }
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
-+ rx_fifo_size = params->dev_rx_fifo_size;
-+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+ /*
-+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_tx_fifo_size array and the FIFO size registers in
-+ * the dtxfsiz array run from 0 to 14.
-+ */
-+
-+ /* Non-periodic Tx FIFO */
-+ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ start_address = params->dev_rx_fifo_size;
-+ nptxfifosize.b.startaddr = start_address;
-+
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+
-+ start_address += nptxfifosize.b.depth;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
-+
-+ txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
-+ txfifosize[i].b.startaddr = start_address;
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ txfifosize[i].d32);
-+
-+ start_address += txfifosize[i].b.depth;
-+ }
-+
-+ /** Check if register values are set correctly */
-+ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
-+ retval = 0;
-+ }
-+
-+ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
-+ retval = 0;
-+ }
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ if (txfifosize[i].d32 !=
-+ DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
-+ retval = 0;
-+ }
-+ }
-+
-+ /** If register values are not set correctly, reset old values */
-+ if (retval == 0) {
-+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ txfsz_bak[i]);
-+ }
-+ }
-+ } else {
-+ return 0;
-+ }
-+
-+ /* Flush the FIFOs */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
-+{
-+ int retval;
-+ uint32_t fsiz;
-+ uint16_t size;
-+ uint16_t ep_addr;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+ tx_fifo_size_setup_t *ptxfifoval;
-+
-+ ptxfifoval = (tx_fifo_size_setup_t *) buf;
-+ ep_addr = ptxfifoval->bEndpointAddress;
-+ size = ptxfifoval->wDepth;
-+
-+ ep = get_ep_by_addr(pcd, ep_addr);
-+
-+ CFI_INFO
-+ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
-+ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
-+
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, ep_addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
-+
-+ if (resize_fifos(GET_CORE_IF(pcd))) {
-+ retval = 0;
-+ } else {
-+ CFI_INFO
-+ ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
-+ __func__, ep_addr);
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
-+{
-+ int retval;
-+ uint32_t fsiz;
-+ uint16_t size;
-+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+ rx_fifo_size_setup_t *prxfifoval;
-+
-+ prxfifoval = (rx_fifo_size_setup_t *) buf;
-+ size = prxfifoval->wDepth;
-+
-+ fsiz = params->dev_rx_fifo_size;
-+ params->dev_rx_fifo_size = size;
-+
-+ if (resize_fifos(GET_CORE_IF(pcd))) {
-+ retval = 0;
-+ } else {
-+ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
-+ __func__);
-+ params->dev_rx_fifo_size = fsiz;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function reads the SG of an EP's buffer setup into the buffer buf
-+ */
-+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+
-+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+ addr = req->wValue & 0xFF;
-+ if (addr == 0) /* The address should be non-zero */
-+ return retval;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+ __func__, addr);
-+ return retval;
-+ }
-+
-+ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
-+ retval = BS_SG_VAL_DESC_LEN;
-+ return retval;
-+}
-+
-+/**
-+ * This function reads the Concatenation value of an EP's buffer mode into
-+ * the buffer buf
-+ */
-+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+ uint8_t desc_count;
-+
-+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+ addr = req->wValue & 0xFF;
-+ if (addr == 0) /* The address should be non-zero */
-+ return retval;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+ __func__, addr);
-+ return retval;
-+ }
-+
-+ /* Copy the header to the buffer */
-+ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
-+ /* Advance the buffer pointer by the header size */
-+ buf += BS_CONCAT_VAL_HDR_LEN;
-+
-+ desc_count = ep->bm_concat->hdr.bDescCount;
-+ /* Copy alll the wTxBytes to the buffer */
-+ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
-+
-+ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
-+ return retval;
-+}
-+
-+/**
-+ * This function reads the buffer Alignment value of an EP's buffer mode into
-+ * the buffer buf
-+ *
-+ * @return The total number of bytes copied to the buffer or negative error code.
-+ */
-+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+
-+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+ addr = req->wValue & 0xFF;
-+ if (addr == 0) /* The address should be non-zero */
-+ return retval;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+ __func__, addr);
-+ return retval;
-+ }
-+
-+ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
-+ retval = BS_ALIGN_VAL_HDR_LEN;
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the specified feature
-+ *
-+ * @param pcd A pointer to the PCD object
-+ *
-+ * @return 0 if successful, negative error code otherwise to stall the DCE.
-+ */
-+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
-+{
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+ uint16_t wIndex, wValue;
-+ uint8_t bRequest;
-+ struct dwc_otg_core_if *coreif;
-+ cfiobject_t *cfi = pcd->cfi;
-+ struct cfi_usb_ctrlrequest *ctrl_req;
-+ uint8_t *buf;
-+ ctrl_req = &cfi->ctrl_req;
-+
-+ buf = pcd->cfi->ctrl_req.data;
-+
-+ coreif = GET_CORE_IF(pcd);
-+ bRequest = ctrl_req->bRequest;
-+ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
-+ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
-+
-+ /* See which feature is to be modified */
-+ switch (wIndex) {
-+ case FT_ID_DMA_BUFFER_SETUP:
-+ /* Modify the feature */
-+ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
-+ return retval;
-+
-+ /* And send this request to the gadget */
-+ cfi->need_gadget_att = 1;
-+ break;
-+
-+ case FT_ID_DMA_BUFF_ALIGN:
-+ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 1;
-+ break;
-+
-+ case FT_ID_DMA_CONCAT_SETUP:
-+ /* Modify the feature */
-+ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 1;
-+ break;
-+
-+ case FT_ID_DMA_CIRCULAR:
-+ CFI_INFO("FT_ID_DMA_CIRCULAR\n");
-+ break;
-+
-+ case FT_ID_THRESHOLD_SETUP:
-+ CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
-+ break;
-+
-+ case FT_ID_DFIFO_DEPTH:
-+ CFI_INFO("FT_ID_DFIFO_DEPTH\n");
-+ break;
-+
-+ case FT_ID_TX_FIFO_DEPTH:
-+ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
-+ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 0;
-+ break;
-+
-+ case FT_ID_RX_FIFO_DEPTH:
-+ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
-+ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 0;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+#endif //DWC_UTE_CFI
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cfi.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,320 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_CFI_H__)
-+#define __DWC_OTG_CFI_H__
-+
-+#include "dwc_otg_pcd.h"
-+#include "dwc_cfi_common.h"
-+
-+/**
-+ * @file
-+ * This file contains the CFI related OTG PCD specific common constants,
-+ * interfaces(functions and macros) and data structures.The CFI Protocol is an
-+ * optional interface for internal testing purposes that a DUT may implement to
-+ * support testing of configurable features.
-+ *
-+ */
-+
-+struct dwc_otg_pcd;
-+struct dwc_otg_pcd_ep;
-+
-+/** OTG CFI Features (properties) ID constants */
-+/** This is a request for all Core Features */
-+#define FT_ID_DMA_MODE 0x0001
-+#define FT_ID_DMA_BUFFER_SETUP 0x0002
-+#define FT_ID_DMA_BUFF_ALIGN 0x0003
-+#define FT_ID_DMA_CONCAT_SETUP 0x0004
-+#define FT_ID_DMA_CIRCULAR 0x0005
-+#define FT_ID_THRESHOLD_SETUP 0x0006
-+#define FT_ID_DFIFO_DEPTH 0x0007
-+#define FT_ID_TX_FIFO_DEPTH 0x0008
-+#define FT_ID_RX_FIFO_DEPTH 0x0009
-+
-+/**********************************************************/
-+#define CFI_INFO_DEF
-+
-+#ifdef CFI_INFO_DEF
-+#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt);
-+#else
-+#define CFI_INFO(fmt...)
-+#endif
-+
-+#define min(x,y) ({ \
-+ x < y ? x : y; })
-+
-+#define max(x,y) ({ \
-+ x > y ? x : y; })
-+
-+/**
-+ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
-+ * also used for setting up a buffer for Circular DDMA.
-+ */
-+struct _ddma_sg_buffer_setup {
-+#define BS_SG_VAL_DESC_LEN 6
-+ /* The OUT EP address */
-+ uint8_t bOutEndpointAddress;
-+ /* The IN EP address */
-+ uint8_t bInEndpointAddress;
-+ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
-+ uint8_t bOffset;
-+ /* The number of transfer segments (a DMA descriptors per each segment) */
-+ uint8_t bCount;
-+ /* Size (in byte) of each transfer segment */
-+ uint16_t wSize;
-+} __attribute__ ((packed));
-+typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
-+
-+/** Descriptor DMA Concatenation Buffer setup structure */
-+struct _ddma_concat_buffer_setup_hdr {
-+#define BS_CONCAT_VAL_HDR_LEN 4
-+ /* The endpoint for which the buffer is to be set up */
-+ uint8_t bEndpointAddress;
-+ /* The count of descriptors to be used */
-+ uint8_t bDescCount;
-+ /* The total size of the transfer */
-+ uint16_t wSize;
-+} __attribute__ ((packed));
-+typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
-+
-+/** Descriptor DMA Concatenation Buffer setup structure */
-+struct _ddma_concat_buffer_setup {
-+ /* The SG header */
-+ ddma_concat_buffer_setup_hdr_t hdr;
-+
-+ /* The XFER sizes pointer (allocated dynamically) */
-+ uint16_t *wTxBytes;
-+} __attribute__ ((packed));
-+typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
-+
-+/** Descriptor DMA Alignment Buffer setup structure */
-+struct _ddma_align_buffer_setup {
-+#define BS_ALIGN_VAL_HDR_LEN 2
-+ uint8_t bEndpointAddress;
-+ uint8_t bAlign;
-+} __attribute__ ((packed));
-+typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
-+
-+/** Transmit FIFO Size setup structure */
-+struct _tx_fifo_size_setup {
-+ uint8_t bEndpointAddress;
-+ uint16_t wDepth;
-+} __attribute__ ((packed));
-+typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
-+
-+/** Transmit FIFO Size setup structure */
-+struct _rx_fifo_size_setup {
-+ uint16_t wDepth;
-+} __attribute__ ((packed));
-+typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
-+
-+/**
-+ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
-+ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
-+ * to the data returned in the data stage of a 3-stage Control Write requests.
-+ */
-+struct cfi_usb_ctrlrequest {
-+ uint8_t bRequestType;
-+ uint8_t bRequest;
-+ uint16_t wValue;
-+ uint16_t wIndex;
-+ uint16_t wLength;
-+ uint8_t *data;
-+} UPACKED;
-+
-+/*---------------------------------------------------------------------------*/
-+
-+/**
-+ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
-+ * This structure is used to store the buffer setup data for any
-+ * enabled endpoint in the PCD.
-+ */
-+struct cfi_ep {
-+ /* Entry for the list container */
-+ dwc_list_link_t lh;
-+ /* Pointer to the active PCD endpoint structure */
-+ struct dwc_otg_pcd_ep *ep;
-+ /* The last descriptor in the chain of DMA descriptors of the endpoint */
-+ struct dwc_otg_dma_desc *dma_desc_last;
-+ /* The SG feature value */
-+ ddma_sg_buffer_setup_t *bm_sg;
-+ /* The Circular feature value */
-+ ddma_sg_buffer_setup_t *bm_circ;
-+ /* The Concatenation feature value */
-+ ddma_concat_buffer_setup_t *bm_concat;
-+ /* The Alignment feature value */
-+ ddma_align_buffer_setup_t *bm_align;
-+ /* XFER length */
-+ uint32_t xfer_len;
-+ /*
-+ * Count of DMA descriptors currently used.
-+ * The total should not exceed the MAX_DMA_DESCS_PER_EP value
-+ * defined in the dwc_otg_cil.h
-+ */
-+ uint32_t desc_count;
-+};
-+typedef struct cfi_ep cfi_ep_t;
-+
-+typedef struct cfi_dma_buff {
-+#define CFI_IN_BUF_LEN 1024
-+#define CFI_OUT_BUF_LEN 1024
-+ dma_addr_t addr;
-+ uint8_t *buf;
-+} cfi_dma_buff_t;
-+
-+struct cfiobject;
-+
-+/**
-+ * This is the interface for the CFI operations.
-+ *
-+ * @param ep_enable Called when any endpoint is enabled and activated.
-+ * @param release Called when the CFI object is released and it needs to correctly
-+ * deallocate the dynamic memory
-+ * @param ctrl_write_complete Called when the data stage of the request is complete
-+ */
-+typedef struct cfi_ops {
-+ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
-+ struct dwc_otg_pcd_ep * ep);
-+ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
-+ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
-+ unsigned size, gfp_t flags);
-+ void (*release) (struct cfiobject * cfi);
-+ int (*ctrl_write_complete) (struct cfiobject * cfi,
-+ struct dwc_otg_pcd * pcd);
-+ void (*build_descriptors) (struct cfiobject * cfi,
-+ struct dwc_otg_pcd * pcd,
-+ struct dwc_otg_pcd_ep * ep,
-+ dwc_otg_pcd_request_t * req);
-+} cfi_ops_t;
-+
-+struct cfiobject {
-+ cfi_ops_t ops;
-+ struct dwc_otg_pcd *pcd;
-+ struct usb_gadget *gadget;
-+
-+ /* Buffers used to send/receive CFI-related request data */
-+ cfi_dma_buff_t buf_in;
-+ cfi_dma_buff_t buf_out;
-+
-+ /* CFI specific Control request wrapper */
-+ struct cfi_usb_ctrlrequest ctrl_req;
-+
-+ /* The list of active EP's in the PCD of type cfi_ep_t */
-+ dwc_list_link_t active_eps;
-+
-+ /* This flag shall control the propagation of a specific request
-+ * to the gadget's processing routines.
-+ * 0 - no gadget handling
-+ * 1 - the gadget needs to know about this request (w/o completing a status
-+ * phase - just return a 0 to the _setup callback)
-+ */
-+ uint8_t need_gadget_att;
-+
-+ /* Flag indicating whether the status IN phase needs to be
-+ * completed by the PCD
-+ */
-+ uint8_t need_status_in_complete;
-+};
-+typedef struct cfiobject cfiobject_t;
-+
-+#define DUMP_MSG
-+
-+#if defined(DUMP_MSG)
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+ unsigned int start, num, i;
-+ char line[52], *p;
-+
-+ if (length >= 512)
-+ return;
-+
-+ start = 0;
-+ while (length > 0) {
-+ num = min(length, 16u);
-+ p = line;
-+ for (i = 0; i < num; ++i) {
-+ if (i == 8)
-+ *p++ = ' ';
-+ DWC_SPRINTF(p, " %02x", buf[i]);
-+ p += 3;
-+ }
-+ *p = 0;
-+ DWC_DEBUG("%6x: %s\n", start, line);
-+ buf += num;
-+ start += num;
-+ length -= num;
-+ }
-+}
-+#else
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function returns a pointer to cfi_ep_t object with the addr address.
-+ */
-+static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
-+ uint8_t addr)
-+{
-+ struct cfi_ep *pcfiep;
-+ dwc_list_link_t *tmp;
-+
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+
-+ if (pcfiep->ep->desc->bEndpointAddress == addr) {
-+ return pcfiep;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * This function returns a pointer to cfi_ep_t object that matches
-+ * the dwc_otg_pcd_ep object.
-+ */
-+static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
-+ struct dwc_otg_pcd_ep *ep)
-+{
-+ struct cfi_ep *pcfiep = NULL;
-+ dwc_list_link_t *tmp;
-+
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ if (pcfiep->ep == ep) {
-+ return pcfiep;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
-+
-+#endif /* (__DWC_OTG_CFI_H__) */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cil.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cil.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,7151 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
-+ * $Revision: #191 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * The CIL manages the memory map for the core so that the HCD and PCD
-+ * don't have to do this separately. It also handles basic tasks like
-+ * reading/writing the registers and data FIFOs in the controller.
-+ * Some of the data access functions provide encapsulation of several
-+ * operations required to perform a task, such as writing multiple
-+ * registers to start a transfer. Finally, the CIL performs basic
-+ * services that are not specific to either the host or device modes
-+ * of operation. These services include management of the OTG Host
-+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
-+ * Diagnostic API is also provided to allow testing of the controller
-+ * hardware.
-+ *
-+ * The Core Interface Layer has the following requirements:
-+ * - Provides basic controller operations.
-+ * - Minimal use of OS services.
-+ * - The OS services used will be abstracted by using inline functions
-+ * or macros.
-+ *
-+ */
-+
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+
-+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * This function is called to initialize the DWC_otg CSR data
-+ * structures. The register addresses in the device and host
-+ * structures are initialized from the base address supplied by the
-+ * caller. The calling function must make the OS calls to get the
-+ * base address of the DWC_otg controller registers. The core_params
-+ * argument holds the parameters that specify how the core should be
-+ * configured.
-+ *
-+ * @param reg_base_addr Base address of DWC_otg core registers
-+ *
-+ */
-+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
-+{
-+ dwc_otg_core_if_t *core_if = 0;
-+ dwc_otg_dev_if_t *dev_if = 0;
-+ dwc_otg_host_if_t *host_if = 0;
-+ uint8_t *reg_base = (uint8_t *) reg_base_addr;
-+ int i = 0;
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
-+
-+ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
-+
-+ if (core_if == NULL) {
-+ DWC_DEBUGPL(DBG_CIL,
-+ "Allocation of dwc_otg_core_if_t failed\n");
-+ return 0;
-+ }
-+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
-+
-+ /*
-+ * Allocate the Device Mode structures.
-+ */
-+ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
-+
-+ if (dev_if == NULL) {
-+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ dev_if->dev_global_regs =
-+ (dwc_otg_device_global_regs_t *) (reg_base +
-+ DWC_DEV_GLOBAL_REG_OFFSET);
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
-+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
-+ (i * DWC_EP_REG_OFFSET));
-+
-+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
-+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
-+ (i * DWC_EP_REG_OFFSET));
-+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
-+ i, &dev_if->in_ep_regs[i]->diepctl);
-+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
-+ i, &dev_if->out_ep_regs[i]->doepctl);
-+ }
-+
-+ dev_if->speed = 0; // unknown
-+
-+ core_if->dev_if = dev_if;
-+
-+ /*
-+ * Allocate the Host Mode structures.
-+ */
-+ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
-+
-+ if (host_if == NULL) {
-+ DWC_DEBUGPL(DBG_CIL,
-+ "Allocation of dwc_otg_host_if_t failed\n");
-+ DWC_FREE(dev_if);
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
-+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
-+
-+ host_if->hprt0 =
-+ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
-+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
-+ (i * DWC_OTG_CHAN_REGS_OFFSET));
-+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
-+ i, &host_if->hc_regs[i]->hcchar);
-+ }
-+
-+ host_if->num_host_channels = MAX_EPS_CHANNELS;
-+ core_if->host_if = host_if;
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ core_if->data_fifo[i] =
-+ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
-+ (i * DWC_OTG_DATA_FIFO_SIZE));
-+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
-+ i, (unsigned long)core_if->data_fifo[i]);
-+ }
-+
-+ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
-+
-+ /* Initiate lx_state to L3 disconnected state */
-+ core_if->lx_state = DWC_OTG_L3;
-+ /*
-+ * Store the contents of the hardware configuration registers here for
-+ * easy access later.
-+ */
-+ core_if->hwcfg1.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
-+ core_if->hwcfg2.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
-+ core_if->hwcfg3.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
-+ core_if->hwcfg4.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
-+
-+ /* Force host mode to get HPTXFSIZ exact power on value */
-+ {
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ gusbcfg.b.force_host_mode = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+ dwc_mdelay(100);
-+ core_if->hptxfsiz.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ gusbcfg.b.force_host_mode = 0;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+ dwc_mdelay(100);
-+ }
-+
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
-+
-+ core_if->hcfg.d32 =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ core_if->dcfg.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+
-+ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
-+ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
-+ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
-+ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
-+ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
-+ core_if->hwcfg2.b.num_host_chan);
-+ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
-+ core_if->hwcfg2.b.nonperio_tx_q_depth);
-+ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
-+ core_if->hwcfg2.b.host_perio_tx_q_depth);
-+ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
-+ core_if->hwcfg2.b.dev_token_q_depth);
-+
-+ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
-+ core_if->hwcfg3.b.dfifo_depth);
-+ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
-+ core_if->hwcfg3.b.xfer_size_cntr_width);
-+
-+ /*
-+ * Set the SRP sucess bit for FS-I2c
-+ */
-+ core_if->srp_success = 0;
-+ core_if->srp_timer_started = 0;
-+
-+ /*
-+ * Create new workqueue and init works
-+ */
-+ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
-+ if (core_if->wq_otg == 0) {
-+ DWC_WARN("DWC_WORKQ_ALLOC failed\n");
-+ DWC_FREE(host_if);
-+ DWC_FREE(dev_if);
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
-+
-+ DWC_PRINTF("Core Release: %x.%x%x%x\n",
-+ (core_if->snpsid >> 12 & 0xF),
-+ (core_if->snpsid >> 8 & 0xF),
-+ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
-+
-+ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
-+ w_wakeup_detected, core_if);
-+ if (core_if->wkp_timer == 0) {
-+ DWC_WARN("DWC_TIMER_ALLOC failed\n");
-+ DWC_FREE(host_if);
-+ DWC_FREE(dev_if);
-+ DWC_WORKQ_FREE(core_if->wq_otg);
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ if (dwc_otg_setup_params(core_if)) {
-+ DWC_WARN("Error while setting core params\n");
-+ }
-+
-+ core_if->hibernation_suspend = 0;
-+
-+ /** ADP initialization */
-+ dwc_otg_adp_init(core_if);
-+
-+ return core_if;
-+}
-+
-+/**
-+ * This function frees the structures allocated by dwc_otg_cil_init().
-+ *
-+ * @param core_if The core interface pointer returned from
-+ * dwc_otg_cil_init().
-+ *
-+ */
-+void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
-+{
-+ dctl_data_t dctl = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
-+
-+ /* Disable all interrupts */
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
-+
-+ dctl.b.sftdiscon = 1;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
-+ dctl.d32);
-+ }
-+
-+ if (core_if->wq_otg) {
-+ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
-+ DWC_WORKQ_FREE(core_if->wq_otg);
-+ }
-+ if (core_if->dev_if) {
-+ DWC_FREE(core_if->dev_if);
-+ }
-+ if (core_if->host_if) {
-+ DWC_FREE(core_if->host_if);
-+ }
-+
-+ /** Remove ADP Stuff */
-+ dwc_otg_adp_remove(core_if);
-+ if (core_if->core_params) {
-+ DWC_FREE(core_if->core_params);
-+ }
-+ if (core_if->wkp_timer) {
-+ DWC_TIMER_FREE(core_if->wkp_timer);
-+ }
-+ if (core_if->srp_timer) {
-+ DWC_TIMER_FREE(core_if->srp_timer);
-+ }
-+ DWC_FREE(core_if);
-+}
-+
-+/**
-+ * This function enables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
-+}
-+
-+/**
-+ * This function disables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the commmon interrupts, used in both
-+ * device and host modes.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ /* Clear any pending OTG Interrupts */
-+ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
-+
-+ /* Clear any pending interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /*
-+ * Enable the interrupts in the GINTMSK.
-+ */
-+ intr_mask.b.modemismatch = 1;
-+ intr_mask.b.otgintr = 1;
-+
-+ if (!core_if->dma_enable) {
-+ intr_mask.b.rxstsqlvl = 1;
-+ }
-+
-+ intr_mask.b.conidstschng = 1;
-+ intr_mask.b.wkupintr = 1;
-+ intr_mask.b.disconnect = 0;
-+ intr_mask.b.usbsuspend = 1;
-+ intr_mask.b.sessreqintr = 1;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (core_if->core_params->lpm_enable) {
-+ intr_mask.b.lpmtranrcvd = 1;
-+ }
-+#endif
-+ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
-+}
-+
-+/*
-+ * The restore operation is modified to support Synopsys Emulated Powerdown and
-+ * Hibernation. This function is for exiting from Device mode hibernation by
-+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
-+ * @param reset - indicates whether resume is initiated by Reset.
-+ */
-+int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+
-+ int timeout = 2000;
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
-+ /* Switch-on voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Assert Restore signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ if (rem_wakeup) {
-+ dwc_udelay(70);
-+ }
-+
-+ /* Deassert Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Mask interrupts from gpwrdn */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.connect_det_msk = 1;
-+ gpwrdn.b.srp_det_msk = 1;
-+ gpwrdn.b.disconn_det_msk = 1;
-+ gpwrdn.b.rst_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Indicates that we are going out from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /*
-+ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
-+ * indicates restore from remote_wakeup
-+ */
-+ restore_essential_regs(core_if, rem_wakeup, 0);
-+
-+ /*
-+ * Wait a little for seeing new value of variable hibernation_suspend if
-+ * Restore done interrupt received before polling
-+ */
-+ dwc_udelay(10);
-+
-+ if (core_if->hibernation_suspend == 0) {
-+ /*
-+ * Wait For Restore_done Interrupt. This mechanism of polling the
-+ * interrupt is introduced to avoid any possible race conditions
-+ */
-+ do {
-+ gintsts_data_t gintsts;
-+ gintsts.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (gintsts.b.restoredone) {
-+ gintsts.d32 = 0;
-+ gintsts.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, gintsts.d32);
-+ DWC_PRINTF("Restore Done Interrupt seen\n");
-+ break;
-+ }
-+ dwc_udelay(10);
-+ } while (--timeout);
-+ if (!timeout) {
-+ DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
-+ }
-+ }
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* De-assert Restore */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ if (!rem_wakeup) {
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ }
-+
-+ /* Restore GUSBCFG and DCFG */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+ core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+ core_if->dr_backup->dcfg);
-+
-+ /* De-assert Wakeup Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ if (!rem_wakeup) {
-+ /* Set Device programming done bit */
-+ dctl.b.pwronprgdone = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ } else {
-+ /* Start Remote Wakeup Signaling */
-+ dctl.d32 = core_if->dr_backup->dctl;
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+ }
-+
-+ dwc_mdelay(2);
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Restore global registers */
-+ dwc_otg_restore_global_regs(core_if);
-+ /* Restore device global registers */
-+ dwc_otg_restore_dev_regs(core_if, rem_wakeup);
-+
-+ if (rem_wakeup) {
-+ dwc_mdelay(7);
-+ dctl.d32 = 0;
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+ }
-+
-+ core_if->hibernation_suspend = 0;
-+ /* The core will be in ON STATE */
-+ core_if->lx_state = DWC_OTG_L0;
-+ DWC_PRINTF("Hibernation recovery completes here\n");
-+
-+ return 1;
-+}
-+
-+/*
-+ * The restore operation is modified to support Synopsys Emulated Powerdown and
-+ * Hibernation. This function is for exiting from Host mode hibernation by
-+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
-+ * @param reset - indicates whether resume is initiated by Reset.
-+ */
-+int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+ int timeout = 2000;
-+
-+ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
-+ /* Switch-on voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Assert Restore signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ if (!rem_wakeup) {
-+ dwc_udelay(50);
-+ }
-+
-+ /* Deassert Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.connect_det_msk = 1;
-+ gpwrdn.b.srp_det_msk = 1;
-+ gpwrdn.b.disconn_det_msk = 1;
-+ gpwrdn.b.rst_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Indicates that we are going out from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Set Restore Essential Regs bit in PCGCCTL register */
-+ restore_essential_regs(core_if, rem_wakeup, 1);
-+
-+ /* Wait a little for seeing new value of variable hibernation_suspend if
-+ * Restore done interrupt received before polling */
-+ dwc_udelay(10);
-+
-+ if (core_if->hibernation_suspend == 0) {
-+ /* Wait For Restore_done Interrupt. This mechanism of polling the
-+ * interrupt is introduced to avoid any possible race conditions
-+ */
-+ do {
-+ gintsts_data_t gintsts;
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (gintsts.b.restoredone) {
-+ gintsts.d32 = 0;
-+ gintsts.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
-+ break;
-+ }
-+ dwc_udelay(10);
-+ } while (--timeout);
-+ if (!timeout) {
-+ DWC_WARN("Restore Done interrupt wasn't generated\n");
-+ }
-+ }
-+
-+ /* Set the flag's value to 0 again after receiving restore done interrupt */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* This step is not described in functional spec but if not wait for this
-+ * delay, mismatch interrupts occurred because just after restore core is
-+ * in Device mode(gintsts.curmode == 0) */
-+ dwc_mdelay(100);
-+
-+ /* Clear all pending interrupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* De-assert Restore */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Restore GUSBCFG and HCFG */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+ core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
-+ core_if->hr_backup->hcfg_local);
-+
-+ /* De-assert Wakeup Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Start the Resume operation by programming HPRT0 */
-+ hprt0.d32 = core_if->hr_backup->hprt0_local;
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtsusp = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ DWC_PRINTF("Resume Starts Now\n");
-+ if (!reset) { // Indicates it is Resume Operation
-+ hprt0.d32 = core_if->hr_backup->hprt0_local;
-+ hprt0.b.prtres = 1;
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtsusp = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ if (!rem_wakeup)
-+ hprt0.b.prtres = 0;
-+ /* Wait for Resume time and then program HPRT again */
-+ dwc_mdelay(100);
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ } else { // Indicates it is Reset Operation
-+ hprt0.d32 = core_if->hr_backup->hprt0_local;
-+ hprt0.b.prtrst = 1;
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtsusp = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ /* Wait for Reset time and then program HPRT again */
-+ dwc_mdelay(60);
-+ hprt0.b.prtrst = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+ /* Clear all interrupt status */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtconndet = 1;
-+ hprt0.b.prtenchng = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Restore global registers */
-+ dwc_otg_restore_global_regs(core_if);
-+ /* Restore host global registers */
-+ dwc_otg_restore_host_regs(core_if, reset);
-+
-+ /* The core will be in ON STATE */
-+ core_if->lx_state = DWC_OTG_L0;
-+ DWC_PRINTF("Hibernation recovery is complete here\n");
-+ return 0;
-+}
-+
-+/** Saves some register values into system memory. */
-+int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+ int i;
-+
-+ gr = core_if->gr_backup;
-+ if (!gr) {
-+ gr = DWC_ALLOC(sizeof(*gr));
-+ if (!gr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->gr_backup = gr;
-+ }
-+
-+ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
-+ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
-+ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+#endif
-+ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
-+ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
-+ gr->gdfifocfg_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ gr->dtxfsiz_local[i] =
-+ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
-+ }
-+
-+ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
-+ gr->gnptxfsiz_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
-+ gr->hptxfsiz_local);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
-+#endif
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
-+ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
-+
-+ return 0;
-+}
-+
-+/** Saves GINTMSK register before setting the msk bits. */
-+int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+
-+ gr = core_if->gr_backup;
-+ if (!gr) {
-+ gr = DWC_ALLOC(sizeof(*gr));
-+ if (!gr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->gr_backup = gr;
-+ }
-+
-+ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
-+
-+ return 0;
-+}
-+
-+int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_dev_regs_backup *dr;
-+ int i;
-+
-+ dr = core_if->dr_backup;
-+ if (!dr) {
-+ dr = DWC_ALLOC(sizeof(*dr));
-+ if (!dr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->dr_backup = dr;
-+ }
-+
-+ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ dr->daintmsk =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ dr->diepmsk =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
-+ dr->doepmsk =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
-+
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ dr->diepctl[i] =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
-+ dr->dieptsiz[i] =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
-+ dr->diepdma[i] =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
-+ }
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "=============Backing Host registers==============\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
-+ dr->daintmsk);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
-+ dr->diepctl[i]);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
-+ i, dr->dieptsiz[i]);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
-+ dr->diepdma[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_host_regs_backup *hr;
-+ int i;
-+
-+ hr = core_if->hr_backup;
-+ if (!hr) {
-+ hr = DWC_ALLOC(sizeof(*hr));
-+ if (!hr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->hr_backup = hr;
-+ }
-+
-+ hr->hcfg_local =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ hr->haintmsk_local =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
-+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+ hr->hcintmsk_local[i] =
-+ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
-+ }
-+ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
-+ hr->hfir_local =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "=============Backing Host registers===============\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
-+ hr->hcfg_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
-+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
-+ hr->hcintmsk_local[i]);
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
-+ hr->hprt0_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
-+ hr->hfir_local);
-+
-+ return 0;
-+}
-+
-+int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+ int i;
-+
-+ gr = core_if->gr_backup;
-+ if (!gr) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
-+ gr->gnptxfsiz_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
-+ gr->hptxfsiz_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
-+ gr->gdfifocfg_local);
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
-+ gr->dtxfsiz_local[i]);
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
-+ (gr->gahbcfg_local));
-+ return 0;
-+}
-+
-+int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
-+{
-+ struct dwc_otg_dev_regs_backup *dr;
-+ int i;
-+
-+ dr = core_if->dr_backup;
-+
-+ if (!dr) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (!rem_wakeup) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ dr->dctl);
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
-+
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
-+{
-+ struct dwc_otg_host_regs_backup *hr;
-+ int i;
-+ hr = core_if->hr_backup;
-+
-+ if (!hr) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
-+ //if (!reset)
-+ //{
-+ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
-+ //}
-+
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
-+ hr->haintmsk_local);
-+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
-+ hr->hcintmsk_local[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+
-+ gr = core_if->gr_backup;
-+
-+ /* Restore values for LPM and I2C */
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
-+#endif
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
-+
-+ return 0;
-+}
-+
-+int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+ /* Restore LPM and I2C registers */
-+ restore_lpm_i2c_regs(core_if);
-+
-+ /* Set PCGCCTL to 0 */
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
-+
-+ gr = core_if->gr_backup;
-+ /* Load restore values for [31:14] bits */
-+ DWC_WRITE_REG32(core_if->pcgcctl,
-+ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
-+
-+ /* Umnask global Interrupt in GAHBCFG and restore it */
-+ gahbcfg.d32 = gr->gahbcfg_local;
-+ gahbcfg.b.glblintrmsk = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
-+
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Unmask restore done interrupt */
-+ gintmsk.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
-+
-+ /* Restore GUSBCFG and HCFG/DCFG */
-+ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+
-+ if (is_host) {
-+ hcfg_data_t hcfg = {.d32 = 0 };
-+ hcfg.d32 = core_if->hr_backup->hcfg_local;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
-+ hcfg.d32);
-+
-+ /* Load restore values for [31:14] bits */
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+
-+ if (rmode)
-+ pcgcctl.b.restoremode = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ /* Load restore values for [31:14] bits and set EssRegRestored bit */
-+ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.b.ess_reg_restored = 1;
-+ if (rmode)
-+ pcgcctl.b.restoremode = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ } else {
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+ dcfg.d32 = core_if->dr_backup->dcfg;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* Load restore values for [31:14] bits */
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+ if (!rmode) {
-+ pcgcctl.d32 |= 0x208;
-+ }
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ /* Load restore values for [31:14] bits */
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+ pcgcctl.b.ess_reg_restored = 1;
-+ if (!rmode)
-+ pcgcctl.d32 |= 0x208;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
-+ * type.
-+ */
-+static void init_fslspclksel(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t val;
-+ hcfg_data_t hcfg;
-+
-+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) ||
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* Full speed PHY */
-+ val = DWC_HCFG_48_MHZ;
-+ } else {
-+ /* High speed PHY running at full speed or high speed */
-+ val = DWC_HCFG_30_60_MHZ;
-+ }
-+
-+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
-+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ hcfg.b.fslspclksel = val;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/**
-+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
-+ * and the enumeration speed of the device.
-+ */
-+static void init_devspd(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t val;
-+ dcfg_data_t dcfg;
-+
-+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) ||
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* Full speed PHY */
-+ val = 0x3;
-+ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+ /* High speed PHY running at full speed */
-+ val = 0x1;
-+ } else {
-+ /* High speed PHY running at high speed */
-+ val = 0x0;
-+ }
-+
-+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
-+
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devspd = val;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+/**
-+ * This function calculates the number of IN EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t num_in_eps = 0;
-+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
-+ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
-+ int i;
-+
-+ for (i = 0; i < num_eps; ++i) {
-+ if (!(hwcfg1 & 0x1))
-+ num_in_eps++;
-+
-+ hwcfg1 >>= 2;
-+ }
-+
-+ if (core_if->hwcfg4.b.ded_fifo_en) {
-+ num_in_eps =
-+ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
-+ }
-+
-+ return num_in_eps;
-+}
-+
-+/**
-+ * This function calculates the number of OUT EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t num_out_eps = 0;
-+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
-+ int i;
-+
-+ for (i = 0; i < num_eps; ++i) {
-+ if (!(hwcfg1 & 0x1))
-+ num_out_eps++;
-+
-+ hwcfg1 >>= 2;
-+ }
-+ return num_out_eps;
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers and
-+ * prepares the core for device mode or host mode operation.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
-+{
-+ int i = 0;
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+ gusbcfg_data_t usbcfg = {.d32 = 0 };
-+ gi2cctl_data_t i2cctl = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
-+ core_if, global_regs);
-+
-+ /* Common Initialization */
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+ /* Program the ULPI External VBUS bit if needed */
-+ usbcfg.b.ulpi_ext_vbus_drv =
-+ (core_if->core_params->phy_ulpi_ext_vbus ==
-+ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
-+
-+ /* Set external TS Dline pulsing */
-+ usbcfg.b.term_sel_dl_pulse =
-+ (core_if->core_params->ts_dline == 1) ? 1 : 0;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Reset the Controller */
-+ dwc_otg_core_reset(core_if);
-+
-+ core_if->adp_enable = core_if->core_params->adp_supp_enable;
-+ core_if->power_down = core_if->core_params->power_down;
-+ core_if->otg_sts = 0;
-+
-+ /* Initialize parameters from Hardware configuration registers. */
-+ dev_if->num_in_eps = calc_num_in_eps(core_if);
-+ dev_if->num_out_eps = calc_num_out_eps(core_if);
-+
-+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
-+ core_if->hwcfg4.b.num_dev_perio_in_ep);
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
-+ dev_if->perio_tx_fifo_size[i] =
-+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
-+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
-+ i, dev_if->perio_tx_fifo_size[i]);
-+ }
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ dev_if->tx_fifo_size[i] =
-+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
-+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
-+ i, dev_if->tx_fifo_size[i]);
-+ }
-+
-+ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
-+ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
-+ core_if->nperio_tx_fifo_size =
-+ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
-+
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
-+ core_if->nperio_tx_fifo_size);
-+
-+ /* This programming sequence needs to happen in FS mode before any other
-+ * programming occurs */
-+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* If FS mode with FS PHY */
-+
-+ /* core_init() is now called on every switch so only call the
-+ * following for the first time through. */
-+ if (!core_if->phy_init_done) {
-+ core_if->phy_init_done = 1;
-+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.physel = 1;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Reset after a PHY select */
-+ dwc_otg_core_reset(core_if);
-+ }
-+
-+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
-+ * do this on HNP Dev/Host mode switches (done in dev_init and
-+ * host_init). */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ init_fslspclksel(core_if);
-+ } else {
-+ init_devspd(core_if);
-+ }
-+
-+ if (core_if->core_params->i2c_enable) {
-+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
-+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.otgutmifssel = 1;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Program GI2CCTL.I2CEn */
-+ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
-+ i2cctl.b.i2cdevaddr = 1;
-+ i2cctl.b.i2cen = 0;
-+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
-+ i2cctl.b.i2cen = 1;
-+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
-+ }
-+
-+ } /* endif speed == DWC_SPEED_PARAM_FULL */
-+ else {
-+ /* High speed PHY. */
-+ if (!core_if->phy_init_done) {
-+ core_if->phy_init_done = 1;
-+ /* HS PHY parameters. These parameters are preserved
-+ * during soft reset so only program the first time. Do
-+ * a soft reset immediately after setting phyif. */
-+
-+ if (core_if->core_params->phy_type == 2) {
-+ /* ULPI interface */
-+ usbcfg.b.ulpi_utmi_sel = 1;
-+ usbcfg.b.phyif = 0;
-+ usbcfg.b.ddrsel =
-+ core_if->core_params->phy_ulpi_ddr;
-+ } else if (core_if->core_params->phy_type == 1) {
-+ /* UTMI+ interface */
-+ usbcfg.b.ulpi_utmi_sel = 0;
-+ if (core_if->core_params->phy_utmi_width == 16) {
-+ usbcfg.b.phyif = 1;
-+
-+ } else {
-+ usbcfg.b.phyif = 0;
-+ }
-+ } else {
-+ DWC_ERROR("FS PHY TYPE\n");
-+ }
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+ /* Reset after setting the PHY parameters */
-+ dwc_otg_core_reset(core_if);
-+ }
-+ }
-+
-+ if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) {
-+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.ulpi_fsls = 1;
-+ usbcfg.b.ulpi_clk_sus_m = 1;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+ } else {
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.ulpi_fsls = 0;
-+ usbcfg.b.ulpi_clk_sus_m = 0;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+ }
-+
-+ /* Program the GAHBCFG Register. */
-+ switch (core_if->hwcfg2.b.architecture) {
-+
-+ case DWC_SLAVE_ONLY_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
-+ ahbcfg.b.nptxfemplvl_txfemplvl =
-+ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+ core_if->dma_enable = 0;
-+ core_if->dma_desc_enable = 0;
-+ break;
-+
-+ case DWC_EXT_DMA_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
-+ {
-+ uint8_t brst_sz = core_if->core_params->dma_burst_size;
-+ ahbcfg.b.hburstlen = 0;
-+ while (brst_sz > 1) {
-+ ahbcfg.b.hburstlen++;
-+ brst_sz >>= 1;
-+ }
-+ }
-+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+ core_if->dma_desc_enable =
-+ (core_if->core_params->dma_desc_enable != 0);
-+ break;
-+
-+ case DWC_INT_DMA_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
-+ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
-+ Host mode ISOC in issue fix - vahrama */
-+ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
-+ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
-+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+ core_if->dma_desc_enable =
-+ (core_if->core_params->dma_desc_enable != 0);
-+ break;
-+
-+ }
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ DWC_PRINTF("Using Descriptor DMA mode\n");
-+ } else {
-+ DWC_PRINTF("Using Buffer DMA mode\n");
-+
-+ }
-+ } else {
-+ DWC_PRINTF("Using Slave mode\n");
-+ core_if->dma_desc_enable = 0;
-+ }
-+
-+ if (core_if->core_params->ahb_single) {
-+ ahbcfg.b.ahbsingle = 1;
-+ }
-+
-+ ahbcfg.b.dmaenable = core_if->dma_enable;
-+ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
-+
-+ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
-+
-+ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
-+ core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
-+ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
-+ ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
-+ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
-+ ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
-+
-+ /*
-+ * Program the GUSBCFG register.
-+ */
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+ switch (core_if->hwcfg2.b.op_mode) {
-+ case DWC_MODE_HNP_SRP_CAPABLE:
-+ usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_SRP_ONLY_CAPABLE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_HNP_SRP_CAPABLE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+
-+ case DWC_MODE_SRP_CAPABLE_DEVICE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+
-+ case DWC_MODE_SRP_CAPABLE_HOST:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_SRP_CAPABLE_HOST:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+ }
-+
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (core_if->core_params->lpm_enable) {
-+ glpmcfg_data_t lpmcfg = {.d32 = 0 };
-+
-+ /* To enable LPM support set lpm_cap_en bit */
-+ lpmcfg.b.lpm_cap_en = 1;
-+
-+ /* Make AppL1Res ACK */
-+ lpmcfg.b.appl_resp = 1;
-+
-+ /* Retry 3 times */
-+ lpmcfg.b.retry_count = 3;
-+
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
-+ 0, lpmcfg.d32);
-+
-+ }
-+#endif
-+ if (core_if->core_params->ic_usb_cap) {
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+ gusbcfg.b.ic_usb_cap = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
-+ 0, gusbcfg.d32);
-+ }
-+ {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gotgctl.b.otgver = core_if->core_params->otg_ver;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
-+ gotgctl.d32);
-+ /* Set OTG version supported */
-+ core_if->otg_ver = core_if->core_params->otg_ver;
-+ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
-+ core_if->core_params->otg_ver, core_if->otg_ver);
-+ }
-+
-+
-+ /* Enable common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /* Do device or host intialization based on mode during PCD
-+ * and HCD initialization */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
-+ core_if->op_state = A_HOST;
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
-+ core_if->op_state = B_PERIPHERAL;
-+#ifdef DWC_DEVICE_ONLY
-+ dwc_otg_core_dev_init(core_if);
-+#endif
-+ }
-+}
-+
-+/**
-+ * This function enables the Device mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
-+
-+ /* Disable all interrupts. */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Enable the common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /* Enable interrupts */
-+ intr_mask.b.usbreset = 1;
-+ intr_mask.b.enumdone = 1;
-+ /* Disable Disconnect interrupt in Device mode */
-+ intr_mask.b.disconnect = 0;
-+
-+ if (!core_if->multiproc_int_enable) {
-+ intr_mask.b.inepintr = 1;
-+ intr_mask.b.outepintr = 1;
-+ }
-+
-+ intr_mask.b.erlysuspend = 1;
-+
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.epmismatch = 1;
-+ }
-+
-+ //intr_mask.b.incomplisoout = 1;
-+ intr_mask.b.incomplisoin = 1;
-+
-+/* Enable the ignore frame number for ISOC xfers - MAS */
-+/* Disable to support high bandwith ISOC transfers - manukz */
-+#if 0
-+#ifdef DWC_UTE_PER_IO
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ dctl_data_t dctl1 = {.d32 = 0 };
-+ dctl1.b.ifrmnum = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, 0, dctl1.d32);
-+ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
-+ DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dctl));
-+ }
-+ }
-+#endif
-+#endif
-+#ifdef DWC_EN_ISOC
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ if (core_if->pti_enh_enable) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.ifrmnum = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dctl,
-+ 0, dctl.d32);
-+ } else {
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+ }
-+ }
-+ } else {
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+ }
-+#endif /* DWC_EN_ISOC */
-+
-+ /** @todo NGS: Should this be a module parameter? */
-+#ifdef USE_PERIODIC_EP
-+ intr_mask.b.isooutdrop = 1;
-+ intr_mask.b.eopframe = 1;
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+#endif
-+
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * device mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+ depctl_data_t diepctl = {.d32 = 0 };
-+ grstctl_t resetctl = {.d32 = 0 };
-+ uint32_t rx_fifo_size;
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t txfifosize;
-+ dthrctl_data_t dthrctl;
-+ fifosize_data_t ptxfifosize;
-+ uint16_t rxfsiz, nptxfsiz;
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ hwcfg3_data_t hwcfg3 = {.d32 = 0 };
-+
-+ /* Restart the Phy Clock */
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+
-+ /* Device configuration register */
-+ init_devspd(core_if);
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
-+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
-+ /* Enable Device OUT NAK in case of DDMA mode*/
-+ if (core_if->core_params->dev_out_nak) {
-+ dcfg.b.endevoutnak = 1;
-+ }
-+
-+ if (core_if->core_params->cont_on_bna) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.encontonbna = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
-+ core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
-+ params->dev_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
-+ params->dev_nperio_tx_fifo_size);
-+
-+ /* Rx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+#ifdef DWC_UTE_CFI
-+ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
-+ core_if->init_rxfsiz = params->dev_rx_fifo_size;
-+#endif
-+ rx_fifo_size = params->dev_rx_fifo_size;
-+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+ /** Set Periodic Tx FIFO Mask all bits 0 */
-+ core_if->p_tx_msk = 0;
-+
-+ /** Set Tx FIFO Mask all bits 0 */
-+ core_if->tx_msk = 0;
-+
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz,
-+ nptxfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ /**@todo NGS: Fix Periodic FIFO Sizing! */
-+ /*
-+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_perio_tx_fifo_size array and the FIFO size registers in
-+ * the dptxfsiz array run from 0 to 14.
-+ */
-+ /** @todo Finish debug of this */
-+ ptxfifosize.b.startaddr =
-+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
-+ ptxfifosize.b.depth =
-+ params->dev_perio_tx_fifo_size[i];
-+ DWC_DEBUGPL(DBG_CIL,
-+ "initial dtxfsiz[%d]=%08x\n", i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ ptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
-+ i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+ ptxfifosize.b.startaddr += ptxfifosize.b.depth;
-+ }
-+ } else {
-+ /*
-+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_tx_fifo_size array and the FIFO size registers in
-+ * the dtxfsiz array run from 0 to 14.
-+ */
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+#ifdef DWC_UTE_CFI
-+ core_if->pwron_gnptxfsiz =
-+ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+ core_if->init_gnptxfsiz =
-+ params->dev_nperio_tx_fifo_size;
-+#endif
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz,
-+ nptxfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ txfifosize.b.startaddr =
-+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+ txfifosize.b.depth =
-+ params->dev_tx_fifo_size[i];
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ "initial dtxfsiz[%d]=%08x\n",
-+ i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+
-+#ifdef DWC_UTE_CFI
-+ core_if->pwron_txfsiz[i] =
-+ (DWC_READ_REG32
-+ (&global_regs->dtxfsiz[i]) >> 16);
-+ core_if->init_txfsiz[i] =
-+ params->dev_tx_fifo_size[i];
-+#endif
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ txfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ "new dtxfsiz[%d]=%08x\n",
-+ i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+
-+ txfifosize.b.startaddr += txfifosize.b.depth;
-+ }
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
-+ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
-+ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
-+ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
-+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
-+ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
-+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+ }
-+ }
-+
-+ /* Flush the FIFOs */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ /* Flush the Learning Queue. */
-+ resetctl.b.intknqflsh = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
-+ core_if->start_predict = 0;
-+ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
-+ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
-+ }
-+ core_if->nextep_seq[0] = 0;
-+ core_if->first_in_nextep_seq = 0;
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+ diepctl.b.nextep = 0;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt = 2;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
-+ }
-+ DWC_DEBUGPL(DBG_CILV,"\n");
-+ }
-+
-+ /* Clear all pending Device Interrupts */
-+ /** @todo - if the condition needed to be checked
-+ * or in any case all pending interrutps should be cleared?
-+ */
-+ if (core_if->multiproc_int_enable) {
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_WRITE_REG32(&dev_if->
-+ dev_global_regs->diepeachintmsk[i], 0);
-+ }
-+ }
-+
-+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ DWC_WRITE_REG32(&dev_if->
-+ dev_global_regs->doepeachintmsk[i], 0);
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
-+ } else {
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
-+ }
-+
-+ for (i = 0; i <= dev_if->num_in_eps; i++) {
-+ depctl_data_t depctl;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (depctl.b.epena) {
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ } else {
-+ depctl.d32 = 0;
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
-+ }
-+
-+ for (i = 0; i <= dev_if->num_out_eps; i++) {
-+ depctl_data_t depctl;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+ if (depctl.b.epena) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ gintmsk_data_t gintsts = {.d32 = 0 };
-+ doepint_data_t doepint = {.d32 = 0 };
-+ dctl.b.sgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ } while (!gintsts.b.goutnakeff);
-+ gintsts.d32 = 0;
-+ gintsts.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[i]->doepint);
-+ } while (!doepint.b.epdisabled);
-+
-+ doepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
-+
-+ dctl.d32 = 0;
-+ dctl.b.cgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ } else {
-+ depctl.d32 = 0;
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
-+ }
-+
-+ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
-+ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
-+ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
-+
-+ dev_if->rx_thr_length = params->rx_thr_length;
-+ dev_if->tx_thr_length = params->tx_thr_length;
-+
-+ dev_if->setup_desc_index = 0;
-+
-+ dthrctl.d32 = 0;
-+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
-+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
-+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
-+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
-+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
-+ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
-+ dthrctl.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
-+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
-+ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
-+ dthrctl.b.rx_thr_len);
-+
-+ }
-+
-+ dwc_otg_enable_device_interrupts(core_if);
-+
-+ {
-+ diepmsk_data_t msk = {.d32 = 0 };
-+ msk.b.txfifoundrn = 1;
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->
-+ diepeachintmsk[0], msk.d32, msk.d32);
-+ } else {
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
-+ msk.d32, msk.d32);
-+ }
-+ }
-+
-+ if (core_if->multiproc_int_enable) {
-+ /* Set NAK on Babble */
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.nakonbble = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+
-+ if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
-+ dctl.b.sftdiscon = 0;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function enables the Host mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
-+
-+ /* Disable all interrupts. */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts. */
-+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Enable the common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /*
-+ * Enable host mode interrupts without disturbing common
-+ * interrupts.
-+ */
-+
-+ intr_mask.b.disconnect = 1;
-+ intr_mask.b.portintr = 1;
-+ intr_mask.b.hcintr = 1;
-+
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+}
-+
-+/**
-+ * This function disables the Host Mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
-+
-+ /*
-+ * Disable host mode interrupts without disturbing common
-+ * interrupts.
-+ */
-+ intr_mask.b.sofintr = 1;
-+ intr_mask.b.portintr = 1;
-+ intr_mask.b.hcintr = 1;
-+ intr_mask.b.ptxfempty = 1;
-+ intr_mask.b.nptxfempty = 1;
-+
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * host mode.
-+ *
-+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
-+ * request queues. Host channels are reset to ensure that they are ready for
-+ * performing transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_host_if_t *host_if = core_if->host_if;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t ptxfifosize;
-+ uint16_t rxfsiz, nptxfsiz, hptxfsiz;
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ int i;
-+ hcchar_data_t hcchar;
-+ hcfg_data_t hcfg;
-+ hfir_data_t hfir;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ int num_channels;
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
-+
-+ /* Restart the Phy Clock */
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+
-+ /* Initialize Host Configuration Register */
-+ init_fslspclksel(core_if);
-+ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
-+ hcfg.b.fslssupp = 1;
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+
-+ }
-+
-+ /* This bit allows dynamic reloading of the HFIR register
-+ * during runtime. This bit needs to be programmed during
-+ * initial configuration and its value must not be changed
-+ * during runtime.*/
-+ if (core_if->core_params->reload_ctl == 1) {
-+ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
-+ hfir.b.hfirrldctrl = 1;
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
-+ }
-+
-+ if (core_if->core_params->dma_desc_enable) {
-+ uint8_t op_mode = core_if->hwcfg2.b.op_mode;
-+ if (!
-+ (core_if->hwcfg4.b.desc_dma
-+ && (core_if->snpsid >= OTG_CORE_REV_2_90a)
-+ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+ || (op_mode ==
-+ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
-+ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
-+ || (op_mode ==
-+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
-+
-+ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
-+ "Either core version is below 2.90a or "
-+ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
-+ "To run the driver in Buffer DMA host mode set dma_desc_enable "
-+ "module parameter to 0.\n");
-+ return;
-+ }
-+ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
-+ hcfg.b.descdma = 1;
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+ }
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
-+ core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
-+ params->host_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
-+ params->host_nperio_tx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
-+ params->host_perio_tx_fifo_size);
-+
-+ /* Rx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+ DWC_WRITE_REG32(&global_regs->grxfsiz,
-+ params->host_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->host_rx_fifo_size;
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ /* Periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->hptxfsiz));
-+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
-+ ptxfifosize.b.startaddr =
-+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->hptxfsiz));
-+
-+ if (core_if->en_multiple_tx_fifo
-+ && core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
-+ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
-+ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
-+ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
-+ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
-+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+ }
-+ }
-+
-+ /* TODO - check this */
-+ /* Clear Host Set HNP Enable in the OTG Control Register */
-+ gotgctl.b.hstsethnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+ /* Make sure the FIFOs are flushed. */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ /* Clear Host Set HNP Enable in the OTG Control Register */
-+ gotgctl.b.hstsethnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+
-+ if (!core_if->core_params->dma_desc_enable) {
-+ /* Flush out any leftover queued requests. */
-+ num_channels = core_if->core_params->host_channels;
-+
-+ for (i = 0; i < num_channels; i++) {
-+ hc_regs = core_if->host_if->hc_regs[i];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.chen = 0;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ }
-+
-+ /* Halt all channels to put them into a known state. */
-+ for (i = 0; i < num_channels; i++) {
-+ int count = 0;
-+ hc_regs = core_if->host_if->hc_regs[i];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
-+ do {
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (++count > 1000) {
-+ DWC_ERROR
-+ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
-+ __func__, i, hcchar.d32, &hc_regs->hcchar);
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (hcchar.b.chen);
-+ }
-+ }
-+
-+ /* Turn on the vbus power. */
-+ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
-+ if (core_if->op_state == A_HOST) {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
-+ if (hprt0.b.prtpwr == 0) {
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
-+ }
-+ }
-+
-+ dwc_otg_enable_host_interrupts(core_if);
-+}
-+
-+/**
-+ * Prepares a host channel for transferring packets to/from a specific
-+ * endpoint. The HCCHARn register is set up with the characteristics specified
-+ * in _hc. Host channel interrupts that may need to be serviced while this
-+ * transfer is in progress are enabled.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ * @param hc Information needed to initialize the host channel
-+ */
-+void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ uint32_t intr_enable;
-+ hcintmsk_data_t hc_intr_mask;
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+
-+ uint8_t hc_num = hc->hc_num;
-+ dwc_otg_host_if_t *host_if = core_if->host_if;
-+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
-+
-+ /* Clear old interrupt conditions for this host channel. */
-+ hc_intr_mask.d32 = 0xFFFFFFFF;
-+ hc_intr_mask.b.reserved14_31 = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
-+
-+ /* Enable channel interrupts required for this transfer. */
-+ hc_intr_mask.d32 = 0;
-+ hc_intr_mask.b.chhltd = 1;
-+ if (core_if->dma_enable) {
-+ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
-+ if (!core_if->dma_desc_enable)
-+ hc_intr_mask.b.ahberr = 1;
-+ else {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ hc_intr_mask.b.xfercompl = 1;
-+ }
-+
-+ if (hc->error_state && !hc->do_split &&
-+ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ hc_intr_mask.b.ack = 1;
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.datatglerr = 1;
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+ hc_intr_mask.b.nak = 1;
-+ }
-+ }
-+ }
-+ } else {
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.stall = 1;
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.datatglerr = 1;
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.bblerr = 1;
-+ } else {
-+ hc_intr_mask.b.nak = 1;
-+ hc_intr_mask.b.nyet = 1;
-+ if (hc->do_ping) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+
-+ if (hc->do_split) {
-+ hc_intr_mask.b.nak = 1;
-+ if (hc->complete_split) {
-+ hc_intr_mask.b.nyet = 1;
-+ } else {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+
-+ if (hc->error_state) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ break;
-+ case DWC_OTG_EP_TYPE_INTR:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.nak = 1;
-+ hc_intr_mask.b.stall = 1;
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.datatglerr = 1;
-+ hc_intr_mask.b.frmovrun = 1;
-+
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ if (hc->error_state) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ if (hc->do_split) {
-+ if (hc->complete_split) {
-+ hc_intr_mask.b.nyet = 1;
-+ } else {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+ break;
-+ case DWC_OTG_EP_TYPE_ISOC:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.frmovrun = 1;
-+ hc_intr_mask.b.ack = 1;
-+
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ break;
-+ }
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
-+
-+ /* Enable the top level host channel interrupt. */
-+ intr_enable = (1 << hc_num);
-+ DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
-+
-+ /* Make sure host channel interrupts are enabled. */
-+ gintmsk.b.hcintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+
-+ /*
-+ * Program the HCCHARn register with the endpoint characteristics for
-+ * the current transfer.
-+ */
-+ hcchar.d32 = 0;
-+ hcchar.b.devaddr = hc->dev_addr;
-+ hcchar.b.epnum = hc->ep_num;
-+ hcchar.b.epdir = hc->ep_is_in;
-+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+ hcchar.b.eptype = hc->ep_type;
-+ hcchar.b.mps = hc->max_packet;
-+
-+ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
-+ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
-+ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, "
-+ "Max Pkt %d, Multi Cnt %d\n",
-+ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
-+ hcchar.b.mps, hcchar.b.multicnt);
-+
-+ /*
-+ * Program the HCSPLIT register for SPLITs
-+ */
-+ hcsplt.d32 = 0;
-+ if (hc->do_split) {
-+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
-+ hc->hc_num,
-+ hc->complete_split ? "CSPLIT" : "SSPLIT");
-+ hcsplt.b.compsplt = hc->complete_split;
-+ hcsplt.b.xactpos = hc->xact_pos;
-+ hcsplt.b.hubaddr = hc->hub_addr;
-+ hcsplt.b.prtaddr = hc->port_addr;
-+ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split);
-+ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos);
-+ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr);
-+ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr);
-+ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in);
-+ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps);
-+ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len);
-+ }
-+ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
-+
-+}
-+
-+/**
-+ * Attempts to halt a host channel. This function should only be called in
-+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
-+ * normal circumstances in DMA mode, the controller halts the channel when the
-+ * transfer is complete or a condition occurs that requires application
-+ * intervention.
-+ *
-+ * In slave mode, checks for a free request queue entry, then sets the Channel
-+ * Enable and Channel Disable bits of the Host Channel Characteristics
-+ * register of the specified channel to intiate the halt. If there is no free
-+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
-+ * register to flush requests for this channel. In the latter case, sets a
-+ * flag to indicate that the host channel needs to be halted when a request
-+ * queue slot is open.
-+ *
-+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
-+ * HCCHARn register. The controller ensures there is space in the request
-+ * queue before submitting the halt request.
-+ *
-+ * Some time may elapse before the core flushes any posted requests for this
-+ * host channel and halts. The Channel Halted interrupt handler completes the
-+ * deactivation of the host channel.
-+ *
-+ * @param core_if Controller register interface.
-+ * @param hc Host channel to halt.
-+ * @param halt_status Reason for halting the channel.
-+ */
-+void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
-+ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
-+{
-+ gnptxsts_data_t nptxsts;
-+ hptxsts_data_t hptxsts;
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ dwc_otg_core_global_regs_t *global_regs;
-+ dwc_otg_host_global_regs_t *host_global_regs;
-+
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ global_regs = core_if->core_global_regs;
-+ host_global_regs = core_if->host_if->host_global_regs;
-+
-+ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
-+ "halt_status = %d\n", halt_status);
-+
-+ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+ halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+ /*
-+ * Disable all channel interrupts except Ch Halted. The QTD
-+ * and QH state associated with this transfer has been cleared
-+ * (in the case of URB_DEQUEUE), so the channel needs to be
-+ * shut down carefully to prevent crashes.
-+ */
-+ hcintmsk_data_t hcintmsk;
-+ hcintmsk.d32 = 0;
-+ hcintmsk.b.chhltd = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
-+
-+ /*
-+ * Make sure no other interrupts besides halt are currently
-+ * pending. Handling another interrupt could cause a crash due
-+ * to the QTD and QH state.
-+ */
-+ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
-+
-+ /*
-+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
-+ * even if the channel was already halted for some other
-+ * reason.
-+ */
-+ hc->halt_status = halt_status;
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen == 0) {
-+ /*
-+ * The channel is either already halted or it hasn't
-+ * started yet. In DMA mode, the transfer may halt if
-+ * it finishes normally or a condition occurs that
-+ * requires driver intervention. Don't want to halt
-+ * the channel again. In either Slave or DMA mode,
-+ * it's possible that the transfer has been assigned
-+ * to a channel, but not started yet when an URB is
-+ * dequeued. Don't want to halt a channel that hasn't
-+ * started yet.
-+ */
-+ return;
-+ }
-+ }
-+ if (hc->halt_pending) {
-+ /*
-+ * A halt has already been issued for this channel. This might
-+ * happen when a transfer is aborted by a higher level in
-+ * the stack.
-+ */
-+#ifdef DEBUG
-+ DWC_PRINTF
-+ ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
-+ __func__, hc->hc_num);
-+
-+#endif
-+ return;
-+ }
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* No need to set the bit in DDMA for disabling the channel */
-+ //TODO check it everywhere channel is disabled
-+ if (!core_if->core_params->dma_desc_enable)
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 1;
-+
-+ if (!core_if->dma_enable) {
-+ /* Check for space in the request queue to issue the halt. */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ if (nptxsts.b.nptxqspcavail == 0) {
-+ hcchar.b.chen = 0;
-+ }
-+ } else {
-+ hptxsts.d32 =
-+ DWC_READ_REG32(&host_global_regs->hptxsts);
-+ if ((hptxsts.b.ptxqspcavail == 0)
-+ || (core_if->queuing_high_bandwidth)) {
-+ hcchar.b.chen = 0;
-+ }
-+ }
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->halt_status = halt_status;
-+
-+ if (hcchar.b.chen) {
-+ hc->halt_pending = 1;
-+ hc->halt_on_queue = 0;
-+ } else {
-+ hc->halt_on_queue = 1;
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
-+
-+ return;
-+}
-+
-+/**
-+ * Clears the transfer state for a host channel. This function is normally
-+ * called after a transfer is done and the host channel is being released.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to clean up.
-+ */
-+void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ dwc_otg_hc_regs_t *hc_regs;
-+
-+ hc->xfer_started = 0;
-+
-+ /*
-+ * Clear channel interrupt enables and any unhandled channel interrupt
-+ * conditions.
-+ */
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
-+ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
-+#ifdef DEBUG
-+ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
-+#endif
-+}
-+
-+/**
-+ * Sets the channel property that indicates in which frame a periodic transfer
-+ * should occur. This is always set to the _next_ frame. This function has no
-+ * effect on non-periodic transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to set up and its properties.
-+ * @param hcchar Current value of the HCCHAR register for the specified host
-+ * channel.
-+ */
-+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
-+ dwc_hc_t * hc, hcchar_data_t * hcchar)
-+{
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ hfnum_data_t hfnum;
-+ hfnum.d32 =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
-+
-+ /* 1 if _next_ frame is odd, 0 if it's even */
-+ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
-+#ifdef DEBUG
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
-+ && !hc->complete_split) {
-+ switch (hfnum.b.frnum & 0x7) {
-+ case 7:
-+ core_if->hfnum_7_samples++;
-+ core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
-+ break;
-+ case 0:
-+ core_if->hfnum_0_samples++;
-+ core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
-+ break;
-+ default:
-+ core_if->hfnum_other_samples++;
-+ core_if->hfnum_other_frrem_accum +=
-+ hfnum.b.frrem;
-+ break;
-+ }
-+ }
-+#endif
-+ }
-+}
-+
-+#ifdef DEBUG
-+void hc_xfer_timeout(void *ptr)
-+{
-+ hc_xfer_info_t *xfer_info = NULL;
-+ int hc_num = 0;
-+
-+ if (ptr)
-+ xfer_info = (hc_xfer_info_t *) ptr;
-+
-+ if (!xfer_info->hc) {
-+ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
-+ return;
-+ }
-+
-+ hc_num = xfer_info->hc->hc_num;
-+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
-+ DWC_WARN(" start_hcchar_val 0x%08x\n",
-+ xfer_info->core_if->start_hcchar_val[hc_num]);
-+}
-+#endif
-+
-+void ep_xfer_timeout(void *ptr)
-+{
-+ ep_xfer_info_t *xfer_info = NULL;
-+ int ep_num = 0;
-+ dctl_data_t dctl = {.d32 = 0 };
-+ gintsts_data_t gintsts = {.d32 = 0 };
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+ if (ptr)
-+ xfer_info = (ep_xfer_info_t *) ptr;
-+
-+ if (!xfer_info->ep) {
-+ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
-+ return;
-+ }
-+
-+ ep_num = xfer_info->ep->num;
-+ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
-+ /* Put the sate to 2 as it was time outed */
-+ xfer_info->state = 2;
-+
-+ dctl.d32 =
-+ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
-+ gintsts.d32 =
-+ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
-+ gintmsk.d32 =
-+ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
-+
-+ if (!gintmsk.b.goutnakeff) {
-+ /* Unmask it */
-+ gintmsk.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
-+ gintmsk.d32);
-+
-+ }
-+
-+ if (!gintsts.b.goutnakeff) {
-+ dctl.b.sgoutnak = 1;
-+ }
-+ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+
-+}
-+
-+void set_pid_isoc(dwc_hc_t * hc)
-+{
-+ /* Set up the initial PID for the transfer. */
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ if (hc->ep_is_in) {
-+ if (hc->multi_count == 1) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ } else if (hc->multi_count == 2) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+ } else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
-+ }
-+ } else {
-+ if (hc->multi_count == 1) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ } else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
-+ }
-+ }
-+ } else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for a host channel and
-+ * starts the transfer. May be called in either Slave mode or DMA mode. In
-+ * Slave mode, the caller must ensure that there is sufficient space in the
-+ * request queue and Tx Data FIFO.
-+ *
-+ * For an OUT transfer in Slave mode, it loads a data packet into the
-+ * appropriate FIFO. If necessary, additional data packets will be loaded in
-+ * the Host ISR.
-+ *
-+ * For an IN transfer in Slave mode, a data packet is requested. The data
-+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
-+ * additional data packets are requested in the Host ISR.
-+ *
-+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
-+ * register along with a packet count of 1 and the channel is enabled. This
-+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
-+ * simply set to 0 since no data transfer occurs in this case.
-+ *
-+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
-+ * all the information required to perform the subsequent data transfer. In
-+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
-+ * controller performs the entire PING protocol, then starts the data
-+ * transfer.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel. The xfer_len
-+ * value may be reduced to accommodate the max widths of the XferSize and
-+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
-+ * to reflect the final xfer_len value.
-+ */
-+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ uint16_t num_packets;
-+ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
-+ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ hctsiz.d32 = 0;
-+
-+ if (hc->do_ping) {
-+ if (!core_if->dma_enable) {
-+ dwc_otg_hc_do_ping(core_if, hc);
-+ hc->xfer_started = 1;
-+ return;
-+ } else {
-+ hctsiz.b.dopng = 1;
-+ }
-+ }
-+
-+ if (hc->do_split) {
-+ num_packets = 1;
-+
-+ if (hc->complete_split && !hc->ep_is_in) {
-+ /* For CSPLIT OUT Transfer, set the size to 0 so the
-+ * core doesn't expect any data written to the FIFO */
-+ hc->xfer_len = 0;
-+ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+ hc->xfer_len = hc->max_packet;
-+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+ hc->xfer_len = 188;
-+ }
-+
-+ hctsiz.b.xfersize = hc->xfer_len;
-+ } else {
-+ /*
-+ * Ensure that the transfer length and packet count will fit
-+ * in the widths allocated for them in the HCTSIZn register.
-+ */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * Make sure the transfer size is no larger than one
-+ * (micro)frame's worth of data. (A check was done
-+ * when the periodic transfer was accepted to ensure
-+ * that a (micro)frame's worth of data can be
-+ * programmed into a channel.)
-+ */
-+ uint32_t max_periodic_len =
-+ hc->multi_count * hc->max_packet;
-+ if (hc->xfer_len > max_periodic_len) {
-+ hc->xfer_len = max_periodic_len;
-+ } else {
-+ }
-+ } else if (hc->xfer_len > max_hc_xfer_size) {
-+ /* Make sure that xfer_len is a multiple of max packet size. */
-+ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
-+ }
-+
-+ if (hc->xfer_len > 0) {
-+ num_packets =
-+ (hc->xfer_len + hc->max_packet -
-+ 1) / hc->max_packet;
-+ if (num_packets > max_hc_pkt_count) {
-+ num_packets = max_hc_pkt_count;
-+ hc->xfer_len = num_packets * hc->max_packet;
-+ }
-+ } else {
-+ /* Need 1 packet for transfer length of 0. */
-+ num_packets = 1;
-+ }
-+
-+ if (hc->ep_is_in) {
-+ /* Always program an integral # of max packets for IN transfers. */
-+ hc->xfer_len = num_packets * hc->max_packet;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * Make sure that the multi_count field matches the
-+ * actual transfer length.
-+ */
-+ hc->multi_count = num_packets;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ set_pid_isoc(hc);
-+
-+ hctsiz.b.xfersize = hc->xfer_len;
-+ }
-+
-+ hc->start_pkt_count = num_packets;
-+ hctsiz.b.pktcnt = num_packets;
-+ hctsiz.b.pid = hc->data_pid_start;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
-+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
-+
-+ if (core_if->dma_enable) {
-+ dwc_dma_t dma_addr;
-+ if (hc->align_buff) {
-+ dma_addr = hc->align_buff;
-+ } else {
-+ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
-+ }
-+
-+ /* Start the split */
-+ if (hc->do_split) {
-+ hcsplt_data_t hcsplt;
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ hcsplt.b.spltena = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
-+ }
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.multicnt = hc->multi_count;
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+#ifdef DEBUG
-+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+ __func__, hc->hc_num, hcchar.d32);
-+ }
-+#endif
-+
-+ /* Set host channel enable after all other setup is complete. */
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->xfer_started = 1;
-+ hc->requests++;
-+
-+ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
-+ /* Load OUT packet into the appropriate Tx FIFO. */
-+ dwc_otg_hc_write_packet(core_if, hc);
-+ }
-+#ifdef DEBUG
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
-+ hc->hc_num, core_if);//GRAYG
-+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+ core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+
-+ /* Start a timer for this transfer. */
-+ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
-+ }
-+#endif
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for a host channel
-+ * and starts the transfer in Descriptor DMA mode.
-+ *
-+ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
-+ * Sets PID and NTD values. For periodic transfers
-+ * initializes SCHED_INFO field with micro-frame bitmap.
-+ *
-+ * Initializes HCDMA register with descriptor list address and CTD value
-+ * then starts the transfer via enabling the channel.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel.
-+ */
-+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ hcdma_data_t hcdma;
-+
-+ hctsiz.d32 = 0;
-+
-+ if (hc->do_ping)
-+ hctsiz.b_ddma.dopng = 1;
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ set_pid_isoc(hc);
-+
-+ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
-+ hctsiz.b_ddma.pid = hc->data_pid_start;
-+ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
-+ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
-+ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
-+
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ hcdma.d32 = 0;
-+ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
-+
-+ /* Always start from first descriptor. */
-+ hcdma.b.ctd = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.multicnt = hc->multi_count;
-+
-+#ifdef DEBUG
-+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+ __func__, hc->hc_num, hcchar.d32);
-+ }
-+#endif
-+
-+ /* Set host channel enable after all other setup is complete. */
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->xfer_started = 1;
-+ hc->requests++;
-+
-+#ifdef DEBUG
-+ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
-+ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
-+ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
-+ hc->hc_num, core_if);//GRAYG
-+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+ core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+ /* Start a timer for this transfer. */
-+ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
-+ }
-+#endif
-+
-+}
-+
-+/**
-+ * This function continues a data transfer that was started by previous call
-+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
-+ * sufficient space in the request queue and Tx Data FIFO. This function
-+ * should only be called in Slave mode. In DMA mode, the controller acts
-+ * autonomously to complete transfers programmed to a host channel.
-+ *
-+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
-+ * if there is any data remaining to be queued. For an IN transfer, another
-+ * data packet is always requested. For the SETUP phase of a control transfer,
-+ * this function does nothing.
-+ *
-+ * @return 1 if a new request is queued, 0 if no more requests are required
-+ * for this transfer.
-+ */
-+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+ if (hc->do_split) {
-+ /* SPLITs always queue just once per channel */
-+ return 0;
-+ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+ /* SETUPs are queued only once since they can't be NAKed. */
-+ return 0;
-+ } else if (hc->ep_is_in) {
-+ /*
-+ * Always queue another request for other IN transfers. If
-+ * back-to-back INs are issued and NAKs are received for both,
-+ * the driver may still be processing the first NAK when the
-+ * second NAK is received. When the interrupt handler clears
-+ * the NAK interrupt for the first NAK, the second NAK will
-+ * not be seen. So we can't depend on the NAK interrupt
-+ * handler to requeue a NAKed request. Instead, IN requests
-+ * are issued each time this function is called. When the
-+ * transfer completes, the extra requests for the channel will
-+ * be flushed.
-+ */
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs =
-+ core_if->host_if->hc_regs[hc->hc_num];
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
-+ hcchar.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ hc->requests++;
-+ return 1;
-+ } else {
-+ /* OUT transfers. */
-+ if (hc->xfer_count < hc->xfer_len) {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+ }
-+
-+ /* Load OUT packet into the appropriate Tx FIFO. */
-+ dwc_otg_hc_write_packet(core_if, hc);
-+ hc->requests++;
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+ }
-+}
-+
-+/**
-+ * Starts a PING transfer. This function should only be called in Slave mode.
-+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
-+ */
-+void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+ hctsiz.d32 = 0;
-+ hctsiz.b.dopng = 1;
-+ hctsiz.b.pktcnt = 1;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+}
-+
-+/*
-+ * This function writes a packet into the Tx FIFO associated with the Host
-+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
-+ * Tx FIFO is written. For a channel associated with a periodic EP, the
-+ * periodic Tx FIFO is written. This function should only be called in Slave
-+ * mode.
-+ *
-+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
-+ * then number of bytes written to the Tx FIFO.
-+ */
-+void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ uint32_t i;
-+ uint32_t remaining_count;
-+ uint32_t byte_count;
-+ uint32_t dword_count;
-+
-+ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
-+ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
-+
-+ remaining_count = hc->xfer_len - hc->xfer_count;
-+ if (remaining_count > hc->max_packet) {
-+ byte_count = hc->max_packet;
-+ } else {
-+ byte_count = remaining_count;
-+ }
-+
-+ dword_count = (byte_count + 3) / 4;
-+
-+ if ((((unsigned long)data_buff) & 0x3) == 0) {
-+ /* xfer_buff is DWORD aligned. */
-+ for (i = 0; i < dword_count; i++, data_buff++) {
-+ DWC_WRITE_REG32(data_fifo, *data_buff);
-+ }
-+ } else {
-+ /* xfer_buff is not DWORD aligned. */
-+ for (i = 0; i < dword_count; i++, data_buff++) {
-+ uint32_t data;
-+ data =
-+ (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
-+ 16 | data_buff[3] << 24);
-+ DWC_WRITE_REG32(data_fifo, data);
-+ }
-+ }
-+
-+ hc->xfer_count += byte_count;
-+ hc->xfer_buff += byte_count;
-+}
-+
-+/**
-+ * Gets the current USB frame number. This is the frame number from the last
-+ * SOF packet.
-+ */
-+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ /* read current frame/microframe number from DSTS register */
-+ return dsts.b.soffn;
-+}
-+
-+/**
-+ * Calculates and gets the frame Interval value of HFIR register according PHY
-+ * type and speed.The application can modify a value of HFIR register only after
-+ * the Port Enable bit of the Host Port Control and Status register
-+ * (HPRT.PrtEnaPort) has been set.
-+*/
-+
-+uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
-+{
-+ gusbcfg_data_t usbcfg;
-+ hwcfg2_data_t hwcfg2;
-+ hprt0_data_t hprt0;
-+ int clock = 60; // default value
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
-+ clock = 60;
-+ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
-+ clock = 48;
-+ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
-+ clock = 30;
-+ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
-+ clock = 60;
-+ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
-+ clock = 48;
-+ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
-+ clock = 48;
-+ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
-+ clock = 48;
-+ if (hprt0.b.prtspd == 0)
-+ /* High speed case */
-+ return 125 * clock;
-+ else
-+ /* FS/LS case */
-+ return 1000 * clock;
-+}
-+
-+/**
-+ * This function reads a setup packet from the Rx FIFO into the destination
-+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
-+ * Interrupt routine when a SETUP packet has been received in Slave mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for packet data.
-+ */
-+void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
-+{
-+ device_grxsts_data_t status;
-+ /* Get the 8 bytes of a setup transaction data */
-+
-+ /* Pop 2 DWORDS off the receive data FIFO into memory */
-+ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
-+ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ status.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
-+ status.b.epnum, status.b.bcnt, status.b.pktsts,
-+ status.b.fn, status.b.fn);
-+ }
-+}
-+
-+/**
-+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
-+ * IN for transmitting packets. It is normally called when the
-+ * "Enumeration Done" interrupt occurs.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dsts_data_t dsts;
-+ depctl_data_t diepctl;
-+ depctl_data_t doepctl;
-+ dctl_data_t dctl = {.d32 = 0 };
-+
-+ ep->stp_rollover = 0;
-+ /* Read the Device Status and Endpoint 0 Control registers */
-+ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
-+
-+ /* Set the MPS of the IN EP based on the enumeration speed */
-+ switch (dsts.b.enumspd) {
-+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+ diepctl.b.mps = DWC_DEP0CTL_MPS_64;
-+ break;
-+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+ diepctl.b.mps = DWC_DEP0CTL_MPS_8;
-+ break;
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Enable OUT EP for receive */
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ doepctl.b.epena = 1;
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+ }
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+ dctl.b.cgnpinnak = 1;
-+
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
-+ DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
-+
-+}
-+
-+/**
-+ * This function activates an EP. The Device EP control register for
-+ * the EP is configured as defined in the ep structure. Note: This
-+ * function is not used for EP0.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to activate.
-+ */
-+void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ depctl_data_t depctl;
-+ volatile uint32_t *addr;
-+ daint_data_t daintmsk = {.d32 = 0 };
-+ dcfg_data_t dcfg;
-+ uint8_t i;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
-+ (ep->is_in ? "IN" : "OUT"));
-+
-+#ifdef DWC_UTE_PER_IO
-+ ep->xiso_frame_num = 0xFFFFFFFF;
-+ ep->xiso_active_xfers = 0;
-+ ep->xiso_queued_xfers = 0;
-+#endif
-+ /* Read DEPCTLn register */
-+ if (ep->is_in == 1) {
-+ addr = &dev_if->in_ep_regs[ep->num]->diepctl;
-+ daintmsk.ep.in = 1 << ep->num;
-+ } else {
-+ addr = &dev_if->out_ep_regs[ep->num]->doepctl;
-+ daintmsk.ep.out = 1 << ep->num;
-+ }
-+
-+ /* If the EP is already active don't change the EP Control
-+ * register. */
-+ depctl.d32 = DWC_READ_REG32(addr);
-+ if (!depctl.b.usbactep) {
-+ depctl.b.mps = ep->maxpacket;
-+ depctl.b.eptype = ep->type;
-+ depctl.b.txfnum = ep->tx_fifo_num;
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ depctl.b.setd0pid = 1; // ???
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ depctl.b.usbactep = 1;
-+
-+ /* Update nextep_seq array and EPMSCNT in DCFG*/
-+ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
-+ break;
-+ }
-+ core_if->nextep_seq[i] = ep->num;
-+ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt++;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV, "%2d\n",
-+ core_if->nextep_seq[i]);
-+ }
-+
-+ }
-+
-+
-+ DWC_WRITE_REG32(addr, depctl.d32);
-+ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
-+ }
-+
-+ /* Enable the Interrupt for this EP */
-+ if (core_if->multiproc_int_enable) {
-+ if (ep->is_in == 1) {
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ diepmsk.b.intknepmis = 1;
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+ diepmsk.b.intknepmis = 0;
-+ diepmsk.b.txfifoundrn = 1; //?????
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ diepmsk.b.nak = 1;
-+ }
-+
-+
-+
-+/*
-+ if (core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+*/
-+/*
-+ if (core_if->dma_enable) {
-+ doepmsk.b.nak = 1;
-+ }
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->
-+ diepeachintmsk[ep->num], diepmsk.d32);
-+
-+ } else {
-+ doepmsk_data_t doepmsk = {.d32 = 0 };
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
-+ doepmsk.b.outtknepdis = 1;
-+
-+/*
-+
-+ if (core_if->dma_desc_enable) {
-+ doepmsk.b.bna = 1;
-+ }
-+*/
-+/*
-+ doepmsk.b.babble = 1;
-+ doepmsk.b.nyet = 1;
-+ doepmsk.b.nak = 1;
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->
-+ doepeachintmsk[ep->num], doepmsk.d32);
-+ }
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
-+ 0, daintmsk.d32);
-+ } else {
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (ep->is_in) {
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.nak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
-+ } else {
-+ doepmsk_data_t doepmsk = {.d32 = 0 };
-+ doepmsk.b.outtknepdis = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
-+ }
-+ }
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
-+ 0, daintmsk.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
-+ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
-+
-+ ep->stall_clear_flag = 0;
-+
-+ return;
-+}
-+
-+/**
-+ * This function deactivates an EP. This is done by clearing the USB Active
-+ * EP bit in the Device EP control register. Note: This function is not used
-+ * for EP0. EP0 cannot be deactivated.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to deactivate.
-+ */
-+void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+ daint_data_t daintmsk = {.d32 = 0 };
-+ dcfg_data_t dcfg;
-+ uint8_t i = 0;
-+
-+#ifdef DWC_UTE_PER_IO
-+ ep->xiso_frame_num = 0xFFFFFFFF;
-+ ep->xiso_active_xfers = 0;
-+ ep->xiso_queued_xfers = 0;
-+#endif
-+
-+ /* Read DEPCTLn register */
-+ if (ep->is_in == 1) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ daintmsk.ep.in = 1 << ep->num;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ daintmsk.ep.out = 1 << ep->num;
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(addr);
-+
-+ depctl.b.usbactep = 0;
-+
-+ /* Update nextep_seq array and EPMSCNT in DCFG*/
-+ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ if (core_if->nextep_seq[i] == ep->num)
-+ break;
-+ }
-+ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
-+ if (core_if->first_in_nextep_seq == ep->num)
-+ core_if->first_in_nextep_seq = i;
-+ core_if->nextep_seq[ep->num] = 0xff;
-+ depctl.b.nextep = 0;
-+ dcfg.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt--;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+ dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
-+ }
-+ }
-+
-+ if (ep->is_in == 1)
-+ depctl.b.txfnum = 0;
-+
-+ if (core_if->dma_desc_enable)
-+ depctl.b.epdis = 1;
-+
-+ DWC_WRITE_REG32(addr, depctl.d32);
-+ depctl.d32 = DWC_READ_REG32(addr);
-+ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
-+ && depctl.b.epena) {
-+ depctl_data_t depctl = {.d32 = 0};
-+ if (ep->is_in) {
-+ diepint_data_t diepint = {.d32 = 0};
-+
-+ depctl.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepctl, depctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->in_ep_regs[ep->num]->
-+ diepint);
-+ } while (!diepint.b.inepnakeff);
-+ diepint.b.inepnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepint, diepint.d32);
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepctl, depctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->in_ep_regs[ep->num]->
-+ diepint);
-+ } while (!diepint.b.epdisabled);
-+ diepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepint, diepint.d32);
-+ } else {
-+ dctl_data_t dctl = {.d32 = 0};
-+ gintmsk_data_t gintsts = {.d32 = 0};
-+ doepint_data_t doepint = {.d32 = 0};
-+ dctl.b.sgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, 0, dctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ } while (!gintsts.b.goutnakeff);
-+ gintsts.d32 = 0;
-+ gintsts.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
-+ do
-+ {
-+ dwc_udelay(10);
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->num]->doepint);
-+ } while (!doepint.b.epdisabled);
-+
-+ doepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
-+
-+ dctl.d32 = 0;
-+ dctl.b.cgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+ }
-+
-+ /* Disable the Interrupt for this EP */
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+ daintmsk.d32, 0);
-+
-+ if (ep->is_in == 1) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ diepeachintmsk[ep->num], 0);
-+ } else {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[ep->num], 0);
-+ }
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
-+ daintmsk.d32, 0);
-+ }
-+
-+}
-+
-+/**
-+ * This function initializes dma descriptor chain.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ uint32_t offset;
-+ uint32_t xfer_est;
-+ int i;
-+ unsigned maxxfer_local, total_len;
-+
-+ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
-+ (ep->maxpacket%4)) {
-+ maxxfer_local = ep->maxpacket;
-+ total_len = ep->xfer_len;
-+ } else {
-+ maxxfer_local = ep->maxxfer;
-+ total_len = ep->total_len;
-+ }
-+
-+ ep->desc_cnt = (total_len / maxxfer_local) +
-+ ((total_len % maxxfer_local) ? 1 : 0);
-+
-+ if (!ep->desc_cnt)
-+ ep->desc_cnt = 1;
-+
-+ if (ep->desc_cnt > MAX_DMA_DESC_CNT)
-+ ep->desc_cnt = MAX_DMA_DESC_CNT;
-+
-+ dma_desc = ep->desc_addr;
-+ if (maxxfer_local == ep->maxpacket) {
-+ if ((total_len % maxxfer_local) &&
-+ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
-+ xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
-+ (total_len % maxxfer_local);
-+ } else
-+ xfer_est = ep->desc_cnt * maxxfer_local;
-+ } else
-+ xfer_est = total_len;
-+ offset = 0;
-+ for (i = 0; i < ep->desc_cnt; ++i) {
-+ /** DMA Descriptor Setup */
-+ if (xfer_est > maxxfer_local) {
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 0;
-+ dma_desc->status.b.ioc = 0;
-+ dma_desc->status.b.sp = 0;
-+ dma_desc->status.b.bytes = maxxfer_local;
-+ dma_desc->buf = ep->dma_addr + offset;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ xfer_est -= maxxfer_local;
-+ offset += maxxfer_local;
-+ } else {
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ if (ep->is_in) {
-+ dma_desc->status.b.sp =
-+ (xfer_est %
-+ ep->maxpacket) ? 1 : ((ep->
-+ sent_zlp) ? 1 : 0);
-+ dma_desc->status.b.bytes = xfer_est;
-+ } else {
-+ if (maxxfer_local == ep->maxpacket)
-+ dma_desc->status.b.bytes = xfer_est;
-+ else
-+ dma_desc->status.b.bytes =
-+ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
-+ }
-+
-+ dma_desc->buf = ep->dma_addr + offset;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+ }
-+ dma_desc++;
-+ }
-+}
-+/**
-+ * This function is called when to write ISOC data into appropriate dedicated
-+ * periodic FIFO.
-+ */
-+static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0 };
-+ uint32_t len = 0;
-+ int epnum = dwc_ep->num;
-+ int dwords;
-+
-+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+ len = dwc_ep->xfer_len - dwc_ep->xfer_count;
-+
-+ if (len > dwc_ep->maxpacket) {
-+ len = dwc_ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
-+
-+ len = dwc_ep->xfer_len - dwc_ep->xfer_count;
-+ if (len > dwc_ep->maxpacket) {
-+ len = dwc_ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
-+ txstatus.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
-+
-+ return 1;
-+}
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
-+ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
-+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
-+ ep->total_len);
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[ep->num];
-+
-+ gnptxsts_data_t gtxstatus;
-+
-+ gtxstatus.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+
-+ if (core_if->en_multiple_tx_fifo == 0
-+ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
-+#ifdef DEBUG
-+ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
-+#endif
-+ return;
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
-+
-+ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
-+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+ ep->maxxfer : (ep->total_len - ep->xfer_len);
-+ else
-+ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
-+ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-+
-+
-+ /* Zero Length Packet? */
-+ if ((ep->xfer_len - ep->xfer_count) == 0) {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+ } else {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - ep->xfer_count - 1 +
-+ ep->maxpacket) / ep->maxpacket;
-+ if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
-+ deptsiz.b.pktcnt = MAX_PKT_CNT;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+ }
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
-+ deptsiz.b.mc = deptsiz.b.pktcnt;
-+ }
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ if (ep->type != DWC_OTG_EP_TYPE_ISOC)
-+ deptsiz.b.mc = 1;
-+ DWC_WRITE_REG32(&in_regs->dieptsiz,
-+ deptsiz.d32);
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+#ifdef DWC_UTE_CFI
-+ /* The descriptor chain should be already initialized by now */
-+ if (ep->buff_mode != BM_STANDARD) {
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ ep->descs_dma_addr);
-+ } else {
-+#endif
-+ init_dma_desc_chain(core_if, ep);
-+ /** DIEPDMAn Register write */
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ ep->dma_desc_addr);
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt,
-+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+ * the data will be written into the fifo by the ISR.
-+ */
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32
-+ (&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk = 1 << ep->num;
-+ DWC_MODIFY_REG32
-+ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+
-+ }
-+ }
-+ } else {
-+ write_isoc_tx_fifo(core_if, ep);
-+ }
-+ }
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ dsts_data_t dsts = {.d32 = 0};
-+ if (ep->bInterval == 1) {
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dsts);
-+ ep->frame_num = dsts.b.soffn + ep->bInterval;
-+ if (ep->frame_num > 0x3FFF) {
-+ ep->frm_overrun = 1;
-+ ep->frame_num &= 0x3FFF;
-+ } else
-+ ep->frm_overrun = 0;
-+ if (ep->frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ }
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ } else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[ep->num];
-+
-+ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
-+
-+ if (!core_if->dma_desc_enable) {
-+ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
-+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+ ep->maxxfer : (ep->total_len - ep->xfer_len);
-+ else
-+ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
-+ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-+ }
-+
-+ /* Program the transfer size and packet count as follows:
-+ *
-+ * pktcnt = N
-+ * xfersize = N * maxpacket
-+ */
-+ if ((ep->xfer_len - ep->xfer_count) == 0) {
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - ep->xfer_count +
-+ (ep->maxpacket - 1)) / ep->maxpacket;
-+ if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
-+ deptsiz.b.pktcnt = MAX_PKT_CNT;
-+ }
-+ if (!core_if->dma_desc_enable) {
-+ ep->xfer_len =
-+ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
-+ }
-+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
-+ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+#ifdef DWC_UTE_CFI
-+ /* The descriptor chain should be already initialized by now */
-+ if (ep->buff_mode != BM_STANDARD) {
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ ep->descs_dma_addr);
-+ } else {
-+#endif
-+ /** This is used for interrupt out transfers*/
-+ if (!ep->xfer_len)
-+ ep->xfer_len = ep->total_len;
-+ init_dma_desc_chain(core_if, ep);
-+
-+ if (core_if->core_params->dev_out_nak) {
-+ if (ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ deptsiz.b.pktcnt = (ep->total_len +
-+ (ep->maxpacket - 1)) / ep->maxpacket;
-+ deptsiz.b.xfersize = ep->total_len;
-+ /* Remember initial value of doeptsiz */
-+ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+ }
-+ }
-+ /** DOEPDMAn Register write */
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ ep->dma_desc_addr);
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ dsts_data_t dsts = {.d32 = 0};
-+ if (ep->bInterval == 1) {
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dsts);
-+ ep->frame_num = dsts.b.soffn + ep->bInterval;
-+ if (ep->frame_num > 0x3FFF) {
-+ ep->frm_overrun = 1;
-+ ep->frame_num &= 0x3FFF;
-+ } else
-+ ep->frm_overrun = 0;
-+
-+ if (ep->frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+
-+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
-+ DWC_READ_REG32(&out_regs->doepctl),
-+ DWC_READ_REG32(&out_regs->doeptsiz));
-+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
-+ daintmsk),
-+ DWC_READ_REG32(&core_if->core_global_regs->
-+ gintmsk));
-+
-+ /* Timer is scheduling only for out bulk transfers for
-+ * "Device DDMA OUT NAK Enhancement" feature to inform user
-+ * about received data payload in case of timeout
-+ */
-+ if (core_if->core_params->dev_out_nak) {
-+ if (ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ core_if->ep_xfer_info[ep->num].core_if = core_if;
-+ core_if->ep_xfer_info[ep->num].ep = ep;
-+ core_if->ep_xfer_info[ep->num].state = 1;
-+
-+ /* Start a timer for this transfer. */
-+ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * This function setup a zero length transfer in Buffer DMA and
-+ * Slave modes for usb requests with zero field set
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+
-+ depctl_data_t depctl;
-+ deptsiz_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+ DWC_PRINTF("zero length transfer is called\n");
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[ep->num];
-+
-+ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
-+
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.b.mc = 1;
-+ DWC_WRITE_REG32(&in_regs->dieptsiz,
-+ deptsiz.d32);
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt,
-+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+ * the data will be written into the fifo by the ISR.
-+ */
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk = 1 << ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ } else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[ep->num];
-+
-+ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
-+
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+
-+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for EP0 and starts
-+ * the transfer. For an IN transfer, the packets will be loaded into
-+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
-+ * unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz0_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+
-+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+ "xfer_buff=%p start_xfer_buff=%p \n",
-+ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
-+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
-+
-+ ep->total_len = ep->xfer_len;
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[0];
-+
-+ gnptxsts_data_t gtxstatus;
-+
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+ if (depctl.b.epena)
-+ return;
-+ }
-+
-+ gtxstatus.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+
-+ /* If dedicated FIFO every time flush fifo before enable ep*/
-+ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
-+
-+ if (core_if->en_multiple_tx_fifo == 0
-+ && gtxstatus.b.nptxqspcavail == 0
-+ && !core_if->dma_enable) {
-+#ifdef DEBUG
-+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
-+ DWC_READ_REG32(&in_regs->diepctl));
-+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
-+ deptsiz.d32,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
-+ gtxstatus.d32);
-+#endif
-+ return;
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+
-+ /* Zero Length Packet? */
-+ if (ep->xfer_len == 0) {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+ } else {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ if (ep->xfer_len > ep->maxpacket) {
-+ ep->xfer_len = ep->maxpacket;
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ } else {
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ }
-+ deptsiz.b.pktcnt = 1;
-+
-+ }
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+ dma_desc = core_if->dev_if->in_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.sp =
-+ (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+ dma_desc->status.b.bytes = ep->xfer_len;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DIEPDMA0 Register write */
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ core_if->
-+ dev_if->dma_in_desc_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ }
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+ * data will be written into the fifo by the ISR.
-+ */
-+ if (!core_if->dma_enable) {
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk |= 1 << ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+ } else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[0];
-+
-+ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
-+
-+ /* Program the transfer size and packet count as follows:
-+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
-+ * pktcnt = N */
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ deptsiz.b.supcnt = 3;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+ dma_desc = core_if->dev_if->out_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ dma_desc->status.b.mtrf = 0;
-+ dma_desc->status.b.sr = 0;
-+ }
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = ep->maxpacket;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ core_if->dev_if->
-+ dma_out_desc_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function continues control IN transfers started by
-+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
-+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
-+ * bit for the packet count.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz0_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[0];
-+ gnptxsts_data_t tx_status = {.d32 = 0 };
-+
-+ tx_status.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+ /** @todo Should there be check for room in the Tx
-+ * Status Queue. If not remove the code above this comment. */
-+
-+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.b.xfersize =
-+ (ep->total_len - ep->xfer_count) >
-+ ep->maxpacket ? ep->maxpacket : (ep->total_len -
-+ ep->xfer_count);
-+ deptsiz.b.pktcnt = 1;
-+ if (core_if->dma_enable == 0) {
-+ ep->xfer_len += deptsiz.b.xfersize;
-+ } else {
-+ ep->xfer_len = deptsiz.b.xfersize;
-+ }
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ } else {
-+ ep->xfer_len =
-+ (ep->total_len - ep->xfer_count) >
-+ ep->maxpacket ? ep->maxpacket : (ep->total_len -
-+ ep->xfer_count);
-+
-+ dma_desc = core_if->dev_if->in_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.sp =
-+ (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+ dma_desc->status.b.bytes = ep->xfer_len;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DIEPDMA0 Register write */
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ core_if->dev_if->dma_in_desc_addr);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+ if (core_if->dma_desc_enable == 0)
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+ * data will be written into the fifo by the ISR.
-+ */
-+ if (!core_if->dma_enable) {
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ /* First clear it from GINTSTS */
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk |= 1 << ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+ } else {
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[0];
-+
-+ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
-+
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+ if (core_if->dma_desc_enable == 0) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ } else {
-+ dma_desc = core_if->dev_if->out_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = ep->maxpacket;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ core_if->dev_if->dma_out_desc_addr);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+ if (core_if->dma_desc_enable == 0)
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+ }
-+}
-+
-+#ifdef DEBUG
-+void dump_msg(const u8 * buf, unsigned int length)
-+{
-+ unsigned int start, num, i;
-+ char line[52], *p;
-+
-+ if (length >= 512)
-+ return;
-+ start = 0;
-+ while (length > 0) {
-+ num = length < 16u ? length : 16u;
-+ p = line;
-+ for (i = 0; i < num; ++i) {
-+ if (i == 8)
-+ *p++ = ' ';
-+ DWC_SPRINTF(p, " %02x", buf[i]);
-+ p += 3;
-+ }
-+ *p = 0;
-+ DWC_PRINTF("%6x: %s\n", start, line);
-+ buf += num;
-+ start += num;
-+ length -= num;
-+ }
-+}
-+#else
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function writes a packet into the Tx FIFO associated with the
-+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
-+ * periodic EPs the periodic Tx FIFO associated with the EP is written
-+ * with all packets for the next micro-frame.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to write packet for.
-+ * @param dma Indicates if DMA is being used.
-+ */
-+void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
-+ int dma)
-+{
-+ /**
-+ * The buffer is padded to DWORD on a per packet basis in
-+ * slave/dma mode if the MPS is not DWORD aligned. The last
-+ * packet, if short, is also padded to a multiple of DWORD.
-+ *
-+ * ep->xfer_buff always starts DWORD aligned in memory and is a
-+ * multiple of DWORD in length
-+ *
-+ * ep->xfer_len can be any number of bytes
-+ *
-+ * ep->xfer_count is a multiple of ep->maxpacket until the last
-+ * packet
-+ *
-+ * FIFO access is DWORD */
-+
-+ uint32_t i;
-+ uint32_t byte_count;
-+ uint32_t dword_count;
-+ uint32_t *fifo;
-+ uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
-+ ep);
-+ if (ep->xfer_count >= ep->xfer_len) {
-+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
-+ return;
-+ }
-+
-+ /* Find the byte length of the packet either short packet or MPS */
-+ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
-+ byte_count = ep->xfer_len - ep->xfer_count;
-+ } else {
-+ byte_count = ep->maxpacket;
-+ }
-+
-+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS
-+ * is not a multiple of DWORD */
-+ dword_count = (byte_count + 3) / 4;
-+
-+#ifdef VERBOSE
-+ dump_msg(ep->xfer_buff, byte_count);
-+#endif
-+
-+ /**@todo NGS Where are the Periodic Tx FIFO addresses
-+ * intialized? What should this be? */
-+
-+ fifo = core_if->data_fifo[ep->num];
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
-+ fifo, data_buff, *data_buff, byte_count);
-+
-+ if (!dma) {
-+ for (i = 0; i < dword_count; i++, data_buff++) {
-+ DWC_WRITE_REG32(fifo, *data_buff);
-+ }
-+ }
-+
-+ ep->xfer_count += byte_count;
-+ ep->xfer_buff += byte_count;
-+ ep->dma_addr += byte_count;
-+}
-+
-+/**
-+ * Set the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to set the stall on.
-+ */
-+void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ volatile uint32_t *depctl_addr;
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in ? "IN" : "OUT"));
-+
-+ if (ep->is_in == 1) {
-+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+ depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+ /* set the disable and stall bits */
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ }
-+ depctl.b.stall = 1;
-+ DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+ } else {
-+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+ depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+ /* set the stall bit */
-+ depctl.b.stall = 1;
-+ DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
-+
-+ return;
-+}
-+
-+/**
-+ * Clear the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to clear stall from.
-+ */
-+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ volatile uint32_t *depctl_addr;
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in ? "IN" : "OUT"));
-+
-+ if (ep->is_in == 1) {
-+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+ } else {
-+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+ /* clear the stall bits */
-+ depctl.b.stall = 0;
-+
-+ /*
-+ * USB Spec 9.4.5: For endpoints using data toggle, regardless
-+ * of whether an endpoint has the Halt feature set, a
-+ * ClearFeature(ENDPOINT_HALT) request always results in the
-+ * data toggle being reinitialized to DATA0.
-+ */
-+ if (ep->type == DWC_OTG_EP_TYPE_INTR ||
-+ ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ depctl.b.setd0pid = 1; /* DATA0 */
-+ }
-+
-+ DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
-+ return;
-+}
-+
-+/**
-+ * This function reads a packet from the Rx FIFO into the destination
-+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for the packet.
-+ * @param bytes Number of bytes to copy to the destination.
-+ */
-+void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
-+ uint8_t * dest, uint16_t bytes)
-+{
-+ int i;
-+ int word_count = (bytes + 3) / 4;
-+
-+ volatile uint32_t *fifo = core_if->data_fifo[0];
-+ uint32_t *data_buff = (uint32_t *) dest;
-+
-+ /**
-+ * @todo Account for the case where _dest is not dword aligned. This
-+ * requires reading data from the FIFO into a uint32_t temp buffer,
-+ * then moving it into the data buffer.
-+ */
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
-+ core_if, dest, bytes);
-+
-+ for (i = 0; i < word_count; i++, data_buff++) {
-+ *data_buff = DWC_READ_REG32(fifo);
-+ }
-+
-+ return;
-+}
-+
-+/**
-+ * This functions reads the device registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINTF("Device Global Registers\n");
-+ addr = &core_if->dev_if->dev_global_regs->dcfg;
-+ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->dctl;
-+ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->dsts;
-+ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->diepmsk;
-+ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->doepmsk;
-+ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->daint;
-+ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->daintmsk;
-+ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr1;
-+ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr2;
-+ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ addr = &core_if->dev_if->dev_global_regs->dvbusdis;
-+ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
-+ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
-+ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ if (core_if->hwcfg2.b.multi_proc_int) {
-+
-+ addr = &core_if->dev_if->dev_global_regs->deachint;
-+ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->deachintmsk;
-+ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ addr =
-+ &core_if->dev_if->
-+ dev_global_regs->diepeachintmsk[i];
-+ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
-+ i, (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ }
-+
-+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+ addr =
-+ &core_if->dev_if->
-+ dev_global_regs->doepeachintmsk[i];
-+ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
-+ i, (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ }
-+ }
-+
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_PRINTF("Device IN EP %d Registers\n", i);
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
-+ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepint;
-+ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
-+ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
-+ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
-+ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
-+ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
-+ }
-+
-+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+ DWC_PRINTF("Device OUT EP %d Registers\n", i);
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
-+ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepint;
-+ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
-+ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
-+ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
-+ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ }
-+}
-+
-+/**
-+ * This functions reads the SPRAM and prints its content
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
-+{
-+ volatile uint8_t *addr, *start_addr, *end_addr;
-+
-+ DWC_PRINTF("SPRAM Data:\n");
-+ start_addr = (void *)core_if->core_global_regs;
-+ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
-+ start_addr += 0x00028000;
-+ end_addr = (void *)core_if->core_global_regs;
-+ end_addr += 0x000280e0;
-+
-+ for (addr = start_addr; addr < end_addr; addr += 16) {
-+ DWC_PRINTF
-+ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
-+ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
-+ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
-+ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
-+ );
-+ }
-+
-+ return;
-+}
-+
-+/**
-+ * This function reads the host registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINTF("Host Global Registers\n");
-+ addr = &core_if->host_if->host_global_regs->hcfg;
-+ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->hfir;
-+ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->hfnum;
-+ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->hptxsts;
-+ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->haint;
-+ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->haintmsk;
-+ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ if (core_if->dma_desc_enable) {
-+ addr = &core_if->host_if->host_global_regs->hflbaddr;
-+ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ addr = core_if->host_if->hprt0;
-+ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ for (i = 0; i < core_if->core_params->host_channels; i++) {
-+ DWC_PRINTF("Host Channel %d Specific Registers\n", i);
-+ addr = &core_if->host_if->hc_regs[i]->hcchar;
-+ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcsplt;
-+ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcint;
-+ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcintmsk;
-+ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hctsiz;
-+ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcdma;
-+ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ if (core_if->dma_desc_enable) {
-+ addr = &core_if->host_if->hc_regs[i]->hcdmab;
-+ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ }
-+ return;
-+}
-+
-+/**
-+ * This function reads the core global registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
-+{
-+ int i, ep_num;
-+ volatile uint32_t *addr;
-+ char *txfsiz;
-+
-+ DWC_PRINTF("Core Global Registers\n");
-+ addr = &core_if->core_global_regs->gotgctl;
-+ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gotgint;
-+ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gahbcfg;
-+ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gusbcfg;
-+ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->grstctl;
-+ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gintsts;
-+ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gintmsk;
-+ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->grxstsr;
-+ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->grxfsiz;
-+ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gnptxfsiz;
-+ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gnptxsts;
-+ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gi2cctl;
-+ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gpvndctl;
-+ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ggpio;
-+ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->guid;
-+ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gsnpsid;
-+ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg1;
-+ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg2;
-+ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg3;
-+ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg4;
-+ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->glpmcfg;
-+ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gpwrdn;
-+ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gdfifocfg;
-+ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->adpctl;
-+ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ dwc_otg_adp_read_reg(core_if));
-+ addr = &core_if->core_global_regs->hptxfsiz;
-+ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
-+ txfsiz = "DPTXFSIZ";
-+ } else {
-+ ep_num = core_if->hwcfg4.b.num_in_eps;
-+ txfsiz = "DIENPTXF";
-+ }
-+ for (i = 0; i < ep_num; i++) {
-+ addr = &core_if->core_global_regs->dtxfsiz[i];
-+ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+ addr = core_if->pcgcctl;
-+ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+}
-+
-+/**
-+ * Flush a Tx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param num Tx FIFO to flush.
-+ */
-+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = {.d32 = 0 };
-+ int count = 0;
-+
-+ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
-+
-+ greset.b.txfflsh = 1;
-+ greset.b.txfnum = num;
-+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+
-+ do {
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
-+ __func__, greset.d32,
-+ DWC_READ_REG32(&global_regs->gnptxsts));
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (greset.b.txfflsh == 1);
-+
-+ /* Wait for 3 PHY Clocks */
-+ dwc_udelay(1);
-+}
-+
-+/**
-+ * Flush Rx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = {.d32 = 0 };
-+ int count = 0;
-+
-+ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
-+ /*
-+ *
-+ */
-+ greset.b.rxfflsh = 1;
-+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+
-+ do {
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (greset.b.rxfflsh == 1);
-+
-+ /* Wait for 3 PHY Clocks */
-+ dwc_udelay(1);
-+}
-+
-+/**
-+ * Do core a soft reset of the core. Be careful with this because it
-+ * resets all the internal state machines of the core.
-+ */
-+void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = {.d32 = 0 };
-+ int count = 0;
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
-+ /* Wait for AHB master IDLE state. */
-+ do {
-+ dwc_udelay(10);
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 100000) {
-+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ return;
-+ }
-+ }
-+ while (greset.b.ahbidle == 0);
-+
-+ /* Core Soft Reset */
-+ count = 0;
-+ greset.b.csftrst = 1;
-+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+ do {
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
-+ __func__, greset.d32);
-+ break;
-+ }
-+ dwc_udelay(1);
-+ }
-+ while (greset.b.csftrst == 1);
-+
-+ /* Wait for 3 PHY Clocks */
-+ dwc_mdelay(100);
-+}
-+
-+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
-+{
-+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
-+}
-+
-+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
-+{
-+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
-+}
-+
-+/**
-+ * Register HCD callbacks. The callbacks are used to start and stop
-+ * the HCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the HCD callback structure.
-+ * @param p pointer to be passed to callback function (usb_hcd*).
-+ */
-+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
-+ dwc_otg_cil_callbacks_t * cb, void *p)
-+{
-+ core_if->hcd_cb = cb;
-+ cb->p = p;
-+}
-+
-+/**
-+ * Register PCD callbacks. The callbacks are used to start and stop
-+ * the PCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the PCD callback structure.
-+ * @param p pointer to be passed to callback function (pcd*).
-+ */
-+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
-+ dwc_otg_cil_callbacks_t * cb, void *p)
-+{
-+ core_if->pcd_cb = cb;
-+ cb->p = p;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function writes isoc data per 1 (micro)frame into tx fifo
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0 };
-+ uint32_t len = 0;
-+ uint32_t dwords;
-+
-+ ep->xfer_len = ep->data_per_frame;
-+ ep->xfer_count = 0;
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[ep->num];
-+
-+ len = ep->xfer_len - ep->xfer_count;
-+
-+ if (len > ep->maxpacket) {
-+ len = ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, ep, 0);
-+
-+ len = ep->xfer_len - ep->xfer_count;
-+ if (len > ep->maxpacket) {
-+ len = ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
-+ txstatus.d32);
-+ }
-+}
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dsts_data_t dsts = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if (ep->is_in) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ ep->xfer_len = ep->data_per_frame;
-+ ep->xfer_count = 0;
-+ ep->xfer_buff = ep->cur_pkt_addr;
-+ ep->dma_addr = ep->cur_pkt_dma_addr;
-+
-+ if (ep->is_in) {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+ deptsiz.b.mc = deptsiz.b.pktcnt;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->in_ep_regs[ep->num]->
-+ diepdma), (uint32_t) ep->dma_addr);
-+ }
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
-+
-+ if (core_if->dma_enable) {
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->
-+ out_ep_regs[ep->num]->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ }
-+
-+ /** Enable endpoint, clear nak */
-+
-+ depctl.d32 = 0;
-+ if (ep->bInterval == 1) {
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ ep->next_frame = dsts.b.soffn + ep->bInterval;
-+
-+ if (ep->next_frame & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ } else {
-+ ep->next_frame += ep->bInterval;
-+
-+ if (ep->next_frame & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(addr, 0, depctl.d32);
-+ depctl.d32 = DWC_READ_REG32(addr);
-+
-+ if (ep->is_in && core_if->dma_enable == 0) {
-+ write_isoc_frame_data(core_if, ep);
-+ }
-+
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+static void dwc_otg_set_uninitialized(int32_t * p, int size)
-+{
-+ int i;
-+ for (i = 0; i < size; i++) {
-+ p[i] = -1;
-+ }
-+}
-+
-+static int dwc_otg_param_initialized(int32_t val)
-+{
-+ return val != -1;
-+}
-+
-+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
-+ if (!core_if->core_params) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
-+ sizeof(*core_if->core_params) /
-+ sizeof(int32_t));
-+ DWC_PRINTF("Setting default values for core params\n");
-+ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
-+ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
-+ dwc_otg_set_param_dma_desc_enable(core_if,
-+ dwc_param_dma_desc_enable_default);
-+ dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
-+ dwc_otg_set_param_dma_burst_size(core_if,
-+ dwc_param_dma_burst_size_default);
-+ dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
-+ dwc_param_host_support_fs_ls_low_power_default);
-+ dwc_otg_set_param_enable_dynamic_fifo(core_if,
-+ dwc_param_enable_dynamic_fifo_default);
-+ dwc_otg_set_param_data_fifo_size(core_if,
-+ dwc_param_data_fifo_size_default);
-+ dwc_otg_set_param_dev_rx_fifo_size(core_if,
-+ dwc_param_dev_rx_fifo_size_default);
-+ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
-+ dwc_param_dev_nperio_tx_fifo_size_default);
-+ dwc_otg_set_param_host_rx_fifo_size(core_if,
-+ dwc_param_host_rx_fifo_size_default);
-+ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
-+ dwc_param_host_nperio_tx_fifo_size_default);
-+ dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
-+ dwc_param_host_perio_tx_fifo_size_default);
-+ dwc_otg_set_param_max_transfer_size(core_if,
-+ dwc_param_max_transfer_size_default);
-+ dwc_otg_set_param_max_packet_count(core_if,
-+ dwc_param_max_packet_count_default);
-+ dwc_otg_set_param_host_channels(core_if,
-+ dwc_param_host_channels_default);
-+ dwc_otg_set_param_dev_endpoints(core_if,
-+ dwc_param_dev_endpoints_default);
-+ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
-+ dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
-+ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
-+ dwc_param_host_ls_low_power_phy_clk_default);
-+ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
-+ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
-+ dwc_param_phy_ulpi_ext_vbus_default);
-+ dwc_otg_set_param_phy_utmi_width(core_if,
-+ dwc_param_phy_utmi_width_default);
-+ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
-+ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
-+ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
-+ dwc_otg_set_param_en_multiple_tx_fifo(core_if,
-+ dwc_param_en_multiple_tx_fifo_default);
-+ for (i = 0; i < 15; i++) {
-+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
-+ dwc_param_dev_perio_tx_fifo_size_default,
-+ i);
-+ }
-+
-+ for (i = 0; i < 15; i++) {
-+ dwc_otg_set_param_dev_tx_fifo_size(core_if,
-+ dwc_param_dev_tx_fifo_size_default,
-+ i);
-+ }
-+ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
-+ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
-+ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
-+ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
-+ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
-+ dwc_otg_set_param_tx_thr_length(core_if,
-+ dwc_param_tx_thr_length_default);
-+ dwc_otg_set_param_rx_thr_length(core_if,
-+ dwc_param_rx_thr_length_default);
-+ dwc_otg_set_param_ahb_thr_ratio(core_if,
-+ dwc_param_ahb_thr_ratio_default);
-+ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
-+ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
-+ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
-+ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
-+ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
-+ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
-+ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
-+ DWC_PRINTF("Finished setting default values for core params\n");
-+
-+ return 0;
-+}
-+
-+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->dma_enable;
-+}
-+
-+/* Checks if the parameter is outside of its valid range of values */
-+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
-+ (((_param_) < (_low_)) || \
-+ ((_param_) > (_high_)))
-+
-+/* Parameter access functions */
-+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int valid;
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
-+ DWC_WARN("Wrong value for otg_cap parameter\n");
-+ DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ valid = 1;
-+ switch (val) {
-+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
-+ if (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ valid = 0;
-+ break;
-+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
-+ if ((core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ && (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+ && (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
-+ && (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
-+ valid = 0;
-+ }
-+ break;
-+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
-+ /* always valid */
-+ break;
-+ }
-+ if (!valid) {
-+ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
-+ DWC_ERROR
-+ ("%d invalid for otg_cap paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (((core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ || (core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+ || (core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
-+ || (core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
-+ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->otg_cap = val;
-+out:
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->otg_cap;
-+}
-+
-+int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for opt parameter\n");
-+ return -DWC_E_INVALID;
-+ }
-+ core_if->core_params->opt = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->opt;
-+}
-+
-+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for dma enable\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for dma_enable paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dma_enable = val;
-+ if (val == 0) {
-+ dwc_otg_set_param_dma_desc_enable(core_if, 0);
-+ }
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dma_enable;
-+}
-+
-+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for dma_enable\n");
-+ DWC_WARN("dma_desc_enable must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1)
-+ && ((dwc_otg_get_param_dma_enable(core_if) == 0)
-+ || (core_if->hwcfg4.b.desc_dma == 0))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dma_desc_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+ core_if->core_params->dma_desc_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dma_desc_enable;
-+}
-+
-+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for host_support_fs_low_power\n");
-+ DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+ core_if->core_params->host_support_fs_ls_low_power = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
-+ core_if)
-+{
-+ return core_if->core_params->host_support_fs_ls_low_power;
-+}
-+
-+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for enable_dynamic_fifo\n");
-+ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->enable_dynamic_fifo)) {
-+ DWC_ERROR
-+ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+ core_if->core_params->enable_dynamic_fifo = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->enable_dynamic_fifo;
-+}
-+
-+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
-+ DWC_WARN("Wrong value for data_fifo_size\n");
-+ DWC_WARN("data_fifo_size must be 32-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > core_if->hwcfg3.b.dfifo_depth) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->data_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = core_if->hwcfg3.b.dfifo_depth;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->data_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->data_fifo_size;
-+}
-+
-+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for dev_rx_fifo_size\n");
-+ DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
-+ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
-+ }
-+ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_rx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_rx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
-+ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_nperio_tx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
-+ 16);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_nperio_tx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_nperio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for host_rx_fifo_size\n");
-+ DWC_WARN("host_rx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_rx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_rx_fifo_size = val;
-+ return retval;
-+
-+}
-+
-+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_rx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
-+ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_nperio_tx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
-+ 16);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_nperio_tx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_nperio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
-+ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > ((core_if->hptxfsiz.d32) >> 16)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_perio_tx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val = (core_if->hptxfsiz.d32) >> 16;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_perio_tx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_perio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
-+ DWC_WARN("Wrong value for max_transfer_size\n");
-+ DWC_WARN("max_transfer_size must be 2047-524288\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->max_transfer_size)) {
-+ DWC_ERROR
-+ ("%d invalid for max_transfer_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
-+ 1);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->max_transfer_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->max_transfer_size;
-+}
-+
-+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
-+ DWC_WARN("Wrong value for max_packet_count\n");
-+ DWC_WARN("max_packet_count must be 15-511\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->max_packet_count)) {
-+ DWC_ERROR
-+ ("%d invalid for max_packet_count. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->max_packet_count = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->max_packet_count;
-+}
-+
-+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
-+ DWC_WARN("Wrong value for host_channels\n");
-+ DWC_WARN("host_channels must be 1-16\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_channels)) {
-+ DWC_ERROR
-+ ("%d invalid for host_channels. Check HW configurations.\n",
-+ val);
-+ }
-+ val = (core_if->hwcfg2.b.num_host_chan + 1);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_channels = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_channels;
-+}
-+
-+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
-+ DWC_WARN("Wrong value for dev_endpoints\n");
-+ DWC_WARN("dev_endpoints must be 1-15\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (core_if->hwcfg2.b.num_dev_ep)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_endpoints)) {
-+ DWC_ERROR
-+ ("%d invalid for dev_endpoints. Check HW configurations.\n",
-+ val);
-+ }
-+ val = core_if->hwcfg2.b.num_dev_ep;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_endpoints = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_endpoints;
-+}
-+
-+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
-+ DWC_WARN("Wrong value for phy_type\n");
-+ DWC_WARN("phy_type must be 0,1 or 2\n");
-+ return -DWC_E_INVALID;
-+ }
-+#ifndef NO_FS_PHY_HW_CHECKS
-+ if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
-+ ((core_if->hwcfg2.b.hs_phy_type == 1) ||
-+ (core_if->hwcfg2.b.hs_phy_type == 3))) {
-+ valid = 1;
-+ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
-+ ((core_if->hwcfg2.b.hs_phy_type == 2) ||
-+ (core_if->hwcfg2.b.hs_phy_type == 3))) {
-+ valid = 1;
-+ } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1)) {
-+ valid = 1;
-+ }
-+ if (!valid) {
-+ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
-+ DWC_ERROR
-+ ("%d invalid for phy_type. Check HW configurations.\n",
-+ val);
-+ }
-+ if (core_if->hwcfg2.b.hs_phy_type) {
-+ if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
-+ (core_if->hwcfg2.b.hs_phy_type == 1)) {
-+ val = DWC_PHY_TYPE_PARAM_UTMI;
-+ } else {
-+ val = DWC_PHY_TYPE_PARAM_ULPI;
-+ }
-+ }
-+ retval = -DWC_E_INVALID;
-+ }
-+#endif
-+ core_if->core_params->phy_type = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_type;
-+}
-+
-+int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for speed parameter\n");
-+ DWC_WARN("max_speed parameter must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+ if ((val == 0)
-+ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
-+ if (dwc_otg_param_initialized(core_if->core_params->speed)) {
-+ DWC_ERROR
-+ ("%d invalid for speed paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (dwc_otg_get_param_phy_type(core_if) ==
-+ DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
-+ retval = -DWC_E_INVALID;
-+ }
-+ core_if->core_params->speed = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->speed;
-+}
-+
-+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN
-+ ("Wrong value for host_ls_low_power_phy_clk parameter\n");
-+ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
-+ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_ls_low_power_phy_clk)) {
-+ DWC_ERROR
-+ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (dwc_otg_get_param_phy_type(core_if) ==
-+ DWC_PHY_TYPE_PARAM_FS) ?
-+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
-+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_ls_low_power_phy_clk = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_ls_low_power_phy_clk;
-+}
-+
-+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for phy_ulpi_ddr\n");
-+ DWC_WARN("phy_upli_ddr must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->phy_ulpi_ddr = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_ulpi_ddr;
-+}
-+
-+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
-+ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->phy_ulpi_ext_vbus = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_ulpi_ext_vbus;
-+}
-+
-+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
-+ DWC_WARN("Wrong valaue for phy_utmi_width\n");
-+ DWC_WARN("phy_utmi_width must be 8 or 16\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->phy_utmi_width = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_utmi_width;
-+}
-+
-+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
-+ DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->ulpi_fs_ls = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ulpi_fs_ls;
-+}
-+
-+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for ts_dline\n");
-+ DWC_WARN("ts_dline must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->ts_dline = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ts_dline;
-+}
-+
-+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for i2c_enable\n");
-+ DWC_WARN("i2c_enable must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+#ifndef NO_FS_PHY_HW_CHECK
-+ if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for i2c_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+#endif
-+
-+ core_if->core_params->i2c_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->i2c_enable;
-+}
-+
-+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val, int fifo_num)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
-+ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
-+ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val >
-+ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
-+ DWC_ERROR
-+ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
-+ val, fifo_num);
-+ }
-+ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num)
-+{
-+ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
-+}
-+
-+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
-+ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->en_multiple_tx_fifo)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->en_multiple_tx_fifo = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->en_multiple_tx_fifo;
-+}
-+
-+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
-+ int fifo_num)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
-+ DWC_WARN("Wrong value for dev_tx_fifo_size\n");
-+ DWC_WARN("dev_tx_fifo_size must be 4-768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val >
-+ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
-+ DWC_ERROR
-+ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
-+ val, fifo_num);
-+ }
-+ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num)
-+{
-+ return core_if->core_params->dev_tx_fifo_size[fifo_num];
-+}
-+
-+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
-+ DWC_WARN("Wrong value for thr_ctl\n");
-+ DWC_WARN("thr_ctl must be 0-7\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val != 0) &&
-+ (!dwc_otg_get_param_dma_enable(core_if) ||
-+ !core_if->hwcfg4.b.ded_fifo_en)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->thr_ctl = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->thr_ctl;
-+}
-+
-+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for lpm_enable\n");
-+ DWC_WARN("lpm_enable must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val && !core_if->hwcfg3.b.otg_lpm_en) {
-+ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->lpm_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->lpm_enable;
-+}
-+
-+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
-+ DWC_WARN("Wrong valaue for tx_thr_length\n");
-+ DWC_WARN("tx_thr_length must be 8 - 128\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->tx_thr_length = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->tx_thr_length;
-+}
-+
-+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
-+ DWC_WARN("Wrong valaue for rx_thr_length\n");
-+ DWC_WARN("rx_thr_length must be 8 - 128\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->rx_thr_length = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->rx_thr_length;
-+}
-+
-+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
-+ DWC_OTG_PARAM_TEST(val, 4, 4) &&
-+ DWC_OTG_PARAM_TEST(val, 8, 8) &&
-+ DWC_OTG_PARAM_TEST(val, 16, 16) &&
-+ DWC_OTG_PARAM_TEST(val, 32, 32) &&
-+ DWC_OTG_PARAM_TEST(val, 64, 64) &&
-+ DWC_OTG_PARAM_TEST(val, 128, 128) &&
-+ DWC_OTG_PARAM_TEST(val, 256, 256)) {
-+ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ core_if->core_params->dma_burst_size = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dma_burst_size;
-+}
-+
-+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter pti_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->pti_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->pti_enable;
-+}
-+
-+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->mpi_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->mpi_enable;
-+}
-+
-+int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->adp_supp_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter adp_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->adp_supp_enable = val;
-+ /*Set OTG version 2.0 in case of enabling ADP*/
-+ if (val)
-+ dwc_otg_set_param_otg_ver(core_if, 1);
-+
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->adp_supp_enable;
-+}
-+
-+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
-+ DWC_WARN("ic_usb_cap must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->ic_usb_cap = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ic_usb_cap;
-+}
-+
-+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
-+ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
-+ DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val
-+ && (core_if->snpsid < OTG_CORE_REV_2_81a
-+ || !dwc_otg_get_param_thr_ctl(core_if))) {
-+ valid = 0;
-+ } else if (val
-+ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
-+ 4)) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->ahb_thr_ratio)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+
-+ core_if->core_params->ahb_thr_ratio = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ahb_thr_ratio;
-+}
-+
-+int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+ hwcfg4_data_t hwcfg4 = {.d32 = 0 };
-+ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
-+ DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
-+ DWC_WARN("power_down must be 0 - 2\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
-+ valid = 0;
-+ }
-+ if ((val == 3)
-+ && ((core_if->snpsid < OTG_CORE_REV_3_00a)
-+ || (hwcfg4.b.xhiber == 0))) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter power_down. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->power_down = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->power_down;
-+}
-+
-+int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
-+ DWC_WARN("reload_ctl must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
-+ DWC_ERROR("%d invalid for parameter reload_ctl."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->reload_ctl = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->reload_ctl;
-+}
-+
-+int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
-+ DWC_WARN("dev_out_nak must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
-+ !(core_if->core_params->dma_desc_enable))) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
-+ DWC_ERROR("%d invalid for parameter dev_out_nak."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->dev_out_nak = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_out_nak;
-+}
-+
-+int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
-+ DWC_WARN("cont_on_bna must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
-+ !(core_if->core_params->dma_desc_enable))) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
-+ DWC_ERROR("%d invalid for parameter cont_on_bna."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->cont_on_bna = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->cont_on_bna;
-+}
-+
-+int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
-+ DWC_WARN("ahb_single must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
-+ DWC_ERROR("%d invalid for parameter ahb_single."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->ahb_single = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ahb_single;
-+}
-+
-+int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
-+ DWC_WARN
-+ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->otg_ver = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->otg_ver;
-+}
-+
-+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
-+{
-+ gotgctl_data_t otgctl;
-+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ return otgctl.b.hstnegscs;
-+}
-+
-+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
-+{
-+ gotgctl_data_t otgctl;
-+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ return otgctl.b.sesreqscs;
-+}
-+
-+void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ if(core_if->otg_ver == 0) {
-+ gotgctl_data_t otgctl;
-+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ otgctl.b.hnpreq = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
-+ } else {
-+ core_if->otg_sts = val;
-+ }
-+}
-+
-+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->snpsid;
-+}
-+
-+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ return gintsts.b.curmode;
-+}
-+
-+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ return usbcfg.b.hnpcap;
-+}
-+
-+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ usbcfg.b.hnpcap = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ return usbcfg.b.srpcap;
-+}
-+
-+void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ usbcfg.b.srpcap = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
-+{
-+ dcfg_data_t dcfg;
-+ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
-+
-+ dcfg.d32 = -1; //GRAYG
-+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
-+ if (NULL == core_if)
-+ DWC_ERROR("reg request with NULL core_if\n");
-+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
-+ core_if, core_if->dev_if);
-+ if (NULL == core_if->dev_if)
-+ DWC_ERROR("reg request with NULL dev_if\n");
-+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
-+ "dev_global_regs(%p)\n", __func__,
-+ core_if, core_if->dev_if,
-+ core_if->dev_if->dev_global_regs);
-+ if (NULL == core_if->dev_if->dev_global_regs)
-+ DWC_ERROR("reg request with NULL dev_global_regs\n");
-+ else {
-+ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
-+ "dev_global_regs(%p)->dcfg = %p\n", __func__,
-+ core_if, core_if->dev_if,
-+ core_if->dev_if->dev_global_regs,
-+ &core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ }
-+ return dcfg.b.devspd;
-+}
-+
-+void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ dcfg_data_t dcfg;
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devspd = val;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ return hprt0.b.prtconnsts;
-+}
-+
-+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ return dsts.b.enumspd;
-+}
-+
-+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ return hprt0.b.prtpwr;
-+
-+}
-+
-+uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->hibernation_suspend;
-+}
-+
-+void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = val;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ return hprt0.b.prtsusp;
-+
-+}
-+
-+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = val;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
-+{
-+ hfir_data_t hfir;
-+ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+ return hfir.b.frint;
-+
-+}
-+
-+void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hfir_data_t hfir;
-+ uint32_t fram_int;
-+ fram_int = calc_frame_interval(core_if);
-+ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+ if (!core_if->core_params->reload_ctl) {
-+ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
-+ "not set to 1.\nShould load driver with reload_ctl=1"
-+ " module parameter\n");
-+ return;
-+ }
-+ switch (fram_int) {
-+ case 3750:
-+ if ((val < 3350) || (val > 4150)) {
-+ DWC_WARN("HFIR interval for HS core and 30 MHz"
-+ "clock freq should be from 3350 to 4150\n");
-+ return;
-+ }
-+ break;
-+ case 30000:
-+ if ((val < 26820) || (val > 33180)) {
-+ DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
-+ "clock freq should be from 26820 to 33180\n");
-+ return;
-+ }
-+ break;
-+ case 6000:
-+ if ((val < 5360) || (val > 6640)) {
-+ DWC_WARN("HFIR interval for HS core and 48 MHz"
-+ "clock freq should be from 5360 to 6640\n");
-+ return;
-+ }
-+ break;
-+ case 48000:
-+ if ((val < 42912) || (val > 53088)) {
-+ DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
-+ "clock freq should be from 42912 to 53088\n");
-+ return;
-+ }
-+ break;
-+ case 7500:
-+ if ((val < 6700) || (val > 8300)) {
-+ DWC_WARN("HFIR interval for HS core and 60 MHz"
-+ "clock freq should be from 6700 to 8300\n");
-+ return;
-+ }
-+ break;
-+ case 60000:
-+ if ((val < 53640) || (val > 65536)) {
-+ DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
-+ "clock freq should be from 53640 to 65536\n");
-+ return;
-+ }
-+ break;
-+ default:
-+ DWC_WARN("Unknown frame interval\n");
-+ return;
-+ break;
-+
-+ }
-+ hfir.b.frint = val;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
-+}
-+
-+uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
-+{
-+ hcfg_data_t hcfg;
-+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ return hcfg.b.modechtimen;
-+
-+}
-+
-+void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hcfg_data_t hcfg;
-+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ hcfg.b.modechtimen = val;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtres = val;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
-+{
-+ dctl_data_t dctl;
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ return dctl.b.rmtwkupsig;
-+}
-+
-+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+
-+ DWC_ASSERT(!
-+ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
-+ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
-+ core_if->lx_state, lpmcfg.b.prt_sleep_sts);
-+
-+ return lpmcfg.b.prt_sleep_sts;
-+}
-+
-+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.rem_wkup_en;
-+}
-+
-+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.appl_resp;
-+}
-+
-+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.appl_resp = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.hsic_connect;
-+}
-+
-+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.hsic_connect = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.inv_sel_hsic;
-+
-+}
-+
-+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.inv_sel_hsic = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+}
-+
-+void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
-+}
-+
-+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+}
-+
-+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
-+}
-+
-+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+}
-+
-+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
-+}
-+
-+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
-+}
-+
-+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
-+}
-+
-+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
-+}
-+
-+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
-+}
-+
-+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
-+}
-+
-+void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
-+}
-+
-+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(core_if->host_if->hprt0);
-+
-+}
-+
-+void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, val);
-+}
-+
-+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->guid);
-+}
-+
-+void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
-+}
-+
-+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+}
-+
-+uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
-+{
-+ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
-+}
-+
-+/**
-+ * Start the SRP timer to detect when the SRP does not complete within
-+ * 6 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->srp_timer_started = 1;
-+ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
-+}
-+
-+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
-+ gotgctl_data_t mem;
-+ gotgctl_data_t val;
-+
-+ val.d32 = DWC_READ_REG32(addr);
-+ if (val.b.sesreq) {
-+ DWC_ERROR("Session Request Already active!\n");
-+ return;
-+ }
-+
-+ DWC_INFO("Session Request Initated\n"); //NOTICE
-+ mem.d32 = DWC_READ_REG32(addr);
-+ mem.b.sesreq = 1;
-+ DWC_WRITE_REG32(addr, mem.d32);
-+
-+ /* Start the SRP timer */
-+ dwc_otg_pcd_start_srp_timer(core_if);
-+ return;
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cil.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cil.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,1464 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
-+ * $Revision: #123 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CIL_H__)
-+#define __DWC_CIL_H__
-+
-+#include "dwc_list.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_regs.h"
-+
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_adp.h"
-+
-+/**
-+ * @file
-+ * This file contains the interface to the Core Interface Layer.
-+ */
-+
-+#ifdef DWC_UTE_CFI
-+
-+#define MAX_DMA_DESCS_PER_EP 256
-+
-+/**
-+ * Enumeration for the data buffer mode
-+ */
-+typedef enum _data_buffer_mode {
-+ BM_STANDARD = 0, /* data buffer is in normal mode */
-+ BM_SG = 1, /* data buffer uses the scatter/gather mode */
-+ BM_CONCAT = 2, /* data buffer uses the concatenation mode */
-+ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
-+ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
-+} data_buffer_mode_e;
-+#endif //DWC_UTE_CFI
-+
-+/** Macros defined for DWC OTG HW Release version */
-+
-+#define OTG_CORE_REV_2_60a 0x4F54260A
-+#define OTG_CORE_REV_2_71a 0x4F54271A
-+#define OTG_CORE_REV_2_72a 0x4F54272A
-+#define OTG_CORE_REV_2_80a 0x4F54280A
-+#define OTG_CORE_REV_2_81a 0x4F54281A
-+#define OTG_CORE_REV_2_90a 0x4F54290A
-+#define OTG_CORE_REV_2_91a 0x4F54291A
-+#define OTG_CORE_REV_2_92a 0x4F54292A
-+#define OTG_CORE_REV_2_93a 0x4F54293A
-+#define OTG_CORE_REV_2_94a 0x4F54294A
-+#define OTG_CORE_REV_3_00a 0x4F54300A
-+
-+/**
-+ * Information for each ISOC packet.
-+ */
-+typedef struct iso_pkt_info {
-+ uint32_t offset;
-+ uint32_t length;
-+ int32_t status;
-+} iso_pkt_info_t;
-+
-+/**
-+ * The <code>dwc_ep</code> structure represents the state of a single
-+ * endpoint when acting in device mode. It contains the data items
-+ * needed for an endpoint to be activated and transfer packets.
-+ */
-+typedef struct dwc_ep {
-+ /** EP number used for register address lookup */
-+ uint8_t num;
-+ /** EP direction 0 = OUT */
-+ unsigned is_in:1;
-+ /** EP active. */
-+ unsigned active:1;
-+
-+ /**
-+ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
-+ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
-+ unsigned tx_fifo_num:4;
-+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
-+ unsigned type:2;
-+#define DWC_OTG_EP_TYPE_CONTROL 0
-+#define DWC_OTG_EP_TYPE_ISOC 1
-+#define DWC_OTG_EP_TYPE_BULK 2
-+#define DWC_OTG_EP_TYPE_INTR 3
-+
-+ /** DATA start PID for INTR and BULK EP */
-+ unsigned data_pid_start:1;
-+ /** Frame (even/odd) for ISOC EP */
-+ unsigned even_odd_frame:1;
-+ /** Max Packet bytes */
-+ unsigned maxpacket:11;
-+
-+ /** Max Transfer size */
-+ uint32_t maxxfer;
-+
-+ /** @name Transfer state */
-+ /** @{ */
-+
-+ /**
-+ * Pointer to the beginning of the transfer buffer -- do not modify
-+ * during transfer.
-+ */
-+
-+ dwc_dma_t dma_addr;
-+
-+ dwc_dma_t dma_desc_addr;
-+ dwc_otg_dev_dma_desc_t *desc_addr;
-+
-+ uint8_t *start_xfer_buff;
-+ /** pointer to the transfer buffer */
-+ uint8_t *xfer_buff;
-+ /** Number of bytes to transfer */
-+ unsigned xfer_len:19;
-+ /** Number of bytes transferred. */
-+ unsigned xfer_count:19;
-+ /** Sent ZLP */
-+ unsigned sent_zlp:1;
-+ /** Total len for control transfer */
-+ unsigned total_len:19;
-+
-+ /** stall clear flag */
-+ unsigned stall_clear_flag:1;
-+
-+ /** SETUP pkt cnt rollover flag for EP0 out*/
-+ unsigned stp_rollover;
-+
-+#ifdef DWC_UTE_CFI
-+ /* The buffer mode */
-+ data_buffer_mode_e buff_mode;
-+
-+ /* The chain of DMA descriptors.
-+ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
-+ */
-+ dwc_otg_dma_desc_t *descs;
-+
-+ /* The DMA address of the descriptors chain start */
-+ dma_addr_t descs_dma_addr;
-+ /** This variable stores the length of the last enqueued request */
-+ uint32_t cfi_req_len;
-+#endif //DWC_UTE_CFI
-+
-+/** Max DMA Descriptor count for any EP */
-+#define MAX_DMA_DESC_CNT 256
-+ /** Allocated DMA Desc count */
-+ uint32_t desc_cnt;
-+
-+ /** bInterval */
-+ uint32_t bInterval;
-+ /** Next frame num to setup next ISOC transfer */
-+ uint32_t frame_num;
-+ /** Indicates SOF number overrun in DSTS */
-+ uint8_t frm_overrun;
-+
-+#ifdef DWC_UTE_PER_IO
-+ /** Next frame num for which will be setup DMA Desc */
-+ uint32_t xiso_frame_num;
-+ /** bInterval */
-+ uint32_t xiso_bInterval;
-+ /** Count of currently active transfers - shall be either 0 or 1 */
-+ int xiso_active_xfers;
-+ int xiso_queued_xfers;
-+#endif
-+#ifdef DWC_EN_ISOC
-+ /**
-+ * Variables specific for ISOC EPs
-+ *
-+ */
-+ /** DMA addresses of ISOC buffers */
-+ dwc_dma_t dma_addr0;
-+ dwc_dma_t dma_addr1;
-+
-+ dwc_dma_t iso_dma_desc_addr;
-+ dwc_otg_dev_dma_desc_t *iso_desc_addr;
-+
-+ /** pointer to the transfer buffers */
-+ uint8_t *xfer_buff0;
-+ uint8_t *xfer_buff1;
-+
-+ /** number of ISOC Buffer is processing */
-+ uint32_t proc_buf_num;
-+ /** Interval of ISOC Buffer processing */
-+ uint32_t buf_proc_intrvl;
-+ /** Data size for regular frame */
-+ uint32_t data_per_frame;
-+
-+ /* todo - pattern data support is to be implemented in the future */
-+ /** Data size for pattern frame */
-+ uint32_t data_pattern_frame;
-+ /** Frame number of pattern data */
-+ uint32_t sync_frame;
-+
-+ /** bInterval */
-+ uint32_t bInterval;
-+ /** ISO Packet number per frame */
-+ uint32_t pkt_per_frm;
-+ /** Next frame num for which will be setup DMA Desc */
-+ uint32_t next_frame;
-+ /** Number of packets per buffer processing */
-+ uint32_t pkt_cnt;
-+ /** Info for all isoc packets */
-+ iso_pkt_info_t *pkt_info;
-+ /** current pkt number */
-+ uint32_t cur_pkt;
-+ /** current pkt number */
-+ uint8_t *cur_pkt_addr;
-+ /** current pkt number */
-+ uint32_t cur_pkt_dma_addr;
-+#endif /* DWC_EN_ISOC */
-+
-+/** @} */
-+} dwc_ep_t;
-+
-+/*
-+ * Reasons for halting a host channel.
-+ */
-+typedef enum dwc_otg_halt_status {
-+ DWC_OTG_HC_XFER_NO_HALT_STATUS,
-+ DWC_OTG_HC_XFER_COMPLETE,
-+ DWC_OTG_HC_XFER_URB_COMPLETE,
-+ DWC_OTG_HC_XFER_ACK,
-+ DWC_OTG_HC_XFER_NAK,
-+ DWC_OTG_HC_XFER_NYET,
-+ DWC_OTG_HC_XFER_STALL,
-+ DWC_OTG_HC_XFER_XACT_ERR,
-+ DWC_OTG_HC_XFER_FRAME_OVERRUN,
-+ DWC_OTG_HC_XFER_BABBLE_ERR,
-+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
-+ DWC_OTG_HC_XFER_AHB_ERR,
-+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE
-+} dwc_otg_halt_status_e;
-+
-+/**
-+ * Host channel descriptor. This structure represents the state of a single
-+ * host channel when acting in host mode. It contains the data items needed to
-+ * transfer packets to an endpoint via a host channel.
-+ */
-+typedef struct dwc_hc {
-+ /** Host channel number used for register address lookup */
-+ uint8_t hc_num;
-+
-+ /** Device to access */
-+ unsigned dev_addr:7;
-+
-+ /** EP to access */
-+ unsigned ep_num:4;
-+
-+ /** EP direction. 0: OUT, 1: IN */
-+ unsigned ep_is_in:1;
-+
-+ /**
-+ * EP speed.
-+ * One of the following values:
-+ * - DWC_OTG_EP_SPEED_LOW
-+ * - DWC_OTG_EP_SPEED_FULL
-+ * - DWC_OTG_EP_SPEED_HIGH
-+ */
-+ unsigned speed:2;
-+#define DWC_OTG_EP_SPEED_LOW 0
-+#define DWC_OTG_EP_SPEED_FULL 1
-+#define DWC_OTG_EP_SPEED_HIGH 2
-+
-+ /**
-+ * Endpoint type.
-+ * One of the following values:
-+ * - DWC_OTG_EP_TYPE_CONTROL: 0
-+ * - DWC_OTG_EP_TYPE_ISOC: 1
-+ * - DWC_OTG_EP_TYPE_BULK: 2
-+ * - DWC_OTG_EP_TYPE_INTR: 3
-+ */
-+ unsigned ep_type:2;
-+
-+ /** Max packet size in bytes */
-+ unsigned max_packet:11;
-+
-+ /**
-+ * PID for initial transaction.
-+ * 0: DATA0,<br>
-+ * 1: DATA2,<br>
-+ * 2: DATA1,<br>
-+ * 3: MDATA (non-Control EP),
-+ * SETUP (Control EP)
-+ */
-+ unsigned data_pid_start:2;
-+#define DWC_OTG_HC_PID_DATA0 0
-+#define DWC_OTG_HC_PID_DATA2 1
-+#define DWC_OTG_HC_PID_DATA1 2
-+#define DWC_OTG_HC_PID_MDATA 3
-+#define DWC_OTG_HC_PID_SETUP 3
-+
-+ /** Number of periodic transactions per (micro)frame */
-+ unsigned multi_count:2;
-+
-+ /** @name Transfer State */
-+ /** @{ */
-+
-+ /** Pointer to the current transfer buffer position. */
-+ uint8_t *xfer_buff;
-+ /**
-+ * In Buffer DMA mode this buffer will be used
-+ * if xfer_buff is not DWORD aligned.
-+ */
-+ dwc_dma_t align_buff;
-+ /** Total number of bytes to transfer. */
-+ uint32_t xfer_len;
-+ /** Number of bytes transferred so far. */
-+ uint32_t xfer_count;
-+ /** Packet count at start of transfer.*/
-+ uint16_t start_pkt_count;
-+
-+ /**
-+ * Flag to indicate whether the transfer has been started. Set to 1 if
-+ * it has been started, 0 otherwise.
-+ */
-+ uint8_t xfer_started;
-+
-+ /**
-+ * Set to 1 to indicate that a PING request should be issued on this
-+ * channel. If 0, process normally.
-+ */
-+ uint8_t do_ping;
-+
-+ /**
-+ * Set to 1 to indicate that the error count for this transaction is
-+ * non-zero. Set to 0 if the error count is 0.
-+ */
-+ uint8_t error_state;
-+
-+ /**
-+ * Set to 1 to indicate that this channel should be halted the next
-+ * time a request is queued for the channel. This is necessary in
-+ * slave mode if no request queue space is available when an attempt
-+ * is made to halt the channel.
-+ */
-+ uint8_t halt_on_queue;
-+
-+ /**
-+ * Set to 1 if the host channel has been halted, but the core is not
-+ * finished flushing queued requests. Otherwise 0.
-+ */
-+ uint8_t halt_pending;
-+
-+ /**
-+ * Reason for halting the host channel.
-+ */
-+ dwc_otg_halt_status_e halt_status;
-+
-+ /*
-+ * Split settings for the host channel
-+ */
-+ uint8_t do_split; /**< Enable split for the channel */
-+ uint8_t complete_split; /**< Enable complete split */
-+ uint8_t hub_addr; /**< Address of high speed hub */
-+
-+ uint8_t port_addr; /**< Port of the low/full speed device */
-+ /** Split transaction position
-+ * One of the following values:
-+ * - DWC_HCSPLIT_XACTPOS_MID
-+ * - DWC_HCSPLIT_XACTPOS_BEGIN
-+ * - DWC_HCSPLIT_XACTPOS_END
-+ * - DWC_HCSPLIT_XACTPOS_ALL */
-+ uint8_t xact_pos;
-+
-+ /** Set when the host channel does a short read. */
-+ uint8_t short_read;
-+
-+ /**
-+ * Number of requests issued for this channel since it was assigned to
-+ * the current transfer (not counting PINGs).
-+ */
-+ uint8_t requests;
-+
-+ /**
-+ * Queue Head for the transfer being processed by this channel.
-+ */
-+ struct dwc_otg_qh *qh;
-+
-+ /** @} */
-+
-+ /** Entry in list of host channels. */
-+ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
-+
-+ /** @name Descriptor DMA support */
-+ /** @{ */
-+
-+ /** Number of Transfer Descriptors */
-+ uint16_t ntd;
-+
-+ /** Descriptor List DMA address */
-+ dwc_dma_t desc_list_addr;
-+
-+ /** Scheduling micro-frame bitmap. */
-+ uint8_t schinfo;
-+
-+ /** @} */
-+} dwc_hc_t;
-+
-+/**
-+ * The following parameters may be specified when starting the module. These
-+ * parameters define how the DWC_otg controller should be configured.
-+ */
-+typedef struct dwc_otg_core_params {
-+ int32_t opt;
-+
-+ /**
-+ * Specifies the OTG capabilities. The driver will automatically
-+ * detect the value for this parameter if none is specified.
-+ * 0 - HNP and SRP capable (default)
-+ * 1 - SRP Only capable
-+ * 2 - No HNP/SRP capable
-+ */
-+ int32_t otg_cap;
-+
-+ /**
-+ * Specifies whether to use slave or DMA mode for accessing the data
-+ * FIFOs. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - Slave
-+ * 1 - DMA (default, if available)
-+ */
-+ int32_t dma_enable;
-+
-+ /**
-+ * When DMA mode is enabled specifies whether to use address DMA or DMA
-+ * Descriptor mode for accessing the data FIFOs in device mode. The driver
-+ * will automatically detect the value for this if none is specified.
-+ * 0 - address DMA
-+ * 1 - DMA Descriptor(default, if available)
-+ */
-+ int32_t dma_desc_enable;
-+ /** The DMA Burst size (applicable only for External DMA
-+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ */
-+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */
-+
-+ /**
-+ * Specifies the maximum speed of operation in host and device mode.
-+ * The actual speed depends on the speed of the attached device and
-+ * the value of phy_type. The actual speed depends on the speed of the
-+ * attached device.
-+ * 0 - High Speed (default)
-+ * 1 - Full Speed
-+ */
-+ int32_t speed;
-+ /** Specifies whether low power mode is supported when attached
-+ * to a Full Speed or Low Speed device in host mode.
-+ * 0 - Don't support low power mode (default)
-+ * 1 - Support low power mode
-+ */
-+ int32_t host_support_fs_ls_low_power;
-+
-+ /** Specifies the PHY clock rate in low power mode when connected to a
-+ * Low Speed device in host mode. This parameter is applicable only if
-+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+ * then defaults to 6 MHZ otherwise 48 MHZ.
-+ *
-+ * 0 - 48 MHz
-+ * 1 - 6 MHz
-+ */
-+ int32_t host_ls_low_power_phy_clk;
-+
-+ /**
-+ * 0 - Use cC FIFO size parameters
-+ * 1 - Allow dynamic FIFO sizing (default)
-+ */
-+ int32_t enable_dynamic_fifo;
-+
-+ /** Total number of 4-byte words in the data FIFO memory. This
-+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+ * Tx FIFOs.
-+ * 32 to 32768 (default 8192)
-+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ */
-+ int32_t data_fifo_size;
-+
-+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1064)
-+ */
-+ int32_t dev_rx_fifo_size;
-+
-+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+ * when dynamic FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t dev_nperio_tx_fifo_size;
-+
-+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+
-+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_rx_fifo_size;
-+
-+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+ * when Dynamic FIFO sizing is enabled in the core.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_nperio_tx_fifo_size;
-+
-+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_perio_tx_fifo_size;
-+
-+ /** The maximum transfer size supported in bytes.
-+ * 2047 to 65,535 (default 65,535)
-+ */
-+ int32_t max_transfer_size;
-+
-+ /** The maximum number of packets in a transfer.
-+ * 15 to 511 (default 511)
-+ */
-+ int32_t max_packet_count;
-+
-+ /** The number of host channel registers to use.
-+ * 1 to 16 (default 12)
-+ * Note: The FPGA configuration supports a maximum of 12 host channels.
-+ */
-+ int32_t host_channels;
-+
-+ /** The number of endpoints in addition to EP0 available for device
-+ * mode operations.
-+ * 1 to 15 (default 6 IN and OUT)
-+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+ * endpoints in addition to EP0.
-+ */
-+ int32_t dev_endpoints;
-+
-+ /**
-+ * Specifies the type of PHY interface to use. By default, the driver
-+ * will automatically detect the phy_type.
-+ *
-+ * 0 - Full Speed PHY
-+ * 1 - UTMI+ (default)
-+ * 2 - ULPI
-+ */
-+ int32_t phy_type;
-+
-+ /**
-+ * Specifies the UTMI+ Data Width. This parameter is
-+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+ * PHY_TYPE, this parameter indicates the data width between
-+ * the MAC and the ULPI Wrapper.) Also, this parameter is
-+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+ * to "8 and 16 bits", meaning that the core has been
-+ * configured to work at either data path width.
-+ *
-+ * 8 or 16 bits (default 16)
-+ */
-+ int32_t phy_utmi_width;
-+
-+ /**
-+ * Specifies whether the ULPI operates at double or single
-+ * data rate. This parameter is only applicable if PHY_TYPE is
-+ * ULPI.
-+ *
-+ * 0 - single data rate ULPI interface with 8 bit wide data
-+ * bus (default)
-+ * 1 - double data rate ULPI interface with 4 bit wide data
-+ * bus
-+ */
-+ int32_t phy_ulpi_ddr;
-+
-+ /**
-+ * Specifies whether to use the internal or external supply to
-+ * drive the vbus with a ULPI phy.
-+ */
-+ int32_t phy_ulpi_ext_vbus;
-+
-+ /**
-+ * Specifies whether to use the I2Cinterface for full speed PHY. This
-+ * parameter is only applicable if PHY_TYPE is FS.
-+ * 0 - No (default)
-+ * 1 - Yes
-+ */
-+ int32_t i2c_enable;
-+
-+ int32_t ulpi_fs_ls;
-+
-+ int32_t ts_dline;
-+
-+ /**
-+ * Specifies whether dedicated transmit FIFOs are
-+ * enabled for non periodic IN endpoints in device mode
-+ * 0 - No
-+ * 1 - Yes
-+ */
-+ int32_t en_multiple_tx_fifo;
-+
-+ /** Number of 4-byte words in each of the Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+
-+ /** Thresholding enable flag-
-+ * bit 0 - enable non-ISO Tx thresholding
-+ * bit 1 - enable ISO Tx thresholding
-+ * bit 2 - enable Rx thresholding
-+ */
-+ uint32_t thr_ctl;
-+
-+ /** Thresholding length for Tx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+ uint32_t tx_thr_length;
-+
-+ /** Thresholding length for Rx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+ uint32_t rx_thr_length;
-+
-+ /**
-+ * Specifies whether LPM (Link Power Management) support is enabled
-+ */
-+ int32_t lpm_enable;
-+
-+ /** Per Transfer Interrupt
-+ * mode enable flag
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t pti_enable;
-+
-+ /** Multi Processor Interrupt
-+ * mode enable flag
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t mpi_enable;
-+
-+ /** IS_USB Capability
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t ic_usb_cap;
-+
-+ /** AHB Threshold Ratio
-+ * 2'b00 AHB Threshold = MAC Threshold
-+ * 2'b01 AHB Threshold = 1/2 MAC Threshold
-+ * 2'b10 AHB Threshold = 1/4 MAC Threshold
-+ * 2'b11 AHB Threshold = 1/8 MAC Threshold
-+ */
-+ int32_t ahb_thr_ratio;
-+
-+ /** ADP Support
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t adp_supp_enable;
-+
-+ /** HFIR Reload Control
-+ * 0 - The HFIR cannot be reloaded dynamically.
-+ * 1 - Allow dynamic reloading of the HFIR register during runtime.
-+ */
-+ int32_t reload_ctl;
-+
-+ /** DCFG: Enable device Out NAK
-+ * 0 - The core does not set NAK after Bulk Out transfer complete.
-+ * 1 - The core sets NAK after Bulk OUT transfer complete.
-+ */
-+ int32_t dev_out_nak;
-+
-+ /** DCFG: Enable Continue on BNA
-+ * After receiving BNA interrupt the core disables the endpoint,when the
-+ * endpoint is re-enabled by the application the core starts processing
-+ * 0 - from the DOEPDMA descriptor
-+ * 1 - from the descriptor which received the BNA.
-+ */
-+ int32_t cont_on_bna;
-+
-+ /** GAHBCFG: AHB Single Support
-+ * This bit when programmed supports SINGLE transfers for remainder
-+ * data in a transfer for DMA mode of operation.
-+ * 0 - in this case the remainder data will be sent using INCR burst size.
-+ * 1 - in this case the remainder data will be sent using SINGLE burst size.
-+ */
-+ int32_t ahb_single;
-+
-+ /** Core Power down mode
-+ * 0 - No Power Down is enabled
-+ * 1 - Reserved
-+ * 2 - Complete Power Down (Hibernation)
-+ */
-+ int32_t power_down;
-+
-+ /** OTG revision supported
-+ * 0 - OTG 1.3 revision
-+ * 1 - OTG 2.0 revision
-+ */
-+ int32_t otg_ver;
-+
-+} dwc_otg_core_params_t;
-+
-+#ifdef DEBUG
-+struct dwc_otg_core_if;
-+typedef struct hc_xfer_info {
-+ struct dwc_otg_core_if *core_if;
-+ dwc_hc_t *hc;
-+} hc_xfer_info_t;
-+#endif
-+
-+typedef struct ep_xfer_info {
-+ struct dwc_otg_core_if *core_if;
-+ dwc_ep_t *ep;
-+ uint8_t state;
-+} ep_xfer_info_t;
-+/*
-+ * Device States
-+ */
-+typedef enum dwc_otg_lx_state {
-+ /** On state */
-+ DWC_OTG_L0,
-+ /** LPM sleep state*/
-+ DWC_OTG_L1,
-+ /** USB suspend state*/
-+ DWC_OTG_L2,
-+ /** Off state*/
-+ DWC_OTG_L3
-+} dwc_otg_lx_state_e;
-+
-+struct dwc_otg_global_regs_backup {
-+ uint32_t gotgctl_local;
-+ uint32_t gintmsk_local;
-+ uint32_t gahbcfg_local;
-+ uint32_t gusbcfg_local;
-+ uint32_t grxfsiz_local;
-+ uint32_t gnptxfsiz_local;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ uint32_t glpmcfg_local;
-+#endif
-+ uint32_t gi2cctl_local;
-+ uint32_t hptxfsiz_local;
-+ uint32_t pcgcctl_local;
-+ uint32_t gdfifocfg_local;
-+ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
-+ uint32_t gpwrdn_local;
-+ uint32_t xhib_pcgcctl;
-+ uint32_t xhib_gpwrdn;
-+};
-+
-+struct dwc_otg_host_regs_backup {
-+ uint32_t hcfg_local;
-+ uint32_t haintmsk_local;
-+ uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
-+ uint32_t hprt0_local;
-+ uint32_t hfir_local;
-+};
-+
-+struct dwc_otg_dev_regs_backup {
-+ uint32_t dcfg;
-+ uint32_t dctl;
-+ uint32_t daintmsk;
-+ uint32_t diepmsk;
-+ uint32_t doepmsk;
-+ uint32_t diepctl[MAX_EPS_CHANNELS];
-+ uint32_t dieptsiz[MAX_EPS_CHANNELS];
-+ uint32_t diepdma[MAX_EPS_CHANNELS];
-+};
-+/**
-+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
-+ * the DWC_otg controller acting in either host or device mode. It
-+ * represents the programming view of the controller as a whole.
-+ */
-+struct dwc_otg_core_if {
-+ /** Parameters that define how the core should be configured.*/
-+ dwc_otg_core_params_t *core_params;
-+
-+ /** Core Global registers starting at offset 000h. */
-+ dwc_otg_core_global_regs_t *core_global_regs;
-+
-+ /** Device-specific information */
-+ dwc_otg_dev_if_t *dev_if;
-+ /** Host-specific information */
-+ dwc_otg_host_if_t *host_if;
-+
-+ /** Value from SNPSID register */
-+ uint32_t snpsid;
-+
-+ /*
-+ * Set to 1 if the core PHY interface bits in USBCFG have been
-+ * initialized.
-+ */
-+ uint8_t phy_init_done;
-+
-+ /*
-+ * SRP Success flag, set by srp success interrupt in FS I2C mode
-+ */
-+ uint8_t srp_success;
-+ uint8_t srp_timer_started;
-+ /** Timer for SRP. If it expires before SRP is successful
-+ * clear the SRP. */
-+ dwc_timer_t *srp_timer;
-+
-+#ifdef DWC_DEV_SRPCAP
-+ /* This timer is needed to power on the hibernated host core if SRP is not
-+ * initiated on connected SRP capable device for limited period of time
-+ */
-+ uint8_t pwron_timer_started;
-+ dwc_timer_t *pwron_timer;
-+#endif
-+ /* Common configuration information */
-+ /** Power and Clock Gating Control Register */
-+ volatile uint32_t *pcgcctl;
-+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
-+
-+ /** Push/pop addresses for endpoints or host channels.*/
-+ uint32_t *data_fifo[MAX_EPS_CHANNELS];
-+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
-+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
-+
-+ /** Total RAM for FIFOs (Bytes) */
-+ uint16_t total_fifo_size;
-+ /** Size of Rx FIFO (Bytes) */
-+ uint16_t rx_fifo_size;
-+ /** Size of Non-periodic Tx FIFO (Bytes) */
-+ uint16_t nperio_tx_fifo_size;
-+
-+ /** 1 if DMA is enabled, 0 otherwise. */
-+ uint8_t dma_enable;
-+
-+ /** 1 if DMA descriptor is enabled, 0 otherwise. */
-+ uint8_t dma_desc_enable;
-+
-+ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
-+ uint8_t pti_enh_enable;
-+
-+ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
-+ uint8_t multiproc_int_enable;
-+
-+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
-+ uint8_t en_multiple_tx_fifo;
-+
-+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in
-+ * process of being queued */
-+ uint8_t queuing_high_bandwidth;
-+
-+ /** Hardware Configuration -- stored here for convenience.*/
-+ hwcfg1_data_t hwcfg1;
-+ hwcfg2_data_t hwcfg2;
-+ hwcfg3_data_t hwcfg3;
-+ hwcfg4_data_t hwcfg4;
-+ fifosize_data_t hptxfsiz;
-+
-+ /** Host and Device Configuration -- stored here for convenience.*/
-+ hcfg_data_t hcfg;
-+ dcfg_data_t dcfg;
-+
-+ /** The operational State, during transations
-+ * (a_host>>a_peripherial and b_device=>b_host) this may not
-+ * match the core but allows the software to determine
-+ * transitions.
-+ */
-+ uint8_t op_state;
-+
-+ /**
-+ * Set to 1 if the HCD needs to be restarted on a session request
-+ * interrupt. This is required if no connector ID status change has
-+ * occurred since the HCD was last disconnected.
-+ */
-+ uint8_t restart_hcd_on_session_req;
-+
-+ /** HCD callbacks */
-+ /** A-Device is a_host */
-+#define A_HOST (1)
-+ /** A-Device is a_suspend */
-+#define A_SUSPEND (2)
-+ /** A-Device is a_peripherial */
-+#define A_PERIPHERAL (3)
-+ /** B-Device is operating as a Peripheral. */
-+#define B_PERIPHERAL (4)
-+ /** B-Device is operating as a Host. */
-+#define B_HOST (5)
-+
-+ /** HCD callbacks */
-+ struct dwc_otg_cil_callbacks *hcd_cb;
-+ /** PCD callbacks */
-+ struct dwc_otg_cil_callbacks *pcd_cb;
-+
-+ /** Device mode Periodic Tx FIFO Mask */
-+ uint32_t p_tx_msk;
-+ /** Device mode Periodic Tx FIFO Mask */
-+ uint32_t tx_msk;
-+
-+ /** Workqueue object used for handling several interrupts */
-+ dwc_workq_t *wq_otg;
-+
-+ /** Timer object used for handling "Wakeup Detected" Interrupt */
-+ dwc_timer_t *wkp_timer;
-+ /** This arrays used for debug purposes for DEV OUT NAK enhancement */
-+ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
-+ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
-+ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
-+#ifdef DEBUG
-+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
-+
-+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
-+ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
-+
-+ uint32_t hfnum_7_samples;
-+ uint64_t hfnum_7_frrem_accum;
-+ uint32_t hfnum_0_samples;
-+ uint64_t hfnum_0_frrem_accum;
-+ uint32_t hfnum_other_samples;
-+ uint64_t hfnum_other_frrem_accum;
-+#endif
-+
-+#ifdef DWC_UTE_CFI
-+ uint16_t pwron_rxfsiz;
-+ uint16_t pwron_gnptxfsiz;
-+ uint16_t pwron_txfsiz[15];
-+
-+ uint16_t init_rxfsiz;
-+ uint16_t init_gnptxfsiz;
-+ uint16_t init_txfsiz[15];
-+#endif
-+
-+ /** Lx state of device */
-+ dwc_otg_lx_state_e lx_state;
-+
-+ /** Saved Core Global registers */
-+ struct dwc_otg_global_regs_backup *gr_backup;
-+ /** Saved Host registers */
-+ struct dwc_otg_host_regs_backup *hr_backup;
-+ /** Saved Device registers */
-+ struct dwc_otg_dev_regs_backup *dr_backup;
-+
-+ /** Power Down Enable */
-+ uint32_t power_down;
-+
-+ /** ADP support Enable */
-+ uint32_t adp_enable;
-+
-+ /** ADP structure object */
-+ dwc_otg_adp_t adp;
-+
-+ /** hibernation/suspend flag */
-+ int hibernation_suspend;
-+
-+ /** Device mode extended hibernation flag */
-+ int xhib;
-+
-+ /** OTG revision supported */
-+ uint32_t otg_ver;
-+
-+ /** OTG status flag used for HNP polling */
-+ uint8_t otg_sts;
-+
-+ /** Pointer to either hcd->lock or pcd->lock */
-+ dwc_spinlock_t *lock;
-+
-+ /** Start predict NextEP based on Learning Queue if equal 1,
-+ * also used as counter of disabled NP IN EP's */
-+ uint8_t start_predict;
-+
-+ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
-+ * active, 0xff otherwise */
-+ uint8_t nextep_seq[MAX_EPS_CHANNELS];
-+
-+ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
-+ uint8_t first_in_nextep_seq;
-+
-+ /** Frame number while entering to ISR - needed for ISOCs **/
-+ uint32_t frame_num;
-+
-+};
-+
-+#ifdef DEBUG
-+/*
-+ * This function is called when transfer is timed out.
-+ */
-+extern void hc_xfer_timeout(void *ptr);
-+#endif
-+
-+/*
-+ * This function is called when transfer is timed out on endpoint.
-+ */
-+extern void ep_xfer_timeout(void *ptr);
-+
-+/*
-+ * The following functions are functions for works
-+ * using during handling some interrupts
-+ */
-+extern void w_conn_id_status_change(void *p);
-+
-+extern void w_wakeup_detected(void *p);
-+
-+/** Saves global register values into system memory. */
-+extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
-+/** Saves device register values into system memory. */
-+extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
-+/** Saves host register values into system memory. */
-+extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
-+/** Restore global register values. */
-+extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
-+/** Restore host register values. */
-+extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
-+/** Restore device register values. */
-+extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup);
-+extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
-+extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
-+ int is_host);
-+
-+extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int restore_mode, int reset);
-+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset);
-+
-+/*
-+ * The following functions support initialization of the CIL driver component
-+ * and the DWC_otg controller.
-+ */
-+extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
-+
-+/** @name Device CIL Functions
-+ * The following functions support managing the DWC_otg controller in device
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
-+ uint32_t * _dest);
-+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep, int _dma);
-+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+#ifdef DWC_EN_ISOC
-+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep);
-+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep);
-+#endif /* DWC_EN_ISOC */
-+/**@}*/
-+
-+/** @name Host CIL Functions
-+ * The following functions support managing the DWC_otg controller in host
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
-+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc);
-+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc);
-+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc);
-+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
-+ dwc_hc_t * hc);
-+
-+extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
-+
-+/* Macro used to clear one channel interrupt */
-+#define clear_hc_int(_hc_regs_, _intr_) \
-+do { \
-+ hcint_data_t hcint_clear = {.d32 = 0}; \
-+ hcint_clear.b._intr_ = 1; \
-+ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
-+} while (0)
-+
-+/*
-+ * Macro used to disable one channel interrupt. Channel interrupts are
-+ * disabled when the channel is halted or released by the interrupt handler.
-+ * There is no need to handle further interrupts of that type until the
-+ * channel is re-assigned. In fact, subsequent handling may cause crashes
-+ * because the channel structures are cleaned up when the channel is released.
-+ */
-+#define disable_hc_int(_hc_regs_, _intr_) \
-+do { \
-+ hcintmsk_data_t hcintmsk = {.d32 = 0}; \
-+ hcintmsk.b._intr_ = 1; \
-+ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
-+} while (0)
-+
-+/**
-+ * This function Reads HPRT0 in preparation to modify. It keeps the
-+ * WC bits 0 so that if they are read as 1, they won't clear when you
-+ * write it back
-+ */
-+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtconndet = 0;
-+ hprt0.b.prtenchng = 0;
-+ hprt0.b.prtovrcurrchng = 0;
-+ return hprt0.d32;
-+}
-+
-+/**@}*/
-+
-+/** @name Common CIL Functions
-+ * The following functions support managing the DWC_otg controller in either
-+ * device or host mode.
-+ */
-+/**@{*/
-+
-+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
-+ uint8_t * dest, uint16_t bytes);
-+
-+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
-+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
-+{
-+ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
-+ DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function returns the OTG Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
-+{
-+ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the IN endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
-+ core_if)
-+{
-+
-+ uint32_t v;
-+
-+ if (core_if->multiproc_int_enable) {
-+ v = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->deachint) &
-+ DWC_READ_REG32(&core_if->
-+ dev_if->dev_global_regs->deachintmsk);
-+ } else {
-+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ }
-+ return (v & 0xffff);
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the OUT endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
-+ core_if)
-+{
-+ uint32_t v;
-+
-+ if (core_if->multiproc_int_enable) {
-+ v = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->deachint) &
-+ DWC_READ_REG32(&core_if->
-+ dev_if->dev_global_regs->deachintmsk);
-+ } else {
-+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ }
-+
-+ return ((v & 0xffff0000) >> 16);
-+}
-+
-+/**
-+ * This function returns the Device IN EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ uint32_t v, msk, emp;
-+
-+ if (core_if->multiproc_int_enable) {
-+ msk =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->diepeachintmsk[ep->num]);
-+ emp =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->dtknqr4_fifoemptymsk);
-+ msk |= ((emp >> ep->num) & 0x1) << 7;
-+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+ } else {
-+ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
-+ emp =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->dtknqr4_fifoemptymsk);
-+ msk |= ((emp >> ep->num) & 0x1) << 7;
-+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+ }
-+
-+ return v;
-+}
-+
-+/**
-+ * This function returns the Device OUT EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
-+ _core_if, dwc_ep_t * _ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
-+ uint32_t v;
-+ doepmsk_data_t msk = {.d32 = 0 };
-+
-+ if (_core_if->multiproc_int_enable) {
-+ msk.d32 =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->doepeachintmsk[_ep->num]);
-+ if (_core_if->pti_enh_enable) {
-+ msk.b.pktdrpsts = 1;
-+ }
-+ v = DWC_READ_REG32(&dev_if->
-+ out_ep_regs[_ep->num]->doepint) & msk.d32;
-+ } else {
-+ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
-+ if (_core_if->pti_enh_enable) {
-+ msk.b.pktdrpsts = 1;
-+ }
-+ v = DWC_READ_REG32(&dev_if->
-+ out_ep_regs[_ep->num]->doepint) & msk.d32;
-+ }
-+ return v;
-+}
-+
-+/**
-+ * This function returns the Host All Channel Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
-+ _core_if)
-+{
-+ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
-+}
-+
-+static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
-+ _core_if, dwc_hc_t * _hc)
-+{
-+ return (DWC_READ_REG32
-+ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
-+}
-+
-+/**
-+ * This function returns the mode of the operation, host or device.
-+ *
-+ * @return 0 - Device Mode, 1 - Host Mode
-+ */
-+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
-+{
-+ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
-+}
-+
-+/**@}*/
-+
-+/**
-+ * DWC_otg CIL callback structure. This structure allows the HCD and
-+ * PCD to register functions used for starting and stopping the PCD
-+ * and HCD for role change on for a DRD.
-+ */
-+typedef struct dwc_otg_cil_callbacks {
-+ /** Start function for role change */
-+ int (*start) (void *_p);
-+ /** Stop Function for role change */
-+ int (*stop) (void *_p);
-+ /** Disconnect Function for role change */
-+ int (*disconnect) (void *_p);
-+ /** Resume/Remote wakeup Function */
-+ int (*resume_wakeup) (void *_p);
-+ /** Suspend function */
-+ int (*suspend) (void *_p);
-+ /** Session Start (SRP) */
-+ int (*session_start) (void *_p);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ /** Sleep (switch to L0 state) */
-+ int (*sleep) (void *_p);
-+#endif
-+ /** Pointer passed to start() and stop() */
-+ void *p;
-+} dwc_otg_cil_callbacks_t;
-+
-+extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
-+ dwc_otg_cil_callbacks_t * _cb,
-+ void *_p);
-+extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
-+ dwc_otg_cil_callbacks_t * _cb,
-+ void *_p);
-+
-+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
-+
-+//////////////////////////////////////////////////////////////////////
-+/** Start the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->start) {
-+ core_if->hcd_cb->start(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Stop the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->stop) {
-+ core_if->hcd_cb->stop(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Disconnect the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
-+ core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Inform the HCD the a New Session has begun. Helper function for
-+ * using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
-+ core_if->hcd_cb->session_start(core_if->hcd_cb->p);
-+ }
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * Inform the HCD about LPM sleep.
-+ * Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
-+ core_if->hcd_cb->sleep(core_if->hcd_cb->p);
-+ }
-+}
-+#endif
-+
-+/** Resume the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
-+ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Start the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->start) {
-+ core_if->pcd_cb->start(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/** Stop the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->stop) {
-+ core_if->pcd_cb->stop(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/** Suspend the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
-+ core_if->pcd_cb->suspend(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/** Resume the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+}
-+
-+//////////////////////////////////////////////////////////////////////
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,1594 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
-+ * $Revision: #32 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * This file contains the Common Interrupt handlers.
-+ */
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_hcd.h"
-+
-+#ifdef DEBUG
-+inline const char *op_state_str(dwc_otg_core_if_t * core_if)
-+{
-+ return (core_if->op_state == A_HOST ? "a_host" :
-+ (core_if->op_state == A_SUSPEND ? "a_suspend" :
-+ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
-+ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
-+ (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
-+}
-+#endif
-+
-+/** This function will log a debug message
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
-+ dwc_otg_mode(core_if) ? "Host" : "Device");
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.modemismatch = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This function handles the OTG Interrupts. It reads the OTG
-+ * Interrupt Register (GOTGINT) to determine what interrupt has
-+ * occurred.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gotgint_data_t gotgint;
-+ gotgctl_data_t gotgctl;
-+ gintmsk_data_t gintmsk;
-+ gpwrdn_data_t gpwrdn;
-+
-+ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
-+ op_state_str(core_if));
-+
-+ if (gotgint.b.sesenddet) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Session End Detected++ (%s)\n",
-+ op_state_str(core_if));
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+
-+ if (core_if->op_state == B_HOST) {
-+ cil_pcd_start(core_if);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else {
-+ /* If not B_HOST and Device HNP still set. HNP
-+ * Did not succeed!*/
-+ if (gotgctl.b.devhnpen) {
-+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
-+ __DWC_ERROR("Device Not Connected/Responding!\n");
-+ }
-+
-+ /* If Session End Detected the B-Cable has
-+ * been disconnected. */
-+ /* Reset PCD and Gadget driver to a
-+ * clean state. */
-+ core_if->lx_state = DWC_OTG_L0;
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ if (core_if->adp_enable) {
-+ if (core_if->power_down == 2) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+ }
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ dwc_otg_adp_sense_start(core_if);
-+ }
-+ }
-+
-+ gotgctl.d32 = 0;
-+ gotgctl.b.devhnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+ }
-+ if (gotgint.b.sesreqsucstschng) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Session Reqeust Success Status Change++\n");
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+ if (gotgctl.b.sesreqscs) {
-+
-+ if ((core_if->core_params->phy_type ==
-+ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
-+ core_if->srp_success = 1;
-+ } else {
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_resume(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ /* Clear Session Request */
-+ gotgctl.d32 = 0;
-+ gotgctl.b.sesreq = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+ }
-+ }
-+ }
-+ if (gotgint.b.hstnegsucstschng) {
-+ /* Print statements during the HNP interrupt handling
-+ * can cause it to fail.*/
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+ /* WA for 3.00a- HW is not setting cur_mode, even sometimes
-+ * this does not help*/
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ dwc_udelay(100);
-+ if (gotgctl.b.hstnegscs) {
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ core_if->op_state = B_HOST;
-+ /*
-+ * Need to disable SOF interrupt immediately.
-+ * When switching from device to host, the PCD
-+ * interrupt handler won't handle the
-+ * interrupt if host mode is already set. The
-+ * HCD interrupt handler won't get called if
-+ * the HCD state is HALT. This means that the
-+ * interrupt does not get handled and Linux
-+ * complains loudly.
-+ */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk,
-+ gintmsk.d32, 0);
-+ /* Call callback function with spin lock released */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ cil_hcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = B_HOST;
-+ }
-+ } else {
-+ gotgctl.d32 = 0;
-+ gotgctl.b.hnpreq = 1;
-+ gotgctl.b.devhnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
-+ __DWC_ERROR("Device Not Connected/Responding\n");
-+ }
-+ }
-+ if (gotgint.b.hstnegdet) {
-+ /* The disconnect interrupt is set at the same time as
-+ * Host Negotiation Detected. During the mode
-+ * switch all interrupts are cleared so the disconnect
-+ * interrupt handler will not get executed.
-+ */
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Host Negotiation Detected++ (%s)\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" :
-+ "Device"));
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
-+ core_if->op_state);
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_disconnect(core_if);
-+ cil_pcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = A_PERIPHERAL;
-+ } else {
-+ /*
-+ * Need to disable SOF interrupt immediately. When
-+ * switching from device to host, the PCD interrupt
-+ * handler won't handle the interrupt if host mode is
-+ * already set. The HCD interrupt handler won't get
-+ * called if the HCD state is HALT. This means that
-+ * the interrupt does not get handled and Linux
-+ * complains loudly.
-+ */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ cil_hcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = A_HOST;
-+ }
-+ }
-+ if (gotgint.b.adevtoutchng) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "A-Device Timeout Change++\n");
-+ }
-+ if (gotgint.b.debdone) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
-+ }
-+
-+ /* Clear GOTGINT */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
-+
-+ return 1;
-+}
-+
-+void w_conn_id_status_change(void *p)
-+{
-+ dwc_otg_core_if_t *core_if = p;
-+ uint32_t count = 0;
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
-+
-+ /* B-Device connector (Device Mode) */
-+ if (gotgctl.b.conidsts) {
-+ /* Wait for switch to device mode. */
-+ while (!dwc_otg_is_device_mode(core_if)) {
-+ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" :
-+ "Peripheral"));
-+ dwc_mdelay(100);
-+ if (++count > 10000)
-+ break;
-+ }
-+ DWC_ASSERT(++count < 10000,
-+ "Connection id status change timed out");
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ } else {
-+ /* A-Device connector (Host Mode) */
-+ while (!dwc_otg_is_host_mode(core_if)) {
-+ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" :
-+ "Peripheral"));
-+ dwc_mdelay(100);
-+ if (++count > 10000)
-+ break;
-+ }
-+ DWC_ASSERT(++count < 10000,
-+ "Connection id status change timed out");
-+ core_if->op_state = A_HOST;
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+}
-+
-+/**
-+ * This function handles the Connector ID Status Change Interrupt. It
-+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
-+ * is a Device to Host Mode transition or a Host Mode to Device
-+ * Transition.
-+ *
-+ * This only occurs when the cable is connected/removed from the PHY
-+ * connector.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
-+{
-+
-+ /*
-+ * Need to disable SOF interrupt immediately. If switching from device
-+ * to host, the PCD interrupt handler won't handle the interrupt if
-+ * host mode is already set. The HCD interrupt handler won't get
-+ * called if the HCD state is HALT. This means that the interrupt does
-+ * not get handled and Linux complains loudly.
-+ */
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ gintsts_data_t gintsts = {.d32 = 0 };
-+
-+ gintmsk.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ " ++Connector ID Status Change Interrupt++ (%s)\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
-+
-+ DWC_SPINUNLOCK(core_if->lock);
-+
-+ /*
-+ * Need to schedule a work, as there are possible DELAY function calls
-+ * Release lock before scheduling workq as it holds spinlock during scheduling
-+ */
-+
-+ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
-+ core_if, "connection id status change");
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ /* Set flag and clear interrupt */
-+ gintsts.b.conidstschng = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device is initiating the Session
-+ * Request Protocol to request the host to turn on bus power so a new
-+ * session can begin. The handler responds by turning on bus power. If
-+ * the DWC_otg controller is in low power mode, the handler brings the
-+ * controller out of low power mode before turning on bus power.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+#ifndef DWC_HOST_ONLY
-+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_PRINTF("SRP: Device mode\n");
-+ } else {
-+ hprt0_data_t hprt0;
-+ DWC_PRINTF("SRP: Host mode\n");
-+
-+ /* Turn on the port power bit. */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Start the Connection timer. So a message can be displayed
-+ * if connect does not occur within 10 seconds. */
-+ cil_hcd_session_start(core_if);
-+ }
-+#endif
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.sessreqintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+void w_wakeup_detected(void *p)
-+{
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
-+ /*
-+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
-+ * so that OPT tests pass with all PHYs).
-+ */
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+#if 0
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ /* Restart the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ dwc_udelay(10);
-+#endif //0
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
-+// dwc_mdelay(70);
-+ hprt0.b.prtres = 0; /* Resume */
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
-+ DWC_READ_REG32(core_if->host_if->hprt0));
-+
-+ cil_hcd_resume(core_if);
-+
-+ /** Change to L0 state*/
-+ core_if->lx_state = DWC_OTG_L0;
-+}
-+
-+/**
-+ * This interrupt indicates that the DWC_otg controller has detected a
-+ * resume or remote wakeup sequence. If the DWC_otg controller is in
-+ * low power mode, the handler must brings the controller out of low
-+ * power mode. The controller automatically begins resume
-+ * signaling. The handler schedules a time to stop resume signaling.
-+ */
-+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "++Resume and Remote Wakeup Detected Interrupt++\n");
-+
-+ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
-+ dsts));
-+ if (core_if->lx_state == DWC_OTG_L2) {
-+#ifdef PARTIAL_POWER_DOWN
-+ if (core_if->hwcfg4.b.power_optimiz) {
-+ pcgcctl_data_t power = {.d32 = 0 };
-+
-+ power.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
-+ power.d32);
-+
-+ power.b.stoppclk = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+ power.b.pwrclmp = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+ power.b.rstpdwnmodule = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+ }
-+#endif
-+ /* Clear the Remote Wakeup Signaling */
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, dctl.d32, 0);
-+
-+ DWC_SPINUNLOCK(core_if->lock);
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+ DWC_SPINLOCK(core_if->lock);
-+ } else {
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+ }
-+ /** Change to L0 state*/
-+ core_if->lx_state = DWC_OTG_L0;
-+ } else {
-+ if (core_if->lx_state != DWC_OTG_L1) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+
-+ /* Restart the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
-+ } else {
-+ /** Change to L0 state*/
-+ core_if->lx_state = DWC_OTG_L0;
-+ }
-+ }
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.wkupintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * Device disconnect.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
-+{
-+ gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
-+ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps*/
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ if (gpwrdn_temp.b.idsts) {
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ } else {
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * remote wakeup sequence.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_ANY,
-+ "++Powerdown Remote Wakeup Detected Interrupt++\n");
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (gpwrdn.b.idsts) { // Device Mode
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ dwc_otg_device_hibernation_restore(core_if, 0, 0);
-+ }
-+ } else {
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ dwc_otg_host_hibernation_restore(core_if, 1, 0);
-+ }
-+ }
-+ return 1;
-+}
-+
-+static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (core_if->power_down == 2) {
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /*Indicates that we are exiting from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
-+ if (gpwrdn.b.dis_vbus == 1) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ }
-+
-+ if (gpwrdn_temp.b.idsts) {
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ } else {
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+ }
-+
-+ if (core_if->adp_enable) {
-+ uint8_t is_host = 0;
-+ DWC_SPINUNLOCK(core_if->lock);
-+ /* Change the core_if's lock to hcd/pcd lock depend on mode? */
-+#ifndef DWC_HOST_ONLY
-+ if (gpwrdn_temp.b.idsts)
-+ core_if->lock = otg_dev->pcd->lock;
-+#endif
-+#ifndef DWC_DEVICE_ONLY
-+ if (!gpwrdn_temp.b.idsts) {
-+ core_if->lock = otg_dev->hcd->lock;
-+ is_host = 1;
-+ }
-+#endif
-+ DWC_PRINTF("RESTART ADP\n");
-+ if (core_if->adp.probe_enabled)
-+ dwc_otg_adp_probe_stop(core_if);
-+ if (core_if->adp.sense_enabled)
-+ dwc_otg_adp_sense_stop(core_if);
-+ if (core_if->adp.sense_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+ if (core_if->adp.vbuson_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
-+ core_if->adp.probe_timer_values[0] = -1;
-+ core_if->adp.probe_timer_values[1] = -1;
-+ core_if->adp.sense_timer_started = 0;
-+ core_if->adp.vbuson_timer_started = 0;
-+ core_if->adp.probe_counter = 0;
-+ core_if->adp.gpwrdn = 0;
-+
-+ /* Disable PMU and restart ADP */
-+ gpwrdn_temp.d32 = 0;
-+ gpwrdn_temp.b.pmuactv = 1;
-+ gpwrdn_temp.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ DWC_PRINTF("Check point 1\n");
-+ dwc_mdelay(110);
-+ dwc_otg_adp_start(core_if, is_host);
-+ DWC_SPINLOCK(core_if->lock);
-+ }
-+
-+
-+ return 1;
-+}
-+
-+static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ int32_t otg_cap_param = core_if->core_params->otg_cap;
-+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (core_if->power_down == 2) {
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
-+ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
-+ gpwrdn.b.bsessvld == 0) {
-+ /* Save gpwrdn register for further usage if stschng interrupt */
-+ core_if->gr_backup->gpwrdn_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
-+ return 1;
-+ }
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /*Indicates that we are exiting from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
-+ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
-+ /*
-+ * Initiate SRP after initial ADP probe.
-+ */
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+ }
-+
-+ return 1;
-+}
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * status change either on IDDIG or BSessVld.
-+ */
-+static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
-+{
-+ int retval;
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (core_if->power_down == 2) {
-+ if (core_if->hibernation_suspend <= 0) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ } else
-+ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
-+
-+ } else {
-+ gpwrdn_temp.d32 = core_if->adp.gpwrdn;
-+ }
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
-+ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
-+ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
-+ retval = dwc_otg_handle_pwrdn_session_change(core_if);
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * SRP.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+#ifdef DWC_DEV_SRPCAP
-+ if (core_if->pwron_timer_started) {
-+ core_if->pwron_timer_started = 0;
-+ DWC_TIMER_CANCEL(core_if->pwron_timer);
-+ }
-+#endif
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Indicates that we are exiting from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Programm Disable VBUS to 0 */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /*Initialize the core as Host */
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+
-+ return 1;
-+}
-+
-+/** This interrupt indicates that restore command after Hibernation
-+ * was completed by the core. */
-+int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
-+{
-+ pcgcctl_data_t pcgcctl;
-+ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
-+
-+ //TODO De-assert restore signal. 8.a
-+ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+ if (pcgcctl.b.restoremode == 1) {
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ /*
-+ * If restore mode is Remote Wakeup,
-+ * unmask Remote Wakeup interrupt.
-+ */
-+ gintmsk.b.wkupintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ 0, gintmsk.d32);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device has been disconnected from
-+ * the root port.
-+ */
-+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
-+ op_state_str(core_if));
-+
-+/** @todo Consolidate this if statement. */
-+#ifndef DWC_HOST_ONLY
-+ if (core_if->op_state == B_HOST) {
-+ /* If in device mode Disconnect and stop the HCD, then
-+ * start the PCD. */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_disconnect(core_if);
-+ cil_pcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else if (dwc_otg_is_device_mode(core_if)) {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gotgctl.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ if (gotgctl.b.hstsethnpen == 1) {
-+ /* Do nothing, if HNP in process the OTG
-+ * interrupt "Host Negotiation Detected"
-+ * interrupt will do the mode switch.
-+ */
-+ } else if (gotgctl.b.devhnpen == 0) {
-+ /* If in device mode Disconnect and stop the HCD, then
-+ * start the PCD. */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_disconnect(core_if);
-+ cil_pcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
-+ }
-+ } else {
-+ if (core_if->op_state == A_HOST) {
-+ /* A-Cable still connected but device disconnected. */
-+ cil_hcd_disconnect(core_if);
-+ if (core_if->adp_enable) {
-+ gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+ cil_hcd_stop(core_if);
-+ /* Enable Power Down Logic */
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_otg_adp_probe_start(core_if);
-+
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32
-+ (&core_if->core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+ }
-+ }
-+ }
-+ }
-+#endif
-+ /* Change to L3(OFF) state */
-+ core_if->lx_state = DWC_OTG_L3;
-+
-+ gintsts.d32 = 0;
-+ gintsts.b.disconnect = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that SUSPEND state has been detected on
-+ * the USB.
-+ *
-+ * For HNP the USB Suspend interrupt signals the change from
-+ * "a_peripheral" to "a_host".
-+ *
-+ * When power management is enabled the core will be put in low power
-+ * mode.
-+ */
-+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ gintsts_data_t gintsts;
-+ dcfg_data_t dcfg;
-+
-+ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ /* Check the Device status register to determine if the Suspend
-+ * state is active. */
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
-+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
-+ "HWCFG4.power Optimize=%d\n",
-+ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
-+
-+#ifdef PARTIAL_POWER_DOWN
-+/** @todo Add a module parameter for power management. */
-+
-+ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
-+ pcgcctl_data_t power = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_CIL, "suspend\n");
-+
-+ power.b.pwrclmp = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+ power.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
-+
-+ power.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
-+
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
-+ }
-+#endif
-+ /* PCD callback for suspend. Release the lock inside of callback function */
-+ cil_pcd_suspend(core_if);
-+ if (core_if->power_down == 2)
-+ {
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
-+ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
-+
-+ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+
-+ /* Change to L2(suspend) state */
-+ core_if->lx_state = DWC_OTG_L2;
-+
-+ /* Clear interrupt in gintsts */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, gintsts.d32);
-+ DWC_PRINTF("Start of hibernation completed\n");
-+ dwc_otg_save_global_regs(core_if);
-+ dwc_otg_save_dev_regs(core_if);
-+
-+ gusbcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->
-+ gusbcfg);
-+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ /* Suspend the Phy Clock */
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ } else {
-+ /* UTMI+ Interface */
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ }
-+
-+ /* Set flag to indicate that we are in hibernation */
-+ core_if->hibernation_suspend = 1;
-+ /* Enable interrupts from wake up logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Unmask device mode interrupts in GPWRDN */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.rst_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ gpwrdn.b.sts_chngint_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Enable Power Down Clamp */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Switch off VDD */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ /* Save gpwrdn register for further usage if stschng interrupt */
-+ core_if->gr_backup->gpwrdn_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ DWC_PRINTF("Hibernation completed\n");
-+
-+ return 1;
-+ }
-+ } else if (core_if->power_down == 3) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
-+ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
-+
-+ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
-+ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
-+ core_if->xhib = 1;
-+
-+ /* Clear interrupt in gintsts */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, gintsts.d32);
-+
-+ dwc_otg_save_global_regs(core_if);
-+ dwc_otg_save_dev_regs(core_if);
-+
-+ /* Wait for 10 PHY clocks */
-+ dwc_udelay(10);
-+
-+ /* Program GPIO register while entering to xHib */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
-+
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.extnd_hiber_pwrclmp = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.extnd_hiber_switch = 1;
-+ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
-+
-+ return 1;
-+ }
-+ }
-+ } else {
-+ if (core_if->op_state == A_PERIPHERAL) {
-+ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
-+ /* Clear the a_peripheral flag, back to a_host. */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ cil_hcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = A_HOST;
-+ }
-+ }
-+
-+ /* Change to L2(suspend) state */
-+ core_if->lx_state = DWC_OTG_L2;
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+
-+ dwc_udelay(10);
-+
-+ /* Program GPIO register while entering to xHib */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
-+
-+ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
-+ pcgcctl.b.extnd_hiber_pwrclmp = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
-+ gpwrdn.b.restore = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ restore_lpm_i2c_regs(core_if);
-+
-+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+ pcgcctl.b.max_xcvrselect = 1;
-+ pcgcctl.b.ess_reg_restored = 0;
-+ pcgcctl.b.extnd_hiber_switch = 0;
-+ pcgcctl.b.extnd_hiber_pwrclmp = 0;
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+
-+ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
-+ gahbcfg.b.glblintrmsk = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+ core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+ core_if->dr_backup->dcfg);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+ pcgcctl.b.max_xcvrselect = 1;
-+ pcgcctl.d32 |= 0x608;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+ pcgcctl.b.max_xcvrselect = 1;
-+ pcgcctl.b.ess_reg_restored = 1;
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ pcgcctl.b.rstpdwnmodule = 1;
-+ pcgcctl.b.restoremode = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+
-+ return 1;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * This function hadles LPM transaction received interrupt.
-+ */
-+static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ gintsts_data_t gintsts;
-+
-+ if (!core_if->core_params->lpm_enable) {
-+ DWC_PRINTF("Unexpected LPM interrupt\n");
-+ }
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
-+
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ cil_hcd_sleep(core_if);
-+ } else {
-+ lpmcfg.b.hird_thres |= (1 << 4);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+ }
-+
-+ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
-+ dwc_udelay(10);
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.prt_sleep_sts) {
-+ /* Save the current state */
-+ core_if->lx_state = DWC_OTG_L1;
-+ }
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.lpmtranrcvd = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
-+{
-+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+ gintmsk_data_t gintmsk_common = {.d32 = 0 };
-+ gintmsk_common.b.wkupintr = 1;
-+ gintmsk_common.b.sessreqintr = 1;
-+ gintmsk_common.b.conidstschng = 1;
-+ gintmsk_common.b.otgintr = 1;
-+ gintmsk_common.b.modemismatch = 1;
-+ gintmsk_common.b.disconnect = 1;
-+ gintmsk_common.b.usbsuspend = 1;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ gintmsk_common.b.lpmtranrcvd = 1;
-+#endif
-+ gintmsk_common.b.restoredone = 1;
-+ if(dwc_otg_is_device_mode(core_if))
-+ {
-+ /** @todo: The port interrupt occurs while in device
-+ * mode. Added code to CIL to clear the interrupt for now!
-+ */
-+ gintmsk_common.b.portintr = 1;
-+ }
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+ if(fiq_enable) {
-+ local_fiq_disable();
-+ /* Pull in the interrupts that the FIQ has masked */
-+ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
-+ gintmsk.d32 |= gintmsk_common.d32;
-+ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
-+ reenable_gintmsk->d32 = gintmsk.d32;
-+ local_fiq_enable();
-+ }
-+
-+ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
-+
-+#ifdef DEBUG
-+ /* if any common interrupts set */
-+ if (gintsts.d32 & gintmsk_common.d32) {
-+ DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n",
-+ gintsts.d32, gintmsk.d32);
-+ }
-+#endif
-+ if (!fiq_enable){
-+ if (gahbcfg.b.glblintrmsk)
-+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+ else
-+ return 0;
-+ } else {
-+ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
-+ * Can't trust the global interrupt mask bit in this case.
-+ */
-+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+ }
-+
-+}
-+
-+/* MACRO for clearing interupt bits in GPWRDN register */
-+#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
-+do { \
-+ gpwrdn_data_t gpwrdn = {.d32=0}; \
-+ gpwrdn.b.__intr = 1; \
-+ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
-+ 0, gpwrdn.d32); \
-+} while (0)
-+
-+/**
-+ * Common interrupt handler.
-+ *
-+ * The common interrupts are those that occur in both Host and Device mode.
-+ * This handler handles the following interrupts:
-+ * - Mode Mismatch Interrupt
-+ * - Disconnect Interrupt
-+ * - OTG Interrupt
-+ * - Connector ID Status Change Interrupt
-+ * - Session Request Interrupt.
-+ * - Resume / Remote Wakeup Detected Interrupt.
-+ * - LPM Transaction Received Interrupt
-+ * - ADP Transaction Received Interrupt
-+ *
-+ */
-+int32_t dwc_otg_handle_common_intr(void *dev)
-+{
-+ int retval = 0;
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ dwc_otg_device_t *otg_dev = dev;
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (dwc_otg_is_device_mode(core_if))
-+ core_if->frame_num = dwc_otg_get_frame_number(core_if);
-+
-+ if (core_if->lock)
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ if (core_if->power_down == 3 && core_if->xhib == 1) {
-+ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
-+ retval |= dwc_otg_handle_xhib_exit_intr(core_if);
-+ core_if->xhib = 2;
-+ if (core_if->lock)
-+ DWC_SPINUNLOCK(core_if->lock);
-+
-+ return retval;
-+ }
-+
-+ if (core_if->hibernation_suspend <= 0) {
-+ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
-+ * of this handler - god only knows why it's done like this
-+ */
-+ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
-+
-+ if (gintsts.b.modemismatch) {
-+ retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
-+ }
-+ if (gintsts.b.otgintr) {
-+ retval |= dwc_otg_handle_otg_intr(core_if);
-+ }
-+ if (gintsts.b.conidstschng) {
-+ retval |=
-+ dwc_otg_handle_conn_id_status_change_intr(core_if);
-+ }
-+ if (gintsts.b.disconnect) {
-+ retval |= dwc_otg_handle_disconnect_intr(core_if);
-+ }
-+ if (gintsts.b.sessreqintr) {
-+ retval |= dwc_otg_handle_session_req_intr(core_if);
-+ }
-+ if (gintsts.b.wkupintr) {
-+ retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
-+ }
-+ if (gintsts.b.usbsuspend) {
-+ retval |= dwc_otg_handle_usb_suspend_intr(core_if);
-+ }
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (gintsts.b.lpmtranrcvd) {
-+ retval |= dwc_otg_handle_lpm_intr(core_if);
-+ }
-+#endif
-+ if (gintsts.b.restoredone) {
-+ gintsts.d32 = 0;
-+ if (core_if->power_down == 2)
-+ core_if->hibernation_suspend = -1;
-+ else if (core_if->power_down == 3 && core_if->xhib == 2) {
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, 0xFFFFFFFF);
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "RESTORE DONE generated\n");
-+
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ pcgcctl.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
-+ dwc_udelay(50);
-+
-+ dctl.b.pwronprgdone = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ dwc_udelay(10);
-+
-+ dwc_otg_restore_global_regs(core_if);
-+ dwc_otg_restore_dev_regs(core_if, 0);
-+
-+ dctl.d32 = 0;
-+ dctl.b.pwronprgdone = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+ dwc_udelay(10);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+ /* The core will be in ON STATE */
-+ core_if->lx_state = DWC_OTG_L0;
-+ core_if->xhib = 0;
-+
-+ DWC_SPINUNLOCK(core_if->lock);
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ }
-+
-+ gintsts.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
-+ DWC_PRINTF(" --Restore done interrupt received-- \n");
-+ retval |= 1;
-+ }
-+ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
-+ /* The port interrupt occurs while in device mode with HPRT0
-+ * Port Enable/Disable.
-+ */
-+ gintsts.d32 = 0;
-+ gintsts.b.portintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
-+ retval |= 1;
-+ gintmsk_reenable.b.portintr = 1;
-+
-+ }
-+ /* Did we actually handle anything? if so, unmask the interrupt */
-+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
-+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
-+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
-+ if (retval && fiq_enable) {
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
-+ }
-+
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
-+
-+ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, disconn_det);
-+ if (gpwrdn.b.linestate == 0) {
-+ dwc_otg_handle_pwrdn_disconnect_intr(core_if);
-+ } else {
-+ DWC_PRINTF("Disconnect detected while linestate is not 0\n");
-+ }
-+
-+ retval |= 1;
-+ }
-+ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, lnstschng);
-+ /* remote wakeup from hibernation */
-+ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
-+ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
-+ } else {
-+ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
-+ }
-+ retval |= 1;
-+ }
-+ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, rst_det);
-+ if (gpwrdn.b.linestate == 0) {
-+ DWC_PRINTF("Reset detected\n");
-+ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
-+ }
-+ }
-+ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, srp_det);
-+ dwc_otg_handle_pwrdn_srp_intr(core_if);
-+ retval |= 1;
-+ }
-+ }
-+ /* Handle ADP interrupt here */
-+ if (gpwrdn.b.adp_int) {
-+ DWC_PRINTF("ADP interrupt\n");
-+ CLEAR_GPWRDN_INTR(core_if, adp_int);
-+ dwc_otg_adp_handle_intr(core_if);
-+ retval |= 1;
-+ }
-+ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
-+ DWC_PRINTF("STS CHNG interrupt asserted\n");
-+ CLEAR_GPWRDN_INTR(core_if, sts_chngint);
-+ dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
-+
-+ retval |= 1;
-+ }
-+ if (core_if->lock)
-+ DWC_SPINUNLOCK(core_if->lock);
-+ return retval;
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_core_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,705 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
-+ * $Revision: #13 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#if !defined(__DWC_CORE_IF_H__)
-+#define __DWC_CORE_IF_H__
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ * This file defines DWC_OTG Core API
-+ */
-+
-+struct dwc_otg_core_if;
-+typedef struct dwc_otg_core_if dwc_otg_core_if_t;
-+
-+/** Maximum number of Periodic FIFOs */
-+#define MAX_PERIO_FIFOS 15
-+/** Maximum number of Periodic FIFOs */
-+#define MAX_TX_FIFOS 15
-+
-+/** Maximum number of Endpoints/HostChannels */
-+#define MAX_EPS_CHANNELS 16
-+
-+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
-+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
-+
-+extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
-+extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
-+
-+extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
-+
-+/** This function should be called on every hardware interrupt. */
-+extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
-+
-+/** @name OTG Core Parameters */
-+/** @{ */
-+
-+/**
-+ * Specifies the OTG capabilities. The driver will automatically
-+ * detect the value for this parameter if none is specified.
-+ * 0 - HNP and SRP capable (default)
-+ * 1 - SRP Only capable
-+ * 2 - No HNP/SRP capable
-+ */
-+extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
-+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
-+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
-+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
-+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
-+
-+extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
-+#define dwc_param_opt_default 1
-+
-+/**
-+ * Specifies whether to use slave or DMA mode for accessing the data
-+ * FIFOs. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - Slave
-+ * 1 - DMA (default, if available)
-+ */
-+extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dma_enable_default 1
-+
-+/**
-+ * When DMA mode is enabled specifies whether to use
-+ * address DMA or DMA Descritor mode for accessing the data
-+ * FIFOs in device mode. The driver will automatically detect
-+ * the value for this parameter if none is specified.
-+ * 0 - address DMA
-+ * 1 - DMA Descriptor(default, if available)
-+ */
-+extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_dma_desc_enable_default 1
-+#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
-+
-+/** The DMA Burst size (applicable only for External DMA
-+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ */
-+extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dma_burst_size_default 32
-+
-+/**
-+ * Specifies the maximum speed of operation in host and device mode.
-+ * The actual speed depends on the speed of the attached device and
-+ * the value of phy_type. The actual speed depends on the speed of the
-+ * attached device.
-+ * 0 - High Speed (default)
-+ * 1 - Full Speed
-+ */
-+extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
-+#define dwc_param_speed_default 0
-+#define DWC_SPEED_PARAM_HIGH 0
-+#define DWC_SPEED_PARAM_FULL 1
-+
-+/** Specifies whether low power mode is supported when attached
-+ * to a Full Speed or Low Speed device in host mode.
-+ * 0 - Don't support low power mode (default)
-+ * 1 - Support low power mode
-+ */
-+extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
-+ * core_if);
-+#define dwc_param_host_support_fs_ls_low_power_default 0
-+
-+/** Specifies the PHY clock rate in low power mode when connected to a
-+ * Low Speed device in host mode. This parameter is applicable only if
-+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+ * then defaults to 6 MHZ otherwise 48 MHZ.
-+ *
-+ * 0 - 48 MHz
-+ * 1 - 6 MHz
-+ */
-+extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_host_ls_low_power_phy_clk_default 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
-+
-+/**
-+ * 0 - Use cC FIFO size parameters
-+ * 1 - Allow dynamic FIFO sizing (default)
-+ */
-+extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_enable_dynamic_fifo_default 1
-+
-+/** Total number of 4-byte words in the data FIFO memory. This
-+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+ * Tx FIFOs.
-+ * 32 to 32768 (default 8192)
-+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ */
-+extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_data_fifo_size_default 8192
-+#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1064)
-+ */
-+extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_rx_fifo_size_default 1064
-+
-+/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+ * when dynamic FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
-+
-+/** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val, int fifo_num);
-+extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int fifo_num);
-+#define dwc_param_dev_perio_tx_fifo_size_default 256
-+
-+/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_host_rx_fifo_size_default 1024
-+#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+ * when Dynamic FIFO sizing is enabled in the core.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if);
-+//#define dwc_param_host_nperio_tx_fifo_size_default 1024
-+#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if);
-+//#define dwc_param_host_perio_tx_fifo_size_default 1024
-+#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
-+
-+/** The maximum transfer size supported in bytes.
-+ * 2047 to 65,535 (default 65,535)
-+ */
-+extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_max_transfer_size_default 65535
-+
-+/** The maximum number of packets in a transfer.
-+ * 15 to 511 (default 511)
-+ */
-+extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
-+#define dwc_param_max_packet_count_default 511
-+
-+/** The number of host channel registers to use.
-+ * 1 to 16 (default 12)
-+ * Note: The FPGA configuration supports a maximum of 12 host channels.
-+ */
-+extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_host_channels_default 12
-+#define dwc_param_host_channels_default 8 // Broadcom BCM2708
-+
-+/** The number of endpoints in addition to EP0 available for device
-+ * mode operations.
-+ * 1 to 15 (default 6 IN and OUT)
-+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+ * endpoints in addition to EP0.
-+ */
-+extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_endpoints_default 6
-+
-+/**
-+ * Specifies the type of PHY interface to use. By default, the driver
-+ * will automatically detect the phy_type.
-+ *
-+ * 0 - Full Speed PHY
-+ * 1 - UTMI+ (default)
-+ * 2 - ULPI
-+ */
-+extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
-+#define DWC_PHY_TYPE_PARAM_FS 0
-+#define DWC_PHY_TYPE_PARAM_UTMI 1
-+#define DWC_PHY_TYPE_PARAM_ULPI 2
-+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
-+
-+/**
-+ * Specifies the UTMI+ Data Width. This parameter is
-+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+ * PHY_TYPE, this parameter indicates the data width between
-+ * the MAC and the ULPI Wrapper.) Also, this parameter is
-+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+ * to "8 and 16 bits", meaning that the core has been
-+ * configured to work at either data path width.
-+ *
-+ * 8 or 16 bits (default 16)
-+ */
-+extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_phy_utmi_width_default 16
-+#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
-+
-+/**
-+ * Specifies whether the ULPI operates at double or single
-+ * data rate. This parameter is only applicable if PHY_TYPE is
-+ * ULPI.
-+ *
-+ * 0 - single data rate ULPI interface with 8 bit wide data
-+ * bus (default)
-+ * 1 - double data rate ULPI interface with 4 bit wide data
-+ * bus
-+ */
-+extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
-+#define dwc_param_phy_ulpi_ddr_default 0
-+
-+/**
-+ * Specifies whether to use the internal or external supply to
-+ * drive the vbus with a ULPI phy.
-+ */
-+extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
-+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
-+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
-+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
-+
-+/**
-+ * Specifies whether to use the I2Cinterface for full speed PHY. This
-+ * parameter is only applicable if PHY_TYPE is FS.
-+ * 0 - No (default)
-+ * 1 - Yes
-+ */
-+extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_i2c_enable_default 0
-+
-+extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ulpi_fs_ls_default 0
-+
-+extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ts_dline_default 0
-+
-+/**
-+ * Specifies whether dedicated transmit FIFOs are
-+ * enabled for non periodic IN endpoints in device mode
-+ * 0 - No
-+ * 1 - Yes
-+ */
-+extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_en_multiple_tx_fifo_default 1
-+
-+/** Number of 4-byte words in each of the Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num, int32_t val);
-+extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num);
-+#define dwc_param_dev_tx_fifo_size_default 768
-+
-+/** Thresholding enable flag-
-+ * bit 0 - enable non-ISO Tx thresholding
-+ * bit 1 - enable ISO Tx thresholding
-+ * bit 2 - enable Rx thresholding
-+ */
-+extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
-+#define dwc_param_thr_ctl_default 0
-+
-+/** Thresholding length for Tx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
-+#define dwc_param_tx_thr_length_default 64
-+
-+/** Thresholding length for Rx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
-+#define dwc_param_rx_thr_length_default 64
-+
-+/**
-+ * Specifies whether LPM (Link Power Management) support is enabled
-+ */
-+extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_lpm_enable_default 1
-+
-+/**
-+ * Specifies whether PTI enhancement is enabled
-+ */
-+extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_pti_enable_default 0
-+
-+/**
-+ * Specifies whether MPI enhancement is enabled
-+ */
-+extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_mpi_enable_default 0
-+
-+/**
-+ * Specifies whether ADP capability is enabled
-+ */
-+extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_adp_enable_default 0
-+
-+/**
-+ * Specifies whether IC_USB capability is enabled
-+ */
-+
-+extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ic_usb_cap_default 0
-+
-+extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ahb_thr_ratio_default 0
-+
-+extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
-+#define dwc_param_power_down_default 0
-+
-+extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
-+#define dwc_param_reload_ctl_default 0
-+
-+extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_out_nak_default 0
-+
-+extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
-+#define dwc_param_cont_on_bna_default 0
-+
-+extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ahb_single_default 0
-+
-+extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
-+#define dwc_param_otg_ver_default 0
-+
-+/** @} */
-+
-+/** @name Access to registers and bit-fields */
-+
-+/**
-+ * Dump core registers and SPRAM
-+ */
-+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
-+
-+/**
-+ * Get host negotiation status.
-+ */
-+extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get srp status
-+ */
-+extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Set hnpreq bit in the GOTGCTL register.
-+ */
-+extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get Content of SNPSID register.
-+ */
-+extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get current mode.
-+ * Returns 0 if in device mode, and 1 if in host mode.
-+ */
-+extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of hnpcapable field in the GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of hnpcapable field in the GUSBCFG register
-+ */
-+extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of srpcapable field in the GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of srpcapable field in the GUSBCFG register
-+ */
-+extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of devspeed field in the DCFG register
-+ */
-+extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of devspeed field in the DCFG register
-+ */
-+extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get the value of busconnected field from the HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Gets the device enumeration Speed.
-+ */
-+extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of prtpwr field from the HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of flag indicating core state - hibernated or not
-+ */
-+extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Set value of prtpwr field from the HPRT0 register
-+ */
-+extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of prtsusp field from the HPRT0 regsiter
-+ */
-+extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of prtpwr field from the HPRT0 register
-+ */
-+extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of ModeChTimEn field from the HCFG regsiter
-+ */
-+extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of ModeChTimEn field from the HCFG regsiter
-+ */
-+extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of Fram Interval field from the HFIR regsiter
-+ */
-+extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of Frame Interval field from the HFIR regsiter
-+ */
-+extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Set value of prtres field from the HPRT0 register
-+ *FIXME Remove?
-+ */
-+extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of rmtwkupsig bit in DCTL register
-+ */
-+extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of prt_sleep_sts field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of rem_wkup_en field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of appl_resp field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of appl_resp field from the GLPMCFG register
-+ */
-+extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of hsic_connect field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of hsic_connect field from the GLPMCFG register
-+ */
-+extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of inv_sel_hsic field from the GLPMCFG register.
-+ */
-+extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of inv_sel_hsic field from the GLPMFG register.
-+ */
-+extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/*
-+ * Some functions for accessing registers
-+ */
-+
-+/**
-+ * GOTGCTL register
-+ */
-+extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GRXFSIZ register
-+ */
-+extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GNPTXFSIZ register
-+ */
-+extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GGPIO register
-+ */
-+extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GUID register
-+ */
-+extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GHPTXFSIZE
-+ */
-+extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
-+
-+/** @} */
-+
-+#endif /* __DWC_CORE_IF_H__ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_dbg.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,117 @@
-+/* ==========================================================================
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_DBG_H__
-+#define __DWC_OTG_DBG_H__
-+
-+/** @file
-+ * This file defines debug levels.
-+ * Debugging support vanishes in non-debug builds.
-+ */
-+
-+/**
-+ * The Debug Level bit-mask variable.
-+ */
-+extern uint32_t g_dbg_lvl;
-+/**
-+ * Set the Debug Level variable.
-+ */
-+static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
-+{
-+ uint32_t old = g_dbg_lvl;
-+ g_dbg_lvl = new;
-+ return old;
-+}
-+
-+#define DBG_USER (0x1)
-+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
-+#define DBG_CIL (0x2)
-+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
-+ * messages */
-+#define DBG_CILV (0x20)
-+/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
-+ * messages */
-+#define DBG_PCD (0x4)
-+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
-+ * messages */
-+#define DBG_PCDV (0x40)
-+/** When debug level has the DBG_HCD bit set, display Host debug messages */
-+#define DBG_HCD (0x8)
-+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
-+ * messages */
-+#define DBG_HCDV (0x80)
-+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
-+ * mode. */
-+#define DBG_HCD_URB (0x800)
-+/** When debug level has the DBG_HCDI bit set, display host interrupt
-+ * messages. */
-+#define DBG_HCDI (0x1000)
-+
-+/** When debug level has any bit set, display debug messages */
-+#define DBG_ANY (0xFF)
-+
-+/** All debug messages off */
-+#define DBG_OFF 0
-+
-+/** Prefix string for DWC_DEBUG print macros. */
-+#define USB_DWC "DWC_otg: "
-+
-+/**
-+ * Print a debug message when the Global debug level variable contains
-+ * the bit defined in <code>lvl</code>.
-+ *
-+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
-+ * @param[in] x - like printf
-+ *
-+ * Example:<p>
-+ * <code>
-+ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
-+ * </code>
-+ * <br>
-+ * results in:<br>
-+ * <code>
-+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
-+ * </code>
-+ */
-+#ifdef DEBUG
-+
-+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
-+# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
-+
-+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
-+
-+#else
-+
-+# define DWC_DEBUGPL(lvl, x...) do{}while(0)
-+# define DWC_DEBUGP(x...)
-+
-+# define CHK_DEBUG_LEVEL(level) (0)
-+
-+#endif /*DEBUG*/
-+#endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_driver.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_driver.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,1749 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
-+ * $Revision: #92 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ * The dwc_otg_driver module provides the initialization and cleanup entry
-+ * points for the DWC_otg driver. This module will be dynamically installed
-+ * after Linux is booted using the insmod command. When the module is
-+ * installed, the dwc_otg_driver_init function is called. When the module is
-+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
-+ *
-+ * This module also defines a data structure for the dwc_otg_driver, which is
-+ * used in conjunction with the standard ARM lm_device structure. These
-+ * structures allow the OTG driver to comply with the standard Linux driver
-+ * model in which devices and drivers are registered with a bus driver. This
-+ * has the benefit that Linux can expose attributes of the driver and device
-+ * in its special sysfs file system. Users can then read or write files in
-+ * this file system to perform diagnostics on the driver components or the
-+ * device.
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_os.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
-+#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
-+
-+bool microframe_schedule=true;
-+
-+static const char dwc_driver_name[] = "dwc_otg";
-+
-+
-+extern int pcd_init(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+extern int hcd_init(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+
-+extern int pcd_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *_dev
-+#endif
-+ );
-+
-+extern void hcd_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *_dev
-+#endif
-+ );
-+
-+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
-+
-+/*-------------------------------------------------------------------------*/
-+/* Encapsulate the module parameter settings */
-+
-+struct dwc_otg_driver_module_params {
-+ int32_t opt;
-+ int32_t otg_cap;
-+ int32_t dma_enable;
-+ int32_t dma_desc_enable;
-+ int32_t dma_burst_size;
-+ int32_t speed;
-+ int32_t host_support_fs_ls_low_power;
-+ int32_t host_ls_low_power_phy_clk;
-+ int32_t enable_dynamic_fifo;
-+ int32_t data_fifo_size;
-+ int32_t dev_rx_fifo_size;
-+ int32_t dev_nperio_tx_fifo_size;
-+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+ int32_t host_rx_fifo_size;
-+ int32_t host_nperio_tx_fifo_size;
-+ int32_t host_perio_tx_fifo_size;
-+ int32_t max_transfer_size;
-+ int32_t max_packet_count;
-+ int32_t host_channels;
-+ int32_t dev_endpoints;
-+ int32_t phy_type;
-+ int32_t phy_utmi_width;
-+ int32_t phy_ulpi_ddr;
-+ int32_t phy_ulpi_ext_vbus;
-+ int32_t i2c_enable;
-+ int32_t ulpi_fs_ls;
-+ int32_t ts_dline;
-+ int32_t en_multiple_tx_fifo;
-+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+ uint32_t thr_ctl;
-+ uint32_t tx_thr_length;
-+ uint32_t rx_thr_length;
-+ int32_t pti_enable;
-+ int32_t mpi_enable;
-+ int32_t lpm_enable;
-+ int32_t ic_usb_cap;
-+ int32_t ahb_thr_ratio;
-+ int32_t power_down;
-+ int32_t reload_ctl;
-+ int32_t dev_out_nak;
-+ int32_t cont_on_bna;
-+ int32_t ahb_single;
-+ int32_t otg_ver;
-+ int32_t adp_enable;
-+};
-+
-+static struct dwc_otg_driver_module_params dwc_otg_module_params = {
-+ .opt = -1,
-+ .otg_cap = -1,
-+ .dma_enable = -1,
-+ .dma_desc_enable = -1,
-+ .dma_burst_size = -1,
-+ .speed = -1,
-+ .host_support_fs_ls_low_power = -1,
-+ .host_ls_low_power_phy_clk = -1,
-+ .enable_dynamic_fifo = -1,
-+ .data_fifo_size = -1,
-+ .dev_rx_fifo_size = -1,
-+ .dev_nperio_tx_fifo_size = -1,
-+ .dev_perio_tx_fifo_size = {
-+ /* dev_perio_tx_fifo_size_1 */
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1
-+ /* 15 */
-+ },
-+ .host_rx_fifo_size = -1,
-+ .host_nperio_tx_fifo_size = -1,
-+ .host_perio_tx_fifo_size = -1,
-+ .max_transfer_size = -1,
-+ .max_packet_count = -1,
-+ .host_channels = -1,
-+ .dev_endpoints = -1,
-+ .phy_type = -1,
-+ .phy_utmi_width = -1,
-+ .phy_ulpi_ddr = -1,
-+ .phy_ulpi_ext_vbus = -1,
-+ .i2c_enable = -1,
-+ .ulpi_fs_ls = -1,
-+ .ts_dline = -1,
-+ .en_multiple_tx_fifo = -1,
-+ .dev_tx_fifo_size = {
-+ /* dev_tx_fifo_size */
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1
-+ /* 15 */
-+ },
-+ .thr_ctl = -1,
-+ .tx_thr_length = -1,
-+ .rx_thr_length = -1,
-+ .pti_enable = -1,
-+ .mpi_enable = -1,
-+ .lpm_enable = 0,
-+ .ic_usb_cap = -1,
-+ .ahb_thr_ratio = -1,
-+ .power_down = -1,
-+ .reload_ctl = -1,
-+ .dev_out_nak = -1,
-+ .cont_on_bna = -1,
-+ .ahb_single = -1,
-+ .otg_ver = -1,
-+ .adp_enable = -1,
-+};
-+
-+//Global variable to switch the fiq fix on or off
-+bool fiq_enable = 1;
-+// Global variable to enable the split transaction fix
-+bool fiq_fsm_enable = true;
-+//Bulk split-transaction NAK holdoff in microframes
-+uint16_t nak_holdoff = 8;
-+
-+unsigned short fiq_fsm_mask = 0x07;
-+
-+/**
-+ * This function shows the Driver Version.
-+ */
-+static ssize_t version_show(struct device_driver *dev, char *buf)
-+{
-+ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
-+ DWC_DRIVER_VERSION);
-+}
-+
-+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
-+
-+/**
-+ * Global Debug Level Mask.
-+ */
-+uint32_t g_dbg_lvl = 0; /* OFF */
-+
-+/**
-+ * This function shows the driver Debug Level.
-+ */
-+static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
-+{
-+ return sprintf(buf, "0x%0x\n", g_dbg_lvl);
-+}
-+
-+/**
-+ * This function stores the driver Debug Level.
-+ */
-+static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
-+ size_t count)
-+{
-+ g_dbg_lvl = simple_strtoul(buf, NULL, 16);
-+ return count;
-+}
-+
-+static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
-+ dbg_level_store);
-+
-+/**
-+ * This function is called during module intialization
-+ * to pass module parameters to the DWC_OTG CORE.
-+ */
-+static int set_parameters(dwc_otg_core_if_t * core_if)
-+{
-+ int retval = 0;
-+ int i;
-+
-+ if (dwc_otg_module_params.otg_cap != -1) {
-+ retval +=
-+ dwc_otg_set_param_otg_cap(core_if,
-+ dwc_otg_module_params.otg_cap);
-+ }
-+ if (dwc_otg_module_params.dma_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_dma_enable(core_if,
-+ dwc_otg_module_params.
-+ dma_enable);
-+ }
-+ if (dwc_otg_module_params.dma_desc_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_dma_desc_enable(core_if,
-+ dwc_otg_module_params.
-+ dma_desc_enable);
-+ }
-+ if (dwc_otg_module_params.opt != -1) {
-+ retval +=
-+ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
-+ }
-+ if (dwc_otg_module_params.dma_burst_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_dma_burst_size(core_if,
-+ dwc_otg_module_params.
-+ dma_burst_size);
-+ }
-+ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
-+ dwc_otg_module_params.
-+ host_support_fs_ls_low_power);
-+ }
-+ if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
-+ retval +=
-+ dwc_otg_set_param_enable_dynamic_fifo(core_if,
-+ dwc_otg_module_params.
-+ enable_dynamic_fifo);
-+ }
-+ if (dwc_otg_module_params.data_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_data_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ data_fifo_size);
-+ }
-+ if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_rx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_rx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_nperio_tx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.host_rx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_rx_fifo_size(core_if,
-+ dwc_otg_module_params.host_rx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ host_nperio_tx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ host_perio_tx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.max_transfer_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_max_transfer_size(core_if,
-+ dwc_otg_module_params.
-+ max_transfer_size);
-+ }
-+ if (dwc_otg_module_params.max_packet_count != -1) {
-+ retval +=
-+ dwc_otg_set_param_max_packet_count(core_if,
-+ dwc_otg_module_params.
-+ max_packet_count);
-+ }
-+ if (dwc_otg_module_params.host_channels != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_channels(core_if,
-+ dwc_otg_module_params.
-+ host_channels);
-+ }
-+ if (dwc_otg_module_params.dev_endpoints != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_endpoints(core_if,
-+ dwc_otg_module_params.
-+ dev_endpoints);
-+ }
-+ if (dwc_otg_module_params.phy_type != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_type(core_if,
-+ dwc_otg_module_params.phy_type);
-+ }
-+ if (dwc_otg_module_params.speed != -1) {
-+ retval +=
-+ dwc_otg_set_param_speed(core_if,
-+ dwc_otg_module_params.speed);
-+ }
-+ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
-+ dwc_otg_module_params.
-+ host_ls_low_power_phy_clk);
-+ }
-+ if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_ulpi_ddr(core_if,
-+ dwc_otg_module_params.
-+ phy_ulpi_ddr);
-+ }
-+ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
-+ dwc_otg_module_params.
-+ phy_ulpi_ext_vbus);
-+ }
-+ if (dwc_otg_module_params.phy_utmi_width != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_utmi_width(core_if,
-+ dwc_otg_module_params.
-+ phy_utmi_width);
-+ }
-+ if (dwc_otg_module_params.ulpi_fs_ls != -1) {
-+ retval +=
-+ dwc_otg_set_param_ulpi_fs_ls(core_if,
-+ dwc_otg_module_params.ulpi_fs_ls);
-+ }
-+ if (dwc_otg_module_params.ts_dline != -1) {
-+ retval +=
-+ dwc_otg_set_param_ts_dline(core_if,
-+ dwc_otg_module_params.ts_dline);
-+ }
-+ if (dwc_otg_module_params.i2c_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_i2c_enable(core_if,
-+ dwc_otg_module_params.
-+ i2c_enable);
-+ }
-+ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
-+ retval +=
-+ dwc_otg_set_param_en_multiple_tx_fifo(core_if,
-+ dwc_otg_module_params.
-+ en_multiple_tx_fifo);
-+ }
-+ for (i = 0; i < 15; i++) {
-+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_perio_tx_fifo_size
-+ [i], i);
-+ }
-+ }
-+
-+ for (i = 0; i < 15; i++) {
-+ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
-+ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_tx_fifo_size
-+ [i], i);
-+ }
-+ }
-+ if (dwc_otg_module_params.thr_ctl != -1) {
-+ retval +=
-+ dwc_otg_set_param_thr_ctl(core_if,
-+ dwc_otg_module_params.thr_ctl);
-+ }
-+ if (dwc_otg_module_params.mpi_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_mpi_enable(core_if,
-+ dwc_otg_module_params.
-+ mpi_enable);
-+ }
-+ if (dwc_otg_module_params.pti_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_pti_enable(core_if,
-+ dwc_otg_module_params.
-+ pti_enable);
-+ }
-+ if (dwc_otg_module_params.lpm_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_lpm_enable(core_if,
-+ dwc_otg_module_params.
-+ lpm_enable);
-+ }
-+ if (dwc_otg_module_params.ic_usb_cap != -1) {
-+ retval +=
-+ dwc_otg_set_param_ic_usb_cap(core_if,
-+ dwc_otg_module_params.
-+ ic_usb_cap);
-+ }
-+ if (dwc_otg_module_params.tx_thr_length != -1) {
-+ retval +=
-+ dwc_otg_set_param_tx_thr_length(core_if,
-+ dwc_otg_module_params.tx_thr_length);
-+ }
-+ if (dwc_otg_module_params.rx_thr_length != -1) {
-+ retval +=
-+ dwc_otg_set_param_rx_thr_length(core_if,
-+ dwc_otg_module_params.
-+ rx_thr_length);
-+ }
-+ if (dwc_otg_module_params.ahb_thr_ratio != -1) {
-+ retval +=
-+ dwc_otg_set_param_ahb_thr_ratio(core_if,
-+ dwc_otg_module_params.ahb_thr_ratio);
-+ }
-+ if (dwc_otg_module_params.power_down != -1) {
-+ retval +=
-+ dwc_otg_set_param_power_down(core_if,
-+ dwc_otg_module_params.power_down);
-+ }
-+ if (dwc_otg_module_params.reload_ctl != -1) {
-+ retval +=
-+ dwc_otg_set_param_reload_ctl(core_if,
-+ dwc_otg_module_params.reload_ctl);
-+ }
-+
-+ if (dwc_otg_module_params.dev_out_nak != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_out_nak(core_if,
-+ dwc_otg_module_params.dev_out_nak);
-+ }
-+
-+ if (dwc_otg_module_params.cont_on_bna != -1) {
-+ retval +=
-+ dwc_otg_set_param_cont_on_bna(core_if,
-+ dwc_otg_module_params.cont_on_bna);
-+ }
-+
-+ if (dwc_otg_module_params.ahb_single != -1) {
-+ retval +=
-+ dwc_otg_set_param_ahb_single(core_if,
-+ dwc_otg_module_params.ahb_single);
-+ }
-+
-+ if (dwc_otg_module_params.otg_ver != -1) {
-+ retval +=
-+ dwc_otg_set_param_otg_ver(core_if,
-+ dwc_otg_module_params.otg_ver);
-+ }
-+ if (dwc_otg_module_params.adp_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_adp_enable(core_if,
-+ dwc_otg_module_params.
-+ adp_enable);
-+ }
-+ return retval;
-+}
-+
-+/**
-+ * This function is the top level interrupt handler for the Common
-+ * (Device and host modes) interrupts.
-+ */
-+static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
-+{
-+ int32_t retval = IRQ_NONE;
-+
-+ retval = dwc_otg_handle_common_intr(dev);
-+ if (retval != 0) {
-+ S3C2410X_CLEAR_EINTPEND();
-+ }
-+ return IRQ_RETVAL(retval);
-+}
-+
-+/**
-+ * This function is called when a lm_device is unregistered with the
-+ * dwc_otg_driver. This happens, for example, when the rmmod command is
-+ * executed. The device may or may not be electrically present. If it is
-+ * present, the driver stops device processing. Any resources used on behalf
-+ * of this device are freed.
-+ *
-+ * @param _dev
-+ */
-+#ifdef LM_INTERFACE
-+#define REM_RETVAL(n)
-+static void dwc_otg_driver_remove( struct lm_device *_dev )
-+{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
-+#elif defined(PCI_INTERFACE)
-+#define REM_RETVAL(n)
-+static void dwc_otg_driver_remove( struct pci_dev *_dev )
-+{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
-+#elif defined(PLATFORM_INTERFACE)
-+#define REM_RETVAL(n) n
-+static int dwc_otg_driver_remove( struct platform_device *_dev )
-+{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
-+#endif
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
-+
-+ if (!otg_dev) {
-+ /* Memory allocation for the dwc_otg_device failed. */
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
-+ return REM_RETVAL(-ENOMEM);
-+ }
-+#ifndef DWC_DEVICE_ONLY
-+ if (otg_dev->hcd) {
-+ hcd_remove(_dev);
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
-+ return REM_RETVAL(-EINVAL);
-+ }
-+#endif
-+
-+#ifndef DWC_HOST_ONLY
-+ if (otg_dev->pcd) {
-+ pcd_remove(_dev);
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
-+ return REM_RETVAL(-EINVAL);
-+ }
-+#endif
-+ /*
-+ * Free the IRQ
-+ */
-+ if (otg_dev->common_irq_installed) {
-+#ifdef PLATFORM_INTERFACE
-+ free_irq(platform_get_irq(_dev, 0), otg_dev);
-+#else
-+ free_irq(_dev->irq, otg_dev);
-+#endif
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
-+ return REM_RETVAL(-ENXIO);
-+ }
-+
-+ if (otg_dev->core_if) {
-+ dwc_otg_cil_remove(otg_dev->core_if);
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
-+ return REM_RETVAL(-ENXIO);
-+ }
-+
-+ /*
-+ * Remove the device attributes
-+ */
-+ dwc_otg_attr_remove(_dev);
-+
-+ /*
-+ * Return the memory.
-+ */
-+ if (otg_dev->os_dep.base) {
-+ iounmap(otg_dev->os_dep.base);
-+ }
-+ DWC_FREE(otg_dev);
-+
-+ /*
-+ * Clear the drvdata pointer.
-+ */
-+#ifdef LM_INTERFACE
-+ lm_set_drvdata(_dev, 0);
-+#elif defined(PCI_INTERFACE)
-+ release_mem_region(otg_dev->os_dep.rsrc_start,
-+ otg_dev->os_dep.rsrc_len);
-+ pci_set_drvdata(_dev, 0);
-+#elif defined(PLATFORM_INTERFACE)
-+ platform_set_drvdata(_dev, 0);
-+#endif
-+ return REM_RETVAL(0);
-+}
-+
-+/**
-+ * This function is called when an lm_device is bound to a
-+ * dwc_otg_driver. It creates the driver components required to
-+ * control the device (CIL, HCD, and PCD) and it initializes the
-+ * device. The driver components are stored in a dwc_otg_device
-+ * structure. A reference to the dwc_otg_device is saved in the
-+ * lm_device. This allows the driver to access the dwc_otg_device
-+ * structure on subsequent calls to driver methods for this device.
-+ *
-+ * @param _dev Bus device
-+ */
-+static int dwc_otg_driver_probe(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev,
-+ const struct pci_device_id *id
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *_dev
-+#endif
-+ )
-+{
-+ int retval = 0;
-+ dwc_otg_device_t *dwc_otg_device;
-+ int devirq;
-+
-+ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
-+#ifdef LM_INTERFACE
-+ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
-+#elif defined(PCI_INTERFACE)
-+ if (!id) {
-+ DWC_ERROR("Invalid pci_device_id %p", id);
-+ return -EINVAL;
-+ }
-+
-+ if (!_dev || (pci_enable_device(_dev) < 0)) {
-+ DWC_ERROR("Invalid pci_device %p", _dev);
-+ return -ENODEV;
-+ }
-+ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
-+ /* other stuff needed as well? */
-+
-+#elif defined(PLATFORM_INTERFACE)
-+ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
-+ (unsigned)_dev->resource->start,
-+ (unsigned)(_dev->resource->end - _dev->resource->start));
-+#endif
-+
-+ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
-+
-+ if (!dwc_otg_device) {
-+ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
-+ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
-+
-+ /*
-+ * Map the DWC_otg Core memory into virtual address space.
-+ */
-+#ifdef LM_INTERFACE
-+ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
-+
-+ if (!dwc_otg_device->os_dep.base) {
-+ dev_err(&_dev->dev, "ioremap() failed\n");
-+ DWC_FREE(dwc_otg_device);
-+ return -ENOMEM;
-+ }
-+ dev_dbg(&_dev->dev, "base=0x%08x\n",
-+ (unsigned)dwc_otg_device->os_dep.base);
-+#elif defined(PCI_INTERFACE)
-+ _dev->current_state = PCI_D0;
-+ _dev->dev.power.power_state = PMSG_ON;
-+
-+ if (!_dev->irq) {
-+ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
-+ pci_name(_dev));
-+ iounmap(dwc_otg_device->os_dep.base);
-+ DWC_FREE(dwc_otg_device);
-+ return -ENODEV;
-+ }
-+
-+ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
-+ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
-+ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
-+ (unsigned)dwc_otg_device->os_dep.rsrc_start,
-+ (unsigned)dwc_otg_device->os_dep.rsrc_len);
-+ if (!request_mem_region
-+ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
-+ "dwc_otg")) {
-+ dev_dbg(&_dev->dev, "error requesting memory\n");
-+ iounmap(dwc_otg_device->os_dep.base);
-+ DWC_FREE(dwc_otg_device);
-+ return -EFAULT;
-+ }
-+
-+ dwc_otg_device->os_dep.base =
-+ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
-+ dwc_otg_device->os_dep.rsrc_len);
-+ if (dwc_otg_device->os_dep.base == NULL) {
-+ dev_dbg(&_dev->dev, "error mapping memory\n");
-+ release_mem_region(dwc_otg_device->os_dep.rsrc_start,
-+ dwc_otg_device->os_dep.rsrc_len);
-+ iounmap(dwc_otg_device->os_dep.base);
-+ DWC_FREE(dwc_otg_device);
-+ return -EFAULT;
-+ }
-+ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
-+ dwc_otg_device->os_dep.base);
-+ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
-+ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
-+ dwc_otg_device->os_dep.base);
-+ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
-+ (unsigned)dwc_otg_device->os_dep.rsrc_start,
-+ dwc_otg_device->os_dep.base);
-+
-+ pci_set_master(_dev);
-+ pci_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
-+ _dev->resource->start,
-+ _dev->resource->end - _dev->resource->start + 1);
-+#if 1
-+ if (!request_mem_region(_dev->resource[0].start,
-+ _dev->resource[0].end - _dev->resource[0].start + 1,
-+ "dwc_otg")) {
-+ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
-+ retval = -EFAULT;
-+ goto fail;
-+ }
-+
-+ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
-+ _dev->resource[0].end -
-+ _dev->resource[0].start+1);
-+ if (fiq_enable)
-+ {
-+ if (!request_mem_region(_dev->resource[1].start,
-+ _dev->resource[1].end - _dev->resource[1].start + 1,
-+ "dwc_otg")) {
-+ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
-+ retval = -EFAULT;
-+ goto fail;
-+ }
-+
-+ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
-+ _dev->resource[1].end -
-+ _dev->resource[1].start + 1);
-+ }
-+
-+#else
-+ {
-+ struct map_desc desc = {
-+ .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
-+ .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
-+ .length = SZ_128K,
-+ .type = MT_DEVICE
-+ };
-+ iotable_init(&desc, 1);
-+ dwc_otg_device->os_dep.base = (void *)desc.virtual;
-+ }
-+#endif
-+ if (!dwc_otg_device->os_dep.base) {
-+ dev_err(&_dev->dev, "ioremap() failed\n");
-+ retval = -ENOMEM;
-+ goto fail;
-+ }
-+ dev_dbg(&_dev->dev, "base=0x%08x\n",
-+ (unsigned)dwc_otg_device->os_dep.base);
-+#endif
-+
-+ /*
-+ * Initialize driver data to point to the global DWC_otg
-+ * Device structure.
-+ */
-+#ifdef LM_INTERFACE
-+ lm_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+ platform_set_drvdata(_dev, dwc_otg_device);
-+#endif
-+ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
-+
-+ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
-+ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
-+ dwc_otg_device, dwc_otg_device->core_if);//GRAYG
-+
-+ if (!dwc_otg_device->core_if) {
-+ dev_err(&_dev->dev, "CIL initialization failed!\n");
-+ retval = -ENOMEM;
-+ goto fail;
-+ }
-+
-+ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
-+ /*
-+ * Attempt to ensure this device is really a DWC_otg Controller.
-+ * Read and verify the SNPSID register contents. The value should be
-+ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
-+ * as in "OTG version 2.XX" or "OTG version 3.XX".
-+ */
-+
-+ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
-+ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
-+ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
-+ dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
-+ retval = -EINVAL;
-+ goto fail;
-+ }
-+
-+ /*
-+ * Validate parameter values.
-+ */
-+ dev_dbg(&_dev->dev, "Calling set_parameters\n");
-+ if (set_parameters(dwc_otg_device->core_if)) {
-+ retval = -EINVAL;
-+ goto fail;
-+ }
-+
-+ /*
-+ * Create Device Attributes in sysfs
-+ */
-+ dev_dbg(&_dev->dev, "Calling attr_create\n");
-+ dwc_otg_attr_create(_dev);
-+
-+ /*
-+ * Disable the global interrupt until all the interrupt
-+ * handlers are installed.
-+ */
-+ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
-+ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
-+
-+ /*
-+ * Install the interrupt handler for the common interrupts before
-+ * enabling common interrupts in core_init below.
-+ */
-+
-+#if defined(PLATFORM_INTERFACE)
-+ devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
-+#else
-+ devirq = _dev->irq;
-+#endif
-+ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
-+ devirq);
-+ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
-+ retval = request_irq(devirq, dwc_otg_common_irq,
-+ IRQF_SHARED,
-+ "dwc_otg", dwc_otg_device);
-+ if (retval) {
-+ DWC_ERROR("request of irq%d failed\n", devirq);
-+ retval = -EBUSY;
-+ goto fail;
-+ } else {
-+ dwc_otg_device->common_irq_installed = 1;
-+ }
-+
-+#ifndef IRQF_TRIGGER_LOW
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+ dev_dbg(&_dev->dev, "Calling set_irq_type\n");
-+ set_irq_type(devirq,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
-+ IRQT_LOW
-+#else
-+ IRQ_TYPE_LEVEL_LOW
-+#endif
-+ );
-+#endif
-+#endif /*IRQF_TRIGGER_LOW*/
-+
-+ /*
-+ * Initialize the DWC_otg core.
-+ */
-+ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
-+ dwc_otg_core_init(dwc_otg_device->core_if);
-+
-+#ifndef DWC_HOST_ONLY
-+ /*
-+ * Initialize the PCD
-+ */
-+ dev_dbg(&_dev->dev, "Calling pcd_init\n");
-+ retval = pcd_init(_dev);
-+ if (retval != 0) {
-+ DWC_ERROR("pcd_init failed\n");
-+ dwc_otg_device->pcd = NULL;
-+ goto fail;
-+ }
-+#endif
-+#ifndef DWC_DEVICE_ONLY
-+ /*
-+ * Initialize the HCD
-+ */
-+ dev_dbg(&_dev->dev, "Calling hcd_init\n");
-+ retval = hcd_init(_dev);
-+ if (retval != 0) {
-+ DWC_ERROR("hcd_init failed\n");
-+ dwc_otg_device->hcd = NULL;
-+ goto fail;
-+ }
-+#endif
-+ /* Recover from drvdata having been overwritten by hcd_init() */
-+#ifdef LM_INTERFACE
-+ lm_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+ platform_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PCI_INTERFACE)
-+ pci_set_drvdata(_dev, dwc_otg_device);
-+ dwc_otg_device->os_dep.pcidev = _dev;
-+#endif
-+
-+ /*
-+ * Enable the global interrupt after all the interrupt
-+ * handlers are installed if there is no ADP support else
-+ * perform initial actions required for Internal ADP logic.
-+ */
-+ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
-+ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
-+ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
-+ dev_dbg(&_dev->dev, "Done\n");
-+ } else
-+ dwc_otg_adp_start(dwc_otg_device->core_if,
-+ dwc_otg_is_host_mode(dwc_otg_device->core_if));
-+
-+ return 0;
-+
-+fail:
-+ dwc_otg_driver_remove(_dev);
-+ return retval;
-+}
-+
-+/**
-+ * This structure defines the methods to be called by a bus driver
-+ * during the lifecycle of a device on that bus. Both drivers and
-+ * devices are registered with a bus driver. The bus driver matches
-+ * devices to drivers based on information in the device and driver
-+ * structures.
-+ *
-+ * The probe function is called when the bus driver matches a device
-+ * to this driver. The remove function is called when a device is
-+ * unregistered with the bus driver.
-+ */
-+#ifdef LM_INTERFACE
-+static struct lm_driver dwc_otg_driver = {
-+ .drv = {.name = (char *)dwc_driver_name,},
-+ .probe = dwc_otg_driver_probe,
-+ .remove = dwc_otg_driver_remove,
-+ // 'suspend' and 'resume' absent
-+};
-+#elif defined(PCI_INTERFACE)
-+static const struct pci_device_id pci_ids[] = { {
-+ PCI_DEVICE(0x16c3, 0xabcd),
-+ .driver_data =
-+ (unsigned long)0xdeadbeef,
-+ }, { /* end: all zeroes */ }
-+};
-+
-+MODULE_DEVICE_TABLE(pci, pci_ids);
-+
-+/* pci driver glue; this is a "new style" PCI driver module */
-+static struct pci_driver dwc_otg_driver = {
-+ .name = "dwc_otg",
-+ .id_table = pci_ids,
-+
-+ .probe = dwc_otg_driver_probe,
-+ .remove = dwc_otg_driver_remove,
-+
-+ .driver = {
-+ .name = (char *)dwc_driver_name,
-+ },
-+};
-+#elif defined(PLATFORM_INTERFACE)
-+static struct platform_device_id platform_ids[] = {
-+ {
-+ .name = "bcm2708_usb",
-+ .driver_data = (kernel_ulong_t) 0xdeadbeef,
-+ },
-+ { /* end: all zeroes */ }
-+};
-+MODULE_DEVICE_TABLE(platform, platform_ids);
-+
-+static struct platform_driver dwc_otg_driver = {
-+ .driver = {
-+ .name = (char *)dwc_driver_name,
-+ },
-+ .id_table = platform_ids,
-+
-+ .probe = dwc_otg_driver_probe,
-+ .remove = dwc_otg_driver_remove,
-+ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
-+};
-+#endif
-+
-+/**
-+ * This function is called when the dwc_otg_driver is installed with the
-+ * insmod command. It registers the dwc_otg_driver structure with the
-+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
-+ * to be called. In addition, the bus driver will automatically expose
-+ * attributes defined for the device and driver in the special sysfs file
-+ * system.
-+ *
-+ * @return
-+ */
-+static int __init dwc_otg_driver_init(void)
-+{
-+ int retval = 0;
-+ int error;
-+ struct device_driver *drv;
-+
-+ if(fiq_fsm_enable && !fiq_enable) {
-+ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
-+ fiq_enable = 1;
-+ }
-+
-+ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
-+ DWC_DRIVER_VERSION,
-+#ifdef LM_INTERFACE
-+ "logicmodule");
-+ retval = lm_driver_register(&dwc_otg_driver);
-+ drv = &dwc_otg_driver.drv;
-+#elif defined(PCI_INTERFACE)
-+ "pci");
-+ retval = pci_register_driver(&dwc_otg_driver);
-+ drv = &dwc_otg_driver.driver;
-+#elif defined(PLATFORM_INTERFACE)
-+ "platform");
-+ retval = platform_driver_register(&dwc_otg_driver);
-+ drv = &dwc_otg_driver.driver;
-+#endif
-+ if (retval < 0) {
-+ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
-+ return retval;
-+ }
-+ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
-+ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
-+ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
-+
-+ error = driver_create_file(drv, &driver_attr_version);
-+#ifdef DEBUG
-+ error = driver_create_file(drv, &driver_attr_debuglevel);
-+#endif
-+ return retval;
-+}
-+
-+module_init(dwc_otg_driver_init);
-+
-+/**
-+ * This function is called when the driver is removed from the kernel
-+ * with the rmmod command. The driver unregisters itself with its bus
-+ * driver.
-+ *
-+ */
-+static void __exit dwc_otg_driver_cleanup(void)
-+{
-+ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
-+
-+#ifdef LM_INTERFACE
-+ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
-+ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
-+ lm_driver_unregister(&dwc_otg_driver);
-+#elif defined(PCI_INTERFACE)
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
-+ pci_unregister_driver(&dwc_otg_driver);
-+#elif defined(PLATFORM_INTERFACE)
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
-+ platform_driver_unregister(&dwc_otg_driver);
-+#endif
-+
-+ printk(KERN_INFO "%s module removed\n", dwc_driver_name);
-+}
-+
-+module_exit(dwc_otg_driver_cleanup);
-+
-+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
-+MODULE_AUTHOR("Synopsys Inc.");
-+MODULE_LICENSE("GPL");
-+
-+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
-+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
-+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
-+MODULE_PARM_DESC(opt, "OPT Mode");
-+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
-+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
-+
-+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
-+ 0444);
-+MODULE_PARM_DESC(dma_desc_enable,
-+ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
-+
-+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
-+ 0444);
-+MODULE_PARM_DESC(dma_burst_size,
-+ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
-+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
-+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
-+module_param_named(host_support_fs_ls_low_power,
-+ dwc_otg_module_params.host_support_fs_ls_low_power, int,
-+ 0444);
-+MODULE_PARM_DESC(host_support_fs_ls_low_power,
-+ "Support Low Power w/FS or LS 0=Support 1=Don't Support");
-+module_param_named(host_ls_low_power_phy_clk,
-+ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
-+MODULE_PARM_DESC(host_ls_low_power_phy_clk,
-+ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
-+module_param_named(enable_dynamic_fifo,
-+ dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
-+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
-+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
-+ 0444);
-+MODULE_PARM_DESC(data_fifo_size,
-+ "Total number of words in the data FIFO memory 32-32768");
-+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
-+ int, 0444);
-+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
-+module_param_named(dev_nperio_tx_fifo_size,
-+ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
-+ "Number of words in the non-periodic Tx FIFO 16-32768");
-+module_param_named(dev_perio_tx_fifo_size_1,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_2,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_3,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_4,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_5,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_6,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_7,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_8,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_9,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_10,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_11,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_12,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_13,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_14,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_15,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
-+ int, 0444);
-+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
-+module_param_named(host_nperio_tx_fifo_size,
-+ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(host_nperio_tx_fifo_size,
-+ "Number of words in the non-periodic Tx FIFO 16-32768");
-+module_param_named(host_perio_tx_fifo_size,
-+ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(host_perio_tx_fifo_size,
-+ "Number of words in the host periodic Tx FIFO 16-32768");
-+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
-+ int, 0444);
-+/** @todo Set the max to 512K, modify checks */
-+MODULE_PARM_DESC(max_transfer_size,
-+ "The maximum transfer size supported in bytes 2047-65535");
-+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
-+ int, 0444);
-+MODULE_PARM_DESC(max_packet_count,
-+ "The maximum number of packets in a transfer 15-511");
-+module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
-+ 0444);
-+MODULE_PARM_DESC(host_channels,
-+ "The number of host channel registers to use 1-16");
-+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
-+ 0444);
-+MODULE_PARM_DESC(dev_endpoints,
-+ "The number of endpoints in addition to EP0 available for device mode 1-15");
-+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
-+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
-+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
-+ 0444);
-+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
-+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
-+MODULE_PARM_DESC(phy_ulpi_ddr,
-+ "ULPI at double or single data rate 0=Single 1=Double");
-+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
-+ int, 0444);
-+MODULE_PARM_DESC(phy_ulpi_ext_vbus,
-+ "ULPI PHY using internal or external vbus 0=Internal");
-+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
-+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
-+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
-+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
-+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
-+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
-+module_param_named(debug, g_dbg_lvl, int, 0444);
-+MODULE_PARM_DESC(debug, "");
-+
-+module_param_named(en_multiple_tx_fifo,
-+ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
-+MODULE_PARM_DESC(en_multiple_tx_fifo,
-+ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
-+module_param_named(dev_tx_fifo_size_1,
-+ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_2,
-+ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_3,
-+ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_4,
-+ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_5,
-+ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_6,
-+ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_7,
-+ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_8,
-+ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_9,
-+ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_10,
-+ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_11,
-+ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_12,
-+ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_13,
-+ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_14,
-+ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_15,
-+ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
-+
-+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
-+MODULE_PARM_DESC(thr_ctl,
-+ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
-+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
-+ 0444);
-+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
-+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
-+ 0444);
-+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
-+
-+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
-+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
-+module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
-+MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
-+module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
-+MODULE_PARM_DESC(ic_usb_cap,
-+ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
-+module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
-+ 0444);
-+MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
-+module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
-+MODULE_PARM_DESC(power_down, "Power Down Mode");
-+module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
-+MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
-+module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
-+MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
-+module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
-+MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
-+module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
-+MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
-+module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
-+MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
-+module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
-+MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
-+module_param(microframe_schedule, bool, 0444);
-+MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
-+
-+module_param(fiq_enable, bool, 0444);
-+MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
-+module_param(nak_holdoff, ushort, 0644);
-+MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
-+module_param(fiq_fsm_enable, bool, 0444);
-+MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
-+module_param(fiq_fsm_mask, ushort, 0444);
-+MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
-+ "Bit 0 : Non-periodic split transactions\n"
-+ "Bit 1 : Periodic split transactions\n"
-+ "Bit 2 : High-speed multi-transfer isochronous\n"
-+ "All other bits should be set 0.");
-+
-+
-+/** @page "Module Parameters"
-+ *
-+ * The following parameters may be specified when starting the module.
-+ * These parameters define how the DWC_otg controller should be
-+ * configured. Parameter values are passed to the CIL initialization
-+ * function dwc_otg_cil_init
-+ *
-+ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
-+ *
-+
-+ <table>
-+ <tr><td>Parameter Name</td><td>Meaning</td></tr>
-+
-+ <tr>
-+ <td>otg_cap</td>
-+ <td>Specifies the OTG capabilities. The driver will automatically detect the
-+ value for this parameter if none is specified.
-+ - 0: HNP and SRP capable (default, if available)
-+ - 1: SRP Only capable
-+ - 2: No HNP/SRP capable
-+ </td></tr>
-+
-+ <tr>
-+ <td>dma_enable</td>
-+ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Slave
-+ - 1: DMA (default, if available)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dma_burst_size</td>
-+ <td>The DMA Burst size (applicable only for External DMA Mode).
-+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ </td></tr>
-+
-+ <tr>
-+ <td>speed</td>
-+ <td>Specifies the maximum speed of operation in host and device mode. The
-+ actual speed depends on the speed of the attached device and the value of
-+ phy_type.
-+ - 0: High Speed (default)
-+ - 1: Full Speed
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_support_fs_ls_low_power</td>
-+ <td>Specifies whether low power mode is supported when attached to a Full
-+ Speed or Low Speed device in host mode.
-+ - 0: Don't support low power mode (default)
-+ - 1: Support low power mode
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_ls_low_power_phy_clk</td>
-+ <td>Specifies the PHY clock rate in low power mode when connected to a Low
-+ Speed device in host mode. This parameter is applicable only if
-+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
-+ - 0: 48 MHz (default)
-+ - 1: 6 MHz
-+ </td></tr>
-+
-+ <tr>
-+ <td>enable_dynamic_fifo</td>
-+ <td> Specifies whether FIFOs may be resized by the driver software.
-+ - 0: Use cC FIFO size parameters
-+ - 1: Allow dynamic FIFO sizing (default)
-+ </td></tr>
-+
-+ <tr>
-+ <td>data_fifo_size</td>
-+ <td>Total number of 4-byte words in the data FIFO memory. This memory
-+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
-+ - Values: 32 to 32768 (default 8192)
-+
-+ Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_rx_fifo_size</td>
-+ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ FIFO sizing is enabled.
-+ - Values: 16 to 32768 (default 1064)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_nperio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
-+ dynamic FIFO sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
-+ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
-+ when dynamic FIFO sizing is enabled.
-+ - Values: 4 to 768 (default 256)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_rx_fifo_size</td>
-+ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
-+ sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_nperio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
-+ dynamic FIFO sizing is enabled in the core.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_perio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
-+ sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>max_transfer_size</td>
-+ <td>The maximum transfer size supported in bytes.
-+ - Values: 2047 to 65,535 (default 65,535)
-+ </td></tr>
-+
-+ <tr>
-+ <td>max_packet_count</td>
-+ <td>The maximum number of packets in a transfer.
-+ - Values: 15 to 511 (default 511)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_channels</td>
-+ <td>The number of host channel registers to use.
-+ - Values: 1 to 16 (default 12)
-+
-+ Note: The FPGA configuration supports a maximum of 12 host channels.
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_endpoints</td>
-+ <td>The number of endpoints in addition to EP0 available for device mode
-+ operations.
-+ - Values: 1 to 15 (default 6 IN and OUT)
-+
-+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
-+ addition to EP0.
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_type</td>
-+ <td>Specifies the type of PHY interface to use. By default, the driver will
-+ automatically detect the phy_type.
-+ - 0: Full Speed
-+ - 1: UTMI+ (default, if available)
-+ - 2: ULPI
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_utmi_width</td>
-+ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
-+ phy_type of UTMI+. Also, this parameter is applicable only if the
-+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
-+ core has been configured to work at either data path width.
-+ - Values: 8 or 16 bits (default 16)
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_ulpi_ddr</td>
-+ <td>Specifies whether the ULPI operates at double or single data rate. This
-+ parameter is only applicable if phy_type is ULPI.
-+ - 0: single data rate ULPI interface with 8 bit wide data bus (default)
-+ - 1: double data rate ULPI interface with 4 bit wide data bus
-+ </td></tr>
-+
-+ <tr>
-+ <td>i2c_enable</td>
-+ <td>Specifies whether to use the I2C interface for full speed PHY. This
-+ parameter is only applicable if PHY_TYPE is FS.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>ulpi_fs_ls</td>
-+ <td>Specifies whether to use ULPI FS/LS mode only.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>ts_dline</td>
-+ <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>en_multiple_tx_fifo</td>
-+ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Disabled
-+ - 1: Enabled (default, if available)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
-+ <td>Number of 4-byte words in each of the Tx FIFOs in device mode
-+ when dynamic FIFO sizing is enabled.
-+ - Values: 4 to 768 (default 256)
-+ </td></tr>
-+
-+ <tr>
-+ <td>tx_thr_length</td>
-+ <td>Transmit Threshold length in 32 bit double words
-+ - Values: 8 to 128 (default 64)
-+ </td></tr>
-+
-+ <tr>
-+ <td>rx_thr_length</td>
-+ <td>Receive Threshold length in 32 bit double words
-+ - Values: 8 to 128 (default 64)
-+ </td></tr>
-+
-+<tr>
-+ <td>thr_ctl</td>
-+ <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
-+ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
-+ Rx transfers accordingly.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - Values: 0 to 7 (default 0)
-+ Bit values indicate:
-+ - 0: Thresholding disabled
-+ - 1: Thresholding enabled
-+ </td></tr>
-+
-+<tr>
-+ <td>dma_desc_enable</td>
-+ <td>Specifies whether to enable Descriptor DMA mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Descriptor DMA disabled
-+ - 1: Descriptor DMA (default, if available)
-+ </td></tr>
-+
-+<tr>
-+ <td>mpi_enable</td>
-+ <td>Specifies whether to enable MPI enhancement mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: MPI disabled (default)
-+ - 1: MPI enable
-+ </td></tr>
-+
-+<tr>
-+ <td>pti_enable</td>
-+ <td>Specifies whether to enable PTI enhancement support.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: PTI disabled (default)
-+ - 1: PTI enable
-+ </td></tr>
-+
-+<tr>
-+ <td>lpm_enable</td>
-+ <td>Specifies whether to enable LPM support.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: LPM disabled
-+ - 1: LPM enable (default, if available)
-+ </td></tr>
-+
-+<tr>
-+ <td>ic_usb_cap</td>
-+ <td>Specifies whether to enable IC_USB capability.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: IC_USB disabled (default, if available)
-+ - 1: IC_USB enable
-+ </td></tr>
-+
-+<tr>
-+ <td>ahb_thr_ratio</td>
-+ <td>Specifies AHB Threshold ratio.
-+ - Values: 0 to 3 (default 0)
-+ </td></tr>
-+
-+<tr>
-+ <td>power_down</td>
-+ <td>Specifies Power Down(Hibernation) Mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Power Down disabled (default)
-+ - 2: Power Down enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>reload_ctl</td>
-+ <td>Specifies whether dynamic reloading of the HFIR register is allowed during
-+ run time. The driver will automatically detect the value for this parameter if
-+ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
-+ the core might misbehave.
-+ - 0: Reload Control disabled (default)
-+ - 1: Reload Control enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_out_nak</td>
-+ <td>Specifies whether Device OUT NAK enhancement enabled or no.
-+ The driver will automatically detect the value for this parameter if
-+ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
-+ - 0: The core does not set NAK after Bulk OUT transfer complete (default)
-+ - 1: The core sets NAK after Bulk OUT transfer complete
-+ </td></tr>
-+
-+ <tr>
-+ <td>cont_on_bna</td>
-+ <td>Specifies whether Enable Continue on BNA enabled or no.
-+ After receiving BNA interrupt the core disables the endpoint,when the
-+ endpoint is re-enabled by the application the
-+ - 0: Core starts processing from the DOEPDMA descriptor (default)
-+ - 1: Core starts processing from the descriptor which received the BNA.
-+ This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
-+ </td></tr>
-+
-+ <tr>
-+ <td>ahb_single</td>
-+ <td>This bit when programmed supports SINGLE transfers for remainder data
-+ in a transfer for DMA mode of operation.
-+ - 0: The remainder data will be sent using INCR burst size (default)
-+ - 1: The remainder data will be sent using SINGLE burst size.
-+ </td></tr>
-+
-+<tr>
-+ <td>adp_enable</td>
-+ <td>Specifies whether ADP feature is enabled.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: ADP feature disabled (default)
-+ - 1: ADP feature enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>otg_ver</td>
-+ <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
-+ USB OTG device.
-+ - 0: OTG 2.0 support disabled (default)
-+ - 1: OTG 2.0 support enabled
-+ </td></tr>
-+
-+*/
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_driver.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_driver.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,86 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
-+ * $Revision: #19 $
-+ * $Date: 2010/11/15 $
-+ * $Change: 1627671 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_DRIVER_H__
-+#define __DWC_OTG_DRIVER_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux driver.
-+ */
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_otg_core_if.h"
-+
-+/* Type declarations */
-+struct dwc_otg_pcd;
-+struct dwc_otg_hcd;
-+
-+/**
-+ * This structure is a wrapper that encapsulates the driver components used to
-+ * manage a single DWC_otg controller.
-+ */
-+typedef struct dwc_otg_device {
-+ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
-+ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
-+ * require this. */
-+ struct os_dependent os_dep;
-+
-+ /** Pointer to the core interface structure. */
-+ dwc_otg_core_if_t *core_if;
-+
-+ /** Pointer to the PCD structure. */
-+ struct dwc_otg_pcd *pcd;
-+
-+ /** Pointer to the HCD structure. */
-+ struct dwc_otg_hcd *hcd;
-+
-+ /** Flag to indicate whether the common IRQ handler is installed. */
-+ uint8_t common_irq_installed;
-+
-+} dwc_otg_device_t;
-+
-+/*We must clear S3C24XX_EINTPEND external interrupt register
-+ * because after clearing in this register trigerred IRQ from
-+ * H/W core in kernel interrupt can be occured again before OTG
-+ * handlers clear all IRQ sources of Core registers because of
-+ * timing latencies and Low Level IRQ Type.
-+ */
-+#ifdef CONFIG_MACH_IPMATE
-+#define S3C2410X_CLEAR_EINTPEND() \
-+do { \
-+ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
-+} while (0)
-+#else
-+#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
-+#endif
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,1294 @@
-+/*
-+ * dwc_otg_fiq_fsm.c - The finite state machine FIQ
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Raspberry Pi nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This FIQ implements functionality that performs split transactions on
-+ * the dwc_otg hardware without any outside intervention. A split transaction
-+ * is "queued" by nominating a specific host channel to perform the entirety
-+ * of a split transaction. This FIQ will then perform the microframe-precise
-+ * scheduling required in each phase of the transaction until completion.
-+ *
-+ * The FIQ functionality is glued into the Synopsys driver via the entry point
-+ * in the FSM enqueue function, and at the exit point in handling a HC interrupt
-+ * for a FSM-enabled channel.
-+ *
-+ * NB: Large parts of this implementation have architecture-specific code.
-+ * For porting this functionality to other ARM machines, the minimum is required:
-+ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
-+ * to the FIQ
-+ * - A method of forcing a software generated interrupt from FIQ mode that then
-+ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
-+ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
-+ * processor core - there is no locking between the FIQ and IRQ (aside from
-+ * local_fiq_disable)
-+ *
-+ */
-+
-+#include "dwc_otg_fiq_fsm.h"
-+
-+
-+char buffer[1000*16];
-+int wptr;
-+void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
-+{
-+ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
-+ va_list args;
-+ char text[17];
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
-+
-+ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
-+ {
-+ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
-+ va_start(args, fmt);
-+ vsnprintf(text+8, 9, fmt, args);
-+ va_end(args);
-+
-+ memcpy(buffer + wptr, text, 16);
-+ wptr = (wptr + 16) % sizeof(buffer);
-+ }
-+}
-+
-+/**
-+ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
-+ * @channel: channel to re-enable
-+ */
-+static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
-+{
-+ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
-+
-+ hcchar.b.chen = 0;
-+ if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+ /* Hardware bug workaround: update the ssplit index */
-+ if (st->channel[n].hcsplt_copy.b.spltena)
-+ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
-+
-+ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
-+ }
-+
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
-+ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ hcchar.b.chen = 1;
-+
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
-+ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
-+}
-+
-+/**
-+ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
-+ * @st: Pointer to the channel's state
-+ * @n : channel number
-+ *
-+ * Change host channel registers to perform a complete-split transaction. Being mindful of the
-+ * endpoint direction, set control regs up correctly.
-+ */
-+static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
-+{
-+ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
-+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+
-+ hcsplt.b.compsplt = 1;
-+ if (st->channel[n].hcchar_copy.b.epdir == 1) {
-+ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
-+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
-+ } else {
-+ // If OUT, the CSPLIT result contains handshake only.
-+ hctsiz.b.xfersize = 0;
-+ }
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+ mb();
-+}
-+
-+static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
-+{
-+ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
-+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+
-+ if (st->channel[n].hcchar_copy.b.epdir == 0) {
-+ return st->channel[n].hctsiz_copy.b.xfersize;
-+ } else {
-+ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
-+ }
-+
-+}
-+
-+
-+/**
-+ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
-+ *
-+ * Of use only for IN periodic transfers.
-+ */
-+static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
-+{
-+ hcdma_data_t hcdma;
-+ int i = st->channel[n].dma_info.index;
-+ int len;
-+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
-+
-+ len = fiq_get_xfer_len(st, n);
-+ fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
-+ st->channel[n].dma_info.slot_len[i] = len;
-+ i++;
-+ if (i > 6)
-+ BUG();
-+
-+ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
-+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+ st->channel[n].dma_info.index = i;
-+ return 0;
-+}
-+
-+/**
-+ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
-+ */
-+static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
-+{
-+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
-+ hctsiz.b.pktcnt = 1;
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+}
-+
-+/**
-+ * fiq_iso_out_advance() - update DMA address and split position bits
-+ * for isochronous OUT transactions.
-+ *
-+ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
-+ * Split-BEGIN states are not handled - this is done when the transaction was queued.
-+ *
-+ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
-+ */
-+static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
-+{
-+ hcsplt_data_t hcsplt;
-+ hctsiz_data_t hctsiz;
-+ hcdma_data_t hcdma;
-+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
-+ int last = 0;
-+ int i = st->channel[n].dma_info.index;
-+
-+ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
-+ i++;
-+ if (i == 4)
-+ last = 1;
-+ if (st->channel[n].dma_info.slot_len[i+1] == 255)
-+ last = 1;
-+
-+ /* New DMA address - address of bounce buffer referred to in index */
-+ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
-+ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
-+ //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
-+ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
-+ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
-+ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
-+ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
-+ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
-+ /* Set up new packet length */
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
-+ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
-+
-+ st->channel[n].dma_info.index++;
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+ return last;
-+}
-+
-+/**
-+ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
-+ *
-+ * Despite the limitations of the DWC core, we can force a microframe pipeline of
-+ * isochronous OUT start-split transactions while waiting for a corresponding other-type
-+ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
-+ * is very unlikely that filling the start-split FIFO will cause data loss.
-+ * This allows much better interleaving of transactions in an order-independent way-
-+ * there is no requirement to prioritise isochronous, just a state-space search has
-+ * to be performed on each periodic start-split complete interrupt.
-+ */
-+static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
-+{
-+ int hub_addr = st->channel[n].hub_addr;
-+ int port_addr = st->channel[n].port_addr;
-+ int i, poked = 0;
-+ for (i = 0; i < num_channels; i++) {
-+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
-+ continue;
-+ if (st->channel[i].hub_addr == hub_addr &&
-+ st->channel[i].port_addr == port_addr) {
-+ switch (st->channel[i].fsm) {
-+ case FIQ_PER_ISO_OUT_PENDING:
-+ if (st->channel[i].nrpackets == 1) {
-+ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
-+ } else {
-+ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ }
-+ fiq_fsm_restart_channel(st, i, 0);
-+ poked = 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ }
-+ if (poked)
-+ break;
-+ }
-+ return poked;
-+}
-+
-+/**
-+ * fiq_fsm_tt_in_use() - search for host channels using this TT
-+ * @n: Channel to use as reference
-+ *
-+ */
-+int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
-+{
-+ int hub_addr = st->channel[n].hub_addr;
-+ int port_addr = st->channel[n].port_addr;
-+ int i, in_use = 0;
-+ for (i = 0; i < num_channels; i++) {
-+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
-+ continue;
-+ switch (st->channel[i].fsm) {
-+ /* TT is reserved for channels that are in the middle of a periodic
-+ * split transaction.
-+ */
-+ case FIQ_PER_SSPLIT_STARTED:
-+ case FIQ_PER_CSPLIT_WAIT:
-+ case FIQ_PER_CSPLIT_NYET1:
-+ //case FIQ_PER_CSPLIT_POLL:
-+ case FIQ_PER_ISO_OUT_ACTIVE:
-+ case FIQ_PER_ISO_OUT_LAST:
-+ if (st->channel[i].hub_addr == hub_addr &&
-+ st->channel[i].port_addr == port_addr) {
-+ in_use = 1;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ if (in_use)
-+ break;
-+ }
-+ return in_use;
-+}
-+
-+/**
-+ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
-+ * to be issued for this IN transaction.
-+ *
-+ * We cannot tell the inbound PID of a data packet due to hardware limitations.
-+ * we need to make an educated guess as to whether we need to queue another CSPLIT
-+ * or not. A no-brainer is when we have received enough data to fill the endpoint
-+ * size, but for endpoints that give variable-length data then we have to resort
-+ * to heuristics.
-+ *
-+ * We also return whether this is the last CSPLIT to be queued, again based on
-+ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
-+ * Note: requires at least 1 CSPLIT to have been performed prior to being called.
-+ */
-+
-+/*
-+ * We need some way of guaranteeing if a returned periodic packet of size X
-+ * has a DATA0 PID.
-+ * The heuristic value of 144 bytes assumes that the received data has maximal
-+ * bit-stuffing and the clock frequency of the transmitting device is at the lowest
-+ * permissible limit. If the transfer length results in a final packet size
-+ * 144 < p <= 188, then an erroneous CSPLIT will be issued.
-+ * Also used to ensure that an endpoint will nominally only return a single
-+ * complete-split worth of data.
-+ */
-+#define DATA0_PID_HEURISTIC 144
-+
-+static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
-+{
-+
-+ int i;
-+ int total_len = 0;
-+ int more_needed = 1;
-+ struct fiq_channel_state *st = &state->channel[n];
-+
-+ for (i = 0; i < st->dma_info.index; i++) {
-+ total_len += st->dma_info.slot_len[i];
-+ }
-+
-+ *probably_last = 0;
-+
-+ if (st->hcchar_copy.b.eptype == 0x3) {
-+ /*
-+ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
-+ * then this is definitely the last CSPLIT.
-+ */
-+ *probably_last = 1;
-+ } else {
-+ /* Isoc IN. This is a bit risky if we are the first transaction:
-+ * we may have been held off slightly. */
-+ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
-+ more_needed = 0;
-+ }
-+ /* If in the next uframe we will receive enough data to fill the endpoint,
-+ * then only issue 1 more csplit.
-+ */
-+ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
-+ *probably_last = 1;
-+ }
-+
-+ if (total_len >= st->hctsiz_copy.b.xfersize ||
-+ i == 6 || total_len == 0)
-+ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
-+ * a single endpoint. Accepting more would completely break our scheduling mechanism though
-+ * - in these extreme cases we will pass through a truncated packet.
-+ */
-+ more_needed = 0;
-+
-+ return more_needed;
-+}
-+
-+/**
-+ * fiq_fsm_too_late() - Test transaction for lateness
-+ *
-+ * If a SSPLIT for a large IN transaction is issued too late in a frame,
-+ * the hub will disable the port to the device and respond with ERR handshakes.
-+ * The hub status endpoint will not reflect this change.
-+ * Returns 1 if we will issue a SSPLIT that will result in a device babble.
-+ */
-+int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
-+{
-+ int uframe;
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+ uframe = hfnum.b.frnum & 0x7;
-+ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+}
-+
-+
-+/**
-+ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
-+ *
-+ * Search pending transactions in the start-split pending state and queue them.
-+ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
-+ * Note: we specifically don't do isochronous OUT transactions first because better
-+ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
-+ */
-+static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
-+{
-+ int n;
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+ if ((hfnum.b.frnum & 0x7) == 5)
-+ return;
-+ for (n = 0; n < num_channels; n++) {
-+ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
-+ /* Check to see if any other transactions are using this TT */
-+ if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
-+ if (!fiq_fsm_too_late(st, n)) {
-+ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
-+ fiq_print(FIQDBG_INT, st, "NEXTPER ");
-+ fiq_fsm_restart_channel(st, n, 0);
-+ } else {
-+ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+ }
-+ break;
-+ }
-+ }
-+ }
-+ for (n = 0; n < num_channels; n++) {
-+ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
-+ if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
-+ fiq_print(FIQDBG_INT, st, "NEXTISO ");
-+ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ fiq_fsm_restart_channel(st, n, 0);
-+ break;
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
-+ * @state: Pointer to fiq_state
-+ * @n: Channel transaction is active on
-+ * @hcint: Copy of host channel interrupt register
-+ *
-+ * Returns 0 if there are no more transactions for this HC to do, 1
-+ * otherwise.
-+ */
-+static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
-+{
-+ struct fiq_channel_state *st = &state->channel[n];
-+ int xfer_len = 0, nrpackets = 0;
-+ hcdma_data_t hcdma;
-+ fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
-+
-+ xfer_len = fiq_get_xfer_len(state, n);
-+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
-+
-+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
-+
-+ st->hs_isoc_info.index++;
-+ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
-+ return 0;
-+ }
-+
-+ /* grab the next DMA address offset from the array */
-+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
-+ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+
-+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
-+ * the core needs to be told to send the correct number. Caution: for IN transfers,
-+ * this is always set to the maximum size of the endpoint. */
-+ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
-+ /* Integer divide in a FIQ: fun. FIXME: make this not suck */
-+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
-+ if (nrpackets == 0)
-+ nrpackets = 1;
-+ st->hcchar_copy.b.multicnt = nrpackets;
-+ st->hctsiz_copy.b.pktcnt = nrpackets;
-+
-+ /* Initial PID also needs to be set */
-+ if (st->hcchar_copy.b.epdir == 0) {
-+ st->hctsiz_copy.b.xfersize = xfer_len;
-+ switch (st->hcchar_copy.b.multicnt) {
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_MDATA;
-+ break;
-+ }
-+
-+ } else {
-+ switch (st->hcchar_copy.b.multicnt) {
-+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA1;
-+ break;
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA2;
-+ break;
-+ }
-+ }
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
-+ /* Channel is enabled on hcint handler exit */
-+ fiq_print(FIQDBG_INT, state, "HSISOOUT");
-+ return 1;
-+}
-+
-+
-+/**
-+ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
-+ * @state: Pointer to the state struct passed from banked FIQ mode registers.
-+ * @num_channels: set according to the DWC hardware configuration
-+ *
-+ * The SOF handler in FSM mode has two functions
-+ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
-+ * nothing to do
-+ * 2. Advance certain FSM states that require either a microframe delay, or a microframe
-+ * of holdoff.
-+ *
-+ * The second part is architecture-specific to mach-bcm2835 -
-+ * a sane interrupt controller would have a mask register for ARM interrupt sources
-+ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
-+ * number (USB) can be enabled. This means that certain parts of the USB specification
-+ * that require "wait a little while, then issue another packet" cannot be fulfilled with
-+ * the timing granularity required to achieve optimal throughout. The workaround is to use
-+ * the SOF "timer" (125uS) to perform this task.
-+ */
-+static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
-+{
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
-+ int n;
-+ int kick_irq = 0;
-+
-+ if ((hfnum.b.frnum & 0x7) == 1) {
-+ /* We cannot issue csplits for transactions in the last frame past (n+1).1
-+ * Check to see if there are any transactions that are stale.
-+ * Boot them out.
-+ */
-+ for (n = 0; n < num_channels; n++) {
-+ switch (state->channel[n].fsm) {
-+ case FIQ_PER_CSPLIT_WAIT:
-+ case FIQ_PER_CSPLIT_NYET1:
-+ case FIQ_PER_CSPLIT_POLL:
-+ case FIQ_PER_CSPLIT_LAST:
-+ /* Check if we are no longer in the same full-speed frame. */
-+ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
-+ (hfnum.b.frnum & ~0x7))
-+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+ }
-+
-+ for (n = 0; n < num_channels; n++) {
-+ switch (state->channel[n].fsm) {
-+
-+ case FIQ_NP_SSPLIT_RETRY:
-+ case FIQ_NP_IN_CSPLIT_RETRY:
-+ case FIQ_NP_OUT_CSPLIT_RETRY:
-+ fiq_fsm_restart_channel(state, n, 0);
-+ break;
-+
-+ case FIQ_HS_ISOC_SLEEPING:
-+ state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
-+ fiq_fsm_restart_channel(state, n, 0);
-+ break;
-+
-+ case FIQ_PER_SSPLIT_QUEUED:
-+ if ((hfnum.b.frnum & 0x7) == 5)
-+ break;
-+ if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
-+ if (!fiq_fsm_too_late(state, n)) {
-+ fiq_print(FIQDBG_INT, st, "SOF GO %01d", n);
-+ fiq_fsm_restart_channel(state, n, 0);
-+ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
-+ } else {
-+ /* Transaction cannot be started without risking a device babble error */
-+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+ state->haintmsk_saved.b2.chint &= ~(1 << n);
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
-+ kick_irq |= 1;
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_PENDING:
-+ /* Ordinarily, this should be poked after the SSPLIT
-+ * complete interrupt for a competing transfer on the same
-+ * TT. Doesn't happen for aborted transactions though.
-+ */
-+ if ((hfnum.b.frnum & 0x7) >= 5)
-+ break;
-+ if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
-+ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt
-+ * that caused this.
-+ */
-+ fiq_fsm_restart_channel(state, n, 0);
-+ fiq_print(FIQDBG_INT, state, "SOF ISOC");
-+ if (state->channel[n].nrpackets == 1) {
-+ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
-+ } else {
-+ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_WAIT:
-+ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt
-+ * occurred when the bus transaction occurred. The SOF interrupt reversal bug
-+ * will utterly bugger this up though.
-+ */
-+ if (hfnum.b.frnum != state->channel[n].expected_uframe) {
-+ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
-+ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
-+ fiq_fsm_restart_channel(state, n, 0);
-+ fiq_fsm_start_next_periodic(state, num_channels);
-+
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_TIMEOUT:
-+ case FIQ_DEQUEUE_ISSUED:
-+ /* Ugly: we have to force a HCD interrupt.
-+ * Poke the mask for the channel in question.
-+ * We will take a fake SOF because of this, but
-+ * that's OK.
-+ */
-+ state->haintmsk_saved.b2.chint &= ~(1 << n);
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
-+ kick_irq |= 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ }
-+
-+ if (state->kick_np_queues ||
-+ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
-+ kick_irq |= 1;
-+
-+ return !kick_irq;
-+}
-+
-+
-+/**
-+ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
-+ * @state: Pointer to the FIQ state struct
-+ * @num_channels: Number of channels as per hardware config
-+ * @n: channel for which HAINT(i) was raised
-+ *
-+ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
-+ */
-+static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
-+{
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ hcint_data_t hcint_probe;
-+ hcchar_data_t hcchar;
-+ int handled = 0;
-+ int restart = 0;
-+ int last_csplit = 0;
-+ int start_next_periodic = 0;
-+ struct fiq_channel_state *st = &state->channel[n];
-+ hfnum_data_t hfnum;
-+
-+ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
-+ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
-+ hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
-+
-+ if (st->fsm != FIQ_PASSTHROUGH) {
-+ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
-+ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
-+ }
-+
-+ switch (st->fsm) {
-+
-+ case FIQ_PASSTHROUGH:
-+ case FIQ_DEQUEUE_ISSUED:
-+ /* doesn't belong to us, kick it upstairs */
-+ break;
-+
-+ case FIQ_PASSTHROUGH_ERRORSTATE:
-+ /* We are here to emulate the error recovery mechanism of the dwc HCD.
-+ * Several interrupts are unmasked if a previous transaction failed - it's
-+ * death for the FIQ to attempt to handle them as the channel isn't halted.
-+ * Emulate what the HCD does in this situation: mask and continue.
-+ * The FSM has no other state setup so this has to be handled out-of-band.
-+ */
-+ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
-+ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
-+ fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
-+ /* In some random cases we can get a NAK interrupt coincident with a Xacterr
-+ * interrupt, after the device has disappeared.
-+ */
-+ if (!hcint.b.xacterr)
-+ st->nr_errors = 0;
-+ hcintmsk.b.nak = 0;
-+ hcintmsk.b.ack = 0;
-+ hcintmsk.b.datatglerr = 0;
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
-+ return 1;
-+ }
-+ if (hcint_probe.b.chhltd) {
-+ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
-+ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
-+ return 0;
-+ }
-+ break;
-+
-+ /* Non-periodic state groups */
-+ case FIQ_NP_SSPLIT_STARTED:
-+ case FIQ_NP_SSPLIT_RETRY:
-+ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
-+ if (hcint.b.ack) {
-+ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
-+ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
-+ */
-+ if(st->hcchar_copy.b.epdir == 1)
-+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
-+ else
-+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+ st->nr_errors = 0;
-+ handled = 1;
-+ fiq_fsm_setup_csplit(state, n);
-+ } else if (hcint.b.nak) {
-+ // No buffer space in TT. Retry on a uframe boundary.
-+ st->fsm = FIQ_NP_SSPLIT_RETRY;
-+ handled = 1;
-+ } else if (hcint.b.xacterr) {
-+ // The only other one we care about is xacterr. This implies HS bus error - retry.
-+ st->nr_errors++;
-+ st->fsm = FIQ_NP_SSPLIT_RETRY;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ restart = 1;
-+ }
-+ } else {
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ handled = 0;
-+ restart = 0;
-+ }
-+ break;
-+
-+ case FIQ_NP_IN_CSPLIT_RETRY:
-+ /* Received a CSPLIT done interrupt.
-+ * Expected Data/NAK/STALL/NYET for IN.
-+ */
-+ if (hcint.b.xfercomp) {
-+ /* For IN, data is present. */
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nak) {
-+ /* no endpoint data. Punt it upstairs */
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nyet) {
-+ /* CSPLIT NYET - retry on a uframe boundary. */
-+ handled = 1;
-+ st->nr_errors = 0;
-+ } else if (hcint.b.datatglerr) {
-+ /* data toggle errors do not set the xfercomp bit. */
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ } else if (hcint.b.xacterr) {
-+ /* HS error. Retry immediate */
-+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ restart = 1;
-+ }
-+ } else if (hcint.b.stall || hcint.b.bblerr) {
-+ /* A STALL implies either a LS bus error or a genuine STALL. */
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ } else {
-+ /* Hardware bug. It's possible in some cases to
-+ * get a channel halt with nothing else set when
-+ * the response was a NYET. Treat as local 3-strikes retry.
-+ */
-+ hcint_data_t hcint_test = hcint;
-+ hcint_test.b.chhltd = 0;
-+ if (!hcint_test.d32) {
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ }
-+ } else {
-+ /* Bail out if something unexpected happened */
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ }
-+ }
-+ break;
-+
-+ case FIQ_NP_OUT_CSPLIT_RETRY:
-+ /* Received a CSPLIT done interrupt.
-+ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
-+ if (hcint.b.xfercomp) {
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nak) {
-+ // The HCD will implement the holdoff on frame boundaries.
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nyet) {
-+ // Hub still processing.
-+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+ handled = 1;
-+ st->nr_errors = 0;
-+ //restart = 1;
-+ } else if (hcint.b.xacterr) {
-+ /* HS error. retry immediate */
-+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ restart = 1;
-+ }
-+ } else if (hcint.b.stall) {
-+ /* LS bus error or genuine stall */
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ } else {
-+ /*
-+ * Hardware bug. It's possible in some cases to get a
-+ * channel halt with nothing else set when the response was a NYET.
-+ * Treat as local 3-strikes retry.
-+ */
-+ hcint_data_t hcint_test = hcint;
-+ hcint_test.b.chhltd = 0;
-+ if (!hcint_test.d32) {
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ }
-+ } else {
-+ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ }
-+ }
-+ break;
-+
-+ /* Periodic split states (except isoc out) */
-+ case FIQ_PER_SSPLIT_STARTED:
-+ /* Expect an ACK or failure for SSPLIT */
-+ if (hcint.b.ack) {
-+ /*
-+ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
-+ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
-+ * point for microframe n-3, the packet will not appear on the bus until microframe n.
-+ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
-+ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
-+ * coincident with SOF for n+1.
-+ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
-+ * These appear to be caused by timing/clock crossing bugs within the core itself.
-+ * State machine workaround.
-+ */
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ fiq_fsm_setup_csplit(state, n);
-+ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
-+ * time. If not, then we're in the next SOF.
-+ */
-+ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
-+ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
-+ st->expected_uframe = hfnum.b.frnum;
-+ st->fsm = FIQ_PER_CSPLIT_WAIT;
-+ } else {
-+ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n);
-+ /* For isochronous IN endpoints,
-+ * we need to hold off if we are expecting a lot of data */
-+ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
-+ start_next_periodic = 1;
-+ }
-+ /* Danger will robinson: we are in a broken state. If our first interrupt after
-+ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
-+ * lag. Unmask the NYET interrupt.
-+ */
-+ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
-+ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
-+ restart = 1;
-+ }
-+ handled = 1;
-+ } else if (hcint.b.xacterr) {
-+ /* 3-strikes retry is enabled, we have hit our max nr_errors */
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ start_next_periodic = 1;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ start_next_periodic = 1;
-+ }
-+ /* We can now queue the next isochronous OUT transaction, if one is pending. */
-+ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
-+ fiq_print(FIQDBG_INT, state, "NEXTISO ");
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_NYET1:
-+ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
-+ * we are too late and the TT has dropped its CSPLIT fifo.
-+ */
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ start_next_periodic = 1;
-+ if (hcint.b.nak) {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ } else if (hcint.b.xfercomp) {
-+ fiq_increment_dma_buf(state, num_channels, n);
-+ st->fsm = FIQ_PER_CSPLIT_POLL;
-+ st->nr_errors = 0;
-+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+ handled = 1;
-+ restart = 1;
-+ if (!last_csplit)
-+ start_next_periodic = 0;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ } else if (hcint.b.nyet) {
-+ /* Doh. Data lost. */
-+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_BROKEN_NYET1:
-+ /*
-+ * we got here because our host channel is in the delayed-interrupt
-+ * state and we cannot take a NYET interrupt any later than when it
-+ * occurred. Disable then re-enable the channel if this happens to force
-+ * CSPLITs to occur at the right time.
-+ */
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
-+ if (hcint.b.nak) {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ start_next_periodic = 1;
-+ } else if (hcint.b.xfercomp) {
-+ fiq_increment_dma_buf(state, num_channels, n);
-+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+ st->fsm = FIQ_PER_CSPLIT_POLL;
-+ handled = 1;
-+ restart = 1;
-+ start_next_periodic = 1;
-+ /* Reload HCTSIZ for the next transfer */
-+ fiq_fsm_reload_hctsiz(state, n);
-+ if (!last_csplit)
-+ start_next_periodic = 0;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ } else if (hcint.b.nyet) {
-+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+ start_next_periodic = 1;
-+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/
-+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_POLL:
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ start_next_periodic = 1;
-+ if (hcint.b.nak) {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ } else if (hcint.b.xfercomp) {
-+ fiq_increment_dma_buf(state, num_channels, n);
-+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+ handled = 1;
-+ restart = 1;
-+ /* Reload HCTSIZ for the next transfer */
-+ fiq_fsm_reload_hctsiz(state, n);
-+ if (!last_csplit)
-+ start_next_periodic = 0;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ } else if (hcint.b.nyet) {
-+ /* Are we a NYET after the first data packet? */
-+ if (st->nrpackets == 0) {
-+ st->fsm = FIQ_PER_CSPLIT_NYET1;
-+ handled = 1;
-+ restart = 1;
-+ } else {
-+ /* We got a NYET when polling CSPLITs. Can happen
-+ * if our heuristic fails, or if someone disables us
-+ * for any significant length of time.
-+ */
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ }
-+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
-+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ }
-+ break;
-+
-+ case FIQ_HS_ISOC_TURBO:
-+ if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
-+ /* more transactions to come */
-+ handled = 1;
-+ restart = 1;
-+ fiq_print(FIQDBG_INT, state, "HSISO M ");
-+ } else {
-+ st->fsm = FIQ_HS_ISOC_DONE;
-+ fiq_print(FIQDBG_INT, state, "HSISO F ");
-+ }
-+ break;
-+
-+ case FIQ_HS_ISOC_ABORTED:
-+ /* This abort is called by the driver rewriting the state mid-transaction
-+ * which allows the dequeue mechanism to work more effectively.
-+ */
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_ACTIVE:
-+ if (hcint.b.ack) {
-+ if(fiq_iso_out_advance(state, num_channels, n)) {
-+ /* last OUT transfer */
-+ st->fsm = FIQ_PER_ISO_OUT_LAST;
-+ /*
-+ * Assuming the periodic FIFO in the dwc core
-+ * actually does its job properly, we can queue
-+ * the next ssplit now and in theory, the wire
-+ * transactions will be in-order.
-+ */
-+ // No it doesn't. It appears to process requests in host channel order.
-+ //start_next_periodic = 1;
-+ }
-+ handled = 1;
-+ restart = 1;
-+ } else {
-+ /*
-+ * Isochronous transactions carry on regardless. Log the error
-+ * and continue.
-+ */
-+ //explode += 1;
-+ st->nr_errors++;
-+ if(fiq_iso_out_advance(state, num_channels, n)) {
-+ st->fsm = FIQ_PER_ISO_OUT_LAST;
-+ //start_next_periodic = 1;
-+ }
-+ handled = 1;
-+ restart = 1;
-+ }
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_LAST:
-+ if (hcint.b.ack) {
-+ /* All done here */
-+ st->fsm = FIQ_PER_ISO_OUT_DONE;
-+ } else {
-+ st->fsm = FIQ_PER_ISO_OUT_DONE;
-+ st->nr_errors++;
-+ }
-+ start_next_periodic = 1;
-+ break;
-+
-+ case FIQ_PER_SPLIT_TIMEOUT:
-+ /* SOF kicked us because we overran. */
-+ start_next_periodic = 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ if (handled) {
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
-+ } else {
-+ /* Copy the regs into the state so the IRQ knows what to do */
-+ st->hcint_copy.d32 = hcint.d32;
-+ }
-+
-+ if (restart) {
-+ /* Restart always implies handled. */
-+ if (restart == 2) {
-+ /* For complete-split INs, the show must go on.
-+ * Force a channel restart */
-+ fiq_fsm_restart_channel(state, n, 1);
-+ } else {
-+ fiq_fsm_restart_channel(state, n, 0);
-+ }
-+ }
-+ if (start_next_periodic) {
-+ fiq_fsm_start_next_periodic(state, num_channels);
-+ }
-+ if (st->fsm != FIQ_PASSTHROUGH)
-+ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
-+
-+ return handled;
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
-+ * @state: pointer to state struct passed from the banked FIQ mode registers.
-+ * @num_channels: set according to the DWC hardware configuration
-+ * @dma: pointer to DMA bounce buffers for split transaction slots
-+ *
-+ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
-+ * inside an EHCI or similar host controller regarding split transactions. The DWC core
-+ * interrupts each and every time a split transaction packet is received or sent successfully.
-+ * This results in either an interrupt storm when everything is working "properly", or
-+ * the interrupt latency of the system in general breaks time-sensitive periodic split
-+ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
-+ * solves these problems.
-+ *
-+ * Return: void
-+ */
-+void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
-+{
-+ gintsts_data_t gintsts, gintsts_handled;
-+ gintmsk_data_t gintmsk;
-+ //hfnum_data_t hfnum;
-+ haint_data_t haint, haint_handled;
-+ haintmsk_data_t haintmsk;
-+ int kick_irq = 0;
-+
-+ gintsts_handled.d32 = 0;
-+ haint_handled.d32 = 0;
-+
-+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
-+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
-+ gintsts.d32 &= gintmsk.d32;
-+
-+ if (gintsts.b.sofintr) {
-+ /* For FSM mode, SOF is required to keep the state machine advance for
-+ * certain stages of the periodic pipeline. It's death to mask this
-+ * interrupt in that case.
-+ */
-+
-+ if (!fiq_fsm_do_sof(state, num_channels)) {
-+ /* Kick IRQ once. Queue advancement means that all pending transactions
-+ * will get serviced when the IRQ finally executes.
-+ */
-+ if (state->gintmsk_saved.b.sofintr == 1)
-+ kick_irq |= 1;
-+ state->gintmsk_saved.b.sofintr = 0;
-+ }
-+ gintsts_handled.b.sofintr = 1;
-+ }
-+
-+ if (gintsts.b.hcintr) {
-+ int i;
-+ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
-+ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
-+ haint.d32 &= haintmsk.d32;
-+ haint_handled.d32 = 0;
-+ for (i=0; i<num_channels; i++) {
-+ if (haint.b2.chint & (1 << i)) {
-+ if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
-+ /* HCINT was not handled in FIQ
-+ * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
-+ * Mask HAINT(i) but keep top-level hcint unmasked.
-+ */
-+ state->haintmsk_saved.b2.chint &= ~(1 << i);
-+ } else {
-+ /* do_hcintr cleaned up after itself, but clear haint */
-+ haint_handled.b2.chint |= (1 << i);
-+ }
-+ }
-+ }
-+
-+ if (haint_handled.b2.chint) {
-+ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
-+ }
-+
-+ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
-+ /*
-+ * This is necessary to avoid multiple retriggers of the MPHI in the case
-+ * where interrupts are held off and HCINTs start to pile up.
-+ * Only wake up the IRQ if a new interrupt came in, was not handled and was
-+ * masked.
-+ */
-+ haintmsk.d32 &= state->haintmsk_saved.d32;
-+ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
-+ kick_irq |= 1;
-+ }
-+ /* Top-Level interrupt - always handled because it's level-sensitive */
-+ gintsts_handled.b.hcintr = 1;
-+ }
-+
-+
-+ /* Clear the bits in the saved register that were not handled but were triggered. */
-+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
-+
-+ /* FIQ didn't handle something - mask has changed - write new mask */
-+ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
-+ gintmsk.d32 &= state->gintmsk_saved.d32;
-+ gintmsk.b.sofintr = 1;
-+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+// fiq_print(FIQDBG_INT, state, "KICKGINT");
-+// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
-+// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
-+ kick_irq |= 1;
-+ }
-+
-+ if (gintsts_handled.d32) {
-+ /* Only applies to edge-sensitive bits in GINTSTS */
-+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
-+ }
-+
-+ /* We got an interrupt, didn't handle it. */
-+ if (kick_irq) {
-+ state->mphi_int_count++;
-+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
-+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
-+
-+ }
-+ state->fiq_done++;
-+ mb();
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_nop() - FIQ "lite"
-+ * @state: pointer to state struct passed from the banked FIQ mode registers.
-+ *
-+ * The "nop" handler does not intervene on any interrupts other than SOF.
-+ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
-+ * with non-periodic/periodic queues) needs to be kicked.
-+ *
-+ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
-+ *
-+ * Return: void
-+ */
-+void notrace dwc_otg_fiq_nop(struct fiq_state *state)
-+{
-+ gintsts_data_t gintsts, gintsts_handled;
-+ gintmsk_data_t gintmsk;
-+ hfnum_data_t hfnum;
-+
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
-+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
-+ gintsts.d32 &= gintmsk.d32;
-+ gintsts_handled.d32 = 0;
-+
-+ if (gintsts.b.sofintr) {
-+ if (!state->kick_np_queues &&
-+ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
-+ /* SOF handled, no work to do, just ACK interrupt */
-+ gintsts_handled.b.sofintr = 1;
-+ } else {
-+ /* Kick IRQ */
-+ state->gintmsk_saved.b.sofintr = 0;
-+ }
-+ }
-+
-+ /* Reset handled interrupts */
-+ if(gintsts_handled.d32) {
-+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
-+ }
-+
-+ /* Clear the bits in the saved register that were not handled but were triggered. */
-+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
-+
-+ /* We got an interrupt, didn't handle it and want to mask it */
-+ if (~(state->gintmsk_saved.d32)) {
-+ state->mphi_int_count++;
-+ gintmsk.d32 &= state->gintmsk_saved.d32;
-+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+ /* Force a clear before another dummy send */
-+ FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
-+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
-+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
-+
-+ }
-+ state->fiq_done++;
-+ mb();
-+}
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,353 @@
-+/*
-+ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Raspberry Pi nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This FIQ implements functionality that performs split transactions on
-+ * the dwc_otg hardware without any outside intervention. A split transaction
-+ * is "queued" by nominating a specific host channel to perform the entirety
-+ * of a split transaction. This FIQ will then perform the microframe-precise
-+ * scheduling required in each phase of the transaction until completion.
-+ *
-+ * The FIQ functionality has been surgically implanted into the Synopsys
-+ * vendor-provided driver.
-+ *
-+ */
-+
-+#ifndef DWC_OTG_FIQ_FSM_H_
-+#define DWC_OTG_FIQ_FSM_H_
-+
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_hcd.h"
-+#include <linux/kernel.h>
-+#include <linux/irqflags.h>
-+#include <linux/string.h>
-+#include <asm/barrier.h>
-+
-+#if 0
-+#define FLAME_ON(x) \
-+do { \
-+ int gpioreg; \
-+ \
-+ gpioreg = readl(__io_address(0x20200000+0x8)); \
-+ gpioreg &= ~(7 << (x-20)*3); \
-+ gpioreg |= 0x1 << (x-20)*3; \
-+ writel(gpioreg, __io_address(0x20200000+0x8)); \
-+ \
-+ writel(1<<x, __io_address(0x20200000+(0x1C))); \
-+} while (0)
-+
-+#define FLAME_OFF(x) \
-+do { \
-+ writel(1<<x, __io_address(0x20200000+(0x28))); \
-+} while (0)
-+#else
-+#define FLAME_ON(x) do { } while (0)
-+#define FLAME_OFF(X) do { } while (0)
-+#endif
-+
-+/* This is a quick-and-dirty arch-specific register read/write. We know that
-+ * writes to a peripheral on BCM2835 will always arrive in-order, also that
-+ * reads and writes are executed in-order therefore the need for memory barriers
-+ * is obviated if we're only talking to USB.
-+ */
-+#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
-+#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
-+
-+/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
-+#define GINTSTS 0x014
-+#define GINTMSK 0x018
-+/* Debug register. Poll the top of the received packets FIFO. */
-+#define GRXSTSR 0x01C
-+#define HFNUM 0x408
-+#define HAINT 0x414
-+#define HAINTMSK 0x418
-+#define HPRT0 0x440
-+
-+/* HC_regs start from an offset of 0x500 */
-+#define HC_START 0x500
-+#define HC_OFFSET 0x020
-+
-+#define HC_DMA 0x514
-+
-+#define HCCHAR 0x00
-+#define HCSPLT 0x04
-+#define HCINT 0x08
-+#define HCINTMSK 0x0C
-+#define HCTSIZ 0x10
-+
-+#define ISOC_XACTPOS_ALL 0b11
-+#define ISOC_XACTPOS_BEGIN 0b10
-+#define ISOC_XACTPOS_MID 0b00
-+#define ISOC_XACTPOS_END 0b01
-+
-+#define DWC_PID_DATA2 0b01
-+#define DWC_PID_MDATA 0b11
-+#define DWC_PID_DATA1 0b10
-+#define DWC_PID_DATA0 0b00
-+
-+typedef struct {
-+ volatile void* base;
-+ volatile void* ctrl;
-+ volatile void* outdda;
-+ volatile void* outddb;
-+ volatile void* intstat;
-+} mphi_regs_t;
-+
-+
-+enum fiq_debug_level {
-+ FIQDBG_SCHED = (1 << 0),
-+ FIQDBG_INT = (1 << 1),
-+ FIQDBG_ERR = (1 << 2),
-+ FIQDBG_PORTHUB = (1 << 3),
-+};
-+
-+struct fiq_state;
-+
-+extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
-+#if 0
-+#define fiq_print _fiq_print
-+#else
-+#define fiq_print(x, y, ...)
-+#endif
-+
-+extern bool fiq_enable, fiq_fsm_enable;
-+extern ushort nak_holdoff;
-+
-+/**
-+ * enum fiq_fsm_state - The FIQ FSM states.
-+ *
-+ * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
-+ * USB2.0 specification for host responses to various transaction states.
-+ * There are modifications to this host state machine because of a variety of
-+ * quirks and limitations in the dwc_otg hardware.
-+ *
-+ * The fsm state is also used to communicate back to the driver on completion of
-+ * a split transaction. The end states are used in conjunction with the interrupts
-+ * raised by the final transaction.
-+ */
-+enum fiq_fsm_state {
-+ /* FIQ isn't enabled for this host channel */
-+ FIQ_PASSTHROUGH = 0,
-+ /* For the first interrupt received for this channel,
-+ * the FIQ has to ack any interrupts indicating success. */
-+ FIQ_PASSTHROUGH_ERRORSTATE = 31,
-+ /* Nonperiodic state groups */
-+ FIQ_NP_SSPLIT_STARTED = 1,
-+ FIQ_NP_SSPLIT_RETRY = 2,
-+ FIQ_NP_OUT_CSPLIT_RETRY = 3,
-+ FIQ_NP_IN_CSPLIT_RETRY = 4,
-+ FIQ_NP_SPLIT_DONE = 5,
-+ FIQ_NP_SPLIT_LS_ABORTED = 6,
-+ /* This differentiates a HS transaction error from a LS one
-+ * (handling the hub state is different) */
-+ FIQ_NP_SPLIT_HS_ABORTED = 7,
-+
-+ /* Periodic state groups */
-+ /* Periodic transactions are either started directly by the IRQ handler
-+ * or deferred if the TT is already in use.
-+ */
-+ FIQ_PER_SSPLIT_QUEUED = 8,
-+ FIQ_PER_SSPLIT_STARTED = 9,
-+ FIQ_PER_SSPLIT_LAST = 10,
-+
-+
-+ FIQ_PER_ISO_OUT_PENDING = 11,
-+ FIQ_PER_ISO_OUT_ACTIVE = 12,
-+ FIQ_PER_ISO_OUT_LAST = 13,
-+ FIQ_PER_ISO_OUT_DONE = 27,
-+
-+ FIQ_PER_CSPLIT_WAIT = 14,
-+ FIQ_PER_CSPLIT_NYET1 = 15,
-+ FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
-+ FIQ_PER_CSPLIT_NYET_FAFF = 29,
-+ /* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
-+ FIQ_PER_CSPLIT_POLL = 16,
-+ /* The last CSPLIT for a transaction has been issued, differentiates
-+ * for the state machine to queue the next packet.
-+ */
-+ FIQ_PER_CSPLIT_LAST = 17,
-+
-+ FIQ_PER_SPLIT_DONE = 18,
-+ FIQ_PER_SPLIT_LS_ABORTED = 19,
-+ FIQ_PER_SPLIT_HS_ABORTED = 20,
-+ FIQ_PER_SPLIT_NYET_ABORTED = 21,
-+ /* Frame rollover has occurred without the transaction finishing. */
-+ FIQ_PER_SPLIT_TIMEOUT = 22,
-+
-+ /* FIQ-accelerated HS Isochronous state groups */
-+ FIQ_HS_ISOC_TURBO = 23,
-+ /* For interval > 1, SOF wakes up the isochronous FSM */
-+ FIQ_HS_ISOC_SLEEPING = 24,
-+ FIQ_HS_ISOC_DONE = 25,
-+ FIQ_HS_ISOC_ABORTED = 26,
-+ FIQ_DEQUEUE_ISSUED = 30,
-+ FIQ_TEST = 32,
-+};
-+
-+struct fiq_stack {
-+ int magic1;
-+ uint8_t stack[2048];
-+ int magic2;
-+};
-+
-+
-+/**
-+ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
-+ * @index: Number of slots reported used for IN transactions / number of slots
-+ * transmitted for an OUT transaction
-+ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
-+ *
-+ * Split transaction transfers can have variable length depending on other bus
-+ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
-+ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
-+ * can happen per-frame.
-+ */
-+struct fiq_dma_info {
-+ u8 index;
-+ u8 slot_len[6];
-+};
-+
-+struct __attribute__((packed)) fiq_split_dma_slot {
-+ u8 buf[188];
-+};
-+
-+struct fiq_dma_channel {
-+ struct __attribute__((packed)) fiq_split_dma_slot index[6];
-+};
-+
-+struct fiq_dma_blob {
-+ struct __attribute__((packed)) fiq_dma_channel channel[0];
-+};
-+
-+/**
-+ * struct fiq_hs_isoc_info - USB2.0 isochronous data
-+ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
-+ * @nrframes: Total length of iso_frame_desc array
-+ * @index: Current index (FIQ-maintained)
-+ *
-+ */
-+struct fiq_hs_isoc_info {
-+ struct dwc_otg_hcd_iso_packet_desc *iso_desc;
-+ unsigned int nrframes;
-+ unsigned int index;
-+};
-+
-+/**
-+ * struct fiq_channel_state - FIQ state machine storage
-+ * @fsm: Current state of the channel as understood by the FIQ
-+ * @nr_errors: Number of transaction errors on this split-transaction
-+ * @hub_addr: SSPLIT/CSPLIT destination hub
-+ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub
-+ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For
-+ * split-IN, number of CSPLIT data packets that were received.
-+ * @hcchar_copy:
-+ * @hcsplt_copy:
-+ * @hcintmsk_copy:
-+ * @hctsiz_copy: Copies of the host channel registers.
-+ * For use as scratch, or for returning state.
-+ *
-+ * The fiq_channel_state is state storage between interrupts for a host channel. The
-+ * FSM state is stored here. Members of this structure must only be set up by the
-+ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
-+ * has updated the state to either a COMPLETE state group or ABORT state group.
-+ */
-+
-+struct fiq_channel_state {
-+ enum fiq_fsm_state fsm;
-+ unsigned int nr_errors;
-+ unsigned int hub_addr;
-+ unsigned int port_addr;
-+ /* Hardware bug workaround: sometimes channel halt interrupts are
-+ * delayed until the next SOF. Keep track of when we expected to get interrupted. */
-+ unsigned int expected_uframe;
-+ /* in/out for communicating number of dma buffers used, or number of ISOC to do */
-+ unsigned int nrpackets;
-+ struct fiq_dma_info dma_info;
-+ struct fiq_hs_isoc_info hs_isoc_info;
-+ /* Copies of HC registers - in/out communication from/to IRQ handler
-+ * and for ease of channel setup. A bit of mungeing is performed - for
-+ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
-+ */
-+ hcchar_data_t hcchar_copy;
-+ hcsplt_data_t hcsplt_copy;
-+ hcint_data_t hcint_copy;
-+ hcintmsk_data_t hcintmsk_copy;
-+ hctsiz_data_t hctsiz_copy;
-+ hcdma_data_t hcdma_copy;
-+};
-+
-+/**
-+ * struct fiq_state - top-level FIQ state machine storage
-+ * @mphi_regs: virtual address of the MPHI peripheral register file
-+ * @dwc_regs_base: virtual address of the base of the DWC core register file
-+ * @dma_base: physical address for the base of the DMA bounce buffers
-+ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral
-+ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled.
-+ * Used for determining which interrupts fired to set off the IRQ handler.
-+ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally.
-+ * @np_count: Non-periodic transactions in the active queue
-+ * @np_sent: Count of non-periodic transactions that have completed
-+ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism,
-+ * this is the next frame on which a SOF interrupt is required. Used to hold off
-+ * passing SOF through to the driver until necessary.
-+ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host
-+ * channels configured into the core logic.
-+ *
-+ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
-+ * It contains top-level state information.
-+ */
-+struct fiq_state {
-+ mphi_regs_t mphi_regs;
-+ void *dwc_regs_base;
-+ dma_addr_t dma_base;
-+ struct fiq_dma_blob *fiq_dmab;
-+ void *dummy_send;
-+ gintmsk_data_t gintmsk_saved;
-+ haintmsk_data_t haintmsk_saved;
-+ int mphi_int_count;
-+ unsigned int fiq_done;
-+ unsigned int kick_np_queues;
-+ unsigned int next_sched_frame;
-+#ifdef FIQ_DEBUG
-+ char * buffer;
-+ unsigned int bufsiz;
-+#endif
-+ struct fiq_channel_state channel[0];
-+};
-+
-+extern int fiq_fsm_too_late(struct fiq_state *st, int n);
-+
-+extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
-+
-+extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
-+
-+extern void dwc_otg_fiq_nop(struct fiq_state *state);
-+
-+#endif /* DWC_OTG_FIQ_FSM_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,81 @@
-+/*
-+ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Raspberry Pi nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+#include <asm/assembler.h>
-+#include <linux/linkage.h>
-+
-+
-+.text
-+
-+.global _dwc_otg_fiq_stub_end;
-+
-+/**
-+ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
-+ * a C-style function call with arguments from the FIQ banked registers.
-+ * r0 = &hcd->fiq_state
-+ * r1 = &hcd->num_channels
-+ * r2 = &hcd->dma_buffers
-+ * Tramples: r0, r1, r2, r4, fp, ip
-+ */
-+
-+ENTRY(_dwc_otg_fiq_stub)
-+ /* Stash unbanked regs - SP will have been set up for us */
-+ mov ip, sp;
-+ stmdb sp!, {r0-r12, lr};
-+#ifdef FIQ_DEBUG
-+ // Cycle profiling - read cycle counter at start
-+ mrc p15, 0, r5, c15, c12, 1;
-+#endif
-+ /* r11 = fp, don't trample it */
-+ mov r4, fp;
-+ /* set EABI frame size */
-+ sub fp, ip, #512;
-+
-+ /* for fiq NOP mode - just need state */
-+ mov r0, r8;
-+ /* r9 = num_channels */
-+ mov r1, r9;
-+ /* r10 = struct *dma_bufs */
-+// mov r2, r10;
-+
-+ /* r4 = &fiq_c_function */
-+ blx r4;
-+#ifdef FIQ_DEBUG
-+ mrc p15, 0, r4, c15, c12, 1;
-+ subs r5, r5, r4;
-+ // r5 is now the cycle count time for executing the FIQ. Store it somewhere?
-+#endif
-+ ldmia sp!, {r0-r12, lr};
-+ subs pc, lr, #4;
-+_dwc_otg_fiq_stub_end:
-+END(_dwc_otg_fiq_stub)
-+
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,4212 @@
-+
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
-+ * $Revision: #104 $
-+ * $Date: 2011/10/24 $
-+ * $Change: 1871159 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/** @file
-+ * This file implements HCD Core. All code in this file is portable and doesn't
-+ * use any OS specific functions.
-+ * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
-+ * header file.
-+ */
-+
-+#include <linux/usb.h>
-+#include <linux/usb/hcd.h>
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+extern bool microframe_schedule;
-+extern uint16_t fiq_fsm_mask, nak_holdoff;
-+
-+//#define DEBUG_HOST_CHANNELS
-+#ifdef DEBUG_HOST_CHANNELS
-+static int last_sel_trans_num_per_scheduled = 0;
-+static int last_sel_trans_num_nonper_scheduled = 0;
-+static int last_sel_trans_num_avail_hc_at_start = 0;
-+static int last_sel_trans_num_avail_hc_at_end = 0;
-+#endif /* DEBUG_HOST_CHANNELS */
-+
-+
-+dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
-+{
-+ return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
-+}
-+
-+/**
-+ * Connection timeout function. An OTG host is required to display a
-+ * message if the device does not connect within 10 seconds.
-+ */
-+void dwc_otg_hcd_connect_timeout(void *ptr)
-+{
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
-+ DWC_PRINTF("Connect Timeout\n");
-+ __DWC_ERROR("Device Not Connected/Responding\n");
-+}
-+
-+#if defined(DEBUG)
-+static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ if (qh->channel != NULL) {
-+ dwc_hc_t *hc = qh->channel;
-+ dwc_list_link_t *item;
-+ dwc_otg_qh_t *qh_item;
-+ int num_channels = hcd->core_if->core_params->host_channels;
-+ int i;
-+
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+ hctsiz_data_t hctsiz;
-+ uint32_t hcdma;
-+
-+ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ hcdma = DWC_READ_REG32(&hc_regs->hcdma);
-+
-+ DWC_PRINTF(" Assigned to channel %p:\n", hc);
-+ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
-+ hcsplt.d32);
-+ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
-+ hcdma);
-+ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
-+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
-+ DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
-+ DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
-+ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
-+ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
-+ DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
-+ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
-+ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
-+ DWC_PRINTF(" qh: %p\n", hc->qh);
-+ DWC_PRINTF(" NP inactive sched:\n");
-+ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
-+ qh_item =
-+ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+ DWC_PRINTF(" %p\n", qh_item);
-+ }
-+ DWC_PRINTF(" NP active sched:\n");
-+ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
-+ qh_item =
-+ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+ DWC_PRINTF(" %p\n", qh_item);
-+ }
-+ DWC_PRINTF(" Channels: \n");
-+ for (i = 0; i < num_channels; i++) {
-+ dwc_hc_t *hc = hcd->hc_ptr_array[i];
-+ DWC_PRINTF(" %2d: %p\n", i, hc);
-+ }
-+ }
-+}
-+#else
-+#define dump_channel_info(hcd, qh)
-+#endif /* DEBUG */
-+
-+/**
-+ * Work queue function for starting the HCD when A-Cable is connected.
-+ * The hcd_start() must be called in a process context.
-+ */
-+static void hcd_start_func(void *_vp)
-+{
-+ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
-+ if (hcd) {
-+ hcd->fops->start(hcd);
-+ }
-+}
-+
-+static void del_xfer_timers(dwc_otg_hcd_t * hcd)
-+{
-+#ifdef DEBUG
-+ int i;
-+ int num_channels = hcd->core_if->core_params->host_channels;
-+ for (i = 0; i < num_channels; i++) {
-+ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
-+ }
-+#endif
-+}
-+
-+static void del_timers(dwc_otg_hcd_t * hcd)
-+{
-+ del_xfer_timers(hcd);
-+ DWC_TIMER_CANCEL(hcd->conn_timer);
-+}
-+
-+/**
-+ * Processes all the URBs in a single list of QHs. Completes them with
-+ * -ESHUTDOWN and frees the QTD.
-+ */
-+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
-+{
-+ dwc_list_link_t *qh_item, *qh_tmp;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+
-+ DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
-+ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
-+ &qh->qtd_list, qtd_list_entry) {
-+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+ if (qtd->urb != NULL) {
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_SHUTDOWN);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+ }
-+
-+ }
-+ if(qh->channel) {
-+ /* Using hcchar.chen == 1 is not a reliable test.
-+ * It is possible that the channel has already halted
-+ * but not yet been through the IRQ handler.
-+ */
-+ dwc_otg_hc_halt(hcd->core_if, qh->channel,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE);
-+ if(microframe_schedule)
-+ hcd->available_host_channels++;
-+ qh->channel = NULL;
-+ }
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ }
-+}
-+
-+/**
-+ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
-+ * and periodic schedules. The QTD associated with each URB is removed from
-+ * the schedule and freed. This function may be called when a disconnect is
-+ * detected or when the HCD is being stopped.
-+ */
-+static void kill_all_urbs(dwc_otg_hcd_t * hcd)
-+{
-+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
-+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
-+}
-+
-+/**
-+ * Start the connection timer. An OTG host is required to display a
-+ * message if the device does not connect within 10 seconds. The
-+ * timer is deleted if a port connect interrupt occurs before the
-+ * timer expires.
-+ */
-+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
-+{
-+ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
-+}
-+
-+/**
-+ * HCD Callback function for disconnect of the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_session_start_cb(void *p)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
-+ dwc_otg_hcd = p;
-+ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
-+ return 1;
-+}
-+
-+/**
-+ * HCD Callback function for starting the HCD when A-Cable is
-+ * connected.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_start_cb(void *p)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = p;
-+ dwc_otg_core_if_t *core_if;
-+ hprt0_data_t hprt0;
-+
-+ core_if = dwc_otg_hcd->core_if;
-+
-+ if (core_if->op_state == B_HOST) {
-+ /*
-+ * Reset the port. During a HNP mode switch the reset
-+ * needs to occur within 1ms and have a duration of at
-+ * least 50ms.
-+ */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtrst = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
-+ hcd_start_func, dwc_otg_hcd, 50,
-+ "start hcd");
-+
-+ return 1;
-+}
-+
-+/**
-+ * HCD Callback function for disconnect of the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_disconnect_cb(void *p)
-+{
-+ gintsts_data_t intr;
-+ dwc_otg_hcd_t *dwc_otg_hcd = p;
-+
-+ /*
-+ * Set status flags for the hub driver.
-+ */
-+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
-+ dwc_otg_hcd->flags.b.port_connect_status = 0;
-+ if(fiq_enable)
-+ local_fiq_disable();
-+ /*
-+ * Shutdown any transfers in process by clearing the Tx FIFO Empty
-+ * interrupt mask and status bits and disabling subsequent host
-+ * channel interrupts.
-+ */
-+ intr.d32 = 0;
-+ intr.b.nptxfempty = 1;
-+ intr.b.ptxfempty = 1;
-+ intr.b.hcintr = 1;
-+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
-+ intr.d32, 0);
-+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
-+ intr.d32, 0);
-+
-+ del_timers(dwc_otg_hcd);
-+
-+ /*
-+ * Turn off the vbus power only if the core has transitioned to device
-+ * mode. If still in host mode, need to keep power on to detect a
-+ * reconnection.
-+ */
-+ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
-+ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ DWC_PRINTF("Disconnect: PortPower off\n");
-+ hprt0.b.prtpwr = 0;
-+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
-+ hprt0.d32);
-+ }
-+
-+ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
-+ }
-+
-+ /* Respond with an error status to all URBs in the schedule. */
-+ kill_all_urbs(dwc_otg_hcd);
-+
-+ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
-+ /* Clean up any host channels that were in use. */
-+ int num_channels;
-+ int i;
-+ dwc_hc_t *channel;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hcchar_data_t hcchar;
-+
-+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
-+
-+ if (!dwc_otg_hcd->core_if->dma_enable) {
-+ /* Flush out any channel requests in slave mode. */
-+ for (i = 0; i < num_channels; i++) {
-+ channel = dwc_otg_hcd->hc_ptr_array[i];
-+ if (DWC_CIRCLEQ_EMPTY_ENTRY
-+ (channel, hc_list_entry)) {
-+ hc_regs =
-+ dwc_otg_hcd->core_if->
-+ host_if->hc_regs[i];
-+ hcchar.d32 =
-+ DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chen = 0;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ DWC_WRITE_REG32
-+ (&hc_regs->hcchar,
-+ hcchar.d32);
-+ }
-+ }
-+ }
-+ }
-+
-+ for (i = 0; i < num_channels; i++) {
-+ channel = dwc_otg_hcd->hc_ptr_array[i];
-+ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
-+ hc_regs =
-+ dwc_otg_hcd->core_if->host_if->hc_regs[i];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ /* Halt the channel. */
-+ hcchar.b.chdis = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar,
-+ hcchar.d32);
-+ }
-+
-+ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
-+ channel);
-+ DWC_CIRCLEQ_INSERT_TAIL
-+ (&dwc_otg_hcd->free_hc_list, channel,
-+ hc_list_entry);
-+ /*
-+ * Added for Descriptor DMA to prevent channel double cleanup
-+ * in release_channel_ddma(). Which called from ep_disable
-+ * when device disconnect.
-+ */
-+ channel->qh = NULL;
-+ }
-+ }
-+ if(fiq_fsm_enable) {
-+ for(i=0; i < 128; i++) {
-+ dwc_otg_hcd->hub_port[i] = 0;
-+ }
-+ }
-+
-+ }
-+
-+ if(fiq_enable)
-+ local_fiq_enable();
-+
-+ if (dwc_otg_hcd->fops->disconnect) {
-+ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * HCD Callback function for stopping the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_stop_cb(void *p)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = p;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
-+ dwc_otg_hcd_stop(dwc_otg_hcd);
-+ return 1;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * HCD Callback function for sleep of HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int dwc_otg_hcd_sleep_cb(void *p)
-+{
-+ dwc_otg_hcd_t *hcd = p;
-+
-+ dwc_otg_hcd_free_hc_from_lpm(hcd);
-+
-+ return 0;
-+}
-+#endif
-+
-+
-+/**
-+ * HCD Callback function for Remote Wakeup.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int dwc_otg_hcd_rem_wakeup_cb(void *p)
-+{
-+ dwc_otg_hcd_t *hcd = p;
-+
-+ if (hcd->core_if->lx_state == DWC_OTG_L2) {
-+ hcd->flags.b.port_suspend_change = 1;
-+ }
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ else {
-+ hcd->flags.b.port_l1_change = 1;
-+ }
-+#endif
-+ return 0;
-+}
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ */
-+void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
-+{
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
-+
-+ /*
-+ * The root hub should be disconnected before this function is called.
-+ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
-+ * and the QH lists (via ..._hcd_endpoint_disable).
-+ */
-+
-+ /* Turn off all host-specific interrupts. */
-+ dwc_otg_disable_host_interrupts(hcd->core_if);
-+
-+ /* Turn off the vbus power */
-+ DWC_PRINTF("PortPower off\n");
-+ hprt0.b.prtpwr = 0;
-+ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
-+ dwc_mdelay(1);
-+}
-+
-+int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
-+ int atomic_alloc)
-+{
-+ int retval = 0;
-+ uint8_t needs_scheduling = 0;
-+ dwc_otg_transaction_type_e tr_type;
-+ dwc_otg_qtd_t *qtd;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ hprt0_data_t hprt0 = { .d32 = 0 };
-+
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+ if (NULL == hcd->core_if) {
-+ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
-+ /* No longer connected. */
-+ return -DWC_E_INVALID;
-+ }
-+#endif
-+ if (!hcd->flags.b.port_connect_status) {
-+ /* No longer connected. */
-+ DWC_ERROR("Not connected\n");
-+ return -DWC_E_NO_DEVICE;
-+ }
-+
-+ /* Some core configurations cannot support LS traffic on a FS root port */
-+ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
-+ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
-+ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+ return -DWC_E_NO_DEVICE;
-+ }
-+ }
-+
-+ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
-+ if (qtd == NULL) {
-+ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+ if (qtd->urb == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ if (qtd->urb->priv == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+#endif
-+ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
-+ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
-+ if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
-+ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
-+ needs_scheduling = 0;
-+
-+ retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
-+ // creates a new queue in ep_handle if it doesn't exist already
-+ if (retval < 0) {
-+ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
-+ "Error status %d\n", retval);
-+ dwc_otg_hcd_qtd_free(qtd);
-+ return retval;
-+ }
-+
-+ if(needs_scheduling) {
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ }
-+ }
-+ return retval;
-+}
-+
-+int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_qtd_t *urb_qtd;
-+ BUG_ON(!hcd);
-+ BUG_ON(!dwc_otg_urb);
-+
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+
-+ if (hcd == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
-+ return -DWC_E_INVALID;
-+ }
-+ if (dwc_otg_urb == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
-+ return -DWC_E_INVALID;
-+ }
-+ if (dwc_otg_urb->qtd == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
-+ return -DWC_E_INVALID;
-+ }
-+ urb_qtd = dwc_otg_urb->qtd;
-+ BUG_ON(!urb_qtd);
-+ if (urb_qtd->qh == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
-+ return -DWC_E_INVALID;
-+ }
-+#else
-+ urb_qtd = dwc_otg_urb->qtd;
-+ BUG_ON(!urb_qtd);
-+#endif
-+ qh = urb_qtd->qh;
-+ BUG_ON(!qh);
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ if (urb_qtd->in_process) {
-+ dump_channel_info(hcd, qh);
-+ }
-+ }
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+ if (hcd->core_if == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
-+ return -DWC_E_INVALID;
-+ }
-+#endif
-+ if (urb_qtd->in_process && qh->channel) {
-+ /* The QTD is in process (it has been assigned to a channel). */
-+ if (hcd->flags.b.port_connect_status) {
-+ int n = qh->channel->hc_num;
-+ /*
-+ * If still connected (i.e. in host mode), halt the
-+ * channel so it can be used for other transfers. If
-+ * no longer connected, the host registers can't be
-+ * written to halt the channel since the core is in
-+ * device mode.
-+ */
-+ /* In FIQ FSM mode, we need to shut down carefully.
-+ * The FIQ may attempt to restart a disabled channel */
-+ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
-+ qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
-+ qh->channel->halt_pending = 1;
-+ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
-+ } else {
-+ dwc_otg_hc_halt(hcd->core_if, qh->channel,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE);
-+ }
-+ }
-+ }
-+
-+ /*
-+ * Free the QTD and clean up the associated QH. Leave the QH in the
-+ * schedule if it has any remaining QTDs.
-+ */
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
-+ "delete %sQueue handler\n",
-+ hcd->core_if->dma_desc_enable?"DMA ":"");
-+ if (!hcd->core_if->dma_desc_enable) {
-+ uint8_t b = urb_qtd->in_process;
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
-+ if (b) {
-+ dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
-+ qh->channel = NULL;
-+ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ }
-+ } else {
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
-+ }
-+ return 0;
-+}
-+
-+int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
-+ int retry)
-+{
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ int retval = 0;
-+ dwc_irqflags_t flags;
-+
-+ if (retry < 0) {
-+ retval = -DWC_E_INVALID;
-+ goto done;
-+ }
-+
-+ if (!qh) {
-+ retval = -DWC_E_INVALID;
-+ goto done;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+
-+ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ retry--;
-+ dwc_msleep(5);
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ }
-+
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ /*
-+ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
-+ * and qh_free to prevent stack dump on DWC_DMA_FREE() with
-+ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
-+ * and dwc_otg_hcd_frame_list_alloc().
-+ */
-+ dwc_otg_hcd_qh_free(hcd, qh);
-+
-+done:
-+ return retval;
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ int retval = 0;
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ if (!qh)
-+ return -DWC_E_INVALID;
-+
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ return retval;
-+}
-+#endif
-+
-+/**
-+ * HCD Callback structure for handling mode switching.
-+ */
-+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
-+ .start = dwc_otg_hcd_start_cb,
-+ .stop = dwc_otg_hcd_stop_cb,
-+ .disconnect = dwc_otg_hcd_disconnect_cb,
-+ .session_start = dwc_otg_hcd_session_start_cb,
-+ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ .sleep = dwc_otg_hcd_sleep_cb,
-+#endif
-+ .p = 0,
-+};
-+
-+/**
-+ * Reset tasklet function
-+ */
-+static void reset_tasklet_func(void *data)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
-+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+ hprt0_data_t hprt0;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtrst = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ dwc_mdelay(60);
-+
-+ hprt0.b.prtrst = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ dwc_otg_hcd->flags.b.port_reset_change = 1;
-+}
-+
-+static void completion_tasklet_func(void *ptr)
-+{
-+ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
-+ struct urb *urb;
-+ urb_tq_entry_t *item;
-+ dwc_irqflags_t flags;
-+
-+ /* This could just be spin_lock_irq */
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
-+ item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
-+ urb = item->urb;
-+ DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
-+ urb_tq_entries);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ DWC_FREE(item);
-+
-+ usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
-+
-+
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ return;
-+}
-+
-+static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
-+{
-+ dwc_list_link_t *item;
-+ dwc_otg_qh_t *qh;
-+ dwc_irqflags_t flags;
-+
-+ if (!qh_list->next) {
-+ /* The list hasn't been initialized yet. */
-+ return;
-+ }
-+ /*
-+ * Hold spinlock here. Not needed in that case if bellow
-+ * function is being called from ISR
-+ */
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ /* Ensure there are no QTDs or URBs left. */
-+ kill_urbs_in_qh_list(hcd, qh_list);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+
-+ DWC_LIST_FOREACH(item, qh_list) {
-+ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+ dwc_otg_hcd_qh_remove_and_free(hcd, qh);
-+ }
-+}
-+
-+/**
-+ * Exit from Hibernation if Host did not detect SRP from connected SRP capable
-+ * Device during SRP time by host power up.
-+ */
-+void dwc_otg_hcd_power_up(void *ptr)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return;
-+ }
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Enable VBUS */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+}
-+
-+void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
-+{
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+ struct fiq_dma_blob *blob = hcd->fiq_dmab;
-+ int i;
-+
-+ st->fsm = FIQ_PASSTHROUGH;
-+ st->hcchar_copy.d32 = 0;
-+ st->hcsplt_copy.d32 = 0;
-+ st->hcint_copy.d32 = 0;
-+ st->hcintmsk_copy.d32 = 0;
-+ st->hctsiz_copy.d32 = 0;
-+ st->hcdma_copy.d32 = 0;
-+ st->nr_errors = 0;
-+ st->hub_addr = 0;
-+ st->port_addr = 0;
-+ st->expected_uframe = 0;
-+ st->nrpackets = 0;
-+ st->dma_info.index = 0;
-+ for (i = 0; i < 6; i++)
-+ st->dma_info.slot_len[i] = 255;
-+ st->hs_isoc_info.index = 0;
-+ st->hs_isoc_info.iso_desc = NULL;
-+ st->hs_isoc_info.nrframes = 0;
-+
-+ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
-+}
-+
-+/**
-+ * Frees secondary storage associated with the dwc_otg_hcd structure contained
-+ * in the struct usb_hcd field.
-+ */
-+static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int i;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
-+
-+ del_timers(dwc_otg_hcd);
-+
-+ /* Free memory for QH/QTD lists */
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
-+
-+ /* Free memory for the host channels. */
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
-+
-+#ifdef DEBUG
-+ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
-+ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
-+ }
-+#endif
-+ if (hc != NULL) {
-+ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
-+ i, hc);
-+ DWC_FREE(hc);
-+ }
-+ }
-+
-+ if (dwc_otg_hcd->core_if->dma_enable) {
-+ if (dwc_otg_hcd->status_buf_dma) {
-+ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
-+ dwc_otg_hcd->status_buf,
-+ dwc_otg_hcd->status_buf_dma);
-+ }
-+ } else if (dwc_otg_hcd->status_buf != NULL) {
-+ DWC_FREE(dwc_otg_hcd->status_buf);
-+ }
-+ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock);
-+ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
-+ /* Set core_if's lock pointer to NULL */
-+ dwc_otg_hcd->core_if->lock = NULL;
-+
-+ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
-+ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
-+ DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
-+ DWC_FREE(dwc_otg_hcd->fiq_state);
-+
-+#ifdef DWC_DEV_SRPCAP
-+ if (dwc_otg_hcd->core_if->power_down == 2 &&
-+ dwc_otg_hcd->core_if->pwron_timer) {
-+ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
-+ }
-+#endif
-+ DWC_FREE(dwc_otg_hcd);
-+}
-+
-+int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
-+
-+int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
-+{
-+ int retval = 0;
-+ int num_channels;
-+ int i;
-+ dwc_hc_t *channel;
-+
-+ hcd->lock = DWC_SPINLOCK_ALLOC();
-+ hcd->channel_lock = DWC_SPINLOCK_ALLOC();
-+ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
-+ hcd, core_if);
-+ if (!hcd->lock) {
-+ DWC_ERROR("Could not allocate lock for pcd");
-+ DWC_FREE(hcd);
-+ retval = -DWC_E_NO_MEMORY;
-+ goto out;
-+ }
-+ hcd->core_if = core_if;
-+
-+ /* Register the HCD CIL Callbacks */
-+ dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
-+ &hcd_cil_callbacks, hcd);
-+
-+ /* Initialize the non-periodic schedule. */
-+ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
-+ DWC_LIST_INIT(&hcd->non_periodic_sched_active);
-+
-+ /* Initialize the periodic schedule. */
-+ DWC_LIST_INIT(&hcd->periodic_sched_inactive);
-+ DWC_LIST_INIT(&hcd->periodic_sched_ready);
-+ DWC_LIST_INIT(&hcd->periodic_sched_assigned);
-+ DWC_LIST_INIT(&hcd->periodic_sched_queued);
-+ DWC_TAILQ_INIT(&hcd->completed_urb_list);
-+ /*
-+ * Create a host channel descriptor for each host channel implemented
-+ * in the controller. Initialize the channel descriptor array.
-+ */
-+ DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
-+ for (i = 0; i < num_channels; i++) {
-+ channel = DWC_ALLOC(sizeof(dwc_hc_t));
-+ if (channel == NULL) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: host channel allocation failed\n",
-+ __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+ channel->hc_num = i;
-+ hcd->hc_ptr_array[i] = channel;
-+#ifdef DEBUG
-+ hcd->core_if->hc_xfer_timer[i] =
-+ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
-+ &hcd->core_if->hc_xfer_info[i]);
-+#endif
-+ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
-+ channel);
-+ }
-+
-+ if (fiq_enable) {
-+ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
-+ if (!hcd->fiq_state) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
-+
-+ for (i = 0; i < num_channels; i++) {
-+ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
-+ }
-+ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
-+
-+ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
-+ if (!hcd->fiq_stack) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+ hcd->fiq_stack->magic1 = 0xDEADBEEF;
-+ hcd->fiq_stack->magic2 = 0xD00DFEED;
-+ hcd->fiq_state->gintmsk_saved.d32 = ~0;
-+ hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
-+
-+ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
-+ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
-+ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
-+ * moderately readable array casts.
-+ */
-+ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
-+ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
-+ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
-+ sizeof(struct fiq_dma_channel) * num_channels);
-+
-+ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
-+
-+ /* pointer for debug in fiq_print */
-+ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
-+ if (fiq_fsm_enable) {
-+ int i;
-+ for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
-+ dwc_otg_cleanup_fiq_channel(hcd, i);
-+ }
-+ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
-+ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
-+ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
-+ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
-+ (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
-+ }
-+ }
-+
-+ /* Initialize the Connection timeout timer. */
-+ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
-+ dwc_otg_hcd_connect_timeout, 0);
-+
-+ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
-+ if (microframe_schedule)
-+ init_hcd_usecs(hcd);
-+
-+ /* Initialize reset tasklet. */
-+ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
-+
-+ hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
-+ completion_tasklet_func, hcd);
-+#ifdef DWC_DEV_SRPCAP
-+ if (hcd->core_if->power_down == 2) {
-+ /* Initialize Power on timer for Host power up in case hibernation */
-+ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
-+ dwc_otg_hcd_power_up, core_if);
-+ }
-+#endif
-+
-+ /*
-+ * Allocate space for storing data on status transactions. Normally no
-+ * data is sent, but this space acts as a bit bucket. This must be
-+ * done after usb_add_hcd since that function allocates the DMA buffer
-+ * pool.
-+ */
-+ if (hcd->core_if->dma_enable) {
-+ hcd->status_buf =
-+ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
-+ &hcd->status_buf_dma);
-+ } else {
-+ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
-+ }
-+ if (!hcd->status_buf) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: status_buf allocation failed\n", __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+
-+ hcd->otg_port = 1;
-+ hcd->frame_list = NULL;
-+ hcd->frame_list_dma = 0;
-+ hcd->periodic_qh_count = 0;
-+
-+ DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
-+#ifdef FIQ_DEBUG
-+ DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
-+#endif
-+
-+out:
-+ return retval;
-+}
-+
-+void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
-+{
-+ /* Turn off all host-specific interrupts. */
-+ dwc_otg_disable_host_interrupts(hcd->core_if);
-+
-+ dwc_otg_hcd_free(hcd);
-+}
-+
-+/**
-+ * Initializes dynamic portions of the DWC_otg HCD state.
-+ */
-+static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
-+{
-+ int num_channels;
-+ int i;
-+ dwc_hc_t *channel;
-+ dwc_hc_t *channel_tmp;
-+
-+ hcd->flags.d32 = 0;
-+
-+ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
-+ if (!microframe_schedule) {
-+ hcd->non_periodic_channels = 0;
-+ hcd->periodic_channels = 0;
-+ } else {
-+ hcd->available_host_channels = hcd->core_if->core_params->host_channels;
-+ }
-+ /*
-+ * Put all channels in the free channel list and clean up channel
-+ * states.
-+ */
-+ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
-+ &hcd->free_hc_list, hc_list_entry) {
-+ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
-+ }
-+
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ for (i = 0; i < num_channels; i++) {
-+ channel = hcd->hc_ptr_array[i];
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
-+ hc_list_entry);
-+ dwc_otg_hc_cleanup(hcd->core_if, channel);
-+ }
-+
-+ /* Initialize the DWC core for host mode operation. */
-+ dwc_otg_core_host_init(hcd->core_if);
-+
-+ /* Set core_if's lock pointer to the hcd->lock */
-+ hcd->core_if->lock = hcd->lock;
-+}
-+
-+/**
-+ * Assigns transactions from a QTD to a free host channel and initializes the
-+ * host channel to perform the transactions. The host channel is removed from
-+ * the free list.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param qh Transactions from the first QTD for this QH are selected and
-+ * assigned to a free host channel.
-+ */
-+static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ dwc_hc_t *hc;
-+ dwc_otg_qtd_t *qtd;
-+ dwc_otg_hcd_urb_t *urb;
-+ void* ptr = NULL;
-+
-+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+ urb = qtd->urb;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
-+
-+ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
-+ urb->actual_length = urb->length;
-+
-+
-+ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
-+
-+ /* Remove the host channel from the free list. */
-+ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+ qh->channel = hc;
-+
-+ qtd->in_process = 1;
-+
-+ /*
-+ * Use usb_pipedevice to determine device address. This address is
-+ * 0 before the SET_ADDRESS command and the correct address afterward.
-+ */
-+ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
-+ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
-+ hc->speed = qh->dev_speed;
-+ hc->max_packet = dwc_max_packet(qh->maxp);
-+
-+ hc->xfer_started = 0;
-+ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
-+ hc->error_state = (qtd->error_count > 0);
-+ hc->halt_on_queue = 0;
-+ hc->halt_pending = 0;
-+ hc->requests = 0;
-+
-+ /*
-+ * The following values may be modified in the transfer type section
-+ * below. The xfer_len value may be reduced when the transfer is
-+ * started to accommodate the max widths of the XferSize and PktCnt
-+ * fields in the HCTSIZn register.
-+ */
-+
-+ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
-+ if (hc->ep_is_in) {
-+ hc->do_ping = 0;
-+ } else {
-+ hc->do_ping = qh->ping_state;
-+ }
-+
-+ hc->data_pid_start = qh->data_toggle;
-+ hc->multi_count = 1;
-+
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
-+
-+ /* For non-dword aligned case */
-+ if (((unsigned long)hc->xfer_buff & 0x3)
-+ && !hcd->core_if->dma_desc_enable) {
-+ ptr = (uint8_t *) urb->buf + urb->actual_length;
-+ }
-+ } else {
-+ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
-+ }
-+ hc->xfer_len = urb->length - urb->actual_length;
-+ hc->xfer_count = 0;
-+
-+ /*
-+ * Set the split attributes
-+ */
-+ hc->do_split = 0;
-+ if (qh->do_split) {
-+ uint32_t hub_addr, port_addr;
-+ hc->do_split = 1;
-+ hc->xact_pos = qtd->isoc_split_pos;
-+ /* We don't need to do complete splits anymore */
-+// if(fiq_fsm_enable)
-+ if (0)
-+ hc->complete_split = qtd->complete_split = 0;
-+ else
-+ hc->complete_split = qtd->complete_split;
-+
-+ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
-+ hc->hub_addr = (uint8_t) hub_addr;
-+ hc->port_addr = (uint8_t) port_addr;
-+ }
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
-+ case UE_CONTROL:
-+ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
-+ switch (qtd->control_phase) {
-+ case DWC_OTG_CONTROL_SETUP:
-+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
-+ hc->do_ping = 0;
-+ hc->ep_is_in = 0;
-+ hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) urb->setup_dma;
-+ } else {
-+ hc->xfer_buff = (uint8_t *) urb->setup_packet;
-+ }
-+ hc->xfer_len = 8;
-+ ptr = NULL;
-+ break;
-+ case DWC_OTG_CONTROL_DATA:
-+ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
-+ hc->data_pid_start = qtd->data_toggle;
-+ break;
-+ case DWC_OTG_CONTROL_STATUS:
-+ /*
-+ * Direction is opposite of data direction or IN if no
-+ * data.
-+ */
-+ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
-+ if (urb->length == 0) {
-+ hc->ep_is_in = 1;
-+ } else {
-+ hc->ep_is_in =
-+ dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
-+ }
-+ if (hc->ep_is_in) {
-+ hc->do_ping = 0;
-+ }
-+
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+
-+ hc->xfer_len = 0;
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
-+ } else {
-+ hc->xfer_buff = (uint8_t *) hcd->status_buf;
-+ }
-+ ptr = NULL;
-+ break;
-+ }
-+ break;
-+ case UE_BULK:
-+ hc->ep_type = DWC_OTG_EP_TYPE_BULK;
-+ break;
-+ case UE_INTERRUPT:
-+ hc->ep_type = DWC_OTG_EP_TYPE_INTR;
-+ break;
-+ case UE_ISOCHRONOUS:
-+ {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+ hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
-+
-+ if (hcd->core_if->dma_desc_enable)
-+ break;
-+
-+ frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
-+
-+ frame_desc->status = 0;
-+
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) urb->dma;
-+ } else {
-+ hc->xfer_buff = (uint8_t *) urb->buf;
-+ }
-+ hc->xfer_buff +=
-+ frame_desc->offset + qtd->isoc_split_offset;
-+ hc->xfer_len =
-+ frame_desc->length - qtd->isoc_split_offset;
-+
-+ /* For non-dword aligned buffers */
-+ if (((unsigned long)hc->xfer_buff & 0x3)
-+ && hcd->core_if->dma_enable) {
-+ ptr =
-+ (uint8_t *) urb->buf + frame_desc->offset +
-+ qtd->isoc_split_offset;
-+ } else
-+ ptr = NULL;
-+
-+ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
-+ if (hc->xfer_len <= 188) {
-+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+ } else {
-+ hc->xact_pos =
-+ DWC_HCSPLIT_XACTPOS_BEGIN;
-+ }
-+ }
-+ }
-+ break;
-+ }
-+ /* non DWORD-aligned buffer case */
-+ if (ptr) {
-+ uint32_t buf_size;
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ buf_size = hcd->core_if->core_params->max_transfer_size;
-+ } else {
-+ buf_size = 4096;
-+ }
-+ if (!qh->dw_align_buf) {
-+ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
-+ &qh->dw_align_buf_dma);
-+ if (!qh->dw_align_buf) {
-+ DWC_ERROR
-+ ("%s: Failed to allocate memory to handle "
-+ "non-dword aligned buffer case\n",
-+ __func__);
-+ return;
-+ }
-+ }
-+ if (!hc->ep_is_in) {
-+ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
-+ }
-+ hc->align_buff = qh->dw_align_buf_dma;
-+ } else {
-+ hc->align_buff = 0;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * This value may be modified when the transfer is started to
-+ * reflect the actual transfer length.
-+ */
-+ hc->multi_count = dwc_hb_mult(qh->maxp);
-+ }
-+
-+ if (hcd->core_if->dma_desc_enable)
-+ hc->desc_list_addr = qh->desc_list_dma;
-+
-+ dwc_otg_hc_init(hcd->core_if, hc);
-+ hc->qh = qh;
-+}
-+
-+
-+/**
-+ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
-+ * @qh: pointer to the endpoint's queue head
-+ *
-+ * Transaction start/end control flow is grafted onto the existing dwc_otg
-+ * mechanisms, to avoid spaghettifying the functions more than they already are.
-+ * This function's eligibility check is altered by debug parameter.
-+ *
-+ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
-+ */
-+
-+int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh)
-+{
-+ if (qh->do_split) {
-+ switch (qh->ep_type) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ if (fiq_fsm_mask & (1 << 0))
-+ return 1;
-+ break;
-+ case UE_INTERRUPT:
-+ case UE_ISOCHRONOUS:
-+ if (fiq_fsm_mask & (1 << 1))
-+ return 1;
-+ break;
-+ default:
-+ break;
-+ }
-+ } else if (qh->ep_type == UE_ISOCHRONOUS) {
-+ if (fiq_fsm_mask & (1 << 2)) {
-+ /* HS ISOCH support. We test for compatibility:
-+ * - DWORD aligned buffers
-+ * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
-+ * If yes, then the fsm enqueue function will handle the state machine setup.
-+ */
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs;
-+ int nr_iso_frames = urb->packet_count;
-+ int i;
-+ uint32_t ptr;
-+
-+ if (nr_iso_frames < 2)
-+ return 0;
-+ for (i = 0; i < nr_iso_frames; i++) {
-+ ptr = urb->dma + iso_descs[i]->offset;
-+ if (ptr & 0x3) {
-+ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset."
-+ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n",
-+ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num);
-+ return 0;
-+ }
-+ }
-+ return 1;
-+ }
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * Periodic split transactions are transmitted modulo 188 bytes.
-+ * This necessitates slicing data up into buckets for isochronous out
-+ * and fixing up the DMA address for all IN transfers.
-+ *
-+ * Returns 1 if the DMA bounce buffers have been used, 0 if the default
-+ * HC buffer has been used.
-+ */
-+int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
-+ {
-+ int frame_length, i = 0;
-+ uint8_t *ptr = NULL;
-+ dwc_hc_t *hc = qh->channel;
-+ struct fiq_dma_blob *blob;
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+ for (i = 0; i < 6; i++) {
-+ st->dma_info.slot_len[i] = 255;
-+ }
-+ st->dma_info.index = 0;
-+ i = 0;
-+ if (hc->ep_is_in) {
-+ /*
-+ * Set dma_regs to bounce buffer. FIQ will update the
-+ * state depending on transaction progress.
-+ */
-+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
-+ /* Calculate the max number of CSPLITS such that the FIQ can time out
-+ * a transaction if it fails.
-+ */
-+ frame_length = st->hcchar_copy.b.mps;
-+ do {
-+ i++;
-+ frame_length -= 188;
-+ } while (frame_length >= 0);
-+ st->nrpackets = i;
-+ return 1;
-+ } else {
-+ if (qh->ep_type == UE_ISOCHRONOUS) {
-+
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ frame_length = frame_desc->length;
-+
-+ /* Virtual address for bounce buffers */
-+ blob = hcd->fiq_dmab;
-+
-+ ptr = qtd->urb->buf + frame_desc->offset;
-+ if (frame_length == 0) {
-+ /*
-+ * for isochronous transactions, we must still transmit a packet
-+ * even if the length is zero.
-+ */
-+ st->dma_info.slot_len[0] = 0;
-+ st->nrpackets = 1;
-+ } else {
-+ do {
-+ if (frame_length <= 188) {
-+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
-+ st->dma_info.slot_len[i] = frame_length;
-+ ptr += frame_length;
-+ } else {
-+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
-+ st->dma_info.slot_len[i] = 188;
-+ ptr += 188;
-+ }
-+ i++;
-+ frame_length -= 188;
-+ } while (frame_length > 0);
-+ st->nrpackets = i;
-+ }
-+ ptr = qtd->urb->buf + frame_desc->offset;
-+ /* Point the HC at the DMA address of the bounce buffers */
-+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
-+
-+ /* fixup xfersize to the actual packet size */
-+ st->hctsiz_copy.b.pid = 0;
-+ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
-+ return 1;
-+ } else {
-+ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
-+ return 0;
-+ }
-+ }
-+}
-+
-+/*
-+ * Pushing a periodic request into the queue near the EOF1 point
-+ * in a microframe causes erroneous behaviour (frmovrun) interrupt.
-+ * Usually, the request goes out on the bus causing a transfer but
-+ * the core does not transfer the data to memory.
-+ * This guard interval (in number of 60MHz clocks) is required which
-+ * must cater for CPU latency between reading the value and enabling
-+ * the channel.
-+ */
-+#define PERIODIC_FRREM_BACKOFF 1000
-+
-+int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+ dwc_hc_t *hc = qh->channel;
-+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+ int frame;
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
-+ int xfer_len, nrpackets;
-+ hcdma_data_t hcdma;
-+ hfnum_data_t hfnum;
-+
-+ if (st->fsm != FIQ_PASSTHROUGH)
-+ return 0;
-+
-+ st->nr_errors = 0;
-+
-+ st->hcchar_copy.d32 = 0;
-+ st->hcchar_copy.b.mps = hc->max_packet;
-+ st->hcchar_copy.b.epdir = hc->ep_is_in;
-+ st->hcchar_copy.b.devaddr = hc->dev_addr;
-+ st->hcchar_copy.b.epnum = hc->ep_num;
-+ st->hcchar_copy.b.eptype = hc->ep_type;
-+
-+ st->hcintmsk_copy.b.chhltd = 1;
-+
-+ frame = dwc_otg_hcd_get_frame_number(hcd);
-+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
-+
-+ st->hcchar_copy.b.lspddev = 0;
-+ /* Enable the channel later as a final register write. */
-+
-+ st->hcsplt_copy.d32 = 0;
-+
-+ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
-+ st->hs_isoc_info.nrframes = qtd->urb->packet_count;
-+ /* grab the next DMA address offset from the array */
-+ st->hcdma_copy.d32 = qtd->urb->dma;
-+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
-+
-+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
-+ * the core needs to be told to send the correct number. Caution: for IN transfers,
-+ * this is always set to the maximum size of the endpoint. */
-+ xfer_len = st->hs_isoc_info.iso_desc[0].length;
-+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
-+ if (nrpackets == 0)
-+ nrpackets = 1;
-+ st->hcchar_copy.b.multicnt = nrpackets;
-+ st->hctsiz_copy.b.pktcnt = nrpackets;
-+
-+ /* Initial PID also needs to be set */
-+ if (st->hcchar_copy.b.epdir == 0) {
-+ st->hctsiz_copy.b.xfersize = xfer_len;
-+ switch (st->hcchar_copy.b.multicnt) {
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_MDATA;
-+ break;
-+ }
-+
-+ } else {
-+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+ switch (st->hcchar_copy.b.multicnt) {
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA1;
-+ break;
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA2;
-+ break;
-+ }
-+ }
-+
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
-+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+ local_fiq_disable();
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
-+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
-+ /* Prevent queueing near EOF1. Bad things happen if a periodic
-+ * split transaction is queued very close to EOF.
-+ */
-+ st->fsm = FIQ_HS_ISOC_SLEEPING;
-+ } else {
-+ st->fsm = FIQ_HS_ISOC_TURBO;
-+ st->hcchar_copy.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ }
-+ mb();
-+ st->hcchar_copy.b.chen = 0;
-+ local_fiq_enable();
-+ return 0;
-+}
-+
-+
-+/**
-+ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * This overrides the dwc_otg driver's normal method of queueing a transaction.
-+ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
-+ * for the nominated host channel.
-+ *
-+ * For periodic transfers, it also peeks at the FIQ state to see if an immediate
-+ * start is possible. If not, then the FIQ is left to start the transfer.
-+ */
-+int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+ int start_immediate = 1, i;
-+ hfnum_data_t hfnum;
-+ dwc_hc_t *hc = qh->channel;
-+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
-+ int hub_addr, port_addr, frame, uframe;
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
-+
-+ if (st->fsm != FIQ_PASSTHROUGH)
-+ return 0;
-+ st->nr_errors = 0;
-+
-+ st->hcchar_copy.d32 = 0;
-+ st->hcchar_copy.b.mps = hc->max_packet;
-+ st->hcchar_copy.b.epdir = hc->ep_is_in;
-+ st->hcchar_copy.b.devaddr = hc->dev_addr;
-+ st->hcchar_copy.b.epnum = hc->ep_num;
-+ st->hcchar_copy.b.eptype = hc->ep_type;
-+ if (hc->ep_type & 0x1) {
-+ if (hc->ep_is_in)
-+ st->hcchar_copy.b.multicnt = 3;
-+ else
-+ /* Docs say set this to 1, but driver sets to 0! */
-+ st->hcchar_copy.b.multicnt = 0;
-+ } else {
-+ st->hcchar_copy.b.multicnt = 1;
-+ st->hcchar_copy.b.oddfrm = 0;
-+ }
-+ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
-+ /* Enable the channel later as a final register write. */
-+
-+ st->hcsplt_copy.d32 = 0;
-+ if(qh->do_split) {
-+ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
-+ st->hcsplt_copy.b.compsplt = 0;
-+ st->hcsplt_copy.b.spltena = 1;
-+ // XACTPOS is for isoc-out only but needs initialising anyway.
-+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
-+ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
-+ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
-+ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
-+ * will update as necessary.
-+ */
-+ if (hc->xfer_len > 188) {
-+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
-+ }
-+ }
-+ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
-+ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
-+ st->hub_addr = hub_addr;
-+ st->port_addr = port_addr;
-+ }
-+
-+ st->hctsiz_copy.d32 = 0;
-+ st->hctsiz_copy.b.dopng = 0;
-+ st->hctsiz_copy.b.pid = hc->data_pid_start;
-+
-+ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+ hc->xfer_len = hc->max_packet;
-+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+ hc->xfer_len = 188;
-+ }
-+ st->hctsiz_copy.b.xfersize = hc->xfer_len;
-+
-+ st->hctsiz_copy.b.pktcnt = 1;
-+
-+ if (hc->ep_type & 0x1) {
-+ /*
-+ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
-+ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
-+ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
-+ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
-+ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
-+ * must not touch internal driver state.
-+ */
-+ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
-+ if (hc->align_buff) {
-+ st->hcdma_copy.d32 = hc->align_buff;
-+ } else {
-+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+ }
-+ }
-+ } else {
-+ if (hc->align_buff) {
-+ st->hcdma_copy.d32 = hc->align_buff;
-+ } else {
-+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+ }
-+ }
-+ /* The FIQ depends upon no other interrupts being enabled except channel halt.
-+ * Fixup channel interrupt mask. */
-+ st->hcintmsk_copy.d32 = 0;
-+ st->hcintmsk_copy.b.chhltd = 1;
-+ st->hcintmsk_copy.b.ahberr = 1;
-+
-+ /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
-+ * as Control puts the transfer into the non-periodic request queue and the
-+ * non-periodic handler in the hub. Makes things lots easier.
-+ */
-+ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
-+ st->hcchar_copy.b.multicnt = 0;
-+ st->hcchar_copy.b.oddfrm = 0;
-+ st->hcchar_copy.b.eptype = UE_CONTROL;
-+ if (hc->align_buff) {
-+ st->hcdma_copy.d32 = hc->align_buff;
-+ } else {
-+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+ }
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
-+
-+ local_fiq_disable();
-+ mb();
-+
-+ if (hc->ep_type & 0x1) {
-+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+ frame = (hfnum.b.frnum & ~0x7) >> 3;
-+ uframe = hfnum.b.frnum & 0x7;
-+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
-+ /* Prevent queueing near EOF1. Bad things happen if a periodic
-+ * split transaction is queued very close to EOF.
-+ */
-+ start_immediate = 0;
-+ } else if (uframe == 5) {
-+ start_immediate = 0;
-+ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
-+ start_immediate = 0;
-+ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
-+ start_immediate = 0;
-+ } else {
-+ /* Search through all host channels to determine if a transaction
-+ * is currently in progress */
-+ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
-+ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
-+ continue;
-+ switch (hcd->fiq_state->channel[i].fsm) {
-+ /* TT is reserved for channels that are in the middle of a periodic
-+ * split transaction.
-+ */
-+ case FIQ_PER_SSPLIT_STARTED:
-+ case FIQ_PER_CSPLIT_WAIT:
-+ case FIQ_PER_CSPLIT_NYET1:
-+ case FIQ_PER_CSPLIT_POLL:
-+ case FIQ_PER_ISO_OUT_ACTIVE:
-+ case FIQ_PER_ISO_OUT_LAST:
-+ if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
-+ hcd->fiq_state->channel[i].port_addr == port_addr) {
-+ start_immediate = 0;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ if (!start_immediate)
-+ break;
-+ }
-+ }
-+ }
-+ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
-+ start_immediate = 1;
-+
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
-+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
-+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
-+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
-+ switch (hc->ep_type) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ st->fsm = FIQ_NP_SSPLIT_STARTED;
-+ break;
-+ case UE_ISOCHRONOUS:
-+ if (hc->ep_is_in) {
-+ if (start_immediate) {
-+ st->fsm = FIQ_PER_SSPLIT_STARTED;
-+ } else {
-+ st->fsm = FIQ_PER_SSPLIT_QUEUED;
-+ }
-+ } else {
-+ if (start_immediate) {
-+ /* Single-isoc OUT packets don't require FIQ involvement */
-+ if (st->nrpackets == 1) {
-+ st->fsm = FIQ_PER_ISO_OUT_LAST;
-+ } else {
-+ st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ }
-+ } else {
-+ st->fsm = FIQ_PER_ISO_OUT_PENDING;
-+ }
-+ }
-+ break;
-+ case UE_INTERRUPT:
-+ if (fiq_fsm_mask & 0x8) {
-+ st->fsm = FIQ_NP_SSPLIT_STARTED;
-+ } else if (start_immediate) {
-+ st->fsm = FIQ_PER_SSPLIT_STARTED;
-+ } else {
-+ st->fsm = FIQ_PER_SSPLIT_QUEUED;
-+ }
-+ default:
-+ break;
-+ }
-+ if (start_immediate) {
-+ /* Set the oddfrm bit as close as possible to actual queueing */
-+ frame = dwc_otg_hcd_get_frame_number(hcd);
-+ st->expected_uframe = (frame + 1) & 0x3FFF;
-+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
-+ st->hcchar_copy.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ }
-+ mb();
-+ local_fiq_enable();
-+ return 0;
-+}
-+
-+
-+/**
-+ * This function selects transactions from the HCD transfer schedule and
-+ * assigns them to available host channels. It is called from HCD interrupt
-+ * handler functions.
-+ *
-+ * @param hcd The HCD state structure.
-+ *
-+ * @return The types of new transactions that were assigned to host channels.
-+ */
-+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
-+{
-+ dwc_list_link_t *qh_ptr;
-+ dwc_otg_qh_t *qh;
-+ int num_channels;
-+ dwc_irqflags_t flags;
-+ dwc_spinlock_t *channel_lock = hcd->channel_lock;
-+ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
-+
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_per_scheduled = 0;
-+ last_sel_trans_num_nonper_scheduled = 0;
-+ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
-+#endif /* DEBUG_HOST_CHANNELS */
-+
-+ /* Process entries in the periodic ready list. */
-+ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
-+
-+ while (qh_ptr != &hcd->periodic_sched_ready &&
-+ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+
-+ if (microframe_schedule) {
-+ // Make sure we leave one channel for non periodic transactions.
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ if (hcd->available_host_channels <= 1) {
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ break;
-+ }
-+ hcd->available_host_channels--;
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_per_scheduled++;
-+#endif /* DEBUG_HOST_CHANNELS */
-+ }
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+ assign_and_init_hc(hcd, qh);
-+
-+ /*
-+ * Move the QH from the periodic ready schedule to the
-+ * periodic assigned schedule.
-+ */
-+ qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+ &qh->qh_list_entry);
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ }
-+
-+ /*
-+ * Process entries in the inactive portion of the non-periodic
-+ * schedule. Some free host channels may not be used if they are
-+ * reserved for periodic transfers.
-+ */
-+ qh_ptr = hcd->non_periodic_sched_inactive.next;
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ while (qh_ptr != &hcd->non_periodic_sched_inactive &&
-+ (microframe_schedule || hcd->non_periodic_channels <
-+ num_channels - hcd->periodic_channels) &&
-+ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+ /*
-+ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
-+ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
-+ * cheeky devices that just hold off using NAKs
-+ */
-+ if (nak_holdoff && qh->do_split) {
-+ if (qh->nak_frame != 0xffff) {
-+ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
-+ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
-+ if (dwc_frame_num_le(frame, next_frame)) {
-+ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
-+ hcd->fiq_state->next_sched_frame = next_frame;
-+ }
-+ qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+ continue;
-+ } else {
-+ qh->nak_frame = 0xFFFF;
-+ }
-+ }
-+ }
-+
-+ if (microframe_schedule) {
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ if (hcd->available_host_channels < 1) {
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ break;
-+ }
-+ hcd->available_host_channels--;
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_nonper_scheduled++;
-+#endif /* DEBUG_HOST_CHANNELS */
-+ }
-+
-+ assign_and_init_hc(hcd, qh);
-+
-+ /*
-+ * Move the QH from the non-periodic inactive schedule to the
-+ * non-periodic active schedule.
-+ */
-+ qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
-+ &qh->qh_list_entry);
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+
-+
-+ if (!microframe_schedule)
-+ hcd->non_periodic_channels++;
-+ }
-+ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
-+ * stop the FIQ from kicking us. We could potentially still have elements here if we
-+ * ran out of host channels.
-+ */
-+ if (fiq_enable) {
-+ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
-+ hcd->fiq_state->kick_np_queues = 0;
-+ } else {
-+ /* For each entry remaining in the NP inactive queue,
-+ * if this a NAK'd retransmit then don't set the kick flag.
-+ */
-+ if(nak_holdoff) {
-+ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+ if (qh->nak_frame == 0xFFFF) {
-+ hcd->fiq_state->kick_np_queues = 1;
-+ }
-+ }
-+ }
-+ }
-+ }
-+ if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
-+ ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
-+
-+ if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
-+ ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
-+
-+
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
-+#endif /* DEBUG_HOST_CHANNELS */
-+ return ret_val;
-+}
-+
-+/**
-+ * Attempts to queue a single transaction request for a host channel
-+ * associated with either a periodic or non-periodic transfer. This function
-+ * assumes that there is space available in the appropriate request queue. For
-+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
-+ * is available in the appropriate Tx FIFO.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param hc Host channel descriptor associated with either a periodic or
-+ * non-periodic transfer.
-+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
-+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
-+ * transfers.
-+ *
-+ * @return 1 if a request is queued and more requests may be needed to
-+ * complete the transfer, 0 if no more requests are required for this
-+ * transfer, -1 if there is insufficient space in the Tx FIFO.
-+ */
-+static int queue_transaction(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc, uint16_t fifo_dwords_avail)
-+{
-+ int retval;
-+
-+ if (hcd->core_if->dma_enable) {
-+ if (hcd->core_if->dma_desc_enable) {
-+ if (!hc->xfer_started
-+ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
-+ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
-+ hc->qh->ping_state = 0;
-+ }
-+ } else if (!hc->xfer_started) {
-+ if (fiq_fsm_enable && hc->error_state) {
-+ hcd->fiq_state->channel[hc->hc_num].nr_errors =
-+ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
-+ hcd->fiq_state->channel[hc->hc_num].fsm =
-+ FIQ_PASSTHROUGH_ERRORSTATE;
-+ }
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ hc->qh->ping_state = 0;
-+ }
-+ retval = 0;
-+ } else if (hc->halt_pending) {
-+ /* Don't queue a request if the channel has been halted. */
-+ retval = 0;
-+ } else if (hc->halt_on_queue) {
-+ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
-+ retval = 0;
-+ } else if (hc->do_ping) {
-+ if (!hc->xfer_started) {
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ }
-+ retval = 0;
-+ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+ if ((fifo_dwords_avail * 4) >= hc->max_packet) {
-+ if (!hc->xfer_started) {
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ retval = 1;
-+ } else {
-+ retval =
-+ dwc_otg_hc_continue_transfer(hcd->core_if,
-+ hc);
-+ }
-+ } else {
-+ retval = -1;
-+ }
-+ } else {
-+ if (!hc->xfer_started) {
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ retval = 1;
-+ } else {
-+ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
-+ }
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * Processes periodic channels for the next frame and queues transactions for
-+ * these channels to the DWC_otg controller. After queueing transactions, the
-+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
-+ * to queue as Periodic Tx FIFO or request queue space becomes available.
-+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
-+ */
-+static void process_periodic_channels(dwc_otg_hcd_t * hcd)
-+{
-+ hptxsts_data_t tx_status;
-+ dwc_list_link_t *qh_ptr;
-+ dwc_otg_qh_t *qh;
-+ int status = 0;
-+ int no_queue_space = 0;
-+ int no_fifo_space = 0;
-+
-+ dwc_otg_host_global_regs_t *host_regs;
-+ host_regs = hcd->core_if->host_if->host_global_regs;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " P Tx Req Queue Space Avail (before queue): %d\n",
-+ tx_status.b.ptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
-+ tx_status.b.ptxfspcavail);
-+#endif
-+
-+ qh_ptr = hcd->periodic_sched_assigned.next;
-+ while (qh_ptr != &hcd->periodic_sched_assigned) {
-+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+ if (tx_status.b.ptxqspcavail == 0) {
-+ no_queue_space = 1;
-+ break;
-+ }
-+
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+
-+ // Do not send a split start transaction any later than frame .6
-+ // Note, we have to schedule a periodic in .5 to make it go in .6
-+ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
-+ {
-+ qh_ptr = qh_ptr->next;
-+ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
-+ continue;
-+ }
-+
-+ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
-+ if (qh->do_split)
-+ fiq_fsm_queue_split_transaction(hcd, qh);
-+ else
-+ fiq_fsm_queue_isoc_transaction(hcd, qh);
-+ } else {
-+
-+ /*
-+ * Set a flag if we're queueing high-bandwidth in slave mode.
-+ * The flag prevents any halts to get into the request queue in
-+ * the middle of multiple high-bandwidth packets getting queued.
-+ */
-+ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
-+ hcd->core_if->queuing_high_bandwidth = 1;
-+ }
-+ status = queue_transaction(hcd, qh->channel,
-+ tx_status.b.ptxfspcavail);
-+ if (status < 0) {
-+ no_fifo_space = 1;
-+ break;
-+ }
-+ }
-+
-+ /*
-+ * In Slave mode, stay on the current transfer until there is
-+ * nothing more to do or the high-bandwidth request count is
-+ * reached. In DMA mode, only need to queue one request. The
-+ * controller automatically handles multiple packets for
-+ * high-bandwidth transfers.
-+ */
-+ if (hcd->core_if->dma_enable || status == 0 ||
-+ qh->channel->requests == qh->channel->multi_count) {
-+ qh_ptr = qh_ptr->next;
-+ /*
-+ * Move the QH from the periodic assigned schedule to
-+ * the periodic queued schedule.
-+ */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
-+ &qh->qh_list_entry);
-+
-+ /* done queuing high bandwidth */
-+ hcd->core_if->queuing_high_bandwidth = 0;
-+ }
-+ }
-+
-+ if (!hcd->core_if->dma_enable) {
-+ dwc_otg_core_global_regs_t *global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ global_regs = hcd->core_if->core_global_regs;
-+ intr_mask.b.ptxfempty = 1;
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " P Tx Req Queue Space Avail (after queue): %d\n",
-+ tx_status.b.ptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " P Tx FIFO Space Avail (after queue): %d\n",
-+ tx_status.b.ptxfspcavail);
-+#endif
-+ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
-+ no_queue_space || no_fifo_space) {
-+ /*
-+ * May need to queue more transactions as the request
-+ * queue or Tx FIFO empties. Enable the periodic Tx
-+ * FIFO empty interrupt. (Always use the half-empty
-+ * level to ensure that new requests are loaded as
-+ * soon as possible.)
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
-+ intr_mask.d32);
-+ } else {
-+ /*
-+ * Disable the Tx FIFO empty interrupt since there are
-+ * no more transactions that need to be queued right
-+ * now. This function is called from interrupt
-+ * handlers to queue more transactions as transfer
-+ * states change.
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
-+ 0);
-+ }
-+ }
-+}
-+
-+/**
-+ * Processes active non-periodic channels and queues transactions for these
-+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
-+ * FIFO Empty interrupt is enabled if there are more transactions to queue as
-+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
-+ * FIFO Empty interrupt is disabled.
-+ */
-+static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
-+{
-+ gnptxsts_data_t tx_status;
-+ dwc_list_link_t *orig_qh_ptr;
-+ dwc_otg_qh_t *qh;
-+ int status;
-+ int no_queue_space = 0;
-+ int no_fifo_space = 0;
-+ int more_to_do = 0;
-+
-+ dwc_otg_core_global_regs_t *global_regs =
-+ hcd->core_if->core_global_regs;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " NP Tx Req Queue Space Avail (before queue): %d\n",
-+ tx_status.b.nptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
-+ tx_status.b.nptxfspcavail);
-+#endif
-+ /*
-+ * Keep track of the starting point. Skip over the start-of-list
-+ * entry.
-+ */
-+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
-+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
-+ }
-+ orig_qh_ptr = hcd->non_periodic_qh_ptr;
-+
-+ /*
-+ * Process once through the active list or until no more space is
-+ * available in the request queue or the Tx FIFO.
-+ */
-+ do {
-+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
-+ no_queue_space = 1;
-+ break;
-+ }
-+
-+ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
-+ qh_list_entry);
-+
-+ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
-+ fiq_fsm_queue_split_transaction(hcd, qh);
-+ } else {
-+ status = queue_transaction(hcd, qh->channel,
-+ tx_status.b.nptxfspcavail);
-+
-+ if (status > 0) {
-+ more_to_do = 1;
-+ } else if (status < 0) {
-+ no_fifo_space = 1;
-+ break;
-+ }
-+ }
-+ /* Advance to next QH, skipping start-of-list entry. */
-+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
-+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
-+ hcd->non_periodic_qh_ptr =
-+ hcd->non_periodic_qh_ptr->next;
-+ }
-+
-+ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
-+
-+ if (!hcd->core_if->dma_enable) {
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ intr_mask.b.nptxfempty = 1;
-+
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " NP Tx Req Queue Space Avail (after queue): %d\n",
-+ tx_status.b.nptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " NP Tx FIFO Space Avail (after queue): %d\n",
-+ tx_status.b.nptxfspcavail);
-+#endif
-+ if (more_to_do || no_queue_space || no_fifo_space) {
-+ /*
-+ * May need to queue more transactions as the request
-+ * queue or Tx FIFO empties. Enable the non-periodic
-+ * Tx FIFO empty interrupt. (Always use the half-empty
-+ * level to ensure that new requests are loaded as
-+ * soon as possible.)
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
-+ intr_mask.d32);
-+ } else {
-+ /*
-+ * Disable the Tx FIFO empty interrupt since there are
-+ * no more transactions that need to be queued right
-+ * now. This function is called from interrupt
-+ * handlers to queue more transactions as transfer
-+ * states change.
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
-+ 0);
-+ }
-+ }
-+}
-+
-+/**
-+ * This function processes the currently active host channels and queues
-+ * transactions for these channels to the DWC_otg controller. It is called
-+ * from HCD interrupt handler functions.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param tr_type The type(s) of transactions to queue (non-periodic,
-+ * periodic, or both).
-+ */
-+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
-+ dwc_otg_transaction_type_e tr_type)
-+{
-+#ifdef DEBUG_SOF
-+ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
-+#endif
-+ /* Process host channels associated with periodic transfers. */
-+ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
-+ tr_type == DWC_OTG_TRANSACTION_ALL) &&
-+ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
-+
-+ process_periodic_channels(hcd);
-+ }
-+
-+ /* Process host channels associated with non-periodic transfers. */
-+ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
-+ tr_type == DWC_OTG_TRANSACTION_ALL) {
-+ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
-+ process_non_periodic_channels(hcd);
-+ } else {
-+ /*
-+ * Ensure NP Tx FIFO empty interrupt is disabled when
-+ * there are no non-periodic transfers to process.
-+ */
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ gintmsk.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&hcd->core_if->
-+ core_global_regs->gintmsk, gintmsk.d32,
-+ 0);
-+ }
-+ }
-+}
-+
-+#ifdef DWC_HS_ELECT_TST
-+/*
-+ * Quick and dirty hack to implement the HS Electrical Test
-+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
-+ *
-+ * This code was copied from our userspace app "hset". It sends a
-+ * Get Device Descriptor control sequence in two parts, first the
-+ * Setup packet by itself, followed some time later by the In and
-+ * Ack packets. Rather than trying to figure out how to add this
-+ * functionality to the normal driver code, we just hijack the
-+ * hardware, using these two function to drive the hardware
-+ * directly.
-+ */
-+
-+static dwc_otg_core_global_regs_t *global_regs;
-+static dwc_otg_host_global_regs_t *hc_global_regs;
-+static dwc_otg_hc_regs_t *hc_regs;
-+static uint32_t *data_fifo;
-+
-+static void do_setup(void)
-+{
-+ gintsts_data_t gintsts;
-+ hctsiz_data_t hctsiz;
-+ hcchar_data_t hcchar;
-+ haint_data_t haint;
-+ hcint_data_t hcint;
-+
-+ /* Enable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
-+
-+ /* Enable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /*
-+ * Send Setup packet (Get Device Descriptor)
-+ */
-+
-+ /* Make sure channel is disabled */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chdis = 1;
-+// hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ //sleep(1);
-+ dwc_mdelay(1000);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ }
-+
-+ /* Set HCTSIZ */
-+ hctsiz.d32 = 0;
-+ hctsiz.b.xfersize = 8;
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ /* Set HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.epdir = 0;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.mps = 8;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ /* Fill FIFO with Setup data for Get Device Descriptor */
-+ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
-+ DWC_WRITE_REG32(data_fifo++, 0x01000680);
-+ DWC_WRITE_REG32(data_fifo++, 0x00080000);
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for host channel interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.hcintr == 0);
-+
-+ /* Disable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
-+
-+ /* Disable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+}
-+
-+static void do_in_ack(void)
-+{
-+ gintsts_data_t gintsts;
-+ hctsiz_data_t hctsiz;
-+ hcchar_data_t hcchar;
-+ haint_data_t haint;
-+ hcint_data_t hcint;
-+ host_grxsts_data_t grxsts;
-+
-+ /* Enable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
-+
-+ /* Enable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /*
-+ * Receive Control In packet
-+ */
-+
-+ /* Make sure channel is disabled */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chdis = 1;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ //sleep(1);
-+ dwc_mdelay(1000);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ }
-+
-+ /* Set HCTSIZ */
-+ hctsiz.d32 = 0;
-+ hctsiz.b.xfersize = 8;
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ /* Set HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.epdir = 1;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.mps = 8;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for receive status queue interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.rxstsqlvl == 0);
-+
-+ /* Read RXSTS */
-+ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+ /* Clear RXSTSQLVL in GINTSTS */
-+ gintsts.d32 = 0;
-+ gintsts.b.rxstsqlvl = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ switch (grxsts.b.pktsts) {
-+ case DWC_GRXSTS_PKTSTS_IN:
-+ /* Read the data into the host buffer */
-+ if (grxsts.b.bcnt > 0) {
-+ int i;
-+ int word_count = (grxsts.b.bcnt + 3) / 4;
-+
-+ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
-+
-+ for (i = 0; i < word_count; i++) {
-+ (void)DWC_READ_REG32(data_fifo++);
-+ }
-+ }
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for receive status queue interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.rxstsqlvl == 0);
-+
-+ /* Read RXSTS */
-+ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+ /* Clear RXSTSQLVL in GINTSTS */
-+ gintsts.d32 = 0;
-+ gintsts.b.rxstsqlvl = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ switch (grxsts.b.pktsts) {
-+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for host channel interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.hcintr == 0);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+// usleep(100000);
-+// mdelay(100);
-+ dwc_mdelay(1);
-+
-+ /*
-+ * Send handshake packet
-+ */
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Make sure channel is disabled */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chdis = 1;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ //sleep(1);
-+ dwc_mdelay(1000);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ }
-+
-+ /* Set HCTSIZ */
-+ hctsiz.d32 = 0;
-+ hctsiz.b.xfersize = 0;
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ /* Set HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.epdir = 0;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.mps = 8;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for host channel interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.hcintr == 0);
-+
-+ /* Disable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
-+
-+ /* Disable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+}
-+#endif
-+
-+/** Handles hub class-specific requests. */
-+int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
-+ uint16_t typeReq,
-+ uint16_t wValue,
-+ uint16_t wIndex, uint8_t * buf, uint16_t wLength)
-+{
-+ int retval = 0;
-+
-+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+ usb_hub_descriptor_t *hub_desc;
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+ uint32_t port_status;
-+
-+ switch (typeReq) {
-+ case UCR_CLEAR_HUB_FEATURE:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearHubFeature 0x%x\n", wValue);
-+ switch (wValue) {
-+ case UHF_C_HUB_LOCAL_POWER:
-+ case UHF_C_HUB_OVER_CURRENT:
-+ /* Nothing required here */
-+ break;
-+ default:
-+ retval = -DWC_E_INVALID;
-+ DWC_ERROR("DWC OTG HCD - "
-+ "ClearHubFeature request %xh unknown\n",
-+ wValue);
-+ }
-+ break;
-+ case UCR_CLEAR_PORT_FEATURE:
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (wValue != UHF_PORT_L1)
-+#endif
-+ if (!wIndex || wIndex > 1)
-+ goto error;
-+
-+ switch (wValue) {
-+ case UHF_PORT_ENABLE:
-+ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtena = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ break;
-+ case UHF_PORT_SUSPEND:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-+
-+ if (core_if->power_down == 2) {
-+ dwc_otg_host_hibernation_restore(core_if, 0, 0);
-+ } else {
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+ dwc_mdelay(5);
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtres = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ hprt0.b.prtsusp = 0;
-+ /* Clear Resume bit */
-+ dwc_mdelay(100);
-+ hprt0.b.prtres = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+ break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ case UHF_PORT_L1:
-+ {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ glpmcfg_data_t lpmcfg = {.d32 = 0 };
-+
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->
-+ core_global_regs->glpmcfg);
-+ lpmcfg.b.en_utmi_sleep = 0;
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ lpmcfg.b.prt_sleep_sts = 1;
-+ DWC_WRITE_REG32(&core_if->
-+ core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+
-+ /* Clear Enbl_L1Gating bit. */
-+ pcgcctl.b.enbl_sleep_gating = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
-+ 0);
-+
-+ dwc_mdelay(5);
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtres = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+ /* This bit will be cleared in wakeup interrupt handle */
-+ break;
-+ }
-+#endif
-+ case UHF_PORT_POWER:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_POWER\n");
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ break;
-+ case UHF_PORT_INDICATOR:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
-+ /* Port inidicator not supported */
-+ break;
-+ case UHF_C_PORT_CONNECTION:
-+ /* Clears drivers internal connect status change
-+ * flag */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
-+ dwc_otg_hcd->flags.b.port_connect_status_change = 0;
-+ break;
-+ case UHF_C_PORT_RESET:
-+ /* Clears the driver's internal Port Reset Change
-+ * flag */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
-+ dwc_otg_hcd->flags.b.port_reset_change = 0;
-+ break;
-+ case UHF_C_PORT_ENABLE:
-+ /* Clears the driver's internal Port
-+ * Enable/Disable Change flag */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
-+ dwc_otg_hcd->flags.b.port_enable_change = 0;
-+ break;
-+ case UHF_C_PORT_SUSPEND:
-+ /* Clears the driver's internal Port Suspend
-+ * Change flag, which is set when resume signaling on
-+ * the host port is complete */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
-+ dwc_otg_hcd->flags.b.port_suspend_change = 0;
-+ break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ case UHF_C_PORT_L1:
-+ dwc_otg_hcd->flags.b.port_l1_change = 0;
-+ break;
-+#endif
-+ case UHF_C_PORT_OVER_CURRENT:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
-+ dwc_otg_hcd->flags.b.port_over_current_change = 0;
-+ break;
-+ default:
-+ retval = -DWC_E_INVALID;
-+ DWC_ERROR("DWC OTG HCD - "
-+ "ClearPortFeature request %xh "
-+ "unknown or unsupported\n", wValue);
-+ }
-+ break;
-+ case UCR_GET_HUB_DESCRIPTOR:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "GetHubDescriptor\n");
-+ hub_desc = (usb_hub_descriptor_t *) buf;
-+ hub_desc->bDescLength = 9;
-+ hub_desc->bDescriptorType = 0x29;
-+ hub_desc->bNbrPorts = 1;
-+ USETW(hub_desc->wHubCharacteristics, 0x08);
-+ hub_desc->bPwrOn2PwrGood = 1;
-+ hub_desc->bHubContrCurrent = 0;
-+ hub_desc->DeviceRemovable[0] = 0;
-+ hub_desc->DeviceRemovable[1] = 0xff;
-+ break;
-+ case UCR_GET_HUB_STATUS:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "GetHubStatus\n");
-+ DWC_MEMSET(buf, 0, 4);
-+ break;
-+ case UCR_GET_PORT_STATUS:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
-+ wIndex, dwc_otg_hcd->flags.d32);
-+ if (!wIndex || wIndex > 1)
-+ goto error;
-+
-+ port_status = 0;
-+
-+ if (dwc_otg_hcd->flags.b.port_connect_status_change)
-+ port_status |= (1 << UHF_C_PORT_CONNECTION);
-+
-+ if (dwc_otg_hcd->flags.b.port_enable_change)
-+ port_status |= (1 << UHF_C_PORT_ENABLE);
-+
-+ if (dwc_otg_hcd->flags.b.port_suspend_change)
-+ port_status |= (1 << UHF_C_PORT_SUSPEND);
-+
-+ if (dwc_otg_hcd->flags.b.port_l1_change)
-+ port_status |= (1 << UHF_C_PORT_L1);
-+
-+ if (dwc_otg_hcd->flags.b.port_reset_change) {
-+ port_status |= (1 << UHF_C_PORT_RESET);
-+ }
-+
-+ if (dwc_otg_hcd->flags.b.port_over_current_change) {
-+ DWC_WARN("Overcurrent change detected\n");
-+ port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
-+ }
-+
-+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
-+ /*
-+ * The port is disconnected, which means the core is
-+ * either in device mode or it soon will be. Just
-+ * return 0's for the remainder of the port status
-+ * since the port register can't be read if the core
-+ * is in device mode.
-+ */
-+ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
-+ break;
-+ }
-+
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
-+
-+ if (hprt0.b.prtconnsts)
-+ port_status |= (1 << UHF_PORT_CONNECTION);
-+
-+ if (hprt0.b.prtena)
-+ port_status |= (1 << UHF_PORT_ENABLE);
-+
-+ if (hprt0.b.prtsusp)
-+ port_status |= (1 << UHF_PORT_SUSPEND);
-+
-+ if (hprt0.b.prtovrcurract)
-+ port_status |= (1 << UHF_PORT_OVER_CURRENT);
-+
-+ if (hprt0.b.prtrst)
-+ port_status |= (1 << UHF_PORT_RESET);
-+
-+ if (hprt0.b.prtpwr)
-+ port_status |= (1 << UHF_PORT_POWER);
-+
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
-+ port_status |= (1 << UHF_PORT_HIGH_SPEED);
-+ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
-+ port_status |= (1 << UHF_PORT_LOW_SPEED);
-+
-+ if (hprt0.b.prttstctl)
-+ port_status |= (1 << UHF_PORT_TEST);
-+ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
-+ port_status |= (1 << UHF_PORT_L1);
-+ }
-+ /*
-+ For Synopsys HW emulation of Power down wkup_control asserts the
-+ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
-+ We intentionally tell the software that port is in L2Suspend state.
-+ Only for STE.
-+ */
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ port_status |= (1 << UHF_PORT_SUSPEND);
-+ }
-+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
-+
-+ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
-+
-+ break;
-+ case UCR_SET_HUB_FEATURE:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetHubFeature\n");
-+ /* No HUB features supported */
-+ break;
-+ case UCR_SET_PORT_FEATURE:
-+ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
-+ goto error;
-+
-+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
-+ /*
-+ * The port is disconnected, which means the core is
-+ * either in device mode or it soon will be. Just
-+ * return without doing anything since the port
-+ * register can't be written if the core is in device
-+ * mode.
-+ */
-+ break;
-+ }
-+
-+ switch (wValue) {
-+ case UHF_PORT_SUSPEND:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
-+ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
-+ goto error;
-+ }
-+ if (core_if->power_down == 2) {
-+ int timeout = 300;
-+ dwc_irqflags_t flags;
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+#ifdef DWC_DEV_SRPCAP
-+ int32_t otg_cap_param = core_if->core_params->otg_cap;
-+#endif
-+ DWC_PRINTF("Preparing for complete power-off\n");
-+
-+ /* Save registers before hibernation */
-+ dwc_otg_save_global_regs(core_if);
-+ dwc_otg_save_host_regs(core_if);
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 1;
-+ hprt0.b.prtena = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ /* Spin hprt0.b.prtsusp to became 1 */
-+ do {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ if (hprt0.b.prtsusp) {
-+ break;
-+ }
-+ dwc_mdelay(1);
-+ } while (--timeout);
-+ if (!timeout) {
-+ DWC_WARN("Suspend wasn't genereted\n");
-+ }
-+ dwc_udelay(10);
-+
-+ /*
-+ * We need to disable interrupts to prevent servicing of any IRQ
-+ * during going to hibernation
-+ */
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ core_if->lx_state = DWC_OTG_L2;
-+#ifdef DWC_DEV_SRPCAP
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 0;
-+ hprt0.b.prtena = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+#endif
-+ gusbcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->
-+ gusbcfg);
-+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ /* Suspend the Phy Clock */
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ } else {
-+ /* UTMI+ Interface */
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+ dwc_udelay(10);
-+ }
-+#ifdef DWC_DEV_SRPCAP
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+#endif
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ gpwrdn.d32 = 0;
-+#ifdef DWC_DEV_SRPCAP
-+ gpwrdn.b.srp_det_msk = 1;
-+#endif
-+ gpwrdn.b.disconn_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ gpwrdn.b.sts_chngint_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Enable Power Down Clamp and all interrupts in GPWRDN */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Switch off VDD */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+#ifdef DWC_DEV_SRPCAP
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
-+ {
-+ core_if->pwron_timer_started = 1;
-+ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
-+ }
-+#endif
-+ /* Save gpwrdn register for further usage if stschng interrupt */
-+ core_if->gr_backup->gpwrdn_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ /* Set flag to indicate that we are in hibernation */
-+ core_if->hibernation_suspend = 1;
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
-+
-+ DWC_PRINTF("Host hibernation completed\n");
-+ // Exit from case statement
-+ break;
-+
-+ }
-+ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
-+ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gotgctl.b.hstsethnpen = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gotgctl, 0, gotgctl.d32);
-+ core_if->op_state = A_SUSPEND;
-+ }
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ {
-+ dwc_irqflags_t flags;
-+ /* Update lx_state */
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ core_if->lx_state = DWC_OTG_L2;
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+ }
-+ /* Suspend the Phy Clock */
-+ {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ }
-+
-+ /* For HNP the bus must be suspended for at least 200ms. */
-+ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ dwc_mdelay(200);
-+ }
-+
-+ /** @todo - check how sw can wait for 1 sec to check asesvld??? */
-+#if 0 //vahrama !!!!!!!!!!!!!!!!!!
-+ if (core_if->adp_enable) {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn;
-+
-+ while (gotgctl.b.asesvld == 1) {
-+ gotgctl.d32 =
-+ DWC_READ_REG32(&core_if->
-+ core_global_regs->
-+ gotgctl);
-+ dwc_mdelay(100);
-+ }
-+
-+ /* Enable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ /* Unmask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ dwc_otg_adp_probe_start(core_if);
-+ }
-+#endif
-+ break;
-+ case UHF_PORT_POWER:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_POWER\n");
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ break;
-+ case UHF_PORT_RESET:
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ /* If we are going to exit from Hibernated
-+ * state via USB RESET.
-+ */
-+ dwc_otg_host_hibernation_restore(core_if, 0, 1);
-+ } else {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+
-+ DWC_DEBUGPL(DBG_HCD,
-+ "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_RESET\n");
-+ {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ pcgcctl.b.enbl_sleep_gating = 1;
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+ }
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ {
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.prt_sleep_sts) {
-+ lpmcfg.b.en_utmi_sleep = 0;
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ DWC_WRITE_REG32
-+ (&core_if->core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+ dwc_mdelay(1);
-+ }
-+ }
-+#endif
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ /* Clear suspend bit if resetting from suspended state. */
-+ hprt0.b.prtsusp = 0;
-+ /* When B-Host the Port reset bit is set in
-+ * the Start HCD Callback function, so that
-+ * the reset is started within 1ms of the HNP
-+ * success interrupt. */
-+ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtrst = 1;
-+ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+ }
-+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
-+ dwc_mdelay(60);
-+ hprt0.b.prtrst = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
-+ }
-+ break;
-+#ifdef DWC_HS_ELECT_TST
-+ case UHF_PORT_TEST:
-+ {
-+ uint32_t t;
-+ gintmsk_data_t gintmsk;
-+
-+ t = (wIndex >> 8); /* MSB wIndex USB */
-+ DWC_DEBUGPL(DBG_HCD,
-+ "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
-+ t);
-+ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
-+ if (t < 6) {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prttstctl = t;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+ } else {
-+ /* Setup global vars with reg addresses (quick and
-+ * dirty hack, should be cleaned up)
-+ */
-+ global_regs = core_if->core_global_regs;
-+ hc_global_regs =
-+ core_if->host_if->host_global_regs;
-+ hc_regs =
-+ (dwc_otg_hc_regs_t *) ((char *)
-+ global_regs +
-+ 0x500);
-+ data_fifo =
-+ (uint32_t *) ((char *)global_regs +
-+ 0x1000);
-+
-+ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
-+ /* Save current interrupt mask */
-+ gintmsk.d32 =
-+ DWC_READ_REG32
-+ (&global_regs->gintmsk);
-+
-+ /* Disable all interrupts while we muck with
-+ * the hardware directly
-+ */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* 15 second delay per the test spec */
-+ dwc_mdelay(15000);
-+
-+ /* Drive suspend on the root port */
-+ hprt0.d32 =
-+ dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 1;
-+ hprt0.b.prtres = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* 15 second delay per the test spec */
-+ dwc_mdelay(15000);
-+
-+ /* Drive resume on the root port */
-+ hprt0.d32 =
-+ dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 0;
-+ hprt0.b.prtres = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ dwc_mdelay(100);
-+
-+ /* Clear the resume bit */
-+ hprt0.b.prtres = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Restore interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
-+ /* Save current interrupt mask */
-+ gintmsk.d32 =
-+ DWC_READ_REG32
-+ (&global_regs->gintmsk);
-+
-+ /* Disable all interrupts while we muck with
-+ * the hardware directly
-+ */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* 15 second delay per the test spec */
-+ dwc_mdelay(15000);
-+
-+ /* Send the Setup packet */
-+ do_setup();
-+
-+ /* 15 second delay so nothing else happens for awhile */
-+ dwc_mdelay(15000);
-+
-+ /* Restore interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
-+ /* Save current interrupt mask */
-+ gintmsk.d32 =
-+ DWC_READ_REG32
-+ (&global_regs->gintmsk);
-+
-+ /* Disable all interrupts while we muck with
-+ * the hardware directly
-+ */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* Send the Setup packet */
-+ do_setup();
-+
-+ /* 15 second delay so nothing else happens for awhile */
-+ dwc_mdelay(15000);
-+
-+ /* Send the In and Ack packets */
-+ do_in_ack();
-+
-+ /* 15 second delay so nothing else happens for awhile */
-+ dwc_mdelay(15000);
-+
-+ /* Restore interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+ }
-+ }
-+ break;
-+ }
-+#endif /* DWC_HS_ELECT_TST */
-+
-+ case UHF_PORT_INDICATOR:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
-+ /* Not supported */
-+ break;
-+ default:
-+ retval = -DWC_E_INVALID;
-+ DWC_ERROR("DWC OTG HCD - "
-+ "SetPortFeature request %xh "
-+ "unknown or unsupported\n", wValue);
-+ break;
-+ }
-+ break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ case UCR_SET_AND_TEST_PORT_FEATURE:
-+ if (wValue != UHF_PORT_L1) {
-+ goto error;
-+ }
-+ {
-+ int portnum, hird, devaddr, remwake;
-+ glpmcfg_data_t lpmcfg;
-+ uint32_t time_usecs;
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+
-+ if (!dwc_otg_get_param_lpm_enable(core_if)) {
-+ goto error;
-+ }
-+ if (wValue != UHF_PORT_L1 || wLength != 1) {
-+ goto error;
-+ }
-+ /* Check if the port currently is in SLEEP state */
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.prt_sleep_sts) {
-+ DWC_INFO("Port is already in sleep mode\n");
-+ buf[0] = 0; /* Return success */
-+ break;
-+ }
-+
-+ portnum = wIndex & 0xf;
-+ hird = (wIndex >> 4) & 0xf;
-+ devaddr = (wIndex >> 8) & 0x7f;
-+ remwake = (wIndex >> 15);
-+
-+ if (portnum != 1) {
-+ retval = -DWC_E_INVALID;
-+ DWC_WARN
-+ ("Wrong port number(%d) in SetandTestPortFeature request\n",
-+ portnum);
-+ break;
-+ }
-+
-+ DWC_PRINTF
-+ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
-+ portnum, hird, devaddr, remwake);
-+ /* Disable LPM interrupt */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.lpmtranrcvd = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ gintmsk.d32, 0);
-+
-+ if (dwc_otg_hcd_send_lpm
-+ (dwc_otg_hcd, devaddr, hird, remwake)) {
-+ retval = -DWC_E_INVALID;
-+ break;
-+ }
-+
-+ time_usecs = 10 * (lpmcfg.b.retry_count + 1);
-+ /* We will consider timeout if time_usecs microseconds pass,
-+ * and we don't receive LPM transaction status.
-+ * After receiving non-error responce(ACK/NYET/STALL) from device,
-+ * core will set lpmtranrcvd bit.
-+ */
-+ do {
-+ gintsts.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (gintsts.b.lpmtranrcvd) {
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (--time_usecs);
-+ /* lpm_int bit will be cleared in LPM interrupt handler */
-+
-+ /* Now fill status
-+ * 0x00 - Success
-+ * 0x10 - NYET
-+ * 0x11 - Timeout
-+ */
-+ if (!gintsts.b.lpmtranrcvd) {
-+ buf[0] = 0x3; /* Completion code is Timeout */
-+ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
-+ } else {
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.lpm_resp == 0x3) {
-+ /* ACK responce from the device */
-+ buf[0] = 0x00; /* Success */
-+ } else if (lpmcfg.b.lpm_resp == 0x2) {
-+ /* NYET responce from the device */
-+ buf[0] = 0x2;
-+ } else {
-+ /* Otherwise responce with Timeout */
-+ buf[0] = 0x3;
-+ }
-+ }
-+ DWC_PRINTF("Device responce to LPM trans is %x\n",
-+ lpmcfg.b.lpm_resp);
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
-+ gintmsk.d32);
-+
-+ break;
-+ }
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+ default:
-+error:
-+ retval = -DWC_E_INVALID;
-+ DWC_WARN("DWC OTG HCD - "
-+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
-+ typeReq, wIndex, wValue);
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/** Returns index of host channel to perform LPM transaction. */
-+int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
-+{
-+ dwc_otg_core_if_t *core_if = hcd->core_if;
-+ dwc_hc_t *hc;
-+ hcchar_data_t hcchar;
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+ DWC_PRINTF("No free channel to select for LPM transaction\n");
-+ return -1;
-+ }
-+
-+ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
-+
-+ /* Mask host channel interrupts. */
-+ gintmsk.b.hcintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+ /* Fill fields that core needs for LPM transaction */
-+ hcchar.b.devaddr = devaddr;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.mps = 64;
-+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+ hcchar.b.epdir = 0; /* OUT */
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
-+ hcchar.d32);
-+
-+ /* Remove the host channel from the free list. */
-+ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
-+
-+ return hc->hc_num;
-+}
-+
-+/** Release hc after performing LPM transaction */
-+void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
-+{
-+ dwc_hc_t *hc;
-+ glpmcfg_data_t lpmcfg;
-+ uint8_t hc_num;
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
-+ hc_num = lpmcfg.b.lpm_chan_index;
-+
-+ hc = hcd->hc_ptr_array[hc_num];
-+
-+ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
-+ /* Return host channel to free list */
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+}
-+
-+int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
-+ uint8_t bRemoteWake)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ int channel;
-+
-+ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
-+ if (channel < 0) {
-+ return channel;
-+ }
-+
-+ pcgcctl.b.enbl_sleep_gating = 1;
-+ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ /* Read LPM config register */
-+ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
-+
-+ /* Program LPM transaction fields */
-+ lpmcfg.b.rem_wkup_en = bRemoteWake;
-+ lpmcfg.b.hird = hird;
-+ lpmcfg.b.hird_thres = 0x1c;
-+ lpmcfg.b.lpm_chan_index = channel;
-+ lpmcfg.b.en_utmi_sleep = 1;
-+ /* Program LPM config register */
-+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+ /* Send LPM transaction */
-+ lpmcfg.b.send_lpm = 1;
-+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+ return 0;
-+}
-+
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+
-+int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
-+{
-+ int retval;
-+
-+ if (port != 1) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ retval = (hcd->flags.b.port_connect_status_change ||
-+ hcd->flags.b.port_reset_change ||
-+ hcd->flags.b.port_enable_change ||
-+ hcd->flags.b.port_suspend_change ||
-+ hcd->flags.b.port_over_current_change);
-+#ifdef DEBUG
-+ if (retval) {
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
-+ " Root port status changed\n");
-+ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
-+ hcd->flags.b.port_connect_status_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
-+ hcd->flags.b.port_reset_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
-+ hcd->flags.b.port_enable_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
-+ hcd->flags.b.port_suspend_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
-+ hcd->flags.b.port_over_current_change);
-+ }
-+#endif
-+ return retval;
-+}
-+
-+int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ hfnum_data_t hfnum;
-+ hfnum.d32 =
-+ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
-+ hfnum);
-+
-+#ifdef DEBUG_SOF
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
-+ hfnum.b.frnum);
-+#endif
-+ return hfnum.b.frnum;
-+}
-+
-+int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
-+ struct dwc_otg_hcd_function_ops *fops)
-+{
-+ int retval = 0;
-+
-+ hcd->fops = fops;
-+ if (!dwc_otg_is_device_mode(hcd->core_if) &&
-+ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
-+ dwc_otg_hcd_reinit(hcd);
-+ } else {
-+ retval = -DWC_E_NO_DEVICE;
-+ }
-+
-+ return retval;
-+}
-+
-+void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
-+{
-+ return hcd->priv;
-+}
-+
-+void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
-+{
-+ hcd->priv = priv_data;
-+}
-+
-+uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
-+{
-+ return hcd->otg_port;
-+}
-+
-+uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
-+{
-+ uint32_t is_b_host;
-+ if (hcd->core_if->op_state == B_HOST) {
-+ is_b_host = 1;
-+ } else {
-+ is_b_host = 0;
-+ }
-+
-+ return is_b_host;
-+}
-+
-+dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
-+ int iso_desc_count, int atomic_alloc)
-+{
-+ dwc_otg_hcd_urb_t *dwc_otg_urb;
-+ uint32_t size;
-+
-+ size =
-+ sizeof(*dwc_otg_urb) +
-+ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
-+ if (atomic_alloc)
-+ dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
-+ else
-+ dwc_otg_urb = DWC_ALLOC(size);
-+
-+ if (dwc_otg_urb)
-+ dwc_otg_urb->packet_count = iso_desc_count;
-+ else {
-+ DWC_ERROR("**** DWC OTG HCD URB alloc - "
-+ "%salloc of %db failed\n",
-+ atomic_alloc?"atomic ":"", size);
-+ }
-+ return dwc_otg_urb;
-+}
-+
-+void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ uint8_t dev_addr, uint8_t ep_num,
-+ uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
-+{
-+ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
-+ ep_type, ep_dir, mps);
-+#if 0
-+ DWC_PRINTF
-+ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
-+ dev_addr, ep_num, ep_dir, ep_type, mps);
-+#endif
-+}
-+
-+void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ void *urb_handle, void *buf, dwc_dma_t dma,
-+ uint32_t buflen, void *setup_packet,
-+ dwc_dma_t setup_dma, uint32_t flags,
-+ uint16_t interval)
-+{
-+ dwc_otg_urb->priv = urb_handle;
-+ dwc_otg_urb->buf = buf;
-+ dwc_otg_urb->dma = dma;
-+ dwc_otg_urb->length = buflen;
-+ dwc_otg_urb->setup_packet = setup_packet;
-+ dwc_otg_urb->setup_dma = setup_dma;
-+ dwc_otg_urb->flags = flags;
-+ dwc_otg_urb->interval = interval;
-+ dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ return dwc_otg_urb->status;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ return dwc_otg_urb->actual_length;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ return dwc_otg_urb->error_count;
-+}
-+
-+void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int desc_num, uint32_t offset,
-+ uint32_t length)
-+{
-+ dwc_otg_urb->iso_descs[desc_num].offset = offset;
-+ dwc_otg_urb->iso_descs[desc_num].length = length;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int desc_num)
-+{
-+ return dwc_otg_urb->iso_descs[desc_num].status;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb, int desc_num)
-+{
-+ return dwc_otg_urb->iso_descs[desc_num].actual_length;
-+}
-+
-+int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ int allocated = 0;
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+
-+ if (qh) {
-+ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ allocated = 1;
-+ }
-+ }
-+ return allocated;
-+}
-+
-+int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ int freed = 0;
-+ DWC_ASSERT(qh, "qh is not allocated\n");
-+
-+ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ freed = 1;
-+ }
-+
-+ return freed;
-+}
-+
-+uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ DWC_ASSERT(qh, "qh is not allocated\n");
-+ return qh->usecs;
-+}
-+
-+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
-+{
-+#ifdef DEBUG
-+ int num_channels;
-+ int i;
-+ gnptxsts_data_t np_tx_status;
-+ hptxsts_data_t p_tx_status;
-+
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF
-+ ("************************************************************\n");
-+ DWC_PRINTF("HCD State:\n");
-+ DWC_PRINTF(" Num channels: %d\n", num_channels);
-+ for (i = 0; i < num_channels; i++) {
-+ dwc_hc_t *hc = hcd->hc_ptr_array[i];
-+ DWC_PRINTF(" Channel %d:\n", i);
-+ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
-+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
-+ DWC_PRINTF(" speed: %d\n", hc->speed);
-+ DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
-+ DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
-+ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
-+ DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
-+ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
-+ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
-+ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
-+ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
-+ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
-+ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
-+ DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
-+ DWC_PRINTF(" do_split: %d\n", hc->do_split);
-+ DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
-+ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
-+ DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
-+ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
-+ DWC_PRINTF(" requests: %d\n", hc->requests);
-+ DWC_PRINTF(" qh: %p\n", hc->qh);
-+ if (hc->xfer_started) {
-+ hfnum_data_t hfnum;
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ hfnum.d32 =
-+ DWC_READ_REG32(&hcd->core_if->
-+ host_if->host_global_regs->hfnum);
-+ hcchar.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hcchar);
-+ hctsiz.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hctsiz);
-+ hcint.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hcint);
-+ hcintmsk.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hcintmsk);
-+ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
-+ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
-+ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
-+ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
-+ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
-+ }
-+ if (hc->xfer_started && hc->qh) {
-+ dwc_otg_qtd_t *qtd;
-+ dwc_otg_hcd_urb_t *urb;
-+
-+ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
-+ if (!qtd->in_process)
-+ break;
-+
-+ urb = qtd->urb;
-+ DWC_PRINTF(" URB Info:\n");
-+ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
-+ if (urb) {
-+ DWC_PRINTF(" Dev: %d, EP: %d %s\n",
-+ dwc_otg_hcd_get_dev_addr(&urb->
-+ pipe_info),
-+ dwc_otg_hcd_get_ep_num(&urb->
-+ pipe_info),
-+ dwc_otg_hcd_is_pipe_in(&urb->
-+ pipe_info) ?
-+ "IN" : "OUT");
-+ DWC_PRINTF(" Max packet size: %d\n",
-+ dwc_otg_hcd_get_mps(&urb->
-+ pipe_info));
-+ DWC_PRINTF(" transfer_buffer: %p\n",
-+ urb->buf);
-+ DWC_PRINTF(" transfer_dma: %p\n",
-+ (void *)urb->dma);
-+ DWC_PRINTF(" transfer_buffer_length: %d\n",
-+ urb->length);
-+ DWC_PRINTF(" actual_length: %d\n",
-+ urb->actual_length);
-+ }
-+ }
-+ }
-+ }
-+ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
-+ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
-+ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
-+ np_tx_status.d32 =
-+ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
-+ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
-+ np_tx_status.b.nptxqspcavail);
-+ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
-+ np_tx_status.b.nptxfspcavail);
-+ p_tx_status.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
-+ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
-+ p_tx_status.b.ptxqspcavail);
-+ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
-+ dwc_otg_hcd_dump_frrem(hcd);
-+ dwc_otg_dump_global_registers(hcd->core_if);
-+ dwc_otg_dump_host_registers(hcd->core_if);
-+ DWC_PRINTF
-+ ("************************************************************\n");
-+ DWC_PRINTF("\n");
-+#endif
-+}
-+
-+#ifdef DEBUG
-+void dwc_print_setup_data(uint8_t * setup)
-+{
-+ int i;
-+ if (CHK_DEBUG_LEVEL(DBG_HCD)) {
-+ DWC_PRINTF("Setup Data = MSB ");
-+ for (i = 7; i >= 0; i--)
-+ DWC_PRINTF("%02x ", setup[i]);
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF(" bmRequestType Tranfer = %s\n",
-+ (setup[0] & 0x80) ? "Device-to-Host" :
-+ "Host-to-Device");
-+ DWC_PRINTF(" bmRequestType Type = ");
-+ switch ((setup[0] & 0x60) >> 5) {
-+ case 0:
-+ DWC_PRINTF("Standard\n");
-+ break;
-+ case 1:
-+ DWC_PRINTF("Class\n");
-+ break;
-+ case 2:
-+ DWC_PRINTF("Vendor\n");
-+ break;
-+ case 3:
-+ DWC_PRINTF("Reserved\n");
-+ break;
-+ }
-+ DWC_PRINTF(" bmRequestType Recipient = ");
-+ switch (setup[0] & 0x1f) {
-+ case 0:
-+ DWC_PRINTF("Device\n");
-+ break;
-+ case 1:
-+ DWC_PRINTF("Interface\n");
-+ break;
-+ case 2:
-+ DWC_PRINTF("Endpoint\n");
-+ break;
-+ case 3:
-+ DWC_PRINTF("Other\n");
-+ break;
-+ default:
-+ DWC_PRINTF("Reserved\n");
-+ break;
-+ }
-+ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
-+ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
-+ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
-+ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
-+ }
-+}
-+#endif
-+
-+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
-+{
-+#if 0
-+ DWC_PRINTF("Frame remaining at SOF:\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->frrem_samples, hcd->frrem_accum,
-+ (hcd->frrem_samples > 0) ?
-+ hcd->frrem_accum / hcd->frrem_samples : 0);
-+
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->core_if->hfnum_7_samples,
-+ hcd->core_if->hfnum_7_frrem_accum,
-+ (hcd->core_if->hfnum_7_samples >
-+ 0) ? hcd->core_if->hfnum_7_frrem_accum /
-+ hcd->core_if->hfnum_7_samples : 0);
-+ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->core_if->hfnum_0_samples,
-+ hcd->core_if->hfnum_0_frrem_accum,
-+ (hcd->core_if->hfnum_0_samples >
-+ 0) ? hcd->core_if->hfnum_0_frrem_accum /
-+ hcd->core_if->hfnum_0_samples : 0);
-+ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->core_if->hfnum_other_samples,
-+ hcd->core_if->hfnum_other_frrem_accum,
-+ (hcd->core_if->hfnum_other_samples >
-+ 0) ? hcd->core_if->hfnum_other_frrem_accum /
-+ hcd->core_if->hfnum_other_samples : 0);
-+
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
-+ (hcd->hfnum_7_samples_a > 0) ?
-+ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
-+ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
-+ (hcd->hfnum_0_samples_a > 0) ?
-+ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
-+ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
-+ (hcd->hfnum_other_samples_a > 0) ?
-+ hcd->hfnum_other_frrem_accum_a /
-+ hcd->hfnum_other_samples_a : 0);
-+
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
-+ (hcd->hfnum_7_samples_b > 0) ?
-+ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
-+ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
-+ (hcd->hfnum_0_samples_b > 0) ?
-+ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
-+ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
-+ (hcd->hfnum_other_samples_b > 0) ?
-+ hcd->hfnum_other_frrem_accum_b /
-+ hcd->hfnum_other_samples_b : 0);
-+#endif
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,1132 @@
-+/*==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
-+ * $Revision: #10 $
-+ * $Date: 2011/10/20 $
-+ * $Change: 1869464 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/** @file
-+ * This file contains Descriptor DMA support implementation for host mode.
-+ */
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+extern bool microframe_schedule;
-+
-+static inline uint8_t frame_list_idx(uint16_t frame)
-+{
-+ return (frame & (MAX_FRLIST_EN_NUM - 1));
-+}
-+
-+static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
-+{
-+ return (idx + inc) &
-+ (((speed ==
-+ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
-+ MAX_DMA_DESC_NUM_GENERIC) - 1);
-+}
-+
-+static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
-+{
-+ return (idx - inc) &
-+ (((speed ==
-+ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
-+ MAX_DMA_DESC_NUM_GENERIC) - 1);
-+}
-+
-+static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
-+{
-+ return (((qh->ep_type == UE_ISOCHRONOUS)
-+ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
-+ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
-+}
-+static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
-+{
-+ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
-+ ? ((qh->interval + 8 - 1) / 8)
-+ : qh->interval);
-+}
-+
-+static int desc_list_alloc(dwc_otg_qh_t * qh)
-+{
-+ int retval = 0;
-+
-+ qh->desc_list = (dwc_otg_host_dma_desc_t *)
-+ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
-+ &qh->desc_list_dma);
-+
-+ if (!qh->desc_list) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
-+
-+ }
-+
-+ dwc_memset(qh->desc_list, 0x00,
-+ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
-+
-+ qh->n_bytes =
-+ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
-+
-+ if (!qh->n_bytes) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR
-+ ("%s: Failed to allocate array for descriptors' size actual values\n",
-+ __func__);
-+
-+ }
-+ return retval;
-+
-+}
-+
-+static void desc_list_free(dwc_otg_qh_t * qh)
-+{
-+ if (qh->desc_list) {
-+ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
-+ qh->desc_list_dma);
-+ qh->desc_list = NULL;
-+ }
-+
-+ if (qh->n_bytes) {
-+ DWC_FREE(qh->n_bytes);
-+ qh->n_bytes = NULL;
-+ }
-+}
-+
-+static int frame_list_alloc(dwc_otg_hcd_t * hcd)
-+{
-+ int retval = 0;
-+ if (hcd->frame_list)
-+ return 0;
-+
-+ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
-+ &hcd->frame_list_dma);
-+ if (!hcd->frame_list) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: Frame List allocation failed\n", __func__);
-+ }
-+
-+ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
-+
-+ return retval;
-+}
-+
-+static void frame_list_free(dwc_otg_hcd_t * hcd)
-+{
-+ if (!hcd->frame_list)
-+ return;
-+
-+ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
-+ hcd->frame_list = NULL;
-+}
-+
-+static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
-+{
-+
-+ hcfg_data_t hcfg;
-+
-+ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
-+
-+ if (hcfg.b.perschedena) {
-+ /* already enabled */
-+ return;
-+ }
-+
-+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
-+ hcd->frame_list_dma);
-+
-+ switch (fr_list_en) {
-+ case 64:
-+ hcfg.b.frlisten = 3;
-+ break;
-+ case 32:
-+ hcfg.b.frlisten = 2;
-+ break;
-+ case 16:
-+ hcfg.b.frlisten = 1;
-+ break;
-+ case 8:
-+ hcfg.b.frlisten = 0;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ hcfg.b.perschedena = 1;
-+
-+ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
-+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+
-+}
-+
-+static void per_sched_disable(dwc_otg_hcd_t * hcd)
-+{
-+ hcfg_data_t hcfg;
-+
-+ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
-+
-+ if (!hcfg.b.perschedena) {
-+ /* already disabled */
-+ return;
-+ }
-+ hcfg.b.perschedena = 0;
-+
-+ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
-+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/*
-+ * Activates/Deactivates FrameList entries for the channel
-+ * based on endpoint servicing period.
-+ */
-+void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
-+{
-+ uint16_t i, j, inc;
-+ dwc_hc_t *hc = NULL;
-+
-+ if (!qh->channel) {
-+ DWC_ERROR("qh->channel = %p", qh->channel);
-+ return;
-+ }
-+
-+ if (!hcd) {
-+ DWC_ERROR("------hcd = %p", hcd);
-+ return;
-+ }
-+
-+ if (!hcd->frame_list) {
-+ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
-+ return;
-+ }
-+
-+ hc = qh->channel;
-+ inc = frame_incr_val(qh);
-+ if (qh->ep_type == UE_ISOCHRONOUS)
-+ i = frame_list_idx(qh->sched_frame);
-+ else
-+ i = 0;
-+
-+ j = i;
-+ do {
-+ if (enable)
-+ hcd->frame_list[j] |= (1 << hc->hc_num);
-+ else
-+ hcd->frame_list[j] &= ~(1 << hc->hc_num);
-+ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
-+ }
-+ while (j != i);
-+ if (!enable)
-+ return;
-+ hc->schinfo = 0;
-+ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ j = 1;
-+ /* TODO - check this */
-+ inc = (8 + qh->interval - 1) / qh->interval;
-+ for (i = 0; i < inc; i++) {
-+ hc->schinfo |= j;
-+ j = j << qh->interval;
-+ }
-+ } else {
-+ hc->schinfo = 0xff;
-+ }
-+}
-+
-+#if 1
-+void dump_frame_list(dwc_otg_hcd_t * hcd)
-+{
-+ int i = 0;
-+ DWC_PRINTF("--FRAME LIST (hex) --\n");
-+ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
-+ DWC_PRINTF("%x\t", hcd->frame_list[i]);
-+ if (!(i % 8) && i)
-+ DWC_PRINTF("\n");
-+ }
-+ DWC_PRINTF("\n----\n");
-+
-+}
-+#endif
-+
-+static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ dwc_irqflags_t flags;
-+ dwc_spinlock_t *channel_lock = hcd->channel_lock;
-+
-+ dwc_hc_t *hc = qh->channel;
-+ if (dwc_qh_is_non_per(qh)) {
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ if (!microframe_schedule)
-+ hcd->non_periodic_channels--;
-+ else
-+ hcd->available_host_channels++;
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ } else
-+ update_frame_list(hcd, qh, 0);
-+
-+ /*
-+ * The condition is added to prevent double cleanup try in case of device
-+ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
-+ */
-+ if (hc->qh) {
-+ dwc_otg_hc_cleanup(hcd->core_if, hc);
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+ hc->qh = NULL;
-+ }
-+
-+ qh->channel = NULL;
-+ qh->ntd = 0;
-+
-+ if (qh->desc_list) {
-+ dwc_memset(qh->desc_list, 0x00,
-+ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
-+ }
-+}
-+
-+/**
-+ * Initializes a QH structure's Descriptor DMA related members.
-+ * Allocates memory for descriptor list.
-+ * On first periodic QH, allocates memory for FrameList
-+ * and enables periodic scheduling.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int retval = 0;
-+
-+ if (qh->do_split) {
-+ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
-+ return -1;
-+ }
-+
-+ retval = desc_list_alloc(qh);
-+
-+ if ((retval == 0)
-+ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
-+ if (!hcd->frame_list) {
-+ retval = frame_list_alloc(hcd);
-+ /* Enable periodic schedule on first periodic QH */
-+ if (retval == 0)
-+ per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
-+ }
-+ }
-+
-+ qh->ntd = 0;
-+
-+ return retval;
-+}
-+
-+/**
-+ * Frees descriptor list memory associated with the QH.
-+ * If QH is periodic and the last, frees FrameList memory
-+ * and disables periodic scheduling.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ */
-+void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ desc_list_free(qh);
-+
-+ /*
-+ * Channel still assigned due to some reasons.
-+ * Seen on Isoc URB dequeue. Channel halted but no subsequent
-+ * ChHalted interrupt to release the channel. Afterwards
-+ * when it comes here from endpoint disable routine
-+ * channel remains assigned.
-+ */
-+ if (qh->channel)
-+ release_channel_ddma(hcd, qh);
-+
-+ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
-+ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
-+
-+ per_sched_disable(hcd);
-+ frame_list_free(hcd);
-+ }
-+}
-+
-+static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
-+{
-+ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
-+ /*
-+ * Descriptor set(8 descriptors) index
-+ * which is 8-aligned.
-+ */
-+ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
-+ } else {
-+ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
-+ }
-+}
-+
-+/*
-+ * Determine starting frame for Isochronous transfer.
-+ * Few frames skipped to prevent race condition with HC.
-+ */
-+static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ uint8_t * skip_frames)
-+{
-+ uint16_t frame = 0;
-+ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
-+
-+ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
-+
-+ /*
-+ * skip_frames is used to limit activated descriptors number
-+ * to avoid the situation when HC services the last activated
-+ * descriptor firstly.
-+ * Example for FS:
-+ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
-+ * corresponding to curr_frame+1, the descriptor corresponding to frame 2
-+ * will be fetched. If the number of descriptors is max=64 (or greather) the
-+ * list will be fully programmed with Active descriptors and it is possible
-+ * case(rare) that the latest descriptor(considering rollback) corresponding
-+ * to frame 2 will be serviced first. HS case is more probable because, in fact,
-+ * up to 11 uframes(16 in the code) may be skipped.
-+ */
-+ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
-+ /*
-+ * Consider uframe counter also, to start xfer asap.
-+ * If half of the frame elapsed skip 2 frames otherwise
-+ * just 1 frame.
-+ * Starting descriptor index must be 8-aligned, so
-+ * if the current frame is near to complete the next one
-+ * is skipped as well.
-+ */
-+
-+ if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
-+ *skip_frames = 2 * 8;
-+ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
-+ } else {
-+ *skip_frames = 1 * 8;
-+ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
-+ }
-+
-+ frame = dwc_full_frame_num(frame);
-+ } else {
-+ /*
-+ * Two frames are skipped for FS - the current and the next.
-+ * But for descriptor programming, 1 frame(descriptor) is enough,
-+ * see example above.
-+ */
-+ *skip_frames = 1;
-+ frame = dwc_frame_num_inc(hcd->frame_number, 2);
-+ }
-+
-+ return frame;
-+}
-+
-+/*
-+ * Calculate initial descriptor index for isochronous transfer
-+ * based on scheduled frame.
-+ */
-+static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ uint16_t frame = 0, fr_idx, fr_idx_tmp;
-+ uint8_t skip_frames = 0;
-+ /*
-+ * With current ISOC processing algorithm the channel is being
-+ * released when no more QTDs in the list(qh->ntd == 0).
-+ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
-+ *
-+ * So qh->channel != NULL branch is not used and just not removed from the
-+ * source file. It is required for another possible approach which is,
-+ * do not disable and release the channel when ISOC session completed,
-+ * just move QH to inactive schedule until new QTD arrives.
-+ * On new QTD, the QH moved back to 'ready' schedule,
-+ * starting frame and therefore starting desc_index are recalculated.
-+ * In this case channel is released only on ep_disable.
-+ */
-+
-+ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
-+ if (qh->channel) {
-+ frame = calc_starting_frame(hcd, qh, &skip_frames);
-+ /*
-+ * Calculate initial descriptor index based on FrameList current bitmap
-+ * and servicing period.
-+ */
-+ fr_idx_tmp = frame_list_idx(frame);
-+ fr_idx =
-+ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
-+ fr_idx_tmp)
-+ % frame_incr_val(qh);
-+ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
-+ } else {
-+ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
-+ fr_idx = frame_list_idx(qh->sched_frame);
-+ }
-+
-+ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
-+
-+ return skip_frames;
-+}
-+
-+#define ISOC_URB_GIVEBACK_ASAP
-+
-+#define MAX_ISOC_XFER_SIZE_FS 1023
-+#define MAX_ISOC_XFER_SIZE_HS 3072
-+#define DESCNUM_THRESHOLD 4
-+
-+static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ uint8_t skip_frames)
-+{
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+ dwc_otg_qtd_t *qtd;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
-+
-+ idx = qh->td_last;
-+ inc = qh->interval;
-+ n_desc = 0;
-+
-+ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
-+ if (skip_frames && !qh->channel)
-+ ntd_max = ntd_max - skip_frames / qh->interval;
-+
-+ max_xfer_size =
-+ (qh->dev_speed ==
-+ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
-+ MAX_ISOC_XFER_SIZE_FS;
-+
-+ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
-+ while ((qh->ntd < ntd_max)
-+ && (qtd->isoc_frame_index_last <
-+ qtd->urb->packet_count)) {
-+
-+ dma_desc = &qh->desc_list[idx];
-+ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
-+
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
-+
-+ if (frame_desc->length > max_xfer_size)
-+ qh->n_bytes[idx] = max_xfer_size;
-+ else
-+ qh->n_bytes[idx] = frame_desc->length;
-+ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
-+ dma_desc->status.b_isoc.a = 1;
-+ dma_desc->status.b_isoc.sts = 0;
-+
-+ dma_desc->buf = qtd->urb->dma + frame_desc->offset;
-+
-+ qh->ntd++;
-+
-+ qtd->isoc_frame_index_last++;
-+
-+#ifdef ISOC_URB_GIVEBACK_ASAP
-+ /*
-+ * Set IOC for each descriptor corresponding to the
-+ * last frame of the URB.
-+ */
-+ if (qtd->isoc_frame_index_last ==
-+ qtd->urb->packet_count)
-+ dma_desc->status.b_isoc.ioc = 1;
-+
-+#endif
-+ idx = desclist_idx_inc(idx, inc, qh->dev_speed);
-+ n_desc++;
-+
-+ }
-+ qtd->in_process = 1;
-+ }
-+
-+ qh->td_last = idx;
-+
-+#ifdef ISOC_URB_GIVEBACK_ASAP
-+ /* Set IOC for the last descriptor if descriptor list is full */
-+ if (qh->ntd == ntd_max) {
-+ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
-+ qh->desc_list[idx].status.b_isoc.ioc = 1;
-+ }
-+#else
-+ /*
-+ * Set IOC bit only for one descriptor.
-+ * Always try to be ahead of HW processing,
-+ * i.e. on IOC generation driver activates next descriptors but
-+ * core continues to process descriptors followed the one with IOC set.
-+ */
-+
-+ if (n_desc > DESCNUM_THRESHOLD) {
-+ /*
-+ * Move IOC "up". Required even if there is only one QTD
-+ * in the list, cause QTDs migth continue to be queued,
-+ * but during the activation it was only one queued.
-+ * Actually more than one QTD might be in the list if this function called
-+ * from XferCompletion - QTDs was queued during HW processing of the previous
-+ * descriptor chunk.
-+ */
-+ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
-+ } else {
-+ /*
-+ * Set the IOC for the latest descriptor
-+ * if either number of descriptor is not greather than threshold
-+ * or no more new descriptors activated.
-+ */
-+ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
-+ }
-+
-+ qh->desc_list[idx].status.b_isoc.ioc = 1;
-+#endif
-+}
-+
-+static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+
-+ dwc_hc_t *hc;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ dwc_otg_qtd_t *qtd;
-+ int num_packets, len, n_desc = 0;
-+
-+ hc = qh->channel;
-+
-+ /*
-+ * Start with hc->xfer_buff initialized in
-+ * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
-+ * this pointer re-assigned to the buffer of the currently processed QTD.
-+ * For non-SG request there is always one QTD active.
-+ */
-+
-+ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
-+
-+ if (n_desc) {
-+ /* SG request - more than 1 QTDs */
-+ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
-+ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
-+ }
-+
-+ qtd->n_desc = 0;
-+
-+ do {
-+ dma_desc = &qh->desc_list[n_desc];
-+ len = hc->xfer_len;
-+
-+ if (len > MAX_DMA_DESC_SIZE)
-+ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
-+
-+ if (hc->ep_is_in) {
-+ if (len > 0) {
-+ num_packets = (len + hc->max_packet - 1) / hc->max_packet;
-+ } else {
-+ /* Need 1 packet for transfer length of 0. */
-+ num_packets = 1;
-+ }
-+ /* Always program an integral # of max packets for IN transfers. */
-+ len = num_packets * hc->max_packet;
-+ }
-+
-+ dma_desc->status.b.n_bytes = len;
-+
-+ qh->n_bytes[n_desc] = len;
-+
-+ if ((qh->ep_type == UE_CONTROL)
-+ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
-+ dma_desc->status.b.sup = 1; /* Setup Packet */
-+
-+ dma_desc->status.b.a = 1; /* Active descriptor */
-+ dma_desc->status.b.sts = 0;
-+
-+ dma_desc->buf =
-+ ((unsigned long)hc->xfer_buff & 0xffffffff);
-+
-+ /*
-+ * Last descriptor(or single) of IN transfer
-+ * with actual size less than MaxPacket.
-+ */
-+ if (len > hc->xfer_len) {
-+ hc->xfer_len = 0;
-+ } else {
-+ hc->xfer_buff += len;
-+ hc->xfer_len -= len;
-+ }
-+
-+ qtd->n_desc++;
-+ n_desc++;
-+ }
-+ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
-+
-+
-+ qtd->in_process = 1;
-+
-+ if (qh->ep_type == UE_CONTROL)
-+ break;
-+
-+ if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
-+ break;
-+ }
-+
-+ if (n_desc) {
-+ /* Request Transfer Complete interrupt for the last descriptor */
-+ qh->desc_list[n_desc - 1].status.b.ioc = 1;
-+ /* End of List indicator */
-+ qh->desc_list[n_desc - 1].status.b.eol = 1;
-+
-+ hc->ntd = n_desc;
-+ }
-+}
-+
-+/**
-+ * For Control and Bulk endpoints initializes descriptor list
-+ * and starts the transfer.
-+ *
-+ * For Interrupt and Isochronous endpoints initializes descriptor list
-+ * then updates FrameList, marking appropriate entries as active.
-+ * In case of Isochronous, the starting descriptor index is calculated based
-+ * on the scheduled frame, but only on the first transfer descriptor within a session.
-+ * Then starts the transfer via enabling the channel.
-+ * For Isochronous endpoint the channel is not halted on XferComplete
-+ * interrupt so remains assigned to the endpoint(QH) until session is done.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ /* Channel is already assigned */
-+ dwc_hc_t *hc = qh->channel;
-+ uint8_t skip_frames = 0;
-+
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ init_non_isoc_dma_desc(hcd, qh);
-+
-+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+ break;
-+ case DWC_OTG_EP_TYPE_INTR:
-+ init_non_isoc_dma_desc(hcd, qh);
-+
-+ update_frame_list(hcd, qh, 1);
-+
-+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+ break;
-+ case DWC_OTG_EP_TYPE_ISOC:
-+
-+ if (!qh->ntd)
-+ skip_frames = recalc_initial_desc_idx(hcd, qh);
-+
-+ init_isoc_dma_desc(hcd, qh, skip_frames);
-+
-+ if (!hc->xfer_started) {
-+
-+ update_frame_list(hcd, qh, 1);
-+
-+ /*
-+ * Always set to max, instead of actual size.
-+ * Otherwise ntd will be changed with
-+ * channel being enabled. Not recommended.
-+ *
-+ */
-+ hc->ntd = max_desc_num(qh);
-+ /* Enable channel only once for ISOC */
-+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+ }
-+
-+ break;
-+ default:
-+
-+ break;
-+ }
-+}
-+
-+static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ uint16_t idx, remain;
-+ uint8_t urb_compl;
-+
-+ qh = hc->qh;
-+ idx = qh->td_first;
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
-+ qtd->in_process = 0;
-+ return;
-+ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
-+ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
-+ /*
-+ * Channel is halted in these error cases.
-+ * Considered as serious issues.
-+ * Complete all URBs marking all frames as failed,
-+ * irrespective whether some of the descriptors(frames) succeeded or no.
-+ * Pass error code to completion routine as well, to
-+ * update urb->status, some of class drivers might use it to stop
-+ * queing transfer requests.
-+ */
-+ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
-+ ? (-DWC_E_IO)
-+ : (-DWC_E_OVERFLOW);
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+ for (idx = 0; idx < qtd->urb->packet_count; idx++) {
-+ frame_desc = &qtd->urb->iso_descs[idx];
-+ frame_desc->status = err;
-+ }
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+ }
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+
-+ if (!qtd->in_process)
-+ break;
-+
-+ urb_compl = 0;
-+
-+ do {
-+
-+ dma_desc = &qh->desc_list[idx];
-+
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
-+
-+ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
-+ /*
-+ * XactError or, unable to complete all the transactions
-+ * in the scheduled micro-frame/frame,
-+ * both indicated by DMA_DESC_STS_PKTERR.
-+ */
-+ qtd->urb->error_count++;
-+ frame_desc->actual_length = qh->n_bytes[idx] - remain;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ } else {
-+ /* Success */
-+
-+ frame_desc->actual_length = qh->n_bytes[idx] - remain;
-+ frame_desc->status = 0;
-+ }
-+
-+ if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ /*
-+ * urb->status is not used for isoc transfers here.
-+ * The individual frame_desc status are used instead.
-+ */
-+
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+
-+ /*
-+ * This check is necessary because urb_dequeue can be called
-+ * from urb complete callback(sound driver example).
-+ * All pending URBs are dequeued there, so no need for
-+ * further processing.
-+ */
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ return;
-+ }
-+
-+ urb_compl = 1;
-+
-+ }
-+
-+ qh->ntd--;
-+
-+ /* Stop if IOC requested descriptor reached */
-+ if (dma_desc->status.b_isoc.ioc) {
-+ idx = desclist_idx_inc(idx, qh->interval, hc->speed);
-+ goto stop_scan;
-+ }
-+
-+ idx = desclist_idx_inc(idx, qh->interval, hc->speed);
-+
-+ if (urb_compl)
-+ break;
-+ }
-+ while (idx != qh->td_first);
-+ }
-+stop_scan:
-+ qh->td_first = idx;
-+}
-+
-+uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_host_dma_desc_t * dma_desc,
-+ dwc_otg_halt_status_e halt_status,
-+ uint32_t n_bytes, uint8_t * xfer_done)
-+{
-+
-+ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+ urb->status = -DWC_E_IO;
-+ return 1;
-+ }
-+ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
-+ switch (halt_status) {
-+ case DWC_OTG_HC_XFER_STALL:
-+ urb->status = -DWC_E_PIPE;
-+ break;
-+ case DWC_OTG_HC_XFER_BABBLE_ERR:
-+ urb->status = -DWC_E_OVERFLOW;
-+ break;
-+ case DWC_OTG_HC_XFER_XACT_ERR:
-+ urb->status = -DWC_E_PROTOCOL;
-+ break;
-+ default:
-+ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
-+ halt_status);
-+ break;
-+ }
-+ return 1;
-+ }
-+
-+ if (dma_desc->status.b.a == 1) {
-+ DWC_DEBUGPL(DBG_HCDV,
-+ "Active descriptor encountered on channel %d\n",
-+ hc->hc_num);
-+ return 0;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
-+ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
-+ urb->actual_length += n_bytes - remain;
-+ if (remain || urb->actual_length == urb->length) {
-+ /*
-+ * For Control Data stage do not set urb->status=0 to prevent
-+ * URB callback. Set it when Status phase done. See below.
-+ */
-+ *xfer_done = 1;
-+ }
-+
-+ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
-+ urb->status = 0;
-+ *xfer_done = 1;
-+ }
-+ /* No handling for SETUP stage */
-+ } else {
-+ /* BULK and INTR */
-+ urb->actual_length += n_bytes - remain;
-+ if (remain || urb->actual_length == urb->length) {
-+ urb->status = 0;
-+ *xfer_done = 1;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ dwc_otg_hcd_urb_t *urb = NULL;
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ uint32_t n_bytes, n_desc, i;
-+ uint8_t failed = 0, xfer_done;
-+
-+ n_desc = 0;
-+
-+ qh = hc->qh;
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+ qtd->in_process = 0;
-+ }
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
-+
-+ urb = qtd->urb;
-+
-+ n_bytes = 0;
-+ xfer_done = 0;
-+
-+ for (i = 0; i < qtd->n_desc; i++) {
-+ dma_desc = &qh->desc_list[n_desc];
-+
-+ n_bytes = qh->n_bytes[n_desc];
-+
-+ failed =
-+ update_non_isoc_urb_state_ddma(hcd, hc, qtd,
-+ dma_desc,
-+ halt_status, n_bytes,
-+ &xfer_done);
-+
-+ if (failed
-+ || (xfer_done
-+ && (urb->status != -DWC_E_IN_PROGRESS))) {
-+
-+ hcd->fops->complete(hcd, urb->priv, urb,
-+ urb->status);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+
-+ if (failed)
-+ goto stop_scan;
-+ } else if (qh->ep_type == UE_CONTROL) {
-+ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
-+ if (urb->length > 0) {
-+ qtd->control_phase = DWC_OTG_CONTROL_DATA;
-+ } else {
-+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+ }
-+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
-+ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
-+ if (xfer_done) {
-+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
-+ } else if (i + 1 == qtd->n_desc) {
-+ /*
-+ * Last descriptor for Control data stage which is
-+ * not completed yet.
-+ */
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ }
-+ }
-+ }
-+
-+ n_desc++;
-+ }
-+
-+ }
-+
-+stop_scan:
-+
-+ if (qh->ep_type != UE_CONTROL) {
-+ /*
-+ * Resetting the data toggle for bulk
-+ * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
-+ */
-+ if (halt_status == DWC_OTG_HC_XFER_STALL)
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ else
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ }
-+
-+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+ hcint_data_t hcint;
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ if (hcint.b.nyet) {
-+ /*
-+ * Got a NYET on the last transaction of the transfer. It
-+ * means that the endpoint should be in the PING state at the
-+ * beginning of the next transfer.
-+ */
-+ qh->ping_state = 1;
-+ clear_hc_int(hc_regs, nyet);
-+ }
-+
-+ }
-+
-+}
-+
-+/**
-+ * This function is called from interrupt handlers.
-+ * Scans the descriptor list, updates URB's status and
-+ * calls completion routine for the URB if it's done.
-+ * Releases the channel to be used by other transfers.
-+ * In case of Isochronous endpoint the channel is not halted until
-+ * the end of the session, i.e. QTD list is empty.
-+ * If periodic channel released the FrameList is updated accordingly.
-+ *
-+ * Calls transaction selection routines to activate pending transfers.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param hc Host channel, the transfer is completed on.
-+ * @param hc_regs Host channel registers.
-+ * @param halt_status Reason the channel is being halted,
-+ * or just XferComplete for isochronous transfer
-+ */
-+void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ uint8_t continue_isoc_xfer = 0;
-+ dwc_otg_transaction_type_e tr_type;
-+ dwc_otg_qh_t *qh = hc->qh;
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+
-+ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+
-+ /* Release the channel if halted or session completed */
-+ if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
-+ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+
-+ /* Halt the channel if session completed */
-+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
-+ }
-+
-+ release_channel_ddma(hcd, qh);
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ } else {
-+ /* Keep in assigned schedule to continue transfer */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+ &qh->qh_list_entry);
-+ continue_isoc_xfer = 1;
-+
-+ }
-+ /** @todo Consider the case when period exceeds FrameList size.
-+ * Frame Rollover interrupt should be used.
-+ */
-+ } else {
-+ /* Scan descriptor list to complete the URB(s), then release the channel */
-+ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+
-+ release_channel_ddma(hcd, qh);
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ /* Add back to inactive non-periodic schedule on normal completion */
-+ dwc_otg_hcd_qh_add(hcd, qh);
-+ }
-+
-+ }
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
-+ if (continue_isoc_xfer) {
-+ if (tr_type == DWC_OTG_TRANSACTION_NONE) {
-+ tr_type = DWC_OTG_TRANSACTION_PERIODIC;
-+ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
-+ tr_type = DWC_OTG_TRANSACTION_ALL;
-+ }
-+ }
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ }
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,862 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
-+ * $Revision: #58 $
-+ * $Date: 2011/09/15 $
-+ * $Change: 1846647 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+#ifndef __DWC_HCD_H__
-+#define __DWC_HCD_H__
-+
-+#include "dwc_otg_os_dep.h"
-+#include "usb.h"
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_list.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the structures, constants, and interfaces for
-+ * the Host Contoller Driver (HCD).
-+ *
-+ * The Host Controller Driver (HCD) is responsible for translating requests
-+ * from the USB Driver into the appropriate actions on the DWC_otg controller.
-+ * It isolates the USBD from the specifics of the controller by providing an
-+ * API to the USBD.
-+ */
-+
-+struct dwc_otg_hcd_pipe_info {
-+ uint8_t dev_addr;
-+ uint8_t ep_num;
-+ uint8_t pipe_type;
-+ uint8_t pipe_dir;
-+ uint16_t mps;
-+};
-+
-+struct dwc_otg_hcd_iso_packet_desc {
-+ uint32_t offset;
-+ uint32_t length;
-+ uint32_t actual_length;
-+ uint32_t status;
-+};
-+
-+struct dwc_otg_qtd;
-+
-+struct dwc_otg_hcd_urb {
-+ void *priv;
-+ struct dwc_otg_qtd *qtd;
-+ void *buf;
-+ dwc_dma_t dma;
-+ void *setup_packet;
-+ dwc_dma_t setup_dma;
-+ uint32_t length;
-+ uint32_t actual_length;
-+ uint32_t status;
-+ uint32_t error_count;
-+ uint32_t packet_count;
-+ uint32_t flags;
-+ uint16_t interval;
-+ struct dwc_otg_hcd_pipe_info pipe_info;
-+ struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
-+};
-+
-+static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+ return pipe->ep_num;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return pipe->pipe_type;
-+}
-+
-+static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+ return pipe->mps;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return pipe->dev_addr;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_ISOCHRONOUS);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_INTERRUPT);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_BULK);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_CONTROL);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+ return (pipe->pipe_dir == UE_DIR_IN);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (!dwc_otg_hcd_is_pipe_in(pipe));
-+}
-+
-+static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
-+ uint8_t devaddr, uint8_t ep_num,
-+ uint8_t pipe_type, uint8_t pipe_dir,
-+ uint16_t mps)
-+{
-+ pipe->dev_addr = devaddr;
-+ pipe->ep_num = ep_num;
-+ pipe->pipe_type = pipe_type;
-+ pipe->pipe_dir = pipe_dir;
-+ pipe->mps = mps;
-+}
-+
-+/**
-+ * Phases for control transfers.
-+ */
-+typedef enum dwc_otg_control_phase {
-+ DWC_OTG_CONTROL_SETUP,
-+ DWC_OTG_CONTROL_DATA,
-+ DWC_OTG_CONTROL_STATUS
-+} dwc_otg_control_phase_e;
-+
-+/** Transaction types. */
-+typedef enum dwc_otg_transaction_type {
-+ DWC_OTG_TRANSACTION_NONE = 0,
-+ DWC_OTG_TRANSACTION_PERIODIC = 1,
-+ DWC_OTG_TRANSACTION_NON_PERIODIC = 2,
-+ DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
-+} dwc_otg_transaction_type_e;
-+
-+struct dwc_otg_qh;
-+
-+/**
-+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
-+ * interrupt, or isochronous transfer. A single QTD is created for each URB
-+ * (of one of these types) submitted to the HCD. The transfer associated with
-+ * a QTD may require one or multiple transactions.
-+ *
-+ * A QTD is linked to a Queue Head, which is entered in either the
-+ * non-periodic or periodic schedule for execution. When a QTD is chosen for
-+ * execution, some or all of its transactions may be executed. After
-+ * execution, the state of the QTD is updated. The QTD may be retired if all
-+ * its transactions are complete or if an error occurred. Otherwise, it
-+ * remains in the schedule so more transactions can be executed later.
-+ */
-+typedef struct dwc_otg_qtd {
-+ /**
-+ * Determines the PID of the next data packet for the data phase of
-+ * control transfers. Ignored for other transfer types.<br>
-+ * One of the following values:
-+ * - DWC_OTG_HC_PID_DATA0
-+ * - DWC_OTG_HC_PID_DATA1
-+ */
-+ uint8_t data_toggle;
-+
-+ /** Current phase for control transfers (Setup, Data, or Status). */
-+ dwc_otg_control_phase_e control_phase;
-+
-+ /** Keep track of the current split type
-+ * for FS/LS endpoints on a HS Hub */
-+ uint8_t complete_split;
-+
-+ /** How many bytes transferred during SSPLIT OUT */
-+ uint32_t ssplit_out_xfer_count;
-+
-+ /**
-+ * Holds the number of bus errors that have occurred for a transaction
-+ * within this transfer.
-+ */
-+ uint8_t error_count;
-+
-+ /**
-+ * Index of the next frame descriptor for an isochronous transfer. A
-+ * frame descriptor describes the buffer position and length of the
-+ * data to be transferred in the next scheduled (micro)frame of an
-+ * isochronous transfer. It also holds status for that transaction.
-+ * The frame index starts at 0.
-+ */
-+ uint16_t isoc_frame_index;
-+
-+ /** Position of the ISOC split on full/low speed */
-+ uint8_t isoc_split_pos;
-+
-+ /** Position of the ISOC split in the buffer for the current frame */
-+ uint16_t isoc_split_offset;
-+
-+ /** URB for this transfer */
-+ struct dwc_otg_hcd_urb *urb;
-+
-+ struct dwc_otg_qh *qh;
-+
-+ /** This list of QTDs */
-+ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
-+
-+ /** Indicates if this QTD is currently processed by HW. */
-+ uint8_t in_process;
-+
-+ /** Number of DMA descriptors for this QTD */
-+ uint8_t n_desc;
-+
-+ /**
-+ * Last activated frame(packet) index.
-+ * Used in Descriptor DMA mode only.
-+ */
-+ uint16_t isoc_frame_index_last;
-+
-+} dwc_otg_qtd_t;
-+
-+DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
-+
-+/**
-+ * A Queue Head (QH) holds the static characteristics of an endpoint and
-+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
-+ * be entered in either the non-periodic or periodic schedule.
-+ */
-+typedef struct dwc_otg_qh {
-+ /**
-+ * Endpoint type.
-+ * One of the following values:
-+ * - UE_CONTROL
-+ * - UE_BULK
-+ * - UE_INTERRUPT
-+ * - UE_ISOCHRONOUS
-+ */
-+ uint8_t ep_type;
-+ uint8_t ep_is_in;
-+
-+ /** wMaxPacketSize Field of Endpoint Descriptor. */
-+ uint16_t maxp;
-+
-+ /**
-+ * Device speed.
-+ * One of the following values:
-+ * - DWC_OTG_EP_SPEED_LOW
-+ * - DWC_OTG_EP_SPEED_FULL
-+ * - DWC_OTG_EP_SPEED_HIGH
-+ */
-+ uint8_t dev_speed;
-+
-+ /**
-+ * Determines the PID of the next data packet for non-control
-+ * transfers. Ignored for control transfers.<br>
-+ * One of the following values:
-+ * - DWC_OTG_HC_PID_DATA0
-+ * - DWC_OTG_HC_PID_DATA1
-+ */
-+ uint8_t data_toggle;
-+
-+ /** Ping state if 1. */
-+ uint8_t ping_state;
-+
-+ /**
-+ * List of QTDs for this QH.
-+ */
-+ struct dwc_otg_qtd_list qtd_list;
-+
-+ /** Host channel currently processing transfers for this QH. */
-+ struct dwc_hc *channel;
-+
-+ /** Full/low speed endpoint on high-speed hub requires split. */
-+ uint8_t do_split;
-+
-+ /** @name Periodic schedule information */
-+ /** @{ */
-+
-+ /** Bandwidth in microseconds per (micro)frame. */
-+ uint16_t usecs;
-+
-+ /** Interval between transfers in (micro)frames. */
-+ uint16_t interval;
-+
-+ /**
-+ * (micro)frame to initialize a periodic transfer. The transfer
-+ * executes in the following (micro)frame.
-+ */
-+ uint16_t sched_frame;
-+
-+ /*
-+ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission
-+ */
-+ uint16_t nak_frame;
-+
-+ /** (micro)frame at which last start split was initialized. */
-+ uint16_t start_split_frame;
-+
-+ /** @} */
-+
-+ /**
-+ * Used instead of original buffer if
-+ * it(physical address) is not dword-aligned.
-+ */
-+ uint8_t *dw_align_buf;
-+ dwc_dma_t dw_align_buf_dma;
-+
-+ /** Entry for QH in either the periodic or non-periodic schedule. */
-+ dwc_list_link_t qh_list_entry;
-+
-+ /** @name Descriptor DMA support */
-+ /** @{ */
-+
-+ /** Descriptor List. */
-+ dwc_otg_host_dma_desc_t *desc_list;
-+
-+ /** Descriptor List physical address. */
-+ dwc_dma_t desc_list_dma;
-+
-+ /**
-+ * Xfer Bytes array.
-+ * Each element corresponds to a descriptor and indicates
-+ * original XferSize size value for the descriptor.
-+ */
-+ uint32_t *n_bytes;
-+
-+ /** Actual number of transfer descriptors in a list. */
-+ uint16_t ntd;
-+
-+ /** First activated isochronous transfer descriptor index. */
-+ uint8_t td_first;
-+ /** Last activated isochronous transfer descriptor index. */
-+ uint8_t td_last;
-+
-+ /** @} */
-+
-+
-+ uint16_t speed;
-+ uint16_t frame_usecs[8];
-+
-+ uint32_t skip_count;
-+} dwc_otg_qh_t;
-+
-+DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
-+
-+typedef struct urb_tq_entry {
-+ struct urb *urb;
-+ DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
-+} urb_tq_entry_t;
-+
-+DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
-+
-+/**
-+ * This structure holds the state of the HCD, including the non-periodic and
-+ * periodic schedules.
-+ */
-+struct dwc_otg_hcd {
-+ /** The DWC otg device pointer */
-+ struct dwc_otg_device *otg_dev;
-+ /** DWC OTG Core Interface Layer */
-+ dwc_otg_core_if_t *core_if;
-+
-+ /** Function HCD driver callbacks */
-+ struct dwc_otg_hcd_function_ops *fops;
-+
-+ /** Internal DWC HCD Flags */
-+ volatile union dwc_otg_hcd_internal_flags {
-+ uint32_t d32;
-+ struct {
-+ unsigned port_connect_status_change:1;
-+ unsigned port_connect_status:1;
-+ unsigned port_reset_change:1;
-+ unsigned port_enable_change:1;
-+ unsigned port_suspend_change:1;
-+ unsigned port_over_current_change:1;
-+ unsigned port_l1_change:1;
-+ unsigned reserved:26;
-+ } b;
-+ } flags;
-+
-+ /**
-+ * Inactive items in the non-periodic schedule. This is a list of
-+ * Queue Heads. Transfers associated with these Queue Heads are not
-+ * currently assigned to a host channel.
-+ */
-+ dwc_list_link_t non_periodic_sched_inactive;
-+
-+ /**
-+ * Active items in the non-periodic schedule. This is a list of
-+ * Queue Heads. Transfers associated with these Queue Heads are
-+ * currently assigned to a host channel.
-+ */
-+ dwc_list_link_t non_periodic_sched_active;
-+
-+ /**
-+ * Pointer to the next Queue Head to process in the active
-+ * non-periodic schedule.
-+ */
-+ dwc_list_link_t *non_periodic_qh_ptr;
-+
-+ /**
-+ * Inactive items in the periodic schedule. This is a list of QHs for
-+ * periodic transfers that are _not_ scheduled for the next frame.
-+ * Each QH in the list has an interval counter that determines when it
-+ * needs to be scheduled for execution. This scheduling mechanism
-+ * allows only a simple calculation for periodic bandwidth used (i.e.
-+ * must assume that all periodic transfers may need to execute in the
-+ * same frame). However, it greatly simplifies scheduling and should
-+ * be sufficient for the vast majority of OTG hosts, which need to
-+ * connect to a small number of peripherals at one time.
-+ *
-+ * Items move from this list to periodic_sched_ready when the QH
-+ * interval counter is 0 at SOF.
-+ */
-+ dwc_list_link_t periodic_sched_inactive;
-+
-+ /**
-+ * List of periodic QHs that are ready for execution in the next
-+ * frame, but have not yet been assigned to host channels.
-+ *
-+ * Items move from this list to periodic_sched_assigned as host
-+ * channels become available during the current frame.
-+ */
-+ dwc_list_link_t periodic_sched_ready;
-+
-+ /**
-+ * List of periodic QHs to be executed in the next frame that are
-+ * assigned to host channels.
-+ *
-+ * Items move from this list to periodic_sched_queued as the
-+ * transactions for the QH are queued to the DWC_otg controller.
-+ */
-+ dwc_list_link_t periodic_sched_assigned;
-+
-+ /**
-+ * List of periodic QHs that have been queued for execution.
-+ *
-+ * Items move from this list to either periodic_sched_inactive or
-+ * periodic_sched_ready when the channel associated with the transfer
-+ * is released. If the interval for the QH is 1, the item moves to
-+ * periodic_sched_ready because it must be rescheduled for the next
-+ * frame. Otherwise, the item moves to periodic_sched_inactive.
-+ */
-+ dwc_list_link_t periodic_sched_queued;
-+
-+ /**
-+ * Total bandwidth claimed so far for periodic transfers. This value
-+ * is in microseconds per (micro)frame. The assumption is that all
-+ * periodic transfers may occur in the same (micro)frame.
-+ */
-+ uint16_t periodic_usecs;
-+
-+ /**
-+ * Total bandwidth claimed so far for all periodic transfers
-+ * in a frame.
-+ * This will include a mixture of HS and FS transfers.
-+ * Units are microseconds per (micro)frame.
-+ * We have a budget per frame and have to schedule
-+ * transactions accordingly.
-+ * Watch out for the fact that things are actually scheduled for the
-+ * "next frame".
-+ */
-+ uint16_t frame_usecs[8];
-+
-+
-+ /**
-+ * Frame number read from the core at SOF. The value ranges from 0 to
-+ * DWC_HFNUM_MAX_FRNUM.
-+ */
-+ uint16_t frame_number;
-+
-+ /**
-+ * Count of periodic QHs, if using several eps. For SOF enable/disable.
-+ */
-+ uint16_t periodic_qh_count;
-+
-+ /**
-+ * Free host channels in the controller. This is a list of
-+ * dwc_hc_t items.
-+ */
-+ struct hc_list free_hc_list;
-+ /**
-+ * Number of host channels assigned to periodic transfers. Currently
-+ * assuming that there is a dedicated host channel for each periodic
-+ * transaction and at least one host channel available for
-+ * non-periodic transactions.
-+ */
-+ int periodic_channels; /* microframe_schedule==0 */
-+
-+ /**
-+ * Number of host channels assigned to non-periodic transfers.
-+ */
-+ int non_periodic_channels; /* microframe_schedule==0 */
-+
-+ /**
-+ * Number of host channels assigned to non-periodic transfers.
-+ */
-+ int available_host_channels;
-+
-+ /**
-+ * Array of pointers to the host channel descriptors. Allows accessing
-+ * a host channel descriptor given the host channel number. This is
-+ * useful in interrupt handlers.
-+ */
-+ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
-+
-+ /**
-+ * Buffer to use for any data received during the status phase of a
-+ * control transfer. Normally no data is transferred during the status
-+ * phase. This buffer is used as a bit bucket.
-+ */
-+ uint8_t *status_buf;
-+
-+ /**
-+ * DMA address for status_buf.
-+ */
-+ dma_addr_t status_buf_dma;
-+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
-+
-+ /**
-+ * Connection timer. An OTG host must display a message if the device
-+ * does not connect. Started when the VBus power is turned on via
-+ * sysfs attribute "buspower".
-+ */
-+ dwc_timer_t *conn_timer;
-+
-+ /* Tasket to do a reset */
-+ dwc_tasklet_t *reset_tasklet;
-+
-+ dwc_tasklet_t *completion_tasklet;
-+ struct urb_list completed_urb_list;
-+
-+ /* */
-+ dwc_spinlock_t *lock;
-+ dwc_spinlock_t *channel_lock;
-+ /**
-+ * Private data that could be used by OS wrapper.
-+ */
-+ void *priv;
-+
-+ uint8_t otg_port;
-+
-+ /** Frame List */
-+ uint32_t *frame_list;
-+
-+ /** Hub - Port assignment */
-+ int hub_port[128];
-+#ifdef FIQ_DEBUG
-+ int hub_port_alloc[2048];
-+#endif
-+
-+ /** Frame List DMA address */
-+ dma_addr_t frame_list_dma;
-+
-+ struct fiq_stack *fiq_stack;
-+ struct fiq_state *fiq_state;
-+
-+ /** Virtual address for split transaction DMA bounce buffers */
-+ struct fiq_dma_blob *fiq_dmab;
-+
-+#ifdef DEBUG
-+ uint32_t frrem_samples;
-+ uint64_t frrem_accum;
-+
-+ uint32_t hfnum_7_samples_a;
-+ uint64_t hfnum_7_frrem_accum_a;
-+ uint32_t hfnum_0_samples_a;
-+ uint64_t hfnum_0_frrem_accum_a;
-+ uint32_t hfnum_other_samples_a;
-+ uint64_t hfnum_other_frrem_accum_a;
-+
-+ uint32_t hfnum_7_samples_b;
-+ uint64_t hfnum_7_frrem_accum_b;
-+ uint32_t hfnum_0_samples_b;
-+ uint64_t hfnum_0_frrem_accum_b;
-+ uint32_t hfnum_other_samples_b;
-+ uint64_t hfnum_other_frrem_accum_b;
-+#endif
-+};
-+
-+/** @name Transaction Execution Functions */
-+/** @{ */
-+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
-+ * hcd);
-+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
-+ dwc_otg_transaction_type_e tr_type);
-+
-+int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
-+void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
-+
-+extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
-+extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh);
-+extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
-+
-+/** @} */
-+
-+/** @name Interrupt Handler Functions */
-+/** @{ */
-+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
-+ uint32_t num);
-+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+/** @} */
-+
-+/** @name Schedule Queue Functions */
-+/** @{ */
-+
-+/* Implemented in dwc_otg_hcd_queue.c */
-+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * urb, int atomic_alloc);
-+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ int sched_csplit);
-+
-+/** Remove and free a QH */
-+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
-+ dwc_otg_qh_t * qh)
-+{
-+ dwc_irqflags_t flags;
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ dwc_otg_hcd_qh_free(hcd, qh);
-+}
-+
-+/** Allocates memory for a QH structure.
-+ * @return Returns the memory allocate or NULL on error. */
-+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
-+{
-+ if (atomic_alloc)
-+ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
-+ else
-+ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
-+}
-+
-+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
-+ int atomic_alloc);
-+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
-+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
-+ dwc_otg_qh_t ** qh, int atomic_alloc);
-+
-+/** Allocates memory for a QTD structure.
-+ * @return Returns the memory allocate or NULL on error. */
-+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
-+{
-+ if (atomic_alloc)
-+ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
-+ else
-+ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
-+}
-+
-+/** Frees the memory for a QTD structure. QTD should already be removed from
-+ * list.
-+ * @param qtd QTD to free.*/
-+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
-+{
-+ DWC_FREE(qtd);
-+}
-+
-+/** Removes a QTD from list.
-+ * @param hcd HCD instance.
-+ * @param qtd QTD to remove from list.
-+ * @param qh QTD belongs to.
-+ */
-+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_qh_t * qh)
-+{
-+ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
-+}
-+
-+/** Remove and free a QTD
-+ * Need to disable IRQ and hold hcd lock while calling this function out of
-+ * interrupt servicing chain */
-+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_qh_t * qh)
-+{
-+ dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
-+ dwc_otg_hcd_qtd_free(qtd);
-+}
-+
-+/** @} */
-+
-+/** @name Descriptor DMA Supporting Functions */
-+/** @{ */
-+
-+extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status);
-+
-+extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+
-+/** @} */
-+
-+/** @name Internal Functions */
-+/** @{ */
-+dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
-+/** @} */
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
-+ uint8_t devaddr);
-+extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
-+#endif
-+
-+/** Gets the QH that contains the list_head */
-+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
-+
-+/** Gets the QTD that contains the list_head */
-+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
-+
-+/** Check if QH is non-periodic */
-+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
-+ (_qh_ptr_->ep_type == UE_CONTROL))
-+
-+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
-+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
-+
-+/** Packet size for any kind of endpoint descriptor */
-+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
-+
-+/**
-+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
-+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
-+ * frame number when the max frame number is reached.
-+ */
-+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
-+{
-+ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
-+ (DWC_HFNUM_MAX_FRNUM >> 1);
-+}
-+
-+/**
-+ * Returns true if _frame1 is greater than _frame2. The comparison is done
-+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
-+ * number when the max frame number is reached.
-+ */
-+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
-+{
-+ return (frame1 != frame2) &&
-+ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
-+ (DWC_HFNUM_MAX_FRNUM >> 1));
-+}
-+
-+/**
-+ * Increments _frame by the amount specified by _inc. The addition is done
-+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
-+ */
-+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
-+{
-+ return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
-+}
-+
-+static inline uint16_t dwc_full_frame_num(uint16_t frame)
-+{
-+ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
-+}
-+
-+static inline uint16_t dwc_micro_frame_num(uint16_t frame)
-+{
-+ return frame & 0x7;
-+}
-+
-+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd);
-+
-+#ifdef DEBUG
-+/**
-+ * Macro to sample the remaining PHY clocks left in the current frame. This
-+ * may be used during debugging to determine the average time it takes to
-+ * execute sections of code. There are two possible sample points, "a" and
-+ * "b", so the _letter argument must be one of these values.
-+ *
-+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
-+ * example, "cat /sys/devices/lm0/hcd_frrem".
-+ */
-+#define dwc_sample_frrem(_hcd, _qh, _letter) \
-+{ \
-+ hfnum_data_t hfnum; \
-+ dwc_otg_qtd_t *qtd; \
-+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
-+ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
-+ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
-+ switch (hfnum.b.frnum & 0x7) { \
-+ case 7: \
-+ _hcd->hfnum_7_samples_##_letter++; \
-+ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
-+ break; \
-+ case 0: \
-+ _hcd->hfnum_0_samples_##_letter++; \
-+ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
-+ break; \
-+ default: \
-+ _hcd->hfnum_other_samples_##_letter++; \
-+ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
-+ break; \
-+ } \
-+ } \
-+}
-+#else
-+#define dwc_sample_frrem(_hcd, _qh, _letter)
-+#endif
-+#endif
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,417 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
-+ * $Revision: #12 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+#ifndef __DWC_HCD_IF_H__
-+#define __DWC_HCD_IF_H__
-+
-+#include "dwc_otg_core_if.h"
-+
-+/** @file
-+ * This file defines DWC_OTG HCD Core API.
-+ */
-+
-+struct dwc_otg_hcd;
-+typedef struct dwc_otg_hcd dwc_otg_hcd_t;
-+
-+struct dwc_otg_hcd_urb;
-+typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
-+
-+/** @name HCD Function Driver Callbacks */
-+/** @{ */
-+
-+/** This function is called whenever core switches to host mode. */
-+typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
-+
-+/** This function is called when device has been disconnected */
-+typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
-+
-+/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
-+typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+ void *urb_handle,
-+ uint32_t * hub_addr,
-+ uint32_t * port_addr);
-+/** Via this function HCD core gets device speed */
-+typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+ void *urb_handle);
-+
-+/** This function is called when urb is completed */
-+typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+ void *urb_handle,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int32_t status);
-+
-+/** Via this function HCD core gets b_hnp_enable parameter */
-+typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
-+
-+struct dwc_otg_hcd_function_ops {
-+ dwc_otg_hcd_start_cb_t start;
-+ dwc_otg_hcd_disconnect_cb_t disconnect;
-+ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
-+ dwc_otg_hcd_speed_from_urb_cb_t speed;
-+ dwc_otg_hcd_complete_urb_cb_t complete;
-+ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
-+};
-+/** @} */
-+
-+/** @name HCD Core API */
-+/** @{ */
-+/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
-+extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
-+
-+/** This function should be called to initiate HCD Core.
-+ *
-+ * @param hcd The HCD
-+ * @param core_if The DWC_OTG Core
-+ *
-+ * Returns -DWC_E_NO_MEMORY if no enough memory.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
-+
-+/** Frees HCD
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
-+
-+/** This function should be called on every hardware interrupt.
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ *
-+ * Returns non zero if interrupt is handled
-+ * Return 0 if interrupt is not handled
-+ */
-+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+
-+/** This function is used to handle the fast interrupt
-+ *
-+ */
-+extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
-+
-+/**
-+ * Returns private data set by
-+ * dwc_otg_hcd_set_priv_data function.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Set private data.
-+ *
-+ * @param hcd The HCD
-+ * @param priv_data pointer to be stored in private data
-+ */
-+extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
-+
-+/**
-+ * This function initializes the HCD Core.
-+ *
-+ * @param hcd The HCD
-+ * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
-+ *
-+ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
-+ struct dwc_otg_hcd_function_ops *fops);
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Handles hub class-specific requests.
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param typeReq Request Type
-+ * @param wValue wValue from control request
-+ * @param wIndex wIndex from control request
-+ * @param buf data buffer
-+ * @param wLength data buffer length
-+ *
-+ * Returns -DWC_E_INVALID if invalid argument is passed
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
-+ uint16_t typeReq, uint16_t wValue,
-+ uint16_t wIndex, uint8_t * buf,
-+ uint16_t wLength);
-+
-+/**
-+ * Returns otg port number.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Returns OTG version - either 1.3 or 2.0.
-+ *
-+ * @param core_if The core_if structure pointer
-+ */
-+extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Returns 1 if currently core is acting as B host, and 0 otherwise.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Returns current frame number.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Dumps hcd state.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ * Currently this function is not implemented.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Sends LPM transaction to the local device.
-+ *
-+ * @param hcd The HCD
-+ * @param devaddr Device Address
-+ * @param hird Host initiated resume duration
-+ * @param bRemoteWake Value of bRemoteWake field in LPM transaction
-+ *
-+ * Returns negative value if sending LPM transaction was not succeeded.
-+ * Returns 0 on success.
-+ */
-+extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
-+ uint8_t hird, uint8_t bRemoteWake);
-+
-+/* URB interface */
-+
-+/**
-+ * Allocates memory for dwc_otg_hcd_urb structure.
-+ * Allocated memory should be freed by call of DWC_FREE.
-+ *
-+ * @param hcd The HCD
-+ * @param iso_desc_count Count of ISOC descriptors
-+ * @param atomic_alloc Specefies whether to perform atomic allocation.
-+ */
-+extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
-+ int iso_desc_count,
-+ int atomic_alloc);
-+
-+/**
-+ * Set pipe information in URB.
-+ *
-+ * @param hcd_urb DWC_OTG URB
-+ * @param devaddr Device Address
-+ * @param ep_num Endpoint Number
-+ * @param ep_type Endpoint Type
-+ * @param ep_dir Endpoint Direction
-+ * @param mps Max Packet Size
-+ */
-+extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
-+ uint8_t devaddr, uint8_t ep_num,
-+ uint8_t ep_type, uint8_t ep_dir,
-+ uint16_t mps);
-+
-+/* Transfer flags */
-+#define URB_GIVEBACK_ASAP 0x1
-+#define URB_SEND_ZERO_PACKET 0x2
-+
-+/**
-+ * Sets dwc_otg_hcd_urb parameters.
-+ *
-+ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
-+ * @param urb_handle Unique handle for request, this will be passed back
-+ * to function driver in completion callback.
-+ * @param buf The buffer for the data
-+ * @param dma The DMA buffer for the data
-+ * @param buflen Transfer length
-+ * @param sp Buffer for setup data
-+ * @param sp_dma DMA address of setup data buffer
-+ * @param flags Transfer flags
-+ * @param interval Polling interval for interrupt or isochronous transfers.
-+ */
-+extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
-+ void *urb_handle, void *buf,
-+ dwc_dma_t dma, uint32_t buflen, void *sp,
-+ dwc_dma_t sp_dma, uint32_t flags,
-+ uint16_t interval);
-+
-+/** Gets status from dwc_otg_hcd_urb
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
-+
-+/** Gets actual length from dwc_otg_hcd_urb
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb);
-+
-+/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb);
-+
-+/** Set ISOC descriptor offset and length
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ * @param offset Offset from beginig of buffer.
-+ * @param length Transaction length
-+ */
-+extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int desc_num, uint32_t offset,
-+ uint32_t length);
-+
-+/** Get status of ISOC descriptor, specified by desc_num
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb, int desc_num);
-+
-+/** Get actual length of ISOC descriptor, specified by desc_num
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb,
-+ int desc_num);
-+
-+/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param ep_handle Out parameter for returning endpoint handle
-+ * @param atomic_alloc Flag to do atomic allocation if needed
-+ *
-+ * Returns -DWC_E_NO_DEVICE if no device is connected.
-+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
-+ * Returns 0 on success.
-+ */
-+extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ void **ep_handle, int atomic_alloc);
-+
-+/** De-queue the specified URB
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb);
-+
-+/** Frees resources in the DWC_otg controller related to a given endpoint.
-+ * Any URBs for the endpoint must already be dequeued.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
-+ * @param retry Number of retries if there are queued transfers.
-+ *
-+ * Returns -DWC_E_INVALID if invalid arguments are passed.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
-+ int retry);
-+
-+/* Resets the data toggle in qh structure. This function can be called from
-+ * usb_clear_halt routine.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
-+ *
-+ * Returns -DWC_E_INVALID if invalid arguments are passed.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
-+
-+/** Returns 1 if status of specified port is changed and 0 otherwise.
-+ *
-+ * @param hcd The HCD
-+ * @param port Port number
-+ */
-+extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
-+
-+/** Call this function to check if bandwidth was allocated for specified endpoint.
-+ * Only for ISOC and INTERRUPT endpoints.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
-+ void *ep_handle);
-+
-+/** Call this function to check if bandwidth was freed for specified endpoint.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
-+
-+/** Returns bandwidth allocated for specified endpoint in microseconds.
-+ * Only for ISOC and INTERRUPT endpoints.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
-+ void *ep_handle);
-+
-+/** @} */
-+
-+#endif /* __DWC_HCD_IF_H__ */
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,2688 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
-+ * $Revision: #89 $
-+ * $Date: 2011/10/20 $
-+ * $Change: 1869487 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+#include <linux/jiffies.h>
-+#include <mach/hardware.h>
-+#include <asm/fiq.h>
-+
-+
-+extern bool microframe_schedule;
-+
-+/** @file
-+ * This file contains the implementation of the HCD Interrupt handlers.
-+ */
-+
-+int fiq_done, int_done;
-+
-+#ifdef FIQ_DEBUG
-+char buffer[1000*16];
-+int wptr;
-+void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
-+{
-+ FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
-+ va_list args;
-+ char text[17];
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
-+
-+ if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
-+ {
-+ local_fiq_disable();
-+ snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
-+ va_start(args, fmt);
-+ vsnprintf(text+8, 9, fmt, args);
-+ va_end(args);
-+
-+ memcpy(buffer + wptr, text, 16);
-+ wptr = (wptr + 16) % sizeof(buffer);
-+ local_fiq_enable();
-+ }
-+}
-+#endif
-+
-+/** This function handles interrupts for the HCD. */
-+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int retval = 0;
-+ static int last_time;
-+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+ hfnum_data_t hfnum;
-+ haintmsk_data_t haintmsk;
-+
-+#ifdef DEBUG
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+
-+#endif
-+
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+ /* Exit from ISR if core is hibernated */
-+ if (core_if->hibernation_suspend == 1) {
-+ goto exit_handler_routine;
-+ }
-+ DWC_SPINLOCK(dwc_otg_hcd->lock);
-+ /* Check if HOST Mode */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ /* Pull in from the FIQ's disabled mask */
-+ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
-+ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
-+ }
-+
-+ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
-+ gintsts.b.hcintr = 1;
-+ }
-+
-+ /* Danger will robinson: fake a SOF if necessary */
-+ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
-+ gintsts.b.sofintr = 1;
-+ }
-+ gintsts.d32 &= gintmsk.d32;
-+
-+ if (fiq_enable)
-+ local_fiq_enable();
-+
-+ if (!gintsts.d32) {
-+ goto exit_handler_routine;
-+ }
-+
-+#ifdef DEBUG
-+ // We should be OK doing this because the common interrupts should already have been serviced
-+ /* Don't print debug message in the interrupt handler on SOF */
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ DWC_DEBUGPL(DBG_HCDI, "\n");
-+#endif
-+
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ DWC_DEBUGPL(DBG_HCDI,
-+ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
-+ gintsts.d32, core_if);
-+#endif
-+ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
-+ if (gintsts.b.sofintr) {
-+ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
-+ }
-+
-+ if (gintsts.b.rxstsqlvl) {
-+ retval |=
-+ dwc_otg_hcd_handle_rx_status_q_level_intr
-+ (dwc_otg_hcd);
-+ }
-+ if (gintsts.b.nptxfempty) {
-+ retval |=
-+ dwc_otg_hcd_handle_np_tx_fifo_empty_intr
-+ (dwc_otg_hcd);
-+ }
-+ if (gintsts.b.i2cintr) {
-+ /** @todo Implement i2cintr handler. */
-+ }
-+ if (gintsts.b.portintr) {
-+
-+ gintmsk_data_t gintmsk = { .b.portintr = 1};
-+ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+ }
-+ if (gintsts.b.hcintr) {
-+ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
-+ }
-+ if (gintsts.b.ptxfempty) {
-+ retval |=
-+ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
-+ (dwc_otg_hcd);
-+ }
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ {
-+ DWC_DEBUGPL(DBG_HCDI,
-+ "DWC OTG HCD Finished Servicing Interrupts\n");
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
-+ DWC_READ_REG32(&global_regs->gintsts));
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+ }
-+#endif
-+
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ DWC_DEBUGPL(DBG_HCDI, "\n");
-+#endif
-+
-+ }
-+
-+exit_handler_routine:
-+ if (fiq_enable) {
-+ gintmsk_data_t gintmsk_new;
-+ haintmsk_data_t haintmsk_new;
-+ local_fiq_disable();
-+ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
-+ if(fiq_fsm_enable)
-+ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
-+ else
-+ haintmsk_new.d32 = 0x0000FFFF;
-+
-+ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
-+ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
-+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
-+ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
-+ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
-+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
-+ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
-+ ;
-+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
-+ dwc_otg_hcd->fiq_state->mphi_int_count = 0;
-+ }
-+ int_done++;
-+ }
-+ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
-+ /* Re-enable interrupts that the FIQ masked (first time round) */
-+ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+ local_fiq_enable();
-+
-+ if ((jiffies / HZ) > last_time) {
-+ //dwc_otg_qh_t *qh;
-+ //dwc_list_link_t *cur;
-+ /* Once a second output the fiq and irq numbers, useful for debug */
-+ last_time = jiffies / HZ;
-+ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
-+ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
-+ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
-+ //printk(KERN_WARNING "Periodic queues:\n");
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK(dwc_otg_hcd->lock);
-+ return retval;
-+}
-+
-+#ifdef DWC_TRACK_MISSED_SOFS
-+
-+#warning Compiling code to track missed SOFs
-+#define FRAME_NUM_ARRAY_SIZE 1000
-+/**
-+ * This function is for debug only.
-+ */
-+static inline void track_missed_sofs(uint16_t curr_frame_number)
-+{
-+ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
-+ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
-+ static int frame_num_idx = 0;
-+ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
-+ static int dumped_frame_num_array = 0;
-+
-+ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
-+ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
-+ curr_frame_number) {
-+ frame_num_array[frame_num_idx] = curr_frame_number;
-+ last_frame_num_array[frame_num_idx++] = last_frame_num;
-+ }
-+ } else if (!dumped_frame_num_array) {
-+ int i;
-+ DWC_PRINTF("Frame Last Frame\n");
-+ DWC_PRINTF("----- ----------\n");
-+ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
-+ DWC_PRINTF("0x%04x 0x%04x\n",
-+ frame_num_array[i], last_frame_num_array[i]);
-+ }
-+ dumped_frame_num_array = 1;
-+ }
-+ last_frame_num = curr_frame_number;
-+}
-+#endif
-+
-+/**
-+ * Handles the start-of-frame interrupt in host mode. Non-periodic
-+ * transactions may be queued to the DWC_otg controller for the current
-+ * (micro)frame. Periodic transactions may be queued to the controller for the
-+ * next (micro)frame.
-+ */
-+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
-+{
-+ hfnum_data_t hfnum;
-+ gintsts_data_t gintsts = { .d32 = 0 };
-+ dwc_list_link_t *qh_entry;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_transaction_type_e tr_type;
-+ int did_something = 0;
-+ int32_t next_sched_frame = -1;
-+
-+ hfnum.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+
-+#ifdef DEBUG_SOF
-+ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
-+#endif
-+ hcd->frame_number = hfnum.b.frnum;
-+
-+#ifdef DEBUG
-+ hcd->frrem_accum += hfnum.b.frrem;
-+ hcd->frrem_samples++;
-+#endif
-+
-+#ifdef DWC_TRACK_MISSED_SOFS
-+ track_missed_sofs(hcd->frame_number);
-+#endif
-+ /* Determine whether any periodic QHs should be executed. */
-+ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
-+ while (qh_entry != &hcd->periodic_sched_inactive) {
-+ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
-+ qh_entry = qh_entry->next;
-+ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
-+
-+ /*
-+ * Move QH to the ready list to be executed next
-+ * (micro)frame.
-+ */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
-+ &qh->qh_list_entry);
-+
-+ did_something = 1;
-+ }
-+ else
-+ {
-+ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
-+ {
-+ next_sched_frame = qh->sched_frame;
-+ }
-+ }
-+ }
-+ if (fiq_enable)
-+ hcd->fiq_state->next_sched_frame = next_sched_frame;
-+
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ did_something = 1;
-+ }
-+
-+ /* Clear interrupt - but do not trample on the FIQ sof */
-+ if (!fiq_fsm_enable) {
-+ gintsts.b.sofintr = 1;
-+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
-+ }
-+ return 1;
-+}
-+
-+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
-+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
-+ * memory if the DWC_otg controller is operating in Slave mode. */
-+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ host_grxsts_data_t grxsts;
-+ dwc_hc_t *hc = NULL;
-+
-+ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
-+
-+ grxsts.d32 =
-+ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
-+
-+ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
-+ if (!hc) {
-+ DWC_ERROR("Unable to get corresponding channel\n");
-+ return 0;
-+ }
-+
-+ /* Packet Status */
-+ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
-+ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
-+ hc->data_pid_start);
-+ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
-+
-+ switch (grxsts.b.pktsts) {
-+ case DWC_GRXSTS_PKTSTS_IN:
-+ /* Read the data into the host buffer. */
-+ if (grxsts.b.bcnt > 0) {
-+ dwc_otg_read_packet(dwc_otg_hcd->core_if,
-+ hc->xfer_buff, grxsts.b.bcnt);
-+
-+ /* Update the HC fields for the next packet received. */
-+ hc->xfer_count += grxsts.b.bcnt;
-+ hc->xfer_buff += grxsts.b.bcnt;
-+ }
-+
-+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
-+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
-+ case DWC_GRXSTS_PKTSTS_CH_HALTED:
-+ /* Handled in interrupt, just ignore data */
-+ break;
-+ default:
-+ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
-+ grxsts.b.pktsts);
-+ break;
-+ }
-+
-+ return 1;
-+}
-+
-+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
-+ * data packets may be written to the FIFO for OUT transfers. More requests
-+ * may be written to the non-periodic request queue for IN transfers. This
-+ * interrupt is enabled only in Slave mode. */
-+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
-+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
-+ DWC_OTG_TRANSACTION_NON_PERIODIC);
-+ return 1;
-+}
-+
-+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
-+ * packets may be written to the FIFO for OUT transfers. More requests may be
-+ * written to the periodic request queue for IN transfers. This interrupt is
-+ * enabled only in Slave mode. */
-+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
-+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
-+ DWC_OTG_TRANSACTION_PERIODIC);
-+ return 1;
-+}
-+
-+/** There are multiple conditions that can cause a port interrupt. This function
-+ * determines which interrupt conditions have occurred and handles them
-+ * appropriately. */
-+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int retval = 0;
-+ hprt0_data_t hprt0;
-+ hprt0_data_t hprt0_modify;
-+
-+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+
-+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
-+ * GINTSTS */
-+
-+ hprt0_modify.b.prtena = 0;
-+ hprt0_modify.b.prtconndet = 0;
-+ hprt0_modify.b.prtenchng = 0;
-+ hprt0_modify.b.prtovrcurrchng = 0;
-+
-+ /* Port Connect Detected
-+ * Set flag and clear if detected */
-+ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
-+ // Dont modify port status if we are in hibernation state
-+ hprt0_modify.b.prtconndet = 1;
-+ hprt0_modify.b.prtenchng = 1;
-+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
-+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+ return retval;
-+ }
-+
-+ if (hprt0.b.prtconndet) {
-+ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
-+ if (dwc_otg_hcd->core_if->adp_enable &&
-+ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
-+ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
-+ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
-+ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
-+ /* TODO - check if this is required, as
-+ * host initialization was already performed
-+ * after initial ADP probing
-+ */
-+ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
-+ dwc_otg_core_init(dwc_otg_hcd->core_if);
-+ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
-+ cil_hcd_start(dwc_otg_hcd->core_if);*/
-+ } else {
-+
-+ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
-+ "Port Connect Detected--\n", hprt0.d32);
-+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
-+ dwc_otg_hcd->flags.b.port_connect_status = 1;
-+ hprt0_modify.b.prtconndet = 1;
-+
-+ /* B-Device has connected, Delete the connection timer. */
-+ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
-+ }
-+ /* The Hub driver asserts a reset when it sees port connect
-+ * status change flag */
-+ retval |= 1;
-+ }
-+
-+ /* Port Enable Changed
-+ * Clear if detected - Set internal flag if disabled */
-+ if (hprt0.b.prtenchng) {
-+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
-+ "Port Enable Changed--\n", hprt0.d32);
-+ hprt0_modify.b.prtenchng = 1;
-+ if (hprt0.b.prtena == 1) {
-+ hfir_data_t hfir;
-+ int do_reset = 0;
-+ dwc_otg_core_params_t *params =
-+ dwc_otg_hcd->core_if->core_params;
-+ dwc_otg_core_global_regs_t *global_regs =
-+ dwc_otg_hcd->core_if->core_global_regs;
-+ dwc_otg_host_if_t *host_if =
-+ dwc_otg_hcd->core_if->host_if;
-+
-+ /* Every time when port enables calculate
-+ * HFIR.FrInterval
-+ */
-+ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
-+ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
-+
-+ /* Check if we need to adjust the PHY clock speed for
-+ * low power and adjust it */
-+ if (params->host_support_fs_ls_low_power) {
-+ gusbcfg_data_t usbcfg;
-+
-+ usbcfg.d32 =
-+ DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
-+ || hprt0.b.prtspd ==
-+ DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+ /*
-+ * Low power
-+ */
-+ hcfg_data_t hcfg;
-+ if (usbcfg.b.phylpwrclksel == 0) {
-+ /* Set PHY low power clock select for FS/LS devices */
-+ usbcfg.b.phylpwrclksel = 1;
-+ DWC_WRITE_REG32
-+ (&global_regs->gusbcfg,
-+ usbcfg.d32);
-+ do_reset = 1;
-+ }
-+
-+ hcfg.d32 =
-+ DWC_READ_REG32
-+ (&host_if->host_global_regs->hcfg);
-+
-+ if (hprt0.b.prtspd ==
-+ DWC_HPRT0_PRTSPD_LOW_SPEED
-+ && params->host_ls_low_power_phy_clk
-+ ==
-+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
-+ {
-+ /* 6 MHZ */
-+ DWC_DEBUGPL(DBG_CIL,
-+ "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
-+ if (hcfg.b.fslspclksel !=
-+ DWC_HCFG_6_MHZ) {
-+ hcfg.b.fslspclksel =
-+ DWC_HCFG_6_MHZ;
-+ DWC_WRITE_REG32
-+ (&host_if->host_global_regs->hcfg,
-+ hcfg.d32);
-+ do_reset = 1;
-+ }
-+ } else {
-+ /* 48 MHZ */
-+ DWC_DEBUGPL(DBG_CIL,
-+ "FS_PHY programming HCFG to 48 MHz ()\n");
-+ if (hcfg.b.fslspclksel !=
-+ DWC_HCFG_48_MHZ) {
-+ hcfg.b.fslspclksel =
-+ DWC_HCFG_48_MHZ;
-+ DWC_WRITE_REG32
-+ (&host_if->host_global_regs->hcfg,
-+ hcfg.d32);
-+ do_reset = 1;
-+ }
-+ }
-+ } else {
-+ /*
-+ * Not low power
-+ */
-+ if (usbcfg.b.phylpwrclksel == 1) {
-+ usbcfg.b.phylpwrclksel = 0;
-+ DWC_WRITE_REG32
-+ (&global_regs->gusbcfg,
-+ usbcfg.d32);
-+ do_reset = 1;
-+ }
-+ }
-+
-+ if (do_reset) {
-+ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
-+ }
-+ }
-+
-+ if (!do_reset) {
-+ /* Port has been enabled set the reset change flag */
-+ dwc_otg_hcd->flags.b.port_reset_change = 1;
-+ }
-+ } else {
-+ dwc_otg_hcd->flags.b.port_enable_change = 1;
-+ }
-+ retval |= 1;
-+ }
-+
-+ /** Overcurrent Change Interrupt */
-+ if (hprt0.b.prtovrcurrchng) {
-+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
-+ "Port Overcurrent Changed--\n", hprt0.d32);
-+ dwc_otg_hcd->flags.b.port_over_current_change = 1;
-+ hprt0_modify.b.prtovrcurrchng = 1;
-+ retval |= 1;
-+ }
-+
-+ /* Clear Port Interrupts */
-+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
-+
-+ return retval;
-+}
-+
-+/** This interrupt indicates that one or more host channels has a pending
-+ * interrupt. There are multiple conditions that can cause each host channel
-+ * interrupt. This function determines which conditions have occurred for each
-+ * host channel interrupt and handles them appropriately. */
-+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int i;
-+ int retval = 0;
-+ haint_data_t haint = { .d32 = 0 } ;
-+
-+ /* Clear appropriate bits in HCINTn to clear the interrupt bit in
-+ * GINTSTS */
-+
-+ if (!fiq_fsm_enable)
-+ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
-+
-+ // Overwrite with saved interrupts from fiq handler
-+ if(fiq_fsm_enable)
-+ {
-+ /* check the mask? */
-+ local_fiq_disable();
-+ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
-+ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
-+ local_fiq_enable();
-+ }
-+
-+ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
-+ if (haint.b2.chint & (1 << i)) {
-+ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
-+ }
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * Gets the actual length of a transfer after the transfer halts. _halt_status
-+ * holds the reason for the halt.
-+ *
-+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
-+ * *short_read is set to 1 upon return if less than the requested
-+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
-+ * return. short_read may also be NULL on entry, in which case it remains
-+ * unchanged.
-+ */
-+static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status,
-+ int *short_read)
-+{
-+ hctsiz_data_t hctsiz;
-+ uint32_t length;
-+
-+ if (short_read != NULL) {
-+ *short_read = 0;
-+ }
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+
-+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+ if (hc->ep_is_in) {
-+ length = hc->xfer_len - hctsiz.b.xfersize;
-+ if (short_read != NULL) {
-+ *short_read = (hctsiz.b.xfersize != 0);
-+ }
-+ } else if (hc->qh->do_split) {
-+ //length = split_out_xfersize[hc->hc_num];
-+ length = qtd->ssplit_out_xfer_count;
-+ } else {
-+ length = hc->xfer_len;
-+ }
-+ } else {
-+ /*
-+ * Must use the hctsiz.pktcnt field to determine how much data
-+ * has been transferred. This field reflects the number of
-+ * packets that have been transferred via the USB. This is
-+ * always an integral number of packets if the transfer was
-+ * halted before its normal completion. (Can't use the
-+ * hctsiz.xfersize field because that reflects the number of
-+ * bytes transferred via the AHB, not the USB).
-+ */
-+ length =
-+ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
-+ }
-+
-+ return length;
-+}
-+
-+/**
-+ * Updates the state of the URB after a Transfer Complete interrupt on the
-+ * host channel. Updates the actual_length field of the URB based on the
-+ * number of bytes transferred via the host channel. Sets the URB status
-+ * if the data transfer is finished.
-+ *
-+ * @return 1 if the data transfer specified by the URB is completely finished,
-+ * 0 otherwise.
-+ */
-+static int update_urb_state_xfer_comp(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_hcd_urb_t * urb,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ int xfer_done = 0;
-+ int short_read = 0;
-+
-+ int xfer_length;
-+
-+ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_COMPLETE,
-+ &short_read);
-+
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && xfer_length && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
-+ xfer_length);
-+ }
-+
-+ urb->actual_length += xfer_length;
-+
-+ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
-+ (urb->flags & URB_SEND_ZERO_PACKET)
-+ && (urb->actual_length == urb->length)
-+ && !(urb->length % hc->max_packet)) {
-+ xfer_done = 0;
-+ } else if (short_read || urb->actual_length >= urb->length) {
-+ xfer_done = 1;
-+ urb->status = 0;
-+ }
-+
-+#ifdef DEBUG
-+ {
-+ hctsiz_data_t hctsiz;
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
-+ __func__, (hc->ep_is_in ? "IN" : "OUT"),
-+ hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
-+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
-+ hctsiz.b.xfersize);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
-+ urb->length);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
-+ urb->actual_length);
-+ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
-+ short_read, xfer_done);
-+ }
-+#endif
-+
-+ return xfer_done;
-+}
-+
-+/*
-+ * Save the starting data toggle for the next transfer. The data toggle is
-+ * saved in the QH for non-control transfers and it's saved in the QTD for
-+ * control transfers.
-+ */
-+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
-+{
-+ hctsiz_data_t hctsiz;
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
-+ dwc_otg_qh_t *qh = hc->qh;
-+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ } else {
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA1;
-+ }
-+ } else {
-+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+ qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ } else {
-+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
-+ }
-+ }
-+}
-+
-+/**
-+ * Updates the state of an Isochronous URB when the transfer is stopped for
-+ * any reason. The fields of the current entry in the frame descriptor array
-+ * are set based on the transfer state and the input _halt_status. Completes
-+ * the Isochronous URB if all the URB frames have been completed.
-+ *
-+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
-+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
-+ */
-+static dwc_otg_halt_status_e
-+update_isoc_urb_state(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
-+{
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ dwc_otg_halt_status_e ret_val = halt_status;
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+ frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
-+ switch (halt_status) {
-+ case DWC_OTG_HC_XFER_COMPLETE:
-+ frame_desc->status = 0;
-+ frame_desc->actual_length =
-+ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
-+
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
-+ hc->qh->dw_align_buf, frame_desc->actual_length);
-+ }
-+
-+ break;
-+ case DWC_OTG_HC_XFER_FRAME_OVERRUN:
-+ urb->error_count++;
-+ if (hc->ep_is_in) {
-+ frame_desc->status = -DWC_E_NO_STREAM_RES;
-+ } else {
-+ frame_desc->status = -DWC_E_COMMUNICATION;
-+ }
-+ frame_desc->actual_length = 0;
-+ break;
-+ case DWC_OTG_HC_XFER_BABBLE_ERR:
-+ urb->error_count++;
-+ frame_desc->status = -DWC_E_OVERFLOW;
-+ /* Don't need to update actual_length in this case. */
-+ break;
-+ case DWC_OTG_HC_XFER_XACT_ERR:
-+ urb->error_count++;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ frame_desc->actual_length =
-+ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
-+
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
-+ hc->qh->dw_align_buf, frame_desc->actual_length);
-+ }
-+ /* Skip whole frame */
-+ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
-+ hc->ep_is_in && hcd->core_if->dma_enable) {
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ }
-+
-+ break;
-+ default:
-+ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
-+ break;
-+ }
-+ if (++qtd->isoc_frame_index == urb->packet_count) {
-+ /*
-+ * urb->status is not used for isoc transfers.
-+ * The individual frame_desc statuses are used instead.
-+ */
-+ hcd->fops->complete(hcd, urb->priv, urb, 0);
-+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ } else {
-+ ret_val = DWC_OTG_HC_XFER_COMPLETE;
-+ }
-+ return ret_val;
-+}
-+
-+/**
-+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
-+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
-+ * still linked to the QH, the QH is added to the end of the inactive
-+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
-+ * schedule if no more QTDs are linked to the QH.
-+ */
-+static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
-+{
-+ int continue_split = 0;
-+ dwc_otg_qtd_t *qtd;
-+
-+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
-+
-+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+ if (qtd->complete_split) {
-+ continue_split = 1;
-+ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
-+ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
-+ continue_split = 1;
-+ }
-+
-+ if (free_qtd) {
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+ continue_split = 0;
-+ }
-+
-+ qh->channel = NULL;
-+ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
-+}
-+
-+/**
-+ * Releases a host channel for use by other transfers. Attempts to select and
-+ * queue more transactions since at least one host channel is available.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param hc The host channel to release.
-+ * @param qtd The QTD associated with the host channel. This QTD may be freed
-+ * if the transfer is complete or an error has occurred.
-+ * @param halt_status Reason the channel is being released. This status
-+ * determines the actions taken by this function.
-+ */
-+static void release_channel(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ dwc_otg_transaction_type_e tr_type;
-+ int free_qtd;
-+ dwc_irqflags_t flags;
-+ dwc_spinlock_t *channel_lock = hcd->channel_lock;
-+
-+ int hog_port = 0;
-+
-+ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
-+ __func__, hc->hc_num, halt_status, hc->xfer_len);
-+
-+ if(fiq_fsm_enable && hc->do_split) {
-+ if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
-+ if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
-+ hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
-+ hog_port = 0;
-+ }
-+ }
-+ }
-+
-+ switch (halt_status) {
-+ case DWC_OTG_HC_XFER_URB_COMPLETE:
-+ free_qtd = 1;
-+ break;
-+ case DWC_OTG_HC_XFER_AHB_ERR:
-+ case DWC_OTG_HC_XFER_STALL:
-+ case DWC_OTG_HC_XFER_BABBLE_ERR:
-+ free_qtd = 1;
-+ break;
-+ case DWC_OTG_HC_XFER_XACT_ERR:
-+ if (qtd->error_count >= 3) {
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Complete URB with transaction error\n");
-+ free_qtd = 1;
-+ qtd->urb->status = -DWC_E_PROTOCOL;
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_PROTOCOL);
-+ } else {
-+ free_qtd = 0;
-+ }
-+ break;
-+ case DWC_OTG_HC_XFER_URB_DEQUEUE:
-+ /*
-+ * The QTD has already been removed and the QH has been
-+ * deactivated. Don't want to do anything except release the
-+ * host channel and try to queue more transfers.
-+ */
-+ goto cleanup;
-+ case DWC_OTG_HC_XFER_NO_HALT_STATUS:
-+ free_qtd = 0;
-+ break;
-+ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Complete URB with I/O error\n");
-+ free_qtd = 1;
-+ qtd->urb->status = -DWC_E_IO;
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_IO);
-+ break;
-+ default:
-+ free_qtd = 0;
-+ break;
-+ }
-+
-+ deactivate_qh(hcd, hc->qh, free_qtd);
-+
-+cleanup:
-+ /*
-+ * Release the host channel for use by other transfers. The cleanup
-+ * function clears the channel interrupt enables and conditions, so
-+ * there's no need to clear the Channel Halted interrupt separately.
-+ */
-+ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
-+ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
-+ dwc_otg_hc_cleanup(hcd->core_if, hc);
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+ if (!microframe_schedule) {
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ hcd->non_periodic_channels--;
-+ break;
-+
-+ default:
-+ /*
-+ * Don't release reservations for periodic channels here.
-+ * That's done when a periodic transfer is descheduled (i.e.
-+ * when the QH is removed from the periodic schedule).
-+ */
-+ break;
-+ }
-+ } else {
-+
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ hcd->available_host_channels++;
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ }
-+
-+ /* Try to queue more transfers now that there's a free channel. */
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ }
-+}
-+
-+/**
-+ * Halts a host channel. If the channel cannot be halted immediately because
-+ * the request queue is full, this function ensures that the FIFO empty
-+ * interrupt for the appropriate queue is enabled so that the halt request can
-+ * be queued when there is space in the request queue.
-+ *
-+ * This function may also be called in DMA mode. In that case, the channel is
-+ * simply released since the core always halts the channel automatically in
-+ * DMA mode.
-+ */
-+static void halt_channel(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
-+{
-+ if (hcd->core_if->dma_enable) {
-+ release_channel(hcd, hc, qtd, halt_status);
-+ return;
-+ }
-+
-+ /* Slave mode processing... */
-+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
-+
-+ if (hc->halt_on_queue) {
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ dwc_otg_core_global_regs_t *global_regs;
-+ global_regs = hcd->core_if->core_global_regs;
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+ /*
-+ * Make sure the Non-periodic Tx FIFO empty interrupt
-+ * is enabled so that the non-periodic schedule will
-+ * be processed.
-+ */
-+ gintmsk.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+ } else {
-+ /*
-+ * Move the QH from the periodic queued schedule to
-+ * the periodic assigned schedule. This allows the
-+ * halt to be queued when the periodic schedule is
-+ * processed.
-+ */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+ &hc->qh->qh_list_entry);
-+
-+ /*
-+ * Make sure the Periodic Tx FIFO Empty interrupt is
-+ * enabled so that the periodic schedule will be
-+ * processed.
-+ */
-+ gintmsk.b.ptxfempty = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+ }
-+ }
-+}
-+
-+/**
-+ * Performs common cleanup for non-periodic transfers after a Transfer
-+ * Complete interrupt. This function should be called after any endpoint type
-+ * specific handling is finished to release the host channel.
-+ */
-+static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ hcint_data_t hcint;
-+
-+ qtd->error_count = 0;
-+
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ if (hcint.b.nyet) {
-+ /*
-+ * Got a NYET on the last transaction of the transfer. This
-+ * means that the endpoint should be in the PING state at the
-+ * beginning of the next transfer.
-+ */
-+ hc->qh->ping_state = 1;
-+ clear_hc_int(hc_regs, nyet);
-+ }
-+
-+ /*
-+ * Always halt and release the host channel to make it available for
-+ * more transfers. There may still be more phases for a control
-+ * transfer or more data packets for a bulk transfer at this point,
-+ * but the host channel is still halted. A channel will be reassigned
-+ * to the transfer when the non-periodic schedule is processed after
-+ * the channel is released. This allows transactions to be queued
-+ * properly via dwc_otg_hcd_queue_transactions, which also enables the
-+ * Tx FIFO Empty interrupt if necessary.
-+ */
-+ if (hc->ep_is_in) {
-+ /*
-+ * IN transfers in Slave mode require an explicit disable to
-+ * halt the channel. (In DMA mode, this call simply releases
-+ * the channel.)
-+ */
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ } else {
-+ /*
-+ * The channel is automatically disabled by the core for OUT
-+ * transfers in Slave mode.
-+ */
-+ release_channel(hcd, hc, qtd, halt_status);
-+ }
-+}
-+
-+/**
-+ * Performs common cleanup for periodic transfers after a Transfer Complete
-+ * interrupt. This function should be called after any endpoint type specific
-+ * handling is finished to release the host channel.
-+ */
-+static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ hctsiz_data_t hctsiz;
-+ qtd->error_count = 0;
-+
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
-+ /* Core halts channel in these cases. */
-+ release_channel(hcd, hc, qtd, halt_status);
-+ } else {
-+ /* Flush any outstanding requests from the Tx queue. */
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+}
-+
-+static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ uint32_t len;
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+
-+ len = get_actual_xfer_length(hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_COMPLETE, NULL);
-+
-+ if (!len) {
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ return 0;
-+ }
-+ frame_desc->actual_length += len;
-+
-+ if (hc->align_buff && len)
-+ dwc_memcpy(qtd->urb->buf + frame_desc->offset +
-+ qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
-+ qtd->isoc_split_offset += len;
-+
-+ if (frame_desc->length == frame_desc->actual_length) {
-+ frame_desc->status = 0;
-+ qtd->isoc_frame_index++;
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ }
-+
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+
-+ return 1; /* Indicates that channel released */
-+}
-+
-+/**
-+ * Handles a host channel Transfer Complete interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ int urb_xfer_done;
-+ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Transfer Complete--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+ if (pipe_type == UE_ISOCHRONOUS) {
-+ /* Do not disable the interrupt, just clear it */
-+ clear_hc_int(hc_regs, xfercomp);
-+ return 1;
-+ }
-+ goto handle_xfercomp_done;
-+ }
-+
-+ /*
-+ * Handle xfer complete on CSPLIT.
-+ */
-+
-+ if (hc->qh->do_split) {
-+ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
-+ && hcd->core_if->dma_enable) {
-+ if (qtd->complete_split
-+ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
-+ qtd))
-+ goto handle_xfercomp_done;
-+ } else {
-+ qtd->complete_split = 0;
-+ }
-+ }
-+
-+ /* Update the QTD and URB states. */
-+ switch (pipe_type) {
-+ case UE_CONTROL:
-+ switch (qtd->control_phase) {
-+ case DWC_OTG_CONTROL_SETUP:
-+ if (urb->length > 0) {
-+ qtd->control_phase = DWC_OTG_CONTROL_DATA;
-+ } else {
-+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+ }
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Control setup transaction done\n");
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ break;
-+ case DWC_OTG_CONTROL_DATA:{
-+ urb_xfer_done =
-+ update_urb_state_xfer_comp(hc, hc_regs, urb,
-+ qtd);
-+ if (urb_xfer_done) {
-+ qtd->control_phase =
-+ DWC_OTG_CONTROL_STATUS;
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Control data transfer done\n");
-+ } else {
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ }
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ break;
-+ }
-+ case DWC_OTG_CONTROL_STATUS:
-+ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
-+ if (urb->status == -DWC_E_IN_PROGRESS) {
-+ urb->status = 0;
-+ }
-+ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ break;
-+ }
-+
-+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ case UE_BULK:
-+ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
-+ urb_xfer_done =
-+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
-+ if (urb_xfer_done) {
-+ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ } else {
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ }
-+
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ case UE_INTERRUPT:
-+ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
-+ urb_xfer_done =
-+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
-+
-+ /*
-+ * Interrupt URB is done on the first transfer complete
-+ * interrupt.
-+ */
-+ if (urb_xfer_done) {
-+ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ } else {
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ }
-+
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
-+ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
-+ halt_status =
-+ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ }
-+
-+handle_xfercomp_done:
-+ disable_hc_int(hc_regs, xfercompl);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel STALL interrupt. This handler may be called in
-+ * either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+
-+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
-+ "STALL Received--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
-+ goto handle_stall_done;
-+ }
-+
-+ if (pipe_type == UE_CONTROL) {
-+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
-+ }
-+
-+ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
-+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
-+ /*
-+ * USB protocol requires resetting the data toggle for bulk
-+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
-+ * setup command is issued to the endpoint. Anticipate the
-+ * CLEAR_FEATURE command since a STALL has occurred and reset
-+ * the data toggle now.
-+ */
-+ hc->qh->data_toggle = 0;
-+ }
-+
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
-+
-+handle_stall_done:
-+ disable_hc_int(hc_regs, stall);
-+
-+ return 1;
-+}
-+
-+/*
-+ * Updates the state of the URB when a transfer has been stopped due to an
-+ * abnormal condition before the transfer completes. Modifies the
-+ * actual_length field of the URB to reflect the number of bytes that have
-+ * actually been transferred via the host channel.
-+ */
-+static void update_urb_state_xfer_intr(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_hcd_urb_t * urb,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
-+ halt_status, NULL);
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
-+ bytes_transferred);
-+ }
-+
-+ urb->actual_length += bytes_transferred;
-+
-+#ifdef DEBUG
-+ {
-+ hctsiz_data_t hctsiz;
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
-+ __func__, (hc->ep_is_in ? "IN" : "OUT"),
-+ hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
-+ hc->start_pkt_count);
-+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
-+ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
-+ bytes_transferred);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
-+ urb->actual_length);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
-+ urb->length);
-+ }
-+#endif
-+}
-+
-+/**
-+ * Handles a host channel NAK interrupt. This handler may be called in either
-+ * DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "NAK Received--\n", hc->hc_num);
-+
-+ /*
-+ * When we get bulk NAKs then remember this so we holdoff on this qh until
-+ * the beginning of the next frame
-+ */
-+ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_BULK:
-+ case UE_CONTROL:
-+ if (nak_holdoff && qtd->qh->do_split)
-+ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
-+ }
-+
-+ /*
-+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
-+ * interrupt. Re-start the SSPLIT transfer.
-+ */
-+ if (hc->do_split) {
-+ if (hc->complete_split) {
-+ qtd->error_count = 0;
-+ }
-+ qtd->complete_split = 0;
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+ goto handle_nak_done;
-+ }
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ if (hcd->core_if->dma_enable && hc->ep_is_in) {
-+ /*
-+ * NAK interrupts are enabled on bulk/control IN
-+ * transfers in DMA mode for the sole purpose of
-+ * resetting the error count after a transaction error
-+ * occurs. The core will continue transferring data.
-+ * Disable other interrupts unmasked for the same
-+ * reason.
-+ */
-+ disable_hc_int(hc_regs, datatglerr);
-+ disable_hc_int(hc_regs, ack);
-+ qtd->error_count = 0;
-+ goto handle_nak_done;
-+ }
-+
-+ /*
-+ * NAK interrupts normally occur during OUT transfers in DMA
-+ * or Slave mode. For IN transfers, more requests will be
-+ * queued as request queue space is available.
-+ */
-+ qtd->error_count = 0;
-+
-+ if (!hc->qh->ping_state) {
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd,
-+ DWC_OTG_HC_XFER_NAK);
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
-+ hc->qh->ping_state = 1;
-+ }
-+
-+ /*
-+ * Halt the channel so the transfer can be re-started from
-+ * the appropriate point or the PING protocol will
-+ * start/continue.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+ break;
-+ case UE_INTERRUPT:
-+ qtd->error_count = 0;
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ /* Should never get called for isochronous transfers. */
-+ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
-+ break;
-+ }
-+
-+handle_nak_done:
-+ disable_hc_int(hc_regs, nak);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel ACK interrupt. This interrupt is enabled when
-+ * performing the PING protocol in Slave mode, when errors occur during
-+ * either Slave mode or DMA mode, and during Start Split transactions.
-+ */
-+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "ACK Received--\n", hc->hc_num);
-+
-+ if (hc->do_split) {
-+ /*
-+ * Handle ACK on SSPLIT.
-+ * ACK should not occur in CSPLIT.
-+ */
-+ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
-+ qtd->ssplit_out_xfer_count = hc->xfer_len;
-+ }
-+ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
-+ /* Don't need complete for isochronous out transfers. */
-+ qtd->complete_split = 1;
-+ }
-+
-+ /* ISOC OUT */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
-+ switch (hc->xact_pos) {
-+ case DWC_HCSPLIT_XACTPOS_ALL:
-+ break;
-+ case DWC_HCSPLIT_XACTPOS_END:
-+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+ qtd->isoc_split_offset = 0;
-+ break;
-+ case DWC_HCSPLIT_XACTPOS_BEGIN:
-+ case DWC_HCSPLIT_XACTPOS_MID:
-+ /*
-+ * For BEGIN or MID, calculate the length for
-+ * the next microframe to determine the correct
-+ * SSPLIT token, either MID or END.
-+ */
-+ {
-+ struct dwc_otg_hcd_iso_packet_desc
-+ *frame_desc;
-+
-+ frame_desc =
-+ &qtd->urb->
-+ iso_descs[qtd->isoc_frame_index];
-+ qtd->isoc_split_offset += 188;
-+
-+ if ((frame_desc->length -
-+ qtd->isoc_split_offset) <= 188) {
-+ qtd->isoc_split_pos =
-+ DWC_HCSPLIT_XACTPOS_END;
-+ } else {
-+ qtd->isoc_split_pos =
-+ DWC_HCSPLIT_XACTPOS_MID;
-+ }
-+
-+ }
-+ break;
-+ }
-+ } else {
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
-+ }
-+ } else {
-+ /*
-+ * An unmasked ACK on a non-split DMA transaction is
-+ * for the sole purpose of resetting error counts. Disable other
-+ * interrupts unmasked for the same reason.
-+ */
-+ if(hcd->core_if->dma_enable) {
-+ disable_hc_int(hc_regs, datatglerr);
-+ disable_hc_int(hc_regs, nak);
-+ }
-+ qtd->error_count = 0;
-+
-+ if (hc->qh->ping_state) {
-+ hc->qh->ping_state = 0;
-+ /*
-+ * Halt the channel so the transfer can be re-started
-+ * from the appropriate point. This only happens in
-+ * Slave mode. In DMA mode, the ping_state is cleared
-+ * when the transfer is started because the core
-+ * automatically executes the PING, then the transfer.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
-+ }
-+ }
-+
-+ /*
-+ * If the ACK occurred when _not_ in the PING state, let the channel
-+ * continue transferring data after clearing the error count.
-+ */
-+
-+ disable_hc_int(hc_regs, ack);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel NYET interrupt. This interrupt should only occur on
-+ * Bulk and Control OUT endpoints and for complete split transactions. If a
-+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
-+ * handled in the xfercomp interrupt handler, not here. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "NYET Received--\n", hc->hc_num);
-+
-+ /*
-+ * NYET on CSPLIT
-+ * re-do the CSPLIT immediately on non-periodic
-+ */
-+ if (hc->do_split && hc->complete_split) {
-+ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ && hcd->core_if->dma_enable) {
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ }
-+ else
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ goto handle_nyet_done;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ int frnum = dwc_otg_hcd_get_frame_number(hcd);
-+
-+ // With the FIQ running we only ever see the failed NYET
-+ if (dwc_full_frame_num(frnum) !=
-+ dwc_full_frame_num(hc->qh->sched_frame) ||
-+ fiq_fsm_enable) {
-+ /*
-+ * No longer in the same full speed frame.
-+ * Treat this as a transaction error.
-+ */
-+#if 0
-+ /** @todo Fix system performance so this can
-+ * be treated as an error. Right now complete
-+ * splits cannot be scheduled precisely enough
-+ * due to other system activity, so this error
-+ * occurs regularly in Slave mode.
-+ */
-+ qtd->error_count++;
-+#endif
-+ qtd->complete_split = 0;
-+ halt_channel(hcd, hc, qtd,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+ /** @todo add support for isoc release */
-+ goto handle_nyet_done;
-+ }
-+ }
-+
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
-+ goto handle_nyet_done;
-+ }
-+
-+ hc->qh->ping_state = 1;
-+ qtd->error_count = 0;
-+
-+ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
-+ DWC_OTG_HC_XFER_NYET);
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+
-+ /*
-+ * Halt the channel and re-start the transfer so the PING
-+ * protocol will start.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
-+
-+handle_nyet_done:
-+ disable_hc_int(hc_regs, nyet);
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel babble interrupt. This handler may be called in
-+ * either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Babble Error--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ DWC_OTG_HC_XFER_BABBLE_ERR);
-+ goto handle_babble_done;
-+ }
-+
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_OVERFLOW);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
-+ } else {
-+ dwc_otg_halt_status_e halt_status;
-+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_BABBLE_ERR);
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+
-+handle_babble_done:
-+ disable_hc_int(hc_regs, bblerr);
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel AHB error interrupt. This handler is only called in
-+ * DMA mode.
-+ */
-+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+ hctsiz_data_t hctsiz;
-+ uint32_t hcdma;
-+ char *pipetype, *speed;
-+
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "AHB Error--\n", hc->hc_num);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ hcdma = DWC_READ_REG32(&hc_regs->hcdma);
-+
-+ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
-+ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
-+ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
-+ DWC_ERROR(" Device address: %d\n",
-+ dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
-+ DWC_ERROR(" Endpoint: %d, %s\n",
-+ dwc_otg_hcd_get_ep_num(&urb->pipe_info),
-+ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
-+ case UE_CONTROL:
-+ pipetype = "CONTROL";
-+ break;
-+ case UE_BULK:
-+ pipetype = "BULK";
-+ break;
-+ case UE_INTERRUPT:
-+ pipetype = "INTERRUPT";
-+ break;
-+ case UE_ISOCHRONOUS:
-+ pipetype = "ISOCHRONOUS";
-+ break;
-+ default:
-+ pipetype = "UNKNOWN";
-+ break;
-+ }
-+
-+ DWC_ERROR(" Endpoint type: %s\n", pipetype);
-+
-+ switch (hc->speed) {
-+ case DWC_OTG_EP_SPEED_HIGH:
-+ speed = "HIGH";
-+ break;
-+ case DWC_OTG_EP_SPEED_FULL:
-+ speed = "FULL";
-+ break;
-+ case DWC_OTG_EP_SPEED_LOW:
-+ speed = "LOW";
-+ break;
-+ default:
-+ speed = "UNKNOWN";
-+ break;
-+ };
-+
-+ DWC_ERROR(" Speed: %s\n", speed);
-+
-+ DWC_ERROR(" Max packet size: %d\n",
-+ dwc_otg_hcd_get_mps(&urb->pipe_info));
-+ DWC_ERROR(" Data buffer length: %d\n", urb->length);
-+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
-+ urb->buf, (void *)urb->dma);
-+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
-+ urb->setup_packet, (void *)urb->setup_dma);
-+ DWC_ERROR(" Interval: %d\n", urb->interval);
-+
-+ /* Core haltes the channel for Descriptor DMA mode */
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ DWC_OTG_HC_XFER_AHB_ERR);
-+ goto handle_ahberr_done;
-+ }
-+
-+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
-+
-+ /*
-+ * Force a channel halt. Don't call halt_channel because that won't
-+ * write to the HCCHARn register in DMA mode to force the halt.
-+ */
-+ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
-+handle_ahberr_done:
-+ disable_hc_int(hc_regs, ahberr);
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel transaction error interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Transaction Error--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+ goto handle_xacterr_done;
-+ }
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ qtd->error_count++;
-+ if (!hc->qh->ping_state) {
-+
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ hc->qh->ping_state = 1;
-+ }
-+ }
-+
-+ /*
-+ * Halt the channel so the transfer can be re-started from
-+ * the appropriate point or the PING protocol will start.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ break;
-+ case UE_INTERRUPT:
-+ qtd->error_count++;
-+ if (hc->do_split && hc->complete_split) {
-+ qtd->complete_split = 0;
-+ }
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ {
-+ dwc_otg_halt_status_e halt_status;
-+ halt_status =
-+ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+ break;
-+ }
-+handle_xacterr_done:
-+ disable_hc_int(hc_regs, xacterr);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel frame overrun interrupt. This handler may be called
-+ * in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Frame Overrun--\n", hc->hc_num);
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ break;
-+ case UE_INTERRUPT:
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ {
-+ dwc_otg_halt_status_e halt_status;
-+ halt_status =
-+ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_FRAME_OVERRUN);
-+
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+ break;
-+ }
-+
-+ disable_hc_int(hc_regs, frmovrun);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel data toggle error interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Data Toggle Error on %s transfer--\n",
-+ hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
-+
-+ /* Data toggles on split transactions cause the hc to halt.
-+ * restart transfer */
-+ if(hc->qh->do_split)
-+ {
-+ qtd->error_count++;
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ } else if (hc->ep_is_in) {
-+ /* An unmasked data toggle error on a non-split DMA transaction is
-+ * for the sole purpose of resetting error counts. Disable other
-+ * interrupts unmasked for the same reason.
-+ */
-+ if(hcd->core_if->dma_enable) {
-+ disable_hc_int(hc_regs, ack);
-+ disable_hc_int(hc_regs, nak);
-+ }
-+ qtd->error_count = 0;
-+ }
-+
-+ disable_hc_int(hc_regs, datatglerr);
-+
-+ return 1;
-+}
-+
-+#ifdef DEBUG
-+/**
-+ * This function is for debug only. It checks that a valid halt status is set
-+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
-+ * taken and a warning is issued.
-+ * @return 1 if halt status is ok, 0 otherwise.
-+ */
-+static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ hcsplt_data_t hcsplt;
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
-+ /*
-+ * This code is here only as a check. This condition should
-+ * never happen. Ignore the halt if it does occur.
-+ */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ DWC_WARN
-+ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
-+ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
-+ "hcint 0x%08x, hcintmsk 0x%08x, "
-+ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
-+ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
-+ hcintmsk.d32, hcsplt.d32, qtd->complete_split);
-+
-+ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
-+ __func__, hc->hc_num);
-+ DWC_WARN("\n");
-+ clear_hc_int(hc_regs, chhltd);
-+ return 0;
-+ }
-+
-+ /*
-+ * This code is here only as a check. hcchar.chdis should
-+ * never be set when the halt interrupt occurs. Halt the
-+ * channel again if it does occur.
-+ */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: hcchar.chdis set unexpectedly, "
-+ "hcchar 0x%08x, trying to halt again\n",
-+ __func__, hcchar.d32);
-+ clear_hc_int(hc_regs, chhltd);
-+ hc->halt_pending = 0;
-+ halt_channel(hcd, hc, qtd, hc->halt_status);
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+#endif
-+
-+/**
-+ * Handles a host Channel Halted interrupt in DMA mode. This handler
-+ * determines the reason the channel halted and proceeds accordingly.
-+ */
-+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ int out_nak_enh = 0;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ /* For core with OUT NAK enhancement, the flow for high-
-+ * speed CONTROL/BULK OUT is handled a little differently.
-+ */
-+ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
-+ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
-+ out_nak_enh = 1;
-+ }
-+ }
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
-+ && !hcd->core_if->dma_desc_enable)) {
-+ /*
-+ * Just release the channel. A dequeue can happen on a
-+ * transfer timeout. In the case of an AHB Error, the channel
-+ * was forced to halt because there's no way to gracefully
-+ * recover.
-+ */
-+ if (hcd->core_if->dma_desc_enable)
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ hc->halt_status);
-+ else
-+ release_channel(hcd, hc, qtd, hc->halt_status);
-+ return;
-+ }
-+
-+ /* Read the HCINTn register to determine the cause for the halt. */
-+
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+
-+ if (hcint.b.xfercomp) {
-+ /** @todo This is here because of a possible hardware bug. Spec
-+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
-+ * interrupt w/ACK bit set should occur, but I only see the
-+ * XFERCOMP bit, even with it masked out. This is a workaround
-+ * for that behavior. Should fix this when hardware is fixed.
-+ */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
-+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
-+ }
-+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.stall) {
-+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
-+ if (out_nak_enh) {
-+ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
-+ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
-+ qtd->error_count = 0;
-+ } else {
-+ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
-+ }
-+ }
-+
-+ /*
-+ * Must handle xacterr before nak or ack. Could get a xacterr
-+ * at the same time as either of these on a BULK/CONTROL OUT
-+ * that started with a PING. The xacterr takes precedence.
-+ */
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
-+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.bblerr) {
-+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.frmovrun) {
-+ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.datatglerr) {
-+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (!out_nak_enh) {
-+ if (hcint.b.nyet) {
-+ /*
-+ * Must handle nyet before nak or ack. Could get a nyet at the
-+ * same time as either of those on a BULK/CONTROL OUT that
-+ * started with a PING. The nyet takes precedence.
-+ */
-+ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.nak && !hcintmsk.b.nak) {
-+ /*
-+ * If nak is not masked, it's because a non-split IN transfer
-+ * is in an error state. In that case, the nak is handled by
-+ * the nak interrupt handler, not here. Handle nak here for
-+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow
-+ * rewinding the buffer pointer.
-+ */
-+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ack && !hcintmsk.b.ack) {
-+ /*
-+ * If ack is not masked, it's because a non-split IN transfer
-+ * is in an error state. In that case, the ack is handled by
-+ * the ack interrupt handler, not here. Handle ack here for
-+ * split transfers. Start splits halt on ACK.
-+ */
-+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * A periodic transfer halted with no other channel
-+ * interrupts set. Assume it was halted by the core
-+ * because it could not be completed in its scheduled
-+ * (micro)frame.
-+ */
-+#ifdef DEBUG
-+ DWC_PRINTF
-+ ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
-+ __func__, hc->hc_num);
-+#endif
-+ halt_channel(hcd, hc, qtd,
-+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
-+ } else {
-+ DWC_ERROR
-+ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
-+ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
-+ __func__, hc->hc_num, hcint.d32,
-+ DWC_READ_REG32(&hcd->
-+ core_if->core_global_regs->
-+ gintsts));
-+ /* Failthrough: use 3-strikes rule */
-+ qtd->error_count++;
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ }
-+
-+ }
-+ } else {
-+ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
-+ hcint.d32);
-+ /* Failthrough: use 3-strikes rule */
-+ qtd->error_count++;
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ }
-+}
-+
-+/**
-+ * Handles a host channel Channel Halted interrupt.
-+ *
-+ * In slave mode, this handler is called only when the driver specifically
-+ * requests a halt. This occurs during handling other host channel interrupts
-+ * (e.g. nak, xacterr, stall, nyet, etc.).
-+ *
-+ * In DMA mode, this is the interrupt that occurs when the core has finished
-+ * processing a transfer on a channel. Other host channel interrupts (except
-+ * ahberr) are disabled in DMA mode.
-+ */
-+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Channel Halted--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_enable) {
-+ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
-+ } else {
-+#ifdef DEBUG
-+ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
-+ return 1;
-+ }
-+#endif
-+ release_channel(hcd, hc, qtd, hc->halt_status);
-+ }
-+
-+ return 1;
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
-+ * FIQ transfer completion
-+ * @hcd: Pointer to dwc_otg_hcd struct
-+ * @num: Host channel number
-+ *
-+ * 1. Un-mangle the status as recorded in each iso_frame_desc status
-+ * 2. Copy it from the dwc_otg_urb into the real URB
-+ */
-+void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
-+{
-+ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
-+ int nr_frames = dwc_urb->packet_count;
-+ int i;
-+ hcint_data_t frame_hcint;
-+
-+ for (i = 0; i < nr_frames; i++) {
-+ frame_hcint.d32 = dwc_urb->iso_descs[i].status;
-+ if (frame_hcint.b.xfercomp) {
-+ dwc_urb->iso_descs[i].status = 0;
-+ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
-+ } else if (frame_hcint.b.frmovrun) {
-+ if (qh->ep_is_in)
-+ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
-+ else
-+ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
-+ dwc_urb->error_count++;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ } else if (frame_hcint.b.xacterr) {
-+ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
-+ dwc_urb->error_count++;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ } else if (frame_hcint.b.bblerr) {
-+ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
-+ dwc_urb->error_count++;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ } else {
-+ /* Something went wrong */
-+ dwc_urb->iso_descs[i].status = -1;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ dwc_urb->error_count++;
-+ }
-+ }
-+ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
-+ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
-+ hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0);
-+ release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+}
-+
-+/**
-+ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
-+ * @hcd: Pointer to dwc_otg_hcd struct
-+ * @num: Host channel number
-+ *
-+ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
-+ * Returns total length of data or -1 if the buffers were not used.
-+ *
-+ */
-+int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
-+{
-+ dwc_hc_t *hc = qh->channel;
-+ struct fiq_dma_blob *blob = hcd->fiq_dmab;
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+ uint8_t *ptr = NULL;
-+ int index = 0, len = 0;
-+ int i = 0;
-+ if (hc->ep_is_in) {
-+ /* Copy data out of the DMA bounce buffers to the URB's buffer.
-+ * The align_buf is ignored as this is ignored on FSM enqueue. */
-+ ptr = qtd->urb->buf;
-+ if (qh->ep_type == UE_ISOCHRONOUS) {
-+ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
-+ index = qtd->isoc_frame_index;
-+ ptr += qtd->urb->iso_descs[index].offset;
-+ } else {
-+ /* Need to increment by actual_length for interrupt IN */
-+ ptr += qtd->urb->actual_length;
-+ }
-+
-+ for (i = 0; i < st->dma_info.index; i++) {
-+ len += st->dma_info.slot_len[i];
-+ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
-+ ptr += st->dma_info.slot_len[i];
-+ }
-+ return len;
-+ } else {
-+ /* OUT endpoints - nothing to do. */
-+ return -1;
-+ }
-+
-+}
-+/**
-+ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
-+ * from a channel handled in the FIQ
-+ * @hcd: Pointer to dwc_otg_hcd struct
-+ * @num: Host channel number
-+ *
-+ * If a host channel interrupt was received by the IRQ and this was a channel
-+ * used by the FIQ, the execution flow for transfer completion is substantially
-+ * different from the normal (messy) path. This function and its friends handles
-+ * channel cleanup and transaction completion from a FIQ transaction.
-+ */
-+int32_t dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
-+{
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+ dwc_hc_t *hc = hcd->hc_ptr_array[num];
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
-+ dwc_otg_qh_t *qh = hc->qh;
-+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
-+ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
-+ int hostchannels = 0;
-+ int ret = 0;
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
-+
-+ hostchannels = hcd->available_host_channels;
-+ switch (st->fsm) {
-+ case FIQ_TEST:
-+ break;
-+
-+ case FIQ_DEQUEUE_ISSUED:
-+ /* hc_halt was called. QTD no longer exists. */
-+ /* TODO: for a nonperiodic split transaction, need to issue a
-+ * CLEAR_TT_BUFFER hub command if we were in the start-split phase.
-+ */
-+ release_channel(hcd, hc, NULL, hc->halt_status);
-+ ret = 1;
-+ break;
-+
-+ case FIQ_NP_SPLIT_DONE:
-+ /* Nonperiodic transaction complete. */
-+ if (!hc->ep_is_in) {
-+ qtd->ssplit_out_xfer_count = hc->xfer_len;
-+ }
-+ if (hcint.b.xfercomp) {
-+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.nak) {
-+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+ }
-+ ret = 1;
-+ break;
-+
-+ case FIQ_NP_SPLIT_HS_ABORTED:
-+ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
-+ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
-+ * because there's no guarantee which order a non-periodic split happened in.
-+ * We could end up clearing a perfectly good transaction out of the buffer.
-+ */
-+ if (hcint.b.xacterr) {
-+ qtd->error_count += st->nr_errors;
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ahberr) {
-+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ local_fiq_disable();
-+ BUG();
-+ }
-+ break;
-+
-+ case FIQ_NP_SPLIT_LS_ABORTED:
-+ /* A few cases can cause this - either an unknown state on a SSPLIT or
-+ * STALL/data toggle error response on a CSPLIT */
-+ if (hcint.b.stall) {
-+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.datatglerr) {
-+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.bblerr) {
-+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ahberr) {
-+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ local_fiq_disable();
-+ BUG();
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_DONE:
-+ /* Isoc IN or Interrupt IN/OUT */
-+
-+ /* Flow control here is different from the normal execution by the driver.
-+ * We need to completely ignore most of the driver's method of handling
-+ * split transactions and do it ourselves.
-+ */
-+ if (hc->ep_type == UE_INTERRUPT) {
-+ if (hcint.b.nak) {
-+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hc->ep_is_in) {
-+ int len;
-+ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
-+ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
-+ qtd->urb->actual_length += len;
-+ if (qtd->urb->actual_length >= qtd->urb->length) {
-+ qtd->urb->status = 0;
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ /* Interrupt transfer not complete yet - is it a short read? */
-+ if (len < hc->max_packet) {
-+ /* Interrupt transaction complete */
-+ qtd->urb->status = 0;
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ /* Further transactions required */
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ } else {
-+ /* Interrupt OUT complete. */
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ qtd->urb->actual_length += hc->xfer_len;
-+ if (qtd->urb->actual_length >= qtd->urb->length) {
-+ qtd->urb->status = 0;
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ } else {
-+ /* ISOC IN complete. */
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ int len = 0;
-+ /* Record errors, update qtd. */
-+ if (st->nr_errors) {
-+ frame_desc->actual_length = 0;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ } else {
-+ frame_desc->status = 0;
-+ /* Unswizzle dma */
-+ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num);
-+ frame_desc->actual_length = len;
-+ }
-+ qtd->isoc_frame_index++;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_DONE: {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ /* Record errors, update qtd. */
-+ if (st->nr_errors) {
-+ frame_desc->actual_length = 0;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ } else {
-+ frame_desc->status = 0;
-+ frame_desc->actual_length = frame_desc->length;
-+ }
-+ qtd->isoc_frame_index++;
-+ qtd->isoc_split_offset = 0;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_NYET_ABORTED:
-+ /* Doh. lost the data. */
-+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
-+ "- FIQ reported NYET. Data may have been lost.\n",
-+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
-+ if (hc->ep_type == UE_ISOCHRONOUS) {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ /* Record errors, update qtd. */
-+ frame_desc->actual_length = 0;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ qtd->isoc_frame_index++;
-+ qtd->isoc_split_offset = 0;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ break;
-+
-+ case FIQ_HS_ISOC_DONE:
-+ /* The FIQ has performed a whole pile of isochronous transactions.
-+ * The status is recorded as the interrupt state should the transaction
-+ * fail.
-+ */
-+ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num);
-+ break;
-+
-+ case FIQ_PER_SPLIT_LS_ABORTED:
-+ if (hcint.b.xacterr) {
-+ /* Hub has responded with an ERR packet. Device
-+ * has been unplugged or the port has been disabled.
-+ * TODO: need to issue a reset to the hub port. */
-+ qtd->error_count += 3;
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.stall) {
-+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.bblerr) {
-+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
-+ "- FIQ reported FSM=%d. Data may have been lost.\n",
-+ st->fsm, hc->dev_addr, hc->ep_num);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_HS_ABORTED:
-+ /* Either the SSPLIT phase suffered transaction errors or something
-+ * unexpected happened.
-+ */
-+ qtd->error_count += 3;
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ break;
-+
-+ case FIQ_PER_SPLIT_TIMEOUT:
-+ /* Couldn't complete in the nominated frame */
-+ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
-+ "- FIQ timed out. Data may have been lost.\n",
-+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
-+ if (hc->ep_type == UE_ISOCHRONOUS) {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ /* Record errors, update qtd. */
-+ frame_desc->actual_length = 0;
-+ if (hc->ep_is_in) {
-+ frame_desc->status = -DWC_E_NO_STREAM_RES;
-+ } else {
-+ frame_desc->status = -DWC_E_COMMUNICATION;
-+ }
-+ qtd->isoc_frame_index++;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ break;
-+
-+ default:
-+ local_fiq_disable();
-+ DWC_WARN("unexpected state received on hc=%d fsm=%d", hc->hc_num, st->fsm);
-+ BUG();
-+ }
-+ //if (hostchannels != hcd->available_host_channels) {
-+ /* should have incremented by now! */
-+ // BUG();
-+// }
-+ return ret;
-+}
-+
-+/** Handles interrupt for a specific Host Channel */
-+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
-+{
-+ int retval = 0;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ dwc_hc_t *hc;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ dwc_otg_qtd_t *qtd;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
-+
-+ hc = dwc_otg_hcd->hc_ptr_array[num];
-+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
-+ if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ /* We are responding to a channel disable. Driver
-+ * state is cleared - our qtd has gone away.
-+ */
-+ release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
-+ return 1;
-+ }
-+ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
-+
-+ /*
-+ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
-+ * Execution path is fundamentally different for the channels after a FIQ has completed
-+ * a split transaction.
-+ */
-+ if (fiq_fsm_enable) {
-+ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
-+ case FIQ_PASSTHROUGH:
-+ break;
-+ case FIQ_PASSTHROUGH_ERRORSTATE:
-+ /* Hook into the error count */
-+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
-+ if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
-+ qtd->error_count = 0;
-+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET ");
-+ }
-+ break;
-+ default:
-+ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
-+ return 1;
-+ }
-+ }
-+
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+ hcint.d32 = hcint.d32 & hcintmsk.d32;
-+ if (!dwc_otg_hcd->core_if->dma_enable) {
-+ if (hcint.b.chhltd && hcint.d32 != 0x2) {
-+ hcint.b.chhltd = 0;
-+ }
-+ }
-+
-+ if (hcint.b.xfercomp) {
-+ retval |=
-+ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ /*
-+ * If NYET occurred at same time as Xfer Complete, the NYET is
-+ * handled by the Xfer Complete interrupt handler. Don't want
-+ * to call the NYET interrupt handler in this case.
-+ */
-+ hcint.b.nyet = 0;
-+ }
-+ if (hcint.b.chhltd) {
-+ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.ahberr) {
-+ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.stall) {
-+ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.nak) {
-+ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.ack) {
-+ if(!hcint.b.chhltd)
-+ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.nyet) {
-+ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.xacterr) {
-+ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.bblerr) {
-+ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.frmovrun) {
-+ retval |=
-+ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.datatglerr) {
-+ retval |=
-+ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+
-+ return retval;
-+}
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2015-03-10 17:26:51.302216687 +0100
-@@ -0,0 +1,985 @@
-+
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
-+ * $Revision: #20 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1872981 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the implementation of the HCD. In Linux, the HCD
-+ * implements the hc_driver API.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/string.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/version.h>
-+#include <asm/io.h>
-+#include <asm/fiq.h>
-+#include <linux/usb.h>
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
-+#include <../drivers/usb/core/hcd.h>
-+#else
-+#include <linux/usb/hcd.h>
-+#endif
-+#include <asm/bug.h>
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
-+#define USB_URB_EP_LINKING 1
-+#else
-+#define USB_URB_EP_LINKING 0
-+#endif
-+
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_hcd.h"
-+
-+extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
-+
-+/**
-+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
-+ * qualified with its direction (possible 32 endpoints per device).
-+ */
-+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
-+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
-+
-+static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
-+
-+extern bool fiq_enable;
-+
-+/** @name Linux HC Driver API Functions */
-+/** @{ */
-+/* manage i/o requests, device state */
-+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ struct usb_host_endpoint *ep,
-+#endif
-+ struct urb *urb, gfp_t mem_flags);
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
-+#endif
-+#else /* kernels at or post 2.6.30 */
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
-+ struct urb *urb, int status);
-+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
-+
-+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
-+#endif
-+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
-+extern int hcd_start(struct usb_hcd *hcd);
-+extern void hcd_stop(struct usb_hcd *hcd);
-+static int get_frame_number(struct usb_hcd *hcd);
-+extern int hub_status_data(struct usb_hcd *hcd, char *buf);
-+extern int hub_control(struct usb_hcd *hcd,
-+ u16 typeReq,
-+ u16 wValue, u16 wIndex, char *buf, u16 wLength);
-+
-+struct wrapper_priv_data {
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+};
-+
-+/** @} */
-+
-+static struct hc_driver dwc_otg_hc_driver = {
-+
-+ .description = dwc_otg_hcd_name,
-+ .product_desc = "DWC OTG Controller",
-+ .hcd_priv_size = sizeof(struct wrapper_priv_data),
-+
-+ .irq = dwc_otg_hcd_irq,
-+
-+ .flags = HCD_MEMORY | HCD_USB2,
-+
-+ //.reset =
-+ .start = hcd_start,
-+ //.suspend =
-+ //.resume =
-+ .stop = hcd_stop,
-+
-+ .urb_enqueue = dwc_otg_urb_enqueue,
-+ .urb_dequeue = dwc_otg_urb_dequeue,
-+ .endpoint_disable = endpoint_disable,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+ .endpoint_reset = endpoint_reset,
-+#endif
-+ .get_frame_number = get_frame_number,
-+
-+ .hub_status_data = hub_status_data,
-+ .hub_control = hub_control,
-+ //.bus_suspend =
-+ //.bus_resume =
-+};
-+
-+/** Gets the dwc_otg_hcd from a struct usb_hcd */
-+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
-+{
-+ struct wrapper_priv_data *p;
-+ p = (struct wrapper_priv_data *)(hcd->hcd_priv);
-+ return p->dwc_otg_hcd;
-+}
-+
-+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
-+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
-+}
-+
-+/** Gets the usb_host_endpoint associated with an URB. */
-+inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
-+{
-+ struct usb_device *dev = urb->dev;
-+ int ep_num = usb_pipeendpoint(urb->pipe);
-+
-+ if (usb_pipein(urb->pipe))
-+ return dev->ep_in[ep_num];
-+ else
-+ return dev->ep_out[ep_num];
-+}
-+
-+static int _disconnect(dwc_otg_hcd_t * hcd)
-+{
-+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+
-+ usb_hcd->self.is_b_host = 0;
-+ return 0;
-+}
-+
-+static int _start(dwc_otg_hcd_t * hcd)
-+{
-+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+
-+ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
-+ hcd_start(usb_hcd);
-+
-+ return 0;
-+}
-+
-+static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
-+ uint32_t * port_addr)
-+{
-+ struct urb *urb = (struct urb *)urb_handle;
-+ struct usb_bus *bus;
-+#if 1 //GRAYG - temporary
-+ if (NULL == urb_handle)
-+ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
-+ if (NULL == urb->dev)
-+ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
-+ if (NULL == port_addr)
-+ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
-+#endif
-+ if (urb->dev->tt) {
-+ if (NULL == urb->dev->tt->hub) {
-+ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
-+ __func__); //GRAYG
-+ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
-+ *hub_addr = 0; //GRAYG
-+ // we probably shouldn't have a transaction translator if
-+ // there's no associated hub?
-+ } else {
-+ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
-+ if (urb->dev->tt->hub == bus->root_hub)
-+ *hub_addr = 0;
-+ else
-+ *hub_addr = urb->dev->tt->hub->devnum;
-+ }
-+ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
-+ } else {
-+ *hub_addr = 0;
-+ *port_addr = urb->dev->ttport;
-+ }
-+ return 0;
-+}
-+
-+static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
-+{
-+ struct urb *urb = (struct urb *)urb_handle;
-+ return urb->dev->speed;
-+}
-+
-+static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
-+{
-+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+ return usb_hcd->self.b_hnp_enable;
-+}
-+
-+static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
-+ struct urb *urb)
-+{
-+ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
-+ } else {
-+ hcd_to_bus(hcd)->bandwidth_int_reqs++;
-+ }
-+}
-+
-+static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
-+ struct urb *urb)
-+{
-+ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
-+ } else {
-+ hcd_to_bus(hcd)->bandwidth_int_reqs--;
-+ }
-+}
-+
-+/**
-+ * Sets the final status of an URB and returns it to the device driver. Any
-+ * required cleanup of the URB is performed. The HCD lock should be held on
-+ * entry.
-+ */
-+static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
-+{
-+ struct urb *urb = (struct urb *)urb_handle;
-+ urb_tq_entry_t *new_entry;
-+ int rc = 0;
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
-+ __func__, urb, usb_pipedevice(urb->pipe),
-+ usb_pipeendpoint(urb->pipe),
-+ usb_pipein(urb->pipe) ? "IN" : "OUT", status);
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ int i;
-+ for (i = 0; i < urb->number_of_packets; i++) {
-+ DWC_PRINTF(" ISO Desc %d status: %d\n",
-+ i, urb->iso_frame_desc[i].status);
-+ }
-+ }
-+ }
-+ new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
-+ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
-+ /* Convert status value. */
-+ switch (status) {
-+ case -DWC_E_PROTOCOL:
-+ status = -EPROTO;
-+ break;
-+ case -DWC_E_IN_PROGRESS:
-+ status = -EINPROGRESS;
-+ break;
-+ case -DWC_E_PIPE:
-+ status = -EPIPE;
-+ break;
-+ case -DWC_E_IO:
-+ status = -EIO;
-+ break;
-+ case -DWC_E_TIMEOUT:
-+ status = -ETIMEDOUT;
-+ break;
-+ case -DWC_E_OVERFLOW:
-+ status = -EOVERFLOW;
-+ break;
-+ case -DWC_E_SHUTDOWN:
-+ status = -ESHUTDOWN;
-+ break;
-+ default:
-+ if (status) {
-+ DWC_PRINTF("Uknown urb status %d\n", status);
-+
-+ }
-+ }
-+
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ int i;
-+
-+ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
-+ for (i = 0; i < urb->number_of_packets; ++i) {
-+ urb->iso_frame_desc[i].actual_length =
-+ dwc_otg_hcd_urb_get_iso_desc_actual_length
-+ (dwc_otg_urb, i);
-+ urb->iso_frame_desc[i].status =
-+ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
-+ }
-+ }
-+
-+ urb->status = status;
-+ urb->hcpriv = NULL;
-+ if (!status) {
-+ if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
-+ (urb->actual_length < urb->transfer_buffer_length)) {
-+ urb->status = -EREMOTEIO;
-+ }
-+ }
-+
-+ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
-+ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
-+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
-+ if (ep) {
-+ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
-+ dwc_otg_hcd_get_ep_bandwidth(hcd,
-+ ep->hcpriv),
-+ urb);
-+ }
-+ }
-+ DWC_FREE(dwc_otg_urb);
-+ if (!new_entry) {
-+ DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
-+ urb->status = -EPROTO;
-+ /* don't schedule the tasklet -
-+ * directly return the packet here with error. */
-+#if USB_URB_EP_LINKING
-+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
-+#endif
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
-+#else
-+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
-+#endif
-+ } else {
-+ new_entry->urb = urb;
-+#if USB_URB_EP_LINKING
-+ rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
-+ if(0 == rc) {
-+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
-+ }
-+#endif
-+ if(0 == rc) {
-+ DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
-+ urb_tq_entries);
-+ DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
-+ }
-+ }
-+ return 0;
-+}
-+
-+static struct dwc_otg_hcd_function_ops hcd_fops = {
-+ .start = _start,
-+ .disconnect = _disconnect,
-+ .hub_info = _hub_info,
-+ .speed = _speed,
-+ .complete = _complete,
-+ .get_b_hnp_enable = _get_b_hnp_enable,
-+};
-+
-+static struct fiq_handler fh = {
-+ .name = "usb_fiq",
-+};
-+
-+
-+
-+/**
-+ * Initializes the HCD. This function allocates memory for and initializes the
-+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
-+ * USB bus with the core and calls the hc_driver->start() function. It returns
-+ * a negative error on failure.
-+ */
-+int hcd_init(dwc_bus_dev_t *_dev)
-+{
-+ struct usb_hcd *hcd = NULL;
-+ dwc_otg_hcd_t *dwc_otg_hcd = NULL;
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ int retval = 0;
-+ u64 dmamask;
-+ struct pt_regs regs;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
-+
-+ /* Set device flags indicating whether the HCD supports DMA. */
-+ if (dwc_otg_is_dma_enable(otg_dev->core_if))
-+ dmamask = DMA_BIT_MASK(32);
-+ else
-+ dmamask = 0;
-+
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+ dma_set_mask(&_dev->dev, dmamask);
-+ dma_set_coherent_mask(&_dev->dev, dmamask);
-+#elif defined(PCI_INTERFACE)
-+ pci_set_dma_mask(_dev, dmamask);
-+ pci_set_consistent_dma_mask(_dev, dmamask);
-+#endif
-+
-+ /*
-+ * Allocate memory for the base HCD plus the DWC OTG HCD.
-+ * Initialize the base HCD.
-+ */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
-+#else
-+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
-+ hcd->has_tt = 1;
-+// hcd->uses_new_polling = 1;
-+// hcd->poll_rh = 0;
-+#endif
-+ if (!hcd) {
-+ retval = -ENOMEM;
-+ goto error1;
-+ }
-+
-+ hcd->regs = otg_dev->os_dep.base;
-+
-+
-+ /* Initialize the DWC OTG HCD. */
-+ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
-+ if (!dwc_otg_hcd) {
-+ goto error2;
-+ }
-+ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
-+ dwc_otg_hcd;
-+ otg_dev->hcd = dwc_otg_hcd;
-+
-+ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
-+ goto error2;
-+ }
-+
-+ if (fiq_enable)
-+ {
-+ if (claim_fiq(&fh)) {
-+ DWC_ERROR("Can't claim FIQ");
-+ goto error2;
-+ }
-+
-+ DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
-+ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
-+
-+ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
-+ memset(&regs,0,sizeof(regs));
-+
-+ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
-+ if (fiq_fsm_enable) {
-+ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
-+ //regs.ARM_r10 = dwc_otg_hcd->dma;
-+ regs.ARM_fp = (long) dwc_otg_fiq_fsm;
-+ } else {
-+ regs.ARM_fp = (long) dwc_otg_fiq_nop;
-+ }
-+
-+ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
-+
-+// __show_regs(&regs);
-+ set_fiq_regs(&regs);
-+
-+ //Set the mphi periph to the required registers
-+ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
-+ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
-+ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
-+ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
-+ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
-+ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
-+ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
-+ //Enable mphi peripheral
-+ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
-+#ifdef DEBUG
-+ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
-+ DWC_WARN("MPHI periph has been enabled");
-+ else
-+ DWC_WARN("MPHI periph has NOT been enabled");
-+#endif
-+ // Enable FIQ interrupt from USB peripheral
-+ enable_fiq(INTERRUPT_VC_USB);
-+ local_fiq_enable();
-+ }
-+
-+
-+ otg_dev->hcd->otg_dev = otg_dev;
-+ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
-+ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
-+#endif
-+ /* Don't support SG list at this point */
-+ hcd->self.sg_tablesize = 0;
-+#endif
-+ /*
-+ * Finish generic HCD initialization and start the HCD. This function
-+ * allocates the DMA buffer pool, registers the USB bus, requests the
-+ * IRQ line, and calls hcd_start method.
-+ */
-+#ifdef PLATFORM_INTERFACE
-+ retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED | IRQF_DISABLED);
-+#else
-+ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED | IRQF_DISABLED);
-+#endif
-+ if (retval < 0) {
-+ goto error2;
-+ }
-+
-+ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
-+ return 0;
-+
-+error2:
-+ usb_put_hcd(hcd);
-+error1:
-+ return retval;
-+}
-+
-+/**
-+ * Removes the HCD.
-+ * Frees memory and resources associated with the HCD and deregisters the bus.
-+ */
-+void hcd_remove(dwc_bus_dev_t *_dev)
-+{
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+ struct usb_hcd *hcd;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
-+
-+ if (!otg_dev) {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
-+ return;
-+ }
-+
-+ dwc_otg_hcd = otg_dev->hcd;
-+
-+ if (!dwc_otg_hcd) {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
-+ return;
-+ }
-+
-+ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
-+
-+ if (!hcd) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
-+ __func__);
-+ return;
-+ }
-+ usb_remove_hcd(hcd);
-+ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
-+ dwc_otg_hcd_remove(dwc_otg_hcd);
-+ usb_put_hcd(hcd);
-+}
-+
-+/* =========================================================================
-+ * Linux HC Driver Functions
-+ * ========================================================================= */
-+
-+/** Initializes the DWC_otg controller and its root hub and prepares it for host
-+ * mode operation. Activates the root port. Returns 0 on success and a negative
-+ * error code on failure. */
-+int hcd_start(struct usb_hcd *hcd)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ struct usb_bus *bus;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
-+ bus = hcd_to_bus(hcd);
-+
-+ hcd->state = HC_STATE_RUNNING;
-+ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
-+ return 0;
-+ }
-+
-+ /* Initialize and connect root hub if one is not already attached */
-+ if (bus->root_hub) {
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
-+ /* Inform the HUB driver to resume. */
-+ usb_hcd_resume_root_hub(hcd);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ */
-+void hcd_stop(struct usb_hcd *hcd)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+ dwc_otg_hcd_stop(dwc_otg_hcd);
-+}
-+
-+/** Returns the current frame number. */
-+static int get_frame_number(struct usb_hcd *hcd)
-+{
-+ hprt0_data_t hprt0;
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
-+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
-+ else
-+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
-+}
-+
-+#ifdef DEBUG
-+static void dump_urb_info(struct urb *urb, char *fn_name)
-+{
-+ DWC_PRINTF("%s, urb %p\n", fn_name, urb);
-+ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
-+ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
-+ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
-+ DWC_PRINTF(" Endpoint type: %s\n", ( {
-+ char *pipetype;
-+ switch (usb_pipetype(urb->pipe)) {
-+case PIPE_CONTROL:
-+pipetype = "CONTROL"; break; case PIPE_BULK:
-+pipetype = "BULK"; break; case PIPE_INTERRUPT:
-+pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
-+pipetype = "ISOCHRONOUS"; break; default:
-+ pipetype = "UNKNOWN"; break;};
-+ pipetype;}
-+ )) ;
-+ DWC_PRINTF(" Speed: %s\n", ( {
-+ char *speed; switch (urb->dev->speed) {
-+case USB_SPEED_HIGH:
-+speed = "HIGH"; break; case USB_SPEED_FULL:
-+speed = "FULL"; break; case USB_SPEED_LOW:
-+speed = "LOW"; break; default:
-+ speed = "UNKNOWN"; break;};
-+ speed;}
-+ )) ;
-+ DWC_PRINTF(" Max packet size: %d\n",
-+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
-+ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length);
-+ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n",
-+ urb->transfer_buffer, (void *)urb->transfer_dma);
-+ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n",
-+ urb->setup_packet, (void *)urb->setup_dma);
-+ DWC_PRINTF(" Interval: %d\n", urb->interval);
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ int i;
-+ for (i = 0; i < urb->number_of_packets; i++) {
-+ DWC_PRINTF(" ISO Desc %d:\n", i);
-+ DWC_PRINTF(" offset: %d, length %d\n",
-+ urb->iso_frame_desc[i].offset,
-+ urb->iso_frame_desc[i].length);
-+ }
-+ }
-+}
-+#endif
-+
-+/** Starts processing a USB transfer request specified by a USB Request Block
-+ * (URB). mem_flags indicates the type of memory allocation to use while
-+ * processing this URB. */
-+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ struct usb_host_endpoint *ep,
-+#endif
-+ struct urb *urb, gfp_t mem_flags)
-+{
-+ int retval = 0;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
-+ struct usb_host_endpoint *ep = urb->ep;
-+#endif
-+ dwc_irqflags_t irqflags;
-+ void **ref_ep_hcpriv = &ep->hcpriv;
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ dwc_otg_hcd_urb_t *dwc_otg_urb;
-+ int i;
-+ int alloc_bandwidth = 0;
-+ uint8_t ep_type = 0;
-+ uint32_t flags = 0;
-+ void *buf;
-+
-+#ifdef DEBUG
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ dump_urb_info(urb, "dwc_otg_urb_enqueue");
-+ }
-+#endif
-+
-+ if (!urb->transfer_buffer && urb->transfer_buffer_length)
-+ return -EINVAL;
-+
-+ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
-+ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
-+ if (!dwc_otg_hcd_is_bandwidth_allocated
-+ (dwc_otg_hcd, ref_ep_hcpriv)) {
-+ alloc_bandwidth = 1;
-+ }
-+ }
-+
-+ switch (usb_pipetype(urb->pipe)) {
-+ case PIPE_CONTROL:
-+ ep_type = USB_ENDPOINT_XFER_CONTROL;
-+ break;
-+ case PIPE_ISOCHRONOUS:
-+ ep_type = USB_ENDPOINT_XFER_ISOC;
-+ break;
-+ case PIPE_BULK:
-+ ep_type = USB_ENDPOINT_XFER_BULK;
-+ break;
-+ case PIPE_INTERRUPT:
-+ ep_type = USB_ENDPOINT_XFER_INT;
-+ break;
-+ default:
-+ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
-+ }
-+
-+ /* # of packets is often 0 - do we really need to call this then? */
-+ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
-+ urb->number_of_packets,
-+ mem_flags == GFP_ATOMIC ? 1 : 0);
-+
-+ if(dwc_otg_urb == NULL)
-+ return -ENOMEM;
-+
-+ if (!dwc_otg_urb && urb->number_of_packets)
-+ return -ENOMEM;
-+
-+ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
-+ usb_pipeendpoint(urb->pipe), ep_type,
-+ usb_pipein(urb->pipe),
-+ usb_maxpacket(urb->dev, urb->pipe,
-+ !(usb_pipein(urb->pipe))));
-+
-+ buf = urb->transfer_buffer;
-+ if (hcd->self.uses_dma) {
-+ /*
-+ * Calculate virtual address from physical address,
-+ * because some class driver may not fill transfer_buffer.
-+ * In Buffer DMA mode virual address is used,
-+ * when handling non DWORD aligned buffers.
-+ */
-+ //buf = phys_to_virt(urb->transfer_dma);
-+ // DMA addresses are bus addresses not physical addresses!
-+ buf = dma_to_virt(&urb->dev->dev, urb->transfer_dma);
-+ }
-+
-+ if (!(urb->transfer_flags & URB_NO_INTERRUPT))
-+ flags |= URB_GIVEBACK_ASAP;
-+ if (urb->transfer_flags & URB_ZERO_PACKET)
-+ flags |= URB_SEND_ZERO_PACKET;
-+
-+ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
-+ urb->transfer_dma,
-+ urb->transfer_buffer_length,
-+ urb->setup_packet,
-+ urb->setup_dma, flags, urb->interval);
-+
-+ for (i = 0; i < urb->number_of_packets; ++i) {
-+ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
-+ urb->
-+ iso_frame_desc[i].offset,
-+ urb->
-+ iso_frame_desc[i].length);
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
-+ urb->hcpriv = dwc_otg_urb;
-+#if USB_URB_EP_LINKING
-+ retval = usb_hcd_link_urb_to_ep(hcd, urb);
-+ if (0 == retval)
-+#endif
-+ {
-+ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
-+ /*(dwc_otg_qh_t **)*/
-+ ref_ep_hcpriv, 1);
-+ if (0 == retval) {
-+ if (alloc_bandwidth) {
-+ allocate_bus_bandwidth(hcd,
-+ dwc_otg_hcd_get_ep_bandwidth(
-+ dwc_otg_hcd, *ref_ep_hcpriv),
-+ urb);
-+ }
-+ } else {
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
-+#if USB_URB_EP_LINKING
-+ usb_hcd_unlink_urb_from_ep(hcd, urb);
-+#endif
-+ DWC_FREE(dwc_otg_urb);
-+ urb->hcpriv = NULL;
-+ if (retval == -DWC_E_NO_DEVICE)
-+ retval = -ENODEV;
-+ }
-+ }
-+#if USB_URB_EP_LINKING
-+ else
-+ {
-+ DWC_FREE(dwc_otg_urb);
-+ urb->hcpriv = NULL;
-+ }
-+#endif
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
-+ return retval;
-+}
-+
-+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
-+ * success. */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
-+#else
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
-+#endif
-+{
-+ dwc_irqflags_t flags;
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+ int rc;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
-+
-+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+#ifdef DEBUG
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ dump_urb_info(urb, "dwc_otg_urb_dequeue");
-+ }
-+#endif
-+
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ rc = usb_hcd_check_unlink_urb(hcd, urb, status);
-+ if (0 == rc) {
-+ if(urb->hcpriv != NULL) {
-+ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
-+ (dwc_otg_hcd_urb_t *)urb->hcpriv);
-+
-+ DWC_FREE(urb->hcpriv);
-+ urb->hcpriv = NULL;
-+ }
-+ }
-+
-+ if (0 == rc) {
-+ /* Higher layer software sets URB status. */
-+#if USB_URB_EP_LINKING
-+ usb_hcd_unlink_urb_from_ep(hcd, urb);
-+#endif
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ usb_hcd_giveback_urb(hcd, urb);
-+#else
-+ usb_hcd_giveback_urb(hcd, urb, status);
-+#endif
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
-+ DWC_PRINTF(" 1urb->status = %d\n", urb->status);
-+ }
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
-+ } else {
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
-+ rc);
-+ }
-+
-+ return rc;
-+}
-+
-+/* Frees resources in the DWC_otg controller related to a given endpoint. Also
-+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
-+ * must already be dequeued. */
-+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+ DWC_DEBUGPL(DBG_HCD,
-+ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
-+ "endpoint=%d\n", ep->desc.bEndpointAddress,
-+ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
-+ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
-+ ep->hcpriv = NULL;
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+/* Resets endpoint specific parameter values, in current version used to reset
-+ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
-+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
-+{
-+ dwc_irqflags_t flags;
-+ struct usb_device *udev = NULL;
-+ int epnum = usb_endpoint_num(&ep->desc);
-+ int is_out = usb_endpoint_dir_out(&ep->desc);
-+ int is_control = usb_endpoint_xfer_control(&ep->desc);
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
-+
-+ if (dev)
-+ udev = to_usb_device(dev);
-+ else
-+ return;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
-+
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ usb_settoggle(udev, epnum, is_out, 0);
-+ if (is_control)
-+ usb_settoggle(udev, epnum, !is_out, 0);
-+
-+ if (ep->hcpriv) {
-+ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+}
-+#endif
-+
-+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
-+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
-+ * interrupt.
-+ *
-+ * This function is called by the USB core when an interrupt occurs */
-+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
-+ if (retval != 0) {
-+ S3C2410X_CLEAR_EINTPEND();
-+ }
-+ return IRQ_RETVAL(retval);
-+}
-+
-+/** Creates Status Change bitmap for the root hub and root port. The bitmap is
-+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
-+ * is the status change indicator for the single root port. Returns 1 if either
-+ * change indicator is 1, otherwise returns 0. */
-+int hub_status_data(struct usb_hcd *hcd, char *buf)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+ buf[0] = 0;
-+ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
-+
-+ return (buf[0] != 0);
-+}
-+
-+/** Handles hub class-specific requests. */
-+int hub_control(struct usb_hcd *hcd,
-+ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
-+{
-+ int retval;
-+
-+ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
-+ typeReq, wValue, wIndex, buf, wLength);
-+
-+ switch (retval) {
-+ case -DWC_E_INVALID:
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2015-03-10 17:26:51.306216687 +0100
-@@ -0,0 +1,942 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
-+ * $Revision: #44 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the functions to manage Queue Heads and Queue
-+ * Transfer Descriptors.
-+ */
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+extern bool microframe_schedule;
-+
-+/**
-+ * Free each QTD in the QH's QTD-list then free the QH. QH should already be
-+ * removed from a list. QTD list should already be empty if called from URB
-+ * Dequeue.
-+ *
-+ * @param hcd HCD instance.
-+ * @param qh The QH to free.
-+ */
-+void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+
-+ /* Free each QTD in the QTD list */
-+ DWC_SPINLOCK(hcd->lock);
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
-+ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
-+ dwc_otg_hcd_qtd_free(qtd);
-+ }
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_qh_free_ddma(hcd, qh);
-+ } else if (qh->dw_align_buf) {
-+ uint32_t buf_size;
-+ if (qh->ep_type == UE_ISOCHRONOUS) {
-+ buf_size = 4096;
-+ } else {
-+ buf_size = hcd->core_if->core_params->max_transfer_size;
-+ }
-+ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
-+ }
-+
-+ DWC_FREE(qh);
-+ DWC_SPINUNLOCK(hcd->lock);
-+ return;
-+}
-+
-+#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6)
-+#define HS_HOST_DELAY 5 /* nanoseconds */
-+#define FS_LS_HOST_DELAY 1000 /* nanoseconds */
-+#define HUB_LS_SETUP 333 /* nanoseconds */
-+#define NS_TO_US(ns) ((ns + 500) / 1000)
-+ /* convert & round nanoseconds to microseconds */
-+
-+static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
-+{
-+ unsigned long retval;
-+
-+ switch (speed) {
-+ case USB_SPEED_HIGH:
-+ if (is_isoc) {
-+ retval =
-+ ((38 * 8 * 2083) +
-+ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
-+ HS_HOST_DELAY;
-+ } else {
-+ retval =
-+ ((55 * 8 * 2083) +
-+ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
-+ HS_HOST_DELAY;
-+ }
-+ break;
-+ case USB_SPEED_FULL:
-+ if (is_isoc) {
-+ retval =
-+ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
-+ if (is_in) {
-+ retval = 7268 + FS_LS_HOST_DELAY + retval;
-+ } else {
-+ retval = 6265 + FS_LS_HOST_DELAY + retval;
-+ }
-+ } else {
-+ retval =
-+ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
-+ retval = 9107 + FS_LS_HOST_DELAY + retval;
-+ }
-+ break;
-+ case USB_SPEED_LOW:
-+ if (is_in) {
-+ retval =
-+ (67667 * (31 + 10 * BitStuffTime(bytecount))) /
-+ 1000;
-+ retval =
-+ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
-+ retval;
-+ } else {
-+ retval =
-+ (66700 * (31 + 10 * BitStuffTime(bytecount))) /
-+ 1000;
-+ retval =
-+ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
-+ retval;
-+ }
-+ break;
-+ default:
-+ DWC_WARN("Unknown device speed\n");
-+ retval = -1;
-+ }
-+
-+ return NS_TO_US(retval);
-+}
-+
-+/**
-+ * Initializes a QH structure.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ * @param urb Holds the information about the device/endpoint that we need
-+ * to initialize the QH.
-+ */
-+#define SCHEDULE_SLOP 10
-+void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
-+{
-+ char *speed, *type;
-+ int dev_speed;
-+ uint32_t hub_addr, hub_port;
-+
-+ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
-+
-+ /* Initialize QH */
-+ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
-+
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
-+ DWC_CIRCLEQ_INIT(&qh->qtd_list);
-+ DWC_LIST_INIT(&qh->qh_list_entry);
-+ qh->channel = NULL;
-+
-+ /* FS/LS Enpoint on HS Hub
-+ * NOT virtual root hub */
-+ dev_speed = hcd->fops->speed(hcd, urb->priv);
-+
-+ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
-+ qh->do_split = 0;
-+ if (microframe_schedule)
-+ qh->speed = dev_speed;
-+
-+ qh->nak_frame = 0xffff;
-+
-+ if (((dev_speed == USB_SPEED_LOW) ||
-+ (dev_speed == USB_SPEED_FULL)) &&
-+ (hub_addr != 0 && hub_addr != 1)) {
-+ DWC_DEBUGPL(DBG_HCD,
-+ "QH init: EP %d: TT found at hub addr %d, for port %d\n",
-+ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
-+ hub_port);
-+ qh->do_split = 1;
-+ qh->skip_count = 0;
-+ }
-+
-+ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
-+ /* Compute scheduling parameters once and save them. */
-+ hprt0_data_t hprt;
-+
-+ /** @todo Account for split transfers in the bus time. */
-+ int bytecount =
-+ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
-+
-+ qh->usecs =
-+ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
-+ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
-+ bytecount);
-+ /* Start in a slightly future (micro)frame. */
-+ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
-+ SCHEDULE_SLOP);
-+ qh->interval = urb->interval;
-+
-+#if 0
-+ /* Increase interrupt polling rate for debugging. */
-+ if (qh->ep_type == UE_INTERRUPT) {
-+ qh->interval = 8;
-+ }
-+#endif
-+ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
-+ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
-+ ((dev_speed == USB_SPEED_LOW) ||
-+ (dev_speed == USB_SPEED_FULL))) {
-+ qh->interval *= 8;
-+ qh->sched_frame |= 0x7;
-+ qh->start_split_frame = qh->sched_frame;
-+ }
-+
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
-+ dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
-+ dwc_otg_hcd_get_ep_num(&urb->pipe_info),
-+ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
-+ switch (dev_speed) {
-+ case USB_SPEED_LOW:
-+ qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
-+ speed = "low";
-+ break;
-+ case USB_SPEED_FULL:
-+ qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
-+ speed = "full";
-+ break;
-+ case USB_SPEED_HIGH:
-+ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
-+ speed = "high";
-+ break;
-+ default:
-+ speed = "?";
-+ break;
-+ }
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
-+
-+ switch (qh->ep_type) {
-+ case UE_ISOCHRONOUS:
-+ type = "isochronous";
-+ break;
-+ case UE_INTERRUPT:
-+ type = "interrupt";
-+ break;
-+ case UE_CONTROL:
-+ type = "control";
-+ break;
-+ case UE_BULK:
-+ type = "bulk";
-+ break;
-+ default:
-+ type = "?";
-+ break;
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
-+
-+#ifdef DEBUG
-+ if (qh->ep_type == UE_INTERRUPT) {
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
-+ qh->usecs);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
-+ qh->interval);
-+ }
-+#endif
-+
-+}
-+
-+/**
-+ * This function allocates and initializes a QH.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param urb Holds the information about the device/endpoint that we need
-+ * to initialize the QH.
-+ * @param atomic_alloc Flag to do atomic allocation if needed
-+ *
-+ * @return Returns pointer to the newly allocated QH, or NULL on error. */
-+dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * urb, int atomic_alloc)
-+{
-+ dwc_otg_qh_t *qh;
-+
-+ /* Allocate memory */
-+ /** @todo add memflags argument */
-+ qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
-+ if (qh == NULL) {
-+ DWC_ERROR("qh allocation failed");
-+ return NULL;
-+ }
-+
-+ qh_init(hcd, qh, urb);
-+
-+ if (hcd->core_if->dma_desc_enable
-+ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
-+ dwc_otg_hcd_qh_free(hcd, qh);
-+ return NULL;
-+ }
-+
-+ return qh;
-+}
-+
-+/* microframe_schedule=0 start */
-+
-+/**
-+ * Checks that a channel is available for a periodic transfer.
-+ *
-+ * @return 0 if successful, negative error code otherise.
-+ */
-+static int periodic_channel_available(dwc_otg_hcd_t * hcd)
-+{
-+ /*
-+ * Currently assuming that there is a dedicated host channnel for each
-+ * periodic transaction plus at least one host channel for
-+ * non-periodic transactions.
-+ */
-+ int status;
-+ int num_channels;
-+
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
-+ && (hcd->periodic_channels < num_channels - 1)) {
-+ status = 0;
-+ } else {
-+ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
-+ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE
-+ status = -DWC_E_NO_SPACE;
-+ }
-+
-+ return status;
-+}
-+
-+/**
-+ * Checks that there is sufficient bandwidth for the specified QH in the
-+ * periodic schedule. For simplicity, this calculation assumes that all the
-+ * transfers in the periodic schedule may occur in the same (micro)frame.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH containing periodic bandwidth required.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status;
-+ int16_t max_claimed_usecs;
-+
-+ status = 0;
-+
-+ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
-+ /*
-+ * High speed mode.
-+ * Max periodic usecs is 80% x 125 usec = 100 usec.
-+ */
-+
-+ max_claimed_usecs = 100 - qh->usecs;
-+ } else {
-+ /*
-+ * Full speed mode.
-+ * Max periodic usecs is 90% x 1000 usec = 900 usec.
-+ */
-+ max_claimed_usecs = 900 - qh->usecs;
-+ }
-+
-+ if (hcd->periodic_usecs > max_claimed_usecs) {
-+ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE
-+ status = -DWC_E_NO_SPACE;
-+ }
-+
-+ return status;
-+}
-+
-+/* microframe_schedule=0 end */
-+
-+/**
-+ * Microframe scheduler
-+ * track the total use in hcd->frame_usecs
-+ * keep each qh use in qh->frame_usecs
-+ * when surrendering the qh then donate the time back
-+ */
-+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
-+
-+/*
-+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
-+ */
-+int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
-+{
-+ int i;
-+ for (i=0; i<8; i++) {
-+ _hcd->frame_usecs[i] = max_uframe_usecs[i];
-+ }
-+ return 0;
-+}
-+
-+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+ int i;
-+ unsigned short utime;
-+ int t_left;
-+ int ret;
-+ int done;
-+
-+ ret = -1;
-+ utime = _qh->usecs;
-+ t_left = utime;
-+ i = 0;
-+ done = 0;
-+ while (done == 0) {
-+ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
-+ if (utime <= _hcd->frame_usecs[i]) {
-+ _hcd->frame_usecs[i] -= utime;
-+ _qh->frame_usecs[i] += utime;
-+ t_left -= utime;
-+ ret = i;
-+ done = 1;
-+ return ret;
-+ } else {
-+ i++;
-+ if (i == 8) {
-+ done = 1;
-+ ret = -1;
-+ }
-+ }
-+ }
-+ return ret;
-+ }
-+
-+/*
-+ * use this for FS apps that can span multiple uframes
-+ */
-+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+ int i;
-+ int j;
-+ unsigned short utime;
-+ int t_left;
-+ int ret;
-+ int done;
-+ unsigned short xtime;
-+
-+ ret = -1;
-+ utime = _qh->usecs;
-+ t_left = utime;
-+ i = 0;
-+ done = 0;
-+loop:
-+ while (done == 0) {
-+ if(_hcd->frame_usecs[i] <= 0) {
-+ i++;
-+ if (i == 8) {
-+ done = 1;
-+ ret = -1;
-+ }
-+ goto loop;
-+ }
-+
-+ /*
-+ * we need n consecutive slots
-+ * so use j as a start slot j plus j+1 must be enough time (for now)
-+ */
-+ xtime= _hcd->frame_usecs[i];
-+ for (j = i+1 ; j < 8 ; j++ ) {
-+ /*
-+ * if we add this frame remaining time to xtime we may
-+ * be OK, if not we need to test j for a complete frame
-+ */
-+ if ((xtime+_hcd->frame_usecs[j]) < utime) {
-+ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
-+ j = 8;
-+ ret = -1;
-+ continue;
-+ }
-+ }
-+ if (xtime >= utime) {
-+ ret = i;
-+ j = 8; /* stop loop with a good value ret */
-+ continue;
-+ }
-+ /* add the frame time to x time */
-+ xtime += _hcd->frame_usecs[j];
-+ /* we must have a fully available next frame or break */
-+ if ((xtime < utime)
-+ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
-+ ret = -1;
-+ j = 8; /* stop loop with a bad value ret */
-+ continue;
-+ }
-+ }
-+ if (ret >= 0) {
-+ t_left = utime;
-+ for (j = i; (t_left>0) && (j < 8); j++ ) {
-+ t_left -= _hcd->frame_usecs[j];
-+ if ( t_left <= 0 ) {
-+ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
-+ _hcd->frame_usecs[j]= -t_left;
-+ ret = i;
-+ done = 1;
-+ } else {
-+ _qh->frame_usecs[j] += _hcd->frame_usecs[j];
-+ _hcd->frame_usecs[j] = 0;
-+ }
-+ }
-+ } else {
-+ i++;
-+ if (i == 8) {
-+ done = 1;
-+ ret = -1;
-+ }
-+ }
-+ }
-+ return ret;
-+}
-+
-+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+ int ret;
-+ ret = -1;
-+
-+ if (_qh->speed == USB_SPEED_HIGH) {
-+ /* if this is a hs transaction we need a full frame */
-+ ret = find_single_uframe(_hcd, _qh);
-+ } else {
-+ /* if this is a fs transaction we may need a sequence of frames */
-+ ret = find_multi_uframe(_hcd, _qh);
-+ }
-+ return ret;
-+}
-+
-+/**
-+ * Checks that the max transfer size allowed in a host channel is large enough
-+ * to handle the maximum data transfer in a single (micro)frame for a periodic
-+ * transfer.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for a periodic endpoint.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status;
-+ uint32_t max_xfer_size;
-+ uint32_t max_channel_xfer_size;
-+
-+ status = 0;
-+
-+ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
-+ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
-+
-+ if (max_xfer_size > max_channel_xfer_size) {
-+ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
-+ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE
-+ status = -DWC_E_NO_SPACE;
-+ }
-+
-+ return status;
-+}
-+
-+
-+
-+/**
-+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for the periodic transfer. The QH should already contain the
-+ * scheduling information.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status = 0;
-+
-+ if (microframe_schedule) {
-+ int frame;
-+ status = find_uframe(hcd, qh);
-+ frame = -1;
-+ if (status == 0) {
-+ frame = 7;
-+ } else {
-+ if (status > 0 )
-+ frame = status-1;
-+ }
-+
-+ /* Set the new frame up */
-+ if (frame > -1) {
-+ qh->sched_frame &= ~0x7;
-+ qh->sched_frame |= (frame & 7);
-+ }
-+
-+ if (status != -1)
-+ status = 0;
-+ } else {
-+ status = periodic_channel_available(hcd);
-+ if (status) {
-+ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE
-+ return status;
-+ }
-+
-+ status = check_periodic_bandwidth(hcd, qh);
-+ }
-+ if (status) {
-+ DWC_INFO("%s: Insufficient periodic bandwidth for "
-+ "periodic transfer.\n", __func__);
-+ return status;
-+ }
-+ status = check_max_xfer_size(hcd, qh);
-+ if (status) {
-+ DWC_INFO("%s: Channel max transfer size too small "
-+ "for periodic transfer.\n", __func__);
-+ return status;
-+ }
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ /* Don't rely on SOF and start in ready schedule */
-+ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
-+ }
-+ else {
-+ if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
-+ {
-+ hcd->fiq_state->next_sched_frame = qh->sched_frame;
-+
-+ }
-+ /* Always start in the inactive schedule. */
-+ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
-+ }
-+
-+ if (!microframe_schedule) {
-+ /* Reserve the periodic channel. */
-+ hcd->periodic_channels++;
-+ }
-+
-+ /* Update claimed usecs per (micro)frame. */
-+ hcd->periodic_usecs += qh->usecs;
-+
-+ return status;
-+}
-+
-+
-+/**
-+ * This function adds a QH to either the non periodic or periodic schedule if
-+ * it is not already in the schedule. If the QH is already in the schedule, no
-+ * action is taken.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status = 0;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ /* QH already in a schedule. */
-+ return status;
-+ }
-+
-+ /* Add the new QH to the appropriate schedule */
-+ if (dwc_qh_is_non_per(qh)) {
-+ /* Always start in the inactive schedule. */
-+ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
-+ &qh->qh_list_entry);
-+ //hcd->fiq_state->kick_np_queues = 1;
-+ } else {
-+ status = schedule_periodic(hcd, qh);
-+ if ( !hcd->periodic_qh_count ) {
-+ intr_mask.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ }
-+ hcd->periodic_qh_count++;
-+ }
-+
-+ return status;
-+}
-+
-+/**
-+ * Removes an interrupt or isochronous transfer from the periodic schedule.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for the periodic transfer.
-+ */
-+static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int i;
-+ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
-+
-+ /* Update claimed usecs per (micro)frame. */
-+ hcd->periodic_usecs -= qh->usecs;
-+
-+ if (!microframe_schedule) {
-+ /* Release the periodic channel reservation. */
-+ hcd->periodic_channels--;
-+ } else {
-+ for (i = 0; i < 8; i++) {
-+ hcd->frame_usecs[i] += qh->frame_usecs[i];
-+ qh->frame_usecs[i] = 0;
-+ }
-+ }
-+}
-+
-+/**
-+ * Removes a QH from either the non-periodic or periodic schedule. Memory is
-+ * not freed.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param qh QH to remove from schedule. */
-+void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ /* QH is not in a schedule. */
-+ return;
-+ }
-+
-+ if (dwc_qh_is_non_per(qh)) {
-+ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
-+ hcd->non_periodic_qh_ptr =
-+ hcd->non_periodic_qh_ptr->next;
-+ }
-+ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
-+ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
-+ // hcd->fiq_state->kick_np_queues = 1;
-+ } else {
-+ deschedule_periodic(hcd, qh);
-+ hcd->periodic_qh_count--;
-+ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
-+ intr_mask.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+ }
-+ }
-+}
-+
-+/**
-+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
-+ * non-periodic schedule. The QH is added to the inactive non-periodic
-+ * schedule if any QTDs are still attached to the QH.
-+ *
-+ * For periodic QHs, the QH is removed from the periodic queued schedule. If
-+ * there are any QTDs still attached to the QH, the QH is added to either the
-+ * periodic inactive schedule or the periodic ready schedule and its next
-+ * scheduled frame is calculated. The QH is placed in the ready schedule if
-+ * the scheduled frame has been reached already. Otherwise it's placed in the
-+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
-+ * completely removed from the periodic schedule.
-+ */
-+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ int sched_next_periodic_split)
-+{
-+ if (dwc_qh_is_non_per(qh)) {
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ /* Add back to inactive non-periodic schedule. */
-+ dwc_otg_hcd_qh_add(hcd, qh);
-+ //hcd->fiq_state->kick_np_queues = 1;
-+ }
-+ } else {
-+ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
-+
-+ if (qh->do_split) {
-+ /* Schedule the next continuing periodic split transfer */
-+ if (sched_next_periodic_split) {
-+
-+ qh->sched_frame = frame_number;
-+
-+ if (dwc_frame_num_le(frame_number,
-+ dwc_frame_num_inc
-+ (qh->start_split_frame,
-+ 1))) {
-+ /*
-+ * Allow one frame to elapse after start
-+ * split microframe before scheduling
-+ * complete split, but DONT if we are
-+ * doing the next start split in the
-+ * same frame for an ISOC out.
-+ */
-+ if ((qh->ep_type != UE_ISOCHRONOUS) ||
-+ (qh->ep_is_in != 0)) {
-+ qh->sched_frame =
-+ dwc_frame_num_inc(qh->sched_frame, 1);
-+ }
-+ }
-+ } else {
-+ qh->sched_frame =
-+ dwc_frame_num_inc(qh->start_split_frame,
-+ qh->interval);
-+ if (dwc_frame_num_le
-+ (qh->sched_frame, frame_number)) {
-+ qh->sched_frame = frame_number;
-+ }
-+ qh->sched_frame |= 0x7;
-+ qh->start_split_frame = qh->sched_frame;
-+ }
-+ } else {
-+ qh->sched_frame =
-+ dwc_frame_num_inc(qh->sched_frame, qh->interval);
-+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
-+ qh->sched_frame = frame_number;
-+ }
-+ }
-+
-+ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ } else {
-+ /*
-+ * Remove from periodic_sched_queued and move to
-+ * appropriate queue.
-+ */
-+ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
-+ (!microframe_schedule && qh->sched_frame == frame_number)) {
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
-+ &qh->qh_list_entry);
-+ } else {
-+ if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
-+ {
-+ hcd->fiq_state->next_sched_frame = qh->sched_frame;
-+ }
-+
-+ DWC_LIST_MOVE_HEAD
-+ (&hcd->periodic_sched_inactive,
-+ &qh->qh_list_entry);
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * This function allocates and initializes a QTD.
-+ *
-+ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
-+ * pointing to each other so each pair should have a unique correlation.
-+ * @param atomic_alloc Flag to do atomic alloc if needed
-+ *
-+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
-+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
-+{
-+ dwc_otg_qtd_t *qtd;
-+
-+ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
-+ if (qtd == NULL) {
-+ return NULL;
-+ }
-+
-+ dwc_otg_hcd_qtd_init(qtd, urb);
-+ return qtd;
-+}
-+
-+/**
-+ * Initializes a QTD structure.
-+ *
-+ * @param qtd The QTD to initialize.
-+ * @param urb The URB to use for initialization. */
-+void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
-+{
-+ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
-+ qtd->urb = urb;
-+ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
-+ /*
-+ * The only time the QTD data toggle is used is on the data
-+ * phase of control transfers. This phase always starts with
-+ * DATA1.
-+ */
-+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
-+ qtd->control_phase = DWC_OTG_CONTROL_SETUP;
-+ }
-+
-+ /* start split */
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+ qtd->isoc_split_offset = 0;
-+ qtd->in_process = 0;
-+
-+ /* Store the qtd ptr in the urb to reference what QTD. */
-+ urb->qtd = qtd;
-+ return;
-+}
-+
-+/**
-+ * This function adds a QTD to the QTD-list of a QH. It will find the correct
-+ * QH to place the QTD into. If it does not find a QH, then it will create a
-+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
-+ * is placed into the proper schedule based on its EP type.
-+ * HCD lock must be held and interrupts must be disabled on entry
-+ *
-+ * @param[in] qtd The QTD to add
-+ * @param[in] hcd The DWC HCD structure
-+ * @param[out] qh out parameter to return queue head
-+ * @param atomic_alloc Flag to do atomic alloc if needed
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
-+ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
-+{
-+ int retval = 0;
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+ /*
-+ * Get the QH which holds the QTD-list to insert to. Create QH if it
-+ * doesn't exist.
-+ */
-+ if (*qh == NULL) {
-+ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
-+ if (*qh == NULL) {
-+ retval = -DWC_E_NO_MEMORY;
-+ goto done;
-+ } else {
-+ if (fiq_enable)
-+ hcd->fiq_state->kick_np_queues = 1;
-+ }
-+ }
-+ retval = dwc_otg_hcd_qh_add(hcd, *qh);
-+ if (retval == 0) {
-+ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
-+ qtd_list_entry);
-+ qtd->qh = *qh;
-+ }
-+done:
-+
-+ return retval;
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,188 @@
-+#ifndef _DWC_OS_DEP_H_
-+#define _DWC_OS_DEP_H_
-+
-+/**
-+ * @file
-+ *
-+ * This file contains OS dependent structures.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/slab.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/ctype.h>
-+#include <linux/string.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/jiffies.h>
-+#include <linux/delay.h>
-+#include <linux/timer.h>
-+#include <linux/workqueue.h>
-+#include <linux/stat.h>
-+#include <linux/pci.h>
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+# include <linux/irq.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+# include <linux/usb/gadget.h>
-+#else
-+# include <linux/usb_gadget.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+# include <asm/irq.h>
-+#endif
-+
-+#ifdef PCI_INTERFACE
-+# include <asm/io.h>
-+#endif
-+
-+#ifdef LM_INTERFACE
-+# include <asm/unaligned.h>
-+# include <asm/sizes.h>
-+# include <asm/param.h>
-+# include <asm/io.h>
-+# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
-+# include <asm/arch/hardware.h>
-+# include <asm/arch/lm.h>
-+# include <asm/arch/irqs.h>
-+# include <asm/arch/regs-irq.h>
-+# else
-+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
-+ here we assume that the machine architecture provides definitions
-+ in its own header
-+*/
-+# include <mach/lm.h>
-+# include <mach/hardware.h>
-+# endif
-+#endif
-+
-+#ifdef PLATFORM_INTERFACE
-+#include <linux/platform_device.h>
-+#include <asm/mach/map.h>
-+#endif
-+
-+/** The OS page size */
-+#define DWC_OS_PAGE_SIZE PAGE_SIZE
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
-+typedef int gfp_t;
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
-+# define IRQF_SHARED SA_SHIRQ
-+#endif
-+
-+typedef struct os_dependent {
-+ /** Base address returned from ioremap() */
-+ void *base;
-+
-+ /** Register offset for Diagnostic API */
-+ uint32_t reg_offset;
-+
-+ /** Base address for MPHI peripheral */
-+ void *mphi_base;
-+
-+#ifdef LM_INTERFACE
-+ struct lm_device *lmdev;
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *pcidev;
-+
-+ /** Start address of a PCI region */
-+ resource_size_t rsrc_start;
-+
-+ /** Length address of a PCI region */
-+ resource_size_t rsrc_len;
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *platformdev;
-+#endif
-+
-+} os_dependent_t;
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+
-+
-+/* Type for the our device on the chosen bus */
-+#if defined(LM_INTERFACE)
-+typedef struct lm_device dwc_bus_dev_t;
-+#elif defined(PCI_INTERFACE)
-+typedef struct pci_dev dwc_bus_dev_t;
-+#elif defined(PLATFORM_INTERFACE)
-+typedef struct platform_device dwc_bus_dev_t;
-+#endif
-+
-+/* Helper macro to retrieve drvdata from the device on the chosen bus */
-+#if defined(LM_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
-+#endif
-+
-+/**
-+ * Helper macro returning the otg_device structure of a given struct device
-+ *
-+ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+ struct lm_device *lm_dev = \
-+ container_of(_dev, struct lm_device, dev); \
-+ _var = lm_get_drvdata(lm_dev); \
-+ } while (0)
-+
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+ _var = dev_get_drvdata(_dev); \
-+ } while (0)
-+
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+ struct platform_device *platform_dev = \
-+ container_of(_dev, struct platform_device, dev); \
-+ _var = platform_get_drvdata(platform_dev); \
-+ } while (0)
-+#endif
-+
-+
-+/**
-+ * Helper macro returning the struct dev of the given struct os_dependent
-+ *
-+ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
-+#endif
-+
-+
-+
-+
-+#endif /* _DWC_OS_DEP_H_ */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2015-03-10 17:26:51.306216687 +0100
-@@ -0,0 +1,2708 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
-+ * $Revision: #101 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+/** @file
-+ * This file implements PCD Core. All code in this file is portable and doesn't
-+ * use any OS specific functions.
-+ * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
-+ * header file, which can be used to implement OS specific PCD interface.
-+ *
-+ * An important function of the PCD is managing interrupts generated
-+ * by the DWC_otg controller. The implementation of the DWC_otg device
-+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
-+ *
-+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
-+ * @todo Does it work when the request size is greater than DEPTSIZ
-+ * transfer size
-+ *
-+ */
-+
-+#include "dwc_otg_pcd.h"
-+
-+#ifdef DWC_UTE_CFI
-+#include "dwc_otg_cfi.h"
-+
-+extern int init_cfi(cfiobject_t * cfiobj);
-+#endif
-+
-+/**
-+ * Choose endpoint from ep arrays using usb_ep structure.
-+ */
-+static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
-+{
-+ int i;
-+ if (pcd->ep0.priv == handle) {
-+ return &pcd->ep0;
-+ }
-+ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
-+ if (pcd->in_ep[i].priv == handle)
-+ return &pcd->in_ep[i];
-+ if (pcd->out_ep[i].priv == handle)
-+ return &pcd->out_ep[i];
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * This function completes a request. It call's the request call back.
-+ */
-+void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
-+ int32_t status)
-+{
-+ unsigned stopped = ep->stopped;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
-+ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
-+
-+ /* don't modify queue heads during completion callback */
-+ ep->stopped = 1;
-+ /* spin_unlock/spin_lock now done in fops->complete() */
-+ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
-+ req->actual);
-+
-+ if (ep->pcd->request_pending > 0) {
-+ --ep->pcd->request_pending;
-+ }
-+
-+ ep->stopped = stopped;
-+ DWC_FREE(req);
-+}
-+
-+/**
-+ * This function terminates all the requsts in the EP request queue.
-+ */
-+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_pcd_request_t *req;
-+
-+ ep->stopped = 1;
-+
-+ /* called with irqs blocked?? */
-+ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
-+ }
-+}
-+
-+void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
-+ const struct dwc_otg_pcd_function_ops *fops)
-+{
-+ pcd->fops = fops;
-+}
-+
-+/**
-+ * PCD Callback function for initializing the PCD when switching to
-+ * device mode.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_start_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ /*
-+ * Initialized the Core for Device mode.
-+ */
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dwc_otg_core_dev_init(core_if);
-+ /* Set core_if's lock pointer to the pcd->lock */
-+ core_if->lock = pcd->lock;
-+ }
-+ return 1;
-+}
-+
-+/** CFI-specific buffer allocation function for EP */
-+#ifdef DWC_UTE_CFI
-+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
-+ size_t buflen, int flags)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ ep = get_ep_from_handle(pcd, pep);
-+ if (!ep) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
-+ flags);
-+}
-+#else
-+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
-+ size_t buflen, int flags);
-+#endif
-+
-+/**
-+ * PCD Callback function for notifying the PCD when resuming from
-+ * suspend.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_resume_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+
-+ if (pcd->fops->resume) {
-+ pcd->fops->resume(pcd);
-+ }
-+
-+ /* Stop the SRP timeout timer. */
-+ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
-+ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
-+ if (GET_CORE_IF(pcd)->srp_timer_started) {
-+ GET_CORE_IF(pcd)->srp_timer_started = 0;
-+ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
-+ }
-+ }
-+ return 1;
-+}
-+
-+/**
-+ * PCD Callback function for notifying the PCD device is suspended.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_suspend_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+
-+ if (pcd->fops->suspend) {
-+ DWC_SPINUNLOCK(pcd->lock);
-+ pcd->fops->suspend(pcd);
-+ DWC_SPINLOCK(pcd->lock);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * PCD Callback function for stopping the PCD when switching to Host
-+ * mode.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_stop_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
-+
-+ dwc_otg_pcd_stop(pcd);
-+ return 1;
-+}
-+
-+/**
-+ * PCD Callback structure for handling mode switching.
-+ */
-+static dwc_otg_cil_callbacks_t pcd_callbacks = {
-+ .start = dwc_otg_pcd_start_cb,
-+ .stop = dwc_otg_pcd_stop_cb,
-+ .suspend = dwc_otg_pcd_suspend_cb,
-+ .resume_wakeup = dwc_otg_pcd_resume_cb,
-+ .p = 0, /* Set at registration */
-+};
-+
-+/**
-+ * This function allocates a DMA Descriptor chain for the Endpoint
-+ * buffer to be used for a transfer to/from the specified endpoint.
-+ */
-+dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
-+ uint32_t count)
-+{
-+ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
-+ dma_desc_addr);
-+}
-+
-+/**
-+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
-+ */
-+void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
-+ uint32_t dma_desc_addr, uint32_t count)
-+{
-+ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
-+ dma_desc_addr);
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * dwc_ep)
-+{
-+
-+ dsts_data_t dsts = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+ int i, j;
-+ uint32_t len;
-+
-+ if (dwc_ep->is_in)
-+ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
-+ else
-+ dwc_ep->desc_cnt =
-+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+ dwc_ep->bInterval;
-+
-+ /** Allocate descriptors for double buffering */
-+ dwc_ep->iso_desc_addr =
-+ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
-+ dwc_ep->desc_cnt * 2);
-+ if (dwc_ep->desc_addr) {
-+ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
-+ return;
-+ }
-+
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ /** ISO OUT EP */
-+ if (dwc_ep->is_in == 0) {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
-+ dma_addr_t dma_ad;
-+ uint32_t data_per_desc;
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[dwc_ep->num];
-+ int offset;
-+
-+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
-+ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
-+
-+ /** Buffer 0 descriptors setup */
-+ dma_ad = dwc_ep->dma_addr0;
-+
-+ sts.b_iso_out.bs = BS_HOST_READY;
-+ sts.b_iso_out.rxsts = 0;
-+ sts.b_iso_out.l = 0;
-+ sts.b_iso_out.sp = 0;
-+ sts.b_iso_out.ioc = 0;
-+ sts.b_iso_out.pid = 0;
-+ sts.b_iso_out.framenum = 0;
-+
-+ offset = 0;
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+ }
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+ uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+
-+ sts.b_iso_out.ioc = 1;
-+ len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ dma_desc++;
-+
-+ /** Buffer 1 descriptors setup */
-+ sts.b_iso_out.ioc = 0;
-+ dma_ad = dwc_ep->dma_addr1;
-+
-+ offset = 0;
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+
-+ data_per_desc =
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+ }
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+
-+ sts.b_iso_out.ioc = 1;
-+ sts.b_iso_out.l = 1;
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dwc_ep->next_frame = 0;
-+
-+ /** Write dma_ad into DOEPDMA register */
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) dwc_ep->iso_dma_desc_addr);
-+
-+ }
-+ /** ISO IN EP */
-+ else {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
-+ dma_addr_t dma_ad;
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[dwc_ep->num];
-+ unsigned int frmnumber;
-+ fifosize_data_t txfifosize, rxfifosize;
-+
-+ txfifosize.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
-+ dtxfsts);
-+ rxfifosize.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+
-+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+
-+ dma_ad = dwc_ep->dma_addr0;
-+
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ sts.b_iso_in.bs = BS_HOST_READY;
-+ sts.b_iso_in.txsts = 0;
-+ sts.b_iso_in.sp =
-+ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
-+ sts.b_iso_in.ioc = 0;
-+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
-+
-+ frmnumber = dwc_ep->next_frame;
-+
-+ sts.b_iso_in.framenum = frmnumber;
-+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
-+ sts.b_iso_in.l = 0;
-+
-+ /** Buffer 0 descriptors setup */
-+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ dma_desc++;
-+
-+ dma_ad += dwc_ep->data_per_frame;
-+ sts.b_iso_in.framenum += dwc_ep->bInterval;
-+ }
-+
-+ sts.b_iso_in.ioc = 1;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ ++dma_desc;
-+
-+ /** Buffer 1 descriptors setup */
-+ sts.b_iso_in.ioc = 0;
-+ dma_ad = dwc_ep->dma_addr1;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ dma_desc++;
-+
-+ dma_ad += dwc_ep->data_per_frame;
-+ sts.b_iso_in.framenum += dwc_ep->bInterval;
-+
-+ sts.b_iso_in.ioc = 0;
-+ }
-+ sts.b_iso_in.ioc = 1;
-+ sts.b_iso_in.l = 1;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
-+
-+ /** Write dma_ad into diepdma register */
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) dwc_ep->iso_dma_desc_addr);
-+ }
-+ /** Enable endpoint, clear nak */
-+ depctl.d32 = 0;
-+ depctl.b.epena = 1;
-+ depctl.b.usbactep = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+ depctl.d32 = DWC_READ_REG32(addr);
-+}
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if (ep->is_in) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
-+ return;
-+ } else {
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+
-+ ep->xfer_len =
-+ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
-+ ep->pkt_cnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+ ep->xfer_count = 0;
-+ ep->xfer_buff =
-+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
-+ ep->dma_addr =
-+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
-+
-+ if (ep->is_in) {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.mc = ep->pkt_per_frm;
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ dieptsiz, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->in_ep_regs[ep->num]->
-+ diepdma), (uint32_t) ep->dma_addr);
-+
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len + (ep->maxpacket - 1)) /
-+ ep->maxpacket;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
-+ doeptsiz, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->out_ep_regs[ep->num]->
-+ doepdma), (uint32_t) ep->dma_addr);
-+
-+ }
-+ /** Enable endpoint, clear nak */
-+ depctl.d32 = 0;
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ if (ep->is_in) {
-+ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
-+ } else {
-+ ep->desc_cnt = ep->pkt_cnt;
-+ }
-+ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
-+ } else {
-+ if (core_if->pti_enh_enable) {
-+ dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
-+ } else {
-+ ep->cur_pkt_addr =
-+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
-+ xfer_buff0;
-+ ep->cur_pkt_dma_addr =
-+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->
-+ dma_addr0;
-+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
-+ }
-+ }
-+ } else {
-+ ep->cur_pkt_addr =
-+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
-+ ep->cur_pkt_dma_addr =
-+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
-+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
-+ }
-+}
-+
-+/**
-+ * This function stops transfer for an EP and
-+ * resets the ep's variables.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if (ep->is_in == 1) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ /* disable the ep */
-+ depctl.d32 = DWC_READ_REG32(addr);
-+
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+
-+ DWC_WRITE_REG32(addr, depctl.d32);
-+
-+ if (core_if->dma_desc_enable &&
-+ ep->iso_desc_addr && ep->iso_dma_desc_addr) {
-+ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
-+ ep->iso_dma_desc_addr,
-+ ep->desc_cnt * 2);
-+ }
-+
-+ /* reset varibales */
-+ ep->dma_addr0 = 0;
-+ ep->dma_addr1 = 0;
-+ ep->xfer_buff0 = 0;
-+ ep->xfer_buff1 = 0;
-+ ep->data_per_frame = 0;
-+ ep->data_pattern_frame = 0;
-+ ep->sync_frame = 0;
-+ ep->buf_proc_intrvl = 0;
-+ ep->bInterval = 0;
-+ ep->proc_buf_num = 0;
-+ ep->pkt_per_frm = 0;
-+ ep->pkt_per_frm = 0;
-+ ep->desc_cnt = 0;
-+ ep->iso_desc_addr = 0;
-+ ep->iso_dma_desc_addr = 0;
-+}
-+
-+int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
-+ dwc_dma_t dma1, int sync_frame, int dp_frame,
-+ int data_per_frame, int start_frame,
-+ int buf_proc_intrvl, void *req_handle,
-+ int atomic_alloc)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags = 0;
-+ dwc_ep_t *dwc_ep;
-+ int32_t frm_data;
-+ dsts_data_t dsts;
-+ dwc_otg_core_if_t *core_if;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ core_if = GET_CORE_IF(pcd);
-+ dwc_ep = &ep->dwc_ep;
-+
-+ if (ep->iso_req_handle) {
-+ DWC_WARN("ISO request in progress\n");
-+ }
-+
-+ dwc_ep->dma_addr0 = dma0;
-+ dwc_ep->dma_addr1 = dma1;
-+
-+ dwc_ep->xfer_buff0 = buf0;
-+ dwc_ep->xfer_buff1 = buf1;
-+
-+ dwc_ep->data_per_frame = data_per_frame;
-+
-+ /** @todo - pattern data support is to be implemented in the future */
-+ dwc_ep->data_pattern_frame = dp_frame;
-+ dwc_ep->sync_frame = sync_frame;
-+
-+ dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
-+
-+ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
-+
-+ dwc_ep->proc_buf_num = 0;
-+
-+ dwc_ep->pkt_per_frm = 0;
-+ frm_data = ep->dwc_ep.data_per_frame;
-+ while (frm_data > 0) {
-+ dwc_ep->pkt_per_frm++;
-+ frm_data -= ep->dwc_ep.maxpacket;
-+ }
-+
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ if (start_frame == -1) {
-+ dwc_ep->next_frame = dsts.b.soffn + 1;
-+ if (dwc_ep->bInterval != 1) {
-+ dwc_ep->next_frame =
-+ dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
-+ dwc_ep->next_frame %
-+ dwc_ep->bInterval);
-+ }
-+ } else {
-+ dwc_ep->next_frame = start_frame;
-+ }
-+
-+ if (!core_if->pti_enh_enable) {
-+ dwc_ep->pkt_cnt =
-+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+ dwc_ep->bInterval;
-+ } else {
-+ dwc_ep->pkt_cnt =
-+ (dwc_ep->data_per_frame *
-+ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
-+ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
-+ }
-+
-+ if (core_if->dma_desc_enable) {
-+ dwc_ep->desc_cnt =
-+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+ dwc_ep->bInterval;
-+ }
-+
-+ if (atomic_alloc) {
-+ dwc_ep->pkt_info =
-+ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+ } else {
-+ dwc_ep->pkt_info =
-+ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+ }
-+ if (!dwc_ep->pkt_info) {
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ if (core_if->pti_enh_enable) {
-+ dwc_memset(dwc_ep->pkt_info, 0,
-+ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+ }
-+
-+ dwc_ep->cur_pkt = 0;
-+ ep->iso_req_handle = req_handle;
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
-+ return 0;
-+}
-+
-+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle)
-+{
-+ dwc_irqflags_t flags = 0;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+ dwc_ep = &ep->dwc_ep;
-+
-+ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
-+
-+ DWC_FREE(dwc_ep->pkt_info);
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ if (ep->iso_req_handle != req_handle) {
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ ep->iso_req_handle = 0;
-+ return 0;
-+}
-+
-+/**
-+ * This function is used for perodical data exchnage between PCD and gadget drivers.
-+ * for Isochronous EPs
-+ *
-+ * - Every time a sync period completes this function is called to
-+ * perform data exchange between PCD and gadget
-+ */
-+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
-+ void *req_handle)
-+{
-+ int i;
-+ dwc_ep_t *dwc_ep;
-+
-+ dwc_ep = &ep->dwc_ep;
-+
-+ DWC_SPINUNLOCK(ep->pcd->lock);
-+ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
-+ dwc_ep->proc_buf_num ^ 0x1);
-+ DWC_SPINLOCK(ep->pcd->lock);
-+
-+ for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
-+ dwc_ep->pkt_info[i].status = 0;
-+ dwc_ep->pkt_info[i].offset = 0;
-+ dwc_ep->pkt_info[i].length = 0;
-+ }
-+}
-+
-+int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *iso_req_handle)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep->desc || ep->dwc_ep.num == 0) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+ dwc_ep = &ep->dwc_ep;
-+
-+ return dwc_ep->pkt_cnt;
-+}
-+
-+void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *iso_req_handle, int packet,
-+ int *status, int *actual, int *offset)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep)
-+ DWC_WARN("bad ep\n");
-+
-+ dwc_ep = &ep->dwc_ep;
-+
-+ *status = dwc_ep->pkt_info[packet].status;
-+ *actual = dwc_ep->pkt_info[packet].length;
-+ *offset = dwc_ep->pkt_info[packet].offset;
-+}
-+
-+#endif /* DWC_EN_ISOC */
-+
-+static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
-+ uint32_t is_in, uint32_t ep_num)
-+{
-+ /* Init EP structure */
-+ pcd_ep->desc = 0;
-+ pcd_ep->pcd = pcd;
-+ pcd_ep->stopped = 1;
-+ pcd_ep->queue_sof = 0;
-+
-+ /* Init DWC ep structure */
-+ pcd_ep->dwc_ep.is_in = is_in;
-+ pcd_ep->dwc_ep.num = ep_num;
-+ pcd_ep->dwc_ep.active = 0;
-+ pcd_ep->dwc_ep.tx_fifo_num = 0;
-+ /* Control until ep is actvated */
-+ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
-+ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
-+ pcd_ep->dwc_ep.dma_addr = 0;
-+ pcd_ep->dwc_ep.start_xfer_buff = 0;
-+ pcd_ep->dwc_ep.xfer_buff = 0;
-+ pcd_ep->dwc_ep.xfer_len = 0;
-+ pcd_ep->dwc_ep.xfer_count = 0;
-+ pcd_ep->dwc_ep.sent_zlp = 0;
-+ pcd_ep->dwc_ep.total_len = 0;
-+ pcd_ep->dwc_ep.desc_addr = 0;
-+ pcd_ep->dwc_ep.dma_desc_addr = 0;
-+ DWC_CIRCLEQ_INIT(&pcd_ep->queue);
-+}
-+
-+/**
-+ * Initialize ep's
-+ */
-+static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
-+{
-+ int i;
-+ uint32_t hwcfg1;
-+ dwc_otg_pcd_ep_t *ep;
-+ int in_ep_cntr, out_ep_cntr;
-+ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
-+ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
-+
-+ /**
-+ * Initialize the EP0 structure.
-+ */
-+ ep = &pcd->ep0;
-+ dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
-+
-+ in_ep_cntr = 0;
-+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
-+ for (i = 1; in_ep_cntr < num_in_eps; i++) {
-+ if ((hwcfg1 & 0x1) == 0) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
-+ in_ep_cntr++;
-+ /**
-+ * @todo NGS: Add direction to EP, based on contents
-+ * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
-+ * sprintf(";r
-+ */
-+ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
-+
-+ DWC_CIRCLEQ_INIT(&ep->queue);
-+ }
-+ hwcfg1 >>= 2;
-+ }
-+
-+ out_ep_cntr = 0;
-+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
-+ for (i = 1; out_ep_cntr < num_out_eps; i++) {
-+ if ((hwcfg1 & 0x1) == 0) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
-+ out_ep_cntr++;
-+ /**
-+ * @todo NGS: Add direction to EP, based on contents
-+ * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
-+ * sprintf(";r
-+ */
-+ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
-+ DWC_CIRCLEQ_INIT(&ep->queue);
-+ }
-+ hwcfg1 >>= 2;
-+ }
-+
-+ pcd->ep0state = EP0_DISCONNECT;
-+ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
-+ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
-+}
-+
-+/**
-+ * This function is called when the SRP timer expires. The SRP should
-+ * complete within 6 seconds.
-+ */
-+static void srp_timeout(void *ptr)
-+{
-+ gotgctl_data_t gotgctl;
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
-+
-+ gotgctl.d32 = DWC_READ_REG32(addr);
-+
-+ core_if->srp_timer_started = 0;
-+
-+ if (core_if->adp_enable) {
-+ if (gotgctl.b.bsesvld == 0) {
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+ }
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+ dwc_otg_adp_probe_start(core_if);
-+ } else {
-+ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ }
-+ }
-+
-+ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
-+ (core_if->core_params->i2c_enable)) {
-+ DWC_PRINTF("SRP Timeout\n");
-+
-+ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+
-+ /* Clear Session Request */
-+ gotgctl.d32 = 0;
-+ gotgctl.b.sesreq = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+
-+ core_if->srp_success = 0;
-+ } else {
-+ __DWC_ERROR("Device not connected/responding\n");
-+ gotgctl.b.sesreq = 0;
-+ DWC_WRITE_REG32(addr, gotgctl.d32);
-+ }
-+ } else if (gotgctl.b.sesreq) {
-+ DWC_PRINTF("SRP Timeout\n");
-+
-+ __DWC_ERROR("Device not connected/responding\n");
-+ gotgctl.b.sesreq = 0;
-+ DWC_WRITE_REG32(addr, gotgctl.d32);
-+ } else {
-+ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
-+ }
-+}
-+
-+/**
-+ * Tasklet
-+ *
-+ */
-+extern void start_next_request(dwc_otg_pcd_ep_t * ep);
-+
-+static void start_xfer_tasklet_func(void *data)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ int i;
-+ depctl_data_t diepctl;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
-+
-+ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
-+
-+ if (pcd->ep0.queue_sof) {
-+ pcd->ep0.queue_sof = 0;
-+ start_next_request(&pcd->ep0);
-+ // break;
-+ }
-+
-+ for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
-+ depctl_data_t diepctl;
-+ diepctl.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
-+
-+ if (pcd->in_ep[i].queue_sof) {
-+ pcd->in_ep[i].queue_sof = 0;
-+ start_next_request(&pcd->in_ep[i]);
-+ // break;
-+ }
-+ }
-+
-+ return;
-+}
-+
-+/**
-+ * This function initialized the PCD portion of the driver.
-+ *
-+ */
-+dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_pcd_t *pcd = NULL;
-+ dwc_otg_dev_if_t *dev_if;
-+ int i;
-+
-+ /*
-+ * Allocate PCD structure
-+ */
-+ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
-+
-+ if (pcd == NULL) {
-+ return NULL;
-+ }
-+
-+ pcd->lock = DWC_SPINLOCK_ALLOC();
-+ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
-+ pcd, core_if);//GRAYG
-+ if (!pcd->lock) {
-+ DWC_ERROR("Could not allocate lock for pcd");
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+ /* Set core_if's lock pointer to hcd->lock */
-+ core_if->lock = pcd->lock;
-+ pcd->core_if = core_if;
-+
-+ dev_if = core_if->dev_if;
-+ dev_if->isoc_ep = NULL;
-+
-+ if (core_if->hwcfg4.b.ded_fifo_en) {
-+ DWC_PRINTF("Dedicated Tx FIFOs mode\n");
-+ } else {
-+ DWC_PRINTF("Shared Tx FIFO mode\n");
-+ }
-+
-+ /*
-+ * Initialized the Core for Device mode here if there is nod ADP support.
-+ * Otherwise it will be done later in dwc_otg_adp_start routine.
-+ */
-+ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
-+ dwc_otg_core_dev_init(core_if);
-+ }
-+
-+ /*
-+ * Register the PCD Callbacks.
-+ */
-+ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
-+
-+ /*
-+ * Initialize the DMA buffer for SETUP packets
-+ */
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ pcd->setup_pkt =
-+ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
-+ &pcd->setup_pkt_dma_handle);
-+ if (pcd->setup_pkt == NULL) {
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+
-+ pcd->status_buf =
-+ DWC_DMA_ALLOC(sizeof(uint16_t),
-+ &pcd->status_buf_dma_handle);
-+ if (pcd->status_buf == NULL) {
-+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
-+ pcd->setup_pkt, pcd->setup_pkt_dma_handle);
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dev_if->setup_desc_addr[0] =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_setup_desc_addr[0], 1);
-+ dev_if->setup_desc_addr[1] =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_setup_desc_addr[1], 1);
-+ dev_if->in_desc_addr =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_in_desc_addr, 1);
-+ dev_if->out_desc_addr =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_out_desc_addr, 1);
-+ pcd->data_terminated = 0;
-+
-+ if (dev_if->setup_desc_addr[0] == 0
-+ || dev_if->setup_desc_addr[1] == 0
-+ || dev_if->in_desc_addr == 0
-+ || dev_if->out_desc_addr == 0) {
-+
-+ if (dev_if->out_desc_addr)
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->out_desc_addr,
-+ dev_if->dma_out_desc_addr, 1);
-+ if (dev_if->in_desc_addr)
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->in_desc_addr,
-+ dev_if->dma_in_desc_addr, 1);
-+ if (dev_if->setup_desc_addr[1])
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->setup_desc_addr[1],
-+ dev_if->dma_setup_desc_addr[1], 1);
-+ if (dev_if->setup_desc_addr[0])
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->setup_desc_addr[0],
-+ dev_if->dma_setup_desc_addr[0], 1);
-+
-+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
-+ pcd->setup_pkt,
-+ pcd->setup_pkt_dma_handle);
-+ DWC_DMA_FREE(sizeof(*pcd->status_buf),
-+ pcd->status_buf,
-+ pcd->status_buf_dma_handle);
-+
-+ DWC_FREE(pcd);
-+
-+ return NULL;
-+ }
-+ }
-+ } else {
-+ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
-+ if (pcd->setup_pkt == NULL) {
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+
-+ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
-+ if (pcd->status_buf == NULL) {
-+ DWC_FREE(pcd->setup_pkt);
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+ }
-+
-+ dwc_otg_pcd_reinit(pcd);
-+
-+ /* Allocate the cfi object for the PCD */
-+#ifdef DWC_UTE_CFI
-+ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
-+ if (NULL == pcd->cfi)
-+ goto fail;
-+ if (init_cfi(pcd->cfi)) {
-+ CFI_INFO("%s: Failed to init the CFI object\n", __func__);
-+ goto fail;
-+ }
-+#endif
-+
-+ /* Initialize tasklets */
-+ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
-+ start_xfer_tasklet_func, pcd);
-+ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
-+ do_test_mode, pcd);
-+
-+ /* Initialize SRP timer */
-+ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
-+
-+ if (core_if->core_params->dev_out_nak) {
-+ /**
-+ * Initialize xfer timeout timer. Implemented for
-+ * 2.93a feature "Device DDMA OUT NAK Enhancement"
-+ */
-+ for(i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ pcd->core_if->ep_xfer_timer[i] =
-+ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
-+ &pcd->core_if->ep_xfer_info[i]);
-+ }
-+ }
-+
-+ return pcd;
-+#ifdef DWC_UTE_CFI
-+fail:
-+#endif
-+ if (pcd->setup_pkt)
-+ DWC_FREE(pcd->setup_pkt);
-+ if (pcd->status_buf)
-+ DWC_FREE(pcd->status_buf);
-+#ifdef DWC_UTE_CFI
-+ if (pcd->cfi)
-+ DWC_FREE(pcd->cfi);
-+#endif
-+ if (pcd)
-+ DWC_FREE(pcd);
-+ return NULL;
-+
-+}
-+
-+/**
-+ * Remove PCD specific data
-+ */
-+void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ int i;
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
-+ pcd->core_if->ep_xfer_info[i].state = 0;
-+ }
-+ }
-+
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
-+ pcd->setup_pkt_dma_handle);
-+ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
-+ pcd->status_buf_dma_handle);
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
-+ dev_if->dma_setup_desc_addr
-+ [0], 1);
-+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
-+ dev_if->dma_setup_desc_addr
-+ [1], 1);
-+ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
-+ dev_if->dma_in_desc_addr, 1);
-+ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
-+ dev_if->dma_out_desc_addr,
-+ 1);
-+ }
-+ } else {
-+ DWC_FREE(pcd->setup_pkt);
-+ DWC_FREE(pcd->status_buf);
-+ }
-+ DWC_SPINLOCK_FREE(pcd->lock);
-+ /* Set core_if's lock pointer to NULL */
-+ pcd->core_if->lock = NULL;
-+
-+ DWC_TASK_FREE(pcd->start_xfer_tasklet);
-+ DWC_TASK_FREE(pcd->test_mode_tasklet);
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ if (pcd->core_if->ep_xfer_timer[i]) {
-+ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
-+ }
-+ }
-+ }
-+
-+/* Release the CFI object's dynamic memory */
-+#ifdef DWC_UTE_CFI
-+ if (pcd->cfi->ops.release) {
-+ pcd->cfi->ops.release(pcd->cfi);
-+ }
-+#endif
-+
-+ DWC_FREE(pcd);
-+}
-+
-+/**
-+ * Returns whether registered pcd is dual speed or not
-+ */
-+uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
-+ ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls))) {
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Returns whether registered pcd is OTG capable or not
-+ */
-+uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ gusbcfg_data_t usbcfg = {.d32 = 0 };
-+
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function assigns periodic Tx FIFO to an periodic EP
-+ * in shared Tx FIFO mode
-+ */
-+static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t TxMsk = 1;
-+ int i;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
-+ if ((TxMsk & core_if->tx_msk) == 0) {
-+ core_if->tx_msk |= TxMsk;
-+ return i + 1;
-+ }
-+ TxMsk <<= 1;
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * This function assigns periodic Tx FIFO to an periodic EP
-+ * in shared Tx FIFO mode
-+ */
-+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t PerTxMsk = 1;
-+ int i;
-+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
-+ if ((PerTxMsk & core_if->p_tx_msk) == 0) {
-+ core_if->p_tx_msk |= PerTxMsk;
-+ return i + 1;
-+ }
-+ PerTxMsk <<= 1;
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * This function releases periodic Tx FIFO
-+ * in shared Tx FIFO mode
-+ */
-+static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
-+ uint32_t fifo_num)
-+{
-+ core_if->p_tx_msk =
-+ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
-+}
-+
-+/**
-+ * This function releases periodic Tx FIFO
-+ * in shared Tx FIFO mode
-+ */
-+static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
-+{
-+ core_if->tx_msk =
-+ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
-+}
-+
-+/**
-+ * This function is being called from gadget
-+ * to enable PCD endpoint.
-+ */
-+int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
-+ const uint8_t * ep_desc, void *usb_ep)
-+{
-+ int num, dir;
-+ dwc_otg_pcd_ep_t *ep = NULL;
-+ const usb_endpoint_descriptor_t *desc;
-+ dwc_irqflags_t flags;
-+ fifosize_data_t dptxfsiz = {.d32 = 0 };
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
-+ int retval = 0;
-+ int i, epcount;
-+
-+ desc = (const usb_endpoint_descriptor_t *)ep_desc;
-+
-+ if (!desc) {
-+ pcd->ep0.priv = usb_ep;
-+ ep = &pcd->ep0;
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ num = UE_GET_ADDR(desc->bEndpointAddress);
-+ dir = UE_GET_DIR(desc->bEndpointAddress);
-+
-+ if (!desc->wMaxPacketSize) {
-+ DWC_WARN("bad maxpacketsize\n");
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ if (dir == UE_DIR_IN) {
-+ epcount = pcd->core_if->dev_if->num_in_eps;
-+ for (i = 0; i < epcount; i++) {
-+ if (num == pcd->in_ep[i].dwc_ep.num) {
-+ ep = &pcd->in_ep[i];
-+ break;
-+ }
-+ }
-+ } else {
-+ epcount = pcd->core_if->dev_if->num_out_eps;
-+ for (i = 0; i < epcount; i++) {
-+ if (num == pcd->out_ep[i].dwc_ep.num) {
-+ ep = &pcd->out_ep[i];
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (!ep) {
-+ DWC_WARN("bad address\n");
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ ep->desc = desc;
-+ ep->priv = usb_ep;
-+
-+ /*
-+ * Activate the EP
-+ */
-+ ep->stopped = 0;
-+
-+ ep->dwc_ep.is_in = (dir == UE_DIR_IN);
-+ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
-+
-+ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
-+
-+ if (ep->dwc_ep.is_in) {
-+ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ ep->dwc_ep.tx_fifo_num = 0;
-+
-+ if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
-+ /*
-+ * if ISOC EP then assign a Periodic Tx FIFO.
-+ */
-+ ep->dwc_ep.tx_fifo_num =
-+ assign_perio_tx_fifo(GET_CORE_IF(pcd));
-+ }
-+ } else {
-+ /*
-+ * if Dedicated FIFOs mode is on then assign a Tx FIFO.
-+ */
-+ ep->dwc_ep.tx_fifo_num =
-+ assign_tx_fifo(GET_CORE_IF(pcd));
-+ }
-+
-+ /* Calculating EP info controller base address */
-+ if (ep->dwc_ep.tx_fifo_num
-+ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ gdfifocfg.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+ core_global_regs->gdfifocfg);
-+ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
-+ dptxfsiz.d32 =
-+ (DWC_READ_REG32
-+ (&GET_CORE_IF(pcd)->core_global_regs->
-+ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
-+ gdfifocfg.b.epinfobase =
-+ gdfifocfgbase.d32 + dptxfsiz.d32;
-+ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
-+ core_global_regs->gdfifocfg,
-+ gdfifocfg.d32);
-+ }
-+ }
-+ }
-+ /* Set initial data PID. */
-+ if (ep->dwc_ep.type == UE_BULK) {
-+ ep->dwc_ep.data_pid_start = 0;
-+ }
-+
-+ /* Alloc DMA Descriptors */
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+#ifndef DWC_UTE_PER_IO
-+ if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
-+#endif
-+ ep->dwc_ep.desc_addr =
-+ dwc_otg_ep_alloc_desc_chain(&ep->
-+ dwc_ep.dma_desc_addr,
-+ MAX_DMA_DESC_CNT);
-+ if (!ep->dwc_ep.desc_addr) {
-+ DWC_WARN("%s, can't allocate DMA descriptor\n",
-+ __func__);
-+ retval = -DWC_E_SHUTDOWN;
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ goto out;
-+ }
-+#ifndef DWC_UTE_PER_IO
-+ }
-+#endif
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
-+#ifdef DWC_UTE_PER_IO
-+ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
-+#endif
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
-+ ep->dwc_ep.frame_num = 0xFFFFFFFF;
-+ }
-+
-+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+
-+#ifdef DWC_UTE_CFI
-+ if (pcd->cfi->ops.ep_enable) {
-+ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
-+ }
-+#endif
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+out:
-+ return retval;
-+}
-+
-+/**
-+ * This function is being called from gadget
-+ * to disable PCD endpoint.
-+ */
-+int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ dwc_otg_dev_dma_desc_t *desc_addr;
-+ dwc_dma_t dma_desc_addr;
-+ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ fifosize_data_t dptxfsiz = {.d32 = 0 };
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if (!ep || !ep->desc) {
-+ DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ dwc_otg_request_nuke(ep);
-+
-+ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
-+ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
-+ }
-+ ep->desc = NULL;
-+ ep->stopped = 1;
-+
-+ gdfifocfg.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
-+ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
-+
-+ if (ep->dwc_ep.is_in) {
-+ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ /* Flush the Tx FIFO */
-+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
-+ ep->dwc_ep.tx_fifo_num);
-+ }
-+ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
-+ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
-+ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ /* Decreasing EPinfo Base Addr */
-+ dptxfsiz.d32 =
-+ (DWC_READ_REG32
-+ (&GET_CORE_IF(pcd)->
-+ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
-+ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
-+ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
-+ gdfifocfg.d32);
-+ }
-+ }
-+ }
-+
-+ /* Free DMA Descriptors */
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
-+ desc_addr = ep->dwc_ep.desc_addr;
-+ dma_desc_addr = ep->dwc_ep.dma_desc_addr;
-+
-+ /* Cannot call dma_free_coherent() with IRQs disabled */
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
-+ MAX_DMA_DESC_CNT);
-+
-+ goto out_unlocked;
-+ }
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+out_unlocked:
-+ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT");
-+ return 0;
-+
-+}
-+
-+/******************************************************************************/
-+#ifdef DWC_UTE_PER_IO
-+
-+/**
-+ * Free the request and its extended parts
-+ *
-+ */
-+void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
-+{
-+ DWC_FREE(req->ext_req.per_io_frame_descs);
-+ DWC_FREE(req);
-+}
-+
-+/**
-+ * Start the next request in the endpoint's queue.
-+ *
-+ */
-+int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
-+ dwc_otg_pcd_ep_t * ep)
-+{
-+ int i;
-+ dwc_otg_pcd_request_t *req = NULL;
-+ dwc_ep_t *dwcep = NULL;
-+ struct dwc_iso_xreq_port *ereq = NULL;
-+ struct dwc_iso_pkt_desc_port *ddesc_iso;
-+ uint16_t nat;
-+ depctl_data_t diepctl;
-+
-+ dwcep = &ep->dwc_ep;
-+
-+ if (dwcep->xiso_active_xfers > 0) {
-+#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers
-+ DWC_WARN("There are currently active transfers for EP%d \
-+ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
-+ dwcep->xiso_queued_xfers);
-+#endif
-+ return 0;
-+ }
-+
-+ nat = UGETW(ep->desc->wMaxPacketSize);
-+ nat = (nat >> 11) & 0x03;
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ ereq = &req->ext_req;
-+ ep->stopped = 0;
-+
-+ /* Get the frame number */
-+ dwcep->xiso_frame_num =
-+ dwc_otg_get_frame_number(GET_CORE_IF(pcd));
-+ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
-+
-+ ddesc_iso = ereq->per_io_frame_descs;
-+
-+ if (dwcep->is_in) {
-+ /* Setup DMA Descriptor chain for IN Isoc request */
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ //if ((i % (nat + 1)) == 0)
-+ if ( i > 0 )
-+ dwcep->xiso_frame_num =
-+ (dwcep->xiso_bInterval +
-+ dwcep->xiso_frame_num) & 0x3FFF;
-+ dwcep->desc_addr[i].buf =
-+ req->dma + ddesc_iso[i].offset;
-+ dwcep->desc_addr[i].status.b_iso_in.txbytes =
-+ ddesc_iso[i].length;
-+ dwcep->desc_addr[i].status.b_iso_in.framenum =
-+ dwcep->xiso_frame_num;
-+ dwcep->desc_addr[i].status.b_iso_in.bs =
-+ BS_HOST_READY;
-+ dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
-+ dwcep->desc_addr[i].status.b_iso_in.sp =
-+ (ddesc_iso[i].length %
-+ dwcep->maxpacket) ? 1 : 0;
-+ dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
-+ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
-+ dwcep->desc_addr[i].status.b_iso_in.l = 0;
-+
-+ /* Process the last descriptor */
-+ if (i == ereq->pio_pkt_count - 1) {
-+ dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
-+ dwcep->desc_addr[i].status.b_iso_in.l = 1;
-+ }
-+ }
-+
-+ /* Setup and start the transfer for this endpoint */
-+ dwcep->xiso_active_xfers++;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ in_ep_regs[dwcep->num]->diepdma,
-+ dwcep->dma_desc_addr);
-+ diepctl.d32 = 0;
-+ diepctl.b.epena = 1;
-+ diepctl.b.cnak = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ in_ep_regs[dwcep->num]->diepctl, 0,
-+ diepctl.d32);
-+ } else {
-+ /* Setup DMA Descriptor chain for OUT Isoc request */
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ //if ((i % (nat + 1)) == 0)
-+ dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
-+ dwcep->xiso_frame_num) & 0x3FFF;
-+ dwcep->desc_addr[i].buf =
-+ req->dma + ddesc_iso[i].offset;
-+ dwcep->desc_addr[i].status.b_iso_out.rxbytes =
-+ ddesc_iso[i].length;
-+ dwcep->desc_addr[i].status.b_iso_out.framenum =
-+ dwcep->xiso_frame_num;
-+ dwcep->desc_addr[i].status.b_iso_out.bs =
-+ BS_HOST_READY;
-+ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
-+ dwcep->desc_addr[i].status.b_iso_out.sp =
-+ (ddesc_iso[i].length %
-+ dwcep->maxpacket) ? 1 : 0;
-+ dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
-+ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
-+ dwcep->desc_addr[i].status.b_iso_out.l = 0;
-+
-+ /* Process the last descriptor */
-+ if (i == ereq->pio_pkt_count - 1) {
-+ dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
-+ dwcep->desc_addr[i].status.b_iso_out.l = 1;
-+ }
-+ }
-+
-+ /* Setup and start the transfer for this endpoint */
-+ dwcep->xiso_active_xfers++;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->out_ep_regs[dwcep->num]->
-+ doepdma, dwcep->dma_desc_addr);
-+ diepctl.d32 = 0;
-+ diepctl.b.epena = 1;
-+ diepctl.b.cnak = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->out_ep_regs[dwcep->num]->
-+ doepctl, 0, diepctl.d32);
-+ }
-+
-+ } else {
-+ ep->stopped = 1;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * - Remove the request from the queue
-+ */
-+void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_pcd_request_t *req = NULL;
-+ struct dwc_iso_xreq_port *ereq = NULL;
-+ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
-+ dwc_ep_t *dwcep = NULL;
-+ int i;
-+
-+ //DWC_DEBUG();
-+ dwcep = &ep->dwc_ep;
-+
-+ /* Get the first pending request from the queue */
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (!req) {
-+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+ return;
-+ }
-+ dwcep->xiso_active_xfers--;
-+ dwcep->xiso_queued_xfers--;
-+ /* Remove this request from the queue */
-+ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
-+ } else {
-+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+ return;
-+ }
-+
-+ ep->stopped = 1;
-+ ereq = &req->ext_req;
-+ ddesc_iso = ereq->per_io_frame_descs;
-+
-+ if (dwcep->xiso_active_xfers < 0) {
-+ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
-+ dwcep->xiso_active_xfers);
-+ }
-+
-+ /* Fill the Isoc descs of portable extended req from dma descriptors */
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ if (dwcep->is_in) { /* IN endpoints */
-+ ddesc_iso[i].actual_length = ddesc_iso[i].length -
-+ dwcep->desc_addr[i].status.b_iso_in.txbytes;
-+ ddesc_iso[i].status =
-+ dwcep->desc_addr[i].status.b_iso_in.txsts;
-+ } else { /* OUT endpoints */
-+ ddesc_iso[i].actual_length = ddesc_iso[i].length -
-+ dwcep->desc_addr[i].status.b_iso_out.rxbytes;
-+ ddesc_iso[i].status =
-+ dwcep->desc_addr[i].status.b_iso_out.rxsts;
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK(ep->pcd->lock);
-+
-+ /* Call the completion function in the non-portable logic */
-+ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
-+ &req->ext_req);
-+
-+ DWC_SPINLOCK(ep->pcd->lock);
-+
-+ /* Free the request - specific freeing needed for extended request object */
-+ dwc_pcd_xiso_ereq_free(ep, req);
-+
-+ /* Start the next request */
-+ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
-+
-+ return;
-+}
-+
-+/**
-+ * Create and initialize the Isoc pkt descriptors of the extended request.
-+ *
-+ */
-+static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
-+ void *ereq_nonport,
-+ int atomic_alloc)
-+{
-+ struct dwc_iso_xreq_port *ereq = NULL;
-+ struct dwc_iso_xreq_port *req_mapped = NULL;
-+ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */
-+ uint32_t pkt_count;
-+ int i;
-+
-+ ereq = &req->ext_req;
-+ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
-+ pkt_count = req_mapped->pio_pkt_count;
-+
-+ /* Create the isoc descs */
-+ if (atomic_alloc) {
-+ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
-+ } else {
-+ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
-+ }
-+
-+ if (!ipds) {
-+ DWC_ERROR("Failed to allocate isoc descriptors");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Initialize the extended request fields */
-+ ereq->per_io_frame_descs = ipds;
-+ ereq->error_count = 0;
-+ ereq->pio_alloc_pkt_count = pkt_count;
-+ ereq->pio_pkt_count = pkt_count;
-+ ereq->tr_sub_flags = req_mapped->tr_sub_flags;
-+
-+ /* Init the Isoc descriptors */
-+ for (i = 0; i < pkt_count; i++) {
-+ ipds[i].length = req_mapped->per_io_frame_descs[i].length;
-+ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
-+ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */
-+ ipds[i].actual_length =
-+ req_mapped->per_io_frame_descs[i].actual_length;
-+ }
-+
-+ return 0;
-+}
-+
-+static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
-+{
-+ struct dwc_iso_pkt_desc_port *xfd = NULL;
-+ int i;
-+
-+ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
-+ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
-+ DWC_DEBUG("error_count=%d", ereq->error_count);
-+ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
-+ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
-+ DWC_DEBUG("res=%d", ereq->res);
-+
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ xfd = &ereq->per_io_frame_descs[0];
-+ DWC_DEBUG("FD #%d", i);
-+
-+ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
-+ DWC_DEBUG("xfd->length=%d", xfd->length);
-+ DWC_DEBUG("xfd->offset=%d", xfd->offset);
-+ DWC_DEBUG("xfd->status=%d", xfd->status);
-+ }
-+}
-+
-+/**
-+ *
-+ */
-+int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
-+ int zero, void *req_handle, int atomic_alloc,
-+ void *ereq_nonport)
-+{
-+ dwc_otg_pcd_request_t *req = NULL;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ int res;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ /* We support this extension only for DDMA mode */
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
-+ if (!GET_CORE_IF(pcd)->dma_desc_enable)
-+ return -DWC_E_INVALID;
-+
-+ /* Create a dwc_otg_pcd_request_t object */
-+ if (atomic_alloc) {
-+ req = DWC_ALLOC_ATOMIC(sizeof(*req));
-+ } else {
-+ req = DWC_ALLOC(sizeof(*req));
-+ }
-+
-+ if (!req) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Create the Isoc descs for this request which shall be the exact match
-+ * of the structure sent to us from the non-portable logic */
-+ res =
-+ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
-+ if (res) {
-+ DWC_WARN("Failed to init the Isoc descriptors");
-+ DWC_FREE(req);
-+ return res;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
-+ req->buf = buf;
-+ req->dma = dma_buf;
-+ req->length = buflen;
-+ req->sent_zlp = zero;
-+ req->priv = req_handle;
-+
-+ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ ep->dwc_ep.dma_addr = dma_buf;
-+ ep->dwc_ep.start_xfer_buff = buf;
-+ ep->dwc_ep.xfer_buff = buf;
-+ ep->dwc_ep.xfer_len = 0;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = buflen;
-+
-+ /* Add this request to the tail */
-+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+ ep->dwc_ep.xiso_queued_xfers++;
-+
-+//DWC_DEBUG("CP_0");
-+//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
-+//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
-+//prn_ext_request(&req->ext_req);
-+
-+ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ /* If the req->status == ASAP then check if there is any active transfer
-+ * for this endpoint. If no active transfers, then get the first entry
-+ * from the queue and start that transfer
-+ */
-+ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
-+ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
-+ if (res) {
-+ DWC_WARN("Failed to start the next Isoc transfer");
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ DWC_FREE(req);
-+ return res;
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return 0;
-+}
-+
-+#endif
-+/* END ifdef DWC_UTE_PER_IO ***************************************************/
-+int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
-+ int zero, void *req_handle, int atomic_alloc)
-+{
-+ dwc_irqflags_t flags;
-+ dwc_otg_pcd_request_t *req;
-+ dwc_otg_pcd_ep_t *ep;
-+ uint32_t max_transfer;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (atomic_alloc) {
-+ req = DWC_ALLOC_ATOMIC(sizeof(*req));
-+ } else {
-+ req = DWC_ALLOC(sizeof(*req));
-+ }
-+
-+ if (!req) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
-+ if (!GET_CORE_IF(pcd)->core_params->opt) {
-+ if (ep->dwc_ep.num != 0) {
-+ DWC_ERROR("queue req %p, len %d buf %p\n",
-+ req_handle, buflen, buf);
-+ }
-+ }
-+
-+ req->buf = buf;
-+ req->dma = dma_buf;
-+ req->length = buflen;
-+ req->sent_zlp = zero;
-+ req->priv = req_handle;
-+ req->dw_align_buf = NULL;
-+ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
-+ && !GET_CORE_IF(pcd)->dma_desc_enable)
-+ req->dw_align_buf = DWC_DMA_ALLOC(buflen,
-+ &req->dw_align_buf_dma);
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ /*
-+ * After adding request to the queue for IN ISOC wait for In Token Received
-+ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
-+ * Received when EP is disabled interrupt to obtain starting microframe
-+ * (odd/even) start transfer
-+ */
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (req != 0) {
-+ depctl_data_t depctl = {.d32 =
-+ DWC_READ_REG32(&pcd->core_if->dev_if->
-+ in_ep_regs[ep->dwc_ep.num]->
-+ diepctl) };
-+ ++pcd->request_pending;
-+
-+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+ if (ep->dwc_ep.is_in) {
-+ depctl.b.cnak = 1;
-+ DWC_WRITE_REG32(&pcd->core_if->dev_if->
-+ in_ep_regs[ep->dwc_ep.num]->
-+ diepctl, depctl.d32);
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ }
-+ return 0;
-+ }
-+
-+ /*
-+ * For EP0 IN without premature status, zlp is required?
-+ */
-+ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
-+ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
-+ //_req->zero = 1;
-+ }
-+
-+ /* Start the transfer */
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
-+ /* EP0 Transfer? */
-+ if (ep->dwc_ep.num == 0) {
-+ switch (pcd->ep0state) {
-+ case EP0_IN_DATA_PHASE:
-+ DWC_DEBUGPL(DBG_PCD,
-+ "%s ep0: EP0_IN_DATA_PHASE\n",
-+ __func__);
-+ break;
-+
-+ case EP0_OUT_DATA_PHASE:
-+ DWC_DEBUGPL(DBG_PCD,
-+ "%s ep0: EP0_OUT_DATA_PHASE\n",
-+ __func__);
-+ if (pcd->request_config) {
-+ /* Complete STATUS PHASE */
-+ ep->dwc_ep.is_in = 1;
-+ pcd->ep0state = EP0_IN_STATUS_PHASE;
-+ }
-+ break;
-+
-+ case EP0_IN_STATUS_PHASE:
-+ DWC_DEBUGPL(DBG_PCD,
-+ "%s ep0: EP0_IN_STATUS_PHASE\n",
-+ __func__);
-+ break;
-+
-+ default:
-+ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
-+ pcd->ep0state);
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_SHUTDOWN;
-+ }
-+
-+ ep->dwc_ep.dma_addr = dma_buf;
-+ ep->dwc_ep.start_xfer_buff = buf;
-+ ep->dwc_ep.xfer_buff = buf;
-+ ep->dwc_ep.xfer_len = buflen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ if (zero) {
-+ if ((ep->dwc_ep.xfer_len %
-+ ep->dwc_ep.maxpacket == 0)
-+ && (ep->dwc_ep.xfer_len != 0)) {
-+ ep->dwc_ep.sent_zlp = 1;
-+ }
-+
-+ }
-+
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ } // non-ep0 endpoints
-+ else {
-+#ifdef DWC_UTE_CFI
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ /* store the request length */
-+ ep->dwc_ep.cfi_req_len = buflen;
-+ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
-+ ep, req);
-+ } else {
-+#endif
-+ max_transfer =
-+ GET_CORE_IF(ep->pcd)->core_params->
-+ max_transfer_size;
-+
-+ /* Setup and start the Transfer */
-+ if (req->dw_align_buf){
-+ if (ep->dwc_ep.is_in)
-+ dwc_memcpy(req->dw_align_buf,
-+ buf, buflen);
-+ ep->dwc_ep.dma_addr =
-+ req->dw_align_buf_dma;
-+ ep->dwc_ep.start_xfer_buff =
-+ req->dw_align_buf;
-+ ep->dwc_ep.xfer_buff =
-+ req->dw_align_buf;
-+ } else {
-+ ep->dwc_ep.dma_addr = dma_buf;
-+ ep->dwc_ep.start_xfer_buff = buf;
-+ ep->dwc_ep.xfer_buff = buf;
-+ }
-+ ep->dwc_ep.xfer_len = 0;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = buflen;
-+
-+ ep->dwc_ep.maxxfer = max_transfer;
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ uint32_t out_max_xfer =
-+ DDMA_MAX_TRANSFER_SIZE -
-+ (DDMA_MAX_TRANSFER_SIZE % 4);
-+ if (ep->dwc_ep.is_in) {
-+ if (ep->dwc_ep.maxxfer >
-+ DDMA_MAX_TRANSFER_SIZE) {
-+ ep->dwc_ep.maxxfer =
-+ DDMA_MAX_TRANSFER_SIZE;
-+ }
-+ } else {
-+ if (ep->dwc_ep.maxxfer >
-+ out_max_xfer) {
-+ ep->dwc_ep.maxxfer =
-+ out_max_xfer;
-+ }
-+ }
-+ }
-+ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
-+ ep->dwc_ep.maxxfer -=
-+ (ep->dwc_ep.maxxfer %
-+ ep->dwc_ep.maxpacket);
-+ }
-+
-+ if (zero) {
-+ if ((ep->dwc_ep.total_len %
-+ ep->dwc_ep.maxpacket == 0)
-+ && (ep->dwc_ep.total_len != 0)) {
-+ ep->dwc_ep.sent_zlp = 1;
-+ }
-+ }
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ }
-+ }
-+
-+ if (req != 0) {
-+ ++pcd->request_pending;
-+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+ if (ep->dwc_ep.is_in && ep->stopped
-+ && !(GET_CORE_IF(pcd)->dma_enable)) {
-+ /** @todo NGS Create a function for this. */
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.intktxfemp = 1;
-+ if (GET_CORE_IF(pcd)->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->dev_global_regs->diepeachintmsk
-+ [ep->dwc_ep.num], 0,
-+ diepmsk.d32);
-+ } else {
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->dev_global_regs->
-+ diepmsk, 0, diepmsk.d32);
-+ }
-+
-+ }
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return 0;
-+}
-+
-+int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle)
-+{
-+ dwc_irqflags_t flags;
-+ dwc_otg_pcd_request_t *req;
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
-+ DWC_WARN("bad argument\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ /* make sure it's actually queued on this endpoint */
-+ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
-+ if (req->priv == (void *)req_handle) {
-+ break;
-+ }
-+ }
-+
-+ if (req->priv != (void *)req_handle) {
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
-+ dwc_otg_request_done(ep, req, -DWC_E_RESTART);
-+ } else {
-+ req = NULL;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return req ? 0 : -DWC_E_SHUTDOWN;
-+
-+}
-+
-+/**
-+ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
-+ *
-+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
-+ * requests. If the gadget driver clears the halt status, it will
-+ * automatically unwedge the endpoint.
-+ *
-+ * Returns zero on success, else negative DWC error code.
-+ */
-+int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ int retval = 0;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if ((!ep->desc && ep != &pcd->ep0) ||
-+ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
-+ DWC_WARN("%s, bad ep\n", __func__);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT");
-+ retval = -DWC_E_AGAIN;
-+ } else {
-+ /* This code needs to be reviewed */
-+ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dtxfsts_data_t txstatus;
-+ fifosize_data_t txfifosize;
-+
-+ txfifosize.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+ core_global_regs->dtxfsiz[ep->dwc_ep.
-+ tx_fifo_num]);
-+ txstatus.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->in_ep_regs[ep->dwc_ep.num]->
-+ dtxfsts);
-+
-+ if (txstatus.b.txfspcavail < txfifosize.b.depth) {
-+ DWC_WARN("%s() Data In Tx Fifo\n", __func__);
-+ retval = -DWC_E_AGAIN;
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ }
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return retval;
-+}
-+
-+int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ int retval = 0;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if (!ep || (!ep->desc && ep != &pcd->ep0) ||
-+ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
-+ DWC_WARN("%s, bad ep\n", __func__);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT");
-+ retval = -DWC_E_AGAIN;
-+ } else if (value == 0) {
-+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ } else if (value == 1) {
-+ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dtxfsts_data_t txstatus;
-+ fifosize_data_t txfifosize;
-+
-+ txfifosize.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
-+ dtxfsiz[ep->dwc_ep.tx_fifo_num]);
-+ txstatus.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ in_ep_regs[ep->dwc_ep.num]->dtxfsts);
-+
-+ if (txstatus.b.txfspcavail < txfifosize.b.depth) {
-+ DWC_WARN("%s() Data In Tx Fifo\n", __func__);
-+ retval = -DWC_E_AGAIN;
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ }
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ }
-+ } else if (value == 2) {
-+ ep->dwc_ep.stall_clear_flag = 0;
-+ } else if (value == 3) {
-+ ep->dwc_ep.stall_clear_flag = 1;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function initiates remote wakeup of the host from suspend state.
-+ */
-+void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
-+{
-+ dctl_data_t dctl = { 0 };
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dsts_data_t dsts;
-+
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ if (!dsts.b.suspsts) {
-+ DWC_WARN("Remote wakeup while is not in suspend state\n");
-+ }
-+ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
-+ if (pcd->remote_wakeup_enable) {
-+ if (set) {
-+
-+ if (core_if->adp_enable) {
-+ gpwrdn_data_t gpwrdn;
-+
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Mask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+
-+ /* Disable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Device mode.
-+ */
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, 0, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
-+
-+ dwc_mdelay(2);
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, dctl.d32, 0);
-+ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
-+ }
-+ } else {
-+ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
-+ }
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * This function initiates remote wakeup of the host from L1 sleep state.
-+ */
-+void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+
-+ /* Check if we are in L1 state */
-+ if (!lpmcfg.b.prt_sleep_sts) {
-+ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
-+ return;
-+ }
-+
-+ /* Check if host allows remote wakeup */
-+ if (!lpmcfg.b.rem_wkup_en) {
-+ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
-+ return;
-+ }
-+
-+ /* Check if Resume OK */
-+ if (!lpmcfg.b.sleep_state_resumeok) {
-+ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
-+ return;
-+ }
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.en_utmi_sleep = 0;
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+ if (set) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.rmtwkupsig = 1;
-+ /* Set RmtWkUpSig bit to start remote wakup signaling.
-+ * Hardware will automatically clear this bit.
-+ */
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ 0, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
-+ }
-+
-+}
-+#endif
-+
-+/**
-+ * Performs remote wakeup.
-+ */
-+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_irqflags_t flags;
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (core_if->lx_state == DWC_OTG_L1) {
-+ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
-+ } else {
-+#endif
-+ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ }
-+#endif
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ }
-+ return;
-+}
-+
-+void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dctl_data_t dctl = { 0 };
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dctl.b.sftdiscon = 1;
-+ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ dwc_udelay(no_of_usecs);
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
-+
-+ } else{
-+ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
-+ }
-+ return;
-+
-+}
-+
-+int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
-+{
-+ dsts_data_t dsts;
-+ gotgctl_data_t gotgctl;
-+
-+ /*
-+ * This function starts the Protocol if no session is in progress. If
-+ * a session is already in progress, but the device is suspended,
-+ * remote wakeup signaling is started.
-+ */
-+
-+ /* Check if valid session */
-+ gotgctl.d32 =
-+ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
-+ if (gotgctl.b.bsesvld) {
-+ /* Check if suspend state */
-+ dsts.d32 =
-+ DWC_READ_REG32(&
-+ (GET_CORE_IF(pcd)->dev_if->
-+ dev_global_regs->dsts));
-+ if (dsts.b.suspsts) {
-+ dwc_otg_pcd_remote_wakeup(pcd, 1);
-+ }
-+ } else {
-+ dwc_otg_pcd_initiate_srp(pcd);
-+ }
-+
-+ return 0;
-+
-+}
-+
-+/**
-+ * Start the SRP timer to detect when the SRP does not complete within
-+ * 6 seconds.
-+ *
-+ * @param pcd the pcd structure.
-+ */
-+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_irqflags_t flags;
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ dwc_otg_initiate_srp(GET_CORE_IF(pcd));
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+}
-+
-+int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
-+{
-+ return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
-+}
-+
-+int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
-+{
-+ return GET_CORE_IF(pcd)->core_params->lpm_enable;
-+}
-+
-+uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->b_hnp_enable;
-+}
-+
-+uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->a_hnp_support;
-+}
-+
-+uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->a_alt_hnp_support;
-+}
-+
-+int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->remote_wakeup_enable;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,266 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
-+ * $Revision: #48 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+#if !defined(__DWC_PCD_H__)
-+#define __DWC_PCD_H__
-+
-+#include "dwc_otg_os_dep.h"
-+#include "usb.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_pcd_if.h"
-+struct cfiobject;
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the structures, constants, and interfaces for
-+ * the Perpherial Contoller Driver (PCD).
-+ *
-+ * The Peripheral Controller Driver (PCD) for Linux will implement the
-+ * Gadget API, so that the existing Gadget drivers can be used. For
-+ * the Mass Storage Function driver the File-backed USB Storage Gadget
-+ * (FBS) driver will be used. The FBS driver supports the
-+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
-+ * transports.
-+ *
-+ */
-+
-+/** Invalid DMA Address */
-+#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
-+
-+/** Max Transfer size for any EP */
-+#define DDMA_MAX_TRANSFER_SIZE 65535
-+
-+/**
-+ * Get the pointer to the core_if from the pcd pointer.
-+ */
-+#define GET_CORE_IF( _pcd ) (_pcd->core_if)
-+
-+/**
-+ * States of EP0.
-+ */
-+typedef enum ep0_state {
-+ EP0_DISCONNECT, /* no host */
-+ EP0_IDLE,
-+ EP0_IN_DATA_PHASE,
-+ EP0_OUT_DATA_PHASE,
-+ EP0_IN_STATUS_PHASE,
-+ EP0_OUT_STATUS_PHASE,
-+ EP0_STALL,
-+} ep0state_e;
-+
-+/** Fordward declaration.*/
-+struct dwc_otg_pcd;
-+
-+/** DWC_otg iso request structure.
-+ *
-+ */
-+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
-+
-+#ifdef DWC_UTE_PER_IO
-+
-+/**
-+ * This shall be the exact analogy of the same type structure defined in the
-+ * usb_gadget.h. Each descriptor contains
-+ */
-+struct dwc_iso_pkt_desc_port {
-+ uint32_t offset;
-+ uint32_t length; /* expected length */
-+ uint32_t actual_length;
-+ uint32_t status;
-+};
-+
-+struct dwc_iso_xreq_port {
-+ /** transfer/submission flag */
-+ uint32_t tr_sub_flags;
-+ /** Start the request ASAP */
-+#define DWC_EREQ_TF_ASAP 0x00000002
-+ /** Just enqueue the request w/o initiating a transfer */
-+#define DWC_EREQ_TF_ENQUEUE 0x00000004
-+
-+ /**
-+ * count of ISO packets attached to this request - shall
-+ * not exceed the pio_alloc_pkt_count
-+ */
-+ uint32_t pio_pkt_count;
-+ /** count of ISO packets allocated for this request */
-+ uint32_t pio_alloc_pkt_count;
-+ /** number of ISO packet errors */
-+ uint32_t error_count;
-+ /** reserved for future extension */
-+ uint32_t res;
-+ /** Will be allocated and freed in the UTE gadget and based on the CFC value */
-+ struct dwc_iso_pkt_desc_port *per_io_frame_descs;
-+};
-+#endif
-+/** DWC_otg request structure.
-+ * This structure is a list of requests.
-+ */
-+typedef struct dwc_otg_pcd_request {
-+ void *priv;
-+ void *buf;
-+ dwc_dma_t dma;
-+ uint32_t length;
-+ uint32_t actual;
-+ unsigned sent_zlp:1;
-+ /**
-+ * Used instead of original buffer if
-+ * it(physical address) is not dword-aligned.
-+ **/
-+ uint8_t *dw_align_buf;
-+ dwc_dma_t dw_align_buf_dma;
-+
-+ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
-+#ifdef DWC_UTE_PER_IO
-+ struct dwc_iso_xreq_port ext_req;
-+ //void *priv_ereq_nport; /* */
-+#endif
-+} dwc_otg_pcd_request_t;
-+
-+DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
-+
-+/** PCD EP structure.
-+ * This structure describes an EP, there is an array of EPs in the PCD
-+ * structure.
-+ */
-+typedef struct dwc_otg_pcd_ep {
-+ /** USB EP Descriptor */
-+ const usb_endpoint_descriptor_t *desc;
-+
-+ /** queue of dwc_otg_pcd_requests. */
-+ struct req_list queue;
-+ unsigned stopped:1;
-+ unsigned disabling:1;
-+ unsigned dma:1;
-+ unsigned queue_sof:1;
-+
-+#ifdef DWC_EN_ISOC
-+ /** ISOC req handle passed */
-+ void *iso_req_handle;
-+#endif //_EN_ISOC_
-+
-+ /** DWC_otg ep data. */
-+ dwc_ep_t dwc_ep;
-+
-+ /** Pointer to PCD */
-+ struct dwc_otg_pcd *pcd;
-+
-+ void *priv;
-+} dwc_otg_pcd_ep_t;
-+
-+/** DWC_otg PCD Structure.
-+ * This structure encapsulates the data for the dwc_otg PCD.
-+ */
-+struct dwc_otg_pcd {
-+ const struct dwc_otg_pcd_function_ops *fops;
-+ /** The DWC otg device pointer */
-+ struct dwc_otg_device *otg_dev;
-+ /** Core Interface */
-+ dwc_otg_core_if_t *core_if;
-+ /** State of EP0 */
-+ ep0state_e ep0state;
-+ /** EP0 Request is pending */
-+ unsigned ep0_pending:1;
-+ /** Indicates when SET CONFIGURATION Request is in process */
-+ unsigned request_config:1;
-+ /** The state of the Remote Wakeup Enable. */
-+ unsigned remote_wakeup_enable:1;
-+ /** The state of the B-Device HNP Enable. */
-+ unsigned b_hnp_enable:1;
-+ /** The state of A-Device HNP Support. */
-+ unsigned a_hnp_support:1;
-+ /** The state of the A-Device Alt HNP support. */
-+ unsigned a_alt_hnp_support:1;
-+ /** Count of pending Requests */
-+ unsigned request_pending;
-+
-+ /** SETUP packet for EP0
-+ * This structure is allocated as a DMA buffer on PCD initialization
-+ * with enough space for up to 3 setup packets.
-+ */
-+ union {
-+ usb_device_request_t req;
-+ uint32_t d32[2];
-+ } *setup_pkt;
-+
-+ dwc_dma_t setup_pkt_dma_handle;
-+
-+ /* Additional buffer and flag for CTRL_WR premature case */
-+ uint8_t *backup_buf;
-+ unsigned data_terminated;
-+
-+ /** 2-byte dma buffer used to return status from GET_STATUS */
-+ uint16_t *status_buf;
-+ dwc_dma_t status_buf_dma_handle;
-+
-+ /** EP0 */
-+ dwc_otg_pcd_ep_t ep0;
-+
-+ /** Array of IN EPs. */
-+ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
-+ /** Array of OUT EPs. */
-+ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
-+ /** number of valid EPs in the above array. */
-+// unsigned num_eps : 4;
-+ dwc_spinlock_t *lock;
-+
-+ /** Tasklet to defer starting of TEST mode transmissions until
-+ * Status Phase has been completed.
-+ */
-+ dwc_tasklet_t *test_mode_tasklet;
-+
-+ /** Tasklet to delay starting of xfer in DMA mode */
-+ dwc_tasklet_t *start_xfer_tasklet;
-+
-+ /** The test mode to enter when the tasklet is executed. */
-+ unsigned test_mode;
-+ /** The cfi_api structure that implements most of the CFI API
-+ * and OTG specific core configuration functionality
-+ */
-+#ifdef DWC_UTE_CFI
-+ struct cfiobject *cfi;
-+#endif
-+
-+};
-+
-+//FIXME this functions should be static, and this prototypes should be removed
-+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
-+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
-+ dwc_otg_pcd_request_t * req, int32_t status);
-+
-+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
-+ void *req_handle);
-+
-+extern void do_test_mode(void *data);
-+#endif
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,360 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
-+ * $Revision: #11 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+#if !defined(__DWC_PCD_IF_H__)
-+#define __DWC_PCD_IF_H__
-+
-+//#include "dwc_os.h"
-+#include "dwc_otg_core_if.h"
-+
-+/** @file
-+ * This file defines DWC_OTG PCD Core API.
-+ */
-+
-+struct dwc_otg_pcd;
-+typedef struct dwc_otg_pcd dwc_otg_pcd_t;
-+
-+/** Maxpacket size for EP0 */
-+#define MAX_EP0_SIZE 64
-+/** Maxpacket size for any EP */
-+#define MAX_PACKET_SIZE 1024
-+
-+/** @name Function Driver Callbacks */
-+/** @{ */
-+
-+/** This function will be called whenever a previously queued request has
-+ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
-+ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
-+ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
-+ * parameters. */
-+typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status,
-+ uint32_t actual);
-+/**
-+ * This function will be called whenever a previousle queued ISOC request has
-+ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
-+ * function.
-+ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
-+ * functions.
-+ */
-+typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int proc_buf_num);
-+/** This function should handle any SETUP request that cannot be handled by the
-+ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
-+ * class-specific requests, etc. The function must non-blocking.
-+ *
-+ * Returns 0 on success.
-+ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
-+ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
-+ * Returns -DWC_E_SHUTDOWN on any other error. */
-+typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
-+/** This is called whenever the device has been disconnected. The function
-+ * driver should take appropriate action to clean up all pending requests in the
-+ * PCD Core, remove all endpoints (except ep0), and initialize back to reset
-+ * state. */
-+typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has been connected. */
-+typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
-+/** This function is called when device has been suspended */
-+typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has received LPM tokens, i.e.
-+ * device has been sent to sleep state. */
-+typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has been resumed
-+ * from suspend(L2) or L1 sleep state. */
-+typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called whenever hnp params has been changed.
-+ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
-+ * to get hnp parameters. */
-+typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called whenever USB RESET is detected. */
-+typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
-+
-+typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
-+
-+/**
-+ *
-+ * @param ep_handle Void pointer to the usb_ep structure
-+ * @param ereq_port Pointer to the extended request structure created in the
-+ * portable part.
-+ */
-+typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status,
-+ void *ereq_port);
-+/** Function Driver Ops Data Structure */
-+struct dwc_otg_pcd_function_ops {
-+ dwc_connect_cb_t connect;
-+ dwc_disconnect_cb_t disconnect;
-+ dwc_setup_cb_t setup;
-+ dwc_completion_cb_t complete;
-+ dwc_isoc_completion_cb_t isoc_complete;
-+ dwc_suspend_cb_t suspend;
-+ dwc_sleep_cb_t sleep;
-+ dwc_resume_cb_t resume;
-+ dwc_reset_cb_t reset;
-+ dwc_hnp_params_changed_cb_t hnp_changed;
-+ cfi_setup_cb_t cfi_setup;
-+#ifdef DWC_UTE_PER_IO
-+ xiso_completion_cb_t xisoc_complete;
-+#endif
-+};
-+/** @} */
-+
-+/** @name Function Driver Functions */
-+/** @{ */
-+
-+/** Call this function to get pointer on dwc_otg_pcd_t,
-+ * this pointer will be used for all PCD API functions.
-+ *
-+ * @param core_if The DWC_OTG Core
-+ */
-+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
-+
-+/** Frees PCD allocated by dwc_otg_pcd_init
-+ *
-+ * @param pcd The PCD
-+ */
-+extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
-+
-+/** Call this to bind the function driver to the PCD Core.
-+ *
-+ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
-+ * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
-+ */
-+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
-+ const struct dwc_otg_pcd_function_ops *fops);
-+
-+/** Enables an endpoint for use. This function enables an endpoint in
-+ * the PCD. The endpoint is described by the ep_desc which has the
-+ * same format as a USB ep descriptor. The ep_handle parameter is used to refer
-+ * to the endpoint from other API functions and in callbacks. Normally this
-+ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
-+ * core for that interface.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_desc Endpoint descriptor
-+ * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
-+ */
-+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
-+ const uint8_t * ep_desc, void *usb_ep);
-+
-+/** Disable the endpoint referenced by ep_handle.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error occurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
-+
-+/** Queue a data transfer request on the endpoint referenced by ep_handle.
-+ * After the transfer is completes, the complete callback will be called with
-+ * the request status.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param buf The buffer for the data
-+ * @param dma_buf The DMA buffer for the data
-+ * @param buflen The length of the data transfer
-+ * @param zero Specifies whether to send zero length last packet.
-+ * @param req_handle Set this handle to any value to use to reference this
-+ * request in the ep_dequeue function or from the complete callback
-+ * @param atomic_alloc If driver need to perform atomic allocations
-+ * for internal data structures.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf,
-+ uint32_t buflen, int zero, void *req_handle,
-+ int atomic_alloc);
-+#ifdef DWC_UTE_PER_IO
-+/**
-+ *
-+ * @param ereq_nonport Pointer to the extended request part of the
-+ * usb_request structure defined in usb_gadget.h file.
-+ */
-+extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf,
-+ uint32_t buflen, int zero,
-+ void *req_handle, int atomic_alloc,
-+ void *ereq_nonport);
-+
-+#endif
-+
-+/** De-queue the specified data transfer that has not yet completed.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle);
-+
-+/** Halt (STALL) an endpoint or clear it.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
-+
-+/** This function */
-+extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
-+
-+/** This function should be called on every hardware interrupt */
-+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns current frame number */
-+extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
-+
-+/**
-+ * Start isochronous transfers on the endpoint referenced by ep_handle.
-+ * For isochronous transfers duble buffering is used.
-+ * After processing each of buffers comlete callback will be called with
-+ * status for each transaction.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param buf0 The virtual address of first data buffer
-+ * @param buf1 The virtual address of second data buffer
-+ * @param dma0 The DMA address of first data buffer
-+ * @param dma1 The DMA address of second data buffer
-+ * @param sync_frame Data pattern frame number
-+ * @param dp_frame Data size for pattern frame
-+ * @param data_per_frame Data size for regular frame
-+ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
-+ * @param buf_proc_intrvl Interval of ISOC Buffer processing
-+ * @param req_handle Handle of ISOC request
-+ * @param atomic_alloc Specefies whether to perform atomic allocation for
-+ * internal data structures.
-+ *
-+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
-+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
-+ * Returns -DW_E_SHUTDOWN for any other error.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf0, uint8_t * buf1,
-+ dwc_dma_t dma0, dwc_dma_t dma1,
-+ int sync_frame, int dp_frame,
-+ int data_per_frame, int start_frame,
-+ int buf_proc_intrvl, void *req_handle,
-+ int atomic_alloc);
-+
-+/** Stop ISOC transfers on endpoint referenced by ep_handle.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param req_handle Handle of ISOC request
-+ *
-+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
-+ * Returns 0 on success
-+ */
-+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle);
-+
-+/** Get ISOC packet status.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param iso_req_handle Isochronoush request handle
-+ * @param packet Number of packet
-+ * @param status Out parameter for returning status
-+ * @param actual Out parameter for returning actual length
-+ * @param offset Out parameter for returning offset
-+ *
-+ */
-+extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
-+ void *ep_handle,
-+ void *iso_req_handle, int packet,
-+ int *status, int *actual,
-+ int *offset);
-+
-+/** Get ISOC packet count.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param iso_req_handle
-+ */
-+extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
-+ void *ep_handle,
-+ void *iso_req_handle);
-+
-+/** This function starts the SRP Protocol if no session is in progress. If
-+ * a session is already in progress, but the device is suspended,
-+ * remote wakeup signaling is started.
-+ */
-+extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
-+extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
-+extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
-+
-+/** Initiate SRP */
-+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
-+
-+/** Starts remote wakeup signaling. */
-+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
-+
-+/** Starts micorsecond soft disconnect. */
-+extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
-+/** This function returns whether device is dualspeed.*/
-+extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns whether device is otg. */
-+extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
-+
-+/** These functions allow to get hnp parameters */
-+extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
-+extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
-+extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
-+
-+/** CFI specific Interface functions */
-+/** Allocate a cfi buffer */
-+extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
-+ dwc_dma_t * addr, size_t buflen,
-+ int flags);
-+
-+/******************************************************************************/
-+
-+/** @} */
-+
-+#endif /* __DWC_PCD_IF_H__ */
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,5147 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
-+ * $Revision: #116 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+#include "dwc_otg_pcd.h"
-+
-+#ifdef DWC_UTE_CFI
-+#include "dwc_otg_cfi.h"
-+#endif
-+
-+#ifdef DWC_UTE_PER_IO
-+extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
-+#endif
-+//#define PRINT_CFI_DMA_DESCS
-+
-+#define DEBUG_EP0
-+
-+/**
-+ * This function updates OTG.
-+ */
-+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
-+{
-+
-+ if (reset) {
-+ pcd->b_hnp_enable = 0;
-+ pcd->a_hnp_support = 0;
-+ pcd->a_alt_hnp_support = 0;
-+ }
-+
-+ if (pcd->fops->hnp_changed) {
-+ pcd->fops->hnp_changed(pcd);
-+ }
-+}
-+
-+/** @file
-+ * This file contains the implementation of the PCD Interrupt handlers.
-+ *
-+ * The PCD handles the device interrupts. Many conditions can cause a
-+ * device interrupt. When an interrupt occurs, the device interrupt
-+ * service routine determines the cause of the interrupt and
-+ * dispatches handling to the appropriate function. These interrupt
-+ * handling functions are described below.
-+ * All interrupt registers are processed from LSB to MSB.
-+ */
-+
-+/**
-+ * This function prints the ep0 state for debug purposes.
-+ */
-+static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
-+{
-+#ifdef DEBUG
-+ char str[40];
-+
-+ switch (pcd->ep0state) {
-+ case EP0_DISCONNECT:
-+ dwc_strcpy(str, "EP0_DISCONNECT");
-+ break;
-+ case EP0_IDLE:
-+ dwc_strcpy(str, "EP0_IDLE");
-+ break;
-+ case EP0_IN_DATA_PHASE:
-+ dwc_strcpy(str, "EP0_IN_DATA_PHASE");
-+ break;
-+ case EP0_OUT_DATA_PHASE:
-+ dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
-+ break;
-+ case EP0_IN_STATUS_PHASE:
-+ dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
-+ break;
-+ case EP0_OUT_STATUS_PHASE:
-+ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
-+ break;
-+ case EP0_STALL:
-+ dwc_strcpy(str, "EP0_STALL");
-+ break;
-+ default:
-+ dwc_strcpy(str, "EP0_INVALID");
-+ }
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
-+#endif
-+}
-+
-+/**
-+ * This function calculate the size of the payload in the memory
-+ * for out endpoints and prints size for debug purposes(used in
-+ * 2.93a DevOutNak feature).
-+ */
-+static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
-+{
-+#ifdef DEBUG
-+ deptsiz_data_t deptsiz_init = {.d32 = 0 };
-+ deptsiz_data_t deptsiz_updt = {.d32 = 0 };
-+ int pack_num;
-+ unsigned payload;
-+
-+ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
-+ deptsiz_updt.d32 =
-+ DWC_READ_REG32(&pcd->core_if->dev_if->
-+ out_ep_regs[ep->num]->doeptsiz);
-+ /* Payload will be */
-+ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
-+ /* Packet count is decremented every time a packet
-+ * is written to the RxFIFO not in to the external memory
-+ * So, if payload == 0, then it means no packet was sent to ext memory*/
-+ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Payload for EP%d-%s\n",
-+ ep->num, (ep->is_in ? "IN" : "OUT"));
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Number of transfered bytes = 0x%08x\n", payload);
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Number of transfered packets = %d\n", pack_num);
-+#endif
-+}
-+
-+
-+#ifdef DWC_UTE_CFI
-+static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
-+ const uint8_t * epname, int descnum)
-+{
-+ CFI_INFO
-+ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
-+ epname, descnum, ddesc->buf, ddesc->status.b.bytes,
-+ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
-+ ddesc->status.b.bs);
-+}
-+#endif
-+
-+/**
-+ * This function returns pointer to in ep struct with number ep_num
-+ */
-+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
-+{
-+ int i;
-+ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
-+ if (ep_num == 0) {
-+ return &pcd->ep0;
-+ } else {
-+ for (i = 0; i < num_in_eps; ++i) {
-+ if (pcd->in_ep[i].dwc_ep.num == ep_num)
-+ return &pcd->in_ep[i];
-+ }
-+ return 0;
-+ }
-+}
-+
-+/**
-+ * This function returns pointer to out ep struct with number ep_num
-+ */
-+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
-+{
-+ int i;
-+ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
-+ if (ep_num == 0) {
-+ return &pcd->ep0;
-+ } else {
-+ for (i = 0; i < num_out_eps; ++i) {
-+ if (pcd->out_ep[i].dwc_ep.num == ep_num)
-+ return &pcd->out_ep[i];
-+ }
-+ return 0;
-+ }
-+}
-+
-+/**
-+ * This functions gets a pointer to an EP from the wIndex address
-+ * value of the control request.
-+ */
-+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ uint32_t ep_num = UE_GET_ADDR(wIndex);
-+
-+ if (ep_num == 0) {
-+ ep = &pcd->ep0;
-+ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */
-+ ep = &pcd->in_ep[ep_num - 1];
-+ } else {
-+ ep = &pcd->out_ep[ep_num - 1];
-+ }
-+
-+ return ep;
-+}
-+
-+/**
-+ * This function checks the EP request queue, if the queue is not
-+ * empty the next request is started.
-+ */
-+void start_next_request(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_pcd_request_t *req = 0;
-+ uint32_t max_transfer =
-+ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
-+
-+#ifdef DWC_UTE_CFI
-+ struct dwc_otg_pcd *pcd;
-+ pcd = ep->pcd;
-+#endif
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+
-+#ifdef DWC_UTE_CFI
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ ep->dwc_ep.cfi_req_len = req->length;
-+ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
-+ } else {
-+#endif
-+ /* Setup and start the Transfer */
-+ if (req->dw_align_buf) {
-+ ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
-+ ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
-+ ep->dwc_ep.xfer_buff = req->dw_align_buf;
-+ } else {
-+ ep->dwc_ep.dma_addr = req->dma;
-+ ep->dwc_ep.start_xfer_buff = req->buf;
-+ ep->dwc_ep.xfer_buff = req->buf;
-+ }
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = req->length;
-+ ep->dwc_ep.xfer_len = 0;
-+ ep->dwc_ep.xfer_count = 0;
-+
-+ ep->dwc_ep.maxxfer = max_transfer;
-+ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
-+ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
-+ - (DDMA_MAX_TRANSFER_SIZE % 4);
-+ if (ep->dwc_ep.is_in) {
-+ if (ep->dwc_ep.maxxfer >
-+ DDMA_MAX_TRANSFER_SIZE) {
-+ ep->dwc_ep.maxxfer =
-+ DDMA_MAX_TRANSFER_SIZE;
-+ }
-+ } else {
-+ if (ep->dwc_ep.maxxfer > out_max_xfer) {
-+ ep->dwc_ep.maxxfer =
-+ out_max_xfer;
-+ }
-+ }
-+ }
-+ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
-+ ep->dwc_ep.maxxfer -=
-+ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
-+ }
-+ if (req->sent_zlp) {
-+ if ((ep->dwc_ep.total_len %
-+ ep->dwc_ep.maxpacket == 0)
-+ && (ep->dwc_ep.total_len != 0)) {
-+ ep->dwc_ep.sent_zlp = 1;
-+ }
-+
-+ }
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
-+ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ DWC_PRINTF("There are no more ISOC requests \n");
-+ ep->dwc_ep.frame_num = 0xFFFFFFFF;
-+ }
-+}
-+
-+/**
-+ * This function handles the SOF Interrupts. At this time the SOF
-+ * Interrupt is disabled.
-+ */
-+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_PCD, "SOF\n");
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.sofintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function handles the Rx Status Queue Level Interrupt, which
-+ * indicates that there is a least one packet in the Rx FIFO. The
-+ * packets are moved from the FIFO to memory, where they will be
-+ * processed when the Endpoint Interrupt Register indicates Transfer
-+ * Complete or SETUP Phase Done.
-+ *
-+ * Repeat the following until the Rx Status Queue is empty:
-+ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
-+ * info
-+ * -# If Receive FIFO is empty then skip to step Clear the interrupt
-+ * and exit
-+ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
-+ * SETUP data to the buffer
-+ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
-+ * to the destination buffer
-+ */
-+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t gintmask = {.d32 = 0 };
-+ device_grxsts_data_t status;
-+ dwc_otg_pcd_ep_t *ep;
-+ gintsts_data_t gintsts;
-+#ifdef DEBUG
-+ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
-+#endif
-+
-+ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
-+ /* Disable the Rx Status Queue Level interrupt */
-+ gintmask.b.rxstsqlvl = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
-+
-+ /* Get the Status from the top of the FIFO */
-+ status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
-+ "pktsts:%x Frame:%d(0x%0x)\n",
-+ status.b.epnum, status.b.bcnt,
-+ dpid_str[status.b.dpid],
-+ status.b.pktsts, status.b.fn, status.b.fn);
-+ /* Get pointer to EP structure */
-+ ep = get_out_ep(pcd, status.b.epnum);
-+
-+ switch (status.b.pktsts) {
-+ case DWC_DSTS_GOUT_NAK:
-+ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
-+ break;
-+ case DWC_STS_DATA_UPDT:
-+ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
-+ if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
-+ /** @todo NGS Check for buffer overflow? */
-+ dwc_otg_read_packet(core_if,
-+ ep->dwc_ep.xfer_buff,
-+ status.b.bcnt);
-+ ep->dwc_ep.xfer_count += status.b.bcnt;
-+ ep->dwc_ep.xfer_buff += status.b.bcnt;
-+ }
-+ break;
-+ case DWC_STS_XFER_COMP:
-+ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
-+ break;
-+ case DWC_DSTS_SETUP_COMP:
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
-+#endif
-+ break;
-+ case DWC_DSTS_SETUP_UPDT:
-+ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD,
-+ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
-+ pcd->setup_pkt->req.bmRequestType,
-+ pcd->setup_pkt->req.bRequest,
-+ UGETW(pcd->setup_pkt->req.wValue),
-+ UGETW(pcd->setup_pkt->req.wIndex),
-+ UGETW(pcd->setup_pkt->req.wLength));
-+#endif
-+ ep->dwc_ep.xfer_count += status.b.bcnt;
-+ break;
-+ default:
-+ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
-+ status.b.pktsts);
-+ break;
-+ }
-+
-+ /* Enable the Rx Status Queue Level interrupt */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.rxstsqlvl = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
-+ return 1;
-+}
-+
-+/**
-+ * This function examines the Device IN Token Learning Queue to
-+ * determine the EP number of the last IN token received. This
-+ * implementation is for the Mass Storage device where there are only
-+ * 2 IN EPs (Control-IN and BULK-IN).
-+ *
-+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
-+ * are 8 EP Numbers in each of the other possible DTKNQ Registers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ *
-+ */
-+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_device_global_regs_t *dev_global_regs =
-+ core_if->dev_if->dev_global_regs;
-+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
-+ /* Number of Token Queue Registers */
-+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
-+ dtknq1_data_t dtknqr1;
-+ uint32_t in_tkn_epnums[4];
-+ int ndx = 0;
-+ int i = 0;
-+ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
-+ int epnum = 0;
-+
-+ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
-+
-+ /* Read the DTKNQ Registers */
-+ for (i = 0; i < DTKNQ_REG_CNT; i++) {
-+ in_tkn_epnums[i] = DWC_READ_REG32(addr);
-+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
-+ in_tkn_epnums[i]);
-+ if (addr == &dev_global_regs->dvbusdis) {
-+ addr = &dev_global_regs->dtknqr3_dthrctl;
-+ } else {
-+ ++addr;
-+ }
-+
-+ }
-+
-+ /* Copy the DTKNQR1 data to the bit field. */
-+ dtknqr1.d32 = in_tkn_epnums[0];
-+ /* Get the EP numbers */
-+ in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
-+ ndx = dtknqr1.b.intknwptr - 1;
-+
-+ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
-+ if (ndx == -1) {
-+ /** @todo Find a simpler way to calculate the max
-+ * queue position.*/
-+ int cnt = TOKEN_Q_DEPTH;
-+ if (TOKEN_Q_DEPTH <= 6) {
-+ cnt = TOKEN_Q_DEPTH - 1;
-+ } else if (TOKEN_Q_DEPTH <= 14) {
-+ cnt = TOKEN_Q_DEPTH - 7;
-+ } else if (TOKEN_Q_DEPTH <= 22) {
-+ cnt = TOKEN_Q_DEPTH - 15;
-+ } else {
-+ cnt = TOKEN_Q_DEPTH - 23;
-+ }
-+ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
-+ } else {
-+ if (ndx <= 5) {
-+ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
-+ } else if (ndx <= 13) {
-+ ndx -= 6;
-+ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
-+ } else if (ndx <= 21) {
-+ ndx -= 14;
-+ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
-+ } else if (ndx <= 29) {
-+ ndx -= 22;
-+ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
-+ }
-+ }
-+ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
-+ return epnum;
-+}
-+
-+/**
-+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
-+ * The active request is checked for the next packet to be loaded into
-+ * the non-periodic Tx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ gnptxsts_data_t txstatus = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+
-+ int epnum = 0;
-+ dwc_otg_pcd_ep_t *ep = 0;
-+ uint32_t len = 0;
-+ int dwords;
-+
-+ /* Get the epnum from the IN Token Learning Queue. */
-+ epnum = get_ep_of_last_in_token(core_if);
-+ ep = get_in_ep(pcd, epnum);
-+
-+ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
-+
-+ while (txstatus.b.nptxqspcavail > 0 &&
-+ txstatus.b.nptxfspcavail > dwords &&
-+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxsts));
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.nptxfempty = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function is called when dedicated Tx FIFO Empty interrupt occurs.
-+ * The active request is checked for the next packet to be loaded into
-+ * apropriate Tx FIFO.
-+ */
-+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep = 0;
-+ uint32_t len = 0;
-+ int dwords;
-+
-+ ep = get_in_ep(pcd, epnum);
-+
-+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
-+ ep->dwc_ep.xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
-+
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
-+ txstatus.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function is called when the Device is disconnected. It stops
-+ * any active requests and informs the Gadget driver of the
-+ * disconnect.
-+ */
-+void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
-+{
-+ int i, num_in_eps, num_out_eps;
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_SPINLOCK(pcd->lock);
-+
-+ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
-+ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
-+ /* don't disconnect drivers more than once */
-+ if (pcd->ep0state == EP0_DISCONNECT) {
-+ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
-+ DWC_SPINUNLOCK(pcd->lock);
-+ return;
-+ }
-+ pcd->ep0state = EP0_DISCONNECT;
-+
-+ /* Reset the OTG state. */
-+ dwc_otg_pcd_update_otg(pcd, 1);
-+
-+ /* Disable the NP Tx Fifo Empty Interrupt. */
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Flush the FIFOs */
-+ /**@todo NGS Flush Periodic FIFOs */
-+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
-+ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
-+
-+ /* prevent new request submissions, kill any outstanding requests */
-+ ep = &pcd->ep0;
-+ dwc_otg_request_nuke(ep);
-+ /* prevent new request submissions, kill any outstanding requests */
-+ for (i = 0; i < num_in_eps; i++) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
-+ dwc_otg_request_nuke(ep);
-+ }
-+ /* prevent new request submissions, kill any outstanding requests */
-+ for (i = 0; i < num_out_eps; i++) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
-+ dwc_otg_request_nuke(ep);
-+ }
-+
-+ /* report disconnect; the driver is already quiesced */
-+ if (pcd->fops->disconnect) {
-+ DWC_SPINUNLOCK(pcd->lock);
-+ pcd->fops->disconnect(pcd);
-+ DWC_SPINLOCK(pcd->lock);
-+ }
-+ DWC_SPINUNLOCK(pcd->lock);
-+}
-+
-+/**
-+ * This interrupt indicates that ...
-+ */
-+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
-+ intr_mask.b.i2cintr = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.i2cintr = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that ...
-+ */
-+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+#if defined(VERBOSE)
-+ DWC_PRINTF("Early Suspend Detected\n");
-+#endif
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.erlysuspend = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This function configures EPO to receive SETUP packets.
-+ *
-+ * @todo NGS: Update the comments from the HW FS.
-+ *
-+ * -# Program the following fields in the endpoint specific registers
-+ * for Control OUT EP 0, in order to receive a setup packet
-+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
-+ * setup packets)
-+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
-+ * to back setup packets)
-+ * - In DMA mode, DOEPDMA0 Register with a memory address to
-+ * store any setup packets received
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param pcd Programming view of the PCD.
-+ */
-+static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
-+ dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ depctl_data_t doepctl = {.d32 = 0 };
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
-+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+#endif
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
-+ if (doepctl.b.epena) {
-+ return;
-+ }
-+ }
-+
-+ doeptsize0.b.supcnt = 3;
-+ doeptsize0.b.pktcnt = 1;
-+ doeptsize0.b.xfersize = 8 * 3;
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ /** put here as for Hermes mode deptisz register should not be written */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
-+ doeptsize0.d32);
-+
-+ /** @todo dma needs to handle multiple setup packets (up to 3) */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
-+ pcd->setup_pkt_dma_handle);
-+ } else {
-+ dev_if->setup_desc_index =
-+ (dev_if->setup_desc_index + 1) & 1;
-+ dma_desc =
-+ dev_if->setup_desc_addr[dev_if->setup_desc_index];
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ dma_desc->status.b.sr = 0;
-+ dma_desc->status.b.mtrf = 0;
-+ }
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
-+ dma_desc->buf = pcd->setup_pkt_dma_handle;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
-+ dev_if->dma_setup_desc_addr
-+ [dev_if->setup_desc_index]);
-+ }
-+
-+ } else {
-+ /** put here as for Hermes mode deptisz register should not be written */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
-+ doeptsize0.d32);
-+ }
-+
-+ /** DOEPCTL0 Register write cnak will be set after setup interrupt */
-+ doepctl.d32 = 0;
-+ doepctl.b.epena = 1;
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ doepctl.b.cnak = 1;
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+ } else {
-+ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
-+ }
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+}
-+
-+/**
-+ * This interrupt occurs when a USB Reset is detected. When the USB
-+ * Reset Interrupt occurs the device state is set to DEFAULT and the
-+ * EP0 state is set to IDLE.
-+ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
-+ * -# Unmask the following interrupt bits
-+ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
-+ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
-+ * - DOEPMSK.SETUP = 1
-+ * - DOEPMSK.XferCompl = 1
-+ * - DIEPMSK.XferCompl = 1
-+ * - DIEPMSK.TimeOut = 1
-+ * -# Program the following fields in the endpoint specific registers
-+ * for Control OUT EP 0, in order to receive a setup packet
-+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
-+ * setup packets)
-+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
-+ * to back setup packets)
-+ * - In DMA mode, DOEPDMA0 Register with a memory address to
-+ * store any setup packets received
-+ * At this point, all the required initialization, except for enabling
-+ * the control 0 OUT endpoint is done, for receiving SETUP packets.
-+ */
-+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ depctl_data_t doepctl = {.d32 = 0 };
-+ depctl_data_t diepctl = {.d32 = 0 };
-+ daint_data_t daintmsk = {.d32 = 0 };
-+ doepmsk_data_t doepmsk = {.d32 = 0 };
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+ grstctl_t resetctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+ int i = 0;
-+ gintsts_data_t gintsts;
-+ pcgcctl_data_t power = {.d32 = 0 };
-+
-+ power.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+ if (power.b.stoppclk) {
-+ power.d32 = 0;
-+ power.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+
-+ power.b.pwrclmp = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+
-+ power.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+ }
-+
-+ core_if->lx_state = DWC_OTG_L0;
-+
-+ DWC_PRINTF("USB RESET\n");
-+#ifdef DWC_EN_ISOC
-+ for (i = 1; i < 16; ++i) {
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ ep = get_in_ep(pcd, i);
-+ if (ep != 0) {
-+ dwc_ep = &ep->dwc_ep;
-+ dwc_ep->next_frame = 0xffffffff;
-+ }
-+ }
-+#endif /* DWC_EN_ISOC */
-+
-+ /* reset the HNP settings */
-+ dwc_otg_pcd_update_otg(pcd, 1);
-+
-+ /* Clear the Remote Wakeup Signalling */
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+
-+ /* Set NAK for all OUT EPs */
-+ doepctl.b.snak = 1;
-+ for (i = 0; i <= dev_if->num_out_eps; i++) {
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
-+ }
-+
-+ /* Flush the NP Tx FIFO */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10);
-+ /* Flush the Learning Queue */
-+ resetctl.b.intknqflsh = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
-+ core_if->start_predict = 0;
-+ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
-+ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
-+ }
-+ core_if->nextep_seq[0] = 0;
-+ core_if->first_in_nextep_seq = 0;
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+ diepctl.b.nextep = 0;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt = 2;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
-+ }
-+ }
-+
-+ if (core_if->multiproc_int_enable) {
-+ daintmsk.b.inep0 = 1;
-+ daintmsk.b.outep0 = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
-+ daintmsk.d32);
-+
-+ doepmsk.b.setup = 1;
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+
-+ if ((core_if->dma_desc_enable) ||
-+ (core_if->dma_enable
-+ && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
-+ doepmsk.b.stsphsercvd = 1;
-+ }
-+ if (core_if->dma_desc_enable)
-+ doepmsk.b.bna = 1;
-+/*
-+ doepmsk.b.babble = 1;
-+ doepmsk.b.nyet = 1;
-+
-+ if (core_if->dma_enable) {
-+ doepmsk.b.nak = 1;
-+ }
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
-+ doepmsk.d32);
-+
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ diepmsk.b.intknepmis = 1;
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+ diepmsk.b.intknepmis = 0;
-+
-+/* if (core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+*/
-+/*
-+ if (core_if->dma_enable) {
-+ diepmsk.b.nak = 1;
-+ }
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
-+ diepmsk.d32);
-+ } else {
-+ daintmsk.b.inep0 = 1;
-+ daintmsk.b.outep0 = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
-+ daintmsk.d32);
-+
-+ doepmsk.b.setup = 1;
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+
-+ if ((core_if->dma_desc_enable) ||
-+ (core_if->dma_enable
-+ && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
-+ doepmsk.b.stsphsercvd = 1;
-+ }
-+ if (core_if->dma_desc_enable)
-+ doepmsk.b.bna = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
-+
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+ diepmsk.b.intknepmis = 0;
-+/*
-+ if (core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+*/
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
-+ }
-+
-+ /* Reset Device Address */
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devaddr = 0;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* setup EP0 to receive SETUP packets */
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a)
-+ ep0_out_start(core_if, pcd);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbreset = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Get the device speed from the device status register and convert it
-+ * to USB speed constant.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static int get_device_speed(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ int speed = 0;
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ switch (dsts.b.enumspd) {
-+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+ speed = USB_SPEED_HIGH;
-+ break;
-+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+ speed = USB_SPEED_FULL;
-+ break;
-+
-+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+ speed = USB_SPEED_LOW;
-+ break;
-+ }
-+
-+ return speed;
-+}
-+
-+/**
-+ * Read the device status register and set the device speed in the
-+ * data structure.
-+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
-+ */
-+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ gintsts_data_t gintsts;
-+ gusbcfg_data_t gusbcfg;
-+ dwc_otg_core_global_regs_t *global_regs =
-+ GET_CORE_IF(pcd)->core_global_regs;
-+ uint8_t utmi16b, utmi8b;
-+ int speed;
-+ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
-+
-+ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
-+ utmi16b = 6; //vahrama old value was 6;
-+ utmi8b = 9;
-+ } else {
-+ utmi16b = 4;
-+ utmi8b = 8;
-+ }
-+ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
-+ ep0_out_start(GET_CORE_IF(pcd), pcd);
-+ }
-+
-+#ifdef DEBUG_EP0
-+ print_ep0_state(pcd);
-+#endif
-+
-+ if (pcd->ep0state == EP0_DISCONNECT) {
-+ pcd->ep0state = EP0_IDLE;
-+ } else if (pcd->ep0state == EP0_STALL) {
-+ pcd->ep0state = EP0_IDLE;
-+ }
-+
-+ pcd->ep0state = EP0_IDLE;
-+
-+ ep0->stopped = 0;
-+
-+ speed = get_device_speed(GET_CORE_IF(pcd));
-+ pcd->fops->connect(pcd, speed);
-+
-+ /* Set USB turnaround time based on device speed and PHY interface. */
-+ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ if (speed == USB_SPEED_HIGH) {
-+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+ DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
-+ /* ULPI interface */
-+ gusbcfg.b.usbtrdtim = 9;
-+ }
-+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+ DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
-+ /* UTMI+ interface */
-+ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
-+ gusbcfg.b.usbtrdtim = utmi8b;
-+ } else if (GET_CORE_IF(pcd)->hwcfg4.
-+ b.utmi_phy_data_width == 1) {
-+ gusbcfg.b.usbtrdtim = utmi16b;
-+ } else if (GET_CORE_IF(pcd)->
-+ core_params->phy_utmi_width == 8) {
-+ gusbcfg.b.usbtrdtim = utmi8b;
-+ } else {
-+ gusbcfg.b.usbtrdtim = utmi16b;
-+ }
-+ }
-+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
-+ /* UTMI+ OR ULPI interface */
-+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ gusbcfg.b.usbtrdtim = 9;
-+ } else {
-+ /* UTMI+ interface */
-+ if (GET_CORE_IF(pcd)->
-+ core_params->phy_utmi_width == 16) {
-+ gusbcfg.b.usbtrdtim = utmi16b;
-+ } else {
-+ gusbcfg.b.usbtrdtim = utmi8b;
-+ }
-+ }
-+ }
-+ } else {
-+ /* Full or low speed */
-+ gusbcfg.b.usbtrdtim = 9;
-+ }
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.enumdone = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the ISO OUT Packet was dropped due to
-+ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
-+ * read all the data from the Rx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+
-+ DWC_WARN("INTERRUPT Handler not implemented for %s\n",
-+ "ISOC Out Dropped");
-+
-+ intr_mask.b.isooutdrop = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.isooutdrop = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates the end of the portion of the micro-frame
-+ * for periodic transactions. If there is a periodic transaction for
-+ * the next frame, load the packets into the EP periodic Tx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
-+
-+ intr_mask.b.eopframe = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.eopframe = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that EP of the packet on the top of the
-+ * non-periodic Tx FIFO does not match EP of the IN Token received.
-+ *
-+ * The "Device IN Token Queue" Registers are read to determine the
-+ * order the IN Tokens have been received. The non-periodic Tx FIFO
-+ * is flushed, so it can be reloaded in the order seen in the IN Token
-+ * Queue.
-+ */
-+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dctl_data_t dctl;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+ core_if->start_predict = 1;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-+
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (!gintsts.b.ginnakeff) {
-+ /* Disable EP Mismatch interrupt */
-+ intr_mask.d32 = 0;
-+ intr_mask.b.epmismatch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+ /* Enable the Global IN NAK Effective Interrupt */
-+ intr_mask.d32 = 0;
-+ intr_mask.b.ginnakeff = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
-+ /* Set the global non-periodic IN NAK handshake */
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ dctl.b.sgnpinnak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+ } else {
-+ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
-+ }
-+ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
-+ * handler after Global IN NAK Effective interrupt will be asserted */
-+ }
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.epmismatch = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt is valid only in DMA mode. This interrupt indicates that the
-+ * core has stopped fetching data for IN endpoints due to the unavailability of
-+ * TxFIFO space or Request Queue space. This interrupt is used by the
-+ * application for an endpoint mismatch algorithm.
-+ *
-+ * @param pcd The PCD
-+ */
-+int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk_data;
-+ dctl_data_t dctl;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-+
-+ /* Clear the global non-periodic IN NAK handshake */
-+ dctl.d32 = 0;
-+ dctl.b.cgnpinnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+ /* Mask GINTSTS.FETSUSP interrupt */
-+ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+ gintmsk_data.b.fetsusp = 0;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.fetsusp = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+/**
-+ * This funcion stalls EP0.
-+ */
-+static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ usb_device_request_t *ctrl = &pcd->setup_pkt->req;
-+ DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
-+ ctrl->bmRequestType, ctrl->bRequest, err_val);
-+
-+ ep0->dwc_ep.is_in = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+ pcd->ep0.stopped = 1;
-+ pcd->ep0state = EP0_IDLE;
-+ ep0_out_start(GET_CORE_IF(pcd), pcd);
-+}
-+
-+/**
-+ * This functions delegates the setup command to the gadget driver.
-+ */
-+static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
-+ usb_device_request_t * ctrl)
-+{
-+ int ret = 0;
-+ DWC_SPINUNLOCK(pcd->lock);
-+ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
-+ DWC_SPINLOCK(pcd->lock);
-+ if (ret < 0) {
-+ ep0_do_stall(pcd, ret);
-+ }
-+
-+ /** @todo This is a g_file_storage gadget driver specific
-+ * workaround: a DELAYED_STATUS result from the fsg_setup
-+ * routine will result in the gadget queueing a EP0 IN status
-+ * phase for a two-stage control transfer. Exactly the same as
-+ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
-+ * specific request. Need a generic way to know when the gadget
-+ * driver will queue the status phase. Can we assume when we
-+ * call the gadget driver setup() function that it will always
-+ * queue and require the following flag? Need to look into
-+ * this.
-+ */
-+
-+ if (ret == 256 + 999) {
-+ pcd->request_config = 1;
-+ }
-+}
-+
-+#ifdef DWC_UTE_CFI
-+/**
-+ * This functions delegates the CFI setup commands to the gadget driver.
-+ * This function will return a negative value to indicate a failure.
-+ */
-+static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
-+ struct cfi_usb_ctrlrequest *ctrl_req)
-+{
-+ int ret = 0;
-+
-+ if (pcd->fops && pcd->fops->cfi_setup) {
-+ DWC_SPINUNLOCK(pcd->lock);
-+ ret = pcd->fops->cfi_setup(pcd, ctrl_req);
-+ DWC_SPINLOCK(pcd->lock);
-+ if (ret < 0) {
-+ ep0_do_stall(pcd, ret);
-+ return ret;
-+ }
-+ }
-+
-+ return ret;
-+}
-+#endif
-+
-+/**
-+ * This function starts the Zero-Length Packet for the IN status phase
-+ * of a 2 stage control transfer.
-+ */
-+static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ if (pcd->ep0state == EP0_STALL) {
-+ return;
-+ }
-+
-+ pcd->ep0state = EP0_IN_STATUS_PHASE;
-+
-+ /* Prepare for more SETUP Packets */
-+ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
-+ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
-+ && (pcd->core_if->dma_desc_enable)
-+ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Data terminated wait next packet in out_desc_addr\n");
-+ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
-+ pcd->data_terminated = 1;
-+ }
-+ ep0->dwc_ep.xfer_len = 0;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.is_in = 1;
-+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+
-+ /* Prepare for more SETUP Packets */
-+ //ep0_out_start(GET_CORE_IF(pcd), pcd);
-+}
-+
-+/**
-+ * This function starts the Zero-Length Packet for the OUT status phase
-+ * of a 2 stage control transfer.
-+ */
-+static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ if (pcd->ep0state == EP0_STALL) {
-+ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
-+ return;
-+ }
-+ pcd->ep0state = EP0_OUT_STATUS_PHASE;
-+
-+ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
-+ ep0->dwc_ep.xfer_len = 0;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.is_in = 0;
-+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+
-+ /* Prepare for more SETUP Packets */
-+ if (GET_CORE_IF(pcd)->dma_enable == 0) {
-+ ep0_out_start(GET_CORE_IF(pcd), pcd);
-+ }
-+}
-+
-+/**
-+ * Clear the EP halt (STALL) and if pending requests start the
-+ * transfer.
-+ */
-+static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
-+{
-+ if (ep->dwc_ep.stall_clear_flag == 0)
-+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+
-+ /* Reactive the EP */
-+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ if (ep->stopped) {
-+ ep->stopped = 0;
-+ /* If there is a request in the EP queue start it */
-+
-+ /** @todo FIXME: this causes an EP mismatch in DMA mode.
-+ * epmismatch not yet implemented. */
-+
-+ /*
-+ * Above fixme is solved by implmenting a tasklet to call the
-+ * start_next_request(), outside of interrupt context at some
-+ * time after the current time, after a clear-halt setup packet.
-+ * Still need to implement ep mismatch in the future if a gadget
-+ * ever uses more than one endpoint at once
-+ */
-+ ep->queue_sof = 1;
-+ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
-+ }
-+ /* Start Control Status Phase */
-+ do_setup_in_status_phase(pcd);
-+}
-+
-+/**
-+ * This function is called when the SET_FEATURE TEST_MODE Setup packet
-+ * is sent from the host. The Device Control register is written with
-+ * the Test Mode bits set to the specified Test Mode. This is done as
-+ * a tasklet so that the "Status" phase of the control transfer
-+ * completes before transmitting the TEST packets.
-+ *
-+ * @todo This has not been tested since the tasklet struct was put
-+ * into the PCD struct!
-+ *
-+ */
-+void do_test_mode(void *data)
-+{
-+ dctl_data_t dctl;
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ int test_mode = pcd->test_mode;
-+
-+// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
-+
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ switch (test_mode) {
-+ case 1: // TEST_J
-+ dctl.b.tstctl = 1;
-+ break;
-+
-+ case 2: // TEST_K
-+ dctl.b.tstctl = 2;
-+ break;
-+
-+ case 3: // TEST_SE0_NAK
-+ dctl.b.tstctl = 3;
-+ break;
-+
-+ case 4: // TEST_PACKET
-+ dctl.b.tstctl = 4;
-+ break;
-+
-+ case 5: // TEST_FORCE_ENABLE
-+ dctl.b.tstctl = 5;
-+ break;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+}
-+
-+/**
-+ * This function process the GET_STATUS Setup Commands.
-+ */
-+static inline void do_get_status(dwc_otg_pcd_t * pcd)
-+{
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ uint16_t *status = pcd->status_buf;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD,
-+ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+#endif
-+
-+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+ case UT_DEVICE:
-+ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
-+ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
-+ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
-+ DWC_PRINTF("OTG CAP - %d, %d\n",
-+ core_if->core_params->otg_cap,
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+ if (core_if->otg_ver == 1
-+ && core_if->core_params->otg_cap ==
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ uint8_t *otgsts = (uint8_t*)pcd->status_buf;
-+ *otgsts = (core_if->otg_sts & 0x1);
-+ pcd->ep0_pending = 1;
-+ ep0->dwc_ep.start_xfer_buff =
-+ (uint8_t *) otgsts;
-+ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
-+ ep0->dwc_ep.dma_addr =
-+ pcd->status_buf_dma_handle;
-+ ep0->dwc_ep.xfer_len = 1;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ return;
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+ } else {
-+ *status = 0x1; /* Self powered */
-+ *status |= pcd->remote_wakeup_enable << 1;
-+ break;
-+ }
-+ case UT_INTERFACE:
-+ *status = 0;
-+ break;
-+
-+ case UT_ENDPOINT:
-+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+ if (ep == 0 || UGETW(ctrl.wLength) > 2) {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ /** @todo check for EP stall */
-+ *status = ep->stopped;
-+ break;
-+ }
-+ pcd->ep0_pending = 1;
-+ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
-+ ep0->dwc_ep.xfer_buff = (uint8_t *) status;
-+ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
-+ ep0->dwc_ep.xfer_len = 2;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+}
-+
-+/**
-+ * This function process the SET_FEATURE Setup Commands.
-+ */
-+static inline void do_set_feature(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep = 0;
-+ int32_t otg_cap_param = core_if->core_params->otg_cap;
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
-+
-+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+ case UT_DEVICE:
-+ switch (UGETW(ctrl.wValue)) {
-+ case UF_DEVICE_REMOTE_WAKEUP:
-+ pcd->remote_wakeup_enable = 1;
-+ break;
-+
-+ case UF_TEST_MODE:
-+ /* Setup the Test Mode tasklet to do the Test
-+ * Packet generation after the SETUP Status
-+ * phase has completed. */
-+
-+ /** @todo This has not been tested since the
-+ * tasklet struct was put into the PCD
-+ * struct! */
-+ pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
-+ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
-+ break;
-+
-+ case UF_DEVICE_B_HNP_ENABLE:
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
-+
-+ /* dev may initiate HNP */
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ pcd->b_hnp_enable = 1;
-+ dwc_otg_pcd_update_otg(pcd, 0);
-+ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
-+ /**@todo Is the gotgctl.devhnpen cleared
-+ * by a USB Reset? */
-+ gotgctl.b.devhnpen = 1;
-+ gotgctl.b.hnpreq = 1;
-+ DWC_WRITE_REG32(&global_regs->gotgctl,
-+ gotgctl.d32);
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+
-+ case UF_DEVICE_A_HNP_SUPPORT:
-+ /* RH port supports HNP */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ pcd->a_hnp_support = 1;
-+ dwc_otg_pcd_update_otg(pcd, 0);
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+
-+ case UF_DEVICE_A_ALT_HNP_SUPPORT:
-+ /* other RH port does */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ pcd->a_alt_hnp_support = 1;
-+ dwc_otg_pcd_update_otg(pcd, 0);
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+
-+ default:
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+
-+ }
-+ do_setup_in_status_phase(pcd);
-+ break;
-+
-+ case UT_INTERFACE:
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+
-+ case UT_ENDPOINT:
-+ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
-+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+ if (ep == 0) {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
-+ }
-+ do_setup_in_status_phase(pcd);
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function process the CLEAR_FEATURE Setup Commands.
-+ */
-+static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
-+{
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep = 0;
-+
-+ DWC_DEBUGPL(DBG_PCD,
-+ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+
-+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+ case UT_DEVICE:
-+ switch (UGETW(ctrl.wValue)) {
-+ case UF_DEVICE_REMOTE_WAKEUP:
-+ pcd->remote_wakeup_enable = 0;
-+ break;
-+
-+ case UF_TEST_MODE:
-+ /** @todo Add CLEAR_FEATURE for TEST modes. */
-+ break;
-+
-+ default:
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ do_setup_in_status_phase(pcd);
-+ break;
-+
-+ case UT_ENDPOINT:
-+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+ if (ep == 0) {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+
-+ pcd_clear_halt(pcd, ep);
-+
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function process the SET_ADDRESS Setup Commands.
-+ */
-+static inline void do_set_address(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+
-+ if (ctrl.bmRequestType == UT_DEVICE) {
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+
-+#ifdef DEBUG_EP0
-+// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
-+#endif
-+ dcfg.b.devaddr = UGETW(ctrl.wValue);
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
-+ do_setup_in_status_phase(pcd);
-+ }
-+}
-+
-+/**
-+ * This function processes SETUP commands. In Linux, the USB Command
-+ * processing is done in two places - the first being the PCD and the
-+ * second in the Gadget Driver (for example, the File-Backed Storage
-+ * Gadget Driver).
-+ *
-+ * <table>
-+ * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
-+ *
-+ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
-+ * defined in chapter 9 of the USB 2.0 Specification chapter 9
-+ * </td></tr>
-+ *
-+ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
-+ * requests are the ENDPOINT_HALT feature is procesed, all others the
-+ * interface requests are ignored.</td></tr>
-+ *
-+ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
-+ * requests are processed by the PCD. Interface requests are passed
-+ * to the Gadget Driver.</td></tr>
-+ *
-+ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
-+ * with device address received </td></tr>
-+ *
-+ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
-+ * requested descriptor</td></tr>
-+ *
-+ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
-+ * not implemented by any of the existing Gadget Drivers.</td></tr>
-+ *
-+ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
-+ * all EPs and enable EPs for new configuration.</td></tr>
-+ *
-+ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
-+ * the current configuration</td></tr>
-+ *
-+ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
-+ * EPs and enable EPs for new configuration.</td></tr>
-+ *
-+ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
-+ * current interface.</td></tr>
-+ *
-+ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
-+ * message.</td></tr>
-+ * </table>
-+ *
-+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
-+ * processed by pcd_setup. Calling the Function Driver's setup function from
-+ * pcd_setup processes the gadget SETUP commands.
-+ */
-+static inline void pcd_setup(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+
-+ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+
-+#ifdef DWC_UTE_CFI
-+ int retval = 0;
-+ struct cfi_usb_ctrlrequest cfi_req;
-+#endif
-+
-+ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
-+
-+ /** In BDMA more then 1 setup packet is not supported till 3.00a */
-+ if (core_if->dma_enable && core_if->dma_desc_enable == 0
-+ && (doeptsize0.b.supcnt < 2)
-+ && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
-+ DWC_ERROR
-+ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
-+ }
-+ if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
-+ ctrl =
-+ (pcd->setup_pkt +
-+ (3 - doeptsize0.b.supcnt - 1 +
-+ ep0->dwc_ep.stp_rollover))->req;
-+ }
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+#endif
-+
-+ /* Clean up the request queue */
-+ dwc_otg_request_nuke(ep0);
-+ ep0->stopped = 0;
-+
-+ if (ctrl.bmRequestType & UE_DIR_IN) {
-+ ep0->dwc_ep.is_in = 1;
-+ pcd->ep0state = EP0_IN_DATA_PHASE;
-+ } else {
-+ ep0->dwc_ep.is_in = 0;
-+ pcd->ep0state = EP0_OUT_DATA_PHASE;
-+ }
-+
-+ if (UGETW(ctrl.wLength) == 0) {
-+ ep0->dwc_ep.is_in = 1;
-+ pcd->ep0state = EP0_IN_STATUS_PHASE;
-+ }
-+
-+ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
-+
-+#ifdef DWC_UTE_CFI
-+ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
-+
-+ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
-+ ctrl.bRequestType, ctrl.bRequest);
-+ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
-+ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
-+ retval = cfi_setup(pcd, &cfi_req);
-+ if (retval < 0) {
-+ ep0_do_stall(pcd, retval);
-+ pcd->ep0_pending = 0;
-+ return;
-+ }
-+
-+ /* if need gadget setup then call it and check the retval */
-+ if (pcd->cfi->need_gadget_att) {
-+ retval =
-+ cfi_gadget_setup(pcd,
-+ &pcd->
-+ cfi->ctrl_req);
-+ if (retval < 0) {
-+ pcd->ep0_pending = 0;
-+ return;
-+ }
-+ }
-+
-+ if (pcd->cfi->need_status_in_complete) {
-+ do_setup_in_status_phase(pcd);
-+ }
-+ return;
-+ }
-+ }
-+#endif
-+
-+ /* handle non-standard (class/vendor) requests in the gadget driver */
-+ do_gadget_setup(pcd, &ctrl);
-+ return;
-+ }
-+
-+ /** @todo NGS: Handle bad setup packet? */
-+
-+///////////////////////////////////////////
-+//// --- Standard Request handling --- ////
-+
-+ switch (ctrl.bRequest) {
-+ case UR_GET_STATUS:
-+ do_get_status(pcd);
-+ break;
-+
-+ case UR_CLEAR_FEATURE:
-+ do_clear_feature(pcd);
-+ break;
-+
-+ case UR_SET_FEATURE:
-+ do_set_feature(pcd);
-+ break;
-+
-+ case UR_SET_ADDRESS:
-+ do_set_address(pcd);
-+ break;
-+
-+ case UR_SET_INTERFACE:
-+ case UR_SET_CONFIG:
-+// _pcd->request_config = 1; /* Configuration changed */
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+
-+ case UR_SYNCH_FRAME:
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+
-+ default:
-+ /* Call the Gadget Driver's setup functions */
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function completes the ep0 control transfer.
-+ */
-+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
-+ dev_if->in_ep_regs[ep->dwc_ep.num];
-+#ifdef DEBUG_EP0
-+ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
-+ dev_if->out_ep_regs[ep->dwc_ep.num];
-+#endif
-+ deptsiz0_data_t deptsiz;
-+ dev_dma_desc_sts_t desc_sts;
-+ dwc_otg_pcd_request_t *req;
-+ int is_last = 0;
-+ dwc_otg_pcd_t *pcd = ep->pcd;
-+
-+#ifdef DWC_UTE_CFI
-+ struct cfi_usb_ctrlrequest *ctrlreq;
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+#endif
-+
-+ desc_sts.b.bytes = 0;
-+
-+ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ if (ep->dwc_ep.is_in) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
-+#endif
-+ do_setup_out_status_phase(pcd);
-+ } else {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
-+#endif
-+
-+#ifdef DWC_UTE_CFI
-+ ctrlreq = &pcd->cfi->ctrl_req;
-+
-+ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
-+ if (ctrlreq->bRequest > 0xB0
-+ && ctrlreq->bRequest < 0xBF) {
-+
-+ /* Return if the PCD failed to handle the request */
-+ if ((retval =
-+ pcd->cfi->ops.
-+ ctrl_write_complete(pcd->cfi,
-+ pcd)) < 0) {
-+ CFI_INFO
-+ ("ERROR setting a new value in the PCD(%d)\n",
-+ retval);
-+ ep0_do_stall(pcd, retval);
-+ pcd->ep0_pending = 0;
-+ return 0;
-+ }
-+
-+ /* If the gadget needs to be notified on the request */
-+ if (pcd->cfi->need_gadget_att == 1) {
-+ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
-+ retval =
-+ cfi_gadget_setup(pcd,
-+ &pcd->cfi->
-+ ctrl_req);
-+
-+ /* Return from the function if the gadget failed to process
-+ * the request properly - this should never happen !!!
-+ */
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("ERROR setting a new value in the gadget(%d)\n",
-+ retval);
-+ pcd->ep0_pending = 0;
-+ return 0;
-+ }
-+ }
-+
-+ CFI_INFO("%s: RETVAL=%d\n", __func__,
-+ retval);
-+ /* If we hit here then the PCD and the gadget has properly
-+ * handled the request - so send the ZLP IN to the host.
-+ */
-+ /* @todo: MAS - decide whether we need to start the setup
-+ * stage based on the need_setup value of the cfi object
-+ */
-+ do_setup_in_status_phase(pcd);
-+ pcd->ep0_pending = 0;
-+ return 1;
-+ }
-+ }
-+#endif
-+
-+ do_setup_in_status_phase(pcd);
-+ }
-+ pcd->ep0_pending = 0;
-+ return 1;
-+ }
-+
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ return 0;
-+ }
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+
-+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE
-+ || pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ is_last = 1;
-+ } else if (ep->dwc_ep.is_in) {
-+ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
-+ if (core_if->dma_desc_enable != 0)
-+ desc_sts = dev_if->in_desc_addr->status;
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num, ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+#endif
-+
-+ if (((core_if->dma_desc_enable == 0)
-+ && (deptsiz.b.xfersize == 0))
-+ || ((core_if->dma_desc_enable != 0)
-+ && (desc_sts.b.bytes == 0))) {
-+ req->actual = ep->dwc_ep.xfer_count;
-+ /* Is a Zero Len Packet needed? */
-+ if (req->sent_zlp) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
-+#endif
-+ req->sent_zlp = 0;
-+ }
-+ do_setup_out_status_phase(pcd);
-+ }
-+ } else {
-+ /* ep0-OUT */
-+#ifdef DEBUG_EP0
-+ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
-+ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num, ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+#endif
-+ req->actual = ep->dwc_ep.xfer_count;
-+
-+ /* Is a Zero Len Packet needed? */
-+ if (req->sent_zlp) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
-+#endif
-+ req->sent_zlp = 0;
-+ }
-+ /* For older cores do setup in status phase in Slave/BDMA modes,
-+ * starting from 3.00 do that only in slave, and for DMA modes
-+ * just re-enable ep 0 OUT here*/
-+ if (core_if->dma_enable == 0
-+ || (core_if->dma_desc_enable == 0
-+ && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
-+ do_setup_in_status_phase(pcd);
-+ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Enable out ep before in status phase\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+
-+ /* Complete the request */
-+ if (is_last) {
-+ dwc_otg_request_done(ep, req, 0);
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+ return 1;
-+ }
-+ return 0;
-+}
-+
-+#ifdef DWC_UTE_CFI
-+/**
-+ * This function calculates traverses all the CFI DMA descriptors and
-+ * and accumulates the bytes that are left to be transfered.
-+ *
-+ * @return The total bytes left to transfered, or a negative value as failure
-+ */
-+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
-+{
-+ int32_t ret = 0;
-+ int i;
-+ struct dwc_otg_dma_desc *ddesc = NULL;
-+ struct cfi_ep *cfiep;
-+
-+ /* See if the pcd_ep has its respective cfi_ep mapped */
-+ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
-+ if (!cfiep) {
-+ CFI_INFO("%s: Failed to find ep\n", __func__);
-+ return -1;
-+ }
-+
-+ ddesc = ep->dwc_ep.descs;
-+
-+ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
-+
-+#if defined(PRINT_CFI_DMA_DESCS)
-+ print_desc(ddesc, ep->ep.name, i);
-+#endif
-+ ret += ddesc->status.b.bytes;
-+ ddesc++;
-+ }
-+
-+ if (ret)
-+ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
-+ ret);
-+
-+ return ret;
-+}
-+#endif
-+
-+/**
-+ * This function completes the request for the EP. If there are
-+ * additional requests for the EP in the queue they will be started.
-+ */
-+static void complete_ep(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
-+ dev_if->in_ep_regs[ep->dwc_ep.num];
-+ deptsiz_data_t deptsiz;
-+ dev_dma_desc_sts_t desc_sts;
-+ dwc_otg_pcd_request_t *req = 0;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ uint32_t byte_count = 0;
-+ int is_last = 0;
-+ int i;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"));
-+
-+ /* Get any pending requests */
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (!req) {
-+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+ return;
-+ }
-+ } else {
-+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+ return;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
-+
-+ if (ep->dwc_ep.is_in) {
-+ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
-+
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ if (deptsiz.b.xfersize == 0
-+ && deptsiz.b.pktcnt == 0) {
-+ byte_count =
-+ ep->dwc_ep.xfer_len -
-+ ep->dwc_ep.xfer_count;
-+
-+ ep->dwc_ep.xfer_buff += byte_count;
-+ ep->dwc_ep.dma_addr += byte_count;
-+ ep->dwc_ep.xfer_count += byte_count;
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%d-%s len=%d xfersize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num,
-+ (ep->dwc_ep.
-+ is_in ? "IN" : "OUT"),
-+ ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize,
-+ deptsiz.b.pktcnt);
-+
-+ if (ep->dwc_ep.xfer_len <
-+ ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer
-+ (core_if, &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length transfer in case if it is queued
-+ * a transfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Descriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 length.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer
-+ (core_if, &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ } else {
-+ if (ep->dwc_ep.type ==
-+ DWC_OTG_EP_TYPE_ISOC) {
-+ req->actual = 0;
-+ dwc_otg_request_done(ep, req, 0);
-+
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+
-+ /* If there is a request in the queue start it. */
-+ start_next_request(ep);
-+ } else
-+ DWC_WARN
-+ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
-+ ep->dwc_ep.num,
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+ deptsiz.b.xfersize,
-+ deptsiz.b.pktcnt);
-+ }
-+ } else {
-+ dma_desc = ep->dwc_ep.desc_addr;
-+ byte_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+
-+#ifdef DWC_UTE_CFI
-+ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
-+ ep->dwc_ep.buff_mode);
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ int residue;
-+
-+ residue = cfi_calc_desc_residue(ep);
-+ if (residue < 0)
-+ return;
-+
-+ byte_count = residue;
-+ } else {
-+#endif
-+ for (i = 0; i < ep->dwc_ep.desc_cnt;
-+ ++i) {
-+ desc_sts = dma_desc->status;
-+ byte_count += desc_sts.b.bytes;
-+ dma_desc++;
-+ }
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ if (byte_count == 0) {
-+ ep->dwc_ep.xfer_count =
-+ ep->dwc_ep.total_len;
-+ is_last = 1;
-+ } else {
-+ DWC_WARN("Incomplete transfer\n");
-+ }
-+ }
-+ } else {
-+ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%d-%s len=%d xfersize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT",
-+ ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize,
-+ deptsiz.b.pktcnt);
-+
-+ /* Check if the whole transfer was completed,
-+ * if no, setup transfer for next portion of data
-+ */
-+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length trasfer in case if it is queued
-+ * a trasfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Desriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 legth.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ } else {
-+ DWC_WARN
-+ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
-+ ep->dwc_ep.num,
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ }
-+ }
-+ } else {
-+ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
-+ dev_if->out_ep_regs[ep->dwc_ep.num];
-+ desc_sts.d32 = 0;
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ dma_desc = ep->dwc_ep.desc_addr;
-+ byte_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+
-+#ifdef DWC_UTE_CFI
-+ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
-+ ep->dwc_ep.buff_mode);
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ int residue;
-+ residue = cfi_calc_desc_residue(ep);
-+ if (residue < 0)
-+ return;
-+ byte_count = residue;
-+ } else {
-+#endif
-+
-+ for (i = 0; i < ep->dwc_ep.desc_cnt;
-+ ++i) {
-+ desc_sts = dma_desc->status;
-+ byte_count += desc_sts.b.bytes;
-+ dma_desc++;
-+ }
-+
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ /* Checking for interrupt Out transfers with not
-+ * dword aligned mps sizes
-+ */
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
-+ (ep->dwc_ep.maxpacket%4)) {
-+ ep->dwc_ep.xfer_count =
-+ ep->dwc_ep.total_len - byte_count;
-+ if ((ep->dwc_ep.xfer_len %
-+ ep->dwc_ep.maxpacket)
-+ && (ep->dwc_ep.xfer_len /
-+ ep->dwc_ep.maxpacket <
-+ MAX_DMA_DESC_CNT))
-+ ep->dwc_ep.xfer_len -=
-+ (ep->dwc_ep.desc_cnt -
-+ 1) * ep->dwc_ep.maxpacket +
-+ ep->dwc_ep.xfer_len %
-+ ep->dwc_ep.maxpacket;
-+ else
-+ ep->dwc_ep.xfer_len -=
-+ ep->dwc_ep.desc_cnt *
-+ ep->dwc_ep.maxpacket;
-+ if (ep->dwc_ep.xfer_len > 0) {
-+ dwc_otg_ep_start_transfer
-+ (core_if, &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ } else {
-+ ep->dwc_ep.xfer_count =
-+ ep->dwc_ep.total_len - byte_count +
-+ ((4 -
-+ (ep->dwc_ep.
-+ total_len & 0x3)) & 0x3);
-+ is_last = 1;
-+ }
-+ } else {
-+ deptsiz.d32 = 0;
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&out_ep_regs->doeptsiz);
-+
-+ byte_count = (ep->dwc_ep.xfer_len -
-+ ep->dwc_ep.xfer_count -
-+ deptsiz.b.xfersize);
-+ ep->dwc_ep.xfer_buff += byte_count;
-+ ep->dwc_ep.dma_addr += byte_count;
-+ ep->dwc_ep.xfer_count += byte_count;
-+
-+ /* Check if the whole transfer was completed,
-+ * if no, setup transfer for next portion of data
-+ */
-+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length trasfer in case if it is queued
-+ * a trasfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Desriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 legth.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ }
-+ } else {
-+ /* Check if the whole transfer was completed,
-+ * if no, setup transfer for next portion of data
-+ */
-+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length transfer in case if it is queued
-+ * a transfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Descriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 length.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
-+ &out_ep_regs->doeptsiz, ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT",
-+ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ }
-+
-+ /* Complete the request */
-+ if (is_last) {
-+#ifdef DWC_UTE_CFI
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ req->actual = ep->dwc_ep.cfi_req_len - byte_count;
-+ } else {
-+#endif
-+ req->actual = ep->dwc_ep.xfer_count;
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ if (req->dw_align_buf) {
-+ if (!ep->dwc_ep.is_in) {
-+ dwc_memcpy(req->buf, req->dw_align_buf, req->length);
-+ }
-+ DWC_DMA_FREE(req->length, req->dw_align_buf,
-+ req->dw_align_buf_dma);
-+ }
-+
-+ dwc_otg_request_done(ep, req, 0);
-+
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+
-+ /* If there is a request in the queue start it. */
-+ start_next_request(ep);
-+ }
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function BNA interrupt for Isochronous EPs
-+ *
-+ */
-+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+ volatile uint32_t *addr;
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dwc_otg_pcd_t *pcd = ep->pcd;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ int i;
-+
-+ dma_desc =
-+ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
-+
-+ if (dwc_ep->is_in) {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+ sts.d32 = dma_desc->status.d32;
-+ sts.b_iso_in.bs = BS_HOST_READY;
-+ dma_desc->status.d32 = sts.d32;
-+ }
-+ } else {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+ sts.d32 = dma_desc->status.d32;
-+ sts.b_iso_out.bs = BS_HOST_READY;
-+ dma_desc->status.d32 = sts.d32;
-+ }
-+ }
-+
-+ if (dwc_ep->is_in == 0) {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
-+ num]->doepctl;
-+ } else {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+ }
-+ depctl.b.epena = 1;
-+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+}
-+
-+/**
-+ * This function sets latest iso packet information(non-PTI mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ dma_addr_t dma_addr;
-+ uint32_t offset;
-+
-+ if (ep->proc_buf_num)
-+ dma_addr = ep->dma_addr1;
-+ else
-+ dma_addr = ep->dma_addr0;
-+
-+ if (ep->is_in) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[ep->num]->dieptsiz);
-+ offset = ep->data_per_frame;
-+ } else {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->num]->doeptsiz);
-+ offset =
-+ ep->data_per_frame +
-+ (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
-+ }
-+
-+ if (!deptsiz.b.xfersize) {
-+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
-+ ep->pkt_info[ep->cur_pkt].offset =
-+ ep->cur_pkt_dma_addr - dma_addr;
-+ ep->pkt_info[ep->cur_pkt].status = 0;
-+ } else {
-+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
-+ ep->pkt_info[ep->cur_pkt].offset =
-+ ep->cur_pkt_dma_addr - dma_addr;
-+ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
-+ }
-+ ep->cur_pkt_addr += offset;
-+ ep->cur_pkt_dma_addr += offset;
-+ ep->cur_pkt++;
-+}
-+
-+/**
-+ * This function sets latest iso packet information(DDMA mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * dwc_ep)
-+{
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ iso_pkt_info_t *iso_packet;
-+ uint32_t data_per_desc;
-+ uint32_t offset;
-+ int i, j;
-+
-+ iso_packet = dwc_ep->pkt_info;
-+
-+ /** Reinit closed DMA Descriptors*/
-+ /** ISO OUT EP */
-+ if (dwc_ep->is_in == 0) {
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+ offset = 0;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->
-+ data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 -
-+ data_per_desc %
-+ 4) : 0;
-+
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso_packet_decsriptor */
-+ iso_packet->status =
-+ sts.b_iso_out.rxsts +
-+ (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+
-+ /* Received data length */
-+ if (!sts.b_iso_out.rxbytes) {
-+ iso_packet->length =
-+ data_per_desc -
-+ sts.b_iso_out.rxbytes;
-+ } else {
-+ iso_packet->length =
-+ data_per_desc -
-+ sts.b_iso_out.rxbytes + (4 -
-+ dwc_ep->data_per_frame
-+ % 4);
-+ }
-+
-+ iso_packet->offset = offset;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ iso_packet++;
-+ }
-+ }
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso_packet_decsriptor */
-+ iso_packet->status =
-+ sts.b_iso_out.rxsts +
-+ (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+
-+ /* Received data length */
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
-+
-+ iso_packet->offset = offset;
-+
-+ offset += data_per_desc;
-+ iso_packet++;
-+ dma_desc++;
-+ }
-+
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso_packet_decsriptor */
-+ iso_packet->status =
-+ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+ /* Received data length */
-+ if (!sts.b_iso_out.rxbytes) {
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
-+ } else {
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
-+ (4 - dwc_ep->data_per_frame % 4);
-+ }
-+
-+ iso_packet->offset = offset;
-+ } else {
-+/** ISO IN EP */
-+
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso packet descriptor */
-+ iso_packet->status =
-+ sts.b_iso_in.txsts +
-+ (sts.b_iso_in.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status != 0) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+
-+ }
-+ /* Bytes has been transfered */
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
-+
-+ dma_desc++;
-+ iso_packet++;
-+ }
-+
-+ sts.d32 = dma_desc->status.d32;
-+ while (sts.b_iso_in.bs == BS_DMA_BUSY) {
-+ sts.d32 = dma_desc->status.d32;
-+ }
-+
-+ /* Write status in iso packet descriptor ??? do be done with ERROR codes */
-+ iso_packet->status =
-+ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status != 0) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+
-+ /* Bytes has been transfered */
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
-+ }
-+}
-+
-+/**
-+ * This function reinitialize DMA Descriptors for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
-+{
-+ int i, j;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ dma_addr_t dma_ad;
-+ volatile uint32_t *addr;
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ uint32_t data_per_desc;
-+
-+ if (dwc_ep->is_in == 0) {
-+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
-+ } else {
-+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+ }
-+
-+ if (dwc_ep->proc_buf_num == 0) {
-+ /** Buffer 0 descriptors setup */
-+ dma_ad = dwc_ep->dma_addr0;
-+ } else {
-+ /** Buffer 1 descriptors setup */
-+ dma_ad = dwc_ep->dma_addr1;
-+ }
-+
-+ /** Reinit closed DMA Descriptors*/
-+ /** ISO OUT EP */
-+ if (dwc_ep->is_in == 0) {
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+ sts.b_iso_out.bs = BS_HOST_READY;
-+ sts.b_iso_out.rxsts = 0;
-+ sts.b_iso_out.l = 0;
-+ sts.b_iso_out.sp = 0;
-+ sts.b_iso_out.ioc = 0;
-+ sts.b_iso_out.pid = 0;
-+ sts.b_iso_out.framenum = 0;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->
-+ data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 -
-+ data_per_desc %
-+ 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dma_ad += data_per_desc;
-+ dma_desc++;
-+ }
-+ }
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+
-+ sts.b_iso_out.ioc = 1;
-+ sts.b_iso_out.l = dwc_ep->proc_buf_num;
-+
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ } else {
-+/** ISO IN EP */
-+
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+ sts.b_iso_in.bs = BS_HOST_READY;
-+ sts.b_iso_in.txsts = 0;
-+ sts.b_iso_in.sp = 0;
-+ sts.b_iso_in.ioc = 0;
-+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
-+ sts.b_iso_in.framenum = dwc_ep->next_frame;
-+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
-+ sts.b_iso_in.l = 0;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ sts.b_iso_in.framenum += dwc_ep->bInterval;
-+ dma_ad += dwc_ep->data_per_frame;
-+ dma_desc++;
-+ }
-+
-+ sts.b_iso_in.ioc = 1;
-+ sts.b_iso_in.l = dwc_ep->proc_buf_num;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dwc_ep->next_frame =
-+ sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
-+ }
-+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+}
-+
-+/**
-+ * This function is to handle Iso EP transfer complete interrupt
-+ * in case Iso out packet was dropped
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP for wihich transfer complete was asserted
-+ *
-+ */
-+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * dwc_ep)
-+{
-+ uint32_t dma_addr;
-+ uint32_t drp_pkt;
-+ uint32_t drp_pkt_cnt;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ int i;
-+
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[dwc_ep->num]->doeptsiz);
-+
-+ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
-+ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
-+
-+ /* Setting dropped packets status */
-+ for (i = 0; i < drp_pkt_cnt; ++i) {
-+ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
-+ drp_pkt++;
-+ deptsiz.b.pktcnt--;
-+ }
-+
-+ if (deptsiz.b.pktcnt > 0) {
-+ deptsiz.b.xfersize =
-+ dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
-+ deptsiz.b.pktcnt) * dwc_ep->maxpacket;
-+ } else {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 0;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
-+ deptsiz.d32);
-+
-+ if (deptsiz.b.pktcnt > 0) {
-+ if (dwc_ep->proc_buf_num) {
-+ dma_addr =
-+ dwc_ep->dma_addr1 + dwc_ep->xfer_len -
-+ deptsiz.b.xfersize;
-+ } else {
-+ dma_addr =
-+ dwc_ep->dma_addr0 + dwc_ep->xfer_len -
-+ deptsiz.b.xfersize;;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
-+
-+ /** Re-enable endpoint, clear nak */
-+ depctl.d32 = 0;
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(&core_if->dev_if->
-+ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
-+ depctl.d32);
-+ return 0;
-+ } else {
-+ return 1;
-+ }
-+}
-+
-+/**
-+ * This function sets iso packets information(PTI mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ int i, j;
-+ dma_addr_t dma_ad;
-+ iso_pkt_info_t *packet_info = ep->pkt_info;
-+ uint32_t offset;
-+ uint32_t frame_data;
-+ deptsiz_data_t deptsiz;
-+
-+ if (ep->proc_buf_num == 0) {
-+ /** Buffer 0 descriptors setup */
-+ dma_ad = ep->dma_addr0;
-+ } else {
-+ /** Buffer 1 descriptors setup */
-+ dma_ad = ep->dma_addr1;
-+ }
-+
-+ if (ep->is_in) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ dieptsiz);
-+ } else {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
-+ doeptsiz);
-+ }
-+
-+ if (!deptsiz.b.xfersize) {
-+ offset = 0;
-+ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
-+ frame_data = ep->data_per_frame;
-+ for (j = 0; j < ep->pkt_per_frm; ++j) {
-+
-+ /* Packet status - is not set as initially
-+ * it is set to 0 and if packet was sent
-+ successfully, status field will remain 0*/
-+
-+ /* Bytes has been transfered */
-+ packet_info->length =
-+ (ep->maxpacket <
-+ frame_data) ? ep->maxpacket : frame_data;
-+
-+ /* Received packet offset */
-+ packet_info->offset = offset;
-+ offset += packet_info->length;
-+ frame_data -= packet_info->length;
-+
-+ packet_info++;
-+ }
-+ }
-+ return 1;
-+ } else {
-+ /* This is a workaround for in case of Transfer Complete with
-+ * PktDrpSts interrupts merging - in this case Transfer complete
-+ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
-+ * set and with DOEPTSIZ register non zero. Investigations showed,
-+ * that this happens when Out packet is dropped, but because of
-+ * interrupts merging during first interrupt handling PktDrpSts
-+ * bit is cleared and for next merged interrupts it is not reset.
-+ * In this case SW hadles the interrupt as if PktDrpSts bit is set.
-+ */
-+ if (ep->is_in) {
-+ return 1;
-+ } else {
-+ return handle_iso_out_pkt_dropped(core_if, ep);
-+ }
-+ }
-+}
-+
-+/**
-+ * This function is to handle Iso EP transfer complete interrupt
-+ *
-+ * @param pcd The PCD
-+ * @param ep The EP for which transfer complete was asserted
-+ *
-+ */
-+static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+ uint8_t is_last = 0;
-+
-+ if (ep->dwc_ep.next_frame == 0xffffffff) {
-+ DWC_WARN("Next frame is not set!\n");
-+ return;
-+ }
-+
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ set_ddma_iso_pkts_info(core_if, dwc_ep);
-+ reinit_ddma_iso_xfer(core_if, dwc_ep);
-+ is_last = 1;
-+ } else {
-+ if (core_if->pti_enh_enable) {
-+ if (set_iso_pkts_info(core_if, dwc_ep)) {
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+ dwc_otg_iso_ep_start_buf_transfer
-+ (core_if, dwc_ep);
-+ is_last = 1;
-+ }
-+ } else {
-+ set_current_pkt_info(core_if, dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ is_last = 1;
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+ dwc_otg_iso_ep_start_frm_transfer(core_if,
-+ dwc_ep);
-+ }
-+ }
-+ } else {
-+ set_current_pkt_info(core_if, dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ is_last = 1;
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
-+ }
-+ if (is_last)
-+ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+/**
-+ * This function handle BNA interrupt for Non Isochronous EPs
-+ *
-+ */
-+static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+ volatile uint32_t *addr;
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dwc_otg_pcd_t *pcd = ep->pcd;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = ep->pcd->core_if;
-+ int i, start;
-+
-+ if (!dwc_ep->desc_cnt)
-+ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
-+ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
-+
-+ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
-+ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
-+ uint32_t doepdma;
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[dwc_ep->num];
-+ doepdma = DWC_READ_REG32(&(out_regs->doepdma));
-+ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
-+ dma_desc = &(dwc_ep->desc_addr[start]);
-+ } else {
-+ start = 0;
-+ dma_desc = dwc_ep->desc_addr;
-+ }
-+
-+
-+ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+ sts.d32 = dma_desc->status.d32;
-+ sts.b.bs = BS_HOST_READY;
-+ dma_desc->status.d32 = sts.d32;
-+ }
-+
-+ if (dwc_ep->is_in == 0) {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
-+ doepctl;
-+ } else {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+ }
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+ DWC_MODIFY_REG32(addr, 0, depctl.d32);
-+}
-+
-+/**
-+ * This function handles EP0 Control transfers.
-+ *
-+ * The state of the control transfers are tracked in
-+ * <code>ep0state</code>.
-+ */
-+static void handle_ep0(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ dev_dma_desc_sts_t desc_sts;
-+ deptsiz0_data_t deptsiz;
-+ uint32_t byte_count;
-+
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
-+ print_ep0_state(pcd);
-+#endif
-+
-+// DWC_PRINTF("HANDLE EP0\n");
-+
-+ switch (pcd->ep0state) {
-+ case EP0_DISCONNECT:
-+ break;
-+
-+ case EP0_IDLE:
-+ pcd->request_config = 0;
-+
-+ pcd_setup(pcd);
-+ break;
-+
-+ case EP0_IN_DATA_PHASE:
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
-+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
-+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
-+#endif
-+
-+ if (core_if->dma_enable != 0) {
-+ /*
-+ * For EP0 we can only program 1 packet at a time so we
-+ * need to do the make calculations after each complete.
-+ * Call write_packet to make the calculations, as in
-+ * slave mode, and use those values to determine if we
-+ * can complete.
-+ */
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->in_ep_regs[0]->
-+ dieptsiz);
-+ byte_count =
-+ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
-+ } else {
-+ desc_sts =
-+ core_if->dev_if->in_desc_addr->status;
-+ byte_count =
-+ ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
-+ }
-+ ep0->dwc_ep.xfer_count += byte_count;
-+ ep0->dwc_ep.xfer_buff += byte_count;
-+ ep0->dwc_ep.dma_addr += byte_count;
-+ }
-+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
-+ } else if (ep0->dwc_ep.sent_zlp) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ ep0->dwc_ep.sent_zlp = 0;
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
-+ } else {
-+ ep0_complete_request(ep0);
-+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
-+ }
-+ break;
-+ case EP0_OUT_DATA_PHASE:
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
-+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
-+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
-+#endif
-+ if (core_if->dma_enable != 0) {
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->out_ep_regs[0]->
-+ doeptsiz);
-+ byte_count =
-+ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
-+ } else {
-+ desc_sts =
-+ core_if->dev_if->out_desc_addr->status;
-+ byte_count =
-+ ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
-+ }
-+ ep0->dwc_ep.xfer_count += byte_count;
-+ ep0->dwc_ep.xfer_buff += byte_count;
-+ ep0->dwc_ep.dma_addr += byte_count;
-+ }
-+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
-+ } else if (ep0->dwc_ep.sent_zlp) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ ep0->dwc_ep.sent_zlp = 0;
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
-+ } else {
-+ ep0_complete_request(ep0);
-+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
-+ }
-+ break;
-+
-+ case EP0_IN_STATUS_PHASE:
-+ case EP0_OUT_STATUS_PHASE:
-+ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
-+ ep0_complete_request(ep0);
-+ pcd->ep0state = EP0_IDLE;
-+ ep0->stopped = 1;
-+ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
-+
-+ /* Prepare for more SETUP Packets */
-+ if (core_if->dma_enable) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+ break;
-+
-+ case EP0_STALL:
-+ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
-+ break;
-+ }
-+#ifdef DEBUG_EP0
-+ print_ep0_state(pcd);
-+#endif
-+}
-+
-+/**
-+ * Restart transfer
-+ */
-+static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if;
-+ dwc_otg_dev_if_t *dev_if;
-+ deptsiz_data_t dieptsiz = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ ep = get_in_ep(pcd, epnum);
-+
-+#ifdef DWC_EN_ISOC
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ return;
-+ }
-+#endif /* DWC_EN_ISOC */
-+
-+ core_if = GET_CORE_IF(pcd);
-+ dev_if = core_if->dev_if;
-+
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
-+
-+ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
-+ " stopped=%d\n", ep->dwc_ep.xfer_buff,
-+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
-+ /*
-+ * If xfersize is 0 and pktcnt in not 0, resend the last packet.
-+ */
-+ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
-+ ep->dwc_ep.start_xfer_buff != 0) {
-+ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
-+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
-+ } else {
-+ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
-+ /* convert packet size to dwords. */
-+ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
-+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
-+ }
-+ ep->stopped = 0;
-+ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
-+ "xfer_len=%0x stopped=%d\n",
-+ ep->dwc_ep.xfer_buff,
-+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
-+ ep->stopped);
-+ if (epnum == 0) {
-+ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
-+ } else {
-+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
-+ }
-+ }
-+}
-+
-+/*
-+ * This function create new nextep sequnce based on Learn Queue.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void predict_nextep_seq( dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_device_global_regs_t *dev_global_regs =
-+ core_if->dev_if->dev_global_regs;
-+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
-+ /* Number of Token Queue Registers */
-+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
-+ dtknq1_data_t dtknqr1;
-+ uint32_t in_tkn_epnums[4];
-+ uint8_t seqnum[MAX_EPS_CHANNELS];
-+ uint8_t intkn_seq[TOKEN_Q_DEPTH];
-+ grstctl_t resetctl = {.d32 = 0 };
-+ uint8_t temp;
-+ int ndx = 0;
-+ int start = 0;
-+ int end = 0;
-+ int sort_done = 0;
-+ int i = 0;
-+ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
-+
-+
-+ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
-+
-+ /* Read the DTKNQ Registers */
-+ for (i = 0; i < DTKNQ_REG_CNT; i++) {
-+ in_tkn_epnums[i] = DWC_READ_REG32(addr);
-+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
-+ in_tkn_epnums[i]);
-+ if (addr == &dev_global_regs->dvbusdis) {
-+ addr = &dev_global_regs->dtknqr3_dthrctl;
-+ } else {
-+ ++addr;
-+ }
-+
-+ }
-+
-+ /* Copy the DTKNQR1 data to the bit field. */
-+ dtknqr1.d32 = in_tkn_epnums[0];
-+ if (dtknqr1.b.wrap_bit) {
-+ ndx = dtknqr1.b.intknwptr;
-+ end = ndx -1;
-+ if (end < 0)
-+ end = TOKEN_Q_DEPTH -1;
-+ } else {
-+ ndx = 0;
-+ end = dtknqr1.b.intknwptr -1;
-+ if (end < 0)
-+ end = 0;
-+ }
-+ start = ndx;
-+
-+ /* Fill seqnum[] by initial values: EP number + 31 */
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ seqnum[i] = i +31;
-+ }
-+
-+ /* Fill intkn_seq[] from in_tkn_epnums[0] */
-+ for (i=0; i < 6; i++)
-+ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
-+
-+ if (TOKEN_Q_DEPTH > 6) {
-+ /* Fill intkn_seq[] from in_tkn_epnums[1] */
-+ for (i=6; i < 14; i++)
-+ intkn_seq[i] =
-+ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
-+ }
-+
-+ if (TOKEN_Q_DEPTH > 14) {
-+ /* Fill intkn_seq[] from in_tkn_epnums[1] */
-+ for (i=14; i < 22; i++)
-+ intkn_seq[i] =
-+ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
-+ }
-+
-+ if (TOKEN_Q_DEPTH > 22) {
-+ /* Fill intkn_seq[] from in_tkn_epnums[1] */
-+ for (i=22; i < 30; i++)
-+ intkn_seq[i] =
-+ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
-+ start, end);
-+ for (i=0; i<TOKEN_Q_DEPTH; i++)
-+ DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
-+
-+ /* Update seqnum based on intkn_seq[] */
-+ i = 0;
-+ do {
-+ seqnum[intkn_seq[ndx]] = i;
-+ ndx++;
-+ i++;
-+ if (ndx == TOKEN_Q_DEPTH)
-+ ndx = 0;
-+ } while ( i < TOKEN_Q_DEPTH );
-+
-+ /* Mark non active EP's in seqnum[] by 0xff */
-+ for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
-+ if (core_if->nextep_seq[i] == 0xff )
-+ seqnum[i] = 0xff;
-+ }
-+
-+ /* Sort seqnum[] */
-+ sort_done = 0;
-+ while (!sort_done) {
-+ sort_done = 1;
-+ for (i=0; i<core_if->dev_if->num_in_eps; i++) {
-+ if (seqnum[i] > seqnum[i+1]) {
-+ temp = seqnum[i];
-+ seqnum[i] = seqnum[i+1];
-+ seqnum[i+1] = temp;
-+ sort_done = 0;
-+ }
-+ }
-+ }
-+
-+ ndx = start + seqnum[0];
-+ if (ndx >= TOKEN_Q_DEPTH)
-+ ndx = ndx % TOKEN_Q_DEPTH;
-+ core_if->first_in_nextep_seq = intkn_seq[ndx];
-+
-+ /* Update seqnum[] by EP numbers */
-+ for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
-+ ndx = start + i;
-+ if (seqnum[i] < 31) {
-+ ndx = start + seqnum[i];
-+ if (ndx >= TOKEN_Q_DEPTH)
-+ ndx = ndx % TOKEN_Q_DEPTH;
-+ seqnum[i] = intkn_seq[ndx];
-+ } else {
-+ if (seqnum[i] < 0xff) {
-+ seqnum[i] = seqnum[i] - 31;
-+ } else {
-+ break;
-+ }
-+ }
-+ }
-+
-+ /* Update nextep_seq[] based on seqnum[] */
-+ for (i=0; i<core_if->dev_if->num_in_eps; i++) {
-+ if (seqnum[i] != 0xff) {
-+ if (seqnum[i+1] != 0xff) {
-+ core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
-+ } else {
-+ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
-+ break;
-+ }
-+ } else {
-+ break;
-+ }
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
-+ }
-+
-+ /* Flush the Learning Queue */
-+ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
-+ resetctl.b.intknqflsh = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+
-+}
-+
-+/**
-+ * handle the IN EP disable interrupt.
-+ */
-+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ deptsiz_data_t dieptsiz = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ gintmsk_data_t gintmsk_data;
-+ depctl_data_t depctl;
-+ uint32_t diepdma;
-+ uint32_t remain_to_transfer = 0;
-+ uint8_t i;
-+ uint32_t xfer_size;
-+
-+ ep = get_in_ep(pcd, epnum);
-+ dwc_ep = &ep->dwc_ep;
-+
-+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
-+ complete_ep(ep);
-+ return;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+
-+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
-+ dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
-+
-+ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
-+ if (ep->stopped) {
-+ if (core_if->en_multiple_tx_fifo)
-+ /* Flush the Tx FIFO */
-+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
-+ /* Clear the Global IN NP NAK */
-+ dctl.d32 = 0;
-+ dctl.b.cgnpinnak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+ /* Restart the transaction */
-+ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
-+ restart_transfer(pcd, epnum);
-+ }
-+ } else {
-+ /* Restart the transaction */
-+ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
-+ restart_transfer(pcd, epnum);
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
-+ }
-+ return;
-+ }
-+
-+ if (core_if->start_predict > 2) { // NP IN EP
-+ core_if->start_predict--;
-+ return;
-+ }
-+
-+ core_if->start_predict--;
-+
-+ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
-+
-+ predict_nextep_seq(core_if);
-+
-+ /* Update all active IN EP's NextEP field based of nextep_seq[] */
-+ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
-+ depctl.b.nextep = core_if->nextep_seq[i];
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+ }
-+ }
-+ /* Flush Shared NP TxFIFO */
-+ dwc_otg_flush_tx_fifo(core_if, 0);
-+ /* Rewind buffers */
-+ if (!core_if->dma_desc_enable) {
-+ i = core_if->first_in_nextep_seq;
-+ do {
-+ ep = get_in_ep(pcd, i);
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
-+ if (xfer_size > ep->dwc_ep.maxxfer)
-+ xfer_size = ep->dwc_ep.maxxfer;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (dieptsiz.b.pktcnt != 0) {
-+ if (xfer_size == 0) {
-+ remain_to_transfer = 0;
-+ } else {
-+ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
-+ remain_to_transfer =
-+ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
-+ } else {
-+ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
-+ + (xfer_size % ep->dwc_ep.maxpacket);
-+ }
-+ }
-+ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
-+ dieptsiz.b.xfersize = remain_to_transfer;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
-+ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
-+ }
-+ i = core_if->nextep_seq[i];
-+ } while (i != core_if->first_in_nextep_seq);
-+ } else { // dma_desc_enable
-+ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
-+ }
-+
-+ /* Restart transfers in predicted sequences */
-+ i = core_if->first_in_nextep_seq;
-+ do {
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (dieptsiz.b.pktcnt != 0) {
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+ }
-+ i = core_if->nextep_seq[i];
-+ } while (i != core_if->first_in_nextep_seq);
-+
-+ /* Clear the global non-periodic IN NAK handshake */
-+ dctl.d32 = 0;
-+ dctl.b.cgnpinnak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+ /* Unmask EP Mismatch interrupt */
-+ gintmsk_data.d32 = 0;
-+ gintmsk_data.b.epmismatch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
-+
-+ core_if->start_predict = 0;
-+
-+ }
-+}
-+
-+/**
-+ * Handler for the IN EP timeout handshake interrupt.
-+ */
-+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+
-+#ifdef DEBUG
-+ deptsiz_data_t dieptsiz = {.d32 = 0 };
-+ uint32_t num = 0;
-+#endif
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ ep = get_in_ep(pcd, epnum);
-+
-+ /* Disable the NP Tx Fifo Empty Interrrupt */
-+ if (!core_if->dma_enable) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+ }
-+ /** @todo NGS Check EP type.
-+ * Implement for Periodic EPs */
-+ /*
-+ * Non-periodic EP
-+ */
-+ /* Enable the Global IN NAK Effective Interrupt */
-+ intr_mask.b.ginnakeff = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
-+
-+ /* Set Global IN NAK */
-+ dctl.b.sgnpinnak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+ ep->stopped = 1;
-+
-+#ifdef DEBUG
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
-+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
-+ dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
-+#endif
-+
-+#ifdef DISABLE_PERIODIC_EP
-+ /*
-+ * Set the NAK bit for this EP to
-+ * start the disable process.
-+ */
-+ diepctl.d32 = 0;
-+ diepctl.b.snak = 1;
-+ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
-+ diepctl.d32);
-+ ep->disabling = 1;
-+ ep->stopped = 1;
-+#endif
-+}
-+
-+/**
-+ * Handler for the IN EP NAK interrupt.
-+ */
-+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ diepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.nak = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ diepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP Babble interrupt.
-+ */
-+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
-+ "OUT EP Babble");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.babble = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP NAK interrupt.
-+ */
-+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.nak = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP NYET interrupt.
-+ */
-+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.nyet = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that an IN EP has a pending Interrupt.
-+ * The sequence for handling the IN EP interrupt is shown below:
-+ * -# Read the Device All Endpoint Interrupt register
-+ * -# Repeat the following for each IN EP interrupt bit set (from
-+ * LSB to MSB).
-+ * -# Read the Device Endpoint Interrupt (DIEPINTn) register
-+ * -# If "Transfer Complete" call the request complete function
-+ * -# If "Endpoint Disabled" complete the EP disable procedure.
-+ * -# If "AHB Error Interrupt" log error
-+ * -# If "Time-out Handshake" log error
-+ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
-+ * FIFO.
-+ * -# If "IN Token EP Mismatch" (disable, this is handled by EP
-+ * Mismatch Interrupt)
-+ */
-+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
-+{
-+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
-+do { \
-+ diepint_data_t diepint = {.d32=0}; \
-+ diepint.b.__intr = 1; \
-+ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
-+ diepint.d32); \
-+} while (0)
-+
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ diepint_data_t diepint = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ uint32_t ep_intr;
-+ uint32_t epnum = 0;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
-+
-+ /* Read in the device interrupt bits */
-+ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
-+
-+ /* Service the Device IN interrupts for each endpoint */
-+ while (ep_intr) {
-+ if (ep_intr & 0x1) {
-+ uint32_t empty_msk;
-+ /* Get EP pointer */
-+ ep = get_in_ep(pcd, epnum);
-+ dwc_ep = &ep->dwc_ep;
-+
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+ empty_msk =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->dtknqr4_fifoemptymsk);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
-+ epnum, empty_msk, depctl.d32);
-+
-+ DWC_DEBUGPL(DBG_PCD,
-+ "EP%d-%s: type=%d, mps=%d\n",
-+ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
-+ dwc_ep->type, dwc_ep->maxpacket);
-+
-+ diepint.d32 =
-+ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP %d Interrupt Register - 0x%x\n", epnum,
-+ diepint.d32);
-+ /* Transfer complete */
-+ if (diepint.b.xfercompl) {
-+ /* Disable the NP Tx FIFO Empty
-+ * Interrupt */
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32
-+ (&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+ } else {
-+ /* Disable the Tx FIFO Empty Interrupt for this EP */
-+ uint32_t fifoemptymsk =
-+ 0x1 << dwc_ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ fifoemptymsk, 0);
-+ }
-+ /* Clear the bit in DIEPINTn for this interrupt */
-+ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
-+
-+ /* Complete the transfer */
-+ if (epnum == 0) {
-+ handle_ep0(pcd);
-+ }
-+#ifdef DWC_EN_ISOC
-+ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (!ep->stopped)
-+ complete_iso_ep(pcd, ep);
-+ }
-+#endif /* DWC_EN_ISOC */
-+#ifdef DWC_UTE_PER_IO
-+ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (!ep->stopped)
-+ complete_xiso_ep(ep);
-+ }
-+#endif /* DWC_UTE_PER_IO */
-+ else {
-+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
-+ dwc_ep->bInterval > 1) {
-+ dwc_ep->frame_num += dwc_ep->bInterval;
-+ if (dwc_ep->frame_num > 0x3FFF)
-+ {
-+ dwc_ep->frm_overrun = 1;
-+ dwc_ep->frame_num &= 0x3FFF;
-+ } else
-+ dwc_ep->frm_overrun = 0;
-+ }
-+ complete_ep(ep);
-+ if(diepint.b.nak)
-+ CLEAR_IN_EP_INTR(core_if, epnum, nak);
-+ }
-+ }
-+ /* Endpoint disable */
-+ if (diepint.b.epdisabled) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
-+ epnum);
-+ handle_in_ep_disable_intr(pcd, epnum);
-+
-+ /* Clear the bit in DIEPINTn for this interrupt */
-+ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
-+ }
-+ /* AHB Error */
-+ if (diepint.b.ahberr) {
-+ DWC_ERROR("EP%d IN AHB Error\n", epnum);
-+ /* Clear the bit in DIEPINTn for this interrupt */
-+ CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
-+ }
-+ /* TimeOUT Handshake (non-ISOC IN EPs) */
-+ if (diepint.b.timeout) {
-+ DWC_ERROR("EP%d IN Time-out\n", epnum);
-+ handle_in_ep_timeout_intr(pcd, epnum);
-+
-+ CLEAR_IN_EP_INTR(core_if, epnum, timeout);
-+ }
-+ /** IN Token received with TxF Empty */
-+ if (diepint.b.intktxfemp) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d IN TKN TxFifo Empty\n",
-+ epnum);
-+ if (!ep->stopped && epnum != 0) {
-+
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.intktxfemp = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32
-+ (&dev_if->dev_global_regs->diepeachintmsk
-+ [epnum], diepmsk.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32
-+ (&dev_if->dev_global_regs->diepmsk,
-+ diepmsk.d32, 0);
-+ }
-+ } else if (core_if->dma_desc_enable
-+ && epnum == 0
-+ && pcd->ep0state ==
-+ EP0_OUT_STATUS_PHASE) {
-+ // EP0 IN set STALL
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs
-+ [epnum]->diepctl);
-+
-+ /* set the disable and stall bits */
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ }
-+ depctl.b.stall = 1;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs
-+ [epnum]->diepctl,
-+ depctl.d32);
-+ }
-+ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
-+ }
-+ /** IN Token Received with EP mismatch */
-+ if (diepint.b.intknepmis) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d IN TKN EP Mismatch\n", epnum);
-+ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
-+ }
-+ /** IN Endpoint NAK Effective */
-+ if (diepint.b.inepnakeff) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d IN EP NAK Effective\n",
-+ epnum);
-+ /* Periodic EP */
-+ if (ep->disabling) {
-+ depctl.d32 = 0;
-+ depctl.b.snak = 1;
-+ depctl.b.epdis = 1;
-+ DWC_MODIFY_REG32(&dev_if->in_ep_regs
-+ [epnum]->diepctl,
-+ depctl.d32,
-+ depctl.d32);
-+ }
-+ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
-+
-+ }
-+
-+ /** IN EP Tx FIFO Empty Intr */
-+ if (diepint.b.emptyintr) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d Tx FIFO Empty Intr \n",
-+ epnum);
-+ write_empty_tx_fifo(pcd, epnum);
-+
-+ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
-+
-+ }
-+
-+ /** IN EP BNA Intr */
-+ if (diepint.b.bna) {
-+ CLEAR_IN_EP_INTR(core_if, epnum, bna);
-+ if (core_if->dma_desc_enable) {
-+#ifdef DWC_EN_ISOC
-+ if (dwc_ep->type ==
-+ DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * This checking is performed to prevent first "false" BNA
-+ * handling occuring right after reconnect
-+ */
-+ if (dwc_ep->next_frame !=
-+ 0xffffffff)
-+ dwc_otg_pcd_handle_iso_bna(ep);
-+ } else
-+#endif /* DWC_EN_ISOC */
-+ {
-+ dwc_otg_pcd_handle_noniso_bna(ep);
-+ }
-+ }
-+ }
-+ /* NAK Interrutp */
-+ if (diepint.b.nak) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
-+ epnum);
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ depctl_data_t depctl;
-+ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
-+ ep->dwc_ep.frame_num = core_if->frame_num;
-+ if (ep->dwc_ep.bInterval > 1) {
-+ depctl.d32 = 0;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+ if (ep->dwc_ep.frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ depctl.b.setd0pid = 0;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ depctl.b.setd1pid = 0;
-+ }
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
-+ }
-+ start_next_request(ep);
-+ }
-+ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
-+ if (dwc_ep->frame_num > 0x3FFF) {
-+ dwc_ep->frm_overrun = 1;
-+ dwc_ep->frame_num &= 0x3FFF;
-+ } else
-+ dwc_ep->frm_overrun = 0;
-+ }
-+
-+ CLEAR_IN_EP_INTR(core_if, epnum, nak);
-+ }
-+ }
-+ epnum++;
-+ ep_intr >>= 1;
-+ }
-+
-+ return 1;
-+#undef CLEAR_IN_EP_INTR
-+}
-+
-+/**
-+ * This interrupt indicates that an OUT EP has a pending Interrupt.
-+ * The sequence for handling the OUT EP interrupt is shown below:
-+ * -# Read the Device All Endpoint Interrupt register
-+ * -# Repeat the following for each OUT EP interrupt bit set (from
-+ * LSB to MSB).
-+ * -# Read the Device Endpoint Interrupt (DOEPINTn) register
-+ * -# If "Transfer Complete" call the request complete function
-+ * -# If "Endpoint Disabled" complete the EP disable procedure.
-+ * -# If "AHB Error Interrupt" log error
-+ * -# If "Setup Phase Done" process Setup Packet (See Standard USB
-+ * Command Processing)
-+ */
-+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
-+{
-+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
-+do { \
-+ doepint_data_t doepint = {.d32=0}; \
-+ doepint.b.__intr = 1; \
-+ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
-+ doepint.d32); \
-+} while (0)
-+
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ uint32_t ep_intr;
-+ doepint_data_t doepint = {.d32 = 0 };
-+ uint32_t epnum = 0;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ dctl_data_t dctl = {.d32 = 0 };
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
-+
-+ /* Read in the device interrupt bits */
-+ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
-+
-+ while (ep_intr) {
-+ if (ep_intr & 0x1) {
-+ /* Get EP pointer */
-+ ep = get_out_ep(pcd, epnum);
-+ dwc_ep = &ep->dwc_ep;
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP%d-%s: type=%d, mps=%d\n",
-+ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
-+ dwc_ep->type, dwc_ep->maxpacket);
-+#endif
-+ doepint.d32 =
-+ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
-+ /* Moved this interrupt upper due to core deffect of asserting
-+ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
-+ if (doepint.b.stsphsercvd) {
-+ deptsiz0_data_t deptsiz;
-+ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doeptsiz);
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a
-+ && core_if->dma_enable
-+ && core_if->dma_desc_enable == 0
-+ && doepint.b.xfercompl
-+ && deptsiz.b.xfersize == 24) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum,
-+ xfercompl);
-+ doepint.b.xfercompl = 0;
-+ ep0_out_start(core_if, pcd);
-+ }
-+ if ((core_if->dma_desc_enable) ||
-+ (core_if->dma_enable
-+ && core_if->snpsid >=
-+ OTG_CORE_REV_3_00a)) {
-+ do_setup_in_status_phase(pcd);
-+ }
-+ }
-+ /* Transfer complete */
-+ if (doepint.b.xfercompl) {
-+
-+ if (epnum == 0) {
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
-+ doepint.d32);
-+ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
-+
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a
-+ && core_if->dma_enable == 0) {
-+ doepint_data_t doepint;
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doepint);
-+ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+ goto exit_xfercompl;
-+ }
-+ }
-+ /* In case of DDMA look at SR bit to go to the Data Stage */
-+ if (core_if->dma_desc_enable) {
-+ dev_dma_desc_sts_t status = {.d32 = 0};
-+ if (pcd->ep0state == EP0_IDLE) {
-+ status.d32 = core_if->dev_if->setup_desc_addr[core_if->
-+ dev_if->setup_desc_index]->status.d32;
-+ if(pcd->data_terminated) {
-+ pcd->data_terminated = 0;
-+ status.d32 = core_if->dev_if->out_desc_addr->status.d32;
-+ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
-+ }
-+ if (status.b.sr) {
-+ if (doepint.b.setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
-+ /* Already started data stage, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ /* Prepare for more setup packets */
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
-+ pcd->ep0state == EP0_IN_DATA_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP0_IDLE SR=1 setup=0 new setup comes\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+ } else {
-+ dwc_otg_pcd_request_t *req;
-+ dev_dma_desc_sts_t status = {.d32 = 0};
-+ diepint_data_t diepint0;
-+ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+
-+ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
-+ DWC_ERROR("EP0 is stalled/disconnected\n");
-+ }
-+
-+ /* Clear IN xfercompl if set */
-+ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
-+ || pcd->ep0state == EP0_IN_DATA_PHASE)) {
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint, diepint0.d32);
-+ }
-+
-+ status.d32 = core_if->dev_if->setup_desc_addr[core_if->
-+ dev_if->setup_desc_index]->status.d32;
-+
-+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
-+ && (pcd->ep0state == EP0_OUT_DATA_PHASE))
-+ status.d32 = core_if->dev_if->out_desc_addr->status.d32;
-+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
-+ status.d32 = core_if->dev_if->
-+ out_desc_addr->status.d32;
-+
-+ if (status.b.sr) {
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
-+ } else {
-+ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
-+ pcd->ep0state == EP0_OUT_DATA_PHASE) {
-+ /* Read arrived setup packet from req->buf */
-+ dwc_memcpy(&pcd->setup_pkt->req,
-+ req->buf + ep->dwc_ep.xfer_count, 8);
-+ }
-+ req->actual = ep->dwc_ep.xfer_count;
-+ dwc_otg_request_done(ep, req, -ECONNRESET);
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+ }
-+ pcd->ep0state = EP0_IDLE;
-+ if (doepint.b.setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
-+ /* Data stage started, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ /* Prepare for setup packets if ep0in was enabled*/
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+ }
-+ }
-+ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
-+ && core_if->dma_desc_enable == 0) {
-+ doepint_data_t doepint_temp = {.d32 = 0};
-+ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->dwc_ep.num]->doepint);
-+ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->dwc_ep.num]->doeptsiz);
-+ if (pcd->ep0state == EP0_IDLE) {
-+ if (doepint_temp.b.sr) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+ }
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doepint);
-+ if (doeptsize0.b.supcnt == 3) {
-+ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
-+ ep->dwc_ep.stp_rollover = 1;
-+ }
-+ if (doepint.b.setup) {
-+retry:
-+ /* Already started data stage, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ ep->dwc_ep.stp_rollover = 0;
-+ /* Prepare for more setup packets */
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
-+ pcd->ep0state == EP0_IN_DATA_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP0_IDLE SR=1 setup=0 new setup comes\n");
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doepint);
-+ if(doepint.b.setup)
-+ goto retry;
-+ ep0_out_start(core_if, pcd);
-+ }
-+ } else {
-+ dwc_otg_pcd_request_t *req;
-+ diepint_data_t diepint0 = {.d32 = 0};
-+ doepint_data_t doepint_temp = {.d32 = 0};
-+ depctl_data_t diepctl0;
-+ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepctl);
-+
-+ if (pcd->ep0state == EP0_IN_DATA_PHASE
-+ || pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ if (diepint0.b.xfercompl) {
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint, diepint0.d32);
-+ }
-+ if (diepctl0.b.epena) {
-+ diepint_data_t diepint = {.d32 = 0};
-+ diepctl0.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepctl, diepctl0.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+ } while (!diepint.b.inepnakeff);
-+ diepint.b.inepnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint, diepint.d32);
-+ diepctl0.d32 = 0;
-+ diepctl0.b.epdis = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
-+ diepctl0.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+ } while (!diepint.b.epdisabled);
-+ diepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
-+ diepint.d32);
-+ }
-+ }
-+ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->dwc_ep.num]->doepint);
-+ if (doepint_temp.b.sr) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
-+ } else {
-+ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
-+ pcd->ep0state == EP0_OUT_DATA_PHASE) {
-+ /* Read arrived setup packet from req->buf */
-+ dwc_memcpy(&pcd->setup_pkt->req,
-+ req->buf + ep->dwc_ep.xfer_count, 8);
-+ }
-+ req->actual = ep->dwc_ep.xfer_count;
-+ dwc_otg_request_done(ep, req, -ECONNRESET);
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+ }
-+ pcd->ep0state = EP0_IDLE;
-+ if (doepint.b.setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
-+ /* Data stage started, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ /* Prepare for setup packets if ep0in was enabled*/
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+ }
-+ }
-+ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
-+ handle_ep0(pcd);
-+exit_xfercompl:
-+ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
-+ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
-+ } else {
-+ if (core_if->dma_desc_enable == 0
-+ || pcd->ep0state != EP0_IDLE)
-+ handle_ep0(pcd);
-+ }
-+#ifdef DWC_EN_ISOC
-+ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (doepint.b.pktdrpsts == 0) {
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if,
-+ epnum,
-+ xfercompl);
-+ complete_iso_ep(pcd, ep);
-+ } else {
-+
-+ doepint_data_t doepint = {.d32 = 0 };
-+ doepint.b.xfercompl = 1;
-+ doepint.b.pktdrpsts = 1;
-+ DWC_WRITE_REG32
-+ (&core_if->dev_if->out_ep_regs
-+ [epnum]->doepint,
-+ doepint.d32);
-+ if (handle_iso_out_pkt_dropped
-+ (core_if, dwc_ep)) {
-+ complete_iso_ep(pcd,
-+ ep);
-+ }
-+ }
-+#endif /* DWC_EN_ISOC */
-+#ifdef DWC_UTE_PER_IO
-+ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
-+ if (!ep->stopped)
-+ complete_xiso_ep(ep);
-+#endif /* DWC_UTE_PER_IO */
-+ } else {
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if, epnum,
-+ xfercompl);
-+
-+ if (core_if->core_params->dev_out_nak) {
-+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
-+ pcd->core_if->ep_xfer_info[epnum].state = 0;
-+#ifdef DEBUG
-+ print_memory_payload(pcd, dwc_ep);
-+#endif
-+ }
-+ complete_ep(ep);
-+ }
-+
-+ }
-+
-+ /* Endpoint disable */
-+ if (doepint.b.epdisabled) {
-+
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
-+ if (core_if->core_params->dev_out_nak) {
-+#ifdef DEBUG
-+ print_memory_payload(pcd, dwc_ep);
-+#endif
-+ /* In case of timeout condition */
-+ if (core_if->ep_xfer_info[epnum].state == 2) {
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dctl);
-+ dctl.b.cgoutnak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+ /* Unmask goutnakeff interrupt which was masked
-+ * during handle nak out interrupt */
-+ gintmsk.b.goutnakeff = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ 0, gintmsk.d32);
-+
-+ complete_ep(ep);
-+ }
-+ }
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
-+ {
-+ dctl_data_t dctl;
-+ gintmsk_data_t intr_mask = {.d32 = 0};
-+ dwc_otg_pcd_request_t *req = 0;
-+
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dctl);
-+ dctl.b.cgoutnak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+
-+ intr_mask.d32 = 0;
-+ intr_mask.b.incomplisoout = 1;
-+
-+ /* Get any pending requests */
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (!req) {
-+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+ } else {
-+ dwc_otg_request_done(ep, req, 0);
-+ start_next_request(ep);
-+ }
-+ } else {
-+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+ }
-+ }
-+ }
-+ /* AHB Error */
-+ if (doepint.b.ahberr) {
-+ DWC_ERROR("EP%d OUT AHB Error\n", epnum);
-+ DWC_ERROR("EP%d DEPDMA=0x%08x \n",
-+ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
-+ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
-+ }
-+ /* Setup Phase Done (contorl EPs) */
-+ if (doepint.b.setup) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
-+#endif
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+
-+ handle_ep0(pcd);
-+ }
-+
-+ /** OUT EP BNA Intr */
-+ if (doepint.b.bna) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, bna);
-+ if (core_if->dma_desc_enable) {
-+#ifdef DWC_EN_ISOC
-+ if (dwc_ep->type ==
-+ DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * This checking is performed to prevent first "false" BNA
-+ * handling occuring right after reconnect
-+ */
-+ if (dwc_ep->next_frame !=
-+ 0xffffffff)
-+ dwc_otg_pcd_handle_iso_bna(ep);
-+ } else
-+#endif /* DWC_EN_ISOC */
-+ {
-+ dwc_otg_pcd_handle_noniso_bna(ep);
-+ }
-+ }
-+ }
-+ /* Babble Interrupt */
-+ if (doepint.b.babble) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
-+ epnum);
-+ handle_out_ep_babble_intr(pcd, epnum);
-+
-+ CLEAR_OUT_EP_INTR(core_if, epnum, babble);
-+ }
-+ if (doepint.b.outtknepdis) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
-+ disabled\n",epnum);
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ doepmsk_data_t doepmsk = {.d32 = 0};
-+ ep->dwc_ep.frame_num = core_if->frame_num;
-+ if (ep->dwc_ep.bInterval > 1) {
-+ depctl_data_t depctl;
-+ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[epnum]->doepctl);
-+ if (ep->dwc_ep.frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ depctl.b.setd0pid = 0;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ depctl.b.setd1pid = 0;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ out_ep_regs[epnum]->doepctl, depctl.d32);
-+ }
-+ start_next_request(ep);
-+ doepmsk.b.outtknepdis = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ doepmsk.d32, 0);
-+ }
-+ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
-+ }
-+
-+ /* NAK Interrutp */
-+ if (doepint.b.nak) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
-+ handle_out_ep_nak_intr(pcd, epnum);
-+
-+ CLEAR_OUT_EP_INTR(core_if, epnum, nak);
-+ }
-+ /* NYET Interrutp */
-+ if (doepint.b.nyet) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
-+ handle_out_ep_nyet_intr(pcd, epnum);
-+
-+ CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
-+ }
-+ }
-+
-+ epnum++;
-+ ep_intr >>= 1;
-+ }
-+
-+ return 1;
-+
-+#undef CLEAR_OUT_EP_INTR
-+}
-+static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
-+{
-+ int retval = 0;
-+ if(!frm_overrun && curr_fr >= trgt_fr)
-+ retval = 1;
-+ else if (frm_overrun
-+ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
-+ retval = 1;
-+ return retval;
-+}
-+/**
-+ * Incomplete ISO IN Transfer Interrupt.
-+ * This interrupt indicates one of the following conditions occurred
-+ * while transmitting an ISOC transaction.
-+ * - Corrupted IN Token for ISOC EP.
-+ * - Packet not complete in FIFO.
-+ * The follow actions will be taken:
-+ * -# Determine the EP
-+ * -# Set incomplete flag in dwc_ep structure
-+ * -# Disable EP; when "Endpoint Disabled" interrupt is received
-+ * Flush FIFO
-+ */
-+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+
-+#ifdef DWC_EN_ISOC
-+ dwc_otg_dev_if_t *dev_if;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dsts_data_t dsts = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep;
-+ int i;
-+
-+ dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+ for (i = 1; i <= dev_if->num_in_eps; ++i) {
-+ dwc_ep = &pcd->in_ep[i].dwc_ep;
-+ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+
-+ if (depctl.b.epdis && deptsiz.d32) {
-+ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+
-+ dsts.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ dev_global_regs->dsts);
-+ dwc_ep->next_frame = dsts.b.soffn;
-+
-+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
-+ (pcd),
-+ dwc_ep);
-+ }
-+ }
-+ }
-+
-+#else
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep;
-+ dwc_otg_dev_if_t *dev_if;
-+ int i;
-+ dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
-+
-+ for (i = 1; i <= dev_if->num_in_eps; ++i) {
-+ dwc_ep = &pcd->in_ep[i-1].dwc_ep;
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
-+ dwc_ep->frm_overrun))
-+ {
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ depctl.b.snak = 1;
-+ depctl.b.epdis = 1;
-+ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
-+ }
-+ }
-+ }
-+
-+ /*intr_mask.b.incomplisoin = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0); */
-+#endif //DWC_EN_ISOC
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.incomplisoin = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Incomplete ISO OUT Transfer Interrupt.
-+ *
-+ * This interrupt indicates that the core has dropped an ISO OUT
-+ * packet. The following conditions can be the cause:
-+ * - FIFO Full, the entire packet would not fit in the FIFO.
-+ * - CRC Error
-+ * - Corrupted Token
-+ * The follow actions will be taken:
-+ * -# Determine the EP
-+ * -# Set incomplete flag in dwc_ep structure
-+ * -# Read any data from the FIFO
-+ * -# Disable EP. When "Endpoint Disabled" interrupt is received
-+ * re-enable EP.
-+ */
-+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
-+{
-+
-+ gintsts_data_t gintsts;
-+
-+#ifdef DWC_EN_ISOC
-+ dwc_otg_dev_if_t *dev_if;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dsts_data_t dsts = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep;
-+ int i;
-+
-+ dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+ for (i = 1; i <= dev_if->num_out_eps; ++i) {
-+ dwc_ep = &pcd->in_ep[i].dwc_ep;
-+ if (pcd->out_ep[i].dwc_ep.active &&
-+ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+
-+ if (depctl.b.epdis && deptsiz.d32) {
-+ set_current_pkt_info(GET_CORE_IF(pcd),
-+ &pcd->out_ep[i].dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+
-+ dsts.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ dev_global_regs->dsts);
-+ dwc_ep->next_frame = dsts.b.soffn;
-+
-+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
-+ (pcd),
-+ dwc_ep);
-+ }
-+ }
-+ }
-+#else
-+ /** @todo implement ISR */
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep = NULL;
-+ int i;
-+ core_if = GET_CORE_IF(pcd);
-+
-+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ dwc_ep = &pcd->out_ep[i].dwc_ep;
-+ depctl.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
-+ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
-+ core_if->dev_if->isoc_ep = dwc_ep;
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
-+ break;
-+ }
-+ }
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+ if (!intr_mask.b.goutnakeff) {
-+ /* Unmask it */
-+ intr_mask.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
-+ }
-+ if (!gintsts.b.goutnakeff) {
-+ dctl.b.sgoutnak = 1;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+
-+ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
-+
-+ intr_mask.d32 = 0;
-+ intr_mask.b.incomplisoout = 1;
-+
-+#endif /* DWC_EN_ISOC */
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.incomplisoout = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function handles the Global IN NAK Effective interrupt.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ depctl_data_t diepctl = {.d32 = 0 };
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ int i;
-+
-+ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
-+
-+ /* Disable all active IN EPs */
-+ for (i = 0; i <= dev_if->num_in_eps; i++) {
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
-+ if (core_if->start_predict > 0)
-+ core_if->start_predict++;
-+ diepctl.b.epdis = 1;
-+ diepctl.b.snak = 1;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
-+ }
-+ }
-+
-+
-+ /* Disable the Global IN NAK Effective Interrupt */
-+ intr_mask.b.ginnakeff = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.ginnakeff = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * OUT NAK Effective.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ depctl_data_t doepctl;
-+ int i;
-+
-+ /* Disable the Global OUT NAK Effective Interrupt */
-+ intr_mask.b.goutnakeff = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* If DEV OUT NAK enabled*/
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ /* Run over all out endpoints to determine the ep number on
-+ * which the timeout has happened
-+ */
-+ for (i = 0; i <= dev_if->num_out_eps; i++) {
-+ if ( pcd->core_if->ep_xfer_info[i].state == 2 )
-+ break;
-+ }
-+ if (i > dev_if->num_out_eps) {
-+ dctl_data_t dctl;
-+ dctl.d32 =
-+ DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
-+ dctl.b.cgoutnak = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+ goto out;
-+ }
-+
-+ /* Disable the endpoint */
-+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+ if (doepctl.b.epena) {
-+ doepctl.b.epdis = 1;
-+ doepctl.b.snak = 1;
-+ }
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
-+ return 1;
-+ }
-+ /* We come here from Incomplete ISO OUT handler */
-+ if (dev_if->isoc_ep) {
-+ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
-+ uint32_t epnum = dwc_ep->num;
-+ doepint_data_t doepint;
-+ doepint.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
-+ dev_if->isoc_ep = NULL;
-+ doepctl.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
-+ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
-+ if (doepctl.b.epena) {
-+ doepctl.b.epdis = 1;
-+ doepctl.b.snak = 1;
-+ }
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
-+ doepctl.d32);
-+ return 1;
-+ } else
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
-+ "Global OUT NAK Effective\n");
-+
-+out:
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * PCD interrupt handler.
-+ *
-+ * The PCD handles the device interrupts. Many conditions can cause a
-+ * device interrupt. When an interrupt occurs, the device interrupt
-+ * service routine determines the cause of the interrupt and
-+ * dispatches handling to the appropriate function. These interrupt
-+ * handling functions are described below.
-+ *
-+ * All interrupt registers are processed from LSB to MSB.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+#ifdef VERBOSE
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+#endif
-+ gintsts_data_t gintr_status;
-+ int32_t retval = 0;
-+
-+ /* Exit from ISR if core is hibernated */
-+ if (core_if->hibernation_suspend == 1) {
-+ return retval;
-+ }
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
-+ __func__,
-+ DWC_READ_REG32(&global_regs->gintsts),
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+#endif
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_SPINLOCK(pcd->lock);
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
-+ __func__,
-+ DWC_READ_REG32(&global_regs->gintsts),
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+#endif
-+
-+ gintr_status.d32 = dwc_otg_read_core_intr(core_if);
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
-+ __func__, gintr_status.d32);
-+
-+ if (gintr_status.b.sofintr) {
-+ retval |= dwc_otg_pcd_handle_sof_intr(pcd);
-+ }
-+ if (gintr_status.b.rxstsqlvl) {
-+ retval |=
-+ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
-+ }
-+ if (gintr_status.b.nptxfempty) {
-+ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
-+ }
-+ if (gintr_status.b.goutnakeff) {
-+ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
-+ }
-+ if (gintr_status.b.i2cintr) {
-+ retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
-+ }
-+ if (gintr_status.b.erlysuspend) {
-+ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
-+ }
-+ if (gintr_status.b.usbreset) {
-+ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
-+ }
-+ if (gintr_status.b.enumdone) {
-+ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
-+ }
-+ if (gintr_status.b.isooutdrop) {
-+ retval |=
-+ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
-+ (pcd);
-+ }
-+ if (gintr_status.b.eopframe) {
-+ retval |=
-+ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
-+ }
-+ if (gintr_status.b.inepint) {
-+ if (!core_if->multiproc_int_enable) {
-+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
-+ }
-+ }
-+ if (gintr_status.b.outepintr) {
-+ if (!core_if->multiproc_int_enable) {
-+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
-+ }
-+ }
-+ if (gintr_status.b.epmismatch) {
-+ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
-+ }
-+ if (gintr_status.b.fetsusp) {
-+ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
-+ }
-+ if (gintr_status.b.ginnakeff) {
-+ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
-+ }
-+ if (gintr_status.b.incomplisoin) {
-+ retval |=
-+ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
-+ }
-+ if (gintr_status.b.incomplisoout) {
-+ retval |=
-+ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
-+ }
-+
-+ /* In MPI mode Device Endpoints interrupts are asserted
-+ * without setting outepintr and inepint bits set, so these
-+ * Interrupt handlers are called without checking these bit-fields
-+ */
-+ if (core_if->multiproc_int_enable) {
-+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
-+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
-+ }
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
-+ DWC_READ_REG32(&global_regs->gintsts));
-+#endif
-+ DWC_SPINUNLOCK(pcd->lock);
-+ }
-+ return retval;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2015-03-09 10:39:33.218893718 +0100
-@@ -0,0 +1,1360 @@
-+ /* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
-+ * $Revision: #21 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+/** @file
-+ * This file implements the Peripheral Controller Driver.
-+ *
-+ * The Peripheral Controller Driver (PCD) is responsible for
-+ * translating requests from the Function Driver into the appropriate
-+ * actions on the DWC_otg controller. It isolates the Function Driver
-+ * from the specifics of the controller by providing an API to the
-+ * Function Driver.
-+ *
-+ * The Peripheral Controller Driver for Linux will implement the
-+ * Gadget API, so that the existing Gadget drivers can be used.
-+ * (Gadget Driver is the Linux terminology for a Function Driver.)
-+ *
-+ * The Linux Gadget API is defined in the header file
-+ * <code><linux/usb_gadget.h></code>. The USB EP operations API is
-+ * defined in the structure <code>usb_ep_ops</code> and the USB
-+ * Controller API is defined in the structure
-+ * <code>usb_gadget_ops</code>.
-+ *
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_dbg.h"
-+
-+extern bool fiq_enable;
-+
-+static struct gadget_wrapper {
-+ dwc_otg_pcd_t *pcd;
-+
-+ struct usb_gadget gadget;
-+ struct usb_gadget_driver *driver;
-+
-+ struct usb_ep ep0;
-+ struct usb_ep in_ep[16];
-+ struct usb_ep out_ep[16];
-+
-+} *gadget_wrapper;
-+
-+/* Display the contents of the buffer */
-+extern void dump_msg(const u8 * buf, unsigned int length);
-+/**
-+ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
-+ * if the endpoint is not found
-+ */
-+static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
-+{
-+ int i;
-+ if (pcd->ep0.priv == handle) {
-+ return &pcd->ep0;
-+ }
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
-+ if (pcd->in_ep[i].priv == handle)
-+ return &pcd->in_ep[i];
-+ if (pcd->out_ep[i].priv == handle)
-+ return &pcd->out_ep[i];
-+ }
-+
-+ return NULL;
-+}
-+
-+/* USB Endpoint Operations */
-+/*
-+ * The following sections briefly describe the behavior of the Gadget
-+ * API endpoint operations implemented in the DWC_otg driver
-+ * software. Detailed descriptions of the generic behavior of each of
-+ * these functions can be found in the Linux header file
-+ * include/linux/usb_gadget.h.
-+ *
-+ * The Gadget API provides wrapper functions for each of the function
-+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
-+ * function, which then calls the underlying PCD function. The
-+ * following sections are named according to the wrapper
-+ * functions. Within each section, the corresponding DWC_otg PCD
-+ * function name is specified.
-+ *
-+ */
-+
-+/**
-+ * This function is called by the Gadget Driver for each EP to be
-+ * configured for the current configuration (SET_CONFIGURATION).
-+ *
-+ * This function initializes the dwc_otg_ep_t data structure, and then
-+ * calls dwc_otg_ep_activate.
-+ */
-+static int ep_enable(struct usb_ep *usb_ep,
-+ const struct usb_endpoint_descriptor *ep_desc)
-+{
-+ int retval;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
-+
-+ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
-+ DWC_WARN("%s, bad ep or descriptor\n", __func__);
-+ return -EINVAL;
-+ }
-+ if (usb_ep == &gadget_wrapper->ep0) {
-+ DWC_WARN("%s, bad ep(0)\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ /* Check FIFO size? */
-+ if (!ep_desc->wMaxPacketSize) {
-+ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
-+ return -ERANGE;
-+ }
-+
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_WARN("%s, bogus device state\n", __func__);
-+ return -ESHUTDOWN;
-+ }
-+
-+ /* Delete after check - MAS */
-+#if 0
-+ nat = (uint32_t) ep_desc->wMaxPacketSize;
-+ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
-+ nat = (nat >> 11) & 0x03;
-+ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
-+#endif
-+ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
-+ (const uint8_t *)ep_desc,
-+ (void *)usb_ep);
-+ if (retval) {
-+ DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
-+ return -EINVAL;
-+ }
-+
-+ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function is called when an EP is disabled due to disconnect or
-+ * change in configuration. Any pending requests will terminate with a
-+ * status of -ESHUTDOWN.
-+ *
-+ * This function modifies the dwc_otg_ep_t data structure for this EP,
-+ * and then calls dwc_otg_ep_deactivate.
-+ */
-+static int ep_disable(struct usb_ep *usb_ep)
-+{
-+ int retval;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
-+ if (!usb_ep) {
-+ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
-+ usb_ep ? usb_ep->name : NULL);
-+ return -EINVAL;
-+ }
-+
-+ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
-+ if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function allocates a request object to use with the specified
-+ * endpoint.
-+ *
-+ * @param ep The endpoint to be used with with the request
-+ * @param gfp_flags the GFP_* flags to use.
-+ */
-+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
-+ gfp_t gfp_flags)
-+{
-+ struct usb_request *usb_req;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
-+ if (0 == ep) {
-+ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
-+ return 0;
-+ }
-+ usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
-+ if (0 == usb_req) {
-+ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
-+ return 0;
-+ }
-+ memset(usb_req, 0, sizeof(*usb_req));
-+ usb_req->dma = DWC_DMA_ADDR_INVALID;
-+
-+ return usb_req;
-+}
-+
-+/**
-+ * This function frees a request object.
-+ *
-+ * @param ep The endpoint associated with the request
-+ * @param req The request being freed
-+ */
-+static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
-+{
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
-+
-+ if (0 == ep || 0 == req) {
-+ DWC_WARN("%s() %s\n", __func__,
-+ "Invalid ep or req argument!\n");
-+ return;
-+ }
-+
-+ kfree(req);
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+/**
-+ * This function allocates an I/O buffer to be used for a transfer
-+ * to/from the specified endpoint.
-+ *
-+ * @param usb_ep The endpoint to be used with with the request
-+ * @param bytes The desired number of bytes for the buffer
-+ * @param dma Pointer to the buffer's DMA address; must be valid
-+ * @param gfp_flags the GFP_* flags to use.
-+ * @return address of a new buffer or null is buffer could not be allocated.
-+ */
-+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
-+ dma_addr_t * dma, gfp_t gfp_flags)
-+{
-+ void *buf;
-+ dwc_otg_pcd_t *pcd = 0;
-+
-+ pcd = gadget_wrapper->pcd;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
-+ dma, gfp_flags);
-+
-+ /* Check dword alignment */
-+ if ((bytes & 0x3UL) != 0) {
-+ DWC_WARN("%s() Buffer size is not a multiple of"
-+ "DWORD size (%d)", __func__, bytes);
-+ }
-+
-+ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
-+
-+ /* Check dword alignment */
-+ if (((int)buf & 0x3UL) != 0) {
-+ DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
-+ __func__, buf);
-+ }
-+
-+ return buf;
-+}
-+
-+/**
-+ * This function frees an I/O buffer that was allocated by alloc_buffer.
-+ *
-+ * @param usb_ep the endpoint associated with the buffer
-+ * @param buf address of the buffer
-+ * @param dma The buffer's DMA address
-+ * @param bytes The number of bytes of the buffer
-+ */
-+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
-+ dma_addr_t dma, unsigned bytes)
-+{
-+ dwc_otg_pcd_t *pcd = 0;
-+
-+ pcd = gadget_wrapper->pcd;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
-+
-+ dma_free_coherent(NULL, bytes, buf, dma);
-+}
-+#endif
-+
-+/**
-+ * This function is used to submit an I/O Request to an EP.
-+ *
-+ * - When the request completes the request's completion callback
-+ * is called to return the request to the driver.
-+ * - An EP, except control EPs, may have multiple requests
-+ * pending.
-+ * - Once submitted the request cannot be examined or modified.
-+ * - Each request is turned into one or more packets.
-+ * - A BULK EP can queue any amount of data; the transfer is
-+ * packetized.
-+ * - Zero length Packets are specified with the request 'zero'
-+ * flag.
-+ */
-+static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
-+ gfp_t gfp_flags)
-+{
-+ dwc_otg_pcd_t *pcd;
-+ struct dwc_otg_pcd_ep *ep = NULL;
-+ int retval = 0, is_isoc_ep = 0;
-+ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
-+ __func__, usb_ep, usb_req, gfp_flags);
-+
-+ if (!usb_req || !usb_req->complete || !usb_req->buf) {
-+ DWC_WARN("bad params\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ return -EINVAL;
-+ }
-+
-+ pcd = gadget_wrapper->pcd;
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
-+ gadget_wrapper->gadget.speed);
-+ DWC_WARN("bogus device state\n");
-+ return -ESHUTDOWN;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
-+ usb_ep->name, usb_req, usb_req->length, usb_req->buf);
-+
-+ usb_req->status = -EINPROGRESS;
-+ usb_req->actual = 0;
-+
-+ ep = ep_from_handle(pcd, usb_ep);
-+ if (ep == NULL)
-+ is_isoc_ep = 0;
-+ else
-+ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ dma_addr = usb_req->dma;
-+#else
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
-+ struct device *dev = NULL;
-+
-+ if (otg_dev != NULL)
-+ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
-+
-+ if (usb_req->length != 0 &&
-+ usb_req->dma == DWC_DMA_ADDR_INVALID) {
-+ dma_addr = dma_map_single(dev, usb_req->buf,
-+ usb_req->length,
-+ ep->dwc_ep.is_in ?
-+ DMA_TO_DEVICE:
-+ DMA_FROM_DEVICE);
-+ }
-+ }
-+#endif
-+
-+#ifdef DWC_UTE_PER_IO
-+ if (is_isoc_ep == 1) {
-+ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
-+ usb_req->length, usb_req->zero, usb_req,
-+ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
-+ if (retval)
-+ return -EINVAL;
-+
-+ return 0;
-+ }
-+#endif
-+ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
-+ usb_req->length, usb_req->zero, usb_req,
-+ gfp_flags == GFP_ATOMIC ? 1 : 0);
-+ if (retval) {
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function cancels an I/O request from an EP.
-+ */
-+static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
-+{
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
-+
-+ if (!usb_ep || !usb_req) {
-+ DWC_WARN("bad argument\n");
-+ return -EINVAL;
-+ }
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_WARN("bogus device state\n");
-+ return -ESHUTDOWN;
-+ }
-+ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * usb_ep_set_halt stalls an endpoint.
-+ *
-+ * usb_ep_clear_halt clears an endpoint halt and resets its data
-+ * toggle.
-+ *
-+ * Both of these functions are implemented with the same underlying
-+ * function. The behavior depends on the value argument.
-+ *
-+ * @param[in] usb_ep the Endpoint to halt or clear halt.
-+ * @param[in] value
-+ * - 0 means clear_halt.
-+ * - 1 means set_halt,
-+ * - 2 means clear stall lock flag.
-+ * - 3 means set stall lock flag.
-+ */
-+static int ep_halt(struct usb_ep *usb_ep, int value)
-+{
-+ int retval = 0;
-+
-+ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
-+
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ return -EINVAL;
-+ }
-+
-+ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
-+ if (retval == -DWC_E_AGAIN) {
-+ return -EAGAIN;
-+ } else if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
-+#if 0
-+/**
-+ * ep_wedge: sets the halt feature and ignores clear requests
-+ *
-+ * @usb_ep: the endpoint being wedged
-+ *
-+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
-+ * requests. If the gadget driver clears the halt status, it will
-+ * automatically unwedge the endpoint.
-+ *
-+ * Returns zero on success, else negative errno. *
-+ * Check usb_ep_set_wedge() at "usb_gadget.h" for details
-+ */
-+static int ep_wedge(struct usb_ep *usb_ep)
-+{
-+ int retval = 0;
-+
-+ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
-+
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ return -EINVAL;
-+ }
-+
-+ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
-+ if (retval == -DWC_E_AGAIN) {
-+ retval = -EAGAIN;
-+ } else if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+#endif
-+
-+#ifdef DWC_EN_ISOC
-+/**
-+ * This function is used to submit an ISOC Transfer Request to an EP.
-+ *
-+ * - Every time a sync period completes the request's completion callback
-+ * is called to provide data to the gadget driver.
-+ * - Once submitted the request cannot be modified.
-+ * - Each request is turned into periodic data packets untill ISO
-+ * Transfer is stopped..
-+ */
-+static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
-+ gfp_t gfp_flags)
-+{
-+ int retval = 0;
-+
-+ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
-+ DWC_WARN("bad params\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!usb_ep) {
-+ DWC_PRINTF("bad params\n");
-+ return -EINVAL;
-+ }
-+
-+ req->status = -EINPROGRESS;
-+
-+ retval =
-+ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
-+ req->buf1, req->dma0, req->dma1,
-+ req->sync_frame, req->data_pattern_frame,
-+ req->data_per_frame,
-+ req->
-+ flags & USB_REQ_ISO_ASAP ? -1 :
-+ req->start_frame, req->buf_proc_intrvl,
-+ req, gfp_flags == GFP_ATOMIC ? 1 : 0);
-+
-+ if (retval) {
-+ return -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function stops ISO EP Periodic Data Transfer.
-+ */
-+static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
-+{
-+ int retval = 0;
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ }
-+
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
-+ gadget_wrapper->gadget.speed);
-+ DWC_WARN("bogus device state\n");
-+ }
-+
-+ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
-+ if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
-+ int packets, gfp_t gfp_flags)
-+{
-+ struct usb_iso_request *pReq = NULL;
-+ uint32_t req_size;
-+
-+ req_size = sizeof(struct usb_iso_request);
-+ req_size +=
-+ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
-+
-+ pReq = kmalloc(req_size, gfp_flags);
-+ if (!pReq) {
-+ DWC_WARN("Can't allocate Iso Request\n");
-+ return 0;
-+ }
-+ pReq->iso_packet_desc0 = (void *)(pReq + 1);
-+
-+ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
-+
-+ return pReq;
-+}
-+
-+static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
-+{
-+ kfree(req);
-+}
-+
-+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
-+ .ep_ops = {
-+ .enable = ep_enable,
-+ .disable = ep_disable,
-+
-+ .alloc_request = dwc_otg_pcd_alloc_request,
-+ .free_request = dwc_otg_pcd_free_request,
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ .alloc_buffer = dwc_otg_pcd_alloc_buffer,
-+ .free_buffer = dwc_otg_pcd_free_buffer,
-+#endif
-+
-+ .queue = ep_queue,
-+ .dequeue = ep_dequeue,
-+
-+ .set_halt = ep_halt,
-+ .fifo_status = 0,
-+ .fifo_flush = 0,
-+ },
-+ .iso_ep_start = iso_ep_start,
-+ .iso_ep_stop = iso_ep_stop,
-+ .alloc_iso_request = alloc_iso_request,
-+ .free_iso_request = free_iso_request,
-+};
-+
-+#else
-+
-+ int (*enable) (struct usb_ep *ep,
-+ const struct usb_endpoint_descriptor *desc);
-+ int (*disable) (struct usb_ep *ep);
-+
-+ struct usb_request *(*alloc_request) (struct usb_ep *ep,
-+ gfp_t gfp_flags);
-+ void (*free_request) (struct usb_ep *ep, struct usb_request *req);
-+
-+ int (*queue) (struct usb_ep *ep, struct usb_request *req,
-+ gfp_t gfp_flags);
-+ int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
-+
-+ int (*set_halt) (struct usb_ep *ep, int value);
-+ int (*set_wedge) (struct usb_ep *ep);
-+
-+ int (*fifo_status) (struct usb_ep *ep);
-+ void (*fifo_flush) (struct usb_ep *ep);
-+static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
-+ .enable = ep_enable,
-+ .disable = ep_disable,
-+
-+ .alloc_request = dwc_otg_pcd_alloc_request,
-+ .free_request = dwc_otg_pcd_free_request,
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ .alloc_buffer = dwc_otg_pcd_alloc_buffer,
-+ .free_buffer = dwc_otg_pcd_free_buffer,
-+#else
-+ /* .set_wedge = ep_wedge, */
-+ .set_wedge = NULL, /* uses set_halt instead */
-+#endif
-+
-+ .queue = ep_queue,
-+ .dequeue = ep_dequeue,
-+
-+ .set_halt = ep_halt,
-+ .fifo_status = 0,
-+ .fifo_flush = 0,
-+
-+};
-+
-+#endif /* _EN_ISOC_ */
-+/* Gadget Operations */
-+/**
-+ * The following gadget operations will be implemented in the DWC_otg
-+ * PCD. Functions in the API that are not described below are not
-+ * implemented.
-+ *
-+ * The Gadget API provides wrapper functions for each of the function
-+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the
-+ * wrapper function, which then calls the underlying PCD function. The
-+ * following sections are named according to the wrapper functions
-+ * (except for ioctl, which doesn't have a wrapper function). Within
-+ * each section, the corresponding DWC_otg PCD function name is
-+ * specified.
-+ *
-+ */
-+
-+/**
-+ *Gets the USB Frame number of the last SOF.
-+ */
-+static int get_frame_number(struct usb_gadget *gadget)
-+{
-+ struct gadget_wrapper *d;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
-+
-+ if (gadget == 0) {
-+ return -ENODEV;
-+ }
-+
-+ d = container_of(gadget, struct gadget_wrapper, gadget);
-+ return dwc_otg_pcd_get_frame_number(d->pcd);
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+static int test_lpm_enabled(struct usb_gadget *gadget)
-+{
-+ struct gadget_wrapper *d;
-+
-+ d = container_of(gadget, struct gadget_wrapper, gadget);
-+
-+ return dwc_otg_pcd_is_lpm_enabled(d->pcd);
-+}
-+#endif
-+
-+/**
-+ * Initiates Session Request Protocol (SRP) to wakeup the host if no
-+ * session is in progress. If a session is already in progress, but
-+ * the device is suspended, remote wakeup signaling is started.
-+ *
-+ */
-+static int wakeup(struct usb_gadget *gadget)
-+{
-+ struct gadget_wrapper *d;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
-+
-+ if (gadget == 0) {
-+ return -ENODEV;
-+ } else {
-+ d = container_of(gadget, struct gadget_wrapper, gadget);
-+ }
-+ dwc_otg_pcd_wakeup(d->pcd);
-+ return 0;
-+}
-+
-+static const struct usb_gadget_ops dwc_otg_pcd_ops = {
-+ .get_frame = get_frame_number,
-+ .wakeup = wakeup,
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ .lpm_support = test_lpm_enabled,
-+#endif
-+ // current versions must always be self-powered
-+};
-+
-+static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
-+{
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
-+ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
-+ (struct usb_ctrlrequest
-+ *)bytes);
-+ }
-+
-+ if (retval == -ENOTSUPP) {
-+ retval = -DWC_E_NOT_SUPPORTED;
-+ } else if (retval < 0) {
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ return retval;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int proc_buf_num)
-+{
-+ int i, packet_count;
-+ struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
-+ struct usb_iso_request *iso_req = req_handle;
-+
-+ if (proc_buf_num) {
-+ iso_packet = iso_req->iso_packet_desc1;
-+ } else {
-+ iso_packet = iso_req->iso_packet_desc0;
-+ }
-+ packet_count =
-+ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
-+ for (i = 0; i < packet_count; ++i) {
-+ int status;
-+ int actual;
-+ int offset;
-+ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
-+ i, &status, &actual, &offset);
-+ switch (status) {
-+ case -DWC_E_NO_DATA:
-+ status = -ENODATA;
-+ break;
-+ default:
-+ if (status) {
-+ DWC_PRINTF("unknown status in isoc packet\n");
-+ }
-+
-+ }
-+ iso_packet[i].status = status;
-+ iso_packet[i].offset = offset;
-+ iso_packet[i].actual_length = actual;
-+ }
-+
-+ iso_req->status = 0;
-+ iso_req->process_buffer(ep_handle, iso_req);
-+
-+ return 0;
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+#ifdef DWC_UTE_PER_IO
-+/**
-+ * Copy the contents of the extended request to the Linux usb_request's
-+ * extended part and call the gadget's completion.
-+ *
-+ * @param pcd Pointer to the pcd structure
-+ * @param ep_handle Void pointer to the usb_ep structure
-+ * @param req_handle Void pointer to the usb_request structure
-+ * @param status Request status returned from the portable logic
-+ * @param ereq_port Void pointer to the extended request structure
-+ * created in the the portable part that contains the
-+ * results of the processed iso packets.
-+ */
-+static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status, void *ereq_port)
-+{
-+ struct dwc_ute_iso_req_ext *ereqorg = NULL;
-+ struct dwc_iso_xreq_port *ereqport = NULL;
-+ struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
-+ int i;
-+ struct usb_request *req;
-+ //struct dwc_ute_iso_packet_descriptor *
-+ //int status = 0;
-+
-+ req = (struct usb_request *)req_handle;
-+ ereqorg = &req->ext_req;
-+ ereqport = (struct dwc_iso_xreq_port *)ereq_port;
-+ desc_org = ereqorg->per_io_frame_descs;
-+
-+ if (req && req->complete) {
-+ /* Copy the request data from the portable logic to our request */
-+ for (i = 0; i < ereqport->pio_pkt_count; i++) {
-+ desc_org[i].actual_length =
-+ ereqport->per_io_frame_descs[i].actual_length;
-+ desc_org[i].status =
-+ ereqport->per_io_frame_descs[i].status;
-+ }
-+
-+ switch (status) {
-+ case -DWC_E_SHUTDOWN:
-+ req->status = -ESHUTDOWN;
-+ break;
-+ case -DWC_E_RESTART:
-+ req->status = -ECONNRESET;
-+ break;
-+ case -DWC_E_INVALID:
-+ req->status = -EINVAL;
-+ break;
-+ case -DWC_E_TIMEOUT:
-+ req->status = -ETIMEDOUT;
-+ break;
-+ default:
-+ req->status = status;
-+ }
-+
-+ /* And call the gadget's completion */
-+ req->complete(ep_handle, req);
-+ }
-+
-+ return 0;
-+}
-+#endif /* DWC_UTE_PER_IO */
-+
-+static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status, uint32_t actual)
-+{
-+ struct usb_request *req = (struct usb_request *)req_handle;
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
-+ struct dwc_otg_pcd_ep *ep = NULL;
-+#endif
-+
-+ if (req && req->complete) {
-+ switch (status) {
-+ case -DWC_E_SHUTDOWN:
-+ req->status = -ESHUTDOWN;
-+ break;
-+ case -DWC_E_RESTART:
-+ req->status = -ECONNRESET;
-+ break;
-+ case -DWC_E_INVALID:
-+ req->status = -EINVAL;
-+ break;
-+ case -DWC_E_TIMEOUT:
-+ req->status = -ETIMEDOUT;
-+ break;
-+ default:
-+ req->status = status;
-+
-+ }
-+
-+ req->actual = actual;
-+ DWC_SPINUNLOCK(pcd->lock);
-+ req->complete(ep_handle, req);
-+ DWC_SPINLOCK(pcd->lock);
-+ }
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
-+ ep = ep_from_handle(pcd, ep_handle);
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ if (req->length != 0) {
-+ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
-+ struct device *dev = NULL;
-+
-+ if (otg_dev != NULL)
-+ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
-+
-+ dma_unmap_single(dev, req->dma, req->length,
-+ ep->dwc_ep.is_in ?
-+ DMA_TO_DEVICE: DMA_FROM_DEVICE);
-+ }
-+ }
-+#endif
-+
-+ return 0;
-+}
-+
-+static int _connect(dwc_otg_pcd_t * pcd, int speed)
-+{
-+ gadget_wrapper->gadget.speed = speed;
-+ return 0;
-+}
-+
-+static int _disconnect(dwc_otg_pcd_t * pcd)
-+{
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
-+ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
-+ }
-+ return 0;
-+}
-+
-+static int _resume(dwc_otg_pcd_t * pcd)
-+{
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
-+ gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
-+ }
-+
-+ return 0;
-+}
-+
-+static int _suspend(dwc_otg_pcd_t * pcd)
-+{
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
-+ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * This function updates the otg values in the gadget structure.
-+ */
-+static int _hnp_changed(dwc_otg_pcd_t * pcd)
-+{
-+
-+ if (!gadget_wrapper->gadget.is_otg)
-+ return 0;
-+
-+ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
-+ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
-+ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
-+ return 0;
-+}
-+
-+static int _reset(dwc_otg_pcd_t * pcd)
-+{
-+ return 0;
-+}
-+
-+#ifdef DWC_UTE_CFI
-+static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ if (gadget_wrapper->driver->cfi_feature_setup) {
-+ retval =
-+ gadget_wrapper->driver->
-+ cfi_feature_setup(&gadget_wrapper->gadget,
-+ (struct cfi_usb_ctrlrequest *)cfi_req);
-+ }
-+
-+ return retval;
-+}
-+#endif
-+
-+static const struct dwc_otg_pcd_function_ops fops = {
-+ .complete = _complete,
-+#ifdef DWC_EN_ISOC
-+ .isoc_complete = _isoc_complete,
-+#endif
-+ .setup = _setup,
-+ .disconnect = _disconnect,
-+ .connect = _connect,
-+ .resume = _resume,
-+ .suspend = _suspend,
-+ .hnp_changed = _hnp_changed,
-+ .reset = _reset,
-+#ifdef DWC_UTE_CFI
-+ .cfi_setup = _cfi_setup,
-+#endif
-+#ifdef DWC_UTE_PER_IO
-+ .xisoc_complete = _xisoc_complete,
-+#endif
-+};
-+
-+/**
-+ * This function is the top level PCD interrupt handler.
-+ */
-+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
-+{
-+ dwc_otg_pcd_t *pcd = dev;
-+ int32_t retval = IRQ_NONE;
-+
-+ retval = dwc_otg_pcd_handle_intr(pcd);
-+ if (retval != 0) {
-+ S3C2410X_CLEAR_EINTPEND();
-+ }
-+ return IRQ_RETVAL(retval);
-+}
-+
-+/**
-+ * This function initialized the usb_ep structures to there default
-+ * state.
-+ *
-+ * @param d Pointer on gadget_wrapper.
-+ */
-+void gadget_add_eps(struct gadget_wrapper *d)
-+{
-+ static const char *names[] = {
-+
-+ "ep0",
-+ "ep1in",
-+ "ep2in",
-+ "ep3in",
-+ "ep4in",
-+ "ep5in",
-+ "ep6in",
-+ "ep7in",
-+ "ep8in",
-+ "ep9in",
-+ "ep10in",
-+ "ep11in",
-+ "ep12in",
-+ "ep13in",
-+ "ep14in",
-+ "ep15in",
-+ "ep1out",
-+ "ep2out",
-+ "ep3out",
-+ "ep4out",
-+ "ep5out",
-+ "ep6out",
-+ "ep7out",
-+ "ep8out",
-+ "ep9out",
-+ "ep10out",
-+ "ep11out",
-+ "ep12out",
-+ "ep13out",
-+ "ep14out",
-+ "ep15out"
-+ };
-+
-+ int i;
-+ struct usb_ep *ep;
-+ int8_t dev_endpoints;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
-+
-+ INIT_LIST_HEAD(&d->gadget.ep_list);
-+ d->gadget.ep0 = &d->ep0;
-+ d->gadget.speed = USB_SPEED_UNKNOWN;
-+
-+ INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
-+
-+ /**
-+ * Initialize the EP0 structure.
-+ */
-+ ep = &d->ep0;
-+
-+ /* Init the usb_ep structure. */
-+ ep->name = names[0];
-+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+ /**
-+ * @todo NGS: What should the max packet size be set to
-+ * here? Before EP type is set?
-+ */
-+ ep->maxpacket = MAX_PACKET_SIZE;
-+ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
-+
-+ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+
-+ /**
-+ * Initialize the EP structures.
-+ */
-+ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
-+
-+ for (i = 0; i < dev_endpoints; i++) {
-+ ep = &d->in_ep[i];
-+
-+ /* Init the usb_ep structure. */
-+ ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
-+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+ /**
-+ * @todo NGS: What should the max packet size be set to
-+ * here? Before EP type is set?
-+ */
-+ ep->maxpacket = MAX_PACKET_SIZE;
-+ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+ }
-+
-+ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
-+
-+ for (i = 0; i < dev_endpoints; i++) {
-+ ep = &d->out_ep[i];
-+
-+ /* Init the usb_ep structure. */
-+ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
-+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+ /**
-+ * @todo NGS: What should the max packet size be set to
-+ * here? Before EP type is set?
-+ */
-+ ep->maxpacket = MAX_PACKET_SIZE;
-+
-+ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+ }
-+
-+ /* remove ep0 from the list. There is a ep0 pointer. */
-+ list_del_init(&d->ep0.ep_list);
-+
-+ d->ep0.maxpacket = MAX_EP0_SIZE;
-+}
-+
-+/**
-+ * This function releases the Gadget device.
-+ * required by device_unregister().
-+ *
-+ * @todo Should this do something? Should it free the PCD?
-+ */
-+static void dwc_otg_pcd_gadget_release(struct device *dev)
-+{
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
-+}
-+
-+static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
-+{
-+ static char pcd_name[] = "dwc_otg_pcd";
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ struct gadget_wrapper *d;
-+ int retval;
-+
-+ d = DWC_ALLOC(sizeof(*d));
-+ if (d == NULL) {
-+ return NULL;
-+ }
-+
-+ memset(d, 0, sizeof(*d));
-+
-+ d->gadget.name = pcd_name;
-+ d->pcd = otg_dev->pcd;
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+ strcpy(d->gadget.dev.bus_id, "gadget");
-+#else
-+ dev_set_name(&d->gadget.dev, "%s", "gadget");
-+#endif
-+
-+ d->gadget.dev.parent = &_dev->dev;
-+ d->gadget.dev.release = dwc_otg_pcd_gadget_release;
-+ d->gadget.ops = &dwc_otg_pcd_ops;
-+ d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
-+ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
-+
-+ d->driver = 0;
-+ /* Register the gadget device */
-+ retval = device_register(&d->gadget.dev);
-+ if (retval != 0) {
-+ DWC_ERROR("device_register failed\n");
-+ DWC_FREE(d);
-+ return NULL;
-+ }
-+
-+ return d;
-+}
-+
-+static void free_wrapper(struct gadget_wrapper *d)
-+{
-+ if (d->driver) {
-+ /* should have been done already by driver model core */
-+ DWC_WARN("driver '%s' is still registered\n",
-+ d->driver->driver.name);
-+ usb_gadget_unregister_driver(d->driver);
-+ }
-+
-+ device_unregister(&d->gadget.dev);
-+ DWC_FREE(d);
-+}
-+
-+/**
-+ * This function initialized the PCD portion of the driver.
-+ *
-+ */
-+int pcd_init(dwc_bus_dev_t *_dev)
-+{
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ int retval = 0;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
-+
-+ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
-+
-+ if (!otg_dev->pcd) {
-+ DWC_ERROR("dwc_otg_pcd_init failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ otg_dev->pcd->otg_dev = otg_dev;
-+ gadget_wrapper = alloc_wrapper(_dev);
-+
-+ /*
-+ * Initialize EP structures
-+ */
-+ gadget_add_eps(gadget_wrapper);
-+ /*
-+ * Setup interupt handler
-+ */
-+#ifdef PLATFORM_INTERFACE
-+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
-+ platform_get_irq(_dev, fiq_enable ? 0 : 1));
-+ retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq,
-+ IRQF_SHARED, gadget_wrapper->gadget.name,
-+ otg_dev->pcd);
-+ if (retval != 0) {
-+ DWC_ERROR("request of irq%d failed\n",
-+ platform_get_irq(_dev, fiq_enable ? 0 : 1));
-+ free_wrapper(gadget_wrapper);
-+ return -EBUSY;
-+ }
-+#else
-+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
-+ _dev->irq);
-+ retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
-+ IRQF_SHARED | IRQF_DISABLED,
-+ gadget_wrapper->gadget.name, otg_dev->pcd);
-+ if (retval != 0) {
-+ DWC_ERROR("request of irq%d failed\n", _dev->irq);
-+ free_wrapper(gadget_wrapper);
-+ return -EBUSY;
-+ }
-+#endif
-+
-+ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
-+
-+ return retval;
-+}
-+
-+/**
-+ * Cleanup the PCD.
-+ */
-+void pcd_remove(dwc_bus_dev_t *_dev)
-+{
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ dwc_otg_pcd_t *pcd = otg_dev->pcd;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
-+
-+ /*
-+ * Free the IRQ
-+ */
-+#ifdef PLATFORM_INTERFACE
-+ free_irq(platform_get_irq(_dev, 0), pcd);
-+#else
-+ free_irq(_dev->irq, pcd);
-+#endif
-+ dwc_otg_pcd_remove(otg_dev->pcd);
-+ free_wrapper(gadget_wrapper);
-+ otg_dev->pcd = 0;
-+}
-+
-+/**
-+ * This function registers a gadget driver with the PCD.
-+ *
-+ * When a driver is successfully registered, it will receive control
-+ * requests including set_configuration(), which enables non-control
-+ * requests. then usb traffic follows until a disconnect is reported.
-+ * then a host may connect again, or the driver might get unbound.
-+ *
-+ * @param driver The driver being registered
-+ * @param bind The bind function of gadget driver
-+ */
-+
-+int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
-+{
-+ int retval;
-+
-+ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
-+ driver->driver.name);
-+
-+ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
-+ !driver->bind ||
-+ !driver->unbind || !driver->disconnect || !driver->setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
-+ return -EINVAL;
-+ }
-+ if (gadget_wrapper == 0) {
-+ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
-+ return -ENODEV;
-+ }
-+ if (gadget_wrapper->driver != 0) {
-+ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
-+ return -EBUSY;
-+ }
-+
-+ /* hook up the driver */
-+ gadget_wrapper->driver = driver;
-+ gadget_wrapper->gadget.dev.driver = &driver->driver;
-+
-+ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
-+ retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver);
-+ if (retval) {
-+ DWC_ERROR("bind to driver %s --> error %d\n",
-+ driver->driver.name, retval);
-+ gadget_wrapper->driver = 0;
-+ gadget_wrapper->gadget.dev.driver = 0;
-+ return retval;
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
-+ driver->driver.name);
-+ return 0;
-+}
-+EXPORT_SYMBOL(usb_gadget_probe_driver);
-+
-+/**
-+ * This function unregisters a gadget driver
-+ *
-+ * @param driver The driver being unregistered
-+ */
-+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
-+{
-+ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
-+
-+ if (gadget_wrapper == 0) {
-+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
-+ -ENODEV);
-+ return -ENODEV;
-+ }
-+ if (driver == 0 || driver != gadget_wrapper->driver) {
-+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
-+ -EINVAL);
-+ return -EINVAL;
-+ }
-+
-+ driver->unbind(&gadget_wrapper->gadget);
-+ gadget_wrapper->driver = 0;
-+
-+ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
-+ return 0;
-+}
-+
-+EXPORT_SYMBOL(usb_gadget_unregister_driver);
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_regs.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h
---- linux-3.12.38/drivers/usb/host/dwc_otg/dwc_otg_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2015-03-09 10:39:33.222893718 +0100
-@@ -0,0 +1,2550 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
-+ * $Revision: #98 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_REGS_H__
-+#define __DWC_OTG_REGS_H__
-+
-+#include "dwc_otg_core_if.h"
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the data structures for accessing the DWC_otg core registers.
-+ *
-+ * The application interfaces with the HS OTG core by reading from and
-+ * writing to the Control and Status Register (CSR) space through the
-+ * AHB Slave interface. These registers are 32 bits wide, and the
-+ * addresses are 32-bit-block aligned.
-+ * CSRs are classified as follows:
-+ * - Core Global Registers
-+ * - Device Mode Registers
-+ * - Device Global Registers
-+ * - Device Endpoint Specific Registers
-+ * - Host Mode Registers
-+ * - Host Global Registers
-+ * - Host Port CSRs
-+ * - Host Channel Specific Registers
-+ *
-+ * Only the Core Global registers can be accessed in both Device and
-+ * Host modes. When the HS OTG core is operating in one mode, either
-+ * Device or Host, the application must not access registers from the
-+ * other mode. When the core switches from one mode to another, the
-+ * registers in the new mode of operation must be reprogrammed as they
-+ * would be after a power-on reset.
-+ */
-+
-+/****************************************************************************/
-+/** DWC_otg Core registers .
-+ * The dwc_otg_core_global_regs structure defines the size
-+ * and relative field offsets for the Core Global registers.
-+ */
-+typedef struct dwc_otg_core_global_regs {
-+ /** OTG Control and Status Register. <i>Offset: 000h</i> */
-+ volatile uint32_t gotgctl;
-+ /** OTG Interrupt Register. <i>Offset: 004h</i> */
-+ volatile uint32_t gotgint;
-+ /**Core AHB Configuration Register. <i>Offset: 008h</i> */
-+ volatile uint32_t gahbcfg;
-+
-+#define DWC_GLBINTRMASK 0x0001
-+#define DWC_DMAENABLE 0x0020
-+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
-+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
-+#define DWC_PTXEMPTYLVL_EMPTY 0x0100
-+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
-+
-+ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
-+ volatile uint32_t gusbcfg;
-+ /**Core Reset Register. <i>Offset: 010h</i> */
-+ volatile uint32_t grstctl;
-+ /**Core Interrupt Register. <i>Offset: 014h</i> */
-+ volatile uint32_t gintsts;
-+ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
-+ volatile uint32_t gintmsk;
-+ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
-+ volatile uint32_t grxstsr;
-+ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
-+ volatile uint32_t grxstsp;
-+ /**Receive FIFO Size Register. <i>Offset: 024h</i> */
-+ volatile uint32_t grxfsiz;
-+ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
-+ volatile uint32_t gnptxfsiz;
-+ /**Non Periodic Transmit FIFO/Queue Status Register (Read
-+ * Only). <i>Offset: 02Ch</i> */
-+ volatile uint32_t gnptxsts;
-+ /**I2C Access Register. <i>Offset: 030h</i> */
-+ volatile uint32_t gi2cctl;
-+ /**PHY Vendor Control Register. <i>Offset: 034h</i> */
-+ volatile uint32_t gpvndctl;
-+ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
-+ volatile uint32_t ggpio;
-+ /**User ID Register. <i>Offset: 03Ch</i> */
-+ volatile uint32_t guid;
-+ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
-+ volatile uint32_t gsnpsid;
-+ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
-+ volatile uint32_t ghwcfg1;
-+ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
-+ volatile uint32_t ghwcfg2;
-+#define DWC_SLAVE_ONLY_ARCH 0
-+#define DWC_EXT_DMA_ARCH 1
-+#define DWC_INT_DMA_ARCH 2
-+
-+#define DWC_MODE_HNP_SRP_CAPABLE 0
-+#define DWC_MODE_SRP_ONLY_CAPABLE 1
-+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
-+#define DWC_MODE_SRP_CAPABLE_DEVICE 3
-+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
-+#define DWC_MODE_SRP_CAPABLE_HOST 5
-+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
-+
-+ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
-+ volatile uint32_t ghwcfg3;
-+ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
-+ volatile uint32_t ghwcfg4;
-+ /** Core LPM Configuration register <i>Offset: 054h</i>*/
-+ volatile uint32_t glpmcfg;
-+ /** Global PowerDn Register <i>Offset: 058h</i> */
-+ volatile uint32_t gpwrdn;
-+ /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
-+ volatile uint32_t gdfifocfg;
-+ /** ADP Control Register <i>Offset: 060h</i> */
-+ volatile uint32_t adpctl;
-+ /** Reserved <i>Offset: 064h-0FFh</i> */
-+ volatile uint32_t reserved39[39];
-+ /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
-+ volatile uint32_t hptxfsiz;
-+ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
-+ otherwise Device Transmit FIFO#n Register.
-+ * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
-+ volatile uint32_t dtxfsiz[15];
-+} dwc_otg_core_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields of the Core OTG Control
-+ * and Status Register (GOTGCTL). Set the bits using the bit
-+ * fields then write the <i>d32</i> value to the register.
-+ */
-+typedef union gotgctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned sesreqscs:1;
-+ unsigned sesreq:1;
-+ unsigned vbvalidoven:1;
-+ unsigned vbvalidovval:1;
-+ unsigned avalidoven:1;
-+ unsigned avalidovval:1;
-+ unsigned bvalidoven:1;
-+ unsigned bvalidovval:1;
-+ unsigned hstnegscs:1;
-+ unsigned hnpreq:1;
-+ unsigned hstsethnpen:1;
-+ unsigned devhnpen:1;
-+ unsigned reserved12_15:4;
-+ unsigned conidsts:1;
-+ unsigned dbnctime:1;
-+ unsigned asesvld:1;
-+ unsigned bsesvld:1;
-+ unsigned otgver:1;
-+ unsigned reserved1:1;
-+ unsigned multvalidbc:5;
-+ unsigned chirpen:1;
-+ unsigned reserved28_31:4;
-+ } b;
-+} gotgctl_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core OTG Interrupt Register
-+ * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
-+ * value to the register.
-+ */
-+typedef union gotgint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Current Mode */
-+ unsigned reserved0_1:2;
-+
-+ /** Session End Detected */
-+ unsigned sesenddet:1;
-+
-+ unsigned reserved3_7:5;
-+
-+ /** Session Request Success Status Change */
-+ unsigned sesreqsucstschng:1;
-+ /** Host Negotiation Success Status Change */
-+ unsigned hstnegsucstschng:1;
-+
-+ unsigned reserved10_16:7;
-+
-+ /** Host Negotiation Detected */
-+ unsigned hstnegdet:1;
-+ /** A-Device Timeout Change */
-+ unsigned adevtoutchng:1;
-+ /** Debounce Done */
-+ unsigned debdone:1;
-+ /** Multi-Valued input changed */
-+ unsigned mvic:1;
-+
-+ unsigned reserved31_21:11;
-+
-+ } b;
-+} gotgint_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core AHB Configuration
-+ * Register (GAHBCFG). Set/clear the bits using the bit fields then
-+ * write the <i>d32</i> value to the register.
-+ */
-+typedef union gahbcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned glblintrmsk:1;
-+#define DWC_GAHBCFG_GLBINT_ENABLE 1
-+
-+ unsigned hburstlen:4;
-+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
-+
-+ unsigned dmaenable:1;
-+#define DWC_GAHBCFG_DMAENABLE 1
-+ unsigned reserved:1;
-+ unsigned nptxfemplvl_txfemplvl:1;
-+ unsigned ptxfemplvl:1;
-+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
-+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
-+ unsigned reserved9_20:12;
-+ unsigned remmemsupp:1;
-+ unsigned notialldmawrit:1;
-+ unsigned ahbsingle:1;
-+ unsigned reserved24_31:8;
-+ } b;
-+} gahbcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core USB Configuration
-+ * Register (GUSBCFG). Set the bits using the bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union gusbcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned toutcal:3;
-+ unsigned phyif:1;
-+ unsigned ulpi_utmi_sel:1;
-+ unsigned fsintf:1;
-+ unsigned physel:1;
-+ unsigned ddrsel:1;
-+ unsigned srpcap:1;
-+ unsigned hnpcap:1;
-+ unsigned usbtrdtim:4;
-+ unsigned reserved1:1;
-+ unsigned phylpwrclksel:1;
-+ unsigned otgutmifssel:1;
-+ unsigned ulpi_fsls:1;
-+ unsigned ulpi_auto_res:1;
-+ unsigned ulpi_clk_sus_m:1;
-+ unsigned ulpi_ext_vbus_drv:1;
-+ unsigned ulpi_int_vbus_indicator:1;
-+ unsigned term_sel_dl_pulse:1;
-+ unsigned indicator_complement:1;
-+ unsigned indicator_pass_through:1;
-+ unsigned ulpi_int_prot_dis:1;
-+ unsigned ic_usb_cap:1;
-+ unsigned ic_traffic_pull_remove:1;
-+ unsigned tx_end_delay:1;
-+ unsigned force_host_mode:1;
-+ unsigned force_dev_mode:1;
-+ unsigned reserved31:1;
-+ } b;
-+} gusbcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core Reset Register
-+ * (GRSTCTL). Set/clear the bits using the bit fields then write the
-+ * <i>d32</i> value to the register.
-+ */
-+typedef union grstctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Core Soft Reset (CSftRst) (Device and Host)
-+ *
-+ * The application can flush the control logic in the
-+ * entire core using this bit. This bit resets the
-+ * pipelines in the AHB Clock domain as well as the
-+ * PHY Clock domain.
-+ *
-+ * The state machines are reset to an IDLE state, the
-+ * control bits in the CSRs are cleared, all the
-+ * transmit FIFOs and the receive FIFO are flushed.
-+ *
-+ * The status mask bits that control the generation of
-+ * the interrupt, are cleared, to clear the
-+ * interrupt. The interrupt status bits are not
-+ * cleared, so the application can get the status of
-+ * any events that occurred in the core after it has
-+ * set this bit.
-+ *
-+ * Any transactions on the AHB are terminated as soon
-+ * as possible following the protocol. Any
-+ * transactions on the USB are terminated immediately.
-+ *
-+ * The configuration settings in the CSRs are
-+ * unchanged, so the software doesn't have to
-+ * reprogram these registers (Device
-+ * Configuration/Host Configuration/Core System
-+ * Configuration/Core PHY Configuration).
-+ *
-+ * The application can write to this bit, any time it
-+ * wants to reset the core. This is a self clearing
-+ * bit and the core clears this bit after all the
-+ * necessary logic is reset in the core, which may
-+ * take several clocks, depending on the current state
-+ * of the core.
-+ */
-+ unsigned csftrst:1;
-+ /** Hclk Soft Reset
-+ *
-+ * The application uses this bit to reset the control logic in
-+ * the AHB clock domain. Only AHB clock domain pipelines are
-+ * reset.
-+ */
-+ unsigned hsftrst:1;
-+ /** Host Frame Counter Reset (Host Only)<br>
-+ *
-+ * The application can reset the (micro)frame number
-+ * counter inside the core, using this bit. When the
-+ * (micro)frame counter is reset, the subsequent SOF
-+ * sent out by the core, will have a (micro)frame
-+ * number of 0.
-+ */
-+ unsigned hstfrm:1;
-+ /** In Token Sequence Learning Queue Flush
-+ * (INTknQFlsh) (Device Only)
-+ */
-+ unsigned intknqflsh:1;
-+ /** RxFIFO Flush (RxFFlsh) (Device and Host)
-+ *
-+ * The application can flush the entire Receive FIFO
-+ * using this bit. The application must first
-+ * ensure that the core is not in the middle of a
-+ * transaction. The application should write into
-+ * this bit, only after making sure that neither the
-+ * DMA engine is reading from the RxFIFO nor the MAC
-+ * is writing the data in to the FIFO. The
-+ * application should wait until the bit is cleared
-+ * before performing any other operations. This bit
-+ * will takes 8 clocks (slowest of PHY or AHB clock)
-+ * to clear.
-+ */
-+ unsigned rxfflsh:1;
-+ /** TxFIFO Flush (TxFFlsh) (Device and Host).
-+ *
-+ * This bit is used to selectively flush a single or
-+ * all transmit FIFOs. The application must first
-+ * ensure that the core is not in the middle of a
-+ * transaction. The application should write into
-+ * this bit, only after making sure that neither the
-+ * DMA engine is writing into the TxFIFO nor the MAC
-+ * is reading the data out of the FIFO. The
-+ * application should wait until the core clears this
-+ * bit, before performing any operations. This bit
-+ * will takes 8 clocks (slowest of PHY or AHB clock)
-+ * to clear.
-+ */
-+ unsigned txfflsh:1;
-+
-+ /** TxFIFO Number (TxFNum) (Device and Host).
-+ *
-+ * This is the FIFO number which needs to be flushed,
-+ * using the TxFIFO Flush bit. This field should not
-+ * be changed until the TxFIFO Flush bit is cleared by
-+ * the core.
-+ * - 0x0 : Non Periodic TxFIFO Flush
-+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
-+ * or Periodic TxFIFO in host mode
-+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
-+ * - ...
-+ * - 0xF : Periodic TxFIFO #15 Flush in device mode
-+ * - 0x10: Flush all the Transmit NonPeriodic and
-+ * Transmit Periodic FIFOs in the core
-+ */
-+ unsigned txfnum:5;
-+ /** Reserved */
-+ unsigned reserved11_29:19;
-+ /** DMA Request Signal. Indicated DMA request is in
-+ * probress. Used for debug purpose. */
-+ unsigned dmareq:1;
-+ /** AHB Master Idle. Indicates the AHB Master State
-+ * Machine is in IDLE condition. */
-+ unsigned ahbidle:1;
-+ } b;
-+} grstctl_t;
-+
-+/**
-+ * This union represents the bit fields of the Core Interrupt Mask
-+ * Register (GINTMSK). Set/clear the bits using the bit fields then
-+ * write the <i>d32</i> value to the register.
-+ */
-+typedef union gintmsk_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned reserved0:1;
-+ unsigned modemismatch:1;
-+ unsigned otgintr:1;
-+ unsigned sofintr:1;
-+ unsigned rxstsqlvl:1;
-+ unsigned nptxfempty:1;
-+ unsigned ginnakeff:1;
-+ unsigned goutnakeff:1;
-+ unsigned ulpickint:1;
-+ unsigned i2cintr:1;
-+ unsigned erlysuspend:1;
-+ unsigned usbsuspend:1;
-+ unsigned usbreset:1;
-+ unsigned enumdone:1;
-+ unsigned isooutdrop:1;
-+ unsigned eopframe:1;
-+ unsigned restoredone:1;
-+ unsigned epmismatch:1;
-+ unsigned inepintr:1;
-+ unsigned outepintr:1;
-+ unsigned incomplisoin:1;
-+ unsigned incomplisoout:1;
-+ unsigned fetsusp:1;
-+ unsigned resetdet:1;
-+ unsigned portintr:1;
-+ unsigned hcintr:1;
-+ unsigned ptxfempty:1;
-+ unsigned lpmtranrcvd:1;
-+ unsigned conidstschng:1;
-+ unsigned disconnect:1;
-+ unsigned sessreqintr:1;
-+ unsigned wkupintr:1;
-+ } b;
-+} gintmsk_data_t;
-+/**
-+ * This union represents the bit fields of the Core Interrupt Register
-+ * (GINTSTS). Set/clear the bits using the bit fields then write the
-+ * <i>d32</i> value to the register.
-+ */
-+typedef union gintsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+#define DWC_SOF_INTR_MASK 0x0008
-+ /** register bits */
-+ struct {
-+#define DWC_HOST_MODE 1
-+ unsigned curmode:1;
-+ unsigned modemismatch:1;
-+ unsigned otgintr:1;
-+ unsigned sofintr:1;
-+ unsigned rxstsqlvl:1;
-+ unsigned nptxfempty:1;
-+ unsigned ginnakeff:1;
-+ unsigned goutnakeff:1;
-+ unsigned ulpickint:1;
-+ unsigned i2cintr:1;
-+ unsigned erlysuspend:1;
-+ unsigned usbsuspend:1;
-+ unsigned usbreset:1;
-+ unsigned enumdone:1;
-+ unsigned isooutdrop:1;
-+ unsigned eopframe:1;
-+ unsigned restoredone:1;
-+ unsigned epmismatch:1;
-+ unsigned inepint:1;
-+ unsigned outepintr:1;
-+ unsigned incomplisoin:1;
-+ unsigned incomplisoout:1;
-+ unsigned fetsusp:1;
-+ unsigned resetdet:1;
-+ unsigned portintr:1;
-+ unsigned hcintr:1;
-+ unsigned ptxfempty:1;
-+ unsigned lpmtranrcvd:1;
-+ unsigned conidstschng:1;
-+ unsigned disconnect:1;
-+ unsigned sessreqintr:1;
-+ unsigned wkupintr:1;
-+ } b;
-+} gintsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Receive Status Read and
-+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
-+ * element then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union device_grxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned epnum:4;
-+ unsigned bcnt:11;
-+ unsigned dpid:2;
-+
-+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
-+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
-+
-+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
-+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
-+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
-+ unsigned pktsts:4;
-+ unsigned fn:4;
-+ unsigned reserved25_31:7;
-+ } b;
-+} device_grxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Receive Status Read and
-+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
-+ * element then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union host_grxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned chnum:4;
-+ unsigned bcnt:11;
-+ unsigned dpid:2;
-+
-+ unsigned pktsts:4;
-+#define DWC_GRXSTS_PKTSTS_IN 0x2
-+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
-+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
-+#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
-+
-+ unsigned reserved21_31:11;
-+ } b;
-+} host_grxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
-+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
-+ * then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union fifosize_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned startaddr:16;
-+ unsigned depth:16;
-+ } b;
-+} fifosize_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Non-Periodic Transmit
-+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
-+ * <i>d32</i> element then read out the bits using the <i>b</i>it
-+ * elements.
-+ */
-+typedef union gnptxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned nptxfspcavail:16;
-+ unsigned nptxqspcavail:8;
-+ /** Top of the Non-Periodic Transmit Request Queue
-+ * - bit 24 - Terminate (Last entry for the selected
-+ * channel/EP)
-+ * - bits 26:25 - Token Type
-+ * - 2'b00 - IN/OUT
-+ * - 2'b01 - Zero Length OUT
-+ * - 2'b10 - PING/Complete Split
-+ * - 2'b11 - Channel Halt
-+ * - bits 30:27 - Channel/EP Number
-+ */
-+ unsigned nptxqtop_terminate:1;
-+ unsigned nptxqtop_token:2;
-+ unsigned nptxqtop_chnep:4;
-+ unsigned reserved:1;
-+ } b;
-+} gnptxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Transmit
-+ * FIFO Status Register (DTXFSTS). Read the register into the
-+ * <i>d32</i> element then read out the bits using the <i>b</i>it
-+ * elements.
-+ */
-+typedef union dtxfsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned txfspcavail:16;
-+ unsigned reserved:16;
-+ } b;
-+} dtxfsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the I2C Control Register
-+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gi2cctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned rwdata:8;
-+ unsigned regaddr:8;
-+ unsigned addr:7;
-+ unsigned i2cen:1;
-+ unsigned ack:1;
-+ unsigned i2csuspctl:1;
-+ unsigned i2cdevaddr:2;
-+ unsigned i2cdatse0:1;
-+ unsigned reserved:1;
-+ unsigned rw:1;
-+ unsigned bsydne:1;
-+ } b;
-+} gi2cctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the PHY Vendor Control Register
-+ * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gpvndctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned regdata:8;
-+ unsigned vctrl:8;
-+ unsigned regaddr16_21:6;
-+ unsigned regwr:1;
-+ unsigned reserved23_24:2;
-+ unsigned newregreq:1;
-+ unsigned vstsbsy:1;
-+ unsigned vstsdone:1;
-+ unsigned reserved28_30:3;
-+ unsigned disulpidrvr:1;
-+ } b;
-+} gpvndctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the General Purpose
-+ * Input/Output Register (GGPIO).
-+ * Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union ggpio_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned gpi:16;
-+ unsigned gpo:16;
-+ } b;
-+} ggpio_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User ID Register
-+ * (GUID). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union guid_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned rwdata:32;
-+ } b;
-+} guid_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Synopsys ID Register
-+ * (GSNPSID). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gsnpsid_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned rwdata:32;
-+ } b;
-+} gsnpsid_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config1
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg1_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned ep_dir0:2;
-+ unsigned ep_dir1:2;
-+ unsigned ep_dir2:2;
-+ unsigned ep_dir3:2;
-+ unsigned ep_dir4:2;
-+ unsigned ep_dir5:2;
-+ unsigned ep_dir6:2;
-+ unsigned ep_dir7:2;
-+ unsigned ep_dir8:2;
-+ unsigned ep_dir9:2;
-+ unsigned ep_dir10:2;
-+ unsigned ep_dir11:2;
-+ unsigned ep_dir12:2;
-+ unsigned ep_dir13:2;
-+ unsigned ep_dir14:2;
-+ unsigned ep_dir15:2;
-+ } b;
-+} hwcfg1_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config2
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg2_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /* GHWCFG2 */
-+ unsigned op_mode:3;
-+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
-+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
-+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
-+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
-+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
-+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
-+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
-+
-+ unsigned architecture:2;
-+ unsigned point2point:1;
-+ unsigned hs_phy_type:2;
-+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
-+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
-+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
-+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
-+
-+ unsigned fs_phy_type:2;
-+ unsigned num_dev_ep:4;
-+ unsigned num_host_chan:4;
-+ unsigned perio_ep_supported:1;
-+ unsigned dynamic_fifo:1;
-+ unsigned multi_proc_int:1;
-+ unsigned reserved21:1;
-+ unsigned nonperio_tx_q_depth:2;
-+ unsigned host_perio_tx_q_depth:2;
-+ unsigned dev_token_q_depth:5;
-+ unsigned otg_enable_ic_usb:1;
-+ } b;
-+} hwcfg2_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config3
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg3_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /* GHWCFG3 */
-+ unsigned xfer_size_cntr_width:4;
-+ unsigned packet_size_cntr_width:3;
-+ unsigned otg_func:1;
-+ unsigned i2c:1;
-+ unsigned vendor_ctrl_if:1;
-+ unsigned optional_features:1;
-+ unsigned synch_reset_type:1;
-+ unsigned adp_supp:1;
-+ unsigned otg_enable_hsic:1;
-+ unsigned bc_support:1;
-+ unsigned otg_lpm_en:1;
-+ unsigned dfifo_depth:16;
-+ } b;
-+} hwcfg3_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config4
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg4_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned num_dev_perio_in_ep:4;
-+ unsigned power_optimiz:1;
-+ unsigned min_ahb_freq:1;
-+ unsigned hiber:1;
-+ unsigned xhiber:1;
-+ unsigned reserved:6;
-+ unsigned utmi_phy_data_width:2;
-+ unsigned num_dev_mode_ctrl_ep:4;
-+ unsigned iddig_filt_en:1;
-+ unsigned vbus_valid_filt_en:1;
-+ unsigned a_valid_filt_en:1;
-+ unsigned b_valid_filt_en:1;
-+ unsigned session_end_filt_en:1;
-+ unsigned ded_fifo_en:1;
-+ unsigned num_in_eps:4;
-+ unsigned desc_dma:1;
-+ unsigned desc_dma_dyn:1;
-+ } b;
-+} hwcfg4_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core LPM Configuration
-+ * Register (GLPMCFG). Set the bits using bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union glpmctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** LPM-Capable (LPMCap) (Device and Host)
-+ * The application uses this bit to control
-+ * the DWC_otg core LPM capabilities.
-+ */
-+ unsigned lpm_cap_en:1;
-+ /** LPM response programmed by application (AppL1Res) (Device)
-+ * Handshake response to LPM token pre-programmed
-+ * by device application software.
-+ */
-+ unsigned appl_resp:1;
-+ /** Host Initiated Resume Duration (HIRD) (Device and Host)
-+ * In Host mode this field indicates the value of HIRD
-+ * to be sent in an LPM transaction.
-+ * In Device mode this field is updated with the
-+ * Received LPM Token HIRD bmAttribute
-+ * when an ACK/NYET/STALL response is sent
-+ * to an LPM transaction.
-+ */
-+ unsigned hird:4;
-+ /** RemoteWakeEnable (bRemoteWake) (Device and Host)
-+ * In Host mode this bit indicates the value of remote
-+ * wake up to be sent in wIndex field of LPM transaction.
-+ * In Device mode this field is updated with the
-+ * Received LPM Token bRemoteWake bmAttribute
-+ * when an ACK/NYET/STALL response is sent
-+ * to an LPM transaction.
-+ */
-+ unsigned rem_wkup_en:1;
-+ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
-+ * The application uses this bit to control
-+ * the utmi_sleep_n assertion to the PHY when in L1 state.
-+ */
-+ unsigned en_utmi_sleep:1;
-+ /** HIRD Threshold (HIRD_Thres) (Device and Host)
-+ */
-+ unsigned hird_thres:5;
-+ /** LPM Response (CoreL1Res) (Device and Host)
-+ * In Host mode this bit contains handsake response to
-+ * LPM transaction.
-+ * In Device mode the response of the core to
-+ * LPM transaction received is reflected in these two bits.
-+ - 0x0 : ERROR (No handshake response)
-+ - 0x1 : STALL
-+ - 0x2 : NYET
-+ - 0x3 : ACK
-+ */
-+ unsigned lpm_resp:2;
-+ /** Port Sleep Status (SlpSts) (Device and Host)
-+ * This bit is set as long as a Sleep condition
-+ * is present on the USB bus.
-+ */
-+ unsigned prt_sleep_sts:1;
-+ /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
-+ * Indicates that the application or host
-+ * can start resume from Sleep state.
-+ */
-+ unsigned sleep_state_resumeok:1;
-+ /** LPM channel Index (LPM_Chnl_Indx) (Host)
-+ * The channel number on which the LPM transaction
-+ * has to be applied while sending
-+ * an LPM transaction to the local device.
-+ */
-+ unsigned lpm_chan_index:4;
-+ /** LPM Retry Count (LPM_Retry_Cnt) (Host)
-+ * Number host retries that would be performed
-+ * if the device response was not valid response.
-+ */
-+ unsigned retry_count:3;
-+ /** Send LPM Transaction (SndLPM) (Host)
-+ * When set by application software,
-+ * an LPM transaction containing two tokens
-+ * is sent.
-+ */
-+ unsigned send_lpm:1;
-+ /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
-+ * Number of LPM Host Retries still remaining
-+ * to be transmitted for the current LPM sequence
-+ */
-+ unsigned retry_count_sts:3;
-+ unsigned reserved28_29:2;
-+ /** In host mode once this bit is set, the host
-+ * configures to drive the HSIC Idle state on the bus.
-+ * It then waits for the device to initiate the Connect sequence.
-+ * In device mode once this bit is set, the device waits for
-+ * the HSIC Idle line state on the bus. Upon receving the Idle
-+ * line state, it initiates the HSIC Connect sequence.
-+ */
-+ unsigned hsic_connect:1;
-+ /** This bit overrides and functionally inverts
-+ * the if_select_hsic input port signal.
-+ */
-+ unsigned inv_sel_hsic:1;
-+ } b;
-+} glpmcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core ADP Timer, Control and
-+ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union adpctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Probe Discharge (PRB_DSCHG)
-+ * These bits set the times for TADP_DSCHG.
-+ * These bits are defined as follows:
-+ * 2'b00 - 4 msec
-+ * 2'b01 - 8 msec
-+ * 2'b10 - 16 msec
-+ * 2'b11 - 32 msec
-+ */
-+ unsigned prb_dschg:2;
-+ /** Probe Delta (PRB_DELTA)
-+ * These bits set the resolution for RTIM value.
-+ * The bits are defined in units of 32 kHz clock cycles as follows:
-+ * 2'b00 - 1 cycles
-+ * 2'b01 - 2 cycles
-+ * 2'b10 - 3 cycles
-+ * 2'b11 - 4 cycles
-+ * For example if this value is chosen to 2'b01, it means that RTIM
-+ * increments for every 3(three) 32Khz clock cycles.
-+ */
-+ unsigned prb_delta:2;
-+ /** Probe Period (PRB_PER)
-+ * These bits sets the TADP_PRD as shown in Figure 4 as follows:
-+ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
-+ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
-+ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
-+ * 2'b11 - Reserved
-+ */
-+ unsigned prb_per:2;
-+ /** These bits capture the latest time it took for VBUS to ramp from
-+ * VADP_SINK to VADP_PRB.
-+ * 0x000 - 1 cycles
-+ * 0x001 - 2 cycles
-+ * 0x002 - 3 cycles
-+ * etc
-+ * 0x7FF - 2048 cycles
-+ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
-+ */
-+ unsigned rtim:11;
-+ /** Enable Probe (EnaPrb)
-+ * When programmed to 1'b1, the core performs a probe operation.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned enaprb:1;
-+ /** Enable Sense (EnaSns)
-+ * When programmed to 1'b1, the core performs a Sense operation.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned enasns:1;
-+ /** ADP Reset (ADPRes)
-+ * When set, ADP controller is reset.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adpres:1;
-+ /** ADP Enable (ADPEn)
-+ * When set, the core performs either ADP probing or sensing
-+ * based on EnaPrb or EnaSns.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adpen:1;
-+ /** ADP Probe Interrupt (ADP_PRB_INT)
-+ * When this bit is set, it means that the VBUS
-+ * voltage is greater than VADP_PRB or VADP_PRB is reached.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_prb_int:1;
-+ /**
-+ * ADP Sense Interrupt (ADP_SNS_INT)
-+ * When this bit is set, it means that the VBUS voltage is greater than
-+ * VADP_SNS value or VADP_SNS is reached.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_sns_int:1;
-+ /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
-+ * This bit is relevant only for an ADP probe.
-+ * When this bit is set, it means that the ramp time has
-+ * completed ie ADPCTL.RTIM has reached its terminal value
-+ * of 0x7FF. This is a debug feature that allows software
-+ * to read the ramp time after each cycle.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_tmout_int:1;
-+ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
-+ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_prb_int_msk:1;
-+ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
-+ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_sns_int_msk:1;
-+ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
-+ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_tmout_int_msk:1;
-+ /** Access Request
-+ * 2'b00 - Read/Write Valid (updated by the core)
-+ * 2'b01 - Read
-+ * 2'b00 - Write
-+ * 2'b00 - Reserved
-+ */
-+ unsigned ar:2;
-+ /** Reserved */
-+ unsigned reserved29_31:3;
-+ } b;
-+} adpctl_data_t;
-+
-+////////////////////////////////////////////
-+// Device Registers
-+/**
-+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
-+ *
-+ * The following structures define the size and relative field offsets
-+ * for the Device Mode Registers.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_global_regs {
-+ /** Device Configuration Register. <i>Offset 800h</i> */
-+ volatile uint32_t dcfg;
-+ /** Device Control Register. <i>Offset: 804h</i> */
-+ volatile uint32_t dctl;
-+ /** Device Status Register (Read Only). <i>Offset: 808h</i> */
-+ volatile uint32_t dsts;
-+ /** Reserved. <i>Offset: 80Ch</i> */
-+ uint32_t unused;
-+ /** Device IN Endpoint Common Interrupt Mask
-+ * Register. <i>Offset: 810h</i> */
-+ volatile uint32_t diepmsk;
-+ /** Device OUT Endpoint Common Interrupt Mask
-+ * Register. <i>Offset: 814h</i> */
-+ volatile uint32_t doepmsk;
-+ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
-+ volatile uint32_t daint;
-+ /** Device All Endpoints Interrupt Mask Register. <i>Offset:
-+ * 81Ch</i> */
-+ volatile uint32_t daintmsk;
-+ /** Device IN Token Queue Read Register-1 (Read Only).
-+ * <i>Offset: 820h</i> */
-+ volatile uint32_t dtknqr1;
-+ /** Device IN Token Queue Read Register-2 (Read Only).
-+ * <i>Offset: 824h</i> */
-+ volatile uint32_t dtknqr2;
-+ /** Device VBUS discharge Register. <i>Offset: 828h</i> */
-+ volatile uint32_t dvbusdis;
-+ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
-+ volatile uint32_t dvbuspulse;
-+ /** Device IN Token Queue Read Register-3 (Read Only). /
-+ * Device Thresholding control register (Read/Write)
-+ * <i>Offset: 830h</i> */
-+ volatile uint32_t dtknqr3_dthrctl;
-+ /** Device IN Token Queue Read Register-4 (Read Only). /
-+ * Device IN EPs empty Inr. Mask Register (Read/Write)
-+ * <i>Offset: 834h</i> */
-+ volatile uint32_t dtknqr4_fifoemptymsk;
-+ /** Device Each Endpoint Interrupt Register (Read Only). /
-+ * <i>Offset: 838h</i> */
-+ volatile uint32_t deachint;
-+ /** Device Each Endpoint Interrupt mask Register (Read/Write). /
-+ * <i>Offset: 83Ch</i> */
-+ volatile uint32_t deachintmsk;
-+ /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
-+ * <i>Offset: 840h</i> */
-+ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
-+ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
-+ * <i>Offset: 880h</i> */
-+ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
-+} dwc_otg_device_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Configuration
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements. Write the
-+ * <i>d32</i> member to the dcfg register.
-+ */
-+typedef union dcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Device Speed */
-+ unsigned devspd:2;
-+ /** Non Zero Length Status OUT Handshake */
-+ unsigned nzstsouthshk:1;
-+#define DWC_DCFG_SEND_STALL 1
-+
-+ unsigned ena32khzs:1;
-+ /** Device Addresses */
-+ unsigned devaddr:7;
-+ /** Periodic Frame Interval */
-+ unsigned perfrint:2;
-+#define DWC_DCFG_FRAME_INTERVAL_80 0
-+#define DWC_DCFG_FRAME_INTERVAL_85 1
-+#define DWC_DCFG_FRAME_INTERVAL_90 2
-+#define DWC_DCFG_FRAME_INTERVAL_95 3
-+
-+ /** Enable Device OUT NAK for bulk in DDMA mode */
-+ unsigned endevoutnak:1;
-+
-+ unsigned reserved14_17:4;
-+ /** In Endpoint Mis-match count */
-+ unsigned epmscnt:5;
-+ /** Enable Descriptor DMA in Device mode */
-+ unsigned descdma:1;
-+ unsigned perschintvl:2;
-+ unsigned resvalid:6;
-+ } b;
-+} dcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Control
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union dctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Remote Wakeup */
-+ unsigned rmtwkupsig:1;
-+ /** Soft Disconnect */
-+ unsigned sftdiscon:1;
-+ /** Global Non-Periodic IN NAK Status */
-+ unsigned gnpinnaksts:1;
-+ /** Global OUT NAK Status */
-+ unsigned goutnaksts:1;
-+ /** Test Control */
-+ unsigned tstctl:3;
-+ /** Set Global Non-Periodic IN NAK */
-+ unsigned sgnpinnak:1;
-+ /** Clear Global Non-Periodic IN NAK */
-+ unsigned cgnpinnak:1;
-+ /** Set Global OUT NAK */
-+ unsigned sgoutnak:1;
-+ /** Clear Global OUT NAK */
-+ unsigned cgoutnak:1;
-+ /** Power-On Programming Done */
-+ unsigned pwronprgdone:1;
-+ /** Reserved */
-+ unsigned reserved:1;
-+ /** Global Multi Count */
-+ unsigned gmc:2;
-+ /** Ignore Frame Number for ISOC EPs */
-+ unsigned ifrmnum:1;
-+ /** NAK on Babble */
-+ unsigned nakonbble:1;
-+ /** Enable Continue on BNA */
-+ unsigned encontonbna:1;
-+
-+ unsigned reserved18_31:14;
-+ } b;
-+} dctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Status
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union dsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Suspend Status */
-+ unsigned suspsts:1;
-+ /** Enumerated Speed */
-+ unsigned enumspd:2;
-+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
-+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
-+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
-+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
-+ /** Erratic Error */
-+ unsigned errticerr:1;
-+ unsigned reserved4_7:4;
-+ /** Frame or Microframe Number of the received SOF */
-+ unsigned soffn:14;
-+ unsigned reserved22_31:10;
-+ } b;
-+} dsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN EP Interrupt
-+ * Register and the Device IN EP Common Mask Register.
-+ *
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union diepint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer complete mask */
-+ unsigned xfercompl:1;
-+ /** Endpoint disable mask */
-+ unsigned epdisabled:1;
-+ /** AHB Error mask */
-+ unsigned ahberr:1;
-+ /** TimeOUT Handshake mask (non-ISOC EPs) */
-+ unsigned timeout:1;
-+ /** IN Token received with TxF Empty mask */
-+ unsigned intktxfemp:1;
-+ /** IN Token Received with EP mismatch mask */
-+ unsigned intknepmis:1;
-+ /** IN Endpoint NAK Effective mask */
-+ unsigned inepnakeff:1;
-+ /** Reserved */
-+ unsigned emptyintr:1;
-+
-+ unsigned txfifoundrn:1;
-+
-+ /** BNA Interrupt mask */
-+ unsigned bna:1;
-+
-+ unsigned reserved10_12:3;
-+ /** BNA Interrupt mask */
-+ unsigned nak:1;
-+
-+ unsigned reserved14_31:18;
-+ } b;
-+} diepint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN EP
-+ * Common/Dedicated Interrupt Mask Register.
-+ */
-+typedef union diepint_data diepmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device OUT EP Interrupt
-+ * Registerand Device OUT EP Common Interrupt Mask Register.
-+ *
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union doepint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer complete */
-+ unsigned xfercompl:1;
-+ /** Endpoint disable */
-+ unsigned epdisabled:1;
-+ /** AHB Error */
-+ unsigned ahberr:1;
-+ /** Setup Phase Done (contorl EPs) */
-+ unsigned setup:1;
-+ /** OUT Token Received when Endpoint Disabled */
-+ unsigned outtknepdis:1;
-+
-+ unsigned stsphsercvd:1;
-+ /** Back-to-Back SETUP Packets Received */
-+ unsigned back2backsetup:1;
-+
-+ unsigned reserved7:1;
-+ /** OUT packet Error */
-+ unsigned outpkterr:1;
-+ /** BNA Interrupt */
-+ unsigned bna:1;
-+
-+ unsigned reserved10:1;
-+ /** Packet Drop Status */
-+ unsigned pktdrpsts:1;
-+ /** Babble Interrupt */
-+ unsigned babble:1;
-+ /** NAK Interrupt */
-+ unsigned nak:1;
-+ /** NYET Interrupt */
-+ unsigned nyet:1;
-+ /** Bit indicating setup packet received */
-+ unsigned sr:1;
-+
-+ unsigned reserved16_31:16;
-+ } b;
-+} doepint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device OUT EP
-+ * Common/Dedicated Interrupt Mask Register.
-+ */
-+typedef union doepint_data doepmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device All EP Interrupt
-+ * and Mask Registers.
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union daint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** IN Endpoint bits */
-+ unsigned in:16;
-+ /** OUT Endpoint bits */
-+ unsigned out:16;
-+ } ep;
-+ struct {
-+ /** IN Endpoint bits */
-+ unsigned inep0:1;
-+ unsigned inep1:1;
-+ unsigned inep2:1;
-+ unsigned inep3:1;
-+ unsigned inep4:1;
-+ unsigned inep5:1;
-+ unsigned inep6:1;
-+ unsigned inep7:1;
-+ unsigned inep8:1;
-+ unsigned inep9:1;
-+ unsigned inep10:1;
-+ unsigned inep11:1;
-+ unsigned inep12:1;
-+ unsigned inep13:1;
-+ unsigned inep14:1;
-+ unsigned inep15:1;
-+ /** OUT Endpoint bits */
-+ unsigned outep0:1;
-+ unsigned outep1:1;
-+ unsigned outep2:1;
-+ unsigned outep3:1;
-+ unsigned outep4:1;
-+ unsigned outep5:1;
-+ unsigned outep6:1;
-+ unsigned outep7:1;
-+ unsigned outep8:1;
-+ unsigned outep9:1;
-+ unsigned outep10:1;
-+ unsigned outep11:1;
-+ unsigned outep12:1;
-+ unsigned outep13:1;
-+ unsigned outep14:1;
-+ unsigned outep15:1;
-+ } b;
-+} daint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN Token Queue
-+ * Read Registers.
-+ * - Read the register into the <i>d32</i> member.
-+ * - READ-ONLY Register
-+ */
-+typedef union dtknq1_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** In Token Queue Write Pointer */
-+ unsigned intknwptr:5;
-+ /** Reserved */
-+ unsigned reserved05_06:2;
-+ /** write pointer has wrapped. */
-+ unsigned wrap_bit:1;
-+ /** EP Numbers of IN Tokens 0 ... 4 */
-+ unsigned epnums0_5:24;
-+ } b;
-+} dtknq1_data_t;
-+
-+/**
-+ * This union represents Threshold control Register
-+ * - Read and write the register into the <i>d32</i> member.
-+ * - READ-WRITABLE Register
-+ */
-+typedef union dthrctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** non ISO Tx Thr. Enable */
-+ unsigned non_iso_thr_en:1;
-+ /** ISO Tx Thr. Enable */
-+ unsigned iso_thr_en:1;
-+ /** Tx Thr. Length */
-+ unsigned tx_thr_len:9;
-+ /** AHB Threshold ratio */
-+ unsigned ahb_thr_ratio:2;
-+ /** Reserved */
-+ unsigned reserved13_15:3;
-+ /** Rx Thr. Enable */
-+ unsigned rx_thr_en:1;
-+ /** Rx Thr. Length */
-+ unsigned rx_thr_len:9;
-+ unsigned reserved26:1;
-+ /** Arbiter Parking Enable*/
-+ unsigned arbprken:1;
-+ /** Reserved */
-+ unsigned reserved28_31:4;
-+ } b;
-+} dthrctl_data_t;
-+
-+/**
-+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
-+ * 900h-AFCh</i>
-+ *
-+ * There will be one set of endpoint registers per logical endpoint
-+ * implemented.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_in_ep_regs {
-+ /** Device IN Endpoint Control Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 00h</i> */
-+ volatile uint32_t diepctl;
-+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
-+ uint32_t reserved04;
-+ /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 08h</i> */
-+ volatile uint32_t diepint;
-+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
-+ uint32_t reserved0C;
-+ /** Device IN Endpoint Transfer Size
-+ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
-+ volatile uint32_t dieptsiz;
-+ /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 14h</i> */
-+ volatile uint32_t diepdma;
-+ /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 18h</i> */
-+ volatile uint32_t dtxfsts;
-+ /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 1Ch</i> */
-+ volatile uint32_t diepdmab;
-+} dwc_otg_dev_in_ep_regs_t;
-+
-+/**
-+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
-+ * B00h-CFCh</i>
-+ *
-+ * There will be one set of endpoint registers per logical endpoint
-+ * implemented.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_out_ep_regs {
-+ /** Device OUT Endpoint Control Register. <i>Offset:B00h +
-+ * (ep_num * 20h) + 00h</i> */
-+ volatile uint32_t doepctl;
-+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
-+ uint32_t reserved04;
-+ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
-+ * (ep_num * 20h) + 08h</i> */
-+ volatile uint32_t doepint;
-+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
-+ uint32_t reserved0C;
-+ /** Device OUT Endpoint Transfer Size Register. <i>Offset:
-+ * B00h + (ep_num * 20h) + 10h</i> */
-+ volatile uint32_t doeptsiz;
-+ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
-+ * + (ep_num * 20h) + 14h</i> */
-+ volatile uint32_t doepdma;
-+ /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
-+ uint32_t unused;
-+ /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
-+ * + (ep_num * 20h) + 1Ch</i> */
-+ uint32_t doepdmab;
-+} dwc_otg_dev_out_ep_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP Control
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union depctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Maximum Packet Size
-+ * IN/OUT EPn
-+ * IN/OUT EP0 - 2 bits
-+ * 2'b00: 64 Bytes
-+ * 2'b01: 32
-+ * 2'b10: 16
-+ * 2'b11: 8 */
-+ unsigned mps:11;
-+#define DWC_DEP0CTL_MPS_64 0
-+#define DWC_DEP0CTL_MPS_32 1
-+#define DWC_DEP0CTL_MPS_16 2
-+#define DWC_DEP0CTL_MPS_8 3
-+
-+ /** Next Endpoint
-+ * IN EPn/IN EP0
-+ * OUT EPn/OUT EP0 - reserved */
-+ unsigned nextep:4;
-+
-+ /** USB Active Endpoint */
-+ unsigned usbactep:1;
-+
-+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
-+ * This field contains the PID of the packet going to
-+ * be received or transmitted on this endpoint. The
-+ * application should program the PID of the first
-+ * packet going to be received or transmitted on this
-+ * endpoint , after the endpoint is
-+ * activated. Application use the SetD1PID and
-+ * SetD0PID fields of this register to program either
-+ * D0 or D1 PID.
-+ *
-+ * The encoding for this field is
-+ * - 0: D0
-+ * - 1: D1
-+ */
-+ unsigned dpid:1;
-+
-+ /** NAK Status */
-+ unsigned naksts:1;
-+
-+ /** Endpoint Type
-+ * 2'b00: Control
-+ * 2'b01: Isochronous
-+ * 2'b10: Bulk
-+ * 2'b11: Interrupt */
-+ unsigned eptype:2;
-+
-+ /** Snoop Mode
-+ * OUT EPn/OUT EP0
-+ * IN EPn/IN EP0 - reserved */
-+ unsigned snp:1;
-+
-+ /** Stall Handshake */
-+ unsigned stall:1;
-+
-+ /** Tx Fifo Number
-+ * IN EPn/IN EP0
-+ * OUT EPn/OUT EP0 - reserved */
-+ unsigned txfnum:4;
-+
-+ /** Clear NAK */
-+ unsigned cnak:1;
-+ /** Set NAK */
-+ unsigned snak:1;
-+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
-+ * Writing to this field sets the Endpoint DPID (DPID)
-+ * field in this register to DATA0. Set Even
-+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
-+ * Writing to this field sets the Even/Odd
-+ * (micro)frame (EO_FrNum) field to even (micro)
-+ * frame.
-+ */
-+ unsigned setd0pid:1;
-+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
-+ * Writing to this field sets the Endpoint DPID (DPID)
-+ * field in this register to DATA1 Set Odd
-+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
-+ * Writing to this field sets the Even/Odd
-+ * (micro)frame (EO_FrNum) field to odd (micro) frame.
-+ */
-+ unsigned setd1pid:1;
-+
-+ /** Endpoint Disable */
-+ unsigned epdis:1;
-+ /** Endpoint Enable */
-+ unsigned epena:1;
-+ } b;
-+} depctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP Transfer
-+ * Size Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union deptsiz_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer size */
-+ unsigned xfersize:19;
-+/** Max packet count for EP (pow(2,10)-1) */
-+#define MAX_PKT_CNT 1023
-+ /** Packet Count */
-+ unsigned pktcnt:10;
-+ /** Multi Count - Periodic IN endpoints */
-+ unsigned mc:2;
-+ unsigned reserved:1;
-+ } b;
-+} deptsiz_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP 0 Transfer
-+ * Size Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union deptsiz0_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer size */
-+ unsigned xfersize:7;
-+ /** Reserved */
-+ unsigned reserved7_18:12;
-+ /** Packet Count */
-+ unsigned pktcnt:2;
-+ /** Reserved */
-+ unsigned reserved21_28:8;
-+ /**Setup Packet Count (DOEPTSIZ0 Only) */
-+ unsigned supcnt:2;
-+ unsigned reserved31;
-+ } b;
-+} deptsiz0_data_t;
-+
-+/////////////////////////////////////////////////
-+// DMA Descriptor Specific Structures
-+//
-+
-+/** Buffer status definitions */
-+
-+#define BS_HOST_READY 0x0
-+#define BS_DMA_BUSY 0x1
-+#define BS_DMA_DONE 0x2
-+#define BS_HOST_BUSY 0x3
-+
-+/** Receive/Transmit status definitions */
-+
-+#define RTS_SUCCESS 0x0
-+#define RTS_BUFFLUSH 0x1
-+#define RTS_RESERVED 0x2
-+#define RTS_BUFERR 0x3
-+
-+/**
-+ * This union represents the bit fields in the DMA Descriptor
-+ * status quadlet. Read the quadlet into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
-+ * <i>b_iso_in</i> elements.
-+ */
-+typedef union dev_dma_desc_sts {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** quadlet bits */
-+ struct {
-+ /** Received number of bytes */
-+ unsigned bytes:16;
-+ /** NAK bit - only for OUT EPs */
-+ unsigned nak:1;
-+ unsigned reserved17_22:6;
-+ /** Multiple Transfer - only for OUT EPs */
-+ unsigned mtrf:1;
-+ /** Setup Packet received - only for OUT EPs */
-+ unsigned sr:1;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** Short Packet */
-+ unsigned sp:1;
-+ /** Last */
-+ unsigned l:1;
-+ /** Receive Status */
-+ unsigned sts:2;
-+ /** Buffer Status */
-+ unsigned bs:2;
-+ } b;
-+
-+//#ifdef DWC_EN_ISOC
-+ /** iso out quadlet bits */
-+ struct {
-+ /** Received number of bytes */
-+ unsigned rxbytes:11;
-+
-+ unsigned reserved11:1;
-+ /** Frame Number */
-+ unsigned framenum:11;
-+ /** Received ISO Data PID */
-+ unsigned pid:2;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** Short Packet */
-+ unsigned sp:1;
-+ /** Last */
-+ unsigned l:1;
-+ /** Receive Status */
-+ unsigned rxsts:2;
-+ /** Buffer Status */
-+ unsigned bs:2;
-+ } b_iso_out;
-+
-+ /** iso in quadlet bits */
-+ struct {
-+ /** Transmited number of bytes */
-+ unsigned txbytes:12;
-+ /** Frame Number */
-+ unsigned framenum:11;
-+ /** Transmited ISO Data PID */
-+ unsigned pid:2;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** Short Packet */
-+ unsigned sp:1;
-+ /** Last */
-+ unsigned l:1;
-+ /** Transmit Status */
-+ unsigned txsts:2;
-+ /** Buffer Status */
-+ unsigned bs:2;
-+ } b_iso_in;
-+//#endif /* DWC_EN_ISOC */
-+} dev_dma_desc_sts_t;
-+
-+/**
-+ * DMA Descriptor structure
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+typedef struct dwc_otg_dev_dma_desc {
-+ /** DMA Descriptor status quadlet */
-+ dev_dma_desc_sts_t status;
-+ /** DMA Descriptor data buffer pointer */
-+ uint32_t buf;
-+} dwc_otg_dev_dma_desc_t;
-+
-+/**
-+ * The dwc_otg_dev_if structure contains information needed to manage
-+ * the DWC_otg controller acting in device mode. It represents the
-+ * programming view of the device-specific aspects of the controller.
-+ */
-+typedef struct dwc_otg_dev_if {
-+ /** Pointer to device Global registers.
-+ * Device Global Registers starting at offset 800h
-+ */
-+ dwc_otg_device_global_regs_t *dev_global_regs;
-+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
-+
-+ /**
-+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh
-+ */
-+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
-+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
-+#define DWC_EP_REG_OFFSET 0x20
-+
-+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
-+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
-+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
-+
-+ /* Device configuration information */
-+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
-+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
-+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
-+
-+ /** Size of periodic FIFOs (Bytes) */
-+ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+
-+ /** Size of Tx FIFOs (Bytes) */
-+ uint16_t tx_fifo_size[MAX_TX_FIFOS];
-+
-+ /** Thresholding enable flags and length varaiables **/
-+ uint16_t rx_thr_en;
-+ uint16_t iso_tx_thr_en;
-+ uint16_t non_iso_tx_thr_en;
-+
-+ uint16_t rx_thr_length;
-+ uint16_t tx_thr_length;
-+
-+ /**
-+ * Pointers to the DMA Descriptors for EP0 Control
-+ * transfers (virtual and physical)
-+ */
-+
-+ /** 2 descriptors for SETUP packets */
-+ dwc_dma_t dma_setup_desc_addr[2];
-+ dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
-+
-+ /** Pointer to Descriptor with latest SETUP packet */
-+ dwc_otg_dev_dma_desc_t *psetup;
-+
-+ /** Index of current SETUP handler descriptor */
-+ uint32_t setup_desc_index;
-+
-+ /** Descriptor for Data In or Status In phases */
-+ dwc_dma_t dma_in_desc_addr;
-+ dwc_otg_dev_dma_desc_t *in_desc_addr;
-+
-+ /** Descriptor for Data Out or Status Out phases */
-+ dwc_dma_t dma_out_desc_addr;
-+ dwc_otg_dev_dma_desc_t *out_desc_addr;
-+
-+ /** Setup Packet Detected - if set clear NAK when queueing */
-+ uint32_t spd;
-+ /** Isoc ep pointer on which incomplete happens */
-+ void *isoc_ep;
-+
-+} dwc_otg_dev_if_t;
-+
-+/////////////////////////////////////////////////
-+// Host Mode Register Structures
-+//
-+/**
-+ * The Host Global Registers structure defines the size and relative
-+ * field offsets for the Host Mode Global Registers. Host Global
-+ * Registers offsets 400h-7FFh.
-+*/
-+typedef struct dwc_otg_host_global_regs {
-+ /** Host Configuration Register. <i>Offset: 400h</i> */
-+ volatile uint32_t hcfg;
-+ /** Host Frame Interval Register. <i>Offset: 404h</i> */
-+ volatile uint32_t hfir;
-+ /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
-+ volatile uint32_t hfnum;
-+ /** Reserved. <i>Offset: 40Ch</i> */
-+ uint32_t reserved40C;
-+ /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
-+ volatile uint32_t hptxsts;
-+ /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
-+ volatile uint32_t haint;
-+ /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
-+ volatile uint32_t haintmsk;
-+ /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
-+ volatile uint32_t hflbaddr;
-+} dwc_otg_host_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Configuration Register.
-+ * Read the register into the <i>d32</i> member then set/clear the bits using
-+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
-+ */
-+typedef union hcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** FS/LS Phy Clock Select */
-+ unsigned fslspclksel:2;
-+#define DWC_HCFG_30_60_MHZ 0
-+#define DWC_HCFG_48_MHZ 1
-+#define DWC_HCFG_6_MHZ 2
-+
-+ /** FS/LS Only Support */
-+ unsigned fslssupp:1;
-+ unsigned reserved3_6:4;
-+ /** Enable 32-KHz Suspend Mode */
-+ unsigned ena32khzs:1;
-+ /** Resume Validation Periiod */
-+ unsigned resvalid:8;
-+ unsigned reserved16_22:7;
-+ /** Enable Scatter/gather DMA in Host mode */
-+ unsigned descdma:1;
-+ /** Frame List Entries */
-+ unsigned frlisten:2;
-+ /** Enable Periodic Scheduling */
-+ unsigned perschedena:1;
-+ unsigned reserved27_30:4;
-+ unsigned modechtimen:1;
-+ } b;
-+} hcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Frame Remaing/Number
-+ * Register.
-+ */
-+typedef union hfir_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned frint:16;
-+ unsigned hfirrldctrl:1;
-+ unsigned reserved:15;
-+ } b;
-+} hfir_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Frame Remaing/Number
-+ * Register.
-+ */
-+typedef union hfnum_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned frnum:16;
-+#define DWC_HFNUM_MAX_FRNUM 0x3FFF
-+ unsigned frrem:16;
-+ } b;
-+} hfnum_data_t;
-+
-+typedef union hptxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned ptxfspcavail:16;
-+ unsigned ptxqspcavail:8;
-+ /** Top of the Periodic Transmit Request Queue
-+ * - bit 24 - Terminate (last entry for the selected channel)
-+ * - bits 26:25 - Token Type
-+ * - 2'b00 - Zero length
-+ * - 2'b01 - Ping
-+ * - 2'b10 - Disable
-+ * - bits 30:27 - Channel Number
-+ * - bit 31 - Odd/even microframe
-+ */
-+ unsigned ptxqtop_terminate:1;
-+ unsigned ptxqtop_token:2;
-+ unsigned ptxqtop_chnum:4;
-+ unsigned ptxqtop_odd:1;
-+ } b;
-+} hptxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Port Control and Status
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hprt0 register.
-+ */
-+typedef union hprt0_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned prtconnsts:1;
-+ unsigned prtconndet:1;
-+ unsigned prtena:1;
-+ unsigned prtenchng:1;
-+ unsigned prtovrcurract:1;
-+ unsigned prtovrcurrchng:1;
-+ unsigned prtres:1;
-+ unsigned prtsusp:1;
-+ unsigned prtrst:1;
-+ unsigned reserved9:1;
-+ unsigned prtlnsts:2;
-+ unsigned prtpwr:1;
-+ unsigned prttstctl:4;
-+ unsigned prtspd:2;
-+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
-+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
-+#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
-+ unsigned reserved19_31:13;
-+ } b;
-+} hprt0_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union haint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned ch0:1;
-+ unsigned ch1:1;
-+ unsigned ch2:1;
-+ unsigned ch3:1;
-+ unsigned ch4:1;
-+ unsigned ch5:1;
-+ unsigned ch6:1;
-+ unsigned ch7:1;
-+ unsigned ch8:1;
-+ unsigned ch9:1;
-+ unsigned ch10:1;
-+ unsigned ch11:1;
-+ unsigned ch12:1;
-+ unsigned ch13:1;
-+ unsigned ch14:1;
-+ unsigned ch15:1;
-+ unsigned reserved:16;
-+ } b;
-+
-+ struct {
-+ unsigned chint:16;
-+ unsigned reserved:16;
-+ } b2;
-+} haint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union haintmsk_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned ch0:1;
-+ unsigned ch1:1;
-+ unsigned ch2:1;
-+ unsigned ch3:1;
-+ unsigned ch4:1;
-+ unsigned ch5:1;
-+ unsigned ch6:1;
-+ unsigned ch7:1;
-+ unsigned ch8:1;
-+ unsigned ch9:1;
-+ unsigned ch10:1;
-+ unsigned ch11:1;
-+ unsigned ch12:1;
-+ unsigned ch13:1;
-+ unsigned ch14:1;
-+ unsigned ch15:1;
-+ unsigned reserved:16;
-+ } b;
-+
-+ struct {
-+ unsigned chint:16;
-+ unsigned reserved:16;
-+ } b2;
-+} haintmsk_data_t;
-+
-+/**
-+ * Host Channel Specific Registers. <i>500h-5FCh</i>
-+ */
-+typedef struct dwc_otg_hc_regs {
-+ /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
-+ volatile uint32_t hcchar;
-+ /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
-+ volatile uint32_t hcsplt;
-+ /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
-+ volatile uint32_t hcint;
-+ /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
-+ volatile uint32_t hcintmsk;
-+ /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
-+ volatile uint32_t hctsiz;
-+ /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
-+ volatile uint32_t hcdma;
-+ volatile uint32_t reserved;
-+ /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
-+ volatile uint32_t hcdmab;
-+} dwc_otg_hc_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Characteristics
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcchar register.
-+ */
-+typedef union hcchar_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Maximum packet size in bytes */
-+ unsigned mps:11;
-+
-+ /** Endpoint number */
-+ unsigned epnum:4;
-+
-+ /** 0: OUT, 1: IN */
-+ unsigned epdir:1;
-+
-+ unsigned reserved:1;
-+
-+ /** 0: Full/high speed device, 1: Low speed device */
-+ unsigned lspddev:1;
-+
-+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
-+ unsigned eptype:2;
-+
-+ /** Packets per frame for periodic transfers. 0 is reserved. */
-+ unsigned multicnt:2;
-+
-+ /** Device address */
-+ unsigned devaddr:7;
-+
-+ /**
-+ * Frame to transmit periodic transaction.
-+ * 0: even, 1: odd
-+ */
-+ unsigned oddfrm:1;
-+
-+ /** Channel disable */
-+ unsigned chdis:1;
-+
-+ /** Channel enable */
-+ unsigned chen:1;
-+ } b;
-+} hcchar_data_t;
-+
-+typedef union hcsplt_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Port Address */
-+ unsigned prtaddr:7;
-+
-+ /** Hub Address */
-+ unsigned hubaddr:7;
-+
-+ /** Transaction Position */
-+ unsigned xactpos:2;
-+#define DWC_HCSPLIT_XACTPOS_MID 0
-+#define DWC_HCSPLIT_XACTPOS_END 1
-+#define DWC_HCSPLIT_XACTPOS_BEGIN 2
-+#define DWC_HCSPLIT_XACTPOS_ALL 3
-+
-+ /** Do Complete Split */
-+ unsigned compsplt:1;
-+
-+ /** Reserved */
-+ unsigned reserved:14;
-+
-+ /** Split Enble */
-+ unsigned spltena:1;
-+ } b;
-+} hcsplt_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union hcint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer Complete */
-+ unsigned xfercomp:1;
-+ /** Channel Halted */
-+ unsigned chhltd:1;
-+ /** AHB Error */
-+ unsigned ahberr:1;
-+ /** STALL Response Received */
-+ unsigned stall:1;
-+ /** NAK Response Received */
-+ unsigned nak:1;
-+ /** ACK Response Received */
-+ unsigned ack:1;
-+ /** NYET Response Received */
-+ unsigned nyet:1;
-+ /** Transaction Err */
-+ unsigned xacterr:1;
-+ /** Babble Error */
-+ unsigned bblerr:1;
-+ /** Frame Overrun */
-+ unsigned frmovrun:1;
-+ /** Data Toggle Error */
-+ unsigned datatglerr:1;
-+ /** Buffer Not Available (only for DDMA mode) */
-+ unsigned bna:1;
-+ /** Exessive transaction error (only for DDMA mode) */
-+ unsigned xcs_xact:1;
-+ /** Frame List Rollover interrupt */
-+ unsigned frm_list_roll:1;
-+ /** Reserved */
-+ unsigned reserved14_31:18;
-+ } b;
-+} hcint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Interrupt Mask
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcintmsk register.
-+ */
-+typedef union hcintmsk_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned xfercompl:1;
-+ unsigned chhltd:1;
-+ unsigned ahberr:1;
-+ unsigned stall:1;
-+ unsigned nak:1;
-+ unsigned ack:1;
-+ unsigned nyet:1;
-+ unsigned xacterr:1;
-+ unsigned bblerr:1;
-+ unsigned frmovrun:1;
-+ unsigned datatglerr:1;
-+ unsigned bna:1;
-+ unsigned xcs_xact:1;
-+ unsigned frm_list_roll:1;
-+ unsigned reserved14_31:18;
-+ } b;
-+} hcintmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Transfer Size
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcchar register.
-+ */
-+
-+typedef union hctsiz_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Total transfer size in bytes */
-+ unsigned xfersize:19;
-+
-+ /** Data packets to transfer */
-+ unsigned pktcnt:10;
-+
-+ /**
-+ * Packet ID for next data packet
-+ * 0: DATA0
-+ * 1: DATA2
-+ * 2: DATA1
-+ * 3: MDATA (non-Control), SETUP (Control)
-+ */
-+ unsigned pid:2;
-+#define DWC_HCTSIZ_DATA0 0
-+#define DWC_HCTSIZ_DATA1 2
-+#define DWC_HCTSIZ_DATA2 1
-+#define DWC_HCTSIZ_MDATA 3
-+#define DWC_HCTSIZ_SETUP 3
-+
-+ /** Do PING protocol when 1 */
-+ unsigned dopng:1;
-+ } b;
-+
-+ /** register bits */
-+ struct {
-+ /** Scheduling information */
-+ unsigned schinfo:8;
-+
-+ /** Number of transfer descriptors.
-+ * Max value:
-+ * 64 in general,
-+ * 256 only for HS isochronous endpoint.
-+ */
-+ unsigned ntd:8;
-+
-+ /** Data packets to transfer */
-+ unsigned reserved16_28:13;
-+
-+ /**
-+ * Packet ID for next data packet
-+ * 0: DATA0
-+ * 1: DATA2
-+ * 2: DATA1
-+ * 3: MDATA (non-Control)
-+ */
-+ unsigned pid:2;
-+
-+ /** Do PING protocol when 1 */
-+ unsigned dopng:1;
-+ } b_ddma;
-+} hctsiz_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host DMA Address
-+ * Register used in Descriptor DMA mode.
-+ */
-+typedef union hcdma_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned reserved0_2:3;
-+ /** Current Transfer Descriptor. Not used for ISOC */
-+ unsigned ctd:8;
-+ /** Start Address of Descriptor List */
-+ unsigned dma_addr:21;
-+ } b;
-+} hcdma_data_t;
-+
-+/**
-+ * This union represents the bit fields in the DMA Descriptor
-+ * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union host_dma_desc_sts {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** quadlet bits */
-+
-+ /* for non-isochronous */
-+ struct {
-+ /** Number of bytes */
-+ unsigned n_bytes:17;
-+ /** QTD offset to jump when Short Packet received - only for IN EPs */
-+ unsigned qtd_offset:6;
-+ /**
-+ * Set to request the core to jump to alternate QTD if
-+ * Short Packet received - only for IN EPs
-+ */
-+ unsigned a_qtd:1;
-+ /**
-+ * Setup Packet bit. When set indicates that buffer contains
-+ * setup packet.
-+ */
-+ unsigned sup:1;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** End of List */
-+ unsigned eol:1;
-+ unsigned reserved27:1;
-+ /** Rx/Tx Status */
-+ unsigned sts:2;
-+#define DMA_DESC_STS_PKTERR 1
-+ unsigned reserved30:1;
-+ /** Active Bit */
-+ unsigned a:1;
-+ } b;
-+ /* for isochronous */
-+ struct {
-+ /** Number of bytes */
-+ unsigned n_bytes:12;
-+ unsigned reserved12_24:13;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ unsigned reserved26_27:2;
-+ /** Rx/Tx Status */
-+ unsigned sts:2;
-+ unsigned reserved30:1;
-+ /** Active Bit */
-+ unsigned a:1;
-+ } b_isoc;
-+} host_dma_desc_sts_t;
-+
-+#define MAX_DMA_DESC_SIZE 131071
-+#define MAX_DMA_DESC_NUM_GENERIC 64
-+#define MAX_DMA_DESC_NUM_HS_ISOC 256
-+#define MAX_FRLIST_EN_NUM 64
-+/**
-+ * Host-mode DMA Descriptor structure
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+typedef struct dwc_otg_host_dma_desc {
-+ /** DMA Descriptor status quadlet */
-+ host_dma_desc_sts_t status;
-+ /** DMA Descriptor data buffer pointer */
-+ uint32_t buf;
-+} dwc_otg_host_dma_desc_t;
-+
-+/** OTG Host Interface Structure.
-+ *
-+ * The OTG Host Interface Structure structure contains information
-+ * needed to manage the DWC_otg controller acting in host mode. It
-+ * represents the programming view of the host-specific aspects of the
-+ * controller.
-+ */
-+typedef struct dwc_otg_host_if {
-+ /** Host Global Registers starting at offset 400h.*/
-+ dwc_otg_host_global_regs_t *host_global_regs;
-+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
-+
-+ /** Host Port 0 Control and Status Register */
-+ volatile uint32_t *hprt0;
-+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
-+
-+ /** Host Channel Specific Registers at offsets 500h-5FCh. */
-+ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
-+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
-+#define DWC_OTG_CHAN_REGS_OFFSET 0x20
-+
-+ /* Host configuration information */
-+ /** Number of Host Channels (range: 1-16) */
-+ uint8_t num_host_channels;
-+ /** Periodic EPs supported (0: no, 1: yes) */
-+ uint8_t perio_eps_supported;
-+ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
-+ uint16_t perio_tx_fifo_size;
-+
-+} dwc_otg_host_if_t;
-+
-+/**
-+ * This union represents the bit fields in the Power and Clock Gating Control
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union pcgcctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Stop Pclk */
-+ unsigned stoppclk:1;
-+ /** Gate Hclk */
-+ unsigned gatehclk:1;
-+ /** Power Clamp */
-+ unsigned pwrclmp:1;
-+ /** Reset Power Down Modules */
-+ unsigned rstpdwnmodule:1;
-+ /** Reserved */
-+ unsigned reserved:1;
-+ /** Enable Sleep Clock Gating (Enbl_L1Gating) */
-+ unsigned enbl_sleep_gating:1;
-+ /** PHY In Sleep (PhySleep) */
-+ unsigned phy_in_sleep:1;
-+ /** Deep Sleep*/
-+ unsigned deep_sleep:1;
-+ unsigned resetaftsusp:1;
-+ unsigned restoremode:1;
-+ unsigned enbl_extnd_hiber:1;
-+ unsigned extnd_hiber_pwrclmp:1;
-+ unsigned extnd_hiber_switch:1;
-+ unsigned ess_reg_restored:1;
-+ unsigned prt_clk_sel:2;
-+ unsigned port_power:1;
-+ unsigned max_xcvrselect:2;
-+ unsigned max_termsel:1;
-+ unsigned mac_dev_addr:7;
-+ unsigned p2hd_dev_enum_spd:2;
-+ unsigned p2hd_prt_spd:2;
-+ unsigned if_dev_mode:1;
-+ } b;
-+} pcgcctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Global Data FIFO Software
-+ * Configuration Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union gdfifocfg_data {
-+ /* raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** OTG Data FIFO depth */
-+ unsigned gdfifocfg:16;
-+ /** Start address of EP info controller */
-+ unsigned epinfobase:16;
-+ } b;
-+} gdfifocfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Global Power Down Register
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gpwrdn_data {
-+ /* raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** PMU Interrupt Select */
-+ unsigned pmuintsel:1;
-+ /** PMU Active */
-+ unsigned pmuactv:1;
-+ /** Restore */
-+ unsigned restore:1;
-+ /** Power Down Clamp */
-+ unsigned pwrdnclmp:1;
-+ /** Power Down Reset */
-+ unsigned pwrdnrstn:1;
-+ /** Power Down Switch */
-+ unsigned pwrdnswtch:1;
-+ /** Disable VBUS */
-+ unsigned dis_vbus:1;
-+ /** Line State Change */
-+ unsigned lnstschng:1;
-+ /** Line state change mask */
-+ unsigned lnstchng_msk:1;
-+ /** Reset Detected */
-+ unsigned rst_det:1;
-+ /** Reset Detect mask */
-+ unsigned rst_det_msk:1;
-+ /** Disconnect Detected */
-+ unsigned disconn_det:1;
-+ /** Disconnect Detect mask */
-+ unsigned disconn_det_msk:1;
-+ /** Connect Detected*/
-+ unsigned connect_det:1;
-+ /** Connect Detected Mask*/
-+ unsigned connect_det_msk:1;
-+ /** SRP Detected */
-+ unsigned srp_det:1;
-+ /** SRP Detect mask */
-+ unsigned srp_det_msk:1;
-+ /** Status Change Interrupt */
-+ unsigned sts_chngint:1;
-+ /** Status Change Interrupt Mask */
-+ unsigned sts_chngint_msk:1;
-+ /** Line State */
-+ unsigned linestate:2;
-+ /** Indicates current mode(status of IDDIG signal) */
-+ unsigned idsts:1;
-+ /** B Session Valid signal status*/
-+ unsigned bsessvld:1;
-+ /** ADP Event Detected */
-+ unsigned adp_int:1;
-+ /** Multi Valued ID pin */
-+ unsigned mult_val_id_bc:5;
-+ /** Reserved 24_31 */
-+ unsigned reserved29_31:3;
-+ } b;
-+} gpwrdn_data_t;
-+
-+#endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/Makefile linux-rpi/drivers/usb/host/dwc_otg/Makefile
---- linux-3.12.38/drivers/usb/host/dwc_otg/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/Makefile 2015-03-09 10:39:33.214893718 +0100
-@@ -0,0 +1,82 @@
-+#
-+# Makefile for DWC_otg Highspeed USB controller driver
-+#
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+# Use the BUS_INTERFACE variable to compile the software for either
-+# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
-+ifeq ($(BUS_INTERFACE),)
-+# BUS_INTERFACE = -DPCI_INTERFACE
-+# BUS_INTERFACE = -DLM_INTERFACE
-+ BUS_INTERFACE = -DPLATFORM_INTERFACE
-+endif
-+
-+#ccflags-y += -DDEBUG
-+#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
-+
-+# Use one of the following flags to compile the software in host-only or
-+# device-only mode.
-+#ccflags-y += -DDWC_HOST_ONLY
-+#ccflags-y += -DDWC_DEVICE_ONLY
-+
-+ccflags-y += -Dlinux -DDWC_HS_ELECT_TST
-+#ccflags-y += -DDWC_EN_ISOC
-+ccflags-y += -I$(obj)/../dwc_common_port
-+#ccflags-y += -I$(PORTLIB)
-+ccflags-y += -DDWC_LINUX
-+ccflags-y += $(CFI)
-+ccflags-y += $(BUS_INTERFACE)
-+#ccflags-y += -DDWC_DEV_SRPCAP
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
-+
-+dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
-+dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
-+dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
-+dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
-+dwc_otg-objs += dwc_otg_adp.o
-+dwc_otg-objs += dwc_otg_fiq_fsm.o
-+dwc_otg-objs += dwc_otg_fiq_stub.o
-+ifneq ($(CFI),)
-+dwc_otg-objs += dwc_otg_cfi.o
-+endif
-+
-+kernrelwd := $(subst ., ,$(KERNELRELEASE))
-+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
-+
-+ifneq ($(kernrel3),2.6.20)
-+ccflags-y += $(CPPFLAGS)
-+endif
-+
-+else
-+
-+PWD := $(shell pwd)
-+PORTLIB := $(PWD)/../dwc_common_port
-+
-+# Command paths
-+CTAGS := $(CTAGS)
-+DOXYGEN := $(DOXYGEN)
-+
-+default: portlib
-+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+install: default
-+ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
-+ $(MAKE) -C$(KDIR) M=$(PWD) modules_install
-+
-+portlib:
-+ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+ cp $(PORTLIB)/Module.symvers $(PWD)/
-+
-+docs: $(wildcard *.[hc]) doc/doxygen.cfg
-+ $(DOXYGEN) doc/doxygen.cfg
-+
-+tags: $(wildcard *.[hc])
-+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+
-+clean:
-+ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
-+
-+endif
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
---- linux-3.12.38/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 2015-03-09 10:39:33.222893718 +0100
-@@ -0,0 +1,337 @@
-+package dwc_otg_test;
-+
-+use strict;
-+use Exporter ();
-+
-+use vars qw(@ISA @EXPORT
-+$sysfsdir $paramdir $errors $params
-+);
-+
-+@ISA = qw(Exporter);
-+
-+#
-+# Globals
-+#
-+$sysfsdir = "/sys/devices/lm0";
-+$paramdir = "/sys/module/dwc_otg";
-+$errors = 0;
-+
-+$params = [
-+ {
-+ NAME => "otg_cap",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 2
-+ },
-+ {
-+ NAME => "dma_enable",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "dma_burst_size",
-+ DEFAULT => 32,
-+ ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
-+ LOW => 1,
-+ HIGH => 256
-+ },
-+ {
-+ NAME => "host_speed",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "host_support_fs_ls_low_power",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "host_ls_low_power_phy_clk",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "dev_speed",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "enable_dynamic_fifo",
-+ DEFAULT => 1,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "data_fifo_size",
-+ DEFAULT => 8192,
-+ ENUM => [],
-+ LOW => 32,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "dev_rx_fifo_size",
-+ DEFAULT => 1064,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "dev_nperio_tx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_1",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_2",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_3",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_4",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_5",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_6",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_7",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_8",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_9",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_10",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_11",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_12",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_13",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_14",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_15",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "host_rx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "host_nperio_tx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "host_perio_tx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "max_transfer_size",
-+ DEFAULT => 65535,
-+ ENUM => [],
-+ LOW => 2047,
-+ HIGH => 65535
-+ },
-+ {
-+ NAME => "max_packet_count",
-+ DEFAULT => 511,
-+ ENUM => [],
-+ LOW => 15,
-+ HIGH => 511
-+ },
-+ {
-+ NAME => "host_channels",
-+ DEFAULT => 12,
-+ ENUM => [],
-+ LOW => 1,
-+ HIGH => 16
-+ },
-+ {
-+ NAME => "dev_endpoints",
-+ DEFAULT => 6,
-+ ENUM => [],
-+ LOW => 1,
-+ HIGH => 15
-+ },
-+ {
-+ NAME => "phy_type",
-+ DEFAULT => 1,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 2
-+ },
-+ {
-+ NAME => "phy_utmi_width",
-+ DEFAULT => 16,
-+ ENUM => [8, 16],
-+ LOW => 8,
-+ HIGH => 16
-+ },
-+ {
-+ NAME => "phy_ulpi_ddr",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ ];
-+
-+
-+#
-+#
-+sub check_arch {
-+ $_ = `uname -m`;
-+ chomp;
-+ unless (m/armv4tl/) {
-+ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n";
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+#
-+#
-+sub load_module {
-+ my $params = shift;
-+ print "\nRemoving Module\n";
-+ system "rmmod dwc_otg";
-+ print "Loading Module\n";
-+ if ($params ne "") {
-+ print "Module Parameters: $params\n";
-+ }
-+ if (system("modprobe dwc_otg $params")) {
-+ warn "Unable to load module\n";
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+#
-+#
-+sub test_status {
-+ my $arg = shift;
-+
-+ print "\n";
-+
-+ if (defined $arg) {
-+ warn "WARNING: $arg\n";
-+ }
-+
-+ if ($errors > 0) {
-+ warn "TEST FAILED with $errors errors\n";
-+ return 0;
-+ } else {
-+ print "TEST PASSED\n";
-+ return 0 if (defined $arg);
-+ }
-+ return 1;
-+}
-+
-+#
-+#
-+@EXPORT = qw(
-+$sysfsdir
-+$paramdir
-+$params
-+$errors
-+check_arch
-+load_module
-+test_status
-+);
-+
-+1;
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/test/Makefile linux-rpi/drivers/usb/host/dwc_otg/test/Makefile
---- linux-3.12.38/drivers/usb/host/dwc_otg/test/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/Makefile 2015-03-09 10:39:33.222893718 +0100
-@@ -0,0 +1,16 @@
-+
-+PERL=/usr/bin/perl
-+PL_TESTS=test_sysfs.pl test_mod_param.pl
-+
-+.PHONY : test
-+test : perl_tests
-+
-+perl_tests :
-+ @echo
-+ @echo Running perl tests
-+ @for test in $(PL_TESTS); do \
-+ if $(PERL) ./$$test ; then \
-+ echo "=======> $$test, PASSED" ; \
-+ else echo "=======> $$test, FAILED" ; \
-+ fi \
-+ done
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/test/test_mod_param.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl
---- linux-3.12.38/drivers/usb/host/dwc_otg/test/test_mod_param.pl 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl 2015-03-09 10:39:33.222893718 +0100
-@@ -0,0 +1,133 @@
-+#!/usr/bin/perl -w
-+#
-+# Run this program on the integrator.
-+#
-+# - Tests module parameter default values.
-+# - Tests setting of valid module parameter values via modprobe.
-+# - Tests invalid module parameter values.
-+# -----------------------------------------------------------------------------
-+use strict;
-+use dwc_otg_test;
-+
-+check_arch() or die;
-+
-+#
-+#
-+sub test {
-+ my ($param,$expected) = @_;
-+ my $value = get($param);
-+
-+ if ($value == $expected) {
-+ print "$param = $value, okay\n";
-+ }
-+
-+ else {
-+ warn "ERROR: value of $param != $expected, $value\n";
-+ $errors ++;
-+ }
-+}
-+
-+#
-+#
-+sub get {
-+ my $param = shift;
-+ my $tmp = `cat $paramdir/$param`;
-+ chomp $tmp;
-+ return $tmp;
-+}
-+
-+#
-+#
-+sub test_main {
-+
-+ print "\nTesting Module Parameters\n";
-+
-+ load_module("") or die;
-+
-+ # Test initial values
-+ print "\nTesting Default Values\n";
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+
-+ # Test low value
-+ print "\nTesting Low Value\n";
-+ my $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{LOW});
-+ }
-+
-+ # Test high value
-+ print "\nTesting High Value\n";
-+ $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{HIGH});
-+ }
-+
-+ # Test Enum
-+ print "\nTesting Enumerated\n";
-+ foreach (@{$params}) {
-+ if (defined $_->{ENUM}) {
-+ my $value;
-+ foreach $value (@{$_->{ENUM}}) {
-+ $cmd_params = "$_->{NAME}=$value";
-+ load_module($cmd_params) or die;
-+ test ($_->{NAME}, $value);
-+ }
-+ }
-+ }
-+
-+ # Test Invalid Values
-+ print "\nTesting Invalid Values\n";
-+ $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+
-+ $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+
-+ print "\nTesting Enumerated\n";
-+ foreach (@{$params}) {
-+ if (defined $_->{ENUM}) {
-+ my $value;
-+ foreach $value (@{$_->{ENUM}}) {
-+ $value = $value + 1;
-+ $cmd_params = "$_->{NAME}=$value";
-+ load_module($cmd_params) or die;
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ $value = $value - 2;
-+ $cmd_params = "$_->{NAME}=$value";
-+ load_module($cmd_params) or die;
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+ }
-+ }
-+
-+ test_status() or die;
-+}
-+
-+test_main();
-+0;
-diff -Nur linux-3.12.38/drivers/usb/host/dwc_otg/test/test_sysfs.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl
---- linux-3.12.38/drivers/usb/host/dwc_otg/test/test_sysfs.pl 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl 2015-03-09 10:39:33.222893718 +0100
-@@ -0,0 +1,193 @@
-+#!/usr/bin/perl -w
-+#
-+# Run this program on the integrator
-+# - Tests select sysfs attributes.
-+# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
-+# -----------------------------------------------------------------------------
-+use strict;
-+use dwc_otg_test;
-+
-+check_arch() or die;
-+
-+#
-+#
-+sub test {
-+ my ($attr,$expected) = @_;
-+ my $string = get($attr);
-+
-+ if ($string eq $expected) {
-+ printf("$attr = $string, okay\n");
-+ }
-+ else {
-+ warn "ERROR: value of $attr != $expected, $string\n";
-+ $errors ++;
-+ }
-+}
-+
-+#
-+#
-+sub set {
-+ my ($reg, $value) = @_;
-+ system "echo $value > $sysfsdir/$reg";
-+}
-+
-+#
-+#
-+sub get {
-+ my $attr = shift;
-+ my $string = `cat $sysfsdir/$attr`;
-+ chomp $string;
-+ if ($string =~ m/\s\=\s/) {
-+ my $tmp;
-+ ($tmp, $string) = split /\s=\s/, $string;
-+ }
-+ return $string;
-+}
-+
-+#
-+#
-+sub test_main {
-+ print("\nTesting Sysfs Attributes\n");
-+
-+ load_module("") or die;
-+
-+ # Test initial values of regoffset/regvalue/guid/gsnpsid
-+ print("\nTesting Default Values\n");
-+
-+ test("regoffset", "0xffffffff");
-+ test("regvalue", "invalid offset");
-+ test("guid", "0x12345678"); # this will fail if it has been changed
-+ test("gsnpsid", "0x4f54200a");
-+
-+ # Test operation of regoffset/regvalue
-+ print("\nTesting regoffset\n");
-+ set('regoffset', '5a5a5a5a');
-+ test("regoffset", "0xffffffff");
-+
-+ set('regoffset', '0');
-+ test("regoffset", "0x00000000");
-+
-+ set('regoffset', '40000');
-+ test("regoffset", "0x00000000");
-+
-+ set('regoffset', '3ffff');
-+ test("regoffset", "0x0003ffff");
-+
-+ set('regoffset', '1');
-+ test("regoffset", "0x00000001");
-+
-+ print("\nTesting regvalue\n");
-+ set('regoffset', '3c');
-+ test("regvalue", "0x12345678");
-+ set('regvalue', '5a5a5a5a');
-+ test("regvalue", "0x5a5a5a5a");
-+ set('regvalue','a5a5a5a5');
-+ test("regvalue", "0xa5a5a5a5");
-+ set('guid','12345678');
-+
-+ # Test HNP Capable
-+ print("\nTesting HNP Capable bit\n");
-+ set('hnpcapable', '1');
-+ test("hnpcapable", "0x1");
-+ set('hnpcapable','0');
-+ test("hnpcapable", "0x0");
-+
-+ set('regoffset','0c');
-+
-+ my $old = get('gusbcfg');
-+ print("setting hnpcapable\n");
-+ set('hnpcapable', '1');
-+ test("hnpcapable", "0x1");
-+ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
-+ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
-+
-+ $old = get('gusbcfg');
-+ print("clearing hnpcapable\n");
-+ set('hnpcapable', '0');
-+ test("hnpcapable", "0x0");
-+ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
-+ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
-+
-+ # Test SRP Capable
-+ print("\nTesting SRP Capable bit\n");
-+ set('srpcapable', '1');
-+ test("srpcapable", "0x1");
-+ set('srpcapable','0');
-+ test("srpcapable", "0x0");
-+
-+ set('regoffset','0c');
-+
-+ $old = get('gusbcfg');
-+ print("setting srpcapable\n");
-+ set('srpcapable', '1');
-+ test("srpcapable", "0x1");
-+ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
-+ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
-+
-+ $old = get('gusbcfg');
-+ print("clearing srpcapable\n");
-+ set('srpcapable', '0');
-+ test("srpcapable", "0x0");
-+ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
-+ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
-+
-+ # Test GGPIO
-+ print("\nTesting GGPIO\n");
-+ set('ggpio','5a5a5a5a');
-+ test('ggpio','0x5a5a0000');
-+ set('ggpio','a5a5a5a5');
-+ test('ggpio','0xa5a50000');
-+ set('ggpio','11110000');
-+ test('ggpio','0x11110000');
-+ set('ggpio','00001111');
-+ test('ggpio','0x00000000');
-+
-+ # Test DEVSPEED
-+ print("\nTesting DEVSPEED\n");
-+ set('regoffset','800');
-+ $old = get('regvalue');
-+ set('devspeed','0');
-+ test('devspeed','0x0');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
-+ set('devspeed','1');
-+ test('devspeed','0x1');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
-+ set('devspeed','2');
-+ test('devspeed','0x2');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
-+ set('devspeed','3');
-+ test('devspeed','0x3');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
-+ set('devspeed','4');
-+ test('devspeed','0x0');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
-+ set('devspeed','5');
-+ test('devspeed','0x1');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
-+
-+
-+ # mode Returns the current mode:0 for device mode1 for host mode Read
-+ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write
-+ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write
-+ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write
-+ # bussuspend Suspend the USB bus. Read/Write
-+ # busconnected Get the connection status of the bus Read
-+
-+ # gotgctl Get or set the Core Control Status Register. Read/Write
-+ ## gusbcfg Get or set the Core USB Configuration Register Read/Write
-+ # grxfsiz Get or set the Receive FIFO Size Register Read/Write
-+ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write
-+ # gpvndctl Get or set the PHY Vendor Control Register Read/Write
-+ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
-+ ## guid Get or set the value of the User ID Register Read/Write
-+ ## gsnpsid Get the value of the Synopsys ID Regester Read
-+ ## devspeed Get or set the device speed setting in the DCFG register Read/Write
-+ # enumspeed Gets the device enumeration Speed. Read
-+ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read
-+ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write
-+
-+ test_status("TEST NYI") or die;
-+}
-+
-+test_main();
-+0;
-diff -Nur linux-3.12.38/drivers/usb/host/ehci-sched.c linux-rpi/drivers/usb/host/ehci-sched.c
---- linux-3.12.38/drivers/usb/host/ehci-sched.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/host/ehci-sched.c 2015-03-10 17:26:51.306216687 +0100
-@@ -1384,10 +1384,6 @@
-
- now = ehci_read_frame_index(ehci) & (mod - 1);
-
-- /* If needed, initialize last_iso_frame so that this URB will be seen */
-- if (ehci->isoc_count == 0)
-- ehci->last_iso_frame = now >> 3;
--
- /* Typical case: reuse current schedule, stream is still active.
- * Hopefully there are no gaps from the host falling behind
- * (irq delays etc). If there are, the behavior depends on
-@@ -1497,6 +1493,10 @@
- urb->start_frame = stream->next_uframe;
- if (!stream->highspeed)
- urb->start_frame >>= 3;
-+
-+ /* Make sure scan_isoc() sees these */
-+ if (ehci->isoc_count == 0)
-+ ehci->last_iso_frame = now >> 3;
- return 0;
-
- fail:
-diff -Nur linux-3.12.38/drivers/usb/host/Kconfig linux-rpi/drivers/usb/host/Kconfig
---- linux-3.12.38/drivers/usb/host/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/host/Kconfig 2015-03-10 17:26:51.302216687 +0100
-@@ -650,6 +650,19 @@
- To compile this driver a module, choose M here: the module
- will be called "hwa-hc".
-
-+config USB_DWCOTG
-+ tristate "Synopsis DWC host support"
-+ depends on USB
-+ help
-+ The Synopsis DWC controller is a dual-role
-+ host/peripheral/OTG ("On The Go") USB controllers.
-+
-+ Enable this option to support this IP in host controller mode.
-+ If unsure, say N.
-+
-+ To compile this driver as a module, choose M here: the
-+ modules built will be called dwc_otg and dwc_common_port.
-+
- config USB_IMX21_HCD
- tristate "i.MX21 HCD support"
- depends on ARM && ARCH_MXC
-diff -Nur linux-3.12.38/drivers/usb/host/Makefile linux-rpi/drivers/usb/host/Makefile
---- linux-3.12.38/drivers/usb/host/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/host/Makefile 2015-03-10 17:26:51.302216687 +0100
-@@ -56,6 +56,8 @@
- obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
- obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
- obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/
- obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
- obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
- obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
-diff -Nur linux-3.12.38/drivers/usb/host/pci-quirks.c linux-rpi/drivers/usb/host/pci-quirks.c
---- linux-3.12.38/drivers/usb/host/pci-quirks.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/host/pci-quirks.c 2015-03-10 17:26:51.314216687 +0100
-@@ -560,8 +560,7 @@
- {
- void __iomem *base;
- u32 control;
-- u32 fminterval = 0;
-- bool no_fminterval = false;
-+ u32 fminterval;
- int cnt;
-
- if (!mmio_resource_enabled(pdev, 0))
-@@ -571,13 +570,6 @@
- if (base == NULL)
- return;
-
-- /*
-- * ULi M5237 OHCI controller locks the whole system when accessing
-- * the OHCI_FMINTERVAL offset.
-- */
-- if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
-- no_fminterval = true;
--
- control = readl(base + OHCI_CONTROL);
-
- /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
-@@ -616,9 +608,7 @@
- }
-
- /* software reset of the controller, preserving HcFmInterval */
-- if (!no_fminterval)
-- fminterval = readl(base + OHCI_FMINTERVAL);
--
-+ fminterval = readl(base + OHCI_FMINTERVAL);
- writel(OHCI_HCR, base + OHCI_CMDSTATUS);
-
- /* reset requires max 10 us delay */
-@@ -627,9 +617,7 @@
- break;
- udelay(1);
- }
--
-- if (!no_fminterval)
-- writel(fminterval, base + OHCI_FMINTERVAL);
-+ writel(fminterval, base + OHCI_FMINTERVAL);
-
- /* Now the controller is safely in SUSPEND and nothing can wake it up */
- iounmap(base);
-diff -Nur linux-3.12.38/drivers/usb/Makefile linux-rpi/drivers/usb/Makefile
---- linux-3.12.38/drivers/usb/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/Makefile 2015-03-10 17:26:51.278216688 +0100
-@@ -23,6 +23,7 @@
- obj-$(CONFIG_USB_R8A66597_HCD) += host/
- obj-$(CONFIG_USB_HWA_HCD) += host/
- obj-$(CONFIG_USB_ISP1760_HCD) += host/
-+obj-$(CONFIG_USB_DWCOTG) += host/
- obj-$(CONFIG_USB_IMX21_HCD) += host/
- obj-$(CONFIG_USB_FSL_MPH_DR_OF) += host/
- obj-$(CONFIG_USB_FUSBH200_HCD) += host/
-diff -Nur linux-3.12.38/drivers/usb/misc/adutux.c linux-rpi/drivers/usb/misc/adutux.c
---- linux-3.12.38/drivers/usb/misc/adutux.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/misc/adutux.c 2015-03-10 17:26:51.318216687 +0100
-@@ -815,10 +815,15 @@
- usb_set_intfdata(interface, NULL);
-
- /* if the device is not opened, then we clean up right now */
-+ dev_dbg(&dev->udev->dev, "%s : open count %d\n",
-+ __func__, dev->open_count);
- if (!dev->open_count)
- adu_delete(dev);
-
- mutex_unlock(&adutux_mutex);
-+
-+ dev_info(&interface->dev, "ADU device adutux%d now disconnected\n",
-+ (minor - ADU_MINOR_BASE));
- }
-
- /* usb specific object needed to register this driver with the usb subsystem */
-diff -Nur linux-3.12.38/drivers/usb/musb/musb_cppi41.c linux-rpi/drivers/usb/musb/musb_cppi41.c
---- linux-3.12.38/drivers/usb/musb/musb_cppi41.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/musb/musb_cppi41.c 2015-03-10 17:26:51.322216687 +0100
-@@ -586,9 +586,9 @@
- ret = of_property_read_string_index(np, "dma-names", i, &str);
- if (ret)
- goto err;
-- if (strstarts(str, "tx"))
-+ if (!strncmp(str, "tx", 2))
- is_tx = 1;
-- else if (strstarts(str, "rx"))
-+ else if (!strncmp(str, "rx", 2))
- is_tx = 0;
- else {
- dev_err(dev, "Wrong dmatype %s\n", str);
-diff -Nur linux-3.12.38/drivers/usb/musb/musb_debugfs.c linux-rpi/drivers/usb/musb/musb_debugfs.c
---- linux-3.12.38/drivers/usb/musb/musb_debugfs.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/musb/musb_debugfs.c 2015-03-09 10:39:33.242893718 +0100
-@@ -194,30 +194,30 @@
- if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
- return -EFAULT;
-
-- if (strstarts(buf, "force host"))
-+ if (!strncmp(buf, "force host", 9))
- test = MUSB_TEST_FORCE_HOST;
-
-- if (strstarts(buf, "fifo access"))
-+ if (!strncmp(buf, "fifo access", 11))
- test = MUSB_TEST_FIFO_ACCESS;
-
-- if (strstarts(buf, "force full-speed"))
-+ if (!strncmp(buf, "force full-speed", 15))
- test = MUSB_TEST_FORCE_FS;
-
-- if (strstarts(buf, "force high-speed"))
-+ if (!strncmp(buf, "force high-speed", 15))
- test = MUSB_TEST_FORCE_HS;
-
-- if (strstarts(buf, "test packet")) {
-+ if (!strncmp(buf, "test packet", 10)) {
- test = MUSB_TEST_PACKET;
- musb_load_testpacket(musb);
- }
-
-- if (strstarts(buf, "test K"))
-+ if (!strncmp(buf, "test K", 6))
- test = MUSB_TEST_K;
-
-- if (strstarts(buf, "test J"))
-+ if (!strncmp(buf, "test J", 6))
- test = MUSB_TEST_J;
-
-- if (strstarts(buf, "test SE0 NAK"))
-+ if (!strncmp(buf, "test SE0 NAK", 12))
- test = MUSB_TEST_SE0_NAK;
-
- musb_writeb(musb->mregs, MUSB_TESTMODE, test);
-diff -Nur linux-3.12.38/drivers/usb/musb/musb_host.c linux-rpi/drivers/usb/musb/musb_host.c
---- linux-3.12.38/drivers/usb/musb/musb_host.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/musb/musb_host.c 2015-03-10 17:26:51.322216687 +0100
-@@ -2631,6 +2631,7 @@
- if (musb->port_mode == MUSB_PORT_MODE_GADGET)
- return;
- usb_remove_hcd(musb->hcd);
-+ musb->hcd = NULL;
- }
-
- void musb_host_free(struct musb *musb)
-diff -Nur linux-3.12.38/drivers/usb/serial/console.c linux-rpi/drivers/usb/serial/console.c
---- linux-3.12.38/drivers/usb/serial/console.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/serial/console.c 2015-03-10 17:26:51.330216687 +0100
-@@ -47,8 +47,6 @@
- * ------------------------------------------------------------
- */
-
--static const struct tty_operations usb_console_fake_tty_ops = {
--};
-
- /*
- * The parsing of the command line works exactly like the
-@@ -141,18 +139,14 @@
- goto reset_open_count;
- }
- kref_init(&tty->kref);
-+ tty_port_tty_set(&port->port, tty);
- tty->driver = usb_serial_tty_driver;
- tty->index = co->index;
-- init_ldsem(&tty->ldisc_sem);
-- INIT_LIST_HEAD(&tty->tty_files);
-- kref_get(&tty->driver->kref);
-- tty->ops = &usb_console_fake_tty_ops;
- if (tty_init_termios(tty)) {
- retval = -ENOMEM;
- dev_err(&port->dev, "no more memory\n");
-- goto put_tty;
-+ goto free_tty;
- }
-- tty_port_tty_set(&port->port, tty);
- }
-
- /* only call the device specific open if this
-@@ -170,7 +164,7 @@
- serial->type->set_termios(tty, port, &dummy);
-
- tty_port_tty_set(&port->port, NULL);
-- tty_kref_put(tty);
-+ kfree(tty);
- }
- set_bit(ASYNCB_INITIALIZED, &port->port.flags);
- }
-@@ -186,8 +180,8 @@
-
- fail:
- tty_port_tty_set(&port->port, NULL);
-- put_tty:
-- tty_kref_put(tty);
-+ free_tty:
-+ kfree(tty);
- reset_open_count:
- port->port.count = 0;
- usb_autopm_put_interface(serial->interface);
-diff -Nur linux-3.12.38/drivers/usb/serial/cp210x.c linux-rpi/drivers/usb/serial/cp210x.c
---- linux-3.12.38/drivers/usb/serial/cp210x.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/serial/cp210x.c 2015-03-10 17:26:51.330216687 +0100
-@@ -120,12 +120,10 @@
- { USB_DEVICE(0x10C4, 0x85F8) }, /* Virtenio Preon32 */
- { USB_DEVICE(0x10C4, 0x8664) }, /* AC-Services CAN-IF */
- { USB_DEVICE(0x10C4, 0x8665) }, /* AC-Services OBD-IF */
-- { USB_DEVICE(0x10C4, 0x8856) }, /* CEL EM357 ZigBee USB Stick - LR */
-- { USB_DEVICE(0x10C4, 0x8857) }, /* CEL EM357 ZigBee USB Stick */
-+ { USB_DEVICE(0x10C4, 0x8875) }, /* CEL MeshConnect USB Stick */
- { USB_DEVICE(0x10C4, 0x88A4) }, /* MMB Networks ZigBee USB Device */
- { USB_DEVICE(0x10C4, 0x88A5) }, /* Planet Innovation Ingeni ZigBee USB Device */
- { USB_DEVICE(0x10C4, 0x8946) }, /* Ketra N1 Wireless Interface */
-- { USB_DEVICE(0x10C4, 0x8977) }, /* CEL MeshWorks DevKit Device */
- { USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */
- { USB_DEVICE(0x10C4, 0xEA61) }, /* Silicon Labs factory default */
- { USB_DEVICE(0x10C4, 0xEA70) }, /* Silicon Labs factory default */
-diff -Nur linux-3.12.38/drivers/usb/serial/keyspan.c linux-rpi/drivers/usb/serial/keyspan.c
---- linux-3.12.38/drivers/usb/serial/keyspan.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/usb/serial/keyspan.c 2015-03-10 17:26:51.334216687 +0100
-@@ -422,8 +422,6 @@
- }
- port = serial->port[msg->port];
- p_priv = usb_get_serial_port_data(port);
-- if (!p_priv)
-- goto resubmit;
-
- /* Update handshaking pin state information */
- old_dcd_state = p_priv->dcd_state;
-@@ -434,7 +432,7 @@
-
- if (old_dcd_state != p_priv->dcd_state)
- tty_port_tty_hangup(&port->port, true);
--resubmit:
-+
- /* Resubmit urb so we continue receiving */
- err = usb_submit_urb(urb, GFP_ATOMIC);
- if (err != 0)
-@@ -544,8 +542,6 @@
- }
- port = serial->port[msg->port];
- p_priv = usb_get_serial_port_data(port);
-- if (!p_priv)
-- goto resubmit;
-
- /* Update handshaking pin state information */
- old_dcd_state = p_priv->dcd_state;
-@@ -556,7 +552,7 @@
-
- if (old_dcd_state != p_priv->dcd_state && old_dcd_state)
- tty_port_tty_hangup(&port->port, true);
--resubmit:
-+
- /* Resubmit urb so we continue receiving */
- err = usb_submit_urb(urb, GFP_ATOMIC);
- if (err != 0)
-@@ -629,8 +625,6 @@
- }
- port = serial->port[msg->portNumber];
- p_priv = usb_get_serial_port_data(port);
-- if (!p_priv)
-- goto resubmit;
-
- /* Update handshaking pin state information */
- old_dcd_state = p_priv->dcd_state;
-@@ -641,7 +635,7 @@
-
- if (old_dcd_state != p_priv->dcd_state && old_dcd_state)
- tty_port_tty_hangup(&port->port, true);
--resubmit:
-+
- /* Resubmit urb so we continue receiving */
- err = usb_submit_urb(urb, GFP_ATOMIC);
- if (err != 0)
-@@ -879,8 +873,6 @@
-
- port = serial->port[0];
- p_priv = usb_get_serial_port_data(port);
-- if (!p_priv)
-- goto resubmit;
-
- /* Update handshaking pin state information */
- old_dcd_state = p_priv->dcd_state;
-@@ -891,7 +883,7 @@
-
- if (old_dcd_state != p_priv->dcd_state && old_dcd_state)
- tty_port_tty_hangup(&port->port, true);
--resubmit:
-+
- /* Resubmit urb so we continue receiving */
- err = usb_submit_urb(urb, GFP_ATOMIC);
- if (err != 0)
-@@ -952,8 +944,6 @@
-
- port = serial->port[msg->port];
- p_priv = usb_get_serial_port_data(port);
-- if (!p_priv)
-- goto resubmit;
-
- /* Update handshaking pin state information */
- old_dcd_state = p_priv->dcd_state;
-@@ -962,7 +952,7 @@
-
- if (old_dcd_state != p_priv->dcd_state && old_dcd_state)
- tty_port_tty_hangup(&port->port, true);
--resubmit:
-+
- /* Resubmit urb so we continue receiving */
- err = usb_submit_urb(urb, GFP_ATOMIC);
- if (err != 0)
-diff -Nur linux-3.12.38/drivers/vfio/pci/vfio_pci.c linux-rpi/drivers/vfio/pci/vfio_pci.c
---- linux-3.12.38/drivers/vfio/pci/vfio_pci.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/vfio/pci/vfio_pci.c 2015-03-10 17:26:51.342216687 +0100
-@@ -821,11 +821,13 @@
-
- static int vfio_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
- {
-+ u8 type;
- struct vfio_pci_device *vdev;
- struct iommu_group *group;
- int ret;
-
-- if (pdev->hdr_type != PCI_HEADER_TYPE_NORMAL)
-+ pci_read_config_byte(pdev, PCI_HEADER_TYPE, &type);
-+ if ((type & PCI_HEADER_TYPE) != PCI_HEADER_TYPE_NORMAL)
- return -EINVAL;
-
- group = iommu_group_get(&pdev->dev);
-diff -Nur linux-3.12.38/drivers/vhost/scsi.c linux-rpi/drivers/vhost/scsi.c
---- linux-3.12.38/drivers/vhost/scsi.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/vhost/scsi.c 2015-03-10 17:26:51.342216687 +0100
-@@ -861,23 +861,6 @@
- return 0;
- }
-
--static int vhost_scsi_to_tcm_attr(int attr)
--{
-- switch (attr) {
-- case VIRTIO_SCSI_S_SIMPLE:
-- return MSG_SIMPLE_TAG;
-- case VIRTIO_SCSI_S_ORDERED:
-- return MSG_ORDERED_TAG;
-- case VIRTIO_SCSI_S_HEAD:
-- return MSG_HEAD_TAG;
-- case VIRTIO_SCSI_S_ACA:
-- return MSG_ACA_TAG;
-- default:
-- break;
-- }
-- return MSG_SIMPLE_TAG;
--}
--
- static void tcm_vhost_submission_work(struct work_struct *work)
- {
- struct tcm_vhost_cmd *cmd =
-@@ -904,9 +887,9 @@
- rc = target_submit_cmd_map_sgls(se_cmd, tv_nexus->tvn_se_sess,
- cmd->tvc_cdb, &cmd->tvc_sense_buf[0],
- cmd->tvc_lun, cmd->tvc_exp_data_len,
-- vhost_scsi_to_tcm_attr(cmd->tvc_task_attr),
-- cmd->tvc_data_direction, TARGET_SCF_ACK_KREF,
-- sg_ptr, cmd->tvc_sgl_count, sg_bidi_ptr, sg_no_bidi);
-+ cmd->tvc_task_attr, cmd->tvc_data_direction,
-+ TARGET_SCF_ACK_KREF, sg_ptr, cmd->tvc_sgl_count,
-+ sg_bidi_ptr, sg_no_bidi);
- if (rc < 0) {
- transport_send_check_condition_and_sense(se_cmd,
- TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE, 0);
-diff -Nur linux-3.12.38/drivers/video/bcm2708_fb.c linux-rpi/drivers/video/bcm2708_fb.c
---- linux-3.12.38/drivers/video/bcm2708_fb.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/video/bcm2708_fb.c 2015-03-10 17:26:51.354216687 +0100
-@@ -0,0 +1,818 @@
-+/*
-+ * linux/drivers/video/bcm2708_fb.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Broadcom simple framebuffer driver
-+ *
-+ * This file is derived from cirrusfb.c
-+ * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/list.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/printk.h>
-+#include <linux/console.h>
-+#include <linux/debugfs.h>
-+
-+#include <mach/dma.h>
-+#include <mach/platform.h>
-+#include <mach/vcio.h>
-+
-+#include <asm/sizes.h>
-+#include <linux/io.h>
-+#include <linux/dma-mapping.h>
-+
-+//#define BCM2708_FB_DEBUG
-+#define MODULE_NAME "bcm2708_fb"
-+
-+#ifdef BCM2708_FB_DEBUG
-+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+
-+/* This is limited to 16 characters when displayed by X startup */
-+static const char *bcm2708_name = "BCM2708 FB";
-+
-+#define DRIVER_NAME "bcm2708_fb"
-+
-+static int fbwidth = 800; /* module parameter */
-+static int fbheight = 480; /* module parameter */
-+static int fbdepth = 16; /* module parameter */
-+static int fbswap = 0; /* module parameter */
-+
-+static u32 dma_busy_wait_threshold = 1<<15;
-+module_param(dma_busy_wait_threshold, int, 0644);
-+MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area");
-+
-+/* this data structure describes each frame buffer device we find */
-+
-+struct fbinfo_s {
-+ u32 xres, yres, xres_virtual, yres_virtual;
-+ u32 pitch, bpp;
-+ u32 xoffset, yoffset;
-+ u32 base;
-+ u32 screen_size;
-+ u16 cmap[256];
-+};
-+
-+struct bcm2708_fb_stats {
-+ struct debugfs_regset32 regset;
-+ u32 dma_copies;
-+ u32 dma_irqs;
-+};
-+
-+struct bcm2708_fb {
-+ struct fb_info fb;
-+ struct platform_device *dev;
-+ struct fbinfo_s *info;
-+ dma_addr_t dma;
-+ u32 cmap[16];
-+ int dma_chan;
-+ int dma_irq;
-+ void __iomem *dma_chan_base;
-+ void *cb_base; /* DMA control blocks */
-+ dma_addr_t cb_handle;
-+ struct dentry *debugfs_dir;
-+ wait_queue_head_t dma_waitq;
-+ struct bcm2708_fb_stats stats;
-+ unsigned long fb_bus_address;
-+};
-+
-+#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb)
-+
-+static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb)
-+{
-+ debugfs_remove_recursive(fb->debugfs_dir);
-+ fb->debugfs_dir = NULL;
-+}
-+
-+static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb)
-+{
-+ static struct debugfs_reg32 stats_registers[] = {
-+ {
-+ "dma_copies",
-+ offsetof(struct bcm2708_fb_stats, dma_copies)
-+ },
-+ {
-+ "dma_irqs",
-+ offsetof(struct bcm2708_fb_stats, dma_irqs)
-+ },
-+ };
-+
-+ fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);
-+ if (!fb->debugfs_dir) {
-+ pr_warn("%s: could not create debugfs entry\n",
-+ __func__);
-+ return -EFAULT;
-+ }
-+
-+ fb->stats.regset.regs = stats_registers;
-+ fb->stats.regset.nregs = ARRAY_SIZE(stats_registers);
-+ fb->stats.regset.base = &fb->stats;
-+
-+ if (!debugfs_create_regset32(
-+ "stats", 0444, fb->debugfs_dir, &fb->stats.regset)) {
-+ pr_warn("%s: could not create statistics registers\n",
-+ __func__);
-+ goto fail;
-+ }
-+ return 0;
-+
-+fail:
-+ bcm2708_fb_debugfs_deinit(fb);
-+ return -EFAULT;
-+}
-+
-+static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var)
-+{
-+ int ret = 0;
-+
-+ memset(&var->transp, 0, sizeof(var->transp));
-+
-+ var->red.msb_right = 0;
-+ var->green.msb_right = 0;
-+ var->blue.msb_right = 0;
-+
-+ switch (var->bits_per_pixel) {
-+ case 1:
-+ case 2:
-+ case 4:
-+ case 8:
-+ var->red.length = var->bits_per_pixel;
-+ var->red.offset = 0;
-+ var->green.length = var->bits_per_pixel;
-+ var->green.offset = 0;
-+ var->blue.length = var->bits_per_pixel;
-+ var->blue.offset = 0;
-+ break;
-+ case 16:
-+ var->red.length = 5;
-+ var->blue.length = 5;
-+ /*
-+ * Green length can be 5 or 6 depending whether
-+ * we're operating in RGB555 or RGB565 mode.
-+ */
-+ if (var->green.length != 5 && var->green.length != 6)
-+ var->green.length = 6;
-+ break;
-+ case 24:
-+ var->red.length = 8;
-+ var->blue.length = 8;
-+ var->green.length = 8;
-+ break;
-+ case 32:
-+ var->red.length = 8;
-+ var->green.length = 8;
-+ var->blue.length = 8;
-+ var->transp.length = 8;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ /*
-+ * >= 16bpp displays have separate colour component bitfields
-+ * encoded in the pixel data. Calculate their position from
-+ * the bitfield length defined above.
-+ */
-+ if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) {
-+ var->blue.offset = 0;
-+ var->green.offset = var->blue.offset + var->blue.length;
-+ var->red.offset = var->green.offset + var->green.length;
-+ var->transp.offset = var->red.offset + var->red.length;
-+ } else if (ret == 0 && var->bits_per_pixel >= 24) {
-+ var->red.offset = 0;
-+ var->green.offset = var->red.offset + var->red.length;
-+ var->blue.offset = var->green.offset + var->green.length;
-+ var->transp.offset = var->blue.offset + var->blue.length;
-+ } else if (ret == 0 && var->bits_per_pixel >= 16) {
-+ var->blue.offset = 0;
-+ var->green.offset = var->blue.offset + var->blue.length;
-+ var->red.offset = var->green.offset + var->green.length;
-+ var->transp.offset = var->red.offset + var->red.length;
-+ }
-+
-+ return ret;
-+}
-+
-+static int bcm2708_fb_check_var(struct fb_var_screeninfo *var,
-+ struct fb_info *info)
-+{
-+ /* info input, var output */
-+ int yres;
-+
-+ /* info input, var output */
-+ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+ info->var.xres, info->var.yres, info->var.xres_virtual,
-+ info->var.yres_virtual, (int)info->screen_size,
-+ info->var.bits_per_pixel);
-+ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var,
-+ var->xres, var->yres, var->xres_virtual, var->yres_virtual,
-+ var->bits_per_pixel);
-+
-+ if (!var->bits_per_pixel)
-+ var->bits_per_pixel = 16;
-+
-+ if (bcm2708_fb_set_bitfields(var) != 0) {
-+ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n",
-+ var->bits_per_pixel);
-+ return -EINVAL;
-+ }
-+
-+
-+ if (var->xres_virtual < var->xres)
-+ var->xres_virtual = var->xres;
-+ /* use highest possible virtual resolution */
-+ if (var->yres_virtual == -1) {
-+ var->yres_virtual = 480;
-+
-+ pr_err
-+ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n",
-+ var->xres_virtual, var->yres_virtual);
-+ }
-+ if (var->yres_virtual < var->yres)
-+ var->yres_virtual = var->yres;
-+
-+ if (var->xoffset < 0)
-+ var->xoffset = 0;
-+ if (var->yoffset < 0)
-+ var->yoffset = 0;
-+
-+ /* truncate xoffset and yoffset to maximum if too high */
-+ if (var->xoffset > var->xres_virtual - var->xres)
-+ var->xoffset = var->xres_virtual - var->xres - 1;
-+ if (var->yoffset > var->yres_virtual - var->yres)
-+ var->yoffset = var->yres_virtual - var->yres - 1;
-+
-+ yres = var->yres;
-+ if (var->vmode & FB_VMODE_DOUBLE)
-+ yres *= 2;
-+ else if (var->vmode & FB_VMODE_INTERLACED)
-+ yres = (yres + 1) / 2;
-+
-+ return 0;
-+}
-+
-+static int bcm2708_fb_set_par(struct fb_info *info)
-+{
-+ uint32_t val = 0;
-+ struct bcm2708_fb *fb = to_bcm2708(info);
-+ volatile struct fbinfo_s *fbinfo = fb->info;
-+ fbinfo->xres = info->var.xres;
-+ fbinfo->yres = info->var.yres;
-+ fbinfo->xres_virtual = info->var.xres_virtual;
-+ fbinfo->yres_virtual = info->var.yres_virtual;
-+ fbinfo->bpp = info->var.bits_per_pixel;
-+ fbinfo->xoffset = info->var.xoffset;
-+ fbinfo->yoffset = info->var.yoffset;
-+ fbinfo->base = 0; /* filled in by VC */
-+ fbinfo->pitch = 0; /* filled in by VC */
-+
-+ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+ info->var.xres, info->var.yres, info->var.xres_virtual,
-+ info->var.yres_virtual, (int)info->screen_size,
-+ info->var.bits_per_pixel);
-+
-+ /* ensure last write to fbinfo is visible to GPU */
-+ wmb();
-+
-+ /* inform vc about new framebuffer */
-+ bcm_mailbox_write(MBOX_CHAN_FB, fb->dma);
-+
-+ /* TODO: replace fb driver with vchiq version */
-+ /* wait for response */
-+ bcm_mailbox_read(MBOX_CHAN_FB, &val);
-+
-+ /* ensure GPU writes are visible to us */
-+ rmb();
-+
-+ if (val == 0) {
-+ fb->fb.fix.line_length = fbinfo->pitch;
-+
-+ if (info->var.bits_per_pixel <= 8)
-+ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
-+ else
-+ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
-+
-+ fb->fb_bus_address = fbinfo->base;
-+ fbinfo->base &= ~0xc0000000;
-+ fb->fb.fix.smem_start = fbinfo->base;
-+ fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual;
-+ fb->fb.screen_size = fbinfo->screen_size;
-+ if (fb->fb.screen_base)
-+ iounmap(fb->fb.screen_base);
-+ fb->fb.screen_base =
-+ (void *)ioremap_wc(fbinfo->base, fb->fb.screen_size);
-+ if (!fb->fb.screen_base) {
-+ /* the console may currently be locked */
-+ console_trylock();
-+ console_unlock();
-+
-+ BUG(); /* what can we do here */
-+ }
-+ }
-+ print_debug
-+ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n",
-+ (void *)fb->fb.screen_base, (void *)fb->fb_bus_address,
-+ fbinfo->xres, fbinfo->yres, fbinfo->bpp,
-+ fbinfo->pitch, (int)fb->fb.screen_size, val);
-+
-+ return val;
-+}
-+
-+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
-+{
-+ unsigned int mask = (1 << bf->length) - 1;
-+
-+ return (val >> (16 - bf->length) & mask) << bf->offset;
-+}
-+
-+
-+static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red,
-+ unsigned int green, unsigned int blue,
-+ unsigned int transp, struct fb_info *info)
-+{
-+ struct bcm2708_fb *fb = to_bcm2708(info);
-+
-+ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/
-+ if (fb->fb.var.bits_per_pixel <= 8) {
-+ if (regno < 256) {
-+ /* blue [0:4], green [5:10], red [11:15] */
-+ fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 |
-+ ((green >> (16-6)) & 0x3f) << 5 |
-+ ((blue >> (16-5)) & 0x1f) << 0;
-+ }
-+ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */
-+ /* So just call it for what looks like the last colour in a list for now. */
-+ if (regno == 15 || regno == 255)
-+ bcm2708_fb_set_par(info);
-+ } else if (regno < 16) {
-+ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
-+ convert_bitfield(blue, &fb->fb.var.blue) |
-+ convert_bitfield(green, &fb->fb.var.green) |
-+ convert_bitfield(red, &fb->fb.var.red);
-+ }
-+ return regno > 255;
-+}
-+
-+static int bcm2708_fb_blank(int blank_mode, struct fb_info *info)
-+{
-+ s32 result = -1;
-+ u32 p[7];
-+ if ( (blank_mode == FB_BLANK_NORMAL) ||
-+ (blank_mode == FB_BLANK_UNBLANK)) {
-+
-+ p[0] = 28; // size = sizeof u32 * length of p
-+ p[1] = VCMSG_PROCESS_REQUEST; // process request
-+ p[2] = VCMSG_SET_BLANK_SCREEN; // (the tag id)
-+ p[3] = 4; // (size of the response buffer)
-+ p[4] = 4; // (size of the request data)
-+ p[5] = blank_mode;
-+ p[6] = VCMSG_PROPERTY_END; // end tag
-+
-+ bcm_mailbox_property(&p, p[0]);
-+
-+ if ( p[1] == VCMSG_REQUEST_SUCCESSFUL )
-+ result = 0;
-+ else
-+ pr_err("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]);
-+ }
-+ return result;
-+}
-+
-+static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-+{
-+ s32 result = -1;
-+ info->var.xoffset = var->xoffset;
-+ info->var.yoffset = var->yoffset;
-+ result = bcm2708_fb_set_par(info);
-+ if (result != 0)
-+ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result);
-+ return result;
-+}
-+
-+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
-+{
-+ s32 result = -1;
-+ u32 p[7];
-+ if (cmd == FBIO_WAITFORVSYNC) {
-+ p[0] = 28; // size = sizeof u32 * length of p
-+ p[1] = VCMSG_PROCESS_REQUEST; // process request
-+ p[2] = VCMSG_SET_VSYNC; // (the tag id)
-+ p[3] = 4; // (size of the response buffer)
-+ p[4] = 4; // (size of the request data)
-+ p[5] = 0; // dummy
-+ p[6] = VCMSG_PROPERTY_END; // end tag
-+
-+ bcm_mailbox_property(&p, p[0]);
-+
-+ pr_info("bcm2708_fb_ioctl %x,%lx returns=%d p[1]=0x%x\n", cmd, arg, p[5], p[1]);
-+
-+ if ( p[1] == VCMSG_REQUEST_SUCCESSFUL )
-+ result = 0;
-+ }
-+ return result;
-+}
-+static void bcm2708_fb_fillrect(struct fb_info *info,
-+ const struct fb_fillrect *rect)
-+{
-+ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */
-+ cfb_fillrect(info, rect);
-+}
-+
-+/* A helper function for configuring dma control block */
-+static void set_dma_cb(struct bcm2708_dma_cb *cb,
-+ int burst_size,
-+ dma_addr_t dst,
-+ int dst_stride,
-+ dma_addr_t src,
-+ int src_stride,
-+ int w,
-+ int h)
-+{
-+ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |
-+ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |
-+ BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;
-+ cb->dst = dst;
-+ cb->src = src;
-+ /*
-+ * This is not really obvious from the DMA documentation,
-+ * but the top 16 bits must be programmmed to "height -1"
-+ * and not "height" in 2D mode.
-+ */
-+ cb->length = ((h - 1) << 16) | w;
-+ cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w);
-+ cb->pad[0] = 0;
-+ cb->pad[1] = 0;
-+}
-+
-+static void bcm2708_fb_copyarea(struct fb_info *info,
-+ const struct fb_copyarea *region)
-+{
-+ struct bcm2708_fb *fb = to_bcm2708(info);
-+ struct bcm2708_dma_cb *cb = fb->cb_base;
-+ int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;
-+ /* Channel 0 supports larger bursts and is a bit faster */
-+ int burst_size = (fb->dma_chan == 0) ? 8 : 2;
-+ int pixels = region->width * region->height;
-+
-+ /* Fallback to cfb_copyarea() if we don't like something */
-+ if (in_atomic() ||
-+ bytes_per_pixel > 4 ||
-+ info->var.xres * info->var.yres > 1920 * 1200 ||
-+ region->width <= 0 || region->width > info->var.xres ||
-+ region->height <= 0 || region->height > info->var.yres ||
-+ region->sx < 0 || region->sx >= info->var.xres ||
-+ region->sy < 0 || region->sy >= info->var.yres ||
-+ region->dx < 0 || region->dx >= info->var.xres ||
-+ region->dy < 0 || region->dy >= info->var.yres ||
-+ region->sx + region->width > info->var.xres ||
-+ region->dx + region->width > info->var.xres ||
-+ region->sy + region->height > info->var.yres ||
-+ region->dy + region->height > info->var.yres) {
-+ cfb_copyarea(info, region);
-+ return;
-+ }
-+
-+ if (region->dy == region->sy && region->dx > region->sx) {
-+ /*
-+ * A difficult case of overlapped copy. Because DMA can't
-+ * copy individual scanlines in backwards direction, we need
-+ * two-pass processing. We do it by programming a chain of dma
-+ * control blocks in the first 16K part of the buffer and use
-+ * the remaining 48K as the intermediate temporary scratch
-+ * buffer. The buffer size is sufficient to handle up to
-+ * 1920x1200 resolution at 32bpp pixel depth.
-+ */
-+ int y;
-+ dma_addr_t control_block_pa = fb->cb_handle;
-+ dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024;
-+ int scanline_size = bytes_per_pixel * region->width;
-+ int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size;
-+
-+ for (y = 0; y < region->height; y += scanlines_per_cb) {
-+ dma_addr_t src =
-+ fb->fb_bus_address +
-+ bytes_per_pixel * region->sx +
-+ (region->sy + y) * fb->fb.fix.line_length;
-+ dma_addr_t dst =
-+ fb->fb_bus_address +
-+ bytes_per_pixel * region->dx +
-+ (region->dy + y) * fb->fb.fix.line_length;
-+
-+ if (region->height - y < scanlines_per_cb)
-+ scanlines_per_cb = region->height - y;
-+
-+ set_dma_cb(cb, burst_size, scratchbuf, scanline_size,
-+ src, fb->fb.fix.line_length,
-+ scanline_size, scanlines_per_cb);
-+ control_block_pa += sizeof(struct bcm2708_dma_cb);
-+ cb->next = control_block_pa;
-+ cb++;
-+
-+ set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length,
-+ scratchbuf, scanline_size,
-+ scanline_size, scanlines_per_cb);
-+ control_block_pa += sizeof(struct bcm2708_dma_cb);
-+ cb->next = control_block_pa;
-+ cb++;
-+ }
-+ /* move the pointer back to the last dma control block */
-+ cb--;
-+ } else {
-+ /* A single dma control block is enough. */
-+ int sy, dy, stride;
-+ if (region->dy <= region->sy) {
-+ /* processing from top to bottom */
-+ dy = region->dy;
-+ sy = region->sy;
-+ stride = fb->fb.fix.line_length;
-+ } else {
-+ /* processing from bottom to top */
-+ dy = region->dy + region->height - 1;
-+ sy = region->sy + region->height - 1;
-+ stride = -fb->fb.fix.line_length;
-+ }
-+ set_dma_cb(cb, burst_size,
-+ fb->fb_bus_address + dy * fb->fb.fix.line_length +
-+ bytes_per_pixel * region->dx,
-+ stride,
-+ fb->fb_bus_address + sy * fb->fb.fix.line_length +
-+ bytes_per_pixel * region->sx,
-+ stride,
-+ region->width * bytes_per_pixel,
-+ region->height);
-+ }
-+
-+ /* end of dma control blocks chain */
-+ cb->next = 0;
-+
-+
-+ if (pixels < dma_busy_wait_threshold) {
-+ bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+ bcm_dma_wait_idle(fb->dma_chan_base);
-+ } else {
-+ void __iomem *dma_chan = fb->dma_chan_base;
-+ cb->info |= BCM2708_DMA_INT_EN;
-+ bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+ while (bcm_dma_is_busy(dma_chan)) {
-+ wait_event_interruptible(
-+ fb->dma_waitq,
-+ !bcm_dma_is_busy(dma_chan));
-+ }
-+ fb->stats.dma_irqs++;
-+ }
-+ fb->stats.dma_copies++;
-+}
-+
-+static void bcm2708_fb_imageblit(struct fb_info *info,
-+ const struct fb_image *image)
-+{
-+ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */
-+ cfb_imageblit(info, image);
-+}
-+
-+static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt)
-+{
-+ struct bcm2708_fb *fb = cxt;
-+
-+ /* FIXME: should read status register to check if this is
-+ * actually interrupting us or not, in case this interrupt
-+ * ever becomes shared amongst several DMA channels
-+ *
-+ * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ;
-+ */
-+
-+ /* acknowledge the interrupt */
-+ writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS);
-+
-+ wake_up(&fb->dma_waitq);
-+ return IRQ_HANDLED;
-+}
-+
-+static struct fb_ops bcm2708_fb_ops = {
-+ .owner = THIS_MODULE,
-+ .fb_check_var = bcm2708_fb_check_var,
-+ .fb_set_par = bcm2708_fb_set_par,
-+ .fb_setcolreg = bcm2708_fb_setcolreg,
-+ .fb_blank = bcm2708_fb_blank,
-+ .fb_fillrect = bcm2708_fb_fillrect,
-+ .fb_copyarea = bcm2708_fb_copyarea,
-+ .fb_imageblit = bcm2708_fb_imageblit,
-+ .fb_pan_display = bcm2708_fb_pan_display,
-+ .fb_ioctl = bcm2708_ioctl,
-+};
-+
-+static int bcm2708_fb_register(struct bcm2708_fb *fb)
-+{
-+ int ret;
-+ dma_addr_t dma;
-+ void *mem;
-+
-+ mem =
-+ dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), &dma,
-+ GFP_KERNEL);
-+
-+ if (NULL == mem) {
-+ pr_err(": unable to allocate fbinfo buffer\n");
-+ ret = -ENOMEM;
-+ } else {
-+ fb->info = (struct fbinfo_s *)mem;
-+ fb->dma = dma;
-+ }
-+ fb->fb.fbops = &bcm2708_fb_ops;
-+ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA;
-+ fb->fb.pseudo_palette = fb->cmap;
-+
-+ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id));
-+ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
-+ fb->fb.fix.type_aux = 0;
-+ fb->fb.fix.xpanstep = 1;
-+ fb->fb.fix.ypanstep = 1;
-+ fb->fb.fix.ywrapstep = 0;
-+ fb->fb.fix.accel = FB_ACCEL_NONE;
-+
-+ fb->fb.var.xres = fbwidth;
-+ fb->fb.var.yres = fbheight;
-+ fb->fb.var.xres_virtual = fbwidth;
-+ fb->fb.var.yres_virtual = fbheight;
-+ fb->fb.var.bits_per_pixel = fbdepth;
-+ fb->fb.var.vmode = FB_VMODE_NONINTERLACED;
-+ fb->fb.var.activate = FB_ACTIVATE_NOW;
-+ fb->fb.var.nonstd = 0;
-+ fb->fb.var.height = -1; /* height of picture in mm */
-+ fb->fb.var.width = -1; /* width of picture in mm */
-+ fb->fb.var.accel_flags = 0;
-+
-+ fb->fb.monspecs.hfmin = 0;
-+ fb->fb.monspecs.hfmax = 100000;
-+ fb->fb.monspecs.vfmin = 0;
-+ fb->fb.monspecs.vfmax = 400;
-+ fb->fb.monspecs.dclkmin = 1000000;
-+ fb->fb.monspecs.dclkmax = 100000000;
-+
-+ bcm2708_fb_set_bitfields(&fb->fb.var);
-+ init_waitqueue_head(&fb->dma_waitq);
-+
-+ /*
-+ * Allocate colourmap.
-+ */
-+
-+ fb_set_var(&fb->fb, &fb->fb.var);
-+ bcm2708_fb_set_par(&fb->fb);
-+
-+ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth
-+ fbheight, fbdepth, fbswap);
-+
-+ ret = register_framebuffer(&fb->fb);
-+ print_debug("BCM2708FB: register framebuffer (%d)\n", ret);
-+ if (ret == 0)
-+ goto out;
-+
-+ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret);
-+out:
-+ return ret;
-+}
-+
-+static int bcm2708_fb_probe(struct platform_device *dev)
-+{
-+ struct bcm2708_fb *fb;
-+ int ret;
-+
-+ fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL);
-+ if (!fb) {
-+ dev_err(&dev->dev,
-+ "could not allocate new bcm2708_fb struct\n");
-+ ret = -ENOMEM;
-+ goto free_region;
-+ }
-+
-+ bcm2708_fb_debugfs_init(fb);
-+
-+ fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K,
-+ &fb->cb_handle, GFP_KERNEL);
-+ if (!fb->cb_base) {
-+ dev_err(&dev->dev, "cannot allocate DMA CBs\n");
-+ ret = -ENOMEM;
-+ goto free_fb;
-+ }
-+
-+ pr_info("BCM2708FB: allocated DMA memory %08x\n",
-+ fb->cb_handle);
-+
-+ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK,
-+ &fb->dma_chan_base, &fb->dma_irq);
-+ if (ret < 0) {
-+ dev_err(&dev->dev, "couldn't allocate a DMA channel\n");
-+ goto free_cb;
-+ }
-+ fb->dma_chan = ret;
-+
-+ ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq,
-+ 0, "bcm2708_fb dma", fb);
-+ if (ret) {
-+ pr_err("%s: failed to request DMA irq\n", __func__);
-+ goto free_dma_chan;
-+ }
-+
-+
-+ pr_info("BCM2708FB: allocated DMA channel %d @ %p\n",
-+ fb->dma_chan, fb->dma_chan_base);
-+
-+ fb->dev = dev;
-+
-+ ret = bcm2708_fb_register(fb);
-+ if (ret == 0) {
-+ platform_set_drvdata(dev, fb);
-+ goto out;
-+ }
-+
-+free_dma_chan:
-+ bcm_dma_chan_free(fb->dma_chan);
-+free_cb:
-+ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
-+free_fb:
-+ kfree(fb);
-+free_region:
-+ dev_err(&dev->dev, "probe failed, err %d\n", ret);
-+out:
-+ return ret;
-+}
-+
-+static int bcm2708_fb_remove(struct platform_device *dev)
-+{
-+ struct bcm2708_fb *fb = platform_get_drvdata(dev);
-+
-+ platform_set_drvdata(dev, NULL);
-+
-+ if (fb->fb.screen_base)
-+ iounmap(fb->fb.screen_base);
-+ unregister_framebuffer(&fb->fb);
-+
-+ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
-+ bcm_dma_chan_free(fb->dma_chan);
-+
-+ dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info,
-+ fb->dma);
-+ bcm2708_fb_debugfs_deinit(fb);
-+
-+ free_irq(fb->dma_irq, fb);
-+
-+ kfree(fb);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm2708_fb_driver = {
-+ .probe = bcm2708_fb_probe,
-+ .remove = bcm2708_fb_remove,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init bcm2708_fb_init(void)
-+{
-+ return platform_driver_register(&bcm2708_fb_driver);
-+}
-+
-+module_init(bcm2708_fb_init);
-+
-+static void __exit bcm2708_fb_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_fb_driver);
-+}
-+
-+module_exit(bcm2708_fb_exit);
-+
-+module_param(fbwidth, int, 0644);
-+module_param(fbheight, int, 0644);
-+module_param(fbdepth, int, 0644);
-+module_param(fbswap, int, 0644);
-+
-+MODULE_DESCRIPTION("BCM2708 framebuffer driver");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer");
-+MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer");
-+MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer");
-+MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes");
-diff -Nur linux-3.12.38/drivers/video/cfbimgblt.c linux-rpi/drivers/video/cfbimgblt.c
---- linux-3.12.38/drivers/video/cfbimgblt.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/video/cfbimgblt.c 2015-03-10 17:26:51.354216687 +0100
-@@ -28,6 +28,11 @@
- *
- * Also need to add code to deal with cards endians that are different than
- * the native cpu endians. I also need to deal with MSB position in the word.
-+ * Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013:
-+ * - Provide optimized versions of fast_imageblit for 16 and 32bpp that are
-+ * significantly faster than the previous implementation.
-+ * - Simplify the fast/slow_imageblit selection code, avoiding integer
-+ * divides.
- */
- #include <linux/module.h>
- #include <linux/string.h>
-@@ -262,6 +267,133 @@
- }
- }
-
-+/*
-+ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded
-+ * into the code, main loop unrolled.
-+ */
-+
-+static inline void fast_imageblit16(const struct fb_image *image,
-+ struct fb_info *p, u8 __iomem * dst1,
-+ u32 fgcolor, u32 bgcolor)
-+{
-+ u32 fgx = fgcolor, bgx = bgcolor;
-+ u32 spitch = (image->width + 7) / 8;
-+ u32 end_mask, eorx;
-+ const char *s = image->data, *src;
-+ u32 __iomem *dst;
-+ const u32 *tab = NULL;
-+ int i, j, k;
-+
-+ tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;
-+
-+ fgx <<= 16;
-+ bgx <<= 16;
-+ fgx |= fgcolor;
-+ bgx |= bgcolor;
-+
-+ eorx = fgx ^ bgx;
-+ k = image->width / 2;
-+
-+ for (i = image->height; i--;) {
-+ dst = (u32 __iomem *) dst1;
-+ src = s;
-+
-+ j = k;
-+ while (j >= 4) {
-+ u8 bits = *src;
-+ end_mask = tab[(bits >> 6) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 4) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 2) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[bits & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ src++;
-+ j -= 4;
-+ }
-+ if (j != 0) {
-+ u8 bits = *src;
-+ end_mask = tab[(bits >> 6) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ if (j >= 2) {
-+ end_mask = tab[(bits >> 4) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ if (j == 3) {
-+ end_mask = tab[(bits >> 2) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst);
-+ }
-+ }
-+ }
-+ dst1 += p->fix.line_length;
-+ s += spitch;
-+ }
-+}
-+
-+/*
-+ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded
-+ * into the code, main loop unrolled.
-+ */
-+
-+static inline void fast_imageblit32(const struct fb_image *image,
-+ struct fb_info *p, u8 __iomem * dst1,
-+ u32 fgcolor, u32 bgcolor)
-+{
-+ u32 fgx = fgcolor, bgx = bgcolor;
-+ u32 spitch = (image->width + 7) / 8;
-+ u32 end_mask, eorx;
-+ const char *s = image->data, *src;
-+ u32 __iomem *dst;
-+ const u32 *tab = NULL;
-+ int i, j, k;
-+
-+ tab = cfb_tab32;
-+
-+ eorx = fgx ^ bgx;
-+ k = image->width;
-+
-+ for (i = image->height; i--;) {
-+ dst = (u32 __iomem *) dst1;
-+ src = s;
-+
-+ j = k;
-+ while (j >= 8) {
-+ u8 bits = *src;
-+ end_mask = tab[(bits >> 7) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 6) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 5) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 4) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 3) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 2) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 1) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[bits & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ src++;
-+ j -= 8;
-+ }
-+ if (j != 0) {
-+ u32 bits = (u32) * src;
-+ while (j > 1) {
-+ end_mask = tab[(bits >> 7) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ bits <<= 1;
-+ j--;
-+ }
-+ end_mask = tab[(bits >> 7) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst);
-+ }
-+ dst1 += p->fix.line_length;
-+ s += spitch;
-+ }
-+}
-+
- void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
- {
- u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
-@@ -294,11 +426,21 @@
- bgcolor = image->bg_color;
- }
-
-- if (32 % bpp == 0 && !start_index && !pitch_index &&
-- ((width & (32/bpp-1)) == 0) &&
-- bpp >= 8 && bpp <= 32)
-- fast_imageblit(image, p, dst1, fgcolor, bgcolor);
-- else
-+ if (!start_index && !pitch_index) {
-+ if (bpp == 32)
-+ fast_imageblit32(image, p, dst1, fgcolor,
-+ bgcolor);
-+ else if (bpp == 16 && (width & 1) == 0)
-+ fast_imageblit16(image, p, dst1, fgcolor,
-+ bgcolor);
-+ else if (bpp == 8 && (width & 3) == 0)
-+ fast_imageblit(image, p, dst1, fgcolor,
-+ bgcolor);
-+ else
-+ slow_imageblit(image, p, dst1, fgcolor,
-+ bgcolor,
-+ start_index, pitch_index);
-+ } else
- slow_imageblit(image, p, dst1, fgcolor, bgcolor,
- start_index, pitch_index);
- } else
-diff -Nur linux-3.12.38/drivers/video/fbmem.c linux-rpi/drivers/video/fbmem.c
---- linux-3.12.38/drivers/video/fbmem.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/video/fbmem.c 2015-03-10 17:26:51.358216687 +0100
-@@ -1083,6 +1083,25 @@
- }
- EXPORT_SYMBOL(fb_blank);
-
-+static int fb_copyarea_user(struct fb_info *info,
-+ struct fb_copyarea *copy)
-+{
-+ int ret = 0;
-+ if (!lock_fb_info(info))
-+ return -ENODEV;
-+ if (copy->dx + copy->width > info->var.xres ||
-+ copy->sx + copy->width > info->var.xres ||
-+ copy->dy + copy->height > info->var.yres ||
-+ copy->sy + copy->height > info->var.yres) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ info->fbops->fb_copyarea(info, copy);
-+out:
-+ unlock_fb_info(info);
-+ return ret;
-+}
-+
- static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
- unsigned long arg)
- {
-@@ -1093,6 +1112,7 @@
- struct fb_cmap cmap_from;
- struct fb_cmap_user cmap;
- struct fb_event event;
-+ struct fb_copyarea copy;
- void __user *argp = (void __user *)arg;
- long ret = 0;
-
-@@ -1210,6 +1230,15 @@
- unlock_fb_info(info);
- console_unlock();
- break;
-+ case FBIOCOPYAREA:
-+ if (info->flags & FBINFO_HWACCEL_COPYAREA) {
-+ /* only provide this ioctl if it is accelerated */
-+ if (copy_from_user(&copy, argp, sizeof(copy)))
-+ return -EFAULT;
-+ ret = fb_copyarea_user(info, &copy);
-+ break;
-+ }
-+ /* fall through */
- default:
- if (!lock_fb_info(info))
- return -ENODEV;
-@@ -1364,6 +1393,7 @@
- case FBIOPAN_DISPLAY:
- case FBIOGET_CON2FBMAP:
- case FBIOPUT_CON2FBMAP:
-+ case FBIOCOPYAREA:
- arg = (unsigned long) compat_ptr(arg);
- case FBIOBLANK:
- ret = do_fb_ioctl(info, cmd, arg);
-diff -Nur linux-3.12.38/drivers/video/Kconfig linux-rpi/drivers/video/Kconfig
---- linux-3.12.38/drivers/video/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/video/Kconfig 2015-03-10 17:26:51.346216687 +0100
-@@ -310,6 +310,20 @@
- help
- Support the Permedia2 FIFO disconnect feature.
-
-+config FB_BCM2708
-+ tristate "BCM2708 framebuffer support"
-+ depends on FB && ARM
-+ select FB_CFB_FILLRECT
-+ select FB_CFB_COPYAREA
-+ select FB_CFB_IMAGEBLIT
-+ help
-+ This framebuffer device driver is for the BCM2708 framebuffer.
-+
-+ If you want to compile this as a module (=code which can be
-+ inserted into and removed from the running kernel), say M
-+ here and read <file:Documentation/kbuild/modules.txt>. The module
-+ will be called bcm2708_fb.
-+
- config FB_ARMCLCD
- tristate "ARM PrimeCell PL110 support"
- depends on FB && ARM && ARM_AMBA
-diff -Nur linux-3.12.38/drivers/video/logo/logo.c linux-rpi/drivers/video/logo/logo.c
---- linux-3.12.38/drivers/video/logo/logo.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/video/logo/logo.c 2015-03-10 17:26:51.362216687 +0100
-@@ -25,21 +25,6 @@
- module_param(nologo, bool, 0);
- MODULE_PARM_DESC(nologo, "Disables startup logo");
-
--/*
-- * Logos are located in the initdata, and will be freed in kernel_init.
-- * Use late_init to mark the logos as freed to prevent any further use.
-- */
--
--static bool logos_freed;
--
--static int __init fb_logo_late_init(void)
--{
-- logos_freed = true;
-- return 0;
--}
--
--late_initcall(fb_logo_late_init);
--
- /* logo's are marked __initdata. Use __init_refok to tell
- * modpost that it is intended that this function uses data
- * marked __initdata.
-@@ -48,7 +33,7 @@
- {
- const struct linux_logo *logo = NULL;
-
-- if (nologo || logos_freed)
-+ if (nologo)
- return NULL;
-
- if (depth >= 1) {
-diff -Nur linux-3.12.38/drivers/video/logo/logo_linux_clut224.ppm linux-rpi/drivers/video/logo/logo_linux_clut224.ppm
---- linux-3.12.38/drivers/video/logo/logo_linux_clut224.ppm 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/video/logo/logo_linux_clut224.ppm 2015-03-09 10:39:33.534893716 +0100
-@@ -1,1604 +1,883 @@
- P3
--# Standard 224-color Linux logo
--80 80
-+63 80
- 255
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 6 6 6 10 10 10 10 10 10
-- 10 10 10 6 6 6 6 6 6 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 10 10 10 14 14 14
-- 22 22 22 26 26 26 30 30 30 34 34 34
-- 30 30 30 30 30 30 26 26 26 18 18 18
-- 14 14 14 10 10 10 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 14 14 14 26 26 26 42 42 42
-- 54 54 54 66 66 66 78 78 78 78 78 78
-- 78 78 78 74 74 74 66 66 66 54 54 54
-- 42 42 42 26 26 26 18 18 18 10 10 10
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 22 22 22 42 42 42 66 66 66 86 86 86
-- 66 66 66 38 38 38 38 38 38 22 22 22
-- 26 26 26 34 34 34 54 54 54 66 66 66
-- 86 86 86 70 70 70 46 46 46 26 26 26
-- 14 14 14 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 10 10 10 26 26 26
-- 50 50 50 82 82 82 58 58 58 6 6 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 6 6 6 54 54 54 86 86 86 66 66 66
-- 38 38 38 18 18 18 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 22 22 22 50 50 50
-- 78 78 78 34 34 34 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 6 6 6 70 70 70
-- 78 78 78 46 46 46 22 22 22 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
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-- 10 10 10 30 30 30 66 66 66 58 58 58
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 26 26 26
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-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 30 30 30
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-- 2 2 6 2 2 6 2 2 6 2 2 6
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-- 2 2 6 2 2 6 2 2 6 2 2 6
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-- 2 2 6 2 2 6 2 2 6 2 2 6
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-- 2 2 6 2 2 6 2 2 6 2 2 6
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-- 46 46 46 86 86 86 2 2 6 14 14 14
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-- 46 46 46 86 86 86 2 2 6 54 54 54
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-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 34 34 34 66 66 66 78 78 78 6 6 6
-- 2 2 6 18 18 18 218 218 218 253 253 253
--253 253 253 253 253 253 253 253 253 246 246 246
--226 226 226 231 231 231 246 246 246 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 178 178 178 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 18 18 18 90 90 90 62 62 62
-- 30 30 30 10 10 10 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 10 10 10 26 26 26
-- 58 58 58 90 90 90 18 18 18 2 2 6
-- 2 2 6 110 110 110 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 231 231 231 18 18 18 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 18 18 18 94 94 94
-- 54 54 54 26 26 26 10 10 10 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 22 22 22 50 50 50
-- 90 90 90 26 26 26 2 2 6 2 2 6
-- 14 14 14 195 195 195 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 242 242 242 54 54 54 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 38 38 38
-- 86 86 86 50 50 50 22 22 22 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 14 14 14 38 38 38 82 82 82
-- 34 34 34 2 2 6 2 2 6 2 2 6
-- 42 42 42 195 195 195 246 246 246 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--242 242 242 242 242 242 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 246 246 246 238 238 238
--226 226 226 231 231 231 101 101 101 6 6 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 38 38 38 82 82 82 42 42 42 14 14 14
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 10 10 10 26 26 26 62 62 62 66 66 66
-- 2 2 6 2 2 6 2 2 6 6 6 6
-- 70 70 70 170 170 170 206 206 206 234 234 234
--246 246 246 250 250 250 250 250 250 238 238 238
--226 226 226 231 231 231 238 238 238 250 250 250
--250 250 250 250 250 250 246 246 246 231 231 231
--214 214 214 206 206 206 202 202 202 202 202 202
--198 198 198 202 202 202 182 182 182 18 18 18
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 62 62 62 66 66 66 30 30 30
-- 10 10 10 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 14 14 14 42 42 42 82 82 82 18 18 18
-- 2 2 6 2 2 6 2 2 6 10 10 10
-- 94 94 94 182 182 182 218 218 218 242 242 242
--250 250 250 253 253 253 253 253 253 250 250 250
--234 234 234 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 246 246
--238 238 238 226 226 226 210 210 210 202 202 202
--195 195 195 195 195 195 210 210 210 158 158 158
-- 6 6 6 14 14 14 50 50 50 14 14 14
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 6 6 6 86 86 86 46 46 46
-- 18 18 18 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 22 22 22 54 54 54 70 70 70 2 2 6
-- 2 2 6 10 10 10 2 2 6 22 22 22
--166 166 166 231 231 231 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--242 242 242 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 246 246
--231 231 231 206 206 206 198 198 198 226 226 226
-- 94 94 94 2 2 6 6 6 6 38 38 38
-- 30 30 30 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 62 62 62 66 66 66
-- 26 26 26 10 10 10 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 30 30 30 74 74 74 50 50 50 2 2 6
-- 26 26 26 26 26 26 2 2 6 106 106 106
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 246 246 246 218 218 218 202 202 202
--210 210 210 14 14 14 2 2 6 2 2 6
-- 30 30 30 22 22 22 2 2 6 2 2 6
-- 2 2 6 2 2 6 18 18 18 86 86 86
-- 42 42 42 14 14 14 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 42 42 42 90 90 90 22 22 22 2 2 6
-- 42 42 42 2 2 6 18 18 18 218 218 218
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 250 250 250 221 221 221
--218 218 218 101 101 101 2 2 6 14 14 14
-- 18 18 18 38 38 38 10 10 10 2 2 6
-- 2 2 6 2 2 6 2 2 6 78 78 78
-- 58 58 58 22 22 22 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 18 18 18
-- 54 54 54 82 82 82 2 2 6 26 26 26
-- 22 22 22 2 2 6 123 123 123 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--238 238 238 198 198 198 6 6 6 38 38 38
-- 58 58 58 26 26 26 38 38 38 2 2 6
-- 2 2 6 2 2 6 2 2 6 46 46 46
-- 78 78 78 30 30 30 10 10 10 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 10 10 10 30 30 30
-- 74 74 74 58 58 58 2 2 6 42 42 42
-- 2 2 6 22 22 22 231 231 231 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 246 246 246 46 46 46 38 38 38
-- 42 42 42 14 14 14 38 38 38 14 14 14
-- 2 2 6 2 2 6 2 2 6 6 6 6
-- 86 86 86 46 46 46 14 14 14 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 14 14 14 42 42 42
-- 90 90 90 18 18 18 18 18 18 26 26 26
-- 2 2 6 116 116 116 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 250 250 250 238 238 238
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 94 94 94 6 6 6
-- 2 2 6 2 2 6 10 10 10 34 34 34
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 74 74 74 58 58 58 22 22 22 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 10 10 10 26 26 26 66 66 66
-- 82 82 82 2 2 6 38 38 38 6 6 6
-- 14 14 14 210 210 210 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 246 246 246 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 144 144 144 2 2 6
-- 2 2 6 2 2 6 2 2 6 46 46 46
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 42 42 42 74 74 74 30 30 30 10 10 10
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 14 14 14 42 42 42 90 90 90
-- 26 26 26 6 6 6 42 42 42 2 2 6
-- 74 74 74 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 242 242 242 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 182 182 182 2 2 6
-- 2 2 6 2 2 6 2 2 6 46 46 46
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 10 10 10 86 86 86 38 38 38 10 10 10
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 10 10 10 26 26 26 66 66 66 82 82 82
-- 2 2 6 22 22 22 18 18 18 2 2 6
--149 149 149 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 206 206 206 2 2 6
-- 2 2 6 2 2 6 2 2 6 38 38 38
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 6 6 6 86 86 86 46 46 46 14 14 14
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 18 18 18 46 46 46 86 86 86 18 18 18
-- 2 2 6 34 34 34 10 10 10 6 6 6
--210 210 210 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 221 221 221 6 6 6
-- 2 2 6 2 2 6 6 6 6 30 30 30
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 82 82 82 54 54 54 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 26 26 26 66 66 66 62 62 62 2 2 6
-- 2 2 6 38 38 38 10 10 10 26 26 26
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 238 238 238
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 6 6 6
-- 2 2 6 2 2 6 10 10 10 30 30 30
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 58 58 58 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 38 38 38 78 78 78 6 6 6 2 2 6
-- 2 2 6 46 46 46 14 14 14 42 42 42
--246 246 246 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 10 10 10
-- 2 2 6 2 2 6 22 22 22 14 14 14
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 62 62 62 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 18 18 18
-- 50 50 50 74 74 74 2 2 6 2 2 6
-- 14 14 14 70 70 70 34 34 34 62 62 62
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 14 14 14
-- 2 2 6 2 2 6 30 30 30 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 62 62 62 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 18 18 18
-- 54 54 54 62 62 62 2 2 6 2 2 6
-- 2 2 6 30 30 30 46 46 46 70 70 70
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 226 226 226 10 10 10
-- 2 2 6 6 6 6 30 30 30 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 58 58 58 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 22 22 22
-- 58 58 58 62 62 62 2 2 6 2 2 6
-- 2 2 6 2 2 6 30 30 30 78 78 78
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 206 206 206 2 2 6
-- 22 22 22 34 34 34 18 14 6 22 22 22
-- 26 26 26 18 18 18 6 6 6 2 2 6
-- 2 2 6 82 82 82 54 54 54 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 26 26 26
-- 62 62 62 106 106 106 74 54 14 185 133 11
--210 162 10 121 92 8 6 6 6 62 62 62
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 158 158 158 18 18 18
-- 14 14 14 2 2 6 2 2 6 2 2 6
-- 6 6 6 18 18 18 66 66 66 38 38 38
-- 6 6 6 94 94 94 50 50 50 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 10 10 10 10 10 10 18 18 18 38 38 38
-- 78 78 78 142 134 106 216 158 10 242 186 14
--246 190 14 246 190 14 156 118 10 10 10 10
-- 90 90 90 238 238 238 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 230 190
--238 204 91 238 204 91 181 142 44 37 26 9
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 38 38 38 46 46 46
-- 26 26 26 106 106 106 54 54 54 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 14 14 14 22 22 22
-- 30 30 30 38 38 38 50 50 50 70 70 70
--106 106 106 190 142 34 226 170 11 242 186 14
--246 190 14 246 190 14 246 190 14 154 114 10
-- 6 6 6 74 74 74 226 226 226 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 228 184 62
--241 196 14 241 208 19 232 195 16 38 30 10
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 6 6 6 30 30 30 26 26 26
--203 166 17 154 142 90 66 66 66 26 26 26
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 18 18 18 38 38 38 58 58 58
-- 78 78 78 86 86 86 101 101 101 123 123 123
--175 146 61 210 150 10 234 174 13 246 186 14
--246 190 14 246 190 14 246 190 14 238 190 10
--102 78 10 2 2 6 46 46 46 198 198 198
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 224 178 62
--242 186 14 241 196 14 210 166 10 22 18 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 6 6 6 121 92 8
--238 202 15 232 195 16 82 82 82 34 34 34
-- 10 10 10 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 14 14 14 38 38 38 70 70 70 154 122 46
--190 142 34 200 144 11 197 138 11 197 138 11
--213 154 11 226 170 11 242 186 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--225 175 15 46 32 6 2 2 6 22 22 22
--158 158 158 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 242 242 242 224 178 62
--239 182 13 236 186 11 213 154 11 46 32 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 61 42 6 225 175 15
--238 190 10 236 186 11 112 100 78 42 42 42
-- 14 14 14 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 22 22 22 54 54 54 154 122 46 213 154 11
--226 170 11 230 174 11 226 170 11 226 170 11
--236 178 12 242 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--241 196 14 184 144 12 10 10 10 2 2 6
-- 6 6 6 116 116 116 242 242 242 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 231 231 231 198 198 198 214 170 54
--236 178 12 236 178 12 210 150 10 137 92 6
-- 18 14 6 2 2 6 2 2 6 2 2 6
-- 6 6 6 70 47 6 200 144 11 236 178 12
--239 182 13 239 182 13 124 112 88 58 58 58
-- 22 22 22 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
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-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-+0 0 0 0 0 0 0 0 0
-diff -Nur linux-3.12.38/drivers/video/Makefile linux-rpi/drivers/video/Makefile
---- linux-3.12.38/drivers/video/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/video/Makefile 2015-03-10 17:26:51.346216687 +0100
-@@ -100,6 +100,7 @@
- obj-$(CONFIG_FB_VOODOO1) += sstfb.o
- obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o
- obj-$(CONFIG_FB_GOLDFISH) += goldfishfb.o
-+obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o
- obj-$(CONFIG_FB_68328) += 68328fb.o
- obj-$(CONFIG_FB_GBE) += gbefb.o
- obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o
-diff -Nur linux-3.12.38/drivers/w1/masters/w1-gpio.c linux-rpi/drivers/w1/masters/w1-gpio.c
---- linux-3.12.38/drivers/w1/masters/w1-gpio.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/w1/masters/w1-gpio.c 2015-03-10 17:26:51.410216687 +0100
-@@ -22,6 +22,15 @@
- #include "../w1.h"
- #include "../w1_int.h"
-
-+static int w1_gpio_pullup = -1;
-+static int w1_gpio_pullup_orig = -1;
-+module_param_named(pullup, w1_gpio_pullup, int, 0);
-+MODULE_PARM_DESC(pullup, "GPIO pin pullup number");
-+static int w1_gpio_pin = -1;
-+static int w1_gpio_pin_orig = -1;
-+module_param_named(gpiopin, w1_gpio_pin, int, 0);
-+MODULE_PARM_DESC(gpiopin, "GPIO pin number");
-+
- static void w1_gpio_write_bit_dir(void *data, u8 bit)
- {
- struct w1_gpio_platform_data *pdata = data;
-@@ -46,6 +55,16 @@
- return gpio_get_value(pdata->pin) ? 1 : 0;
- }
-
-+static void w1_gpio_bitbang_pullup(void *data, u8 on)
-+{
-+ struct w1_gpio_platform_data *pdata = data;
-+
-+ if (on)
-+ gpio_direction_output(pdata->pin, 1);
-+ else
-+ gpio_direction_input(pdata->pin);
-+}
-+
- #if defined(CONFIG_OF)
- static struct of_device_id w1_gpio_dt_ids[] = {
- { .compatible = "w1-gpio" },
-@@ -76,14 +95,16 @@
- static int w1_gpio_probe(struct platform_device *pdev)
- {
- struct w1_bus_master *master;
-- struct w1_gpio_platform_data *pdata;
-+ struct w1_gpio_platform_data *pdata = pdev->dev.platform_data;
- int err;
-
-- if (of_have_populated_dt()) {
-- err = w1_gpio_probe_dt(pdev);
-- if (err < 0) {
-- dev_err(&pdev->dev, "Failed to parse DT\n");
-- return err;
-+ if(pdata == NULL) {
-+ if (of_have_populated_dt()) {
-+ err = w1_gpio_probe_dt(pdev);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to parse DT\n");
-+ return err;
-+ }
- }
- }
-
-@@ -100,6 +121,19 @@
- return -ENOMEM;
- }
-
-+ w1_gpio_pin_orig = pdata->pin;
-+ w1_gpio_pullup_orig = pdata->ext_pullup_enable_pin;
-+
-+ if(gpio_is_valid(w1_gpio_pin)) {
-+ pdata->pin = w1_gpio_pin;
-+ pdata->ext_pullup_enable_pin = -1;
-+ }
-+ if(gpio_is_valid(w1_gpio_pullup)) {
-+ pdata->ext_pullup_enable_pin = w1_gpio_pullup;
-+ }
-+
-+ dev_info(&pdev->dev, "gpio pin %d, gpio pullup pin %d\n", pdata->pin, pdata->ext_pullup_enable_pin);
-+
- err = gpio_request(pdata->pin, "w1");
- if (err) {
- dev_err(&pdev->dev, "gpio_request (pin) failed\n");
-@@ -127,6 +161,14 @@
- master->write_bit = w1_gpio_write_bit_dir;
- }
-
-+ if (gpio_is_valid(w1_gpio_pullup)) {
-+ if (pdata->is_open_drain)
-+ printk(KERN_ERR "w1-gpio 'pullup' option "
-+ "doesn't work with open drain GPIO\n");
-+ else
-+ master->bitbang_pullup = w1_gpio_bitbang_pullup;
-+ }
-+
- err = w1_add_master_device(master);
- if (err) {
- dev_err(&pdev->dev, "w1_add_master device failed\n");
-@@ -167,8 +209,14 @@
-
- w1_remove_master_device(master);
- gpio_free(pdata->pin);
-+ if (gpio_is_valid(pdata->ext_pullup_enable_pin))
-+ gpio_free(pdata->ext_pullup_enable_pin);
-+
- kfree(master);
-
-+ pdata->pin = w1_gpio_pin_orig;
-+ pdata->ext_pullup_enable_pin = w1_gpio_pullup_orig;
-+
- return 0;
- }
-
-diff -Nur linux-3.12.38/drivers/w1/w1.h linux-rpi/drivers/w1/w1.h
---- linux-3.12.38/drivers/w1/w1.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/w1/w1.h 2015-03-10 17:26:51.410216687 +0100
-@@ -148,6 +148,12 @@
- */
- u8 (*set_pullup)(void *, int);
-
-+ /**
-+ * Turns the pullup on/off in bitbanging mode, takes an on/off argument.
-+ * @return -1=Error, 0=completed
-+ */
-+ void (*bitbang_pullup) (void *, u8);
-+
- /** Really nice hardware can handles the different types of ROM search
- * w1_master* is passed to the slave found callback.
- */
-diff -Nur linux-3.12.38/drivers/w1/w1_int.c linux-rpi/drivers/w1/w1_int.c
---- linux-3.12.38/drivers/w1/w1_int.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/w1/w1_int.c 2015-03-10 17:26:51.410216687 +0100
-@@ -130,6 +130,20 @@
- master->set_pullup = NULL;
- }
-
-+ /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup
-+ * and takes care of timing itself */
-+ if (!master->write_byte && !master->touch_bit && master->set_pullup) {
-+ printk(KERN_ERR "w1_add_master_device: set_pullup requires "
-+ "write_byte or touch_bit, disabling\n");
-+ master->set_pullup = NULL;
-+ }
-+
-+ if (master->set_pullup && master->bitbang_pullup) {
-+ printk(KERN_ERR "w1_add_master_device: set_pullup should not "
-+ "be set when bitbang_pullup is used, disabling\n");
-+ master->set_pullup = NULL;
-+ }
-+
- /* Lock until the device is added (or not) to w1_masters. */
- mutex_lock(&w1_mlock);
- /* Search for the first available id (starting at 1). */
-diff -Nur linux-3.12.38/drivers/w1/w1_io.c linux-rpi/drivers/w1/w1_io.c
---- linux-3.12.38/drivers/w1/w1_io.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/w1/w1_io.c 2015-03-10 17:26:51.410216687 +0100
-@@ -127,10 +127,22 @@
- static void w1_post_write(struct w1_master *dev)
- {
- if (dev->pullup_duration) {
-- if (dev->enable_pullup && dev->bus_master->set_pullup)
-- dev->bus_master->set_pullup(dev->bus_master->data, 0);
-- else
-+ if (dev->enable_pullup) {
-+ if (dev->bus_master->set_pullup) {
-+ dev->bus_master->set_pullup(dev->
-+ bus_master->data,
-+ 0);
-+ } else if (dev->bus_master->bitbang_pullup) {
-+ dev->bus_master->
-+ bitbang_pullup(dev->bus_master->data, 1);
- msleep(dev->pullup_duration);
-+ dev->bus_master->
-+ bitbang_pullup(dev->bus_master->data, 0);
-+ }
-+ } else {
-+ msleep(dev->pullup_duration);
-+ }
-+
- dev->pullup_duration = 0;
- }
- }
-diff -Nur linux-3.12.38/drivers/watchdog/bcm2708_wdog.c linux-rpi/drivers/watchdog/bcm2708_wdog.c
---- linux-3.12.38/drivers/watchdog/bcm2708_wdog.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/drivers/watchdog/bcm2708_wdog.c 2015-03-10 17:26:51.410216687 +0100
-@@ -0,0 +1,384 @@
-+/*
-+ * Broadcom BCM2708 watchdog driver.
-+ *
-+ * (c) Copyright 2010 Broadcom Europe Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ *
-+ * BCM2708 watchdog driver. Loosely based on wdt driver.
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/miscdevice.h>
-+#include <linux/watchdog.h>
-+#include <linux/fs.h>
-+#include <linux/ioport.h>
-+#include <linux/notifier.h>
-+#include <linux/reboot.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <mach/platform.h>
-+
-+#include <asm/system.h>
-+
-+#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
-+#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
-+
-+static unsigned long wdog_is_open;
-+static uint32_t wdog_ticks; /* Ticks to load into wdog timer */
-+static char expect_close;
-+
-+/*
-+ * Module parameters
-+ */
-+
-+#define WD_TIMO 10 /* Default heartbeat = 60 seconds */
-+static int heartbeat = WD_TIMO; /* Heartbeat in seconds */
-+
-+module_param(heartbeat, int, 0);
-+MODULE_PARM_DESC(heartbeat,
-+ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default="
-+ __MODULE_STRING(WD_TIMO) ")");
-+
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout,
-+ "Watchdog cannot be stopped once started (default="
-+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-+
-+static DEFINE_SPINLOCK(wdog_lock);
-+
-+/**
-+ * Start the watchdog driver.
-+ */
-+
-+static int wdog_start(unsigned long timeout)
-+{
-+ uint32_t cur;
-+ unsigned long flags;
-+ spin_lock_irqsave(&wdog_lock, flags);
-+
-+ /* enable the watchdog */
-+ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET),
-+ __io_address(PM_WDOG));
-+ cur = ioread32(__io_address(PM_RSTC));
-+ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
-+ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC));
-+
-+ spin_unlock_irqrestore(&wdog_lock, flags);
-+ return 0;
-+}
-+
-+/**
-+ * Stop the watchdog driver.
-+ */
-+
-+static int wdog_stop(void)
-+{
-+ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC));
-+ printk(KERN_INFO "watchdog stopped\n");
-+ return 0;
-+}
-+
-+/**
-+ * Reload counter one with the watchdog heartbeat. We don't bother
-+ * reloading the cascade counter.
-+ */
-+
-+static void wdog_ping(void)
-+{
-+ wdog_start(wdog_ticks);
-+}
-+
-+/**
-+ * @t: the new heartbeat value that needs to be set.
-+ *
-+ * Set a new heartbeat value for the watchdog device. If the heartbeat
-+ * value is incorrect we keep the old value and return -EINVAL. If
-+ * successful we return 0.
-+ */
-+
-+static int wdog_set_heartbeat(int t)
-+{
-+ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET))
-+ return -EINVAL;
-+
-+ heartbeat = t;
-+ wdog_ticks = SECS_TO_WDOG_TICKS(t);
-+ return 0;
-+}
-+
-+/**
-+ * @file: file handle to the watchdog
-+ * @buf: buffer to write (unused as data does not matter here
-+ * @count: count of bytes
-+ * @ppos: pointer to the position to write. No seeks allowed
-+ *
-+ * A write to a watchdog device is defined as a keepalive signal.
-+ *
-+ * if 'nowayout' is set then normally a close() is ignored. But
-+ * if you write 'V' first then the close() will stop the timer.
-+ */
-+
-+static ssize_t wdog_write(struct file *file, const char __user *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ if (count) {
-+ if (!nowayout) {
-+ size_t i;
-+
-+ /* In case it was set long ago */
-+ expect_close = 0;
-+
-+ for (i = 0; i != count; i++) {
-+ char c;
-+ if (get_user(c, buf + i))
-+ return -EFAULT;
-+ if (c == 'V')
-+ expect_close = 42;
-+ }
-+ }
-+ wdog_ping();
-+ }
-+ return count;
-+}
-+
-+static int wdog_get_status(void)
-+{
-+ unsigned long flags;
-+ int status = 0;
-+ spin_lock_irqsave(&wdog_lock, flags);
-+ /* FIXME: readback reset reason */
-+ spin_unlock_irqrestore(&wdog_lock, flags);
-+ return status;
-+}
-+
-+static uint32_t wdog_get_remaining(void)
-+{
-+ uint32_t ret = ioread32(__io_address(PM_WDOG));
-+ return ret & PM_WDOG_TIME_SET;
-+}
-+
-+/**
-+ * @file: file handle to the device
-+ * @cmd: watchdog command
-+ * @arg: argument pointer
-+ *
-+ * The watchdog API defines a common set of functions for all watchdogs
-+ * according to their available features. We only actually usefully support
-+ * querying capabilities and current status.
-+ */
-+
-+static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ void __user *argp = (void __user *)arg;
-+ int __user *p = argp;
-+ int new_heartbeat;
-+ int status;
-+ int options;
-+ uint32_t remaining;
-+
-+ struct watchdog_info ident = {
-+ .options = WDIOF_SETTIMEOUT|
-+ WDIOF_MAGICCLOSE|
-+ WDIOF_KEEPALIVEPING,
-+ .firmware_version = 1,
-+ .identity = "BCM2708",
-+ };
-+
-+ switch (cmd) {
-+ case WDIOC_GETSUPPORT:
-+ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
-+ case WDIOC_GETSTATUS:
-+ status = wdog_get_status();
-+ return put_user(status, p);
-+ case WDIOC_GETBOOTSTATUS:
-+ return put_user(0, p);
-+ case WDIOC_KEEPALIVE:
-+ wdog_ping();
-+ return 0;
-+ case WDIOC_SETTIMEOUT:
-+ if (get_user(new_heartbeat, p))
-+ return -EFAULT;
-+ if (wdog_set_heartbeat(new_heartbeat))
-+ return -EINVAL;
-+ wdog_ping();
-+ /* Fall */
-+ case WDIOC_GETTIMEOUT:
-+ return put_user(heartbeat, p);
-+ case WDIOC_GETTIMELEFT:
-+ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining());
-+ return put_user(remaining, p);
-+ case WDIOC_SETOPTIONS:
-+ if (get_user(options, p))
-+ return -EFAULT;
-+ if (options & WDIOS_DISABLECARD)
-+ wdog_stop();
-+ if (options & WDIOS_ENABLECARD)
-+ wdog_start(wdog_ticks);
-+ return 0;
-+ default:
-+ return -ENOTTY;
-+ }
-+}
-+
-+/**
-+ * @inode: inode of device
-+ * @file: file handle to device
-+ *
-+ * The watchdog device has been opened. The watchdog device is single
-+ * open and on opening we load the counters.
-+ */
-+
-+static int wdog_open(struct inode *inode, struct file *file)
-+{
-+ if (test_and_set_bit(0, &wdog_is_open))
-+ return -EBUSY;
-+ /*
-+ * Activate
-+ */
-+ wdog_start(wdog_ticks);
-+ return nonseekable_open(inode, file);
-+}
-+
-+/**
-+ * @inode: inode to board
-+ * @file: file handle to board
-+ *
-+ * The watchdog has a configurable API. There is a religious dispute
-+ * between people who want their watchdog to be able to shut down and
-+ * those who want to be sure if the watchdog manager dies the machine
-+ * reboots. In the former case we disable the counters, in the latter
-+ * case you have to open it again very soon.
-+ */
-+
-+static int wdog_release(struct inode *inode, struct file *file)
-+{
-+ if (expect_close == 42) {
-+ wdog_stop();
-+ } else {
-+ printk(KERN_CRIT
-+ "wdt: WDT device closed unexpectedly. WDT will not stop!\n");
-+ wdog_ping();
-+ }
-+ clear_bit(0, &wdog_is_open);
-+ expect_close = 0;
-+ return 0;
-+}
-+
-+/**
-+ * @this: our notifier block
-+ * @code: the event being reported
-+ * @unused: unused
-+ *
-+ * Our notifier is called on system shutdowns. Turn the watchdog
-+ * off so that it does not fire during the next reboot.
-+ */
-+
-+static int wdog_notify_sys(struct notifier_block *this, unsigned long code,
-+ void *unused)
-+{
-+ if (code == SYS_DOWN || code == SYS_HALT)
-+ wdog_stop();
-+ return NOTIFY_DONE;
-+}
-+
-+/*
-+ * Kernel Interfaces
-+ */
-+
-+
-+static const struct file_operations wdog_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .write = wdog_write,
-+ .unlocked_ioctl = wdog_ioctl,
-+ .open = wdog_open,
-+ .release = wdog_release,
-+};
-+
-+static struct miscdevice wdog_miscdev = {
-+ .minor = WATCHDOG_MINOR,
-+ .name = "watchdog",
-+ .fops = &wdog_fops,
-+};
-+
-+/*
-+ * The WDT card needs to learn about soft shutdowns in order to
-+ * turn the timebomb registers off.
-+ */
-+
-+static struct notifier_block wdog_notifier = {
-+ .notifier_call = wdog_notify_sys,
-+};
-+
-+/**
-+ * cleanup_module:
-+ *
-+ * Unload the watchdog. You cannot do this with any file handles open.
-+ * If your watchdog is set to continue ticking on close and you unload
-+ * it, well it keeps ticking. We won't get the interrupt but the board
-+ * will not touch PC memory so all is fine. You just have to load a new
-+ * module in 60 seconds or reboot.
-+ */
-+
-+static void __exit wdog_exit(void)
-+{
-+ misc_deregister(&wdog_miscdev);
-+ unregister_reboot_notifier(&wdog_notifier);
-+}
-+
-+static int __init wdog_init(void)
-+{
-+ int ret;
-+
-+ /* Check that the heartbeat value is within it's range;
-+ if not reset to the default */
-+ if (wdog_set_heartbeat(heartbeat)) {
-+ wdog_set_heartbeat(WD_TIMO);
-+ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be "
-+ "0 < heartbeat < %d, using %d\n",
-+ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
-+ WD_TIMO);
-+ }
-+
-+ ret = register_reboot_notifier(&wdog_notifier);
-+ if (ret) {
-+ printk(KERN_ERR
-+ "wdt: cannot register reboot notifier (err=%d)\n", ret);
-+ goto out_reboot;
-+ }
-+
-+ ret = misc_register(&wdog_miscdev);
-+ if (ret) {
-+ printk(KERN_ERR
-+ "wdt: cannot register miscdev on minor=%d (err=%d)\n",
-+ WATCHDOG_MINOR, ret);
-+ goto out_misc;
-+ }
-+
-+ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n",
-+ heartbeat, nowayout);
-+ return 0;
-+
-+out_misc:
-+ unregister_reboot_notifier(&wdog_notifier);
-+out_reboot:
-+ return ret;
-+}
-+
-+module_init(wdog_init);
-+module_exit(wdog_exit);
-+
-+MODULE_AUTHOR("Luke Diamand");
-+MODULE_DESCRIPTION("Driver for BCM2708 watchdog");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS_MISCDEV(TEMP_MINOR);
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.12.38/drivers/watchdog/Kconfig linux-rpi/drivers/watchdog/Kconfig
---- linux-3.12.38/drivers/watchdog/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/watchdog/Kconfig 2015-03-10 17:26:51.410216687 +0100
-@@ -392,6 +392,12 @@
- To compile this driver as a module, choose M here: the
- module will be called retu_wdt.
-
-+config BCM2708_WDT
-+ tristate "BCM2708 Watchdog"
-+ depends on ARCH_BCM2708
-+ help
-+ Enables BCM2708 watchdog support.
-+
- # AVR32 Architecture
-
- config AT32AP700X_WDT
-diff -Nur linux-3.12.38/drivers/watchdog/Makefile linux-rpi/drivers/watchdog/Makefile
---- linux-3.12.38/drivers/watchdog/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/drivers/watchdog/Makefile 2015-03-10 17:26:51.410216687 +0100
-@@ -54,6 +54,7 @@
- obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
- obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
- obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
-+obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o
- obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
-
- # AVR32 Architecture
-diff -Nur linux-3.12.38/fs/affs/amigaffs.c linux-rpi/fs/affs/amigaffs.c
---- linux-3.12.38/fs/affs/amigaffs.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/affs/amigaffs.c 2015-03-10 17:26:51.426216687 +0100
-@@ -126,7 +126,7 @@
- {
- struct dentry *dentry;
- spin_lock(&inode->i_lock);
-- hlist_for_each_entry(dentry, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(dentry, &inode->i_dentry, d_alias) {
- if (entry_ino == (u32)(long)dentry->d_fsdata) {
- dentry->d_fsdata = (void *)inode->i_ino;
- break;
-diff -Nur linux-3.12.38/fs/autofs4/expire.c linux-rpi/fs/autofs4/expire.c
---- linux-3.12.38/fs/autofs4/expire.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/autofs4/expire.c 2015-03-10 17:26:51.426216687 +0100
-@@ -91,7 +91,7 @@
- spin_lock(&root->d_lock);
-
- if (prev)
-- next = prev->d_child.next;
-+ next = prev->d_u.d_child.next;
- else {
- prev = dget_dlock(root);
- next = prev->d_subdirs.next;
-@@ -105,13 +105,13 @@
- return NULL;
- }
-
-- q = list_entry(next, struct dentry, d_child);
-+ q = list_entry(next, struct dentry, d_u.d_child);
-
- spin_lock_nested(&q->d_lock, DENTRY_D_LOCK_NESTED);
- /* Already gone or negative dentry (under construction) - try next */
- if (!d_count(q) || !simple_positive(q)) {
- spin_unlock(&q->d_lock);
-- next = q->d_child.next;
-+ next = q->d_u.d_child.next;
- goto cont;
- }
- dget_dlock(q);
-@@ -161,13 +161,13 @@
- goto relock;
- }
- spin_unlock(&p->d_lock);
-- next = p->d_child.next;
-+ next = p->d_u.d_child.next;
- p = parent;
- if (next != &parent->d_subdirs)
- break;
- }
- }
-- ret = list_entry(next, struct dentry, d_child);
-+ ret = list_entry(next, struct dentry, d_u.d_child);
-
- spin_lock_nested(&ret->d_lock, DENTRY_D_LOCK_NESTED);
- /* Negative dentry - try next */
-@@ -447,7 +447,7 @@
- spin_lock(&sbi->lookup_lock);
- spin_lock(&expired->d_parent->d_lock);
- spin_lock_nested(&expired->d_lock, DENTRY_D_LOCK_NESTED);
-- list_move(&expired->d_parent->d_subdirs, &expired->d_child);
-+ list_move(&expired->d_parent->d_subdirs, &expired->d_u.d_child);
- spin_unlock(&expired->d_lock);
- spin_unlock(&expired->d_parent->d_lock);
- spin_unlock(&sbi->lookup_lock);
-diff -Nur linux-3.12.38/fs/autofs4/root.c linux-rpi/fs/autofs4/root.c
---- linux-3.12.38/fs/autofs4/root.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/autofs4/root.c 2015-03-10 17:26:51.426216687 +0100
-@@ -655,7 +655,7 @@
- /* only consider parents below dentrys in the root */
- if (IS_ROOT(parent->d_parent))
- return;
-- d_child = &dentry->d_child;
-+ d_child = &dentry->d_u.d_child;
- /* Set parent managed if it's becoming empty */
- if (d_child->next == &parent->d_subdirs &&
- d_child->prev == &parent->d_subdirs)
-diff -Nur linux-3.12.38/fs/ceph/addr.c linux-rpi/fs/ceph/addr.c
---- linux-3.12.38/fs/ceph/addr.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ceph/addr.c 2015-03-10 17:26:51.446216687 +0100
-@@ -672,7 +672,7 @@
- int rc = 0;
- unsigned wsize = 1 << inode->i_blkbits;
- struct ceph_osd_request *req = NULL;
-- int do_sync = 0;
-+ int do_sync;
- u64 truncate_size, snap_size;
- u32 truncate_seq;
-
-diff -Nur linux-3.12.38/fs/ceph/dir.c linux-rpi/fs/ceph/dir.c
---- linux-3.12.38/fs/ceph/dir.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ceph/dir.c 2015-03-10 17:26:51.446216687 +0100
-@@ -103,7 +103,7 @@
- /*
- * When possible, we try to satisfy a readdir by peeking at the
- * dcache. We make this work by carefully ordering dentries on
-- * d_child when we initially get results back from the MDS, and
-+ * d_u.d_child when we initially get results back from the MDS, and
- * falling back to a "normal" sync readdir if any dentries in the dir
- * are dropped.
- *
-@@ -138,11 +138,11 @@
- p = parent->d_subdirs.prev;
- dout(" initial p %p/%p\n", p->prev, p->next);
- } else {
-- p = last->d_child.prev;
-+ p = last->d_u.d_child.prev;
- }
-
- more:
-- dentry = list_entry(p, struct dentry, d_child);
-+ dentry = list_entry(p, struct dentry, d_u.d_child);
- di = ceph_dentry(dentry);
- while (1) {
- dout(" p %p/%p %s d_subdirs %p/%p\n", p->prev, p->next,
-@@ -164,7 +164,7 @@
- !dentry->d_inode ? " null" : "");
- spin_unlock(&dentry->d_lock);
- p = p->prev;
-- dentry = list_entry(p, struct dentry, d_child);
-+ dentry = list_entry(p, struct dentry, d_u.d_child);
- di = ceph_dentry(dentry);
- }
-
-diff -Nur linux-3.12.38/fs/ceph/inode.c linux-rpi/fs/ceph/inode.c
---- linux-3.12.38/fs/ceph/inode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ceph/inode.c 2015-03-10 17:26:51.446216687 +0100
-@@ -880,9 +880,9 @@
-
- spin_lock(&dir->d_lock);
- spin_lock_nested(&dn->d_lock, DENTRY_D_LOCK_NESTED);
-- list_move(&dn->d_child, &dir->d_subdirs);
-+ list_move(&dn->d_u.d_child, &dir->d_subdirs);
- dout("set_dentry_offset %p %lld (%p %p)\n", dn, di->offset,
-- dn->d_child.prev, dn->d_child.next);
-+ dn->d_u.d_child.prev, dn->d_u.d_child.next);
- spin_unlock(&dn->d_lock);
- spin_unlock(&dir->d_lock);
- }
-@@ -1309,7 +1309,7 @@
- /* reorder parent's d_subdirs */
- spin_lock(&parent->d_lock);
- spin_lock_nested(&dn->d_lock, DENTRY_D_LOCK_NESTED);
-- list_move(&dn->d_child, &parent->d_subdirs);
-+ list_move(&dn->d_u.d_child, &parent->d_subdirs);
- spin_unlock(&dn->d_lock);
- spin_unlock(&parent->d_lock);
- }
-diff -Nur linux-3.12.38/fs/cifs/file.c linux-rpi/fs/cifs/file.c
---- linux-3.12.38/fs/cifs/file.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/cifs/file.c 2015-03-10 17:26:51.450216686 +0100
-@@ -366,7 +366,6 @@
- struct cifsLockInfo *li, *tmp;
- struct cifs_fid fid;
- struct cifs_pending_open open;
-- bool oplock_break_cancelled;
-
- spin_lock(&cifs_file_list_lock);
- if (--cifs_file->count > 0) {
-@@ -398,7 +397,7 @@
- }
- spin_unlock(&cifs_file_list_lock);
-
-- oplock_break_cancelled = cancel_work_sync(&cifs_file->oplock_break);
-+ cancel_work_sync(&cifs_file->oplock_break);
-
- if (!tcon->need_reconnect && !cifs_file->invalidHandle) {
- struct TCP_Server_Info *server = tcon->ses->server;
-@@ -410,9 +409,6 @@
- _free_xid(xid);
- }
-
-- if (oplock_break_cancelled)
-- cifs_done_oplock_break(cifsi);
--
- cifs_del_pending_open(&open);
-
- /*
-diff -Nur linux-3.12.38/fs/cifs/inode.c linux-rpi/fs/cifs/inode.c
---- linux-3.12.38/fs/cifs/inode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/cifs/inode.c 2015-03-10 17:26:51.450216686 +0100
-@@ -874,7 +874,7 @@
- struct dentry *dentry;
-
- spin_lock(&inode->i_lock);
-- hlist_for_each_entry(dentry, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(dentry, &inode->i_dentry, d_alias) {
- if (!d_unhashed(dentry) || IS_ROOT(dentry)) {
- spin_unlock(&inode->i_lock);
- return true;
-diff -Nur linux-3.12.38/fs/coda/cache.c linux-rpi/fs/coda/cache.c
---- linux-3.12.38/fs/coda/cache.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/coda/cache.c 2015-03-10 17:26:51.454216686 +0100
-@@ -92,7 +92,7 @@
- struct dentry *de;
-
- spin_lock(&parent->d_lock);
-- list_for_each_entry(de, &parent->d_subdirs, d_child) {
-+ list_for_each_entry(de, &parent->d_subdirs, d_u.d_child) {
- /* don't know what to do with negative dentries */
- if (de->d_inode )
- coda_flag_inode(de->d_inode, flag);
-diff -Nur linux-3.12.38/fs/dcache.c linux-rpi/fs/dcache.c
---- linux-3.12.38/fs/dcache.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/dcache.c 2015-03-10 17:26:51.458216686 +0100
-@@ -44,7 +44,7 @@
- /*
- * Usage:
- * dcache->d_inode->i_lock protects:
-- * - i_dentry, d_u.d_alias, d_inode of aliases
-+ * - i_dentry, d_alias, d_inode of aliases
- * dcache_hash_bucket lock protects:
- * - the dcache hash table
- * s_anon bl list spinlock protects:
-@@ -59,7 +59,7 @@
- * - d_unhashed()
- * - d_parent and d_subdirs
- * - childrens' d_child and d_parent
-- * - d_u.d_alias, d_inode
-+ * - d_alias, d_inode
- *
- * Ordering:
- * dentry->d_inode->i_lock
-@@ -268,6 +268,7 @@
- {
- struct dentry *dentry = container_of(head, struct dentry, d_u.d_rcu);
-
-+ WARN_ON(!hlist_unhashed(&dentry->d_alias));
- if (dname_external(dentry))
- kfree(dentry->d_name.name);
- kmem_cache_free(dentry_cache, dentry);
-@@ -275,7 +276,6 @@
-
- static void dentry_free(struct dentry *dentry)
- {
-- WARN_ON(!hlist_unhashed(&dentry->d_u.d_alias));
- /* if dentry was never visible to RCU, immediate free is OK */
- if (!(dentry->d_flags & DCACHE_RCUACCESS))
- __d_free(&dentry->d_u.d_rcu);
-@@ -309,7 +309,7 @@
- struct inode *inode = dentry->d_inode;
- if (inode) {
- dentry->d_inode = NULL;
-- hlist_del_init(&dentry->d_u.d_alias);
-+ hlist_del_init(&dentry->d_alias);
- spin_unlock(&dentry->d_lock);
- spin_unlock(&inode->i_lock);
- if (!inode->i_nlink)
-@@ -333,7 +333,7 @@
- {
- struct inode *inode = dentry->d_inode;
- dentry->d_inode = NULL;
-- hlist_del_init(&dentry->d_u.d_alias);
-+ hlist_del_init(&dentry->d_alias);
- dentry_rcuwalk_barrier(dentry);
- spin_unlock(&dentry->d_lock);
- spin_unlock(&inode->i_lock);
-@@ -488,7 +488,7 @@
- }
- /* if it was on the hash then remove it */
- __d_drop(dentry);
-- __list_del_entry(&dentry->d_child);
-+ list_del(&dentry->d_u.d_child);
- /*
- * Inform d_walk() that we are no longer attached to the
- * dentry tree
-@@ -772,7 +772,7 @@
-
- again:
- discon_alias = NULL;
-- hlist_for_each_entry(alias, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(alias, &inode->i_dentry, d_alias) {
- spin_lock(&alias->d_lock);
- if (S_ISDIR(inode->i_mode) || !d_unhashed(alias)) {
- if (IS_ROOT(alias) &&
-@@ -825,7 +825,7 @@
- struct dentry *dentry;
- restart:
- spin_lock(&inode->i_lock);
-- hlist_for_each_entry(dentry, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(dentry, &inode->i_dentry, d_alias) {
- spin_lock(&dentry->d_lock);
- if (!dentry->d_lockref.count) {
- /*
-@@ -1110,7 +1110,7 @@
- resume:
- while (next != &this_parent->d_subdirs) {
- struct list_head *tmp = next;
-- struct dentry *dentry = list_entry(tmp, struct dentry, d_child);
-+ struct dentry *dentry = list_entry(tmp, struct dentry, d_u.d_child);
- next = tmp->next;
-
- spin_lock_nested(&dentry->d_lock, DENTRY_D_LOCK_NESTED);
-@@ -1142,31 +1142,33 @@
- /*
- * All done at this level ... ascend and resume the search.
- */
-- rcu_read_lock();
--ascend:
- if (this_parent != parent) {
- struct dentry *child = this_parent;
- this_parent = child->d_parent;
-
-+ rcu_read_lock();
- spin_unlock(&child->d_lock);
- spin_lock(&this_parent->d_lock);
-
-- /* might go back up the wrong parent if we have had a rename. */
-- if (need_seqretry(&rename_lock, seq))
-+ /*
-+ * might go back up the wrong parent if we have had a rename
-+ * or deletion
-+ */
-+ if (this_parent != child->d_parent ||
-+ (child->d_flags & DCACHE_DENTRY_KILLED) ||
-+ need_seqretry(&rename_lock, seq)) {
-+ spin_unlock(&this_parent->d_lock);
-+ rcu_read_unlock();
- goto rename_retry;
-- next = child->d_child.next;
-- while (unlikely(child->d_flags & DCACHE_DENTRY_KILLED)) {
-- if (next == &this_parent->d_subdirs)
-- goto ascend;
-- child = list_entry(next, struct dentry, d_child);
-- next = next->next;
- }
- rcu_read_unlock();
-+ next = child->d_u.d_child.next;
- goto resume;
- }
-- if (need_seqretry(&rename_lock, seq))
-+ if (need_seqretry(&rename_lock, seq)) {
-+ spin_unlock(&this_parent->d_lock);
- goto rename_retry;
-- rcu_read_unlock();
-+ }
- if (finish)
- finish(data);
-
-@@ -1176,9 +1178,6 @@
- return;
-
- rename_retry:
-- spin_unlock(&this_parent->d_lock);
-- rcu_read_unlock();
-- BUG_ON(seq & 1);
- if (!retry)
- return;
- seq = 1;
-@@ -1498,8 +1497,8 @@
- INIT_HLIST_BL_NODE(&dentry->d_hash);
- INIT_LIST_HEAD(&dentry->d_lru);
- INIT_LIST_HEAD(&dentry->d_subdirs);
-- INIT_HLIST_NODE(&dentry->d_u.d_alias);
-- INIT_LIST_HEAD(&dentry->d_child);
-+ INIT_HLIST_NODE(&dentry->d_alias);
-+ INIT_LIST_HEAD(&dentry->d_u.d_child);
- d_set_d_op(dentry, dentry->d_sb->s_d_op);
-
- this_cpu_inc(nr_dentry);
-@@ -1529,7 +1528,7 @@
- */
- __dget_dlock(parent);
- dentry->d_parent = parent;
-- list_add(&dentry->d_child, &parent->d_subdirs);
-+ list_add(&dentry->d_u.d_child, &parent->d_subdirs);
- spin_unlock(&parent->d_lock);
-
- return dentry;
-@@ -1589,7 +1588,7 @@
- if (inode) {
- if (unlikely(IS_AUTOMOUNT(inode)))
- dentry->d_flags |= DCACHE_NEED_AUTOMOUNT;
-- hlist_add_head(&dentry->d_u.d_alias, &inode->i_dentry);
-+ hlist_add_head(&dentry->d_alias, &inode->i_dentry);
- }
- dentry->d_inode = inode;
- dentry_rcuwalk_barrier(dentry);
-@@ -1614,7 +1613,7 @@
-
- void d_instantiate(struct dentry *entry, struct inode * inode)
- {
-- BUG_ON(!hlist_unhashed(&entry->d_u.d_alias));
-+ BUG_ON(!hlist_unhashed(&entry->d_alias));
- if (inode)
- spin_lock(&inode->i_lock);
- __d_instantiate(entry, inode);
-@@ -1653,7 +1652,7 @@
- return NULL;
- }
-
-- hlist_for_each_entry(alias, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(alias, &inode->i_dentry, d_alias) {
- /*
- * Don't need alias->d_lock here, because aliases with
- * d_parent == entry->d_parent are not subject to name or
-@@ -1679,7 +1678,7 @@
- {
- struct dentry *result;
-
-- BUG_ON(!hlist_unhashed(&entry->d_u.d_alias));
-+ BUG_ON(!hlist_unhashed(&entry->d_alias));
-
- if (inode)
- spin_lock(&inode->i_lock);
-@@ -1722,7 +1721,7 @@
-
- if (hlist_empty(&inode->i_dentry))
- return NULL;
-- alias = hlist_entry(inode->i_dentry.first, struct dentry, d_u.d_alias);
-+ alias = hlist_entry(inode->i_dentry.first, struct dentry, d_alias);
- __dget(alias);
- return alias;
- }
-@@ -1796,7 +1795,7 @@
- spin_lock(&tmp->d_lock);
- tmp->d_inode = inode;
- tmp->d_flags |= DCACHE_DISCONNECTED;
-- hlist_add_head(&tmp->d_u.d_alias, &inode->i_dentry);
-+ hlist_add_head(&tmp->d_alias, &inode->i_dentry);
- hlist_bl_lock(&tmp->d_sb->s_anon);
- hlist_bl_add_head(&tmp->d_hash, &tmp->d_sb->s_anon);
- hlist_bl_unlock(&tmp->d_sb->s_anon);
-@@ -2239,7 +2238,7 @@
- struct dentry *child;
-
- spin_lock(&dparent->d_lock);
-- list_for_each_entry(child, &dparent->d_subdirs, d_child) {
-+ list_for_each_entry(child, &dparent->d_subdirs, d_u.d_child) {
- if (dentry == child) {
- spin_lock_nested(&dentry->d_lock, DENTRY_D_LOCK_NESTED);
- __dget_dlock(dentry);
-@@ -2486,8 +2485,8 @@
- /* Unhash the target: dput() will then get rid of it */
- __d_drop(target);
-
-- list_del(&dentry->d_child);
-- list_del(&target->d_child);
-+ list_del(&dentry->d_u.d_child);
-+ list_del(&target->d_u.d_child);
-
- /* Switch the names.. */
- switch_names(dentry, target);
-@@ -2497,15 +2496,15 @@
- if (IS_ROOT(dentry)) {
- dentry->d_parent = target->d_parent;
- target->d_parent = target;
-- INIT_LIST_HEAD(&target->d_child);
-+ INIT_LIST_HEAD(&target->d_u.d_child);
- } else {
- swap(dentry->d_parent, target->d_parent);
-
- /* And add them back to the (new) parent lists */
-- list_add(&target->d_child, &target->d_parent->d_subdirs);
-+ list_add(&target->d_u.d_child, &target->d_parent->d_subdirs);
- }
-
-- list_add(&dentry->d_child, &dentry->d_parent->d_subdirs);
-+ list_add(&dentry->d_u.d_child, &dentry->d_parent->d_subdirs);
-
- write_seqcount_end(&target->d_seq);
- write_seqcount_end(&dentry->d_seq);
-@@ -2612,9 +2611,9 @@
- swap(dentry->d_name.hash, anon->d_name.hash);
-
- dentry->d_parent = dentry;
-- list_del_init(&dentry->d_child);
-+ list_del_init(&dentry->d_u.d_child);
- anon->d_parent = dparent;
-- list_move(&anon->d_child, &dparent->d_subdirs);
-+ list_move(&anon->d_u.d_child, &dparent->d_subdirs);
-
- write_seqcount_end(&dentry->d_seq);
- write_seqcount_end(&anon->d_seq);
-@@ -3242,7 +3241,7 @@
- {
- inode_dec_link_count(inode);
- BUG_ON(dentry->d_name.name != dentry->d_iname ||
-- !hlist_unhashed(&dentry->d_u.d_alias) ||
-+ !hlist_unhashed(&dentry->d_alias) ||
- !d_unlinked(dentry));
- spin_lock(&dentry->d_parent->d_lock);
- spin_lock_nested(&dentry->d_lock, DENTRY_D_LOCK_NESTED);
-diff -Nur linux-3.12.38/fs/debugfs/inode.c linux-rpi/fs/debugfs/inode.c
---- linux-3.12.38/fs/debugfs/inode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/debugfs/inode.c 2015-03-10 17:26:51.458216686 +0100
-@@ -549,10 +549,10 @@
- /*
- * The parent->d_subdirs is protected by the d_lock. Outside that
- * lock, the child can be unlinked and set to be freed which can
-- * use the d_child as the rcu head and corrupt this list.
-+ * use the d_u.d_child as the rcu head and corrupt this list.
- */
- spin_lock(&parent->d_lock);
-- list_for_each_entry(child, &parent->d_subdirs, d_child) {
-+ list_for_each_entry(child, &parent->d_subdirs, d_u.d_child) {
- if (!debugfs_positive(child))
- continue;
-
-diff -Nur linux-3.12.38/fs/exportfs/expfs.c linux-rpi/fs/exportfs/expfs.c
---- linux-3.12.38/fs/exportfs/expfs.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/exportfs/expfs.c 2015-03-10 17:26:51.462216686 +0100
-@@ -50,7 +50,7 @@
-
- inode = result->d_inode;
- spin_lock(&inode->i_lock);
-- hlist_for_each_entry(dentry, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(dentry, &inode->i_dentry, d_alias) {
- dget(dentry);
- spin_unlock(&inode->i_lock);
- if (toput)
-diff -Nur linux-3.12.38/fs/ext4/file.c linux-rpi/fs/ext4/file.c
---- linux-3.12.38/fs/ext4/file.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ext4/file.c 2015-03-10 17:26:51.470216686 +0100
-@@ -100,7 +100,7 @@
- struct blk_plug plug;
- int unaligned_aio = 0;
- ssize_t ret;
-- int *overwrite = iocb->private;
-+ int overwrite = 0;
- size_t length = iov_length(iov, nr_segs);
-
- if (ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS) &&
-@@ -118,6 +118,8 @@
- mutex_lock(&inode->i_mutex);
- blk_start_plug(&plug);
-
-+ iocb->private = &overwrite;
-+
- /* check whether we do a DIO overwrite or not */
- if (ext4_should_dioread_nolock(inode) && !unaligned_aio &&
- !file->f_mapping->nrpages && pos + length <= i_size_read(inode)) {
-@@ -141,7 +143,7 @@
- * So we should check these two conditions.
- */
- if (err == len && (map.m_flags & EXT4_MAP_MAPPED))
-- *overwrite = 1;
-+ overwrite = 1;
- }
-
- ret = __generic_file_aio_write(iocb, iov, nr_segs, &iocb->ki_pos);
-@@ -168,7 +170,6 @@
- {
- struct inode *inode = file_inode(iocb->ki_filp);
- ssize_t ret;
-- int overwrite = 0;
-
- /*
- * If we have encountered a bitmap-format file, the size limit
-@@ -189,7 +190,6 @@
- }
- }
-
-- iocb->private = &overwrite;
- if (unlikely(iocb->ki_filp->f_flags & O_DIRECT))
- ret = ext4_file_dio_write(iocb, iov, nr_segs, pos);
- else
-diff -Nur linux-3.12.38/fs/fs-writeback.c linux-rpi/fs/fs-writeback.c
---- linux-3.12.38/fs/fs-writeback.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/fs-writeback.c 2015-03-10 17:26:51.478216686 +0100
-@@ -475,28 +475,12 @@
- * write_inode()
- */
- spin_lock(&inode->i_lock);
--
-+ /* Clear I_DIRTY_PAGES if we've written out all dirty pages */
-+ if (!mapping_tagged(mapping, PAGECACHE_TAG_DIRTY))
-+ inode->i_state &= ~I_DIRTY_PAGES;
- dirty = inode->i_state & I_DIRTY;
-- inode->i_state &= ~I_DIRTY;
--
-- /*
-- * Paired with smp_mb() in __mark_inode_dirty(). This allows
-- * __mark_inode_dirty() to test i_state without grabbing i_lock -
-- * either they see the I_DIRTY bits cleared or we see the dirtied
-- * inode.
-- *
-- * I_DIRTY_PAGES is always cleared together above even if @mapping
-- * still has dirty pages. The flag is reinstated after smp_mb() if
-- * necessary. This guarantees that either __mark_inode_dirty()
-- * sees clear I_DIRTY_PAGES or we see PAGECACHE_TAG_DIRTY.
-- */
-- smp_mb();
--
-- if (mapping_tagged(mapping, PAGECACHE_TAG_DIRTY))
-- inode->i_state |= I_DIRTY_PAGES;
--
-+ inode->i_state &= ~(I_DIRTY_SYNC | I_DIRTY_DATASYNC);
- spin_unlock(&inode->i_lock);
--
- /* Don't write the inode if only I_DIRTY_PAGES was set */
- if (dirty & (I_DIRTY_SYNC | I_DIRTY_DATASYNC)) {
- int err = write_inode(inode, wbc);
-@@ -1160,11 +1144,12 @@
- }
-
- /*
-- * Paired with smp_mb() in __writeback_single_inode() for the
-- * following lockless i_state test. See there for details.
-+ * make sure that changes are seen by all cpus before we test i_state
-+ * -- mikulas
- */
- smp_mb();
-
-+ /* avoid the locking if we can */
- if ((inode->i_state & flags) == flags)
- return;
-
-diff -Nur linux-3.12.38/fs/libfs.c linux-rpi/fs/libfs.c
---- linux-3.12.38/fs/libfs.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/libfs.c 2015-03-10 17:26:51.498216686 +0100
-@@ -105,18 +105,18 @@
-
- spin_lock(&dentry->d_lock);
- /* d_lock not required for cursor */
-- list_del(&cursor->d_child);
-+ list_del(&cursor->d_u.d_child);
- p = dentry->d_subdirs.next;
- while (n && p != &dentry->d_subdirs) {
- struct dentry *next;
-- next = list_entry(p, struct dentry, d_child);
-+ next = list_entry(p, struct dentry, d_u.d_child);
- spin_lock_nested(&next->d_lock, DENTRY_D_LOCK_NESTED);
- if (simple_positive(next))
- n--;
- spin_unlock(&next->d_lock);
- p = p->next;
- }
-- list_add_tail(&cursor->d_child, p);
-+ list_add_tail(&cursor->d_u.d_child, p);
- spin_unlock(&dentry->d_lock);
- }
- }
-@@ -140,7 +140,7 @@
- {
- struct dentry *dentry = file->f_path.dentry;
- struct dentry *cursor = file->private_data;
-- struct list_head *p, *q = &cursor->d_child;
-+ struct list_head *p, *q = &cursor->d_u.d_child;
-
- if (!dir_emit_dots(file, ctx))
- return 0;
-@@ -149,7 +149,7 @@
- list_move(q, &dentry->d_subdirs);
-
- for (p = q->next; p != &dentry->d_subdirs; p = p->next) {
-- struct dentry *next = list_entry(p, struct dentry, d_child);
-+ struct dentry *next = list_entry(p, struct dentry, d_u.d_child);
- spin_lock_nested(&next->d_lock, DENTRY_D_LOCK_NESTED);
- if (!simple_positive(next)) {
- spin_unlock(&next->d_lock);
-@@ -270,7 +270,7 @@
- int ret = 0;
-
- spin_lock(&dentry->d_lock);
-- list_for_each_entry(child, &dentry->d_subdirs, d_child) {
-+ list_for_each_entry(child, &dentry->d_subdirs, d_u.d_child) {
- spin_lock_nested(&child->d_lock, DENTRY_D_LOCK_NESTED);
- if (simple_positive(child)) {
- spin_unlock(&child->d_lock);
-diff -Nur linux-3.12.38/fs/lockd/svc.c linux-rpi/fs/lockd/svc.c
---- linux-3.12.38/fs/lockd/svc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/lockd/svc.c 2015-03-10 17:26:51.498216686 +0100
-@@ -137,6 +137,10 @@
-
- dprintk("NFS locking service started (ver " LOCKD_VERSION ").\n");
-
-+ if (!nlm_timeout)
-+ nlm_timeout = LOCKD_DFLT_TIMEO;
-+ nlmsvc_timeout = nlm_timeout * HZ;
-+
- /*
- * The main request loop. We don't terminate until the last
- * NFS mount or NFS daemon has gone away.
-@@ -342,10 +346,6 @@
- printk(KERN_WARNING
- "lockd_up: no pid, %d users??\n", nlmsvc_users);
-
-- if (!nlm_timeout)
-- nlm_timeout = LOCKD_DFLT_TIMEO;
-- nlmsvc_timeout = nlm_timeout * HZ;
--
- serv = svc_create(&nlmsvc_program, LOCKD_BUFSIZE, NULL);
- if (!serv) {
- printk(KERN_WARNING "lockd_up: create service failed\n");
-diff -Nur linux-3.12.38/fs/ncpfs/dir.c linux-rpi/fs/ncpfs/dir.c
---- linux-3.12.38/fs/ncpfs/dir.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ncpfs/dir.c 2015-03-10 17:26:51.498216686 +0100
-@@ -407,7 +407,7 @@
- spin_lock(&parent->d_lock);
- next = parent->d_subdirs.next;
- while (next != &parent->d_subdirs) {
-- dent = list_entry(next, struct dentry, d_child);
-+ dent = list_entry(next, struct dentry, d_u.d_child);
- if ((unsigned long)dent->d_fsdata == fpos) {
- if (dent->d_inode)
- dget(dent);
-diff -Nur linux-3.12.38/fs/ncpfs/ncplib_kernel.h linux-rpi/fs/ncpfs/ncplib_kernel.h
---- linux-3.12.38/fs/ncpfs/ncplib_kernel.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ncpfs/ncplib_kernel.h 2015-03-10 17:26:51.502216686 +0100
-@@ -194,7 +194,7 @@
- spin_lock(&parent->d_lock);
- next = parent->d_subdirs.next;
- while (next != &parent->d_subdirs) {
-- dentry = list_entry(next, struct dentry, d_child);
-+ dentry = list_entry(next, struct dentry, d_u.d_child);
-
- if (dentry->d_fsdata == NULL)
- ncp_age_dentry(server, dentry);
-@@ -216,7 +216,7 @@
- spin_lock(&parent->d_lock);
- next = parent->d_subdirs.next;
- while (next != &parent->d_subdirs) {
-- dentry = list_entry(next, struct dentry, d_child);
-+ dentry = list_entry(next, struct dentry, d_u.d_child);
- dentry->d_fsdata = NULL;
- ncp_age_dentry(server, dentry);
- next = next->next;
-diff -Nur linux-3.12.38/fs/nfs/direct.c linux-rpi/fs/nfs/direct.c
---- linux-3.12.38/fs/nfs/direct.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nfs/direct.c 2015-03-10 17:26:51.502216686 +0100
-@@ -123,12 +123,6 @@
- */
- ssize_t nfs_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov, loff_t pos, unsigned long nr_segs)
- {
-- struct inode *inode = iocb->ki_filp->f_mapping->host;
--
-- /* we only support swap file calling nfs_direct_IO */
-- if (!IS_SWAPFILE(inode))
-- return 0;
--
- #ifndef CONFIG_NFS_SWAP
- dprintk("NFS: nfs_direct_IO (%s) off/no(%Ld/%lu) EINVAL\n",
- iocb->ki_filp->f_path.dentry->d_name.name,
-diff -Nur linux-3.12.38/fs/nfs/getroot.c linux-rpi/fs/nfs/getroot.c
---- linux-3.12.38/fs/nfs/getroot.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nfs/getroot.c 2015-03-10 17:26:51.502216686 +0100
-@@ -58,7 +58,7 @@
- */
- spin_lock(&sb->s_root->d_inode->i_lock);
- spin_lock(&sb->s_root->d_lock);
-- hlist_del_init(&sb->s_root->d_u.d_alias);
-+ hlist_del_init(&sb->s_root->d_alias);
- spin_unlock(&sb->s_root->d_lock);
- spin_unlock(&sb->s_root->d_inode->i_lock);
- }
-diff -Nur linux-3.12.38/fs/nfs/nfs4client.c linux-rpi/fs/nfs/nfs4client.c
---- linux-3.12.38/fs/nfs/nfs4client.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nfs/nfs4client.c 2015-03-10 17:26:51.506216686 +0100
-@@ -561,14 +561,20 @@
- }
-
- /*
-- * Returns true if the server major ids match
-+ * Returns true if the server owners match
- */
- static bool
--nfs4_check_clientid_trunking(struct nfs_client *a, struct nfs_client *b)
-+nfs4_match_serverowners(struct nfs_client *a, struct nfs_client *b)
- {
- struct nfs41_server_owner *o1 = a->cl_serverowner;
- struct nfs41_server_owner *o2 = b->cl_serverowner;
-
-+ if (o1->minor_id != o2->minor_id) {
-+ dprintk("NFS: --> %s server owner minor IDs do not match\n",
-+ __func__);
-+ return false;
-+ }
-+
- if (o1->major_id_sz != o2->major_id_sz)
- goto out_major_mismatch;
- if (memcmp(o1->major_id, o2->major_id, o1->major_id_sz) != 0)
-@@ -629,7 +635,7 @@
- prev = pos;
-
- status = nfs_wait_client_init_complete(pos);
-- if (pos->cl_cons_state == NFS_CS_SESSION_INITING) {
-+ if (status == 0) {
- nfs4_schedule_lease_recovery(pos);
- status = nfs4_wait_clnt_recover(pos);
- }
-@@ -644,12 +650,7 @@
- if (!nfs4_match_clientids(pos, new))
- continue;
-
-- /*
-- * Note that session trunking is just a special subcase of
-- * client id trunking. In either case, we want to fall back
-- * to using the existing nfs_client.
-- */
-- if (!nfs4_check_clientid_trunking(pos, new))
-+ if (!nfs4_match_serverowners(pos, new))
- continue;
-
- atomic_inc(&pos->cl_count);
-diff -Nur linux-3.12.38/fs/nfsd/nfs4state.c linux-rpi/fs/nfsd/nfs4state.c
---- linux-3.12.38/fs/nfsd/nfs4state.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nfsd/nfs4state.c 2015-03-10 17:26:51.514216686 +0100
-@@ -1197,14 +1197,15 @@
- return 0;
- }
-
--static int
-+static long long
- compare_blob(const struct xdr_netobj *o1, const struct xdr_netobj *o2)
- {
-- if (o1->len < o2->len)
-- return -1;
-- if (o1->len > o2->len)
-- return 1;
-- return memcmp(o1->data, o2->data, o1->len);
-+ long long res;
-+
-+ res = o1->len - o2->len;
-+ if (res)
-+ return res;
-+ return (long long)memcmp(o1->data, o2->data, o1->len);
- }
-
- static int same_name(const char *n1, const char *n2)
-@@ -1388,7 +1389,7 @@
- static struct nfs4_client *
- find_clp_in_name_tree(struct xdr_netobj *name, struct rb_root *root)
- {
-- int cmp;
-+ long long cmp;
- struct rb_node *node = root->rb_node;
- struct nfs4_client *clp;
-
-diff -Nur linux-3.12.38/fs/nfsd/nfs4xdr.c linux-rpi/fs/nfsd/nfs4xdr.c
---- linux-3.12.38/fs/nfsd/nfs4xdr.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nfsd/nfs4xdr.c 2015-03-10 17:26:51.514216686 +0100
-@@ -1786,9 +1786,6 @@
- }
- else
- end++;
-- if (found_esc)
-- end = next;
--
- str = end;
- }
- *pp = p;
-diff -Nur linux-3.12.38/fs/nilfs2/inode.c linux-rpi/fs/nilfs2/inode.c
---- linux-3.12.38/fs/nilfs2/inode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nilfs2/inode.c 2015-03-10 17:26:51.514216686 +0100
-@@ -49,8 +49,6 @@
- int for_gc;
- };
-
--static int nilfs_iget_test(struct inode *inode, void *opaque);
--
- void nilfs_inode_add_blocks(struct inode *inode, int n)
- {
- struct nilfs_root *root = NILFS_I(inode)->i_root;
-@@ -349,17 +347,6 @@
- .is_partially_uptodate = block_is_partially_uptodate,
- };
-
--static int nilfs_insert_inode_locked(struct inode *inode,
-- struct nilfs_root *root,
-- unsigned long ino)
--{
-- struct nilfs_iget_args args = {
-- .ino = ino, .root = root, .cno = 0, .for_gc = 0
-- };
--
-- return insert_inode_locked4(inode, ino, nilfs_iget_test, &args);
--}
--
- struct inode *nilfs_new_inode(struct inode *dir, umode_t mode)
- {
- struct super_block *sb = dir->i_sb;
-@@ -395,7 +382,7 @@
- if (S_ISREG(mode) || S_ISDIR(mode) || S_ISLNK(mode)) {
- err = nilfs_bmap_read(ii->i_bmap, NULL);
- if (err < 0)
-- goto failed_after_creation;
-+ goto failed_bmap;
-
- set_bit(NILFS_I_BMAP, &ii->i_state);
- /* No lock is needed; iget() ensures it. */
-@@ -411,24 +398,21 @@
- spin_lock(&nilfs->ns_next_gen_lock);
- inode->i_generation = nilfs->ns_next_generation++;
- spin_unlock(&nilfs->ns_next_gen_lock);
-- if (nilfs_insert_inode_locked(inode, root, ino) < 0) {
-- err = -EIO;
-- goto failed_after_creation;
-- }
-+ insert_inode_hash(inode);
-
- err = nilfs_init_acl(inode, dir);
- if (unlikely(err))
-- goto failed_after_creation; /* never occur. When supporting
-+ goto failed_acl; /* never occur. When supporting
- nilfs_init_acl(), proper cancellation of
- above jobs should be considered */
-
- return inode;
-
-- failed_after_creation:
-+ failed_acl:
-+ failed_bmap:
- clear_nlink(inode);
-- unlock_new_inode(inode);
- iput(inode); /* raw_inode will be deleted through
-- nilfs_evict_inode() */
-+ generic_delete_inode() */
- goto failed;
-
- failed_ifile_create_inode:
-@@ -476,8 +460,8 @@
- inode->i_atime.tv_nsec = le32_to_cpu(raw_inode->i_mtime_nsec);
- inode->i_ctime.tv_nsec = le32_to_cpu(raw_inode->i_ctime_nsec);
- inode->i_mtime.tv_nsec = le32_to_cpu(raw_inode->i_mtime_nsec);
-- if (inode->i_nlink == 0)
-- return -ESTALE; /* this inode is deleted */
-+ if (inode->i_nlink == 0 && inode->i_mode == 0)
-+ return -EINVAL; /* this inode is deleted */
-
- inode->i_blocks = le64_to_cpu(raw_inode->i_blocks);
- ii->i_flags = le32_to_cpu(raw_inode->i_flags);
-diff -Nur linux-3.12.38/fs/nilfs2/namei.c linux-rpi/fs/nilfs2/namei.c
---- linux-3.12.38/fs/nilfs2/namei.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nilfs2/namei.c 2015-03-10 17:26:51.514216686 +0100
-@@ -51,11 +51,9 @@
- int err = nilfs_add_link(dentry, inode);
- if (!err) {
- d_instantiate(dentry, inode);
-- unlock_new_inode(inode);
- return 0;
- }
- inode_dec_link_count(inode);
-- unlock_new_inode(inode);
- iput(inode);
- return err;
- }
-@@ -184,7 +182,6 @@
- out_fail:
- drop_nlink(inode);
- nilfs_mark_inode_dirty(inode);
-- unlock_new_inode(inode);
- iput(inode);
- goto out;
- }
-@@ -204,15 +201,11 @@
- inode_inc_link_count(inode);
- ihold(inode);
-
-- err = nilfs_add_link(dentry, inode);
-- if (!err) {
-- d_instantiate(dentry, inode);
-+ err = nilfs_add_nondir(dentry, inode);
-+ if (!err)
- err = nilfs_transaction_commit(dir->i_sb);
-- } else {
-- inode_dec_link_count(inode);
-- iput(inode);
-+ else
- nilfs_transaction_abort(dir->i_sb);
-- }
-
- return err;
- }
-@@ -250,7 +243,6 @@
-
- nilfs_mark_inode_dirty(inode);
- d_instantiate(dentry, inode);
-- unlock_new_inode(inode);
- out:
- if (!err)
- err = nilfs_transaction_commit(dir->i_sb);
-@@ -263,7 +255,6 @@
- drop_nlink(inode);
- drop_nlink(inode);
- nilfs_mark_inode_dirty(inode);
-- unlock_new_inode(inode);
- iput(inode);
- out_dir:
- drop_nlink(dir);
-diff -Nur linux-3.12.38/fs/nilfs2/nilfs.h linux-rpi/fs/nilfs2/nilfs.h
---- linux-3.12.38/fs/nilfs2/nilfs.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nilfs2/nilfs.h 2015-03-10 17:26:51.514216686 +0100
-@@ -141,6 +141,7 @@
- * @ti_save: Backup of journal_info field of task_struct
- * @ti_flags: Flags
- * @ti_count: Nest level
-+ * @ti_garbage: List of inode to be put when releasing semaphore
- */
- struct nilfs_transaction_info {
- u32 ti_magic;
-@@ -149,6 +150,7 @@
- one of other filesystems has a bug. */
- unsigned short ti_flags;
- unsigned short ti_count;
-+ struct list_head ti_garbage;
- };
-
- /* ti_magic */
-diff -Nur linux-3.12.38/fs/nilfs2/segment.c linux-rpi/fs/nilfs2/segment.c
---- linux-3.12.38/fs/nilfs2/segment.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nilfs2/segment.c 2015-03-10 17:26:51.514216686 +0100
-@@ -305,6 +305,7 @@
- ti->ti_count = 0;
- ti->ti_save = cur_ti;
- ti->ti_magic = NILFS_TI_MAGIC;
-+ INIT_LIST_HEAD(&ti->ti_garbage);
- current->journal_info = ti;
-
- for (;;) {
-@@ -331,6 +332,8 @@
-
- up_write(&nilfs->ns_segctor_sem);
- current->journal_info = ti->ti_save;
-+ if (!list_empty(&ti->ti_garbage))
-+ nilfs_dispose_list(nilfs, &ti->ti_garbage, 0);
- }
-
- static void *nilfs_segctor_map_segsum_entry(struct nilfs_sc_info *sci,
-@@ -743,15 +746,6 @@
- }
- }
-
--static void nilfs_iput_work_func(struct work_struct *work)
--{
-- struct nilfs_sc_info *sci = container_of(work, struct nilfs_sc_info,
-- sc_iput_work);
-- struct the_nilfs *nilfs = sci->sc_super->s_fs_info;
--
-- nilfs_dispose_list(nilfs, &sci->sc_iput_queue, 0);
--}
--
- static int nilfs_test_metadata_dirty(struct the_nilfs *nilfs,
- struct nilfs_root *root)
- {
-@@ -1906,8 +1900,8 @@
- static void nilfs_segctor_drop_written_files(struct nilfs_sc_info *sci,
- struct the_nilfs *nilfs)
- {
-+ struct nilfs_transaction_info *ti = current->journal_info;
- struct nilfs_inode_info *ii, *n;
-- int defer_iput = false;
-
- spin_lock(&nilfs->ns_inode_lock);
- list_for_each_entry_safe(ii, n, &sci->sc_dirty_files, i_dirty) {
-@@ -1918,24 +1912,9 @@
- clear_bit(NILFS_I_BUSY, &ii->i_state);
- brelse(ii->i_bh);
- ii->i_bh = NULL;
-- list_del_init(&ii->i_dirty);
-- if (!ii->vfs_inode.i_nlink) {
-- /*
-- * Defer calling iput() to avoid a deadlock
-- * over I_SYNC flag for inodes with i_nlink == 0
-- */
-- list_add_tail(&ii->i_dirty, &sci->sc_iput_queue);
-- defer_iput = true;
-- } else {
-- spin_unlock(&nilfs->ns_inode_lock);
-- iput(&ii->vfs_inode);
-- spin_lock(&nilfs->ns_inode_lock);
-- }
-+ list_move_tail(&ii->i_dirty, &ti->ti_garbage);
- }
- spin_unlock(&nilfs->ns_inode_lock);
--
-- if (defer_iput)
-- schedule_work(&sci->sc_iput_work);
- }
-
- /*
-@@ -2604,8 +2583,6 @@
- INIT_LIST_HEAD(&sci->sc_segbufs);
- INIT_LIST_HEAD(&sci->sc_write_logs);
- INIT_LIST_HEAD(&sci->sc_gc_inodes);
-- INIT_LIST_HEAD(&sci->sc_iput_queue);
-- INIT_WORK(&sci->sc_iput_work, nilfs_iput_work_func);
- init_timer(&sci->sc_timer);
-
- sci->sc_interval = HZ * NILFS_SC_DEFAULT_TIMEOUT;
-@@ -2632,8 +2609,6 @@
- ret = nilfs_segctor_construct(sci, SC_LSEG_SR);
- nilfs_transaction_unlock(sci->sc_super);
-
-- flush_work(&sci->sc_iput_work);
--
- } while (ret && retrycount-- > 0);
- }
-
-@@ -2658,9 +2633,6 @@
- || sci->sc_seq_request != sci->sc_seq_done);
- spin_unlock(&sci->sc_state_lock);
-
-- if (flush_work(&sci->sc_iput_work))
-- flag = true;
--
- if (flag || !nilfs_segctor_confirm(sci))
- nilfs_segctor_write_out(sci);
-
-@@ -2670,12 +2642,6 @@
- nilfs_dispose_list(nilfs, &sci->sc_dirty_files, 1);
- }
-
-- if (!list_empty(&sci->sc_iput_queue)) {
-- nilfs_warning(sci->sc_super, __func__,
-- "iput queue is not empty\n");
-- nilfs_dispose_list(nilfs, &sci->sc_iput_queue, 1);
-- }
--
- WARN_ON(!list_empty(&sci->sc_segbufs));
- WARN_ON(!list_empty(&sci->sc_write_logs));
-
-diff -Nur linux-3.12.38/fs/nilfs2/segment.h linux-rpi/fs/nilfs2/segment.h
---- linux-3.12.38/fs/nilfs2/segment.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/nilfs2/segment.h 2015-03-10 17:26:51.514216686 +0100
-@@ -26,7 +26,6 @@
- #include <linux/types.h>
- #include <linux/fs.h>
- #include <linux/buffer_head.h>
--#include <linux/workqueue.h>
- #include <linux/nilfs2_fs.h>
- #include "nilfs.h"
-
-@@ -93,8 +92,6 @@
- * @sc_nblk_inc: Block count of current generation
- * @sc_dirty_files: List of files to be written
- * @sc_gc_inodes: List of GC inodes having blocks to be written
-- * @sc_iput_queue: list of inodes for which iput should be done
-- * @sc_iput_work: work struct to defer iput call
- * @sc_freesegs: array of segment numbers to be freed
- * @sc_nfreesegs: number of segments on @sc_freesegs
- * @sc_dsync_inode: inode whose data pages are written for a sync operation
-@@ -138,8 +135,6 @@
-
- struct list_head sc_dirty_files;
- struct list_head sc_gc_inodes;
-- struct list_head sc_iput_queue;
-- struct work_struct sc_iput_work;
-
- __u64 *sc_freesegs;
- size_t sc_nfreesegs;
-diff -Nur linux-3.12.38/fs/notify/fsnotify.c linux-rpi/fs/notify/fsnotify.c
---- linux-3.12.38/fs/notify/fsnotify.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/notify/fsnotify.c 2015-03-10 17:26:51.530216686 +0100
-@@ -63,14 +63,14 @@
- spin_lock(&inode->i_lock);
- /* run all of the dentries associated with this inode. Since this is a
- * directory, there damn well better only be one item on this list */
-- hlist_for_each_entry(alias, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(alias, &inode->i_dentry, d_alias) {
- struct dentry *child;
-
- /* run all of the children of the original inode and fix their
- * d_flags to indicate parental interest (their parent is the
- * original inode) */
- spin_lock(&alias->d_lock);
-- list_for_each_entry(child, &alias->d_subdirs, d_child) {
-+ list_for_each_entry(child, &alias->d_subdirs, d_u.d_child) {
- if (!child->d_inode)
- continue;
-
-diff -Nur linux-3.12.38/fs/notify/inode_mark.c linux-rpi/fs/notify/inode_mark.c
---- linux-3.12.38/fs/notify/inode_mark.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/notify/inode_mark.c 2015-03-10 17:26:51.530216686 +0100
-@@ -288,25 +288,20 @@
- spin_unlock(&inode->i_lock);
-
- /* In case the dropping of a reference would nuke next_i. */
-- while (&next_i->i_sb_list != list) {
-+ if ((&next_i->i_sb_list != list) &&
-+ atomic_read(&next_i->i_count)) {
- spin_lock(&next_i->i_lock);
-- if (!(next_i->i_state & (I_FREEING | I_WILL_FREE)) &&
-- atomic_read(&next_i->i_count)) {
-+ if (!(next_i->i_state & (I_FREEING | I_WILL_FREE))) {
- __iget(next_i);
- need_iput = next_i;
-- spin_unlock(&next_i->i_lock);
-- break;
- }
- spin_unlock(&next_i->i_lock);
-- next_i = list_entry(next_i->i_sb_list.next,
-- struct inode, i_sb_list);
- }
-
- /*
-- * We can safely drop inode_sb_list_lock here because either
-- * we actually hold references on both inode and next_i or
-- * end of list. Also no new inodes will be added since the
-- * umount has begun.
-+ * We can safely drop inode_sb_list_lock here because we hold
-+ * references on both inode and next_i. Also no new inodes
-+ * will be added since the umount has begun.
- */
- spin_unlock(&inode_sb_list_lock);
-
-diff -Nur linux-3.12.38/fs/ocfs2/aops.c linux-rpi/fs/ocfs2/aops.c
---- linux-3.12.38/fs/ocfs2/aops.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ocfs2/aops.c 2015-03-10 17:26:51.534216686 +0100
-@@ -912,7 +912,7 @@
- }
- }
-
--static void ocfs2_unlock_pages(struct ocfs2_write_ctxt *wc)
-+static void ocfs2_free_write_ctxt(struct ocfs2_write_ctxt *wc)
- {
- int i;
-
-@@ -933,11 +933,7 @@
- page_cache_release(wc->w_target_page);
- }
- ocfs2_unlock_and_free_pages(wc->w_pages, wc->w_num_pages);
--}
-
--static void ocfs2_free_write_ctxt(struct ocfs2_write_ctxt *wc)
--{
-- ocfs2_unlock_pages(wc);
- brelse(wc->w_di_bh);
- kfree(wc);
- }
-@@ -2059,19 +2055,11 @@
- di->i_mtime_nsec = di->i_ctime_nsec = cpu_to_le32(inode->i_mtime.tv_nsec);
- ocfs2_journal_dirty(handle, wc->w_di_bh);
-
-- /* unlock pages before dealloc since it needs acquiring j_trans_barrier
-- * lock, or it will cause a deadlock since journal commit threads holds
-- * this lock and will ask for the page lock when flushing the data.
-- * put it here to preserve the unlock order.
-- */
-- ocfs2_unlock_pages(wc);
--
- ocfs2_commit_trans(osb, handle);
-
- ocfs2_run_deallocs(osb, &wc->w_dealloc);
-
-- brelse(wc->w_di_bh);
-- kfree(wc);
-+ ocfs2_free_write_ctxt(wc);
-
- return copied;
- }
-diff -Nur linux-3.12.38/fs/ocfs2/dcache.c linux-rpi/fs/ocfs2/dcache.c
---- linux-3.12.38/fs/ocfs2/dcache.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ocfs2/dcache.c 2015-03-10 17:26:51.534216686 +0100
-@@ -172,7 +172,7 @@
- struct dentry *dentry;
-
- spin_lock(&inode->i_lock);
-- hlist_for_each_entry(dentry, &inode->i_dentry, d_u.d_alias) {
-+ hlist_for_each_entry(dentry, &inode->i_dentry, d_alias) {
- spin_lock(&dentry->d_lock);
- if (ocfs2_match_dentry(dentry, parent_blkno, skip_unhashed)) {
- trace_ocfs2_find_local_alias(dentry->d_name.len,
-diff -Nur linux-3.12.38/fs/ocfs2/file.c linux-rpi/fs/ocfs2/file.c
---- linux-3.12.38/fs/ocfs2/file.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/ocfs2/file.c 2015-03-10 17:26:51.538216686 +0100
-@@ -2376,7 +2376,9 @@
- if (ret < 0)
- written = ret;
-
-- if (!ret) {
-+ if (!ret && ((old_size != i_size_read(inode)) ||
-+ (old_clusters != OCFS2_I(inode)->ip_clusters) ||
-+ has_refcount)) {
- ret = jbd2_journal_force_commit(osb->journal->j_journal);
- if (ret < 0)
- written = ret;
-diff -Nur linux-3.12.38/fs/proc/stat.c linux-rpi/fs/proc/stat.c
---- linux-3.12.38/fs/proc/stat.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/proc/stat.c 2015-03-10 17:26:51.546216686 +0100
-@@ -159,7 +159,7 @@
-
- /* sum again ? it could be updated? */
- for_each_irq_nr(j)
-- seq_put_decimal_ull(p, ' ', kstat_irqs_usr(j));
-+ seq_put_decimal_ull(p, ' ', kstat_irqs(j));
-
- seq_printf(p,
- "\nctxt %llu\n"
-diff -Nur linux-3.12.38/fs/pstore/ram.c linux-rpi/fs/pstore/ram.c
---- linux-3.12.38/fs/pstore/ram.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/pstore/ram.c 2015-03-10 17:26:51.546216686 +0100
-@@ -61,11 +61,6 @@
- MODULE_PARM_DESC(mem_size,
- "size of reserved RAM used to store oops/panic logs");
-
--static unsigned int mem_type;
--module_param(mem_type, uint, 0600);
--MODULE_PARM_DESC(mem_type,
-- "set to 1 to try to use unbuffered memory (default 0)");
--
- static int dump_oops = 1;
- module_param(dump_oops, int, 0600);
- MODULE_PARM_DESC(dump_oops,
-@@ -84,7 +79,6 @@
- struct persistent_ram_zone *fprz;
- phys_addr_t phys_addr;
- unsigned long size;
-- unsigned int memtype;
- size_t record_size;
- size_t console_size;
- size_t ftrace_size;
-@@ -92,7 +86,6 @@
- struct persistent_ram_ecc_info ecc_info;
- unsigned int max_dump_cnt;
- unsigned int dump_write_cnt;
-- /* _read_cnt need clear on ramoops_pstore_open */
- unsigned int dump_read_cnt;
- unsigned int console_read_cnt;
- unsigned int ftrace_read_cnt;
-@@ -108,7 +101,6 @@
-
- cxt->dump_read_cnt = 0;
- cxt->console_read_cnt = 0;
-- cxt->ftrace_read_cnt = 0;
- return 0;
- }
-
-@@ -125,15 +117,13 @@
- return NULL;
-
- prz = przs[i];
-- if (!prz)
-- return NULL;
-
-- /* Update old/shadowed buffer. */
-- if (update)
-+ if (update) {
-+ /* Update old/shadowed buffer. */
- persistent_ram_save_old(prz);
--
-- if (!persistent_ram_old_size(prz))
-- return NULL;
-+ if (!persistent_ram_old_size(prz))
-+ return NULL;
-+ }
-
- *typep = type;
- *id = i;
-@@ -363,8 +353,7 @@
- size_t sz = cxt->record_size;
-
- cxt->przs[i] = persistent_ram_new(*paddr, sz, 0,
-- &cxt->ecc_info,
-- cxt->memtype);
-+ &cxt->ecc_info);
- if (IS_ERR(cxt->przs[i])) {
- err = PTR_ERR(cxt->przs[i]);
- dev_err(dev, "failed to request mem region (0x%zx@0x%llx): %d\n",
-@@ -394,7 +383,7 @@
- return -ENOMEM;
- }
-
-- *prz = persistent_ram_new(*paddr, sz, sig, &cxt->ecc_info, cxt->memtype);
-+ *prz = persistent_ram_new(*paddr, sz, sig, &cxt->ecc_info);
- if (IS_ERR(*prz)) {
- int err = PTR_ERR(*prz);
-
-@@ -439,9 +428,9 @@
- if (pdata->ftrace_size && !is_power_of_2(pdata->ftrace_size))
- pdata->ftrace_size = rounddown_pow_of_two(pdata->ftrace_size);
-
-+ cxt->dump_read_cnt = 0;
- cxt->size = pdata->mem_size;
- cxt->phys_addr = pdata->mem_address;
-- cxt->memtype = pdata->mem_type;
- cxt->record_size = pdata->record_size;
- cxt->console_size = pdata->console_size;
- cxt->ftrace_size = pdata->ftrace_size;
-@@ -572,7 +561,6 @@
-
- dummy_data->mem_size = mem_size;
- dummy_data->mem_address = mem_address;
-- dummy_data->mem_type = 0;
- dummy_data->record_size = record_size;
- dummy_data->console_size = ramoops_console_size;
- dummy_data->ftrace_size = ramoops_ftrace_size;
-diff -Nur linux-3.12.38/fs/pstore/ram_core.c linux-rpi/fs/pstore/ram_core.c
---- linux-3.12.38/fs/pstore/ram_core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/pstore/ram_core.c 2015-03-10 17:26:51.546216686 +0100
-@@ -380,8 +380,7 @@
- persistent_ram_update_header_ecc(prz);
- }
-
--static void *persistent_ram_vmap(phys_addr_t start, size_t size,
-- unsigned int memtype)
-+static void *persistent_ram_vmap(phys_addr_t start, size_t size)
- {
- struct page **pages;
- phys_addr_t page_start;
-@@ -393,10 +392,7 @@
- page_start = start - offset_in_page(start);
- page_count = DIV_ROUND_UP(size + offset_in_page(start), PAGE_SIZE);
-
-- if (memtype)
-- prot = pgprot_noncached(PAGE_KERNEL);
-- else
-- prot = pgprot_writecombine(PAGE_KERNEL);
-+ prot = pgprot_noncached(PAGE_KERNEL);
-
- pages = kmalloc(sizeof(struct page *) * page_count, GFP_KERNEL);
- if (!pages) {
-@@ -415,11 +411,8 @@
- return vaddr;
- }
-
--static void *persistent_ram_iomap(phys_addr_t start, size_t size,
-- unsigned int memtype)
-+static void *persistent_ram_iomap(phys_addr_t start, size_t size)
- {
-- void *va;
--
- if (!request_mem_region(start, size, "persistent_ram")) {
- pr_err("request mem region (0x%llx@0x%llx) failed\n",
- (unsigned long long)size, (unsigned long long)start);
-@@ -429,24 +422,19 @@
- buffer_start_add = buffer_start_add_locked;
- buffer_size_add = buffer_size_add_locked;
-
-- if (memtype)
-- va = ioremap(start, size);
-- else
-- va = ioremap_wc(start, size);
--
-- return va;
-+ return ioremap(start, size);
- }
-
- static int persistent_ram_buffer_map(phys_addr_t start, phys_addr_t size,
-- struct persistent_ram_zone *prz, int memtype)
-+ struct persistent_ram_zone *prz)
- {
- prz->paddr = start;
- prz->size = size;
-
- if (pfn_valid(start >> PAGE_SHIFT))
-- prz->vaddr = persistent_ram_vmap(start, size, memtype);
-+ prz->vaddr = persistent_ram_vmap(start, size);
- else
-- prz->vaddr = persistent_ram_iomap(start, size, memtype);
-+ prz->vaddr = persistent_ram_iomap(start, size);
-
- if (!prz->vaddr) {
- pr_err("%s: Failed to map 0x%llx pages at 0x%llx\n", __func__,
-@@ -514,8 +502,7 @@
- }
-
- struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, size_t size,
-- u32 sig, struct persistent_ram_ecc_info *ecc_info,
-- unsigned int memtype)
-+ u32 sig, struct persistent_ram_ecc_info *ecc_info)
- {
- struct persistent_ram_zone *prz;
- int ret = -ENOMEM;
-@@ -526,7 +513,7 @@
- goto err;
- }
-
-- ret = persistent_ram_buffer_map(start, size, prz, memtype);
-+ ret = persistent_ram_buffer_map(start, size, prz);
- if (ret)
- goto err;
-
-diff -Nur linux-3.12.38/fs/udf/dir.c linux-rpi/fs/udf/dir.c
---- linux-3.12.38/fs/udf/dir.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/udf/dir.c 2015-03-10 17:26:51.562216686 +0100
-@@ -167,8 +167,7 @@
- continue;
- }
-
-- flen = udf_get_filename(dir->i_sb, nameptr, lfi, fname,
-- UDF_NAME_LEN);
-+ flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi);
- if (!flen)
- continue;
-
-diff -Nur linux-3.12.38/fs/udf/inode.c linux-rpi/fs/udf/inode.c
---- linux-3.12.38/fs/udf/inode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/udf/inode.c 2015-03-10 17:26:51.562216686 +0100
-@@ -1495,24 +1495,6 @@
- iinfo->i_checkpoint = le32_to_cpu(efe->checkpoint);
- }
-
-- /* Sanity checks for files in ICB so that we don't get confused later */
-- if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
-- /*
-- * For file in ICB data is stored in allocation descriptor
-- * so sizes should match
-- */
-- if (iinfo->i_lenAlloc != inode->i_size) {
-- make_bad_inode(inode);
-- return;
-- }
-- /* File in ICB has to fit in there... */
-- if (inode->i_size > inode->i_sb->s_blocksize -
-- udf_file_entry_alloc_offset(inode)) {
-- make_bad_inode(inode);
-- return;
-- }
-- }
--
- switch (fe->icbTag.fileType) {
- case ICBTAG_FILE_TYPE_DIRECTORY:
- inode->i_op = &udf_dir_inode_operations;
-diff -Nur linux-3.12.38/fs/udf/namei.c linux-rpi/fs/udf/namei.c
---- linux-3.12.38/fs/udf/namei.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/udf/namei.c 2015-03-10 17:26:51.562216686 +0100
-@@ -233,8 +233,7 @@
- if (!lfi)
- continue;
-
-- flen = udf_get_filename(dir->i_sb, nameptr, lfi, fname,
-- UDF_NAME_LEN);
-+ flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi);
- if (flen && udf_match(flen, fname, child->len, child->name))
- goto out_ok;
- }
-diff -Nur linux-3.12.38/fs/udf/symlink.c linux-rpi/fs/udf/symlink.c
---- linux-3.12.38/fs/udf/symlink.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/udf/symlink.c 2015-03-10 17:26:51.562216686 +0100
-@@ -30,73 +30,49 @@
- #include <linux/buffer_head.h>
- #include "udf_i.h"
-
--static int udf_pc_to_char(struct super_block *sb, unsigned char *from,
-- int fromlen, unsigned char *to, int tolen)
-+static void udf_pc_to_char(struct super_block *sb, unsigned char *from,
-+ int fromlen, unsigned char *to)
- {
- struct pathComponent *pc;
- int elen = 0;
-- int comp_len;
- unsigned char *p = to;
-
-- /* Reserve one byte for terminating \0 */
-- tolen--;
- while (elen < fromlen) {
- pc = (struct pathComponent *)(from + elen);
-- elen += sizeof(struct pathComponent);
- switch (pc->componentType) {
- case 1:
- /*
- * Symlink points to some place which should be agreed
- * upon between originator and receiver of the media. Ignore.
- */
-- if (pc->lengthComponentIdent > 0) {
-- elen += pc->lengthComponentIdent;
-+ if (pc->lengthComponentIdent > 0)
- break;
-- }
- /* Fall through */
- case 2:
-- if (tolen == 0)
-- return -ENAMETOOLONG;
- p = to;
- *p++ = '/';
-- tolen--;
- break;
- case 3:
-- if (tolen < 3)
-- return -ENAMETOOLONG;
- memcpy(p, "../", 3);
- p += 3;
-- tolen -= 3;
- break;
- case 4:
-- if (tolen < 2)
-- return -ENAMETOOLONG;
- memcpy(p, "./", 2);
- p += 2;
-- tolen -= 2;
- /* that would be . - just ignore */
- break;
- case 5:
-- elen += pc->lengthComponentIdent;
-- if (elen > fromlen)
-- return -EIO;
-- comp_len = udf_get_filename(sb, pc->componentIdent,
-- pc->lengthComponentIdent,
-- p, tolen);
-- p += comp_len;
-- tolen -= comp_len;
-- if (tolen == 0)
-- return -ENAMETOOLONG;
-+ p += udf_get_filename(sb, pc->componentIdent, p,
-+ pc->lengthComponentIdent);
- *p++ = '/';
-- tolen--;
- break;
- }
-+ elen += sizeof(struct pathComponent) + pc->lengthComponentIdent;
- }
- if (p > to + 1)
- p[-1] = '\0';
- else
- p[0] = '\0';
-- return 0;
- }
-
- static int udf_symlink_filler(struct file *file, struct page *page)
-@@ -132,10 +108,8 @@
- symlink = bh->b_data;
- }
-
-- err = udf_pc_to_char(inode->i_sb, symlink, inode->i_size, p, PAGE_SIZE);
-+ udf_pc_to_char(inode->i_sb, symlink, inode->i_size, p);
- brelse(bh);
-- if (err)
-- goto out_unlock_inode;
-
- up_read(&iinfo->i_data_sem);
- SetPageUptodate(page);
-diff -Nur linux-3.12.38/fs/udf/udfdecl.h linux-rpi/fs/udf/udfdecl.h
---- linux-3.12.38/fs/udf/udfdecl.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/udf/udfdecl.h 2015-03-10 17:26:51.562216686 +0100
-@@ -201,8 +201,7 @@
- }
-
- /* unicode.c */
--extern int udf_get_filename(struct super_block *, uint8_t *, int, uint8_t *,
-- int);
-+extern int udf_get_filename(struct super_block *, uint8_t *, uint8_t *, int);
- extern int udf_put_filename(struct super_block *, const uint8_t *, uint8_t *,
- int);
- extern int udf_build_ustr(struct ustr *, dstring *, int);
-diff -Nur linux-3.12.38/fs/udf/unicode.c linux-rpi/fs/udf/unicode.c
---- linux-3.12.38/fs/udf/unicode.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/fs/udf/unicode.c 2015-03-10 17:26:51.562216686 +0100
-@@ -28,8 +28,7 @@
-
- #include "udf_sb.h"
-
--static int udf_translate_to_linux(uint8_t *, int, uint8_t *, int, uint8_t *,
-- int);
-+static int udf_translate_to_linux(uint8_t *, uint8_t *, int, uint8_t *, int);
-
- static int udf_char_to_ustr(struct ustr *dest, const uint8_t *src, int strlen)
- {
-@@ -334,8 +333,8 @@
- return u_len + 1;
- }
-
--int udf_get_filename(struct super_block *sb, uint8_t *sname, int slen,
-- uint8_t *dname, int dlen)
-+int udf_get_filename(struct super_block *sb, uint8_t *sname, uint8_t *dname,
-+ int flen)
- {
- struct ustr *filename, *unifilename;
- int len = 0;
-@@ -348,7 +347,7 @@
- if (!unifilename)
- goto out1;
-
-- if (udf_build_ustr_exact(unifilename, sname, slen))
-+ if (udf_build_ustr_exact(unifilename, sname, flen))
- goto out2;
-
- if (UDF_QUERY_FLAG(sb, UDF_FLAG_UTF8)) {
-@@ -367,8 +366,7 @@
- } else
- goto out2;
-
-- len = udf_translate_to_linux(dname, dlen,
-- filename->u_name, filename->u_len,
-+ len = udf_translate_to_linux(dname, filename->u_name, filename->u_len,
- unifilename->u_name, unifilename->u_len);
- out2:
- kfree(unifilename);
-@@ -405,12 +403,10 @@
- #define EXT_MARK '.'
- #define CRC_MARK '#'
- #define EXT_SIZE 5
--/* Number of chars we need to store generated CRC to make filename unique */
--#define CRC_LEN 5
-
--static int udf_translate_to_linux(uint8_t *newName, int newLen,
-- uint8_t *udfName, int udfLen,
-- uint8_t *fidName, int fidNameLen)
-+static int udf_translate_to_linux(uint8_t *newName, uint8_t *udfName,
-+ int udfLen, uint8_t *fidName,
-+ int fidNameLen)
- {
- int index, newIndex = 0, needsCRC = 0;
- int extIndex = 0, newExtIndex = 0, hasExt = 0;
-@@ -444,7 +440,7 @@
- newExtIndex = newIndex;
- }
- }
-- if (newIndex < newLen)
-+ if (newIndex < 256)
- newName[newIndex++] = curr;
- else
- needsCRC = 1;
-@@ -472,13 +468,13 @@
- }
- ext[localExtIndex++] = curr;
- }
-- maxFilenameLen = newLen - CRC_LEN - localExtIndex;
-+ maxFilenameLen = 250 - localExtIndex;
- if (newIndex > maxFilenameLen)
- newIndex = maxFilenameLen;
- else
- newIndex = newExtIndex;
-- } else if (newIndex > newLen - CRC_LEN)
-- newIndex = newLen - CRC_LEN;
-+ } else if (newIndex > 250)
-+ newIndex = 250;
- newName[newIndex++] = CRC_MARK;
- valueCRC = crc_itu_t(0, fidName, fidNameLen);
- newName[newIndex++] = hexChar[(valueCRC & 0xf000) >> 12];
-diff -Nur linux-3.12.38/include/linux/broadcom/vc_cma.h linux-rpi/include/linux/broadcom/vc_cma.h
---- linux-3.12.38/include/linux/broadcom/vc_cma.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/include/linux/broadcom/vc_cma.h 2015-03-09 10:39:35.806893702 +0100
-@@ -0,0 +1,29 @@
-+/*****************************************************************************
-+* Copyright 2012 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#if !defined( VC_CMA_H )
-+#define VC_CMA_H
-+
-+#include <linux/ioctl.h>
-+
-+#define VC_CMA_IOC_MAGIC 0xc5
-+
-+#define VC_CMA_IOC_RESERVE _IO(VC_CMA_IOC_MAGIC, 0)
-+
-+#ifdef __KERNEL__
-+extern void __init vc_cma_early_init(void);
-+extern void __init vc_cma_reserve(void);
-+#endif
-+
-+#endif /* VC_CMA_H */
-diff -Nur linux-3.12.38/include/linux/compat.h linux-rpi/include/linux/compat.h
---- linux-3.12.38/include/linux/compat.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/compat.h 2015-03-10 17:26:51.594216686 +0100
-@@ -318,7 +318,7 @@
- asmlinkage long compat_sys_msgsnd(int msqid, compat_uptr_t msgp,
- compat_ssize_t msgsz, int msgflg);
- asmlinkage long compat_sys_msgrcv(int msqid, compat_uptr_t msgp,
-- compat_ssize_t msgsz, compat_long_t msgtyp, int msgflg);
-+ compat_ssize_t msgsz, long msgtyp, int msgflg);
- long compat_sys_msgctl(int first, int second, void __user *uptr);
- long compat_sys_shmctl(int first, int second, void __user *uptr);
- long compat_sys_semtimedop(int semid, struct sembuf __user *tsems,
-diff -Nur linux-3.12.38/include/linux/crypto.h linux-rpi/include/linux/crypto.h
---- linux-3.12.38/include/linux/crypto.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/crypto.h 2015-03-10 17:26:51.594216686 +0100
-@@ -26,19 +26,6 @@
- #include <linux/uaccess.h>
-
- /*
-- * Autoloaded crypto modules should only use a prefixed name to avoid allowing
-- * arbitrary modules to be loaded. Loading from userspace may still need the
-- * unprefixed names, so retains those aliases as well.
-- * This uses __MODULE_INFO directly instead of MODULE_ALIAS because pre-4.3
-- * gcc (e.g. avr32 toolchain) uses __LINE__ for uniqueness, and this macro
-- * expands twice on the same line. Instead, use a separate base name for the
-- * alias.
-- */
--#define MODULE_ALIAS_CRYPTO(name) \
-- __MODULE_INFO(alias, alias_userspace, name); \
-- __MODULE_INFO(alias, alias_crypto, "crypto-" name)
--
--/*
- * Algorithm masks and types.
- */
- #define CRYPTO_ALG_TYPE_MASK 0x0000000f
-diff -Nur linux-3.12.38/include/linux/dcache.h linux-rpi/include/linux/dcache.h
---- linux-3.12.38/include/linux/dcache.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/dcache.h 2015-03-10 17:26:51.594216686 +0100
-@@ -122,15 +122,15 @@
- void *d_fsdata; /* fs-specific data */
-
- struct list_head d_lru; /* LRU list */
-- struct list_head d_child; /* child of parent list */
-- struct list_head d_subdirs; /* our children */
- /*
-- * d_alias and d_rcu can share memory
-+ * d_child and d_rcu can share memory
- */
- union {
-- struct hlist_node d_alias; /* inode alias list */
-+ struct list_head d_child; /* child of parent list */
- struct rcu_head d_rcu;
- } d_u;
-+ struct list_head d_subdirs; /* our children */
-+ struct hlist_node d_alias; /* inode alias list */
- };
-
- /*
-diff -Nur linux-3.12.38/include/linux/kernel_stat.h linux-rpi/include/linux/kernel_stat.h
---- linux-3.12.38/include/linux/kernel_stat.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/kernel_stat.h 2015-03-10 17:26:51.606216686 +0100
-@@ -74,7 +74,6 @@
- * Number of interrupts per specific IRQ source, since bootup
- */
- extern unsigned int kstat_irqs(unsigned int irq);
--extern unsigned int kstat_irqs_usr(unsigned int irq);
-
- /*
- * Number of interrupts per cpu, since bootup
-diff -Nur linux-3.12.38/include/linux/mmc/host.h linux-rpi/include/linux/mmc/host.h
---- linux-3.12.38/include/linux/mmc/host.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/mmc/host.h 2015-03-10 17:26:51.618216685 +0100
-@@ -281,6 +281,7 @@
- MMC_CAP2_PACKED_WR)
- #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
- #define MMC_CAP2_SANITIZE (1 << 15) /* Support Sanitize */
-+#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
-
- mmc_pm_flag_t pm_caps; /* supported pm features */
-
-diff -Nur linux-3.12.38/include/linux/mmc/sdhci.h linux-rpi/include/linux/mmc/sdhci.h
---- linux-3.12.38/include/linux/mmc/sdhci.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/mmc/sdhci.h 2015-03-10 17:26:51.618216685 +0100
-@@ -98,12 +98,9 @@
- #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
- /* Controller has a non-standard host control register */
- #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
--/* Controller does not support HS200 */
--#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
--/* Controller does not support DDR50 */
--#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
-
- int irq; /* Device IRQ */
-+ int second_irq; /* Additional IRQ to disable/enable in low-latency mode */
- void __iomem *ioaddr; /* Mapped address */
-
- const struct sdhci_ops *ops; /* Low level hw interface */
-@@ -135,6 +132,7 @@
- #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
- #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
- #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
-+#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
-
- unsigned int version; /* SDHCI spec. version */
-
-@@ -150,6 +148,7 @@
-
- struct mmc_request *mrq; /* Current request */
- struct mmc_command *cmd; /* Current command */
-+ int last_cmdop; /* Opcode of last cmd sent */
- struct mmc_data *data; /* Current data request */
- unsigned int data_early:1; /* Data finished before cmd */
-
-diff -Nur linux-3.12.38/include/linux/mm.h linux-rpi/include/linux/mm.h
---- linux-3.12.38/include/linux/mm.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/mm.h 2015-03-10 17:26:51.618216685 +0100
-@@ -1642,7 +1642,7 @@
- #if VM_GROWSUP
- extern int expand_upwards(struct vm_area_struct *vma, unsigned long address);
- #else
-- #define expand_upwards(vma, address) (0)
-+ #define expand_upwards(vma, address) do { } while (0)
- #endif
-
- /* Look up the first VMA which satisfies addr < vm_end, NULL if none. */
-diff -Nur linux-3.12.38/include/linux/pagemap.h linux-rpi/include/linux/pagemap.h
---- linux-3.12.38/include/linux/pagemap.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/pagemap.h 2015-03-10 17:26:51.622216685 +0100
-@@ -256,7 +256,7 @@
- #define FGP_NOWAIT 0x00000020
-
- struct page *pagecache_get_page(struct address_space *mapping, pgoff_t offset,
-- int fgp_flags, gfp_t cache_gfp_mask);
-+ int fgp_flags, gfp_t cache_gfp_mask, gfp_t radix_gfp_mask);
-
- /**
- * find_get_page - find and get a page reference
-@@ -271,13 +271,13 @@
- static inline struct page *find_get_page(struct address_space *mapping,
- pgoff_t offset)
- {
-- return pagecache_get_page(mapping, offset, 0, 0);
-+ return pagecache_get_page(mapping, offset, 0, 0, 0);
- }
-
- static inline struct page *find_get_page_flags(struct address_space *mapping,
- pgoff_t offset, int fgp_flags)
- {
-- return pagecache_get_page(mapping, offset, fgp_flags, 0);
-+ return pagecache_get_page(mapping, offset, fgp_flags, 0, 0);
- }
-
- /**
-@@ -297,7 +297,7 @@
- static inline struct page *find_lock_page(struct address_space *mapping,
- pgoff_t offset)
- {
-- return pagecache_get_page(mapping, offset, FGP_LOCK, 0);
-+ return pagecache_get_page(mapping, offset, FGP_LOCK, 0, 0);
- }
-
- /**
-@@ -324,7 +324,7 @@
- {
- return pagecache_get_page(mapping, offset,
- FGP_LOCK|FGP_ACCESSED|FGP_CREAT,
-- gfp_mask);
-+ gfp_mask, gfp_mask & GFP_RECLAIM_MASK);
- }
-
- /**
-@@ -345,7 +345,8 @@
- {
- return pagecache_get_page(mapping, index,
- FGP_LOCK|FGP_CREAT|FGP_NOFS|FGP_NOWAIT,
-- mapping_gfp_mask(mapping));
-+ mapping_gfp_mask(mapping),
-+ GFP_NOFS);
- }
-
- struct page *find_get_entry(struct address_space *mapping, pgoff_t offset);
-diff -Nur linux-3.12.38/include/linux/platform_data/bcm2708.h linux-rpi/include/linux/platform_data/bcm2708.h
---- linux-3.12.38/include/linux/platform_data/bcm2708.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/include/linux/platform_data/bcm2708.h 2015-03-09 10:39:36.394893698 +0100
-@@ -0,0 +1,23 @@
-+/*
-+ * include/linux/platform_data/bcm2708.h
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * (C) 2014 Julian Scheel <julian@jusst.de>
-+ *
-+ */
-+#ifndef __BCM2708_H_
-+#define __BCM2708_H_
-+
-+typedef enum {
-+ BCM2708_PULL_OFF,
-+ BCM2708_PULL_UP,
-+ BCM2708_PULL_DOWN
-+} bcm2708_gpio_pull_t;
-+
-+extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
-+ bcm2708_gpio_pull_t value);
-+
-+#endif
-diff -Nur linux-3.12.38/include/linux/pstore_ram.h linux-rpi/include/linux/pstore_ram.h
---- linux-3.12.38/include/linux/pstore_ram.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/pstore_ram.h 2015-03-10 17:26:51.630216685 +0100
-@@ -53,8 +53,7 @@
- };
-
- struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, size_t size,
-- u32 sig, struct persistent_ram_ecc_info *ecc_info,
-- unsigned int memtype);
-+ u32 sig, struct persistent_ram_ecc_info *ecc_info);
- void persistent_ram_free(struct persistent_ram_zone *prz);
- void persistent_ram_zap(struct persistent_ram_zone *prz);
-
-@@ -77,7 +76,6 @@
- struct ramoops_platform_data {
- unsigned long mem_size;
- unsigned long mem_address;
-- unsigned int mem_type;
- unsigned long record_size;
- unsigned long console_size;
- unsigned long ftrace_size;
-diff -Nur linux-3.12.38/include/linux/time.h linux-rpi/include/linux/time.h
---- linux-3.12.38/include/linux/time.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/time.h 2015-03-10 17:26:51.638216685 +0100
-@@ -173,19 +173,6 @@
- extern void monotonic_to_bootbased(struct timespec *ts);
- extern void get_monotonic_boottime(struct timespec *ts);
-
--static inline bool timeval_valid(const struct timeval *tv)
--{
-- /* Dates before 1970 are bogus */
-- if (tv->tv_sec < 0)
-- return false;
--
-- /* Can't have more microseconds then a second */
-- if (tv->tv_usec < 0 || tv->tv_usec >= USEC_PER_SEC)
-- return false;
--
-- return true;
--}
--
- extern struct timespec timespec_trunc(struct timespec t, unsigned gran);
- extern int timekeeping_valid_for_hres(void);
- extern u64 timekeeping_max_deferment(void);
-diff -Nur linux-3.12.38/include/linux/vmstat.h linux-rpi/include/linux/vmstat.h
---- linux-3.12.38/include/linux/vmstat.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/linux/vmstat.h 2015-03-10 17:26:51.642216685 +0100
-@@ -239,7 +239,11 @@
- static inline void __dec_zone_state(struct zone *zone, enum zone_stat_item item)
- {
- atomic_long_dec(&zone->vm_stat[item]);
-+ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&zone->vm_stat[item]) < 0))
-+ atomic_long_set(&zone->vm_stat[item], 0);
- atomic_long_dec(&vm_stat[item]);
-+ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&vm_stat[item]) < 0))
-+ atomic_long_set(&vm_stat[item], 0);
- }
-
- static inline void __dec_zone_page_state(struct page *page,
-diff -Nur linux-3.12.38/include/net/ip.h linux-rpi/include/net/ip.h
---- linux-3.12.38/include/net/ip.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/net/ip.h 2015-03-10 17:26:51.650216685 +0100
-@@ -37,12 +37,11 @@
- struct ip_options opt; /* Compiled IP options */
- unsigned char flags;
-
--#define IPSKB_FORWARDED BIT(0)
--#define IPSKB_XFRM_TUNNEL_SIZE BIT(1)
--#define IPSKB_XFRM_TRANSFORMED BIT(2)
--#define IPSKB_FRAG_COMPLETE BIT(3)
--#define IPSKB_REROUTED BIT(4)
--#define IPSKB_DOREDIRECT BIT(5)
-+#define IPSKB_FORWARDED 1
-+#define IPSKB_XFRM_TUNNEL_SIZE 2
-+#define IPSKB_XFRM_TRANSFORMED 4
-+#define IPSKB_FRAG_COMPLETE 8
-+#define IPSKB_REROUTED 16
-
- u16 frag_max_size;
- };
-@@ -163,7 +162,7 @@
- return (arg->flags & IP_REPLY_ARG_NOSRCCHECK) ? FLOWI_FLAG_ANYSRC : 0;
- }
-
--void ip_send_unicast_reply(struct sock *sk, struct sk_buff *skb, __be32 daddr,
-+void ip_send_unicast_reply(struct net *net, struct sk_buff *skb, __be32 daddr,
- __be32 saddr, const struct ip_reply_arg *arg,
- unsigned int len);
-
-diff -Nur linux-3.12.38/include/net/netns/ipv4.h linux-rpi/include/net/netns/ipv4.h
---- linux-3.12.38/include/net/netns/ipv4.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/net/netns/ipv4.h 2015-03-10 17:26:51.654216685 +0100
-@@ -43,7 +43,6 @@
- struct inet_peer_base *peers;
- struct tcpm_hash_bucket *tcp_metrics_hash;
- unsigned int tcp_metrics_hash_log;
-- struct sock * __percpu *tcp_sk;
- struct netns_frags frags;
- #ifdef CONFIG_NETFILTER
- struct xt_table *iptable_filter;
-diff -Nur linux-3.12.38/include/sound/ak4113.h linux-rpi/include/sound/ak4113.h
---- linux-3.12.38/include/sound/ak4113.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/sound/ak4113.h 2015-03-10 17:26:51.662216685 +0100
-@@ -286,7 +286,7 @@
- ak4113_write_t *write;
- ak4113_read_t *read;
- void *private_data;
-- atomic_t wq_processing;
-+ unsigned int init:1;
- spinlock_t lock;
- unsigned char regmap[AK4113_WRITABLE_REGS];
- struct snd_kcontrol *kctls[AK4113_CONTROLS];
-diff -Nur linux-3.12.38/include/sound/ak4114.h linux-rpi/include/sound/ak4114.h
---- linux-3.12.38/include/sound/ak4114.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/sound/ak4114.h 2015-03-10 17:26:51.662216685 +0100
-@@ -168,7 +168,7 @@
- ak4114_write_t * write;
- ak4114_read_t * read;
- void * private_data;
-- atomic_t wq_processing;
-+ unsigned int init: 1;
- spinlock_t lock;
- unsigned char regmap[7];
- unsigned char txcsb[5];
-diff -Nur linux-3.12.38/include/sound/soc-dai.h linux-rpi/include/sound/soc-dai.h
---- linux-3.12.38/include/sound/soc-dai.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/sound/soc-dai.h 2015-03-10 17:26:51.666216685 +0100
-@@ -105,6 +105,8 @@
- int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
- int pll_id, int source, unsigned int freq_in, unsigned int freq_out);
-
-+int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio);
-+
- /* Digital Audio interface formatting */
- int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
-
-@@ -131,6 +133,7 @@
- int (*set_pll)(struct snd_soc_dai *dai, int pll_id, int source,
- unsigned int freq_in, unsigned int freq_out);
- int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div);
-+ int (*set_bclk_ratio)(struct snd_soc_dai *dai, unsigned int ratio);
-
- /*
- * DAI format configuration
-diff -Nur linux-3.12.38/include/uapi/linux/fb.h linux-rpi/include/uapi/linux/fb.h
---- linux-3.12.38/include/uapi/linux/fb.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/uapi/linux/fb.h 2015-03-09 10:39:36.978893695 +0100
-@@ -34,6 +34,11 @@
- #define FBIOPUT_MODEINFO 0x4617
- #define FBIOGET_DISPINFO 0x4618
- #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
-+/*
-+ * HACK: use 'z' in order not to clash with any other ioctl numbers which might
-+ * be concurrently added to the mainline kernel
-+ */
-+#define FBIOCOPYAREA _IOW('z', 0x21, struct fb_copyarea)
-
- #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
- #define FB_TYPE_PLANES 1 /* Non interleaved planes */
-diff -Nur linux-3.12.38/include/uapi/linux/in6.h linux-rpi/include/uapi/linux/in6.h
---- linux-3.12.38/include/uapi/linux/in6.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/uapi/linux/in6.h 2015-03-10 17:26:51.670216685 +0100
-@@ -156,7 +156,7 @@
- /*
- * IPV6 socket options
- */
--#if __UAPI_DEF_IPV6_OPTIONS
-+
- #define IPV6_ADDRFORM 1
- #define IPV6_2292PKTINFO 2
- #define IPV6_2292HOPOPTS 3
-@@ -195,7 +195,6 @@
-
- #define IPV6_IPSEC_POLICY 34
- #define IPV6_XFRM_POLICY 35
--#endif
-
- /*
- * Multicast:
-diff -Nur linux-3.12.38/include/uapi/linux/libc-compat.h linux-rpi/include/uapi/linux/libc-compat.h
---- linux-3.12.38/include/uapi/linux/libc-compat.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/include/uapi/linux/libc-compat.h 2015-03-10 17:26:51.674216685 +0100
-@@ -69,7 +69,6 @@
- #define __UAPI_DEF_SOCKADDR_IN6 0
- #define __UAPI_DEF_IPV6_MREQ 0
- #define __UAPI_DEF_IPPROTO_V6 0
--#define __UAPI_DEF_IPV6_OPTIONS 0
-
- #else
-
-@@ -83,7 +82,6 @@
- #define __UAPI_DEF_SOCKADDR_IN6 1
- #define __UAPI_DEF_IPV6_MREQ 1
- #define __UAPI_DEF_IPPROTO_V6 1
--#define __UAPI_DEF_IPV6_OPTIONS 1
-
- #endif /* _NETINET_IN_H */
-
-@@ -105,7 +103,6 @@
- #define __UAPI_DEF_SOCKADDR_IN6 1
- #define __UAPI_DEF_IPV6_MREQ 1
- #define __UAPI_DEF_IPPROTO_V6 1
--#define __UAPI_DEF_IPV6_OPTIONS 1
-
- /* Definitions for xattr.h */
- #define __UAPI_DEF_XATTR 1
-diff -Nur linux-3.12.38/ipc/compat.c linux-rpi/ipc/compat.c
---- linux-3.12.38/ipc/compat.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/ipc/compat.c 2015-03-10 17:26:51.682216685 +0100
-@@ -381,7 +381,7 @@
- uptr = compat_ptr(ipck.msgp);
- fifth = ipck.msgtyp;
- }
-- return do_msgrcv(first, uptr, second, (s32)fifth, third,
-+ return do_msgrcv(first, uptr, second, fifth, third,
- compat_do_msg_fill);
- }
- case MSGGET:
-@@ -430,9 +430,9 @@
- }
-
- COMPAT_SYSCALL_DEFINE5(msgrcv, int, msqid, compat_uptr_t, msgp,
-- compat_ssize_t, msgsz, compat_long_t, msgtyp, int, msgflg)
-+ compat_ssize_t, msgsz, long, msgtyp, int, msgflg)
- {
-- return do_msgrcv(msqid, compat_ptr(msgp), (ssize_t)msgsz, (long)msgtyp,
-+ return do_msgrcv(msqid, compat_ptr(msgp), (ssize_t)msgsz, msgtyp,
- msgflg, compat_do_msg_fill);
- }
-
-diff -Nur linux-3.12.38/ipc/sem.c linux-rpi/ipc/sem.c
---- linux-3.12.38/ipc/sem.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/ipc/sem.c 2015-03-10 17:26:51.682216685 +0100
-@@ -326,17 +326,10 @@
-
- /* Then check that the global lock is free */
- if (!spin_is_locked(&sma->sem_perm.lock)) {
-- /*
-- * The ipc object lock check must be visible on all
-- * cores before rechecking the complex count. Otherwise
-- * we can race with another thread that does:
-- * complex_count++;
-- * spin_unlock(sem_perm.lock);
-- */
-- smp_rmb();
-+ /* spin_is_locked() is not a memory barrier */
-+ smp_mb();
-
-- /*
-- * Now repeat the test of complex_count:
-+ /* Now repeat the test of complex_count:
- * It can't change anymore until we drop sem->lock.
- * Thus: if is now 0, then it will stay 0.
- */
-diff -Nur linux-3.12.38/kernel/cgroup.c linux-rpi/kernel/cgroup.c
---- linux-3.12.38/kernel/cgroup.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/cgroup.c 2015-03-10 17:26:51.686216685 +0100
-@@ -1012,7 +1012,7 @@
- parent = dentry->d_parent;
- spin_lock(&parent->d_lock);
- spin_lock_nested(&dentry->d_lock, DENTRY_D_LOCK_NESTED);
-- list_del_init(&dentry->d_child);
-+ list_del_init(&dentry->d_u.d_child);
- spin_unlock(&dentry->d_lock);
- spin_unlock(&parent->d_lock);
- remove_dir(dentry);
-@@ -5558,6 +5558,33 @@
- }
- __setup("cgroup_disable=", cgroup_disable);
-
-+static int __init cgroup_enable(char *str)
-+{
-+ struct cgroup_subsys *ss;
-+ char *token;
-+ int i;
-+
-+ while ((token = strsep(&str, ",")) != NULL) {
-+ if (!*token)
-+ continue;
-+
-+ /*
-+ * cgroup_disable, being at boot time, can't know about
-+ * module subsystems, so we don't worry about them.
-+ */
-+ for_each_builtin_subsys(ss, i) {
-+ if (!strcmp(token, ss->name)) {
-+ ss->disabled = 0;
-+ printk(KERN_INFO "Disabling %s control group"
-+ " subsystem\n", ss->name);
-+ break;
-+ }
-+ }
-+ }
-+ return 1;
-+}
-+__setup("cgroup_enable=", cgroup_enable);
-+
- /*
- * Functons for CSS ID.
- */
-diff -Nur linux-3.12.38/kernel/events/core.c linux-rpi/kernel/events/core.c
---- linux-3.12.38/kernel/events/core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/events/core.c 2015-03-10 17:26:51.690216685 +0100
-@@ -7167,11 +7167,11 @@
-
- if (move_group) {
- synchronize_rcu();
-- perf_install_in_context(ctx, group_leader, group_leader->cpu);
-+ perf_install_in_context(ctx, group_leader, event->cpu);
- get_ctx(ctx);
- list_for_each_entry(sibling, &group_leader->sibling_list,
- group_entry) {
-- perf_install_in_context(ctx, sibling, sibling->cpu);
-+ perf_install_in_context(ctx, sibling, event->cpu);
- get_ctx(ctx);
- }
- }
-diff -Nur linux-3.12.38/kernel/irq/internals.h linux-rpi/kernel/irq/internals.h
---- linux-3.12.38/kernel/irq/internals.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/irq/internals.h 2015-03-10 17:26:51.690216685 +0100
-@@ -74,14 +74,6 @@
- extern void mask_irq(struct irq_desc *desc);
- extern void unmask_irq(struct irq_desc *desc);
-
--#ifdef CONFIG_SPARSE_IRQ
--extern void irq_lock_sparse(void);
--extern void irq_unlock_sparse(void);
--#else
--static inline void irq_lock_sparse(void) { }
--static inline void irq_unlock_sparse(void) { }
--#endif
--
- extern void init_kstat_irqs(struct irq_desc *desc, int node, int nr);
-
- irqreturn_t handle_irq_event_percpu(struct irq_desc *desc, struct irqaction *action);
-diff -Nur linux-3.12.38/kernel/irq/irqdesc.c linux-rpi/kernel/irq/irqdesc.c
---- linux-3.12.38/kernel/irq/irqdesc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/irq/irqdesc.c 2015-03-10 17:26:51.694216685 +0100
-@@ -131,16 +131,6 @@
- static inline void free_masks(struct irq_desc *desc) { }
- #endif
-
--void irq_lock_sparse(void)
--{
-- mutex_lock(&sparse_irq_lock);
--}
--
--void irq_unlock_sparse(void)
--{
-- mutex_unlock(&sparse_irq_lock);
--}
--
- static struct irq_desc *alloc_desc(int irq, int node, struct module *owner)
- {
- struct irq_desc *desc;
-@@ -177,12 +167,6 @@
-
- unregister_irq_proc(irq, desc);
-
-- /*
-- * sparse_irq_lock protects also show_interrupts() and
-- * kstat_irq_usr(). Once we deleted the descriptor from the
-- * sparse tree we can free it. Access in proc will fail to
-- * lookup the descriptor.
-- */
- mutex_lock(&sparse_irq_lock);
- delete_irq_desc(irq);
- mutex_unlock(&sparse_irq_lock);
-@@ -505,15 +489,6 @@
- raw_spin_unlock_irqrestore(&desc->lock, flags);
- }
-
--/**
-- * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu
-- * @irq: The interrupt number
-- * @cpu: The cpu number
-- *
-- * Returns the sum of interrupt counts on @cpu since boot for
-- * @irq. The caller must ensure that the interrupt is not removed
-- * concurrently.
-- */
- unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
- {
- struct irq_desc *desc = irq_to_desc(irq);
-@@ -522,14 +497,6 @@
- *per_cpu_ptr(desc->kstat_irqs, cpu) : 0;
- }
-
--/**
-- * kstat_irqs - Get the statistics for an interrupt
-- * @irq: The interrupt number
-- *
-- * Returns the sum of interrupt counts on all cpus since boot for
-- * @irq. The caller must ensure that the interrupt is not removed
-- * concurrently.
-- */
- unsigned int kstat_irqs(unsigned int irq)
- {
- struct irq_desc *desc = irq_to_desc(irq);
-@@ -542,22 +509,3 @@
- sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
- return sum;
- }
--
--/**
-- * kstat_irqs_usr - Get the statistics for an interrupt
-- * @irq: The interrupt number
-- *
-- * Returns the sum of interrupt counts on all cpus since boot for
-- * @irq. Contrary to kstat_irqs() this can be called from any
-- * preemptible context. It's protected against concurrent removal of
-- * an interrupt descriptor when sparse irqs are enabled.
-- */
--unsigned int kstat_irqs_usr(unsigned int irq)
--{
-- int sum;
--
-- irq_lock_sparse();
-- sum = kstat_irqs(irq);
-- irq_unlock_sparse();
-- return sum;
--}
-diff -Nur linux-3.12.38/kernel/irq/proc.c linux-rpi/kernel/irq/proc.c
---- linux-3.12.38/kernel/irq/proc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/irq/proc.c 2015-03-10 17:26:51.694216685 +0100
-@@ -15,23 +15,6 @@
-
- #include "internals.h"
-
--/*
-- * Access rules:
-- *
-- * procfs protects read/write of /proc/irq/N/ files against a
-- * concurrent free of the interrupt descriptor. remove_proc_entry()
-- * immediately prevents new read/writes to happen and waits for
-- * already running read/write functions to complete.
-- *
-- * We remove the proc entries first and then delete the interrupt
-- * descriptor from the radix tree and free it. So it is guaranteed
-- * that irq_to_desc(N) is valid as long as the read/writes are
-- * permitted by procfs.
-- *
-- * The read from /proc/interrupts is a different problem because there
-- * is no protection. So the lookup and the access to irqdesc
-- * information must be protected by sparse_irq_lock.
-- */
- static struct proc_dir_entry *root_irq_dir;
-
- #ifdef CONFIG_SMP
-@@ -454,10 +437,9 @@
- seq_putc(p, '\n');
- }
-
-- irq_lock_sparse();
- desc = irq_to_desc(i);
- if (!desc)
-- goto outsparse;
-+ return 0;
-
- raw_spin_lock_irqsave(&desc->lock, flags);
- for_each_online_cpu(j)
-@@ -497,8 +479,6 @@
- seq_putc(p, '\n');
- out:
- raw_spin_unlock_irqrestore(&desc->lock, flags);
--outsparse:
-- irq_unlock_sparse();
- return 0;
- }
- #endif
-diff -Nur linux-3.12.38/kernel/smpboot.c linux-rpi/kernel/smpboot.c
---- linux-3.12.38/kernel/smpboot.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/smpboot.c 2015-03-10 17:26:51.706216685 +0100
-@@ -279,7 +279,6 @@
- unsigned int cpu;
- int ret = 0;
-
-- get_online_cpus();
- mutex_lock(&smpboot_threads_lock);
- for_each_online_cpu(cpu) {
- ret = __smpboot_create_thread(plug_thread, cpu);
-@@ -292,7 +291,6 @@
- list_add(&plug_thread->list, &hotplug_threads);
- out:
- mutex_unlock(&smpboot_threads_lock);
-- put_online_cpus();
- return ret;
- }
- EXPORT_SYMBOL_GPL(smpboot_register_percpu_thread);
-diff -Nur linux-3.12.38/kernel/time/ntp.c linux-rpi/kernel/time/ntp.c
---- linux-3.12.38/kernel/time/ntp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/time/ntp.c 2015-03-10 17:26:51.706216685 +0100
-@@ -631,13 +631,6 @@
- if ((txc->modes & ADJ_SETOFFSET) && (!capable(CAP_SYS_TIME)))
- return -EPERM;
-
-- if (txc->modes & ADJ_FREQUENCY) {
-- if (LONG_MIN / PPM_SCALE > txc->freq)
-- return -EINVAL;
-- if (LONG_MAX / PPM_SCALE < txc->freq)
-- return -EINVAL;
-- }
--
- return 0;
- }
-
-diff -Nur linux-3.12.38/kernel/time/tick-sched.c linux-rpi/kernel/time/tick-sched.c
---- linux-3.12.38/kernel/time/tick-sched.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/time/tick-sched.c 2015-03-10 17:26:51.710216685 +0100
-@@ -806,6 +806,7 @@
-
- local_irq_enable();
- }
-+EXPORT_SYMBOL_GPL(tick_nohz_idle_enter);
-
- /**
- * tick_nohz_irq_exit - update next tick event from interrupt exit
-@@ -933,6 +934,7 @@
-
- local_irq_enable();
- }
-+EXPORT_SYMBOL_GPL(tick_nohz_idle_exit);
-
- static int tick_nohz_reprogram(struct tick_sched *ts, ktime_t now)
- {
-diff -Nur linux-3.12.38/kernel/time.c linux-rpi/kernel/time.c
---- linux-3.12.38/kernel/time.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/time.c 2015-03-10 17:26:51.706216685 +0100
-@@ -195,10 +195,6 @@
- if (tv) {
- if (copy_from_user(&user_tv, tv, sizeof(*tv)))
- return -EFAULT;
--
-- if (!timeval_valid(&user_tv))
-- return -EINVAL;
--
- new_ts.tv_sec = user_tv.tv_sec;
- new_ts.tv_nsec = user_tv.tv_usec * NSEC_PER_USEC;
- }
-diff -Nur linux-3.12.38/kernel/trace/trace.c linux-rpi/kernel/trace/trace.c
---- linux-3.12.38/kernel/trace/trace.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/trace/trace.c 2015-03-10 17:26:51.710216685 +0100
-@@ -6063,7 +6063,7 @@
- int ret;
-
- /* Paranoid: Make sure the parent is the "instances" directory */
-- parent = hlist_entry(inode->i_dentry.first, struct dentry, d_u.d_alias);
-+ parent = hlist_entry(inode->i_dentry.first, struct dentry, d_alias);
- if (WARN_ON_ONCE(parent != trace_instance_dir))
- return -ENOENT;
-
-@@ -6090,7 +6090,7 @@
- int ret;
-
- /* Paranoid: Make sure the parent is the "instances" directory */
-- parent = hlist_entry(inode->i_dentry.first, struct dentry, d_u.d_alias);
-+ parent = hlist_entry(inode->i_dentry.first, struct dentry, d_alias);
- if (WARN_ON_ONCE(parent != trace_instance_dir))
- return -ENOENT;
-
-diff -Nur linux-3.12.38/kernel/trace/trace_events.c linux-rpi/kernel/trace/trace_events.c
---- linux-3.12.38/kernel/trace/trace_events.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/trace/trace_events.c 2015-03-10 17:26:51.710216685 +0100
-@@ -427,7 +427,7 @@
-
- if (dir) {
- spin_lock(&dir->d_lock); /* probably unneeded */
-- list_for_each_entry(child, &dir->d_subdirs, d_child) {
-+ list_for_each_entry(child, &dir->d_subdirs, d_u.d_child) {
- if (child->d_inode) /* probably unneeded */
- child->d_inode->i_private = NULL;
- }
-diff -Nur linux-3.12.38/kernel/workqueue.c linux-rpi/kernel/workqueue.c
---- linux-3.12.38/kernel/workqueue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/kernel/workqueue.c 2015-03-10 17:26:51.714216685 +0100
-@@ -1954,13 +1954,17 @@
- * spin_lock_irq(pool->lock) which may be released and regrabbed
- * multiple times. Does GFP_KERNEL allocations. Called only from
- * manager.
-+ *
-+ * Return:
-+ * %false if no action was taken and pool->lock stayed locked, %true
-+ * otherwise.
- */
--static void maybe_create_worker(struct worker_pool *pool)
-+static bool maybe_create_worker(struct worker_pool *pool)
- __releases(&pool->lock)
- __acquires(&pool->lock)
- {
- if (!need_to_create_worker(pool))
-- return;
-+ return false;
- restart:
- spin_unlock_irq(&pool->lock);
-
-@@ -1977,7 +1981,7 @@
- start_worker(worker);
- if (WARN_ON_ONCE(need_to_create_worker(pool)))
- goto restart;
-- return;
-+ return true;
- }
-
- if (!need_to_create_worker(pool))
-@@ -1994,7 +1998,7 @@
- spin_lock_irq(&pool->lock);
- if (need_to_create_worker(pool))
- goto restart;
-- return;
-+ return true;
- }
-
- /**
-@@ -2007,9 +2011,15 @@
- * LOCKING:
- * spin_lock_irq(pool->lock) which may be released and regrabbed
- * multiple times. Called only from manager.
-+ *
-+ * Return:
-+ * %false if no action was taken and pool->lock stayed locked, %true
-+ * otherwise.
- */
--static void maybe_destroy_workers(struct worker_pool *pool)
-+static bool maybe_destroy_workers(struct worker_pool *pool)
- {
-+ bool ret = false;
-+
- while (too_many_workers(pool)) {
- struct worker *worker;
- unsigned long expires;
-@@ -2023,7 +2033,10 @@
- }
-
- destroy_worker(worker);
-+ ret = true;
- }
-+
-+ return ret;
- }
-
- /**
-@@ -2043,14 +2056,16 @@
- * multiple times. Does GFP_KERNEL allocations.
- *
- * Return:
-- * %false if the pool doesn't need management and the caller can safely
-- * start processing works, %true if management function was performed and
-- * the conditions that the caller verified before calling the function may
-- * no longer be true.
-+ * %false if the pool don't need management and the caller can safely start
-+ * processing works, %true indicates that the function released pool->lock
-+ * and reacquired it to perform some management function and that the
-+ * conditions that the caller verified while holding the lock before
-+ * calling the function might no longer be true.
- */
- static bool manage_workers(struct worker *worker)
- {
- struct worker_pool *pool = worker->pool;
-+ bool ret = false;
-
- /*
- * Managership is governed by two mutexes - manager_arb and
-@@ -2074,7 +2089,7 @@
- * manager_mutex.
- */
- if (!mutex_trylock(&pool->manager_arb))
-- return false;
-+ return ret;
-
- /*
- * With manager arbitration won, manager_mutex would be free in
-@@ -2084,6 +2099,7 @@
- spin_unlock_irq(&pool->lock);
- mutex_lock(&pool->manager_mutex);
- spin_lock_irq(&pool->lock);
-+ ret = true;
- }
-
- pool->flags &= ~POOL_MANAGE_WORKERS;
-@@ -2092,12 +2108,12 @@
- * Destroy and then create so that may_start_working() is true
- * on return.
- */
-- maybe_destroy_workers(pool);
-- maybe_create_worker(pool);
-+ ret |= maybe_destroy_workers(pool);
-+ ret |= maybe_create_worker(pool);
-
- mutex_unlock(&pool->manager_mutex);
- mutex_unlock(&pool->manager_arb);
-- return true;
-+ return ret;
- }
-
- /**
-diff -Nur linux-3.12.38/lib/checksum.c linux-rpi/lib/checksum.c
---- linux-3.12.38/lib/checksum.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/lib/checksum.c 2015-03-10 17:26:51.718216685 +0100
-@@ -181,15 +181,6 @@
- EXPORT_SYMBOL(csum_partial_copy);
-
- #ifndef csum_tcpudp_nofold
--static inline u32 from64to32(u64 x)
--{
-- /* add up 32-bit and 32-bit for 32+c bit */
-- x = (x & 0xffffffff) + (x >> 32);
-- /* add up carry.. */
-- x = (x & 0xffffffff) + (x >> 32);
-- return (u32)x;
--}
--
- __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- unsigned short len,
- unsigned short proto,
-@@ -204,7 +195,8 @@
- #else
- s += (proto + len) << 8;
- #endif
-- return (__force __wsum)from64to32(s);
-+ s += (s >> 32);
-+ return (__force __wsum)s;
- }
- EXPORT_SYMBOL(csum_tcpudp_nofold);
- #endif
-diff -Nur linux-3.12.38/lib/decompress_bunzip2.c linux-rpi/lib/decompress_bunzip2.c
---- linux-3.12.38/lib/decompress_bunzip2.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/lib/decompress_bunzip2.c 2015-03-10 17:26:51.718216685 +0100
-@@ -184,7 +184,7 @@
- if (get_bits(bd, 1))
- return RETVAL_OBSOLETE_INPUT;
- origPtr = get_bits(bd, 24);
-- if (origPtr >= dbufSize)
-+ if (origPtr > dbufSize)
- return RETVAL_DATA_ERROR;
- /* mapping table: if some byte values are never used (encoding things
- like ascii text), the compression code removes the gaps to have fewer
-diff -Nur linux-3.12.38/mm/filemap.c linux-rpi/mm/filemap.c
---- linux-3.12.38/mm/filemap.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/mm/filemap.c 2015-03-10 17:26:51.722216685 +0100
-@@ -897,7 +897,7 @@
- * @mapping: the address_space to search
- * @offset: the page index
- * @fgp_flags: PCG flags
-- * @gfp_mask: gfp mask to use for the page cache data page allocation
-+ * @gfp_mask: gfp mask to use if a page is to be allocated
- *
- * Looks up the page cache slot at @mapping & @offset.
- *
-@@ -916,7 +916,7 @@
- * If there is a page cache page, it is returned with an increased refcount.
- */
- struct page *pagecache_get_page(struct address_space *mapping, pgoff_t offset,
-- int fgp_flags, gfp_t gfp_mask)
-+ int fgp_flags, gfp_t cache_gfp_mask, gfp_t radix_gfp_mask)
- {
- struct page *page;
-
-@@ -953,11 +953,13 @@
- if (!page && (fgp_flags & FGP_CREAT)) {
- int err;
- if ((fgp_flags & FGP_WRITE) && mapping_cap_account_dirty(mapping))
-- gfp_mask |= __GFP_WRITE;
-- if (fgp_flags & FGP_NOFS)
-- gfp_mask &= ~__GFP_FS;
-+ cache_gfp_mask |= __GFP_WRITE;
-+ if (fgp_flags & FGP_NOFS) {
-+ cache_gfp_mask &= ~__GFP_FS;
-+ radix_gfp_mask &= ~__GFP_FS;
-+ }
-
-- page = __page_cache_alloc(gfp_mask);
-+ page = __page_cache_alloc(cache_gfp_mask);
- if (!page)
- return NULL;
-
-@@ -968,8 +970,7 @@
- if (fgp_flags & FGP_ACCESSED)
- init_page_accessed(page);
-
-- err = add_to_page_cache_lru(page, mapping, offset,
-- gfp_mask & GFP_RECLAIM_MASK);
-+ err = add_to_page_cache_lru(page, mapping, offset, radix_gfp_mask);
- if (unlikely(err)) {
- page_cache_release(page);
- page = NULL;
-@@ -2461,7 +2462,8 @@
- fgp_flags |= FGP_NOFS;
-
- page = pagecache_get_page(mapping, index, fgp_flags,
-- mapping_gfp_mask(mapping));
-+ mapping_gfp_mask(mapping),
-+ GFP_KERNEL);
- if (page)
- wait_for_stable_page(page);
-
-diff -Nur linux-3.12.38/mm/memcontrol.c linux-rpi/mm/memcontrol.c
---- linux-3.12.38/mm/memcontrol.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/mm/memcontrol.c 2015-03-10 17:26:51.726216685 +0100
-@@ -7066,6 +7066,7 @@
- .base_cftypes = mem_cgroup_files,
- .early_init = 0,
- .use_id = 1,
-+ .disabled = 1,
- };
-
- #ifdef CONFIG_MEMCG_SWAP
-diff -Nur linux-3.12.38/mm/memory.c linux-rpi/mm/memory.c
---- linux-3.12.38/mm/memory.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/mm/memory.c 2015-03-10 17:26:51.730216685 +0100
-@@ -3194,7 +3194,7 @@
- if (prev && prev->vm_end == address)
- return prev->vm_flags & VM_GROWSDOWN ? 0 : -ENOMEM;
-
-- return expand_downwards(vma, address - PAGE_SIZE);
-+ expand_downwards(vma, address - PAGE_SIZE);
- }
- if ((vma->vm_flags & VM_GROWSUP) && address + PAGE_SIZE == vma->vm_end) {
- struct vm_area_struct *next = vma->vm_next;
-@@ -3203,7 +3203,7 @@
- if (next && next->vm_start == address + PAGE_SIZE)
- return next->vm_flags & VM_GROWSUP ? 0 : -ENOMEM;
-
-- return expand_upwards(vma, address + PAGE_SIZE);
-+ expand_upwards(vma, address + PAGE_SIZE);
- }
- return 0;
- }
-diff -Nur linux-3.12.38/mm/mmap.c linux-rpi/mm/mmap.c
---- linux-3.12.38/mm/mmap.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/mm/mmap.c 2015-03-10 17:26:51.730216685 +0100
-@@ -2049,17 +2049,14 @@
- {
- struct mm_struct *mm = vma->vm_mm;
- struct rlimit *rlim = current->signal->rlim;
-- unsigned long new_start, actual_size;
-+ unsigned long new_start;
-
- /* address space limit tests */
- if (!may_expand_vm(mm, grow))
- return -ENOMEM;
-
- /* Stack limit test */
-- actual_size = size;
-- if (size && (vma->vm_flags & (VM_GROWSUP | VM_GROWSDOWN)))
-- actual_size -= PAGE_SIZE;
-- if (actual_size > ACCESS_ONCE(rlim[RLIMIT_STACK].rlim_cur))
-+ if (size > ACCESS_ONCE(rlim[RLIMIT_STACK].rlim_cur))
- return -ENOMEM;
-
- /* mlock limit tests */
-diff -Nur linux-3.12.38/mm/pagewalk.c linux-rpi/mm/pagewalk.c
---- linux-3.12.38/mm/pagewalk.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/mm/pagewalk.c 2015-03-10 17:26:51.734216685 +0100
-@@ -199,10 +199,7 @@
- */
- if ((vma->vm_start <= addr) &&
- (vma->vm_flags & VM_PFNMAP)) {
-- if (walk->pte_hole)
-- err = walk->pte_hole(addr, next, walk);
-- if (err)
-- break;
-+ next = vma->vm_end;
- pgd = pgd_offset(walk->mm, next);
- continue;
- }
-diff -Nur linux-3.12.38/mm/vmscan.c linux-rpi/mm/vmscan.c
---- linux-3.12.38/mm/vmscan.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/mm/vmscan.c 2015-03-10 17:26:51.738216685 +0100
-@@ -2868,20 +2868,18 @@
- return false;
-
- /*
-- * The throttled processes are normally woken up in balance_pgdat() as
-- * soon as pfmemalloc_watermark_ok() is true. But there is a potential
-- * race between when kswapd checks the watermarks and a process gets
-- * throttled. There is also a potential race if processes get
-- * throttled, kswapd wakes, a large process exits thereby balancing the
-- * zones, which causes kswapd to exit balance_pgdat() before reaching
-- * the wake up checks. If kswapd is going to sleep, no process should
-- * be sleeping on pfmemalloc_wait, so wake them now if necessary. If
-- * the wake up is premature, processes will wake kswapd and get
-- * throttled again. The difference from wake ups in balance_pgdat() is
-- * that here we are under prepare_to_wait().
-+ * There is a potential race between when kswapd checks its watermarks
-+ * and a process gets throttled. There is also a potential race if
-+ * processes get throttled, kswapd wakes, a large process exits therby
-+ * balancing the zones that causes kswapd to miss a wakeup. If kswapd
-+ * is going to sleep, no process should be sleeping on pfmemalloc_wait
-+ * so wake them now if necessary. If necessary, processes will wake
-+ * kswapd and get throttled again
- */
-- if (waitqueue_active(&pgdat->pfmemalloc_wait))
-- wake_up_all(&pgdat->pfmemalloc_wait);
-+ if (waitqueue_active(&pgdat->pfmemalloc_wait)) {
-+ wake_up(&pgdat->pfmemalloc_wait);
-+ return false;
-+ }
-
- return pgdat_balanced(pgdat, order, classzone_idx);
- }
-diff -Nur linux-3.12.38/net/core/dev.c linux-rpi/net/core/dev.c
---- linux-3.12.38/net/core/dev.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/core/dev.c 2015-03-10 17:26:51.758216685 +0100
-@@ -1698,7 +1698,6 @@
-
- skb_scrub_packet(skb, true);
- skb->protocol = eth_type_trans(skb, dev);
-- skb_postpull_rcsum(skb, eth_hdr(skb), ETH_HLEN);
-
- return netif_rx(skb);
- }
-@@ -2505,14 +2504,11 @@
- if (skb_shinfo(skb)->gso_segs > dev->gso_max_segs)
- features &= ~NETIF_F_GSO_MASK;
-
-- if (!vlan_tx_tag_present(skb)) {
-- if (unlikely(protocol == htons(ETH_P_8021Q) ||
-- protocol == htons(ETH_P_8021AD))) {
-- struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
-- protocol = veh->h_vlan_encapsulated_proto;
-- } else {
-- return harmonize_features(skb, dev, features);
-- }
-+ if (protocol == htons(ETH_P_8021Q) || protocol == htons(ETH_P_8021AD)) {
-+ struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
-+ protocol = veh->h_vlan_encapsulated_proto;
-+ } else if (!vlan_tx_tag_present(skb)) {
-+ return harmonize_features(skb, dev, features);
- }
-
- features = netdev_intersect_features(features,
-@@ -6405,20 +6401,10 @@
- oldsd->output_queue = NULL;
- oldsd->output_queue_tailp = &oldsd->output_queue;
- }
-- /* Append NAPI poll list from offline CPU, with one exception :
-- * process_backlog() must be called by cpu owning percpu backlog.
-- * We properly handle process_queue & input_pkt_queue later.
-- */
-- while (!list_empty(&oldsd->poll_list)) {
-- struct napi_struct *napi = list_first_entry(&oldsd->poll_list,
-- struct napi_struct,
-- poll_list);
--
-- list_del_init(&napi->poll_list);
-- if (napi->poll == process_backlog)
-- napi->state = 0;
-- else
-- ____napi_schedule(sd, napi);
-+ /* Append NAPI poll list from offline CPU. */
-+ if (!list_empty(&oldsd->poll_list)) {
-+ list_splice_init(&oldsd->poll_list, &sd->poll_list);
-+ raise_softirq_irqoff(NET_RX_SOFTIRQ);
- }
-
- raise_softirq_irqoff(NET_TX_SOFTIRQ);
-@@ -6429,7 +6415,7 @@
- netif_rx(skb);
- input_queue_head_incr(oldsd);
- }
-- while ((skb = skb_dequeue(&oldsd->input_pkt_queue))) {
-+ while ((skb = __skb_dequeue(&oldsd->input_pkt_queue))) {
- netif_rx(skb);
- input_queue_head_incr(oldsd);
- }
-diff -Nur linux-3.12.38/net/core/rtnetlink.c linux-rpi/net/core/rtnetlink.c
---- linux-3.12.38/net/core/rtnetlink.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/core/rtnetlink.c 2015-03-10 17:26:51.762216685 +0100
-@@ -2542,16 +2542,12 @@
- goto errout;
- }
-
-- if (!skb->len)
-- goto errout;
--
- rtnl_notify(skb, net, 0, RTNLGRP_LINK, NULL, GFP_ATOMIC);
- return 0;
- errout:
- WARN_ON(err == -EMSGSIZE);
- kfree_skb(skb);
-- if (err)
-- rtnl_set_sk_err(net, RTNLGRP_LINK, err);
-+ rtnl_set_sk_err(net, RTNLGRP_LINK, err);
- return err;
- }
-
-diff -Nur linux-3.12.38/net/core/skbuff.c linux-rpi/net/core/skbuff.c
---- linux-3.12.38/net/core/skbuff.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/core/skbuff.c 2015-03-10 17:26:51.762216685 +0100
-@@ -3523,7 +3523,6 @@
- skb->local_df = 0;
- skb_dst_drop(skb);
- skb->mark = 0;
-- skb_init_secmark(skb);
- secpath_reset(skb);
- nf_reset(skb);
- nf_reset_trace(skb);
-diff -Nur linux-3.12.38/net/ipv4/ip_forward.c linux-rpi/net/ipv4/ip_forward.c
---- linux-3.12.38/net/ipv4/ip_forward.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/ip_forward.c 2015-03-10 17:26:51.770216685 +0100
-@@ -175,8 +175,7 @@
- * We now generate an ICMP HOST REDIRECT giving the route
- * we calculated.
- */
-- if (IPCB(skb)->flags & IPSKB_DOREDIRECT && !opt->srr &&
-- !skb_sec_path(skb))
-+ if (rt->rt_flags&RTCF_DOREDIRECT && !opt->srr && !skb_sec_path(skb))
- ip_rt_send_redirect(skb);
-
- skb->priority = rt_tos2priority(iph->tos);
-diff -Nur linux-3.12.38/net/ipv4/ip_output.c linux-rpi/net/ipv4/ip_output.c
---- linux-3.12.38/net/ipv4/ip_output.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/ip_output.c 2015-03-10 17:26:51.770216685 +0100
-@@ -1451,8 +1451,23 @@
- /*
- * Generic function to send a packet as reply to another packet.
- * Used to send some TCP resets/acks so far.
-+ *
-+ * Use a fake percpu inet socket to avoid false sharing and contention.
- */
--void ip_send_unicast_reply(struct sock *sk, struct sk_buff *skb, __be32 daddr,
-+static DEFINE_PER_CPU(struct inet_sock, unicast_sock) = {
-+ .sk = {
-+ .__sk_common = {
-+ .skc_refcnt = ATOMIC_INIT(1),
-+ },
-+ .sk_wmem_alloc = ATOMIC_INIT(1),
-+ .sk_allocation = GFP_ATOMIC,
-+ .sk_flags = (1UL << SOCK_USE_WRITE_QUEUE),
-+ },
-+ .pmtudisc = IP_PMTUDISC_WANT,
-+ .uc_ttl = -1,
-+};
-+
-+void ip_send_unicast_reply(struct net *net, struct sk_buff *skb, __be32 daddr,
- __be32 saddr, const struct ip_reply_arg *arg,
- unsigned int len)
- {
-@@ -1460,8 +1475,9 @@
- struct ipcm_cookie ipc;
- struct flowi4 fl4;
- struct rtable *rt = skb_rtable(skb);
-- struct net *net = sock_net(sk);
- struct sk_buff *nskb;
-+ struct sock *sk;
-+ struct inet_sock *inet;
- int err;
-
- if (ip_options_echo(&replyopts.opt.opt, skb))
-@@ -1489,11 +1505,15 @@
- if (IS_ERR(rt))
- return;
-
-- inet_sk(sk)->tos = arg->tos;
-+ inet = &get_cpu_var(unicast_sock);
-
-+ inet->tos = arg->tos;
-+ sk = &inet->sk;
- sk->sk_priority = skb->priority;
- sk->sk_protocol = ip_hdr(skb)->protocol;
- sk->sk_bound_dev_if = arg->bound_dev_if;
-+ sock_net_set(sk, net);
-+ __skb_queue_head_init(&sk->sk_write_queue);
- sk->sk_sndbuf = sysctl_wmem_default;
- err = ip_append_data(sk, &fl4, ip_reply_glue_bits, arg->iov->iov_base,
- len, 0, &ipc, &rt, MSG_DONTWAIT);
-@@ -1509,10 +1529,13 @@
- arg->csumoffset) = csum_fold(csum_add(nskb->csum,
- arg->csum));
- nskb->ip_summed = CHECKSUM_NONE;
-+ skb_orphan(nskb);
- skb_set_queue_mapping(nskb, skb_get_queue_mapping(skb));
- ip_push_pending_frames(sk, &fl4);
- }
- out:
-+ put_cpu_var(unicast_sock);
-+
- ip_rt_put(rt);
- }
-
-diff -Nur linux-3.12.38/net/ipv4/ip_sockglue.c linux-rpi/net/ipv4/ip_sockglue.c
---- linux-3.12.38/net/ipv4/ip_sockglue.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/ip_sockglue.c 2015-03-10 17:26:51.770216685 +0100
-@@ -410,11 +410,15 @@
-
- memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err));
- sin = &errhdr.offender;
-- memset(sin, 0, sizeof(*sin));
-+ sin->sin_family = AF_UNSPEC;
- if (serr->ee.ee_origin == SO_EE_ORIGIN_ICMP) {
-+ struct inet_sock *inet = inet_sk(sk);
-+
- sin->sin_family = AF_INET;
- sin->sin_addr.s_addr = ip_hdr(skb)->saddr;
-- if (inet_sk(sk)->cmsg_flags)
-+ sin->sin_port = 0;
-+ memset(&sin->sin_zero, 0, sizeof(sin->sin_zero));
-+ if (inet->cmsg_flags)
- ip_cmsg_recv(msg, skb);
- }
-
-diff -Nur linux-3.12.38/net/ipv4/ping.c linux-rpi/net/ipv4/ping.c
---- linux-3.12.38/net/ipv4/ping.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/ping.c 2015-03-10 17:26:51.774216685 +0100
-@@ -959,11 +959,8 @@
-
- sk = ping_lookup(net, skb, ntohs(icmph->un.echo.id));
- if (sk != NULL) {
-- struct sk_buff *skb2 = skb_clone(skb, GFP_ATOMIC);
--
- pr_debug("rcv on socket %p\n", sk);
-- if (skb2)
-- ping_queue_rcv_skb(sk, skb2);
-+ ping_queue_rcv_skb(sk, skb_get(skb));
- sock_put(sk);
- return;
- }
-diff -Nur linux-3.12.38/net/ipv4/route.c linux-rpi/net/ipv4/route.c
---- linux-3.12.38/net/ipv4/route.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/route.c 2015-03-10 17:26:51.774216685 +0100
-@@ -1561,10 +1561,11 @@
-
- do_cache = res->fi && !itag;
- if (out_dev == in_dev && err && IN_DEV_TX_REDIRECTS(out_dev) &&
-- skb->protocol == htons(ETH_P_IP) &&
- (IN_DEV_SHARED_MEDIA(out_dev) ||
-- inet_addr_onlink(out_dev, saddr, FIB_RES_GW(*res))))
-- IPCB(skb)->flags |= IPSKB_DOREDIRECT;
-+ inet_addr_onlink(out_dev, saddr, FIB_RES_GW(*res)))) {
-+ flags |= RTCF_DOREDIRECT;
-+ do_cache = false;
-+ }
-
- if (skb->protocol != htons(ETH_P_IP)) {
- /* Not IP (i.e. ARP). Do not create route, if it is
-@@ -2306,8 +2307,6 @@
- r->rtm_flags = (rt->rt_flags & ~0xFFFF) | RTM_F_CLONED;
- if (rt->rt_flags & RTCF_NOTIFY)
- r->rtm_flags |= RTM_F_NOTIFY;
-- if (IPCB(skb)->flags & IPSKB_DOREDIRECT)
-- r->rtm_flags |= RTCF_DOREDIRECT;
-
- if (nla_put_be32(skb, RTA_DST, dst))
- goto nla_put_failure;
-diff -Nur linux-3.12.38/net/ipv4/tcp_ipv4.c linux-rpi/net/ipv4/tcp_ipv4.c
---- linux-3.12.38/net/ipv4/tcp_ipv4.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/tcp_ipv4.c 2015-03-10 17:26:51.778216684 +0100
-@@ -690,8 +690,7 @@
-
- net = dev_net(skb_dst(skb)->dev);
- arg.tos = ip_hdr(skb)->tos;
-- ip_send_unicast_reply(*this_cpu_ptr(net->ipv4.tcp_sk),
-- skb, ip_hdr(skb)->saddr,
-+ ip_send_unicast_reply(net, skb, ip_hdr(skb)->saddr,
- ip_hdr(skb)->daddr, &arg, arg.iov[0].iov_len);
-
- TCP_INC_STATS_BH(net, TCP_MIB_OUTSEGS);
-@@ -774,8 +773,7 @@
- if (oif)
- arg.bound_dev_if = oif;
- arg.tos = tos;
-- ip_send_unicast_reply(*this_cpu_ptr(net->ipv4.tcp_sk),
-- skb, ip_hdr(skb)->saddr,
-+ ip_send_unicast_reply(net, skb, ip_hdr(skb)->saddr,
- ip_hdr(skb)->daddr, &arg, arg.iov[0].iov_len);
-
- TCP_INC_STATS_BH(net, TCP_MIB_OUTSEGS);
-@@ -2830,39 +2828,14 @@
- };
- EXPORT_SYMBOL(tcp_prot);
-
--static void __net_exit tcp_sk_exit(struct net *net)
--{
-- int cpu;
--
-- for_each_possible_cpu(cpu)
-- inet_ctl_sock_destroy(*per_cpu_ptr(net->ipv4.tcp_sk, cpu));
-- free_percpu(net->ipv4.tcp_sk);
--}
--
- static int __net_init tcp_sk_init(struct net *net)
- {
-- int res, cpu;
--
-- net->ipv4.tcp_sk = alloc_percpu(struct sock *);
-- if (!net->ipv4.tcp_sk)
-- return -ENOMEM;
--
-- for_each_possible_cpu(cpu) {
-- struct sock *sk;
--
-- res = inet_ctl_sock_create(&sk, PF_INET, SOCK_RAW,
-- IPPROTO_TCP, net);
-- if (res)
-- goto fail;
-- *per_cpu_ptr(net->ipv4.tcp_sk, cpu) = sk;
-- }
- net->ipv4.sysctl_tcp_ecn = 2;
- return 0;
-+}
-
--fail:
-- tcp_sk_exit(net);
--
-- return res;
-+static void __net_exit tcp_sk_exit(struct net *net)
-+{
- }
-
- static void __net_exit tcp_sk_exit_batch(struct list_head *net_exit_list)
-diff -Nur linux-3.12.38/net/ipv4/tcp_output.c linux-rpi/net/ipv4/tcp_output.c
---- linux-3.12.38/net/ipv4/tcp_output.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/tcp_output.c 2015-03-10 17:26:51.778216684 +0100
-@@ -1871,7 +1871,7 @@
- if (unlikely(!tcp_snd_wnd_test(tp, skb, mss_now)))
- break;
-
-- if (tso_segs == 1 || !sk->sk_gso_max_segs) {
-+ if (tso_segs == 1) {
- if (unlikely(!tcp_nagle_test(tp, skb, mss_now,
- (tcp_skb_is_last(sk, skb) ?
- nonagle : TCP_NAGLE_PUSH))))
-@@ -1908,7 +1908,7 @@
- }
-
- limit = mss_now;
-- if (tso_segs > 1 && sk->sk_gso_max_segs && !tcp_urg_mode(tp))
-+ if (tso_segs > 1 && !tcp_urg_mode(tp))
- limit = tcp_mss_split_point(sk, skb, mss_now,
- min_t(unsigned int,
- cwnd_quota,
-diff -Nur linux-3.12.38/net/ipv4/udp_diag.c linux-rpi/net/ipv4/udp_diag.c
---- linux-3.12.38/net/ipv4/udp_diag.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv4/udp_diag.c 2015-03-10 17:26:51.782216684 +0100
-@@ -99,13 +99,11 @@
- s_slot = cb->args[0];
- num = s_num = cb->args[1];
-
-- for (slot = s_slot; slot <= table->mask; s_num = 0, slot++) {
-+ for (slot = s_slot; slot <= table->mask; num = s_num = 0, slot++) {
- struct sock *sk;
- struct hlist_nulls_node *node;
- struct udp_hslot *hslot = &table->hash[slot];
-
-- num = 0;
--
- if (hlist_nulls_empty(&hslot->head))
- continue;
-
-diff -Nur linux-3.12.38/net/ipv6/datagram.c linux-rpi/net/ipv6/datagram.c
---- linux-3.12.38/net/ipv6/datagram.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv6/datagram.c 2015-03-10 17:26:51.782216684 +0100
-@@ -374,10 +374,11 @@
-
- memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err));
- sin = &errhdr.offender;
-- memset(sin, 0, sizeof(*sin));
--
-+ sin->sin6_family = AF_UNSPEC;
- if (serr->ee.ee_origin != SO_EE_ORIGIN_LOCAL) {
- sin->sin6_family = AF_INET6;
-+ sin->sin6_flowinfo = 0;
-+ sin->sin6_port = 0;
- if (skb->protocol == htons(ETH_P_IPV6)) {
- sin->sin6_addr = ipv6_hdr(skb)->saddr;
- if (np->rxopt.all)
-@@ -386,9 +387,12 @@
- ipv6_iface_scope_id(&sin->sin6_addr,
- IP6CB(skb)->iif);
- } else {
-+ struct inet_sock *inet = inet_sk(sk);
-+
- ipv6_addr_set_v4mapped(ip_hdr(skb)->saddr,
- &sin->sin6_addr);
-- if (inet_sk(sk)->cmsg_flags)
-+ sin->sin6_scope_id = 0;
-+ if (inet->cmsg_flags)
- ip_cmsg_recv(msg, skb);
- }
- }
-diff -Nur linux-3.12.38/net/ipv6/ip6_fib.c linux-rpi/net/ipv6/ip6_fib.c
---- linux-3.12.38/net/ipv6/ip6_fib.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv6/ip6_fib.c 2015-03-10 17:26:51.782216684 +0100
-@@ -638,29 +638,6 @@
- RTF_GATEWAY;
- }
-
--static void fib6_purge_rt(struct rt6_info *rt, struct fib6_node *fn,
-- struct net *net)
--{
-- if (atomic_read(&rt->rt6i_ref) != 1) {
-- /* This route is used as dummy address holder in some split
-- * nodes. It is not leaked, but it still holds other resources,
-- * which must be released in time. So, scan ascendant nodes
-- * and replace dummy references to this route with references
-- * to still alive ones.
-- */
-- while (fn) {
-- if (!(fn->fn_flags & RTN_RTINFO) && fn->leaf == rt) {
-- fn->leaf = fib6_find_prefix(net, fn);
-- atomic_inc(&fn->leaf->rt6i_ref);
-- rt6_release(rt);
-- }
-- fn = fn->parent;
-- }
-- /* No more references are possible at this point. */
-- BUG_ON(atomic_read(&rt->rt6i_ref) != 1);
-- }
--}
--
- /*
- * Insert routing information in a node.
- */
-@@ -798,12 +775,11 @@
- rt->dst.rt6_next = iter->dst.rt6_next;
- atomic_inc(&rt->rt6i_ref);
- inet6_rt_notify(RTM_NEWROUTE, rt, info);
-+ rt6_release(iter);
- if (!(fn->fn_flags & RTN_RTINFO)) {
- info->nl_net->ipv6.rt6_stats->fib_route_nodes++;
- fn->fn_flags |= RTN_RTINFO;
- }
-- fib6_purge_rt(iter, fn, info->nl_net);
-- rt6_release(iter);
- }
-
- return 0;
-@@ -1308,7 +1284,24 @@
- fn = fib6_repair_tree(net, fn);
- }
-
-- fib6_purge_rt(rt, fn, net);
-+ if (atomic_read(&rt->rt6i_ref) != 1) {
-+ /* This route is used as dummy address holder in some split
-+ * nodes. It is not leaked, but it still holds other resources,
-+ * which must be released in time. So, scan ascendant nodes
-+ * and replace dummy references to this route with references
-+ * to still alive ones.
-+ */
-+ while (fn) {
-+ if (!(fn->fn_flags & RTN_RTINFO) && fn->leaf == rt) {
-+ fn->leaf = fib6_find_prefix(net, fn);
-+ atomic_inc(&fn->leaf->rt6i_ref);
-+ rt6_release(rt);
-+ }
-+ fn = fn->parent;
-+ }
-+ /* No more references are possible at this point. */
-+ BUG_ON(atomic_read(&rt->rt6i_ref) != 1);
-+ }
-
- inet6_rt_notify(RTM_DELROUTE, rt, info);
- rt6_release(rt);
-diff -Nur linux-3.12.38/net/ipv6/route.c linux-rpi/net/ipv6/route.c
---- linux-3.12.38/net/ipv6/route.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/ipv6/route.c 2015-03-10 17:26:51.786216684 +0100
-@@ -1144,9 +1144,12 @@
- struct net *net = dev_net(dst->dev);
-
- rt6->rt6i_flags |= RTF_MODIFIED;
-- if (mtu < IPV6_MIN_MTU)
-+ if (mtu < IPV6_MIN_MTU) {
-+ u32 features = dst_metric(dst, RTAX_FEATURES);
- mtu = IPV6_MIN_MTU;
--
-+ features |= RTAX_FEATURE_ALLFRAG;
-+ dst_metric_set(dst, RTAX_FEATURES, features);
-+ }
- dst_metric_set(dst, RTAX_MTU, mtu);
- rt6_update_expires(rt6, net->ipv6.sysctl.ip6_rt_mtu_expires);
- }
-diff -Nur linux-3.12.38/net/mac80211/rx.c linux-rpi/net/mac80211/rx.c
---- linux-3.12.38/net/mac80211/rx.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/mac80211/rx.c 2015-03-10 17:26:51.802216684 +0100
-@@ -261,7 +261,7 @@
- else if (rate && rate->flags & IEEE80211_RATE_ERP_G)
- channel_flags |= IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ;
- else if (rate)
-- channel_flags |= IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ;
-+ channel_flags |= IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ;
- else
- channel_flags |= IEEE80211_CHAN_2GHZ;
- put_unaligned_le16(channel_flags, pos);
-diff -Nur linux-3.12.38/net/netfilter/ipset/ip_set_core.c linux-rpi/net/netfilter/ipset/ip_set_core.c
---- linux-3.12.38/net/netfilter/ipset/ip_set_core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/netfilter/ipset/ip_set_core.c 2015-03-10 17:26:51.806216684 +0100
-@@ -1753,12 +1753,6 @@
- if (*op < IP_SET_OP_VERSION) {
- /* Check the version at the beginning of operations */
- struct ip_set_req_version *req_version = data;
--
-- if (*len < sizeof(struct ip_set_req_version)) {
-- ret = -EINVAL;
-- goto done;
-- }
--
- if (req_version->version != IPSET_PROTOCOL) {
- ret = -EPROTO;
- goto done;
-diff -Nur linux-3.12.38/net/netfilter/ipvs/ip_vs_ftp.c linux-rpi/net/netfilter/ipvs/ip_vs_ftp.c
---- linux-3.12.38/net/netfilter/ipvs/ip_vs_ftp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/netfilter/ipvs/ip_vs_ftp.c 2015-03-10 17:26:51.806216684 +0100
-@@ -183,8 +183,6 @@
- struct nf_conn *ct;
- struct net *net;
-
-- *diff = 0;
--
- #ifdef CONFIG_IP_VS_IPV6
- /* This application helper doesn't work with IPv6 yet,
- * so turn this into a no-op for IPv6 packets
-@@ -193,6 +191,8 @@
- return 1;
- #endif
-
-+ *diff = 0;
-+
- /* Only useful for established sessions */
- if (cp->state != IP_VS_TCP_S_ESTABLISHED)
- return 1;
-@@ -321,9 +321,6 @@
- struct ip_vs_conn *n_cp;
- struct net *net;
-
-- /* no diff required for incoming packets */
-- *diff = 0;
--
- #ifdef CONFIG_IP_VS_IPV6
- /* This application helper doesn't work with IPv6 yet,
- * so turn this into a no-op for IPv6 packets
-@@ -332,6 +329,9 @@
- return 1;
- #endif
-
-+ /* no diff required for incoming packets */
-+ *diff = 0;
-+
- /* Only useful for established sessions */
- if (cp->state != IP_VS_TCP_S_ESTABLISHED)
- return 1;
-diff -Nur linux-3.12.38/net/netfilter/ipvs/ip_vs_nfct.c linux-rpi/net/netfilter/ipvs/ip_vs_nfct.c
---- linux-3.12.38/net/netfilter/ipvs/ip_vs_nfct.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/netfilter/ipvs/ip_vs_nfct.c 2015-03-10 17:26:51.806216684 +0100
-@@ -63,7 +63,6 @@
- #include <net/ip_vs.h>
- #include <net/netfilter/nf_conntrack_core.h>
- #include <net/netfilter/nf_conntrack_expect.h>
--#include <net/netfilter/nf_conntrack_seqadj.h>
- #include <net/netfilter/nf_conntrack_helper.h>
- #include <net/netfilter/nf_conntrack_zones.h>
-
-@@ -98,11 +97,6 @@
- if (CTINFO2DIR(ctinfo) != IP_CT_DIR_ORIGINAL)
- return;
-
-- /* Applications may adjust TCP seqs */
-- if (cp->app && nf_ct_protonum(ct) == IPPROTO_TCP &&
-- !nfct_seqadj(ct) && !nfct_seqadj_ext_add(ct))
-- return;
--
- /*
- * The connection is not yet in the hashtable, so we update it.
- * CIP->VIP will remain the same, so leave the tuple in
-diff -Nur linux-3.12.38/net/netlink/af_netlink.c linux-rpi/net/netlink/af_netlink.c
---- linux-3.12.38/net/netlink/af_netlink.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/netlink/af_netlink.c 2015-03-10 17:26:51.814216684 +0100
-@@ -502,14 +502,14 @@
- return err;
- }
-
--static void netlink_frame_flush_dcache(const struct nl_mmap_hdr *hdr, unsigned int nm_len)
-+static void netlink_frame_flush_dcache(const struct nl_mmap_hdr *hdr)
- {
- #if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE == 1
- struct page *p_start, *p_end;
-
- /* First page is flushed through netlink_{get,set}_status */
- p_start = pgvec_to_page(hdr + PAGE_SIZE);
-- p_end = pgvec_to_page((void *)hdr + NL_MMAP_HDRLEN + nm_len - 1);
-+ p_end = pgvec_to_page((void *)hdr + NL_MMAP_HDRLEN + hdr->nm_len - 1);
- while (p_start <= p_end) {
- flush_dcache_page(p_start);
- p_start++;
-@@ -527,9 +527,9 @@
- static void netlink_set_status(struct nl_mmap_hdr *hdr,
- enum nl_mmap_status status)
- {
-- smp_mb();
- hdr->nm_status = status;
- flush_dcache_page(pgvec_to_page(hdr));
-+ smp_wmb();
- }
-
- static struct nl_mmap_hdr *
-@@ -691,16 +691,24 @@
- struct nl_mmap_hdr *hdr;
- struct sk_buff *skb;
- unsigned int maxlen;
-+ bool excl = true;
- int err = 0, len = 0;
-
-+ /* Netlink messages are validated by the receiver before processing.
-+ * In order to avoid userspace changing the contents of the message
-+ * after validation, the socket and the ring may only be used by a
-+ * single process, otherwise we fall back to copying.
-+ */
-+ if (atomic_long_read(&sk->sk_socket->file->f_count) > 1 ||
-+ atomic_read(&nlk->mapped) > 1)
-+ excl = false;
-+
- mutex_lock(&nlk->pg_vec_lock);
-
- ring = &nlk->tx_ring;
- maxlen = ring->frame_size - NL_MMAP_HDRLEN;
-
- do {
-- unsigned int nm_len;
--
- hdr = netlink_current_frame(ring, NL_MMAP_STATUS_VALID);
- if (hdr == NULL) {
- if (!(msg->msg_flags & MSG_DONTWAIT) &&
-@@ -708,23 +716,35 @@
- schedule();
- continue;
- }
--
-- nm_len = ACCESS_ONCE(hdr->nm_len);
-- if (nm_len > maxlen) {
-+ if (hdr->nm_len > maxlen) {
- err = -EINVAL;
- goto out;
- }
-
-- netlink_frame_flush_dcache(hdr, nm_len);
-+ netlink_frame_flush_dcache(hdr);
-
-- skb = alloc_skb(nm_len, GFP_KERNEL);
-- if (skb == NULL) {
-- err = -ENOBUFS;
-- goto out;
-+ if (likely(dst_portid == 0 && dst_group == 0 && excl)) {
-+ skb = alloc_skb_head(GFP_KERNEL);
-+ if (skb == NULL) {
-+ err = -ENOBUFS;
-+ goto out;
-+ }
-+ sock_hold(sk);
-+ netlink_ring_setup_skb(skb, sk, ring, hdr);
-+ NETLINK_CB(skb).flags |= NETLINK_SKB_TX;
-+ __skb_put(skb, hdr->nm_len);
-+ netlink_set_status(hdr, NL_MMAP_STATUS_RESERVED);
-+ atomic_inc(&ring->pending);
-+ } else {
-+ skb = alloc_skb(hdr->nm_len, GFP_KERNEL);
-+ if (skb == NULL) {
-+ err = -ENOBUFS;
-+ goto out;
-+ }
-+ __skb_put(skb, hdr->nm_len);
-+ memcpy(skb->data, (void *)hdr + NL_MMAP_HDRLEN, hdr->nm_len);
-+ netlink_set_status(hdr, NL_MMAP_STATUS_UNUSED);
- }
-- __skb_put(skb, nm_len);
-- memcpy(skb->data, (void *)hdr + NL_MMAP_HDRLEN, nm_len);
-- netlink_set_status(hdr, NL_MMAP_STATUS_UNUSED);
-
- netlink_increment_head(ring);
-
-@@ -770,7 +790,7 @@
- hdr->nm_pid = NETLINK_CB(skb).creds.pid;
- hdr->nm_uid = from_kuid(sk_user_ns(sk), NETLINK_CB(skb).creds.uid);
- hdr->nm_gid = from_kgid(sk_user_ns(sk), NETLINK_CB(skb).creds.gid);
-- netlink_frame_flush_dcache(hdr, hdr->nm_len);
-+ netlink_frame_flush_dcache(hdr);
- netlink_set_status(hdr, NL_MMAP_STATUS_VALID);
-
- NETLINK_CB(skb).flags |= NETLINK_SKB_DELIVERED;
-diff -Nur linux-3.12.38/net/sctp/associola.c linux-rpi/net/sctp/associola.c
---- linux-3.12.38/net/sctp/associola.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/sctp/associola.c 2015-03-10 17:26:51.830216684 +0100
-@@ -1282,6 +1282,7 @@
- asoc->peer.peer_hmacs = new->peer.peer_hmacs;
- new->peer.peer_hmacs = NULL;
-
-+ sctp_auth_key_put(asoc->asoc_shared_key);
- sctp_auth_asoc_init_active_key(asoc, GFP_ATOMIC);
- }
-
-diff -Nur linux-3.12.38/net/sctp/sm_make_chunk.c linux-rpi/net/sctp/sm_make_chunk.c
---- linux-3.12.38/net/sctp/sm_make_chunk.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/sctp/sm_make_chunk.c 2015-03-10 17:26:51.834216684 +0100
-@@ -2621,7 +2621,7 @@
-
- addr_param = param.v + sizeof(sctp_addip_param_t);
-
-- af = sctp_get_af_specific(param_type2af(addr_param->p.type));
-+ af = sctp_get_af_specific(param_type2af(param.p->type));
- if (af == NULL)
- break;
-
-diff -Nur linux-3.12.38/net/socket.c linux-rpi/net/socket.c
---- linux-3.12.38/net/socket.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/socket.c 2015-03-10 17:26:51.834216684 +0100
-@@ -885,6 +885,9 @@
- static struct sock_iocb *alloc_sock_iocb(struct kiocb *iocb,
- struct sock_iocb *siocb)
- {
-+ if (!is_sync_kiocb(iocb))
-+ BUG();
-+
- siocb->kiocb = iocb;
- iocb->private = siocb;
- return siocb;
-diff -Nur linux-3.12.38/net/sunrpc/clnt.c linux-rpi/net/sunrpc/clnt.c
---- linux-3.12.38/net/sunrpc/clnt.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/sunrpc/clnt.c 2015-03-10 17:26:51.838216684 +0100
-@@ -1637,12 +1637,10 @@
- return;
- case -ECONNREFUSED: /* connection problems */
- case -ECONNRESET:
-- case -ECONNABORTED:
- case -ENOTCONN:
- case -EHOSTDOWN:
- case -EHOSTUNREACH:
- case -ENETUNREACH:
-- case -ENOBUFS:
- case -EPIPE:
- dprintk("RPC: %5u remote rpcbind unreachable: %d\n",
- task->tk_pid, task->tk_status);
-@@ -1701,25 +1699,20 @@
- dprint_status(task);
-
- trace_rpc_connect_status(task, status);
-- task->tk_status = 0;
- switch (status) {
-+ /* if soft mounted, test if we've timed out */
-+ case -ETIMEDOUT:
-+ task->tk_action = call_timeout;
-+ return;
- case -ECONNREFUSED:
- case -ECONNRESET:
-- case -ECONNABORTED:
- case -ENETUNREACH:
-- case -EHOSTUNREACH:
-- case -ENOBUFS:
-- case -EPIPE:
- if (RPC_IS_SOFTCONN(task))
- break;
- /* retry with existing socket, after a delay */
-- rpc_delay(task, 3*HZ);
-- case -EAGAIN:
-- /* Check for timeouts before looping back to call_bind */
-- case -ETIMEDOUT:
-- task->tk_action = call_timeout;
-- return;
- case 0:
-+ case -EAGAIN:
-+ task->tk_status = 0;
- clnt->cl_stats->netreconn++;
- task->tk_action = call_transmit;
- return;
-@@ -1811,9 +1804,7 @@
- break;
- }
- case -ECONNRESET:
-- case -ECONNABORTED:
- case -ENOTCONN:
-- case -ENOBUFS:
- case -EPIPE:
- rpc_task_force_reencode(task);
- }
-@@ -1922,11 +1913,9 @@
- xprt_conditional_disconnect(req->rq_xprt,
- req->rq_connect_cookie);
- break;
-- case -ECONNREFUSED:
- case -ECONNRESET:
-- case -ECONNABORTED:
-+ case -ECONNREFUSED:
- rpc_force_rebind(clnt);
-- case -ENOBUFS:
- rpc_delay(task, 3*HZ);
- case -EPIPE:
- case -ENOTCONN:
-diff -Nur linux-3.12.38/net/sunrpc/sched.c linux-rpi/net/sunrpc/sched.c
---- linux-3.12.38/net/sunrpc/sched.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/sunrpc/sched.c 2015-03-10 17:26:51.838216684 +0100
-@@ -831,8 +831,7 @@
- * @size: requested byte size
- *
- * To prevent rpciod from hanging, this allocator never sleeps,
-- * returning NULL and suppressing warning if the request cannot be serviced
-- * immediately.
-+ * returning NULL if the request cannot be serviced immediately.
- * The caller can arrange to sleep in a way that is safe for rpciod.
- *
- * Most requests are 'small' (under 2KiB) and can be serviced from a
-@@ -845,7 +844,7 @@
- void *rpc_malloc(struct rpc_task *task, size_t size)
- {
- struct rpc_buffer *buf;
-- gfp_t gfp = GFP_NOWAIT | __GFP_NOWARN;
-+ gfp_t gfp = GFP_NOWAIT;
-
- if (RPC_IS_SWAPPER(task))
- gfp |= __GFP_MEMALLOC;
-diff -Nur linux-3.12.38/net/sunrpc/xprt.c linux-rpi/net/sunrpc/xprt.c
---- linux-3.12.38/net/sunrpc/xprt.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/sunrpc/xprt.c 2015-03-10 17:26:51.838216684 +0100
-@@ -745,12 +745,6 @@
- }
-
- switch (task->tk_status) {
-- case -ECONNREFUSED:
-- case -ECONNRESET:
-- case -ECONNABORTED:
-- case -ENETUNREACH:
-- case -EHOSTUNREACH:
-- case -EPIPE:
- case -EAGAIN:
- dprintk("RPC: %5u xprt_connect_status: retrying\n", task->tk_pid);
- break;
-diff -Nur linux-3.12.38/net/sunrpc/xprtsock.c linux-rpi/net/sunrpc/xprtsock.c
---- linux-3.12.38/net/sunrpc/xprtsock.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/sunrpc/xprtsock.c 2015-03-10 17:26:51.842216684 +0100
-@@ -588,7 +588,6 @@
- }
-
- switch (status) {
-- case -ENOBUFS:
- case -EAGAIN:
- status = xs_nospace(task);
- break;
-@@ -656,7 +655,6 @@
- dprintk("RPC: sendmsg returned unrecognized error %d\n",
- -status);
- case -ENETUNREACH:
-- case -ENOBUFS:
- case -EPIPE:
- case -ECONNREFUSED:
- /* When the server has died, an ICMP port unreachable message
-@@ -754,7 +752,6 @@
- status = -ENOTCONN;
- /* Should we call xs_close() here? */
- break;
-- case -ENOBUFS:
- case -EAGAIN:
- status = xs_nospace(task);
- break;
-@@ -1931,7 +1928,6 @@
- dprintk("RPC: xprt %p connected to %s\n",
- xprt, xprt->address_strings[RPC_DISPLAY_ADDR]);
- xprt_set_connected(xprt);
-- case -ENOBUFS:
- break;
- case -ENOENT:
- dprintk("RPC: xprt %p: socket %s does not exist\n",
-@@ -2255,7 +2251,6 @@
- case -ECONNREFUSED:
- case -ECONNRESET:
- case -ENETUNREACH:
-- case -ENOBUFS:
- /* retry with existing socket, after a delay */
- goto out;
- }
-diff -Nur linux-3.12.38/net/wireless/nl80211.c linux-rpi/net/wireless/nl80211.c
---- linux-3.12.38/net/wireless/nl80211.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/wireless/nl80211.c 2015-03-10 17:26:51.850216684 +0100
-@@ -2659,9 +2659,6 @@
- if (!rdev->ops->get_key)
- return -EOPNOTSUPP;
-
-- if (!pairwise && mac_addr && !(rdev->wiphy.flags & WIPHY_FLAG_IBSS_RSN))
-- return -ENOENT;
--
- msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
- if (!msg)
- return -ENOMEM;
-@@ -2681,6 +2678,10 @@
- nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, mac_addr))
- goto nla_put_failure;
-
-+ if (pairwise && mac_addr &&
-+ !(rdev->wiphy.flags & WIPHY_FLAG_IBSS_RSN))
-+ return -ENOENT;
-+
- err = rdev_get_key(rdev, dev, key_idx, pairwise, mac_addr, &cookie,
- get_key_callback);
-
-@@ -2851,7 +2852,7 @@
- wdev_lock(dev->ieee80211_ptr);
- err = nl80211_key_allowed(dev->ieee80211_ptr);
-
-- if (key.type == NL80211_KEYTYPE_GROUP && mac_addr &&
-+ if (key.type == NL80211_KEYTYPE_PAIRWISE && mac_addr &&
- !(rdev->wiphy.flags & WIPHY_FLAG_IBSS_RSN))
- err = -ENOENT;
-
-diff -Nur linux-3.12.38/net/wireless/reg.c linux-rpi/net/wireless/reg.c
---- linux-3.12.38/net/wireless/reg.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/net/wireless/reg.c 2015-03-10 17:26:51.850216684 +0100
-@@ -1432,7 +1432,7 @@
- __regulatory_hint(struct wiphy *wiphy,
- struct regulatory_request *pending_request)
- {
-- const struct ieee80211_regdomain *regd, *tmp;
-+ const struct ieee80211_regdomain *regd;
- bool intersect = false;
- enum reg_request_treatment treatment;
- struct regulatory_request *lr;
-@@ -1448,9 +1448,7 @@
- kfree(pending_request);
- return PTR_ERR(regd);
- }
-- tmp = get_wiphy_regdom(wiphy);
- rcu_assign_pointer(wiphy->regd, regd);
-- rcu_free_regdom(tmp);
- }
- intersect = true;
- break;
-@@ -1470,9 +1468,7 @@
- return REG_REQ_IGNORE;
- }
- treatment = REG_REQ_ALREADY_SET;
-- tmp = get_wiphy_regdom(wiphy);
- rcu_assign_pointer(wiphy->regd, regd);
-- rcu_free_regdom(tmp);
- goto new_request;
- }
- kfree(pending_request);
-diff -Nur linux-3.12.38/scripts/kconfig/menu.c linux-rpi/scripts/kconfig/menu.c
---- linux-3.12.38/scripts/kconfig/menu.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/scripts/kconfig/menu.c 2015-03-10 17:26:51.858216684 +0100
-@@ -544,7 +544,7 @@
- {
- int i, j;
- struct menu *submenu[8], *menu, *location = NULL;
-- struct jump_key *jump = NULL;
-+ struct jump_key *jump;
-
- str_printf(r, _("Prompt: %s\n"), _(prop->text));
- menu = prop->menu->parent;
-@@ -582,8 +582,8 @@
- str_printf(r, _(" Location:\n"));
- for (j = 4; --i >= 0; j += 2) {
- menu = submenu[i];
-- if (jump && menu == location)
-- jump->offset = strlen(r->s);
-+ if (head && location && menu == location)
-+ jump->offset = r->len - 1;
- str_printf(r, "%*c-> %s", j, ' ',
- _(menu_get_prompt(menu)));
- if (menu->sym) {
-diff -Nur linux-3.12.38/scripts/kernel-doc linux-rpi/scripts/kernel-doc
---- linux-3.12.38/scripts/kernel-doc 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/scripts/kernel-doc 2015-03-10 17:26:51.862216684 +0100
-@@ -1750,7 +1750,7 @@
- # strip kmemcheck_bitfield_{begin,end}.*;
- $members =~ s/kmemcheck_bitfield_.*?;//gos;
- # strip attributes
-- $members =~ s/__aligned\s*\([^;]*\)//gos;
-+ $members =~ s/__aligned\s*\(.+\)//gos;
-
- create_parameterlist($members, ';', $file);
- check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested);
-diff -Nur linux-3.12.38/scripts/recordmcount.pl linux-rpi/scripts/recordmcount.pl
---- linux-3.12.38/scripts/recordmcount.pl 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/scripts/recordmcount.pl 2015-03-10 17:26:51.862216684 +0100
-@@ -262,6 +262,7 @@
- # force flags for this arch
- $ld .= " -m shlelf_linux";
- $objcopy .= " -O elf32-sh-linux";
-+ $cc .= " -m32";
-
- } elsif ($arch eq "powerpc") {
- $local_regex = "^[0-9a-fA-F]+\\s+t\\s+(\\.?\\S+)";
-diff -Nur linux-3.12.38/security/keys/gc.c linux-rpi/security/keys/gc.c
---- linux-3.12.38/security/keys/gc.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/security/keys/gc.c 2015-03-10 17:26:51.866216684 +0100
-@@ -201,12 +201,12 @@
- if (test_bit(KEY_FLAG_INSTANTIATED, &key->flags))
- atomic_dec(&key->user->nikeys);
-
-+ key_user_put(key->user);
-+
- /* now throw away the key memory */
- if (key->type->destroy)
- key->type->destroy(key);
-
-- key_user_put(key->user);
--
- kfree(key->description);
-
- #ifdef KEY_DEBUGGING
-diff -Nur linux-3.12.38/security/selinux/selinuxfs.c linux-rpi/security/selinux/selinuxfs.c
---- linux-3.12.38/security/selinux/selinuxfs.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/security/selinux/selinuxfs.c 2015-03-10 17:26:51.870216684 +0100
-@@ -1190,7 +1190,7 @@
- spin_lock(&de->d_lock);
- node = de->d_subdirs.next;
- while (node != &de->d_subdirs) {
-- struct dentry *d = list_entry(node, struct dentry, d_child);
-+ struct dentry *d = list_entry(node, struct dentry, d_u.d_child);
-
- spin_lock_nested(&d->d_lock, DENTRY_D_LOCK_NESTED);
- list_del_init(node);
-@@ -1664,12 +1664,12 @@
-
- list_for_each(class_node, &class_dir->d_subdirs) {
- struct dentry *class_subdir = list_entry(class_node,
-- struct dentry, d_child);
-+ struct dentry, d_u.d_child);
- struct list_head *class_subdir_node;
-
- list_for_each(class_subdir_node, &class_subdir->d_subdirs) {
- struct dentry *d = list_entry(class_subdir_node,
-- struct dentry, d_child);
-+ struct dentry, d_u.d_child);
-
- if (d->d_inode)
- if (d->d_inode->i_mode & S_IFDIR)
-diff -Nur linux-3.12.38/security/selinux/ss/policydb.c linux-rpi/security/selinux/ss/policydb.c
---- linux-3.12.38/security/selinux/ss/policydb.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/security/selinux/ss/policydb.c 2015-03-10 17:26:51.870216684 +0100
-@@ -3215,8 +3215,9 @@
-
- static int range_write(struct policydb *p, void *fp)
- {
-+ size_t nel;
- __le32 buf[1];
-- int rc, nel;
-+ int rc;
- struct policy_data pd;
-
- pd.p = p;
-diff -Nur linux-3.12.38/sound/arm/bcm2835.c linux-rpi/sound/arm/bcm2835.c
---- linux-3.12.38/sound/arm/bcm2835.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/arm/bcm2835.c 2015-03-10 17:26:51.874216684 +0100
-@@ -0,0 +1,420 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/platform_device.h>
-+
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+
-+#include "bcm2835.h"
-+
-+/* module parameters (see "Module Parameters") */
-+/* SNDRV_CARDS: maximum number of cards supported by this module */
-+static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 };
-+static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL };
-+static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 };
-+
-+/* HACKY global pointers needed for successive probes to work : ssp
-+ * But compared against the changes we will have to do in VC audio_ipc code
-+ * to export 8 audio_ipc devices as a single IPC device and then monitor all
-+ * four devices in a thread, this gets things done quickly and should be easier
-+ * to debug if we run into issues
-+ */
-+
-+static struct snd_card *g_card = NULL;
-+static bcm2835_chip_t *g_chip = NULL;
-+
-+static int snd_bcm2835_free(bcm2835_chip_t * chip)
-+{
-+ kfree(chip);
-+ return 0;
-+}
-+
-+/* component-destructor
-+ * (see "Management of Cards and Components")
-+ */
-+static int snd_bcm2835_dev_free(struct snd_device *device)
-+{
-+ return snd_bcm2835_free(device->device_data);
-+}
-+
-+/* chip-specific constructor
-+ * (see "Management of Cards and Components")
-+ */
-+static int snd_bcm2835_create(struct snd_card *card,
-+ struct platform_device *pdev,
-+ bcm2835_chip_t ** rchip)
-+{
-+ bcm2835_chip_t *chip;
-+ int err;
-+ static struct snd_device_ops ops = {
-+ .dev_free = snd_bcm2835_dev_free,
-+ };
-+
-+ *rchip = NULL;
-+
-+ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
-+ if (chip == NULL)
-+ return -ENOMEM;
-+
-+ chip->card = card;
-+
-+ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
-+ if (err < 0) {
-+ snd_bcm2835_free(chip);
-+ return err;
-+ }
-+
-+ *rchip = chip;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_alsa_probe(struct platform_device *pdev)
-+{
-+ static int dev;
-+ bcm2835_chip_t *chip;
-+ struct snd_card *card;
-+ int err;
-+
-+ if (dev >= MAX_SUBSTREAMS)
-+ return -ENODEV;
-+
-+ if (!enable[dev]) {
-+ dev++;
-+ return -ENOENT;
-+ }
-+
-+ if (dev > 0)
-+ goto add_register_map;
-+
-+ err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &g_card);
-+ if (err < 0)
-+ goto out;
-+
-+ snd_card_set_dev(g_card, &pdev->dev);
-+ strcpy(g_card->driver, "bcm2835");
-+ strcpy(g_card->shortname, "bcm2835 ALSA");
-+ sprintf(g_card->longname, "%s", g_card->shortname);
-+
-+ err = snd_bcm2835_create(g_card, pdev, &chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create bcm2835 chip\n");
-+ goto out_bcm2835_create;
-+ }
-+
-+ g_chip = chip;
-+ err = snd_bcm2835_new_pcm(chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create new BCM2835 pcm device\n");
-+ goto out_bcm2835_new_pcm;
-+ }
-+
-+ err = snd_bcm2835_new_spdif_pcm(chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create new BCM2835 spdif pcm device\n");
-+ goto out_bcm2835_new_spdif;
-+ }
-+
-+ err = snd_bcm2835_new_ctl(chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create new BCM2835 ctl\n");
-+ goto out_bcm2835_new_ctl;
-+ }
-+
-+add_register_map:
-+ card = g_card;
-+ chip = g_chip;
-+
-+ BUG_ON(!(card && chip));
-+
-+ chip->avail_substreams |= (1 << dev);
-+ chip->pdev[dev] = pdev;
-+
-+ if (dev == 0) {
-+ err = snd_card_register(card);
-+ if (err < 0) {
-+ dev_err(&pdev->dev,
-+ "Failed to register bcm2835 ALSA card \n");
-+ goto out_card_register;
-+ }
-+ platform_set_drvdata(pdev, card);
-+ audio_info("bcm2835 ALSA card created!\n");
-+ } else {
-+ audio_info("bcm2835 ALSA chip created!\n");
-+ platform_set_drvdata(pdev, (void *)dev);
-+ }
-+
-+ dev++;
-+
-+ return 0;
-+
-+out_card_register:
-+out_bcm2835_new_ctl:
-+out_bcm2835_new_spdif:
-+out_bcm2835_new_pcm:
-+out_bcm2835_create:
-+ BUG_ON(!g_card);
-+ if (snd_card_free(g_card))
-+ dev_err(&pdev->dev, "Failed to free Registered alsa card\n");
-+ g_card = NULL;
-+out:
-+ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */
-+ dev_err(&pdev->dev, "BCM2835 ALSA Probe failed !!\n");
-+ return err;
-+}
-+
-+static int snd_bcm2835_alsa_remove(struct platform_device *pdev)
-+{
-+ uint32_t idx;
-+ void *drv_data;
-+
-+ drv_data = platform_get_drvdata(pdev);
-+
-+ if (drv_data == (void *)g_card) {
-+ /* This is the card device */
-+ snd_card_free((struct snd_card *)drv_data);
-+ g_card = NULL;
-+ g_chip = NULL;
-+ } else {
-+ idx = (uint32_t) drv_data;
-+ if (g_card != NULL) {
-+ BUG_ON(!g_chip);
-+ /* We pass chip device numbers in audio ipc devices
-+ * other than the one we registered our card with
-+ */
-+ idx = (uint32_t) drv_data;
-+ BUG_ON(!idx || idx > MAX_SUBSTREAMS);
-+ g_chip->avail_substreams &= ~(1 << idx);
-+ /* There should be atleast one substream registered
-+ * after we are done here, as it wil be removed when
-+ * the *remove* is called for the card device
-+ */
-+ BUG_ON(!g_chip->avail_substreams);
-+ }
-+ }
-+
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static int snd_bcm2835_alsa_suspend(struct platform_device *pdev,
-+ pm_message_t state)
-+{
-+ return 0;
-+}
-+
-+static int snd_bcm2835_alsa_resume(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+
-+#endif
-+
-+static struct platform_driver bcm2835_alsa0_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD0",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa1_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD1",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa2_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD2",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa3_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD3",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa4_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD4",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa5_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD5",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa6_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD6",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa7_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD7",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int bcm2835_alsa_device_init(void)
-+{
-+ int err;
-+ err = platform_driver_register(&bcm2835_alsa0_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto out;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa1_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_0;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa2_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_1;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa3_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_2;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa4_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_3;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa5_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_4;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa6_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_5;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa7_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_6;
-+ }
-+
-+ return 0;
-+
-+unregister_6:
-+ platform_driver_unregister(&bcm2835_alsa6_driver);
-+unregister_5:
-+ platform_driver_unregister(&bcm2835_alsa5_driver);
-+unregister_4:
-+ platform_driver_unregister(&bcm2835_alsa4_driver);
-+unregister_3:
-+ platform_driver_unregister(&bcm2835_alsa3_driver);
-+unregister_2:
-+ platform_driver_unregister(&bcm2835_alsa2_driver);
-+unregister_1:
-+ platform_driver_unregister(&bcm2835_alsa1_driver);
-+unregister_0:
-+ platform_driver_unregister(&bcm2835_alsa0_driver);
-+out:
-+ return err;
-+}
-+
-+static void bcm2835_alsa_device_exit(void)
-+{
-+ platform_driver_unregister(&bcm2835_alsa0_driver);
-+ platform_driver_unregister(&bcm2835_alsa1_driver);
-+ platform_driver_unregister(&bcm2835_alsa2_driver);
-+ platform_driver_unregister(&bcm2835_alsa3_driver);
-+ platform_driver_unregister(&bcm2835_alsa4_driver);
-+ platform_driver_unregister(&bcm2835_alsa5_driver);
-+ platform_driver_unregister(&bcm2835_alsa6_driver);
-+ platform_driver_unregister(&bcm2835_alsa7_driver);
-+}
-+
-+late_initcall(bcm2835_alsa_device_init);
-+module_exit(bcm2835_alsa_device_exit);
-+
-+MODULE_AUTHOR("Dom Cobley");
-+MODULE_DESCRIPTION("Alsa driver for BCM2835 chip");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:bcm2835_alsa");
-diff -Nur linux-3.12.38/sound/arm/bcm2835-ctl.c linux-rpi/sound/arm/bcm2835-ctl.c
---- linux-3.12.38/sound/arm/bcm2835-ctl.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/arm/bcm2835-ctl.c 2015-03-09 10:39:38.302893687 +0100
-@@ -0,0 +1,323 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/platform_device.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/jiffies.h>
-+#include <linux/slab.h>
-+#include <linux/time.h>
-+#include <linux/wait.h>
-+#include <linux/delay.h>
-+#include <linux/moduleparam.h>
-+#include <linux/sched.h>
-+
-+#include <sound/core.h>
-+#include <sound/control.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/rawmidi.h>
-+#include <sound/initval.h>
-+#include <sound/tlv.h>
-+#include <sound/asoundef.h>
-+
-+#include "bcm2835.h"
-+
-+/* volume maximum and minimum in terms of 0.01dB */
-+#define CTRL_VOL_MAX 400
-+#define CTRL_VOL_MIN -10239 /* originally -10240 */
-+
-+
-+static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ audio_info(" ... IN\n");
-+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) {
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = CTRL_VOL_MIN;
-+ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) {
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = 1;
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) {
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = AUDIO_DEST_MAX-1;
-+ }
-+ audio_info(" ... OUT\n");
-+ return 0;
-+}
-+
-+/* toggles mute on or off depending on the value of nmute, and returns
-+ * 1 if the mute value was changed, otherwise 0
-+ */
-+static int toggle_mute(struct bcm2835_chip *chip, int nmute)
-+{
-+ /* if settings are ok, just return 0 */
-+ if(chip->mute == nmute)
-+ return 0;
-+
-+ /* if the sound is muted then we need to unmute */
-+ if(chip->mute == CTRL_VOL_MUTE)
-+ {
-+ chip->volume = chip->old_volume; /* copy the old volume back */
-+ audio_info("Unmuting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume);
-+ }
-+ else /* otherwise we mute */
-+ {
-+ chip->old_volume = chip->volume;
-+ chip->volume = 26214; /* set volume to minimum level AKA mute */
-+ audio_info("Muting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume);
-+ }
-+
-+ chip->mute = nmute;
-+ return 1;
-+}
-+
-+static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+
-+ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK));
-+
-+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME)
-+ ucontrol->value.integer.value[0] = chip2alsa(chip->volume);
-+ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE)
-+ ucontrol->value.integer.value[0] = chip->mute;
-+ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE)
-+ ucontrol->value.integer.value[0] = chip->dest;
-+
-+ return 0;
-+}
-+
-+static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ int changed = 0;
-+
-+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) {
-+ audio_info("Volume change attempted.. volume = %d new_volume = %d\n", chip->volume, (int)ucontrol->value.integer.value[0]);
-+ if (chip->mute == CTRL_VOL_MUTE) {
-+ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */
-+ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */
-+ }
-+ if (changed
-+ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) {
-+
-+ chip->volume = alsa2chip(ucontrol->value.integer.value[0]);
-+ changed = 1;
-+ }
-+
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) {
-+ /* Now implemented */
-+ audio_info(" Mute attempted\n");
-+ changed = toggle_mute(chip, ucontrol->value.integer.value[0]);
-+
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) {
-+ if (ucontrol->value.integer.value[0] != chip->dest) {
-+ chip->dest = ucontrol->value.integer.value[0];
-+ changed = 1;
-+ }
-+ }
-+
-+ if (changed) {
-+ if (bcm2835_audio_set_ctls(chip))
-+ printk(KERN_ERR "Failed to set ALSA controls..\n");
-+ }
-+
-+ return changed;
-+}
-+
-+static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1);
-+
-+static struct snd_kcontrol_new snd_bcm2835_ctl[] = {
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "PCM Playback Volume",
-+ .index = 0,
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,
-+ .private_value = PCM_PLAYBACK_VOLUME,
-+ .info = snd_bcm2835_ctl_info,
-+ .get = snd_bcm2835_ctl_get,
-+ .put = snd_bcm2835_ctl_put,
-+ .count = 1,
-+ .tlv = {.p = snd_bcm2835_db_scale}
-+ },
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "PCM Playback Switch",
-+ .index = 0,
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
-+ .private_value = PCM_PLAYBACK_MUTE,
-+ .info = snd_bcm2835_ctl_info,
-+ .get = snd_bcm2835_ctl_get,
-+ .put = snd_bcm2835_ctl_put,
-+ .count = 1,
-+ },
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "PCM Playback Route",
-+ .index = 0,
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
-+ .private_value = PCM_PLAYBACK_DEVICE,
-+ .info = snd_bcm2835_ctl_info,
-+ .get = snd_bcm2835_ctl_get,
-+ .put = snd_bcm2835_ctl_put,
-+ .count = 1,
-+ },
-+};
-+
-+static int snd_bcm2835_spdif_default_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+ uinfo->count = 1;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_default_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ int i;
-+
-+ for (i = 0; i < 4; i++)
-+ ucontrol->value.iec958.status[i] =
-+ (chip->spdif_status >> (i * 8)) && 0xff;
-+
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_default_put(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ unsigned int val = 0;
-+ int i, change;
-+
-+ for (i = 0; i < 4; i++)
-+ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
-+
-+ change = val != chip->spdif_status;
-+ chip->spdif_status = val;
-+
-+ return change;
-+}
-+
-+static int snd_bcm2835_spdif_mask_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+ uinfo->count = 1;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_mask_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ /* bcm2835 supports only consumer mode and sets all other format flags
-+ * automatically. So the only thing left is signalling non-audio
-+ * content */
-+ ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_stream_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+ uinfo->count = 1;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_stream_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ int i;
-+
-+ for (i = 0; i < 4; i++)
-+ ucontrol->value.iec958.status[i] =
-+ (chip->spdif_status >> (i * 8)) & 0xff;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_stream_put(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ unsigned int val = 0;
-+ int i, change;
-+
-+ for (i = 0; i < 4; i++)
-+ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
-+ change = val != chip->spdif_status;
-+ chip->spdif_status = val;
-+
-+ return change;
-+}
-+
-+static struct snd_kcontrol_new snd_bcm2835_spdif[] = {
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
-+ .info = snd_bcm2835_spdif_default_info,
-+ .get = snd_bcm2835_spdif_default_get,
-+ .put = snd_bcm2835_spdif_default_put
-+ },
-+ {
-+ .access = SNDRV_CTL_ELEM_ACCESS_READ,
-+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
-+ .info = snd_bcm2835_spdif_mask_info,
-+ .get = snd_bcm2835_spdif_mask_get,
-+ },
-+ {
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
-+ SNDRV_CTL_ELEM_ACCESS_INACTIVE,
-+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
-+ .info = snd_bcm2835_spdif_stream_info,
-+ .get = snd_bcm2835_spdif_stream_get,
-+ .put = snd_bcm2835_spdif_stream_put,
-+ },
-+};
-+
-+int snd_bcm2835_new_ctl(bcm2835_chip_t * chip)
-+{
-+ int err;
-+ unsigned int idx;
-+
-+ strcpy(chip->card->mixername, "Broadcom Mixer");
-+ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) {
-+ err =
-+ snd_ctl_add(chip->card,
-+ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip));
-+ if (err < 0)
-+ return err;
-+ }
-+ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_spdif); idx++) {
-+ err = snd_ctl_add(chip->card,
-+ snd_ctl_new1(&snd_bcm2835_spdif[idx], chip));
-+ if (err < 0)
-+ return err;
-+ }
-+ return 0;
-+}
-diff -Nur linux-3.12.38/sound/arm/bcm2835.h linux-rpi/sound/arm/bcm2835.h
---- linux-3.12.38/sound/arm/bcm2835.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/arm/bcm2835.h 2015-03-09 10:39:38.302893687 +0100
-@@ -0,0 +1,167 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __SOUND_ARM_BCM2835_H
-+#define __SOUND_ARM_BCM2835_H
-+
-+#include <linux/device.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/wait.h>
-+#include <sound/core.h>
-+#include <sound/initval.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/pcm-indirect.h>
-+#include <linux/workqueue.h>
-+
-+/*
-+#define AUDIO_DEBUG_ENABLE
-+#define AUDIO_VERBOSE_DEBUG_ENABLE
-+*/
-+
-+/* Debug macros */
-+
-+#ifdef AUDIO_DEBUG_ENABLE
-+#ifdef AUDIO_VERBOSE_DEBUG_ENABLE
-+
-+#define audio_debug(fmt, arg...) \
-+ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define audio_info(fmt, arg...) \
-+ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#else
-+
-+#define audio_debug(fmt, arg...)
-+
-+#define audio_info(fmt, arg...)
-+
-+#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */
-+
-+#else
-+
-+#define audio_debug(fmt, arg...)
-+
-+#define audio_info(fmt, arg...)
-+
-+#endif /* AUDIO_DEBUG_ENABLE */
-+
-+#define audio_error(fmt, arg...) \
-+ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define audio_warning(fmt, arg...) \
-+ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define audio_alert(fmt, arg...) \
-+ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define MAX_SUBSTREAMS (8)
-+#define AVAIL_SUBSTREAMS_MASK (0xff)
-+enum {
-+ CTRL_VOL_MUTE,
-+ CTRL_VOL_UNMUTE
-+};
-+
-+/* macros for alsa2chip and chip2alsa, instead of functions */
-+
-+#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */
-+#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */
-+
-+/* Some constants for values .. */
-+typedef enum {
-+ AUDIO_DEST_AUTO = 0,
-+ AUDIO_DEST_HEADPHONES = 1,
-+ AUDIO_DEST_HDMI = 2,
-+ AUDIO_DEST_MAX,
-+} SND_BCM2835_ROUTE_T;
-+
-+typedef enum {
-+ PCM_PLAYBACK_VOLUME,
-+ PCM_PLAYBACK_MUTE,
-+ PCM_PLAYBACK_DEVICE,
-+} SND_BCM2835_CTRL_T;
-+
-+/* definition of the chip-specific record */
-+typedef struct bcm2835_chip {
-+ struct snd_card *card;
-+ struct snd_pcm *pcm;
-+ struct snd_pcm *pcm_spdif;
-+ /* Bitmat for valid reg_base and irq numbers */
-+ uint32_t avail_substreams;
-+ struct platform_device *pdev[MAX_SUBSTREAMS];
-+ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS];
-+
-+ int volume;
-+ int old_volume; /* stores the volume value whist muted */
-+ int dest;
-+ int mute;
-+
-+ unsigned int opened;
-+ unsigned int spdif_status;
-+ struct mutex audio_mutex;
-+} bcm2835_chip_t;
-+
-+typedef struct bcm2835_alsa_stream {
-+ bcm2835_chip_t *chip;
-+ struct snd_pcm_substream *substream;
-+ struct snd_pcm_indirect pcm_indirect;
-+
-+ struct semaphore buffers_update_sem;
-+ struct semaphore control_sem;
-+ spinlock_t lock;
-+ volatile uint32_t control;
-+ volatile uint32_t status;
-+
-+ int open;
-+ int running;
-+ int draining;
-+
-+ int channels;
-+ int params_rate;
-+ int pcm_format_width;
-+
-+ unsigned int pos;
-+ unsigned int buffer_size;
-+ unsigned int period_size;
-+
-+ uint32_t enable_fifo_irq;
-+ irq_handler_t fifo_irq_handler;
-+
-+ atomic_t retrieved;
-+ struct opaque_AUDIO_INSTANCE_T *instance;
-+ struct workqueue_struct *my_wq;
-+ int idx;
-+} bcm2835_alsa_stream_t;
-+
-+int snd_bcm2835_new_ctl(bcm2835_chip_t * chip);
-+int snd_bcm2835_new_pcm(bcm2835_chip_t * chip);
-+int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip);
-+
-+int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream,
-+ uint32_t channels, uint32_t samplerate,
-+ uint32_t bps);
-+int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_set_ctls(bcm2835_chip_t * chip);
-+int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count,
-+ void *src);
-+uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream);
-+void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream);
-+void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream);
-+
-+#endif /* __SOUND_ARM_BCM2835_H */
-diff -Nur linux-3.12.38/sound/arm/bcm2835-pcm.c linux-rpi/sound/arm/bcm2835-pcm.c
---- linux-3.12.38/sound/arm/bcm2835-pcm.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/arm/bcm2835-pcm.c 2015-03-09 10:39:38.302893687 +0100
-@@ -0,0 +1,552 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+
-+#include <sound/asoundef.h>
-+
-+#include "bcm2835.h"
-+
-+/* hardware definition */
-+static struct snd_pcm_hardware snd_bcm2835_playback_hw = {
-+ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
-+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
-+ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
-+ .rate_min = 8000,
-+ .rate_max = 48000,
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .buffer_bytes_max = 128 * 1024,
-+ .period_bytes_min = 1 * 1024,
-+ .period_bytes_max = 128 * 1024,
-+ .periods_min = 1,
-+ .periods_max = 128,
-+};
-+
-+static struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = {
-+ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
-+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 |
-+ SNDRV_PCM_RATE_48000,
-+ .rate_min = 44100,
-+ .rate_max = 48000,
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .buffer_bytes_max = 128 * 1024,
-+ .period_bytes_min = 1 * 1024,
-+ .period_bytes_max = 128 * 1024,
-+ .periods_min = 1,
-+ .periods_max = 128,
-+};
-+
-+static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime)
-+{
-+ audio_info("Freeing up alsa stream here ..\n");
-+ if (runtime->private_data)
-+ kfree(runtime->private_data);
-+ runtime->private_data = NULL;
-+}
-+
-+static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id)
-+{
-+ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id;
-+ uint32_t consumed = 0;
-+ int new_period = 0;
-+
-+ audio_info(" .. IN\n");
-+
-+ audio_info("alsa_stream=%p substream=%p\n", alsa_stream,
-+ alsa_stream ? alsa_stream->substream : 0);
-+
-+ if (alsa_stream->open)
-+ consumed = bcm2835_audio_retrieve_buffers(alsa_stream);
-+
-+ /* We get called only if playback was triggered, So, the number of buffers we retrieve in
-+ * each iteration are the buffers that have been played out already
-+ */
-+
-+ if (alsa_stream->period_size) {
-+ if ((alsa_stream->pos / alsa_stream->period_size) !=
-+ ((alsa_stream->pos + consumed) / alsa_stream->period_size))
-+ new_period = 1;
-+ }
-+ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n",
-+ alsa_stream->pos,
-+ consumed,
-+ alsa_stream->buffer_size,
-+ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods),
-+ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr),
-+ new_period);
-+ if (alsa_stream->buffer_size) {
-+ alsa_stream->pos += consumed &~ (1<<30);
-+ alsa_stream->pos %= alsa_stream->buffer_size;
-+ }
-+
-+ if (alsa_stream->substream) {
-+ if (new_period)
-+ snd_pcm_period_elapsed(alsa_stream->substream);
-+ } else {
-+ audio_warning(" unexpected NULL substream\n");
-+ }
-+ audio_info(" .. OUT\n");
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/* open callback */
-+static int snd_bcm2835_playback_open_generic(
-+ struct snd_pcm_substream *substream, int spdif)
-+{
-+ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream);
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+ int idx;
-+ int err;
-+
-+ audio_info(" .. IN (%d)\n", substream->number);
-+
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ audio_info("Alsa open (%d)\n", substream->number);
-+ idx = substream->number;
-+
-+ if (spdif && chip->opened != 0)
-+ return -EBUSY;
-+ else if (!spdif && (chip->opened & (1 << idx)))
-+ return -EBUSY;
-+
-+ if (idx > MAX_SUBSTREAMS) {
-+ audio_error
-+ ("substream(%d) device doesn't exist max(%d) substreams allowed\n",
-+ idx, MAX_SUBSTREAMS);
-+ err = -ENODEV;
-+ goto out;
-+ }
-+
-+ /* Check if we are ready */
-+ if (!(chip->avail_substreams & (1 << idx))) {
-+ /* We are not ready yet */
-+ audio_error("substream(%d) device is not ready yet\n", idx);
-+ err = -EAGAIN;
-+ goto out;
-+ }
-+
-+ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL);
-+ if (alsa_stream == NULL) {
-+ err = -ENOMEM;
-+ goto out;
-+ }
-+
-+ /* Initialise alsa_stream */
-+ alsa_stream->chip = chip;
-+ alsa_stream->substream = substream;
-+ alsa_stream->idx = idx;
-+
-+ sema_init(&alsa_stream->buffers_update_sem, 0);
-+ sema_init(&alsa_stream->control_sem, 0);
-+ spin_lock_init(&alsa_stream->lock);
-+
-+ /* Enabled in start trigger, called on each "fifo irq" after that */
-+ alsa_stream->enable_fifo_irq = 0;
-+ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq;
-+
-+ err = bcm2835_audio_open(alsa_stream);
-+ if (err != 0) {
-+ kfree(alsa_stream);
-+ return err;
-+ }
-+ runtime->private_data = alsa_stream;
-+ runtime->private_free = snd_bcm2835_playback_free;
-+ if (spdif) {
-+ runtime->hw = snd_bcm2835_playback_spdif_hw;
-+ } else {
-+ /* clear spdif status, as we are not in spdif mode */
-+ chip->spdif_status = 0;
-+ runtime->hw = snd_bcm2835_playback_hw;
-+ }
-+ /* minimum 16 bytes alignment (for vchiq bulk transfers) */
-+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
-+ 16);
-+
-+ chip->alsa_stream[idx] = alsa_stream;
-+
-+ chip->opened |= (1 << idx);
-+ alsa_stream->open = 1;
-+ alsa_stream->draining = 1;
-+
-+out:
-+ mutex_unlock(&chip->audio_mutex);
-+
-+ audio_info(" .. OUT =%d\n", err);
-+
-+ return err;
-+}
-+
-+static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream)
-+{
-+ return snd_bcm2835_playback_open_generic(substream, 0);
-+}
-+
-+static int snd_bcm2835_playback_spdif_open(struct snd_pcm_substream *substream)
-+{
-+ return snd_bcm2835_playback_open_generic(substream, 1);
-+}
-+
-+/* close callback */
-+static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream)
-+{
-+ /* the hardware-specific codes will be here */
-+
-+ bcm2835_chip_t *chip;
-+ struct snd_pcm_runtime *runtime;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+
-+ audio_info(" .. IN\n");
-+
-+ chip = snd_pcm_substream_chip(substream);
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ runtime = substream->runtime;
-+ alsa_stream = runtime->private_data;
-+
-+ audio_info("Alsa close\n");
-+
-+ /*
-+ * Call stop if it's still running. This happens when app
-+ * is force killed and we don't get a stop trigger.
-+ */
-+ if (alsa_stream->running) {
-+ int err;
-+ err = bcm2835_audio_stop(alsa_stream);
-+ alsa_stream->running = 0;
-+ if (err != 0)
-+ audio_error(" Failed to STOP alsa device\n");
-+ }
-+
-+ alsa_stream->period_size = 0;
-+ alsa_stream->buffer_size = 0;
-+
-+ if (alsa_stream->open) {
-+ alsa_stream->open = 0;
-+ bcm2835_audio_close(alsa_stream);
-+ }
-+ if (alsa_stream->chip)
-+ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL;
-+ /*
-+ * Do not free up alsa_stream here, it will be freed up by
-+ * runtime->private_free callback we registered in *_open above
-+ */
-+
-+ chip->opened &= ~(1 << substream->number);
-+
-+ mutex_unlock(&chip->audio_mutex);
-+ audio_info(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+/* hw_params callback */
-+static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+
-+ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
-+ if (err < 0) {
-+ audio_error
-+ (" pcm_lib_malloc failed to allocated pages for buffers\n");
-+ return err;
-+ }
-+
-+ alsa_stream->channels = params_channels(params);
-+ alsa_stream->params_rate = params_rate(params);
-+ alsa_stream->pcm_format_width = snd_pcm_format_width(params_format (params));
-+ audio_info(" .. OUT\n");
-+
-+ return err;
-+}
-+
-+/* hw_free callback */
-+static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream)
-+{
-+ audio_info(" .. IN\n");
-+ return snd_pcm_lib_free_pages(substream);
-+}
-+
-+/* prepare callback */
-+static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream)
-+{
-+ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream);
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ int channels;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+
-+ /* notify the vchiq that it should enter spdif passthrough mode by
-+ * setting channels=0 (see
-+ * https://github.com/raspberrypi/linux/issues/528) */
-+ if (chip->spdif_status & IEC958_AES0_NONAUDIO)
-+ channels = 0;
-+ else
-+ channels = alsa_stream->channels;
-+
-+ err = bcm2835_audio_set_params(alsa_stream, channels,
-+ alsa_stream->params_rate,
-+ alsa_stream->pcm_format_width);
-+ if (err < 0) {
-+ audio_error(" error setting hw params\n");
-+ }
-+
-+ bcm2835_audio_setup(alsa_stream);
-+
-+ /* in preparation of the stream, set the controls (volume level) of the stream */
-+ bcm2835_audio_set_ctls(alsa_stream->chip);
-+
-+
-+ memset(&alsa_stream->pcm_indirect, 0, sizeof(alsa_stream->pcm_indirect));
-+
-+ alsa_stream->pcm_indirect.hw_buffer_size =
-+ alsa_stream->pcm_indirect.sw_buffer_size =
-+ snd_pcm_lib_buffer_bytes(substream);
-+
-+ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream);
-+ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream);
-+ alsa_stream->pos = 0;
-+
-+ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n",
-+ alsa_stream->buffer_size, alsa_stream->period_size,
-+ alsa_stream->pos, runtime->frame_bits);
-+
-+ audio_info(" .. OUT\n");
-+ return 0;
-+}
-+
-+static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream,
-+ struct snd_pcm_indirect *rec, size_t bytes)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ void *src = (void *)(substream->runtime->dma_area + rec->sw_data);
-+ int err;
-+
-+ err = bcm2835_audio_write(alsa_stream, bytes, src);
-+ if (err)
-+ audio_error(" Failed to transfer to alsa device (%d)\n", err);
-+
-+}
-+
-+static int snd_bcm2835_pcm_ack(struct snd_pcm_substream *substream)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ struct snd_pcm_indirect *pcm_indirect = &alsa_stream->pcm_indirect;
-+
-+ pcm_indirect->hw_queue_size = runtime->hw.buffer_bytes_max;
-+ snd_pcm_indirect_playback_transfer(substream, pcm_indirect,
-+ snd_bcm2835_pcm_transfer);
-+ return 0;
-+}
-+
-+/* trigger callback */
-+static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ int err = 0;
-+
-+ audio_info(" .. IN\n");
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n",
-+ alsa_stream->running);
-+ if (!alsa_stream->running) {
-+ err = bcm2835_audio_start(alsa_stream);
-+ if (err == 0) {
-+ alsa_stream->pcm_indirect.hw_io =
-+ alsa_stream->pcm_indirect.hw_data =
-+ bytes_to_frames(runtime,
-+ alsa_stream->pos);
-+ substream->ops->ack(substream);
-+ alsa_stream->running = 1;
-+ alsa_stream->draining = 1;
-+ } else {
-+ audio_error(" Failed to START alsa device (%d)\n", err);
-+ }
-+ }
-+ break;
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ audio_debug
-+ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n",
-+ alsa_stream->running, runtime->status->state == SNDRV_PCM_STATE_DRAINING);
-+ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) {
-+ audio_info("DRAINING\n");
-+ alsa_stream->draining = 1;
-+ } else {
-+ audio_info("DROPPING\n");
-+ alsa_stream->draining = 0;
-+ }
-+ if (alsa_stream->running) {
-+ err = bcm2835_audio_stop(alsa_stream);
-+ if (err != 0)
-+ audio_error(" Failed to STOP alsa device (%d)\n", err);
-+ alsa_stream->running = 0;
-+ }
-+ break;
-+ default:
-+ err = -EINVAL;
-+ }
-+
-+ audio_info(" .. OUT\n");
-+ return err;
-+}
-+
-+/* pointer callback */
-+static snd_pcm_uframes_t
-+snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+
-+ audio_info(" .. IN\n");
-+
-+ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0,
-+ frames_to_bytes(runtime, runtime->status->hw_ptr),
-+ frames_to_bytes(runtime, runtime->control->appl_ptr),
-+ alsa_stream->pos);
-+
-+ audio_info(" .. OUT\n");
-+ return snd_pcm_indirect_playback_pointer(substream,
-+ &alsa_stream->pcm_indirect,
-+ alsa_stream->pos);
-+}
-+
-+static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream,
-+ unsigned int cmd, void *arg)
-+{
-+ int ret = snd_pcm_lib_ioctl(substream, cmd, arg);
-+ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream,
-+ cmd, arg, arg ? *(unsigned *)arg : 0, ret);
-+ return ret;
-+}
-+
-+/* operators */
-+static struct snd_pcm_ops snd_bcm2835_playback_ops = {
-+ .open = snd_bcm2835_playback_open,
-+ .close = snd_bcm2835_playback_close,
-+ .ioctl = snd_bcm2835_pcm_lib_ioctl,
-+ .hw_params = snd_bcm2835_pcm_hw_params,
-+ .hw_free = snd_bcm2835_pcm_hw_free,
-+ .prepare = snd_bcm2835_pcm_prepare,
-+ .trigger = snd_bcm2835_pcm_trigger,
-+ .pointer = snd_bcm2835_pcm_pointer,
-+ .ack = snd_bcm2835_pcm_ack,
-+};
-+
-+static struct snd_pcm_ops snd_bcm2835_playback_spdif_ops = {
-+ .open = snd_bcm2835_playback_spdif_open,
-+ .close = snd_bcm2835_playback_close,
-+ .ioctl = snd_bcm2835_pcm_lib_ioctl,
-+ .hw_params = snd_bcm2835_pcm_hw_params,
-+ .hw_free = snd_bcm2835_pcm_hw_free,
-+ .prepare = snd_bcm2835_pcm_prepare,
-+ .trigger = snd_bcm2835_pcm_trigger,
-+ .pointer = snd_bcm2835_pcm_pointer,
-+ .ack = snd_bcm2835_pcm_ack,
-+};
-+
-+/* create a pcm device */
-+int snd_bcm2835_new_pcm(bcm2835_chip_t * chip)
-+{
-+ struct snd_pcm *pcm;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+ mutex_init(&chip->audio_mutex);
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ err =
-+ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm);
-+ if (err < 0)
-+ return err;
-+ pcm->private_data = chip;
-+ strcpy(pcm->name, "bcm2835 ALSA");
-+ chip->pcm = pcm;
-+ chip->dest = AUDIO_DEST_AUTO;
-+ chip->volume = alsa2chip(0);
-+ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */
-+ /* set operators */
-+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
-+ &snd_bcm2835_playback_ops);
-+
-+ /* pre-allocation of buffers */
-+ /* NOTE: this may fail */
-+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
-+ snd_dma_continuous_data
-+ (GFP_KERNEL), 64 * 1024,
-+ 64 * 1024);
-+
-+ mutex_unlock(&chip->audio_mutex);
-+ audio_info(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip)
-+{
-+ struct snd_pcm *pcm;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 1, 1, 0, &pcm);
-+ if (err < 0)
-+ return err;
-+
-+ pcm->private_data = chip;
-+ strcpy(pcm->name, "bcm2835 IEC958/HDMI");
-+ chip->pcm_spdif = pcm;
-+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
-+ &snd_bcm2835_playback_spdif_ops);
-+
-+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
-+ snd_dma_continuous_data (GFP_KERNEL),
-+ 64 * 1024, 64 * 1024);
-+ mutex_unlock(&chip->audio_mutex);
-+ audio_info(" .. OUT\n");
-+
-+ return 0;
-+}
-diff -Nur linux-3.12.38/sound/arm/bcm2835-vchiq.c linux-rpi/sound/arm/bcm2835-vchiq.c
---- linux-3.12.38/sound/arm/bcm2835-vchiq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/arm/bcm2835-vchiq.c 2015-03-10 17:26:51.874216684 +0100
-@@ -0,0 +1,901 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/device.h>
-+#include <sound/core.h>
-+#include <sound/initval.h>
-+#include <sound/pcm.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include <linux/fs.h>
-+#include <linux/file.h>
-+#include <linux/mm.h>
-+#include <linux/syscalls.h>
-+#include <asm/uaccess.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/atomic.h>
-+#include <linux/module.h>
-+#include <linux/completion.h>
-+
-+#include "bcm2835.h"
-+
-+/* ---- Include Files -------------------------------------------------------- */
-+
-+#include "interface/vchi/vchi.h"
-+#include "vc_vchi_audioserv_defs.h"
-+
-+/* ---- Private Constants and Types ------------------------------------------ */
-+
-+#define BCM2835_AUDIO_STOP 0
-+#define BCM2835_AUDIO_START 1
-+#define BCM2835_AUDIO_WRITE 2
-+
-+/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */
-+#ifdef AUDIO_DEBUG_ENABLE
-+ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+#else
-+ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_WARN( fmt, arg... )
-+ #define LOG_INFO( fmt, arg... )
-+ #define LOG_DBG( fmt, arg... )
-+#endif
-+
-+typedef struct opaque_AUDIO_INSTANCE_T {
-+ uint32_t num_connections;
-+ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
-+ struct completion msg_avail_comp;
-+ struct mutex vchi_mutex;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+ int32_t result;
-+ short peer_version;
-+} AUDIO_INSTANCE_T;
-+
-+bool force_bulk = false;
-+
-+/* ---- Private Variables ---------------------------------------------------- */
-+
-+/* ---- Private Function Prototypes ------------------------------------------ */
-+
-+/* ---- Private Functions ---------------------------------------------------- */
-+
-+static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream);
-+static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream);
-+static int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream,
-+ uint32_t count, void *src);
-+
-+typedef struct {
-+ struct work_struct my_work;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+ int cmd;
-+ void *src;
-+ uint32_t count;
-+} my_work_t;
-+
-+static void my_wq_function(struct work_struct *work)
-+{
-+ my_work_t *w = (my_work_t *) work;
-+ int ret = -9;
-+ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->cmd);
-+ switch (w->cmd) {
-+ case BCM2835_AUDIO_START:
-+ ret = bcm2835_audio_start_worker(w->alsa_stream);
-+ break;
-+ case BCM2835_AUDIO_STOP:
-+ ret = bcm2835_audio_stop_worker(w->alsa_stream);
-+ break;
-+ case BCM2835_AUDIO_WRITE:
-+ ret = bcm2835_audio_write_worker(w->alsa_stream, w->count,
-+ w->src);
-+ break;
-+ default:
-+ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->cmd);
-+ break;
-+ }
-+ kfree((void *)work);
-+ LOG_DBG(" .. OUT %d\n", ret);
-+}
-+
-+int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ int ret = -1;
-+ LOG_DBG(" .. IN\n");
-+ if (alsa_stream->my_wq) {
-+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
-+ /*--- Queue some work (item 1) ---*/
-+ if (work) {
-+ INIT_WORK((struct work_struct *)work, my_wq_function);
-+ work->alsa_stream = alsa_stream;
-+ work->cmd = BCM2835_AUDIO_START;
-+ if (queue_work
-+ (alsa_stream->my_wq, (struct work_struct *)work))
-+ ret = 0;
-+ } else
-+ LOG_ERR(" .. Error: NULL work kmalloc\n");
-+ }
-+ LOG_DBG(" .. OUT %d\n", ret);
-+ return ret;
-+}
-+
-+int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ int ret = -1;
-+ LOG_DBG(" .. IN\n");
-+ if (alsa_stream->my_wq) {
-+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
-+ /*--- Queue some work (item 1) ---*/
-+ if (work) {
-+ INIT_WORK((struct work_struct *)work, my_wq_function);
-+ work->alsa_stream = alsa_stream;
-+ work->cmd = BCM2835_AUDIO_STOP;
-+ if (queue_work
-+ (alsa_stream->my_wq, (struct work_struct *)work))
-+ ret = 0;
-+ } else
-+ LOG_ERR(" .. Error: NULL work kmalloc\n");
-+ }
-+ LOG_DBG(" .. OUT %d\n", ret);
-+ return ret;
-+}
-+
-+int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream,
-+ uint32_t count, void *src)
-+{
-+ int ret = -1;
-+ LOG_DBG(" .. IN\n");
-+ if (alsa_stream->my_wq) {
-+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
-+ /*--- Queue some work (item 1) ---*/
-+ if (work) {
-+ INIT_WORK((struct work_struct *)work, my_wq_function);
-+ work->alsa_stream = alsa_stream;
-+ work->cmd = BCM2835_AUDIO_WRITE;
-+ work->src = src;
-+ work->count = count;
-+ if (queue_work
-+ (alsa_stream->my_wq, (struct work_struct *)work))
-+ ret = 0;
-+ } else
-+ LOG_ERR(" .. Error: NULL work kmalloc\n");
-+ }
-+ LOG_DBG(" .. OUT %d\n", ret);
-+ return ret;
-+}
-+
-+void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ alsa_stream->my_wq = alloc_workqueue("my_queue", WQ_HIGHPRI, 1);
-+ return;
-+}
-+
-+void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ if (alsa_stream->my_wq) {
-+ flush_workqueue(alsa_stream->my_wq);
-+ destroy_workqueue(alsa_stream->my_wq);
-+ alsa_stream->my_wq = NULL;
-+ }
-+ return;
-+}
-+
-+static void audio_vchi_callback(void *param,
-+ const VCHI_CALLBACK_REASON_T reason,
-+ void *msg_handle)
-+{
-+ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param;
-+ int32_t status;
-+ int32_t msg_len;
-+ VC_AUDIO_MSG_T m;
-+ LOG_DBG(" .. IN instance=%p, handle=%p, alsa=%p, reason=%d, handle=%p\n",
-+ instance, instance ? instance->vchi_handle[0] : NULL, instance ? instance->alsa_stream : NULL, reason, msg_handle);
-+
-+ if (reason != VCHI_CALLBACK_MSG_AVAILABLE) {
-+ return;
-+ }
-+ if (!instance) {
-+ LOG_ERR(" .. instance is null\n");
-+ BUG();
-+ return;
-+ }
-+ if (!instance->vchi_handle[0]) {
-+ LOG_ERR(" .. instance->vchi_handle[0] is null\n");
-+ BUG();
-+ return;
-+ }
-+ status = vchi_msg_dequeue(instance->vchi_handle[0],
-+ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE);
-+ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) {
-+ LOG_DBG
-+ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n",
-+ instance, m.u.result.success);
-+ instance->result = m.u.result.success;
-+ complete(&instance->msg_avail_comp);
-+ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) {
-+ bcm2835_alsa_stream_t *alsa_stream = instance->alsa_stream;
-+ irq_handler_t callback = (irq_handler_t) m.u.complete.callback;
-+ LOG_DBG
-+ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n",
-+ instance, m.u.complete.count);
-+ if (alsa_stream && callback) {
-+ atomic_add(m.u.complete.count, &alsa_stream->retrieved);
-+ callback(0, alsa_stream);
-+ } else {
-+ LOG_ERR(" .. unexpected alsa_stream=%p, callback=%p\n",
-+ alsa_stream, callback);
-+ }
-+ } else {
-+ LOG_ERR(" .. unexpected m.type=%d\n", m.type);
-+ }
-+ LOG_DBG(" .. OUT\n");
-+}
-+
-+static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance,
-+ VCHI_CONNECTION_T **
-+ vchi_connections,
-+ uint32_t num_connections)
-+{
-+ uint32_t i;
-+ AUDIO_INSTANCE_T *instance;
-+ int status;
-+
-+ LOG_DBG("%s: start", __func__);
-+
-+ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
-+ LOG_ERR("%s: unsupported number of connections %u (max=%u)\n",
-+ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
-+
-+ return NULL;
-+ }
-+ /* Allocate memory for this instance */
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+ if (!instance)
-+ return NULL;
-+
-+ instance->num_connections = num_connections;
-+
-+ /* Create a lock for exclusive, serialized VCHI connection access */
-+ mutex_init(&instance->vchi_mutex);
-+ /* Open the VCHI service connections */
-+ for (i = 0; i < num_connections; i++) {
-+ SERVICE_CREATION_T params = {
-+ VCHI_VERSION_EX(VC_AUDIOSERV_VER, VC_AUDIOSERV_MIN_VER),
-+ VC_AUDIO_SERVER_NAME, // 4cc service code
-+ vchi_connections[i], // passed in fn pointers
-+ 0, // rx fifo size (unused)
-+ 0, // tx fifo size (unused)
-+ audio_vchi_callback, // service callback
-+ instance, // service callback parameter
-+ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves
-+ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits
-+ 0 // want crc check on bulk transfers
-+ };
-+
-+ LOG_DBG("%s: about to open %i\n", __func__, i);
-+ status = vchi_service_open(vchi_instance, &params,
-+ &instance->vchi_handle[i]);
-+ LOG_DBG("%s: opened %i: %p=%d\n", __func__, i, instance->vchi_handle[i], status);
-+ if (status) {
-+ LOG_ERR
-+ ("%s: failed to open VCHI service connection (status=%d)\n",
-+ __func__, status);
-+
-+ goto err_close_services;
-+ }
-+ /* Finished with the service for now */
-+ vchi_service_release(instance->vchi_handle[i]);
-+ }
-+
-+ LOG_DBG("%s: okay\n", __func__);
-+ return instance;
-+
-+err_close_services:
-+ for (i = 0; i < instance->num_connections; i++) {
-+ LOG_ERR("%s: closing %i: %p\n", __func__, i, instance->vchi_handle[i]);
-+ if (instance->vchi_handle[i])
-+ vchi_service_close(instance->vchi_handle[i]);
-+ }
-+
-+ kfree(instance);
-+ LOG_ERR("%s: error\n", __func__);
-+
-+ return NULL;
-+}
-+
-+static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance)
-+{
-+ uint32_t i;
-+
-+ LOG_DBG(" .. IN\n");
-+
-+ if (instance == NULL) {
-+ LOG_ERR("%s: invalid handle %p\n", __func__, instance);
-+
-+ return -1;
-+ }
-+
-+ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections);
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+
-+ /* Close all VCHI service connections */
-+ for (i = 0; i < instance->num_connections; i++) {
-+ int32_t success;
-+ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]);
-+ vchi_service_use(instance->vchi_handle[i]);
-+
-+ success = vchi_service_close(instance->vchi_handle[i]);
-+ if (success != 0) {
-+ LOG_ERR
-+ ("%s: failed to close VCHI service connection (status=%d)\n",
-+ __func__, success);
-+ }
-+ }
-+
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ kfree(instance);
-+
-+ LOG_DBG(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ static VCHI_INSTANCE_T vchi_instance;
-+ static VCHI_CONNECTION_T *vchi_connection;
-+ static int initted;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO("%s: start\n", __func__);
-+ BUG_ON(instance);
-+ if (instance) {
-+ LOG_ERR("%s: VCHI instance already open (%p)\n",
-+ __func__, instance);
-+ instance->alsa_stream = alsa_stream;
-+ alsa_stream->instance = instance;
-+ ret = 0; // xxx todo -1;
-+ goto err_free_mem;
-+ }
-+
-+ /* Initialize and create a VCHI connection */
-+ if (!initted) {
-+ ret = vchi_initialise(&vchi_instance);
-+ if (ret != 0) {
-+ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+ ret = vchi_connect(NULL, 0, vchi_instance);
-+ if (ret != 0) {
-+ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+ initted = 1;
-+ }
-+
-+ /* Initialize an instance of the audio service */
-+ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1);
-+
-+ if (instance == NULL) {
-+ LOG_ERR("%s: failed to initialize audio service\n", __func__);
-+
-+ ret = -EPERM;
-+ goto err_free_mem;
-+ }
-+
-+ instance->alsa_stream = alsa_stream;
-+ alsa_stream->instance = instance;
-+
-+ LOG_DBG(" success !\n");
-+err_free_mem:
-+ LOG_DBG(" .. OUT\n");
-+
-+ return ret;
-+}
-+
-+int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ AUDIO_INSTANCE_T *instance;
-+ VC_AUDIO_MSG_T m;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ my_workqueue_init(alsa_stream);
-+
-+ ret = bcm2835_audio_open_connection(alsa_stream);
-+ if (ret != 0) {
-+ ret = -1;
-+ goto exit;
-+ }
-+ instance = alsa_stream->instance;
-+ LOG_DBG(" instance (%p)\n", instance);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_OPEN;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+exit:
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream,
-+ bcm2835_chip_t * chip)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO
-+ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ instance->result = -1;
-+
-+ m.type = VC_AUDIO_MSG_TYPE_CONTROL;
-+ m.u.control.dest = chip->dest;
-+ m.u.control.volume = chip->volume;
-+
-+ /* Create the message available completion */
-+ init_completion(&instance->msg_avail_comp);
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ /* We are expecting a reply from the videocore */
-+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
-+ if (ret) {
-+ LOG_ERR("%s: failed on waiting for event (status=%d)\n",
-+ __func__, success);
-+ goto unlock;
-+ }
-+
-+ if (instance->result != 0) {
-+ LOG_ERR("%s: result=%d\n", __func__, instance->result);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_set_ctls(bcm2835_chip_t * chip)
-+{
-+ int i;
-+ int ret = 0;
-+ LOG_DBG(" .. IN\n");
-+ LOG_DBG(" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume);
-+
-+ /* change ctls for all substreams */
-+ for (i = 0; i < MAX_SUBSTREAMS; i++) {
-+ if (chip->avail_substreams & (1 << i)) {
-+ if (!chip->alsa_stream[i])
-+ {
-+ LOG_DBG(" No ALSA stream available?! %i:%p (%x)\n", i, chip->alsa_stream[i], chip->avail_substreams);
-+ ret = 0;
-+ }
-+ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */
-+ (chip->alsa_stream[i], chip) != 0)
-+ {
-+ LOG_ERR("Couldn't set the controls for stream %d\n", i);
-+ ret = -1;
-+ }
-+ else LOG_DBG(" Controls set for stream %d\n", i);
-+ }
-+ }
-+ LOG_DBG(" .. OUT ret=%d\n", ret);
-+ return ret;
-+}
-+
-+int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream,
-+ uint32_t channels, uint32_t samplerate,
-+ uint32_t bps)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO
-+ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n",
-+ channels, samplerate, bps);
-+
-+ /* resend ctls - alsa_stream may not have been open when first send */
-+ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip);
-+ if (ret != 0) {
-+ LOG_ERR(" Alsa controls not supported\n");
-+ return -EINVAL;
-+ }
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ instance->result = -1;
-+
-+ m.type = VC_AUDIO_MSG_TYPE_CONFIG;
-+ m.u.config.channels = channels;
-+ m.u.config.samplerate = samplerate;
-+ m.u.config.bps = bps;
-+
-+ /* Create the message available completion */
-+ init_completion(&instance->msg_avail_comp);
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ /* We are expecting a reply from the videocore */
-+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
-+ if (ret) {
-+ LOG_ERR("%s: failed on waiting for event (status=%d)\n",
-+ __func__, success);
-+ goto unlock;
-+ }
-+
-+ if (instance->result != 0) {
-+ LOG_ERR("%s: result=%d", __func__, instance->result);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_DBG(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_START;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_STOP;
-+ m.u.stop.draining = alsa_stream->draining;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ my_workqueue_quit(alsa_stream);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_CLOSE;
-+
-+ /* Create the message available completion */
-+ init_completion(&instance->msg_avail_comp);
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
-+ if (ret) {
-+ LOG_ERR("%s: failed on waiting for event (status=%d)\n",
-+ __func__, success);
-+ goto unlock;
-+ }
-+ if (instance->result != 0) {
-+ LOG_ERR("%s: failed result (status=%d)\n",
-+ __func__, instance->result);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ /* Stop the audio service */
-+ if (instance) {
-+ vc_vchi_audio_deinit(instance);
-+ alsa_stream->instance = NULL;
-+ }
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream,
-+ uint32_t count, void *src)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO(" Writing %d bytes from %p\n", count, src);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ if ( instance->peer_version==0 && vchi_get_peer_version(instance->vchi_handle[0], &instance->peer_version) == 0 ) {
-+ LOG_DBG("%s: client version %d connected\n", __func__, instance->peer_version);
-+ }
-+ m.type = VC_AUDIO_MSG_TYPE_WRITE;
-+ m.u.write.count = count;
-+ // old version uses bulk, new version uses control
-+ m.u.write.max_packet = instance->peer_version < 2 || force_bulk ? 0:4000;
-+ m.u.write.callback = alsa_stream->fifo_irq_handler;
-+ m.u.write.cookie = alsa_stream;
-+ m.u.write.silence = src == NULL;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+ if (!m.u.write.silence) {
-+ if (m.u.write.max_packet == 0) {
-+ /* Send the message to the videocore */
-+ success = vchi_bulk_queue_transmit(instance->vchi_handle[0],
-+ src, count,
-+ 0 *
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED
-+ +
-+ 1 *
-+ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ,
-+ NULL);
-+ } else {
-+ while (count > 0) {
-+ int bytes = min((int)m.u.write.max_packet, (int)count);
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ src, bytes,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+ src = (char *)src + bytes;
-+ count -= bytes;
-+ }
-+ }
-+ if (success != 0) {
-+ LOG_ERR
-+ ("%s: failed on vchi_bulk_queue_transmit (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+ }
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+/**
-+ * Returns all buffers from arm->vc
-+ */
-+void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ LOG_DBG(" .. IN\n");
-+ LOG_DBG(" .. OUT\n");
-+ return;
-+}
-+
-+/**
-+ * Forces VC to flush(drop) its filled playback buffers and
-+ * return them the us. (VC->ARM)
-+ */
-+void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ LOG_DBG(" .. IN\n");
-+ LOG_DBG(" .. OUT\n");
-+}
-+
-+uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ uint32_t count = atomic_read(&alsa_stream->retrieved);
-+ atomic_sub(count, &alsa_stream->retrieved);
-+ return count;
-+}
-+
-+module_param(force_bulk, bool, 0444);
-+MODULE_PARM_DESC(force_bulk, "Force use of vchiq bulk for audio");
-diff -Nur linux-3.12.38/sound/arm/Kconfig linux-rpi/sound/arm/Kconfig
---- linux-3.12.38/sound/arm/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/arm/Kconfig 2015-03-10 17:26:51.874216684 +0100
-@@ -39,5 +39,12 @@
- Say Y or M if you want to support any AC97 codec attached to
- the PXA2xx AC97 interface.
-
-+config SND_BCM2835
-+ tristate "BCM2835 ALSA driver"
-+ depends on ARCH_BCM2708 && BCM2708_VCHIQ && SND
-+ select SND_PCM
-+ help
-+ Say Y or M if you want to support BCM2835 Alsa pcm card driver
-+
- endif # SND_ARM
-
-diff -Nur linux-3.12.38/sound/arm/Makefile linux-rpi/sound/arm/Makefile
---- linux-3.12.38/sound/arm/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/arm/Makefile 2015-03-09 10:39:38.302893687 +0100
-@@ -14,3 +14,8 @@
-
- obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o
- snd-pxa2xx-ac97-objs := pxa2xx-ac97.o
-+
-+obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o
-+snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o
-+
-+ccflags-y += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000
-diff -Nur linux-3.12.38/sound/arm/vc_vchi_audioserv_defs.h linux-rpi/sound/arm/vc_vchi_audioserv_defs.h
---- linux-3.12.38/sound/arm/vc_vchi_audioserv_defs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/arm/vc_vchi_audioserv_defs.h 2015-03-09 10:39:38.302893687 +0100
-@@ -0,0 +1,116 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef _VC_AUDIO_DEFS_H_
-+#define _VC_AUDIO_DEFS_H_
-+
-+#define VC_AUDIOSERV_MIN_VER 1
-+#define VC_AUDIOSERV_VER 2
-+
-+// FourCC code used for VCHI connection
-+#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS")
-+
-+// Maximum message length
-+#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T ))
-+
-+// List of screens that are currently supported
-+// All message types supported for HOST->VC direction
-+typedef enum {
-+ VC_AUDIO_MSG_TYPE_RESULT, // Generic result
-+ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result
-+ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio
-+ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio
-+ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio
-+ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio
-+ VC_AUDIO_MSG_TYPE_START, // Configure audio
-+ VC_AUDIO_MSG_TYPE_STOP, // Configure audio
-+ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio
-+ VC_AUDIO_MSG_TYPE_MAX
-+} VC_AUDIO_MSG_TYPE;
-+
-+// configure the audio
-+typedef struct {
-+ uint32_t channels;
-+ uint32_t samplerate;
-+ uint32_t bps;
-+
-+} VC_AUDIO_CONFIG_T;
-+
-+typedef struct {
-+ uint32_t volume;
-+ uint32_t dest;
-+
-+} VC_AUDIO_CONTROL_T;
-+
-+// audio
-+typedef struct {
-+ uint32_t dummy;
-+
-+} VC_AUDIO_OPEN_T;
-+
-+// audio
-+typedef struct {
-+ uint32_t dummy;
-+
-+} VC_AUDIO_CLOSE_T;
-+// audio
-+typedef struct {
-+ uint32_t dummy;
-+
-+} VC_AUDIO_START_T;
-+// audio
-+typedef struct {
-+ uint32_t draining;
-+
-+} VC_AUDIO_STOP_T;
-+
-+// configure the write audio samples
-+typedef struct {
-+ uint32_t count; // in bytes
-+ void *callback;
-+ void *cookie;
-+ uint16_t silence;
-+ uint16_t max_packet;
-+} VC_AUDIO_WRITE_T;
-+
-+// Generic result for a request (VC->HOST)
-+typedef struct {
-+ int32_t success; // Success value
-+
-+} VC_AUDIO_RESULT_T;
-+
-+// Generic result for a request (VC->HOST)
-+typedef struct {
-+ int32_t count; // Success value
-+ void *callback;
-+ void *cookie;
-+} VC_AUDIO_COMPLETE_T;
-+
-+// Message header for all messages in HOST->VC direction
-+typedef struct {
-+ int32_t type; // Message type (VC_AUDIO_MSG_TYPE)
-+ union {
-+ VC_AUDIO_CONFIG_T config;
-+ VC_AUDIO_CONTROL_T control;
-+ VC_AUDIO_OPEN_T open;
-+ VC_AUDIO_CLOSE_T close;
-+ VC_AUDIO_START_T start;
-+ VC_AUDIO_STOP_T stop;
-+ VC_AUDIO_WRITE_T write;
-+ VC_AUDIO_RESULT_T result;
-+ VC_AUDIO_COMPLETE_T complete;
-+ } u;
-+} VC_AUDIO_MSG_T;
-+
-+#endif // _VC_AUDIO_DEFS_H_
-diff -Nur linux-3.12.38/sound/core/seq/seq_dummy.c linux-rpi/sound/core/seq/seq_dummy.c
---- linux-3.12.38/sound/core/seq/seq_dummy.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/core/seq/seq_dummy.c 2015-03-10 17:26:51.878216684 +0100
-@@ -82,6 +82,36 @@
- static int my_client = -1;
-
- /*
-+ * unuse callback - send ALL_SOUNDS_OFF and RESET_CONTROLLERS events
-+ * to subscribers.
-+ * Note: this callback is called only after all subscribers are removed.
-+ */
-+static int
-+dummy_unuse(void *private_data, struct snd_seq_port_subscribe *info)
-+{
-+ struct snd_seq_dummy_port *p;
-+ int i;
-+ struct snd_seq_event ev;
-+
-+ p = private_data;
-+ memset(&ev, 0, sizeof(ev));
-+ if (p->duplex)
-+ ev.source.port = p->connect;
-+ else
-+ ev.source.port = p->port;
-+ ev.dest.client = SNDRV_SEQ_ADDRESS_SUBSCRIBERS;
-+ ev.type = SNDRV_SEQ_EVENT_CONTROLLER;
-+ for (i = 0; i < 16; i++) {
-+ ev.data.control.channel = i;
-+ ev.data.control.param = MIDI_CTL_ALL_SOUNDS_OFF;
-+ snd_seq_kernel_client_dispatch(p->client, &ev, 0, 0);
-+ ev.data.control.param = MIDI_CTL_RESET_CONTROLLERS;
-+ snd_seq_kernel_client_dispatch(p->client, &ev, 0, 0);
-+ }
-+ return 0;
-+}
-+
-+/*
- * event input callback - just redirect events to subscribers
- */
- static int
-@@ -145,6 +175,7 @@
- | SNDRV_SEQ_PORT_TYPE_PORT;
- memset(&pcb, 0, sizeof(pcb));
- pcb.owner = THIS_MODULE;
-+ pcb.unuse = dummy_unuse;
- pcb.event_input = dummy_input;
- pcb.private_free = dummy_free;
- pcb.private_data = rec;
-diff -Nur linux-3.12.38/sound/i2c/other/ak4113.c linux-rpi/sound/i2c/other/ak4113.c
---- linux-3.12.38/sound/i2c/other/ak4113.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/i2c/other/ak4113.c 2015-03-10 17:26:51.882216684 +0100
-@@ -56,7 +56,8 @@
-
- static void snd_ak4113_free(struct ak4113 *chip)
- {
-- atomic_inc(&chip->wq_processing); /* don't schedule new work */
-+ chip->init = 1; /* don't schedule new work */
-+ mb();
- cancel_delayed_work_sync(&chip->work);
- kfree(chip);
- }
-@@ -88,7 +89,6 @@
- chip->write = write;
- chip->private_data = private_data;
- INIT_DELAYED_WORK(&chip->work, ak4113_stats);
-- atomic_set(&chip->wq_processing, 0);
-
- for (reg = 0; reg < AK4113_WRITABLE_REGS ; reg++)
- chip->regmap[reg] = pgm[reg];
-@@ -139,11 +139,13 @@
-
- void snd_ak4113_reinit(struct ak4113 *chip)
- {
-- if (atomic_inc_return(&chip->wq_processing) == 1)
-- cancel_delayed_work_sync(&chip->work);
-+ chip->init = 1;
-+ mb();
-+ flush_delayed_work(&chip->work);
- ak4113_init_regs(chip);
- /* bring up statistics / event queing */
-- if (atomic_dec_and_test(&chip->wq_processing))
-+ chip->init = 0;
-+ if (chip->kctls[0])
- schedule_delayed_work(&chip->work, HZ / 10);
- }
- EXPORT_SYMBOL_GPL(snd_ak4113_reinit);
-@@ -630,9 +632,8 @@
- {
- struct ak4113 *chip = container_of(work, struct ak4113, work.work);
-
-- if (atomic_inc_return(&chip->wq_processing) == 1)
-+ if (!chip->init)
- snd_ak4113_check_rate_and_errors(chip, chip->check_flags);
-
-- if (atomic_dec_and_test(&chip->wq_processing))
-- schedule_delayed_work(&chip->work, HZ / 10);
-+ schedule_delayed_work(&chip->work, HZ / 10);
- }
-diff -Nur linux-3.12.38/sound/i2c/other/ak4114.c linux-rpi/sound/i2c/other/ak4114.c
---- linux-3.12.38/sound/i2c/other/ak4114.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/i2c/other/ak4114.c 2015-03-10 17:26:51.882216684 +0100
-@@ -66,7 +66,8 @@
-
- static void snd_ak4114_free(struct ak4114 *chip)
- {
-- atomic_inc(&chip->wq_processing); /* don't schedule new work */
-+ chip->init = 1; /* don't schedule new work */
-+ mb();
- cancel_delayed_work_sync(&chip->work);
- kfree(chip);
- }
-@@ -99,7 +100,6 @@
- chip->write = write;
- chip->private_data = private_data;
- INIT_DELAYED_WORK(&chip->work, ak4114_stats);
-- atomic_set(&chip->wq_processing, 0);
-
- for (reg = 0; reg < 7; reg++)
- chip->regmap[reg] = pgm[reg];
-@@ -152,11 +152,13 @@
-
- void snd_ak4114_reinit(struct ak4114 *chip)
- {
-- if (atomic_inc_return(&chip->wq_processing) == 1)
-- cancel_delayed_work_sync(&chip->work);
-+ chip->init = 1;
-+ mb();
-+ flush_delayed_work(&chip->work);
- ak4114_init_regs(chip);
- /* bring up statistics / event queing */
-- if (atomic_dec_and_test(&chip->wq_processing))
-+ chip->init = 0;
-+ if (chip->kctls[0])
- schedule_delayed_work(&chip->work, HZ / 10);
- }
-
-@@ -610,10 +612,10 @@
- {
- struct ak4114 *chip = container_of(work, struct ak4114, work.work);
-
-- if (atomic_inc_return(&chip->wq_processing) == 1)
-+ if (!chip->init)
- snd_ak4114_check_rate_and_errors(chip, chip->check_flags);
-- if (atomic_dec_and_test(&chip->wq_processing))
-- schedule_delayed_work(&chip->work, HZ / 10);
-+
-+ schedule_delayed_work(&chip->work, HZ / 10);
- }
-
- EXPORT_SYMBOL(snd_ak4114_create);
-diff -Nur linux-3.12.38/sound/pci/hda/hda_codec.c linux-rpi/sound/pci/hda/hda_codec.c
---- linux-3.12.38/sound/pci/hda/hda_codec.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/pci/hda/hda_codec.c 2015-03-10 17:26:51.906216684 +0100
-@@ -329,10 +329,8 @@
- unsigned int parm;
-
- parm = snd_hda_param_read(codec, nid, AC_PAR_NODE_COUNT);
-- if (parm == -1) {
-- *start_id = 0;
-+ if (parm == -1)
- return 0;
-- }
- *start_id = (parm >> 16) & 0x7fff;
- return (int)(parm & 0x7fff);
- }
-diff -Nur linux-3.12.38/sound/pci/hda/patch_sigmatel.c linux-rpi/sound/pci/hda/patch_sigmatel.c
---- linux-3.12.38/sound/pci/hda/patch_sigmatel.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/pci/hda/patch_sigmatel.c 2015-03-10 17:26:51.914216684 +0100
-@@ -582,9 +582,9 @@
- spec->gpio_mask;
- }
- if (get_int_hint(codec, "gpio_dir", &spec->gpio_dir))
-- spec->gpio_dir &= spec->gpio_mask;
-+ spec->gpio_mask &= spec->gpio_mask;
- if (get_int_hint(codec, "gpio_data", &spec->gpio_data))
-- spec->gpio_data &= spec->gpio_mask;
-+ spec->gpio_dir &= spec->gpio_mask;
- if (get_int_hint(codec, "eapd_mask", &spec->eapd_mask))
- spec->eapd_mask &= spec->gpio_mask;
- if (get_int_hint(codec, "gpio_mute", &spec->gpio_mute))
-diff -Nur linux-3.12.38/sound/soc/atmel/atmel_ssc_dai.c linux-rpi/sound/soc/atmel/atmel_ssc_dai.c
---- linux-3.12.38/sound/soc/atmel/atmel_ssc_dai.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/atmel/atmel_ssc_dai.c 2015-03-10 17:26:51.926216684 +0100
-@@ -344,6 +344,7 @@
- struct atmel_pcm_dma_params *dma_params;
- int dir, channels, bits;
- u32 tfmr, rfmr, tcmr, rcmr;
-+ int start_event;
- int ret;
-
- /*
-@@ -450,10 +451,19 @@
- * The SSC transmit clock is obtained from the BCLK signal on
- * on the TK line, and the SSC receive clock is
- * generated from the transmit clock.
-+ *
-+ * For single channel data, one sample is transferred
-+ * on the falling edge of the LRC clock.
-+ * For two channel data, one sample is
-+ * transferred on both edges of the LRC clock.
- */
-+ start_event = ((channels == 1)
-+ ? SSC_START_FALLING_RF
-+ : SSC_START_EDGE_RF);
-+
- rcmr = SSC_BF(RCMR_PERIOD, 0)
- | SSC_BF(RCMR_STTDLY, START_DELAY)
-- | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
-+ | SSC_BF(RCMR_START, start_event)
- | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
- | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
- | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
-@@ -461,14 +471,14 @@
- rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
- | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
- | SSC_BF(RFMR_FSLEN, 0)
-- | SSC_BF(RFMR_DATNB, (channels - 1))
-+ | SSC_BF(RFMR_DATNB, 0)
- | SSC_BIT(RFMR_MSBF)
- | SSC_BF(RFMR_LOOP, 0)
- | SSC_BF(RFMR_DATLEN, (bits - 1));
-
- tcmr = SSC_BF(TCMR_PERIOD, 0)
- | SSC_BF(TCMR_STTDLY, START_DELAY)
-- | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
-+ | SSC_BF(TCMR_START, start_event)
- | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
- | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
- | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
-@@ -477,7 +487,7 @@
- | SSC_BF(TFMR_FSDEN, 0)
- | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
- | SSC_BF(TFMR_FSLEN, 0)
-- | SSC_BF(TFMR_DATNB, (channels - 1))
-+ | SSC_BF(TFMR_DATNB, 0)
- | SSC_BIT(TFMR_MSBF)
- | SSC_BF(TFMR_DATDEF, 0)
- | SSC_BF(TFMR_DATLEN, (bits - 1));
-diff -Nur linux-3.12.38/sound/soc/bcm/bcm2708-i2s.c linux-rpi/sound/soc/bcm/bcm2708-i2s.c
---- linux-3.12.38/sound/soc/bcm/bcm2708-i2s.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/bcm2708-i2s.c 2015-03-10 17:26:51.926216684 +0100
-@@ -0,0 +1,998 @@
-+/*
-+ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * Based on
-+ * Raspberry Pi PCM I2S ALSA Driver
-+ * Copyright (c) by Phil Poole 2013
-+ *
-+ * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
-+ * Vladimir Barinov, <vbarinov@embeddedalley.com>
-+ * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
-+ *
-+ * OMAP ALSA SoC DAI driver using McBSP port
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
-+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
-+ *
-+ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
-+ * Author: Timur Tabi <timur@freescale.com>
-+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include "bcm2708-i2s.h"
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <mach/gpio.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/initval.h>
-+#include <sound/soc.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include <asm/system_info.h>
-+
-+/* Clock registers */
-+#define BCM2708_CLK_PCMCTL_REG 0x00
-+#define BCM2708_CLK_PCMDIV_REG 0x04
-+
-+/* Clock register settings */
-+#define BCM2708_CLK_PASSWD (0x5a000000)
-+#define BCM2708_CLK_PASSWD_MASK (0xff000000)
-+#define BCM2708_CLK_MASH(v) ((v) << 9)
-+#define BCM2708_CLK_FLIP BIT(8)
-+#define BCM2708_CLK_BUSY BIT(7)
-+#define BCM2708_CLK_KILL BIT(5)
-+#define BCM2708_CLK_ENAB BIT(4)
-+#define BCM2708_CLK_SRC(v) (v)
-+
-+#define BCM2708_CLK_SHIFT (12)
-+#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
-+#define BCM2708_CLK_DIVF(v) (v)
-+#define BCM2708_CLK_DIVF_MASK (0xFFF)
-+
-+enum {
-+ BCM2708_CLK_MASH_0 = 0,
-+ BCM2708_CLK_MASH_1,
-+ BCM2708_CLK_MASH_2,
-+ BCM2708_CLK_MASH_3,
-+};
-+
-+enum {
-+ BCM2708_CLK_SRC_GND = 0,
-+ BCM2708_CLK_SRC_OSC,
-+ BCM2708_CLK_SRC_DBG0,
-+ BCM2708_CLK_SRC_DBG1,
-+ BCM2708_CLK_SRC_PLLA,
-+ BCM2708_CLK_SRC_PLLC,
-+ BCM2708_CLK_SRC_PLLD,
-+ BCM2708_CLK_SRC_HDMI,
-+};
-+
-+/* Most clocks are not useable (freq = 0) */
-+static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
-+ [BCM2708_CLK_SRC_GND] = 0,
-+ [BCM2708_CLK_SRC_OSC] = 19200000,
-+ [BCM2708_CLK_SRC_DBG0] = 0,
-+ [BCM2708_CLK_SRC_DBG1] = 0,
-+ [BCM2708_CLK_SRC_PLLA] = 0,
-+ [BCM2708_CLK_SRC_PLLC] = 0,
-+ [BCM2708_CLK_SRC_PLLD] = 500000000,
-+ [BCM2708_CLK_SRC_HDMI] = 0,
-+};
-+
-+/* I2S registers */
-+#define BCM2708_I2S_CS_A_REG 0x00
-+#define BCM2708_I2S_FIFO_A_REG 0x04
-+#define BCM2708_I2S_MODE_A_REG 0x08
-+#define BCM2708_I2S_RXC_A_REG 0x0c
-+#define BCM2708_I2S_TXC_A_REG 0x10
-+#define BCM2708_I2S_DREQ_A_REG 0x14
-+#define BCM2708_I2S_INTEN_A_REG 0x18
-+#define BCM2708_I2S_INTSTC_A_REG 0x1c
-+#define BCM2708_I2S_GRAY_REG 0x20
-+
-+/* I2S register settings */
-+#define BCM2708_I2S_STBY BIT(25)
-+#define BCM2708_I2S_SYNC BIT(24)
-+#define BCM2708_I2S_RXSEX BIT(23)
-+#define BCM2708_I2S_RXF BIT(22)
-+#define BCM2708_I2S_TXE BIT(21)
-+#define BCM2708_I2S_RXD BIT(20)
-+#define BCM2708_I2S_TXD BIT(19)
-+#define BCM2708_I2S_RXR BIT(18)
-+#define BCM2708_I2S_TXW BIT(17)
-+#define BCM2708_I2S_CS_RXERR BIT(16)
-+#define BCM2708_I2S_CS_TXERR BIT(15)
-+#define BCM2708_I2S_RXSYNC BIT(14)
-+#define BCM2708_I2S_TXSYNC BIT(13)
-+#define BCM2708_I2S_DMAEN BIT(9)
-+#define BCM2708_I2S_RXTHR(v) ((v) << 7)
-+#define BCM2708_I2S_TXTHR(v) ((v) << 5)
-+#define BCM2708_I2S_RXCLR BIT(4)
-+#define BCM2708_I2S_TXCLR BIT(3)
-+#define BCM2708_I2S_TXON BIT(2)
-+#define BCM2708_I2S_RXON BIT(1)
-+#define BCM2708_I2S_EN (1)
-+
-+#define BCM2708_I2S_CLKDIS BIT(28)
-+#define BCM2708_I2S_PDMN BIT(27)
-+#define BCM2708_I2S_PDME BIT(26)
-+#define BCM2708_I2S_FRXP BIT(25)
-+#define BCM2708_I2S_FTXP BIT(24)
-+#define BCM2708_I2S_CLKM BIT(23)
-+#define BCM2708_I2S_CLKI BIT(22)
-+#define BCM2708_I2S_FSM BIT(21)
-+#define BCM2708_I2S_FSI BIT(20)
-+#define BCM2708_I2S_FLEN(v) ((v) << 10)
-+#define BCM2708_I2S_FSLEN(v) (v)
-+
-+#define BCM2708_I2S_CHWEX BIT(15)
-+#define BCM2708_I2S_CHEN BIT(14)
-+#define BCM2708_I2S_CHPOS(v) ((v) << 4)
-+#define BCM2708_I2S_CHWID(v) (v)
-+#define BCM2708_I2S_CH1(v) ((v) << 16)
-+#define BCM2708_I2S_CH2(v) (v)
-+
-+#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
-+#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
-+#define BCM2708_I2S_TX(v) ((v) << 8)
-+#define BCM2708_I2S_RX(v) (v)
-+
-+#define BCM2708_I2S_INT_RXERR BIT(3)
-+#define BCM2708_I2S_INT_TXERR BIT(2)
-+#define BCM2708_I2S_INT_RXR BIT(1)
-+#define BCM2708_I2S_INT_TXW BIT(0)
-+
-+/* I2S DMA interface */
-+#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
-+#define BCM2708_DMA_DREQ_PCM_TX 2
-+#define BCM2708_DMA_DREQ_PCM_RX 3
-+
-+/* I2S pin configuration */
-+static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO;
-+
-+/* General device struct */
-+struct bcm2708_i2s_dev {
-+ struct device *dev;
-+ struct snd_dmaengine_dai_dma_data dma_data[2];
-+ unsigned int fmt;
-+ unsigned int bclk_ratio;
-+
-+ struct regmap *i2s_regmap;
-+ struct regmap *clk_regmap;
-+};
-+
-+void bcm2708_i2s_set_gpio(int gpio) {
-+ bcm2708_i2s_gpio=gpio;
-+}
-+EXPORT_SYMBOL(bcm2708_i2s_set_gpio);
-+
-+
-+static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
-+{
-+ /* Start the clock if in master mode */
-+ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
-+
-+ switch (master) {
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ case SND_SOC_DAIFMT_CBS_CFM:
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
-+ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
-+{
-+ uint32_t clkreg;
-+ int timeout = 1000;
-+
-+ /* Stop clock */
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
-+ BCM2708_CLK_PASSWD);
-+
-+ /* Wait for the BUSY flag going down */
-+ while (--timeout) {
-+ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
-+ if (!(clkreg & BCM2708_CLK_BUSY))
-+ break;
-+ }
-+
-+ if (!timeout) {
-+ /* KILL the clock */
-+ dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
-+ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
-+ }
-+}
-+
-+static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
-+ bool tx, bool rx)
-+{
-+ int timeout = 1000;
-+ uint32_t syncval;
-+ uint32_t csreg;
-+ uint32_t i2s_active_state;
-+ uint32_t clkreg;
-+ uint32_t clk_active_state;
-+ uint32_t off;
-+ uint32_t clr;
-+
-+ off = tx ? BCM2708_I2S_TXON : 0;
-+ off |= rx ? BCM2708_I2S_RXON : 0;
-+
-+ clr = tx ? BCM2708_I2S_TXCLR : 0;
-+ clr |= rx ? BCM2708_I2S_RXCLR : 0;
-+
-+ /* Backup the current state */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
-+ i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
-+
-+ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
-+ clk_active_state = clkreg & BCM2708_CLK_ENAB;
-+
-+ /* Start clock if not running */
-+ if (!clk_active_state) {
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
-+ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
-+ }
-+
-+ /* Stop I2S module */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
-+
-+ /*
-+ * Clear the FIFOs
-+ * Requires at least 2 PCM clock cycles to take effect
-+ */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
-+
-+ /* Wait for 2 PCM clock cycles */
-+
-+ /*
-+ * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
-+ * FIXME: This does not seem to work for slave mode!
-+ */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
-+ syncval &= BCM2708_I2S_SYNC;
-+
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_SYNC, ~syncval);
-+
-+ /* Wait for the SYNC flag changing it's state */
-+ while (--timeout) {
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
-+ if ((csreg & BCM2708_I2S_SYNC) != syncval)
-+ break;
-+ }
-+
-+ if (!timeout)
-+ dev_err(dev->dev, "I2S SYNC error!\n");
-+
-+ /* Stop clock if it was not running before */
-+ if (!clk_active_state)
-+ bcm2708_i2s_stop_clock(dev);
-+
-+ /* Restore I2S state */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
-+}
-+
-+static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
-+ unsigned int fmt)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ dev->fmt = fmt;
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
-+ unsigned int ratio)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ dev->bclk_ratio = ratio;
-+ return 0;
-+}
-+
-+
-+static int bcm2708_i2s_set_function(unsigned offset, int function)
-+{
-+ #define GPIOFSEL(x) (0x00+(x)*4)
-+ void __iomem *gpio = __io_address(GPIO_BASE);
-+ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2;
-+ unsigned gpiodir;
-+ unsigned gpio_bank = offset / 10;
-+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ gpiodir = readl(gpio + GPIOFSEL(gpio_bank));
-+ gpiodir &= ~(7 << gpio_field_offset);
-+ gpiodir |= alt << gpio_field_offset;
-+ writel(gpiodir, gpio + GPIOFSEL(gpio_bank));
-+ return 0;
-+}
-+
-+static void bcm2708_i2s_setup_gpio(void)
-+{
-+ /*
-+ * This is the common way to handle the GPIO pins for
-+ * the Raspberry Pi.
-+ * TODO Better way would be to handle
-+ * this in the device tree!
-+ */
-+ int pin,pinconfig,startpin,alt;
-+
-+ /* SPI is on different GPIOs on different boards */
-+ /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */
-+ if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) {
-+ if ((system_rev & 0xffffff) >= 0x10) {
-+ /* Model B+ */
-+ pinconfig=BCM2708_I2S_GPIO_PIN18;
-+ } else {
-+ /* original */
-+ pinconfig=BCM2708_I2S_GPIO_PIN28;
-+ }
-+ } else {
-+ pinconfig=bcm2708_i2s_gpio;
-+ }
-+
-+ if (pinconfig==BCM2708_I2S_GPIO_PIN18) {
-+ startpin=18;
-+ alt=BCM2708_I2S_GPIO_PIN18_ALT;
-+ } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) {
-+ startpin=28;
-+ alt=BCM2708_I2S_GPIO_PIN28_ALT;
-+ } else {
-+ printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig);
-+ return;
-+ }
-+
-+ /* configure I2S pins to correct ALT mode */
-+ for (pin = startpin; pin <= startpin+3; pin++) {
-+ bcm2708_i2s_set_function(pin, alt);
-+ }
-+}
-+
-+static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ unsigned int sampling_rate = params_rate(params);
-+ unsigned int data_length, data_delay, bclk_ratio;
-+ unsigned int ch1pos, ch2pos, mode, format;
-+ unsigned int mash = BCM2708_CLK_MASH_1;
-+ unsigned int divi, divf, target_frequency;
-+ int clk_src = -1;
-+ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
-+ bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
-+ || master == SND_SOC_DAIFMT_CBS_CFM);
-+
-+ bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
-+ || master == SND_SOC_DAIFMT_CBM_CFS);
-+ uint32_t csreg;
-+
-+ /*
-+ * If a stream is already enabled,
-+ * the registers are already set properly.
-+ */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
-+
-+ if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
-+ return 0;
-+
-+
-+ bcm2708_i2s_setup_gpio();
-+
-+ /*
-+ * Adjust the data length according to the format.
-+ * We prefill the half frame length with an integer
-+ * divider of 2400 as explained at the clock settings.
-+ * Maybe it is overwritten there, if the Integer mode
-+ * does not apply.
-+ */
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ data_length = 16;
-+ bclk_ratio = 50;
-+ break;
-+ case SNDRV_PCM_FORMAT_S24_LE:
-+ data_length = 24;
-+ bclk_ratio = 50;
-+ break;
-+ case SNDRV_PCM_FORMAT_S32_LE:
-+ data_length = 32;
-+ bclk_ratio = 100;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /* If bclk_ratio already set, use that one. */
-+ if (dev->bclk_ratio)
-+ bclk_ratio = dev->bclk_ratio;
-+
-+ /*
-+ * Clock Settings
-+ *
-+ * The target frequency of the bit clock is
-+ * sampling rate * frame length
-+ *
-+ * Integer mode:
-+ * Sampling rates that are multiples of 8000 kHz
-+ * can be driven by the oscillator of 19.2 MHz
-+ * with an integer divider as long as the frame length
-+ * is an integer divider of 19200000/8000=2400 as set up above.
-+ * This is no longer possible if the sampling rate
-+ * is too high (e.g. 192 kHz), because the oscillator is too slow.
-+ *
-+ * MASH mode:
-+ * For all other sampling rates, it is not possible to
-+ * have an integer divider. Approximate the clock
-+ * with the MASH module that induces a slight frequency
-+ * variance. To minimize that it is best to have the fastest
-+ * clock here. That is PLLD with 500 MHz.
-+ */
-+ target_frequency = sampling_rate * bclk_ratio;
-+ clk_src = BCM2708_CLK_SRC_OSC;
-+ mash = BCM2708_CLK_MASH_0;
-+
-+ if (bcm2708_clk_freq[clk_src] % target_frequency == 0
-+ && bit_master && frame_master) {
-+ divi = bcm2708_clk_freq[clk_src] / target_frequency;
-+ divf = 0;
-+ } else {
-+ uint64_t dividend;
-+
-+ if (!dev->bclk_ratio) {
-+ /*
-+ * Overwrite bclk_ratio, because the
-+ * above trick is not needed or can
-+ * not be used.
-+ */
-+ bclk_ratio = 2 * data_length;
-+ }
-+
-+ target_frequency = sampling_rate * bclk_ratio;
-+
-+ clk_src = BCM2708_CLK_SRC_PLLD;
-+ mash = BCM2708_CLK_MASH_1;
-+
-+ dividend = bcm2708_clk_freq[clk_src];
-+ dividend <<= BCM2708_CLK_SHIFT;
-+ do_div(dividend, target_frequency);
-+ divi = dividend >> BCM2708_CLK_SHIFT;
-+ divf = dividend & BCM2708_CLK_DIVF_MASK;
-+ }
-+
-+ /* Set clock divider */
-+ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
-+ | BCM2708_CLK_DIVI(divi)
-+ | BCM2708_CLK_DIVF(divf));
-+
-+ /* Setup clock, but don't start it yet */
-+ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
-+ | BCM2708_CLK_MASH(mash)
-+ | BCM2708_CLK_SRC(clk_src));
-+
-+ /* Setup the frame format */
-+ format = BCM2708_I2S_CHEN;
-+
-+ if (data_length >= 24)
-+ format |= BCM2708_I2S_CHWEX;
-+
-+ format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
-+
-+ switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+ case SND_SOC_DAIFMT_I2S:
-+ data_delay = 1;
-+ break;
-+ default:
-+ /*
-+ * TODO
-+ * Others are possible but are not implemented at the moment.
-+ */
-+ dev_err(dev->dev, "%s:bad format\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ ch1pos = data_delay;
-+ ch2pos = bclk_ratio / 2 + data_delay;
-+
-+ switch (params_channels(params)) {
-+ case 2:
-+ format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
-+ format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
-+ format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * Set format for both streams.
-+ * We cannot set another frame length
-+ * (and therefore word length) anyway,
-+ * so the format will be the same.
-+ */
-+ regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
-+ regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
-+
-+ /* Setup the I2S mode */
-+ mode = 0;
-+
-+ if (data_length <= 16) {
-+ /*
-+ * Use frame packed mode (2 channels per 32 bit word)
-+ * We cannot set another frame length in the second stream
-+ * (and therefore word length) anyway,
-+ * so the format will be the same.
-+ */
-+ mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
-+ }
-+
-+ mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
-+ mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
-+
-+ /* Master or slave? */
-+ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ /* CPU is master */
-+ break;
-+ case SND_SOC_DAIFMT_CBM_CFS:
-+ /*
-+ * CODEC is bit clock master
-+ * CPU is frame master
-+ */
-+ mode |= BCM2708_I2S_CLKM;
-+ break;
-+ case SND_SOC_DAIFMT_CBS_CFM:
-+ /*
-+ * CODEC is frame master
-+ * CPU is bit clock master
-+ */
-+ mode |= BCM2708_I2S_FSM;
-+ break;
-+ case SND_SOC_DAIFMT_CBM_CFM:
-+ /* CODEC is master */
-+ mode |= BCM2708_I2S_CLKM;
-+ mode |= BCM2708_I2S_FSM;
-+ break;
-+ default:
-+ dev_err(dev->dev, "%s:bad master\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * Invert clocks?
-+ *
-+ * The BCM approach seems to be inverted to the classical I2S approach.
-+ */
-+ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
-+ case SND_SOC_DAIFMT_NB_NF:
-+ /* None. Therefore, both for BCM */
-+ mode |= BCM2708_I2S_CLKI;
-+ mode |= BCM2708_I2S_FSI;
-+ break;
-+ case SND_SOC_DAIFMT_IB_IF:
-+ /* Both. Therefore, none for BCM */
-+ break;
-+ case SND_SOC_DAIFMT_NB_IF:
-+ /*
-+ * Invert only frame sync. Therefore,
-+ * invert only bit clock for BCM
-+ */
-+ mode |= BCM2708_I2S_CLKI;
-+ break;
-+ case SND_SOC_DAIFMT_IB_NF:
-+ /*
-+ * Invert only bit clock. Therefore,
-+ * invert only frame sync for BCM
-+ */
-+ mode |= BCM2708_I2S_FSI;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
-+
-+ /* Setup the DMA parameters */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_RXTHR(1)
-+ | BCM2708_I2S_TXTHR(1)
-+ | BCM2708_I2S_DMAEN, 0xffffffff);
-+
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
-+ BCM2708_I2S_TX_PANIC(0x10)
-+ | BCM2708_I2S_RX_PANIC(0x30)
-+ | BCM2708_I2S_TX(0x30)
-+ | BCM2708_I2S_RX(0x20), 0xffffffff);
-+
-+ /* Clear FIFOs */
-+ bcm2708_i2s_clear_fifos(dev, true, true);
-+
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cs_reg;
-+
-+ bcm2708_i2s_start_clock(dev);
-+
-+ /*
-+ * Clear both FIFOs if the one that should be started
-+ * is not empty at the moment. This should only happen
-+ * after overrun. Otherwise, hw_params would have cleared
-+ * the FIFO.
-+ */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
-+ && !(cs_reg & BCM2708_I2S_TXE))
-+ bcm2708_i2s_clear_fifos(dev, true, false);
-+ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
-+ && (cs_reg & BCM2708_I2S_RXD))
-+ bcm2708_i2s_clear_fifos(dev, false, true);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
-+ struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ uint32_t mask;
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-+ mask = BCM2708_I2S_RXON;
-+ else
-+ mask = BCM2708_I2S_TXON;
-+
-+ regmap_update_bits(dev->i2s_regmap,
-+ BCM2708_I2S_CS_A_REG, mask, 0);
-+
-+ /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
-+ if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
-+ bcm2708_i2s_stop_clock(dev);
-+}
-+
-+static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ uint32_t mask;
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+ bcm2708_i2s_start_clock(dev);
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-+ mask = BCM2708_I2S_RXON;
-+ else
-+ mask = BCM2708_I2S_TXON;
-+
-+ regmap_update_bits(dev->i2s_regmap,
-+ BCM2708_I2S_CS_A_REG, mask, mask);
-+ break;
-+
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+ bcm2708_i2s_stop(dev, substream, dai);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ if (dai->active)
-+ return 0;
-+
-+ /* Should this still be running stop it */
-+ bcm2708_i2s_stop_clock(dev);
-+
-+ /* Enable PCM block */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_EN, BCM2708_I2S_EN);
-+
-+ /*
-+ * Disable STBY.
-+ * Requires at least 4 PCM clock cycles to take effect.
-+ */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_STBY, BCM2708_I2S_STBY);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ bcm2708_i2s_stop(dev, substream, dai);
-+
-+ /* If both streams are stopped, disable module and clock */
-+ if (dai->active)
-+ return;
-+
-+ /* Disable the module */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_EN, 0);
-+
-+ /*
-+ * Stopping clock is necessary, because stop does
-+ * not stop the clock when SND_SOC_DAIFMT_CONT
-+ */
-+ bcm2708_i2s_stop_clock(dev);
-+}
-+
-+static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
-+ .startup = bcm2708_i2s_startup,
-+ .shutdown = bcm2708_i2s_shutdown,
-+ .prepare = bcm2708_i2s_prepare,
-+ .trigger = bcm2708_i2s_trigger,
-+ .hw_params = bcm2708_i2s_hw_params,
-+ .set_fmt = bcm2708_i2s_set_dai_fmt,
-+ .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
-+};
-+
-+static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
-+ dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
-+
-+ return 0;
-+}
-+
-+static struct snd_soc_dai_driver bcm2708_i2s_dai = {
-+ .name = "bcm2708-i2s",
-+ .probe = bcm2708_i2s_dai_probe,
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE
-+ | SNDRV_PCM_FMTBIT_S24_LE
-+ | SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+ .capture = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE
-+ | SNDRV_PCM_FMTBIT_S24_LE
-+ | SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+ .ops = &bcm2708_i2s_dai_ops,
-+ .symmetric_rates = 1
-+};
-+
-+static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case BCM2708_I2S_CS_A_REG:
-+ case BCM2708_I2S_FIFO_A_REG:
-+ case BCM2708_I2S_INTSTC_A_REG:
-+ case BCM2708_I2S_GRAY_REG:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case BCM2708_I2S_FIFO_A_REG:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case BCM2708_CLK_PCMCTL_REG:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static const struct regmap_config bcm2708_regmap_config[] = {
-+ {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .max_register = BCM2708_I2S_GRAY_REG,
-+ .precious_reg = bcm2708_i2s_precious_reg,
-+ .volatile_reg = bcm2708_i2s_volatile_reg,
-+ .cache_type = REGCACHE_RBTREE,
-+ .name = "i2s",
-+ },
-+ {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .max_register = BCM2708_CLK_PCMDIV_REG,
-+ .volatile_reg = bcm2708_clk_volatile_reg,
-+ .cache_type = REGCACHE_RBTREE,
-+ .name = "clk",
-+ },
-+};
-+
-+static const struct snd_soc_component_driver bcm2708_i2s_component = {
-+ .name = "bcm2708-i2s-comp",
-+};
-+
-+static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
-+ .info = SNDRV_PCM_INFO_INTERLEAVED |
-+ SNDRV_PCM_INFO_JOINT_DUPLEX,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE |
-+ SNDRV_PCM_FMTBIT_S32_LE,
-+ .period_bytes_min = 32,
-+ .period_bytes_max = 64 * PAGE_SIZE,
-+ .periods_min = 2,
-+ .periods_max = 255,
-+ .buffer_bytes_max = 128 * PAGE_SIZE,
-+};
-+
-+static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
-+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
-+ .pcm_hardware = &bcm2708_pcm_hardware,
-+ .prealloc_buffer_size = 256 * PAGE_SIZE,
-+};
-+
-+
-+static int bcm2708_i2s_probe(struct platform_device *pdev)
-+{
-+ struct bcm2708_i2s_dev *dev;
-+ int i;
-+ int ret;
-+ struct regmap *regmap[2];
-+ struct resource *mem[2];
-+
-+ /* Request both ioareas */
-+ for (i = 0; i <= 1; i++) {
-+ void __iomem *base;
-+
-+ mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
-+ base = devm_ioremap_resource(&pdev->dev, mem[i]);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
-+ &bcm2708_regmap_config[i]);
-+ if (IS_ERR(regmap[i])) {
-+ dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
-+ return PTR_ERR(regmap[i]);
-+ }
-+ }
-+
-+ dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
-+ GFP_KERNEL);
-+ if (IS_ERR(dev))
-+ return PTR_ERR(dev);
-+
-+ dev->i2s_regmap = regmap[0];
-+ dev->clk_regmap = regmap[1];
-+
-+ /* Set the DMA address */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
-+ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
-+
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
-+ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
-+
-+ /* Set the DREQ */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
-+ BCM2708_DMA_DREQ_PCM_TX;
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
-+ BCM2708_DMA_DREQ_PCM_RX;
-+
-+ /* Set the bus width */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
-+ DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
-+ DMA_SLAVE_BUSWIDTH_4_BYTES;
-+
-+ /* Set burst */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
-+
-+ /* BCLK ratio - use default */
-+ dev->bclk_ratio = 0;
-+
-+ /* Store the pdev */
-+ dev->dev = &pdev->dev;
-+ dev_set_drvdata(&pdev->dev, dev);
-+
-+ ret = snd_soc_register_component(&pdev->dev,
-+ &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
-+
-+ if (ret) {
-+ dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
-+ ret = -ENOMEM;
-+ return ret;
-+ }
-+
-+ ret = snd_dmaengine_pcm_register(&pdev->dev,
-+ &bcm2708_dmaengine_pcm_config,
-+ SND_DMAENGINE_PCM_FLAG_COMPAT);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
-+ snd_soc_unregister_component(&pdev->dev);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_remove(struct platform_device *pdev)
-+{
-+ snd_dmaengine_pcm_unregister(&pdev->dev);
-+ snd_soc_unregister_component(&pdev->dev);
-+ return 0;
-+}
-+
-+static struct platform_driver bcm2708_i2s_driver = {
-+ .probe = bcm2708_i2s_probe,
-+ .remove = bcm2708_i2s_remove,
-+ .driver = {
-+ .name = "bcm2708-i2s",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+module_platform_driver(bcm2708_i2s_driver);
-+
-+MODULE_ALIAS("platform:bcm2708-i2s");
-+MODULE_DESCRIPTION("BCM2708 I2S interface");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/bcm/bcm2708-i2s.h linux-rpi/sound/soc/bcm/bcm2708-i2s.h
---- linux-3.12.38/sound/soc/bcm/bcm2708-i2s.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/bcm2708-i2s.h 2015-03-09 10:39:38.554893685 +0100
-@@ -0,0 +1,35 @@
-+/*
-+ * I2S configuration for sound cards.
-+ *
-+ * Copyright (c) 2014 Daniel Matuschek <daniel@hifiberry.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef BCM2708_I2S_H
-+#define BCM2708_I2S_H
-+
-+/* I2S pin assignment */
-+#define BCM2708_I2S_GPIO_AUTO 0
-+#define BCM2708_I2S_GPIO_PIN18 1
-+#define BCM2708_I2S_GPIO_PIN28 2
-+
-+/* Alt mode to enable I2S */
-+#define BCM2708_I2S_GPIO_PIN18_ALT 0
-+#define BCM2708_I2S_GPIO_PIN28_ALT 2
-+
-+extern void bcm2708_i2s_set_gpio(int gpio);
-+
-+#endif
-diff -Nur linux-3.12.38/sound/soc/bcm/hifiberry_amp.c linux-rpi/sound/soc/bcm/hifiberry_amp.c
---- linux-3.12.38/sound/soc/bcm/hifiberry_amp.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/hifiberry_amp.c 2015-03-10 17:26:51.930216684 +0100
-@@ -0,0 +1,106 @@
-+/*
-+ * ASoC Driver for HifiBerry AMP
-+ *
-+ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ * Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ // ToDo: init of the dsp-registers.
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params )
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = {
-+ .hw_params = snd_rpi_hifiberry_amp_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = {
-+ {
-+ .name = "HifiBerry AMP",
-+ .stream_name = "HifiBerry AMP HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "tas5713-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "tas5713.1-001b",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S |
-+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_hifiberry_amp_ops,
-+ .init = snd_rpi_hifiberry_amp_init,
-+ },
-+};
-+
-+
-+static struct snd_soc_card snd_rpi_hifiberry_amp = {
-+ .name = "snd_rpi_hifiberry_amp",
-+ .dai_link = snd_rpi_hifiberry_amp_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai),
-+};
-+
-+
-+static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_amp.dev = &pdev->dev;
-+
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_amp);
-+
-+ if (ret != 0) {
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+ }
-+
-+ return ret;
-+}
-+
-+
-+static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_amp);
-+}
-+
-+
-+static struct platform_driver snd_rpi_hifiberry_amp_driver = {
-+ .driver = {
-+ .name = "snd-hifiberry-amp",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = snd_rpi_hifiberry_amp_probe,
-+ .remove = snd_rpi_hifiberry_amp_remove,
-+};
-+
-+
-+module_platform_driver(snd_rpi_hifiberry_amp_driver);
-+
-+
-+MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
-+MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/bcm/hifiberry_dac.c linux-rpi/sound/soc/bcm/hifiberry_dac.c
---- linux-3.12.38/sound/soc/bcm/hifiberry_dac.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/hifiberry_dac.c 2015-03-10 17:26:51.930216684 +0100
-@@ -0,0 +1,100 @@
-+/*
-+ * ASoC Driver for HifiBerry DAC
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ unsigned int sample_bits =
-+ snd_pcm_format_physical_width(params_format(params));
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = {
-+ .hw_params = snd_rpi_hifiberry_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = {
-+{
-+ .name = "HifiBerry DAC",
-+ .stream_name = "HifiBerry DAC HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm5102a-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm5102a-codec",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_hifiberry_dac_ops,
-+ .init = snd_rpi_hifiberry_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_dac = {
-+ .name = "snd_rpi_hifiberry_dac",
-+ .dai_link = snd_rpi_hifiberry_dac_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai),
-+};
-+
-+static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_dac.dev = &pdev->dev;
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_dac);
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_dac);
-+}
-+
-+static struct platform_driver snd_rpi_hifiberry_dac_driver = {
-+ .driver = {
-+ .name = "snd-hifiberry-dac",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = snd_rpi_hifiberry_dac_probe,
-+ .remove = snd_rpi_hifiberry_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/bcm/hifiberry_dacplus.c linux-rpi/sound/soc/bcm/hifiberry_dacplus.c
---- linux-3.12.38/sound/soc/bcm/hifiberry_dacplus.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/hifiberry_dacplus.c 2015-03-10 17:26:51.930216684 +0100
-@@ -0,0 +1,119 @@
-+/*
-+ * ASoC Driver for HiFiBerry DAC+
-+ *
-+ * Author: Daniel Matuschek
-+ * Copyright 2014
-+ * based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/pcm512x.h"
-+
-+static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
-+ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
-+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_startup(struct snd_pcm_substream *substream) {
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+ return 0;
-+}
-+
-+static void snd_rpi_hifiberry_dacplus_shutdown(struct snd_pcm_substream *substream) {
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = {
-+ .hw_params = snd_rpi_hifiberry_dacplus_hw_params,
-+ .startup = snd_rpi_hifiberry_dacplus_startup,
-+ .shutdown = snd_rpi_hifiberry_dacplus_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = {
-+{
-+ .name = "HiFiBerry DAC+",
-+ .stream_name = "HiFiBerry DAC+ HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm512x-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm512x.1-004d",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_hifiberry_dacplus_ops,
-+ .init = snd_rpi_hifiberry_dacplus_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_dacplus = {
-+ .name = "snd_rpi_hifiberry_dacplus",
-+ .dai_link = snd_rpi_hifiberry_dacplus_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai),
-+};
-+
-+static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_dacplus.dev = &pdev->dev;
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus);
-+ if (ret)
-+ dev_err(&pdev->dev,
-+ "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus);
-+}
-+
-+static struct platform_driver snd_rpi_hifiberry_dacplus_driver = {
-+ .driver = {
-+ .name = "snd-rpi-hifiberry-dacplus",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = snd_rpi_hifiberry_dacplus_probe,
-+ .remove = snd_rpi_hifiberry_dacplus_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_dacplus_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <daniel@hifiberry.com>");
-+MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/bcm/hifiberry_digi.c linux-rpi/sound/soc/bcm/hifiberry_digi.c
---- linux-3.12.38/sound/soc/bcm/hifiberry_digi.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/hifiberry_digi.c 2015-03-10 17:26:51.930216684 +0100
-@@ -0,0 +1,153 @@
-+/*
-+ * ASoC Driver for HifiBerry Digi
-+ *
-+ * Author: Daniel Matuschek <info@crazy-audio.com>
-+ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8804.h"
-+
-+static int samplerate=44100;
-+
-+static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ struct snd_soc_codec *codec = rtd->codec;
-+
-+ /* enable TX output */
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ int sysclk = 27000000; /* This is fixed on this board */
-+
-+ long mclk_freq=0;
-+ int mclk_div=1;
-+
-+ int ret;
-+
-+ samplerate = params_rate(params);
-+
-+ switch (samplerate) {
-+ case 44100:
-+ case 48000:
-+ case 88200:
-+ case 96000:
-+ mclk_freq=samplerate*256;
-+ mclk_div=WM8804_MCLKDIV_256FS;
-+ break;
-+ case 176400:
-+ case 192000:
-+ mclk_freq=samplerate*128;
-+ mclk_div=WM8804_MCLKDIV_128FS;
-+ break;
-+ default:
-+ dev_err(substream->pcm->dev,
-+ "Failed to set WM8804 SYSCLK, unsupported samplerate\n");
-+ }
-+
-+ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+ sysclk, SND_SOC_CLOCK_OUT);
-+ if (ret < 0) {
-+ dev_err(substream->pcm->dev,
-+ "Failed to set WM8804 SYSCLK: %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Enable TX output */
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+ /* Power on */
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai,64);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = {
-+ .hw_params = snd_rpi_hifiberry_digi_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = {
-+{
-+ .name = "HifiBerry Digi",
-+ .stream_name = "HifiBerry Digi HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "wm8804-spdif",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "wm8804.1-003b",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBM_CFM,
-+ .ops = &snd_rpi_hifiberry_digi_ops,
-+ .init = snd_rpi_hifiberry_digi_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_digi = {
-+ .name = "snd_rpi_hifiberry_digi",
-+ .dai_link = snd_rpi_hifiberry_digi_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai),
-+};
-+
-+static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_digi.dev = &pdev->dev;
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_digi);
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_digi);
-+}
-+
-+static struct platform_driver snd_rpi_hifiberry_digi_driver = {
-+ .driver = {
-+ .name = "snd-hifiberry-digi",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = snd_rpi_hifiberry_digi_probe,
-+ .remove = snd_rpi_hifiberry_digi_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_digi_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <info@crazy-audio.com>");
-+MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/bcm/iqaudio-dac.c linux-rpi/sound/soc/bcm/iqaudio-dac.c
---- linux-3.12.38/sound/soc/bcm/iqaudio-dac.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/iqaudio-dac.c 2015-03-10 17:26:51.930216684 +0100
-@@ -0,0 +1,111 @@
-+/*
-+ * ASoC Driver for IQaudIO DAC
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+// NOT USED struct snd_soc_codec *codec = rtd->codec;
-+
-+ return 0;
-+}
-+
-+static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+// NOT USED struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+// NOT USED struct snd_soc_codec *codec = rtd->codec;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ unsigned int sample_bits =
-+ snd_pcm_format_physical_width(params_format(params));
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = {
-+ .hw_params = snd_rpi_iqaudio_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {
-+{
-+ .name = "IQaudIO DAC",
-+ .stream_name = "IQaudIO DAC HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm512x-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm512x.1-004c",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_iqaudio_dac_ops,
-+ .init = snd_rpi_iqaudio_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_iqaudio_dac = {
-+ .name = "snd_rpi_iqaudio_dac",
-+ .dai_link = snd_rpi_iqaudio_dac_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai),
-+};
-+
-+static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_iqaudio_dac.dev = &pdev->dev;
-+ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac);
-+ if (ret)
-+ dev_err(&pdev->dev,
-+ "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_iqaudio_dac);
-+}
-+
-+static const struct of_device_id iqaudio_of_match[] = {
-+ { .compatible = "iqaudio,iqaudio-dac", },
-+ {},
-+};
-+
-+static struct platform_driver snd_rpi_iqaudio_dac_driver = {
-+ .driver = {
-+ .name = "snd-rpi-iqaudio-dac",
-+ .owner = THIS_MODULE,
-+ .of_match_table = iqaudio_of_match,
-+ },
-+ .probe = snd_rpi_iqaudio_dac_probe,
-+ .remove = snd_rpi_iqaudio_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_iqaudio_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/bcm/Kconfig linux-rpi/sound/soc/bcm/Kconfig
---- linux-3.12.38/sound/soc/bcm/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/Kconfig 2015-03-10 17:26:51.926216684 +0100
-@@ -0,0 +1,52 @@
-+config SND_BCM2708_SOC_I2S
-+ tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
-+ depends on MACH_BCM2708
-+ select REGMAP_MMIO
-+ select SND_SOC_DMAENGINE_PCM
-+ select SND_SOC_GENERIC_DMAENGINE_PCM
-+ help
-+ Say Y or M if you want to add support for codecs attached to
-+ the BCM2708 I2S interface. You will also need
-+ to select the audio interfaces to support below.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DAC
-+ tristate "Support for HifiBerry DAC"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM5102A
-+ help
-+ Say Y or M if you want to add support for HifiBerry DAC.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DACPLUS
-+ tristate "Support for HifiBerry DAC+"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM512x
-+ help
-+ Say Y or M if you want to add support for HifiBerry DAC+.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DIGI
-+ tristate "Support for HifiBerry Digi"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_WM8804
-+ help
-+ Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_AMP
-+ tristate "Support for the HifiBerry Amp"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_TAS5713
-+ help
-+ Say Y or M if you want to add support for the HifiBerry Amp amplifier board.
-+
-+config SND_BCM2708_SOC_RPI_DAC
-+ tristate "Support for RPi-DAC"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM1794A
-+ help
-+ Say Y or M if you want to add support for RPi-DAC.
-+
-+config SND_BCM2708_SOC_IQAUDIO_DAC
-+ tristate "Support for IQaudIO-DAC"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM512x
-+ help
-+ Say Y or M if you want to add support for IQaudIO-DAC.
-diff -Nur linux-3.12.38/sound/soc/bcm/Makefile linux-rpi/sound/soc/bcm/Makefile
---- linux-3.12.38/sound/soc/bcm/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/Makefile 2015-03-10 17:26:51.926216684 +0100
-@@ -0,0 +1,19 @@
-+# BCM2708 Platform Support
-+snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
-+
-+obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
-+
-+# BCM2708 Machine Support
-+snd-soc-hifiberry-dac-objs := hifiberry_dac.o
-+snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
-+snd-soc-hifiberry-digi-objs := hifiberry_digi.o
-+snd-soc-hifiberry-amp-objs := hifiberry_amp.o
-+snd-soc-rpi-dac-objs := rpi-dac.o
-+snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-+
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
-diff -Nur linux-3.12.38/sound/soc/bcm/rpi-dac.c linux-rpi/sound/soc/bcm/rpi-dac.c
---- linux-3.12.38/sound/soc/bcm/rpi-dac.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/bcm/rpi-dac.c 2015-03-09 10:39:38.554893685 +0100
-@@ -0,0 +1,97 @@
-+/*
-+ * ASoC Driver for RPi-DAC.
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ return 0;
-+}
-+
-+static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_rpi_dac_ops = {
-+ .hw_params = snd_rpi_rpi_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = {
-+{
-+ .name = "RPi-DAC",
-+ .stream_name = "RPi-DAC HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm1794a-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm1794a-codec",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_rpi_dac_ops,
-+ .init = snd_rpi_rpi_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_rpi_dac = {
-+ .name = "snd_rpi_rpi_dac",
-+ .dai_link = snd_rpi_rpi_dac_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_rpi_dac_dai),
-+};
-+
-+static int snd_rpi_rpi_dac_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_rpi_dac.dev = &pdev->dev;
-+ ret = snd_soc_register_card(&snd_rpi_rpi_dac);
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_rpi_dac_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_rpi_dac);
-+}
-+
-+static struct platform_driver snd_rpi_rpi_dac_driver = {
-+ .driver = {
-+ .name = "snd-rpi-dac",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = snd_rpi_rpi_dac_probe,
-+ .remove = snd_rpi_rpi_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_rpi_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for RPi-DAC");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/codecs/Kconfig linux-rpi/sound/soc/codecs/Kconfig
---- linux-3.12.38/sound/soc/codecs/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/Kconfig 2015-03-10 17:26:51.930216684 +0100
-@@ -59,6 +59,9 @@
- select SND_SOC_PCM1681 if I2C
- select SND_SOC_PCM1792A if SPI_MASTER
- select SND_SOC_PCM3008
-+ select SND_SOC_PCM1794A
-+ select SND_SOC_PCM5102A
-+ select SND_SOC_PCM512x if SND_SOC_I2C_AND_SPI
- select SND_SOC_RT5631 if I2C
- select SND_SOC_RT5640 if I2C
- select SND_SOC_SGTL5000 if I2C
-@@ -71,6 +74,7 @@
- select SND_SOC_STA529 if I2C
- select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
- select SND_SOC_TAS5086 if I2C
-+ select SND_SOC_TAS5713 if I2C
- select SND_SOC_TLV320AIC23 if I2C
- select SND_SOC_TLV320AIC26 if SPI_MASTER
- select SND_SOC_TLV320AIC32X4 if I2C
-@@ -311,6 +315,15 @@
- config SND_SOC_PCM3008
- tristate
-
-+config SND_SOC_PCM1794A
-+ tristate
-+
-+config SND_SOC_PCM5102A
-+ tristate
-+
-+config SND_SOC_PCM512x
-+ tristate
-+
- config SND_SOC_RT5631
- tristate
-
-@@ -352,6 +365,9 @@
- config SND_SOC_TAS5086
- tristate
-
-+config SND_SOC_TAS5713
-+ tristate
-+
- config SND_SOC_TLV320AIC23
- tristate
-
-diff -Nur linux-3.12.38/sound/soc/codecs/Makefile linux-rpi/sound/soc/codecs/Makefile
---- linux-3.12.38/sound/soc/codecs/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/Makefile 2015-03-10 17:26:51.930216684 +0100
-@@ -46,6 +46,9 @@
- snd-soc-pcm1681-objs := pcm1681.o
- snd-soc-pcm1792a-codec-objs := pcm1792a.o
- snd-soc-pcm3008-objs := pcm3008.o
-+snd-soc-pcm1794a-objs := pcm1794a.o
-+snd-soc-pcm5102a-objs := pcm5102a.o
-+snd-soc-pcm512x-objs := pcm512x.o
- snd-soc-rt5631-objs := rt5631.o
- snd-soc-rt5640-objs := rt5640.o
- snd-soc-sgtl5000-objs := sgtl5000.o
-@@ -62,6 +65,7 @@
- snd-soc-sta529-objs := sta529.o
- snd-soc-stac9766-objs := stac9766.o
- snd-soc-tas5086-objs := tas5086.o
-+snd-soc-tas5713-objs := tas5713.o
- snd-soc-tlv320aic23-objs := tlv320aic23.o
- snd-soc-tlv320aic26-objs := tlv320aic26.o
- snd-soc-tlv320aic3x-objs := tlv320aic3x.o
-@@ -179,6 +183,9 @@
- obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o
- obj-$(CONFIG_SND_SOC_PCM1792A) += snd-soc-pcm1792a-codec.o
- obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
-+obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o
-+obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o
-+obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
- obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
- obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
- obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
-@@ -192,6 +199,7 @@
- obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o
- obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
- obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
-+obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
- obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o
- obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
-diff -Nur linux-3.12.38/sound/soc/codecs/max98090.c linux-rpi/sound/soc/codecs/max98090.c
---- linux-3.12.38/sound/soc/codecs/max98090.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/max98090.c 2015-03-10 17:26:51.934216684 +0100
-@@ -1378,8 +1378,8 @@
- {"STENL Mux", "Sidetone Left", "DMICL"},
- {"STENR Mux", "Sidetone Right", "ADCR"},
- {"STENR Mux", "Sidetone Right", "DMICR"},
-- {"DACL", NULL, "STENL Mux"},
-- {"DACR", NULL, "STENL Mux"},
-+ {"DACL", "NULL", "STENL Mux"},
-+ {"DACR", "NULL", "STENL Mux"},
-
- {"AIFINL", NULL, "SHDN"},
- {"AIFINR", NULL, "SHDN"},
-diff -Nur linux-3.12.38/sound/soc/codecs/pcm1794a.c linux-rpi/sound/soc/codecs/pcm1794a.c
---- linux-3.12.38/sound/soc/codecs/pcm1794a.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/pcm1794a.c 2015-03-09 10:39:38.566893685 +0100
-@@ -0,0 +1,62 @@
-+/*
-+ * Driver for the PCM1794A codec
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/soc.h>
-+
-+static struct snd_soc_dai_driver pcm1794a_dai = {
-+ .name = "pcm1794a-hifi",
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE
-+ },
-+};
-+
-+static struct snd_soc_codec_driver soc_codec_dev_pcm1794a;
-+
-+static int pcm1794a_probe(struct platform_device *pdev)
-+{
-+ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a,
-+ &pcm1794a_dai, 1);
-+}
-+
-+static int pcm1794a_remove(struct platform_device *pdev)
-+{
-+ snd_soc_unregister_codec(&pdev->dev);
-+ return 0;
-+}
-+
-+static struct platform_driver pcm1794a_codec_driver = {
-+ .probe = pcm1794a_probe,
-+ .remove = pcm1794a_remove,
-+ .driver = {
-+ .name = "pcm1794a-codec",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+module_platform_driver(pcm1794a_codec_driver);
-+
-+MODULE_DESCRIPTION("ASoC PCM1794A codec driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/codecs/pcm5102a.c linux-rpi/sound/soc/codecs/pcm5102a.c
---- linux-3.12.38/sound/soc/codecs/pcm5102a.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/pcm5102a.c 2015-03-10 17:26:51.938216684 +0100
-@@ -0,0 +1,63 @@
-+/*
-+ * Driver for the PCM5102A codec
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/soc.h>
-+
-+static struct snd_soc_dai_driver pcm5102a_dai = {
-+ .name = "pcm5102a-hifi",
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE |
-+ SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+};
-+
-+static struct snd_soc_codec_driver soc_codec_dev_pcm5102a;
-+
-+static int pcm5102a_probe(struct platform_device *pdev)
-+{
-+ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm5102a,
-+ &pcm5102a_dai, 1);
-+}
-+
-+static int pcm5102a_remove(struct platform_device *pdev)
-+{
-+ snd_soc_unregister_codec(&pdev->dev);
-+ return 0;
-+}
-+
-+static struct platform_driver pcm5102a_codec_driver = {
-+ .probe = pcm5102a_probe,
-+ .remove = pcm5102a_remove,
-+ .driver = {
-+ .name = "pcm5102a-codec",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+module_platform_driver(pcm5102a_codec_driver);
-+
-+MODULE_DESCRIPTION("ASoC PCM5102A codec driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/codecs/pcm512x.c linux-rpi/sound/soc/codecs/pcm512x.c
---- linux-3.12.38/sound/soc/codecs/pcm512x.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/pcm512x.c 2015-03-10 17:26:51.938216684 +0100
-@@ -0,0 +1,678 @@
-+/*
-+ * Driver for the PCM512x CODECs
-+ *
-+ * Author: Mark Brown <broonie@linaro.org>
-+ * Copyright 2014 Linaro Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/i2c.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/spi/spi.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/tlv.h>
-+
-+#include "pcm512x.h"
-+
-+#define PCM512x_NUM_SUPPLIES 3
-+static const char *pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
-+ "AVDD",
-+ "DVDD",
-+ "CPVDD",
-+};
-+
-+struct pcm512x_priv {
-+ struct regmap *regmap;
-+ struct clk *sclk;
-+ struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
-+ struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
-+};
-+
-+/*
-+ * We can't use the same notifier block for more than one supply and
-+ * there's no way I can see to get from a callback to the caller
-+ * except container_of().
-+ */
-+#define PCM512x_REGULATOR_EVENT(n) \
-+static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
-+ unsigned long event, void *data) \
-+{ \
-+ struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
-+ supply_nb[n]); \
-+ if (event & REGULATOR_EVENT_DISABLE) { \
-+ regcache_mark_dirty(pcm512x->regmap); \
-+ regcache_cache_only(pcm512x->regmap, true); \
-+ } \
-+ return 0; \
-+}
-+
-+PCM512x_REGULATOR_EVENT(0)
-+PCM512x_REGULATOR_EVENT(1)
-+PCM512x_REGULATOR_EVENT(2)
-+
-+static const struct reg_default pcm512x_reg_defaults[] = {
-+ { PCM512x_RESET, 0x00 },
-+ { PCM512x_POWER, 0x00 },
-+ { PCM512x_MUTE, 0x00 },
-+ { PCM512x_DSP, 0x00 },
-+ { PCM512x_PLL_REF, 0x00 },
-+ { PCM512x_DAC_ROUTING, 0x11 },
-+ { PCM512x_DSP_PROGRAM, 0x01 },
-+ { PCM512x_CLKDET, 0x00 },
-+ { PCM512x_AUTO_MUTE, 0x00 },
-+ { PCM512x_ERROR_DETECT, 0x00 },
-+ { PCM512x_DIGITAL_VOLUME_1, 0x00 },
-+ { PCM512x_DIGITAL_VOLUME_2, 0x30 },
-+ { PCM512x_DIGITAL_VOLUME_3, 0x30 },
-+ { PCM512x_DIGITAL_MUTE_1, 0x22 },
-+ { PCM512x_DIGITAL_MUTE_2, 0x00 },
-+ { PCM512x_DIGITAL_MUTE_3, 0x07 },
-+};
-+
-+static bool pcm512x_readable(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case PCM512x_RESET:
-+ case PCM512x_POWER:
-+ case PCM512x_MUTE:
-+ case PCM512x_PLL_EN:
-+ case PCM512x_SPI_MISO_FUNCTION:
-+ case PCM512x_DSP:
-+ case PCM512x_GPIO_EN:
-+ case PCM512x_BCLK_LRCLK_CFG:
-+ case PCM512x_DSP_GPIO_INPUT:
-+ case PCM512x_MASTER_MODE:
-+ case PCM512x_PLL_REF:
-+ case PCM512x_PLL_COEFF_0:
-+ case PCM512x_PLL_COEFF_1:
-+ case PCM512x_PLL_COEFF_2:
-+ case PCM512x_PLL_COEFF_3:
-+ case PCM512x_PLL_COEFF_4:
-+ case PCM512x_DSP_CLKDIV:
-+ case PCM512x_DAC_CLKDIV:
-+ case PCM512x_NCP_CLKDIV:
-+ case PCM512x_OSR_CLKDIV:
-+ case PCM512x_MASTER_CLKDIV_1:
-+ case PCM512x_MASTER_CLKDIV_2:
-+ case PCM512x_FS_SPEED_MODE:
-+ case PCM512x_IDAC_1:
-+ case PCM512x_IDAC_2:
-+ case PCM512x_ERROR_DETECT:
-+ case PCM512x_I2S_1:
-+ case PCM512x_I2S_2:
-+ case PCM512x_DAC_ROUTING:
-+ case PCM512x_DSP_PROGRAM:
-+ case PCM512x_CLKDET:
-+ case PCM512x_AUTO_MUTE:
-+ case PCM512x_DIGITAL_VOLUME_1:
-+ case PCM512x_DIGITAL_VOLUME_2:
-+ case PCM512x_DIGITAL_VOLUME_3:
-+ case PCM512x_DIGITAL_MUTE_1:
-+ case PCM512x_DIGITAL_MUTE_2:
-+ case PCM512x_DIGITAL_MUTE_3:
-+ case PCM512x_GPIO_OUTPUT_1:
-+ case PCM512x_GPIO_OUTPUT_2:
-+ case PCM512x_GPIO_OUTPUT_3:
-+ case PCM512x_GPIO_OUTPUT_4:
-+ case PCM512x_GPIO_OUTPUT_5:
-+ case PCM512x_GPIO_OUTPUT_6:
-+ case PCM512x_GPIO_CONTROL_1:
-+ case PCM512x_GPIO_CONTROL_2:
-+ case PCM512x_OVERFLOW:
-+ case PCM512x_RATE_DET_1:
-+ case PCM512x_RATE_DET_2:
-+ case PCM512x_RATE_DET_3:
-+ case PCM512x_RATE_DET_4:
-+ case PCM512x_ANALOG_MUTE_DET:
-+ case PCM512x_GPIN:
-+ case PCM512x_DIGITAL_MUTE_DET:
-+ return true;
-+ default:
-+ return false;
-+ }
-+}
-+
-+static bool pcm512x_volatile(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case PCM512x_PLL_EN:
-+ case PCM512x_OVERFLOW:
-+ case PCM512x_RATE_DET_1:
-+ case PCM512x_RATE_DET_2:
-+ case PCM512x_RATE_DET_3:
-+ case PCM512x_RATE_DET_4:
-+ case PCM512x_ANALOG_MUTE_DET:
-+ case PCM512x_GPIN:
-+ case PCM512x_DIGITAL_MUTE_DET:
-+ return true;
-+ default:
-+ return false;
-+ }
-+}
-+
-+static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
-+
-+static const char *pcm512x_dsp_program_texts[] = {
-+ "FIR interpolation with de-emphasis",
-+ "Low latency IIR with de-emphasis",
-+ "High attenuation with de-emphasis",
-+ "Ringing-less low latency FIR",
-+};
-+
-+static const unsigned int pcm512x_dsp_program_values[] = {
-+ 1,
-+ 2,
-+ 3,
-+ 5,
-+ 7,
-+};
-+
-+static const SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
-+ PCM512x_DSP_PROGRAM, 0, 0x1f,
-+ pcm512x_dsp_program_texts,
-+ pcm512x_dsp_program_values);
-+
-+static const char *pcm512x_clk_missing_text[] = {
-+ "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
-+};
-+
-+static const struct soc_enum pcm512x_clk_missing =
-+ SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 7, pcm512x_clk_missing_text);
-+
-+static const char *pcm512x_autom_text[] = {
-+ "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
-+};
-+
-+static const struct soc_enum pcm512x_autom_l =
-+ SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 7,
-+ pcm512x_autom_text);
-+
-+static const struct soc_enum pcm512x_autom_r =
-+ SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 7,
-+ pcm512x_autom_text);
-+
-+static const char *pcm512x_ramp_rate_text[] = {
-+ "1 sample/update", "2 samples/update", "4 samples/update",
-+ "Immediate"
-+};
-+
-+static const struct soc_enum pcm512x_vndf =
-+ SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
-+ pcm512x_ramp_rate_text);
-+
-+static const struct soc_enum pcm512x_vnuf =
-+ SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
-+ pcm512x_ramp_rate_text);
-+
-+static const struct soc_enum pcm512x_vedf =
-+ SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
-+ pcm512x_ramp_rate_text);
-+
-+static const char *pcm512x_ramp_step_text[] = {
-+ "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
-+};
-+
-+static const struct soc_enum pcm512x_vnds =
-+ SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
-+ pcm512x_ramp_step_text);
-+
-+static const struct soc_enum pcm512x_vnus =
-+ SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
-+ pcm512x_ramp_step_text);
-+
-+static const struct soc_enum pcm512x_veds =
-+ SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
-+ pcm512x_ramp_step_text);
-+
-+/* Don't let the DAC go into clipping by limiting the alsa volume control range */
-+static const struct snd_kcontrol_new pcm512x_controls[] = {
-+SOC_DOUBLE_R_RANGE_TLV("Playback Digital Volume", PCM512x_DIGITAL_VOLUME_2,
-+ PCM512x_DIGITAL_VOLUME_3, 0, 40, 255, 1, digital_tlv),
-+SOC_DOUBLE("Playback Digital Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
-+ PCM512x_RQMR_SHIFT, 1, 1),
-+
-+SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
-+SOC_VALUE_ENUM("DSP Program", pcm512x_dsp_program),
-+
-+SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
-+SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
-+SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
-+SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
-+ PCM512x_ACTL_SHIFT, 1, 0),
-+SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
-+ PCM512x_AMLR_SHIFT, 1, 0),
-+
-+SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
-+SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
-+SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
-+SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
-+SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
-+SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
-+};
-+
-+static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
-+SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
-+SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
-+
-+SND_SOC_DAPM_OUTPUT("OUTL"),
-+SND_SOC_DAPM_OUTPUT("OUTR"),
-+};
-+
-+static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
-+ { "DACL", NULL, "Playback" },
-+ { "DACR", NULL, "Playback" },
-+
-+ { "OUTL", NULL, "DACL" },
-+ { "OUTR", NULL, "DACR" },
-+};
-+
-+static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
-+ enum snd_soc_bias_level level)
-+{
-+ struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev);
-+ int ret;
-+
-+ switch (level) {
-+ case SND_SOC_BIAS_ON:
-+ case SND_SOC_BIAS_PREPARE:
-+ break;
-+
-+ case SND_SOC_BIAS_STANDBY:
-+ ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
-+ PCM512x_RQST, 0);
-+ if (ret != 0) {
-+ dev_err(codec->dev, "Failed to remove standby: %d\n",
-+ ret);
-+ return ret;
-+ }
-+ break;
-+
-+ case SND_SOC_BIAS_OFF:
-+ ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
-+ PCM512x_RQST, PCM512x_RQST);
-+ if (ret != 0) {
-+ dev_err(codec->dev, "Failed to request standby: %d\n",
-+ ret);
-+ return ret;
-+ }
-+ break;
-+ }
-+
-+ codec->dapm.bias_level = level;
-+
-+ return 0;
-+}
-+
-+static struct snd_soc_dai_driver pcm512x_dai = {
-+ .name = "pcm512x-hifi",
-+ .playback = {
-+ .stream_name = "Playback",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE |
-+ SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+};
-+
-+static struct snd_soc_codec_driver pcm512x_codec_driver = {
-+ .set_bias_level = pcm512x_set_bias_level,
-+ .idle_bias_off = true,
-+
-+ .controls = pcm512x_controls,
-+ .num_controls = ARRAY_SIZE(pcm512x_controls),
-+ .dapm_widgets = pcm512x_dapm_widgets,
-+ .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
-+ .dapm_routes = pcm512x_dapm_routes,
-+ .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
-+};
-+
-+static const struct regmap_config pcm512x_regmap = {
-+ .reg_bits = 8,
-+ .val_bits = 8,
-+
-+ .readable_reg = pcm512x_readable,
-+ .volatile_reg = pcm512x_volatile,
-+
-+ .max_register = PCM512x_MAX_REGISTER,
-+ .reg_defaults = pcm512x_reg_defaults,
-+ .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
-+ .cache_type = REGCACHE_RBTREE,
-+};
-+
-+static const struct of_device_id pcm512x_of_match[] = {
-+ { .compatible = "ti,pcm5121", },
-+ { .compatible = "ti,pcm5122", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, pcm512x_of_match);
-+
-+static int pcm512x_probe(struct device *dev, struct regmap *regmap)
-+{
-+ struct pcm512x_priv *pcm512x;
-+ int i, ret;
-+
-+ pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
-+ if (!pcm512x)
-+ return -ENOMEM;
-+
-+ dev_set_drvdata(dev, pcm512x);
-+ pcm512x->regmap = regmap;
-+
-+ for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
-+ pcm512x->supplies[i].supply = pcm512x_supply_names[i];
-+
-+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
-+ pcm512x->supplies);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to get supplies: %d\n", ret);
-+ return ret;
-+ }
-+
-+ pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
-+ pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
-+ pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
-+
-+ for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
-+ ret = regulator_register_notifier(pcm512x->supplies[i].consumer,
-+ &pcm512x->supply_nb[i]);
-+ if (ret != 0) {
-+ dev_err(dev,
-+ "Failed to register regulator notifier: %d\n",
-+ ret);
-+ }
-+ }
-+
-+ ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
-+ pcm512x->supplies);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to enable supplies: %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Reset the device, verifying I/O in the process for I2C */
-+ ret = regmap_write(regmap, PCM512x_RESET,
-+ PCM512x_RSTM | PCM512x_RSTR);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to reset device: %d\n", ret);
-+ goto err;
-+ }
-+
-+ ret = regmap_write(regmap, PCM512x_RESET, 0);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to reset device: %d\n", ret);
-+ goto err;
-+ }
-+
-+ pcm512x->sclk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(pcm512x->sclk)) {
-+ if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+
-+ dev_info(dev, "No SCLK, using BCLK: %ld\n",
-+ PTR_ERR(pcm512x->sclk));
-+
-+ /* Disable reporting of missing SCLK as an error */
-+ regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
-+ PCM512x_IDCH, PCM512x_IDCH);
-+
-+ /* Switch PLL input to BCLK */
-+ regmap_update_bits(regmap, PCM512x_PLL_REF,
-+ PCM512x_SREF, PCM512x_SREF);
-+ } else {
-+ ret = clk_prepare_enable(pcm512x->sclk);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to enable SCLK: %d\n", ret);
-+ return ret;
-+ }
-+ }
-+
-+ /* Default to standby mode */
-+ ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
-+ PCM512x_RQST, PCM512x_RQST);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to request standby: %d\n",
-+ ret);
-+ goto err_clk;
-+ }
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ pm_runtime_idle(dev);
-+
-+ ret = snd_soc_register_codec(dev, &pcm512x_codec_driver,
-+ &pcm512x_dai, 1);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to register CODEC: %d\n", ret);
-+ goto err_pm;
-+ }
-+
-+ dev_info(dev, "Completed initialisation - pcm512x_probe");
-+
-+ return 0;
-+
-+err_pm:
-+ pm_runtime_disable(dev);
-+err_clk:
-+ if (!IS_ERR(pcm512x->sclk))
-+ clk_disable_unprepare(pcm512x->sclk);
-+err:
-+ regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
-+ pcm512x->supplies);
-+ return ret;
-+}
-+
-+static void pcm512x_remove(struct device *dev)
-+{
-+ struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
-+
-+ snd_soc_unregister_codec(dev);
-+ pm_runtime_disable(dev);
-+ if (!IS_ERR(pcm512x->sclk))
-+ clk_disable_unprepare(pcm512x->sclk);
-+ regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
-+ pcm512x->supplies);
-+}
-+
-+/* TODO
-+static int pcm512x_suspend(struct device *dev)
-+{
-+ struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
-+ int ret;
-+
-+ ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
-+ PCM512x_RQPD, PCM512x_RQPD);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to request power down: %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
-+ pcm512x->supplies);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to disable supplies: %d\n", ret);
-+ return ret;
-+ }
-+
-+ if (!IS_ERR(pcm512x->sclk))
-+ clk_disable_unprepare(pcm512x->sclk);
-+
-+ return 0;
-+}
-+
-+static int pcm512x_resume(struct device *dev)
-+{
-+ struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
-+ int ret;
-+
-+ if (!IS_ERR(pcm512x->sclk)) {
-+ ret = clk_prepare_enable(pcm512x->sclk);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to enable SCLK: %d\n", ret);
-+ return ret;
-+ }
-+ }
-+
-+ ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
-+ pcm512x->supplies);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to enable supplies: %d\n", ret);
-+ return ret;
-+ }
-+
-+ regcache_cache_only(pcm512x->regmap, false);
-+ ret = regcache_sync(pcm512x->regmap);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to sync cache: %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
-+ PCM512x_RQPD, 0);
-+ if (ret != 0) {
-+ dev_err(dev, "Failed to remove power down: %d\n", ret);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+// END OF PCM512x_suspend and resume calls TODO
-+*/
-+
-+static const struct dev_pm_ops pcm512x_pm_ops = {
-+ SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
-+};
-+
-+#if IS_ENABLED(CONFIG_I2C)
-+static int pcm512x_i2c_probe(struct i2c_client *i2c,
-+ const struct i2c_device_id *id)
-+{
-+ struct regmap *regmap;
-+
-+ regmap = devm_regmap_init_i2c(i2c, &pcm512x_regmap);
-+ if (IS_ERR(regmap))
-+ return PTR_ERR(regmap);
-+
-+ return pcm512x_probe(&i2c->dev, regmap);
-+}
-+
-+static int pcm512x_i2c_remove(struct i2c_client *i2c)
-+{
-+ pcm512x_remove(&i2c->dev);
-+ return 0;
-+}
-+
-+static const struct i2c_device_id pcm512x_i2c_id[] = {
-+ { "pcm5121", },
-+ { "pcm5122", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(i2c, pcm512x_i2c_id);
-+
-+static struct i2c_driver pcm512x_i2c_driver = {
-+ .probe = pcm512x_i2c_probe,
-+ .remove = pcm512x_i2c_remove,
-+ .id_table = pcm512x_i2c_id,
-+ .driver = {
-+ .name = "pcm512x",
-+ .owner = THIS_MODULE,
-+ .of_match_table = pcm512x_of_match,
-+ .pm = &pcm512x_pm_ops,
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SPI_MASTER)
-+static int pcm512x_spi_probe(struct spi_device *spi)
-+{
-+ struct regmap *regmap;
-+ int ret;
-+
-+ regmap = devm_regmap_init_spi(spi, &pcm512x_regmap);
-+ if (IS_ERR(regmap)) {
-+ ret = PTR_ERR(regmap);
-+ return ret;
-+ }
-+
-+ return pcm512x_probe(&spi->dev, regmap);
-+}
-+
-+static int pcm512x_spi_remove(struct spi_device *spi)
-+{
-+ pcm512x_remove(&spi->dev);
-+ return 0;
-+}
-+
-+static const struct spi_device_id pcm512x_spi_id[] = {
-+ { "pcm5121", },
-+ { "pcm5122", },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(spi, pcm512x_spi_id);
-+
-+static struct spi_driver pcm512x_spi_driver = {
-+ .probe = pcm512x_spi_probe,
-+ .remove = pcm512x_spi_remove,
-+ .id_table = pcm512x_spi_id,
-+ .driver = {
-+ .name = "pcm512x",
-+ .owner = THIS_MODULE,
-+ .of_match_table = pcm512x_of_match,
-+ .pm = &pcm512x_pm_ops,
-+ },
-+};
-+#endif
-+
-+static int __init pcm512x_modinit(void)
-+{
-+ int ret = 0;
-+
-+#if IS_ENABLED(CONFIG_I2C)
-+ ret = i2c_add_driver(&pcm512x_i2c_driver);
-+ if (ret) {
-+ printk(KERN_ERR "Failed to register pcm512x I2C driver: %d\n",
-+ ret);
-+ }
-+#endif
-+#if defined(CONFIG_SPI_MASTER)
-+ ret = spi_register_driver(&pcm512x_spi_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR "Failed to register pcm512x SPI driver: %d\n",
-+ ret);
-+ }
-+#endif
-+ return ret;
-+}
-+module_init(pcm512x_modinit);
-+
-+static void __exit pcm512x_exit(void)
-+{
-+#if IS_ENABLED(CONFIG_I2C)
-+ i2c_del_driver(&pcm512x_i2c_driver);
-+#endif
-+#if defined(CONFIG_SPI_MASTER)
-+ spi_unregister_driver(&pcm512x_spi_driver);
-+#endif
-+}
-+module_exit(pcm512x_exit);
-+
-+MODULE_DESCRIPTION("ASoC PCM512x codec driver");
-+MODULE_AUTHOR("Mark Brown <broonie@linaro.org>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/codecs/pcm512x.h linux-rpi/sound/soc/codecs/pcm512x.h
---- linux-3.12.38/sound/soc/codecs/pcm512x.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/pcm512x.h 2015-03-10 17:26:51.938216684 +0100
-@@ -0,0 +1,142 @@
-+/*
-+ * Driver for the PCM512x CODECs
-+ *
-+ * Author: Mark Brown <broonie@linaro.org>
-+ * Copyright 2014 Linaro Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#ifndef _SND_SOC_PCM512X
-+#define _SND_SOC_PCM512X
-+
-+#define PCM512x_PAGE_0_BASE 0
-+
-+#define PCM512x_PAGE 0
-+
-+#define PCM512x_RESET (PCM512x_PAGE_0_BASE + 1)
-+#define PCM512x_POWER (PCM512x_PAGE_0_BASE + 2)
-+#define PCM512x_MUTE (PCM512x_PAGE_0_BASE + 3)
-+#define PCM512x_PLL_EN (PCM512x_PAGE_0_BASE + 4)
-+#define PCM512x_SPI_MISO_FUNCTION (PCM512x_PAGE_0_BASE + 6)
-+#define PCM512x_DSP (PCM512x_PAGE_0_BASE + 7)
-+#define PCM512x_GPIO_EN (PCM512x_PAGE_0_BASE + 8)
-+#define PCM512x_BCLK_LRCLK_CFG (PCM512x_PAGE_0_BASE + 9)
-+#define PCM512x_DSP_GPIO_INPUT (PCM512x_PAGE_0_BASE + 10)
-+#define PCM512x_MASTER_MODE (PCM512x_PAGE_0_BASE + 12)
-+#define PCM512x_PLL_REF (PCM512x_PAGE_0_BASE + 13)
-+#define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_0_BASE + 20)
-+#define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_0_BASE + 21)
-+#define PCM512x_PLL_COEFF_2 (PCM512x_PAGE_0_BASE + 22)
-+#define PCM512x_PLL_COEFF_3 (PCM512x_PAGE_0_BASE + 23)
-+#define PCM512x_PLL_COEFF_4 (PCM512x_PAGE_0_BASE + 24)
-+#define PCM512x_DSP_CLKDIV (PCM512x_PAGE_0_BASE + 27)
-+#define PCM512x_DAC_CLKDIV (PCM512x_PAGE_0_BASE + 28)
-+#define PCM512x_NCP_CLKDIV (PCM512x_PAGE_0_BASE + 29)
-+#define PCM512x_OSR_CLKDIV (PCM512x_PAGE_0_BASE + 30)
-+#define PCM512x_MASTER_CLKDIV_1 (PCM512x_PAGE_0_BASE + 32)
-+#define PCM512x_MASTER_CLKDIV_2 (PCM512x_PAGE_0_BASE + 33)
-+#define PCM512x_FS_SPEED_MODE (PCM512x_PAGE_0_BASE + 34)
-+#define PCM512x_IDAC_1 (PCM512x_PAGE_0_BASE + 35)
-+#define PCM512x_IDAC_2 (PCM512x_PAGE_0_BASE + 36)
-+#define PCM512x_ERROR_DETECT (PCM512x_PAGE_0_BASE + 37)
-+#define PCM512x_I2S_1 (PCM512x_PAGE_0_BASE + 40)
-+#define PCM512x_I2S_2 (PCM512x_PAGE_0_BASE + 41)
-+#define PCM512x_DAC_ROUTING (PCM512x_PAGE_0_BASE + 42)
-+#define PCM512x_DSP_PROGRAM (PCM512x_PAGE_0_BASE + 43)
-+#define PCM512x_CLKDET (PCM512x_PAGE_0_BASE + 44)
-+#define PCM512x_AUTO_MUTE (PCM512x_PAGE_0_BASE + 59)
-+#define PCM512x_DIGITAL_VOLUME_1 (PCM512x_PAGE_0_BASE + 60)
-+#define PCM512x_DIGITAL_VOLUME_2 (PCM512x_PAGE_0_BASE + 61)
-+#define PCM512x_DIGITAL_VOLUME_3 (PCM512x_PAGE_0_BASE + 62)
-+#define PCM512x_DIGITAL_MUTE_1 (PCM512x_PAGE_0_BASE + 63)
-+#define PCM512x_DIGITAL_MUTE_2 (PCM512x_PAGE_0_BASE + 64)
-+#define PCM512x_DIGITAL_MUTE_3 (PCM512x_PAGE_0_BASE + 65)
-+#define PCM512x_GPIO_OUTPUT_1 (PCM512x_PAGE_0_BASE + 80)
-+#define PCM512x_GPIO_OUTPUT_2 (PCM512x_PAGE_0_BASE + 81)
-+#define PCM512x_GPIO_OUTPUT_3 (PCM512x_PAGE_0_BASE + 82)
-+#define PCM512x_GPIO_OUTPUT_4 (PCM512x_PAGE_0_BASE + 83)
-+#define PCM512x_GPIO_OUTPUT_5 (PCM512x_PAGE_0_BASE + 84)
-+#define PCM512x_GPIO_OUTPUT_6 (PCM512x_PAGE_0_BASE + 85)
-+#define PCM512x_GPIO_CONTROL_1 (PCM512x_PAGE_0_BASE + 86)
-+#define PCM512x_GPIO_CONTROL_2 (PCM512x_PAGE_0_BASE + 87)
-+#define PCM512x_OVERFLOW (PCM512x_PAGE_0_BASE + 90)
-+#define PCM512x_RATE_DET_1 (PCM512x_PAGE_0_BASE + 91)
-+#define PCM512x_RATE_DET_2 (PCM512x_PAGE_0_BASE + 92)
-+#define PCM512x_RATE_DET_3 (PCM512x_PAGE_0_BASE + 93)
-+#define PCM512x_RATE_DET_4 (PCM512x_PAGE_0_BASE + 94)
-+#define PCM512x_ANALOG_MUTE_DET (PCM512x_PAGE_0_BASE + 108)
-+#define PCM512x_GPIN (PCM512x_PAGE_0_BASE + 119)
-+#define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAGE_0_BASE + 120)
-+
-+#define PCM512x_MAX_REGISTER (PCM512x_PAGE_0_BASE + 120)
-+
-+/* Page 0, Register 1 - reset */
-+#define PCM512x_RSTR (1 << 0)
-+#define PCM512x_RSTM (1 << 4)
-+
-+/* Page 0, Register 2 - power */
-+#define PCM512x_RQPD (1 << 0)
-+#define PCM512x_RQPD_SHIFT 0
-+#define PCM512x_RQST (1 << 4)
-+#define PCM512x_RQST_SHIFT 4
-+
-+/* Page 0, Register 3 - mute */
-+#define PCM512x_RQMR_SHIFT 0
-+#define PCM512x_RQML_SHIFT 4
-+
-+/* Page 0, Register 4 - PLL */
-+#define PCM512x_PLCE (1 << 0)
-+#define PCM512x_RLCE_SHIFT 0
-+#define PCM512x_PLCK (1 << 4)
-+#define PCM512x_PLCK_SHIFT 4
-+
-+/* Page 0, Register 7 - DSP */
-+#define PCM512x_SDSL (1 << 0)
-+#define PCM512x_SDSL_SHIFT 0
-+#define PCM512x_DEMP (1 << 4)
-+#define PCM512x_DEMP_SHIFT 4
-+
-+/* Page 0, Register 13 - PLL reference */
-+#define PCM512x_SREF (1 << 4)
-+
-+/* Page 0, Register 37 - Error detection */
-+#define PCM512x_IPLK (1 << 0)
-+#define PCM512x_DCAS (1 << 1)
-+#define PCM512x_IDCM (1 << 2)
-+#define PCM512x_IDCH (1 << 3)
-+#define PCM512x_IDSK (1 << 4)
-+#define PCM512x_IDBK (1 << 5)
-+#define PCM512x_IDFS (1 << 6)
-+
-+/* Page 0, Register 42 - DAC routing */
-+#define PCM512x_AUPR_SHIFT 0
-+#define PCM512x_AUPL_SHIFT 4
-+
-+/* Page 0, Register 59 - auto mute */
-+#define PCM512x_ATMR_SHIFT 0
-+#define PCM512x_ATML_SHIFT 4
-+
-+/* Page 0, Register 63 - ramp rates */
-+#define PCM512x_VNDF_SHIFT 6
-+#define PCM512x_VNDS_SHIFT 4
-+#define PCM512x_VNUF_SHIFT 2
-+#define PCM512x_VNUS_SHIFT 0
-+
-+/* Page 0, Register 64 - emergency ramp rates */
-+#define PCM512x_VEDF_SHIFT 6
-+#define PCM512x_VEDS_SHIFT 4
-+
-+/* Page 0, Register 65 - Digital mute enables */
-+#define PCM512x_ACTL_SHIFT 2
-+#define PCM512x_AMLE_SHIFT 1
-+#define PCM512x_AMLR_SHIFT 0
-+
-+#endif
-diff -Nur linux-3.12.38/sound/soc/codecs/sgtl5000.c linux-rpi/sound/soc/codecs/sgtl5000.c
---- linux-3.12.38/sound/soc/codecs/sgtl5000.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/sgtl5000.c 2015-03-10 17:26:51.938216684 +0100
-@@ -1550,9 +1550,6 @@
- if (ret)
- return ret;
-
-- /* Need 8 clocks before I2C accesses */
-- udelay(1);
--
- /* read chip information */
- ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
- if (ret)
-diff -Nur linux-3.12.38/sound/soc/codecs/sigmadsp.c linux-rpi/sound/soc/codecs/sigmadsp.c
---- linux-3.12.38/sound/soc/codecs/sigmadsp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/sigmadsp.c 2015-03-10 17:26:51.938216684 +0100
-@@ -176,13 +176,6 @@
- goto done;
- }
-
-- if (ssfw_head->version != 1) {
-- dev_err(dev,
-- "Failed to load firmware: Invalid version %d. Supported firmware versions: 1\n",
-- ssfw_head->version);
-- goto done;
-- }
--
- crc = crc32(0, fw->data + sizeof(*ssfw_head),
- fw->size - sizeof(*ssfw_head));
- pr_debug("%s: crc=%x\n", __func__, crc);
-diff -Nur linux-3.12.38/sound/soc/codecs/tas5713.c linux-rpi/sound/soc/codecs/tas5713.c
---- linux-3.12.38/sound/soc/codecs/tas5713.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/tas5713.c 2015-03-10 17:26:51.938216684 +0100
-@@ -0,0 +1,370 @@
-+/*
-+ * ASoC Driver for TAS5713
-+ *
-+ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ * Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/pm.h>
-+#include <linux/i2c.h>
-+#include <linux/of_device.h>
-+#include <linux/spi/spi.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/slab.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/initval.h>
-+#include <sound/tlv.h>
-+
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/fs.h>
-+#include <asm/uaccess.h>
-+
-+#include "tas5713.h"
-+
-+
-+static struct i2c_client *i2c;
-+
-+struct tas5713_priv {
-+ struct regmap *regmap;
-+ int mclk_div;
-+ struct snd_soc_codec *codec;
-+};
-+
-+static struct tas5713_priv *priv_data;
-+
-+
-+
-+
-+/*
-+ * _ _ ___ _ ___ _ _
-+ * /_\ | | / __| /_\ / __|___ _ _| |_ _ _ ___| |___
-+ * / _ \| |__\__ \/ _ \ | (__/ _ \ ' \ _| '_/ _ \ (_-<
-+ * /_/ \_\____|___/_/ \_\ \___\___/_||_\__|_| \___/_/__/
-+ *
-+ */
-+
-+static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1);
-+
-+
-+static const struct snd_kcontrol_new tas5713_snd_controls[] = {
-+ SOC_SINGLE_TLV ("Master" , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv),
-+ SOC_DOUBLE_R_TLV("Channels" , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv)
-+};
-+
-+
-+
-+
-+/*
-+ * __ __ _ _ ___ _
-+ * | \/ |__ _ __| |_ (_)_ _ ___ | \ _ _(_)_ _____ _ _
-+ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_|
-+ * |_| |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static int tas5713_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ u16 blen = 0x00;
-+
-+ struct snd_soc_codec *codec;
-+ codec = dai->codec;
-+ priv_data->codec = dai->codec;
-+
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ blen = 0x03;
-+ break;
-+ case SNDRV_PCM_FORMAT_S20_3LE:
-+ blen = 0x1;
-+ break;
-+ case SNDRV_PCM_FORMAT_S24_LE:
-+ blen = 0x04;
-+ break;
-+ case SNDRV_PCM_FORMAT_S32_LE:
-+ blen = 0x05;
-+ break;
-+ default:
-+ dev_err(dai->dev, "Unsupported word length: %u\n",
-+ params_format(params));
-+ return -EINVAL;
-+ }
-+
-+ // set word length
-+ snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen);
-+
-+ return 0;
-+}
-+
-+
-+static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
-+{
-+ unsigned int val = 0;
-+
-+ struct tas5713_priv *tas5713;
-+ struct snd_soc_codec *codec = dai->codec;
-+ tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+ if (mute) {
-+ val = TAS5713_SOFT_MUTE_ALL;
-+ }
-+
-+ return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val);
-+}
-+
-+
-+static const struct snd_soc_dai_ops tas5713_dai_ops = {
-+ .hw_params = tas5713_hw_params,
-+ .mute_stream = tas5713_mute_stream,
-+};
-+
-+
-+static struct snd_soc_dai_driver tas5713_dai = {
-+ .name = "tas5713-hifi",
-+ .playback = {
-+ .stream_name = "Playback",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_48000,
-+ .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ),
-+ },
-+ .ops = &tas5713_dai_ops,
-+};
-+
-+
-+
-+
-+/*
-+ * ___ _ ___ _
-+ * / __|___ __| |___ __ | \ _ _(_)_ _____ _ _
-+ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_|
-+ * \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static int tas5713_remove(struct snd_soc_codec *codec)
-+{
-+ struct tas5713_priv *tas5713;
-+
-+ tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+ return 0;
-+}
-+
-+
-+static int tas5713_probe(struct snd_soc_codec *codec)
-+{
-+ struct tas5713_priv *tas5713;
-+ int i, ret;
-+
-+ i2c = container_of(codec->dev, struct i2c_client, dev);
-+
-+ tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+ codec->control_data = tas5713->regmap;
-+
-+ ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
-+ if (ret < 0) {
-+ dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
-+ return ret;
-+ }
-+
-+ // Reset error
-+ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
-+
-+ // Trim oscillator
-+ ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00);
-+ msleep(1000);
-+
-+ // Reset error
-+ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
-+
-+ // Clock mode: 44/48kHz, MCLK=64xfs
-+ ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60);
-+
-+ // I2S 24bit
-+ ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05);
-+
-+ // Unmute
-+ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
-+ ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00);
-+
-+ // Set volume to 0db
-+ ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00);
-+
-+ // Now start programming the default initialization sequence
-+ for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) {
-+ ret = i2c_master_send(i2c,
-+ tas5713_init_sequence[i].data,
-+ tas5713_init_sequence[i].size);
-+
-+ if (ret < 0) {
-+ printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret);
-+ }
-+ }
-+
-+ // Unmute
-+ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
-+
-+
-+ return 0;
-+}
-+
-+
-+static struct snd_soc_codec_driver soc_codec_dev_tas5713 = {
-+ .probe = tas5713_probe,
-+ .remove = tas5713_remove,
-+ .controls = tas5713_snd_controls,
-+ .num_controls = ARRAY_SIZE(tas5713_snd_controls),
-+};
-+
-+
-+
-+
-+/*
-+ * ___ ___ ___ ___ _
-+ * |_ _|_ ) __| | \ _ _(_)_ _____ _ _
-+ * | | / / (__ | |) | '_| \ V / -_) '_|
-+ * |___/___\___| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static const struct reg_default tas5713_reg_defaults[] = {
-+ { 0x07 ,0x80 }, // R7 - VOL_MASTER - -40dB
-+ { 0x08 , 30 }, // R8 - VOL_CH1 - 0dB
-+ { 0x09 , 30 }, // R9 - VOL_CH2 - 0dB
-+ { 0x0A ,0x80 }, // R10 - VOL_HEADPHONE - -40dB
-+};
-+
-+
-+static bool tas5713_reg_volatile(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case TAS5713_DEVICE_ID:
-+ case TAS5713_ERROR_STATUS:
-+ return true;
-+ default:
-+ return false;
-+ }
-+}
-+
-+
-+static const struct of_device_id tas5713_of_match[] = {
-+ { .compatible = "ti,tas5713", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, tas5713_of_match);
-+
-+
-+static struct regmap_config tas5713_regmap_config = {
-+ .reg_bits = 8,
-+ .val_bits = 8,
-+
-+ .max_register = TAS5713_MAX_REGISTER,
-+ .volatile_reg = tas5713_reg_volatile,
-+
-+ .cache_type = REGCACHE_RBTREE,
-+ .reg_defaults = tas5713_reg_defaults,
-+ .num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults),
-+};
-+
-+
-+static int tas5713_i2c_probe(struct i2c_client *i2c,
-+ const struct i2c_device_id *id)
-+{
-+ int ret;
-+
-+ priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL);
-+ if (!priv_data)
-+ return -ENOMEM;
-+
-+ priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config);
-+ if (IS_ERR(priv_data->regmap)) {
-+ ret = PTR_ERR(priv_data->regmap);
-+ return ret;
-+ }
-+
-+ i2c_set_clientdata(i2c, priv_data);
-+
-+ ret = snd_soc_register_codec(&i2c->dev,
-+ &soc_codec_dev_tas5713, &tas5713_dai, 1);
-+
-+ return ret;
-+}
-+
-+
-+static int tas5713_i2c_remove(struct i2c_client *i2c)
-+{
-+ snd_soc_unregister_codec(&i2c->dev);
-+ i2c_set_clientdata(i2c, NULL);
-+
-+ kfree(priv_data);
-+
-+ return 0;
-+}
-+
-+
-+static const struct i2c_device_id tas5713_i2c_id[] = {
-+ { "tas5713", 0 },
-+ { }
-+};
-+
-+MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id);
-+
-+
-+static struct i2c_driver tas5713_i2c_driver = {
-+ .driver = {
-+ .name = "tas5713",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tas5713_of_match,
-+ },
-+ .probe = tas5713_i2c_probe,
-+ .remove = tas5713_i2c_remove,
-+ .id_table = tas5713_i2c_id
-+};
-+
-+
-+static int __init tas5713_modinit(void)
-+{
-+ int ret = 0;
-+
-+ ret = i2c_add_driver(&tas5713_i2c_driver);
-+ if (ret) {
-+ printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n",
-+ ret);
-+ }
-+
-+ return ret;
-+}
-+module_init(tas5713_modinit);
-+
-+
-+static void __exit tas5713_exit(void)
-+{
-+ i2c_del_driver(&tas5713_i2c_driver);
-+}
-+module_exit(tas5713_exit);
-+
-+
-+MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
-+MODULE_DESCRIPTION("ASoC driver for TAS5713");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.12.38/sound/soc/codecs/tas5713.h linux-rpi/sound/soc/codecs/tas5713.h
---- linux-3.12.38/sound/soc/codecs/tas5713.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/tas5713.h 2015-03-10 17:26:51.938216684 +0100
-@@ -0,0 +1,210 @@
-+/*
-+ * ASoC Driver for TAS5713
-+ *
-+ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ * Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#ifndef _TAS5713_H
-+#define _TAS5713_H
-+
-+
-+// TAS5713 I2C-bus register addresses
-+
-+#define TAS5713_CLOCK_CTRL 0x00
-+#define TAS5713_DEVICE_ID 0x01
-+#define TAS5713_ERROR_STATUS 0x02
-+#define TAS5713_SYSTEM_CTRL1 0x03
-+#define TAS5713_SERIAL_DATA_INTERFACE 0x04
-+#define TAS5713_SYSTEM_CTRL2 0x05
-+#define TAS5713_SOFT_MUTE 0x06
-+#define TAS5713_VOL_MASTER 0x07
-+#define TAS5713_VOL_CH1 0x08
-+#define TAS5713_VOL_CH2 0x09
-+#define TAS5713_VOL_HEADPHONE 0x0A
-+#define TAS5713_VOL_CONFIG 0x0E
-+#define TAS5713_MODULATION_LIMIT 0x10
-+#define TAS5713_IC_DLY_CH1 0x11
-+#define TAS5713_IC_DLY_CH2 0x12
-+#define TAS5713_IC_DLY_CH3 0x13
-+#define TAS5713_IC_DLY_CH4 0x14
-+
-+#define TAS5713_START_STOP_PERIOD 0x1A
-+#define TAS5713_OSC_TRIM 0x1B
-+#define TAS5713_BKND_ERR 0x1C
-+
-+#define TAS5713_INPUT_MUX 0x20
-+#define TAS5713_SRC_SELECT_CH4 0x21
-+#define TAS5713_PWM_MUX 0x25
-+
-+#define TAS5713_CH1_BQ0 0x29
-+#define TAS5713_CH1_BQ1 0x2A
-+#define TAS5713_CH1_BQ2 0x2B
-+#define TAS5713_CH1_BQ3 0x2C
-+#define TAS5713_CH1_BQ4 0x2D
-+#define TAS5713_CH1_BQ5 0x2E
-+#define TAS5713_CH1_BQ6 0x2F
-+#define TAS5713_CH1_BQ7 0x58
-+#define TAS5713_CH1_BQ8 0x59
-+
-+#define TAS5713_CH2_BQ0 0x30
-+#define TAS5713_CH2_BQ1 0x31
-+#define TAS5713_CH2_BQ2 0x32
-+#define TAS5713_CH2_BQ3 0x33
-+#define TAS5713_CH2_BQ4 0x34
-+#define TAS5713_CH2_BQ5 0x35
-+#define TAS5713_CH2_BQ6 0x36
-+#define TAS5713_CH2_BQ7 0x5C
-+#define TAS5713_CH2_BQ8 0x5D
-+
-+#define TAS5713_CH4_BQ0 0x5A
-+#define TAS5713_CH4_BQ1 0x5B
-+#define TAS5713_CH3_BQ0 0x5E
-+#define TAS5713_CH3_BQ1 0x5F
-+
-+#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA 0x3B
-+#define TAS5713_DRC1_ATTACK_RELEASE_RATE 0x3C
-+#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA 0x3E
-+#define TAS5713_DRC2_ATTACK_RELEASE_RATE 0x3F
-+#define TAS5713_DRC1_ATTACK_RELEASE_THRES 0x40
-+#define TAS5713_DRC2_ATTACK_RELEASE_THRES 0x43
-+#define TAS5713_DRC_CTRL 0x46
-+
-+#define TAS5713_BANK_SW_CTRL 0x50
-+#define TAS5713_CH1_OUTPUT_MIXER 0x51
-+#define TAS5713_CH2_OUTPUT_MIXER 0x52
-+#define TAS5713_CH1_INPUT_MIXER 0x53
-+#define TAS5713_CH2_INPUT_MIXER 0x54
-+#define TAS5713_OUTPUT_POST_SCALE 0x56
-+#define TAS5713_OUTPUT_PRESCALE 0x57
-+
-+#define TAS5713_IDF_POST_SCALE 0x62
-+
-+#define TAS5713_CH1_INLINE_MIXER 0x70
-+#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71
-+#define TAS5713_CH1_R_CHANNEL_MIXER 0x72
-+#define TAS5713_CH1_L_CHANNEL_MIXER 0x73
-+#define TAS5713_CH2_INLINE_MIXER 0x74
-+#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75
-+#define TAS5713_CH2_L_CHANNEL_MIXER 0x76
-+#define TAS5713_CH2_R_CHANNEL_MIXER 0x77
-+
-+#define TAS5713_UPDATE_DEV_ADDR_KEY 0xF8
-+#define TAS5713_UPDATE_DEV_ADDR_REG 0xF9
-+
-+#define TAS5713_REGISTER_COUNT 0x46
-+#define TAS5713_MAX_REGISTER 0xF9
-+
-+
-+// Bitmasks for registers
-+#define TAS5713_SOFT_MUTE_ALL 0x07
-+
-+
-+
-+struct tas5713_init_command {
-+ const int size;
-+ const char *const data;
-+};
-+
-+static const struct tas5713_init_command tas5713_init_sequence[] = {
-+
-+ // Trim oscillator
-+ { .size = 2, .data = "\x1B\x00" },
-+ // System control register 1 (0x03): block DC
-+ { .size = 2, .data = "\x03\x80" },
-+ // Mute everything
-+ { .size = 2, .data = "\x05\x40" },
-+ // Modulation limit register (0x10): 97.7%
-+ { .size = 2, .data = "\x10\x02" },
-+ // Interchannel delay registers
-+ // (0x11, 0x12, 0x13, and 0x14): BD mode
-+ { .size = 2, .data = "\x11\xB8" },
-+ { .size = 2, .data = "\x12\x60" },
-+ { .size = 2, .data = "\x13\xA0" },
-+ { .size = 2, .data = "\x14\x48" },
-+ // PWM shutdown group register (0x19): no shutdown
-+ { .size = 2, .data = "\x19\x00" },
-+ // Input multiplexer register (0x20): BD mode
-+ { .size = 2, .data = "\x20\x00\x89\x77\x72" },
-+ // PWM output mux register (0x25)
-+ // Channel 1 --> OUTA, channel 1 neg --> OUTB
-+ // Channel 2 --> OUTC, channel 2 neg --> OUTD
-+ { .size = 5, .data = "\x25\x01\x02\x13\x45" },
-+ // DRC control (0x46): DRC off
-+ { .size = 5, .data = "\x46\x00\x00\x00\x00" },
-+ // BKND_ERR register (0x1C): 299ms reset period
-+ { .size = 2, .data = "\x1C\x07" },
-+ // Mute channel 3
-+ { .size = 2, .data = "\x0A\xFF" },
-+ // Volume configuration register (0x0E): volume slew 512 steps
-+ { .size = 2, .data = "\x0E\x90" },
-+ // Clock control register (0x00): 44/48kHz, MCLK=64xfs
-+ { .size = 2, .data = "\x00\x60" },
-+ // Bank switch and eq control (0x50): no bank switching
-+ { .size = 5, .data = "\x50\x00\x00\x00\x00" },
-+ // Volume registers (0x07, 0x08, 0x09, 0x0A)
-+ { .size = 2, .data = "\x07\x20" },
-+ { .size = 2, .data = "\x08\x30" },
-+ { .size = 2, .data = "\x09\x30" },
-+ { .size = 2, .data = "\x0A\xFF" },
-+ // 0x72, 0x73, 0x76, 0x77 input mixer:
-+ // no intermix between channels
-+ { .size = 5, .data = "\x72\x00\x00\x00\x00" },
-+ { .size = 5, .data = "\x73\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x76\x00\x00\x00\x00" },
-+ { .size = 5, .data = "\x77\x00\x80\x00\x00" },
-+ // 0x70, 0x71, 0x74, 0x75 inline DRC mixer:
-+ // no inline DRC inmix
-+ { .size = 5, .data = "\x70\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x71\x00\x00\x00\x00" },
-+ { .size = 5, .data = "\x74\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x75\x00\x00\x00\x00" },
-+ // 0x56, 0x57 Output scale
-+ { .size = 5, .data = "\x56\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x57\x00\x02\x00\x00" },
-+ // 0x3B, 0x3c
-+ { .size = 9, .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" },
-+ { .size = 9, .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ { .size = 9, .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" },
-+ { .size = 9, .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ { .size = 9, .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ { .size = 9, .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ // 0x51, 0x52: output mixer
-+ { .size = 9, .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" },
-+ { .size = 9, .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" },
-+ // PEQ defaults
-+ { .size = 21, .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+};
-+
-+
-+#endif /* _TAS5713_H */
-diff -Nur linux-3.12.38/sound/soc/codecs/wm8804.c linux-rpi/sound/soc/codecs/wm8804.c
---- linux-3.12.38/sound/soc/codecs/wm8804.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/wm8804.c 2015-03-10 17:26:51.946216683 +0100
-@@ -63,6 +63,7 @@
- struct regmap *regmap;
- struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
- struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
-+ int mclk_div;
- };
-
- static int txsrc_get(struct snd_kcontrol *kcontrol,
-@@ -277,6 +278,7 @@
- blen = 0x1;
- break;
- case SNDRV_PCM_FORMAT_S24_LE:
-+ case SNDRV_PCM_FORMAT_S32_LE:
- blen = 0x2;
- break;
- default:
-@@ -318,7 +320,7 @@
-
- #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
- static int pll_factors(struct pll_div *pll_div, unsigned int target,
-- unsigned int source)
-+ unsigned int source, unsigned int mclk_div)
- {
- u64 Kpart;
- unsigned long int K, Ndiv, Nmod, tmp;
-@@ -330,7 +332,8 @@
- */
- for (i = 0; i < ARRAY_SIZE(post_table); i++) {
- tmp = target * post_table[i].div;
-- if (tmp >= 90000000 && tmp <= 100000000) {
-+ if ((tmp >= 90000000 && tmp <= 100000000) &&
-+ (mclk_div == post_table[i].mclkdiv)) {
- pll_div->freqmode = post_table[i].freqmode;
- pll_div->mclkdiv = post_table[i].mclkdiv;
- target *= post_table[i].div;
-@@ -387,8 +390,11 @@
- } else {
- int ret;
- struct pll_div pll_div;
-+ struct wm8804_priv *wm8804;
-
-- ret = pll_factors(&pll_div, freq_out, freq_in);
-+ wm8804 = snd_soc_codec_get_drvdata(codec);
-+
-+ ret = pll_factors(&pll_div, freq_out, freq_in, wm8804->mclk_div);
- if (ret)
- return ret;
-
-@@ -452,6 +458,7 @@
- int div_id, int div)
- {
- struct snd_soc_codec *codec;
-+ struct wm8804_priv *wm8804;
-
- codec = dai->codec;
- switch (div_id) {
-@@ -459,6 +466,10 @@
- snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
- (div & 0x3) << 4);
- break;
-+ case WM8804_MCLK_DIV:
-+ wm8804 = snd_soc_codec_get_drvdata(codec);
-+ wm8804->mclk_div = div;
-+ break;
- default:
- dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
- return -EINVAL;
-@@ -641,7 +652,7 @@
- };
-
- #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
-- SNDRV_PCM_FMTBIT_S24_LE)
-+ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
-
- #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
- SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
-@@ -674,7 +685,7 @@
- .suspend = wm8804_suspend,
- .resume = wm8804_resume,
- .set_bias_level = wm8804_set_bias_level,
-- .idle_bias_off = true,
-+ .idle_bias_off = false,
-
- .controls = wm8804_snd_controls,
- .num_controls = ARRAY_SIZE(wm8804_snd_controls),
-diff -Nur linux-3.12.38/sound/soc/codecs/wm8804.h linux-rpi/sound/soc/codecs/wm8804.h
---- linux-3.12.38/sound/soc/codecs/wm8804.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/wm8804.h 2015-03-09 10:39:38.578893685 +0100
-@@ -57,5 +57,9 @@
- #define WM8804_CLKOUT_SRC_OSCCLK 4
-
- #define WM8804_CLKOUT_DIV 1
-+#define WM8804_MCLK_DIV 2
-+
-+#define WM8804_MCLKDIV_256FS 0
-+#define WM8804_MCLKDIV_128FS 1
-
- #endif /* _WM8804_H */
-diff -Nur linux-3.12.38/sound/soc/codecs/wm8960.c linux-rpi/sound/soc/codecs/wm8960.c
---- linux-3.12.38/sound/soc/codecs/wm8960.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/codecs/wm8960.c 2015-03-10 17:26:51.946216683 +0100
-@@ -555,7 +555,7 @@
- { 22050, 2 },
- { 24000, 2 },
- { 16000, 3 },
-- { 11025, 4 },
-+ { 11250, 4 },
- { 12000, 4 },
- { 8000, 5 },
- };
-diff -Nur linux-3.12.38/sound/soc/dwc/designware_i2s.c linux-rpi/sound/soc/dwc/designware_i2s.c
---- linux-3.12.38/sound/soc/dwc/designware_i2s.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/dwc/designware_i2s.c 2015-03-10 17:26:51.954216683 +0100
-@@ -263,19 +263,6 @@
- snd_soc_dai_set_dma_data(dai, substream, NULL);
- }
-
--static int dw_i2s_prepare(struct snd_pcm_substream *substream,
-- struct snd_soc_dai *dai)
--{
-- struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
--
-- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-- i2s_write_reg(dev->i2s_base, TXFFR, 1);
-- else
-- i2s_write_reg(dev->i2s_base, RXFFR, 1);
--
-- return 0;
--}
--
- static int dw_i2s_trigger(struct snd_pcm_substream *substream,
- int cmd, struct snd_soc_dai *dai)
- {
-@@ -307,7 +294,6 @@
- .startup = dw_i2s_startup,
- .shutdown = dw_i2s_shutdown,
- .hw_params = dw_i2s_hw_params,
-- .prepare = dw_i2s_prepare,
- .trigger = dw_i2s_trigger,
- };
-
-diff -Nur linux-3.12.38/sound/soc/generic/simple-card.c linux-rpi/sound/soc/generic/simple-card.c
---- linux-3.12.38/sound/soc/generic/simple-card.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/generic/simple-card.c 2015-03-10 17:26:51.954216683 +0100
-@@ -27,6 +27,11 @@
- if (!ret && daifmt)
- ret = snd_soc_dai_set_fmt(dai, daifmt);
-
-+ if (ret == -ENOTSUPP) {
-+ dev_dbg(dai->dev, "ASoC: set_fmt is not supported\n");
-+ ret = 0;
-+ }
-+
- if (!ret && set->sysclk)
- ret = snd_soc_dai_set_sysclk(dai, 0, set->sysclk, 0);
-
-diff -Nur linux-3.12.38/sound/soc/Kconfig linux-rpi/sound/soc/Kconfig
---- linux-3.12.38/sound/soc/Kconfig 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/Kconfig 2015-03-10 17:26:51.926216684 +0100
-@@ -33,6 +33,7 @@
- # All the supported SoCs
- source "sound/soc/atmel/Kconfig"
- source "sound/soc/au1x/Kconfig"
-+source "sound/soc/bcm/Kconfig"
- source "sound/soc/blackfin/Kconfig"
- source "sound/soc/cirrus/Kconfig"
- source "sound/soc/davinci/Kconfig"
-diff -Nur linux-3.12.38/sound/soc/Makefile linux-rpi/sound/soc/Makefile
---- linux-3.12.38/sound/soc/Makefile 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/Makefile 2015-03-10 17:26:51.926216684 +0100
-@@ -10,6 +10,7 @@
- obj-$(CONFIG_SND_SOC) += generic/
- obj-$(CONFIG_SND_SOC) += atmel/
- obj-$(CONFIG_SND_SOC) += au1x/
-+obj-$(CONFIG_SND_SOC) += bcm/
- obj-$(CONFIG_SND_SOC) += blackfin/
- obj-$(CONFIG_SND_SOC) += cirrus/
- obj-$(CONFIG_SND_SOC) += davinci/
-diff -Nur linux-3.12.38/sound/soc/omap/omap-mcbsp.c linux-rpi/sound/soc/omap/omap-mcbsp.c
---- linux-3.12.38/sound/soc/omap/omap-mcbsp.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/omap/omap-mcbsp.c 2015-03-10 17:26:51.958216683 +0100
-@@ -436,7 +436,7 @@
- case SND_SOC_DAIFMT_CBM_CFS:
- /* McBSP slave. FS clock as output */
- regs->srgr2 |= FSGM;
-- regs->pcr0 |= FSXM | FSRM;
-+ regs->pcr0 |= FSXM;
- break;
- case SND_SOC_DAIFMT_CBM_CFM:
- /* McBSP slave */
-diff -Nur linux-3.12.38/sound/soc/soc-core.c linux-rpi/sound/soc/soc-core.c
---- linux-3.12.38/sound/soc/soc-core.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/soc/soc-core.c 2015-03-10 17:26:51.962216683 +0100
-@@ -3038,8 +3038,8 @@
-
- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
- uinfo->count = snd_soc_volsw_is_stereo(mc) ? 2 : 1;
-- uinfo->value.integer.min = 0;
-- uinfo->value.integer.max = platform_max - min;
-+ uinfo->value.integer.min = min;
-+ uinfo->value.integer.max = platform_max;
-
- return 0;
- }
-@@ -3070,9 +3070,10 @@
- unsigned int val, val_mask;
- int ret;
-
-- val = ((ucontrol->value.integer.value[0] + min) & mask);
- if (invert)
-- val = max - val;
-+ val = ((max - ucontrol->value.integer.value[0] + min) & mask);
-+ else
-+ val = (ucontrol->value.integer.value[0] & mask);
- val_mask = mask << shift;
- val = val << shift;
-
-@@ -3081,9 +3082,10 @@
- return ret;
-
- if (snd_soc_volsw_is_stereo(mc)) {
-- val = ((ucontrol->value.integer.value[1] + min) & mask);
- if (invert)
-- val = max - val;
-+ val = ((max - ucontrol->value.integer.value[1] + min) & mask);
-+ else
-+ val = (ucontrol->value.integer.value[1] & mask);
- val_mask = mask << shift;
- val = val << shift;
-
-@@ -3121,18 +3123,14 @@
- (snd_soc_read(codec, reg) >> shift) & mask;
- if (invert)
- ucontrol->value.integer.value[0] =
-- max - ucontrol->value.integer.value[0];
-- ucontrol->value.integer.value[0] =
-- ucontrol->value.integer.value[0] - min;
-+ max - ucontrol->value.integer.value[0] + min;
-
- if (snd_soc_volsw_is_stereo(mc)) {
- ucontrol->value.integer.value[1] =
- (snd_soc_read(codec, rreg) >> shift) & mask;
- if (invert)
- ucontrol->value.integer.value[1] =
-- max - ucontrol->value.integer.value[1];
-- ucontrol->value.integer.value[1] =
-- ucontrol->value.integer.value[1] - min;
-+ max - ucontrol->value.integer.value[1] + min;
- }
-
- return 0;
-@@ -3576,6 +3574,22 @@
- EXPORT_SYMBOL_GPL(snd_soc_codec_set_pll);
-
- /**
-+ * snd_soc_dai_set_bclk_ratio - configure BCLK to sample rate ratio.
-+ * @dai: DAI
-+ * @ratio Ratio of BCLK to Sample rate.
-+ *
-+ * Configures the DAI for a preset BCLK to sample rate ratio.
-+ */
-+int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
-+{
-+ if (dai->driver && dai->driver->ops->set_bclk_ratio)
-+ return dai->driver->ops->set_bclk_ratio(dai, ratio);
-+ else
-+ return -EINVAL;
-+}
-+EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio);
-+
-+/**
- * snd_soc_dai_set_fmt - configure DAI hardware audio format.
- * @dai: DAI
- * @fmt: SND_SOC_DAIFMT_ format value.
-diff -Nur linux-3.12.38/sound/usb/mixer.c linux-rpi/sound/usb/mixer.c
---- linux-3.12.38/sound/usb/mixer.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/usb/mixer.c 2015-03-10 17:26:51.970216683 +0100
-@@ -886,7 +886,6 @@
- case USB_ID(0x046d, 0x0807): /* Logitech Webcam C500 */
- case USB_ID(0x046d, 0x0808):
- case USB_ID(0x046d, 0x0809):
-- case USB_ID(0x046d, 0x0819): /* Logitech Webcam C210 */
- case USB_ID(0x046d, 0x081b): /* HD Webcam c310 */
- case USB_ID(0x046d, 0x081d): /* HD Webcam c510 */
- case USB_ID(0x046d, 0x0825): /* HD Webcam c270 */
-diff -Nur linux-3.12.38/sound/usb/mixer_maps.c linux-rpi/sound/usb/mixer_maps.c
---- linux-3.12.38/sound/usb/mixer_maps.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/usb/mixer_maps.c 2015-03-10 17:26:51.970216683 +0100
-@@ -322,11 +322,8 @@
- { 0 } /* terminator */
- };
-
--/* some (all?) SCMS USB3318 devices are affected by a firmware lock up
-- * when anything attempts to access FU 10 (control)
-- */
--static const struct usbmix_name_map scms_usb3318_map[] = {
-- { 10, NULL },
-+static const struct usbmix_name_map kef_x300a_map[] = {
-+ { 10, NULL }, /* firmware locks up (?) when we try to access this FU */
- { 0 }
- };
-
-@@ -418,14 +415,8 @@
- .map = ebox44_map,
- },
- {
-- /* KEF X300A */
- .id = USB_ID(0x27ac, 0x1000),
-- .map = scms_usb3318_map,
-- },
-- {
-- /* Arcam rPAC */
-- .id = USB_ID(0x25c4, 0x0003),
-- .map = scms_usb3318_map,
-+ .map = kef_x300a_map,
- },
- { 0 } /* terminator */
- };
-diff -Nur linux-3.12.38/sound/usb/quirks.c linux-rpi/sound/usb/quirks.c
---- linux-3.12.38/sound/usb/quirks.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/usb/quirks.c 2015-03-10 17:26:51.970216683 +0100
-@@ -662,9 +662,8 @@
-
- /*
- * Novation Twitch DJ controller
-- * Focusrite Novation Saffire 6 USB audio card
- */
--static int snd_usb_novation_boot_quirk(struct usb_device *dev)
-+static int snd_usb_twitch_boot_quirk(struct usb_device *dev)
- {
- /* preemptively set up the device because otherwise the
- * raw MIDI endpoints are not active */
-@@ -973,9 +972,9 @@
- /* Digidesign Mbox 2 */
- return snd_usb_mbox2_boot_quirk(dev);
-
-- case USB_ID(0x1235, 0x0010): /* Focusrite Novation Saffire 6 USB */
-- case USB_ID(0x1235, 0x0018): /* Focusrite Novation Twitch */
-- return snd_usb_novation_boot_quirk(dev);
-+ case USB_ID(0x1235, 0x0018):
-+ /* Focusrite Novation Twitch */
-+ return snd_usb_twitch_boot_quirk(dev);
-
- case USB_ID(0x133e, 0x0815):
- /* Access Music VirusTI Desktop */
-diff -Nur linux-3.12.38/sound/usb/quirks-table.h linux-rpi/sound/usb/quirks-table.h
---- linux-3.12.38/sound/usb/quirks-table.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/sound/usb/quirks-table.h 2015-03-10 17:26:51.970216683 +0100
-@@ -72,21 +72,22 @@
- }
- },
-
--/* Creative/E-Mu devices */
-+/* Creative/Toshiba Multimedia Center SB-0500 */
- {
-- USB_DEVICE(0x041e, 0x3010),
-+ USB_DEVICE(0x041e, 0x3048),
- .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
-- .vendor_name = "Creative Labs",
-- .product_name = "Sound Blaster MP3+",
-+ .vendor_name = "Toshiba",
-+ .product_name = "SB-0500",
- .ifnum = QUIRK_NO_INTERFACE
- }
- },
--/* Creative/Toshiba Multimedia Center SB-0500 */
-+
-+/* Creative/E-Mu devices */
- {
-- USB_DEVICE(0x041e, 0x3048),
-+ USB_DEVICE(0x041e, 0x3010),
- .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
-- .vendor_name = "Toshiba",
-- .product_name = "SB-0500",
-+ .vendor_name = "Creative Labs",
-+ .product_name = "Sound Blaster MP3+",
- .ifnum = QUIRK_NO_INTERFACE
- }
- },
-@@ -2579,46 +2580,6 @@
- }
- },
- {
-- USB_DEVICE(0x1235, 0x0010),
-- .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-- .vendor_name = "Focusrite",
-- .product_name = "Saffire 6 USB",
-- .ifnum = QUIRK_ANY_INTERFACE,
-- .type = QUIRK_COMPOSITE,
-- .data = (const struct snd_usb_audio_quirk[]) {
-- {
-- .ifnum = 0,
-- .type = QUIRK_AUDIO_FIXED_ENDPOINT,
-- .data = &(const struct audioformat) {
-- .formats = SNDRV_PCM_FMTBIT_S24_3LE,
-- .channels = 4,
-- .iface = 0,
-- .altsetting = 1,
-- .altset_idx = 1,
-- .attributes = UAC_EP_CS_ATTR_SAMPLE_RATE,
-- .endpoint = 0x01,
-- .ep_attr = USB_ENDPOINT_XFER_ISOC,
-- .rates = SNDRV_PCM_RATE_44100 |
-- SNDRV_PCM_RATE_48000,
-- .rate_min = 44100,
-- .rate_max = 48000,
-- .nr_rates = 2,
-- .rate_table = (unsigned int[]) {
-- 44100, 48000
-- }
-- }
-- },
-- {
-- .ifnum = 1,
-- .type = QUIRK_MIDI_RAW_BYTES
-- },
-- {
-- .ifnum = -1
-- }
-- }
-- }
--},
--{
- USB_DEVICE(0x1235, 0x0018),
- .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
- .vendor_name = "Novation",
-@@ -2667,57 +2628,6 @@
- .type = QUIRK_MIDI_NOVATION
- }
- },
--{
-- /*
-- * Focusrite Scarlett 18i6
-- *
-- * Avoid mixer creation, which otherwise fails because some of
-- * the interface descriptor subtypes for interface 0 are
-- * unknown. That should be fixed or worked-around but this at
-- * least allows the device to be used successfully with a DAW
-- * and an external mixer. See comments below about other
-- * ignored interfaces.
-- */
-- USB_DEVICE(0x1235, 0x8004),
-- .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
-- .vendor_name = "Focusrite",
-- .product_name = "Scarlett 18i6",
-- .ifnum = QUIRK_ANY_INTERFACE,
-- .type = QUIRK_COMPOSITE,
-- .data = & (const struct snd_usb_audio_quirk[]) {
-- {
-- /* InterfaceSubClass 1 (Control Device) */
-- .ifnum = 0,
-- .type = QUIRK_IGNORE_INTERFACE
-- },
-- {
-- .ifnum = 1,
-- .type = QUIRK_AUDIO_STANDARD_INTERFACE
-- },
-- {
-- .ifnum = 2,
-- .type = QUIRK_AUDIO_STANDARD_INTERFACE
-- },
-- {
-- /* InterfaceSubClass 1 (Control Device) */
-- .ifnum = 3,
-- .type = QUIRK_IGNORE_INTERFACE
-- },
-- {
-- .ifnum = 4,
-- .type = QUIRK_MIDI_STANDARD_INTERFACE
-- },
-- {
-- /* InterfaceSubClass 1 (Device Firmware Update) */
-- .ifnum = 5,
-- .type = QUIRK_IGNORE_INTERFACE
-- },
-- {
-- .ifnum = -1
-- }
-- }
-- }
--},
-
- /* Access Music devices */
- {
-@@ -2804,45 +2714,133 @@
- }
- },
-
--/*
-- * Auvitek au0828 devices with audio interface.
-- * This should be kept in sync with drivers/media/usb/au0828/au0828-cards.c
-- * Please notice that some drivers are DVB only, and don't need to be
-- * here. That's the case, for example, of DVICO_FUSIONHDTV7.
-- */
--
--#define AU0828_DEVICE(vid, pid, vname, pname) { \
-- USB_DEVICE_VENDOR_SPEC(vid, pid), \
-- .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
-- USB_DEVICE_ID_MATCH_INT_CLASS | \
-- USB_DEVICE_ID_MATCH_INT_SUBCLASS, \
-- .bInterfaceClass = USB_CLASS_AUDIO, \
-- .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL, \
-- .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { \
-- .vendor_name = vname, \
-- .product_name = pname, \
-- .ifnum = QUIRK_ANY_INTERFACE, \
-- .type = QUIRK_AUDIO_ALIGN_TRANSFER, \
-- } \
--}
--
--AU0828_DEVICE(0x2040, 0x7200, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x7240, "Hauppauge", "HVR-850"),
--AU0828_DEVICE(0x2040, 0x7210, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x7217, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x721b, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x721e, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x721f, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x7280, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x0fd9, 0x0008, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x7201, "Hauppauge", "HVR-950Q-MXL"),
--AU0828_DEVICE(0x2040, 0x7211, "Hauppauge", "HVR-950Q-MXL"),
--AU0828_DEVICE(0x2040, 0x7281, "Hauppauge", "HVR-950Q-MXL"),
--AU0828_DEVICE(0x05e1, 0x0480, "Hauppauge", "Woodbury"),
--AU0828_DEVICE(0x2040, 0x8200, "Hauppauge", "Woodbury"),
--AU0828_DEVICE(0x2040, 0x7260, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x7213, "Hauppauge", "HVR-950Q"),
--AU0828_DEVICE(0x2040, 0x7270, "Hauppauge", "HVR-950Q"),
-+/* Hauppauge HVR-950Q and HVR-850 */
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x7200),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x7240),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-850",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x7210),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x7217),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x721b),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x721e),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x721f),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x2040, 0x7280),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-+{
-+ USB_DEVICE_VENDOR_SPEC(0x0fd9, 0x0008),
-+ .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
-+ USB_DEVICE_ID_MATCH_INT_CLASS |
-+ USB_DEVICE_ID_MATCH_INT_SUBCLASS,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
-+ .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Hauppauge",
-+ .product_name = "HVR-950Q",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_AUDIO_ALIGN_TRANSFER,
-+ }
-+},
-
- /* Digidesign Mbox */
- {
-@@ -3108,6 +3106,58 @@
- },
- {
- .ifnum = -1
-+ }
-+ }
-+ }
-+},
-+
-+{
-+ /*
-+ * Focusrite Scarlett 18i6
-+ *
-+ * Avoid mixer creation, which otherwise fails because some of
-+ * the interface descriptor subtypes for interface 0 are
-+ * unknown. That should be fixed or worked-around but this at
-+ * least allows the device to be used successfully with a DAW
-+ * and an external mixer. See comments below about other
-+ * ignored interfaces.
-+ */
-+ USB_DEVICE(0x1235, 0x8004),
-+ .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
-+ .vendor_name = "Focusrite",
-+ .product_name = "Scarlett 18i6",
-+ .ifnum = QUIRK_ANY_INTERFACE,
-+ .type = QUIRK_COMPOSITE,
-+ .data = & (const struct snd_usb_audio_quirk[]) {
-+ {
-+ /* InterfaceSubClass 1 (Control Device) */
-+ .ifnum = 0,
-+ .type = QUIRK_IGNORE_INTERFACE
-+ },
-+ {
-+ .ifnum = 1,
-+ .type = QUIRK_AUDIO_STANDARD_INTERFACE
-+ },
-+ {
-+ .ifnum = 2,
-+ .type = QUIRK_AUDIO_STANDARD_INTERFACE
-+ },
-+ {
-+ /* InterfaceSubClass 1 (Control Device) */
-+ .ifnum = 3,
-+ .type = QUIRK_IGNORE_INTERFACE
-+ },
-+ {
-+ .ifnum = 4,
-+ .type = QUIRK_MIDI_STANDARD_INTERFACE
-+ },
-+ {
-+ /* InterfaceSubClass 1 (Device Firmware Update) */
-+ .ifnum = 5,
-+ .type = QUIRK_IGNORE_INTERFACE
-+ },
-+ {
-+ .ifnum = -1
- }
- }
- }
-diff -Nur linux-3.12.38/tools/perf/util/hist.h linux-rpi/tools/perf/util/hist.h
---- linux-3.12.38/tools/perf/util/hist.h 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/tools/perf/util/hist.h 2015-03-10 17:26:51.986216683 +0100
-@@ -35,7 +35,6 @@
- u32 nr_invalid_chains;
- u32 nr_unknown_id;
- u32 nr_unprocessable_samples;
-- u32 nr_unordered_events;
- };
-
- enum hist_column {
-diff -Nur linux-3.12.38/tools/perf/util/session.c linux-rpi/tools/perf/util/session.c
---- linux-3.12.38/tools/perf/util/session.c 2015-02-16 16:15:42.000000000 +0100
-+++ linux-rpi/tools/perf/util/session.c 2015-03-10 17:26:51.990216683 +0100
-@@ -681,7 +681,8 @@
- return -ETIME;
-
- if (timestamp < s->ordered_samples.last_flush) {
-- s->stats.nr_unordered_events++;
-+ printf("Warning: Timestamp below last timeslice flush\n");
-+ return -EINVAL;
- }
-
- if (!list_empty(sc)) {
-@@ -1167,8 +1168,6 @@
- "Do you have a KVM guest running and not using 'perf kvm'?\n",
- session->stats.nr_unprocessable_samples);
- }
-- if (session->stats.nr_unordered_events != 0)
-- ui__warning("%u out of order events recorded.\n", session->stats.nr_unordered_events);
- }
-
- volatile int session_done;
diff --git a/target/arm/bcm28xx/patches/3.12.44/0001-rpi-proto-driver.patch b/target/arm/bcm28xx/patches/3.12.44/0001-rpi-proto-driver.patch
deleted file mode 100644
index 4c1ca535b..000000000
--- a/target/arm/bcm28xx/patches/3.12.44/0001-rpi-proto-driver.patch
+++ /dev/null
@@ -1,235 +0,0 @@
-diff -Nur linux-3.12.37.orig/arch/arm/mach-bcm2708/bcm2708.c linux-3.12.37/arch/arm/mach-bcm2708/bcm2708.c
---- linux-3.12.37.orig/arch/arm/mach-bcm2708/bcm2708.c 2015-02-18 14:32:14.988546928 +0100
-+++ linux-3.12.37/arch/arm/mach-bcm2708/bcm2708.c 2015-02-18 15:20:32.564560932 +0100
-@@ -769,6 +769,19 @@
- };
- #endif
-
-+#ifdef CONFIG_SND_BCM2708_SOC_RPI_PROTO_MODULE
-+static struct platform_device snd_rpi_proto_device = {
-+ .name = "snd-rpi-proto",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+static struct i2c_board_info __initdata snd_rpi_proto_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("wm8731", 0x1a)
-+ },
-+};
-+#endif
-+
- int __init bcm_register_device(struct platform_device *pdev)
- {
- int ret;
-@@ -944,6 +957,10 @@
- bcm_register_device(&snd_rpi_iqaudio_dac_device);
- i2c_register_board_info(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
- #endif
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_PROTO) || defined(CONFIG_SND_BCM2708_SOC_RPI_PROTO_MODULE)
-+ bcm_register_device(&snd_rpi_proto_device);
-+ i2c_register_board_info(1, snd_rpi_proto_i2c_devices, ARRAY_SIZE(snd_rpi_proto_i2c_devices));
-+#endif
-
-
- for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-diff -Nur linux-3.12.37.orig/sound/soc/bcm/bcm2708-i2s.c linux-3.12.37/sound/soc/bcm/bcm2708-i2s.c
---- linux-3.12.37.orig/sound/soc/bcm/bcm2708-i2s.c 2015-02-18 14:32:15.128546928 +0100
-+++ linux-3.12.37/sound/soc/bcm/bcm2708-i2s.c 2015-02-18 15:10:07.452557911 +0100
-@@ -171,6 +171,11 @@
- /* I2S pin configuration */
- static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO;
-
-+static bool use_mmap = 1;
-+module_param(use_mmap, bool, S_IRUGO);
-+MODULE_PARM_DESC(use_mmap, "Use MMAP");
-+
-+
- /* General device struct */
- struct bcm2708_i2s_dev {
- struct device *dev;
-@@ -870,7 +875,7 @@
- .name = "bcm2708-i2s-comp",
- };
-
--static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
-+static struct snd_pcm_hardware bcm2708_pcm_hardware = {
- .info = SNDRV_PCM_INFO_INTERLEAVED |
- SNDRV_PCM_INFO_JOINT_DUPLEX,
- .formats = SNDRV_PCM_FMTBIT_S16_LE |
-@@ -962,6 +967,11 @@
- return ret;
- }
-
-+ if (use_mmap) {
-+ bcm2708_pcm_hardware.info |= SNDRV_PCM_INFO_MMAP;
-+ bcm2708_pcm_hardware.info |= SNDRV_PCM_INFO_MMAP_VALID;
-+ }
-+
- ret = snd_dmaengine_pcm_register(&pdev->dev,
- &bcm2708_dmaengine_pcm_config,
- SND_DMAENGINE_PCM_FLAG_COMPAT);
-diff -Nur linux-3.12.37.orig/sound/soc/bcm/Kconfig linux-3.12.37/sound/soc/bcm/Kconfig
---- linux-3.12.37.orig/sound/soc/bcm/Kconfig 2015-02-18 14:32:15.128546928 +0100
-+++ linux-3.12.37/sound/soc/bcm/Kconfig 2015-02-18 15:18:22.948560306 +0100
-@@ -50,3 +50,11 @@
- select SND_SOC_PCM512x
- help
- Say Y or M if you want to add support for IQaudIO-DAC.
-+
-+config SND_BCM2708_SOC_RPI_PROTO
-+ tristate "Support for Rpi-PROTO"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_WM8731
-+ help
-+ Say Y if you want to add support for Audio Codec Board -
-+ PROTO (WM8731)
-diff -Nur linux-3.12.37.orig/sound/soc/bcm/Makefile linux-3.12.37/sound/soc/bcm/Makefile
---- linux-3.12.37.orig/sound/soc/bcm/Makefile 2015-02-18 14:32:15.128546928 +0100
-+++ linux-3.12.37/sound/soc/bcm/Makefile 2015-02-18 15:18:39.484560386 +0100
-@@ -10,6 +10,7 @@
- snd-soc-hifiberry-amp-objs := hifiberry_amp.o
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-+snd-soc-rpi-proto-objs := rpi-proto.o
-
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
-@@ -17,3 +18,4 @@
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
-diff -Nur linux-3.12.37.orig/sound/soc/bcm/rpi-proto.c linux-3.12.37/sound/soc/bcm/rpi-proto.c
---- linux-3.12.37.orig/sound/soc/bcm/rpi-proto.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-3.12.37/sound/soc/bcm/rpi-proto.c 2015-02-18 15:10:01.164557881 +0100
-@@ -0,0 +1,130 @@
-+/*
-+ * ASoC driver for PROTO AudioCODEC (with a WM8731)
-+ * connected to a Raspberry Pi
-+ *
-+ * Author: Florian Meier, <koalo@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8731.h"
-+
-+static const unsigned int wm8731_rates_12288000[] = {
-+ 8000, 32000, 48000, 96000,
-+};
-+
-+static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {
-+ .list = wm8731_rates_12288000,
-+ .count = ARRAY_SIZE(wm8731_rates_12288000),
-+};
-+
-+static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)
-+{
-+ /* Setup constraints, because there is a 12.288 MHz XTAL on the board */
-+ snd_pcm_hw_constraint_list(substream->runtime, 0,
-+ SNDRV_PCM_HW_PARAM_RATE,
-+ &wm8731_constraints_12288000);
-+ return 0;
-+}
-+
-+static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+ int sysclk = 12288000; /* This is fixed on this board */
-+
-+ /* Set proto bclk */
-+ int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2);
-+ if (ret < 0){
-+ dev_err(substream->pcm->dev,
-+ "Failed to set BCLK ratio %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Set proto sysclk */
-+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
-+ sysclk, SND_SOC_CLOCK_IN);
-+ if (ret < 0) {
-+ dev_err(substream->pcm->dev,
-+ "Failed to set WM8731 SYSCLK: %d\n", ret);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_proto_ops = {
-+ .startup = snd_rpi_proto_startup,
-+ .hw_params = snd_rpi_proto_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_proto_dai[] = {
-+{
-+ .name = "WM8731",
-+ .stream_name = "WM8731 HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "wm8731-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "wm8731.1-001a",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S
-+ | SND_SOC_DAIFMT_NB_NF
-+ | SND_SOC_DAIFMT_CBM_CFM,
-+ .ops = &snd_rpi_proto_ops,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_proto = {
-+ .name = "snd_rpi_proto",
-+ .dai_link = snd_rpi_proto_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_proto_dai),
-+};
-+
-+static int snd_rpi_proto_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_proto.dev = &pdev->dev;
-+ ret = snd_soc_register_card(&snd_rpi_proto);
-+ if (ret) {
-+ dev_err(&pdev->dev,
-+ "snd_soc_register_card() failed: %d\n", ret);
-+ }
-+
-+ return ret;
-+}
-+
-+
-+static int snd_rpi_proto_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_proto);
-+}
-+
-+static struct platform_driver snd_rpi_proto_driver = {
-+ .driver = {
-+ .name = "snd-rpi-proto",
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = snd_rpi_proto_probe,
-+ .remove = snd_rpi_proto_remove,
-+};
-+
-+module_platform_driver(snd_rpi_proto_driver);
-+
-+MODULE_AUTHOR("Florian Meier");
-+MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)");
-+MODULE_LICENSE("GPL");
diff --git a/target/arm/bcm28xx/patches/3.18.16/0000-raspberry-pi.patch b/target/arm/bcm28xx/patches/3.18.16/0000-raspberry-pi.patch
deleted file mode 100644
index 05e671894..000000000
--- a/target/arm/bcm28xx/patches/3.18.16/0000-raspberry-pi.patch
+++ /dev/null
@@ -1,139856 +0,0 @@
-diff -Nur linux-3.18.14/arch/arm/boot/dts/ads7846-overlay.dts linux-rpi/arch/arm/boot/dts/ads7846-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/ads7846-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/ads7846-overlay.dts 2015-05-31 14:46:07.961661006 -0500
-@@ -0,0 +1,83 @@
-+/*
-+ * Generic Device Tree overlay for the ADS7846 touch controller
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ ads7846_pins: ads7846_pins {
-+ brcm,pins = <255>; /* illegal default value */
-+ brcm,function = <0>; /* in */
-+ brcm,pull = <0>; /* none */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ads7846: ads7846@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ads7846_pins>;
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <255 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 255 0>;
-+
-+ /* driver defaults */
-+ ti,x-min = /bits/ 16 <0>;
-+ ti,y-min = /bits/ 16 <0>;
-+ ti,x-max = /bits/ 16 <0x0FFF>;
-+ ti,y-max = /bits/ 16 <0x0FFF>;
-+ ti,pressure-min = /bits/ 16 <0>;
-+ ti,pressure-max = /bits/ 16 <0xFFFF>;
-+ ti,x-plate-ohms = /bits/ 16 <400>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ cs = <&ads7846>,"reg:0";
-+ speed = <&ads7846>,"spi-max-frequency:0";
-+ penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */
-+ <&ads7846>,"interrupts:0",
-+ <&ads7846>,"pendown-gpio:4";
-+ penirq_pull = <&ads7846_pins>,"brcm,pull:0";
-+ swapxy = <&ads7846>,"ti,swap-xy?";
-+ xmin = <&ads7846>,"ti,x-min;0";
-+ ymin = <&ads7846>,"ti,y-min;0";
-+ xmax = <&ads7846>,"ti,x-max;0";
-+ ymax = <&ads7846>,"ti,y-max;0";
-+ pmin = <&ads7846>,"ti,pressure-min;0";
-+ pmax = <&ads7846>,"ti,pressure-max;0";
-+ xohms = <&ads7846>,"ti,x-plate-ohms;0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2708.dtsi linux-rpi/arch/arm/boot/dts/bcm2708.dtsi
---- linux-3.18.14/arch/arm/boot/dts/bcm2708.dtsi 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2708.dtsi 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,128 @@
-+/include/ "skeleton.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+ model = "BCM2708";
-+
-+ interrupt-parent = <&intc>;
-+
-+ chosen {
-+ /* No padding required - the boot loader can do that. */
-+ bootargs = "";
-+ };
-+
-+ soc: soc {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x7e000000 0x20000000 0x01000000>;
-+
-+ intc: interrupt-controller {
-+ compatible = "brcm,bcm2708-armctrl-ic";
-+ reg = <0x7e00b200 0x200>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio: gpio {
-+ compatible = "brcm,bcm2835-gpio";
-+ reg = <0x7e200000 0xb4>;
-+ interrupts = <2 17>, <2 18>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ mmc: mmc@7e300000 {
-+ compatible = "brcm,bcm2835-mmc";
-+ reg = <0x7e300000 0x100>;
-+ interrupts = <2 30>;
-+ clocks = <&clk_mmc>;
-+ //dmas = <&dma 11>,
-+ // <&dma 11>;
-+ dma-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
-+ i2s: i2s@7e203000 {
-+ compatible = "brcm,bcm2708-i2s";
-+ reg = <0x7e203000 0x20>,
-+ <0x7e101098 0x02>;
-+
-+ //dmas = <&dma 2>,
-+ // <&dma 3>;
-+ dma-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
-+ spi0: spi@7e204000 {
-+ compatible = "brcm,bcm2708-spi";
-+ reg = <0x7e204000 0x1000>;
-+ interrupts = <2 22>;
-+ clocks = <&clk_spi>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c0: i2c@7e205000 {
-+ compatible = "brcm,bcm2708-i2c";
-+ reg = <0x7e205000 0x1000>;
-+ interrupts = <2 21>;
-+ clocks = <&clk_i2c>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c1: i2c@7e804000 {
-+ compatible = "brcm,bcm2708-i2c";
-+ reg = <0x7e804000 0x1000>;
-+ interrupts = <2 21>;
-+ clocks = <&clk_i2c>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ leds: leds {
-+ compatible = "gpio-leds";
-+ };
-+
-+ arm-pmu {
-+ compatible = "arm,arm1176-pmu";
-+ };
-+ };
-+
-+ clocks {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ clk_mmc: clock@0 {
-+ compatible = "fixed-clock";
-+ reg = <0>;
-+ #clock-cells = <0>;
-+ clock-output-names = "mmc";
-+ clock-frequency = <250000000>;
-+ };
-+
-+ clk_i2c: i2c {
-+ compatible = "fixed-clock";
-+ reg = <1>;
-+ #clock-cells = <0>;
-+ clock-frequency = <250000000>;
-+ };
-+
-+ clk_spi: clock@2 {
-+ compatible = "fixed-clock";
-+ reg = <2>;
-+ #clock-cells = <0>;
-+ clock-output-names = "spi";
-+ clock-frequency = <250000000>;
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-b.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts
---- linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-b.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,112 @@
-+/dts-v1/;
-+
-+/include/ "bcm2708.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+ model = "Raspberry Pi Model B";
-+
-+ aliases {
-+ soc = &soc;
-+ spi0 = &spi0;
-+ i2c0 = &i2c0;
-+ i2c1 = &i2c1;
-+ i2s = &i2s;
-+ gpio = &gpio;
-+ intc = &intc;
-+ leds = &leds;
-+ sound = &sound;
-+ };
-+
-+ sound: sound {
-+ };
-+};
-+
-+&gpio {
-+ spi0_pins: spi0_pins {
-+ brcm,pins = <7 8 9 10 11>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+
-+ i2c0_pins: i2c0 {
-+ brcm,pins = <0 1>;
-+ brcm,function = <4>;
-+ };
-+
-+ i2c1_pins: i2c1 {
-+ brcm,pins = <2 3>;
-+ brcm,function = <4>;
-+ };
-+
-+ i2s_pins: i2s {
-+ brcm,pins = <28 29 30 31>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+};
-+
-+&mmc {
-+ status = "okay";
-+ bus-width = <4>;
-+};
-+
-+&spi0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi0_pins>;
-+
-+ spidev@0{
-+ compatible = "spidev";
-+ reg = <0>; /* CE0 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi-max-frequency = <500000>;
-+ };
-+
-+ spidev@1{
-+ compatible = "spidev";
-+ reg = <1>; /* CE1 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi-max-frequency = <500000>;
-+ };
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins>;
-+ clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c1_pins>;
-+ clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+ #sound-dai-cells = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+ act_led: act {
-+ label = "led0";
-+ linux,default-trigger = "mmc0";
-+ gpios = <&gpio 16 1>;
-+ };
-+};
-+
-+/ {
-+ __overrides__ {
-+ i2s = <&i2s>,"status";
-+ spi = <&spi0>,"status";
-+ i2c0 = <&i2c0>,"status";
-+ i2c1 = <&i2c1>,"status";
-+ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
-+ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
-+
-+ act_led_gpio = <&act_led>,"gpios:4";
-+ act_led_activelow = <&act_led>,"gpios:8";
-+ act_led_trigger = <&act_led>,"linux,default-trigger";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
---- linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,122 @@
-+/dts-v1/;
-+
-+/include/ "bcm2708.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+ model = "Raspberry Pi Model B+";
-+
-+ aliases {
-+ soc = &soc;
-+ spi0 = &spi0;
-+ i2c0 = &i2c0;
-+ i2c1 = &i2c1;
-+ i2s = &i2s;
-+ gpio = &gpio;
-+ intc = &intc;
-+ leds = &leds;
-+ sound = &sound;
-+ };
-+
-+ sound: sound {
-+ };
-+};
-+
-+&gpio {
-+ spi0_pins: spi0_pins {
-+ brcm,pins = <7 8 9 10 11>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+
-+ i2c0_pins: i2c0 {
-+ brcm,pins = <0 1>;
-+ brcm,function = <4>;
-+ };
-+
-+ i2c1_pins: i2c1 {
-+ brcm,pins = <2 3>;
-+ brcm,function = <4>;
-+ };
-+
-+ i2s_pins: i2s {
-+ brcm,pins = <18 19 20 21>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+};
-+
-+&mmc {
-+ status = "okay";
-+ bus-width = <4>;
-+};
-+
-+&spi0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi0_pins>;
-+
-+ spidev@0{
-+ compatible = "spidev";
-+ reg = <0>; /* CE0 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi-max-frequency = <500000>;
-+ };
-+
-+ spidev@1{
-+ compatible = "spidev";
-+ reg = <1>; /* CE1 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi-max-frequency = <500000>;
-+ };
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins>;
-+ clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c1_pins>;
-+ clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+ #sound-dai-cells = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+ act_led: act {
-+ label = "led0";
-+ linux,default-trigger = "mmc0";
-+ gpios = <&gpio 47 0>;
-+ };
-+
-+ pwr_led: pwr {
-+ label = "led1";
-+ linux,default-trigger = "input";
-+ gpios = <&gpio 35 0>;
-+ };
-+};
-+
-+/ {
-+ __overrides__ {
-+ i2s = <&i2s>,"status";
-+ spi = <&spi0>,"status";
-+ i2c0 = <&i2c0>,"status";
-+ i2c1 = <&i2c1>,"status";
-+ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
-+ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
-+
-+ act_led_gpio = <&act_led>,"gpios:4";
-+ act_led_activelow = <&act_led>,"gpios:8";
-+ act_led_trigger = <&act_led>,"linux,default-trigger";
-+
-+ pwr_led_gpio = <&pwr_led>,"gpios:4";
-+ pwr_led_activelow = <&pwr_led>,"gpios:8";
-+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-cm.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts
---- linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-cm.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,7 @@
-+/dts-v1/;
-+
-+/include/ "bcm2708-rpi-cm.dtsi"
-+
-+/ {
-+ model = "Raspberry Pi Compute Module";
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi
---- linux-3.18.14/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,39 @@
-+/include/ "bcm2708.dtsi"
-+
-+/ {
-+ aliases {
-+ soc = &soc;
-+ spi0 = &spi0;
-+ i2c0 = &i2c0;
-+ i2c1 = &i2c1;
-+ i2s = &i2s;
-+ gpio = &gpio;
-+ intc = &intc;
-+ leds = &leds;
-+ sound = &sound;
-+ };
-+
-+ sound: sound {
-+ };
-+};
-+
-+&leds {
-+ act_led: act {
-+ label = "led0";
-+ linux,default-trigger = "mmc0";
-+ gpios = <&gpio 47 0>;
-+ };
-+};
-+
-+&mmc {
-+ status = "okay";
-+ bus-width = <4>;
-+};
-+
-+/ {
-+ __overrides__ {
-+ act_led_gpio = <&act_led>,"gpios:4";
-+ act_led_activelow = <&act_led>,"gpios:8";
-+ act_led_trigger = <&act_led>,"linux,default-trigger";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2709.dtsi linux-rpi/arch/arm/boot/dts/bcm2709.dtsi
---- linux-3.18.14/arch/arm/boot/dts/bcm2709.dtsi 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2709.dtsi 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,179 @@
-+/include/ "skeleton.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm2709";
-+ model = "BCM2709";
-+
-+ interrupt-parent = <&intc>;
-+
-+ chosen {
-+ /* No padding required - the boot loader can do that. */
-+ bootargs = "";
-+ };
-+
-+ soc: soc {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x7e000000 0x3f000000 0x01000000>;
-+
-+ intc: interrupt-controller {
-+ compatible = "brcm,bcm2708-armctrl-ic";
-+ reg = <0x7e00b200 0x200>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ gpio: gpio {
-+ compatible = "brcm,bcm2835-gpio";
-+ reg = <0x7e200000 0xb4>;
-+ interrupts = <2 17>, <2 18>;
-+
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+
-+ mmc: mmc@7e300000 {
-+ compatible = "brcm,bcm2835-mmc";
-+ reg = <0x7e300000 0x100>;
-+ interrupts = <2 30>;
-+ clocks = <&clk_mmc>;
-+ //dmas = <&dma 11>,
-+ // <&dma 11>;
-+ dma-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
-+ i2s: i2s@7e203000 {
-+ compatible = "brcm,bcm2708-i2s";
-+ reg = <0x7e203000 0x20>,
-+ <0x7e101098 0x02>;
-+
-+ //dmas = <&dma 2>,
-+ // <&dma 3>;
-+ dma-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
-+ spi0: spi@7e204000 {
-+ compatible = "brcm,bcm2708-spi";
-+ reg = <0x7e204000 0x1000>;
-+ interrupts = <2 22>;
-+ clocks = <&clk_spi>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c0: i2c@7e205000 {
-+ compatible = "brcm,bcm2708-i2c";
-+ reg = <0x7e205000 0x1000>;
-+ interrupts = <2 21>;
-+ clocks = <&clk_i2c>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ i2c1: i2c@7e804000 {
-+ compatible = "brcm,bcm2708-i2c";
-+ reg = <0x7e804000 0x1000>;
-+ interrupts = <2 21>;
-+ clocks = <&clk_i2c>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ leds: leds {
-+ compatible = "gpio-leds";
-+ };
-+
-+ arm-pmu {
-+ compatible = "arm,cortex-a7-pmu";
-+ interrupts = <3 9>;
-+ };
-+ };
-+
-+ clocks {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ clk_mmc: clock@0 {
-+ compatible = "fixed-clock";
-+ reg = <0>;
-+ #clock-cells = <0>;
-+ clock-output-names = "mmc";
-+ clock-frequency = <250000000>;
-+ };
-+
-+ clk_i2c: i2c {
-+ compatible = "fixed-clock";
-+ reg = <1>;
-+ #clock-cells = <0>;
-+ clock-frequency = <250000000>;
-+ };
-+
-+ clk_spi: clock@2 {
-+ compatible = "fixed-clock";
-+ reg = <2>;
-+ #clock-cells = <0>;
-+ clock-output-names = "spi";
-+ clock-frequency = <250000000>;
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv7-timer";
-+ clock-frequency = <19200000>;
-+ interrupts = <3 0>, // PHYS_SECURE_PPI
-+ <3 1>, // PHYS_NONSECURE_PPI
-+ <3 3>, // VIRT_PPI
-+ <3 2>; // HYP_PPI
-+ always-on;
-+ };
-+
-+ cpus: cpus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ v7_cpu0: cpu@0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a7";
-+ reg = <0xf00>;
-+ clock-frequency = <800000000>;
-+ };
-+
-+ v7_cpu1: cpu@1 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a7";
-+ reg = <0xf01>;
-+ clock-frequency = <800000000>;
-+ };
-+
-+ v7_cpu2: cpu@2 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a7";
-+ reg = <0xf02>;
-+ clock-frequency = <800000000>;
-+ };
-+
-+ v7_cpu3: cpu@3 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a7";
-+ reg = <0xf03>;
-+ clock-frequency = <800000000>;
-+ };
-+ };
-+
-+ __overrides__ {
-+ arm_freq = <&v7_cpu0>, "clock-frequency:0",
-+ <&v7_cpu1>, "clock-frequency:0",
-+ <&v7_cpu2>, "clock-frequency:0",
-+ <&v7_cpu3>, "clock-frequency:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2709-rpi-2-b.dts linux-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
---- linux-3.18.14/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,122 @@
-+/dts-v1/;
-+
-+/include/ "bcm2709.dtsi"
-+
-+/ {
-+ compatible = "brcm,bcm2709";
-+ model = "Raspberry Pi 2 Model B";
-+
-+ aliases {
-+ soc = &soc;
-+ spi0 = &spi0;
-+ i2c0 = &i2c0;
-+ i2c1 = &i2c1;
-+ i2s = &i2s;
-+ gpio = &gpio;
-+ intc = &intc;
-+ leds = &leds;
-+ sound = &sound;
-+ };
-+
-+ sound: sound {
-+ };
-+};
-+
-+&gpio {
-+ spi0_pins: spi0_pins {
-+ brcm,pins = <7 8 9 10 11>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+
-+ i2c0_pins: i2c0 {
-+ brcm,pins = <0 1>;
-+ brcm,function = <4>;
-+ };
-+
-+ i2c1_pins: i2c1 {
-+ brcm,pins = <2 3>;
-+ brcm,function = <4>;
-+ };
-+
-+ i2s_pins: i2s {
-+ brcm,pins = <18 19 20 21>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+};
-+
-+&mmc {
-+ status = "okay";
-+ bus-width = <4>;
-+};
-+
-+&spi0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi0_pins>;
-+
-+ spidev@0{
-+ compatible = "spidev";
-+ reg = <0>; /* CE0 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi-max-frequency = <500000>;
-+ };
-+
-+ spidev@1{
-+ compatible = "spidev";
-+ reg = <1>; /* CE1 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi-max-frequency = <500000>;
-+ };
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins>;
-+ clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c1_pins>;
-+ clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+ #sound-dai-cells = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+ act_led: act {
-+ label = "led0";
-+ linux,default-trigger = "mmc0";
-+ gpios = <&gpio 47 0>;
-+ };
-+
-+ pwr_led: pwr {
-+ label = "led1";
-+ linux,default-trigger = "input";
-+ gpios = <&gpio 35 0>;
-+ };
-+};
-+
-+/ {
-+ __overrides__ {
-+ i2s = <&i2s>,"status";
-+ spi = <&spi0>,"status";
-+ i2c0 = <&i2c0>,"status";
-+ i2c1 = <&i2c1>,"status";
-+ i2c0_baudrate = <&i2c0>,"clock-frequency:0";
-+ i2c1_baudrate = <&i2c1>,"clock-frequency:0";
-+
-+ act_led_gpio = <&act_led>,"gpios:4";
-+ act_led_activelow = <&act_led>,"gpios:8";
-+ act_led_trigger = <&act_led>,"linux,default-trigger";
-+
-+ pwr_led_gpio = <&pwr_led>,"gpios:4";
-+ pwr_led_activelow = <&pwr_led>,"gpios:8";
-+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2835.dtsi linux-rpi/arch/arm/boot/dts/bcm2835.dtsi
---- linux-3.18.14/arch/arm/boot/dts/bcm2835.dtsi 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/boot/dts/bcm2835.dtsi 2015-05-31 14:46:07.981661006 -0500
-@@ -122,11 +122,14 @@
- status = "disabled";
- };
-
-- sdhci: sdhci@7e300000 {
-- compatible = "brcm,bcm2835-sdhci";
-+ mmc: mmc@7e300000 {
-+ compatible = "brcm,bcm2835-mmc";
- reg = <0x7e300000 0x100>;
- interrupts = <2 30>;
- clocks = <&clk_mmc>;
-+ dmas = <&dma 11>,
-+ <&dma 11>;
-+ dma-names = "tx", "rx";
- status = "disabled";
- };
-
-@@ -161,7 +164,7 @@
- reg = <0>;
- #clock-cells = <0>;
- clock-output-names = "mmc";
-- clock-frequency = <100000000>;
-+ clock-frequency = <250000000>;
- };
-
- clk_i2c: clock@1 {
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bcm2835-rpi-b.dts linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts
---- linux-3.18.14/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -57,7 +57,7 @@
- clock-frequency = <100000>;
- };
-
--&sdhci {
-+&mmc {
- status = "okay";
- bus-width = <4>;
- };
-diff -Nur linux-3.18.14/arch/arm/boot/dts/bmp085_i2c-sensor-overlay.dts linux-rpi/arch/arm/boot/dts/bmp085_i2c-sensor-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/bmp085_i2c-sensor-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/bmp085_i2c-sensor-overlay.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,23 @@
-+// Definitions for BMP085/BMP180 digital barometric pressure and temperature sensors from Bosch Sensortec
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ bmp085@77 {
-+ compatible = "bosch,bmp085";
-+ reg = <0x77>;
-+ default-oversampling = <3>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/ds1307-rtc-overlay.dts linux-rpi/arch/arm/boot/dts/ds1307-rtc-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/ds1307-rtc-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/ds1307-rtc-overlay.dts 2015-05-31 14:46:07.981661006 -0500
-@@ -0,0 +1,22 @@
-+// Definitions for DS1307 Real Time Clock
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ ds1307@68 {
-+ compatible = "maxim,ds1307";
-+ reg = <0x68>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/enc28j60-overlay.dts linux-rpi/arch/arm/boot/dts/enc28j60-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/enc28j60-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/enc28j60-overlay.dts 2015-05-31 14:46:07.985661006 -0500
-@@ -0,0 +1,50 @@
-+// Overlay for the Microchip ENC28J60 Ethernet Controller
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ eth1: enc28j60@0{
-+ compatible = "microchip,enc28j60";
-+ reg = <0>; /* CE0 */
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&eth1_pins>;
-+ interrupt-parent = <&gpio>;
-+ interrupts = <25 0x2>; /* falling edge */
-+ spi-max-frequency = <12000000>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ eth1_pins: eth1_pins {
-+ brcm,pins = <25>;
-+ brcm,function = <0>; /* in */
-+ brcm,pull = <0>; /* none */
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ int_pin = <&eth1>, "interrupts:0",
-+ <&eth1_pins>, "brcm,pins:0";
-+ speed = <&eth1>, "spi-max-frequency:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/hifiberry-amp-overlay.dts linux-rpi/arch/arm/boot/dts/hifiberry-amp-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/hifiberry-amp-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/hifiberry-amp-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for HiFiBerry Amp/Amp+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "hifiberry,hifiberry-amp";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ tas5713@1b {
-+ #sound-dai-cells = <0>;
-+ compatible = "ti,tas5713";
-+ reg = <0x1b>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/hifiberry-dac-overlay.dts linux-rpi/arch/arm/boot/dts/hifiberry-dac-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/hifiberry-dac-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/hifiberry-dac-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,34 @@
-+// Definitions for HiFiBerry DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "hifiberry,hifiberry-dac";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target-path = "/";
-+ __overlay__ {
-+ pcm5102a-codec {
-+ #sound-dai-cells = <0>;
-+ compatible = "ti,pcm5102a";
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/hifiberry-dacplus-overlay.dts linux-rpi/arch/arm/boot/dts/hifiberry-dacplus-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/hifiberry-dacplus-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/hifiberry-dacplus-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for HiFiBerry DAC+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "hifiberry,hifiberry-dacplus";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ pcm5122@4d {
-+ #sound-dai-cells = <0>;
-+ compatible = "ti,pcm5122";
-+ reg = <0x4d>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/hifiberry-digi-overlay.dts linux-rpi/arch/arm/boot/dts/hifiberry-digi-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/hifiberry-digi-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/hifiberry-digi-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for HiFiBerry Digi
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "hifiberry,hifiberry-digi";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ wm8804@3b {
-+ #sound-dai-cells = <0>;
-+ compatible = "wlf,wm8804";
-+ reg = <0x3b>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/hy28a-overlay.dts linux-rpi/arch/arm/boot/dts/hy28a-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/hy28a-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/hy28a-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,87 @@
-+/*
-+ * Device Tree overlay for HY28A display
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ hy28a_pins: hy28a_pins {
-+ brcm,pins = <17 25 18>;
-+ brcm,function = <0 1 1>; /* in out out */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ hy28a: hy28a@0{
-+ compatible = "ilitek,ili9320";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hy28a_pins>;
-+
-+ spi-max-frequency = <32000000>;
-+ spi-cpol;
-+ spi-cpha;
-+ rotate = <270>;
-+ bgr;
-+ fps = <50>;
-+ buswidth = <8>;
-+ startbyte = <0x70>;
-+ reset-gpios = <&gpio 25 0>;
-+ led-gpios = <&gpio 18 1>;
-+ debug = <0>;
-+ };
-+
-+ hy28a_ts: hy28a-ts@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <17 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 17 0>;
-+ ti,x-plate-ohms = /bits/ 16 <100>;
-+ ti,pressure-max = /bits/ 16 <255>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ speed = <&hy28a>,"spi-max-frequency:0";
-+ rotate = <&hy28a>,"rotate:0";
-+ fps = <&hy28a>,"fps:0";
-+ debug = <&hy28a>,"debug:0";
-+ xohms = <&hy28a_ts>,"ti,x-plate-ohms;0";
-+ resetgpio = <&hy28a>,"reset-gpios:4",
-+ <&hy28a_pins>, "brcm,pins:1";
-+ ledgpio = <&hy28a>,"led-gpios:4",
-+ <&hy28a_pins>, "brcm,pins:2";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/hy28b-overlay.dts linux-rpi/arch/arm/boot/dts/hy28b-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/hy28b-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/hy28b-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,142 @@
-+/*
-+ * Device Tree overlay for HY28b display shield by Texy
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ hy28b_pins: hy28b_pins {
-+ brcm,pins = <17 25 18>;
-+ brcm,function = <0 1 1>; /* in out out */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ hy28b: hy28b@0{
-+ compatible = "ilitek,ili9325";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hy28b_pins>;
-+
-+ spi-max-frequency = <48000000>;
-+ spi-cpol;
-+ spi-cpha;
-+ rotate = <270>;
-+ bgr;
-+ fps = <50>;
-+ buswidth = <8>;
-+ startbyte = <0x70>;
-+ reset-gpios = <&gpio 25 0>;
-+ led-gpios = <&gpio 18 1>;
-+
-+ gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7";
-+
-+ init = <0x10000e7 0x0010
-+ 0x1000000 0x0001
-+ 0x1000001 0x0100
-+ 0x1000002 0x0700
-+ 0x1000003 0x1030
-+ 0x1000004 0x0000
-+ 0x1000008 0x0207
-+ 0x1000009 0x0000
-+ 0x100000a 0x0000
-+ 0x100000c 0x0001
-+ 0x100000d 0x0000
-+ 0x100000f 0x0000
-+ 0x1000010 0x0000
-+ 0x1000011 0x0007
-+ 0x1000012 0x0000
-+ 0x1000013 0x0000
-+ 0x2000032
-+ 0x1000010 0x1590
-+ 0x1000011 0x0227
-+ 0x2000032
-+ 0x1000012 0x009c
-+ 0x2000032
-+ 0x1000013 0x1900
-+ 0x1000029 0x0023
-+ 0x100002b 0x000e
-+ 0x2000032
-+ 0x1000020 0x0000
-+ 0x1000021 0x0000
-+ 0x2000032
-+ 0x1000050 0x0000
-+ 0x1000051 0x00ef
-+ 0x1000052 0x0000
-+ 0x1000053 0x013f
-+ 0x1000060 0xa700
-+ 0x1000061 0x0001
-+ 0x100006a 0x0000
-+ 0x1000080 0x0000
-+ 0x1000081 0x0000
-+ 0x1000082 0x0000
-+ 0x1000083 0x0000
-+ 0x1000084 0x0000
-+ 0x1000085 0x0000
-+ 0x1000090 0x0010
-+ 0x1000092 0x0000
-+ 0x1000093 0x0003
-+ 0x1000095 0x0110
-+ 0x1000097 0x0000
-+ 0x1000098 0x0000
-+ 0x1000007 0x0133
-+ 0x1000020 0x0000
-+ 0x1000021 0x0000
-+ 0x2000064>;
-+ debug = <0>;
-+ };
-+
-+ hy28b_ts: hy28b-ts@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <17 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 17 0>;
-+ ti,x-plate-ohms = /bits/ 16 <100>;
-+ ti,pressure-max = /bits/ 16 <255>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ speed = <&hy28b>,"spi-max-frequency:0";
-+ rotate = <&hy28b>,"rotate:0";
-+ fps = <&hy28b>,"fps:0";
-+ debug = <&hy28b>,"debug:0";
-+ xohms = <&hy28b_ts>,"ti,x-plate-ohms;0";
-+ resetgpio = <&hy28b>,"reset-gpios:4",
-+ <&hy28b_pins>, "brcm,pins:1";
-+ ledgpio = <&hy28b>,"led-gpios:4",
-+ <&hy28b_pins>, "brcm,pins:2";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/i2c-rtc-overlay.dts linux-rpi/arch/arm/boot/dts/i2c-rtc-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/i2c-rtc-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/i2c-rtc-overlay.dts 2015-05-31 14:46:08.001661006 -0500
-@@ -0,0 +1,49 @@
-+// Definitions for several I2C based Real Time Clocks
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ ds1307: ds1307@68 {
-+ compatible = "maxim,ds1307";
-+ reg = <0x68>;
-+ status = "disable";
-+ };
-+ ds3231: ds3231@68 {
-+ compatible = "maxim,ds3231";
-+ reg = <0x68>;
-+ status = "disable";
-+ };
-+ pcf2127: pcf2127@51 {
-+ compatible = "nxp,pcf2127";
-+ reg = <0x51>;
-+ status = "disable";
-+ };
-+ pcf8523: pcf8523@68 {
-+ compatible = "nxp,pcf8523";
-+ reg = <0x68>;
-+ status = "disable";
-+ };
-+ pcf8563: pcf8563@51 {
-+ compatible = "nxp,pcf8563";
-+ reg = <0x51>;
-+ status = "disable";
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ ds1307 = <&ds1307>,"status";
-+ ds3231 = <&ds3231>,"status";
-+ pcf2127 = <&pcf2127>,"status";
-+ pcf8523 = <&pcf8523>,"status";
-+ pcf8563 = <&pcf8563>,"status";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/iqaudio-dac-overlay.dts linux-rpi/arch/arm/boot/dts/iqaudio-dac-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/iqaudio-dac-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/iqaudio-dac-overlay.dts 2015-05-31 14:46:08.029661006 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for IQaudIO DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "iqaudio,iqaudio-dac";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ pcm5122@4c {
-+ #sound-dai-cells = <0>;
-+ compatible = "ti,pcm5122";
-+ reg = <0x4c>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/iqaudio-dacplus-overlay.dts linux-rpi/arch/arm/boot/dts/iqaudio-dacplus-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/iqaudio-dacplus-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/iqaudio-dacplus-overlay.dts 2015-05-31 14:46:08.029661006 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for IQaudIO DAC+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "iqaudio,iqaudio-dac";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ pcm5122@4c {
-+ #sound-dai-cells = <0>;
-+ compatible = "ti,pcm5122";
-+ reg = <0x4c>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/lirc-rpi-overlay.dts linux-rpi/arch/arm/boot/dts/lirc-rpi-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/lirc-rpi-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/lirc-rpi-overlay.dts 2015-05-31 14:46:08.033661006 -0500
-@@ -0,0 +1,57 @@
-+// Definitions for lirc-rpi module
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target-path = "/";
-+ __overlay__ {
-+ lirc_rpi: lirc_rpi {
-+ compatible = "rpi,lirc-rpi";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lirc_pins>;
-+ status = "okay";
-+
-+ // Override autodetection of IR receiver circuit
-+ // (0 = active high, 1 = active low, -1 = no override )
-+ rpi,sense = <0xffffffff>;
-+
-+ // Software carrier
-+ // (0 = off, 1 = on)
-+ rpi,softcarrier = <1>;
-+
-+ // Invert output
-+ // (0 = off, 1 = on)
-+ rpi,invert = <0>;
-+
-+ // Enable debugging messages
-+ // (0 = off, 1 = on)
-+ rpi,debug = <0>;
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ lirc_pins: lirc_pins {
-+ brcm,pins = <17 18>;
-+ brcm,function = <1 0>; // out in
-+ brcm,pull = <0 1>; // off down
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ gpio_out_pin = <&lirc_pins>,"brcm,pins:0";
-+ gpio_in_pin = <&lirc_pins>,"brcm,pins:4";
-+ gpio_in_pull = <&lirc_pins>,"brcm,pull:4";
-+
-+ sense = <&lirc_rpi>,"rpi,sense:0";
-+ softcarrier = <&lirc_rpi>,"rpi,softcarrier:0";
-+ invert = <&lirc_rpi>,"rpi,invert:0";
-+ debug = <&lirc_rpi>,"rpi,debug:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/Makefile linux-rpi/arch/arm/boot/dts/Makefile
---- linux-3.18.14/arch/arm/boot/dts/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/boot/dts/Makefile 2015-05-31 14:46:07.961661006 -0500
-@@ -53,7 +53,50 @@
-
- dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
- dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
-+
-+# Raspberry Pi
-+ifeq ($(CONFIG_BCM2708_DT),y)
-+ RPI_DT_OVERLAYS=y
-+endif
-+ifeq ($(CONFIG_BCM2709_DT),y)
-+ RPI_DT_OVERLAYS=y
-+endif
-+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb
-+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb
-+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-cm.dtb
-+dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb
-+dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += ds1307-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += i2c-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-digi-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hy28a-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += hy28b-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pcf2127-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pcf8523-rtc-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb
-+dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
-+
- dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
- dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
- dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
-@@ -519,6 +562,12 @@
-
- targets += dtbs dtbs_install
- targets += $(dtb-y)
-+
-+endif
-+
-+# Enable fixups to support overlays on BCM2708 platforms
-+ifeq ($(RPI_DT_OVERLAYS),y)
-+ DTC_FLAGS ?= -@
- endif
-
- # *.dtb used to be generated in the directory above. Clean out the
-diff -Nur linux-3.18.14/arch/arm/boot/dts/mcp2515-can0-overlay.dts linux-rpi/arch/arm/boot/dts/mcp2515-can0-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/mcp2515-can0-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/mcp2515-can0-overlay.dts 2015-05-31 14:46:08.033661006 -0500
-@@ -0,0 +1,69 @@
-+/*
-+ * Device tree overlay for mcp251x/can0 on spi0.0
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+ /* disable spi-dev for spi0.0 */
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+ spidev@0{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ /* the interrupt pin of the can-controller */
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ can0_pins: can0_pins {
-+ brcm,pins = <25>;
-+ brcm,function = <0>; /* input */
-+ };
-+ };
-+ };
-+
-+ /* the clock/oscillator of the can-controller */
-+ fragment@2 {
-+ target-path = "/clocks";
-+ __overlay__ {
-+ /* external oscillator of mcp2515 on SPI0.0 */
-+ can0_osc: can0_osc {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <16000000>;
-+ };
-+ };
-+ };
-+
-+ /* the spi config of the can-controller itself binding everything together */
-+ fragment@3 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ can0: mcp2515@0 {
-+ reg = <0>;
-+ compatible = "microchip,mcp2515";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&can0_pins>;
-+ spi-max-frequency = <10000000>;
-+ interrupt-parent = <&gpio>;
-+ interrupts = <25 0x2>;
-+ clocks = <&can0_osc>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ oscillator = <&can0_osc>,"clock-frequency:0";
-+ spimaxfrequency = <&can0>,"spi-max-frequency:0";
-+ interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/mmc-overlay.dts linux-rpi/arch/arm/boot/dts/mmc-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/mmc-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/mmc-overlay.dts 2015-05-31 14:46:08.033661006 -0500
-@@ -0,0 +1,19 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&mmc>;
-+
-+ __overlay__ {
-+ brcm,overclock-50 = <0>;
-+ };
-+ };
-+
-+ __overrides__ {
-+ overclock_50 = <&mmc>,"brcm,overclock-50:0";
-+ force_pio = <&mmc>,"brcm,force-pio?";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/mz61581-overlay.dts linux-rpi/arch/arm/boot/dts/mz61581-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/mz61581-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/mz61581-overlay.dts 2015-05-31 14:46:08.041661006 -0500
-@@ -0,0 +1,109 @@
-+/*
-+ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ mz61581_pins: mz61581_pins {
-+ brcm,pins = <4 15 18 25>;
-+ brcm,function = <0 1 1 1>; /* in out out out */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mz61581: mz61581@0{
-+ compatible = "samsung,s6d02a1";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mz61581_pins>;
-+
-+ spi-max-frequency = <128000000>;
-+ spi-cpol;
-+ spi-cpha;
-+
-+ width = <320>;
-+ height = <480>;
-+ rotate = <270>;
-+ bgr;
-+ fps = <30>;
-+ buswidth = <8>;
-+
-+ reset-gpios = <&gpio 15 0>;
-+ dc-gpios = <&gpio 25 0>;
-+ led-gpios = <&gpio 18 0>;
-+
-+ init = <0x10000b0 00
-+ 0x1000011
-+ 0x20000ff
-+ 0x10000b3 0x02 0x00 0x00 0x00
-+ 0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43
-+ 0x10000c1 0x08 0x16 0x08 0x08
-+ 0x10000c4 0x11 0x07 0x03 0x03
-+ 0x10000c6 0x00
-+ 0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00
-+ 0x1000035 0x00
-+ 0x1000036 0xa0
-+ 0x100003a 0x55
-+ 0x1000044 0x00 0x01
-+ 0x10000d0 0x07 0x07 0x1d 0x03
-+ 0x10000d1 0x03 0x30 0x10
-+ 0x10000d2 0x03 0x14 0x04
-+ 0x1000029
-+ 0x100002c>;
-+
-+ /* This is a workaround to make sure the init sequence slows down and doesn't fail */
-+ debug = <3>;
-+ };
-+
-+ mz61581_ts: mz61581_ts@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <4 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 4 0>;
-+
-+ ti,x-plate-ohms = /bits/ 16 <60>;
-+ ti,pressure-max = /bits/ 16 <255>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ speed = <&mz61581>, "spi-max-frequency:0";
-+ rotate = <&mz61581>, "rotate:0";
-+ fps = <&mz61581>, "fps:0";
-+ debug = <&mz61581>, "debug:0";
-+ xohms = <&mz61581_ts>,"ti,x-plate-ohms;0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/pcf2127-rtc-overlay.dts linux-rpi/arch/arm/boot/dts/pcf2127-rtc-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/pcf2127-rtc-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/pcf2127-rtc-overlay.dts 2015-05-31 14:46:08.045661006 -0500
-@@ -0,0 +1,22 @@
-+// Definitions for PCF2127 Real Time Clock
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ pcf2127@51 {
-+ compatible = "nxp,pcf2127";
-+ reg = <0x51>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/pcf8523-rtc-overlay.dts linux-rpi/arch/arm/boot/dts/pcf8523-rtc-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/pcf8523-rtc-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/pcf8523-rtc-overlay.dts 2015-05-31 14:46:08.045661006 -0500
-@@ -0,0 +1,22 @@
-+// Definitions for PCF8523 Real Time Clock
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ pcf8523@68 {
-+ compatible = "nxp,pcf8523";
-+ reg = <0x68>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/piscreen-overlay.dts linux-rpi/arch/arm/boot/dts/piscreen-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/piscreen-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/piscreen-overlay.dts 2015-05-31 14:46:08.045661006 -0500
-@@ -0,0 +1,96 @@
-+/*
-+ * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ piscreen_pins: piscreen_pins {
-+ brcm,pins = <17 25 24 22>;
-+ brcm,function = <0 1 1 1>; /* in out out out */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ piscreen: piscreen@0{
-+ compatible = "ilitek,ili9486";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&piscreen_pins>;
-+
-+ spi-max-frequency = <24000000>;
-+ rotate = <270>;
-+ bgr;
-+ fps = <30>;
-+ buswidth = <8>;
-+ regwidth = <16>;
-+ reset-gpios = <&gpio 25 0>;
-+ dc-gpios = <&gpio 24 0>;
-+ led-gpios = <&gpio 22 1>;
-+ debug = <0>;
-+
-+ init = <0x10000b0 0x00
-+ 0x1000011
-+ 0x20000ff
-+ 0x100003a 0x55
-+ 0x1000036 0x28
-+ 0x10000c2 0x44
-+ 0x10000c5 0x00 0x00 0x00 0x00
-+ 0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00
-+ 0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00
-+ 0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00
-+ 0x1000011
-+ 0x1000029>;
-+ };
-+
-+ piscreen_ts: piscreen-ts@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <17 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 17 0>;
-+ ti,swap-xy;
-+ ti,x-plate-ohms = /bits/ 16 <100>;
-+ ti,pressure-max = /bits/ 16 <255>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ speed = <&piscreen>,"spi-max-frequency:0";
-+ rotate = <&piscreen>,"rotate:0";
-+ fps = <&piscreen>,"fps:0";
-+ debug = <&piscreen>,"debug:0";
-+ xohms = <&piscreen_ts>,"ti,x-plate-ohms;0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/pitft28-resistive-overlay.dts linux-rpi/arch/arm/boot/dts/pitft28-resistive-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/pitft28-resistive-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/pitft28-resistive-overlay.dts 2015-05-31 14:46:08.045661006 -0500
-@@ -0,0 +1,115 @@
-+/*
-+ * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ pitft_pins: pitft_pins {
-+ brcm,pins = <24 25>;
-+ brcm,function = <0 1>; /* in out */
-+ brcm,pull = <2 0>; /* pullup none */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pitft: pitft@0{
-+ compatible = "ilitek,ili9340";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pitft_pins>;
-+
-+ spi-max-frequency = <32000000>;
-+ rotate = <90>;
-+ fps = <25>;
-+ bgr;
-+ buswidth = <8>;
-+ dc-gpios = <&gpio 25 0>;
-+ debug = <0>;
-+ };
-+
-+ pitft_ts@1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stmpe610";
-+ reg = <1>;
-+
-+ spi-max-frequency = <500000>;
-+ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */
-+ interrupts = <24 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ interrupt-controller;
-+
-+ stmpe_touchscreen {
-+ compatible = "st,stmpe-ts";
-+ st,sample-time = <4>;
-+ st,mod-12b = <1>;
-+ st,ref-sel = <0>;
-+ st,adc-freq = <2>;
-+ st,ave-ctrl = <3>;
-+ st,touch-det-delay = <4>;
-+ st,settling = <2>;
-+ st,fraction-z = <7>;
-+ st,i-drive = <0>;
-+ };
-+
-+ stmpe_gpio: stmpe_gpio {
-+ #gpio-cells = <2>;
-+ compatible = "st,stmpe-gpio";
-+ /*
-+ * only GPIO2 is wired/available
-+ * and it is wired to the backlight
-+ */
-+ st,norequest-mask = <0x7b>;
-+ };
-+ };
-+ };
-+ };
-+
-+ fragment@3 {
-+ target-path = "/soc";
-+ __overlay__ {
-+ backlight {
-+ compatible = "gpio-backlight";
-+ gpios = <&stmpe_gpio 2 0>;
-+ default-on;
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ speed = <&pitft>,"spi-max-frequency:0";
-+ rotate = <&pitft>,"rotate:0";
-+ fps = <&pitft>,"fps:0";
-+ debug = <&pitft>,"debug:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/pps-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/pps-gpio-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/pps-gpio-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/pps-gpio-overlay.dts 2015-05-31 14:46:08.061661005 -0500
-@@ -0,0 +1,34 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+ fragment@0 {
-+ target-path = "/";
-+ __overlay__ {
-+ pps: pps {
-+ compatible = "pps-gpio";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pps_pins>;
-+ gpios = <&gpio 18 0>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ pps_pins: pps_pins {
-+ brcm,pins = <18>;
-+ brcm,function = <0>; // in
-+ brcm,pull = <0>; // off
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ gpiopin = <&pps>,"gpios:4",
-+ <&pps_pins>,"brcm,pins:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/rpi-dac-overlay.dts linux-rpi/arch/arm/boot/dts/rpi-dac-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/rpi-dac-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/rpi-dac-overlay.dts 2015-05-31 14:46:08.061661005 -0500
-@@ -0,0 +1,34 @@
-+// Definitions for RPi DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "rpi,rpi-dac";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target-path = "/";
-+ __overlay__ {
-+ pcm1794a-codec {
-+ #sound-dai-cells = <0>;
-+ compatible = "ti,pcm1794a";
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/rpi-display-overlay.dts linux-rpi/arch/arm/boot/dts/rpi-display-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/rpi-display-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/rpi-display-overlay.dts 2015-05-31 14:46:08.061661005 -0500
-@@ -0,0 +1,82 @@
-+/*
-+ * Device Tree overlay for rpi-display by Watterott
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ rpi_display_pins: rpi_display_pins {
-+ brcm,pins = <18 23 24 25>;
-+ brcm,function = <1 1 1 0>; /* out out out in */
-+ brcm,pull = <0 0 0 2>; /* - - - up */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rpidisplay: rpi-display@0{
-+ compatible = "ilitek,ili9341";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&rpi_display_pins>;
-+
-+ spi-max-frequency = <32000000>;
-+ rotate = <270>;
-+ bgr;
-+ fps = <30>;
-+ buswidth = <8>;
-+ reset-gpios = <&gpio 23 0>;
-+ dc-gpios = <&gpio 24 0>;
-+ led-gpios = <&gpio 18 1>;
-+ debug = <0>;
-+ };
-+
-+ rpidisplay_ts: rpi-display-ts@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <25 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 25 0>;
-+ ti,x-plate-ohms = /bits/ 16 <60>;
-+ ti,pressure-max = /bits/ 16 <255>;
-+ };
-+ };
-+ };
-+ __overrides__ {
-+ speed = <&rpidisplay>,"spi-max-frequency:0";
-+ rotate = <&rpidisplay>,"rotate:0";
-+ fps = <&rpidisplay>,"fps:0";
-+ debug = <&rpidisplay>,"debug:0";
-+ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/rpi-proto-overlay.dts linux-rpi/arch/arm/boot/dts/rpi-proto-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/rpi-proto-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/rpi-proto-overlay.dts 2015-05-31 14:46:08.061661005 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for Rpi-Proto
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&sound>;
-+ __overlay__ {
-+ compatible = "rpi,rpi-proto";
-+ i2s-controller = <&i2s>;
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2s>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "okay";
-+
-+ wm8731@1a {
-+ #sound-dai-cells = <0>;
-+ compatible = "wlf,wm8731";
-+ reg = <0x1a>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/sdhost-overlay.dts linux-rpi/arch/arm/boot/dts/sdhost-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/sdhost-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/sdhost-overlay.dts 2015-05-31 14:46:08.065661006 -0500
-@@ -0,0 +1,75 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target = <&soc>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ sdhost: sdhost@7e202000 {
-+ compatible = "brcm,bcm2835-sdhost";
-+ reg = <0x7e202000 0x100>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdhost_pins>;
-+ interrupts = <2 24>;
-+ clocks = <&clk_sdhost>;
-+ //dmas = <&dma 13>,
-+ // <&dma 13>;
-+ dma-names = "tx", "rx";
-+ brcm,delay-after-stop = <0>;
-+ brcm,overclock-50 = <0>;
-+ status = "okay";
-+ };
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ clk_sdhost: clock@3 {
-+ compatible = "fixed-clock";
-+ reg = <0>;
-+ #clock-cells = <0>;
-+ clock-output-names = "sdhost";
-+ clock-frequency = <250000000>;
-+ };
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ sdhost_pins: sdhost_pins {
-+ brcm,pins = <48 49 50 51 52 53>;
-+ brcm,function = <4>; /* alt0 */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&mmc>;
-+ __overlay__ {
-+ /* Find a way to disable the other driver */
-+ compatible = "";
-+ status = "disabled";
-+ };
-+ };
-+
-+ fragment@3 {
-+ target-path = "/__overrides__";
-+ __overlay__ {
-+ sdhost_freq = <&clk_sdhost>,"clock-frequency:0";
-+ };
-+ };
-+
-+ __overrides__ {
-+ delay_after_stop = <&sdhost>,"brcm,delay-after-stop:0";
-+ overclock_50 = <&sdhost>,"brcm,overclock-50:0";
-+ force_pio = <&sdhost>,"brcm,force-pio?";
-+ sdhost_freq = <&clk_sdhost>,"clock-frequency:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/spi-bcm2835-overlay.dts linux-rpi/arch/arm/boot/dts/spi-bcm2835-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/spi-bcm2835-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/spi-bcm2835-overlay.dts 2015-05-31 14:46:08.065661006 -0500
-@@ -0,0 +1,18 @@
-+/*
-+ * Device tree overlay for spi-bcm2835
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+ /* setting up compatiblity to allow loading the spi-bcm2835 driver */
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+ compatible = "brcm,bcm2835-spi";
-+ };
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/tinylcd35-overlay.dts linux-rpi/arch/arm/boot/dts/tinylcd35-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/tinylcd35-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/tinylcd35-overlay.dts 2015-05-31 14:46:08.073661005 -0500
-@@ -0,0 +1,216 @@
-+/*
-+ * tinylcd35-overlay.dts
-+ *
-+ * -------------------------------------------------
-+ * www.tinlylcd.com
-+ * -------------------------------------------------
-+ * Device---Driver-----BUS GPIO's
-+ * display tinylcd35 spi0.0 25 24 18
-+ * touch ads7846 spi0.1 5
-+ * rtc ds1307 i2c1-0068
-+ * rtc pcf8563 i2c1-0051
-+ * keypad gpio-keys --------- 17 22 27 23 28
-+ *
-+ *
-+ * TinyLCD.com 3.5 inch TFT
-+ *
-+ * Version 001
-+ * 5/3/2015 -- Noralf Trønnes Initial Device tree framework
-+ * 10/3/2015 -- tinylcd@gmail.com added ds1307 support.
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+ fragment@0 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ status = "okay";
-+
-+ spidev@0{
-+ status = "disabled";
-+ };
-+
-+ spidev@1{
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ tinylcd35_pins: tinylcd35_pins {
-+ brcm,pins = <25 24 18>;
-+ brcm,function = <1>; /* out */
-+ };
-+ tinylcd35_ts_pins: tinylcd35_ts_pins {
-+ brcm,pins = <5>;
-+ brcm,function = <0>; /* in */
-+ };
-+ keypad_pins: keypad_pins {
-+ brcm,pins = <4 17 22 23 27>;
-+ brcm,function = <0>; /* in */
-+ brcm,pull = <1>; /* down */
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&spi0>;
-+ __overlay__ {
-+ /* needed to avoid dtc warning */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tinylcd35: tinylcd35@0{
-+ compatible = "neosec,tinylcd";
-+ reg = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&tinylcd35_pins>,
-+ <&tinylcd35_ts_pins>;
-+
-+ spi-max-frequency = <48000000>;
-+ rotate = <270>;
-+ fps = <20>;
-+ bgr;
-+ buswidth = <8>;
-+ reset-gpios = <&gpio 25 0>;
-+ dc-gpios = <&gpio 24 0>;
-+ led-gpios = <&gpio 18 1>;
-+ debug = <0>;
-+
-+ init = <0x10000B0 0x80
-+ 0x10000C0 0x0A 0x0A
-+ 0x10000C1 0x01 0x01
-+ 0x10000C2 0x33
-+ 0x10000C5 0x00 0x42 0x80
-+ 0x10000B1 0xD0 0x11
-+ 0x10000B4 0x02
-+ 0x10000B6 0x00 0x22 0x3B
-+ 0x10000B7 0x07
-+ 0x1000036 0x58
-+ 0x10000F0 0x36 0xA5 0xD3
-+ 0x10000E5 0x80
-+ 0x10000E5 0x01
-+ 0x10000B3 0x00
-+ 0x10000E5 0x00
-+ 0x10000F0 0x36 0xA5 0x53
-+ 0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00
-+ 0x100003A 0x55
-+ 0x1000011
-+ 0x2000001
-+ 0x1000029>;
-+ };
-+
-+ tinylcd35_ts: tinylcd35_ts@1 {
-+ compatible = "ti,ads7846";
-+ reg = <1>;
-+ status = "disabled";
-+
-+ spi-max-frequency = <2000000>;
-+ interrupts = <5 2>; /* high-to-low edge triggered */
-+ interrupt-parent = <&gpio>;
-+ pendown-gpio = <&gpio 5 0>;
-+ ti,x-plate-ohms = /bits/ 16 <100>;
-+ ti,pressure-max = /bits/ 16 <255>;
-+ };
-+ };
-+ };
-+
-+ /* RTC */
-+
-+ fragment@3 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pcf8563: pcf8563@51 {
-+ compatible = "nxp,pcf8563";
-+ reg = <0x51>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ fragment@4 {
-+ target = <&i2c1>;
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ds1307: ds1307@68 {
-+ compatible = "maxim,ds1307";
-+ reg = <0x68>;
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
-+ /*
-+ * Values for input event code is found under the
-+ * 'Keys and buttons' heading in include/uapi/linux/input.h
-+ */
-+ fragment@5 {
-+ target-path = "/soc";
-+ __overlay__ {
-+ keypad: keypad {
-+ compatible = "gpio-keys";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&keypad_pins>;
-+ status = "disabled";
-+ autorepeat;
-+
-+ button@17 {
-+ label = "GPIO KEY_UP";
-+ linux,code = <103>;
-+ gpios = <&gpio 17 0>;
-+ };
-+ button@22 {
-+ label = "GPIO KEY_DOWN";
-+ linux,code = <108>;
-+ gpios = <&gpio 22 0>;
-+ };
-+ button@27 {
-+ label = "GPIO KEY_LEFT";
-+ linux,code = <105>;
-+ gpios = <&gpio 27 0>;
-+ };
-+ button@23 {
-+ label = "GPIO KEY_RIGHT";
-+ linux,code = <106>;
-+ gpios = <&gpio 23 0>;
-+ };
-+ button@4 {
-+ label = "GPIO KEY_ENTER";
-+ linux,code = <28>;
-+ gpios = <&gpio 4 0>;
-+ };
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ speed = <&tinylcd35>,"spi-max-frequency:0";
-+ rotate = <&tinylcd35>,"rotate:0";
-+ fps = <&tinylcd35>,"fps:0";
-+ debug = <&tinylcd35>,"debug:0";
-+ touch = <&tinylcd35_ts>,"status";
-+ touchgpio = <&tinylcd35_ts_pins>,"brcm,pins:0",
-+ <&tinylcd35_ts>,"interrupts:0",
-+ <&tinylcd35_ts>,"pendown-gpio:4";
-+ xohms = <&tinylcd35_ts>,"ti,x-plate-ohms;0";
-+ rtc-pcf = <&i2c1>,"status",
-+ <&pcf8563>,"status";
-+ rtc-ds = <&i2c1>,"status",
-+ <&ds1307>,"status";
-+ keypad = <&keypad>,"status";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/w1-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/w1-gpio-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/w1-gpio-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/w1-gpio-overlay.dts 2015-05-31 14:46:08.089661005 -0500
-@@ -0,0 +1,39 @@
-+// Definitions for w1-gpio module (without external pullup)
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target-path = "/";
-+ __overlay__ {
-+
-+ w1: onewire@0 {
-+ compatible = "w1-gpio";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&w1_pins>;
-+ gpios = <&gpio 4 0>;
-+ rpi,parasitic-power = <0>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ w1_pins: w1_pins {
-+ brcm,pins = <4>;
-+ brcm,function = <0>; // in (initially)
-+ brcm,pull = <0>; // off
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ gpiopin = <&w1>,"gpios:4",
-+ <&w1_pins>,"brcm,pins:0";
-+ pullup = <&w1>,"rpi,parasitic-power:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/boot/dts/w1-gpio-pullup-overlay.dts linux-rpi/arch/arm/boot/dts/w1-gpio-pullup-overlay.dts
---- linux-3.18.14/arch/arm/boot/dts/w1-gpio-pullup-overlay.dts 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/boot/dts/w1-gpio-pullup-overlay.dts 2015-05-31 14:46:08.089661005 -0500
-@@ -0,0 +1,41 @@
-+// Definitions for w1-gpio module (with external pullup)
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "brcm,bcm2708";
-+
-+ fragment@0 {
-+ target-path = "/";
-+ __overlay__ {
-+
-+ w1: onewire@0 {
-+ compatible = "w1-gpio";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&w1_pins>;
-+ gpios = <&gpio 4 0>, <&gpio 5 1>;
-+ rpi,parasitic-power = <0>;
-+ status = "okay";
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&gpio>;
-+ __overlay__ {
-+ w1_pins: w1_pins {
-+ brcm,pins = <4 5>;
-+ brcm,function = <0 1>; // in out
-+ brcm,pull = <0 0>; // off off
-+ };
-+ };
-+ };
-+
-+ __overrides__ {
-+ gpiopin = <&w1>,"gpios:4",
-+ <&w1_pins>,"brcm,pins:0";
-+ extpullup = <&w1>,"gpios:16",
-+ <&w1_pins>,"brcm,pins:4";
-+ pullup = <&w1>,"rpi,parasitic-power:0";
-+ };
-+};
-diff -Nur linux-3.18.14/arch/arm/configs/bcm2709_defconfig linux-rpi/arch/arm/configs/bcm2709_defconfig
---- linux-3.18.14/arch/arm/configs/bcm2709_defconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/configs/bcm2709_defconfig 2015-05-31 14:46:08.113661005 -0500
-@@ -0,0 +1,1207 @@
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+CONFIG_PHYS_OFFSET=0
-+CONFIG_LOCALVERSION="-v7"
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_FHANDLE=y
-+CONFIG_AUDIT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+CONFIG_TASK_XACCT=y
-+CONFIG_TASK_IO_ACCOUNTING=y
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_RESOURCE_COUNTERS=y
-+CONFIG_MEMCG=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_NAMESPACES=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_JUMP_LABEL=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_BCM2709=y
-+CONFIG_BCM2709_DT=y
-+# CONFIG_CACHE_L2X0 is not set
-+CONFIG_SMP=y
-+CONFIG_HAVE_ARM_ARCH_TIMER=y
-+CONFIG_VMSPLIT_2G=y
-+CONFIG_PREEMPT=y
-+CONFIG_AEABI=y
-+CONFIG_OABI_COMPAT=y
-+CONFIG_CLEANCACHE=y
-+CONFIG_FRONTSWAP=y
-+CONFIG_CMA=y
-+CONFIG_ZSMALLOC=m
-+CONFIG_PGTABLE_MAPPING=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_SECCOMP=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_STAT=m
-+CONFIG_CPU_FREQ_STAT_DETAILS=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_VFP=y
-+CONFIG_NEON=y
-+CONFIG_KERNEL_MODE_NEON=y
-+CONFIG_BINFMT_MISC=m
-+# CONFIG_SUSPEND is not set
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE_DEMUX=m
-+CONFIG_NET_IPGRE=m
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IP_PIMSM_V1=y
-+CONFIG_IP_PIMSM_V2=y
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+CONFIG_INET_IPCOMP=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+CONFIG_INET_LRO=m
-+CONFIG_INET_DIAG=m
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_IPV6_TUNNEL=m
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IPV6_PIMSM_V2=y
-+CONFIG_NETFILTER=y
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_ZONES=y
-+CONFIG_NF_CONNTRACK_EVENTS=y
-+CONFIG_NF_CONNTRACK_TIMESTAMP=y
-+CONFIG_NF_CT_PROTO_DCCP=m
-+CONFIG_NF_CT_PROTO_UDPLITE=m
-+CONFIG_NF_CONNTRACK_AMANDA=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_H323=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-+CONFIG_NF_CONNTRACK_SNMP=m
-+CONFIG_NF_CONNTRACK_PPTP=m
-+CONFIG_NF_CONNTRACK_SANE=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CONNTRACK_TFTP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XT_SET=m
-+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-+CONFIG_NETFILTER_XT_TARGET_DSCP=m
-+CONFIG_NETFILTER_XT_TARGET_HMARK=m
-+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-+CONFIG_NETFILTER_XT_TARGET_LED=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TEE=m
-+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-+CONFIG_NETFILTER_XT_TARGET_TRACE=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_BPF=m
-+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_CPU=m
-+CONFIG_NETFILTER_XT_MATCH_DCCP=m
-+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-+CONFIG_NETFILTER_XT_MATCH_DSCP=m
-+CONFIG_NETFILTER_XT_MATCH_ESP=m
-+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_HELPER=m
-+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-+CONFIG_NETFILTER_XT_MATCH_IPVS=m
-+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-+CONFIG_NETFILTER_XT_MATCH_OSF=m
-+CONFIG_NETFILTER_XT_MATCH_OWNER=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-+CONFIG_NETFILTER_XT_MATCH_REALM=m
-+CONFIG_NETFILTER_XT_MATCH_RECENT=m
-+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-+CONFIG_NETFILTER_XT_MATCH_STRING=m
-+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NETFILTER_XT_MATCH_U32=m
-+CONFIG_IP_SET=m
-+CONFIG_IP_SET_BITMAP_IP=m
-+CONFIG_IP_SET_BITMAP_IPMAC=m
-+CONFIG_IP_SET_BITMAP_PORT=m
-+CONFIG_IP_SET_HASH_IP=m
-+CONFIG_IP_SET_HASH_IPPORT=m
-+CONFIG_IP_SET_HASH_IPPORTIP=m
-+CONFIG_IP_SET_HASH_IPPORTNET=m
-+CONFIG_IP_SET_HASH_NET=m
-+CONFIG_IP_SET_HASH_NETPORT=m
-+CONFIG_IP_SET_HASH_NETIFACE=m
-+CONFIG_IP_SET_LIST_SET=m
-+CONFIG_IP_VS=m
-+CONFIG_IP_VS_PROTO_TCP=y
-+CONFIG_IP_VS_PROTO_UDP=y
-+CONFIG_IP_VS_PROTO_ESP=y
-+CONFIG_IP_VS_PROTO_AH=y
-+CONFIG_IP_VS_PROTO_SCTP=y
-+CONFIG_IP_VS_RR=m
-+CONFIG_IP_VS_WRR=m
-+CONFIG_IP_VS_LC=m
-+CONFIG_IP_VS_WLC=m
-+CONFIG_IP_VS_LBLC=m
-+CONFIG_IP_VS_LBLCR=m
-+CONFIG_IP_VS_DH=m
-+CONFIG_IP_VS_SH=m
-+CONFIG_IP_VS_SED=m
-+CONFIG_IP_VS_NQ=m
-+CONFIG_IP_VS_FTP=m
-+CONFIG_IP_VS_PE_SIP=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_MATCH_AH=m
-+CONFIG_IP_NF_MATCH_ECN=m
-+CONFIG_IP_NF_MATCH_TTL=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_NAT=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_NETMAP=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_TARGET_CLUSTERIP=m
-+CONFIG_IP_NF_TARGET_ECN=m
-+CONFIG_IP_NF_TARGET_TTL=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_IP_NF_ARPTABLES=m
-+CONFIG_IP_NF_ARPFILTER=m
-+CONFIG_IP_NF_ARP_MANGLE=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_HL=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_TARGET_HL=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_IP6_NF_NAT=m
-+CONFIG_IP6_NF_TARGET_MASQUERADE=m
-+CONFIG_IP6_NF_TARGET_NPT=m
-+CONFIG_BRIDGE_NF_EBTABLES=m
-+CONFIG_BRIDGE_EBT_BROUTE=m
-+CONFIG_BRIDGE_EBT_T_FILTER=m
-+CONFIG_BRIDGE_EBT_T_NAT=m
-+CONFIG_BRIDGE_EBT_802_3=m
-+CONFIG_BRIDGE_EBT_AMONG=m
-+CONFIG_BRIDGE_EBT_ARP=m
-+CONFIG_BRIDGE_EBT_IP=m
-+CONFIG_BRIDGE_EBT_IP6=m
-+CONFIG_BRIDGE_EBT_LIMIT=m
-+CONFIG_BRIDGE_EBT_MARK=m
-+CONFIG_BRIDGE_EBT_PKTTYPE=m
-+CONFIG_BRIDGE_EBT_STP=m
-+CONFIG_BRIDGE_EBT_VLAN=m
-+CONFIG_BRIDGE_EBT_ARPREPLY=m
-+CONFIG_BRIDGE_EBT_DNAT=m
-+CONFIG_BRIDGE_EBT_MARK_T=m
-+CONFIG_BRIDGE_EBT_REDIRECT=m
-+CONFIG_BRIDGE_EBT_SNAT=m
-+CONFIG_BRIDGE_EBT_LOG=m
-+CONFIG_BRIDGE_EBT_NFLOG=m
-+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-+CONFIG_ATM=m
-+CONFIG_L2TP=m
-+CONFIG_L2TP_V3=y
-+CONFIG_L2TP_IP=m
-+CONFIG_L2TP_ETH=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+CONFIG_VLAN_8021Q_GVRP=y
-+CONFIG_ATALK=m
-+CONFIG_6LOWPAN=m
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_CBQ=m
-+CONFIG_NET_SCH_HTB=m
-+CONFIG_NET_SCH_HFSC=m
-+CONFIG_NET_SCH_PRIO=m
-+CONFIG_NET_SCH_MULTIQ=m
-+CONFIG_NET_SCH_RED=m
-+CONFIG_NET_SCH_SFB=m
-+CONFIG_NET_SCH_SFQ=m
-+CONFIG_NET_SCH_TEQL=m
-+CONFIG_NET_SCH_TBF=m
-+CONFIG_NET_SCH_GRED=m
-+CONFIG_NET_SCH_DSMARK=m
-+CONFIG_NET_SCH_NETEM=m
-+CONFIG_NET_SCH_DRR=m
-+CONFIG_NET_SCH_MQPRIO=m
-+CONFIG_NET_SCH_CHOKE=m
-+CONFIG_NET_SCH_QFQ=m
-+CONFIG_NET_SCH_CODEL=m
-+CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_INGRESS=m
-+CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_CLS_BASIC=m
-+CONFIG_NET_CLS_TCINDEX=m
-+CONFIG_NET_CLS_ROUTE4=m
-+CONFIG_NET_CLS_FW=m
-+CONFIG_NET_CLS_U32=m
-+CONFIG_CLS_U32_MARK=y
-+CONFIG_NET_CLS_RSVP=m
-+CONFIG_NET_CLS_RSVP6=m
-+CONFIG_NET_CLS_FLOW=m
-+CONFIG_NET_CLS_CGROUP=m
-+CONFIG_NET_EMATCH=y
-+CONFIG_NET_EMATCH_CMP=m
-+CONFIG_NET_EMATCH_NBYTE=m
-+CONFIG_NET_EMATCH_U32=m
-+CONFIG_NET_EMATCH_META=m
-+CONFIG_NET_EMATCH_TEXT=m
-+CONFIG_NET_EMATCH_IPSET=m
-+CONFIG_NET_CLS_ACT=y
-+CONFIG_NET_ACT_POLICE=m
-+CONFIG_NET_ACT_GACT=m
-+CONFIG_GACT_PROB=y
-+CONFIG_NET_ACT_MIRRED=m
-+CONFIG_NET_ACT_IPT=m
-+CONFIG_NET_ACT_NAT=m
-+CONFIG_NET_ACT_PEDIT=m
-+CONFIG_NET_ACT_SIMP=m
-+CONFIG_NET_ACT_SKBEDIT=m
-+CONFIG_NET_ACT_CSUM=m
-+CONFIG_BATMAN_ADV=m
-+CONFIG_OPENVSWITCH=m
-+CONFIG_NET_PKTGEN=m
-+CONFIG_HAMRADIO=y
-+CONFIG_AX25=m
-+CONFIG_NETROM=m
-+CONFIG_ROSE=m
-+CONFIG_MKISS=m
-+CONFIG_6PACK=m
-+CONFIG_BPQETHER=m
-+CONFIG_BAYCOM_SER_FDX=m
-+CONFIG_BAYCOM_SER_HDX=m
-+CONFIG_YAM=m
-+CONFIG_CAN=m
-+CONFIG_CAN_VCAN=m
-+CONFIG_CAN_MCP251X=m
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_BT=m
-+CONFIG_BT_6LOWPAN=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_BT_WILINK=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_RFKILL=m
-+CONFIG_RFKILL_INPUT=y
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_NFC_PN533=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_ZRAM=m
-+CONFIG_ZRAM_LZ4_COMPRESS=y
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_DRBD=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_ATA_OVER_ETH=m
-+CONFIG_EEPROM_AT24=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_CHR_DEV_ST=m
-+CONFIG_CHR_DEV_OSST=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_CHR_DEV_SG=m
-+CONFIG_SCSI_ISCSI_ATTRS=y
-+CONFIG_ISCSI_TCP=m
-+CONFIG_ISCSI_BOOT_SYSFS=m
-+CONFIG_MD=y
-+CONFIG_MD_LINEAR=m
-+CONFIG_MD_RAID0=m
-+CONFIG_BLK_DEV_DM=m
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_LOG_USERSPACE=m
-+CONFIG_DM_RAID=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_DELAY=m
-+CONFIG_NETDEVICES=y
-+CONFIG_BONDING=m
-+CONFIG_DUMMY=m
-+CONFIG_IFB=m
-+CONFIG_MACVLAN=m
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_VETH=m
-+CONFIG_ENC28J60=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOATM=m
-+CONFIG_PPPOE=m
-+CONFIG_PPPOL2TP=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_SLIP_SMART=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_RTL8152=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_AX88179_178A=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_CDC_NCM=m
-+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-+CONFIG_USB_NET_CDC_MBIM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SR9700=m
-+CONFIG_USB_NET_SR9800=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_EPSON2888=y
-+CONFIG_USB_KC2190=y
-+CONFIG_USB_NET_ZAURUS=m
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_QMI_WWAN=m
-+CONFIG_USB_HSO=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_RTL8187=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_ATH_CARDS=m
-+CONFIG_ATH9K=m
-+CONFIG_ATH9K_HTC=m
-+CONFIG_CARL9170=m
-+CONFIG_ATH6KL=m
-+CONFIG_ATH6KL_USB=m
-+CONFIG_AR5523=m
-+CONFIG_B43=m
-+# CONFIG_B43_PHY_N is not set
-+CONFIG_B43LEGACY=m
-+CONFIG_BRCMFMAC=m
-+CONFIG_BRCMFMAC_USB=y
-+CONFIG_HOSTAP=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT3573=y
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RT2800USB_RT55XX=y
-+CONFIG_RT2800USB_UNKNOWN=y
-+CONFIG_RTL8192CU=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_INPUT_POLLDEV=m
-+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_KEYBOARD_ATKBD is not set
-+CONFIG_KEYBOARD_GPIO=m
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_JOYSTICK=y
-+CONFIG_JOYSTICK_IFORCE=m
-+CONFIG_JOYSTICK_IFORCE_USB=y
-+CONFIG_JOYSTICK_XPAD=m
-+CONFIG_JOYSTICK_XPAD_FF=y
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-+CONFIG_TOUCHSCREEN_STMPE=m
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_HW_RANDOM_BCM2708=m
-+CONFIG_RAW_DRIVER=y
-+CONFIG_BRCM_CHAR_DRIVERS=y
-+CONFIG_BCM_VC_CMA=y
-+CONFIG_BCM_VC_SM=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_MUX=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2835=m
-+CONFIG_SPI_BCM2708=m
-+CONFIG_SPI_SPIDEV=y
-+CONFIG_PPS=m
-+CONFIG_PPS_CLIENT_LDISC=m
-+CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_ARIZONA=m
-+CONFIG_GPIO_STMPE=y
-+CONFIG_W1=m
-+CONFIG_W1_MASTER_DS2490=m
-+CONFIG_W1_MASTER_DS2482=m
-+CONFIG_W1_MASTER_DS1WM=m
-+CONFIG_W1_MASTER_GPIO=m
-+CONFIG_W1_SLAVE_THERM=m
-+CONFIG_W1_SLAVE_SMEM=m
-+CONFIG_W1_SLAVE_DS2408=m
-+CONFIG_W1_SLAVE_DS2413=m
-+CONFIG_W1_SLAVE_DS2406=m
-+CONFIG_W1_SLAVE_DS2423=m
-+CONFIG_W1_SLAVE_DS2431=m
-+CONFIG_W1_SLAVE_DS2433=m
-+CONFIG_W1_SLAVE_DS2760=m
-+CONFIG_W1_SLAVE_DS2780=m
-+CONFIG_W1_SLAVE_DS2781=m
-+CONFIG_W1_SLAVE_DS28E04=m
-+CONFIG_W1_SLAVE_BQ27000=m
-+CONFIG_BATTERY_DS2760=m
-+# CONFIG_HWMON is not set
-+CONFIG_THERMAL=y
-+CONFIG_THERMAL_BCM2835=y
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2708_WDT=m
-+CONFIG_UCB1400_CORE=m
-+CONFIG_MFD_STMPE=y
-+CONFIG_STMPE_SPI=y
-+CONFIG_MFD_ARIZONA_I2C=m
-+CONFIG_MFD_ARIZONA_SPI=m
-+CONFIG_MFD_WM5102=y
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_RC_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_LIRC=m
-+CONFIG_RC_DEVICES=y
-+CONFIG_RC_ATI_REMOTE=m
-+CONFIG_IR_IMON=m
-+CONFIG_IR_MCEUSB=m
-+CONFIG_IR_REDRAT3=m
-+CONFIG_IR_STREAMZAP=m
-+CONFIG_IR_IGUANA=m
-+CONFIG_IR_TTUSBIR=m
-+CONFIG_RC_LOOPBACK=m
-+CONFIG_IR_GPIO_CIR=m
-+CONFIG_MEDIA_USB_SUPPORT=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_M5602=m
-+CONFIG_USB_STV06XX=m
-+CONFIG_USB_GL860=m
-+CONFIG_USB_GSPCA_BENQ=m
-+CONFIG_USB_GSPCA_CONEX=m
-+CONFIG_USB_GSPCA_CPIA1=m
-+CONFIG_USB_GSPCA_DTCS033=m
-+CONFIG_USB_GSPCA_ETOMS=m
-+CONFIG_USB_GSPCA_FINEPIX=m
-+CONFIG_USB_GSPCA_JEILINJ=m
-+CONFIG_USB_GSPCA_JL2005BCD=m
-+CONFIG_USB_GSPCA_KINECT=m
-+CONFIG_USB_GSPCA_KONICA=m
-+CONFIG_USB_GSPCA_MARS=m
-+CONFIG_USB_GSPCA_MR97310A=m
-+CONFIG_USB_GSPCA_NW80X=m
-+CONFIG_USB_GSPCA_OV519=m
-+CONFIG_USB_GSPCA_OV534=m
-+CONFIG_USB_GSPCA_OV534_9=m
-+CONFIG_USB_GSPCA_PAC207=m
-+CONFIG_USB_GSPCA_PAC7302=m
-+CONFIG_USB_GSPCA_PAC7311=m
-+CONFIG_USB_GSPCA_SE401=m
-+CONFIG_USB_GSPCA_SN9C2028=m
-+CONFIG_USB_GSPCA_SN9C20X=m
-+CONFIG_USB_GSPCA_SONIXB=m
-+CONFIG_USB_GSPCA_SONIXJ=m
-+CONFIG_USB_GSPCA_SPCA500=m
-+CONFIG_USB_GSPCA_SPCA501=m
-+CONFIG_USB_GSPCA_SPCA505=m
-+CONFIG_USB_GSPCA_SPCA506=m
-+CONFIG_USB_GSPCA_SPCA508=m
-+CONFIG_USB_GSPCA_SPCA561=m
-+CONFIG_USB_GSPCA_SPCA1528=m
-+CONFIG_USB_GSPCA_SQ905=m
-+CONFIG_USB_GSPCA_SQ905C=m
-+CONFIG_USB_GSPCA_SQ930X=m
-+CONFIG_USB_GSPCA_STK014=m
-+CONFIG_USB_GSPCA_STK1135=m
-+CONFIG_USB_GSPCA_STV0680=m
-+CONFIG_USB_GSPCA_SUNPLUS=m
-+CONFIG_USB_GSPCA_T613=m
-+CONFIG_USB_GSPCA_TOPRO=m
-+CONFIG_USB_GSPCA_TV8532=m
-+CONFIG_USB_GSPCA_VC032X=m
-+CONFIG_USB_GSPCA_VICAM=m
-+CONFIG_USB_GSPCA_XIRLINK_CIT=m
-+CONFIG_USB_GSPCA_ZC3XX=m
-+CONFIG_USB_PWC=m
-+CONFIG_VIDEO_CPIA2=m
-+CONFIG_USB_ZR364XX=m
-+CONFIG_USB_STKWEBCAM=m
-+CONFIG_USB_S2255=m
-+CONFIG_VIDEO_USBTV=m
-+CONFIG_VIDEO_PVRUSB2=m
-+CONFIG_VIDEO_HDPVR=m
-+CONFIG_VIDEO_TLG2300=m
-+CONFIG_VIDEO_USBVISION=m
-+CONFIG_VIDEO_STK1160_COMMON=m
-+CONFIG_VIDEO_STK1160_AC97=y
-+CONFIG_VIDEO_GO7007=m
-+CONFIG_VIDEO_GO7007_USB=m
-+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-+CONFIG_VIDEO_AU0828=m
-+CONFIG_VIDEO_AU0828_RC=y
-+CONFIG_VIDEO_CX231XX=m
-+CONFIG_VIDEO_CX231XX_ALSA=m
-+CONFIG_VIDEO_CX231XX_DVB=m
-+CONFIG_VIDEO_TM6000=m
-+CONFIG_VIDEO_TM6000_ALSA=m
-+CONFIG_VIDEO_TM6000_DVB=m
-+CONFIG_DVB_USB=m
-+CONFIG_DVB_USB_A800=m
-+CONFIG_DVB_USB_DIBUSB_MB=m
-+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-+CONFIG_DVB_USB_DIBUSB_MC=m
-+CONFIG_DVB_USB_DIB0700=m
-+CONFIG_DVB_USB_UMT_010=m
-+CONFIG_DVB_USB_CXUSB=m
-+CONFIG_DVB_USB_M920X=m
-+CONFIG_DVB_USB_DIGITV=m
-+CONFIG_DVB_USB_VP7045=m
-+CONFIG_DVB_USB_VP702X=m
-+CONFIG_DVB_USB_GP8PSK=m
-+CONFIG_DVB_USB_NOVA_T_USB2=m
-+CONFIG_DVB_USB_TTUSB2=m
-+CONFIG_DVB_USB_DTT200U=m
-+CONFIG_DVB_USB_OPERA1=m
-+CONFIG_DVB_USB_AF9005=m
-+CONFIG_DVB_USB_AF9005_REMOTE=m
-+CONFIG_DVB_USB_PCTV452E=m
-+CONFIG_DVB_USB_DW2102=m
-+CONFIG_DVB_USB_CINERGY_T2=m
-+CONFIG_DVB_USB_DTV5100=m
-+CONFIG_DVB_USB_FRIIO=m
-+CONFIG_DVB_USB_AZ6027=m
-+CONFIG_DVB_USB_TECHNISAT_USB2=m
-+CONFIG_DVB_USB_V2=m
-+CONFIG_DVB_USB_AF9015=m
-+CONFIG_DVB_USB_AF9035=m
-+CONFIG_DVB_USB_ANYSEE=m
-+CONFIG_DVB_USB_AU6610=m
-+CONFIG_DVB_USB_AZ6007=m
-+CONFIG_DVB_USB_CE6230=m
-+CONFIG_DVB_USB_EC168=m
-+CONFIG_DVB_USB_GL861=m
-+CONFIG_DVB_USB_LME2510=m
-+CONFIG_DVB_USB_MXL111SF=m
-+CONFIG_DVB_USB_RTL28XXU=m
-+CONFIG_DVB_USB_DVBSKY=m
-+CONFIG_SMS_USB_DRV=m
-+CONFIG_DVB_B2C2_FLEXCOP_USB=m
-+CONFIG_DVB_AS102=m
-+CONFIG_VIDEO_EM28XX=m
-+CONFIG_VIDEO_EM28XX_V4L2=m
-+CONFIG_VIDEO_EM28XX_ALSA=m
-+CONFIG_VIDEO_EM28XX_DVB=m
-+CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_BCM2835=y
-+CONFIG_VIDEO_BCM2835_MMAL=m
-+CONFIG_RADIO_SI470X=y
-+CONFIG_USB_SI470X=m
-+CONFIG_I2C_SI470X=m
-+CONFIG_RADIO_SI4713=m
-+CONFIG_I2C_SI4713=m
-+CONFIG_USB_MR800=m
-+CONFIG_USB_DSBR=m
-+CONFIG_RADIO_SHARK=m
-+CONFIG_RADIO_SHARK2=m
-+CONFIG_USB_KEENE=m
-+CONFIG_USB_MA901=m
-+CONFIG_RADIO_TEA5764=m
-+CONFIG_RADIO_SAA7706H=m
-+CONFIG_RADIO_TEF6862=m
-+CONFIG_RADIO_WL1273=m
-+CONFIG_RADIO_WL128X=m
-+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-+CONFIG_VIDEO_UDA1342=m
-+CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_TVP5150=m
-+CONFIG_VIDEO_TW2804=m
-+CONFIG_VIDEO_TW9903=m
-+CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV7640=m
-+CONFIG_VIDEO_MT9V011=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FB_UDL=m
-+CONFIG_FB_SSD1307=m
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_GPIO=m
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_SEQUENCER_OSS=y
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_BCM2835=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_CAIAQ_INPUT=y
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_SOC=m
-+CONFIG_SND_BCM2708_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
-+CONFIG_SND_BCM2708_SOC_RPI_DAC=m
-+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
-+CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_SOUND_PRIME=m
-+CONFIG_HIDRAW=y
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_ELO=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THINGM=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_WACOM=m
-+CONFIG_HID_WIIMOTE=m
-+CONFIG_HID_XINMO=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USBIP_CORE=m
-+CONFIG_USBIP_VHCI_HCD=m
-+CONFIG_USBIP_HOST=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_F81232=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_METRO=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_XSENS_MT=m
-+CONFIG_USB_SERIAL_WISHBONE=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_QT2=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_LED=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_USB_ATM=m
-+CONFIG_USB_SPEEDTOUCH=m
-+CONFIG_USB_CXACRU=m
-+CONFIG_USB_UEAGLEATM=m
-+CONFIG_USB_XUSBATM=m
-+CONFIG_MMC=y
-+CONFIG_MMC_BLOCK_MINORS=32
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_MMC_BCM2835_SDHOST=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SPI=m
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_ONESHOT=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-+CONFIG_LEDS_TRIGGER_CPU=y
-+CONFIG_LEDS_TRIGGER_GPIO=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TRANSIENT=m
-+CONFIG_LEDS_TRIGGER_CAMERA=m
-+CONFIG_LEDS_TRIGGER_INPUT=y
-+CONFIG_RTC_CLASS=y
-+# CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_DS1307=m
-+CONFIG_RTC_DRV_DS1374=m
-+CONFIG_RTC_DRV_DS1672=m
-+CONFIG_RTC_DRV_DS3232=m
-+CONFIG_RTC_DRV_MAX6900=m
-+CONFIG_RTC_DRV_RS5C372=m
-+CONFIG_RTC_DRV_ISL1208=m
-+CONFIG_RTC_DRV_ISL12022=m
-+CONFIG_RTC_DRV_ISL12057=m
-+CONFIG_RTC_DRV_X1205=m
-+CONFIG_RTC_DRV_PCF2127=m
-+CONFIG_RTC_DRV_PCF8523=m
-+CONFIG_RTC_DRV_PCF8563=m
-+CONFIG_RTC_DRV_PCF8583=m
-+CONFIG_RTC_DRV_M41T80=m
-+CONFIG_RTC_DRV_BQ32K=m
-+CONFIG_RTC_DRV_S35390A=m
-+CONFIG_RTC_DRV_FM3130=m
-+CONFIG_RTC_DRV_RX8581=m
-+CONFIG_RTC_DRV_RX8025=m
-+CONFIG_RTC_DRV_EM3027=m
-+CONFIG_RTC_DRV_RV3029C2=m
-+CONFIG_RTC_DRV_M41T93=m
-+CONFIG_RTC_DRV_M41T94=m
-+CONFIG_RTC_DRV_DS1305=m
-+CONFIG_RTC_DRV_DS1390=m
-+CONFIG_RTC_DRV_MAX6902=m
-+CONFIG_RTC_DRV_R9701=m
-+CONFIG_RTC_DRV_RS5C348=m
-+CONFIG_RTC_DRV_DS3234=m
-+CONFIG_RTC_DRV_PCF2123=m
-+CONFIG_RTC_DRV_RX4581=m
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_BCM2708=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+CONFIG_STAGING=y
-+CONFIG_PRISM2_USB=m
-+CONFIG_R8712U=m
-+CONFIG_R8188EU=m
-+CONFIG_R8723AU=m
-+CONFIG_VT6656=m
-+CONFIG_SPEAKUP=m
-+CONFIG_SPEAKUP_SYNTH_SOFT=m
-+CONFIG_STAGING_MEDIA=y
-+CONFIG_LIRC_STAGING=y
-+CONFIG_LIRC_IGORPLUGUSB=m
-+CONFIG_LIRC_IMON=m
-+CONFIG_LIRC_RPI=m
-+CONFIG_LIRC_SASEM=m
-+CONFIG_LIRC_SERIAL=m
-+CONFIG_FB_TFT=m
-+CONFIG_FB_TFT_AGM1264K_FL=m
-+CONFIG_FB_TFT_BD663474=m
-+CONFIG_FB_TFT_HX8340BN=m
-+CONFIG_FB_TFT_HX8347D=m
-+CONFIG_FB_TFT_HX8353D=m
-+CONFIG_FB_TFT_ILI9320=m
-+CONFIG_FB_TFT_ILI9325=m
-+CONFIG_FB_TFT_ILI9340=m
-+CONFIG_FB_TFT_ILI9341=m
-+CONFIG_FB_TFT_ILI9481=m
-+CONFIG_FB_TFT_ILI9486=m
-+CONFIG_FB_TFT_PCD8544=m
-+CONFIG_FB_TFT_RA8875=m
-+CONFIG_FB_TFT_S6D02A1=m
-+CONFIG_FB_TFT_S6D1121=m
-+CONFIG_FB_TFT_SSD1289=m
-+CONFIG_FB_TFT_SSD1306=m
-+CONFIG_FB_TFT_SSD1331=m
-+CONFIG_FB_TFT_SSD1351=m
-+CONFIG_FB_TFT_ST7735R=m
-+CONFIG_FB_TFT_TINYLCD=m
-+CONFIG_FB_TFT_TLS8204=m
-+CONFIG_FB_TFT_UC1701=m
-+CONFIG_FB_TFT_UPD161704=m
-+CONFIG_FB_TFT_WATTEROTT=m
-+CONFIG_FB_FLEX=m
-+CONFIG_FB_TFT_FBTFT_DEVICE=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_EXTCON=m
-+CONFIG_EXTCON_ARIZONA=m
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_FANOTIFY=y
-+CONFIG_QFMT_V1=m
-+CONFIG_QFMT_V2=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_NTFS_RW=y
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_CONFIGFS_FS=y
-+CONFIG_ECRYPT_FS=m
-+CONFIG_HFS_FS=m
-+CONFIG_HFSPLUS_FS=m
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_F2FS_FS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_SWAP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3_ACL=y
-+CONFIG_NFSD_V4=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_UPCALL=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_DLM=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+CONFIG_TIMER_STATS=y
-+# CONFIG_DEBUG_PREEMPT is not set
-+CONFIG_IRQSOFF_TRACER=y
-+CONFIG_SCHED_TRACER=y
-+CONFIG_STACK_TRACER=y
-+CONFIG_BLK_DEV_IO_TRACE=y
-+# CONFIG_KPROBE_EVENT is not set
-+CONFIG_FUNCTION_PROFILER=y
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_CRYPTO_USER=m
-+CONFIG_CRYPTO_NULL=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_CTS=m
-+CONFIG_CRYPTO_XTS=m
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_SHA1_ARM_NEON=m
-+CONFIG_CRYPTO_SHA512_ARM_NEON=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_AES_ARM_BS=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-diff -Nur linux-3.18.14/arch/arm/configs/bcmrpi_defconfig linux-rpi/arch/arm/configs/bcmrpi_defconfig
---- linux-3.18.14/arch/arm/configs/bcmrpi_defconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/configs/bcmrpi_defconfig 2015-05-31 14:46:08.113661005 -0500
-@@ -0,0 +1,1203 @@
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+CONFIG_PHYS_OFFSET=0
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_FHANDLE=y
-+CONFIG_AUDIT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+CONFIG_TASK_XACCT=y
-+CONFIG_TASK_IO_ACCOUNTING=y
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_RESOURCE_COUNTERS=y
-+CONFIG_MEMCG=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_NAMESPACES=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_JUMP_LABEL=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_BCM2708=y
-+CONFIG_BCM2708_DT=y
-+CONFIG_PREEMPT=y
-+CONFIG_AEABI=y
-+CONFIG_OABI_COMPAT=y
-+CONFIG_CLEANCACHE=y
-+CONFIG_FRONTSWAP=y
-+CONFIG_CMA=y
-+CONFIG_ZSMALLOC=m
-+CONFIG_PGTABLE_MAPPING=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_SECCOMP=y
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_KEXEC=y
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_STAT=m
-+CONFIG_CPU_FREQ_STAT_DETAILS=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_VFP=y
-+CONFIG_BINFMT_MISC=m
-+# CONFIG_SUSPEND is not set
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE_DEMUX=m
-+CONFIG_NET_IPGRE=m
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IP_PIMSM_V1=y
-+CONFIG_IP_PIMSM_V2=y
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+CONFIG_INET_IPCOMP=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+CONFIG_INET_LRO=m
-+CONFIG_INET_DIAG=m
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_IPV6_TUNNEL=m
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IPV6_PIMSM_V2=y
-+CONFIG_NETFILTER=y
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_ZONES=y
-+CONFIG_NF_CONNTRACK_EVENTS=y
-+CONFIG_NF_CONNTRACK_TIMESTAMP=y
-+CONFIG_NF_CT_PROTO_DCCP=m
-+CONFIG_NF_CT_PROTO_UDPLITE=m
-+CONFIG_NF_CONNTRACK_AMANDA=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_H323=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-+CONFIG_NF_CONNTRACK_SNMP=m
-+CONFIG_NF_CONNTRACK_PPTP=m
-+CONFIG_NF_CONNTRACK_SANE=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CONNTRACK_TFTP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XT_SET=m
-+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-+CONFIG_NETFILTER_XT_TARGET_DSCP=m
-+CONFIG_NETFILTER_XT_TARGET_HMARK=m
-+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-+CONFIG_NETFILTER_XT_TARGET_LED=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TEE=m
-+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-+CONFIG_NETFILTER_XT_TARGET_TRACE=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_BPF=m
-+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_CPU=m
-+CONFIG_NETFILTER_XT_MATCH_DCCP=m
-+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-+CONFIG_NETFILTER_XT_MATCH_DSCP=m
-+CONFIG_NETFILTER_XT_MATCH_ESP=m
-+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_HELPER=m
-+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-+CONFIG_NETFILTER_XT_MATCH_IPVS=m
-+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-+CONFIG_NETFILTER_XT_MATCH_OSF=m
-+CONFIG_NETFILTER_XT_MATCH_OWNER=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-+CONFIG_NETFILTER_XT_MATCH_REALM=m
-+CONFIG_NETFILTER_XT_MATCH_RECENT=m
-+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-+CONFIG_NETFILTER_XT_MATCH_STRING=m
-+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NETFILTER_XT_MATCH_U32=m
-+CONFIG_IP_SET=m
-+CONFIG_IP_SET_BITMAP_IP=m
-+CONFIG_IP_SET_BITMAP_IPMAC=m
-+CONFIG_IP_SET_BITMAP_PORT=m
-+CONFIG_IP_SET_HASH_IP=m
-+CONFIG_IP_SET_HASH_IPPORT=m
-+CONFIG_IP_SET_HASH_IPPORTIP=m
-+CONFIG_IP_SET_HASH_IPPORTNET=m
-+CONFIG_IP_SET_HASH_NET=m
-+CONFIG_IP_SET_HASH_NETPORT=m
-+CONFIG_IP_SET_HASH_NETIFACE=m
-+CONFIG_IP_SET_LIST_SET=m
-+CONFIG_IP_VS=m
-+CONFIG_IP_VS_PROTO_TCP=y
-+CONFIG_IP_VS_PROTO_UDP=y
-+CONFIG_IP_VS_PROTO_ESP=y
-+CONFIG_IP_VS_PROTO_AH=y
-+CONFIG_IP_VS_PROTO_SCTP=y
-+CONFIG_IP_VS_RR=m
-+CONFIG_IP_VS_WRR=m
-+CONFIG_IP_VS_LC=m
-+CONFIG_IP_VS_WLC=m
-+CONFIG_IP_VS_LBLC=m
-+CONFIG_IP_VS_LBLCR=m
-+CONFIG_IP_VS_DH=m
-+CONFIG_IP_VS_SH=m
-+CONFIG_IP_VS_SED=m
-+CONFIG_IP_VS_NQ=m
-+CONFIG_IP_VS_FTP=m
-+CONFIG_IP_VS_PE_SIP=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_MATCH_AH=m
-+CONFIG_IP_NF_MATCH_ECN=m
-+CONFIG_IP_NF_MATCH_TTL=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_NAT=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_NETMAP=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_TARGET_CLUSTERIP=m
-+CONFIG_IP_NF_TARGET_ECN=m
-+CONFIG_IP_NF_TARGET_TTL=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_IP_NF_ARPTABLES=m
-+CONFIG_IP_NF_ARPFILTER=m
-+CONFIG_IP_NF_ARP_MANGLE=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_HL=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_TARGET_HL=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_IP6_NF_NAT=m
-+CONFIG_IP6_NF_TARGET_MASQUERADE=m
-+CONFIG_IP6_NF_TARGET_NPT=m
-+CONFIG_BRIDGE_NF_EBTABLES=m
-+CONFIG_BRIDGE_EBT_BROUTE=m
-+CONFIG_BRIDGE_EBT_T_FILTER=m
-+CONFIG_BRIDGE_EBT_T_NAT=m
-+CONFIG_BRIDGE_EBT_802_3=m
-+CONFIG_BRIDGE_EBT_AMONG=m
-+CONFIG_BRIDGE_EBT_ARP=m
-+CONFIG_BRIDGE_EBT_IP=m
-+CONFIG_BRIDGE_EBT_IP6=m
-+CONFIG_BRIDGE_EBT_LIMIT=m
-+CONFIG_BRIDGE_EBT_MARK=m
-+CONFIG_BRIDGE_EBT_PKTTYPE=m
-+CONFIG_BRIDGE_EBT_STP=m
-+CONFIG_BRIDGE_EBT_VLAN=m
-+CONFIG_BRIDGE_EBT_ARPREPLY=m
-+CONFIG_BRIDGE_EBT_DNAT=m
-+CONFIG_BRIDGE_EBT_MARK_T=m
-+CONFIG_BRIDGE_EBT_REDIRECT=m
-+CONFIG_BRIDGE_EBT_SNAT=m
-+CONFIG_BRIDGE_EBT_LOG=m
-+CONFIG_BRIDGE_EBT_NFLOG=m
-+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-+CONFIG_ATM=m
-+CONFIG_L2TP=m
-+CONFIG_L2TP_V3=y
-+CONFIG_L2TP_IP=m
-+CONFIG_L2TP_ETH=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+CONFIG_VLAN_8021Q_GVRP=y
-+CONFIG_ATALK=m
-+CONFIG_6LOWPAN=m
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_CBQ=m
-+CONFIG_NET_SCH_HTB=m
-+CONFIG_NET_SCH_HFSC=m
-+CONFIG_NET_SCH_PRIO=m
-+CONFIG_NET_SCH_MULTIQ=m
-+CONFIG_NET_SCH_RED=m
-+CONFIG_NET_SCH_SFB=m
-+CONFIG_NET_SCH_SFQ=m
-+CONFIG_NET_SCH_TEQL=m
-+CONFIG_NET_SCH_TBF=m
-+CONFIG_NET_SCH_GRED=m
-+CONFIG_NET_SCH_DSMARK=m
-+CONFIG_NET_SCH_NETEM=m
-+CONFIG_NET_SCH_DRR=m
-+CONFIG_NET_SCH_MQPRIO=m
-+CONFIG_NET_SCH_CHOKE=m
-+CONFIG_NET_SCH_QFQ=m
-+CONFIG_NET_SCH_CODEL=m
-+CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_INGRESS=m
-+CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_CLS_BASIC=m
-+CONFIG_NET_CLS_TCINDEX=m
-+CONFIG_NET_CLS_ROUTE4=m
-+CONFIG_NET_CLS_FW=m
-+CONFIG_NET_CLS_U32=m
-+CONFIG_CLS_U32_MARK=y
-+CONFIG_NET_CLS_RSVP=m
-+CONFIG_NET_CLS_RSVP6=m
-+CONFIG_NET_CLS_FLOW=m
-+CONFIG_NET_CLS_CGROUP=m
-+CONFIG_NET_EMATCH=y
-+CONFIG_NET_EMATCH_CMP=m
-+CONFIG_NET_EMATCH_NBYTE=m
-+CONFIG_NET_EMATCH_U32=m
-+CONFIG_NET_EMATCH_META=m
-+CONFIG_NET_EMATCH_TEXT=m
-+CONFIG_NET_EMATCH_IPSET=m
-+CONFIG_NET_CLS_ACT=y
-+CONFIG_NET_ACT_POLICE=m
-+CONFIG_NET_ACT_GACT=m
-+CONFIG_GACT_PROB=y
-+CONFIG_NET_ACT_MIRRED=m
-+CONFIG_NET_ACT_IPT=m
-+CONFIG_NET_ACT_NAT=m
-+CONFIG_NET_ACT_PEDIT=m
-+CONFIG_NET_ACT_SIMP=m
-+CONFIG_NET_ACT_SKBEDIT=m
-+CONFIG_NET_ACT_CSUM=m
-+CONFIG_BATMAN_ADV=m
-+CONFIG_OPENVSWITCH=m
-+CONFIG_NET_PKTGEN=m
-+CONFIG_HAMRADIO=y
-+CONFIG_AX25=m
-+CONFIG_NETROM=m
-+CONFIG_ROSE=m
-+CONFIG_MKISS=m
-+CONFIG_6PACK=m
-+CONFIG_BPQETHER=m
-+CONFIG_BAYCOM_SER_FDX=m
-+CONFIG_BAYCOM_SER_HDX=m
-+CONFIG_YAM=m
-+CONFIG_CAN=m
-+CONFIG_CAN_VCAN=m
-+CONFIG_CAN_MCP251X=m
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_BT=m
-+CONFIG_BT_6LOWPAN=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_BT_WILINK=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_RFKILL=m
-+CONFIG_RFKILL_INPUT=y
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_NFC_PN533=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_ZRAM=m
-+CONFIG_ZRAM_LZ4_COMPRESS=y
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_DRBD=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_ATA_OVER_ETH=m
-+CONFIG_EEPROM_AT24=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_CHR_DEV_ST=m
-+CONFIG_CHR_DEV_OSST=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_CHR_DEV_SG=m
-+CONFIG_SCSI_ISCSI_ATTRS=y
-+CONFIG_ISCSI_TCP=m
-+CONFIG_ISCSI_BOOT_SYSFS=m
-+CONFIG_MD=y
-+CONFIG_MD_LINEAR=m
-+CONFIG_MD_RAID0=m
-+CONFIG_BLK_DEV_DM=m
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_LOG_USERSPACE=m
-+CONFIG_DM_RAID=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_DELAY=m
-+CONFIG_NETDEVICES=y
-+CONFIG_BONDING=m
-+CONFIG_DUMMY=m
-+CONFIG_IFB=m
-+CONFIG_MACVLAN=m
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_VETH=m
-+CONFIG_ENC28J60=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOATM=m
-+CONFIG_PPPOE=m
-+CONFIG_PPPOL2TP=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_SLIP_SMART=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_RTL8152=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_AX88179_178A=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_CDC_NCM=m
-+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-+CONFIG_USB_NET_CDC_MBIM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SR9700=m
-+CONFIG_USB_NET_SR9800=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_EPSON2888=y
-+CONFIG_USB_KC2190=y
-+CONFIG_USB_NET_ZAURUS=m
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_QMI_WWAN=m
-+CONFIG_USB_HSO=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_RTL8187=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_ATH_CARDS=m
-+CONFIG_ATH9K=m
-+CONFIG_ATH9K_HTC=m
-+CONFIG_CARL9170=m
-+CONFIG_ATH6KL=m
-+CONFIG_ATH6KL_USB=m
-+CONFIG_AR5523=m
-+CONFIG_B43=m
-+# CONFIG_B43_PHY_N is not set
-+CONFIG_B43LEGACY=m
-+CONFIG_BRCMFMAC=m
-+CONFIG_BRCMFMAC_USB=y
-+CONFIG_HOSTAP=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT3573=y
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RT2800USB_RT55XX=y
-+CONFIG_RT2800USB_UNKNOWN=y
-+CONFIG_RTL8192CU=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_INPUT_POLLDEV=m
-+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_KEYBOARD_ATKBD is not set
-+CONFIG_KEYBOARD_GPIO=m
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_JOYSTICK=y
-+CONFIG_JOYSTICK_IFORCE=m
-+CONFIG_JOYSTICK_IFORCE_USB=y
-+CONFIG_JOYSTICK_XPAD=m
-+CONFIG_JOYSTICK_XPAD_FF=y
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-+CONFIG_TOUCHSCREEN_STMPE=m
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_HW_RANDOM_BCM2708=m
-+CONFIG_RAW_DRIVER=y
-+CONFIG_BRCM_CHAR_DRIVERS=y
-+CONFIG_BCM_VC_CMA=y
-+CONFIG_BCM_VC_SM=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_MUX=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2835=m
-+CONFIG_SPI_BCM2708=m
-+CONFIG_SPI_SPIDEV=y
-+CONFIG_PPS=m
-+CONFIG_PPS_CLIENT_LDISC=m
-+CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_ARIZONA=m
-+CONFIG_GPIO_STMPE=y
-+CONFIG_W1=m
-+CONFIG_W1_MASTER_DS2490=m
-+CONFIG_W1_MASTER_DS2482=m
-+CONFIG_W1_MASTER_DS1WM=m
-+CONFIG_W1_MASTER_GPIO=m
-+CONFIG_W1_SLAVE_THERM=m
-+CONFIG_W1_SLAVE_SMEM=m
-+CONFIG_W1_SLAVE_DS2408=m
-+CONFIG_W1_SLAVE_DS2413=m
-+CONFIG_W1_SLAVE_DS2406=m
-+CONFIG_W1_SLAVE_DS2423=m
-+CONFIG_W1_SLAVE_DS2431=m
-+CONFIG_W1_SLAVE_DS2433=m
-+CONFIG_W1_SLAVE_DS2760=m
-+CONFIG_W1_SLAVE_DS2780=m
-+CONFIG_W1_SLAVE_DS2781=m
-+CONFIG_W1_SLAVE_DS28E04=m
-+CONFIG_W1_SLAVE_BQ27000=m
-+CONFIG_BATTERY_DS2760=m
-+# CONFIG_HWMON is not set
-+CONFIG_THERMAL=y
-+CONFIG_THERMAL_BCM2835=y
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2708_WDT=m
-+CONFIG_UCB1400_CORE=m
-+CONFIG_MFD_STMPE=y
-+CONFIG_STMPE_SPI=y
-+CONFIG_MFD_ARIZONA_I2C=m
-+CONFIG_MFD_ARIZONA_SPI=m
-+CONFIG_MFD_WM5102=y
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_RC_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_LIRC=m
-+CONFIG_RC_DEVICES=y
-+CONFIG_RC_ATI_REMOTE=m
-+CONFIG_IR_IMON=m
-+CONFIG_IR_MCEUSB=m
-+CONFIG_IR_REDRAT3=m
-+CONFIG_IR_STREAMZAP=m
-+CONFIG_IR_IGUANA=m
-+CONFIG_IR_TTUSBIR=m
-+CONFIG_RC_LOOPBACK=m
-+CONFIG_IR_GPIO_CIR=m
-+CONFIG_MEDIA_USB_SUPPORT=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_M5602=m
-+CONFIG_USB_STV06XX=m
-+CONFIG_USB_GL860=m
-+CONFIG_USB_GSPCA_BENQ=m
-+CONFIG_USB_GSPCA_CONEX=m
-+CONFIG_USB_GSPCA_CPIA1=m
-+CONFIG_USB_GSPCA_DTCS033=m
-+CONFIG_USB_GSPCA_ETOMS=m
-+CONFIG_USB_GSPCA_FINEPIX=m
-+CONFIG_USB_GSPCA_JEILINJ=m
-+CONFIG_USB_GSPCA_JL2005BCD=m
-+CONFIG_USB_GSPCA_KINECT=m
-+CONFIG_USB_GSPCA_KONICA=m
-+CONFIG_USB_GSPCA_MARS=m
-+CONFIG_USB_GSPCA_MR97310A=m
-+CONFIG_USB_GSPCA_NW80X=m
-+CONFIG_USB_GSPCA_OV519=m
-+CONFIG_USB_GSPCA_OV534=m
-+CONFIG_USB_GSPCA_OV534_9=m
-+CONFIG_USB_GSPCA_PAC207=m
-+CONFIG_USB_GSPCA_PAC7302=m
-+CONFIG_USB_GSPCA_PAC7311=m
-+CONFIG_USB_GSPCA_SE401=m
-+CONFIG_USB_GSPCA_SN9C2028=m
-+CONFIG_USB_GSPCA_SN9C20X=m
-+CONFIG_USB_GSPCA_SONIXB=m
-+CONFIG_USB_GSPCA_SONIXJ=m
-+CONFIG_USB_GSPCA_SPCA500=m
-+CONFIG_USB_GSPCA_SPCA501=m
-+CONFIG_USB_GSPCA_SPCA505=m
-+CONFIG_USB_GSPCA_SPCA506=m
-+CONFIG_USB_GSPCA_SPCA508=m
-+CONFIG_USB_GSPCA_SPCA561=m
-+CONFIG_USB_GSPCA_SPCA1528=m
-+CONFIG_USB_GSPCA_SQ905=m
-+CONFIG_USB_GSPCA_SQ905C=m
-+CONFIG_USB_GSPCA_SQ930X=m
-+CONFIG_USB_GSPCA_STK014=m
-+CONFIG_USB_GSPCA_STK1135=m
-+CONFIG_USB_GSPCA_STV0680=m
-+CONFIG_USB_GSPCA_SUNPLUS=m
-+CONFIG_USB_GSPCA_T613=m
-+CONFIG_USB_GSPCA_TOPRO=m
-+CONFIG_USB_GSPCA_TV8532=m
-+CONFIG_USB_GSPCA_VC032X=m
-+CONFIG_USB_GSPCA_VICAM=m
-+CONFIG_USB_GSPCA_XIRLINK_CIT=m
-+CONFIG_USB_GSPCA_ZC3XX=m
-+CONFIG_USB_PWC=m
-+CONFIG_VIDEO_CPIA2=m
-+CONFIG_USB_ZR364XX=m
-+CONFIG_USB_STKWEBCAM=m
-+CONFIG_USB_S2255=m
-+CONFIG_VIDEO_USBTV=m
-+CONFIG_VIDEO_PVRUSB2=m
-+CONFIG_VIDEO_HDPVR=m
-+CONFIG_VIDEO_TLG2300=m
-+CONFIG_VIDEO_USBVISION=m
-+CONFIG_VIDEO_STK1160_COMMON=m
-+CONFIG_VIDEO_STK1160_AC97=y
-+CONFIG_VIDEO_GO7007=m
-+CONFIG_VIDEO_GO7007_USB=m
-+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-+CONFIG_VIDEO_AU0828=m
-+CONFIG_VIDEO_AU0828_RC=y
-+CONFIG_VIDEO_CX231XX=m
-+CONFIG_VIDEO_CX231XX_ALSA=m
-+CONFIG_VIDEO_CX231XX_DVB=m
-+CONFIG_VIDEO_TM6000=m
-+CONFIG_VIDEO_TM6000_ALSA=m
-+CONFIG_VIDEO_TM6000_DVB=m
-+CONFIG_DVB_USB=m
-+CONFIG_DVB_USB_A800=m
-+CONFIG_DVB_USB_DIBUSB_MB=m
-+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-+CONFIG_DVB_USB_DIBUSB_MC=m
-+CONFIG_DVB_USB_DIB0700=m
-+CONFIG_DVB_USB_UMT_010=m
-+CONFIG_DVB_USB_CXUSB=m
-+CONFIG_DVB_USB_M920X=m
-+CONFIG_DVB_USB_DIGITV=m
-+CONFIG_DVB_USB_VP7045=m
-+CONFIG_DVB_USB_VP702X=m
-+CONFIG_DVB_USB_GP8PSK=m
-+CONFIG_DVB_USB_NOVA_T_USB2=m
-+CONFIG_DVB_USB_TTUSB2=m
-+CONFIG_DVB_USB_DTT200U=m
-+CONFIG_DVB_USB_OPERA1=m
-+CONFIG_DVB_USB_AF9005=m
-+CONFIG_DVB_USB_AF9005_REMOTE=m
-+CONFIG_DVB_USB_PCTV452E=m
-+CONFIG_DVB_USB_DW2102=m
-+CONFIG_DVB_USB_CINERGY_T2=m
-+CONFIG_DVB_USB_DTV5100=m
-+CONFIG_DVB_USB_FRIIO=m
-+CONFIG_DVB_USB_AZ6027=m
-+CONFIG_DVB_USB_TECHNISAT_USB2=m
-+CONFIG_DVB_USB_V2=m
-+CONFIG_DVB_USB_AF9015=m
-+CONFIG_DVB_USB_AF9035=m
-+CONFIG_DVB_USB_ANYSEE=m
-+CONFIG_DVB_USB_AU6610=m
-+CONFIG_DVB_USB_AZ6007=m
-+CONFIG_DVB_USB_CE6230=m
-+CONFIG_DVB_USB_EC168=m
-+CONFIG_DVB_USB_GL861=m
-+CONFIG_DVB_USB_LME2510=m
-+CONFIG_DVB_USB_MXL111SF=m
-+CONFIG_DVB_USB_RTL28XXU=m
-+CONFIG_DVB_USB_DVBSKY=m
-+CONFIG_SMS_USB_DRV=m
-+CONFIG_DVB_B2C2_FLEXCOP_USB=m
-+CONFIG_DVB_AS102=m
-+CONFIG_VIDEO_EM28XX=m
-+CONFIG_VIDEO_EM28XX_V4L2=m
-+CONFIG_VIDEO_EM28XX_ALSA=m
-+CONFIG_VIDEO_EM28XX_DVB=m
-+CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_BCM2835=y
-+CONFIG_VIDEO_BCM2835_MMAL=m
-+CONFIG_RADIO_SI470X=y
-+CONFIG_USB_SI470X=m
-+CONFIG_I2C_SI470X=m
-+CONFIG_RADIO_SI4713=m
-+CONFIG_I2C_SI4713=m
-+CONFIG_USB_MR800=m
-+CONFIG_USB_DSBR=m
-+CONFIG_RADIO_SHARK=m
-+CONFIG_RADIO_SHARK2=m
-+CONFIG_USB_KEENE=m
-+CONFIG_USB_MA901=m
-+CONFIG_RADIO_TEA5764=m
-+CONFIG_RADIO_SAA7706H=m
-+CONFIG_RADIO_TEF6862=m
-+CONFIG_RADIO_WL1273=m
-+CONFIG_RADIO_WL128X=m
-+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-+CONFIG_VIDEO_UDA1342=m
-+CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_TVP5150=m
-+CONFIG_VIDEO_TW2804=m
-+CONFIG_VIDEO_TW9903=m
-+CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV7640=m
-+CONFIG_VIDEO_MT9V011=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FB_UDL=m
-+CONFIG_FB_SSD1307=m
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_GPIO=m
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_SEQUENCER_OSS=y
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_BCM2835=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_CAIAQ_INPUT=y
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_SOC=m
-+CONFIG_SND_BCM2708_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
-+CONFIG_SND_BCM2708_SOC_RPI_DAC=m
-+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
-+CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_SOUND_PRIME=m
-+CONFIG_HIDRAW=y
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_ELO=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THINGM=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_WACOM=m
-+CONFIG_HID_WIIMOTE=m
-+CONFIG_HID_XINMO=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USBIP_CORE=m
-+CONFIG_USBIP_VHCI_HCD=m
-+CONFIG_USBIP_HOST=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_F81232=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_METRO=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_XSENS_MT=m
-+CONFIG_USB_SERIAL_WISHBONE=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_QT2=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_LED=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_USB_ATM=m
-+CONFIG_USB_SPEEDTOUCH=m
-+CONFIG_USB_CXACRU=m
-+CONFIG_USB_UEAGLEATM=m
-+CONFIG_USB_XUSBATM=m
-+CONFIG_MMC=y
-+CONFIG_MMC_BLOCK_MINORS=32
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_MMC_BCM2835_SDHOST=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SPI=m
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_ONESHOT=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-+CONFIG_LEDS_TRIGGER_CPU=y
-+CONFIG_LEDS_TRIGGER_GPIO=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TRANSIENT=m
-+CONFIG_LEDS_TRIGGER_CAMERA=m
-+CONFIG_LEDS_TRIGGER_INPUT=y
-+CONFIG_RTC_CLASS=y
-+# CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_DS1307=m
-+CONFIG_RTC_DRV_DS1374=m
-+CONFIG_RTC_DRV_DS1672=m
-+CONFIG_RTC_DRV_DS3232=m
-+CONFIG_RTC_DRV_MAX6900=m
-+CONFIG_RTC_DRV_RS5C372=m
-+CONFIG_RTC_DRV_ISL1208=m
-+CONFIG_RTC_DRV_ISL12022=m
-+CONFIG_RTC_DRV_ISL12057=m
-+CONFIG_RTC_DRV_X1205=m
-+CONFIG_RTC_DRV_PCF2127=m
-+CONFIG_RTC_DRV_PCF8523=m
-+CONFIG_RTC_DRV_PCF8563=m
-+CONFIG_RTC_DRV_PCF8583=m
-+CONFIG_RTC_DRV_M41T80=m
-+CONFIG_RTC_DRV_BQ32K=m
-+CONFIG_RTC_DRV_S35390A=m
-+CONFIG_RTC_DRV_FM3130=m
-+CONFIG_RTC_DRV_RX8581=m
-+CONFIG_RTC_DRV_RX8025=m
-+CONFIG_RTC_DRV_EM3027=m
-+CONFIG_RTC_DRV_RV3029C2=m
-+CONFIG_RTC_DRV_M41T93=m
-+CONFIG_RTC_DRV_M41T94=m
-+CONFIG_RTC_DRV_DS1305=m
-+CONFIG_RTC_DRV_DS1390=m
-+CONFIG_RTC_DRV_MAX6902=m
-+CONFIG_RTC_DRV_R9701=m
-+CONFIG_RTC_DRV_RS5C348=m
-+CONFIG_RTC_DRV_DS3234=m
-+CONFIG_RTC_DRV_PCF2123=m
-+CONFIG_RTC_DRV_RX4581=m
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_BCM2708=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+CONFIG_STAGING=y
-+CONFIG_PRISM2_USB=m
-+CONFIG_R8712U=m
-+CONFIG_R8188EU=m
-+CONFIG_R8723AU=m
-+CONFIG_VT6656=m
-+CONFIG_SPEAKUP=m
-+CONFIG_SPEAKUP_SYNTH_SOFT=m
-+CONFIG_STAGING_MEDIA=y
-+CONFIG_LIRC_STAGING=y
-+CONFIG_LIRC_IGORPLUGUSB=m
-+CONFIG_LIRC_IMON=m
-+CONFIG_LIRC_RPI=m
-+CONFIG_LIRC_SASEM=m
-+CONFIG_LIRC_SERIAL=m
-+CONFIG_FB_TFT=m
-+CONFIG_FB_TFT_AGM1264K_FL=m
-+CONFIG_FB_TFT_BD663474=m
-+CONFIG_FB_TFT_HX8340BN=m
-+CONFIG_FB_TFT_HX8347D=m
-+CONFIG_FB_TFT_HX8353D=m
-+CONFIG_FB_TFT_ILI9320=m
-+CONFIG_FB_TFT_ILI9325=m
-+CONFIG_FB_TFT_ILI9340=m
-+CONFIG_FB_TFT_ILI9341=m
-+CONFIG_FB_TFT_ILI9481=m
-+CONFIG_FB_TFT_ILI9486=m
-+CONFIG_FB_TFT_PCD8544=m
-+CONFIG_FB_TFT_RA8875=m
-+CONFIG_FB_TFT_S6D02A1=m
-+CONFIG_FB_TFT_S6D1121=m
-+CONFIG_FB_TFT_SSD1289=m
-+CONFIG_FB_TFT_SSD1306=m
-+CONFIG_FB_TFT_SSD1331=m
-+CONFIG_FB_TFT_SSD1351=m
-+CONFIG_FB_TFT_ST7735R=m
-+CONFIG_FB_TFT_TINYLCD=m
-+CONFIG_FB_TFT_TLS8204=m
-+CONFIG_FB_TFT_UC1701=m
-+CONFIG_FB_TFT_UPD161704=m
-+CONFIG_FB_TFT_WATTEROTT=m
-+CONFIG_FB_FLEX=m
-+CONFIG_FB_TFT_FBTFT_DEVICE=m
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_EXTCON=m
-+CONFIG_EXTCON_ARIZONA=m
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_FANOTIFY=y
-+CONFIG_QFMT_V1=m
-+CONFIG_QFMT_V2=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_NTFS_RW=y
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_CONFIGFS_FS=y
-+CONFIG_ECRYPT_FS=m
-+CONFIG_HFS_FS=m
-+CONFIG_HFSPLUS_FS=m
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_F2FS_FS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_SWAP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3_ACL=y
-+CONFIG_NFSD_V4=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_UPCALL=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_DLM=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+CONFIG_TIMER_STATS=y
-+# CONFIG_DEBUG_PREEMPT is not set
-+CONFIG_LATENCYTOP=y
-+CONFIG_IRQSOFF_TRACER=y
-+CONFIG_SCHED_TRACER=y
-+CONFIG_STACK_TRACER=y
-+CONFIG_BLK_DEV_IO_TRACE=y
-+# CONFIG_KPROBE_EVENT is not set
-+CONFIG_FUNCTION_PROFILER=y
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_CRYPTO_USER=m
-+CONFIG_CRYPTO_NULL=m
-+CONFIG_CRYPTO_CRYPTD=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_CTS=m
-+CONFIG_CRYPTO_XTS=m
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_SHA1_ARM=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_AES_ARM=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-diff -Nur linux-3.18.14/arch/arm/include/asm/dma-mapping.h linux-rpi/arch/arm/include/asm/dma-mapping.h
---- linux-3.18.14/arch/arm/include/asm/dma-mapping.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/include/asm/dma-mapping.h 2015-05-31 14:46:08.129661005 -0500
-@@ -58,37 +58,21 @@
- #ifndef __arch_pfn_to_dma
- static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
- {
-- if (dev)
-- pfn -= dev->dma_pfn_offset;
- return (dma_addr_t)__pfn_to_bus(pfn);
- }
-
- static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
- {
-- unsigned long pfn = __bus_to_pfn(addr);
--
-- if (dev)
-- pfn += dev->dma_pfn_offset;
--
-- return pfn;
-+ return __bus_to_pfn(addr);
- }
-
- static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
- {
-- if (dev) {
-- unsigned long pfn = dma_to_pfn(dev, addr);
--
-- return phys_to_virt(__pfn_to_phys(pfn));
-- }
--
- return (void *)__bus_to_virt((unsigned long)addr);
- }
-
- static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
- {
-- if (dev)
-- return pfn_to_dma(dev, virt_to_pfn(addr));
--
- return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
- }
-
-diff -Nur linux-3.18.14/arch/arm/include/asm/entry-macro-multi.S linux-rpi/arch/arm/include/asm/entry-macro-multi.S
---- linux-3.18.14/arch/arm/include/asm/entry-macro-multi.S 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/include/asm/entry-macro-multi.S 2015-05-31 14:46:08.129661005 -0500
-@@ -1,5 +1,6 @@
- #include <asm/assembler.h>
-
-+#ifndef CONFIG_ARCH_BCM2709
- /*
- * Interrupt handling. Preserves r7, r8, r9
- */
-@@ -28,6 +29,7 @@
- #endif
- 9997:
- .endm
-+#endif
-
- .macro arch_irq_handler, symbol_name
- .align 5
-diff -Nur linux-3.18.14/arch/arm/include/asm/irqflags.h linux-rpi/arch/arm/include/asm/irqflags.h
---- linux-3.18.14/arch/arm/include/asm/irqflags.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/include/asm/irqflags.h 2015-05-31 14:46:08.141661005 -0500
-@@ -145,12 +145,22 @@
- }
-
- /*
-- * restore saved IRQ & FIQ state
-+ * restore saved IRQ state
- */
- static inline void arch_local_irq_restore(unsigned long flags)
- {
-- asm volatile(
-- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore"
-+ unsigned long temp = 0;
-+ flags &= ~(1 << 6);
-+ asm volatile (
-+ " mrs %0, cpsr"
-+ : "=r" (temp)
-+ :
-+ : "memory", "cc");
-+ /* Preserve FIQ bit */
-+ temp &= (1 << 6);
-+ flags = flags | temp;
-+ asm volatile (
-+ " msr cpsr_c, %0 @ local_irq_restore"
- :
- : "r" (flags)
- : "memory", "cc");
-diff -Nur linux-3.18.14/arch/arm/include/asm/string.h linux-rpi/arch/arm/include/asm/string.h
---- linux-3.18.14/arch/arm/include/asm/string.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/include/asm/string.h 2015-05-31 14:46:08.145661005 -0500
-@@ -24,6 +24,11 @@
- #define __HAVE_ARCH_MEMSET
- extern void * memset(void *, int, __kernel_size_t);
-
-+#ifdef CONFIG_MACH_BCM2708
-+#define __HAVE_ARCH_MEMCMP
-+extern int memcmp(const void *, const void *, size_t);
-+#endif
-+
- extern void __memzero(void *ptr, __kernel_size_t n);
-
- #define memset(p,v,n) \
-diff -Nur linux-3.18.14/arch/arm/include/asm/uaccess.h linux-rpi/arch/arm/include/asm/uaccess.h
---- linux-3.18.14/arch/arm/include/asm/uaccess.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/include/asm/uaccess.h 2015-05-31 14:46:08.145661005 -0500
-@@ -475,6 +475,7 @@
-
- #ifdef CONFIG_MMU
- extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n);
-+extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n);
- extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n);
- extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n);
- extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
-diff -Nur linux-3.18.14/arch/arm/Kconfig linux-rpi/arch/arm/Kconfig
---- linux-3.18.14/arch/arm/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/Kconfig 2015-05-31 14:46:07.957661007 -0500
-@@ -381,6 +381,23 @@
- This enables support for systems based on Atmel
- AT91RM9200 and AT91SAM9* processors.
-
-+config ARCH_BCM2708
-+ bool "Broadcom BCM2708 family"
-+ select CPU_V6
-+ select ARM_AMBA
-+ select HAVE_SCHED_CLOCK
-+ select NEED_MACH_GPIO_H
-+ select NEED_MACH_MEMORY_H
-+ select COMMON_CLK
-+ select ARCH_HAS_CPUFREQ
-+ select GENERIC_CLOCKEVENTS
-+ select ARM_ERRATA_411920
-+ select MACH_BCM2708
-+ select VC4
-+ select FIQ
-+ help
-+ This enables support for Broadcom BCM2708 boards.
-+
- config ARCH_CLPS711X
- bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
- select ARCH_REQUIRE_GPIOLIB
-@@ -786,6 +803,26 @@
- help
- Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
-
-+config ARCH_BCM2709
-+ bool "Broadcom BCM2709 family"
-+ select ARCH_HAS_BARRIERS if SMP
-+ select CPU_V7
-+ select HAVE_SMP
-+ select ARM_AMBA
-+ select MIGHT_HAVE_CACHE_L2X0
-+ select HAVE_SCHED_CLOCK
-+ select NEED_MACH_MEMORY_H
-+ select NEED_MACH_IO_H
-+ select COMMON_CLK
-+ select ARCH_HAS_CPUFREQ
-+ select GENERIC_CLOCKEVENTS
-+ select MACH_BCM2709
-+ select VC4
-+ select FIQ
-+# select ZONE_DMA
-+ help
-+ This enables support for Broadcom BCM2709 boards.
-+
- endchoice
-
- menu "Multiple platform selection"
-@@ -972,6 +1009,8 @@
- source "arch/arm/mach-vt8500/Kconfig"
-
- source "arch/arm/mach-w90x900/Kconfig"
-+source "arch/arm/mach-bcm2708/Kconfig"
-+source "arch/arm/mach-bcm2709/Kconfig"
-
- source "arch/arm/mach-zynq/Kconfig"
-
-diff -Nur linux-3.18.14/arch/arm/Kconfig.debug linux-rpi/arch/arm/Kconfig.debug
---- linux-3.18.14/arch/arm/Kconfig.debug 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/Kconfig.debug 2015-05-31 14:46:07.961661006 -0500
-@@ -985,6 +985,14 @@
- options; the platform specific options are deprecated
- and will be soon removed.
-
-+ config DEBUG_BCM2708_UART0
-+ bool "Broadcom BCM2708 UART0 (PL011)"
-+ depends on MACH_BCM2708
-+ help
-+ Say Y here if you want the debug print routines to direct
-+ their output to UART 0. The port must have been initialised
-+ by the boot-loader before use.
-+
- endchoice
-
- config DEBUG_EXYNOS_UART
-diff -Nur linux-3.18.14/arch/arm/kernel/fiqasm.S linux-rpi/arch/arm/kernel/fiqasm.S
---- linux-3.18.14/arch/arm/kernel/fiqasm.S 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/kernel/fiqasm.S 2015-05-31 14:46:08.157661005 -0500
-@@ -47,3 +47,7 @@
- mov r0, r0 @ avoid hazard prior to ARMv4
- ret lr
- ENDPROC(__get_fiq_regs)
-+
-+ENTRY(__FIQ_Branch)
-+ mov pc, r8
-+ENDPROC(__FIQ_Branch)
-diff -Nur linux-3.18.14/arch/arm/kernel/head.S linux-rpi/arch/arm/kernel/head.S
---- linux-3.18.14/arch/arm/kernel/head.S 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/kernel/head.S 2015-05-31 14:46:08.157661005 -0500
-@@ -673,6 +673,14 @@
- ldrcc r7, [r4], #4 @ use branch for delay slot
- bcc 1b
- ret lr
-+ nop
-+ nop
-+ nop
-+ nop
-+ nop
-+ nop
-+ nop
-+ nop
- #endif
- ENDPROC(__fixup_a_pv_table)
-
-diff -Nur linux-3.18.14/arch/arm/kernel/process.c linux-rpi/arch/arm/kernel/process.c
---- linux-3.18.14/arch/arm/kernel/process.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/kernel/process.c 2015-05-31 14:46:08.169661004 -0500
-@@ -172,6 +172,16 @@
- }
- #endif
-
-+char bcm2708_reboot_mode = 'h';
-+
-+int __init reboot_setup(char *str)
-+{
-+ bcm2708_reboot_mode = str[0];
-+ return 1;
-+}
-+
-+__setup("reboot=", reboot_setup);
-+
- /*
- * Called by kexec, immediately prior to machine_kexec().
- *
-diff -Nur linux-3.18.14/arch/arm/lib/arm-mem.h linux-rpi/arch/arm/lib/arm-mem.h
---- linux-3.18.14/arch/arm/lib/arm-mem.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/arm-mem.h 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,159 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+.macro myfunc fname
-+ .func fname
-+ .global fname
-+fname:
-+.endm
-+
-+.macro preload_leading_step1 backwards, ptr, base
-+/* If the destination is already 16-byte aligned, then we need to preload
-+ * between 0 and prefetch_distance (inclusive) cache lines ahead so there
-+ * are no gaps when the inner loop starts.
-+ */
-+ .if backwards
-+ sub ptr, base, #1
-+ bic ptr, ptr, #31
-+ .else
-+ bic ptr, base, #31
-+ .endif
-+ .set OFFSET, 0
-+ .rept prefetch_distance+1
-+ pld [ptr, #OFFSET]
-+ .if backwards
-+ .set OFFSET, OFFSET-32
-+ .else
-+ .set OFFSET, OFFSET+32
-+ .endif
-+ .endr
-+.endm
-+
-+.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp
-+/* However, if the destination is not 16-byte aligned, we may need to
-+ * preload one more cache line than that. The question we need to ask is:
-+ * are the leading bytes more than the amount by which the source
-+ * pointer will be rounded down for preloading, and if so, by how many
-+ * cache lines?
-+ */
-+ .if backwards
-+/* Here we compare against how many bytes we are into the
-+ * cache line, counting down from the highest such address.
-+ * Effectively, we want to calculate
-+ * leading_bytes = dst&15
-+ * cacheline_offset = 31-((src-leading_bytes-1)&31)
-+ * extra_needed = leading_bytes - cacheline_offset
-+ * and test if extra_needed is <= 0, or rearranging:
-+ * leading_bytes + (src-leading_bytes-1)&31 <= 31
-+ */
-+ mov tmp, base, lsl #32-5
-+ sbc tmp, tmp, leading_bytes, lsl #32-5
-+ adds tmp, tmp, leading_bytes, lsl #32-5
-+ bcc 61f
-+ pld [ptr, #-32*(prefetch_distance+1)]
-+ .else
-+/* Effectively, we want to calculate
-+ * leading_bytes = (-dst)&15
-+ * cacheline_offset = (src+leading_bytes)&31
-+ * extra_needed = leading_bytes - cacheline_offset
-+ * and test if extra_needed is <= 0.
-+ */
-+ mov tmp, base, lsl #32-5
-+ add tmp, tmp, leading_bytes, lsl #32-5
-+ rsbs tmp, tmp, leading_bytes, lsl #32-5
-+ bls 61f
-+ pld [ptr, #32*(prefetch_distance+1)]
-+ .endif
-+61:
-+.endm
-+
-+.macro preload_trailing backwards, base, remain, tmp
-+ /* We need either 0, 1 or 2 extra preloads */
-+ .if backwards
-+ rsb tmp, base, #0
-+ mov tmp, tmp, lsl #32-5
-+ .else
-+ mov tmp, base, lsl #32-5
-+ .endif
-+ adds tmp, tmp, remain, lsl #32-5
-+ adceqs tmp, tmp, #0
-+ /* The instruction above has two effects: ensures Z is only
-+ * set if C was clear (so Z indicates that both shifted quantities
-+ * were 0), and clears C if Z was set (so C indicates that the sum
-+ * of the shifted quantities was greater and not equal to 32) */
-+ beq 82f
-+ .if backwards
-+ sub tmp, base, #1
-+ bic tmp, tmp, #31
-+ .else
-+ bic tmp, base, #31
-+ .endif
-+ bcc 81f
-+ .if backwards
-+ pld [tmp, #-32*(prefetch_distance+1)]
-+81:
-+ pld [tmp, #-32*prefetch_distance]
-+ .else
-+ pld [tmp, #32*(prefetch_distance+2)]
-+81:
-+ pld [tmp, #32*(prefetch_distance+1)]
-+ .endif
-+82:
-+.endm
-+
-+.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1
-+ .if backwards
-+ sub tmp0, base, #1
-+ bic tmp0, tmp0, #31
-+ pld [tmp0]
-+ sub tmp1, base, remain, lsl #shift
-+ .else
-+ bic tmp0, base, #31
-+ pld [tmp0]
-+ add tmp1, base, remain, lsl #shift
-+ sub tmp1, tmp1, #1
-+ .endif
-+ bic tmp1, tmp1, #31
-+ cmp tmp1, tmp0
-+ beq 92f
-+ .if narrow_case
-+ /* In this case, all the data fits in either 1 or 2 cache lines */
-+ pld [tmp1]
-+ .else
-+91:
-+ .if backwards
-+ sub tmp0, tmp0, #32
-+ .else
-+ add tmp0, tmp0, #32
-+ .endif
-+ cmp tmp0, tmp1
-+ pld [tmp0]
-+ bne 91b
-+ .endif
-+92:
-+.endm
-diff -Nur linux-3.18.14/arch/arm/lib/copy_from_user.S linux-rpi/arch/arm/lib/copy_from_user.S
---- linux-3.18.14/arch/arm/lib/copy_from_user.S 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/lib/copy_from_user.S 2015-05-31 14:46:08.177661005 -0500
-@@ -84,11 +84,13 @@
-
- .text
-
--ENTRY(__copy_from_user)
-+ENTRY(__copy_from_user_std)
-+WEAK(__copy_from_user)
-
- #include "copy_template.S"
-
- ENDPROC(__copy_from_user)
-+ENDPROC(__copy_from_user_std)
-
- .pushsection .fixup,"ax"
- .align 0
-diff -Nur linux-3.18.14/arch/arm/lib/exports_rpi.c linux-rpi/arch/arm/lib/exports_rpi.c
---- linux-3.18.14/arch/arm/lib/exports_rpi.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/exports_rpi.c 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,37 @@
-+/**
-+ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+
-+EXPORT_SYMBOL(memcmp);
-diff -Nur linux-3.18.14/arch/arm/lib/Makefile linux-rpi/arch/arm/lib/Makefile
---- linux-3.18.14/arch/arm/lib/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/lib/Makefile 2015-05-31 14:46:08.177661005 -0500
-@@ -6,15 +6,24 @@
-
- lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
- csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
-- delay.o delay-loop.o findbit.o memchr.o memcpy.o \
-- memmove.o memset.o memzero.o setbit.o \
-- strchr.o strrchr.o \
-+ delay.o delay-loop.o findbit.o memchr.o memzero.o \
-+ setbit.o strchr.o strrchr.o \
- testchangebit.o testclearbit.o testsetbit.o \
- ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
- ucmpdi2.o lib1funcs.o div64.o \
- io-readsb.o io-writesb.o io-readsl.o io-writesl.o \
- call_with_stack.o bswapsdi2.o
-
-+# Choose optimised implementations for Raspberry Pi
-+ifeq ($(CONFIG_MACH_BCM2708),y)
-+ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600
-+ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672
-+ obj-$(CONFIG_MODULES) += exports_rpi.o
-+ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o
-+else
-+ lib-y += memcpy.o memmove.o memset.o
-+endif
-+
- mmu-y := clear_user.o copy_page.o getuser.o putuser.o
-
- # the code in uaccess.S is not preemption safe and
-diff -Nur linux-3.18.14/arch/arm/lib/memcmp_rpi.S linux-rpi/arch/arm/lib/memcmp_rpi.S
---- linux-3.18.14/arch/arm/lib/memcmp_rpi.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/memcmp_rpi.S 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,285 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+.macro memcmp_process_head unaligned
-+ .if unaligned
-+ ldr DAT0, [S_1], #4
-+ ldr DAT1, [S_1], #4
-+ ldr DAT2, [S_1], #4
-+ ldr DAT3, [S_1], #4
-+ .else
-+ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3}
-+ .endif
-+ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7}
-+.endm
-+
-+.macro memcmp_process_tail
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ cmpeq DAT2, DAT6
-+ cmpeq DAT3, DAT7
-+ bne 200f
-+.endm
-+
-+.macro memcmp_leading_31bytes
-+ movs DAT0, OFF, lsl #31
-+ ldrmib DAT0, [S_1], #1
-+ ldrcsh DAT1, [S_1], #2
-+ ldrmib DAT4, [S_2], #1
-+ ldrcsh DAT5, [S_2], #2
-+ movpl DAT0, #0
-+ movcc DAT1, #0
-+ movpl DAT4, #0
-+ movcc DAT5, #0
-+ submi N, N, #1
-+ subcs N, N, #2
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ bne 200f
-+ movs DAT0, OFF, lsl #29
-+ ldrmi DAT0, [S_1], #4
-+ ldrcs DAT1, [S_1], #4
-+ ldrcs DAT2, [S_1], #4
-+ ldrmi DAT4, [S_2], #4
-+ ldmcsia S_2!, {DAT5, DAT6}
-+ movpl DAT0, #0
-+ movcc DAT1, #0
-+ movcc DAT2, #0
-+ movpl DAT4, #0
-+ movcc DAT5, #0
-+ movcc DAT6, #0
-+ submi N, N, #4
-+ subcs N, N, #8
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ cmpeq DAT2, DAT6
-+ bne 200f
-+ tst OFF, #16
-+ beq 105f
-+ memcmp_process_head 1
-+ sub N, N, #16
-+ memcmp_process_tail
-+105:
-+.endm
-+
-+.macro memcmp_trailing_15bytes unaligned
-+ movs N, N, lsl #29
-+ .if unaligned
-+ ldrcs DAT0, [S_1], #4
-+ ldrcs DAT1, [S_1], #4
-+ .else
-+ ldmcsia S_1!, {DAT0, DAT1}
-+ .endif
-+ ldrmi DAT2, [S_1], #4
-+ ldmcsia S_2!, {DAT4, DAT5}
-+ ldrmi DAT6, [S_2], #4
-+ movcc DAT0, #0
-+ movcc DAT1, #0
-+ movpl DAT2, #0
-+ movcc DAT4, #0
-+ movcc DAT5, #0
-+ movpl DAT6, #0
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ cmpeq DAT2, DAT6
-+ bne 200f
-+ movs N, N, lsl #2
-+ ldrcsh DAT0, [S_1], #2
-+ ldrmib DAT1, [S_1]
-+ ldrcsh DAT4, [S_2], #2
-+ ldrmib DAT5, [S_2]
-+ movcc DAT0, #0
-+ movpl DAT1, #0
-+ movcc DAT4, #0
-+ movpl DAT5, #0
-+ cmp DAT0, DAT4
-+ cmpeq DAT1, DAT5
-+ bne 200f
-+.endm
-+
-+.macro memcmp_long_inner_loop unaligned
-+110:
-+ memcmp_process_head unaligned
-+ pld [S_2, #prefetch_distance*32 + 16]
-+ memcmp_process_tail
-+ memcmp_process_head unaligned
-+ pld [S_1, OFF]
-+ memcmp_process_tail
-+ subs N, N, #32
-+ bhs 110b
-+ /* Just before the final (prefetch_distance+1) 32-byte blocks,
-+ * deal with final preloads */
-+ preload_trailing 0, S_1, N, DAT0
-+ preload_trailing 0, S_2, N, DAT0
-+ add N, N, #(prefetch_distance+2)*32 - 16
-+120:
-+ memcmp_process_head unaligned
-+ memcmp_process_tail
-+ subs N, N, #16
-+ bhs 120b
-+ /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ memcmp_trailing_15bytes unaligned
-+199: /* Reached end without detecting a difference */
-+ mov a1, #0
-+ setend le
-+ pop {DAT1-DAT6, pc}
-+.endm
-+
-+.macro memcmp_short_inner_loop unaligned
-+ subs N, N, #16 /* simplifies inner loop termination */
-+ blo 122f
-+120:
-+ memcmp_process_head unaligned
-+ memcmp_process_tail
-+ subs N, N, #16
-+ bhs 120b
-+122: /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ memcmp_trailing_15bytes unaligned
-+199: /* Reached end without detecting a difference */
-+ mov a1, #0
-+ setend le
-+ pop {DAT1-DAT6, pc}
-+.endm
-+
-+/*
-+ * int memcmp(const void *s1, const void *s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to buffer 1
-+ * a2 = pointer to buffer 2
-+ * a3 = number of bytes to compare (as unsigned chars)
-+ * On exit:
-+ * a1 = >0/=0/<0 if s1 >/=/< s2
-+ */
-+
-+.set prefetch_distance, 2
-+
-+ENTRY(memcmp)
-+ S_1 .req a1
-+ S_2 .req a2
-+ N .req a3
-+ DAT0 .req a4
-+ DAT1 .req v1
-+ DAT2 .req v2
-+ DAT3 .req v3
-+ DAT4 .req v4
-+ DAT5 .req v5
-+ DAT6 .req v6
-+ DAT7 .req ip
-+ OFF .req lr
-+
-+ push {DAT1-DAT6, lr}
-+ setend be /* lowest-addressed bytes are most significant */
-+
-+ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
-+ cmp N, #(prefetch_distance+3)*32 - 1
-+ blo 170f
-+
-+ /* Long case */
-+ /* Adjust N so that the decrement instruction can also test for
-+ * inner loop termination. We want it to stop when there are
-+ * (prefetch_distance+1) complete blocks to go. */
-+ sub N, N, #(prefetch_distance+2)*32
-+ preload_leading_step1 0, DAT0, S_1
-+ preload_leading_step1 0, DAT1, S_2
-+ tst S_2, #31
-+ beq 154f
-+ rsb OFF, S_2, #0 /* no need to AND with 15 here */
-+ preload_leading_step2 0, DAT0, S_1, OFF, DAT2
-+ preload_leading_step2 0, DAT1, S_2, OFF, DAT2
-+ memcmp_leading_31bytes
-+154: /* Second source now cacheline (32-byte) aligned; we have at
-+ * least one prefetch to go. */
-+ /* Prefetch offset is best selected such that it lies in the
-+ * first 8 of each 32 bytes - but it's just as easy to aim for
-+ * the first one */
-+ and OFF, S_1, #31
-+ rsb OFF, OFF, #32*prefetch_distance
-+ tst S_1, #3
-+ bne 140f
-+ memcmp_long_inner_loop 0
-+140: memcmp_long_inner_loop 1
-+
-+170: /* Short case */
-+ teq N, #0
-+ beq 199f
-+ preload_all 0, 0, 0, S_1, N, DAT0, DAT1
-+ preload_all 0, 0, 0, S_2, N, DAT0, DAT1
-+ tst S_2, #3
-+ beq 174f
-+172: subs N, N, #1
-+ blo 199f
-+ ldrb DAT0, [S_1], #1
-+ ldrb DAT4, [S_2], #1
-+ cmp DAT0, DAT4
-+ bne 200f
-+ tst S_2, #3
-+ bne 172b
-+174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */
-+ tst S_1, #3
-+ bne 140f
-+ memcmp_short_inner_loop 0
-+140: memcmp_short_inner_loop 1
-+
-+200: /* Difference found: determine sign. */
-+ movhi a1, #1
-+ movlo a1, #-1
-+ setend le
-+ pop {DAT1-DAT6, pc}
-+
-+ .unreq S_1
-+ .unreq S_2
-+ .unreq N
-+ .unreq DAT0
-+ .unreq DAT1
-+ .unreq DAT2
-+ .unreq DAT3
-+ .unreq DAT4
-+ .unreq DAT5
-+ .unreq DAT6
-+ .unreq DAT7
-+ .unreq OFF
-+ENDPROC(memcmp)
-diff -Nur linux-3.18.14/arch/arm/lib/memcpymove.h linux-rpi/arch/arm/lib/memcpymove.h
---- linux-3.18.14/arch/arm/lib/memcpymove.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/memcpymove.h 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,506 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8
-+ .if words == 1
-+ .if backwards
-+ mov r1, r0, lsl #32-align*8
-+ ldr r0, [S, #-4]!
-+ orr r1, r1, r0, lsr #align*8
-+ str r1, [D, #-4]!
-+ .else
-+ mov r0, r1, lsr #align*8
-+ ldr r1, [S, #4]!
-+ orr r0, r0, r1, lsl #32-align*8
-+ str r0, [D], #4
-+ .endif
-+ .elseif words == 2
-+ .if backwards
-+ ldr r1, [S, #-4]!
-+ mov r2, r0, lsl #32-align*8
-+ ldr r0, [S, #-4]!
-+ orr r2, r2, r1, lsr #align*8
-+ mov r1, r1, lsl #32-align*8
-+ orr r1, r1, r0, lsr #align*8
-+ stmdb D!, {r1, r2}
-+ .else
-+ ldr r1, [S, #4]!
-+ mov r0, r2, lsr #align*8
-+ ldr r2, [S, #4]!
-+ orr r0, r0, r1, lsl #32-align*8
-+ mov r1, r1, lsr #align*8
-+ orr r1, r1, r2, lsl #32-align*8
-+ stmia D!, {r0, r1}
-+ .endif
-+ .elseif words == 4
-+ .if backwards
-+ ldmdb S!, {r2, r3}
-+ mov r4, r0, lsl #32-align*8
-+ ldmdb S!, {r0, r1}
-+ orr r4, r4, r3, lsr #align*8
-+ mov r3, r3, lsl #32-align*8
-+ orr r3, r3, r2, lsr #align*8
-+ mov r2, r2, lsl #32-align*8
-+ orr r2, r2, r1, lsr #align*8
-+ mov r1, r1, lsl #32-align*8
-+ orr r1, r1, r0, lsr #align*8
-+ stmdb D!, {r1, r2, r3, r4}
-+ .else
-+ ldmib S!, {r1, r2}
-+ mov r0, r4, lsr #align*8
-+ ldmib S!, {r3, r4}
-+ orr r0, r0, r1, lsl #32-align*8
-+ mov r1, r1, lsr #align*8
-+ orr r1, r1, r2, lsl #32-align*8
-+ mov r2, r2, lsr #align*8
-+ orr r2, r2, r3, lsl #32-align*8
-+ mov r3, r3, lsr #align*8
-+ orr r3, r3, r4, lsl #32-align*8
-+ stmia D!, {r0, r1, r2, r3}
-+ .endif
-+ .elseif words == 8
-+ .if backwards
-+ ldmdb S!, {r4, r5, r6, r7}
-+ mov r8, r0, lsl #32-align*8
-+ ldmdb S!, {r0, r1, r2, r3}
-+ .if use_pld
-+ pld [S, OFF]
-+ .endif
-+ orr r8, r8, r7, lsr #align*8
-+ mov r7, r7, lsl #32-align*8
-+ orr r7, r7, r6, lsr #align*8
-+ mov r6, r6, lsl #32-align*8
-+ orr r6, r6, r5, lsr #align*8
-+ mov r5, r5, lsl #32-align*8
-+ orr r5, r5, r4, lsr #align*8
-+ mov r4, r4, lsl #32-align*8
-+ orr r4, r4, r3, lsr #align*8
-+ mov r3, r3, lsl #32-align*8
-+ orr r3, r3, r2, lsr #align*8
-+ mov r2, r2, lsl #32-align*8
-+ orr r2, r2, r1, lsr #align*8
-+ mov r1, r1, lsl #32-align*8
-+ orr r1, r1, r0, lsr #align*8
-+ stmdb D!, {r5, r6, r7, r8}
-+ stmdb D!, {r1, r2, r3, r4}
-+ .else
-+ ldmib S!, {r1, r2, r3, r4}
-+ mov r0, r8, lsr #align*8
-+ ldmib S!, {r5, r6, r7, r8}
-+ .if use_pld
-+ pld [S, OFF]
-+ .endif
-+ orr r0, r0, r1, lsl #32-align*8
-+ mov r1, r1, lsr #align*8
-+ orr r1, r1, r2, lsl #32-align*8
-+ mov r2, r2, lsr #align*8
-+ orr r2, r2, r3, lsl #32-align*8
-+ mov r3, r3, lsr #align*8
-+ orr r3, r3, r4, lsl #32-align*8
-+ mov r4, r4, lsr #align*8
-+ orr r4, r4, r5, lsl #32-align*8
-+ mov r5, r5, lsr #align*8
-+ orr r5, r5, r6, lsl #32-align*8
-+ mov r6, r6, lsr #align*8
-+ orr r6, r6, r7, lsl #32-align*8
-+ mov r7, r7, lsr #align*8
-+ orr r7, r7, r8, lsl #32-align*8
-+ stmia D!, {r0, r1, r2, r3}
-+ stmia D!, {r4, r5, r6, r7}
-+ .endif
-+ .endif
-+.endm
-+
-+.macro memcpy_leading_15bytes backwards, align
-+ movs DAT1, DAT2, lsl #31
-+ sub N, N, DAT2
-+ .if backwards
-+ ldrmib DAT0, [S, #-1]!
-+ ldrcsh DAT1, [S, #-2]!
-+ strmib DAT0, [D, #-1]!
-+ strcsh DAT1, [D, #-2]!
-+ .else
-+ ldrmib DAT0, [S], #1
-+ ldrcsh DAT1, [S], #2
-+ strmib DAT0, [D], #1
-+ strcsh DAT1, [D], #2
-+ .endif
-+ movs DAT1, DAT2, lsl #29
-+ .if backwards
-+ ldrmi DAT0, [S, #-4]!
-+ .if align == 0
-+ ldmcsdb S!, {DAT1, DAT2}
-+ .else
-+ ldrcs DAT2, [S, #-4]!
-+ ldrcs DAT1, [S, #-4]!
-+ .endif
-+ strmi DAT0, [D, #-4]!
-+ stmcsdb D!, {DAT1, DAT2}
-+ .else
-+ ldrmi DAT0, [S], #4
-+ .if align == 0
-+ ldmcsia S!, {DAT1, DAT2}
-+ .else
-+ ldrcs DAT1, [S], #4
-+ ldrcs DAT2, [S], #4
-+ .endif
-+ strmi DAT0, [D], #4
-+ stmcsia D!, {DAT1, DAT2}
-+ .endif
-+.endm
-+
-+.macro memcpy_trailing_15bytes backwards, align
-+ movs N, N, lsl #29
-+ .if backwards
-+ .if align == 0
-+ ldmcsdb S!, {DAT0, DAT1}
-+ .else
-+ ldrcs DAT1, [S, #-4]!
-+ ldrcs DAT0, [S, #-4]!
-+ .endif
-+ ldrmi DAT2, [S, #-4]!
-+ stmcsdb D!, {DAT0, DAT1}
-+ strmi DAT2, [D, #-4]!
-+ .else
-+ .if align == 0
-+ ldmcsia S!, {DAT0, DAT1}
-+ .else
-+ ldrcs DAT0, [S], #4
-+ ldrcs DAT1, [S], #4
-+ .endif
-+ ldrmi DAT2, [S], #4
-+ stmcsia D!, {DAT0, DAT1}
-+ strmi DAT2, [D], #4
-+ .endif
-+ movs N, N, lsl #2
-+ .if backwards
-+ ldrcsh DAT0, [S, #-2]!
-+ ldrmib DAT1, [S, #-1]
-+ strcsh DAT0, [D, #-2]!
-+ strmib DAT1, [D, #-1]
-+ .else
-+ ldrcsh DAT0, [S], #2
-+ ldrmib DAT1, [S]
-+ strcsh DAT0, [D], #2
-+ strmib DAT1, [D]
-+ .endif
-+.endm
-+
-+.macro memcpy_long_inner_loop backwards, align
-+ .if align != 0
-+ .if backwards
-+ ldr DAT0, [S, #-align]!
-+ .else
-+ ldr LAST, [S, #-align]!
-+ .endif
-+ .endif
-+110:
-+ .if align == 0
-+ .if backwards
-+ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ pld [S, OFF]
-+ stmdb D!, {DAT4, DAT5, DAT6, LAST}
-+ stmdb D!, {DAT0, DAT1, DAT2, DAT3}
-+ .else
-+ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ pld [S, OFF]
-+ stmia D!, {DAT0, DAT1, DAT2, DAT3}
-+ stmia D!, {DAT4, DAT5, DAT6, LAST}
-+ .endif
-+ .else
-+ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
-+ .endif
-+ subs N, N, #32
-+ bhs 110b
-+ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */
-+ preload_trailing backwards, S, N, OFF
-+ add N, N, #(prefetch_distance+2)*32 - 32
-+120:
-+ .if align == 0
-+ .if backwards
-+ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ stmdb D!, {DAT4, DAT5, DAT6, LAST}
-+ stmdb D!, {DAT0, DAT1, DAT2, DAT3}
-+ .else
-+ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+ stmia D!, {DAT0, DAT1, DAT2, DAT3}
-+ stmia D!, {DAT4, DAT5, DAT6, LAST}
-+ .endif
-+ .else
-+ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
-+ .endif
-+ subs N, N, #32
-+ bhs 120b
-+ tst N, #16
-+ .if align == 0
-+ .if backwards
-+ ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
-+ stmnedb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldmneia S!, {DAT0, DAT1, DAT2, LAST}
-+ stmneia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+ .else
-+ beq 130f
-+ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST
-+130:
-+ .endif
-+ /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ .if align != 0
-+ add S, S, #align
-+ .endif
-+ memcpy_trailing_15bytes backwards, align
-+199:
-+ pop {DAT3, DAT4, DAT5, DAT6, DAT7}
-+ pop {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy_medium_inner_loop backwards, align
-+120:
-+ .if backwards
-+ .if align == 0
-+ ldmdb S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldr LAST, [S, #-4]!
-+ ldr DAT2, [S, #-4]!
-+ ldr DAT1, [S, #-4]!
-+ ldr DAT0, [S, #-4]!
-+ .endif
-+ stmdb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ .if align == 0
-+ ldmia S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldr DAT0, [S], #4
-+ ldr DAT1, [S], #4
-+ ldr DAT2, [S], #4
-+ ldr LAST, [S], #4
-+ .endif
-+ stmia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+ subs N, N, #16
-+ bhs 120b
-+ /* Trailing words and bytes */
-+ tst N, #15
-+ beq 199f
-+ memcpy_trailing_15bytes backwards, align
-+199:
-+ pop {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy_short_inner_loop backwards, align
-+ tst N, #16
-+ .if backwards
-+ .if align == 0
-+ ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldrne LAST, [S, #-4]!
-+ ldrne DAT2, [S, #-4]!
-+ ldrne DAT1, [S, #-4]!
-+ ldrne DAT0, [S, #-4]!
-+ .endif
-+ stmnedb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ .if align == 0
-+ ldmneia S!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+ ldrne DAT0, [S], #4
-+ ldrne DAT1, [S], #4
-+ ldrne DAT2, [S], #4
-+ ldrne LAST, [S], #4
-+ .endif
-+ stmneia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+ memcpy_trailing_15bytes backwards, align
-+199:
-+ pop {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy backwards
-+ D .req a1
-+ S .req a2
-+ N .req a3
-+ DAT0 .req a4
-+ DAT1 .req v1
-+ DAT2 .req v2
-+ DAT3 .req v3
-+ DAT4 .req v4
-+ DAT5 .req v5
-+ DAT6 .req v6
-+ DAT7 .req sl
-+ LAST .req ip
-+ OFF .req lr
-+
-+ .cfi_startproc
-+
-+ push {D, DAT1, DAT2, lr}
-+
-+ .cfi_def_cfa_offset 16
-+ .cfi_rel_offset D, 0
-+ .cfi_undefined S
-+ .cfi_undefined N
-+ .cfi_undefined DAT0
-+ .cfi_rel_offset DAT1, 4
-+ .cfi_rel_offset DAT2, 8
-+ .cfi_undefined LAST
-+ .cfi_rel_offset lr, 12
-+
-+ .if backwards
-+ add D, D, N
-+ add S, S, N
-+ .endif
-+
-+ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
-+ cmp N, #31
-+ blo 170f
-+ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
-+ cmp N, #(prefetch_distance+3)*32 - 1
-+ blo 160f
-+
-+ /* Long case */
-+ push {DAT3, DAT4, DAT5, DAT6, DAT7}
-+
-+ .cfi_def_cfa_offset 36
-+ .cfi_rel_offset D, 20
-+ .cfi_rel_offset DAT1, 24
-+ .cfi_rel_offset DAT2, 28
-+ .cfi_rel_offset DAT3, 0
-+ .cfi_rel_offset DAT4, 4
-+ .cfi_rel_offset DAT5, 8
-+ .cfi_rel_offset DAT6, 12
-+ .cfi_rel_offset DAT7, 16
-+ .cfi_rel_offset lr, 32
-+
-+ /* Adjust N so that the decrement instruction can also test for
-+ * inner loop termination. We want it to stop when there are
-+ * (prefetch_distance+1) complete blocks to go. */
-+ sub N, N, #(prefetch_distance+2)*32
-+ preload_leading_step1 backwards, DAT0, S
-+ .if backwards
-+ /* Bug in GAS: it accepts, but mis-assembles the instruction
-+ * ands DAT2, D, #60, 2
-+ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow)
-+ */
-+ .word 0xE210513C
-+ beq 154f
-+ .else
-+ ands DAT2, D, #15
-+ beq 154f
-+ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */
-+ .endif
-+ preload_leading_step2 backwards, DAT0, S, DAT2, OFF
-+ memcpy_leading_15bytes backwards, 1
-+154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */
-+ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */
-+ .if backwards
-+ rsb OFF, S, #3
-+ and OFF, OFF, #28
-+ sub OFF, OFF, #32*(prefetch_distance+1)
-+ .else
-+ and OFF, S, #28
-+ rsb OFF, OFF, #32*prefetch_distance
-+ .endif
-+ movs DAT0, S, lsl #31
-+ bhi 157f
-+ bcs 156f
-+ bmi 155f
-+ memcpy_long_inner_loop backwards, 0
-+155: memcpy_long_inner_loop backwards, 1
-+156: memcpy_long_inner_loop backwards, 2
-+157: memcpy_long_inner_loop backwards, 3
-+
-+ .cfi_def_cfa_offset 16
-+ .cfi_rel_offset D, 0
-+ .cfi_rel_offset DAT1, 4
-+ .cfi_rel_offset DAT2, 8
-+ .cfi_same_value DAT3
-+ .cfi_same_value DAT4
-+ .cfi_same_value DAT5
-+ .cfi_same_value DAT6
-+ .cfi_same_value DAT7
-+ .cfi_rel_offset lr, 12
-+
-+160: /* Medium case */
-+ preload_all backwards, 0, 0, S, N, DAT2, OFF
-+ sub N, N, #16 /* simplifies inner loop termination */
-+ .if backwards
-+ ands DAT2, D, #15
-+ beq 164f
-+ .else
-+ ands DAT2, D, #15
-+ beq 164f
-+ rsb DAT2, DAT2, #16
-+ .endif
-+ memcpy_leading_15bytes backwards, align
-+164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */
-+ tst S, #3
-+ bne 140f
-+ memcpy_medium_inner_loop backwards, 0
-+140: memcpy_medium_inner_loop backwards, 1
-+
-+170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */
-+ teq N, #0
-+ beq 199f
-+ preload_all backwards, 1, 0, S, N, DAT2, LAST
-+ tst D, #3
-+ beq 174f
-+172: subs N, N, #1
-+ blo 199f
-+ .if backwards
-+ ldrb DAT0, [S, #-1]!
-+ strb DAT0, [D, #-1]!
-+ .else
-+ ldrb DAT0, [S], #1
-+ strb DAT0, [D], #1
-+ .endif
-+ tst D, #3
-+ bne 172b
-+174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */
-+ tst S, #3
-+ bne 140f
-+ memcpy_short_inner_loop backwards, 0
-+140: memcpy_short_inner_loop backwards, 1
-+
-+ .cfi_endproc
-+
-+ .unreq D
-+ .unreq S
-+ .unreq N
-+ .unreq DAT0
-+ .unreq DAT1
-+ .unreq DAT2
-+ .unreq DAT3
-+ .unreq DAT4
-+ .unreq DAT5
-+ .unreq DAT6
-+ .unreq DAT7
-+ .unreq LAST
-+ .unreq OFF
-+.endm
-diff -Nur linux-3.18.14/arch/arm/lib/memcpy_rpi.S linux-rpi/arch/arm/lib/memcpy_rpi.S
---- linux-3.18.14/arch/arm/lib/memcpy_rpi.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/memcpy_rpi.S 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,59 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+#include "memcpymove.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+/*
-+ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to destination
-+ * a2 = pointer to source
-+ * a3 = number of bytes to copy
-+ * On exit:
-+ * a1 preserved
-+ */
-+
-+.set prefetch_distance, 3
-+
-+ENTRY(memcpy)
-+ memcpy 0
-+ENDPROC(memcpy)
-diff -Nur linux-3.18.14/arch/arm/lib/memmove_rpi.S linux-rpi/arch/arm/lib/memmove_rpi.S
---- linux-3.18.14/arch/arm/lib/memmove_rpi.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/memmove_rpi.S 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,61 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+#include "memcpymove.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+/*
-+ * void *memmove(void *s1, const void *s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to destination
-+ * a2 = pointer to source
-+ * a3 = number of bytes to copy
-+ * On exit:
-+ * a1 preserved
-+ */
-+
-+.set prefetch_distance, 3
-+
-+ENTRY(memmove)
-+ cmp a2, a1
-+ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */
-+ memcpy 1
-+ENDPROC(memmove)
-diff -Nur linux-3.18.14/arch/arm/lib/memset_rpi.S linux-rpi/arch/arm/lib/memset_rpi.S
---- linux-3.18.14/arch/arm/lib/memset_rpi.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/lib/memset_rpi.S 2015-05-31 14:46:08.177661005 -0500
-@@ -0,0 +1,121 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+ * Redistributions of source code must retain the above copyright
-+ notice, this list of conditions and the following disclaimer.
-+ * Redistributions in binary form must reproduce the above copyright
-+ notice, this list of conditions and the following disclaimer in the
-+ documentation and/or other materials provided with the distribution.
-+ * Neither the name of the copyright holder nor the
-+ names of its contributors may be used to endorse or promote products
-+ derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+ .text
-+ .arch armv6
-+ .object_arch armv4
-+ .arm
-+ .altmacro
-+ .p2align 2
-+
-+/*
-+ * void *memset(void *s, int c, size_t n);
-+ * On entry:
-+ * a1 = pointer to buffer to fill
-+ * a2 = byte pattern to fill with (caller-narrowed)
-+ * a3 = number of bytes to fill
-+ * On exit:
-+ * a1 preserved
-+ */
-+ENTRY(memset)
-+ S .req a1
-+ DAT0 .req a2
-+ N .req a3
-+ DAT1 .req a4
-+ DAT2 .req ip
-+ DAT3 .req lr
-+
-+ orr DAT0, DAT0, lsl #8
-+ push {S, lr}
-+ orr DAT0, DAT0, lsl #16
-+ mov DAT1, DAT0
-+
-+ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
-+ cmp N, #31
-+ blo 170f
-+
-+161: sub N, N, #16 /* simplifies inner loop termination */
-+ /* Leading words and bytes */
-+ tst S, #15
-+ beq 164f
-+ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */
-+ movs DAT2, DAT3, lsl #31
-+ submi N, N, #1
-+ strmib DAT0, [S], #1
-+ subcs N, N, #2
-+ strcsh DAT0, [S], #2
-+ movs DAT2, DAT3, lsl #29
-+ submi N, N, #4
-+ strmi DAT0, [S], #4
-+ subcs N, N, #8
-+ stmcsia S!, {DAT0, DAT1}
-+164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */
-+ mov DAT2, DAT0
-+ mov DAT3, DAT0
-+ /* Now the inner loop of 16-byte stores */
-+165: stmia S!, {DAT0, DAT1, DAT2, DAT3}
-+ subs N, N, #16
-+ bhs 165b
-+166: /* Trailing words and bytes */
-+ movs N, N, lsl #29
-+ stmcsia S!, {DAT0, DAT1}
-+ strmi DAT0, [S], #4
-+ movs N, N, lsl #2
-+ strcsh DAT0, [S], #2
-+ strmib DAT0, [S]
-+199: pop {S, pc}
-+
-+170: /* Short case */
-+ mov DAT2, DAT0
-+ mov DAT3, DAT0
-+ tst S, #3
-+ beq 174f
-+172: subs N, N, #1
-+ blo 199b
-+ strb DAT0, [S], #1
-+ tst S, #3
-+ bne 172b
-+174: tst N, #16
-+ stmneia S!, {DAT0, DAT1, DAT2, DAT3}
-+ b 166b
-+
-+ .unreq S
-+ .unreq DAT0
-+ .unreq N
-+ .unreq DAT1
-+ .unreq DAT2
-+ .unreq DAT3
-+ENDPROC(memset)
-diff -Nur linux-3.18.14/arch/arm/lib/uaccess_with_memcpy.c linux-rpi/arch/arm/lib/uaccess_with_memcpy.c
---- linux-3.18.14/arch/arm/lib/uaccess_with_memcpy.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/lib/uaccess_with_memcpy.c 2015-05-31 14:46:08.177661005 -0500
-@@ -22,6 +22,14 @@
- #include <asm/current.h>
- #include <asm/page.h>
-
-+#ifndef COPY_FROM_USER_THRESHOLD
-+#define COPY_FROM_USER_THRESHOLD 64
-+#endif
-+
-+#ifndef COPY_TO_USER_THRESHOLD
-+#define COPY_TO_USER_THRESHOLD 64
-+#endif
-+
- static int
- pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
- {
-@@ -85,7 +93,44 @@
- return 1;
- }
-
--static unsigned long noinline
-+static int
-+pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
-+{
-+ unsigned long addr = (unsigned long)_addr;
-+ pgd_t *pgd;
-+ pmd_t *pmd;
-+ pte_t *pte;
-+ pud_t *pud;
-+ spinlock_t *ptl;
-+
-+ pgd = pgd_offset(current->mm, addr);
-+ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))
-+ {
-+ return 0;
-+ }
-+ pud = pud_offset(pgd, addr);
-+ if (unlikely(pud_none(*pud) || pud_bad(*pud)))
-+ {
-+ return 0;
-+ }
-+
-+ pmd = pmd_offset(pud, addr);
-+ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))
-+ return 0;
-+
-+ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl);
-+ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) {
-+ pte_unmap_unlock(pte, ptl);
-+ return 0;
-+ }
-+
-+ *ptep = pte;
-+ *ptlp = ptl;
-+
-+ return 1;
-+}
-+
-+unsigned long noinline
- __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)
- {
- int atomic;
-@@ -135,6 +180,54 @@
- return n;
- }
-
-+unsigned long noinline
-+__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n)
-+{
-+ int atomic;
-+
-+ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) {
-+ memcpy(to, (const void *)from, n);
-+ return 0;
-+ }
-+
-+ /* the mmap semaphore is taken only if not in an atomic context */
-+ atomic = in_atomic();
-+
-+ if (!atomic)
-+ down_read(&current->mm->mmap_sem);
-+ while (n) {
-+ pte_t *pte;
-+ spinlock_t *ptl;
-+ int tocopy;
-+
-+ while (!pin_page_for_read(from, &pte, &ptl)) {
-+ char temp;
-+ if (!atomic)
-+ up_read(&current->mm->mmap_sem);
-+ if (__get_user(temp, (char __user *)from))
-+ goto out;
-+ if (!atomic)
-+ down_read(&current->mm->mmap_sem);
-+ }
-+
-+ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1;
-+ if (tocopy > n)
-+ tocopy = n;
-+
-+ memcpy(to, (const void *)from, tocopy);
-+ to += tocopy;
-+ from += tocopy;
-+ n -= tocopy;
-+
-+ pte_unmap_unlock(pte, ptl);
-+ }
-+ if (!atomic)
-+ up_read(&current->mm->mmap_sem);
-+
-+out:
-+ return n;
-+}
-+
- unsigned long
- __copy_to_user(void __user *to, const void *from, unsigned long n)
- {
-@@ -145,10 +238,25 @@
- * With frame pointer disabled, tail call optimization kicks in
- * as well making this test almost invisible.
- */
-- if (n < 64)
-+ if (n < COPY_TO_USER_THRESHOLD)
- return __copy_to_user_std(to, from, n);
- return __copy_to_user_memcpy(to, from, n);
- }
-+
-+unsigned long
-+__copy_from_user(void *to, const void __user *from, unsigned long n)
-+{
-+ /*
-+ * This test is stubbed out of the main function above to keep
-+ * the overhead for small copies low by avoiding a large
-+ * register dump on the stack just to reload them right away.
-+ * With frame pointer disabled, tail call optimization kicks in
-+ * as well making this test almost invisible.
-+ */
-+ if (n < COPY_FROM_USER_THRESHOLD)
-+ return __copy_from_user_std(to, from, n);
-+ return __copy_from_user_memcpy(to, from, n);
-+}
-
- static unsigned long noinline
- __clear_user_memset(void __user *addr, unsigned long n)
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/armctrl.c linux-rpi/arch/arm/mach-bcm2708/armctrl.c
---- linux-3.18.14/arch/arm/mach-bcm2708/armctrl.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/armctrl.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,315 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/armctrl.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/init.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/version.h>
-+#include <linux/syscore_ops.h>
-+#include <linux/interrupt.h>
-+#include <linux/irqdomain.h>
-+#include <linux/of.h>
-+
-+#include <asm/mach/irq.h>
-+#include <mach/hardware.h>
-+#include "armctrl.h"
-+
-+/* For support of kernels >= 3.0 assume only one VIC for now*/
-+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
-+ INTERRUPT_VC_JPEG,
-+ INTERRUPT_VC_USB,
-+ INTERRUPT_VC_3D,
-+ INTERRUPT_VC_DMA2,
-+ INTERRUPT_VC_DMA3,
-+ INTERRUPT_VC_I2C,
-+ INTERRUPT_VC_SPI,
-+ INTERRUPT_VC_I2SPCM,
-+ INTERRUPT_VC_SDIO,
-+ INTERRUPT_VC_UART,
-+ INTERRUPT_VC_ARASANSDIO
-+};
-+
-+static void armctrl_mask_irq(struct irq_data *d)
-+{
-+ static const unsigned int disables[4] = {
-+ ARM_IRQ_DIBL1,
-+ ARM_IRQ_DIBL2,
-+ ARM_IRQ_DIBL3,
-+ 0
-+ };
-+
-+ if (d->irq >= FIQ_START) {
-+ writel(0, __io_address(ARM_IRQ_FAST));
-+ } else {
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
-+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
-+ }
-+}
-+
-+static void armctrl_unmask_irq(struct irq_data *d)
-+{
-+ static const unsigned int enables[4] = {
-+ ARM_IRQ_ENBL1,
-+ ARM_IRQ_ENBL2,
-+ ARM_IRQ_ENBL3,
-+ 0
-+ };
-+
-+ if (d->irq >= FIQ_START) {
-+ unsigned int data =
-+ (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
-+ writel(0x80 | data, __io_address(ARM_IRQ_FAST));
-+ } else {
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
-+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
-+ }
-+}
-+
-+#ifdef CONFIG_OF
-+
-+#define NR_IRQS_BANK0 21
-+#define NR_BANKS 3
-+#define IRQS_PER_BANK 32
-+
-+/* from drivers/irqchip/irq-bcm2835.c */
-+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
-+ const u32 *intspec, unsigned int intsize,
-+ unsigned long *out_hwirq, unsigned int *out_type)
-+{
-+ if (WARN_ON(intsize != 2))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[0] >= NR_BANKS))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
-+ return -EINVAL;
-+
-+ if (intspec[0] == 0)
-+ *out_hwirq = ARM_IRQ0_BASE + intspec[1];
-+ else if (intspec[0] == 1)
-+ *out_hwirq = ARM_IRQ1_BASE + intspec[1];
-+ else
-+ *out_hwirq = ARM_IRQ2_BASE + intspec[1];
-+
-+ /* reverse remap_irqs[] */
-+ switch (*out_hwirq) {
-+ case INTERRUPT_VC_JPEG:
-+ *out_hwirq = INTERRUPT_JPEG;
-+ break;
-+ case INTERRUPT_VC_USB:
-+ *out_hwirq = INTERRUPT_USB;
-+ break;
-+ case INTERRUPT_VC_3D:
-+ *out_hwirq = INTERRUPT_3D;
-+ break;
-+ case INTERRUPT_VC_DMA2:
-+ *out_hwirq = INTERRUPT_DMA2;
-+ break;
-+ case INTERRUPT_VC_DMA3:
-+ *out_hwirq = INTERRUPT_DMA3;
-+ break;
-+ case INTERRUPT_VC_I2C:
-+ *out_hwirq = INTERRUPT_I2C;
-+ break;
-+ case INTERRUPT_VC_SPI:
-+ *out_hwirq = INTERRUPT_SPI;
-+ break;
-+ case INTERRUPT_VC_I2SPCM:
-+ *out_hwirq = INTERRUPT_I2SPCM;
-+ break;
-+ case INTERRUPT_VC_SDIO:
-+ *out_hwirq = INTERRUPT_SDIO;
-+ break;
-+ case INTERRUPT_VC_UART:
-+ *out_hwirq = INTERRUPT_UART;
-+ break;
-+ case INTERRUPT_VC_ARASANSDIO:
-+ *out_hwirq = INTERRUPT_ARASANSDIO;
-+ break;
-+ }
-+
-+ *out_type = IRQ_TYPE_NONE;
-+ return 0;
-+}
-+
-+static struct irq_domain_ops armctrl_ops = {
-+ .xlate = armctrl_xlate
-+};
-+
-+void __init armctrl_dt_init(void)
-+{
-+ struct device_node *np;
-+ struct irq_domain *domain;
-+
-+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
-+ if (!np)
-+ return;
-+
-+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
-+ IRQ_ARMCTRL_START, 0,
-+ &armctrl_ops, NULL);
-+ WARN_ON(!domain);
-+}
-+#else
-+void __init armctrl_dt_init(void) { }
-+#endif /* CONFIG_OF */
-+
-+#if defined(CONFIG_PM)
-+
-+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
-+
-+/* Static defines
-+ * struct armctrl_device - VIC PM device (< 3.xx)
-+ * @sysdev: The system device which is registered. (< 3.xx)
-+ * @irq: The IRQ number for the base of the VIC.
-+ * @base: The register base for the VIC.
-+ * @resume_sources: A bitmask of interrupts for resume.
-+ * @resume_irqs: The IRQs enabled for resume.
-+ * @int_select: Save for VIC_INT_SELECT.
-+ * @int_enable: Save for VIC_INT_ENABLE.
-+ * @soft_int: Save for VIC_INT_SOFT.
-+ * @protect: Save for VIC_PROTECT.
-+ */
-+struct armctrl_info {
-+ void __iomem *base;
-+ int irq;
-+ u32 resume_sources;
-+ u32 resume_irqs;
-+ u32 int_select;
-+ u32 int_enable;
-+ u32 soft_int;
-+ u32 protect;
-+} armctrl;
-+
-+static int armctrl_suspend(void)
-+{
-+ return 0;
-+}
-+
-+static void armctrl_resume(void)
-+{
-+ return;
-+}
-+
-+/**
-+ * armctrl_pm_register - Register a VIC for later power management control
-+ * @base: The base address of the VIC.
-+ * @irq: The base IRQ for the VIC.
-+ * @resume_sources: bitmask of interrupts allowed for resume sources.
-+ *
-+ * For older kernels (< 3.xx) do -
-+ * Register the VIC with the system device tree so that it can be notified
-+ * of suspend and resume requests and ensure that the correct actions are
-+ * taken to re-instate the settings on resume.
-+ */
-+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
-+ u32 resume_sources)
-+{
-+ armctrl.base = base;
-+ armctrl.resume_sources = resume_sources;
-+ armctrl.irq = irq;
-+}
-+
-+static int armctrl_set_wake(struct irq_data *d, unsigned int on)
-+{
-+ unsigned int off = d->irq & 31;
-+ u32 bit = 1 << off;
-+
-+ if (!(bit & armctrl.resume_sources))
-+ return -EINVAL;
-+
-+ if (on)
-+ armctrl.resume_irqs |= bit;
-+ else
-+ armctrl.resume_irqs &= ~bit;
-+
-+ return 0;
-+}
-+
-+#else
-+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
-+ u32 arg1)
-+{
-+}
-+
-+#define armctrl_suspend NULL
-+#define armctrl_resume NULL
-+#define armctrl_set_wake NULL
-+#endif /* CONFIG_PM */
-+
-+static struct syscore_ops armctrl_syscore_ops = {
-+ .suspend = armctrl_suspend,
-+ .resume = armctrl_resume,
-+};
-+
-+/**
-+ * armctrl_syscore_init - initicall to register VIC pm functions
-+ *
-+ * This is called via late_initcall() to register
-+ * the resources for the VICs due to the early
-+ * nature of the VIC's registration.
-+*/
-+static int __init armctrl_syscore_init(void)
-+{
-+ register_syscore_ops(&armctrl_syscore_ops);
-+ return 0;
-+}
-+
-+late_initcall(armctrl_syscore_init);
-+
-+static struct irq_chip armctrl_chip = {
-+ .name = "ARMCTRL",
-+ .irq_ack = NULL,
-+ .irq_mask = armctrl_mask_irq,
-+ .irq_unmask = armctrl_unmask_irq,
-+ .irq_set_wake = armctrl_set_wake,
-+};
-+
-+/**
-+ * armctrl_init - initialise a vectored interrupt controller
-+ * @base: iomem base address
-+ * @irq_start: starting interrupt number, must be muliple of 32
-+ * @armctrl_sources: bitmask of interrupt sources to allow
-+ * @resume_sources: bitmask of interrupt sources to allow for resume
-+ */
-+int __init armctrl_init(void __iomem * base, unsigned int irq_start,
-+ u32 armctrl_sources, u32 resume_sources)
-+{
-+ unsigned int irq;
-+
-+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
-+ unsigned int data = irq;
-+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
-+ data = remap_irqs[irq - INTERRUPT_JPEG];
-+
-+ irq_set_chip(irq, &armctrl_chip);
-+ irq_set_chip_data(irq, (void *)data);
-+ irq_set_handler(irq, handle_level_irq);
-+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
-+ }
-+
-+ armctrl_pm_register(base, irq_start, resume_sources);
-+ init_FIQ(FIQ_START);
-+ armctrl_dt_init();
-+ return 0;
-+}
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/armctrl.h linux-rpi/arch/arm/mach-bcm2708/armctrl.h
---- linux-3.18.14/arch/arm/mach-bcm2708/armctrl.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/armctrl.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,27 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/armctrl.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_ARMCTRL_H
-+#define __BCM2708_ARMCTRL_H
-+
-+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
-+ u32 armctrl_sources, u32 resume_sources);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/bcm2708.c linux-rpi/arch/arm/mach-bcm2708/bcm2708.c
---- linux-3.18.14/arch/arm/mach-bcm2708/bcm2708.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,1133 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/serial_8250.h>
-+#include <linux/platform_device.h>
-+#include <linux/syscore_ops.h>
-+#include <linux/interrupt.h>
-+#include <linux/amba/bus.h>
-+#include <linux/amba/clcd.h>
-+#include <linux/clk-provider.h>
-+#include <linux/clkdev.h>
-+#include <linux/clockchips.h>
-+#include <linux/cnt32_to_63.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/spi/spi.h>
-+#include <linux/gpio/machine.h>
-+#include <linux/w1-gpio.h>
-+#include <linux/pps-gpio.h>
-+
-+#include <linux/version.h>
-+#include <linux/clkdev.h>
-+#include <asm/system_info.h>
-+#include <mach/hardware.h>
-+#include <asm/irq.h>
-+#include <linux/leds.h>
-+#include <asm/mach-types.h>
-+#include <linux/sched_clock.h>
-+
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+#include <asm/mach/irq.h>
-+#include <asm/mach/time.h>
-+#include <asm/mach/map.h>
-+
-+#include <mach/timex.h>
-+#include <mach/dma.h>
-+#include <mach/vcio.h>
-+#include <mach/system.h>
-+
-+#include <linux/delay.h>
-+
-+#include "bcm2708.h"
-+#include "armctrl.h"
-+
-+#ifdef CONFIG_BCM_VC_CMA
-+#include <linux/broadcom/vc_cma.h>
-+#endif
-+
-+
-+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
-+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
-+ * represent this window by setting our dmamasks to 26 bits but, in fact
-+ * we're not going to use addresses outside this range (they're not in real
-+ * memory) so we don't bother.
-+ *
-+ * In the future we might include code to use this IOMMU to remap other
-+ * physical addresses onto VideoCore memory then the use of 32-bits would be
-+ * more legitimate.
-+ */
-+#define DMA_MASK_BITS_COMMON 32
-+
-+// use GPIO 4 for the one-wire GPIO pin, if enabled
-+#define W1_GPIO 4
-+// ensure one-wire GPIO pullup is disabled by default
-+#define W1_PULLUP -1
-+
-+/* command line parameters */
-+static unsigned boardrev, serial;
-+static unsigned uart_clock = UART0_CLOCK;
-+static unsigned disk_led_gpio = 16;
-+static unsigned disk_led_active_low = 1;
-+static unsigned reboot_part = 0;
-+static unsigned w1_gpio_pin = W1_GPIO;
-+static unsigned w1_gpio_pullup = W1_PULLUP;
-+static int pps_gpio_pin = -1;
-+static bool vc_i2c_override = false;
-+
-+static unsigned use_dt = 0;
-+
-+static void __init bcm2708_init_led(void);
-+
-+void __init bcm2708_init_irq(void)
-+{
-+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
-+}
-+
-+static struct map_desc bcm2708_io_desc[] __initdata = {
-+ {
-+ .virtual = IO_ADDRESS(ARMCTRL_BASE),
-+ .pfn = __phys_to_pfn(ARMCTRL_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(UART0_BASE),
-+ .pfn = __phys_to_pfn(UART0_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(UART1_BASE),
-+ .pfn = __phys_to_pfn(UART1_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(DMA_BASE),
-+ .pfn = __phys_to_pfn(DMA_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(MCORE_BASE),
-+ .pfn = __phys_to_pfn(MCORE_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(ST_BASE),
-+ .pfn = __phys_to_pfn(ST_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(USB_BASE),
-+ .pfn = __phys_to_pfn(USB_BASE),
-+ .length = SZ_128K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(PM_BASE),
-+ .pfn = __phys_to_pfn(PM_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(GPIO_BASE),
-+ .pfn = __phys_to_pfn(GPIO_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE}
-+};
-+
-+void __init bcm2708_map_io(void)
-+{
-+ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
-+}
-+
-+/* The STC is a free running counter that increments at the rate of 1MHz */
-+#define STC_FREQ_HZ 1000000
-+
-+static inline uint32_t timer_read(void)
-+{
-+ /* STC: a free running counter that increments at the rate of 1MHz */
-+ return readl(__io_address(ST_BASE + 0x04));
-+}
-+
-+static unsigned long bcm2708_read_current_timer(void)
-+{
-+ return timer_read();
-+}
-+
-+static u64 notrace bcm2708_read_sched_clock(void)
-+{
-+ return timer_read();
-+}
-+
-+static cycle_t clksrc_read(struct clocksource *cs)
-+{
-+ return timer_read();
-+}
-+
-+static struct clocksource clocksource_stc = {
-+ .name = "stc",
-+ .rating = 300,
-+ .read = clksrc_read,
-+ .mask = CLOCKSOURCE_MASK(32),
-+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+unsigned long frc_clock_ticks32(void)
-+{
-+ return timer_read();
-+}
-+
-+static void __init bcm2708_clocksource_init(void)
-+{
-+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
-+ printk(KERN_ERR "timer: failed to initialize clock "
-+ "source %s\n", clocksource_stc.name);
-+ }
-+}
-+
-+struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate)
-+{
-+ struct clk *clk;
-+
-+ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
-+ fixed_rate);
-+ if (IS_ERR(clk))
-+ pr_err("%s not registered\n", name);
-+
-+ return clk;
-+}
-+
-+void __init bcm2708_register_clkdev(struct clk *clk, const char *name)
-+{
-+ int ret;
-+
-+ ret = clk_register_clkdev(clk, NULL, name);
-+ if (ret)
-+ pr_err("%s alias not registered\n", name);
-+}
-+
-+void __init bcm2708_init_clocks(void)
-+{
-+ struct clk *clk;
-+
-+ clk = bcm2708_clk_register("uart0_clk", uart_clock);
-+ bcm2708_register_clkdev(clk, "dev:f1");
-+
-+ clk = bcm2708_clk_register("sdhost_clk", 250000000);
-+ bcm2708_register_clkdev(clk, "mmc-bcm2835.0");
-+ bcm2708_register_clkdev(clk, "bcm2708_spi.0");
-+ bcm2708_register_clkdev(clk, "bcm2708_i2c.0");
-+ bcm2708_register_clkdev(clk, "bcm2708_i2c.1");
-+}
-+
-+#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
-+#define UART0_DMA { 15, 14 }
-+
-+AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
-+
-+static struct amba_device *amba_devs[] __initdata = {
-+ &uart0_device,
-+};
-+
-+static struct resource bcm2708_dmaman_resources[] = {
-+ {
-+ .start = DMA_BASE,
-+ .end = DMA_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct platform_device bcm2708_dmaman_device = {
-+ .name = BCM_DMAMAN_DRIVER_NAME,
-+ .id = 0, /* first bcm2708_dma */
-+ .resource = bcm2708_dmaman_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
-+};
-+
-+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-+static struct w1_gpio_platform_data w1_gpio_pdata = {
-+ .pin = W1_GPIO,
-+ .ext_pullup_enable_pin = W1_PULLUP,
-+ .is_open_drain = 0,
-+};
-+
-+static struct platform_device w1_device = {
-+ .name = "w1-gpio",
-+ .id = -1,
-+ .dev.platform_data = &w1_gpio_pdata,
-+};
-+#endif
-+
-+static struct pps_gpio_platform_data pps_gpio_info = {
-+ .assert_falling_edge = false,
-+ .capture_clear = false,
-+ .gpio_pin = -1,
-+ .gpio_label = "PPS",
-+};
-+
-+static struct platform_device pps_gpio_device = {
-+ .name = "pps-gpio",
-+ .id = PLATFORM_DEVID_NONE,
-+ .dev.platform_data = &pps_gpio_info,
-+};
-+
-+static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_fb_device = {
-+ .name = "bcm2708_fb",
-+ .id = -1, /* only one bcm2708_fb */
-+ .resource = NULL,
-+ .num_resources = 0,
-+ .dev = {
-+ .dma_mask = &fb_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
-+ {
-+ .mapbase = UART1_BASE + 0x40,
-+ .irq = IRQ_AUX,
-+ .uartclk = 125000000,
-+ .regshift = 2,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
-+ .type = PORT_8250,
-+ },
-+ {},
-+};
-+
-+static struct platform_device bcm2708_uart1_device = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = bcm2708_uart1_platform_data,
-+ },
-+};
-+
-+static struct resource bcm2708_usb_resources[] = {
-+ [0] = {
-+ .start = USB_BASE,
-+ .end = USB_BASE + SZ_128K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = MPHI_BASE,
-+ .end = MPHI_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [2] = {
-+ .start = IRQ_HOSTPORT,
-+ .end = IRQ_HOSTPORT,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ [3] = {
-+ .start = IRQ_USB,
-+ .end = IRQ_USB,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+
-+static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_usb_device = {
-+ .name = "bcm2708_usb",
-+ .id = -1, /* only one bcm2708_usb */
-+ .resource = bcm2708_usb_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
-+ .dev = {
-+ .dma_mask = &usb_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+static struct resource bcm2708_vcio_resources[] = {
-+ [0] = { /* mailbox/semaphore/doorbell access */
-+ .start = MCORE_BASE,
-+ .end = MCORE_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_vcio_device = {
-+ .name = BCM_VCIO_DRIVER_NAME,
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_vcio_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
-+ .dev = {
-+ .dma_mask = &vcio_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+#ifdef CONFIG_BCM2708_GPIO
-+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
-+
-+static struct resource bcm2708_gpio_resources[] = {
-+ [0] = { /* general purpose I/O */
-+ .start = GPIO_BASE,
-+ .end = GPIO_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_gpio_device = {
-+ .name = BCM_GPIO_DRIVER_NAME,
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_gpio_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
-+ .dev = {
-+ .dma_mask = &gpio_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+#endif
-+
-+static struct resource bcm2708_systemtimer_resources[] = {
-+ [0] = { /* system timer access */
-+ .start = ST_BASE,
-+ .end = ST_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_TIMER3,
-+ .end = IRQ_TIMER3,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+
-+};
-+
-+static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_systemtimer_device = {
-+ .name = "bcm2708_systemtimer",
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_systemtimer_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
-+ .dev = {
-+ .dma_mask = &systemtimer_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
-+static struct resource bcm2835_emmc_resources[] = {
-+ [0] = {
-+ .start = EMMC_BASE,
-+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
-+ /* the memory map actually makes SZ_4K available */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_ARASANSDIO,
-+ .end = IRQ_ARASANSDIO,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
-+
-+struct platform_device bcm2835_emmc_device = {
-+ .name = "mmc-bcm2835",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
-+ .resource = bcm2835_emmc_resources,
-+ .dev = {
-+ .dma_mask = &bcm2835_emmc_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+#endif /* CONFIG_MMC_BCM2835 */
-+
-+static struct resource bcm2708_powerman_resources[] = {
-+ [0] = {
-+ .start = PM_BASE,
-+ .end = PM_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+struct platform_device bcm2708_powerman_device = {
-+ .name = "bcm2708_powerman",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
-+ .resource = bcm2708_powerman_resources,
-+ .dev = {
-+ .dma_mask = &powerman_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+
-+
-+static struct platform_device bcm2708_alsa_devices[] = {
-+ [0] = {
-+ .name = "bcm2835_AUD0",
-+ .id = 0, /* first audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [1] = {
-+ .name = "bcm2835_AUD1",
-+ .id = 1, /* second audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [2] = {
-+ .name = "bcm2835_AUD2",
-+ .id = 2, /* third audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [3] = {
-+ .name = "bcm2835_AUD3",
-+ .id = 3, /* forth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [4] = {
-+ .name = "bcm2835_AUD4",
-+ .id = 4, /* fifth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [5] = {
-+ .name = "bcm2835_AUD5",
-+ .id = 5, /* sixth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [6] = {
-+ .name = "bcm2835_AUD6",
-+ .id = 6, /* seventh audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [7] = {
-+ .name = "bcm2835_AUD7",
-+ .id = 7, /* eighth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+};
-+
-+static struct resource bcm2708_spi_resources[] = {
-+ {
-+ .start = SPI0_BASE,
-+ .end = SPI0_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = IRQ_SPI,
-+ .end = IRQ_SPI,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+
-+static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+static struct platform_device bcm2708_spi_device = {
-+ .name = "bcm2708_spi",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
-+ .resource = bcm2708_spi_resources,
-+ .dev = {
-+ .dma_mask = &bcm2708_spi_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
-+};
-+
-+#ifdef CONFIG_BCM2708_SPIDEV
-+static struct spi_board_info bcm2708_spi_devices[] = {
-+#ifdef CONFIG_SPI_SPIDEV
-+ {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_0,
-+ }, {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 1,
-+ .mode = SPI_MODE_0,
-+ }
-+#endif
-+};
-+#endif
-+
-+static struct resource bcm2708_bsc0_resources[] = {
-+ {
-+ .start = BSC0_BASE,
-+ .end = BSC0_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = INTERRUPT_I2C,
-+ .end = INTERRUPT_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device bcm2708_bsc0_device = {
-+ .name = "bcm2708_i2c",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
-+ .resource = bcm2708_bsc0_resources,
-+};
-+
-+
-+static struct resource bcm2708_bsc1_resources[] = {
-+ {
-+ .start = BSC1_BASE,
-+ .end = BSC1_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = INTERRUPT_I2C,
-+ .end = INTERRUPT_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device bcm2708_bsc1_device = {
-+ .name = "bcm2708_i2c",
-+ .id = 1,
-+ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
-+ .resource = bcm2708_bsc1_resources,
-+};
-+
-+static struct platform_device bcm2835_hwmon_device = {
-+ .name = "bcm2835_hwmon",
-+};
-+
-+static struct platform_device bcm2835_thermal_device = {
-+ .name = "bcm2835_thermal",
-+};
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
-+static struct resource bcm2708_i2s_resources[] = {
-+ {
-+ .start = I2S_BASE,
-+ .end = I2S_BASE + 0x20,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = PCM_CLOCK_BASE,
-+ .end = PCM_CLOCK_BASE + 0x02,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct platform_device bcm2708_i2s_device = {
-+ .name = "bcm2708-i2s",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
-+ .resource = bcm2708_i2s_resources,
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
-+static struct platform_device snd_hifiberry_dac_device = {
-+ .name = "snd-hifiberry-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct platform_device snd_pcm5102a_codec_device = {
-+ .name = "pcm5102a-codec",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
-+static struct platform_device snd_rpi_hifiberry_dacplus_device = {
-+ .name = "snd-rpi-hifiberry-dacplus",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pcm5122", 0x4d)
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
-+static struct platform_device snd_hifiberry_digi_device = {
-+ .name = "snd-hifiberry-digi",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("wm8804", 0x3b)
-+ },
-+};
-+
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
-+static struct platform_device snd_hifiberry_amp_device = {
-+ .name = "snd-hifiberry-amp",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("tas5713", 0x1b)
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
-+static struct platform_device snd_rpi_dac_device = {
-+ .name = "snd-rpi-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct platform_device snd_pcm1794a_codec_device = {
-+ .name = "pcm1794a-codec",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+#endif
-+
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
-+static struct platform_device snd_rpi_iqaudio_dac_device = {
-+ .name = "snd-rpi-iqaudio-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+// Use the actual device name rather than generic driver name
-+static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pcm5122", 0x4c)
-+ },
-+};
-+#endif
-+
-+int __init bcm_register_device(struct platform_device *pdev)
-+{
-+ int ret;
-+
-+ ret = platform_device_register(pdev);
-+ if (ret)
-+ pr_debug("Unable to register platform device '%s': %d\n",
-+ pdev->name, ret);
-+
-+ return ret;
-+}
-+
-+/*
-+ * Use these macros for platform and i2c devices that are present in the
-+ * Device Tree. This way the devices are only added on non-DT systems.
-+ */
-+#define bcm_register_device_dt(pdev) \
-+ if (!use_dt) bcm_register_device(pdev)
-+
-+#define i2c_register_board_info_dt(busnum, info, n) \
-+ if (!use_dt) i2c_register_board_info(busnum, info, n)
-+
-+int calc_rsts(int partition)
-+{
-+ return PM_PASSWORD |
-+ ((partition & (1 << 0)) << 0) |
-+ ((partition & (1 << 1)) << 1) |
-+ ((partition & (1 << 2)) << 2) |
-+ ((partition & (1 << 3)) << 3) |
-+ ((partition & (1 << 4)) << 4) |
-+ ((partition & (1 << 5)) << 5);
-+}
-+
-+static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
-+{
-+ extern char bcm2708_reboot_mode;
-+ uint32_t pm_rstc, pm_wdog;
-+ uint32_t timeout = 10;
-+ uint32_t pm_rsts = 0;
-+
-+ if(bcm2708_reboot_mode == 'q')
-+ {
-+ // NOOBS < 1.3 booting with reboot=q
-+ pm_rsts = readl(__io_address(PM_RSTS));
-+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
-+ }
-+ else if(bcm2708_reboot_mode == 'p')
-+ {
-+ // NOOBS < 1.3 halting
-+ pm_rsts = readl(__io_address(PM_RSTS));
-+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
-+ }
-+ else
-+ {
-+ pm_rsts = calc_rsts(reboot_part);
-+ }
-+
-+ writel(pm_rsts, __io_address(PM_RSTS));
-+
-+ /* Setup watchdog for reset */
-+ pm_rstc = readl(__io_address(PM_RSTC));
-+
-+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
-+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
-+
-+ writel(pm_wdog, __io_address(PM_WDOG));
-+ writel(pm_rstc, __io_address(PM_RSTC));
-+}
-+
-+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
-+static void bcm2708_power_off(void)
-+{
-+ extern char bcm2708_reboot_mode;
-+ if(bcm2708_reboot_mode == 'q')
-+ {
-+ // NOOBS < v1.3
-+ bcm2708_restart('p', "");
-+ }
-+ else
-+ {
-+ /* partition 63 is special code for HALT the bootloader knows not to boot*/
-+ reboot_part = 63;
-+ /* continue with normal reset mechanism */
-+ bcm2708_restart(0, "");
-+ }
-+}
-+
-+#ifdef CONFIG_OF
-+static void __init bcm2708_dt_init(void)
-+{
-+ int ret;
-+
-+ of_clk_init(NULL);
-+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-+ if (ret) {
-+ pr_err("of_platform_populate failed: %d\n", ret);
-+ /* Proceed as if CONFIG_OF was not defined */
-+ } else {
-+ use_dt = 1;
-+ }
-+}
-+#else
-+static void __init bcm2708_dt_init(void) { }
-+#endif /* CONFIG_OF */
-+
-+void __init bcm2708_init(void)
-+{
-+ int i;
-+
-+#if defined(CONFIG_BCM_VC_CMA)
-+ vc_cma_early_init();
-+#endif
-+ printk("bcm2708.uart_clock = %d\n", uart_clock);
-+ pm_power_off = bcm2708_power_off;
-+
-+ bcm2708_init_clocks();
-+ bcm2708_dt_init();
-+
-+ bcm_register_device(&bcm2708_dmaman_device);
-+ bcm_register_device(&bcm2708_vcio_device);
-+#ifdef CONFIG_BCM2708_GPIO
-+ bcm_register_device_dt(&bcm2708_gpio_device);
-+#endif
-+
-+#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE)
-+ if (!use_dt && (pps_gpio_pin >= 0)) {
-+ pr_info("bcm2708: GPIO %d setup as pps-gpio device\n", pps_gpio_pin);
-+ pps_gpio_info.gpio_pin = pps_gpio_pin;
-+ pps_gpio_device.id = pps_gpio_pin;
-+ bcm_register_device(&pps_gpio_device);
-+ }
-+#endif
-+
-+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-+ w1_gpio_pdata.pin = w1_gpio_pin;
-+ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
-+ bcm_register_device_dt(&w1_device);
-+#endif
-+ bcm_register_device(&bcm2708_systemtimer_device);
-+ bcm_register_device(&bcm2708_fb_device);
-+ bcm_register_device(&bcm2708_usb_device);
-+ bcm_register_device(&bcm2708_uart1_device);
-+ bcm_register_device(&bcm2708_powerman_device);
-+
-+#ifdef CONFIG_MMC_BCM2835
-+ bcm_register_device_dt(&bcm2835_emmc_device);
-+#endif
-+ bcm2708_init_led();
-+ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
-+ bcm_register_device(&bcm2708_alsa_devices[i]);
-+
-+ bcm_register_device(&bcm2835_hwmon_device);
-+ bcm_register_device(&bcm2835_thermal_device);
-+
-+ bcm_register_device_dt(&bcm2708_spi_device);
-+
-+ if (vc_i2c_override) {
-+ bcm_register_device_dt(&bcm2708_bsc0_device);
-+ bcm_register_device_dt(&bcm2708_bsc1_device);
-+ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) {
-+ bcm_register_device_dt(&bcm2708_bsc0_device);
-+ } else {
-+ bcm_register_device_dt(&bcm2708_bsc1_device);
-+ }
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
-+ bcm_register_device_dt(&bcm2708_i2s_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
-+ bcm_register_device_dt(&snd_hifiberry_dac_device);
-+ bcm_register_device_dt(&snd_pcm5102a_codec_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
-+ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device);
-+ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
-+ bcm_register_device_dt(&snd_hifiberry_digi_device);
-+ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
-+ bcm_register_device_dt(&snd_hifiberry_amp_device);
-+ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
-+ bcm_register_device_dt(&snd_rpi_dac_device);
-+ bcm_register_device_dt(&snd_pcm1794a_codec_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
-+ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device);
-+ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
-+#endif
-+
-+
-+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-+ struct amba_device *d = amba_devs[i];
-+ amba_device_register(d, &iomem_resource);
-+ }
-+ system_rev = boardrev;
-+ system_serial_low = serial;
-+
-+#ifdef CONFIG_BCM2708_SPIDEV
-+ if (!use_dt)
-+ spi_register_board_info(bcm2708_spi_devices,
-+ ARRAY_SIZE(bcm2708_spi_devices));
-+#endif
-+}
-+
-+static void timer_set_mode(enum clock_event_mode mode,
-+ struct clock_event_device *clk)
-+{
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ break;
-+ case CLOCK_EVT_MODE_PERIODIC:
-+
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_RESUME:
-+
-+ default:
-+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
-+ (int)mode);
-+ break;
-+ }
-+
-+}
-+
-+static int timer_set_next_event(unsigned long cycles,
-+ struct clock_event_device *unused)
-+{
-+ unsigned long stc;
-+ do {
-+ stc = readl(__io_address(ST_BASE + 0x04));
-+ /* We could take a FIQ here, which may push ST above STC3 */
-+ writel(stc + cycles, __io_address(ST_BASE + 0x18));
-+ } while ((signed long) cycles >= 0 &&
-+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
-+ >= (signed long) cycles);
-+ return 0;
-+}
-+
-+static struct clock_event_device timer0_clockevent = {
-+ .name = "timer0",
-+ .shift = 32,
-+ .features = CLOCK_EVT_FEAT_ONESHOT,
-+ .set_mode = timer_set_mode,
-+ .set_next_event = timer_set_next_event,
-+};
-+
-+/*
-+ * IRQ handler for the timer
-+ */
-+static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *evt = &timer0_clockevent;
-+
-+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
-+
-+ evt->event_handler(evt);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction bcm2708_timer_irq = {
-+ .name = "BCM2708 Timer Tick",
-+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = bcm2708_timer_interrupt,
-+};
-+
-+/*
-+ * Set up timer interrupt, and return the current time in seconds.
-+ */
-+
-+static struct delay_timer bcm2708_delay_timer = {
-+ .read_current_timer = bcm2708_read_current_timer,
-+ .freq = STC_FREQ_HZ,
-+};
-+
-+static void __init bcm2708_timer_init(void)
-+{
-+ /* init high res timer */
-+ bcm2708_clocksource_init();
-+
-+ /*
-+ * Initialise to a known state (all timers off)
-+ */
-+ writel(0, __io_address(ARM_T_CONTROL));
-+ /*
-+ * Make irqs happen for the system timer
-+ */
-+ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
-+
-+ sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
-+
-+ timer0_clockevent.mult =
-+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
-+ timer0_clockevent.max_delta_ns =
-+ clockevent_delta2ns(0xffffffff, &timer0_clockevent);
-+ timer0_clockevent.min_delta_ns =
-+ clockevent_delta2ns(0xf, &timer0_clockevent);
-+
-+ timer0_clockevent.cpumask = cpumask_of(0);
-+ clockevents_register_device(&timer0_clockevent);
-+
-+ register_current_timer_delay(&bcm2708_delay_timer);
-+}
-+
-+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-+#include <linux/leds.h>
-+
-+static struct gpio_led bcm2708_leds[] = {
-+ [0] = {
-+ .gpio = 16,
-+ .name = "led0",
-+ .default_trigger = "mmc0",
-+ .active_low = 1,
-+ },
-+};
-+
-+static struct gpio_led_platform_data bcm2708_led_pdata = {
-+ .num_leds = ARRAY_SIZE(bcm2708_leds),
-+ .leds = bcm2708_leds,
-+};
-+
-+static struct platform_device bcm2708_led_device = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &bcm2708_led_pdata,
-+ },
-+};
-+
-+static void __init bcm2708_init_led(void)
-+{
-+ bcm2708_leds[0].gpio = disk_led_gpio;
-+ bcm2708_leds[0].active_low = disk_led_active_low;
-+ bcm_register_device_dt(&bcm2708_led_device);
-+}
-+#else
-+static inline void bcm2708_init_led(void)
-+{
-+}
-+#endif
-+
-+void __init bcm2708_init_early(void)
-+{
-+ /*
-+ * Some devices allocate their coherent buffers from atomic
-+ * context. Increase size of atomic coherent pool to make sure such
-+ * the allocations won't fail.
-+ */
-+ init_dma_coherent_pool_size(SZ_4M);
-+}
-+
-+static void __init board_reserve(void)
-+{
-+#if defined(CONFIG_BCM_VC_CMA)
-+ vc_cma_reserve();
-+#endif
-+}
-+
-+static const char * const bcm2708_compat[] = {
-+ "brcm,bcm2708",
-+ NULL
-+};
-+
-+MACHINE_START(BCM2708, "BCM2708")
-+ /* Maintainer: Broadcom Europe Ltd. */
-+ .map_io = bcm2708_map_io,
-+ .init_irq = bcm2708_init_irq,
-+ .init_time = bcm2708_timer_init,
-+ .init_machine = bcm2708_init,
-+ .init_early = bcm2708_init_early,
-+ .reserve = board_reserve,
-+ .restart = bcm2708_restart,
-+ .dt_compat = bcm2708_compat,
-+MACHINE_END
-+
-+module_param(boardrev, uint, 0644);
-+module_param(serial, uint, 0644);
-+module_param(uart_clock, uint, 0644);
-+module_param(disk_led_gpio, uint, 0644);
-+module_param(disk_led_active_low, uint, 0644);
-+module_param(reboot_part, uint, 0644);
-+module_param(w1_gpio_pin, uint, 0644);
-+module_param(w1_gpio_pullup, uint, 0644);
-+module_param(pps_gpio_pin, int, 0644);
-+MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS");
-+module_param(vc_i2c_override, bool, 0644);
-+MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral.");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c
---- linux-3.18.14/arch/arm/mach-bcm2708/bcm2708_gpio.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,426 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/spinlock.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <mach/gpio.h>
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <mach/platform.h>
-+#include <linux/pinctrl/consumer.h>
-+
-+#include <linux/platform_data/bcm2708.h>
-+
-+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
-+#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
-+#define BCM_GPIO_USE_IRQ 1
-+
-+#define GPIOFSEL(x) (0x00+(x)*4)
-+#define GPIOSET(x) (0x1c+(x)*4)
-+#define GPIOCLR(x) (0x28+(x)*4)
-+#define GPIOLEV(x) (0x34+(x)*4)
-+#define GPIOEDS(x) (0x40+(x)*4)
-+#define GPIOREN(x) (0x4c+(x)*4)
-+#define GPIOFEN(x) (0x58+(x)*4)
-+#define GPIOHEN(x) (0x64+(x)*4)
-+#define GPIOLEN(x) (0x70+(x)*4)
-+#define GPIOAREN(x) (0x7c+(x)*4)
-+#define GPIOAFEN(x) (0x88+(x)*4)
-+#define GPIOUD(x) (0x94+(x)*4)
-+#define GPIOUDCLK(x) (0x98+(x)*4)
-+
-+#define GPIO_BANKS 2
-+
-+enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
-+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
-+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
-+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
-+};
-+
-+ /* Each of the two spinlocks protects a different set of hardware
-+ * regiters and data structurs. This decouples the code of the IRQ from
-+ * the GPIO code. This also makes the case of a GPIO routine call from
-+ * the IRQ code simpler.
-+ */
-+static DEFINE_SPINLOCK(lock); /* GPIO registers */
-+
-+struct bcm2708_gpio {
-+ struct list_head list;
-+ void __iomem *base;
-+ struct gpio_chip gc;
-+ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
-+};
-+
-+static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
-+ int function)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned long flags;
-+ unsigned gpiodir;
-+ unsigned gpio_bank = offset / 10;
-+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
-+
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&lock, flags);
-+
-+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
-+ gpiodir &= ~(7 << gpio_field_offset);
-+ gpiodir |= function << gpio_field_offset;
-+ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
-+ spin_unlock_irqrestore(&lock, flags);
-+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
-+
-+ return 0;
-+}
-+
-+static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
-+{
-+ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
-+}
-+
-+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
-+static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
-+ int value)
-+{
-+ int ret;
-+ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
-+ if (ret >= 0)
-+ bcm2708_gpio_set(gc, offset, value);
-+ return ret;
-+}
-+
-+static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+ unsigned lev;
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return 0;
-+ lev = readl(gpio->base + GPIOLEV(gpio_bank));
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
-+ return 0x1 & (lev >> gpio_field_offset);
-+}
-+
-+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return;
-+ if (value)
-+ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
-+ else
-+ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
-+}
-+
-+/**********************
-+ * extension to configure pullups
-+ */
-+int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
-+ bcm2708_gpio_pull_t value)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ switch (value) {
-+ case BCM2708_PULL_UP:
-+ writel(2, gpio->base + GPIOUD(0));
-+ break;
-+ case BCM2708_PULL_DOWN:
-+ writel(1, gpio->base + GPIOUD(0));
-+ break;
-+ case BCM2708_PULL_OFF:
-+ writel(0, gpio->base + GPIOUD(0));
-+ break;
-+ }
-+
-+ udelay(5);
-+ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
-+ udelay(5);
-+ writel(0, gpio->base + GPIOUD(0));
-+ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(bcm2708_gpio_setpull);
-+
-+/*************************************************************************************************************************
-+ * bcm2708 GPIO IRQ
-+ */
-+
-+#if BCM_GPIO_USE_IRQ
-+
-+static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return gpio_to_irq(gpio);
-+}
-+
-+static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned go = gn % 32;
-+
-+ gpio->rising[gb] &= ~(1 << go);
-+ gpio->falling[gb] &= ~(1 << go);
-+ gpio->high[gb] &= ~(1 << go);
-+ gpio->low[gb] &= ~(1 << go);
-+
-+ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-+ return -EINVAL;
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ gpio->rising[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ gpio->falling[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_LEVEL_HIGH)
-+ gpio->high[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_LEVEL_LOW)
-+ gpio->low[gb] |= (1 << go);
-+ return 0;
-+}
-+
-+static void bcm2708_gpio_irq_mask(struct irq_data *d)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned long rising = readl(gpio->base + GPIOREN(gb));
-+ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
-+ unsigned long high = readl(gpio->base + GPIOHEN(gb));
-+ unsigned long low = readl(gpio->base + GPIOLEN(gb));
-+
-+ gn = gn % 32;
-+
-+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
-+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
-+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
-+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
-+}
-+
-+static void bcm2708_gpio_irq_unmask(struct irq_data *d)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned go = gn % 32;
-+ unsigned long rising = readl(gpio->base + GPIOREN(gb));
-+ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
-+ unsigned long high = readl(gpio->base + GPIOHEN(gb));
-+ unsigned long low = readl(gpio->base + GPIOLEN(gb));
-+
-+ if (gpio->rising[gb] & (1 << go)) {
-+ writel(rising | (1 << go), gpio->base + GPIOREN(gb));
-+ } else {
-+ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
-+ }
-+
-+ if (gpio->falling[gb] & (1 << go)) {
-+ writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
-+ } else {
-+ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
-+ }
-+
-+ if (gpio->high[gb] & (1 << go)) {
-+ writel(high | (1 << go), gpio->base + GPIOHEN(gb));
-+ } else {
-+ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
-+ }
-+
-+ if (gpio->low[gb] & (1 << go)) {
-+ writel(low | (1 << go), gpio->base + GPIOLEN(gb));
-+ } else {
-+ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
-+ }
-+}
-+
-+static struct irq_chip bcm2708_irqchip = {
-+ .name = "GPIO",
-+ .irq_enable = bcm2708_gpio_irq_unmask,
-+ .irq_disable = bcm2708_gpio_irq_mask,
-+ .irq_unmask = bcm2708_gpio_irq_unmask,
-+ .irq_mask = bcm2708_gpio_irq_mask,
-+ .irq_set_type = bcm2708_gpio_irq_set_type,
-+};
-+
-+static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
-+{
-+ unsigned long edsr;
-+ unsigned bank;
-+ int i;
-+ unsigned gpio;
-+ unsigned level_bits;
-+ struct bcm2708_gpio *gpio_data = dev_id;
-+
-+ for (bank = 0; bank < GPIO_BANKS; bank++) {
-+ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
-+ level_bits = gpio_data->high[bank] | gpio_data->low[bank];
-+
-+ for_each_set_bit(i, &edsr, 32) {
-+ gpio = i + bank * 32;
-+ /* ack edge triggered IRQs immediately */
-+ if (!(level_bits & (1<<i)))
-+ writel(1<<i,
-+ __io_address(GPIO_BASE) + GPIOEDS(bank));
-+ generic_handle_irq(gpio_to_irq(gpio));
-+ /* ack level triggered IRQ after handling them */
-+ if (level_bits & (1<<i))
-+ writel(1<<i,
-+ __io_address(GPIO_BASE) + GPIOEDS(bank));
-+ }
-+ }
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction bcm2708_gpio_irq = {
-+ .name = "BCM2708 GPIO catchall handler",
-+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = bcm2708_gpio_interrupt,
-+};
-+
-+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
-+{
-+ unsigned irq;
-+
-+ ucb->gc.to_irq = bcm2708_gpio_to_irq;
-+
-+ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
-+ irq_set_chip_data(irq, ucb);
-+ irq_set_chip_and_handler(irq, &bcm2708_irqchip,
-+ handle_simple_irq);
-+ set_irq_flags(irq, IRQF_VALID);
-+ }
-+
-+ bcm2708_gpio_irq.dev_id = ucb;
-+ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
-+}
-+
-+#else
-+
-+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
-+{
-+}
-+
-+#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
-+
-+static int bcm2708_gpio_probe(struct platform_device *dev)
-+{
-+ struct bcm2708_gpio *ucb;
-+ struct resource *res;
-+ int bank;
-+ int err = 0;
-+
-+ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
-+
-+ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
-+ if (NULL == ucb) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "mailbox memory\n");
-+ err = -ENOMEM;
-+ goto err;
-+ }
-+
-+ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-+
-+ platform_set_drvdata(dev, ucb);
-+ ucb->base = __io_address(GPIO_BASE);
-+
-+ ucb->gc.label = "bcm2708_gpio";
-+ ucb->gc.base = 0;
-+ ucb->gc.ngpio = BCM2708_NR_GPIOS;
-+ ucb->gc.owner = THIS_MODULE;
-+
-+ ucb->gc.direction_input = bcm2708_gpio_dir_in;
-+ ucb->gc.direction_output = bcm2708_gpio_dir_out;
-+ ucb->gc.get = bcm2708_gpio_get;
-+ ucb->gc.set = bcm2708_gpio_set;
-+ ucb->gc.can_sleep = 0;
-+
-+ for (bank = 0; bank < GPIO_BANKS; bank++) {
-+ writel(0, ucb->base + GPIOREN(bank));
-+ writel(0, ucb->base + GPIOFEN(bank));
-+ writel(0, ucb->base + GPIOHEN(bank));
-+ writel(0, ucb->base + GPIOLEN(bank));
-+ writel(0, ucb->base + GPIOAREN(bank));
-+ writel(0, ucb->base + GPIOAFEN(bank));
-+ writel(~0, ucb->base + GPIOEDS(bank));
-+ }
-+
-+ bcm2708_gpio_irq_init(ucb);
-+
-+ err = gpiochip_add(&ucb->gc);
-+
-+err:
-+ return err;
-+
-+}
-+
-+static int bcm2708_gpio_remove(struct platform_device *dev)
-+{
-+ int err = 0;
-+ struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
-+
-+ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
-+
-+ gpiochip_remove(&ucb->gc);
-+
-+ platform_set_drvdata(dev, NULL);
-+ kfree(ucb);
-+
-+ return err;
-+}
-+
-+static struct platform_driver bcm2708_gpio_driver = {
-+ .probe = bcm2708_gpio_probe,
-+ .remove = bcm2708_gpio_remove,
-+ .driver = {
-+ .name = "bcm2708_gpio"},
-+};
-+
-+static int __init bcm2708_gpio_init(void)
-+{
-+ return platform_driver_register(&bcm2708_gpio_driver);
-+}
-+
-+static void __exit bcm2708_gpio_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_gpio_driver);
-+}
-+
-+module_init(bcm2708_gpio_init);
-+module_exit(bcm2708_gpio_exit);
-+
-+MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/bcm2708.h linux-rpi/arch/arm/mach-bcm2708/bcm2708.h
---- linux-3.18.14/arch/arm/mach-bcm2708/bcm2708.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,49 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708.h
-+ *
-+ * BCM2708 machine support header
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_BCM2708_H
-+#define __BCM2708_BCM2708_H
-+
-+#include <linux/amba/bus.h>
-+
-+extern void __init bcm2708_init(void);
-+extern void __init bcm2708_init_irq(void);
-+extern void __init bcm2708_map_io(void);
-+extern struct sys_timer bcm2708_timer;
-+extern unsigned int mmc_status(struct device *dev);
-+
-+#define AMBA_DEVICE(name, busid, base, plat) \
-+static struct amba_device name##_device = { \
-+ .dev = { \
-+ .coherent_dma_mask = ~0, \
-+ .init_name = busid, \
-+ .platform_data = plat, \
-+ }, \
-+ .res = { \
-+ .start = base##_BASE, \
-+ .end = (base##_BASE) + SZ_4K - 1,\
-+ .flags = IORESOURCE_MEM, \
-+ }, \
-+ .irq = base##_IRQ, \
-+}
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/dma.c linux-rpi/arch/arm/mach-bcm2708/dma.c
---- linux-3.18.14/arch/arm/mach-bcm2708/dma.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/dma.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,409 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/dma.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/slab.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/scatterlist.h>
-+
-+#include <mach/dma.h>
-+#include <mach/irqs.h>
-+
-+/*****************************************************************************\
-+ * *
-+ * Configuration *
-+ * *
-+\*****************************************************************************/
-+
-+#define CACHE_LINE_MASK 31
-+#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
-+#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
-+
-+/* valid only for channels 0 - 14, 15 has its own base address */
-+#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
-+#define BCM2708_DMA_CHANIO(dma_base, n) \
-+ ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
-+
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Auxilliary Functions *
-+ * *
-+\*****************************************************************************/
-+
-+/* A DMA buffer on an arbitrary boundary may separate a cache line into a
-+ section inside the DMA buffer and another section outside it.
-+ Even if we flush DMA buffers from the cache there is always the chance that
-+ during a DMA someone will access the part of a cache line that is outside
-+ the DMA buffer - which will then bring in unwelcome data.
-+ Without being able to dictate our own buffer pools we must insist that
-+ DMA buffers consist of a whole number of cache lines.
-+*/
-+
-+extern int
-+bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
-+{
-+ int i;
-+
-+ for (i = 0; i < sg_len; i++) {
-+ if (sg_ptr[i].offset & CACHE_LINE_MASK ||
-+ sg_ptr[i].length & CACHE_LINE_MASK)
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
-+
-+extern void
-+bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
-+{
-+ dsb(); /* ARM data synchronization (push) operation */
-+
-+ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
-+ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
-+}
-+
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
-+{
-+ dsb();
-+
-+ /* ugly busy wait only option for now */
-+ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
-+ cpu_relax();
-+}
-+
-+EXPORT_SYMBOL_GPL(bcm_dma_start);
-+
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
-+{
-+ dsb();
-+
-+ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
-+
-+/* Complete an ongoing DMA (assuming its results are to be ignored)
-+ Does nothing if there is no DMA in progress.
-+ This routine waits for the current AXI transfer to complete before
-+ terminating the current DMA. If the current transfer is hung on a DREQ used
-+ by an uncooperative peripheral the AXI transfer may never complete. In this
-+ case the routine times out and return a non-zero error code.
-+ Use of this routine doesn't guarantee that the ongoing or aborted DMA
-+ does not produce an interrupt.
-+*/
-+extern int
-+bcm_dma_abort(void __iomem *dma_chan_base)
-+{
-+ unsigned long int cs;
-+ int rc = 0;
-+
-+ cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (BCM2708_DMA_ACTIVE & cs) {
-+ long int timeout = 10000;
-+
-+ /* write 0 to the active bit - pause the DMA */
-+ writel(0, dma_chan_base + BCM2708_DMA_CS);
-+
-+ /* wait for any current AXI transfer to complete */
-+ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
-+ cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
-+ /* we'll un-pause when we set of our next DMA */
-+ rc = -ETIMEDOUT;
-+
-+ } else if (BCM2708_DMA_ACTIVE & cs) {
-+ /* terminate the control block chain */
-+ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
-+
-+ /* abort the whole DMA */
-+ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
-+ dma_chan_base + BCM2708_DMA_CS);
-+ }
-+ }
-+
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_abort);
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * DMA Manager Device Methods *
-+ * *
-+\*****************************************************************************/
-+
-+struct vc_dmaman {
-+ void __iomem *dma_base;
-+ u32 chan_available; /* bitmap of available channels */
-+ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
-+};
-+
-+static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
-+ u32 chans_available)
-+{
-+ dmaman->dma_base = dma_base;
-+ dmaman->chan_available = chans_available;
-+ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */
-+}
-+
-+static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
-+ unsigned preferred_feature_set)
-+{
-+ u32 chans;
-+ int feature;
-+
-+ chans = dmaman->chan_available;
-+ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
-+ /* select the subset of available channels with the desired
-+ feature so long as some of the candidate channels have that
-+ feature */
-+ if ((preferred_feature_set & (1 << feature)) &&
-+ (chans & dmaman->has_feature[feature]))
-+ chans &= dmaman->has_feature[feature];
-+
-+ if (chans) {
-+ int chan = 0;
-+ /* return the ordinal of the first channel in the bitmap */
-+ while (chans != 0 && (chans & 1) == 0) {
-+ chans >>= 1;
-+ chan++;
-+ }
-+ /* claim the channel */
-+ dmaman->chan_available &= ~(1 << chan);
-+ return chan;
-+ } else
-+ return -ENOMEM;
-+}
-+
-+static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
-+{
-+ if (chan < 0)
-+ return -EINVAL;
-+ else if ((1 << chan) & dmaman->chan_available)
-+ return -EIDRM;
-+ else {
-+ dmaman->chan_available |= (1 << chan);
-+ return 0;
-+ }
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA IRQs *
-+ * *
-+\*****************************************************************************/
-+
-+static unsigned char bcm_dma_irqs[] = {
-+ IRQ_DMA0,
-+ IRQ_DMA1,
-+ IRQ_DMA2,
-+ IRQ_DMA3,
-+ IRQ_DMA4,
-+ IRQ_DMA5,
-+ IRQ_DMA6,
-+ IRQ_DMA7,
-+ IRQ_DMA8,
-+ IRQ_DMA9,
-+ IRQ_DMA10,
-+ IRQ_DMA11,
-+ IRQ_DMA12
-+};
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * DMA Manager Monitor *
-+ * *
-+\*****************************************************************************/
-+
-+static struct device *dmaman_dev; /* we assume there's only one! */
-+
-+extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+ void __iomem **out_dma_base, int *out_dma_irq)
-+{
-+ if (!dmaman_dev)
-+ return -ENODEV;
-+ else {
-+ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
-+ int rc;
-+
-+ device_lock(dmaman_dev);
-+ rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
-+ if (rc >= 0) {
-+ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
-+ rc);
-+ *out_dma_irq = bcm_dma_irqs[rc];
-+ }
-+ device_unlock(dmaman_dev);
-+
-+ return rc;
-+ }
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
-+
-+extern int bcm_dma_chan_free(int channel)
-+{
-+ if (dmaman_dev) {
-+ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
-+ int rc;
-+
-+ device_lock(dmaman_dev);
-+ rc = vc_dmaman_chan_free(dmaman, channel);
-+ device_unlock(dmaman_dev);
-+
-+ return rc;
-+ } else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
-+
-+static int dev_dmaman_register(const char *dev_name, struct device *dev)
-+{
-+ int rc = dmaman_dev ? -EINVAL : 0;
-+ dmaman_dev = dev;
-+ return rc;
-+}
-+
-+static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
-+{
-+ dmaman_dev = NULL;
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Device *
-+ * *
-+\*****************************************************************************/
-+
-+static int dmachans = -1; /* module parameter */
-+
-+static int bcm_dmaman_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+ struct vc_dmaman *dmaman;
-+ struct resource *dma_res = NULL;
-+ void __iomem *dma_base = NULL;
-+ int have_dma_region = 0;
-+
-+ dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
-+ if (NULL == dmaman) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "DMA management memory\n");
-+ ret = -ENOMEM;
-+ } else {
-+
-+ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (dma_res == NULL) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
-+ "resource\n");
-+ ret = -ENODEV;
-+ } else if (!request_mem_region(dma_res->start,
-+ resource_size(dma_res),
-+ DRIVER_NAME)) {
-+ dev_err(&pdev->dev, "cannot obtain DMA region\n");
-+ ret = -EBUSY;
-+ } else {
-+ have_dma_region = 1;
-+ dma_base = ioremap(dma_res->start,
-+ resource_size(dma_res));
-+ if (!dma_base) {
-+ dev_err(&pdev->dev, "cannot map DMA region\n");
-+ ret = -ENOMEM;
-+ } else {
-+ /* use module parameter if one was provided */
-+ if (dmachans > 0)
-+ vc_dmaman_init(dmaman, dma_base,
-+ dmachans);
-+ else
-+ vc_dmaman_init(dmaman, dma_base,
-+ DEFAULT_DMACHAN_BITMAP);
-+
-+ platform_set_drvdata(pdev, dmaman);
-+ dev_dmaman_register(DRIVER_NAME, &pdev->dev);
-+
-+ printk(KERN_INFO DRIVER_NAME ": DMA manager "
-+ "at %p\n", dma_base);
-+ }
-+ }
-+ }
-+ if (ret != 0) {
-+ if (dma_base)
-+ iounmap(dma_base);
-+ if (dma_res && have_dma_region)
-+ release_mem_region(dma_res->start,
-+ resource_size(dma_res));
-+ if (dmaman)
-+ kfree(dmaman);
-+ }
-+ return ret;
-+}
-+
-+static int bcm_dmaman_remove(struct platform_device *pdev)
-+{
-+ struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
-+ kfree(dmaman);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm_dmaman_driver = {
-+ .probe = bcm_dmaman_probe,
-+ .remove = bcm_dmaman_remove,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+/*****************************************************************************\
-+ * *
-+ * Driver init/exit *
-+ * *
-+\*****************************************************************************/
-+
-+static int __init bcm_dmaman_drv_init(void)
-+{
-+ int ret;
-+
-+ ret = platform_driver_register(&bcm_dmaman_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to register "
-+ "on platform\n");
-+ }
-+
-+ return ret;
-+}
-+
-+static void __exit bcm_dmaman_drv_exit(void)
-+{
-+ platform_driver_unregister(&bcm_dmaman_driver);
-+}
-+
-+module_init(bcm_dmaman_drv_init);
-+module_exit(bcm_dmaman_drv_exit);
-+
-+module_param(dmachans, int, 0644);
-+
-+MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
-+MODULE_DESCRIPTION("DMA channel manager driver");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/arm_control.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,419 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/arm_control.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_ARM_CONTROL_H
-+#define __BCM2708_ARM_CONTROL_H
-+
-+/*
-+ * Definitions and addresses for the ARM CONTROL logic
-+ * This file is manually generated.
-+ */
-+
-+#define ARM_BASE 0x7E00B000
-+
-+/* Basic configuration */
-+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
-+#define ARM_C0_SIZ128M 0x00000000
-+#define ARM_C0_SIZ256M 0x00000001
-+#define ARM_C0_SIZ512M 0x00000002
-+#define ARM_C0_SIZ1G 0x00000003
-+#define ARM_C0_BRESP0 0x00000000
-+#define ARM_C0_BRESP1 0x00000004
-+#define ARM_C0_BRESP2 0x00000008
-+#define ARM_C0_BOOTHI 0x00000010
-+#define ARM_C0_UNUSED05 0x00000020 /* free */
-+#define ARM_C0_FULLPERI 0x00000040
-+#define ARM_C0_UNUSED78 0x00000180 /* free */
-+#define ARM_C0_JTAGMASK 0x00000E00
-+#define ARM_C0_JTAGOFF 0x00000000
-+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
-+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
-+#define ARM_C0_APROTMSK 0x0000F000
-+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
-+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
-+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
-+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
-+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
-+#define ARM_C0_PRIO_L2 0x0F000000
-+#define ARM_C0_PRIO_UC 0xF0000000
-+
-+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
-+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
-+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
-+
-+
-+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
-+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
-+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
-+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
-+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
-+#define ARM_C1_PERSON 0x00000100 /* peripherals on */
-+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
-+
-+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
-+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
-+#define ARM_S_READPEND 0x000003FF /* pending reads counter */
-+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
-+
-+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
-+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
-+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
-+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
-+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
-+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
-+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
-+
-+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
-+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
-+#define ARM_IDVAL 0x364D5241
-+
-+/* Translation memory */
-+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
-+/* 32 locations: 0x100.. 0x17F */
-+/* 32 spare means we CAN go to 64 pages.... */
-+
-+
-+/* Interrupts */
-+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
-+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
-+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
-+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
-+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
-+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
-+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
-+
-+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
-+/* todo: all I1_interrupt sources */
-+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
-+/* todo: all I2_interrupt sources */
-+
-+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
-+#define ARM_IF_INDEX 0x0000007F /* FIQ select */
-+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
-+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
-+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
-+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
-+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
-+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
-+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
-+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
-+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
-+
-+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
-+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
-+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
-+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
-+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
-+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
-+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
-+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
-+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
-+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
-+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
-+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
-+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
-+
-+/* Timer */
-+/* For reg. fields see sp804 spec. */
-+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
-+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
-+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
-+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
-+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
-+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
-+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
-+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
-+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
-+
-+#define TIMER_CTRL_ONESHOT (1 << 0)
-+#define TIMER_CTRL_32BIT (1 << 1)
-+#define TIMER_CTRL_DIV1 (0 << 2)
-+#define TIMER_CTRL_DIV16 (1 << 2)
-+#define TIMER_CTRL_DIV256 (2 << 2)
-+#define TIMER_CTRL_IE (1 << 5)
-+#define TIMER_CTRL_PERIODIC (1 << 6)
-+#define TIMER_CTRL_ENABLE (1 << 7)
-+#define TIMER_CTRL_DBGHALT (1 << 8)
-+#define TIMER_CTRL_ENAFREE (1 << 9)
-+#define TIMER_CTRL_FREEDIV_SHIFT 16)
-+#define TIMER_CTRL_FREEDIV_MASK 0xff
-+
-+/* Semaphores, Doorbells, Mailboxes */
-+#define ARM_SBM_OWN0 (ARM_BASE+0x800)
-+#define ARM_SBM_OWN1 (ARM_BASE+0x900)
-+#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
-+#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
-+
-+/* MAILBOXES
-+ * Register flags are common across all
-+ * owner registers. See end of this section
-+ *
-+ * Semaphores, Doorbells, Mailboxes Owner 0
-+ *
-+ */
-+
-+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
-+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
-+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
-+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
-+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
-+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
-+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
-+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
-+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
-+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
-+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
-+/* MAILBOX 0 access in Owner 0 area */
-+/* Some addresses should ONLY be used by owner 0 */
-+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
-+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
-+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
-+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
-+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
-+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
-+/* MAILBOX 1 access in Owner 0 area */
-+/* Owner 0 should only WRITE to this mailbox */
-+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
-+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
-+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
-+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
-+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 1 */
-+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
-+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
-+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
-+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
-+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
-+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
-+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
-+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
-+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
-+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
-+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
-+/* MAILBOX 0 access in Owner 0 area */
-+/* Owner 1 should only WRITE to this mailbox */
-+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
-+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 0 area */
-+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
-+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
-+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
-+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
-+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
-+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
-+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
-+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
-+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 2 */
-+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
-+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
-+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
-+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
-+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
-+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
-+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
-+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
-+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
-+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
-+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
-+/* MAILBOX 0 access in Owner 2 area */
-+/* Owner 2 should only WRITE to this mailbox */
-+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
-+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 2 area */
-+/* Owner 2 should only WRITE to this mailbox */
-+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
-+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
-+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
-+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
-+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 3 */
-+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
-+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
-+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
-+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
-+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
-+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
-+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
-+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
-+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
-+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
-+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
-+/* MAILBOX 0 access in Owner 3 area */
-+/* Owner 3 should only WRITE to this mailbox */
-+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
-+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 3 area */
-+/* Owner 3 should only WRITE to this mailbox */
-+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
-+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
-+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
-+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
-+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
-+
-+
-+
-+/* Mailbox flags. Valid for all owners */
-+
-+/* Mailbox status register (...0x98) */
-+#define ARM_MS_FULL 0x80000000
-+#define ARM_MS_EMPTY 0x40000000
-+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
-+
-+/* MAILBOX config/status register (...0x9C) */
-+/* ANY write to this register clears the error bits! */
-+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
-+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
-+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
-+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
-+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
-+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
-+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
-+/* Bit 7 is unused */
-+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
-+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
-+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
-+
-+/* Semaphore clear/debug register (...0xE0) */
-+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
-+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
-+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
-+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
-+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
-+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
-+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
-+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
-+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
-+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
-+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
-+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
-+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
-+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
-+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
-+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
-+
-+/* Doorbells clear/debug register (...0xE4) */
-+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
-+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
-+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
-+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
-+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
-+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
-+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
-+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
-+
-+/* MY IRQS register (...0xF8) */
-+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
-+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
-+
-+/* ALL IRQS register (...0xF8) */
-+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
-+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
-+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
-+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
-+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
-+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
-+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
-+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
-+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
-+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
-+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
-+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
-+/* */
-+/* ARM JTAG BASH */
-+/* */
-+#define AJB_BASE 0x7e2000c0
-+
-+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
-+#define AJB_BITS0 0x000000
-+#define AJB_BITS4 0x000004
-+#define AJB_BITS8 0x000008
-+#define AJB_BITS12 0x00000C
-+#define AJB_BITS16 0x000010
-+#define AJB_BITS20 0x000014
-+#define AJB_BITS24 0x000018
-+#define AJB_BITS28 0x00001C
-+#define AJB_BITS32 0x000020
-+#define AJB_BITS34 0x000022
-+#define AJB_OUT_MS 0x000040
-+#define AJB_OUT_LS 0x000000
-+#define AJB_INV_CLK 0x000080
-+#define AJB_D0_RISE 0x000100
-+#define AJB_D0_FALL 0x000000
-+#define AJB_D1_RISE 0x000200
-+#define AJB_D1_FALL 0x000000
-+#define AJB_IN_RISE 0x000400
-+#define AJB_IN_FALL 0x000000
-+#define AJB_ENABLE 0x000800
-+#define AJB_HOLD0 0x000000
-+#define AJB_HOLD1 0x001000
-+#define AJB_HOLD2 0x002000
-+#define AJB_HOLD3 0x003000
-+#define AJB_RESETN 0x004000
-+#define AJB_CLKSHFT 16
-+#define AJB_BUSY 0x80000000
-+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
-+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
-+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/arm_power.h linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_power.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/arm_power.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_power.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,62 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _ARM_POWER_H
-+#define _ARM_POWER_H
-+
-+/* Use meaningful names on each side */
-+#ifdef __VIDEOCORE__
-+#define PREFIX(x) ARM_##x
-+#else
-+#define PREFIX(x) BCM_##x
-+#endif
-+
-+enum {
-+ PREFIX(POWER_SDCARD_BIT),
-+ PREFIX(POWER_UART_BIT),
-+ PREFIX(POWER_MINIUART_BIT),
-+ PREFIX(POWER_USB_BIT),
-+ PREFIX(POWER_I2C0_BIT),
-+ PREFIX(POWER_I2C1_BIT),
-+ PREFIX(POWER_I2C2_BIT),
-+ PREFIX(POWER_SPI_BIT),
-+ PREFIX(POWER_CCP2TX_BIT),
-+ PREFIX(POWER_DSI_BIT),
-+
-+ PREFIX(POWER_MAX)
-+};
-+
-+enum {
-+ PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
-+ PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
-+ PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
-+ PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
-+ PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
-+ PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
-+ PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
-+ PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
-+ PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
-+ PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
-+
-+ PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
-+ PREFIX(POWER_NONE) = 0
-+};
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/clkdev.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,7 @@
-+#ifndef __ASM_MACH_CLKDEV_H
-+#define __ASM_MACH_CLKDEV_H
-+
-+#define __clk_get(clk) ({ 1; })
-+#define __clk_put(clk) do { } while (0)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/debug-macro.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,22 @@
-+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
-+ *
-+ * Debugging macro include header
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 1994-1999 Russell King
-+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+*/
-+
-+#include <mach/platform.h>
-+
-+ .macro addruart, rp, rv, tmp
-+ ldr \rp, =UART0_BASE
-+ ldr \rv, =IO_ADDRESS(UART0_BASE)
-+ .endm
-+
-+#include <debug/pl01x.S>
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/dma.h linux-rpi/arch/arm/mach-bcm2708/include/mach/dma.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/dma.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/dma.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,94 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/include/mach/dma.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+
-+#ifndef _MACH_BCM2708_DMA_H
-+#define _MACH_BCM2708_DMA_H
-+
-+#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
-+
-+/* DMA CS Control and Status bits */
-+#define BCM2708_DMA_ACTIVE (1 << 0)
-+#define BCM2708_DMA_INT (1 << 2)
-+#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
-+#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
-+#define BCM2708_DMA_ERR (1 << 8)
-+#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
-+#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
-+
-+/* DMA control block "info" field bits */
-+#define BCM2708_DMA_INT_EN (1 << 0)
-+#define BCM2708_DMA_TDMODE (1 << 1)
-+#define BCM2708_DMA_WAIT_RESP (1 << 3)
-+#define BCM2708_DMA_D_INC (1 << 4)
-+#define BCM2708_DMA_D_WIDTH (1 << 5)
-+#define BCM2708_DMA_D_DREQ (1 << 6)
-+#define BCM2708_DMA_S_INC (1 << 8)
-+#define BCM2708_DMA_S_WIDTH (1 << 9)
-+#define BCM2708_DMA_S_DREQ (1 << 10)
-+
-+#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
-+#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
-+#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
-+
-+#define BCM2708_DMA_DREQ_EMMC 11
-+#define BCM2708_DMA_DREQ_SDHOST 13
-+
-+#define BCM2708_DMA_CS 0x00 /* Control and Status */
-+#define BCM2708_DMA_ADDR 0x04
-+/* the current control block appears in the following registers - read only */
-+#define BCM2708_DMA_INFO 0x08
-+#define BCM2708_DMA_SOURCE_AD 0x0c
-+#define BCM2708_DMA_DEST_AD 0x10
-+#define BCM2708_DMA_NEXTCB 0x1C
-+#define BCM2708_DMA_DEBUG 0x20
-+
-+#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
-+#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
-+
-+#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
-+
-+struct bcm2708_dma_cb {
-+ unsigned long info;
-+ unsigned long src;
-+ unsigned long dst;
-+ unsigned long length;
-+ unsigned long stride;
-+ unsigned long next;
-+ unsigned long pad[2];
-+};
-+struct scatterlist;
-+
-+extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
-+extern void bcm_dma_start(void __iomem *dma_chan_base,
-+ dma_addr_t control_block);
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base);
-+extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
-+
-+/* When listing features we can ask for when allocating DMA channels give
-+ those with higher priority smaller ordinal numbers */
-+#define BCM_DMA_FEATURE_FAST_ORD 0
-+#define BCM_DMA_FEATURE_BULK_ORD 1
-+#define BCM_DMA_FEATURE_NORMAL_ORD 2
-+#define BCM_DMA_FEATURE_LITE_ORD 3
-+#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
-+#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
-+#define BCM_DMA_FEATURE_NORMAL (1<<BCM_DMA_FEATURE_NORMAL_ORD)
-+#define BCM_DMA_FEATURE_LITE (1<<BCM_DMA_FEATURE_LITE_ORD)
-+#define BCM_DMA_FEATURE_COUNT 4
-+
-+/* return channel no or -ve error */
-+extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+ void __iomem **out_dma_base, int *out_dma_irq);
-+extern int bcm_dma_chan_free(int channel);
-+
-+
-+#endif /* _MACH_BCM2708_DMA_H */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/entry-macro.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,69 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/entry-macro.S
-+ *
-+ * Low-level IRQ helper macros for BCM2708 platforms
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <mach/hardware.h>
-+
-+ .macro disable_fiq
-+ .endm
-+
-+ .macro get_irqnr_preamble, base, tmp
-+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
-+ .endm
-+
-+ .macro arch_ret_to_user, tmp1, tmp2
-+ .endm
-+
-+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-+ /* get masked status */
-+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
-+ mov \irqnr, #(ARM_IRQ0_BASE + 31)
-+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
-+ /* clear bits 8 and 9, and test */
-+ bics \irqstat, \irqstat, #0x300
-+ bne 1010f
-+
-+ tst \tmp, #0x100
-+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
-+ movne \irqnr, #(ARM_IRQ1_BASE + 31)
-+ @ Mask out the interrupts also present in PEND0 - see SW-5809
-+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
-+ bicne \irqstat, #((1<<18) | (1<<19))
-+ bne 1010f
-+
-+ tst \tmp, #0x200
-+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
-+ movne \irqnr, #(ARM_IRQ2_BASE + 31)
-+ @ Mask out the interrupts also present in PEND0 - see SW-5809
-+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
-+ bicne \irqstat, #((1<<30))
-+ beq 1020f
-+
-+1010:
-+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
-+ @ N.B. CLZ is an ARM5 instruction.
-+ sub \tmp, \irqstat, #1
-+ eor \irqstat, \irqstat, \tmp
-+ clz \tmp, \irqstat
-+ sub \irqnr, \tmp
-+
-+1020: @ EQ will be set if no irqs pending
-+
-+ .endm
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/frc.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,38 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/timex.h
-+ *
-+ * BCM2708 free running counter (timer)
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _MACH_FRC_H
-+#define _MACH_FRC_H
-+
-+#define FRC_TICK_RATE (1000000)
-+
-+/*! Free running counter incrementing at the CLOCK_TICK_RATE
-+ (slightly faster than frc_clock_ticks63()
-+ */
-+extern unsigned long frc_clock_ticks32(void);
-+
-+/*! Free running counter incrementing at the CLOCK_TICK_RATE
-+ * Note - top bit should be ignored (see cnt32_to_63)
-+ */
-+extern unsigned long long frc_clock_ticks63(void);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/gpio.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,17 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/gpio.h
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef __ASM_ARCH_GPIO_H
-+#define __ASM_ARCH_GPIO_H
-+
-+#define BCM2708_NR_GPIOS 54 // number of gpio lines
-+
-+#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
-+#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/hardware.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,28 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/hardware.h
-+ *
-+ * This file contains the hardware definitions of the BCM2708 devices.
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_HARDWARE_H
-+#define __ASM_ARCH_HARDWARE_H
-+
-+#include <asm/sizes.h>
-+#include <mach/platform.h>
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/io.h linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/io.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,27 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/io.h
-+ *
-+ * Copyright (C) 2003 ARM Limited
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARM_ARCH_IO_H
-+#define __ASM_ARM_ARCH_IO_H
-+
-+#define IO_SPACE_LIMIT 0xffffffff
-+
-+#define __io(a) __typesafe_io(a)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/irqs.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,199 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/irqs.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _BCM2708_IRQS_H_
-+#define _BCM2708_IRQS_H_
-+
-+#include <mach/platform.h>
-+
-+/*
-+ * IRQ interrupts definitions are the same as the INT definitions
-+ * held within platform.h
-+ */
-+#define IRQ_ARMCTRL_START 0
-+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
-+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
-+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
-+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
-+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
-+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
-+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
-+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
-+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
-+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
-+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
-+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
-+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
-+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
-+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
-+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
-+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
-+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
-+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
-+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
-+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
-+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
-+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
-+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
-+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
-+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
-+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
-+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
-+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
-+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
-+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
-+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
-+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
-+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
-+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
-+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
-+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
-+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
-+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
-+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
-+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
-+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
-+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
-+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
-+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
-+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
-+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
-+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
-+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
-+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
-+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
-+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
-+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
-+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
-+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
-+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
-+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
-+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
-+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
-+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
-+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
-+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
-+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
-+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
-+
-+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
-+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
-+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
-+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
-+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
-+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
-+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
-+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
-+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
-+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
-+
-+#define FIQ_START HARD_IRQS
-+
-+/*
-+ * FIQ interrupts definitions are the same as the INT definitions.
-+ */
-+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
-+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
-+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
-+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
-+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
-+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
-+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
-+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
-+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
-+#define FIQ_USB (FIQ_START+INTERRUPT_USB)
-+#define FIQ_3D (FIQ_START+INTERRUPT_3D)
-+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
-+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
-+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
-+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
-+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
-+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
-+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
-+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
-+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
-+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
-+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
-+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
-+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
-+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
-+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
-+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
-+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
-+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
-+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
-+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
-+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
-+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
-+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
-+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
-+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
-+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
-+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
-+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
-+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
-+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
-+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
-+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
-+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
-+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
-+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
-+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
-+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
-+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
-+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
-+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
-+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
-+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
-+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
-+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
-+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
-+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
-+#define FIQ_UART (FIQ_START+INTERRUPT_UART)
-+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
-+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
-+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
-+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
-+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
-+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
-+
-+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
-+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
-+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
-+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
-+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
-+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
-+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
-+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
-+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
-+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
-+
-+#define HARD_IRQS (64 + 21)
-+#define FIQ_IRQS (64 + 21)
-+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
-+#define GPIO_IRQS (32*5)
-+#define SPARE_ALLOC_IRQS 64
-+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
-+#define FREE_IRQS 128
-+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
-+
-+#endif /* _BCM2708_IRQS_H_ */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/memory.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,57 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/memory.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_MEMORY_H
-+#define __ASM_ARCH_MEMORY_H
-+
-+/* Memory overview:
-+
-+ [ARMcore] <--virtual addr-->
-+ [ARMmmu] <--physical addr-->
-+ [GERTmap] <--bus add-->
-+ [VCperiph]
-+
-+*/
-+
-+/*
-+ * Physical DRAM offset.
-+ */
-+#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
-+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
-+
-+#ifdef CONFIG_BCM2708_NOL2CACHE
-+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
-+#else
-+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
-+#endif
-+
-+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
-+ * will provide the offset into this area as well as setting the bits that
-+ * stop the L1 and L2 cache from being used
-+ *
-+ * WARNING: this only works because the ARM is given memory at a fixed location
-+ * (ARMMEM_OFFSET)
-+ */
-+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
-+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
-+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
-+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
-+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/platform.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,228 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/platform.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _BCM2708_PLATFORM_H
-+#define _BCM2708_PLATFORM_H
-+
-+
-+/* macros to get at IO space when running virtually */
-+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-+
-+#define __io_address(n) IOMEM(IO_ADDRESS(n))
-+
-+
-+/*
-+ * SDRAM
-+ */
-+#define BCM2708_SDRAM_BASE 0x00000000
-+
-+/*
-+ * Logic expansion modules
-+ *
-+ */
-+
-+
-+/* ------------------------------------------------------------------------
-+ * BCM2708 ARMCTRL Registers
-+ * ------------------------------------------------------------------------
-+ */
-+
-+#define HW_REGISTER_RW(addr) (addr)
-+#define HW_REGISTER_RO(addr) (addr)
-+
-+#include "arm_control.h"
-+#undef ARM_BASE
-+
-+/*
-+ * Definitions and addresses for the ARM CONTROL logic
-+ * This file is manually generated.
-+ */
-+
-+#define BCM2708_PERI_BASE 0x20000000
-+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
-+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
-+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
-+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
-+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
-+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
-+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
-+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
-+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
-+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
-+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
-+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
-+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
-+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
-+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
-+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
-+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
-+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
-+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
-+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
-+
-+#define ARMCTRL_BASE (ARM_BASE + 0x000)
-+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
-+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
-+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
-+
-+
-+/*
-+ * Interrupt assignments
-+ */
-+
-+#define ARM_IRQ1_BASE 0
-+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
-+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
-+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
-+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
-+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
-+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
-+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
-+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
-+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
-+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
-+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
-+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
-+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
-+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
-+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
-+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
-+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
-+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
-+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
-+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
-+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
-+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
-+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
-+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
-+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
-+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
-+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
-+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
-+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
-+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
-+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
-+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
-+
-+#define ARM_IRQ2_BASE 32
-+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
-+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
-+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
-+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
-+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
-+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
-+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
-+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
-+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
-+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
-+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
-+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
-+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
-+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
-+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
-+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
-+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
-+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
-+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
-+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
-+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
-+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
-+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
-+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
-+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
-+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
-+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
-+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
-+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
-+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
-+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
-+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
-+
-+#define ARM_IRQ0_BASE 64
-+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
-+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
-+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
-+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
-+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
-+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
-+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
-+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
-+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
-+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
-+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
-+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
-+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
-+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
-+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
-+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
-+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
-+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
-+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
-+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
-+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
-+
-+#define MAXIRQNUM (32 + 32 + 20)
-+#define MAXFIQNUM (32 + 32 + 20)
-+
-+#define MAX_TIMER 2
-+#define MAX_PERIOD 699050
-+#define TICKS_PER_uSEC 1
-+
-+/*
-+ * These are useconds NOT ticks.
-+ *
-+ */
-+#define mSEC_1 1000
-+#define mSEC_5 (mSEC_1 * 5)
-+#define mSEC_10 (mSEC_1 * 10)
-+#define mSEC_25 (mSEC_1 * 25)
-+#define SEC_1 (mSEC_1 * 1000)
-+
-+/*
-+ * Watchdog
-+ */
-+#define PM_RSTC (PM_BASE+0x1c)
-+#define PM_RSTS (PM_BASE+0x20)
-+#define PM_WDOG (PM_BASE+0x24)
-+
-+#define PM_WDOG_RESET 0000000000
-+#define PM_PASSWORD 0x5a000000
-+#define PM_WDOG_TIME_SET 0x000fffff
-+#define PM_RSTC_WRCFG_CLR 0xffffffcf
-+#define PM_RSTC_WRCFG_SET 0x00000030
-+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
-+#define PM_RSTC_RESET 0x00000102
-+
-+#define PM_RSTS_HADPOR_SET 0x00001000
-+#define PM_RSTS_HADSRH_SET 0x00000400
-+#define PM_RSTS_HADSRF_SET 0x00000200
-+#define PM_RSTS_HADSRQ_SET 0x00000100
-+#define PM_RSTS_HADWRH_SET 0x00000040
-+#define PM_RSTS_HADWRF_SET 0x00000020
-+#define PM_RSTS_HADWRQ_SET 0x00000010
-+#define PM_RSTS_HADDRH_SET 0x00000004
-+#define PM_RSTS_HADDRF_SET 0x00000002
-+#define PM_RSTS_HADDRQ_SET 0x00000001
-+
-+#define UART0_CLOCK 3000000
-+
-+#endif
-+
-+/* END */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/power.h linux-rpi/arch/arm/mach-bcm2708/include/mach/power.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/power.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/power.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,26 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/power.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for controlling the power to
-+ * VideoCore subsystems.
-+ */
-+
-+#ifndef _MACH_BCM2708_POWER_H
-+#define _MACH_BCM2708_POWER_H
-+
-+#include <linux/types.h>
-+#include <mach/arm_power.h>
-+
-+typedef unsigned int BCM_POWER_HANDLE_T;
-+
-+extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
-+extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
-+extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/system.h linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/system.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,38 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/system.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_SYSTEM_H
-+#define __ASM_ARCH_SYSTEM_H
-+
-+#include <linux/io.h>
-+#include <mach/hardware.h>
-+#include <mach/platform.h>
-+
-+static inline void arch_idle(void)
-+{
-+ /*
-+ * This should do all the clock switching
-+ * and wait for interrupt tricks
-+ */
-+ cpu_do_idle();
-+}
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/timex.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,23 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/timex.h
-+ *
-+ * BCM2708 sysem clock frequency
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#define CLOCK_TICK_RATE (1000000)
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/uncompress.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,84 @@
-+/*
-+ * arch/arm/mach-bcn2708/include/mach/uncompress.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/amba/serial.h>
-+#include <mach/hardware.h>
-+
-+#define UART_BAUD 115200
-+
-+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
-+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
-+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
-+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
-+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
-+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
-+
-+/*
-+ * This does not append a newline
-+ */
-+static inline void putc(int c)
-+{
-+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
-+ barrier();
-+
-+ __raw_writel(c, BCM2708_UART_DR);
-+}
-+
-+static inline void flush(void)
-+{
-+ int fr;
-+
-+ do {
-+ fr = __raw_readl(BCM2708_UART_FR);
-+ barrier();
-+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
-+}
-+
-+static inline void arch_decomp_setup(void)
-+{
-+ int temp, div, rem, frac;
-+
-+ temp = 16 * UART_BAUD;
-+ div = UART0_CLOCK / temp;
-+ rem = UART0_CLOCK % temp;
-+ temp = (8 * rem) / UART_BAUD;
-+ frac = (temp >> 1) + (temp & 1);
-+
-+ /* Make sure the UART is disabled before we start */
-+ __raw_writel(0, BCM2708_UART_CR);
-+
-+ /* Set the baud rate */
-+ __raw_writel(div, BCM2708_UART_IBRD);
-+ __raw_writel(frac, BCM2708_UART_FBRD);
-+
-+ /* Set the UART to 8n1, FIFO enabled */
-+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
-+
-+ /* Enable the UART */
-+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
-+ BCM2708_UART_CR);
-+}
-+
-+/*
-+ * nothing to do
-+ */
-+#define arch_decomp_wdog()
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vcio.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vcio.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vcio.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vcio.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,165 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/vcio.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef _MACH_BCM2708_VCIO_H
-+#define _MACH_BCM2708_VCIO_H
-+
-+/* Routines to handle I/O via the VideoCore "ARM control" registers
-+ * (semaphores, doorbells, mailboxes)
-+ */
-+
-+#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
-+
-+/* Constants shared with the ARM identifying separate mailbox channels */
-+#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
-+#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
-+#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
-+#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
-+#define MBOX_CHAN_COUNT 9
-+
-+enum {
-+ VCMSG_PROCESS_REQUEST = 0x00000000
-+};
-+enum {
-+ VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
-+ VCMSG_REQUEST_FAILED = 0x80000001
-+};
-+/* Mailbox property tags */
-+enum {
-+ VCMSG_PROPERTY_END = 0x00000000,
-+ VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
-+ VCMSG_GET_BOARD_MODEL = 0x00010001,
-+ VCMSG_GET_BOARD_REVISION = 0x00010002,
-+ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
-+ VCMSG_GET_BOARD_SERIAL = 0x00010004,
-+ VCMSG_GET_ARM_MEMORY = 0x00010005,
-+ VCMSG_GET_VC_MEMORY = 0x00010006,
-+ VCMSG_GET_CLOCKS = 0x00010007,
-+ VCMSG_GET_COMMAND_LINE = 0x00050001,
-+ VCMSG_GET_DMA_CHANNELS = 0x00060001,
-+ VCMSG_GET_POWER_STATE = 0x00020001,
-+ VCMSG_GET_TIMING = 0x00020002,
-+ VCMSG_SET_POWER_STATE = 0x00028001,
-+ VCMSG_GET_CLOCK_STATE = 0x00030001,
-+ VCMSG_SET_CLOCK_STATE = 0x00038001,
-+ VCMSG_GET_CLOCK_RATE = 0x00030002,
-+ VCMSG_SET_CLOCK_RATE = 0x00038002,
-+ VCMSG_GET_VOLTAGE = 0x00030003,
-+ VCMSG_SET_VOLTAGE = 0x00038003,
-+ VCMSG_GET_MAX_CLOCK = 0x00030004,
-+ VCMSG_GET_MAX_VOLTAGE = 0x00030005,
-+ VCMSG_GET_TEMPERATURE = 0x00030006,
-+ VCMSG_GET_MIN_CLOCK = 0x00030007,
-+ VCMSG_GET_MIN_VOLTAGE = 0x00030008,
-+ VCMSG_GET_TURBO = 0x00030009,
-+ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
-+ VCMSG_GET_STC = 0x0003000b,
-+ VCMSG_SET_TURBO = 0x00038009,
-+ VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
-+ VCMSG_SET_LOCK_MEM = 0x0003000d,
-+ VCMSG_SET_UNLOCK_MEM = 0x0003000e,
-+ VCMSG_SET_RELEASE_MEM = 0x0003000f,
-+ VCMSG_SET_EXECUTE_CODE = 0x00030010,
-+ VCMSG_SET_EXECUTE_QPU = 0x00030011,
-+ VCMSG_SET_ENABLE_QPU = 0x00030012,
-+ VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
-+ VCMSG_GET_EDID_BLOCK = 0x00030020,
-+ VCMSG_GET_CUSTOMER_OTP = 0x00030021,
-+ VCMSG_SET_CUSTOMER_OTP = 0x00038021,
-+ VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
-+ VCMSG_SET_RELEASE_BUFFER = 0x00048001,
-+ VCMSG_SET_BLANK_SCREEN = 0x00040002,
-+ VCMSG_TST_BLANK_SCREEN = 0x00044002,
-+ VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
-+ VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
-+ VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
-+ VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
-+ VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
-+ VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
-+ VCMSG_GET_DEPTH = 0x00040005,
-+ VCMSG_TST_DEPTH = 0x00044005,
-+ VCMSG_SET_DEPTH = 0x00048005,
-+ VCMSG_GET_PIXEL_ORDER = 0x00040006,
-+ VCMSG_TST_PIXEL_ORDER = 0x00044006,
-+ VCMSG_SET_PIXEL_ORDER = 0x00048006,
-+ VCMSG_GET_ALPHA_MODE = 0x00040007,
-+ VCMSG_TST_ALPHA_MODE = 0x00044007,
-+ VCMSG_SET_ALPHA_MODE = 0x00048007,
-+ VCMSG_GET_PITCH = 0x00040008,
-+ VCMSG_TST_PITCH = 0x00044008,
-+ VCMSG_SET_PITCH = 0x00048008,
-+ VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
-+ VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
-+ VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
-+ VCMSG_GET_OVERSCAN = 0x0004000a,
-+ VCMSG_TST_OVERSCAN = 0x0004400a,
-+ VCMSG_SET_OVERSCAN = 0x0004800a,
-+ VCMSG_GET_PALETTE = 0x0004000b,
-+ VCMSG_TST_PALETTE = 0x0004400b,
-+ VCMSG_SET_PALETTE = 0x0004800b,
-+ VCMSG_GET_LAYER = 0x0004000c,
-+ VCMSG_TST_LAYER = 0x0004400c,
-+ VCMSG_SET_LAYER = 0x0004800c,
-+ VCMSG_GET_TRANSFORM = 0x0004000d,
-+ VCMSG_TST_TRANSFORM = 0x0004400d,
-+ VCMSG_SET_TRANSFORM = 0x0004800d,
-+ VCMSG_TST_VSYNC = 0x0004400e,
-+ VCMSG_SET_VSYNC = 0x0004800e,
-+ VCMSG_SET_CURSOR_INFO = 0x00008010,
-+ VCMSG_SET_CURSOR_STATE = 0x00008011,
-+};
-+
-+extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
-+extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
-+extern int /*rc*/ bcm_mailbox_property(void *data, int size);
-+
-+#include <linux/ioctl.h>
-+
-+/*
-+ * The major device number. We can't rely on dynamic
-+ * registration any more, because ioctls need to know
-+ * it.
-+ */
-+#define MAJOR_NUM 100
-+
-+/*
-+ * Set the message of the device driver
-+ */
-+#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
-+/*
-+ * _IOWR means that we're creating an ioctl command
-+ * number for passing information from a user process
-+ * to the kernel module and from the kernel module to user process
-+ *
-+ * The first arguments, MAJOR_NUM, is the major device
-+ * number we're using.
-+ *
-+ * The second argument is the number of the command
-+ * (there could be several with different meanings).
-+ *
-+ * The third argument is the type we want to get from
-+ * the process to the kernel.
-+ */
-+
-+/*
-+ * The name of the device file
-+ */
-+#define DEVICE_FILE_NAME "vcio"
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_mem.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_mem.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_mem.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,35 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#if !defined( VC_MEM_H )
-+#define VC_MEM_H
-+
-+#include <linux/ioctl.h>
-+
-+#define VC_MEM_IOC_MAGIC 'v'
-+
-+#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
-+#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
-+#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
-+#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
-+
-+#if defined( __KERNEL__ )
-+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
-+
-+extern unsigned long mm_vc_mem_phys_addr;
-+extern unsigned int mm_vc_mem_size;
-+extern int vc_mem_get_current_size( void );
-+#endif
-+
-+#endif /* VC_MEM_H */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,181 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __VC_SM_DEFS_H__INCLUDED__
-+#define __VC_SM_DEFS_H__INCLUDED__
-+
-+/* FourCC code used for VCHI connection */
-+#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM")
-+
-+/* Maximum message length */
-+#define VC_SM_MAX_MSG_LEN (sizeof(VC_SM_MSG_UNION_T) + \
-+ sizeof(VC_SM_MSG_HDR_T))
-+#define VC_SM_MAX_RSP_LEN (sizeof(VC_SM_MSG_UNION_T))
-+
-+/* Resource name maximum size */
-+#define VC_SM_RESOURCE_NAME 32
-+
-+/* All message types supported for HOST->VC direction */
-+typedef enum {
-+ /* Allocate shared memory block */
-+ VC_SM_MSG_TYPE_ALLOC,
-+ /* Lock allocated shared memory block */
-+ VC_SM_MSG_TYPE_LOCK,
-+ /* Unlock allocated shared memory block */
-+ VC_SM_MSG_TYPE_UNLOCK,
-+ /* Unlock allocated shared memory block, do not answer command */
-+ VC_SM_MSG_TYPE_UNLOCK_NOANS,
-+ /* Free shared memory block */
-+ VC_SM_MSG_TYPE_FREE,
-+ /* Resize a shared memory block */
-+ VC_SM_MSG_TYPE_RESIZE,
-+ /* Walk the allocated shared memory block(s) */
-+ VC_SM_MSG_TYPE_WALK_ALLOC,
-+
-+ /* A previously applied action will need to be reverted */
-+ VC_SM_MSG_TYPE_ACTION_CLEAN,
-+ VC_SM_MSG_TYPE_MAX
-+} VC_SM_MSG_TYPE;
-+
-+/* Type of memory to be allocated */
-+typedef enum {
-+ VC_SM_ALLOC_CACHED,
-+ VC_SM_ALLOC_NON_CACHED,
-+
-+} VC_SM_ALLOC_TYPE_T;
-+
-+/* Message header for all messages in HOST->VC direction */
-+typedef struct {
-+ int32_t type;
-+ uint32_t trans_id;
-+ uint8_t body[0];
-+
-+} VC_SM_MSG_HDR_T;
-+
-+/* Request to allocate memory (HOST->VC) */
-+typedef struct {
-+ /* type of memory to allocate */
-+ VC_SM_ALLOC_TYPE_T type;
-+ /* byte amount of data to allocate per unit */
-+ uint32_t base_unit;
-+ /* number of unit to allocate */
-+ uint32_t num_unit;
-+ /* alignement to be applied on allocation */
-+ uint32_t alignement;
-+ /* identity of who allocated this block */
-+ uint32_t allocator;
-+ /* resource name (for easier tracking on vc side) */
-+ char name[VC_SM_RESOURCE_NAME];
-+
-+} VC_SM_ALLOC_T;
-+
-+/* Result of a requested memory allocation (VC->HOST) */
-+typedef struct {
-+ /* Transaction identifier */
-+ uint32_t trans_id;
-+
-+ /* Resource handle */
-+ uint32_t res_handle;
-+ /* Pointer to resource buffer */
-+ void *res_mem;
-+ /* Resource base size (bytes) */
-+ uint32_t res_base_size;
-+ /* Resource number */
-+ uint32_t res_num;
-+
-+} VC_SM_ALLOC_RESULT_T;
-+
-+/* Request to free a previously allocated memory (HOST->VC) */
-+typedef struct {
-+ /* Resource handle (returned from alloc) */
-+ uint32_t res_handle;
-+ /* Resource buffer (returned from alloc) */
-+ void *res_mem;
-+
-+} VC_SM_FREE_T;
-+
-+/* Request to lock a previously allocated memory (HOST->VC) */
-+typedef struct {
-+ /* Resource handle (returned from alloc) */
-+ uint32_t res_handle;
-+ /* Resource buffer (returned from alloc) */
-+ void *res_mem;
-+
-+} VC_SM_LOCK_UNLOCK_T;
-+
-+/* Request to resize a previously allocated memory (HOST->VC) */
-+typedef struct {
-+ /* Resource handle (returned from alloc) */
-+ uint32_t res_handle;
-+ /* Resource buffer (returned from alloc) */
-+ void *res_mem;
-+ /* Resource *new* size requested (bytes) */
-+ uint32_t res_new_size;
-+
-+} VC_SM_RESIZE_T;
-+
-+/* Result of a requested memory lock (VC->HOST) */
-+typedef struct {
-+ /* Transaction identifier */
-+ uint32_t trans_id;
-+
-+ /* Resource handle */
-+ uint32_t res_handle;
-+ /* Pointer to resource buffer */
-+ void *res_mem;
-+ /* Pointer to former resource buffer if the memory
-+ * was reallocated */
-+ void *res_old_mem;
-+
-+} VC_SM_LOCK_RESULT_T;
-+
-+/* Generic result for a request (VC->HOST) */
-+typedef struct {
-+ /* Transaction identifier */
-+ uint32_t trans_id;
-+
-+ int32_t success;
-+
-+} VC_SM_RESULT_T;
-+
-+/* Request to revert a previously applied action (HOST->VC) */
-+typedef struct {
-+ /* Action of interest */
-+ VC_SM_MSG_TYPE res_action;
-+ /* Transaction identifier for the action of interest */
-+ uint32_t action_trans_id;
-+
-+} VC_SM_ACTION_CLEAN_T;
-+
-+/* Request to remove all data associated with a given allocator (HOST->VC) */
-+typedef struct {
-+ /* Allocator identifier */
-+ uint32_t allocator;
-+
-+} VC_SM_FREE_ALL_T;
-+
-+/* Union of ALL messages */
-+typedef union {
-+ VC_SM_ALLOC_T alloc;
-+ VC_SM_ALLOC_RESULT_T alloc_result;
-+ VC_SM_FREE_T free;
-+ VC_SM_ACTION_CLEAN_T action_clean;
-+ VC_SM_RESIZE_T resize;
-+ VC_SM_LOCK_RESULT_T lock_result;
-+ VC_SM_RESULT_T result;
-+ VC_SM_FREE_ALL_T free_all;
-+
-+} VC_SM_MSG_UNION_T;
-+
-+#endif /* __VC_SM_DEFS_H__INCLUDED__ */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,55 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __VC_SM_KNL_H__INCLUDED__
-+#define __VC_SM_KNL_H__INCLUDED__
-+
-+#if !defined(__KERNEL__)
-+#error "This interface is for kernel use only..."
-+#endif
-+
-+/* Type of memory to be locked (ie mapped) */
-+typedef enum {
-+ VC_SM_LOCK_CACHED,
-+ VC_SM_LOCK_NON_CACHED,
-+
-+} VC_SM_LOCK_CACHE_MODE_T;
-+
-+/* Allocate a shared memory handle and block.
-+*/
-+int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle);
-+
-+/* Free a previously allocated shared memory handle and block.
-+*/
-+int vc_sm_free(int handle);
-+
-+/* Lock a memory handle for use by kernel.
-+*/
-+int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data);
-+
-+/* Unlock a memory handle in use by kernel.
-+*/
-+int vc_sm_unlock(int handle, int flush, int no_vc_unlock);
-+
-+/* Get an internal resource handle mapped from the external one.
-+*/
-+int vc_sm_int_handle(int handle);
-+
-+/* Map a shared memory region for use by kernel.
-+*/
-+int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data);
-+
-+#endif /* __VC_SM_KNL_H__INCLUDED__ */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,82 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __VC_VCHI_SM_H__INCLUDED__
-+#define __VC_VCHI_SM_H__INCLUDED__
-+
-+#include "interface/vchi/vchi.h"
-+
-+#include "vc_sm_defs.h"
-+
-+/* Forward declare.
-+*/
-+typedef struct sm_instance *VC_VCHI_SM_HANDLE_T;
-+
-+/* Initialize the shared memory service, opens up vchi connection to talk to it.
-+*/
-+VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
-+ VCHI_CONNECTION_T **vchi_connections,
-+ uint32_t num_connections);
-+
-+/* Terminates the shared memory service.
-+*/
-+int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle);
-+
-+/* Ask the shared memory service to allocate some memory on videocre and
-+** return the result of this allocation (which upon success will be a pointer
-+** to some memory in videocore space).
-+*/
-+int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_ALLOC_T *alloc,
-+ VC_SM_ALLOC_RESULT_T *alloc_result, uint32_t *trans_id);
-+
-+/* Ask the shared memory service to free up some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_FREE_T *free, uint32_t *trans_id);
-+
-+/* Ask the shared memory service to lock up some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *lock_unlock,
-+ VC_SM_LOCK_RESULT_T *lock_result, uint32_t *trans_id);
-+
-+/* Ask the shared memory service to unlock some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *lock_unlock,
-+ uint32_t *trans_id, uint8_t wait_reply);
-+
-+/* Ask the shared memory service to resize some memory that was previously
-+** allocated by the vc_vchi_sm_alloc function call.
-+*/
-+int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_RESIZE_T *resize, uint32_t *trans_id);
-+
-+/* Walk the allocated resources on the videocore side, the allocation will
-+** show up in the log. This is purely for debug/information and takes no
-+** specific actions.
-+*/
-+int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle);
-+
-+/* Clean up following a previously interrupted action which left the system
-+** in a bad state of some sort.
-+*/
-+int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_ACTION_CLEAN_T *action_clean);
-+
-+#endif /* __VC_VCHI_SM_H__INCLUDED__ */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vmalloc.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,20 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#define VMALLOC_END (0xe8000000)
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h
---- linux-3.18.14/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,248 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*
-+*****************************************************************************/
-+
-+#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__)
-+#define __VMCS_SM_IOCTL_H__INCLUDED__
-+
-+/* ---- Include Files ---------------------------------------------------- */
-+
-+#if defined(__KERNEL__)
-+#include <linux/types.h> /* Needed for standard types */
-+#else
-+#include <stdint.h>
-+#endif
-+
-+#include <linux/ioctl.h>
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+#define VMCS_SM_RESOURCE_NAME 32
-+#define VMCS_SM_RESOURCE_NAME_DEFAULT "sm-host-resource"
-+
-+/* Type define used to create unique IOCTL number */
-+#define VMCS_SM_MAGIC_TYPE 'I'
-+
-+/* IOCTL commands */
-+enum vmcs_sm_cmd_e {
-+ VMCS_SM_CMD_ALLOC = 0x5A, /* Start at 0x5A arbitrarily */
-+ VMCS_SM_CMD_ALLOC_SHARE,
-+ VMCS_SM_CMD_LOCK,
-+ VMCS_SM_CMD_LOCK_CACHE,
-+ VMCS_SM_CMD_UNLOCK,
-+ VMCS_SM_CMD_RESIZE,
-+ VMCS_SM_CMD_UNMAP,
-+ VMCS_SM_CMD_FREE,
-+ VMCS_SM_CMD_FLUSH,
-+ VMCS_SM_CMD_INVALID,
-+
-+ VMCS_SM_CMD_SIZE_USR_HANDLE,
-+ VMCS_SM_CMD_CHK_USR_HANDLE,
-+
-+ VMCS_SM_CMD_MAPPED_USR_HANDLE,
-+ VMCS_SM_CMD_MAPPED_USR_ADDRESS,
-+ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,
-+ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,
-+ VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,
-+
-+ VMCS_SM_CMD_VC_WALK_ALLOC,
-+ VMCS_SM_CMD_HOST_WALK_MAP,
-+ VMCS_SM_CMD_HOST_WALK_PID_ALLOC,
-+ VMCS_SM_CMD_HOST_WALK_PID_MAP,
-+
-+ VMCS_SM_CMD_CLEAN_INVALID,
-+
-+ VMCS_SM_CMD_LAST /* Do no delete */
-+};
-+
-+/* Cache type supported, conveniently matches the user space definition in
-+** user-vcsm.h.
-+*/
-+enum vmcs_sm_cache_e {
-+ VMCS_SM_CACHE_NONE,
-+ VMCS_SM_CACHE_HOST,
-+ VMCS_SM_CACHE_VC,
-+ VMCS_SM_CACHE_BOTH,
-+};
-+
-+/* IOCTL Data structures */
-+struct vmcs_sm_ioctl_alloc {
-+ /* user -> kernel */
-+ unsigned int size;
-+ unsigned int num;
-+ enum vmcs_sm_cache_e cached;
-+ char name[VMCS_SM_RESOURCE_NAME];
-+
-+ /* kernel -> user */
-+ unsigned int handle;
-+ /* unsigned int base_addr; */
-+};
-+
-+struct vmcs_sm_ioctl_alloc_share {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_free {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ /* unsigned int base_addr; */
-+};
-+
-+struct vmcs_sm_ioctl_lock_unlock {
-+ /* user -> kernel */
-+ unsigned int handle;
-+
-+ /* kernel -> user */
-+ unsigned int addr;
-+};
-+
-+struct vmcs_sm_ioctl_lock_cache {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ enum vmcs_sm_cache_e cached;
-+};
-+
-+struct vmcs_sm_ioctl_resize {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ unsigned int new_size;
-+
-+ /* kernel -> user */
-+ unsigned int old_size;
-+};
-+
-+struct vmcs_sm_ioctl_map {
-+ /* user -> kernel */
-+ /* and kernel -> user */
-+ unsigned int pid;
-+ unsigned int handle;
-+ unsigned int addr;
-+
-+ /* kernel -> user */
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_walk {
-+ /* user -> kernel */
-+ unsigned int pid;
-+};
-+
-+struct vmcs_sm_ioctl_chk {
-+ /* user -> kernel */
-+ unsigned int handle;
-+
-+ /* kernel -> user */
-+ unsigned int addr;
-+ unsigned int size;
-+ enum vmcs_sm_cache_e cache;
-+};
-+
-+struct vmcs_sm_ioctl_size {
-+ /* user -> kernel */
-+ unsigned int handle;
-+
-+ /* kernel -> user */
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_cache {
-+ /* user -> kernel */
-+ unsigned int handle;
-+ unsigned int addr;
-+ unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_clean_invalid {
-+ /* user -> kernel */
-+ struct {
-+ unsigned int cmd;
-+ unsigned int handle;
-+ unsigned int addr;
-+ unsigned int size;
-+ } s[8];
-+};
-+
-+/* IOCTL numbers */
-+#define VMCS_SM_IOCTL_MEM_ALLOC\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\
-+ struct vmcs_sm_ioctl_alloc)
-+#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\
-+ struct vmcs_sm_ioctl_alloc_share)
-+#define VMCS_SM_IOCTL_MEM_LOCK\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\
-+ struct vmcs_sm_ioctl_lock_unlock)
-+#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\
-+ struct vmcs_sm_ioctl_lock_cache)
-+#define VMCS_SM_IOCTL_MEM_UNLOCK\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\
-+ struct vmcs_sm_ioctl_lock_unlock)
-+#define VMCS_SM_IOCTL_MEM_RESIZE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\
-+ struct vmcs_sm_ioctl_resize)
-+#define VMCS_SM_IOCTL_MEM_FREE\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\
-+ struct vmcs_sm_ioctl_free)
-+#define VMCS_SM_IOCTL_MEM_FLUSH\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\
-+ struct vmcs_sm_ioctl_cache)
-+#define VMCS_SM_IOCTL_MEM_INVALID\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\
-+ struct vmcs_sm_ioctl_cache)
-+#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID,\
-+ struct vmcs_sm_ioctl_clean_invalid)
-+
-+#define VMCS_SM_IOCTL_SIZE_USR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\
-+ struct vmcs_sm_ioctl_size)
-+#define VMCS_SM_IOCTL_CHK_USR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\
-+ struct vmcs_sm_ioctl_chk)
-+
-+#define VMCS_SM_IOCTL_MAP_USR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\
-+ struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\
-+ struct vmcs_sm_ioctl_map)
-+
-+#define VMCS_SM_IOCTL_VC_WALK_ALLOC\
-+ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC)
-+#define VMCS_SM_IOCTL_HOST_WALK_MAP\
-+ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP)
-+#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\
-+ struct vmcs_sm_ioctl_walk)
-+#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\
-+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\
-+ struct vmcs_sm_ioctl_walk)
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/Kconfig linux-rpi/arch/arm/mach-bcm2708/Kconfig
---- linux-3.18.14/arch/arm/mach-bcm2708/Kconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/Kconfig 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,52 @@
-+menu "Broadcom BCM2708 Implementations"
-+ depends on ARCH_BCM2708
-+
-+config MACH_BCM2708
-+ bool "Broadcom BCM2708 Development Platform"
-+ select NEED_MACH_MEMORY_H
-+ select NEED_MACH_IO_H
-+ select CPU_V6
-+ help
-+ Include support for the Broadcom(R) BCM2708 platform.
-+
-+config BCM2708_DT
-+ bool "BCM2708 Device Tree support"
-+ depends on MACH_BCM2708
-+ default n
-+ select USE_OF
-+ select ARCH_REQUIRE_GPIOLIB
-+ select PINCTRL
-+ select PINCTRL_BCM2835
-+ help
-+ Enable Device Tree support for BCM2708
-+
-+config BCM2708_GPIO
-+ bool "BCM2708 gpio support"
-+ depends on MACH_BCM2708
-+ select ARCH_REQUIRE_GPIOLIB
-+ default y
-+ help
-+ Include support for the Broadcom(R) BCM2708 gpio.
-+
-+config BCM2708_VCMEM
-+ bool "Videocore Memory"
-+ depends on MACH_BCM2708
-+ default y
-+ help
-+ Helper for videocore memory access and total size allocation.
-+
-+config BCM2708_NOL2CACHE
-+ bool "Videocore L2 cache disable"
-+ depends on MACH_BCM2708
-+ default n
-+ help
-+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
-+
-+config BCM2708_SPIDEV
-+ bool "Bind spidev to SPI0 master"
-+ depends on MACH_BCM2708
-+ depends on SPI
-+ default y
-+ help
-+ Binds spidev driver to the SPI0 master
-+endmenu
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/Makefile linux-rpi/arch/arm/mach-bcm2708/Makefile
---- linux-3.18.14/arch/arm/mach-bcm2708/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/Makefile 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,7 @@
-+#
-+# Makefile for the linux kernel.
-+#
-+
-+obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o vcio.o power.o dma.o
-+obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
-+obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/Makefile.boot linux-rpi/arch/arm/mach-bcm2708/Makefile.boot
---- linux-3.18.14/arch/arm/mach-bcm2708/Makefile.boot 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/Makefile.boot 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,3 @@
-+ zreladdr-y := 0x00008000
-+params_phys-y := 0x00000100
-+initrd_phys-y := 0x00800000
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/power.c linux-rpi/arch/arm/mach-bcm2708/power.c
---- linux-3.18.14/arch/arm/mach-bcm2708/power.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/power.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,197 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/power.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for controlling the power to
-+ * VideoCore subsystems.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/semaphore.h>
-+#include <linux/bug.h>
-+#include <mach/power.h>
-+#include <mach/vcio.h>
-+#include <mach/arm_power.h>
-+
-+#define DRIVER_NAME "bcm2708_power"
-+
-+#define BCM_POWER_MAXCLIENTS 4
-+#define BCM_POWER_NOCLIENT (1<<31)
-+
-+/* Some drivers expect there devices to be permanently powered */
-+
-+#ifdef CONFIG_USB
-+#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
-+#endif
-+
-+#if 1
-+#define DPRINTK printk
-+#else
-+#define DPRINTK if (0) printk
-+#endif
-+
-+struct state_struct {
-+ uint32_t global_request;
-+ uint32_t client_request[BCM_POWER_MAXCLIENTS];
-+ struct semaphore client_mutex;
-+ struct semaphore mutex;
-+} g_state;
-+
-+int bcm_power_open(BCM_POWER_HANDLE_T *handle)
-+{
-+ BCM_POWER_HANDLE_T i;
-+ int ret = -EBUSY;
-+
-+ down(&g_state.client_mutex);
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
-+ if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
-+ g_state.client_request[i] = BCM_POWER_NONE;
-+ *handle = i;
-+ ret = 0;
-+ break;
-+ }
-+ }
-+
-+ up(&g_state.client_mutex);
-+
-+ DPRINTK("bcm_power_open() -> %d\n", *handle);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_open);
-+
-+int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
-+{
-+ int rc = 0;
-+
-+ DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
-+
-+ if ((handle < BCM_POWER_MAXCLIENTS) &&
-+ (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
-+ if (down_interruptible(&g_state.mutex) != 0) {
-+ DPRINTK("bcm_power_request -> interrupted\n");
-+ return -EINTR;
-+ }
-+
-+ if (request != g_state.client_request[handle]) {
-+ uint32_t others_request = 0;
-+ uint32_t global_request;
-+ BCM_POWER_HANDLE_T i;
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
-+ if (i != handle)
-+ others_request |=
-+ g_state.client_request[i];
-+ }
-+ others_request &= ~BCM_POWER_NOCLIENT;
-+
-+ global_request = request | others_request;
-+ if (global_request != g_state.global_request) {
-+ uint32_t actual;
-+
-+ /* Send a request to VideoCore */
-+ bcm_mailbox_write(MBOX_CHAN_POWER,
-+ global_request << 4);
-+
-+ /* Wait for a response during power-up */
-+ if (global_request & ~g_state.global_request) {
-+ rc = bcm_mailbox_read(MBOX_CHAN_POWER,
-+ &actual);
-+ DPRINTK
-+ ("bcm_mailbox_read -> %08x, %d\n",
-+ actual, rc);
-+ actual >>= 4;
-+ } else {
-+ rc = 0;
-+ actual = global_request;
-+ }
-+
-+ if (rc == 0) {
-+ if (actual != global_request) {
-+ printk(KERN_ERR
-+ "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
-+ __func__,
-+ g_state.global_request,
-+ global_request, actual, request, others_request);
-+ /* A failure */
-+ BUG_ON((others_request & actual)
-+ != others_request);
-+ request &= actual;
-+ rc = -EIO;
-+ }
-+
-+ g_state.global_request = actual;
-+ g_state.client_request[handle] =
-+ request;
-+ }
-+ }
-+ }
-+ up(&g_state.mutex);
-+ } else {
-+ rc = -EINVAL;
-+ }
-+ DPRINTK("bcm_power_request -> %d\n", rc);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_request);
-+
-+int bcm_power_close(BCM_POWER_HANDLE_T handle)
-+{
-+ int rc;
-+
-+ DPRINTK("bcm_power_close(%d)\n", handle);
-+
-+ rc = bcm_power_request(handle, BCM_POWER_NONE);
-+ if (rc == 0)
-+ g_state.client_request[handle] = BCM_POWER_NOCLIENT;
-+
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_close);
-+
-+static int __init bcm_power_init(void)
-+{
-+#if defined(BCM_POWER_ALWAYS_ON)
-+ BCM_POWER_HANDLE_T always_on_handle;
-+#endif
-+ int rc = 0;
-+ int i;
-+
-+ printk(KERN_INFO "bcm_power: Broadcom power driver\n");
-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0);
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
-+ g_state.client_request[i] = BCM_POWER_NOCLIENT;
-+
-+ sema_init(&g_state.client_mutex, 1);
-+ sema_init(&g_state.mutex, 1);
-+
-+ g_state.global_request = 0;
-+
-+#if defined(BCM_POWER_ALWAYS_ON)
-+ if (BCM_POWER_ALWAYS_ON) {
-+ bcm_power_open(&always_on_handle);
-+ bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
-+ }
-+#endif
-+
-+ return rc;
-+}
-+
-+static void __exit bcm_power_exit(void)
-+{
-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0);
-+}
-+
-+arch_initcall(bcm_power_init); /* Initialize early */
-+module_exit(bcm_power_exit);
-+
-+MODULE_AUTHOR("Phil Elwell");
-+MODULE_DESCRIPTION("Interface to BCM2708 power management");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/vcio.c linux-rpi/arch/arm/mach-bcm2708/vcio.c
---- linux-3.18.14/arch/arm/mach-bcm2708/vcio.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/vcio.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,484 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/vcio.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for writing to the mailboxes,
-+ * semaphores, doorbells etc. that are shared between the ARM and the
-+ * VideoCore processor
-+ */
-+
-+#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include <linux/module.h>
-+#include <linux/console.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+#include <linux/sysrq.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+
-+#include <linux/io.h>
-+
-+#include <mach/vcio.h>
-+#include <mach/platform.h>
-+
-+#include <asm/uaccess.h>
-+
-+
-+#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
-+
-+/* ----------------------------------------------------------------------
-+ * Mailbox
-+ * -------------------------------------------------------------------- */
-+
-+/* offsets from a mail box base address */
-+#define MAIL_WRT 0x00 /* write - and next 4 words */
-+#define MAIL_RD 0x00 /* read - and next 4 words */
-+#define MAIL_POL 0x10 /* read without popping the fifo */
-+#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
-+#define MAIL_STA 0x18 /* status */
-+#define MAIL_CNF 0x1C /* configuration */
-+
-+#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
-+#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
-+#define MBOX_CHAN(msg) ((msg) & 0xf)
-+#define MBOX_DATA28(msg) ((msg) & ~0xf)
-+#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
-+
-+#define MBOX_MAGIC 0xd0d0c0de
-+static struct class *vcio_class = NULL;
-+struct vc_mailbox {
-+ struct device *dev; /* parent device */
-+ void __iomem *status;
-+ void __iomem *config;
-+ void __iomem *read;
-+ void __iomem *write;
-+ uint32_t msg[MBOX_CHAN_COUNT];
-+ struct semaphore sema[MBOX_CHAN_COUNT];
-+ uint32_t magic;
-+};
-+
-+static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
-+ uint32_t addr_mbox)
-+{
-+ int i;
-+
-+ mbox_out->dev = dev;
-+ mbox_out->status = __io_address(addr_mbox + MAIL_STA);
-+ mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
-+ mbox_out->read = __io_address(addr_mbox + MAIL_RD);
-+ /* Write to the other mailbox */
-+ mbox_out->write =
-+ __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
-+ MAIL_WRT);
-+
-+ for (i = 0; i < MBOX_CHAN_COUNT; i++) {
-+ mbox_out->msg[i] = 0;
-+ sema_init(&mbox_out->sema[i], 0);
-+ }
-+
-+ /* Enable the interrupt on data reception */
-+ writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
-+
-+ mbox_out->magic = MBOX_MAGIC;
-+}
-+
-+static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
-+{
-+ int rc;
-+
-+ if (mbox->magic != MBOX_MAGIC)
-+ rc = -EINVAL;
-+ else {
-+ /* wait for the mailbox FIFO to have some space in it */
-+ while (0 != (readl(mbox->status) & ARM_MS_FULL))
-+ cpu_relax();
-+
-+ writel(MBOX_MSG(chan, data28), mbox->write);
-+ rc = 0;
-+ }
-+ return rc;
-+}
-+
-+static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
-+{
-+ int rc;
-+
-+ if (mbox->magic != MBOX_MAGIC)
-+ rc = -EINVAL;
-+ else {
-+ down(&mbox->sema[chan]);
-+ *data28 = MBOX_DATA28(mbox->msg[chan]);
-+ mbox->msg[chan] = 0;
-+ rc = 0;
-+ }
-+ return rc;
-+}
-+
-+static irqreturn_t mbox_irq(int irq, void *dev_id)
-+{
-+ /* wait for the mailbox FIFO to have some data in it */
-+ struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
-+ int status = readl(mbox->status);
-+ int ret = IRQ_NONE;
-+
-+ while (!(status & ARM_MS_EMPTY)) {
-+ uint32_t msg = readl(mbox->read);
-+ int chan = MBOX_CHAN(msg);
-+ if (chan < MBOX_CHAN_COUNT) {
-+ if (mbox->msg[chan]) {
-+ /* Overflow */
-+ printk(KERN_ERR DRIVER_NAME
-+ ": mbox chan %d overflow - drop %08x\n",
-+ chan, msg);
-+ } else {
-+ mbox->msg[chan] = (msg | 0xf);
-+ up(&mbox->sema[chan]);
-+ }
-+ } else {
-+ printk(KERN_ERR DRIVER_NAME
-+ ": invalid channel selector (msg %08x)\n", msg);
-+ }
-+ ret = IRQ_HANDLED;
-+ status = readl(mbox->status);
-+ }
-+ return ret;
-+}
-+
-+static struct irqaction mbox_irqaction = {
-+ .name = "ARM Mailbox IRQ",
-+ .flags = IRQF_DISABLED | IRQF_IRQPOLL,
-+ .handler = mbox_irq,
-+};
-+
-+/* ----------------------------------------------------------------------
-+ * Mailbox Methods
-+ * -------------------------------------------------------------------- */
-+
-+static struct device *mbox_dev; /* we assume there's only one! */
-+
-+static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
-+{
-+ int rc;
-+
-+ struct vc_mailbox *mailbox = dev_get_drvdata(dev);
-+ device_lock(dev);
-+ rc = mbox_write(mailbox, chan, data28);
-+ device_unlock(dev);
-+
-+ return rc;
-+}
-+
-+static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
-+{
-+ int rc;
-+
-+ struct vc_mailbox *mailbox = dev_get_drvdata(dev);
-+ device_lock(dev);
-+ rc = mbox_read(mailbox, chan, data28);
-+ device_unlock(dev);
-+
-+ return rc;
-+}
-+
-+extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
-+{
-+ if (mbox_dev)
-+ return dev_mbox_write(mbox_dev, chan, data28);
-+ else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_write);
-+
-+extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
-+{
-+ if (mbox_dev)
-+ return dev_mbox_read(mbox_dev, chan, data28);
-+ else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_read);
-+
-+static void dev_mbox_register(const char *dev_name, struct device *dev)
-+{
-+ mbox_dev = dev;
-+}
-+
-+static int mbox_copy_from_user(void *dst, const void *src, int size)
-+{
-+ if ( (uint32_t)src < TASK_SIZE)
-+ {
-+ return copy_from_user(dst, src, size);
-+ }
-+ else
-+ {
-+ memcpy( dst, src, size );
-+ return 0;
-+ }
-+}
-+
-+static int mbox_copy_to_user(void *dst, const void *src, int size)
-+{
-+ if ( (uint32_t)dst < TASK_SIZE)
-+ {
-+ return copy_to_user(dst, src, size);
-+ }
-+ else
-+ {
-+ memcpy( dst, src, size );
-+ return 0;
-+ }
-+}
-+
-+static DEFINE_MUTEX(mailbox_lock);
-+extern int bcm_mailbox_property(void *data, int size)
-+{
-+ uint32_t success;
-+ dma_addr_t mem_bus; /* the memory address accessed from videocore */
-+ void *mem_kern; /* the memory address accessed from driver */
-+ int s = 0;
-+
-+ mutex_lock(&mailbox_lock);
-+ /* allocate some memory for the messages communicating with GPU */
-+ mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
-+ if (mem_kern) {
-+ /* create the message */
-+ mbox_copy_from_user(mem_kern, data, size);
-+
-+ /* send the message */
-+ wmb();
-+ s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
-+ if (s == 0) {
-+ s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
-+ }
-+ if (s == 0) {
-+ /* copy the response */
-+ rmb();
-+ mbox_copy_to_user(data, mem_kern, size);
-+ }
-+ dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
-+ } else {
-+ s = -ENOMEM;
-+ }
-+ if (s != 0)
-+ printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
-+
-+ mutex_unlock(&mailbox_lock);
-+ return s;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_property);
-+
-+/* ----------------------------------------------------------------------
-+ * Platform Device for Mailbox
-+ * -------------------------------------------------------------------- */
-+
-+/*
-+ * Is the device open right now? Used to prevent
-+ * concurent access into the same device
-+ */
-+static int Device_Open = 0;
-+
-+/*
-+ * This is called whenever a process attempts to open the device file
-+ */
-+static int device_open(struct inode *inode, struct file *file)
-+{
-+ /*
-+ * We don't want to talk to two processes at the same time
-+ */
-+ if (Device_Open)
-+ return -EBUSY;
-+
-+ Device_Open++;
-+ /*
-+ * Initialize the message
-+ */
-+ try_module_get(THIS_MODULE);
-+ return 0;
-+}
-+
-+static int device_release(struct inode *inode, struct file *file)
-+{
-+ /*
-+ * We're now ready for our next caller
-+ */
-+ Device_Open--;
-+
-+ module_put(THIS_MODULE);
-+ return 0;
-+}
-+
-+/*
-+ * This function is called whenever a process tries to do an ioctl on our
-+ * device file. We get two extra parameters (additional to the inode and file
-+ * structures, which all device functions get): the number of the ioctl called
-+ * and the parameter given to the ioctl function.
-+ *
-+ * If the ioctl is write or read/write (meaning output is returned to the
-+ * calling process), the ioctl call returns the output of this function.
-+ *
-+ */
-+static long device_ioctl(struct file *file, /* see include/linux/fs.h */
-+ unsigned int ioctl_num, /* number and param for ioctl */
-+ unsigned long ioctl_param)
-+{
-+ unsigned size;
-+ /*
-+ * Switch according to the ioctl called
-+ */
-+ switch (ioctl_num) {
-+ case IOCTL_MBOX_PROPERTY:
-+ /*
-+ * Receive a pointer to a message (in user space) and set that
-+ * to be the device's message. Get the parameter given to
-+ * ioctl by the process.
-+ */
-+ mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
-+ return bcm_mailbox_property((void *)ioctl_param, size);
-+ break;
-+ default:
-+ printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/* Module Declarations */
-+
-+/*
-+ * This structure will hold the functions to be called
-+ * when a process does something to the device we
-+ * created. Since a pointer to this structure is kept in
-+ * the devices table, it can't be local to
-+ * init_module. NULL is for unimplemented functios.
-+ */
-+struct file_operations fops = {
-+ .unlocked_ioctl = device_ioctl,
-+ .open = device_open,
-+ .release = device_release, /* a.k.a. close */
-+};
-+
-+static int bcm_vcio_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+ struct vc_mailbox *mailbox;
-+
-+ mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
-+ if (NULL == mailbox) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "mailbox memory\n");
-+ ret = -ENOMEM;
-+ } else {
-+ struct resource *res;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (res == NULL) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
-+ "resource\n");
-+ ret = -ENODEV;
-+ kfree(mailbox);
-+ } else {
-+ /* should be based on the registers from res really */
-+ mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
-+
-+ platform_set_drvdata(pdev, mailbox);
-+ dev_mbox_register(DRIVER_NAME, &pdev->dev);
-+
-+ mbox_irqaction.dev_id = mailbox;
-+ setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
-+ printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
-+ __io_address(ARM_0_MAIL0_RD));
-+ }
-+ }
-+
-+ if (ret == 0) {
-+ /*
-+ * Register the character device
-+ */
-+ ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
-+
-+ /*
-+ * Negative values signify an error
-+ */
-+ if (ret < 0) {
-+ printk(KERN_ERR DRIVER_NAME
-+ "Failed registering the character device %d\n", ret);
-+ return ret;
-+ }
-+ vcio_class = class_create(THIS_MODULE, BCM_VCIO_DRIVER_NAME);
-+ if (IS_ERR(vcio_class)) {
-+ ret = PTR_ERR(vcio_class);
-+ return ret ;
-+ }
-+ device_create(vcio_class, NULL, MKDEV(MAJOR_NUM, 0), NULL,
-+ "vcio");
-+ }
-+ return ret;
-+}
-+
-+static int bcm_vcio_remove(struct platform_device *pdev)
-+{
-+ struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(mailbox);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm_mbox_driver = {
-+ .probe = bcm_vcio_probe,
-+ .remove = bcm_vcio_remove,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init bcm_mbox_init(void)
-+{
-+ int ret;
-+
-+ printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
-+
-+ ret = platform_driver_register(&bcm_mbox_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to register "
-+ "on platform\n");
-+ }
-+
-+ return ret;
-+}
-+
-+static void __exit bcm_mbox_exit(void)
-+{
-+ device_destroy(vcio_class,MKDEV(MAJOR_NUM, 0));
-+ class_destroy(vcio_class);
-+ unregister_chrdev(MAJOR_NUM, DEVICE_FILE_NAME);
-+ platform_driver_unregister(&bcm_mbox_driver);
-+}
-+
-+arch_initcall(bcm_mbox_init); /* Initialize early */
-+module_exit(bcm_mbox_exit);
-+
-+MODULE_AUTHOR("Gray Girling");
-+MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:bcm-mbox");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2708/vc_mem.c linux-rpi/arch/arm/mach-bcm2708/vc_mem.c
---- linux-3.18.14/arch/arm/mach-bcm2708/vc_mem.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2708/vc_mem.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,432 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/debugfs.h>
-+#include <asm/uaccess.h>
-+#include <linux/dma-mapping.h>
-+
-+#ifdef CONFIG_ARCH_KONA
-+#include <chal/chal_ipc.h>
-+#elif CONFIG_ARCH_BCM2708
-+#else
-+#include <csp/chal_ipc.h>
-+#endif
-+
-+#include "mach/vc_mem.h"
-+#include <mach/vcio.h>
-+
-+#define DRIVER_NAME "vc-mem"
-+
-+// Device (/dev) related variables
-+static dev_t vc_mem_devnum = 0;
-+static struct class *vc_mem_class = NULL;
-+static struct cdev vc_mem_cdev;
-+static int vc_mem_inited = 0;
-+
-+#ifdef CONFIG_DEBUG_FS
-+static struct dentry *vc_mem_debugfs_entry;
-+#endif
-+
-+/*
-+ * Videocore memory addresses and size
-+ *
-+ * Drivers that wish to know the videocore memory addresses and sizes should
-+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
-+ * headers. This allows the other drivers to not be tied down to a a certain
-+ * address/size at compile time.
-+ *
-+ * In the future, the goal is to have the videocore memory virtual address and
-+ * size be calculated at boot time rather than at compile time. The decision of
-+ * where the videocore memory resides and its size would be in the hands of the
-+ * bootloader (and/or kernel). When that happens, the values of these variables
-+ * would be calculated and assigned in the init function.
-+ */
-+// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
-+unsigned long mm_vc_mem_phys_addr = 0x00000000;
-+unsigned int mm_vc_mem_size = 0;
-+unsigned int mm_vc_mem_base = 0;
-+
-+EXPORT_SYMBOL(mm_vc_mem_phys_addr);
-+EXPORT_SYMBOL(mm_vc_mem_size);
-+EXPORT_SYMBOL(mm_vc_mem_base);
-+
-+static uint phys_addr = 0;
-+static uint mem_size = 0;
-+static uint mem_base = 0;
-+
-+
-+/****************************************************************************
-+*
-+* vc_mem_open
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_open(struct inode *inode, struct file *file)
-+{
-+ (void) inode;
-+ (void) file;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_release
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_release(struct inode *inode, struct file *file)
-+{
-+ (void) inode;
-+ (void) file;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_size
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_size(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_base
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_base(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_current_size
-+*
-+***************************************************************************/
-+
-+int
-+vc_mem_get_current_size(void)
-+{
-+ return mm_vc_mem_size;
-+}
-+
-+EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
-+
-+/****************************************************************************
-+*
-+* vc_mem_ioctl
-+*
-+***************************************************************************/
-+
-+static long
-+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int rc = 0;
-+
-+ (void) cmd;
-+ (void) arg;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ switch (cmd) {
-+ case VC_MEM_IOC_MEM_PHYS_ADDR:
-+ {
-+ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
-+ __func__, (void *) mm_vc_mem_phys_addr);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
-+ sizeof (mm_vc_mem_phys_addr)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_SIZE:
-+ {
-+ // Get the videocore memory size first
-+ vc_mem_get_size();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
-+ mm_vc_mem_size);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_size,
-+ sizeof (mm_vc_mem_size)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_BASE:
-+ {
-+ // Get the videocore memory base
-+ vc_mem_get_base();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
-+ mm_vc_mem_base);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+ sizeof (mm_vc_mem_base)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_LOAD:
-+ {
-+ // Get the videocore memory base
-+ vc_mem_get_base();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
-+ mm_vc_mem_base);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+ sizeof (mm_vc_mem_base)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ default:
-+ {
-+ return -ENOTTY;
-+ }
-+ }
-+ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_mmap
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+ int rc = 0;
-+ unsigned long length = vma->vm_end - vma->vm_start;
-+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
-+
-+ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
-+ __func__, (long) vma->vm_start, (long) vma->vm_end,
-+ (long) vma->vm_pgoff);
-+
-+ if (offset + length > mm_vc_mem_size) {
-+ pr_err("%s: length %ld is too big\n", __func__, length);
-+ return -EINVAL;
-+ }
-+ // Do not cache the memory map
-+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+
-+ rc = remap_pfn_range(vma, vma->vm_start,
-+ (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
-+ vma->vm_pgoff, length, vma->vm_page_prot);
-+ if (rc != 0) {
-+ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
-+ }
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for the driver.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_mem_fops = {
-+ .owner = THIS_MODULE,
-+ .open = vc_mem_open,
-+ .release = vc_mem_release,
-+ .unlocked_ioctl = vc_mem_ioctl,
-+ .mmap = vc_mem_mmap,
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void vc_mem_debugfs_deinit(void)
-+{
-+ debugfs_remove_recursive(vc_mem_debugfs_entry);
-+ vc_mem_debugfs_entry = NULL;
-+}
-+
-+
-+static int vc_mem_debugfs_init(
-+ struct device *dev)
-+{
-+ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
-+ if (!vc_mem_debugfs_entry) {
-+ dev_warn(dev, "could not create debugfs entry\n");
-+ return -EFAULT;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_phys_addr",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_phys_addr)) {
-+ dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_size",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_size)) {
-+ dev_warn(dev, "%s:could not create vc_mem_size entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_base",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_base)) {
-+ dev_warn(dev, "%s:could not create vc_mem_base entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ return 0;
-+
-+fail:
-+ vc_mem_debugfs_deinit();
-+ return -EFAULT;
-+}
-+
-+#endif /* CONFIG_DEBUG_FS */
-+
-+
-+/****************************************************************************
-+*
-+* vc_mem_init
-+*
-+***************************************************************************/
-+
-+static int __init
-+vc_mem_init(void)
-+{
-+ int rc = -EFAULT;
-+ struct device *dev;
-+
-+ pr_debug("%s: called\n", __func__);
-+
-+ mm_vc_mem_phys_addr = phys_addr;
-+ mm_vc_mem_size = mem_size;
-+ mm_vc_mem_base = mem_base;
-+
-+ vc_mem_get_size();
-+
-+ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
-+ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
-+
-+ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
-+ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
-+ __func__, rc);
-+ goto out_err;
-+ }
-+
-+ cdev_init(&vc_mem_cdev, &vc_mem_fops);
-+ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
-+ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
-+ goto out_unregister;
-+ }
-+
-+ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
-+ if (IS_ERR(vc_mem_class)) {
-+ rc = PTR_ERR(vc_mem_class);
-+ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
-+ goto out_cdev_del;
-+ }
-+
-+ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
-+ DRIVER_NAME);
-+ if (IS_ERR(dev)) {
-+ rc = PTR_ERR(dev);
-+ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
-+ goto out_class_destroy;
-+ }
-+
-+#ifdef CONFIG_DEBUG_FS
-+ /* don't fail if the debug entries cannot be created */
-+ vc_mem_debugfs_init(dev);
-+#endif
-+
-+ vc_mem_inited = 1;
-+ return 0;
-+
-+ device_destroy(vc_mem_class, vc_mem_devnum);
-+
-+ out_class_destroy:
-+ class_destroy(vc_mem_class);
-+ vc_mem_class = NULL;
-+
-+ out_cdev_del:
-+ cdev_del(&vc_mem_cdev);
-+
-+ out_unregister:
-+ unregister_chrdev_region(vc_mem_devnum, 1);
-+
-+ out_err:
-+ return -1;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_exit
-+*
-+***************************************************************************/
-+
-+static void __exit
-+vc_mem_exit(void)
-+{
-+ pr_debug("%s: called\n", __func__);
-+
-+ if (vc_mem_inited) {
-+#if CONFIG_DEBUG_FS
-+ vc_mem_debugfs_deinit();
-+#endif
-+ device_destroy(vc_mem_class, vc_mem_devnum);
-+ class_destroy(vc_mem_class);
-+ cdev_del(&vc_mem_cdev);
-+ unregister_chrdev_region(vc_mem_devnum, 1);
-+ }
-+}
-+
-+module_init(vc_mem_init);
-+module_exit(vc_mem_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-+
-+module_param(phys_addr, uint, 0644);
-+module_param(mem_size, uint, 0644);
-+module_param(mem_base, uint, 0644);
-+
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/armctrl.c linux-rpi/arch/arm/mach-bcm2709/armctrl.c
---- linux-3.18.14/arch/arm/mach-bcm2709/armctrl.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/armctrl.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,369 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/armctrl.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/init.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/version.h>
-+#include <linux/syscore_ops.h>
-+#include <linux/interrupt.h>
-+#include <linux/irqdomain.h>
-+#include <linux/of.h>
-+
-+#include <asm/mach/irq.h>
-+#include <mach/hardware.h>
-+#include "armctrl.h"
-+
-+/* For support of kernels >= 3.0 assume only one VIC for now*/
-+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
-+ INTERRUPT_VC_JPEG,
-+ INTERRUPT_VC_USB,
-+ INTERRUPT_VC_3D,
-+ INTERRUPT_VC_DMA2,
-+ INTERRUPT_VC_DMA3,
-+ INTERRUPT_VC_I2C,
-+ INTERRUPT_VC_SPI,
-+ INTERRUPT_VC_I2SPCM,
-+ INTERRUPT_VC_SDIO,
-+ INTERRUPT_VC_UART,
-+ INTERRUPT_VC_ARASANSDIO
-+};
-+
-+static void armctrl_mask_irq(struct irq_data *d)
-+{
-+ static const unsigned int disables[4] = {
-+ ARM_IRQ_DIBL1,
-+ ARM_IRQ_DIBL2,
-+ ARM_IRQ_DIBL3,
-+ 0
-+ };
-+ int i;
-+ if (d->irq >= FIQ_START) {
-+ writel(0, __io_address(ARM_IRQ_FAST));
-+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
-+#if 1
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
-+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); //
-+ {
-+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
-+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
-+ }
-+#endif
-+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
-+#if 0
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
-+ for (i=0; i<4; i++) {
-+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
-+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
-+ }
-+#endif
-+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
-+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
-+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
-+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR));
-+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
-+}
-+
-+static void armctrl_unmask_irq(struct irq_data *d)
-+{
-+ static const unsigned int enables[4] = {
-+ ARM_IRQ_ENBL1,
-+ ARM_IRQ_ENBL2,
-+ ARM_IRQ_ENBL3,
-+ 0
-+ };
-+ int i;
-+ if (d->irq >= FIQ_START) {
-+ unsigned int data;
-+ if (num_online_cpus() > 1) {
-+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING));
-+ data &= ~0xc;
-+ data |= (1 << 2);
-+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING));
-+ }
-+ /* Unmask in ARMCTRL block after routing it properly */
-+ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
-+ writel(0x80 | data, __io_address(ARM_IRQ_FAST));
-+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
-+#if 1
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
-+ for (i=0; i<4; i++) // i = raw_smp_processor_id();
-+ {
-+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
-+ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
-+ }
-+#endif
-+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
-+#if 0
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
-+ for (i=0; i<4; i++) {
-+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
-+ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
-+ }
-+#endif
-+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
-+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
-+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
-+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) {
-+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET));
-+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
-+}
-+
-+#ifdef CONFIG_OF
-+
-+#define NR_IRQS_BANK0 21
-+#define NR_BANKS 4
-+#define IRQS_PER_BANK 32
-+
-+/* from drivers/irqchip/irq-bcm2835.c */
-+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
-+ const u32 *intspec, unsigned int intsize,
-+ unsigned long *out_hwirq, unsigned int *out_type)
-+{
-+ if (WARN_ON(intsize != 2))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[0] >= NR_BANKS))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
-+ return -EINVAL;
-+
-+ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9))
-+ return -EINVAL;
-+
-+ if (intspec[0] == 0)
-+ *out_hwirq = ARM_IRQ0_BASE + intspec[1];
-+ else if (intspec[0] == 1)
-+ *out_hwirq = ARM_IRQ1_BASE + intspec[1];
-+ else if (intspec[0] == 2)
-+ *out_hwirq = ARM_IRQ2_BASE + intspec[1];
-+ else
-+ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1];
-+
-+ /* reverse remap_irqs[] */
-+ switch (*out_hwirq) {
-+ case INTERRUPT_VC_JPEG:
-+ *out_hwirq = INTERRUPT_JPEG;
-+ break;
-+ case INTERRUPT_VC_USB:
-+ *out_hwirq = INTERRUPT_USB;
-+ break;
-+ case INTERRUPT_VC_3D:
-+ *out_hwirq = INTERRUPT_3D;
-+ break;
-+ case INTERRUPT_VC_DMA2:
-+ *out_hwirq = INTERRUPT_DMA2;
-+ break;
-+ case INTERRUPT_VC_DMA3:
-+ *out_hwirq = INTERRUPT_DMA3;
-+ break;
-+ case INTERRUPT_VC_I2C:
-+ *out_hwirq = INTERRUPT_I2C;
-+ break;
-+ case INTERRUPT_VC_SPI:
-+ *out_hwirq = INTERRUPT_SPI;
-+ break;
-+ case INTERRUPT_VC_I2SPCM:
-+ *out_hwirq = INTERRUPT_I2SPCM;
-+ break;
-+ case INTERRUPT_VC_SDIO:
-+ *out_hwirq = INTERRUPT_SDIO;
-+ break;
-+ case INTERRUPT_VC_UART:
-+ *out_hwirq = INTERRUPT_UART;
-+ break;
-+ case INTERRUPT_VC_ARASANSDIO:
-+ *out_hwirq = INTERRUPT_ARASANSDIO;
-+ break;
-+ }
-+
-+ *out_type = IRQ_TYPE_NONE;
-+ return 0;
-+}
-+
-+static struct irq_domain_ops armctrl_ops = {
-+ .xlate = armctrl_xlate
-+};
-+
-+void __init armctrl_dt_init(void)
-+{
-+ struct device_node *np;
-+ struct irq_domain *domain;
-+
-+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
-+ if (!np)
-+ return;
-+
-+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
-+ IRQ_ARMCTRL_START, 0,
-+ &armctrl_ops, NULL);
-+ WARN_ON(!domain);
-+}
-+#else
-+void __init armctrl_dt_init(void) { }
-+#endif /* CONFIG_OF */
-+
-+#if defined(CONFIG_PM)
-+
-+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
-+
-+/* Static defines
-+ * struct armctrl_device - VIC PM device (< 3.xx)
-+ * @sysdev: The system device which is registered. (< 3.xx)
-+ * @irq: The IRQ number for the base of the VIC.
-+ * @base: The register base for the VIC.
-+ * @resume_sources: A bitmask of interrupts for resume.
-+ * @resume_irqs: The IRQs enabled for resume.
-+ * @int_select: Save for VIC_INT_SELECT.
-+ * @int_enable: Save for VIC_INT_ENABLE.
-+ * @soft_int: Save for VIC_INT_SOFT.
-+ * @protect: Save for VIC_PROTECT.
-+ */
-+struct armctrl_info {
-+ void __iomem *base;
-+ int irq;
-+ u32 resume_sources;
-+ u32 resume_irqs;
-+ u32 int_select;
-+ u32 int_enable;
-+ u32 soft_int;
-+ u32 protect;
-+} armctrl;
-+
-+static int armctrl_suspend(void)
-+{
-+ return 0;
-+}
-+
-+static void armctrl_resume(void)
-+{
-+ return;
-+}
-+
-+/**
-+ * armctrl_pm_register - Register a VIC for later power management control
-+ * @base: The base address of the VIC.
-+ * @irq: The base IRQ for the VIC.
-+ * @resume_sources: bitmask of interrupts allowed for resume sources.
-+ *
-+ * For older kernels (< 3.xx) do -
-+ * Register the VIC with the system device tree so that it can be notified
-+ * of suspend and resume requests and ensure that the correct actions are
-+ * taken to re-instate the settings on resume.
-+ */
-+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
-+ u32 resume_sources)
-+{
-+ armctrl.base = base;
-+ armctrl.resume_sources = resume_sources;
-+ armctrl.irq = irq;
-+}
-+
-+static int armctrl_set_wake(struct irq_data *d, unsigned int on)
-+{
-+ unsigned int off = d->irq & 31;
-+ u32 bit = 1 << off;
-+
-+ if (!(bit & armctrl.resume_sources))
-+ return -EINVAL;
-+
-+ if (on)
-+ armctrl.resume_irqs |= bit;
-+ else
-+ armctrl.resume_irqs &= ~bit;
-+
-+ return 0;
-+}
-+
-+#else
-+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
-+ u32 arg1)
-+{
-+}
-+
-+#define armctrl_suspend NULL
-+#define armctrl_resume NULL
-+#define armctrl_set_wake NULL
-+#endif /* CONFIG_PM */
-+
-+static struct syscore_ops armctrl_syscore_ops = {
-+ .suspend = armctrl_suspend,
-+ .resume = armctrl_resume,
-+};
-+
-+/**
-+ * armctrl_syscore_init - initicall to register VIC pm functions
-+ *
-+ * This is called via late_initcall() to register
-+ * the resources for the VICs due to the early
-+ * nature of the VIC's registration.
-+*/
-+static int __init armctrl_syscore_init(void)
-+{
-+ register_syscore_ops(&armctrl_syscore_ops);
-+ return 0;
-+}
-+
-+late_initcall(armctrl_syscore_init);
-+
-+static struct irq_chip armctrl_chip = {
-+ .name = "ARMCTRL",
-+ .irq_ack = NULL,
-+ .irq_mask = armctrl_mask_irq,
-+ .irq_unmask = armctrl_unmask_irq,
-+ .irq_set_wake = armctrl_set_wake,
-+};
-+
-+/**
-+ * armctrl_init - initialise a vectored interrupt controller
-+ * @base: iomem base address
-+ * @irq_start: starting interrupt number, must be muliple of 32
-+ * @armctrl_sources: bitmask of interrupt sources to allow
-+ * @resume_sources: bitmask of interrupt sources to allow for resume
-+ */
-+int __init armctrl_init(void __iomem * base, unsigned int irq_start,
-+ u32 armctrl_sources, u32 resume_sources)
-+{
-+ unsigned int irq;
-+
-+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
-+ unsigned int data = irq;
-+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
-+ data = remap_irqs[irq - INTERRUPT_JPEG];
-+ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) {
-+ irq_set_percpu_devid(irq);
-+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq);
-+ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
-+ } else {
-+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq);
-+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
-+ }
-+ irq_set_chip_data(irq, (void *)data);
-+ }
-+
-+ armctrl_pm_register(base, irq_start, resume_sources);
-+ init_FIQ(FIQ_START);
-+ armctrl_dt_init();
-+ return 0;
-+}
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/armctrl.h linux-rpi/arch/arm/mach-bcm2709/armctrl.h
---- linux-3.18.14/arch/arm/mach-bcm2709/armctrl.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/armctrl.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,27 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/armctrl.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_ARMCTRL_H
-+#define __BCM2708_ARMCTRL_H
-+
-+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
-+ u32 armctrl_sources, u32 resume_sources);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c
---- linux-3.18.14/arch/arm/mach-bcm2709/bcm2708_gpio.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,426 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/spinlock.h>
-+#include <linux/module.h>
-+#include <linux/delay.h>
-+#include <linux/list.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <mach/gpio.h>
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <mach/platform.h>
-+#include <linux/pinctrl/consumer.h>
-+
-+#include <linux/platform_data/bcm2708.h>
-+
-+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
-+#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
-+#define BCM_GPIO_USE_IRQ 1
-+
-+#define GPIOFSEL(x) (0x00+(x)*4)
-+#define GPIOSET(x) (0x1c+(x)*4)
-+#define GPIOCLR(x) (0x28+(x)*4)
-+#define GPIOLEV(x) (0x34+(x)*4)
-+#define GPIOEDS(x) (0x40+(x)*4)
-+#define GPIOREN(x) (0x4c+(x)*4)
-+#define GPIOFEN(x) (0x58+(x)*4)
-+#define GPIOHEN(x) (0x64+(x)*4)
-+#define GPIOLEN(x) (0x70+(x)*4)
-+#define GPIOAREN(x) (0x7c+(x)*4)
-+#define GPIOAFEN(x) (0x88+(x)*4)
-+#define GPIOUD(x) (0x94+(x)*4)
-+#define GPIOUDCLK(x) (0x98+(x)*4)
-+
-+#define GPIO_BANKS 2
-+
-+enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
-+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
-+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
-+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
-+};
-+
-+ /* Each of the two spinlocks protects a different set of hardware
-+ * regiters and data structurs. This decouples the code of the IRQ from
-+ * the GPIO code. This also makes the case of a GPIO routine call from
-+ * the IRQ code simpler.
-+ */
-+static DEFINE_SPINLOCK(lock); /* GPIO registers */
-+
-+struct bcm2708_gpio {
-+ struct list_head list;
-+ void __iomem *base;
-+ struct gpio_chip gc;
-+ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
-+ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
-+};
-+
-+static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
-+ int function)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned long flags;
-+ unsigned gpiodir;
-+ unsigned gpio_bank = offset / 10;
-+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
-+
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ spin_lock_irqsave(&lock, flags);
-+
-+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
-+ gpiodir &= ~(7 << gpio_field_offset);
-+ gpiodir |= function << gpio_field_offset;
-+ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
-+ spin_unlock_irqrestore(&lock, flags);
-+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
-+
-+ return 0;
-+}
-+
-+static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
-+{
-+ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
-+}
-+
-+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
-+static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
-+ int value)
-+{
-+ int ret;
-+ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
-+ if (ret >= 0)
-+ bcm2708_gpio_set(gc, offset, value);
-+ return ret;
-+}
-+
-+static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+ unsigned lev;
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return 0;
-+ lev = readl(gpio->base + GPIOLEV(gpio_bank));
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
-+ return 0x1 & (lev >> gpio_field_offset);
-+}
-+
-+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return;
-+ if (value)
-+ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
-+ else
-+ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
-+}
-+
-+/**********************
-+ * extension to configure pullups
-+ */
-+int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
-+ bcm2708_gpio_pull_t value)
-+{
-+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
-+ unsigned gpio_bank = offset / 32;
-+ unsigned gpio_field_offset = (offset - 32 * gpio_bank);
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ switch (value) {
-+ case BCM2708_PULL_UP:
-+ writel(2, gpio->base + GPIOUD(0));
-+ break;
-+ case BCM2708_PULL_DOWN:
-+ writel(1, gpio->base + GPIOUD(0));
-+ break;
-+ case BCM2708_PULL_OFF:
-+ writel(0, gpio->base + GPIOUD(0));
-+ break;
-+ }
-+
-+ udelay(5);
-+ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
-+ udelay(5);
-+ writel(0, gpio->base + GPIOUD(0));
-+ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(bcm2708_gpio_setpull);
-+
-+/*************************************************************************************************************************
-+ * bcm2708 GPIO IRQ
-+ */
-+
-+#if BCM_GPIO_USE_IRQ
-+
-+static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return gpio_to_irq(gpio);
-+}
-+
-+static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned go = gn % 32;
-+
-+ gpio->rising[gb] &= ~(1 << go);
-+ gpio->falling[gb] &= ~(1 << go);
-+ gpio->high[gb] &= ~(1 << go);
-+ gpio->low[gb] &= ~(1 << go);
-+
-+ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-+ return -EINVAL;
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ gpio->rising[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ gpio->falling[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_LEVEL_HIGH)
-+ gpio->high[gb] |= (1 << go);
-+ if (type & IRQ_TYPE_LEVEL_LOW)
-+ gpio->low[gb] |= (1 << go);
-+ return 0;
-+}
-+
-+static void bcm2708_gpio_irq_mask(struct irq_data *d)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned long rising = readl(gpio->base + GPIOREN(gb));
-+ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
-+ unsigned long high = readl(gpio->base + GPIOHEN(gb));
-+ unsigned long low = readl(gpio->base + GPIOLEN(gb));
-+
-+ gn = gn % 32;
-+
-+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
-+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
-+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
-+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
-+}
-+
-+static void bcm2708_gpio_irq_unmask(struct irq_data *d)
-+{
-+ unsigned irq = d->irq;
-+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
-+ unsigned gn = irq_to_gpio(irq);
-+ unsigned gb = gn / 32;
-+ unsigned go = gn % 32;
-+ unsigned long rising = readl(gpio->base + GPIOREN(gb));
-+ unsigned long falling = readl(gpio->base + GPIOFEN(gb));
-+ unsigned long high = readl(gpio->base + GPIOHEN(gb));
-+ unsigned long low = readl(gpio->base + GPIOLEN(gb));
-+
-+ if (gpio->rising[gb] & (1 << go)) {
-+ writel(rising | (1 << go), gpio->base + GPIOREN(gb));
-+ } else {
-+ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
-+ }
-+
-+ if (gpio->falling[gb] & (1 << go)) {
-+ writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
-+ } else {
-+ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
-+ }
-+
-+ if (gpio->high[gb] & (1 << go)) {
-+ writel(high | (1 << go), gpio->base + GPIOHEN(gb));
-+ } else {
-+ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
-+ }
-+
-+ if (gpio->low[gb] & (1 << go)) {
-+ writel(low | (1 << go), gpio->base + GPIOLEN(gb));
-+ } else {
-+ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
-+ }
-+}
-+
-+static struct irq_chip bcm2708_irqchip = {
-+ .name = "GPIO",
-+ .irq_enable = bcm2708_gpio_irq_unmask,
-+ .irq_disable = bcm2708_gpio_irq_mask,
-+ .irq_unmask = bcm2708_gpio_irq_unmask,
-+ .irq_mask = bcm2708_gpio_irq_mask,
-+ .irq_set_type = bcm2708_gpio_irq_set_type,
-+};
-+
-+static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
-+{
-+ unsigned long edsr;
-+ unsigned bank;
-+ int i;
-+ unsigned gpio;
-+ unsigned level_bits;
-+ struct bcm2708_gpio *gpio_data = dev_id;
-+
-+ for (bank = 0; bank < GPIO_BANKS; bank++) {
-+ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
-+ level_bits = gpio_data->high[bank] | gpio_data->low[bank];
-+
-+ for_each_set_bit(i, &edsr, 32) {
-+ gpio = i + bank * 32;
-+ /* ack edge triggered IRQs immediately */
-+ if (!(level_bits & (1<<i)))
-+ writel(1<<i,
-+ __io_address(GPIO_BASE) + GPIOEDS(bank));
-+ generic_handle_irq(gpio_to_irq(gpio));
-+ /* ack level triggered IRQ after handling them */
-+ if (level_bits & (1<<i))
-+ writel(1<<i,
-+ __io_address(GPIO_BASE) + GPIOEDS(bank));
-+ }
-+ }
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction bcm2708_gpio_irq = {
-+ .name = "BCM2708 GPIO catchall handler",
-+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = bcm2708_gpio_interrupt,
-+};
-+
-+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
-+{
-+ unsigned irq;
-+
-+ ucb->gc.to_irq = bcm2708_gpio_to_irq;
-+
-+ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
-+ irq_set_chip_data(irq, ucb);
-+ irq_set_chip_and_handler(irq, &bcm2708_irqchip,
-+ handle_simple_irq);
-+ set_irq_flags(irq, IRQF_VALID);
-+ }
-+
-+ bcm2708_gpio_irq.dev_id = ucb;
-+ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
-+}
-+
-+#else
-+
-+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
-+{
-+}
-+
-+#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
-+
-+static int bcm2708_gpio_probe(struct platform_device *dev)
-+{
-+ struct bcm2708_gpio *ucb;
-+ struct resource *res;
-+ int bank;
-+ int err = 0;
-+
-+ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
-+
-+ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
-+ if (NULL == ucb) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "mailbox memory\n");
-+ err = -ENOMEM;
-+ goto err;
-+ }
-+
-+ res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-+
-+ platform_set_drvdata(dev, ucb);
-+ ucb->base = __io_address(GPIO_BASE);
-+
-+ ucb->gc.label = "bcm2708_gpio";
-+ ucb->gc.base = 0;
-+ ucb->gc.ngpio = BCM2708_NR_GPIOS;
-+ ucb->gc.owner = THIS_MODULE;
-+
-+ ucb->gc.direction_input = bcm2708_gpio_dir_in;
-+ ucb->gc.direction_output = bcm2708_gpio_dir_out;
-+ ucb->gc.get = bcm2708_gpio_get;
-+ ucb->gc.set = bcm2708_gpio_set;
-+ ucb->gc.can_sleep = 0;
-+
-+ for (bank = 0; bank < GPIO_BANKS; bank++) {
-+ writel(0, ucb->base + GPIOREN(bank));
-+ writel(0, ucb->base + GPIOFEN(bank));
-+ writel(0, ucb->base + GPIOHEN(bank));
-+ writel(0, ucb->base + GPIOLEN(bank));
-+ writel(0, ucb->base + GPIOAREN(bank));
-+ writel(0, ucb->base + GPIOAFEN(bank));
-+ writel(~0, ucb->base + GPIOEDS(bank));
-+ }
-+
-+ bcm2708_gpio_irq_init(ucb);
-+
-+ err = gpiochip_add(&ucb->gc);
-+
-+err:
-+ return err;
-+
-+}
-+
-+static int bcm2708_gpio_remove(struct platform_device *dev)
-+{
-+ int err = 0;
-+ struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
-+
-+ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
-+
-+ gpiochip_remove(&ucb->gc);
-+
-+ platform_set_drvdata(dev, NULL);
-+ kfree(ucb);
-+
-+ return err;
-+}
-+
-+static struct platform_driver bcm2708_gpio_driver = {
-+ .probe = bcm2708_gpio_probe,
-+ .remove = bcm2708_gpio_remove,
-+ .driver = {
-+ .name = "bcm2708_gpio"},
-+};
-+
-+static int __init bcm2708_gpio_init(void)
-+{
-+ return platform_driver_register(&bcm2708_gpio_driver);
-+}
-+
-+static void __exit bcm2708_gpio_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_gpio_driver);
-+}
-+
-+module_init(bcm2708_gpio_init);
-+module_exit(bcm2708_gpio_exit);
-+
-+MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/bcm2709.c linux-rpi/arch/arm/mach-bcm2709/bcm2709.c
---- linux-3.18.14/arch/arm/mach-bcm2709/bcm2709.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/bcm2709.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,1298 @@
-+/*
-+ * linux/arch/arm/mach-bcm2709/bcm2709.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/serial_8250.h>
-+#include <linux/platform_device.h>
-+#include <linux/syscore_ops.h>
-+#include <linux/interrupt.h>
-+#include <linux/amba/bus.h>
-+#include <linux/amba/clcd.h>
-+#include <linux/clk-provider.h>
-+#include <linux/clkdev.h>
-+#include <linux/clockchips.h>
-+#include <linux/cnt32_to_63.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/spi/spi.h>
-+#include <linux/gpio/machine.h>
-+#include <linux/w1-gpio.h>
-+#include <linux/pps-gpio.h>
-+
-+#include <linux/version.h>
-+#include <linux/clkdev.h>
-+#include <asm/system_info.h>
-+#include <mach/hardware.h>
-+#include <asm/irq.h>
-+#include <linux/leds.h>
-+#include <asm/mach-types.h>
-+#include <asm/cputype.h>
-+#include <linux/sched_clock.h>
-+
-+#include <asm/mach/arch.h>
-+#include <asm/mach/flash.h>
-+#include <asm/mach/irq.h>
-+#include <asm/mach/time.h>
-+#include <asm/mach/map.h>
-+
-+#include <mach/timex.h>
-+#include <mach/dma.h>
-+#include <mach/vcio.h>
-+#include <mach/system.h>
-+
-+#include <linux/delay.h>
-+
-+#include "bcm2709.h"
-+#include "armctrl.h"
-+
-+#ifdef CONFIG_BCM_VC_CMA
-+#include <linux/broadcom/vc_cma.h>
-+#endif
-+
-+//#define SYSTEM_TIMER
-+
-+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
-+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
-+ * represent this window by setting our dmamasks to 26 bits but, in fact
-+ * we're not going to use addresses outside this range (they're not in real
-+ * memory) so we don't bother.
-+ *
-+ * In the future we might include code to use this IOMMU to remap other
-+ * physical addresses onto VideoCore memory then the use of 32-bits would be
-+ * more legitimate.
-+ */
-+#define DMA_MASK_BITS_COMMON 32
-+
-+// use GPIO 4 for the one-wire GPIO pin, if enabled
-+#define W1_GPIO 4
-+// ensure one-wire GPIO pullup is disabled by default
-+#define W1_PULLUP -1
-+
-+/* command line parameters */
-+static unsigned boardrev, serial;
-+static unsigned uart_clock = UART0_CLOCK;
-+static unsigned disk_led_gpio = 16;
-+static unsigned disk_led_active_low = 1;
-+static unsigned reboot_part = 0;
-+static unsigned w1_gpio_pin = W1_GPIO;
-+static unsigned w1_gpio_pullup = W1_PULLUP;
-+static int pps_gpio_pin = -1;
-+static bool vc_i2c_override = false;
-+
-+static unsigned use_dt = 0;
-+
-+static void __init bcm2709_init_led(void);
-+
-+void __init bcm2709_init_irq(void)
-+{
-+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
-+}
-+
-+static struct map_desc bcm2709_io_desc[] __initdata = {
-+ {
-+ .virtual = IO_ADDRESS(ARMCTRL_BASE),
-+ .pfn = __phys_to_pfn(ARMCTRL_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(UART0_BASE),
-+ .pfn = __phys_to_pfn(UART0_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(UART1_BASE),
-+ .pfn = __phys_to_pfn(UART1_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(DMA_BASE),
-+ .pfn = __phys_to_pfn(DMA_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(MCORE_BASE),
-+ .pfn = __phys_to_pfn(MCORE_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(ST_BASE),
-+ .pfn = __phys_to_pfn(ST_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(USB_BASE),
-+ .pfn = __phys_to_pfn(USB_BASE),
-+ .length = SZ_128K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(PM_BASE),
-+ .pfn = __phys_to_pfn(PM_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(GPIO_BASE),
-+ .pfn = __phys_to_pfn(GPIO_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+ {
-+ .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
-+ .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
-+ .length = SZ_4K,
-+ .type = MT_DEVICE},
-+};
-+
-+void __init bcm2709_map_io(void)
-+{
-+ iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
-+}
-+
-+#ifdef SYSTEM_TIMER
-+
-+/* The STC is a free running counter that increments at the rate of 1MHz */
-+#define STC_FREQ_HZ 1000000
-+
-+static inline uint32_t timer_read(void)
-+{
-+ /* STC: a free running counter that increments at the rate of 1MHz */
-+ return readl(__io_address(ST_BASE + 0x04));
-+}
-+
-+static unsigned long bcm2709_read_current_timer(void)
-+{
-+ return timer_read();
-+}
-+
-+static u64 notrace bcm2709_read_sched_clock(void)
-+{
-+ return timer_read();
-+}
-+
-+static cycle_t clksrc_read(struct clocksource *cs)
-+{
-+ return timer_read();
-+}
-+
-+static struct clocksource clocksource_stc = {
-+ .name = "stc",
-+ .rating = 300,
-+ .read = clksrc_read,
-+ .mask = CLOCKSOURCE_MASK(32),
-+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+unsigned long frc_clock_ticks32(void)
-+{
-+ return timer_read();
-+}
-+
-+static void __init bcm2709_clocksource_init(void)
-+{
-+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
-+ printk(KERN_ERR "timer: failed to initialize clock "
-+ "source %s\n", clocksource_stc.name);
-+ }
-+}
-+#endif
-+
-+struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate)
-+{
-+ struct clk *clk;
-+
-+ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
-+ fixed_rate);
-+ if (IS_ERR(clk))
-+ pr_err("%s not registered\n", name);
-+
-+ return clk;
-+}
-+
-+void __init bcm2709_register_clkdev(struct clk *clk, const char *name)
-+{
-+ int ret;
-+
-+ ret = clk_register_clkdev(clk, NULL, name);
-+ if (ret)
-+ pr_err("%s alias not registered\n", name);
-+}
-+
-+void __init bcm2709_init_clocks(void)
-+{
-+ struct clk *clk;
-+
-+ clk = bcm2709_clk_register("uart0_clk", uart_clock);
-+ bcm2709_register_clkdev(clk, "dev:f1");
-+
-+ clk = bcm2709_clk_register("sdhost_clk", 250000000);
-+ bcm2709_register_clkdev(clk, "mmc-bcm2835.0");
-+ bcm2709_register_clkdev(clk, "bcm2708_spi.0");
-+ bcm2709_register_clkdev(clk, "bcm2708_i2c.0");
-+ bcm2709_register_clkdev(clk, "bcm2708_i2c.1");
-+}
-+
-+#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
-+#define UART0_DMA { 15, 14 }
-+
-+AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
-+
-+static struct amba_device *amba_devs[] __initdata = {
-+ &uart0_device,
-+};
-+
-+static struct resource bcm2708_dmaman_resources[] = {
-+ {
-+ .start = DMA_BASE,
-+ .end = DMA_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct platform_device bcm2708_dmaman_device = {
-+ .name = BCM_DMAMAN_DRIVER_NAME,
-+ .id = 0, /* first bcm2708_dma */
-+ .resource = bcm2708_dmaman_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
-+};
-+
-+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-+static struct w1_gpio_platform_data w1_gpio_pdata = {
-+ .pin = W1_GPIO,
-+ .ext_pullup_enable_pin = W1_PULLUP,
-+ .is_open_drain = 0,
-+};
-+
-+static struct platform_device w1_device = {
-+ .name = "w1-gpio",
-+ .id = -1,
-+ .dev.platform_data = &w1_gpio_pdata,
-+};
-+#endif
-+
-+static struct pps_gpio_platform_data pps_gpio_info = {
-+ .assert_falling_edge = false,
-+ .capture_clear = false,
-+ .gpio_pin = -1,
-+ .gpio_label = "PPS",
-+};
-+
-+static struct platform_device pps_gpio_device = {
-+ .name = "pps-gpio",
-+ .id = PLATFORM_DEVID_NONE,
-+ .dev.platform_data = &pps_gpio_info,
-+};
-+
-+static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_fb_device = {
-+ .name = "bcm2708_fb",
-+ .id = -1, /* only one bcm2708_fb */
-+ .resource = NULL,
-+ .num_resources = 0,
-+ .dev = {
-+ .dma_mask = &fb_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
-+ {
-+ .mapbase = UART1_BASE + 0x40,
-+ .irq = IRQ_AUX,
-+ .uartclk = 125000000,
-+ .regshift = 2,
-+ .iotype = UPIO_MEM,
-+ .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
-+ .type = PORT_8250,
-+ },
-+ {},
-+};
-+
-+static struct platform_device bcm2708_uart1_device = {
-+ .name = "serial8250",
-+ .id = PLAT8250_DEV_PLATFORM,
-+ .dev = {
-+ .platform_data = bcm2708_uart1_platform_data,
-+ },
-+};
-+
-+static struct resource bcm2708_usb_resources[] = {
-+ [0] = {
-+ .start = USB_BASE,
-+ .end = USB_BASE + SZ_128K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = MPHI_BASE,
-+ .end = MPHI_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [2] = {
-+ .start = IRQ_HOSTPORT,
-+ .end = IRQ_HOSTPORT,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ [3] = {
-+ .start = IRQ_USB,
-+ .end = IRQ_USB,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ [4] = {
-+ .start = ARM_LOCAL_BASE,
-+ .end = ARM_LOCAL_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [5] = {
-+ .start = IRQ_ARM_LOCAL_MAILBOX1,
-+ .end = IRQ_ARM_LOCAL_MAILBOX1,
-+ .flags = IORESOURCE_IRQ
-+ },
-+};
-+
-+
-+static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_usb_device = {
-+ .name = "bcm2708_usb",
-+ .id = -1, /* only one bcm2708_usb */
-+ .resource = bcm2708_usb_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
-+ .dev = {
-+ .dma_mask = &usb_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+static struct resource bcm2708_vcio_resources[] = {
-+ [0] = { /* mailbox/semaphore/doorbell access */
-+ .start = MCORE_BASE,
-+ .end = MCORE_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_vcio_device = {
-+ .name = BCM_VCIO_DRIVER_NAME,
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_vcio_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
-+ .dev = {
-+ .dma_mask = &vcio_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+
-+#ifdef CONFIG_BCM2708_GPIO
-+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
-+
-+static struct resource bcm2708_gpio_resources[] = {
-+ [0] = { /* general purpose I/O */
-+ .start = GPIO_BASE,
-+ .end = GPIO_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_gpio_device = {
-+ .name = BCM_GPIO_DRIVER_NAME,
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_gpio_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
-+ .dev = {
-+ .dma_mask = &gpio_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+#endif
-+
-+#ifdef SYSTEM_TIMER
-+static struct resource bcm2708_systemtimer_resources[] = {
-+ [0] = { /* system timer access */
-+ .start = ST_BASE,
-+ .end = ST_BASE + SZ_4K - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = IRQ_TIMER3,
-+ .end = IRQ_TIMER3,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+
-+};
-+
-+static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+static struct platform_device bcm2708_systemtimer_device = {
-+ .name = "bcm2708_systemtimer",
-+ .id = -1, /* only one VideoCore I/O area */
-+ .resource = bcm2708_systemtimer_resources,
-+ .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
-+ .dev = {
-+ .dma_mask = &systemtimer_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
-+ },
-+};
-+#endif
-+
-+#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
-+static struct resource bcm2835_emmc_resources[] = {
-+ [0] = {
-+ .start = EMMC_BASE,
-+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
-+ /* the memory map actually makes SZ_4K available */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ [1] = {
-+ .start = IRQ_ARASANSDIO,
-+ .end = IRQ_ARASANSDIO,
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
-+
-+struct platform_device bcm2835_emmc_device = {
-+ .name = "mmc-bcm2835",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
-+ .resource = bcm2835_emmc_resources,
-+ .dev = {
-+ .dma_mask = &bcm2835_emmc_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+#endif /* CONFIG_MMC_BCM2835 */
-+
-+static struct resource bcm2708_powerman_resources[] = {
-+ [0] = {
-+ .start = PM_BASE,
-+ .end = PM_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+
-+struct platform_device bcm2708_powerman_device = {
-+ .name = "bcm2708_powerman",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
-+ .resource = bcm2708_powerman_resources,
-+ .dev = {
-+ .dma_mask = &powerman_dmamask,
-+ .coherent_dma_mask = 0xffffffffUL},
-+};
-+
-+
-+static struct platform_device bcm2708_alsa_devices[] = {
-+ [0] = {
-+ .name = "bcm2835_AUD0",
-+ .id = 0, /* first audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [1] = {
-+ .name = "bcm2835_AUD1",
-+ .id = 1, /* second audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [2] = {
-+ .name = "bcm2835_AUD2",
-+ .id = 2, /* third audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [3] = {
-+ .name = "bcm2835_AUD3",
-+ .id = 3, /* forth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [4] = {
-+ .name = "bcm2835_AUD4",
-+ .id = 4, /* fifth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [5] = {
-+ .name = "bcm2835_AUD5",
-+ .id = 5, /* sixth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [6] = {
-+ .name = "bcm2835_AUD6",
-+ .id = 6, /* seventh audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+ [7] = {
-+ .name = "bcm2835_AUD7",
-+ .id = 7, /* eighth audio device */
-+ .resource = 0,
-+ .num_resources = 0,
-+ },
-+};
-+
-+static struct resource bcm2708_spi_resources[] = {
-+ {
-+ .start = SPI0_BASE,
-+ .end = SPI0_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = IRQ_SPI,
-+ .end = IRQ_SPI,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+
-+static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
-+static struct platform_device bcm2708_spi_device = {
-+ .name = "bcm2708_spi",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
-+ .resource = bcm2708_spi_resources,
-+ .dev = {
-+ .dma_mask = &bcm2708_spi_dmamask,
-+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
-+};
-+
-+#ifdef CONFIG_BCM2708_SPIDEV
-+static struct spi_board_info bcm2708_spi_devices[] = {
-+#ifdef CONFIG_SPI_SPIDEV
-+ {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_0,
-+ }, {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 1,
-+ .mode = SPI_MODE_0,
-+ }
-+#endif
-+};
-+#endif
-+
-+static struct resource bcm2708_bsc0_resources[] = {
-+ {
-+ .start = BSC0_BASE,
-+ .end = BSC0_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = INTERRUPT_I2C,
-+ .end = INTERRUPT_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device bcm2708_bsc0_device = {
-+ .name = "bcm2708_i2c",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
-+ .resource = bcm2708_bsc0_resources,
-+};
-+
-+
-+static struct resource bcm2708_bsc1_resources[] = {
-+ {
-+ .start = BSC1_BASE,
-+ .end = BSC1_BASE + SZ_256 - 1,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = INTERRUPT_I2C,
-+ .end = INTERRUPT_I2C,
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device bcm2708_bsc1_device = {
-+ .name = "bcm2708_i2c",
-+ .id = 1,
-+ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
-+ .resource = bcm2708_bsc1_resources,
-+};
-+
-+static struct platform_device bcm2835_hwmon_device = {
-+ .name = "bcm2835_hwmon",
-+};
-+
-+static struct platform_device bcm2835_thermal_device = {
-+ .name = "bcm2835_thermal",
-+};
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
-+static struct resource bcm2708_i2s_resources[] = {
-+ {
-+ .start = I2S_BASE,
-+ .end = I2S_BASE + 0x20,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = PCM_CLOCK_BASE,
-+ .end = PCM_CLOCK_BASE + 0x02,
-+ .flags = IORESOURCE_MEM,
-+ }
-+};
-+
-+static struct platform_device bcm2708_i2s_device = {
-+ .name = "bcm2708-i2s",
-+ .id = 0,
-+ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
-+ .resource = bcm2708_i2s_resources,
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
-+static struct platform_device snd_hifiberry_dac_device = {
-+ .name = "snd-hifiberry-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct platform_device snd_pcm5102a_codec_device = {
-+ .name = "pcm5102a-codec",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
-+static struct platform_device snd_rpi_hifiberry_dacplus_device = {
-+ .name = "snd-rpi-hifiberry-dacplus",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pcm5122", 0x4d)
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
-+static struct platform_device snd_hifiberry_digi_device = {
-+ .name = "snd-hifiberry-digi",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("wm8804", 0x3b)
-+ },
-+};
-+
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
-+static struct platform_device snd_hifiberry_amp_device = {
-+ .name = "snd-hifiberry-amp",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("tas5713", 0x1b)
-+ },
-+};
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
-+static struct platform_device snd_rpi_dac_device = {
-+ .name = "snd-rpi-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+static struct platform_device snd_pcm1794a_codec_device = {
-+ .name = "pcm1794a-codec",
-+ .id = -1,
-+ .num_resources = 0,
-+};
-+#endif
-+
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
-+static struct platform_device snd_rpi_iqaudio_dac_device = {
-+ .name = "snd-rpi-iqaudio-dac",
-+ .id = 0,
-+ .num_resources = 0,
-+};
-+
-+// Use the actual device name rather than generic driver name
-+static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
-+ {
-+ I2C_BOARD_INFO("pcm5122", 0x4c)
-+ },
-+};
-+#endif
-+
-+int __init bcm_register_device(struct platform_device *pdev)
-+{
-+ int ret;
-+
-+ ret = platform_device_register(pdev);
-+ if (ret)
-+ pr_debug("Unable to register platform device '%s': %d\n",
-+ pdev->name, ret);
-+
-+ return ret;
-+}
-+
-+/*
-+ * Use these macros for platform and i2c devices that are present in the
-+ * Device Tree. This way the devices are only added on non-DT systems.
-+ */
-+#define bcm_register_device_dt(pdev) \
-+ if (!use_dt) bcm_register_device(pdev)
-+
-+#define i2c_register_board_info_dt(busnum, info, n) \
-+ if (!use_dt) i2c_register_board_info(busnum, info, n)
-+
-+int calc_rsts(int partition)
-+{
-+ return PM_PASSWORD |
-+ ((partition & (1 << 0)) << 0) |
-+ ((partition & (1 << 1)) << 1) |
-+ ((partition & (1 << 2)) << 2) |
-+ ((partition & (1 << 3)) << 3) |
-+ ((partition & (1 << 4)) << 4) |
-+ ((partition & (1 << 5)) << 5);
-+}
-+
-+static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
-+{
-+ extern char bcm2708_reboot_mode;
-+ uint32_t pm_rstc, pm_wdog;
-+ uint32_t timeout = 10;
-+ uint32_t pm_rsts = 0;
-+
-+ if(bcm2708_reboot_mode == 'q')
-+ {
-+ // NOOBS < 1.3 booting with reboot=q
-+ pm_rsts = readl(__io_address(PM_RSTS));
-+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
-+ }
-+ else if(bcm2708_reboot_mode == 'p')
-+ {
-+ // NOOBS < 1.3 halting
-+ pm_rsts = readl(__io_address(PM_RSTS));
-+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
-+ }
-+ else
-+ {
-+ pm_rsts = calc_rsts(reboot_part);
-+ }
-+
-+ writel(pm_rsts, __io_address(PM_RSTS));
-+
-+ /* Setup watchdog for reset */
-+ pm_rstc = readl(__io_address(PM_RSTC));
-+
-+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
-+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
-+
-+ writel(pm_wdog, __io_address(PM_WDOG));
-+ writel(pm_rstc, __io_address(PM_RSTC));
-+}
-+
-+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
-+static void bcm2709_power_off(void)
-+{
-+ extern char bcm2708_reboot_mode;
-+ if(bcm2708_reboot_mode == 'q')
-+ {
-+ // NOOBS < v1.3
-+ bcm2709_restart('p', "");
-+ }
-+ else
-+ {
-+ /* partition 63 is special code for HALT the bootloader knows not to boot*/
-+ reboot_part = 63;
-+ /* continue with normal reset mechanism */
-+ bcm2709_restart(0, "");
-+ }
-+}
-+
-+#ifdef CONFIG_OF
-+static void __init bcm2709_dt_init(void)
-+{
-+ int ret;
-+
-+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-+ if (ret) {
-+ pr_err("of_platform_populate failed: %d\n", ret);
-+ use_dt = 0;
-+ }
-+}
-+#else
-+static void __init bcm2709_dt_init(void) { }
-+#endif /* CONFIG_OF */
-+
-+void __init bcm2709_init(void)
-+{
-+ int i;
-+
-+#if defined(CONFIG_BCM_VC_CMA)
-+ vc_cma_early_init();
-+#endif
-+ printk("bcm2709.uart_clock = %d\n", uart_clock);
-+ pm_power_off = bcm2709_power_off;
-+
-+ bcm2709_init_clocks();
-+ if (use_dt)
-+ bcm2709_dt_init();
-+
-+ bcm_register_device(&bcm2708_dmaman_device);
-+ bcm_register_device(&bcm2708_vcio_device);
-+#ifdef CONFIG_BCM2708_GPIO
-+ bcm_register_device_dt(&bcm2708_gpio_device);
-+#endif
-+
-+#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE)
-+ if (!use_dt && (pps_gpio_pin >= 0)) {
-+ pr_info("bcm2709: GPIO %d setup as pps-gpio device\n", pps_gpio_pin);
-+ pps_gpio_info.gpio_pin = pps_gpio_pin;
-+ pps_gpio_device.id = pps_gpio_pin;
-+ bcm_register_device(&pps_gpio_device);
-+ }
-+#endif
-+
-+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
-+ w1_gpio_pdata.pin = w1_gpio_pin;
-+ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
-+ bcm_register_device_dt(&w1_device);
-+#endif
-+#ifdef SYSTEM_TIMER
-+ bcm_register_device(&bcm2708_systemtimer_device);
-+#endif
-+ bcm_register_device(&bcm2708_fb_device);
-+ bcm_register_device(&bcm2708_usb_device);
-+ bcm_register_device(&bcm2708_uart1_device);
-+ bcm_register_device(&bcm2708_powerman_device);
-+
-+#ifdef CONFIG_MMC_BCM2835
-+ bcm_register_device_dt(&bcm2835_emmc_device);
-+#endif
-+ bcm2709_init_led();
-+ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
-+ bcm_register_device(&bcm2708_alsa_devices[i]);
-+
-+ bcm_register_device(&bcm2835_hwmon_device);
-+ bcm_register_device(&bcm2835_thermal_device);
-+
-+ bcm_register_device_dt(&bcm2708_spi_device);
-+
-+ if (vc_i2c_override) {
-+ bcm_register_device_dt(&bcm2708_bsc0_device);
-+ bcm_register_device_dt(&bcm2708_bsc1_device);
-+ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) {
-+ bcm_register_device_dt(&bcm2708_bsc0_device);
-+ } else {
-+ bcm_register_device_dt(&bcm2708_bsc1_device);
-+ }
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
-+ bcm_register_device_dt(&bcm2708_i2s_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
-+ bcm_register_device_dt(&snd_hifiberry_dac_device);
-+ bcm_register_device_dt(&snd_pcm5102a_codec_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
-+ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device);
-+ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
-+ bcm_register_device_dt(&snd_hifiberry_digi_device);
-+ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
-+ bcm_register_device_dt(&snd_hifiberry_amp_device);
-+ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
-+ bcm_register_device_dt(&snd_rpi_dac_device);
-+ bcm_register_device_dt(&snd_pcm1794a_codec_device);
-+#endif
-+
-+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
-+ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device);
-+ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
-+#endif
-+
-+
-+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-+ struct amba_device *d = amba_devs[i];
-+ amba_device_register(d, &iomem_resource);
-+ }
-+ system_rev = boardrev;
-+ system_serial_low = serial;
-+
-+#ifdef CONFIG_BCM2708_SPIDEV
-+ if (!use_dt)
-+ spi_register_board_info(bcm2708_spi_devices,
-+ ARRAY_SIZE(bcm2708_spi_devices));
-+#endif
-+}
-+
-+#ifdef SYSTEM_TIMER
-+static void timer_set_mode(enum clock_event_mode mode,
-+ struct clock_event_device *clk)
-+{
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ break;
-+ case CLOCK_EVT_MODE_PERIODIC:
-+
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_RESUME:
-+
-+ default:
-+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
-+ (int)mode);
-+ break;
-+ }
-+
-+}
-+
-+static int timer_set_next_event(unsigned long cycles,
-+ struct clock_event_device *unused)
-+{
-+ unsigned long stc;
-+ do {
-+ stc = readl(__io_address(ST_BASE + 0x04));
-+ /* We could take a FIQ here, which may push ST above STC3 */
-+ writel(stc + cycles, __io_address(ST_BASE + 0x18));
-+ } while ((signed long) cycles >= 0 &&
-+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
-+ >= (signed long) cycles);
-+ return 0;
-+}
-+
-+static struct clock_event_device timer0_clockevent = {
-+ .name = "timer0",
-+ .shift = 32,
-+ .features = CLOCK_EVT_FEAT_ONESHOT,
-+ .set_mode = timer_set_mode,
-+ .set_next_event = timer_set_next_event,
-+};
-+
-+/*
-+ * IRQ handler for the timer
-+ */
-+static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *evt = &timer0_clockevent;
-+
-+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
-+
-+ evt->event_handler(evt);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction bcm2709_timer_irq = {
-+ .name = "BCM2709 Timer Tick",
-+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = bcm2709_timer_interrupt,
-+};
-+
-+/*
-+ * Set up timer interrupt, and return the current time in seconds.
-+ */
-+
-+static struct delay_timer bcm2709_delay_timer = {
-+ .read_current_timer = bcm2709_read_current_timer,
-+ .freq = STC_FREQ_HZ,
-+};
-+
-+static void __init bcm2709_timer_init(void)
-+{
-+ /* init high res timer */
-+ bcm2709_clocksource_init();
-+
-+ /*
-+ * Make irqs happen for the system timer
-+ */
-+ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
-+
-+ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ);
-+
-+ timer0_clockevent.mult =
-+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
-+ timer0_clockevent.max_delta_ns =
-+ clockevent_delta2ns(0xffffffff, &timer0_clockevent);
-+ timer0_clockevent.min_delta_ns =
-+ clockevent_delta2ns(0xf, &timer0_clockevent);
-+
-+ timer0_clockevent.cpumask = cpumask_of(0);
-+ clockevents_register_device(&timer0_clockevent);
-+
-+ register_current_timer_delay(&bcm2708_delay_timer);
-+}
-+
-+#else
-+
-+static void __init bcm2709_timer_init(void)
-+{
-+ extern void dc4_arch_timer_init(void);
-+ // timer control
-+ writel(0, __io_address(ARM_LOCAL_CONTROL));
-+ // timer pre_scaler
-+ writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
-+ //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
-+
-+ if (use_dt)
-+ {
-+ of_clk_init(NULL);
-+ clocksource_of_init();
-+ }
-+ else
-+ dc4_arch_timer_init();
-+}
-+
-+#endif
-+
-+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-+#include <linux/leds.h>
-+
-+static struct gpio_led bcm2709_leds[] = {
-+ [0] = {
-+ .gpio = 16,
-+ .name = "led0",
-+ .default_trigger = "mmc0",
-+ .active_low = 1,
-+ },
-+};
-+
-+static struct gpio_led_platform_data bcm2709_led_pdata = {
-+ .num_leds = ARRAY_SIZE(bcm2709_leds),
-+ .leds = bcm2709_leds,
-+};
-+
-+static struct platform_device bcm2709_led_device = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = &bcm2709_led_pdata,
-+ },
-+};
-+
-+static void __init bcm2709_init_led(void)
-+{
-+ bcm2709_leds[0].gpio = disk_led_gpio;
-+ bcm2709_leds[0].active_low = disk_led_active_low;
-+ bcm_register_device_dt(&bcm2709_led_device);
-+}
-+#else
-+static inline void bcm2709_init_led(void)
-+{
-+}
-+#endif
-+
-+void __init bcm2709_init_early(void)
-+{
-+ /*
-+ * Some devices allocate their coherent buffers from atomic
-+ * context. Increase size of atomic coherent pool to make sure such
-+ * the allocations won't fail.
-+ */
-+ init_dma_coherent_pool_size(SZ_4M);
-+
-+#ifdef CONFIG_OF
-+ if (of_allnodes)
-+ use_dt = 1;
-+#endif
-+}
-+
-+static void __init board_reserve(void)
-+{
-+#if defined(CONFIG_BCM_VC_CMA)
-+ vc_cma_reserve();
-+#endif
-+}
-+
-+
-+#include <linux/smp.h>
-+
-+#include <mach/hardware.h>
-+#include <asm/cacheflush.h>
-+#include <asm/smp_plat.h>
-+int dc4=0;
-+//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
-+void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
-+
-+static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
-+{
-+ int cpu;
-+ /*
-+ * Ensure that stores to Normal memory are visible to the
-+ * other CPUs before issuing the IPI.
-+ */
-+ dsb();
-+
-+ /* Convert our logical CPU mask into a physical one. */
-+ for_each_cpu(cpu, mask)
-+ {
-+ /* submit softirq */
-+ writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
-+ }
-+}
-+
-+void __init bcm2709_smp_init_cpus(void)
-+{
-+ void secondary_startup(void);
-+ unsigned int i, ncores;
-+
-+ ncores = 4; // xxx scu_get_core_count(NULL);
-+ printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
-+ printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
-+
-+ for (i = 0; i < ncores; i++) {
-+ set_cpu_possible(i, true);
-+ /* enable IRQ (not FIQ) */
-+ writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
-+ //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
-+ }
-+ set_smp_cross_call(bcm2835_send_doorbell);
-+}
-+
-+/*
-+ * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
-+ */
-+void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
-+{
-+ //void __iomem *scu_base;
-+
-+ printk("[%s] enter\n", __FUNCTION__);
-+ //scu_base = scu_base_addr();
-+ //scu_enable(scu_base);
-+}
-+
-+/*
-+ * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
-+ */
-+void __cpuinit bcm2709_secondary_init(unsigned int cpu)
-+{
-+ printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
-+ //gic_secondary_init(0);
-+}
-+
-+/*
-+ * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
-+ */
-+int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
-+{
-+ void secondary_startup(void);
-+ void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
-+ void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
-+ unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
-+ int timeout=20;
-+ unsigned t = -1;
-+ //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
-+
-+ dsb();
-+ BUG_ON(readl(mbox_clr) != 0);
-+ writel(secondary_boot, mbox_set);
-+
-+ while (--timeout > 0) {
-+ t = readl(mbox_clr);
-+ if (t == 0) break;
-+ cpu_relax();
-+ }
-+ if (timeout==0)
-+ printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
-+ else
-+ printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
-+
-+ return 0;
-+}
-+
-+
-+struct smp_operations bcm2709_smp_ops __initdata = {
-+ .smp_init_cpus = bcm2709_smp_init_cpus,
-+ .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
-+ .smp_secondary_init = bcm2709_secondary_init,
-+ .smp_boot_secondary = bcm2709_boot_secondary,
-+};
-+
-+static const char * const bcm2709_compat[] = {
-+ "brcm,bcm2709",
-+ "brcm,bcm2708", /* Could use bcm2708 in a pinch */
-+ NULL
-+};
-+
-+MACHINE_START(BCM2709, "BCM2709")
-+ /* Maintainer: Broadcom Europe Ltd. */
-+ .smp = smp_ops(bcm2709_smp_ops),
-+ .map_io = bcm2709_map_io,
-+ .init_irq = bcm2709_init_irq,
-+ .init_time = bcm2709_timer_init,
-+ .init_machine = bcm2709_init,
-+ .init_early = bcm2709_init_early,
-+ .reserve = board_reserve,
-+ .restart = bcm2709_restart,
-+ .dt_compat = bcm2709_compat,
-+MACHINE_END
-+
-+MACHINE_START(BCM2708, "BCM2709")
-+ /* Maintainer: Broadcom Europe Ltd. */
-+ .smp = smp_ops(bcm2709_smp_ops),
-+ .map_io = bcm2709_map_io,
-+ .init_irq = bcm2709_init_irq,
-+ .init_time = bcm2709_timer_init,
-+ .init_machine = bcm2709_init,
-+ .init_early = bcm2709_init_early,
-+ .reserve = board_reserve,
-+ .restart = bcm2709_restart,
-+ .dt_compat = bcm2709_compat,
-+MACHINE_END
-+
-+module_param(boardrev, uint, 0644);
-+module_param(serial, uint, 0644);
-+module_param(uart_clock, uint, 0644);
-+module_param(disk_led_gpio, uint, 0644);
-+module_param(disk_led_active_low, uint, 0644);
-+module_param(reboot_part, uint, 0644);
-+module_param(w1_gpio_pin, uint, 0644);
-+module_param(w1_gpio_pullup, uint, 0644);
-+module_param(pps_gpio_pin, int, 0644);
-+MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS");
-+module_param(vc_i2c_override, bool, 0644);
-+MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral.");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/bcm2709.h linux-rpi/arch/arm/mach-bcm2709/bcm2709.h
---- linux-3.18.14/arch/arm/mach-bcm2709/bcm2709.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/bcm2709.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,49 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/bcm2708.h
-+ *
-+ * BCM2708 machine support header
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_BCM2708_H
-+#define __BCM2708_BCM2708_H
-+
-+#include <linux/amba/bus.h>
-+
-+extern void __init bcm2708_init(void);
-+extern void __init bcm2708_init_irq(void);
-+extern void __init bcm2708_map_io(void);
-+extern struct sys_timer bcm2708_timer;
-+extern unsigned int mmc_status(struct device *dev);
-+
-+#define AMBA_DEVICE(name, busid, base, plat) \
-+static struct amba_device name##_device = { \
-+ .dev = { \
-+ .coherent_dma_mask = ~0, \
-+ .init_name = busid, \
-+ .platform_data = plat, \
-+ }, \
-+ .res = { \
-+ .start = base##_BASE, \
-+ .end = (base##_BASE) + SZ_4K - 1,\
-+ .flags = IORESOURCE_MEM, \
-+ }, \
-+ .irq = base##_IRQ, \
-+}
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/clock.c linux-rpi/arch/arm/mach-bcm2709/clock.c
---- linux-3.18.14/arch/arm/mach-bcm2709/clock.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/clock.c 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,61 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/clock.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/device.h>
-+#include <linux/list.h>
-+#include <linux/errno.h>
-+#include <linux/err.h>
-+#include <linux/string.h>
-+#include <linux/clk.h>
-+#include <linux/mutex.h>
-+
-+#include <asm/clkdev.h>
-+
-+#include "clock.h"
-+
-+int clk_enable(struct clk *clk)
-+{
-+ return 0;
-+}
-+EXPORT_SYMBOL(clk_enable);
-+
-+void clk_disable(struct clk *clk)
-+{
-+}
-+EXPORT_SYMBOL(clk_disable);
-+
-+unsigned long clk_get_rate(struct clk *clk)
-+{
-+ return clk->rate;
-+}
-+EXPORT_SYMBOL(clk_get_rate);
-+
-+long clk_round_rate(struct clk *clk, unsigned long rate)
-+{
-+ return clk->rate;
-+}
-+EXPORT_SYMBOL(clk_round_rate);
-+
-+int clk_set_rate(struct clk *clk, unsigned long rate)
-+{
-+ return -EIO;
-+}
-+EXPORT_SYMBOL(clk_set_rate);
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/clock.h linux-rpi/arch/arm/mach-bcm2709/clock.h
---- linux-3.18.14/arch/arm/mach-bcm2709/clock.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/clock.h 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,24 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/clock.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+struct module;
-+
-+struct clk {
-+ unsigned long rate;
-+};
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/delay.S linux-rpi/arch/arm/mach-bcm2709/delay.S
---- linux-3.18.14/arch/arm/mach-bcm2709/delay.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/delay.S 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,21 @@
-+/*
-+ * linux/arch/arm/lib/delay.S
-+ *
-+ * Copyright (C) 1995, 1996 Russell King
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/linkage.h>
-+#include <asm/assembler.h>
-+#include <asm/param.h>
-+
-+ .text
-+.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls
-+@ Delay routine
-+ENTRY(bcm2708_delay)
-+ subs r0, r0, #1
-+ bhi bcm2708_delay
-+ mov pc, lr
-+ENDPROC(bcm2708_delay)
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/dma.c linux-rpi/arch/arm/mach-bcm2709/dma.c
---- linux-3.18.14/arch/arm/mach-bcm2709/dma.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/dma.c 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,409 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/dma.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/slab.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/scatterlist.h>
-+
-+#include <mach/dma.h>
-+#include <mach/irqs.h>
-+
-+/*****************************************************************************\
-+ * *
-+ * Configuration *
-+ * *
-+\*****************************************************************************/
-+
-+#define CACHE_LINE_MASK 31
-+#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
-+#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
-+
-+/* valid only for channels 0 - 14, 15 has its own base address */
-+#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
-+#define BCM2708_DMA_CHANIO(dma_base, n) \
-+ ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
-+
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Auxilliary Functions *
-+ * *
-+\*****************************************************************************/
-+
-+/* A DMA buffer on an arbitrary boundary may separate a cache line into a
-+ section inside the DMA buffer and another section outside it.
-+ Even if we flush DMA buffers from the cache there is always the chance that
-+ during a DMA someone will access the part of a cache line that is outside
-+ the DMA buffer - which will then bring in unwelcome data.
-+ Without being able to dictate our own buffer pools we must insist that
-+ DMA buffers consist of a whole number of cache lines.
-+*/
-+
-+extern int
-+bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
-+{
-+ int i;
-+
-+ for (i = 0; i < sg_len; i++) {
-+ if (sg_ptr[i].offset & CACHE_LINE_MASK ||
-+ sg_ptr[i].length & CACHE_LINE_MASK)
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
-+
-+extern void
-+bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
-+{
-+ dsb(); /* ARM data synchronization (push) operation */
-+
-+ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
-+ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
-+}
-+
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
-+{
-+ dsb();
-+
-+ /* ugly busy wait only option for now */
-+ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
-+ cpu_relax();
-+}
-+
-+EXPORT_SYMBOL_GPL(bcm_dma_start);
-+
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
-+{
-+ dsb();
-+
-+ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
-+
-+/* Complete an ongoing DMA (assuming its results are to be ignored)
-+ Does nothing if there is no DMA in progress.
-+ This routine waits for the current AXI transfer to complete before
-+ terminating the current DMA. If the current transfer is hung on a DREQ used
-+ by an uncooperative peripheral the AXI transfer may never complete. In this
-+ case the routine times out and return a non-zero error code.
-+ Use of this routine doesn't guarantee that the ongoing or aborted DMA
-+ does not produce an interrupt.
-+*/
-+extern int
-+bcm_dma_abort(void __iomem *dma_chan_base)
-+{
-+ unsigned long int cs;
-+ int rc = 0;
-+
-+ cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (BCM2708_DMA_ACTIVE & cs) {
-+ long int timeout = 10000;
-+
-+ /* write 0 to the active bit - pause the DMA */
-+ writel(0, dma_chan_base + BCM2708_DMA_CS);
-+
-+ /* wait for any current AXI transfer to complete */
-+ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
-+ cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+ if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
-+ /* we'll un-pause when we set of our next DMA */
-+ rc = -ETIMEDOUT;
-+
-+ } else if (BCM2708_DMA_ACTIVE & cs) {
-+ /* terminate the control block chain */
-+ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
-+
-+ /* abort the whole DMA */
-+ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
-+ dma_chan_base + BCM2708_DMA_CS);
-+ }
-+ }
-+
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_abort);
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * DMA Manager Device Methods *
-+ * *
-+\*****************************************************************************/
-+
-+struct vc_dmaman {
-+ void __iomem *dma_base;
-+ u32 chan_available; /* bitmap of available channels */
-+ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
-+};
-+
-+static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
-+ u32 chans_available)
-+{
-+ dmaman->dma_base = dma_base;
-+ dmaman->chan_available = chans_available;
-+ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */
-+ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */
-+}
-+
-+static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
-+ unsigned preferred_feature_set)
-+{
-+ u32 chans;
-+ int feature;
-+
-+ chans = dmaman->chan_available;
-+ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
-+ /* select the subset of available channels with the desired
-+ feature so long as some of the candidate channels have that
-+ feature */
-+ if ((preferred_feature_set & (1 << feature)) &&
-+ (chans & dmaman->has_feature[feature]))
-+ chans &= dmaman->has_feature[feature];
-+
-+ if (chans) {
-+ int chan = 0;
-+ /* return the ordinal of the first channel in the bitmap */
-+ while (chans != 0 && (chans & 1) == 0) {
-+ chans >>= 1;
-+ chan++;
-+ }
-+ /* claim the channel */
-+ dmaman->chan_available &= ~(1 << chan);
-+ return chan;
-+ } else
-+ return -ENOMEM;
-+}
-+
-+static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
-+{
-+ if (chan < 0)
-+ return -EINVAL;
-+ else if ((1 << chan) & dmaman->chan_available)
-+ return -EIDRM;
-+ else {
-+ dmaman->chan_available |= (1 << chan);
-+ return 0;
-+ }
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA IRQs *
-+ * *
-+\*****************************************************************************/
-+
-+static unsigned char bcm_dma_irqs[] = {
-+ IRQ_DMA0,
-+ IRQ_DMA1,
-+ IRQ_DMA2,
-+ IRQ_DMA3,
-+ IRQ_DMA4,
-+ IRQ_DMA5,
-+ IRQ_DMA6,
-+ IRQ_DMA7,
-+ IRQ_DMA8,
-+ IRQ_DMA9,
-+ IRQ_DMA10,
-+ IRQ_DMA11,
-+ IRQ_DMA12
-+};
-+
-+
-+/***************************************************************************** \
-+ * *
-+ * DMA Manager Monitor *
-+ * *
-+\*****************************************************************************/
-+
-+static struct device *dmaman_dev; /* we assume there's only one! */
-+
-+extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+ void __iomem **out_dma_base, int *out_dma_irq)
-+{
-+ if (!dmaman_dev)
-+ return -ENODEV;
-+ else {
-+ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
-+ int rc;
-+
-+ device_lock(dmaman_dev);
-+ rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
-+ if (rc >= 0) {
-+ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
-+ rc);
-+ *out_dma_irq = bcm_dma_irqs[rc];
-+ }
-+ device_unlock(dmaman_dev);
-+
-+ return rc;
-+ }
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
-+
-+extern int bcm_dma_chan_free(int channel)
-+{
-+ if (dmaman_dev) {
-+ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
-+ int rc;
-+
-+ device_lock(dmaman_dev);
-+ rc = vc_dmaman_chan_free(dmaman, channel);
-+ device_unlock(dmaman_dev);
-+
-+ return rc;
-+ } else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
-+
-+static int dev_dmaman_register(const char *dev_name, struct device *dev)
-+{
-+ int rc = dmaman_dev ? -EINVAL : 0;
-+ dmaman_dev = dev;
-+ return rc;
-+}
-+
-+static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
-+{
-+ dmaman_dev = NULL;
-+}
-+
-+/*****************************************************************************\
-+ * *
-+ * DMA Device *
-+ * *
-+\*****************************************************************************/
-+
-+static int dmachans = -1; /* module parameter */
-+
-+static int bcm_dmaman_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+ struct vc_dmaman *dmaman;
-+ struct resource *dma_res = NULL;
-+ void __iomem *dma_base = NULL;
-+ int have_dma_region = 0;
-+
-+ dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
-+ if (NULL == dmaman) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "DMA management memory\n");
-+ ret = -ENOMEM;
-+ } else {
-+
-+ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (dma_res == NULL) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
-+ "resource\n");
-+ ret = -ENODEV;
-+ } else if (!request_mem_region(dma_res->start,
-+ resource_size(dma_res),
-+ DRIVER_NAME)) {
-+ dev_err(&pdev->dev, "cannot obtain DMA region\n");
-+ ret = -EBUSY;
-+ } else {
-+ have_dma_region = 1;
-+ dma_base = ioremap(dma_res->start,
-+ resource_size(dma_res));
-+ if (!dma_base) {
-+ dev_err(&pdev->dev, "cannot map DMA region\n");
-+ ret = -ENOMEM;
-+ } else {
-+ /* use module parameter if one was provided */
-+ if (dmachans > 0)
-+ vc_dmaman_init(dmaman, dma_base,
-+ dmachans);
-+ else
-+ vc_dmaman_init(dmaman, dma_base,
-+ DEFAULT_DMACHAN_BITMAP);
-+
-+ platform_set_drvdata(pdev, dmaman);
-+ dev_dmaman_register(DRIVER_NAME, &pdev->dev);
-+
-+ printk(KERN_INFO DRIVER_NAME ": DMA manager "
-+ "at %p\n", dma_base);
-+ }
-+ }
-+ }
-+ if (ret != 0) {
-+ if (dma_base)
-+ iounmap(dma_base);
-+ if (dma_res && have_dma_region)
-+ release_mem_region(dma_res->start,
-+ resource_size(dma_res));
-+ if (dmaman)
-+ kfree(dmaman);
-+ }
-+ return ret;
-+}
-+
-+static int bcm_dmaman_remove(struct platform_device *pdev)
-+{
-+ struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
-+ kfree(dmaman);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm_dmaman_driver = {
-+ .probe = bcm_dmaman_probe,
-+ .remove = bcm_dmaman_remove,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+/*****************************************************************************\
-+ * *
-+ * Driver init/exit *
-+ * *
-+\*****************************************************************************/
-+
-+static int __init bcm_dmaman_drv_init(void)
-+{
-+ int ret;
-+
-+ ret = platform_driver_register(&bcm_dmaman_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to register "
-+ "on platform\n");
-+ }
-+
-+ return ret;
-+}
-+
-+static void __exit bcm_dmaman_drv_exit(void)
-+{
-+ platform_driver_unregister(&bcm_dmaman_driver);
-+}
-+
-+module_init(bcm_dmaman_drv_init);
-+module_exit(bcm_dmaman_drv_exit);
-+
-+module_param(dmachans, int, 0644);
-+
-+MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
-+MODULE_DESCRIPTION("DMA channel manager driver");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/dmaer.c linux-rpi/arch/arm/mach-bcm2709/dmaer.c
---- linux-3.18.14/arch/arm/mach-bcm2709/dmaer.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/dmaer.c 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,886 @@
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/kdev_t.h>
-+#include <linux/fs.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/pagemap.h>
-+#include <linux/device.h>
-+#include <linux/jiffies.h>
-+#include <linux/timex.h>
-+#include <linux/dma-mapping.h>
-+
-+#include <asm/uaccess.h>
-+#include <asm/atomic.h>
-+#include <asm/cacheflush.h>
-+#include <asm/io.h>
-+
-+#include <mach/dma.h>
-+#include <mach/vc_support.h>
-+
-+#ifdef ECLIPSE_IGNORE
-+
-+#define __user
-+#define __init
-+#define __exit
-+#define __iomem
-+#define KERN_DEBUG
-+#define KERN_ERR
-+#define KERN_WARNING
-+#define KERN_INFO
-+#define _IOWR(a, b, c) b
-+#define _IOW(a, b, c) b
-+#define _IO(a, b) b
-+
-+#endif
-+
-+//#define inline
-+
-+#define PRINTK(args...) printk(args)
-+//#define PRINTK_VERBOSE(args...) printk(args)
-+//#define PRINTK(args...)
-+#define PRINTK_VERBOSE(args...)
-+
-+/***** TYPES ****/
-+#define PAGES_PER_LIST 500
-+struct PageList
-+{
-+ struct page *m_pPages[PAGES_PER_LIST];
-+ unsigned int m_used;
-+ struct PageList *m_pNext;
-+};
-+
-+struct VmaPageList
-+{
-+ //each vma has a linked list of pages associated with it
-+ struct PageList *m_pPageHead;
-+ struct PageList *m_pPageTail;
-+ unsigned int m_refCount;
-+};
-+
-+struct DmaControlBlock
-+{
-+ unsigned int m_transferInfo;
-+ void __user *m_pSourceAddr;
-+ void __user *m_pDestAddr;
-+ unsigned int m_xferLen;
-+ unsigned int m_tdStride;
-+ struct DmaControlBlock *m_pNext;
-+ unsigned int m_blank1, m_blank2;
-+};
-+
-+/***** DEFINES ******/
-+//magic number defining the module
-+#define DMA_MAGIC 0xdd
-+
-+//do user virtual to physical translation of the CB chain
-+#define DMA_PREPARE _IOWR(DMA_MAGIC, 0, struct DmaControlBlock *)
-+
-+//kick the pre-prepared CB chain
-+#define DMA_KICK _IOW(DMA_MAGIC, 1, struct DmaControlBlock *)
-+
-+//prepare it, kick it, wait for it
-+#define DMA_PREPARE_KICK_WAIT _IOWR(DMA_MAGIC, 2, struct DmaControlBlock *)
-+
-+//prepare it, kick it, don't wait for it
-+#define DMA_PREPARE_KICK _IOWR(DMA_MAGIC, 3, struct DmaControlBlock *)
-+
-+//not currently implemented
-+#define DMA_WAIT_ONE _IO(DMA_MAGIC, 4, struct DmaControlBlock *)
-+
-+//wait on all kicked CB chains
-+#define DMA_WAIT_ALL _IO(DMA_MAGIC, 5)
-+
-+//in order to discover the largest AXI burst that should be programmed into the transfer params
-+#define DMA_MAX_BURST _IO(DMA_MAGIC, 6)
-+
-+//set the address range through which the user address is assumed to already by a physical address
-+#define DMA_SET_MIN_PHYS _IOW(DMA_MAGIC, 7, unsigned long)
-+#define DMA_SET_MAX_PHYS _IOW(DMA_MAGIC, 8, unsigned long)
-+#define DMA_SET_PHYS_OFFSET _IOW(DMA_MAGIC, 9, unsigned long)
-+
-+//used to define the size for the CMA-based allocation *in pages*, can only be done once once the file is opened
-+#define DMA_CMA_SET_SIZE _IOW(DMA_MAGIC, 10, unsigned long)
-+
-+//used to get the version of the module, to test for a capability
-+#define DMA_GET_VERSION _IO(DMA_MAGIC, 99)
-+
-+#define VERSION_NUMBER 1
-+
-+#define VIRT_TO_BUS_CACHE_SIZE 8
-+
-+/***** FILE OPS *****/
-+static int Open(struct inode *pInode, struct file *pFile);
-+static int Release(struct inode *pInode, struct file *pFile);
-+static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg);
-+static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp);
-+static int Mmap(struct file *pFile, struct vm_area_struct *pVma);
-+
-+/***** VMA OPS ****/
-+static void VmaOpen4k(struct vm_area_struct *pVma);
-+static void VmaClose4k(struct vm_area_struct *pVma);
-+static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf);
-+
-+/**** DMA PROTOTYPES */
-+static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError);
-+static int DmaKick(struct DmaControlBlock __user *pUserCB);
-+static void DmaWaitAll(void);
-+
-+/**** GENERIC ****/
-+static int __init dmaer_init(void);
-+static void __exit dmaer_exit(void);
-+
-+/*** OPS ***/
-+static struct vm_operations_struct g_vmOps4k = {
-+ .open = VmaOpen4k,
-+ .close = VmaClose4k,
-+ .fault = VmaFault4k,
-+};
-+
-+static struct file_operations g_fOps = {
-+ .owner = THIS_MODULE,
-+ .llseek = 0,
-+ .read = Read,
-+ .write = 0,
-+ .unlocked_ioctl = Ioctl,
-+ .open = Open,
-+ .release = Release,
-+ .mmap = Mmap,
-+};
-+
-+/***** GLOBALS ******/
-+static dev_t g_majorMinor;
-+
-+//tracking usage of the two files
-+static atomic_t g_oneLock4k = ATOMIC_INIT(1);
-+
-+//device operations
-+static struct cdev g_cDev;
-+static int g_trackedPages = 0;
-+
-+//dma control
-+static unsigned int *g_pDmaChanBase;
-+static int g_dmaIrq;
-+static int g_dmaChan;
-+
-+//cma allocation
-+static int g_cmaHandle;
-+
-+//user virtual to bus address translation acceleration
-+static unsigned long g_virtAddr[VIRT_TO_BUS_CACHE_SIZE];
-+static unsigned long g_busAddr[VIRT_TO_BUS_CACHE_SIZE];
-+static unsigned long g_cbVirtAddr;
-+static unsigned long g_cbBusAddr;
-+static int g_cacheInsertAt;
-+static int g_cacheHit, g_cacheMiss;
-+
-+//off by default
-+static void __user *g_pMinPhys;
-+static void __user *g_pMaxPhys;
-+static unsigned long g_physOffset;
-+
-+/****** CACHE OPERATIONS ********/
-+static inline void FlushAddrCache(void)
-+{
-+ int count = 0;
-+ for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
-+ g_virtAddr[count] = 0xffffffff; //never going to match as we always chop the bottom bits anyway
-+
-+ g_cbVirtAddr = 0xffffffff;
-+
-+ g_cacheInsertAt = 0;
-+}
-+
-+//translate from a user virtual address to a bus address by mapping the page
-+//NB this won't lock a page in memory, so to avoid potential paging issues using kernel logical addresses
-+static inline void __iomem *UserVirtualToBus(void __user *pUser)
-+{
-+ int mapped;
-+ struct page *pPage;
-+ void *phys;
-+
-+ //map it (requiring that the pointer points to something that does not hang off the page boundary)
-+ mapped = get_user_pages(current, current->mm,
-+ (unsigned long)pUser, 1,
-+ 1, 0,
-+ &pPage,
-+ 0);
-+
-+ if (mapped <= 0) //error
-+ return 0;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "user virtual %p arm phys %p bus %p\n",
-+ pUser, page_address(pPage), (void __iomem *)__virt_to_bus(page_address(pPage)));
-+
-+ //get the arm physical address
-+ phys = page_address(pPage) + offset_in_page(pUser);
-+ page_cache_release(pPage);
-+
-+ //and now the bus address
-+ return (void __iomem *)__virt_to_bus(phys);
-+}
-+
-+static inline void __iomem *UserVirtualToBusViaCbCache(void __user *pUser)
-+{
-+ unsigned long virtual_page = (unsigned long)pUser & ~4095;
-+ unsigned long page_offset = (unsigned long)pUser & 4095;
-+ unsigned long bus_addr;
-+
-+ if (g_cbVirtAddr == virtual_page)
-+ {
-+ bus_addr = g_cbBusAddr + page_offset;
-+ g_cacheHit++;
-+ return (void __iomem *)bus_addr;
-+ }
-+ else
-+ {
-+ bus_addr = (unsigned long)UserVirtualToBus(pUser);
-+
-+ if (!bus_addr)
-+ return 0;
-+
-+ g_cbVirtAddr = virtual_page;
-+ g_cbBusAddr = bus_addr & ~4095;
-+ g_cacheMiss++;
-+
-+ return (void __iomem *)bus_addr;
-+ }
-+}
-+
-+//do the same as above, by query our virt->bus cache
-+static inline void __iomem *UserVirtualToBusViaCache(void __user *pUser)
-+{
-+ int count;
-+ //get the page and its offset
-+ unsigned long virtual_page = (unsigned long)pUser & ~4095;
-+ unsigned long page_offset = (unsigned long)pUser & 4095;
-+ unsigned long bus_addr;
-+
-+ if (pUser >= g_pMinPhys && pUser < g_pMaxPhys)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "user->phys passthrough on %p\n", pUser);
-+ return (void __iomem *)((unsigned long)pUser + g_physOffset);
-+ }
-+
-+ //check the cache for our entry
-+ for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
-+ if (g_virtAddr[count] == virtual_page)
-+ {
-+ bus_addr = g_busAddr[count] + page_offset;
-+ g_cacheHit++;
-+ return (void __iomem *)bus_addr;
-+ }
-+
-+ //not found, look up manually and then insert its page address
-+ bus_addr = (unsigned long)UserVirtualToBus(pUser);
-+
-+ if (!bus_addr)
-+ return 0;
-+
-+ g_virtAddr[g_cacheInsertAt] = virtual_page;
-+ g_busAddr[g_cacheInsertAt] = bus_addr & ~4095;
-+
-+ //round robin
-+ g_cacheInsertAt++;
-+ if (g_cacheInsertAt == VIRT_TO_BUS_CACHE_SIZE)
-+ g_cacheInsertAt = 0;
-+
-+ g_cacheMiss++;
-+
-+ return (void __iomem *)bus_addr;
-+}
-+
-+/***** FILE OPERATIONS ****/
-+static int Open(struct inode *pInode, struct file *pFile)
-+{
-+ PRINTK(KERN_DEBUG "file opening: %d/%d\n", imajor(pInode), iminor(pInode));
-+
-+ //check which device we are
-+ if (iminor(pInode) == 0) //4k
-+ {
-+ //only one at a time
-+ if (!atomic_dec_and_test(&g_oneLock4k))
-+ {
-+ atomic_inc(&g_oneLock4k);
-+ return -EBUSY;
-+ }
-+ }
-+ else
-+ return -EINVAL;
-+
-+ //todo there will be trouble if two different processes open the files
-+
-+ //reset after any file is opened
-+ g_pMinPhys = (void __user *)-1;
-+ g_pMaxPhys = (void __user *)0;
-+ g_physOffset = 0;
-+ g_cmaHandle = 0;
-+
-+ return 0;
-+}
-+
-+static int Release(struct inode *pInode, struct file *pFile)
-+{
-+ PRINTK(KERN_DEBUG "file closing, %d pages tracked\n", g_trackedPages);
-+ if (g_trackedPages)
-+ PRINTK(KERN_ERR "we\'re leaking memory!\n");
-+
-+ //wait for any dmas to finish
-+ DmaWaitAll();
-+
-+ //free this memory on the application closing the file or it crashing (implicitly closing the file)
-+ if (g_cmaHandle)
-+ {
-+ PRINTK(KERN_DEBUG "unlocking vc memory\n");
-+ if (UnlockVcMemory(g_cmaHandle))
-+ PRINTK(KERN_ERR "uh-oh, unable to unlock vc memory!\n");
-+ PRINTK(KERN_DEBUG "releasing vc memory\n");
-+ if (ReleaseVcMemory(g_cmaHandle))
-+ PRINTK(KERN_ERR "uh-oh, unable to release vc memory!\n");
-+ }
-+
-+ if (iminor(pInode) == 0)
-+ atomic_inc(&g_oneLock4k);
-+ else
-+ return -EINVAL;
-+
-+ return 0;
-+}
-+
-+static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError)
-+{
-+ struct DmaControlBlock kernCB;
-+ struct DmaControlBlock __user *pUNext;
-+ void __iomem *pSourceBus, __iomem *pDestBus;
-+
-+ //get the control block into kernel memory so we can work on it
-+ if (copy_from_user(&kernCB, pUserCB, sizeof(struct DmaControlBlock)) != 0)
-+ {
-+ PRINTK(KERN_ERR "copy_from_user failed for user cb %p\n", pUserCB);
-+ *pError = 1;
-+ return 0;
-+ }
-+
-+ if (kernCB.m_pSourceAddr == 0 || kernCB.m_pDestAddr == 0)
-+ {
-+ PRINTK(KERN_ERR "faulty source (%p) dest (%p) addresses for user cb %p\n",
-+ kernCB.m_pSourceAddr, kernCB.m_pDestAddr, pUserCB);
-+ *pError = 1;
-+ return 0;
-+ }
-+
-+ pSourceBus = UserVirtualToBusViaCache(kernCB.m_pSourceAddr);
-+ pDestBus = UserVirtualToBusViaCache(kernCB.m_pDestAddr);
-+
-+ if (!pSourceBus || !pDestBus)
-+ {
-+ PRINTK(KERN_ERR "virtual to bus translation failure for source/dest %p/%p->%p/%p\n",
-+ kernCB.m_pSourceAddr, kernCB.m_pDestAddr,
-+ pSourceBus, pDestBus);
-+ *pError = 1;
-+ return 0;
-+ }
-+
-+ //update the user structure with the new bus addresses
-+ kernCB.m_pSourceAddr = pSourceBus;
-+ kernCB.m_pDestAddr = pDestBus;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "final source %p dest %p\n", kernCB.m_pSourceAddr, kernCB.m_pDestAddr);
-+
-+ //sort out the bus address for the next block
-+ pUNext = kernCB.m_pNext;
-+
-+ if (kernCB.m_pNext)
-+ {
-+ void __iomem *pNextBus;
-+ pNextBus = UserVirtualToBusViaCbCache(kernCB.m_pNext);
-+
-+ if (!pNextBus)
-+ {
-+ PRINTK(KERN_ERR "virtual to bus translation failure for m_pNext\n");
-+ *pError = 1;
-+ return 0;
-+ }
-+
-+ //update the pointer with the bus address
-+ kernCB.m_pNext = pNextBus;
-+ }
-+
-+ //write it back to user space
-+ if (copy_to_user(pUserCB, &kernCB, sizeof(struct DmaControlBlock)) != 0)
-+ {
-+ PRINTK(KERN_ERR "copy_to_user failed for cb %p\n", pUserCB);
-+ *pError = 1;
-+ return 0;
-+ }
-+
-+ __cpuc_flush_dcache_area(pUserCB, 32);
-+
-+ *pError = 0;
-+ return pUNext;
-+}
-+
-+static int DmaKick(struct DmaControlBlock __user *pUserCB)
-+{
-+ void __iomem *pBusCB;
-+
-+ pBusCB = UserVirtualToBusViaCbCache(pUserCB);
-+ if (!pBusCB)
-+ {
-+ PRINTK(KERN_ERR "virtual to bus translation failure for cb\n");
-+ return 1;
-+ }
-+
-+ //flush_cache_all();
-+
-+ bcm_dma_start(g_pDmaChanBase, (dma_addr_t)pBusCB);
-+
-+ return 0;
-+}
-+
-+static void DmaWaitAll(void)
-+{
-+ int counter = 0;
-+ volatile int inner_count;
-+ volatile unsigned int cs;
-+ unsigned long time_before, time_after;
-+
-+ time_before = jiffies;
-+ //bcm_dma_wait_idle(g_pDmaChanBase);
-+ dsb();
-+
-+ cs = readl(g_pDmaChanBase);
-+
-+ while ((cs & 1) == 1)
-+ {
-+ cs = readl(g_pDmaChanBase);
-+ counter++;
-+
-+ for (inner_count = 0; inner_count < 32; inner_count++);
-+
-+ asm volatile ("MCR p15,0,r0,c7,c0,4 \n");
-+ //cpu_do_idle();
-+ if (counter >= 1000000)
-+ {
-+ PRINTK(KERN_WARNING "DMA failed to finish in a timely fashion\n");
-+ break;
-+ }
-+ }
-+ time_after = jiffies;
-+ PRINTK_VERBOSE(KERN_DEBUG "done, counter %d, cs %08x", counter, cs);
-+ PRINTK_VERBOSE(KERN_DEBUG "took %ld jiffies, %d HZ\n", time_after - time_before, HZ);
-+}
-+
-+static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg)
-+{
-+ int error = 0;
-+ PRINTK_VERBOSE(KERN_DEBUG "ioctl cmd %x arg %lx\n", cmd, arg);
-+
-+ switch (cmd)
-+ {
-+ case DMA_PREPARE:
-+ case DMA_PREPARE_KICK:
-+ case DMA_PREPARE_KICK_WAIT:
-+ {
-+ struct DmaControlBlock __user *pUCB = (struct DmaControlBlock *)arg;
-+ int steps = 0;
-+ unsigned long start_time = jiffies;
-+ (void)start_time;
-+
-+ //flush our address cache
-+ FlushAddrCache();
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "dma prepare\n");
-+
-+ //do virtual to bus translation for each entry
-+ do
-+ {
-+ pUCB = DmaPrepare(pUCB, &error);
-+ } while (error == 0 && ++steps && pUCB);
-+ PRINTK_VERBOSE(KERN_DEBUG "prepare done in %d steps, %ld\n", steps, jiffies - start_time);
-+
-+ //carry straight on if we want to kick too
-+ if (cmd == DMA_PREPARE || error)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "falling out\n");
-+ return error ? -EINVAL : 0;
-+ }
-+ }
-+ case DMA_KICK:
-+ PRINTK_VERBOSE(KERN_DEBUG "dma begin\n");
-+
-+ if (cmd == DMA_KICK)
-+ FlushAddrCache();
-+
-+ DmaKick((struct DmaControlBlock __user *)arg);
-+
-+ if (cmd != DMA_PREPARE_KICK_WAIT)
-+ break;
-+/* case DMA_WAIT_ONE:
-+ //PRINTK(KERN_DEBUG "dma wait one\n");
-+ break;*/
-+ case DMA_WAIT_ALL:
-+ //PRINTK(KERN_DEBUG "dma wait all\n");
-+ DmaWaitAll();
-+ break;
-+ case DMA_MAX_BURST:
-+ if (g_dmaChan == 0)
-+ return 10;
-+ else
-+ return 5;
-+ case DMA_SET_MIN_PHYS:
-+ g_pMinPhys = (void __user *)arg;
-+ PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
-+ break;
-+ case DMA_SET_MAX_PHYS:
-+ g_pMaxPhys = (void __user *)arg;
-+ PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
-+ break;
-+ case DMA_SET_PHYS_OFFSET:
-+ g_physOffset = arg;
-+ PRINTK(KERN_DEBUG "user/phys bypass offset set to %ld\n", g_physOffset);
-+ break;
-+ case DMA_CMA_SET_SIZE:
-+ {
-+ unsigned int pBusAddr;
-+
-+ if (g_cmaHandle)
-+ {
-+ PRINTK(KERN_ERR "memory has already been allocated (handle %d)\n", g_cmaHandle);
-+ return -EINVAL;
-+ }
-+
-+ PRINTK(KERN_INFO "allocating %ld bytes of VC memory\n", arg * 4096);
-+
-+ //get the memory
-+ if (AllocateVcMemory(&g_cmaHandle, arg * 4096, 4096, MEM_FLAG_L1_NONALLOCATING | MEM_FLAG_NO_INIT | MEM_FLAG_HINT_PERMALOCK))
-+ {
-+ PRINTK(KERN_ERR "failed to allocate %ld bytes of VC memory\n", arg * 4096);
-+ g_cmaHandle = 0;
-+ return -EINVAL;
-+ }
-+
-+ //get an address for it
-+ PRINTK(KERN_INFO "trying to map VC memory\n");
-+
-+ if (LockVcMemory(&pBusAddr, g_cmaHandle))
-+ {
-+ PRINTK(KERN_ERR "failed to map CMA handle %d, releasing memory\n", g_cmaHandle);
-+ ReleaseVcMemory(g_cmaHandle);
-+ g_cmaHandle = 0;
-+ }
-+
-+ PRINTK(KERN_INFO "bus address for CMA memory is %x\n", pBusAddr);
-+ return pBusAddr;
-+ }
-+ case DMA_GET_VERSION:
-+ PRINTK(KERN_DEBUG "returning version number, %d\n", VERSION_NUMBER);
-+ return VERSION_NUMBER;
-+ default:
-+ PRINTK(KERN_DEBUG "unknown ioctl: %d\n", cmd);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp)
-+{
-+ return -EIO;
-+}
-+
-+static int Mmap(struct file *pFile, struct vm_area_struct *pVma)
-+{
-+ struct PageList *pPages;
-+ struct VmaPageList *pVmaList;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "MMAP vma %p, length %ld (%s %d)\n",
-+ pVma, pVma->vm_end - pVma->vm_start,
-+ current->comm, current->pid);
-+ PRINTK_VERBOSE(KERN_DEBUG "MMAP %p %d (tracked %d)\n", pVma, current->pid, g_trackedPages);
-+
-+ //make a new page list
-+ pPages = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
-+ if (!pPages)
-+ {
-+ PRINTK(KERN_ERR "couldn\'t allocate a new page list (%s %d)\n",
-+ current->comm, current->pid);
-+ return -ENOMEM;
-+ }
-+
-+ //clear the page list
-+ pPages->m_used = 0;
-+ pPages->m_pNext = 0;
-+
-+ //insert our vma and new page list somewhere
-+ if (!pVma->vm_private_data)
-+ {
-+ struct VmaPageList *pList;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "new vma list, making new one (%s %d)\n",
-+ current->comm, current->pid);
-+
-+ //make a new vma list
-+ pList = (struct VmaPageList *)kmalloc(sizeof(struct VmaPageList), GFP_KERNEL);
-+ if (!pList)
-+ {
-+ PRINTK(KERN_ERR "couldn\'t allocate vma page list (%s %d)\n",
-+ current->comm, current->pid);
-+ kfree(pPages);
-+ return -ENOMEM;
-+ }
-+
-+ //clear this list
-+ pVma->vm_private_data = (void *)pList;
-+ pList->m_refCount = 0;
-+ }
-+
-+ pVmaList = (struct VmaPageList *)pVma->vm_private_data;
-+
-+ //add it to the vma list
-+ pVmaList->m_pPageHead = pPages;
-+ pVmaList->m_pPageTail = pPages;
-+
-+ pVma->vm_ops = &g_vmOps4k;
-+ pVma->vm_flags |= VM_IO;
-+
-+ VmaOpen4k(pVma);
-+
-+ return 0;
-+}
-+
-+/****** VMA OPERATIONS ******/
-+
-+static void VmaOpen4k(struct vm_area_struct *pVma)
-+{
-+ struct VmaPageList *pVmaList;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "vma open %p private %p (%s %d), %d live pages\n", pVma, pVma->vm_private_data, current->comm, current->pid, g_trackedPages);
-+ PRINTK_VERBOSE(KERN_DEBUG "OPEN %p %d %ld pages (tracked pages %d)\n",
-+ pVma, current->pid, (pVma->vm_end - pVma->vm_start) >> 12,
-+ g_trackedPages);
-+
-+ pVmaList = (struct VmaPageList *)pVma->vm_private_data;
-+
-+ if (pVmaList)
-+ {
-+ pVmaList->m_refCount++;
-+ PRINTK_VERBOSE(KERN_DEBUG "ref count is now %d\n", pVmaList->m_refCount);
-+ }
-+ else
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "err, open but no vma page list\n");
-+ }
-+}
-+
-+static void VmaClose4k(struct vm_area_struct *pVma)
-+{
-+ struct VmaPageList *pVmaList;
-+ int freed = 0;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "vma close %p private %p (%s %d)\n", pVma, pVma->vm_private_data, current->comm, current->pid);
-+
-+ //wait for any dmas to finish
-+ DmaWaitAll();
-+
-+ //find our vma in the list
-+ pVmaList = (struct VmaPageList *)pVma->vm_private_data;
-+
-+ //may be a fork
-+ if (pVmaList)
-+ {
-+ struct PageList *pPages;
-+
-+ pVmaList->m_refCount--;
-+
-+ if (pVmaList->m_refCount == 0)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "found vma, freeing pages (%s %d)\n",
-+ current->comm, current->pid);
-+
-+ pPages = pVmaList->m_pPageHead;
-+
-+ if (!pPages)
-+ {
-+ PRINTK(KERN_ERR "no page list (%s %d)!\n",
-+ current->comm, current->pid);
-+ return;
-+ }
-+
-+ while (pPages)
-+ {
-+ struct PageList *next;
-+ int count;
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "page list (%s %d)\n",
-+ current->comm, current->pid);
-+
-+ next = pPages->m_pNext;
-+ for (count = 0; count < pPages->m_used; count++)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "freeing page %p (%s %d)\n",
-+ pPages->m_pPages[count],
-+ current->comm, current->pid);
-+ __free_pages(pPages->m_pPages[count], 0);
-+ g_trackedPages--;
-+ freed++;
-+ }
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "freeing page list (%s %d)\n",
-+ current->comm, current->pid);
-+ kfree(pPages);
-+ pPages = next;
-+ }
-+
-+ //remove our vma from the list
-+ kfree(pVmaList);
-+ pVma->vm_private_data = 0;
-+ }
-+ else
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "ref count is %d, not closing\n", pVmaList->m_refCount);
-+ }
-+ }
-+ else
-+ {
-+ PRINTK_VERBOSE(KERN_ERR "uh-oh, vma %p not found (%s %d)!\n", pVma, current->comm, current->pid);
-+ PRINTK_VERBOSE(KERN_ERR "CLOSE ERR\n");
-+ }
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "CLOSE %p %d %d pages (tracked pages %d)",
-+ pVma, current->pid, freed, g_trackedPages);
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "%d pages open\n", g_trackedPages);
-+}
-+
-+static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf)
-+{
-+ PRINTK_VERBOSE(KERN_DEBUG "vma fault for vma %p private %p at offset %ld (%s %d)\n", pVma, pVma->vm_private_data, pVmf->pgoff,
-+ current->comm, current->pid);
-+ PRINTK_VERBOSE(KERN_DEBUG "FAULT\n");
-+ pVmf->page = alloc_page(GFP_KERNEL);
-+
-+ if (pVmf->page)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "alloc page virtual %p\n", page_address(pVmf->page));
-+ }
-+
-+ if (!pVmf->page)
-+ {
-+ PRINTK(KERN_ERR "vma fault oom (%s %d)\n", current->comm, current->pid);
-+ return VM_FAULT_OOM;
-+ }
-+ else
-+ {
-+ struct VmaPageList *pVmaList;
-+
-+ get_page(pVmf->page);
-+ g_trackedPages++;
-+
-+ //find our vma in the list
-+ pVmaList = (struct VmaPageList *)pVma->vm_private_data;
-+
-+ if (pVmaList)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "vma found (%s %d)\n", current->comm, current->pid);
-+
-+ if (pVmaList->m_pPageTail->m_used == PAGES_PER_LIST)
-+ {
-+ PRINTK_VERBOSE(KERN_DEBUG "making new page list (%s %d)\n", current->comm, current->pid);
-+ //making a new page list
-+ pVmaList->m_pPageTail->m_pNext = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
-+ if (!pVmaList->m_pPageTail->m_pNext)
-+ return -ENOMEM;
-+
-+ //update the tail pointer
-+ pVmaList->m_pPageTail = pVmaList->m_pPageTail->m_pNext;
-+ pVmaList->m_pPageTail->m_used = 0;
-+ pVmaList->m_pPageTail->m_pNext = 0;
-+ }
-+
-+ PRINTK_VERBOSE(KERN_DEBUG "adding page to list (%s %d)\n", current->comm, current->pid);
-+
-+ pVmaList->m_pPageTail->m_pPages[pVmaList->m_pPageTail->m_used] = pVmf->page;
-+ pVmaList->m_pPageTail->m_used++;
-+ }
-+ else
-+ PRINTK(KERN_ERR "returned page for vma we don\'t know %p (%s %d)\n", pVma, current->comm, current->pid);
-+
-+ return 0;
-+ }
-+}
-+
-+/****** GENERIC FUNCTIONS ******/
-+static int __init dmaer_init(void)
-+{
-+ int result = alloc_chrdev_region(&g_majorMinor, 0, 1, "dmaer");
-+ if (result < 0)
-+ {
-+ PRINTK(KERN_ERR "unable to get major device number\n");
-+ return result;
-+ }
-+ else
-+ PRINTK(KERN_DEBUG "major device number %d\n", MAJOR(g_majorMinor));
-+
-+ PRINTK(KERN_DEBUG "vma list size %d, page list size %d, page size %ld\n",
-+ sizeof(struct VmaPageList), sizeof(struct PageList), PAGE_SIZE);
-+
-+ //get a dma channel to work with
-+ result = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, (void **)&g_pDmaChanBase, &g_dmaIrq);
-+
-+ //uncomment to force to channel 0
-+ //result = 0;
-+ //g_pDmaChanBase = 0xce808000;
-+
-+ if (result < 0)
-+ {
-+ PRINTK(KERN_ERR "failed to allocate dma channel\n");
-+ cdev_del(&g_cDev);
-+ unregister_chrdev_region(g_majorMinor, 1);
-+ }
-+
-+ //reset the channel
-+ PRINTK(KERN_DEBUG "allocated dma channel %d (%p), initial state %08x\n", result, g_pDmaChanBase, *g_pDmaChanBase);
-+ *g_pDmaChanBase = 1 << 31;
-+ PRINTK(KERN_DEBUG "post-reset %08x\n", *g_pDmaChanBase);
-+
-+ g_dmaChan = result;
-+
-+ //clear the cache stats
-+ g_cacheHit = 0;
-+ g_cacheMiss = 0;
-+
-+ //register our device - after this we are go go go
-+ cdev_init(&g_cDev, &g_fOps);
-+ g_cDev.owner = THIS_MODULE;
-+ g_cDev.ops = &g_fOps;
-+
-+ result = cdev_add(&g_cDev, g_majorMinor, 1);
-+ if (result < 0)
-+ {
-+ PRINTK(KERN_ERR "failed to add character device\n");
-+ unregister_chrdev_region(g_majorMinor, 1);
-+ bcm_dma_chan_free(g_dmaChan);
-+ return result;
-+ }
-+
-+ return 0;
-+}
-+
-+static void __exit dmaer_exit(void)
-+{
-+ PRINTK(KERN_INFO "closing dmaer device, cache stats: %d hits %d misses\n", g_cacheHit, g_cacheMiss);
-+ //unregister the device
-+ cdev_del(&g_cDev);
-+ unregister_chrdev_region(g_majorMinor, 1);
-+ //free the dma channel
-+ bcm_dma_chan_free(g_dmaChan);
-+}
-+
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_AUTHOR("Simon Hall");
-+module_init(dmaer_init);
-+module_exit(dmaer_exit);
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/arm_control.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,493 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/arm_control.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef __BCM2708_ARM_CONTROL_H
-+#define __BCM2708_ARM_CONTROL_H
-+
-+/*
-+ * Definitions and addresses for the ARM CONTROL logic
-+ * This file is manually generated.
-+ */
-+
-+#define ARM_BASE 0x7E00B000
-+
-+/* Basic configuration */
-+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
-+#define ARM_C0_SIZ128M 0x00000000
-+#define ARM_C0_SIZ256M 0x00000001
-+#define ARM_C0_SIZ512M 0x00000002
-+#define ARM_C0_SIZ1G 0x00000003
-+#define ARM_C0_BRESP0 0x00000000
-+#define ARM_C0_BRESP1 0x00000004
-+#define ARM_C0_BRESP2 0x00000008
-+#define ARM_C0_BOOTHI 0x00000010
-+#define ARM_C0_UNUSED05 0x00000020 /* free */
-+#define ARM_C0_FULLPERI 0x00000040
-+#define ARM_C0_UNUSED78 0x00000180 /* free */
-+#define ARM_C0_JTAGMASK 0x00000E00
-+#define ARM_C0_JTAGOFF 0x00000000
-+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
-+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
-+#define ARM_C0_APROTMSK 0x0000F000
-+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
-+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
-+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
-+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
-+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
-+#define ARM_C0_PRIO_L2 0x0F000000
-+#define ARM_C0_PRIO_UC 0xF0000000
-+
-+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
-+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
-+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
-+
-+
-+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
-+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
-+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
-+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
-+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
-+#define ARM_C1_PERSON 0x00000100 /* peripherals on */
-+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
-+
-+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
-+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
-+#define ARM_S_READPEND 0x000003FF /* pending reads counter */
-+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
-+
-+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
-+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
-+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
-+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
-+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
-+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
-+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
-+
-+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
-+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
-+#define ARM_IDVAL 0x364D5241
-+
-+/* Translation memory */
-+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
-+/* 32 locations: 0x100.. 0x17F */
-+/* 32 spare means we CAN go to 64 pages.... */
-+
-+
-+/* Interrupts */
-+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
-+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
-+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
-+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
-+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
-+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
-+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
-+
-+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
-+/* todo: all I1_interrupt sources */
-+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
-+/* todo: all I2_interrupt sources */
-+
-+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
-+#define ARM_IF_INDEX 0x0000007F /* FIQ select */
-+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
-+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
-+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
-+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
-+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
-+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
-+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
-+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
-+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
-+
-+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
-+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
-+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
-+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
-+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
-+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
-+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
-+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
-+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
-+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
-+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
-+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
-+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
-+
-+/* Timer */
-+/* For reg. fields see sp804 spec. */
-+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
-+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
-+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
-+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
-+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
-+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
-+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
-+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
-+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
-+
-+#define TIMER_CTRL_ONESHOT (1 << 0)
-+#define TIMER_CTRL_32BIT (1 << 1)
-+#define TIMER_CTRL_DIV1 (0 << 2)
-+#define TIMER_CTRL_DIV16 (1 << 2)
-+#define TIMER_CTRL_DIV256 (2 << 2)
-+#define TIMER_CTRL_IE (1 << 5)
-+#define TIMER_CTRL_PERIODIC (1 << 6)
-+#define TIMER_CTRL_ENABLE (1 << 7)
-+#define TIMER_CTRL_DBGHALT (1 << 8)
-+#define TIMER_CTRL_ENAFREE (1 << 9)
-+#define TIMER_CTRL_FREEDIV_SHIFT 16)
-+#define TIMER_CTRL_FREEDIV_MASK 0xff
-+
-+/* Semaphores, Doorbells, Mailboxes */
-+#define ARM_SBM_OWN0 (ARM_BASE+0x800)
-+#define ARM_SBM_OWN1 (ARM_BASE+0x900)
-+#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
-+#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
-+
-+/* MAILBOXES
-+ * Register flags are common across all
-+ * owner registers. See end of this section
-+ *
-+ * Semaphores, Doorbells, Mailboxes Owner 0
-+ *
-+ */
-+
-+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
-+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
-+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
-+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
-+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
-+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
-+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
-+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
-+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
-+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
-+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
-+/* MAILBOX 0 access in Owner 0 area */
-+/* Some addresses should ONLY be used by owner 0 */
-+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
-+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
-+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
-+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
-+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
-+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
-+/* MAILBOX 1 access in Owner 0 area */
-+/* Owner 0 should only WRITE to this mailbox */
-+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
-+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
-+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
-+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
-+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 1 */
-+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
-+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
-+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
-+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
-+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
-+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
-+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
-+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
-+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
-+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
-+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
-+/* MAILBOX 0 access in Owner 0 area */
-+/* Owner 1 should only WRITE to this mailbox */
-+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
-+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 0 area */
-+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
-+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
-+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
-+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
-+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
-+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
-+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
-+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
-+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 2 */
-+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
-+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
-+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
-+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
-+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
-+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
-+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
-+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
-+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
-+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
-+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
-+/* MAILBOX 0 access in Owner 2 area */
-+/* Owner 2 should only WRITE to this mailbox */
-+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
-+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 2 area */
-+/* Owner 2 should only WRITE to this mailbox */
-+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
-+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
-+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
-+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
-+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
-+
-+/* Semaphores, Doorbells, Mailboxes Owner 3 */
-+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
-+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
-+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
-+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
-+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
-+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
-+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
-+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
-+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
-+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
-+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
-+/* MAILBOX 0 access in Owner 3 area */
-+/* Owner 3 should only WRITE to this mailbox */
-+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
-+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
-+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
-+/* MAILBOX 1 access in Owner 3 area */
-+/* Owner 3 should only WRITE to this mailbox */
-+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
-+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
-+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
-+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
-+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
-+/* General SEM, BELL, MAIL config/status */
-+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
-+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
-+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
-+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
-+
-+
-+
-+/* Mailbox flags. Valid for all owners */
-+
-+/* Mailbox status register (...0x98) */
-+#define ARM_MS_FULL 0x80000000
-+#define ARM_MS_EMPTY 0x40000000
-+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
-+
-+/* MAILBOX config/status register (...0x9C) */
-+/* ANY write to this register clears the error bits! */
-+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
-+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
-+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
-+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
-+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
-+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
-+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
-+/* Bit 7 is unused */
-+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
-+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
-+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
-+
-+/* Semaphore clear/debug register (...0xE0) */
-+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
-+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
-+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
-+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
-+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
-+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
-+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
-+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
-+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
-+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
-+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
-+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
-+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
-+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
-+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
-+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
-+
-+/* Doorbells clear/debug register (...0xE4) */
-+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
-+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
-+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
-+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
-+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
-+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
-+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
-+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
-+
-+/* MY IRQS register (...0xF8) */
-+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
-+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
-+
-+/* ALL IRQS register (...0xF8) */
-+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
-+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
-+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
-+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
-+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
-+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
-+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
-+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
-+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
-+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
-+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
-+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
-+/* */
-+/* ARM JTAG BASH */
-+/* */
-+#define AJB_BASE 0x7e2000c0
-+
-+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
-+#define AJB_BITS0 0x000000
-+#define AJB_BITS4 0x000004
-+#define AJB_BITS8 0x000008
-+#define AJB_BITS12 0x00000C
-+#define AJB_BITS16 0x000010
-+#define AJB_BITS20 0x000014
-+#define AJB_BITS24 0x000018
-+#define AJB_BITS28 0x00001C
-+#define AJB_BITS32 0x000020
-+#define AJB_BITS34 0x000022
-+#define AJB_OUT_MS 0x000040
-+#define AJB_OUT_LS 0x000000
-+#define AJB_INV_CLK 0x000080
-+#define AJB_D0_RISE 0x000100
-+#define AJB_D0_FALL 0x000000
-+#define AJB_D1_RISE 0x000200
-+#define AJB_D1_FALL 0x000000
-+#define AJB_IN_RISE 0x000400
-+#define AJB_IN_FALL 0x000000
-+#define AJB_ENABLE 0x000800
-+#define AJB_HOLD0 0x000000
-+#define AJB_HOLD1 0x001000
-+#define AJB_HOLD2 0x002000
-+#define AJB_HOLD3 0x003000
-+#define AJB_RESETN 0x004000
-+#define AJB_CLKSHFT 16
-+#define AJB_BUSY 0x80000000
-+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
-+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
-+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
-+
-+#define ARM_LOCAL_BASE 0x40000000
-+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
-+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
-+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
-+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
-+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
-+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
-+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
-+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
-+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
-+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
-+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
-+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
-+
-+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
-+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
-+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
-+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
-+
-+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
-+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
-+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
-+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
-+
-+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
-+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
-+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
-+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
-+
-+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
-+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
-+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
-+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
-+
-+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
-+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
-+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
-+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
-+
-+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
-+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
-+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
-+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
-+
-+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
-+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
-+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
-+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
-+
-+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
-+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
-+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
-+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
-+
-+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
-+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
-+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
-+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
-+
-+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
-+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
-+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
-+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
-+
-+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
-+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
-+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
-+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
-+
-+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
-+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
-+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
-+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/arm_power.h linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_power.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/arm_power.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_power.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,62 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _ARM_POWER_H
-+#define _ARM_POWER_H
-+
-+/* Use meaningful names on each side */
-+#ifdef __VIDEOCORE__
-+#define PREFIX(x) ARM_##x
-+#else
-+#define PREFIX(x) BCM_##x
-+#endif
-+
-+enum {
-+ PREFIX(POWER_SDCARD_BIT),
-+ PREFIX(POWER_UART_BIT),
-+ PREFIX(POWER_MINIUART_BIT),
-+ PREFIX(POWER_USB_BIT),
-+ PREFIX(POWER_I2C0_BIT),
-+ PREFIX(POWER_I2C1_BIT),
-+ PREFIX(POWER_I2C2_BIT),
-+ PREFIX(POWER_SPI_BIT),
-+ PREFIX(POWER_CCP2TX_BIT),
-+ PREFIX(POWER_DSI_BIT),
-+
-+ PREFIX(POWER_MAX)
-+};
-+
-+enum {
-+ PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
-+ PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
-+ PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
-+ PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
-+ PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
-+ PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
-+ PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
-+ PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
-+ PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
-+ PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
-+
-+ PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
-+ PREFIX(POWER_NONE) = 0
-+};
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/barriers.h linux-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/barriers.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,3 @@
-+#define mb() dsb()
-+#define rmb() dsb()
-+#define wmb() mb()
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/clkdev.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,7 @@
-+#ifndef __ASM_MACH_CLKDEV_H
-+#define __ASM_MACH_CLKDEV_H
-+
-+#define __clk_get(clk) ({ 1; })
-+#define __clk_put(clk) do { } while (0)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/debug-macro.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,22 @@
-+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
-+ *
-+ * Debugging macro include header
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 1994-1999 Russell King
-+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+*/
-+
-+#include <mach/platform.h>
-+
-+ .macro addruart, rp, rv, tmp
-+ ldr \rp, =UART0_BASE
-+ ldr \rv, =IO_ADDRESS(UART0_BASE)
-+ .endm
-+
-+#include <debug/pl01x.S>
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/dma.h linux-rpi/arch/arm/mach-bcm2709/include/mach/dma.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/dma.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/dma.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,94 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/include/mach/dma.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+
-+#ifndef _MACH_BCM2708_DMA_H
-+#define _MACH_BCM2708_DMA_H
-+
-+#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
-+
-+/* DMA CS Control and Status bits */
-+#define BCM2708_DMA_ACTIVE (1 << 0)
-+#define BCM2708_DMA_INT (1 << 2)
-+#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
-+#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
-+#define BCM2708_DMA_ERR (1 << 8)
-+#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
-+#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
-+
-+/* DMA control block "info" field bits */
-+#define BCM2708_DMA_INT_EN (1 << 0)
-+#define BCM2708_DMA_TDMODE (1 << 1)
-+#define BCM2708_DMA_WAIT_RESP (1 << 3)
-+#define BCM2708_DMA_D_INC (1 << 4)
-+#define BCM2708_DMA_D_WIDTH (1 << 5)
-+#define BCM2708_DMA_D_DREQ (1 << 6)
-+#define BCM2708_DMA_S_INC (1 << 8)
-+#define BCM2708_DMA_S_WIDTH (1 << 9)
-+#define BCM2708_DMA_S_DREQ (1 << 10)
-+
-+#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
-+#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
-+#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
-+
-+#define BCM2708_DMA_DREQ_EMMC 11
-+#define BCM2708_DMA_DREQ_SDHOST 13
-+
-+#define BCM2708_DMA_CS 0x00 /* Control and Status */
-+#define BCM2708_DMA_ADDR 0x04
-+/* the current control block appears in the following registers - read only */
-+#define BCM2708_DMA_INFO 0x08
-+#define BCM2708_DMA_SOURCE_AD 0x0c
-+#define BCM2708_DMA_DEST_AD 0x10
-+#define BCM2708_DMA_NEXTCB 0x1C
-+#define BCM2708_DMA_DEBUG 0x20
-+
-+#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
-+#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
-+
-+#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
-+
-+struct bcm2708_dma_cb {
-+ unsigned long info;
-+ unsigned long src;
-+ unsigned long dst;
-+ unsigned long length;
-+ unsigned long stride;
-+ unsigned long next;
-+ unsigned long pad[2];
-+};
-+struct scatterlist;
-+
-+extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
-+extern void bcm_dma_start(void __iomem *dma_chan_base,
-+ dma_addr_t control_block);
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base);
-+extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
-+
-+/* When listing features we can ask for when allocating DMA channels give
-+ those with higher priority smaller ordinal numbers */
-+#define BCM_DMA_FEATURE_FAST_ORD 0
-+#define BCM_DMA_FEATURE_BULK_ORD 1
-+#define BCM_DMA_FEATURE_NORMAL_ORD 2
-+#define BCM_DMA_FEATURE_LITE_ORD 3
-+#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
-+#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
-+#define BCM_DMA_FEATURE_NORMAL (1<<BCM_DMA_FEATURE_NORMAL_ORD)
-+#define BCM_DMA_FEATURE_LITE (1<<BCM_DMA_FEATURE_LITE_ORD)
-+#define BCM_DMA_FEATURE_COUNT 4
-+
-+/* return channel no or -ve error */
-+extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+ void __iomem **out_dma_base, int *out_dma_irq);
-+extern int bcm_dma_chan_free(int channel);
-+
-+
-+#endif /* _MACH_BCM2708_DMA_H */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/entry-macro.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,120 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/entry-macro.S
-+ *
-+ * Low-level IRQ helper macros for BCM2708 platforms
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#include <mach/hardware.h>
-+#include <mach/irqs.h>
-+
-+ .macro arch_ret_to_user, tmp1, tmp2
-+ .endm
-+
-+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-+
-+ /* get core number */
-+ mrc p15, 0, \base, c0, c0, 5
-+ ubfx \base, \base, #0, #2
-+
-+ /* get core's local interrupt controller */
-+ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
-+ add \irqstat, \irqstat, \base, lsl #2
-+ ldr \tmp, [\irqstat]
-+
-+ /* test for mailbox0 (IPI) interrupt */
-+ tst \tmp, #0x10
-+ beq 1030f
-+
-+ /* get core's mailbox interrupt control */
-+ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
-+ add \irqstat, \irqstat, \base, lsl #4
-+ ldr \tmp, [\irqstat]
-+ clz \tmp, \tmp
-+ rsb \irqnr, \tmp, #31
-+ mov \tmp, #1
-+ lsl \tmp, \irqnr
-+ str \tmp, [\irqstat] @ clear interrupt source
-+ dsb
-+ mov r1, sp
-+ adr lr, BSYM(1b)
-+ b do_IPI
-+
-+1030:
-+ /* check gpu interrupt */
-+ tst \tmp, #0x100
-+ beq 1040f
-+
-+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
-+ /* get masked status */
-+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
-+ mov \irqnr, #(ARM_IRQ0_BASE + 31)
-+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
-+ /* clear bits 8 and 9, and test */
-+ bics \irqstat, \irqstat, #0x300
-+ bne 1010f
-+
-+ tst \tmp, #0x100
-+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
-+ movne \irqnr, #(ARM_IRQ1_BASE + 31)
-+ @ Mask out the interrupts also present in PEND0 - see SW-5809
-+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
-+ bicne \irqstat, #((1<<18) | (1<<19))
-+ bne 1010f
-+
-+ tst \tmp, #0x200
-+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
-+ movne \irqnr, #(ARM_IRQ2_BASE + 31)
-+ @ Mask out the interrupts also present in PEND0 - see SW-5809
-+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
-+ bicne \irqstat, #((1<<30))
-+ beq 1020f
-+1010:
-+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
-+ sub \tmp, \irqstat, #1
-+ eor \irqstat, \irqstat, \tmp
-+ clz \tmp, \irqstat
-+ sub \irqnr, \tmp
-+ b 1050f
-+1040:
-+ cmp \tmp, #0
-+ beq 1020f
-+
-+ /* handle local (e.g. timer) interrupts */
-+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
-+ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
-+ sub \irqstat, \tmp, #1
-+ eor \irqstat, \irqstat, \tmp
-+ clz \tmp, \irqstat
-+ sub \irqnr, \tmp
-+1050:
-+ mov r1, sp
-+ @
-+ @ routine called with r0 = irq number, r1 = struct pt_regs *
-+ @
-+ adr lr, BSYM(1b)
-+ b asm_do_IRQ
-+
-+1020: @ EQ will be set if no irqs pending
-+ .endm
-+
-+/*
-+ * Interrupt handling. Preserves r7, r8, r9
-+ */
-+ .macro arch_irq_handler_default
-+1: get_irqnr_and_base r0, r2, r6, lr
-+ .endm
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2709/include/mach/frc.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/frc.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/frc.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,38 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/timex.h
-+ *
-+ * BCM2708 free running counter (timer)
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _MACH_FRC_H
-+#define _MACH_FRC_H
-+
-+#define FRC_TICK_RATE (1000000)
-+
-+/*! Free running counter incrementing at the CLOCK_TICK_RATE
-+ (slightly faster than frc_clock_ticks63()
-+ */
-+extern unsigned long frc_clock_ticks32(void);
-+
-+/*! Free running counter incrementing at the CLOCK_TICK_RATE
-+ * Note - top bit should be ignored (see cnt32_to_63)
-+ */
-+extern unsigned long long frc_clock_ticks63(void);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/gpio.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,17 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/gpio.h
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef __ASM_ARCH_GPIO_H
-+#define __ASM_ARCH_GPIO_H
-+
-+#define BCM2708_NR_GPIOS 54 // number of gpio lines
-+
-+#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
-+#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/hardware.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,28 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/hardware.h
-+ *
-+ * This file contains the hardware definitions of the BCM2708 devices.
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_HARDWARE_H
-+#define __ASM_ARCH_HARDWARE_H
-+
-+#include <asm/sizes.h>
-+#include <mach/platform.h>
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/io.h linux-rpi/arch/arm/mach-bcm2709/include/mach/io.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/io.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/io.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,27 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/io.h
-+ *
-+ * Copyright (C) 2003 ARM Limited
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARM_ARCH_IO_H
-+#define __ASM_ARM_ARCH_IO_H
-+
-+#define IO_SPACE_LIMIT 0xffffffff
-+
-+#define __io(a) __typesafe_io(a)
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/irqs.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,225 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/irqs.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _BCM2708_IRQS_H_
-+#define _BCM2708_IRQS_H_
-+
-+#include <mach/platform.h>
-+
-+/*
-+ * IRQ interrupts definitions are the same as the INT definitions
-+ * held within platform.h
-+ */
-+#define IRQ_ARMCTRL_START 0
-+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
-+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
-+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
-+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
-+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
-+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
-+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
-+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
-+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
-+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
-+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
-+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
-+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
-+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
-+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
-+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
-+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
-+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
-+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
-+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
-+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
-+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
-+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
-+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
-+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
-+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
-+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
-+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
-+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
-+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
-+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
-+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
-+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
-+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
-+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
-+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
-+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
-+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
-+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
-+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
-+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
-+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
-+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
-+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
-+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
-+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
-+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
-+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
-+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
-+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
-+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
-+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
-+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
-+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
-+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
-+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
-+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
-+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
-+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
-+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
-+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
-+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
-+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
-+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
-+
-+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
-+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
-+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
-+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
-+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
-+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
-+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
-+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
-+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
-+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
-+
-+#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
-+#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
-+#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
-+#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
-+#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
-+#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
-+#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
-+#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
-+#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
-+#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
-+#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
-+#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
-+
-+#define FIQ_START HARD_IRQS
-+
-+/*
-+ * FIQ interrupts definitions are the same as the INT definitions.
-+ */
-+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
-+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
-+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
-+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
-+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
-+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
-+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
-+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
-+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
-+#define FIQ_USB (FIQ_START+INTERRUPT_USB)
-+#define FIQ_3D (FIQ_START+INTERRUPT_3D)
-+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
-+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
-+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
-+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
-+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
-+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
-+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
-+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
-+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
-+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
-+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
-+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
-+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
-+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
-+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
-+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
-+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
-+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
-+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
-+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
-+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
-+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
-+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
-+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
-+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
-+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
-+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
-+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
-+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
-+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
-+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
-+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
-+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
-+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
-+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
-+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
-+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
-+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
-+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
-+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
-+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
-+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
-+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
-+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
-+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
-+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
-+#define FIQ_UART (FIQ_START+INTERRUPT_UART)
-+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
-+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
-+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
-+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
-+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
-+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
-+
-+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
-+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
-+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
-+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
-+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
-+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
-+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
-+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
-+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
-+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
-+
-+#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
-+#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
-+#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
-+#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
-+#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
-+#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
-+#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
-+#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
-+#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
-+#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
-+#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
-+#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
-+
-+#define HARD_IRQS (128)
-+#define FIQ_IRQS (128)
-+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
-+#define GPIO_IRQS (32*5)
-+#define SPARE_ALLOC_IRQS 64
-+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
-+#define FREE_IRQS 128
-+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
-+
-+#endif /* _BCM2708_IRQS_H_ */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2709/include/mach/memory.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/memory.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/memory.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,57 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/memory.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_MEMORY_H
-+#define __ASM_ARCH_MEMORY_H
-+
-+/* Memory overview:
-+
-+ [ARMcore] <--virtual addr-->
-+ [ARMmmu] <--physical addr-->
-+ [GERTmap] <--bus add-->
-+ [VCperiph]
-+
-+*/
-+
-+/*
-+ * Physical DRAM offset.
-+ */
-+#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
-+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
-+
-+#ifdef CONFIG_BCM2708_NOL2CACHE
-+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
-+#else
-+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
-+#endif
-+
-+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
-+ * will provide the offset into this area as well as setting the bits that
-+ * stop the L1 and L2 cache from being used
-+ *
-+ * WARNING: this only works because the ARM is given memory at a fixed location
-+ * (ARMMEM_OFFSET)
-+ */
-+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
-+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
-+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
-+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
-+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2709/include/mach/platform.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/platform.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/platform.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,225 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/platform.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef _BCM2708_PLATFORM_H
-+#define _BCM2708_PLATFORM_H
-+
-+
-+/* macros to get at IO space when running virtually */
-+#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-+
-+#define __io_address(n) IOMEM(IO_ADDRESS(n))
-+
-+
-+/*
-+ * SDRAM
-+ */
-+#define BCM2708_SDRAM_BASE 0x00000000
-+
-+/*
-+ * Logic expansion modules
-+ *
-+ */
-+
-+
-+/* ------------------------------------------------------------------------
-+ * BCM2708 ARMCTRL Registers
-+ * ------------------------------------------------------------------------
-+ */
-+
-+#define HW_REGISTER_RW(addr) (addr)
-+#define HW_REGISTER_RO(addr) (addr)
-+
-+#include "arm_control.h"
-+#undef ARM_BASE
-+
-+/*
-+ * Definitions and addresses for the ARM CONTROL logic
-+ * This file is manually generated.
-+ */
-+
-+#define BCM2708_PERI_BASE 0x3F000000
-+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
-+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
-+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
-+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
-+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
-+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
-+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
-+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
-+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
-+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
-+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
-+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
-+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
-+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
-+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
-+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
-+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
-+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
-+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
-+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
-+
-+#define ARMCTRL_BASE (ARM_BASE + 0x000)
-+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
-+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
-+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
-+
-+
-+/*
-+ * Interrupt assignments
-+ */
-+
-+#define ARM_IRQ1_BASE 0
-+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
-+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
-+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
-+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
-+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
-+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
-+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
-+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
-+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
-+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
-+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
-+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
-+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
-+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
-+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
-+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
-+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
-+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
-+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
-+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
-+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
-+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
-+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
-+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
-+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
-+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
-+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
-+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
-+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
-+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
-+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
-+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
-+
-+#define ARM_IRQ2_BASE 32
-+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
-+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
-+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
-+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
-+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
-+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
-+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
-+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
-+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
-+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
-+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
-+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
-+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
-+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
-+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
-+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
-+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
-+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
-+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
-+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
-+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
-+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
-+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
-+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
-+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
-+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
-+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
-+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
-+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
-+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
-+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
-+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
-+
-+#define ARM_IRQ0_BASE 64
-+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
-+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
-+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
-+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
-+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
-+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
-+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
-+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
-+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
-+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
-+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
-+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
-+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
-+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
-+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
-+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
-+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
-+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
-+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
-+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
-+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
-+
-+#define ARM_IRQ_LOCAL_BASE 96
-+#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0)
-+#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1)
-+#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2)
-+#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3)
-+#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4)
-+#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5)
-+#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6)
-+#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7)
-+#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8)
-+#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9)
-+#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10)
-+#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11)
-+
-+/*
-+ * Watchdog
-+ */
-+#define PM_RSTC (PM_BASE+0x1c)
-+#define PM_RSTS (PM_BASE+0x20)
-+#define PM_WDOG (PM_BASE+0x24)
-+
-+#define PM_WDOG_RESET 0000000000
-+#define PM_PASSWORD 0x5a000000
-+#define PM_WDOG_TIME_SET 0x000fffff
-+#define PM_RSTC_WRCFG_CLR 0xffffffcf
-+#define PM_RSTC_WRCFG_SET 0x00000030
-+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
-+#define PM_RSTC_RESET 0x00000102
-+
-+#define PM_RSTS_HADPOR_SET 0x00001000
-+#define PM_RSTS_HADSRH_SET 0x00000400
-+#define PM_RSTS_HADSRF_SET 0x00000200
-+#define PM_RSTS_HADSRQ_SET 0x00000100
-+#define PM_RSTS_HADWRH_SET 0x00000040
-+#define PM_RSTS_HADWRF_SET 0x00000020
-+#define PM_RSTS_HADWRQ_SET 0x00000010
-+#define PM_RSTS_HADDRH_SET 0x00000004
-+#define PM_RSTS_HADDRF_SET 0x00000002
-+#define PM_RSTS_HADDRQ_SET 0x00000001
-+
-+#define UART0_CLOCK 3000000
-+
-+#endif
-+
-+/* END */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/power.h linux-rpi/arch/arm/mach-bcm2709/include/mach/power.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/power.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/power.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,26 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/power.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for controlling the power to
-+ * VideoCore subsystems.
-+ */
-+
-+#ifndef _MACH_BCM2708_POWER_H
-+#define _MACH_BCM2708_POWER_H
-+
-+#include <linux/types.h>
-+#include <mach/arm_power.h>
-+
-+typedef unsigned int BCM_POWER_HANDLE_T;
-+
-+extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
-+extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
-+extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/system.h linux-rpi/arch/arm/mach-bcm2709/include/mach/system.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/system.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/system.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,38 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/system.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef __ASM_ARCH_SYSTEM_H
-+#define __ASM_ARCH_SYSTEM_H
-+
-+#include <linux/io.h>
-+#include <mach/hardware.h>
-+#include <mach/platform.h>
-+
-+static inline void arch_idle(void)
-+{
-+ /*
-+ * This should do all the clock switching
-+ * and wait for interrupt tricks
-+ */
-+ cpu_do_idle();
-+}
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2709/include/mach/timex.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/timex.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/timex.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,23 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/timex.h
-+ *
-+ * BCM2708 sysem clock frequency
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#define CLOCK_TICK_RATE (1000000)
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/uncompress.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,84 @@
-+/*
-+ * arch/arm/mach-bcn2708/include/mach/uncompress.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ * Copyright (C) 2003 ARM Limited
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/amba/serial.h>
-+#include <mach/hardware.h>
-+
-+#define UART_BAUD 115200
-+
-+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
-+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
-+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
-+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
-+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
-+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
-+
-+/*
-+ * This does not append a newline
-+ */
-+static inline void putc(int c)
-+{
-+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
-+ barrier();
-+
-+ __raw_writel(c, BCM2708_UART_DR);
-+}
-+
-+static inline void flush(void)
-+{
-+ int fr;
-+
-+ do {
-+ fr = __raw_readl(BCM2708_UART_FR);
-+ barrier();
-+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
-+}
-+
-+static inline void arch_decomp_setup(void)
-+{
-+ int temp, div, rem, frac;
-+
-+ temp = 16 * UART_BAUD;
-+ div = UART0_CLOCK / temp;
-+ rem = UART0_CLOCK % temp;
-+ temp = (8 * rem) / UART_BAUD;
-+ frac = (temp >> 1) + (temp & 1);
-+
-+ /* Make sure the UART is disabled before we start */
-+ __raw_writel(0, BCM2708_UART_CR);
-+
-+ /* Set the baud rate */
-+ __raw_writel(div, BCM2708_UART_IBRD);
-+ __raw_writel(frac, BCM2708_UART_FBRD);
-+
-+ /* Set the UART to 8n1, FIFO enabled */
-+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
-+
-+ /* Enable the UART */
-+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
-+ BCM2708_UART_CR);
-+}
-+
-+/*
-+ * nothing to do
-+ */
-+#define arch_decomp_wdog()
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vcio.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vcio.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vcio.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vcio.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,165 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/vcio.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#ifndef _MACH_BCM2708_VCIO_H
-+#define _MACH_BCM2708_VCIO_H
-+
-+/* Routines to handle I/O via the VideoCore "ARM control" registers
-+ * (semaphores, doorbells, mailboxes)
-+ */
-+
-+#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
-+
-+/* Constants shared with the ARM identifying separate mailbox channels */
-+#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
-+#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
-+#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
-+#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
-+#define MBOX_CHAN_COUNT 9
-+
-+enum {
-+ VCMSG_PROCESS_REQUEST = 0x00000000
-+};
-+enum {
-+ VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
-+ VCMSG_REQUEST_FAILED = 0x80000001
-+};
-+/* Mailbox property tags */
-+enum {
-+ VCMSG_PROPERTY_END = 0x00000000,
-+ VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
-+ VCMSG_GET_BOARD_MODEL = 0x00010001,
-+ VCMSG_GET_BOARD_REVISION = 0x00010002,
-+ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
-+ VCMSG_GET_BOARD_SERIAL = 0x00010004,
-+ VCMSG_GET_ARM_MEMORY = 0x00010005,
-+ VCMSG_GET_VC_MEMORY = 0x00010006,
-+ VCMSG_GET_CLOCKS = 0x00010007,
-+ VCMSG_GET_COMMAND_LINE = 0x00050001,
-+ VCMSG_GET_DMA_CHANNELS = 0x00060001,
-+ VCMSG_GET_POWER_STATE = 0x00020001,
-+ VCMSG_GET_TIMING = 0x00020002,
-+ VCMSG_SET_POWER_STATE = 0x00028001,
-+ VCMSG_GET_CLOCK_STATE = 0x00030001,
-+ VCMSG_SET_CLOCK_STATE = 0x00038001,
-+ VCMSG_GET_CLOCK_RATE = 0x00030002,
-+ VCMSG_SET_CLOCK_RATE = 0x00038002,
-+ VCMSG_GET_VOLTAGE = 0x00030003,
-+ VCMSG_SET_VOLTAGE = 0x00038003,
-+ VCMSG_GET_MAX_CLOCK = 0x00030004,
-+ VCMSG_GET_MAX_VOLTAGE = 0x00030005,
-+ VCMSG_GET_TEMPERATURE = 0x00030006,
-+ VCMSG_GET_MIN_CLOCK = 0x00030007,
-+ VCMSG_GET_MIN_VOLTAGE = 0x00030008,
-+ VCMSG_GET_TURBO = 0x00030009,
-+ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
-+ VCMSG_GET_STC = 0x0003000b,
-+ VCMSG_SET_TURBO = 0x00038009,
-+ VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
-+ VCMSG_SET_LOCK_MEM = 0x0003000d,
-+ VCMSG_SET_UNLOCK_MEM = 0x0003000e,
-+ VCMSG_SET_RELEASE_MEM = 0x0003000f,
-+ VCMSG_SET_EXECUTE_CODE = 0x00030010,
-+ VCMSG_SET_EXECUTE_QPU = 0x00030011,
-+ VCMSG_SET_ENABLE_QPU = 0x00030012,
-+ VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
-+ VCMSG_GET_EDID_BLOCK = 0x00030020,
-+ VCMSG_GET_CUSTOMER_OTP = 0x00030021,
-+ VCMSG_SET_CUSTOMER_OTP = 0x00038021,
-+ VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
-+ VCMSG_SET_RELEASE_BUFFER = 0x00048001,
-+ VCMSG_SET_BLANK_SCREEN = 0x00040002,
-+ VCMSG_TST_BLANK_SCREEN = 0x00044002,
-+ VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
-+ VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
-+ VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
-+ VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
-+ VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
-+ VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
-+ VCMSG_GET_DEPTH = 0x00040005,
-+ VCMSG_TST_DEPTH = 0x00044005,
-+ VCMSG_SET_DEPTH = 0x00048005,
-+ VCMSG_GET_PIXEL_ORDER = 0x00040006,
-+ VCMSG_TST_PIXEL_ORDER = 0x00044006,
-+ VCMSG_SET_PIXEL_ORDER = 0x00048006,
-+ VCMSG_GET_ALPHA_MODE = 0x00040007,
-+ VCMSG_TST_ALPHA_MODE = 0x00044007,
-+ VCMSG_SET_ALPHA_MODE = 0x00048007,
-+ VCMSG_GET_PITCH = 0x00040008,
-+ VCMSG_TST_PITCH = 0x00044008,
-+ VCMSG_SET_PITCH = 0x00048008,
-+ VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
-+ VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
-+ VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
-+ VCMSG_GET_OVERSCAN = 0x0004000a,
-+ VCMSG_TST_OVERSCAN = 0x0004400a,
-+ VCMSG_SET_OVERSCAN = 0x0004800a,
-+ VCMSG_GET_PALETTE = 0x0004000b,
-+ VCMSG_TST_PALETTE = 0x0004400b,
-+ VCMSG_SET_PALETTE = 0x0004800b,
-+ VCMSG_GET_LAYER = 0x0004000c,
-+ VCMSG_TST_LAYER = 0x0004400c,
-+ VCMSG_SET_LAYER = 0x0004800c,
-+ VCMSG_GET_TRANSFORM = 0x0004000d,
-+ VCMSG_TST_TRANSFORM = 0x0004400d,
-+ VCMSG_SET_TRANSFORM = 0x0004800d,
-+ VCMSG_TST_VSYNC = 0x0004400e,
-+ VCMSG_SET_VSYNC = 0x0004800e,
-+ VCMSG_SET_CURSOR_INFO = 0x00008010,
-+ VCMSG_SET_CURSOR_STATE = 0x00008011,
-+};
-+
-+extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
-+extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
-+extern int /*rc*/ bcm_mailbox_property(void *data, int size);
-+
-+#include <linux/ioctl.h>
-+
-+/*
-+ * The major device number. We can't rely on dynamic
-+ * registration any more, because ioctls need to know
-+ * it.
-+ */
-+#define MAJOR_NUM 100
-+
-+/*
-+ * Set the message of the device driver
-+ */
-+#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
-+/*
-+ * _IOWR means that we're creating an ioctl command
-+ * number for passing information from a user process
-+ * to the kernel module and from the kernel module to user process
-+ *
-+ * The first arguments, MAJOR_NUM, is the major device
-+ * number we're using.
-+ *
-+ * The second argument is the number of the command
-+ * (there could be several with different meanings).
-+ *
-+ * The third argument is the type we want to get from
-+ * the process to the kernel.
-+ */
-+
-+/*
-+ * The name of the device file
-+ */
-+#define DEVICE_FILE_NAME "vcio"
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vc_mem.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_mem.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vc_mem.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_mem.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,35 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#if !defined( VC_MEM_H )
-+#define VC_MEM_H
-+
-+#include <linux/ioctl.h>
-+
-+#define VC_MEM_IOC_MAGIC 'v'
-+
-+#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
-+#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
-+#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
-+#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
-+
-+#if defined( __KERNEL__ )
-+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
-+
-+extern unsigned long mm_vc_mem_phys_addr;
-+extern unsigned int mm_vc_mem_size;
-+extern int vc_mem_get_current_size( void );
-+#endif
-+
-+#endif /* VC_MEM_H */
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vc_support.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vc_support.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,69 @@
-+#ifndef _VC_SUPPORT_H_
-+#define _VC_SUPPORT_H_
-+
-+/*
-+ * vc_support.h
-+ *
-+ * Created on: 25 Nov 2012
-+ * Author: Simon
-+ */
-+
-+enum {
-+/*
-+ If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
-+ 0 at any time when it is not locked or retained.
-+ */
-+ MEM_FLAG_DISCARDABLE = 1 << 0,
-+
-+ /*
-+ If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
-+ accessed in an allocating fashion through the cache.
-+ */
-+ MEM_FLAG_NORMAL = 0 << 2,
-+ MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
-+
-+ /*
-+ If a MEM_HANDLE_T is direct, its block of memory will be accessed
-+ directly, bypassing the cache.
-+ */
-+ MEM_FLAG_DIRECT = 1 << 2,
-+
-+ /*
-+ If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
-+ non-allocating fashion through the cache.
-+ */
-+ MEM_FLAG_COHERENT = 2 << 2,
-+
-+ /*
-+ If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
-+ the VPU in a fashion which is allocating in L2, but only coherent in L1.
-+ */
-+ MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
-+
-+ /*
-+ If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
-+ MEM_HANDLE_INVALID on allocation and resize up.
-+ */
-+ MEM_FLAG_ZERO = 1 << 4,
-+
-+ /*
-+ If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
-+ (either zero, or all 1's) on allocation.
-+ */
-+ MEM_FLAG_NO_INIT = 1 << 5,
-+
-+ /*
-+ Hints.
-+ */
-+ MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
-+};
-+
-+unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
-+unsigned int ReleaseVcMemory(unsigned int handle);
-+unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
-+unsigned int UnlockVcMemory(unsigned int handle);
-+
-+unsigned int ExecuteVcCode(unsigned int code,
-+ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
-+
-+#endif
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h
---- linux-3.18.14/arch/arm/mach-bcm2709/include/mach/vmalloc.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h 2015-05-31 14:46:08.213661004 -0500
-@@ -0,0 +1,20 @@
-+/*
-+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+#define VMALLOC_END (0xff000000)
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/Kconfig linux-rpi/arch/arm/mach-bcm2709/Kconfig
---- linux-3.18.14/arch/arm/mach-bcm2709/Kconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/Kconfig 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,49 @@
-+menu "Broadcom BCM2709 Implementations"
-+ depends on ARCH_BCM2709
-+
-+config MACH_BCM2709
-+ bool "Broadcom BCM2709 Development Platform"
-+ help
-+ Include support for the Broadcom(R) BCM2709 platform.
-+
-+config BCM2709_DT
-+ bool "BCM2709 Device Tree support"
-+ depends on MACH_BCM2709
-+ default n
-+ select USE_OF
-+ select ARCH_REQUIRE_GPIOLIB
-+ select PINCTRL
-+ select PINCTRL_BCM2835
-+ help
-+ Enable Device Tree support for BCM2709
-+
-+config BCM2708_GPIO
-+ bool "BCM2709 gpio support"
-+ depends on MACH_BCM2709
-+ select ARCH_REQUIRE_GPIOLIB
-+ default y
-+ help
-+ Include support for the Broadcom(R) BCM2709 gpio.
-+
-+config BCM2708_VCMEM
-+ bool "Videocore Memory"
-+ depends on MACH_BCM2709
-+ default y
-+ help
-+ Helper for videocore memory access and total size allocation.
-+
-+config BCM2708_NOL2CACHE
-+ bool "Videocore L2 cache disable"
-+ depends on MACH_BCM2709
-+ default y
-+ help
-+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
-+
-+config BCM2708_SPIDEV
-+ bool "Bind spidev to SPI0 master"
-+ depends on MACH_BCM2709
-+ depends on SPI
-+ default y
-+ help
-+ Binds spidev driver to the SPI0 master
-+endmenu
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/Makefile linux-rpi/arch/arm/mach-bcm2709/Makefile
---- linux-3.18.14/arch/arm/mach-bcm2709/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/Makefile 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,7 @@
-+#
-+# Makefile for the linux kernel.
-+#
-+
-+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o vcio.o power.o dma.o
-+obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
-+obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/Makefile.boot linux-rpi/arch/arm/mach-bcm2709/Makefile.boot
---- linux-3.18.14/arch/arm/mach-bcm2709/Makefile.boot 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/Makefile.boot 2015-05-31 14:46:08.209661004 -0500
-@@ -0,0 +1,3 @@
-+ zreladdr-y := 0x00008000
-+params_phys-y := 0x00000100
-+initrd_phys-y := 0x00800000
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/power.c linux-rpi/arch/arm/mach-bcm2709/power.c
---- linux-3.18.14/arch/arm/mach-bcm2709/power.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/power.c 2015-05-31 14:46:08.217661004 -0500
-@@ -0,0 +1,195 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/power.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for controlling the power to
-+ * VideoCore subsystems.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/semaphore.h>
-+#include <linux/bug.h>
-+#include <mach/power.h>
-+#include <mach/vcio.h>
-+#include <mach/arm_power.h>
-+
-+#define DRIVER_NAME "bcm2708_power"
-+
-+#define BCM_POWER_MAXCLIENTS 4
-+#define BCM_POWER_NOCLIENT (1<<31)
-+
-+/* Some drivers expect there devices to be permanently powered */
-+#ifdef CONFIG_USB
-+#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
-+#endif
-+
-+#if 1
-+#define DPRINTK printk
-+#else
-+#define DPRINTK if (0) printk
-+#endif
-+
-+struct state_struct {
-+ uint32_t global_request;
-+ uint32_t client_request[BCM_POWER_MAXCLIENTS];
-+ struct semaphore client_mutex;
-+ struct semaphore mutex;
-+} g_state;
-+
-+int bcm_power_open(BCM_POWER_HANDLE_T *handle)
-+{
-+ BCM_POWER_HANDLE_T i;
-+ int ret = -EBUSY;
-+
-+ down(&g_state.client_mutex);
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
-+ if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
-+ g_state.client_request[i] = BCM_POWER_NONE;
-+ *handle = i;
-+ ret = 0;
-+ break;
-+ }
-+ }
-+
-+ up(&g_state.client_mutex);
-+
-+ DPRINTK("bcm_power_open() -> %d\n", *handle);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_open);
-+
-+int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
-+{
-+ int rc = 0;
-+
-+ DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
-+
-+ if ((handle < BCM_POWER_MAXCLIENTS) &&
-+ (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
-+ if (down_interruptible(&g_state.mutex) != 0) {
-+ DPRINTK("bcm_power_request -> interrupted\n");
-+ return -EINTR;
-+ }
-+
-+ if (request != g_state.client_request[handle]) {
-+ uint32_t others_request = 0;
-+ uint32_t global_request;
-+ BCM_POWER_HANDLE_T i;
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
-+ if (i != handle)
-+ others_request |=
-+ g_state.client_request[i];
-+ }
-+ others_request &= ~BCM_POWER_NOCLIENT;
-+
-+ global_request = request | others_request;
-+ if (global_request != g_state.global_request) {
-+ uint32_t actual;
-+
-+ /* Send a request to VideoCore */
-+ bcm_mailbox_write(MBOX_CHAN_POWER,
-+ global_request << 4);
-+
-+ /* Wait for a response during power-up */
-+ if (global_request & ~g_state.global_request) {
-+ rc = bcm_mailbox_read(MBOX_CHAN_POWER,
-+ &actual);
-+ DPRINTK
-+ ("bcm_mailbox_read -> %08x, %d\n",
-+ actual, rc);
-+ actual >>= 4;
-+ } else {
-+ rc = 0;
-+ actual = global_request;
-+ }
-+
-+ if (rc == 0) {
-+ if (actual != global_request) {
-+ printk(KERN_ERR
-+ "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
-+ __func__,
-+ g_state.global_request,
-+ global_request, actual, request, others_request);
-+ /* A failure */
-+ BUG_ON((others_request & actual)
-+ != others_request);
-+ request &= actual;
-+ rc = -EIO;
-+ }
-+
-+ g_state.global_request = actual;
-+ g_state.client_request[handle] =
-+ request;
-+ }
-+ }
-+ }
-+ up(&g_state.mutex);
-+ } else {
-+ rc = -EINVAL;
-+ }
-+ DPRINTK("bcm_power_request -> %d\n", rc);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_request);
-+
-+int bcm_power_close(BCM_POWER_HANDLE_T handle)
-+{
-+ int rc;
-+
-+ DPRINTK("bcm_power_close(%d)\n", handle);
-+
-+ rc = bcm_power_request(handle, BCM_POWER_NONE);
-+ if (rc == 0)
-+ g_state.client_request[handle] = BCM_POWER_NOCLIENT;
-+
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_power_close);
-+
-+static int __init bcm_power_init(void)
-+{
-+#if defined(BCM_POWER_ALWAYS_ON)
-+ BCM_POWER_HANDLE_T always_on_handle;
-+#endif
-+ int rc = 0;
-+ int i;
-+
-+ printk(KERN_INFO "bcm_power: Broadcom power driver\n");
-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0);
-+
-+ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
-+ g_state.client_request[i] = BCM_POWER_NOCLIENT;
-+
-+ sema_init(&g_state.client_mutex, 1);
-+ sema_init(&g_state.mutex, 1);
-+
-+ g_state.global_request = 0;
-+#if defined(BCM_POWER_ALWAYS_ON)
-+ if (BCM_POWER_ALWAYS_ON) {
-+ bcm_power_open(&always_on_handle);
-+ bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
-+ }
-+#endif
-+
-+ return rc;
-+}
-+
-+static void __exit bcm_power_exit(void)
-+{
-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0);
-+}
-+
-+arch_initcall(bcm_power_init); /* Initialize early */
-+module_exit(bcm_power_exit);
-+
-+MODULE_AUTHOR("Phil Elwell");
-+MODULE_DESCRIPTION("Interface to BCM2708 power management");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/vcio.c linux-rpi/arch/arm/mach-bcm2709/vcio.c
---- linux-3.18.14/arch/arm/mach-bcm2709/vcio.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/vcio.c 2015-05-31 14:46:08.217661004 -0500
-@@ -0,0 +1,484 @@
-+/*
-+ * linux/arch/arm/mach-bcm2708/vcio.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This device provides a shared mechanism for writing to the mailboxes,
-+ * semaphores, doorbells etc. that are shared between the ARM and the
-+ * VideoCore processor
-+ */
-+
-+#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include <linux/module.h>
-+#include <linux/console.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial.h>
-+#include <linux/errno.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+#include <linux/sysrq.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+
-+#include <linux/io.h>
-+
-+#include <mach/vcio.h>
-+#include <mach/platform.h>
-+
-+#include <asm/uaccess.h>
-+
-+
-+#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
-+
-+/* ----------------------------------------------------------------------
-+ * Mailbox
-+ * -------------------------------------------------------------------- */
-+
-+/* offsets from a mail box base address */
-+#define MAIL_WRT 0x00 /* write - and next 4 words */
-+#define MAIL_RD 0x00 /* read - and next 4 words */
-+#define MAIL_POL 0x10 /* read without popping the fifo */
-+#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
-+#define MAIL_STA 0x18 /* status */
-+#define MAIL_CNF 0x1C /* configuration */
-+
-+#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
-+#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
-+#define MBOX_CHAN(msg) ((msg) & 0xf)
-+#define MBOX_DATA28(msg) ((msg) & ~0xf)
-+#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
-+
-+#define MBOX_MAGIC 0xd0d0c0de
-+static struct class *vcio_class = NULL;
-+struct vc_mailbox {
-+ struct device *dev; /* parent device */
-+ void __iomem *status;
-+ void __iomem *config;
-+ void __iomem *read;
-+ void __iomem *write;
-+ uint32_t msg[MBOX_CHAN_COUNT];
-+ struct semaphore sema[MBOX_CHAN_COUNT];
-+ uint32_t magic;
-+};
-+
-+static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
-+ uint32_t addr_mbox)
-+{
-+ int i;
-+
-+ mbox_out->dev = dev;
-+ mbox_out->status = __io_address(addr_mbox + MAIL_STA);
-+ mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
-+ mbox_out->read = __io_address(addr_mbox + MAIL_RD);
-+ /* Write to the other mailbox */
-+ mbox_out->write =
-+ __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
-+ MAIL_WRT);
-+
-+ for (i = 0; i < MBOX_CHAN_COUNT; i++) {
-+ mbox_out->msg[i] = 0;
-+ sema_init(&mbox_out->sema[i], 0);
-+ }
-+
-+ /* Enable the interrupt on data reception */
-+ writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
-+
-+ mbox_out->magic = MBOX_MAGIC;
-+}
-+
-+static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
-+{
-+ int rc;
-+
-+ if (mbox->magic != MBOX_MAGIC)
-+ rc = -EINVAL;
-+ else {
-+ /* wait for the mailbox FIFO to have some space in it */
-+ while (0 != (readl(mbox->status) & ARM_MS_FULL))
-+ cpu_relax();
-+
-+ writel(MBOX_MSG(chan, data28), mbox->write);
-+ rc = 0;
-+ }
-+ return rc;
-+}
-+
-+static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
-+{
-+ int rc;
-+
-+ if (mbox->magic != MBOX_MAGIC)
-+ rc = -EINVAL;
-+ else {
-+ down(&mbox->sema[chan]);
-+ *data28 = MBOX_DATA28(mbox->msg[chan]);
-+ mbox->msg[chan] = 0;
-+ rc = 0;
-+ }
-+ return rc;
-+}
-+
-+static irqreturn_t mbox_irq(int irq, void *dev_id)
-+{
-+ /* wait for the mailbox FIFO to have some data in it */
-+ struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
-+ int status = readl(mbox->status);
-+ int ret = IRQ_NONE;
-+
-+ while (!(status & ARM_MS_EMPTY)) {
-+ uint32_t msg = readl(mbox->read);
-+ int chan = MBOX_CHAN(msg);
-+ if (chan < MBOX_CHAN_COUNT) {
-+ if (mbox->msg[chan]) {
-+ /* Overflow */
-+ printk(KERN_ERR DRIVER_NAME
-+ ": mbox chan %d overflow - drop %08x\n",
-+ chan, msg);
-+ } else {
-+ mbox->msg[chan] = (msg | 0xf);
-+ up(&mbox->sema[chan]);
-+ }
-+ } else {
-+ printk(KERN_ERR DRIVER_NAME
-+ ": invalid channel selector (msg %08x)\n", msg);
-+ }
-+ ret = IRQ_HANDLED;
-+ status = readl(mbox->status);
-+ }
-+ return ret;
-+}
-+
-+static struct irqaction mbox_irqaction = {
-+ .name = "ARM Mailbox IRQ",
-+ .flags = IRQF_DISABLED | IRQF_IRQPOLL,
-+ .handler = mbox_irq,
-+};
-+
-+/* ----------------------------------------------------------------------
-+ * Mailbox Methods
-+ * -------------------------------------------------------------------- */
-+
-+static struct device *mbox_dev; /* we assume there's only one! */
-+
-+static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
-+{
-+ int rc;
-+
-+ struct vc_mailbox *mailbox = dev_get_drvdata(dev);
-+ device_lock(dev);
-+ rc = mbox_write(mailbox, chan, data28);
-+ device_unlock(dev);
-+
-+ return rc;
-+}
-+
-+static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
-+{
-+ int rc;
-+
-+ struct vc_mailbox *mailbox = dev_get_drvdata(dev);
-+ device_lock(dev);
-+ rc = mbox_read(mailbox, chan, data28);
-+ device_unlock(dev);
-+
-+ return rc;
-+}
-+
-+extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
-+{
-+ if (mbox_dev)
-+ return dev_mbox_write(mbox_dev, chan, data28);
-+ else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_write);
-+
-+extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
-+{
-+ if (mbox_dev)
-+ return dev_mbox_read(mbox_dev, chan, data28);
-+ else
-+ return -ENODEV;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_read);
-+
-+static void dev_mbox_register(const char *dev_name, struct device *dev)
-+{
-+ mbox_dev = dev;
-+}
-+
-+static int mbox_copy_from_user(void *dst, const void *src, int size)
-+{
-+ if ( (uint32_t)src < TASK_SIZE)
-+ {
-+ return copy_from_user(dst, src, size);
-+ }
-+ else
-+ {
-+ memcpy( dst, src, size );
-+ return 0;
-+ }
-+}
-+
-+static int mbox_copy_to_user(void *dst, const void *src, int size)
-+{
-+ if ( (uint32_t)dst < TASK_SIZE)
-+ {
-+ return copy_to_user(dst, src, size);
-+ }
-+ else
-+ {
-+ memcpy( dst, src, size );
-+ return 0;
-+ }
-+}
-+
-+static DEFINE_MUTEX(mailbox_lock);
-+extern int bcm_mailbox_property(void *data, int size)
-+{
-+ uint32_t success;
-+ dma_addr_t mem_bus; /* the memory address accessed from videocore */
-+ void *mem_kern; /* the memory address accessed from driver */
-+ int s = 0;
-+
-+ mutex_lock(&mailbox_lock);
-+ /* allocate some memory for the messages communicating with GPU */
-+ mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
-+ if (mem_kern) {
-+ /* create the message */
-+ mbox_copy_from_user(mem_kern, data, size);
-+
-+ /* send the message */
-+ wmb();
-+ s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
-+ if (s == 0) {
-+ s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
-+ }
-+ if (s == 0) {
-+ /* copy the response */
-+ rmb();
-+ mbox_copy_to_user(data, mem_kern, size);
-+ }
-+ dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
-+ } else {
-+ s = -ENOMEM;
-+ }
-+ if (s != 0)
-+ printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
-+
-+ mutex_unlock(&mailbox_lock);
-+ return s;
-+}
-+EXPORT_SYMBOL_GPL(bcm_mailbox_property);
-+
-+/* ----------------------------------------------------------------------
-+ * Platform Device for Mailbox
-+ * -------------------------------------------------------------------- */
-+
-+/*
-+ * Is the device open right now? Used to prevent
-+ * concurent access into the same device
-+ */
-+static int Device_Open = 0;
-+
-+/*
-+ * This is called whenever a process attempts to open the device file
-+ */
-+static int device_open(struct inode *inode, struct file *file)
-+{
-+ /*
-+ * We don't want to talk to two processes at the same time
-+ */
-+ if (Device_Open)
-+ return -EBUSY;
-+
-+ Device_Open++;
-+ /*
-+ * Initialize the message
-+ */
-+ try_module_get(THIS_MODULE);
-+ return 0;
-+}
-+
-+static int device_release(struct inode *inode, struct file *file)
-+{
-+ /*
-+ * We're now ready for our next caller
-+ */
-+ Device_Open--;
-+
-+ module_put(THIS_MODULE);
-+ return 0;
-+}
-+
-+/*
-+ * This function is called whenever a process tries to do an ioctl on our
-+ * device file. We get two extra parameters (additional to the inode and file
-+ * structures, which all device functions get): the number of the ioctl called
-+ * and the parameter given to the ioctl function.
-+ *
-+ * If the ioctl is write or read/write (meaning output is returned to the
-+ * calling process), the ioctl call returns the output of this function.
-+ *
-+ */
-+static long device_ioctl(struct file *file, /* see include/linux/fs.h */
-+ unsigned int ioctl_num, /* number and param for ioctl */
-+ unsigned long ioctl_param)
-+{
-+ unsigned size;
-+ /*
-+ * Switch according to the ioctl called
-+ */
-+ switch (ioctl_num) {
-+ case IOCTL_MBOX_PROPERTY:
-+ /*
-+ * Receive a pointer to a message (in user space) and set that
-+ * to be the device's message. Get the parameter given to
-+ * ioctl by the process.
-+ */
-+ mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
-+ return bcm_mailbox_property((void *)ioctl_param, size);
-+ break;
-+ default:
-+ printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/* Module Declarations */
-+
-+/*
-+ * This structure will hold the functions to be called
-+ * when a process does something to the device we
-+ * created. Since a pointer to this structure is kept in
-+ * the devices table, it can't be local to
-+ * init_module. NULL is for unimplemented functios.
-+ */
-+struct file_operations fops = {
-+ .unlocked_ioctl = device_ioctl,
-+ .open = device_open,
-+ .release = device_release, /* a.k.a. close */
-+};
-+
-+static int bcm_vcio_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+ struct vc_mailbox *mailbox;
-+
-+ mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
-+ if (NULL == mailbox) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to allocate "
-+ "mailbox memory\n");
-+ ret = -ENOMEM;
-+ } else {
-+ struct resource *res;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (res == NULL) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
-+ "resource\n");
-+ ret = -ENODEV;
-+ kfree(mailbox);
-+ } else {
-+ /* should be based on the registers from res really */
-+ mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
-+
-+ platform_set_drvdata(pdev, mailbox);
-+ dev_mbox_register(DRIVER_NAME, &pdev->dev);
-+
-+ mbox_irqaction.dev_id = mailbox;
-+ setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
-+ printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
-+ __io_address(ARM_0_MAIL0_RD));
-+ }
-+ }
-+
-+ if (ret == 0) {
-+ /*
-+ * Register the character device
-+ */
-+ ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
-+
-+ /*
-+ * Negative values signify an error
-+ */
-+ if (ret < 0) {
-+ printk(KERN_ERR DRIVER_NAME
-+ "Failed registering the character device %d\n", ret);
-+ return ret;
-+ }
-+ vcio_class = class_create(THIS_MODULE, BCM_VCIO_DRIVER_NAME);
-+ if (IS_ERR(vcio_class)) {
-+ ret = PTR_ERR(vcio_class);
-+ return ret ;
-+ }
-+ device_create(vcio_class, NULL, MKDEV(MAJOR_NUM, 0), NULL,
-+ "vcio");
-+ }
-+ return ret;
-+}
-+
-+static int bcm_vcio_remove(struct platform_device *pdev)
-+{
-+ struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+ kfree(mailbox);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm_mbox_driver = {
-+ .probe = bcm_vcio_probe,
-+ .remove = bcm_vcio_remove,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init bcm_mbox_init(void)
-+{
-+ int ret;
-+
-+ printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
-+
-+ ret = platform_driver_register(&bcm_mbox_driver);
-+ if (ret != 0) {
-+ printk(KERN_ERR DRIVER_NAME ": failed to register "
-+ "on platform\n");
-+ }
-+
-+ return ret;
-+}
-+
-+static void __exit bcm_mbox_exit(void)
-+{
-+ device_destroy(vcio_class,MKDEV(MAJOR_NUM, 0));
-+ class_destroy(vcio_class);
-+ unregister_chrdev(MAJOR_NUM, DEVICE_FILE_NAME);
-+ platform_driver_unregister(&bcm_mbox_driver);
-+}
-+
-+arch_initcall(bcm_mbox_init); /* Initialize early */
-+module_exit(bcm_mbox_exit);
-+
-+MODULE_AUTHOR("Gray Girling");
-+MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:bcm-mbox");
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/vc_mem.c linux-rpi/arch/arm/mach-bcm2709/vc_mem.c
---- linux-3.18.14/arch/arm/mach-bcm2709/vc_mem.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/vc_mem.c 2015-05-31 14:46:08.217661004 -0500
-@@ -0,0 +1,431 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/debugfs.h>
-+#include <asm/uaccess.h>
-+#include <linux/dma-mapping.h>
-+
-+#ifdef CONFIG_ARCH_KONA
-+#include <chal/chal_ipc.h>
-+#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
-+#else
-+#include <csp/chal_ipc.h>
-+#endif
-+
-+#include "mach/vc_mem.h"
-+#include <mach/vcio.h>
-+
-+#define DRIVER_NAME "vc-mem"
-+
-+// Device (/dev) related variables
-+static dev_t vc_mem_devnum = 0;
-+static struct class *vc_mem_class = NULL;
-+static struct cdev vc_mem_cdev;
-+static int vc_mem_inited = 0;
-+
-+#ifdef CONFIG_DEBUG_FS
-+static struct dentry *vc_mem_debugfs_entry;
-+#endif
-+
-+/*
-+ * Videocore memory addresses and size
-+ *
-+ * Drivers that wish to know the videocore memory addresses and sizes should
-+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
-+ * headers. This allows the other drivers to not be tied down to a a certain
-+ * address/size at compile time.
-+ *
-+ * In the future, the goal is to have the videocore memory virtual address and
-+ * size be calculated at boot time rather than at compile time. The decision of
-+ * where the videocore memory resides and its size would be in the hands of the
-+ * bootloader (and/or kernel). When that happens, the values of these variables
-+ * would be calculated and assigned in the init function.
-+ */
-+// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
-+unsigned long mm_vc_mem_phys_addr = 0x00000000;
-+unsigned int mm_vc_mem_size = 0;
-+unsigned int mm_vc_mem_base = 0;
-+
-+EXPORT_SYMBOL(mm_vc_mem_phys_addr);
-+EXPORT_SYMBOL(mm_vc_mem_size);
-+EXPORT_SYMBOL(mm_vc_mem_base);
-+
-+static uint phys_addr = 0;
-+static uint mem_size = 0;
-+static uint mem_base = 0;
-+
-+
-+/****************************************************************************
-+*
-+* vc_mem_open
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_open(struct inode *inode, struct file *file)
-+{
-+ (void) inode;
-+ (void) file;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_release
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_release(struct inode *inode, struct file *file)
-+{
-+ (void) inode;
-+ (void) file;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_size
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_size(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_base
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_base(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_get_current_size
-+*
-+***************************************************************************/
-+
-+int
-+vc_mem_get_current_size(void)
-+{
-+ return mm_vc_mem_size;
-+}
-+
-+EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
-+
-+/****************************************************************************
-+*
-+* vc_mem_ioctl
-+*
-+***************************************************************************/
-+
-+static long
-+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int rc = 0;
-+
-+ (void) cmd;
-+ (void) arg;
-+
-+ pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+ switch (cmd) {
-+ case VC_MEM_IOC_MEM_PHYS_ADDR:
-+ {
-+ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
-+ __func__, (void *) mm_vc_mem_phys_addr);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
-+ sizeof (mm_vc_mem_phys_addr)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_SIZE:
-+ {
-+ // Get the videocore memory size first
-+ vc_mem_get_size();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
-+ mm_vc_mem_size);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_size,
-+ sizeof (mm_vc_mem_size)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_BASE:
-+ {
-+ // Get the videocore memory base
-+ vc_mem_get_base();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
-+ mm_vc_mem_base);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+ sizeof (mm_vc_mem_base)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ case VC_MEM_IOC_MEM_LOAD:
-+ {
-+ // Get the videocore memory base
-+ vc_mem_get_base();
-+
-+ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
-+ mm_vc_mem_base);
-+
-+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+ sizeof (mm_vc_mem_base)) != 0) {
-+ rc = -EFAULT;
-+ }
-+ break;
-+ }
-+ default:
-+ {
-+ return -ENOTTY;
-+ }
-+ }
-+ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_mmap
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+ int rc = 0;
-+ unsigned long length = vma->vm_end - vma->vm_start;
-+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
-+
-+ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
-+ __func__, (long) vma->vm_start, (long) vma->vm_end,
-+ (long) vma->vm_pgoff);
-+
-+ if (offset + length > mm_vc_mem_size) {
-+ pr_err("%s: length %ld is too big\n", __func__, length);
-+ return -EINVAL;
-+ }
-+ // Do not cache the memory map
-+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+
-+ rc = remap_pfn_range(vma, vma->vm_start,
-+ (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
-+ vma->vm_pgoff, length, vma->vm_page_prot);
-+ if (rc != 0) {
-+ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
-+ }
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for the driver.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_mem_fops = {
-+ .owner = THIS_MODULE,
-+ .open = vc_mem_open,
-+ .release = vc_mem_release,
-+ .unlocked_ioctl = vc_mem_ioctl,
-+ .mmap = vc_mem_mmap,
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void vc_mem_debugfs_deinit(void)
-+{
-+ debugfs_remove_recursive(vc_mem_debugfs_entry);
-+ vc_mem_debugfs_entry = NULL;
-+}
-+
-+
-+static int vc_mem_debugfs_init(
-+ struct device *dev)
-+{
-+ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
-+ if (!vc_mem_debugfs_entry) {
-+ dev_warn(dev, "could not create debugfs entry\n");
-+ return -EFAULT;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_phys_addr",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_phys_addr)) {
-+ dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_size",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_size)) {
-+ dev_warn(dev, "%s:could not create vc_mem_size entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ if (!debugfs_create_x32("vc_mem_base",
-+ 0444,
-+ vc_mem_debugfs_entry,
-+ (u32 *)&mm_vc_mem_base)) {
-+ dev_warn(dev, "%s:could not create vc_mem_base entry\n",
-+ __func__);
-+ goto fail;
-+ }
-+
-+ return 0;
-+
-+fail:
-+ vc_mem_debugfs_deinit();
-+ return -EFAULT;
-+}
-+
-+#endif /* CONFIG_DEBUG_FS */
-+
-+
-+/****************************************************************************
-+*
-+* vc_mem_init
-+*
-+***************************************************************************/
-+
-+static int __init
-+vc_mem_init(void)
-+{
-+ int rc = -EFAULT;
-+ struct device *dev;
-+
-+ pr_debug("%s: called\n", __func__);
-+
-+ mm_vc_mem_phys_addr = phys_addr;
-+ mm_vc_mem_size = mem_size;
-+ mm_vc_mem_base = mem_base;
-+
-+ vc_mem_get_size();
-+
-+ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
-+ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
-+
-+ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
-+ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
-+ __func__, rc);
-+ goto out_err;
-+ }
-+
-+ cdev_init(&vc_mem_cdev, &vc_mem_fops);
-+ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
-+ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
-+ goto out_unregister;
-+ }
-+
-+ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
-+ if (IS_ERR(vc_mem_class)) {
-+ rc = PTR_ERR(vc_mem_class);
-+ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
-+ goto out_cdev_del;
-+ }
-+
-+ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
-+ DRIVER_NAME);
-+ if (IS_ERR(dev)) {
-+ rc = PTR_ERR(dev);
-+ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
-+ goto out_class_destroy;
-+ }
-+
-+#ifdef CONFIG_DEBUG_FS
-+ /* don't fail if the debug entries cannot be created */
-+ vc_mem_debugfs_init(dev);
-+#endif
-+
-+ vc_mem_inited = 1;
-+ return 0;
-+
-+ device_destroy(vc_mem_class, vc_mem_devnum);
-+
-+ out_class_destroy:
-+ class_destroy(vc_mem_class);
-+ vc_mem_class = NULL;
-+
-+ out_cdev_del:
-+ cdev_del(&vc_mem_cdev);
-+
-+ out_unregister:
-+ unregister_chrdev_region(vc_mem_devnum, 1);
-+
-+ out_err:
-+ return -1;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_mem_exit
-+*
-+***************************************************************************/
-+
-+static void __exit
-+vc_mem_exit(void)
-+{
-+ pr_debug("%s: called\n", __func__);
-+
-+ if (vc_mem_inited) {
-+#if CONFIG_DEBUG_FS
-+ vc_mem_debugfs_deinit();
-+#endif
-+ device_destroy(vc_mem_class, vc_mem_devnum);
-+ class_destroy(vc_mem_class);
-+ cdev_del(&vc_mem_cdev);
-+ unregister_chrdev_region(vc_mem_devnum, 1);
-+ }
-+}
-+
-+module_init(vc_mem_init);
-+module_exit(vc_mem_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-+
-+module_param(phys_addr, uint, 0644);
-+module_param(mem_size, uint, 0644);
-+module_param(mem_base, uint, 0644);
-diff -Nur linux-3.18.14/arch/arm/mach-bcm2709/vc_support.c linux-rpi/arch/arm/mach-bcm2709/vc_support.c
---- linux-3.18.14/arch/arm/mach-bcm2709/vc_support.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/arch/arm/mach-bcm2709/vc_support.c 2015-05-31 14:46:08.217661004 -0500
-@@ -0,0 +1,318 @@
-+/*
-+ * vc_support.c
-+ *
-+ * Created on: 25 Nov 2012
-+ * Author: Simon
-+ */
-+
-+#include <linux/module.h>
-+#include <mach/vcio.h>
-+
-+#ifdef ECLIPSE_IGNORE
-+
-+#define __user
-+#define __init
-+#define __exit
-+#define __iomem
-+#define KERN_DEBUG
-+#define KERN_ERR
-+#define KERN_WARNING
-+#define KERN_INFO
-+#define _IOWR(a, b, c) b
-+#define _IOW(a, b, c) b
-+#define _IO(a, b) b
-+
-+#endif
-+
-+/****** VC MAILBOX FUNCTIONALITY ******/
-+unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
-+{
-+ struct vc_msg
-+ {
-+ unsigned int m_msgSize;
-+ unsigned int m_response;
-+
-+ struct vc_tag
-+ {
-+ unsigned int m_tagId;
-+ unsigned int m_sendBufferSize;
-+ union {
-+ unsigned int m_sendDataSize;
-+ unsigned int m_recvDataSize;
-+ };
-+
-+ struct args
-+ {
-+ union {
-+ unsigned int m_size;
-+ unsigned int m_handle;
-+ };
-+ unsigned int m_alignment;
-+ unsigned int m_flags;
-+ } m_args;
-+ } m_tag;
-+
-+ unsigned int m_endTag;
-+ } msg;
-+ int s;
-+
-+ msg.m_msgSize = sizeof(msg);
-+ msg.m_response = 0;
-+ msg.m_endTag = 0;
-+
-+ //fill in the tag for the allocation command
-+ msg.m_tag.m_tagId = 0x3000c;
-+ msg.m_tag.m_sendBufferSize = 12;
-+ msg.m_tag.m_sendDataSize = 12;
-+
-+ //fill in our args
-+ msg.m_tag.m_args.m_size = size;
-+ msg.m_tag.m_args.m_alignment = alignment;
-+ msg.m_tag.m_args.m_flags = flags;
-+
-+ //run the command
-+ s = bcm_mailbox_property(&msg, sizeof(msg));
-+
-+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
-+ {
-+ *pHandle = msg.m_tag.m_args.m_handle;
-+ return 0;
-+ }
-+ else
-+ {
-+ printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
-+ s, msg.m_response, msg.m_tag.m_recvDataSize);
-+ return 1;
-+ }
-+}
-+
-+unsigned int ReleaseVcMemory(unsigned int handle)
-+{
-+ struct vc_msg
-+ {
-+ unsigned int m_msgSize;
-+ unsigned int m_response;
-+
-+ struct vc_tag
-+ {
-+ unsigned int m_tagId;
-+ unsigned int m_sendBufferSize;
-+ union {
-+ unsigned int m_sendDataSize;
-+ unsigned int m_recvDataSize;
-+ };
-+
-+ struct args
-+ {
-+ union {
-+ unsigned int m_handle;
-+ unsigned int m_error;
-+ };
-+ } m_args;
-+ } m_tag;
-+
-+ unsigned int m_endTag;
-+ } msg;
-+ int s;
-+
-+ msg.m_msgSize = sizeof(msg);
-+ msg.m_response = 0;
-+ msg.m_endTag = 0;
-+
-+ //fill in the tag for the release command
-+ msg.m_tag.m_tagId = 0x3000f;
-+ msg.m_tag.m_sendBufferSize = 4;
-+ msg.m_tag.m_sendDataSize = 4;
-+
-+ //pass across the handle
-+ msg.m_tag.m_args.m_handle = handle;
-+
-+ s = bcm_mailbox_property(&msg, sizeof(msg));
-+
-+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
-+ return 0;
-+ else
-+ {
-+ printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
-+ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
-+ return 1;
-+ }
-+}
-+
-+unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
-+{
-+ struct vc_msg
-+ {
-+ unsigned int m_msgSize;
-+ unsigned int m_response;
-+
-+ struct vc_tag
-+ {
-+ unsigned int m_tagId;
-+ unsigned int m_sendBufferSize;
-+ union {
-+ unsigned int m_sendDataSize;
-+ unsigned int m_recvDataSize;
-+ };
-+
-+ struct args
-+ {
-+ union {
-+ unsigned int m_handle;
-+ unsigned int m_busAddress;
-+ };
-+ } m_args;
-+ } m_tag;
-+
-+ unsigned int m_endTag;
-+ } msg;
-+ int s;
-+
-+ msg.m_msgSize = sizeof(msg);
-+ msg.m_response = 0;
-+ msg.m_endTag = 0;
-+
-+ //fill in the tag for the lock command
-+ msg.m_tag.m_tagId = 0x3000d;
-+ msg.m_tag.m_sendBufferSize = 4;
-+ msg.m_tag.m_sendDataSize = 4;
-+
-+ //pass across the handle
-+ msg.m_tag.m_args.m_handle = handle;
-+
-+ s = bcm_mailbox_property(&msg, sizeof(msg));
-+
-+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
-+ {
-+ //pick out the bus address
-+ *pBusAddress = msg.m_tag.m_args.m_busAddress;
-+ return 0;
-+ }
-+ else
-+ {
-+ printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
-+ s, msg.m_response, msg.m_tag.m_recvDataSize);
-+ return 1;
-+ }
-+}
-+
-+unsigned int UnlockVcMemory(unsigned int handle)
-+{
-+ struct vc_msg
-+ {
-+ unsigned int m_msgSize;
-+ unsigned int m_response;
-+
-+ struct vc_tag
-+ {
-+ unsigned int m_tagId;
-+ unsigned int m_sendBufferSize;
-+ union {
-+ unsigned int m_sendDataSize;
-+ unsigned int m_recvDataSize;
-+ };
-+
-+ struct args
-+ {
-+ union {
-+ unsigned int m_handle;
-+ unsigned int m_error;
-+ };
-+ } m_args;
-+ } m_tag;
-+
-+ unsigned int m_endTag;
-+ } msg;
-+ int s;
-+
-+ msg.m_msgSize = sizeof(msg);
-+ msg.m_response = 0;
-+ msg.m_endTag = 0;
-+
-+ //fill in the tag for the unlock command
-+ msg.m_tag.m_tagId = 0x3000e;
-+ msg.m_tag.m_sendBufferSize = 4;
-+ msg.m_tag.m_sendDataSize = 4;
-+
-+ //pass across the handle
-+ msg.m_tag.m_args.m_handle = handle;
-+
-+ s = bcm_mailbox_property(&msg, sizeof(msg));
-+
-+ //check the error code too
-+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
-+ return 0;
-+ else
-+ {
-+ printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
-+ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
-+ return 1;
-+ }
-+}
-+
-+unsigned int ExecuteVcCode(unsigned int code,
-+ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
-+{
-+ struct vc_msg
-+ {
-+ unsigned int m_msgSize;
-+ unsigned int m_response;
-+
-+ struct vc_tag
-+ {
-+ unsigned int m_tagId;
-+ unsigned int m_sendBufferSize;
-+ union {
-+ unsigned int m_sendDataSize;
-+ unsigned int m_recvDataSize;
-+ };
-+
-+ struct args
-+ {
-+ union {
-+ unsigned int m_pCode;
-+ unsigned int m_return;
-+ };
-+ unsigned int m_r0;
-+ unsigned int m_r1;
-+ unsigned int m_r2;
-+ unsigned int m_r3;
-+ unsigned int m_r4;
-+ unsigned int m_r5;
-+ } m_args;
-+ } m_tag;
-+
-+ unsigned int m_endTag;
-+ } msg;
-+ int s;
-+
-+ msg.m_msgSize = sizeof(msg);
-+ msg.m_response = 0;
-+ msg.m_endTag = 0;
-+
-+ //fill in the tag for the unlock command
-+ msg.m_tag.m_tagId = 0x30010;
-+ msg.m_tag.m_sendBufferSize = 28;
-+ msg.m_tag.m_sendDataSize = 28;
-+
-+ //pass across the handle
-+ msg.m_tag.m_args.m_pCode = code;
-+ msg.m_tag.m_args.m_r0 = r0;
-+ msg.m_tag.m_args.m_r1 = r1;
-+ msg.m_tag.m_args.m_r2 = r2;
-+ msg.m_tag.m_args.m_r3 = r3;
-+ msg.m_tag.m_args.m_r4 = r4;
-+ msg.m_tag.m_args.m_r5 = r5;
-+
-+ s = bcm_mailbox_property(&msg, sizeof(msg));
-+
-+ //check the error code too
-+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
-+ return msg.m_tag.m_args.m_return;
-+ else
-+ {
-+ printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
-+ s, msg.m_response, msg.m_tag.m_recvDataSize);
-+ return 1;
-+ }
-+}
-diff -Nur linux-3.18.14/arch/arm/Makefile linux-rpi/arch/arm/Makefile
---- linux-3.18.14/arch/arm/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/Makefile 2015-05-31 14:46:07.961661006 -0500
-@@ -146,6 +146,8 @@
- machine-$(CONFIG_ARCH_AT91) += at91
- machine-$(CONFIG_ARCH_AXXIA) += axxia
- machine-$(CONFIG_ARCH_BCM) += bcm
-+machine-$(CONFIG_ARCH_BCM2708) += bcm2708
-+machine-$(CONFIG_ARCH_BCM2709) += bcm2709
- machine-$(CONFIG_ARCH_BERLIN) += berlin
- machine-$(CONFIG_ARCH_CLPS711X) += clps711x
- machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
-diff -Nur linux-3.18.14/arch/arm/mm/Kconfig linux-rpi/arch/arm/mm/Kconfig
---- linux-3.18.14/arch/arm/mm/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/mm/Kconfig 2015-05-31 14:46:08.565661001 -0500
-@@ -358,7 +358,7 @@
-
- # ARMv6
- config CPU_V6
-- bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
-+ bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
- select CPU_32v6
- select CPU_ABRT_EV6
- select CPU_CACHE_V6
-diff -Nur linux-3.18.14/arch/arm/mm/proc-v6.S linux-rpi/arch/arm/mm/proc-v6.S
---- linux-3.18.14/arch/arm/mm/proc-v6.S 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/mm/proc-v6.S 2015-05-31 14:46:08.585661001 -0500
-@@ -73,10 +73,19 @@
- *
- * IRQs are already disabled.
- */
-+
-+/* See jira SW-5991 for details of this workaround */
- ENTRY(cpu_v6_do_idle)
-- mov r1, #0
-- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
-- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
-+ .align 5
-+ mov r1, #2
-+1: subs r1, #1
-+ nop
-+ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
-+ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
-+ nop
-+ nop
-+ nop
-+ bne 1b
- ret lr
-
- ENTRY(cpu_v6_dcache_clean_area)
-diff -Nur linux-3.18.14/arch/arm/mm/proc-v7.S linux-rpi/arch/arm/mm/proc-v7.S
---- linux-3.18.14/arch/arm/mm/proc-v7.S 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/mm/proc-v7.S 2015-05-31 14:46:08.585661001 -0500
-@@ -441,6 +441,7 @@
- orr r0, r0, r6 @ set them
- THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
- ret lr @ return to head.S:__ret
-+ .space 256
- ENDPROC(__v7_setup)
-
- .align 2
-diff -Nur linux-3.18.14/arch/arm/tools/mach-types linux-rpi/arch/arm/tools/mach-types
---- linux-3.18.14/arch/arm/tools/mach-types 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/arch/arm/tools/mach-types 2015-05-31 14:46:08.617661000 -0500
-@@ -522,6 +522,8 @@
- prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
- paz00 MACH_PAZ00 PAZ00 3128
- acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
-+bcm2708 MACH_BCM2708 BCM2708 3138
-+bcm2709 MACH_BCM2709 BCM2709 3139
- ag5evm MACH_AG5EVM AG5EVM 3189
- ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
- wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
-diff -Nur linux-3.18.14/Documentation/sound/alsa/ControlNames.txt linux-rpi/Documentation/sound/alsa/ControlNames.txt
---- linux-3.18.14/Documentation/sound/alsa/ControlNames.txt 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/Documentation/sound/alsa/ControlNames.txt 2015-05-31 14:46:07.825661008 -0500
-@@ -49,11 +49,11 @@
- IEC958
-
- Exceptions:
-- [Digital] Capture Source
-- [Digital] Capture Switch (aka input gain switch)
-- [Digital] Capture Volume (aka input gain volume)
-- [Digital] Playback Switch (aka output gain switch)
-- [Digital] Playback Volume (aka output gain volume)
-+ [Analogue|Digital] Capture Source
-+ [Analogue|Digital] Capture Switch (aka input gain switch)
-+ [Analogue|Digital] Capture Volume (aka input gain volume)
-+ [Analogue|Digital] Playback Switch (aka output gain switch)
-+ [Analogue|Digital] Playback Volume (aka output gain volume)
- Tone Control - Switch
- Tone Control - Bass
- Tone Control - Treble
-diff -Nur linux-3.18.14/Documentation/video4linux/bcm2835-v4l2.txt linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt
---- linux-3.18.14/Documentation/video4linux/bcm2835-v4l2.txt 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt 2015-05-31 14:46:07.861661007 -0500
-@@ -0,0 +1,60 @@
-+
-+BCM2835 (aka Raspberry Pi) V4L2 driver
-+======================================
-+
-+1. Copyright
-+============
-+
-+Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+
-+2. License
-+==========
-+
-+This program is free software; you can redistribute it and/or modify
-+it under the terms of the GNU General Public License as published by
-+the Free Software Foundation; either version 2 of the License, or
-+(at your option) any later version.
-+
-+This program is distributed in the hope that it will be useful,
-+but WITHOUT ANY WARRANTY; without even the implied warranty of
-+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+GNU General Public License for more details.
-+
-+You should have received a copy of the GNU General Public License
-+along with this program; if not, write to the Free Software
-+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+
-+3. Quick Start
-+==============
-+
-+You need a version 1.0 or later of v4l2-ctl, available from:
-+ git://git.linuxtv.org/v4l-utils.git
-+
-+$ sudo modprobe bcm2835-v4l2
-+
-+Turn on the overlay:
-+
-+$ v4l2-ctl --overlay=1
-+
-+Turn off the overlay:
-+
-+$ v4l2-ctl --overlay=0
-+
-+Set the capture format for video:
-+
-+$ v4l2-ctl --set-fmt-video=width=1920,height=1088,pixelformat=4
-+
-+(Note: 1088 not 1080).
-+
-+Capture:
-+
-+$ v4l2-ctl --stream-mmap=3 --stream-count=100 --stream-to=somefile.h264
-+
-+Stills capture:
-+
-+$ v4l2-ctl --set-fmt-video=width=2592,height=1944,pixelformat=3
-+$ v4l2-ctl --stream-mmap=3 --stream-count=1 --stream-to=somefile.jpg
-+
-+List of available formats:
-+
-+$ v4l2-ctl --list-formats
-diff -Nur linux-3.18.14/drivers/char/broadcom/Kconfig linux-rpi/drivers/char/broadcom/Kconfig
---- linux-3.18.14/drivers/char/broadcom/Kconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/Kconfig 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,22 @@
-+#
-+# Broadcom char driver config
-+#
-+
-+menuconfig BRCM_CHAR_DRIVERS
-+ bool "Broadcom Char Drivers"
-+ help
-+ Broadcom's char drivers
-+
-+config BCM_VC_CMA
-+ bool "Videocore CMA"
-+ depends on CMA && BRCM_CHAR_DRIVERS && BCM2708_VCHIQ
-+ default n
-+ help
-+ Helper for videocore CMA access.
-+
-+config BCM_VC_SM
-+ tristate "VMCS Shared Memory"
-+ default n
-+ help
-+ Support for the VC shared memory on the Broadcom reference
-+ design. Uses the VCHIQ stack.
-diff -Nur linux-3.18.14/drivers/char/broadcom/Makefile linux-rpi/drivers/char/broadcom/Makefile
---- linux-3.18.14/drivers/char/broadcom/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/Makefile 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,2 @@
-+obj-$(CONFIG_BCM_VC_CMA) += vc_cma/
-+obj-$(CONFIG_BCM_VC_SM) += vc_sm/
-diff -Nur linux-3.18.14/drivers/char/broadcom/vc_cma/Makefile linux-rpi/drivers/char/broadcom/vc_cma/Makefile
---- linux-3.18.14/drivers/char/broadcom/vc_cma/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/vc_cma/Makefile 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,14 @@
-+ccflags-y += -Wall -Wstrict-prototypes -Wno-trigraphs
-+ccflags-y += -Werror
-+ccflags-y += -Iinclude/linux/broadcom
-+ccflags-y += -Idrivers/misc/vc04_services
-+ccflags-y += -Idrivers/misc/vc04_services/interface/vchi
-+ccflags-y += -Idrivers/misc/vc04_services/interface/vchiq_arm
-+
-+ccflags-y += -D__KERNEL__
-+ccflags-y += -D__linux__
-+ccflags-y += -Werror
-+
-+obj-$(CONFIG_BCM_VC_CMA) += vc-cma.o
-+
-+vc-cma-objs := vc_cma.o
-diff -Nur linux-3.18.14/drivers/char/broadcom/vc_cma/vc_cma.c linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c
---- linux-3.18.14/drivers/char/broadcom/vc_cma/vc_cma.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,1193 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/kthread.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dma-contiguous.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+#include <asm/cacheflush.h>
-+
-+#include "vc_cma.h"
-+
-+#include "vchiq_util.h"
-+#include "vchiq_connected.h"
-+//#include "debug_sym.h"
-+//#include "vc_mem.h"
-+
-+#define DRIVER_NAME "vc-cma"
-+
-+#define LOG_DBG(fmt, ...) \
-+ if (vc_cma_debug) \
-+ printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
-+#define LOG_INFO(fmt, ...) \
-+ printk(KERN_INFO fmt "\n", ##__VA_ARGS__)
-+#define LOG_ERR(fmt, ...) \
-+ printk(KERN_ERR fmt "\n", ##__VA_ARGS__)
-+
-+#define VC_CMA_FOURCC VCHIQ_MAKE_FOURCC('C', 'M', 'A', ' ')
-+#define VC_CMA_VERSION 2
-+
-+#define VC_CMA_CHUNK_ORDER 6 /* 256K */
-+#define VC_CMA_CHUNK_SIZE (4096 << VC_CMA_CHUNK_ORDER)
-+#define VC_CMA_MAX_PARAMS_PER_MSG \
-+ ((VCHIQ_MAX_MSG_SIZE - sizeof(unsigned short))/sizeof(unsigned short))
-+#define VC_CMA_RESERVE_COUNT_MAX 16
-+
-+#define PAGES_PER_CHUNK (VC_CMA_CHUNK_SIZE / PAGE_SIZE)
-+
-+#define VCADDR_TO_PHYSADDR(vcaddr) (mm_vc_mem_phys_addr + vcaddr)
-+
-+#define loud_error(...) \
-+ LOG_ERR("===== " __VA_ARGS__)
-+
-+enum {
-+ VC_CMA_MSG_QUIT,
-+ VC_CMA_MSG_OPEN,
-+ VC_CMA_MSG_TICK,
-+ VC_CMA_MSG_ALLOC, /* chunk count */
-+ VC_CMA_MSG_FREE, /* chunk, chunk, ... */
-+ VC_CMA_MSG_ALLOCATED, /* chunk, chunk, ... */
-+ VC_CMA_MSG_REQUEST_ALLOC, /* chunk count */
-+ VC_CMA_MSG_REQUEST_FREE, /* chunk count */
-+ VC_CMA_MSG_RESERVE, /* bytes lo, bytes hi */
-+ VC_CMA_MSG_UPDATE_RESERVE,
-+ VC_CMA_MSG_MAX
-+};
-+
-+struct cma_msg {
-+ unsigned short type;
-+ unsigned short params[VC_CMA_MAX_PARAMS_PER_MSG];
-+};
-+
-+struct vc_cma_reserve_user {
-+ unsigned int pid;
-+ unsigned int reserve;
-+};
-+
-+/* Device (/dev) related variables */
-+static dev_t vc_cma_devnum;
-+static struct class *vc_cma_class;
-+static struct cdev vc_cma_cdev;
-+static int vc_cma_inited;
-+static int vc_cma_debug;
-+
-+/* Proc entry */
-+static struct proc_dir_entry *vc_cma_proc_entry;
-+
-+phys_addr_t vc_cma_base;
-+struct page *vc_cma_base_page;
-+unsigned int vc_cma_size;
-+EXPORT_SYMBOL(vc_cma_size);
-+unsigned int vc_cma_initial;
-+unsigned int vc_cma_chunks;
-+unsigned int vc_cma_chunks_used;
-+unsigned int vc_cma_chunks_reserved;
-+
-+
-+void *vc_cma_dma_alloc;
-+unsigned int vc_cma_dma_size;
-+
-+static int in_loud_error;
-+
-+unsigned int vc_cma_reserve_total;
-+unsigned int vc_cma_reserve_count;
-+struct vc_cma_reserve_user vc_cma_reserve_users[VC_CMA_RESERVE_COUNT_MAX];
-+static DEFINE_SEMAPHORE(vc_cma_reserve_mutex);
-+static DEFINE_SEMAPHORE(vc_cma_worker_queue_push_mutex);
-+
-+static u64 vc_cma_dma_mask = DMA_BIT_MASK(32);
-+static struct platform_device vc_cma_device = {
-+ .name = "vc-cma",
-+ .id = 0,
-+ .dev = {
-+ .dma_mask = &vc_cma_dma_mask,
-+ .coherent_dma_mask = DMA_BIT_MASK(32),
-+ },
-+};
-+
-+static VCHIQ_INSTANCE_T cma_instance;
-+static VCHIQ_SERVICE_HANDLE_T cma_service;
-+static VCHIU_QUEUE_T cma_msg_queue;
-+static struct task_struct *cma_worker;
-+
-+static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid);
-+static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply);
-+static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T * header,
-+ VCHIQ_SERVICE_HANDLE_T service,
-+ void *bulk_userdata);
-+static void send_vc_msg(unsigned short type,
-+ unsigned short param1, unsigned short param2);
-+static bool send_worker_msg(VCHIQ_HEADER_T * msg);
-+
-+static int early_vc_cma_mem(char *p)
-+{
-+ unsigned int new_size;
-+ printk(KERN_NOTICE "early_vc_cma_mem(%s)", p);
-+ vc_cma_size = memparse(p, &p);
-+ vc_cma_initial = vc_cma_size;
-+ if (*p == '/')
-+ vc_cma_size = memparse(p + 1, &p);
-+ if (*p == '@')
-+ vc_cma_base = memparse(p + 1, &p);
-+
-+ new_size = (vc_cma_size - ((-vc_cma_base) & (VC_CMA_CHUNK_SIZE - 1)))
-+ & ~(VC_CMA_CHUNK_SIZE - 1);
-+ if (new_size > vc_cma_size)
-+ vc_cma_size = 0;
-+ vc_cma_initial = (vc_cma_initial + VC_CMA_CHUNK_SIZE - 1)
-+ & ~(VC_CMA_CHUNK_SIZE - 1);
-+ if (vc_cma_initial > vc_cma_size)
-+ vc_cma_initial = vc_cma_size;
-+ vc_cma_base = (vc_cma_base + VC_CMA_CHUNK_SIZE - 1)
-+ & ~(VC_CMA_CHUNK_SIZE - 1);
-+
-+ printk(KERN_NOTICE " -> initial %x, size %x, base %x", vc_cma_initial,
-+ vc_cma_size, (unsigned int)vc_cma_base);
-+
-+ return 0;
-+}
-+
-+early_param("vc-cma-mem", early_vc_cma_mem);
-+
-+void vc_cma_early_init(void)
-+{
-+ LOG_DBG("vc_cma_early_init - vc_cma_chunks = %d", vc_cma_chunks);
-+ if (vc_cma_size) {
-+ int rc = platform_device_register(&vc_cma_device);
-+ LOG_DBG("platform_device_register -> %d", rc);
-+ }
-+}
-+
-+void vc_cma_reserve(void)
-+{
-+ /* if vc_cma_size is set, then declare vc CMA area of the same
-+ * size from the end of memory
-+ */
-+ if (vc_cma_size) {
-+ if (dma_declare_contiguous(&vc_cma_device.dev, vc_cma_size,
-+ vc_cma_base, 0) == 0) {
-+ if (!dev_get_cma_area(NULL)) {
-+ /* There is no default CMA area - make this
-+ the default */
-+ struct cma *vc_cma_area = dev_get_cma_area(
-+ &vc_cma_device.dev);
-+ dma_contiguous_set_default(vc_cma_area);
-+ LOG_INFO("vc_cma_reserve - using vc_cma as "
-+ "the default contiguous DMA area");
-+ }
-+ } else {
-+ LOG_ERR("vc_cma: dma_declare_contiguous(%x,%x) failed",
-+ vc_cma_size, (unsigned int)vc_cma_base);
-+ vc_cma_size = 0;
-+ }
-+ }
-+ vc_cma_chunks = vc_cma_size / VC_CMA_CHUNK_SIZE;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_open
-+*
-+***************************************************************************/
-+
-+static int vc_cma_open(struct inode *inode, struct file *file)
-+{
-+ (void)inode;
-+ (void)file;
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_release
-+*
-+***************************************************************************/
-+
-+static int vc_cma_release(struct inode *inode, struct file *file)
-+{
-+ (void)inode;
-+ (void)file;
-+
-+ vc_cma_set_reserve(0, current->tgid);
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_ioctl
-+*
-+***************************************************************************/
-+
-+static long vc_cma_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int rc = 0;
-+
-+ (void)cmd;
-+ (void)arg;
-+
-+ switch (cmd) {
-+ case VC_CMA_IOC_RESERVE:
-+ rc = vc_cma_set_reserve((unsigned int)arg, current->tgid);
-+ if (rc >= 0)
-+ rc = 0;
-+ break;
-+ default:
-+ LOG_ERR("vc-cma: Unknown ioctl %x", cmd);
-+ return -ENOTTY;
-+ }
-+
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for the driver.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_cma_fops = {
-+ .owner = THIS_MODULE,
-+ .open = vc_cma_open,
-+ .release = vc_cma_release,
-+ .unlocked_ioctl = vc_cma_ioctl,
-+};
-+
-+/****************************************************************************
-+*
-+* vc_cma_proc_open
-+*
-+***************************************************************************/
-+
-+static int vc_cma_show_info(struct seq_file *m, void *v)
-+{
-+ int i;
-+
-+ seq_printf(m, "Videocore CMA:\n");
-+ seq_printf(m, " Base : %08x\n", (unsigned int)vc_cma_base);
-+ seq_printf(m, " Length : %08x\n", vc_cma_size);
-+ seq_printf(m, " Initial : %08x\n", vc_cma_initial);
-+ seq_printf(m, " Chunk size : %08x\n", VC_CMA_CHUNK_SIZE);
-+ seq_printf(m, " Chunks : %4d (%d bytes)\n",
-+ (int)vc_cma_chunks,
-+ (int)(vc_cma_chunks * VC_CMA_CHUNK_SIZE));
-+ seq_printf(m, " Used : %4d (%d bytes)\n",
-+ (int)vc_cma_chunks_used,
-+ (int)(vc_cma_chunks_used * VC_CMA_CHUNK_SIZE));
-+ seq_printf(m, " Reserved : %4d (%d bytes)\n",
-+ (unsigned int)vc_cma_chunks_reserved,
-+ (int)(vc_cma_chunks_reserved * VC_CMA_CHUNK_SIZE));
-+
-+ for (i = 0; i < vc_cma_reserve_count; i++) {
-+ struct vc_cma_reserve_user *user = &vc_cma_reserve_users[i];
-+ seq_printf(m, " PID %5d: %d bytes\n", user->pid,
-+ user->reserve);
-+ }
-+ seq_printf(m, " dma_alloc : %p (%d pages)\n",
-+ vc_cma_dma_alloc ? page_address(vc_cma_dma_alloc) : 0,
-+ vc_cma_dma_size);
-+
-+ seq_printf(m, "\n");
-+
-+ return 0;
-+}
-+
-+static int vc_cma_proc_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, vc_cma_show_info, NULL);
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_proc_write
-+*
-+***************************************************************************/
-+
-+static int vc_cma_proc_write(struct file *file,
-+ const char __user *buffer,
-+ size_t size, loff_t *ppos)
-+{
-+ int rc = -EFAULT;
-+ char input_str[20];
-+
-+ memset(input_str, 0, sizeof(input_str));
-+
-+ if (size > sizeof(input_str)) {
-+ LOG_ERR("%s: input string length too long", __func__);
-+ goto out;
-+ }
-+
-+ if (copy_from_user(input_str, buffer, size - 1)) {
-+ LOG_ERR("%s: failed to get input string", __func__);
-+ goto out;
-+ }
-+#define ALLOC_STR "alloc"
-+#define FREE_STR "free"
-+#define DEBUG_STR "debug"
-+#define RESERVE_STR "reserve"
-+#define DMA_ALLOC_STR "dma_alloc"
-+#define DMA_FREE_STR "dma_free"
-+ if (strncmp(input_str, ALLOC_STR, strlen(ALLOC_STR)) == 0) {
-+ int alloc_size;
-+ char *p = input_str + strlen(ALLOC_STR);
-+
-+ while (*p == ' ')
-+ p++;
-+ alloc_size = memparse(p, NULL);
-+ LOG_INFO("/proc/vc-cma: alloc %d", alloc_size);
-+ if (alloc_size)
-+ send_vc_msg(VC_CMA_MSG_REQUEST_FREE,
-+ alloc_size / VC_CMA_CHUNK_SIZE, 0);
-+ else
-+ LOG_ERR("invalid size '%s'", p);
-+ rc = size;
-+ } else if (strncmp(input_str, FREE_STR, strlen(FREE_STR)) == 0) {
-+ int alloc_size;
-+ char *p = input_str + strlen(FREE_STR);
-+
-+ while (*p == ' ')
-+ p++;
-+ alloc_size = memparse(p, NULL);
-+ LOG_INFO("/proc/vc-cma: free %d", alloc_size);
-+ if (alloc_size)
-+ send_vc_msg(VC_CMA_MSG_REQUEST_ALLOC,
-+ alloc_size / VC_CMA_CHUNK_SIZE, 0);
-+ else
-+ LOG_ERR("invalid size '%s'", p);
-+ rc = size;
-+ } else if (strncmp(input_str, DEBUG_STR, strlen(DEBUG_STR)) == 0) {
-+ char *p = input_str + strlen(DEBUG_STR);
-+ while (*p == ' ')
-+ p++;
-+ if ((strcmp(p, "on") == 0) || (strcmp(p, "1") == 0))
-+ vc_cma_debug = 1;
-+ else if ((strcmp(p, "off") == 0) || (strcmp(p, "0") == 0))
-+ vc_cma_debug = 0;
-+ LOG_INFO("/proc/vc-cma: debug %s", vc_cma_debug ? "on" : "off");
-+ rc = size;
-+ } else if (strncmp(input_str, RESERVE_STR, strlen(RESERVE_STR)) == 0) {
-+ int alloc_size;
-+ int reserved;
-+ char *p = input_str + strlen(RESERVE_STR);
-+ while (*p == ' ')
-+ p++;
-+ alloc_size = memparse(p, NULL);
-+
-+ reserved = vc_cma_set_reserve(alloc_size, current->tgid);
-+ rc = (reserved >= 0) ? size : reserved;
-+ } else if (strncmp(input_str, DMA_ALLOC_STR, strlen(DMA_ALLOC_STR)) == 0) {
-+ int alloc_size;
-+ char *p = input_str + strlen(DMA_ALLOC_STR);
-+ while (*p == ' ')
-+ p++;
-+ alloc_size = memparse(p, NULL);
-+
-+ if (vc_cma_dma_alloc) {
-+ dma_release_from_contiguous(NULL, vc_cma_dma_alloc,
-+ vc_cma_dma_size);
-+ vc_cma_dma_alloc = NULL;
-+ vc_cma_dma_size = 0;
-+ }
-+ vc_cma_dma_alloc = dma_alloc_from_contiguous(NULL, alloc_size, 0);
-+ vc_cma_dma_size = (vc_cma_dma_alloc ? alloc_size : 0);
-+ if (vc_cma_dma_alloc)
-+ LOG_INFO("dma_alloc(%d pages) -> %p", alloc_size, page_address(vc_cma_dma_alloc));
-+ else
-+ LOG_ERR("dma_alloc(%d pages) failed", alloc_size);
-+ rc = size;
-+ } else if (strncmp(input_str, DMA_FREE_STR, strlen(DMA_FREE_STR)) == 0) {
-+ if (vc_cma_dma_alloc) {
-+ dma_release_from_contiguous(NULL, vc_cma_dma_alloc,
-+ vc_cma_dma_size);
-+ vc_cma_dma_alloc = NULL;
-+ vc_cma_dma_size = 0;
-+ }
-+ rc = size;
-+ }
-+
-+out:
-+ return rc;
-+}
-+
-+/****************************************************************************
-+*
-+* File Operations for /proc interface.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_cma_proc_fops = {
-+ .open = vc_cma_proc_open,
-+ .read = seq_read,
-+ .write = vc_cma_proc_write,
-+ .llseek = seq_lseek,
-+ .release = single_release
-+};
-+
-+static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid)
-+{
-+ struct vc_cma_reserve_user *user = NULL;
-+ int delta = 0;
-+ int i;
-+
-+ if (down_interruptible(&vc_cma_reserve_mutex))
-+ return -ERESTARTSYS;
-+
-+ for (i = 0; i < vc_cma_reserve_count; i++) {
-+ if (pid == vc_cma_reserve_users[i].pid) {
-+ user = &vc_cma_reserve_users[i];
-+ delta = reserve - user->reserve;
-+ if (reserve)
-+ user->reserve = reserve;
-+ else {
-+ /* Remove this entry by copying downwards */
-+ while ((i + 1) < vc_cma_reserve_count) {
-+ user[0].pid = user[1].pid;
-+ user[0].reserve = user[1].reserve;
-+ user++;
-+ i++;
-+ }
-+ vc_cma_reserve_count--;
-+ user = NULL;
-+ }
-+ break;
-+ }
-+ }
-+
-+ if (reserve && !user) {
-+ if (vc_cma_reserve_count == VC_CMA_RESERVE_COUNT_MAX) {
-+ LOG_ERR("vc-cma: Too many reservations - "
-+ "increase CMA_RESERVE_COUNT_MAX");
-+ up(&vc_cma_reserve_mutex);
-+ return -EBUSY;
-+ }
-+ user = &vc_cma_reserve_users[vc_cma_reserve_count];
-+ user->pid = pid;
-+ user->reserve = reserve;
-+ delta = reserve;
-+ vc_cma_reserve_count++;
-+ }
-+
-+ vc_cma_reserve_total += delta;
-+
-+ send_vc_msg(VC_CMA_MSG_RESERVE,
-+ vc_cma_reserve_total & 0xffff, vc_cma_reserve_total >> 16);
-+
-+ send_worker_msg((VCHIQ_HEADER_T *) VC_CMA_MSG_UPDATE_RESERVE);
-+
-+ LOG_DBG("/proc/vc-cma: reserve %d (PID %d) - total %u",
-+ reserve, pid, vc_cma_reserve_total);
-+
-+ up(&vc_cma_reserve_mutex);
-+
-+ return vc_cma_reserve_total;
-+}
-+
-+static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T * header,
-+ VCHIQ_SERVICE_HANDLE_T service,
-+ void *bulk_userdata)
-+{
-+ switch (reason) {
-+ case VCHIQ_MESSAGE_AVAILABLE:
-+ if (!send_worker_msg(header))
-+ return VCHIQ_RETRY;
-+ break;
-+ case VCHIQ_SERVICE_CLOSED:
-+ LOG_DBG("CMA service closed");
-+ break;
-+ default:
-+ LOG_ERR("Unexpected CMA callback reason %d", reason);
-+ break;
-+ }
-+ return VCHIQ_SUCCESS;
-+}
-+
-+static void send_vc_msg(unsigned short type,
-+ unsigned short param1, unsigned short param2)
-+{
-+ unsigned short msg[] = { type, param1, param2 };
-+ VCHIQ_ELEMENT_T elem = { &msg, sizeof(msg) };
-+ VCHIQ_STATUS_T ret;
-+ vchiq_use_service(cma_service);
-+ ret = vchiq_queue_message(cma_service, &elem, 1);
-+ vchiq_release_service(cma_service);
-+ if (ret != VCHIQ_SUCCESS)
-+ LOG_ERR("vchiq_queue_message returned %x", ret);
-+}
-+
-+static bool send_worker_msg(VCHIQ_HEADER_T * msg)
-+{
-+ if (down_interruptible(&vc_cma_worker_queue_push_mutex))
-+ return false;
-+ vchiu_queue_push(&cma_msg_queue, msg);
-+ up(&vc_cma_worker_queue_push_mutex);
-+ return true;
-+}
-+
-+static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply)
-+{
-+ int i;
-+ for (i = 0; i < num_chunks; i++) {
-+ struct page *chunk;
-+ unsigned int chunk_num;
-+ uint8_t *chunk_addr;
-+ size_t chunk_size = PAGES_PER_CHUNK << PAGE_SHIFT;
-+
-+ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev,
-+ PAGES_PER_CHUNK,
-+ VC_CMA_CHUNK_ORDER);
-+ if (!chunk)
-+ break;
-+
-+ chunk_addr = page_address(chunk);
-+ dmac_flush_range(chunk_addr, chunk_addr + chunk_size);
-+ outer_inv_range(__pa(chunk_addr), __pa(chunk_addr) +
-+ chunk_size);
-+
-+ chunk_num =
-+ (page_to_phys(chunk) - vc_cma_base) / VC_CMA_CHUNK_SIZE;
-+ BUG_ON(((page_to_phys(chunk) - vc_cma_base) %
-+ VC_CMA_CHUNK_SIZE) != 0);
-+ if (chunk_num >= vc_cma_chunks) {
-+ phys_addr_t _pa = vc_cma_base + vc_cma_size - 1;
-+ LOG_ERR("%s: ===============================",
-+ __func__);
-+ LOG_ERR("%s: chunk phys %x, vc_cma %pa-%pa - "
-+ "bad SPARSEMEM configuration?",
-+ __func__, (unsigned int)page_to_phys(chunk),
-+ &vc_cma_base, &_pa);
-+ LOG_ERR("%s: dev->cma_area = %p", __func__,
-+ (void*)0/*vc_cma_device.dev.cma_area*/);
-+ LOG_ERR("%s: ===============================",
-+ __func__);
-+ break;
-+ }
-+ reply->params[i] = chunk_num;
-+ vc_cma_chunks_used++;
-+ }
-+
-+ if (i < num_chunks) {
-+ LOG_ERR("%s: dma_alloc_from_contiguous failed "
-+ "for %x bytes (alloc %d of %d, %d free)",
-+ __func__, VC_CMA_CHUNK_SIZE, i,
-+ num_chunks, vc_cma_chunks - vc_cma_chunks_used);
-+ num_chunks = i;
-+ }
-+
-+ LOG_DBG("CMA allocated %d chunks -> %d used",
-+ num_chunks, vc_cma_chunks_used);
-+ reply->type = VC_CMA_MSG_ALLOCATED;
-+
-+ {
-+ VCHIQ_ELEMENT_T elem = {
-+ reply,
-+ offsetof(struct cma_msg, params[0]) +
-+ num_chunks * sizeof(reply->params[0])
-+ };
-+ VCHIQ_STATUS_T ret;
-+ vchiq_use_service(cma_service);
-+ ret = vchiq_queue_message(cma_service, &elem, 1);
-+ vchiq_release_service(cma_service);
-+ if (ret != VCHIQ_SUCCESS)
-+ LOG_ERR("vchiq_queue_message return " "%x", ret);
-+ }
-+
-+ return num_chunks;
-+}
-+
-+static int cma_worker_proc(void *param)
-+{
-+ static struct cma_msg reply;
-+ (void)param;
-+
-+ while (1) {
-+ VCHIQ_HEADER_T *msg;
-+ static struct cma_msg msg_copy;
-+ struct cma_msg *cma_msg = &msg_copy;
-+ int type, msg_size;
-+
-+ msg = vchiu_queue_pop(&cma_msg_queue);
-+ if ((unsigned int)msg >= VC_CMA_MSG_MAX) {
-+ msg_size = msg->size;
-+ memcpy(&msg_copy, msg->data, msg_size);
-+ type = cma_msg->type;
-+ vchiq_release_message(cma_service, msg);
-+ } else {
-+ msg_size = 0;
-+ type = (int)msg;
-+ if (type == VC_CMA_MSG_QUIT)
-+ break;
-+ else if (type == VC_CMA_MSG_UPDATE_RESERVE) {
-+ msg = NULL;
-+ cma_msg = NULL;
-+ } else {
-+ BUG();
-+ continue;
-+ }
-+ }
-+
-+ switch (type) {
-+ case VC_CMA_MSG_ALLOC:{
-+ int num_chunks, free_chunks;
-+ num_chunks = cma_msg->params[0];
-+ free_chunks =
-+ vc_cma_chunks - vc_cma_chunks_used;
-+ LOG_DBG("CMA_MSG_ALLOC(%d chunks)", num_chunks);
-+ if (num_chunks > VC_CMA_MAX_PARAMS_PER_MSG) {
-+ LOG_ERR
-+ ("CMA_MSG_ALLOC - chunk count (%d) "
-+ "exceeds VC_CMA_MAX_PARAMS_PER_MSG (%d)",
-+ num_chunks,
-+ VC_CMA_MAX_PARAMS_PER_MSG);
-+ num_chunks = VC_CMA_MAX_PARAMS_PER_MSG;
-+ }
-+
-+ if (num_chunks > free_chunks) {
-+ LOG_ERR
-+ ("CMA_MSG_ALLOC - chunk count (%d) "
-+ "exceeds free chunks (%d)",
-+ num_chunks, free_chunks);
-+ num_chunks = free_chunks;
-+ }
-+
-+ vc_cma_alloc_chunks(num_chunks, &reply);
-+ }
-+ break;
-+
-+ case VC_CMA_MSG_FREE:{
-+ int chunk_count =
-+ (msg_size -
-+ offsetof(struct cma_msg,
-+ params)) /
-+ sizeof(cma_msg->params[0]);
-+ int i;
-+ BUG_ON(chunk_count <= 0);
-+
-+ LOG_DBG("CMA_MSG_FREE(%d chunks - %x, ...)",
-+ chunk_count, cma_msg->params[0]);
-+ for (i = 0; i < chunk_count; i++) {
-+ int chunk_num = cma_msg->params[i];
-+ struct page *page = vc_cma_base_page +
-+ chunk_num * PAGES_PER_CHUNK;
-+ if (chunk_num >= vc_cma_chunks) {
-+ LOG_ERR
-+ ("CMA_MSG_FREE - chunk %d of %d"
-+ " (value %x) exceeds maximum "
-+ "(%x)", i, chunk_count,
-+ chunk_num,
-+ vc_cma_chunks - 1);
-+ break;
-+ }
-+
-+ if (!dma_release_from_contiguous
-+ (&vc_cma_device.dev, page,
-+ PAGES_PER_CHUNK)) {
-+ phys_addr_t _pa = page_to_phys(page);
-+ LOG_ERR
-+ ("CMA_MSG_FREE - failed to "
-+ "release chunk %d (phys %pa, "
-+ "page %x)", chunk_num,
-+ &_pa,
-+ (unsigned int)page);
-+ }
-+ vc_cma_chunks_used--;
-+ }
-+ LOG_DBG("CMA released %d chunks -> %d used",
-+ i, vc_cma_chunks_used);
-+ }
-+ break;
-+
-+ case VC_CMA_MSG_UPDATE_RESERVE:{
-+ int chunks_needed =
-+ ((vc_cma_reserve_total + VC_CMA_CHUNK_SIZE -
-+ 1)
-+ / VC_CMA_CHUNK_SIZE) -
-+ vc_cma_chunks_reserved;
-+
-+ LOG_DBG
-+ ("CMA_MSG_UPDATE_RESERVE(%d chunks needed)",
-+ chunks_needed);
-+
-+ /* Cap the reservations to what is available */
-+ if (chunks_needed > 0) {
-+ if (chunks_needed >
-+ (vc_cma_chunks -
-+ vc_cma_chunks_used))
-+ chunks_needed =
-+ (vc_cma_chunks -
-+ vc_cma_chunks_used);
-+
-+ chunks_needed =
-+ vc_cma_alloc_chunks(chunks_needed,
-+ &reply);
-+ }
-+
-+ LOG_DBG
-+ ("CMA_MSG_UPDATE_RESERVE(%d chunks allocated)",
-+ chunks_needed);
-+ vc_cma_chunks_reserved += chunks_needed;
-+ }
-+ break;
-+
-+ default:
-+ LOG_ERR("unexpected msg type %d", type);
-+ break;
-+ }
-+ }
-+
-+ LOG_DBG("quitting...");
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_connected_init
-+*
-+* This function is called once the videocore has been connected.
-+*
-+***************************************************************************/
-+
-+static void vc_cma_connected_init(void)
-+{
-+ VCHIQ_SERVICE_PARAMS_T service_params;
-+
-+ LOG_DBG("vc_cma_connected_init");
-+
-+ if (!vchiu_queue_init(&cma_msg_queue, 16)) {
-+ LOG_ERR("could not create CMA msg queue");
-+ goto fail_queue;
-+ }
-+
-+ if (vchiq_initialise(&cma_instance) != VCHIQ_SUCCESS)
-+ goto fail_vchiq_init;
-+
-+ vchiq_connect(cma_instance);
-+
-+ service_params.fourcc = VC_CMA_FOURCC;
-+ service_params.callback = cma_service_callback;
-+ service_params.userdata = NULL;
-+ service_params.version = VC_CMA_VERSION;
-+ service_params.version_min = VC_CMA_VERSION;
-+
-+ if (vchiq_open_service(cma_instance, &service_params,
-+ &cma_service) != VCHIQ_SUCCESS) {
-+ LOG_ERR("failed to open service - already in use?");
-+ goto fail_vchiq_open;
-+ }
-+
-+ vchiq_release_service(cma_service);
-+
-+ cma_worker = kthread_create(cma_worker_proc, NULL, "cma_worker");
-+ if (!cma_worker) {
-+ LOG_ERR("could not create CMA worker thread");
-+ goto fail_worker;
-+ }
-+ set_user_nice(cma_worker, -20);
-+ wake_up_process(cma_worker);
-+
-+ return;
-+
-+fail_worker:
-+ vchiq_close_service(cma_service);
-+fail_vchiq_open:
-+ vchiq_shutdown(cma_instance);
-+fail_vchiq_init:
-+ vchiu_queue_delete(&cma_msg_queue);
-+fail_queue:
-+ return;
-+}
-+
-+void
-+loud_error_header(void)
-+{
-+ if (in_loud_error)
-+ return;
-+
-+ LOG_ERR("============================================================"
-+ "================");
-+ LOG_ERR("============================================================"
-+ "================");
-+ LOG_ERR("=====");
-+
-+ in_loud_error = 1;
-+}
-+
-+void
-+loud_error_footer(void)
-+{
-+ if (!in_loud_error)
-+ return;
-+
-+ LOG_ERR("=====");
-+ LOG_ERR("============================================================"
-+ "================");
-+ LOG_ERR("============================================================"
-+ "================");
-+
-+ in_loud_error = 0;
-+}
-+
-+#if 1
-+static int check_cma_config(void) { return 1; }
-+#else
-+static int
-+read_vc_debug_var(VC_MEM_ACCESS_HANDLE_T handle,
-+ const char *symbol,
-+ void *buf, size_t bufsize)
-+{
-+ VC_MEM_ADDR_T vcMemAddr;
-+ size_t vcMemSize;
-+ uint8_t *mapAddr;
-+ off_t vcMapAddr;
-+
-+ if (!LookupVideoCoreSymbol(handle, symbol,
-+ &vcMemAddr,
-+ &vcMemSize)) {
-+ loud_error_header();
-+ loud_error(
-+ "failed to find VC symbol \"%s\".",
-+ symbol);
-+ loud_error_footer();
-+ return 0;
-+ }
-+
-+ if (vcMemSize != bufsize) {
-+ loud_error_header();
-+ loud_error(
-+ "VC symbol \"%s\" is the wrong size.",
-+ symbol);
-+ loud_error_footer();
-+ return 0;
-+ }
-+
-+ vcMapAddr = (off_t)vcMemAddr & VC_MEM_TO_ARM_ADDR_MASK;
-+ vcMapAddr += mm_vc_mem_phys_addr;
-+ mapAddr = ioremap_nocache(vcMapAddr, vcMemSize);
-+ if (mapAddr == 0) {
-+ loud_error_header();
-+ loud_error(
-+ "failed to ioremap \"%s\" @ 0x%x "
-+ "(phys: 0x%x, size: %u).",
-+ symbol,
-+ (unsigned int)vcMapAddr,
-+ (unsigned int)vcMemAddr,
-+ (unsigned int)vcMemSize);
-+ loud_error_footer();
-+ return 0;
-+ }
-+
-+ memcpy(buf, mapAddr, bufsize);
-+ iounmap(mapAddr);
-+
-+ return 1;
-+}
-+
-+
-+static int
-+check_cma_config(void)
-+{
-+ VC_MEM_ACCESS_HANDLE_T mem_hndl;
-+ VC_MEM_ADDR_T mempool_start;
-+ VC_MEM_ADDR_T mempool_end;
-+ VC_MEM_ADDR_T mempool_offline_start;
-+ VC_MEM_ADDR_T mempool_offline_end;
-+ VC_MEM_ADDR_T cam_alloc_base;
-+ VC_MEM_ADDR_T cam_alloc_size;
-+ VC_MEM_ADDR_T cam_alloc_end;
-+ int success = 0;
-+
-+ if (OpenVideoCoreMemory(&mem_hndl) != 0)
-+ goto out;
-+
-+ /* Read the relevant VideoCore variables */
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_START",
-+ &mempool_start,
-+ sizeof(mempool_start)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_END",
-+ &mempool_end,
-+ sizeof(mempool_end)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_START",
-+ &mempool_offline_start,
-+ sizeof(mempool_offline_start)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_END",
-+ &mempool_offline_end,
-+ sizeof(mempool_offline_end)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "cam_alloc_base",
-+ &cam_alloc_base,
-+ sizeof(cam_alloc_base)))
-+ goto close;
-+
-+ if (!read_vc_debug_var(mem_hndl, "cam_alloc_size",
-+ &cam_alloc_size,
-+ sizeof(cam_alloc_size)))
-+ goto close;
-+
-+ cam_alloc_end = cam_alloc_base + cam_alloc_size;
-+
-+ success = 1;
-+
-+ /* Now the sanity checks */
-+ if (!mempool_offline_start)
-+ mempool_offline_start = mempool_start;
-+ if (!mempool_offline_end)
-+ mempool_offline_end = mempool_end;
-+
-+ if (VCADDR_TO_PHYSADDR(mempool_offline_start) != vc_cma_base) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_START(%x -> %lx) doesn't match "
-+ "vc_cma_base(%x)",
-+ mempool_offline_start,
-+ VCADDR_TO_PHYSADDR(mempool_offline_start),
-+ vc_cma_base);
-+ success = 0;
-+ }
-+
-+ if (VCADDR_TO_PHYSADDR(mempool_offline_end) !=
-+ (vc_cma_base + vc_cma_size)) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_END(%x -> %lx) doesn't match "
-+ "vc_cma_base(%x) + vc_cma_size(%x) = %x",
-+ mempool_offline_start,
-+ VCADDR_TO_PHYSADDR(mempool_offline_end),
-+ vc_cma_base, vc_cma_size, vc_cma_base + vc_cma_size);
-+ success = 0;
-+ }
-+
-+ if (mempool_end < mempool_start) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_END(%x) must not be before "
-+ "__MEMPOOL_START(%x)",
-+ mempool_end,
-+ mempool_start);
-+ success = 0;
-+ }
-+
-+ if (mempool_offline_end < mempool_offline_start) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_END(%x) must not be before "
-+ "__MEMPOOL_OFFLINE_START(%x)",
-+ mempool_offline_end,
-+ mempool_offline_start);
-+ success = 0;
-+ }
-+
-+ if (mempool_offline_start < mempool_start) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_START(%x) must not be before "
-+ "__MEMPOOL_START(%x)",
-+ mempool_offline_start,
-+ mempool_start);
-+ success = 0;
-+ }
-+
-+ if (mempool_offline_end > mempool_end) {
-+ loud_error_header();
-+ loud_error(
-+ "__MEMPOOL_OFFLINE_END(%x) must not be after "
-+ "__MEMPOOL_END(%x)",
-+ mempool_offline_end,
-+ mempool_end);
-+ success = 0;
-+ }
-+
-+ if ((cam_alloc_base < mempool_end) &&
-+ (cam_alloc_end > mempool_start)) {
-+ loud_error_header();
-+ loud_error(
-+ "cam_alloc pool(%x-%x) overlaps "
-+ "mempool(%x-%x)",
-+ cam_alloc_base, cam_alloc_end,
-+ mempool_start, mempool_end);
-+ success = 0;
-+ }
-+
-+ loud_error_footer();
-+
-+close:
-+ CloseVideoCoreMemory(mem_hndl);
-+
-+out:
-+ return success;
-+}
-+#endif
-+
-+static int vc_cma_init(void)
-+{
-+ int rc = -EFAULT;
-+ struct device *dev;
-+
-+ if (!check_cma_config())
-+ goto out_release;
-+
-+ LOG_INFO("vc-cma: Videocore CMA driver");
-+ LOG_INFO("vc-cma: vc_cma_base = %pa", &vc_cma_base);
-+ LOG_INFO("vc-cma: vc_cma_size = 0x%08x (%u MiB)",
-+ vc_cma_size, vc_cma_size / (1024 * 1024));
-+ LOG_INFO("vc-cma: vc_cma_initial = 0x%08x (%u MiB)",
-+ vc_cma_initial, vc_cma_initial / (1024 * 1024));
-+
-+ vc_cma_base_page = phys_to_page(vc_cma_base);
-+
-+ if (vc_cma_chunks) {
-+ int chunks_needed = vc_cma_initial / VC_CMA_CHUNK_SIZE;
-+
-+ for (vc_cma_chunks_used = 0;
-+ vc_cma_chunks_used < chunks_needed; vc_cma_chunks_used++) {
-+ struct page *chunk;
-+ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev,
-+ PAGES_PER_CHUNK,
-+ VC_CMA_CHUNK_ORDER);
-+ if (!chunk)
-+ break;
-+ BUG_ON(((page_to_phys(chunk) - vc_cma_base) %
-+ VC_CMA_CHUNK_SIZE) != 0);
-+ }
-+ if (vc_cma_chunks_used != chunks_needed) {
-+ LOG_ERR("%s: dma_alloc_from_contiguous failed (%d "
-+ "bytes, allocation %d of %d)",
-+ __func__, VC_CMA_CHUNK_SIZE,
-+ vc_cma_chunks_used, chunks_needed);
-+ goto out_release;
-+ }
-+
-+ vchiq_add_connected_callback(vc_cma_connected_init);
-+ }
-+
-+ rc = alloc_chrdev_region(&vc_cma_devnum, 0, 1, DRIVER_NAME);
-+ if (rc < 0) {
-+ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
-+ goto out_release;
-+ }
-+
-+ cdev_init(&vc_cma_cdev, &vc_cma_fops);
-+ rc = cdev_add(&vc_cma_cdev, vc_cma_devnum, 1);
-+ if (rc != 0) {
-+ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
-+ goto out_unregister;
-+ }
-+
-+ vc_cma_class = class_create(THIS_MODULE, DRIVER_NAME);
-+ if (IS_ERR(vc_cma_class)) {
-+ rc = PTR_ERR(vc_cma_class);
-+ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
-+ goto out_cdev_del;
-+ }
-+
-+ dev = device_create(vc_cma_class, NULL, vc_cma_devnum, NULL,
-+ DRIVER_NAME);
-+ if (IS_ERR(dev)) {
-+ rc = PTR_ERR(dev);
-+ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
-+ goto out_class_destroy;
-+ }
-+
-+ vc_cma_proc_entry = proc_create(DRIVER_NAME, 0444, NULL, &vc_cma_proc_fops);
-+ if (vc_cma_proc_entry == NULL) {
-+ rc = -EFAULT;
-+ LOG_ERR("%s: proc_create failed", __func__);
-+ goto out_device_destroy;
-+ }
-+
-+ vc_cma_inited = 1;
-+ return 0;
-+
-+out_device_destroy:
-+ device_destroy(vc_cma_class, vc_cma_devnum);
-+
-+out_class_destroy:
-+ class_destroy(vc_cma_class);
-+ vc_cma_class = NULL;
-+
-+out_cdev_del:
-+ cdev_del(&vc_cma_cdev);
-+
-+out_unregister:
-+ unregister_chrdev_region(vc_cma_devnum, 1);
-+
-+out_release:
-+ /* It is tempting to try to clean up by calling
-+ dma_release_from_contiguous for all allocated chunks, but it isn't
-+ a very safe thing to do. If vc_cma_initial is non-zero it is because
-+ VideoCore is already using that memory, so giving it back to Linux
-+ is likely to be fatal.
-+ */
-+ return -1;
-+}
-+
-+/****************************************************************************
-+*
-+* vc_cma_exit
-+*
-+***************************************************************************/
-+
-+static void __exit vc_cma_exit(void)
-+{
-+ LOG_DBG("%s: called", __func__);
-+
-+ if (vc_cma_inited) {
-+ remove_proc_entry(DRIVER_NAME, NULL);
-+ device_destroy(vc_cma_class, vc_cma_devnum);
-+ class_destroy(vc_cma_class);
-+ cdev_del(&vc_cma_cdev);
-+ unregister_chrdev_region(vc_cma_devnum, 1);
-+ }
-+}
-+
-+module_init(vc_cma_init);
-+module_exit(vc_cma_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-diff -Nur linux-3.18.14/drivers/char/broadcom/vc_sm/Makefile linux-rpi/drivers/char/broadcom/vc_sm/Makefile
---- linux-3.18.14/drivers/char/broadcom/vc_sm/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/vc_sm/Makefile 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,21 @@
-+EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2
-+
-+EXTRA_CFLAGS += -I"./arch/arm/mach-bcm2708/include/mach"
-+EXTRA_CFLAGS += -I"drivers/misc/vc04_services"
-+EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchi"
-+EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm"
-+EXTRA_CFLAGS += -I"$(srctree)/fs/"
-+
-+EXTRA_CFLAGS += -DOS_ASSERT_FAILURE
-+EXTRA_CFLAGS += -D__STDC_VERSION=199901L
-+EXTRA_CFLAGS += -D__STDC_VERSION__=199901L
-+EXTRA_CFLAGS += -D__VCCOREVER__=0
-+EXTRA_CFLAGS += -D__KERNEL__
-+EXTRA_CFLAGS += -D__linux__
-+EXTRA_CFLAGS += -Werror
-+
-+obj-$(CONFIG_BCM_VC_SM) := vc-sm.o
-+
-+vc-sm-objs := \
-+ vmcs_sm.o \
-+ vc_vchi_sm.o
-diff -Nur linux-3.18.14/drivers/char/broadcom/vc_sm/vc_vchi_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c
---- linux-3.18.14/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,492 @@
-+/*****************************************************************************
-+* Copyright 2011-2012 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/semaphore.h>
-+#include <linux/mutex.h>
-+#include <linux/slab.h>
-+#include <linux/kthread.h>
-+
-+#include "vc_vchi_sm.h"
-+
-+#define VC_SM_VER 1
-+#define VC_SM_MIN_VER 0
-+
-+/* ---- Private Constants and Types -------------------------------------- */
-+
-+/* Command blocks come from a pool */
-+#define SM_MAX_NUM_CMD_RSP_BLKS 32
-+
-+struct sm_cmd_rsp_blk {
-+ struct list_head head; /* To create lists */
-+ struct semaphore sema; /* To be signaled when the response is there */
-+
-+ uint16_t id;
-+ uint16_t length;
-+
-+ uint8_t msg[VC_SM_MAX_MSG_LEN];
-+
-+ uint32_t wait:1;
-+ uint32_t sent:1;
-+ uint32_t alloc:1;
-+
-+};
-+
-+struct sm_instance {
-+ uint32_t num_connections;
-+ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
-+ struct task_struct *io_thread;
-+ struct semaphore io_sema;
-+
-+ uint32_t trans_id;
-+
-+ struct mutex lock;
-+ struct list_head cmd_list;
-+ struct list_head rsp_list;
-+ struct list_head dead_list;
-+
-+ struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS];
-+ struct list_head free_list;
-+ struct mutex free_lock;
-+ struct semaphore free_sema;
-+
-+};
-+
-+/* ---- Private Variables ------------------------------------------------ */
-+
-+/* ---- Private Function Prototypes -------------------------------------- */
-+
-+/* ---- Private Functions ------------------------------------------------ */
-+static struct
-+sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance,
-+ VC_SM_MSG_TYPE id, void *msg,
-+ uint32_t size, int wait)
-+{
-+ struct sm_cmd_rsp_blk *blk;
-+ VC_SM_MSG_HDR_T *hdr;
-+
-+ if (down_interruptible(&instance->free_sema)) {
-+ blk = kmalloc(sizeof(*blk), GFP_KERNEL);
-+ if (!blk)
-+ return NULL;
-+
-+ blk->alloc = 1;
-+ sema_init(&blk->sema, 0);
-+ } else {
-+ mutex_lock(&instance->free_lock);
-+ blk =
-+ list_first_entry(&instance->free_list,
-+ struct sm_cmd_rsp_blk, head);
-+ list_del(&blk->head);
-+ mutex_unlock(&instance->free_lock);
-+ }
-+
-+ blk->sent = 0;
-+ blk->wait = wait;
-+ blk->length = sizeof(*hdr) + size;
-+
-+ hdr = (VC_SM_MSG_HDR_T *) blk->msg;
-+ hdr->type = id;
-+ mutex_lock(&instance->lock);
-+ hdr->trans_id = blk->id = ++instance->trans_id;
-+ mutex_unlock(&instance->lock);
-+
-+ if (size)
-+ memcpy(hdr->body, msg, size);
-+
-+ return blk;
-+}
-+
-+static void
-+vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk)
-+{
-+ if (blk->alloc) {
-+ kfree(blk);
-+ return;
-+ }
-+
-+ mutex_lock(&instance->free_lock);
-+ list_add(&blk->head, &instance->free_list);
-+ mutex_unlock(&instance->free_lock);
-+ up(&instance->free_sema);
-+}
-+
-+static int vc_vchi_sm_videocore_io(void *arg)
-+{
-+ struct sm_instance *instance = arg;
-+ struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp;
-+ VC_SM_RESULT_T *reply;
-+ uint32_t reply_len;
-+ int32_t status;
-+ int svc_use = 1;
-+
-+ while (1) {
-+ if (svc_use)
-+ vchi_service_release(instance->vchi_handle[0]);
-+ svc_use = 0;
-+ if (!down_interruptible(&instance->io_sema)) {
-+ vchi_service_use(instance->vchi_handle[0]);
-+ svc_use = 1;
-+
-+ do {
-+ unsigned int flags;
-+ /*
-+ * Get new command and move it to response list
-+ */
-+ mutex_lock(&instance->lock);
-+ if (list_empty(&instance->cmd_list)) {
-+ /* no more commands to process */
-+ mutex_unlock(&instance->lock);
-+ break;
-+ }
-+ cmd =
-+ list_first_entry(&instance->cmd_list,
-+ struct sm_cmd_rsp_blk,
-+ head);
-+ list_move(&cmd->head, &instance->rsp_list);
-+ cmd->sent = 1;
-+ mutex_unlock(&instance->lock);
-+
-+ /* Send the command */
-+ flags = VCHI_FLAGS_BLOCK_UNTIL_QUEUED;
-+ status = vchi_msg_queue(
-+ instance->vchi_handle[0],
-+ cmd->msg, cmd->length,
-+ flags, NULL);
-+ if (status) {
-+ pr_err("%s: failed to queue message (%d)",
-+ __func__, status);
-+ }
-+
-+ /* If no reply is needed then we're done */
-+ if (!cmd->wait) {
-+ mutex_lock(&instance->lock);
-+ list_del(&cmd->head);
-+ mutex_unlock(&instance->lock);
-+ vc_vchi_cmd_delete(instance, cmd);
-+ continue;
-+ }
-+
-+ if (status) {
-+ up(&cmd->sema);
-+ continue;
-+ }
-+
-+ } while (1);
-+
-+ while (!vchi_msg_peek
-+ (instance->vchi_handle[0], (void **)&reply,
-+ &reply_len, VCHI_FLAGS_NONE)) {
-+ mutex_lock(&instance->lock);
-+ list_for_each_entry(cmd, &instance->rsp_list,
-+ head) {
-+ if (cmd->id == reply->trans_id)
-+ break;
-+ }
-+ mutex_unlock(&instance->lock);
-+
-+ if (&cmd->head == &instance->rsp_list) {
-+ pr_debug("%s: received response %u, throw away...",
-+ __func__, reply->trans_id);
-+ } else if (reply_len > sizeof(cmd->msg)) {
-+ pr_err("%s: reply too big (%u) %u, throw away...",
-+ __func__, reply_len,
-+ reply->trans_id);
-+ } else {
-+ memcpy(cmd->msg, reply, reply_len);
-+ up(&cmd->sema);
-+ }
-+
-+ vchi_msg_remove(instance->vchi_handle[0]);
-+ }
-+
-+ /* Go through the dead list and free them */
-+ mutex_lock(&instance->lock);
-+ list_for_each_entry_safe(cmd, cmd_tmp,
-+ &instance->dead_list, head) {
-+ list_del(&cmd->head);
-+ vc_vchi_cmd_delete(instance, cmd);
-+ }
-+ mutex_unlock(&instance->lock);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void vc_sm_vchi_callback(void *param,
-+ const VCHI_CALLBACK_REASON_T reason,
-+ void *msg_handle)
-+{
-+ struct sm_instance *instance = param;
-+
-+ (void)msg_handle;
-+
-+ switch (reason) {
-+ case VCHI_CALLBACK_MSG_AVAILABLE:
-+ up(&instance->io_sema);
-+ break;
-+
-+ case VCHI_CALLBACK_SERVICE_CLOSED:
-+ pr_info("%s: service CLOSED!!", __func__);
-+ default:
-+ break;
-+ }
-+}
-+
-+VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
-+ VCHI_CONNECTION_T **vchi_connections,
-+ uint32_t num_connections)
-+{
-+ uint32_t i;
-+ struct sm_instance *instance;
-+ int status;
-+
-+ pr_debug("%s: start", __func__);
-+
-+ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
-+ pr_err("%s: unsupported number of connections %u (max=%u)",
-+ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
-+
-+ goto err_null;
-+ }
-+ /* Allocate memory for this instance */
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+
-+ /* Misc initialisations */
-+ mutex_init(&instance->lock);
-+ sema_init(&instance->io_sema, 0);
-+ INIT_LIST_HEAD(&instance->cmd_list);
-+ INIT_LIST_HEAD(&instance->rsp_list);
-+ INIT_LIST_HEAD(&instance->dead_list);
-+ INIT_LIST_HEAD(&instance->free_list);
-+ sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS);
-+ mutex_init(&instance->free_lock);
-+ for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) {
-+ sema_init(&instance->free_blk[i].sema, 0);
-+ list_add(&instance->free_blk[i].head, &instance->free_list);
-+ }
-+
-+ /* Open the VCHI service connections */
-+ instance->num_connections = num_connections;
-+ for (i = 0; i < num_connections; i++) {
-+ SERVICE_CREATION_T params = {
-+ VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER),
-+ VC_SM_SERVER_NAME,
-+ vchi_connections[i],
-+ 0,
-+ 0,
-+ vc_sm_vchi_callback,
-+ instance,
-+ 0,
-+ 0,
-+ 0,
-+ };
-+
-+ status = vchi_service_open(vchi_instance,
-+ &params, &instance->vchi_handle[i]);
-+ if (status) {
-+ pr_err("%s: failed to open VCHI service (%d)",
-+ __func__, status);
-+
-+ goto err_close_services;
-+ }
-+ }
-+
-+ /* Create the thread which takes care of all io to/from videoocore. */
-+ instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io,
-+ (void *)instance, "SMIO");
-+ if (instance->io_thread == NULL) {
-+ pr_err("%s: failed to create SMIO thread", __func__);
-+
-+ goto err_close_services;
-+ }
-+ set_user_nice(instance->io_thread, -10);
-+ wake_up_process(instance->io_thread);
-+
-+ pr_debug("%s: success - instance 0x%x", __func__, (unsigned)instance);
-+ return instance;
-+
-+err_close_services:
-+ for (i = 0; i < instance->num_connections; i++) {
-+ if (instance->vchi_handle[i] != NULL)
-+ vchi_service_close(instance->vchi_handle[i]);
-+ }
-+ kfree(instance);
-+err_null:
-+ pr_debug("%s: FAILED", __func__);
-+ return NULL;
-+}
-+
-+int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle)
-+{
-+ struct sm_instance *instance;
-+ uint32_t i;
-+
-+ if (handle == NULL) {
-+ pr_err("%s: invalid pointer to handle %p", __func__, handle);
-+ goto lock;
-+ }
-+
-+ if (*handle == NULL) {
-+ pr_err("%s: invalid handle %p", __func__, *handle);
-+ goto lock;
-+ }
-+
-+ instance = *handle;
-+
-+ /* Close all VCHI service connections */
-+ for (i = 0; i < instance->num_connections; i++) {
-+ int32_t success;
-+ vchi_service_use(instance->vchi_handle[i]);
-+
-+ success = vchi_service_close(instance->vchi_handle[i]);
-+ }
-+
-+ kfree(instance);
-+
-+ *handle = NULL;
-+ return 0;
-+
-+lock:
-+ return -EINVAL;
-+}
-+
-+int vc_vchi_sm_send_msg(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_MSG_TYPE msg_id,
-+ void *msg, uint32_t msg_size,
-+ void *result, uint32_t result_size,
-+ uint32_t *cur_trans_id, uint8_t wait_reply)
-+{
-+ int status = 0;
-+ struct sm_instance *instance = handle;
-+ struct sm_cmd_rsp_blk *cmd_blk;
-+
-+ if (handle == NULL) {
-+ pr_err("%s: invalid handle", __func__);
-+ return -EINVAL;
-+ }
-+ if (msg == NULL) {
-+ pr_err("%s: invalid msg pointer", __func__);
-+ return -EINVAL;
-+ }
-+
-+ cmd_blk =
-+ vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply);
-+ if (cmd_blk == NULL) {
-+ pr_err("[%s]: failed to allocate global tracking resource",
-+ __func__);
-+ return -ENOMEM;
-+ }
-+
-+ if (cur_trans_id != NULL)
-+ *cur_trans_id = cmd_blk->id;
-+
-+ mutex_lock(&instance->lock);
-+ list_add_tail(&cmd_blk->head, &instance->cmd_list);
-+ mutex_unlock(&instance->lock);
-+ up(&instance->io_sema);
-+
-+ if (!wait_reply)
-+ /* We're done */
-+ return 0;
-+
-+ /* Wait for the response */
-+ if (down_interruptible(&cmd_blk->sema)) {
-+ mutex_lock(&instance->lock);
-+ if (!cmd_blk->sent) {
-+ list_del(&cmd_blk->head);
-+ mutex_unlock(&instance->lock);
-+ vc_vchi_cmd_delete(instance, cmd_blk);
-+ return -ENXIO;
-+ }
-+ mutex_unlock(&instance->lock);
-+
-+ mutex_lock(&instance->lock);
-+ list_move(&cmd_blk->head, &instance->dead_list);
-+ mutex_unlock(&instance->lock);
-+ up(&instance->io_sema);
-+ return -EINTR; /* We're done */
-+ }
-+
-+ if (result && result_size) {
-+ memcpy(result, cmd_blk->msg, result_size);
-+ } else {
-+ VC_SM_RESULT_T *res = (VC_SM_RESULT_T *) cmd_blk->msg;
-+ status = (res->success == 0) ? 0 : -ENXIO;
-+ }
-+
-+ mutex_lock(&instance->lock);
-+ list_del(&cmd_blk->head);
-+ mutex_unlock(&instance->lock);
-+ vc_vchi_cmd_delete(instance, cmd_blk);
-+ return status;
-+}
-+
-+int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, VC_SM_ALLOC_T *msg,
-+ VC_SM_ALLOC_RESULT_T *result, uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC,
-+ msg, sizeof(*msg), result, sizeof(*result),
-+ cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_FREE_T *msg, uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE,
-+ msg, sizeof(*msg), 0, 0, cur_trans_id, 0);
-+}
-+
-+int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *msg,
-+ VC_SM_LOCK_RESULT_T *result, uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK,
-+ msg, sizeof(*msg), result, sizeof(*result),
-+ cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle,
-+ VC_SM_LOCK_UNLOCK_T *msg,
-+ uint32_t *cur_trans_id, uint8_t wait_reply)
-+{
-+ return vc_vchi_sm_send_msg(handle, wait_reply ?
-+ VC_SM_MSG_TYPE_UNLOCK :
-+ VC_SM_MSG_TYPE_UNLOCK_NOANS, msg,
-+ sizeof(*msg), 0, 0, cur_trans_id,
-+ wait_reply);
-+}
-+
-+int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, VC_SM_RESIZE_T *msg,
-+ uint32_t *cur_trans_id)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE,
-+ msg, sizeof(*msg), 0, 0, cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC,
-+ 0, 0, 0, 0, 0, 0);
-+}
-+
-+int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, VC_SM_ACTION_CLEAN_T *msg)
-+{
-+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN,
-+ msg, sizeof(*msg), 0, 0, 0, 0);
-+}
-diff -Nur linux-3.18.14/drivers/char/broadcom/vc_sm/vmcs_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c
---- linux-3.18.14/drivers/char/broadcom/vc_sm/vmcs_sm.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c 2015-05-31 14:46:10.057660987 -0500
-@@ -0,0 +1,3212 @@
-+/*****************************************************************************
-+* Copyright 2011-2012 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+#include <linux/cdev.h>
-+#include <linux/device.h>
-+#include <linux/debugfs.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/errno.h>
-+#include <linux/fs.h>
-+#include <linux/hugetlb.h>
-+#include <linux/ioctl.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/mm.h>
-+#include <linux/pfn.h>
-+#include <linux/proc_fs.h>
-+#include <linux/pagemap.h>
-+#include <linux/semaphore.h>
-+#include <linux/slab.h>
-+#include <linux/seq_file.h>
-+#include <linux/types.h>
-+#include <asm/cacheflush.h>
-+
-+#include <vc_mem.h>
-+
-+#include "vchiq_connected.h"
-+#include "vc_vchi_sm.h"
-+
-+#include <vmcs_sm_ioctl.h>
-+#include "vc_sm_knl.h"
-+
-+/* ---- Private Constants and Types --------------------------------------- */
-+
-+#define DEVICE_NAME "vcsm"
-+#define DEVICE_MINOR 0
-+
-+#define VC_SM_DIR_ROOT_NAME "vc-smem"
-+#define VC_SM_DIR_ALLOC_NAME "alloc"
-+#define VC_SM_STATE "state"
-+#define VC_SM_STATS "statistics"
-+#define VC_SM_RESOURCES "resources"
-+#define VC_SM_DEBUG "debug"
-+#define VC_SM_WRITE_BUF_SIZE 128
-+
-+/* Statistics tracked per resource and globally.
-+*/
-+enum SM_STATS_T {
-+ /* Attempt. */
-+ ALLOC,
-+ FREE,
-+ LOCK,
-+ UNLOCK,
-+ MAP,
-+ FLUSH,
-+ INVALID,
-+
-+ END_ATTEMPT,
-+
-+ /* Failure. */
-+ ALLOC_FAIL,
-+ FREE_FAIL,
-+ LOCK_FAIL,
-+ UNLOCK_FAIL,
-+ MAP_FAIL,
-+ FLUSH_FAIL,
-+ INVALID_FAIL,
-+
-+ END_ALL,
-+
-+};
-+
-+static const char *const sm_stats_human_read[] = {
-+ "Alloc",
-+ "Free",
-+ "Lock",
-+ "Unlock",
-+ "Map",
-+ "Cache Flush",
-+ "Cache Invalidate",
-+};
-+
-+typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v);
-+struct SM_PDE_T {
-+ VC_SM_SHOW show; /* Debug fs function hookup. */
-+ struct dentry *dir_entry; /* Debug fs directory entry. */
-+ void *priv_data; /* Private data */
-+
-+};
-+
-+/* Single resource allocation tracked for all devices.
-+*/
-+struct sm_mmap {
-+ struct list_head map_list; /* Linked list of maps. */
-+
-+ struct SM_RESOURCE_T *resource; /* Pointer to the resource. */
-+
-+ pid_t res_pid; /* PID owning that resource. */
-+ unsigned int res_vc_hdl; /* Resource handle (videocore). */
-+ unsigned int res_usr_hdl; /* Resource handle (user). */
-+
-+ long unsigned int res_addr; /* Mapped virtual address. */
-+ struct vm_area_struct *vma; /* VM area for this mapping. */
-+ unsigned int ref_count; /* Reference count to this vma. */
-+
-+ /* Used to link maps associated with a resource. */
-+ struct list_head resource_map_list;
-+};
-+
-+/* Single resource allocation tracked for each opened device.
-+*/
-+struct SM_RESOURCE_T {
-+ struct list_head resource_list; /* List of resources. */
-+ struct list_head global_resource_list; /* Global list of resources. */
-+
-+ pid_t pid; /* PID owning that resource. */
-+ uint32_t res_guid; /* Unique identifier. */
-+ uint32_t lock_count; /* Lock count for this resource. */
-+ uint32_t ref_count; /* Ref count for this resource. */
-+
-+ uint32_t res_handle; /* Resource allocation handle. */
-+ void *res_base_mem; /* Resource base memory address. */
-+ uint32_t res_size; /* Resource size allocated. */
-+ enum vmcs_sm_cache_e res_cached; /* Resource cache type. */
-+ struct SM_RESOURCE_T *res_shared; /* Shared resource */
-+
-+ enum SM_STATS_T res_stats[END_ALL]; /* Resource statistics. */
-+
-+ uint8_t map_count; /* Counter of mappings for this resource. */
-+ struct list_head map_list; /* Maps associated with a resource. */
-+
-+ struct SM_PRIV_DATA_T *private;
-+};
-+
-+/* Private file data associated with each opened device.
-+*/
-+struct SM_PRIV_DATA_T {
-+ struct list_head resource_list; /* List of resources. */
-+
-+ pid_t pid; /* PID of creator. */
-+
-+ struct dentry *dir_pid; /* Debug fs entries root. */
-+ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */
-+ struct SM_PDE_T dir_res; /* Debug fs resource sub-tree. */
-+
-+ int restart_sys; /* Tracks restart on interrupt. */
-+ VC_SM_MSG_TYPE int_action; /* Interrupted action. */
-+ uint32_t int_trans_id; /* Interrupted transaction. */
-+
-+};
-+
-+/* Global state information.
-+*/
-+struct SM_STATE_T {
-+ VC_VCHI_SM_HANDLE_T sm_handle; /* Handle for videocore service. */
-+ struct dentry *dir_root; /* Debug fs entries root. */
-+ struct dentry *dir_alloc; /* Debug fs entries allocations. */
-+ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */
-+ struct SM_PDE_T dir_state; /* Debug fs entries state sub-tree. */
-+ struct dentry *debug; /* Debug fs entries debug. */
-+
-+ struct mutex map_lock; /* Global map lock. */
-+ struct list_head map_list; /* List of maps. */
-+ struct list_head resource_list; /* List of resources. */
-+
-+ enum SM_STATS_T deceased[END_ALL]; /* Natural termination stats. */
-+ enum SM_STATS_T terminated[END_ALL]; /* Forced termination stats. */
-+ uint32_t res_deceased_cnt; /* Natural termination counter. */
-+ uint32_t res_terminated_cnt; /* Forced termination counter. */
-+
-+ struct cdev sm_cdev; /* Device. */
-+ dev_t sm_devid; /* Device identifier. */
-+ struct class *sm_class; /* Class. */
-+ struct device *sm_dev; /* Device. */
-+
-+ struct SM_PRIV_DATA_T *data_knl; /* Kernel internal data tracking. */
-+
-+ struct mutex lock; /* Global lock. */
-+ uint32_t guid; /* GUID (next) tracker. */
-+
-+};
-+
-+/* ---- Private Variables ----------------------------------------------- */
-+
-+static struct SM_STATE_T *sm_state;
-+static int sm_inited;
-+
-+static const char *const sm_cache_map_vector[] = {
-+ "(null)",
-+ "host",
-+ "videocore",
-+ "host+videocore",
-+};
-+
-+/* ---- Private Function Prototypes -------------------------------------- */
-+
-+/* ---- Private Functions ------------------------------------------------ */
-+
-+static inline unsigned vcaddr_to_pfn(unsigned long vc_addr)
-+{
-+ unsigned long pfn = vc_addr & 0x3FFFFFFF;
-+ pfn += mm_vc_mem_phys_addr;
-+ pfn >>= PAGE_SHIFT;
-+ return pfn;
-+}
-+
-+/* Carries over to the state statistics the statistics once owned by a deceased
-+** resource.
-+*/
-+static void vc_sm_resource_deceased(struct SM_RESOURCE_T *p_res, int terminated)
-+{
-+ if (sm_state != NULL) {
-+ if (p_res != NULL) {
-+ int ix;
-+
-+ if (terminated)
-+ sm_state->res_terminated_cnt++;
-+ else
-+ sm_state->res_deceased_cnt++;
-+
-+ for (ix = 0; ix < END_ALL; ix++) {
-+ if (terminated)
-+ sm_state->terminated[ix] +=
-+ p_res->res_stats[ix];
-+ else
-+ sm_state->deceased[ix] +=
-+ p_res->res_stats[ix];
-+ }
-+ }
-+ }
-+}
-+
-+/* Fetch a videocore handle corresponding to a mapping of the pid+address
-+** returns 0 (ie NULL) if no such handle exists in the global map.
-+*/
-+static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid,
-+ unsigned int addr)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int handle = 0;
-+
-+ if (!sm_state || addr == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_addr != addr)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n",
-+ __func__, map, map->res_pid, map->res_addr,
-+ map->res_vc_hdl, map->res_usr_hdl);
-+
-+ handle = map->res_vc_hdl;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ ** for something that is not mapped, we do not want a kernel log each
-+ ** time around.
-+ **
-+ ** There are other error log that would pop up accordingly if someone
-+ ** subsequently tries to use something invalid after being told not to
-+ ** use it...
-+ */
-+ if (handle == 0) {
-+ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
-+ __func__, pid, addr);
-+ }
-+
-+ return handle;
-+}
-+
-+/* Fetch a user handle corresponding to a mapping of the pid+address
-+** returns 0 (ie NULL) if no such handle exists in the global map.
-+*/
-+static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid,
-+ unsigned int addr)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int handle = 0;
-+
-+ if (!sm_state || addr == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_addr != addr)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n",
-+ __func__, map, map->res_pid, map->res_addr,
-+ map->res_usr_hdl, map->res_vc_hdl);
-+
-+ handle = map->res_usr_hdl;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ * for something that is not mapped yet.
-+ *
-+ * There are other error log that would pop up accordingly if someone
-+ * subsequently tries to use something invalid after being told not to
-+ * use it...
-+ */
-+ if (handle == 0)
-+ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
-+ __func__, pid, addr);
-+
-+ return handle;
-+}
-+
-+#if defined(DO_NOT_USE)
-+/* Fetch an address corresponding to a mapping of the pid+handle
-+** returns 0 (ie NULL) if no such address exists in the global map.
-+*/
-+static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid,
-+ unsigned int hdl)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int addr = 0;
-+
-+ if (sm_state == NULL || hdl == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_vc_hdl != hdl)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+
-+ addr = map->res_addr;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ ** for something that is not mapped, we do not want a kernel log each
-+ ** time around.
-+ **
-+ ** There are other error log that would pop up accordingly if someone
-+ ** subsequently tries to use something invalid after being told not to
-+ ** use it...
-+ */
-+ if (addr == 0)
-+ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n",
-+ __func__, pid, hdl);
-+
-+ return addr;
-+}
-+#endif
-+
-+/* Fetch an address corresponding to a mapping of the pid+handle
-+** returns 0 (ie NULL) if no such address exists in the global map.
-+*/
-+static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int
-+ pid,
-+ unsigned int
-+ hdl)
-+{
-+ struct sm_mmap *map = NULL;
-+ unsigned int addr = 0;
-+
-+ if (sm_state == NULL || hdl == 0)
-+ goto out;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Lookup the resource.
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (map->res_pid != pid || map->res_usr_hdl != hdl)
-+ continue;
-+
-+ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+
-+ addr = map->res_addr;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+ /* Use a debug log here as it may be a valid situation that we query
-+ * for something that is not mapped, we do not want a kernel log each
-+ * time around.
-+ *
-+ * There are other error log that would pop up accordingly if someone
-+ * subsequently tries to use something invalid after being told not to
-+ * use it...
-+ */
-+ if (addr == 0)
-+ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__,
-+ pid, hdl);
-+
-+ return addr;
-+}
-+
-+/* Adds a resource mapping to the global data list.
-+*/
-+static void vmcs_sm_add_map(struct SM_STATE_T *state,
-+ struct SM_RESOURCE_T *resource, struct sm_mmap *map)
-+{
-+ mutex_lock(&(state->map_lock));
-+
-+ /* Add to the global list of mappings
-+ */
-+ list_add(&map->map_list, &state->map_list);
-+
-+ /* Add to the list of mappings for this resource
-+ */
-+ list_add(&map->resource_map_list, &resource->map_list);
-+ resource->map_count++;
-+
-+ mutex_unlock(&(state->map_lock));
-+
-+ pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+}
-+
-+/* Removes a resource mapping from the global data list.
-+*/
-+static void vmcs_sm_remove_map(struct SM_STATE_T *state,
-+ struct SM_RESOURCE_T *resource,
-+ struct sm_mmap *map)
-+{
-+ mutex_lock(&(state->map_lock));
-+
-+ /* Remove from the global list of mappings
-+ */
-+ list_del(&map->map_list);
-+
-+ /* Remove from the list of mapping for this resource
-+ */
-+ list_del(&map->resource_map_list);
-+ if (resource->map_count > 0)
-+ resource->map_count--;
-+
-+ mutex_unlock(&(state->map_lock));
-+
-+ pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n",
-+ __func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl,
-+ map->res_addr);
-+
-+ kfree(map);
-+}
-+
-+/* Read callback for the global state proc entry.
-+*/
-+static int vc_sm_global_state_show(struct seq_file *s, void *v)
-+{
-+ struct sm_mmap *map = NULL;
-+ int map_count = 0;
-+
-+ if (sm_state == NULL)
-+ return 0;
-+
-+ seq_printf(s, "\nVC-ServiceHandle 0x%x\n",
-+ (unsigned int)sm_state->sm_handle);
-+
-+ /* Log all applicable mapping(s).
-+ */
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ map_count++;
-+
-+ seq_printf(s, "\nMapping 0x%x\n",
-+ (unsigned int)map);
-+ seq_printf(s, " TGID %u\n",
-+ map->res_pid);
-+ seq_printf(s, " VC-HDL 0x%x\n",
-+ map->res_vc_hdl);
-+ seq_printf(s, " USR-HDL 0x%x\n",
-+ map->res_usr_hdl);
-+ seq_printf(s, " USR-ADDR 0x%lx\n",
-+ map->res_addr);
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+ seq_printf(s, "\n\nTotal map count: %d\n\n", map_count);
-+
-+ return 0;
-+}
-+
-+static int vc_sm_global_statistics_show(struct seq_file *s, void *v)
-+{
-+ int ix;
-+
-+ /* Global state tracked statistics.
-+ */
-+ if (sm_state != NULL) {
-+ seq_puts(s, "\nDeceased Resources Statistics\n");
-+
-+ seq_printf(s, "\nNatural Cause (%u occurences)\n",
-+ sm_state->res_deceased_cnt);
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->deceased[ix] > 0) {
-+ seq_printf(s, " %u\t%s\n",
-+ sm_state->deceased[ix],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ seq_puts(s, "\n");
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->deceased[ix + END_ATTEMPT] > 0) {
-+ seq_printf(s, " %u\tFAILED %s\n",
-+ sm_state->deceased[ix + END_ATTEMPT],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+
-+ seq_printf(s, "\nForcefull (%u occurences)\n",
-+ sm_state->res_terminated_cnt);
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->terminated[ix] > 0) {
-+ seq_printf(s, " %u\t%s\n",
-+ sm_state->terminated[ix],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ seq_puts(s, "\n");
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (sm_state->terminated[ix + END_ATTEMPT] > 0) {
-+ seq_printf(s, " %u\tFAILED %s\n",
-+ sm_state->terminated[ix +
-+ END_ATTEMPT],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+#if 0
-+/* Read callback for the statistics proc entry.
-+*/
-+static int vc_sm_statistics_show(struct seq_file *s, void *v)
-+{
-+ int ix;
-+ struct SM_PRIV_DATA_T *file_data;
-+ struct SM_RESOURCE_T *resource;
-+ int res_count = 0;
-+ struct SM_PDE_T *p_pde;
-+
-+ p_pde = (struct SM_PDE_T *)(s->private);
-+ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data);
-+
-+ if (file_data == NULL)
-+ return 0;
-+
-+ /* Per process statistics.
-+ */
-+
-+ seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid);
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&file_data->resource_list)) {
-+ list_for_each_entry(resource, &file_data->resource_list,
-+ resource_list) {
-+ res_count++;
-+
-+ seq_printf(s, "\nGUID: 0x%x\n\n",
-+ resource->res_guid);
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (resource->res_stats[ix] > 0) {
-+ seq_printf(s,
-+ " %u\t%s\n",
-+ resource->res_stats[ix],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ seq_puts(s, "\n");
-+ for (ix = 0; ix < END_ATTEMPT; ix++) {
-+ if (resource->res_stats[ix + END_ATTEMPT] > 0) {
-+ seq_printf(s,
-+ " %u\tFAILED %s\n",
-+ resource->res_stats[
-+ ix + END_ATTEMPT],
-+ sm_stats_human_read[ix]);
-+ }
-+ }
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ seq_printf(s, "\nResources Count %d\n", res_count);
-+
-+ return 0;
-+}
-+#endif
-+
-+#if 0
-+/* Read callback for the allocation proc entry. */
-+static int vc_sm_alloc_show(struct seq_file *s, void *v)
-+{
-+ struct SM_PRIV_DATA_T *file_data;
-+ struct SM_RESOURCE_T *resource;
-+ int alloc_count = 0;
-+ struct SM_PDE_T *p_pde;
-+
-+ p_pde = (struct SM_PDE_T *)(s->private);
-+ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data);
-+
-+ if (!file_data)
-+ return 0;
-+
-+ /* Per process statistics. */
-+ seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid);
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&file_data->resource_list)) {
-+ list_for_each_entry(resource, &file_data->resource_list,
-+ resource_list) {
-+ alloc_count++;
-+
-+ seq_printf(s, "\nGUID: 0x%x\n",
-+ resource->res_guid);
-+ seq_printf(s, "Lock Count: %u\n",
-+ resource->lock_count);
-+ seq_printf(s, "Mapped: %s\n",
-+ (resource->map_count ? "yes" : "no"));
-+ seq_printf(s, "VC-handle: 0x%x\n",
-+ resource->res_handle);
-+ seq_printf(s, "VC-address: 0x%p\n",
-+ resource->res_base_mem);
-+ seq_printf(s, "VC-size (bytes): %u\n",
-+ resource->res_size);
-+ seq_printf(s, "Cache: %s\n",
-+ sm_cache_map_vector[resource->res_cached]);
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count);
-+
-+ return 0;
-+}
-+#endif
-+
-+static int vc_sm_seq_file_show(struct seq_file *s, void *v)
-+{
-+ struct SM_PDE_T *sm_pde;
-+
-+ sm_pde = (struct SM_PDE_T *)(s->private);
-+
-+ if (sm_pde && sm_pde->show)
-+ sm_pde->show(s, v);
-+
-+ return 0;
-+}
-+
-+static int vc_sm_single_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, vc_sm_seq_file_show, inode->i_private);
-+}
-+
-+static const struct file_operations vc_sm_debug_fs_fops = {
-+ .open = vc_sm_single_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+/* Adds a resource to the private data list which tracks all the allocated
-+** data.
-+*/
-+static void vmcs_sm_add_resource(struct SM_PRIV_DATA_T *privdata,
-+ struct SM_RESOURCE_T *resource)
-+{
-+ mutex_lock(&(sm_state->map_lock));
-+ list_add(&resource->resource_list, &privdata->resource_list);
-+ list_add(&resource->global_resource_list, &sm_state->resource_list);
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_base_mem,
-+ resource->res_handle, resource->res_size, resource->res_cached);
-+}
-+
-+/* Locates a resource and acquire a reference on it.
-+** The resource won't be deleted while there is a reference on it.
-+*/
-+static struct SM_RESOURCE_T *vmcs_sm_acquire_resource(struct SM_PRIV_DATA_T
-+ *private,
-+ unsigned int res_guid)
-+{
-+ struct SM_RESOURCE_T *resource, *ret = NULL;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ list_for_each_entry(resource, &private->resource_list, resource_list) {
-+ if (resource->res_guid != res_guid)
-+ continue;
-+
-+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_guid,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, resource->res_cached);
-+ resource->ref_count++;
-+ ret = resource;
-+ break;
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return ret;
-+}
-+
-+/* Locates a resource and acquire a reference on it.
-+** The resource won't be deleted while there is a reference on it.
-+*/
-+static struct SM_RESOURCE_T *vmcs_sm_acquire_first_resource(
-+ struct SM_PRIV_DATA_T *private)
-+{
-+ struct SM_RESOURCE_T *resource, *ret = NULL;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ list_for_each_entry(resource, &private->resource_list, resource_list) {
-+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_guid,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, resource->res_cached);
-+ resource->ref_count++;
-+ ret = resource;
-+ break;
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return ret;
-+}
-+
-+/* Locates a resource and acquire a reference on it.
-+** The resource won't be deleted while there is a reference on it.
-+*/
-+static struct SM_RESOURCE_T *vmcs_sm_acquire_global_resource(unsigned int
-+ res_guid)
-+{
-+ struct SM_RESOURCE_T *resource, *ret = NULL;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ list_for_each_entry(resource, &sm_state->resource_list,
-+ global_resource_list) {
-+ if (resource->res_guid != res_guid)
-+ continue;
-+
-+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+ __func__, resource, resource->res_guid,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, resource->res_cached);
-+ resource->ref_count++;
-+ ret = resource;
-+ break;
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return ret;
-+}
-+
-+/* Release a previously acquired resource.
-+** The resource will be deleted when its refcount reaches 0.
-+*/
-+static void vmcs_sm_release_resource(struct SM_RESOURCE_T *resource, int force)
-+{
-+ struct SM_PRIV_DATA_T *private = resource->private;
-+ struct sm_mmap *map, *map_tmp;
-+ struct SM_RESOURCE_T *res_tmp;
-+ int ret;
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (--resource->ref_count) {
-+ if (force)
-+ pr_err("[%s]: resource %p in use\n", __func__, resource);
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+ return;
-+ }
-+
-+ /* Time to free the resource. Start by removing it from the list */
-+ list_del(&resource->resource_list);
-+ list_del(&resource->global_resource_list);
-+
-+ /* Walk the global resource list, find out if the resource is used
-+ * somewhere else. In which case we don't want to delete it.
-+ */
-+ list_for_each_entry(res_tmp, &sm_state->resource_list,
-+ global_resource_list) {
-+ if (res_tmp->res_handle == resource->res_handle) {
-+ resource->res_handle = 0;
-+ break;
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem);
-+ resource->res_stats[FREE]++;
-+
-+ /* Make sure the resource we're removing is unmapped first */
-+ if (resource->map_count && !list_empty(&resource->map_list)) {
-+ down_write(&current->mm->mmap_sem);
-+ list_for_each_entry_safe(map, map_tmp, &resource->map_list,
-+ resource_map_list) {
-+ ret =
-+ do_munmap(current->mm, map->res_addr,
-+ resource->res_size);
-+ if (ret) {
-+ pr_err("[%s]: could not unmap resource %p\n",
-+ __func__, resource);
-+ }
-+ }
-+ up_write(&current->mm->mmap_sem);
-+ }
-+
-+ /* Free up the videocore allocated resource.
-+ */
-+ if (resource->res_handle) {
-+ VC_SM_FREE_T free = {
-+ resource->res_handle, resource->res_base_mem
-+ };
-+ int status = vc_vchi_sm_free(sm_state->sm_handle, &free,
-+ &private->int_trans_id);
-+ if (status != 0 && status != -EINTR) {
-+ pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ resource->res_stats[FREE_FAIL]++;
-+ ret = -EPERM;
-+ }
-+ }
-+
-+ /* Free up the shared resource.
-+ */
-+ if (resource->res_shared)
-+ vmcs_sm_release_resource(resource->res_shared, 0);
-+
-+ /* Free up the local resource tracking this allocation.
-+ */
-+ vc_sm_resource_deceased(resource, force);
-+ kfree(resource);
-+}
-+
-+/* Dump the map table for the driver. If process is -1, dumps the whole table,
-+** if process is a valid pid (non -1) dump only the entries associated with the
-+** pid of interest.
-+*/
-+static void vmcs_sm_host_walk_map_per_pid(int pid)
-+{
-+ struct sm_mmap *map = NULL;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if (sm_state == NULL) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ return;
-+ }
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ /* Log all applicable mapping(s).
-+ */
-+ if (!list_empty(&sm_state->map_list)) {
-+ list_for_each_entry(map, &sm_state->map_list, map_list) {
-+ if (pid == -1 || map->res_pid == pid) {
-+ pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n",
-+ __func__, map->res_pid, map->res_vc_hdl,
-+ map->res_usr_hdl, map->res_addr);
-+ }
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return;
-+}
-+
-+/* Dump the allocation table from host side point of view. This only dumps the
-+** data allocated for this process/device referenced by the file_data.
-+*/
-+static void vmcs_sm_host_walk_alloc(struct SM_PRIV_DATA_T *file_data)
-+{
-+ struct SM_RESOURCE_T *resource = NULL;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if ((sm_state == NULL) || (file_data == NULL)) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ return;
-+ }
-+
-+ mutex_lock(&(sm_state->map_lock));
-+
-+ if (!list_empty(&file_data->resource_list)) {
-+ list_for_each_entry(resource, &file_data->resource_list,
-+ resource_list) {
-+ pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem, resource->res_size,
-+ resource->res_cached);
-+ }
-+ }
-+
-+ mutex_unlock(&(sm_state->map_lock));
-+
-+ return;
-+}
-+
-+/* Create support for private data tracking.
-+*/
-+static struct SM_PRIV_DATA_T *vc_sm_create_priv_data(pid_t id)
-+{
-+ char alloc_name[32];
-+ struct SM_PRIV_DATA_T *file_data = NULL;
-+
-+ /* Allocate private structure. */
-+ file_data = kzalloc(sizeof(*file_data), GFP_KERNEL);
-+
-+ if (!file_data) {
-+ pr_err("[%s]: cannot allocate file data\n", __func__);
-+ goto out;
-+ }
-+
-+ snprintf(alloc_name, sizeof(alloc_name), "%d", id);
-+
-+ INIT_LIST_HEAD(&file_data->resource_list);
-+ file_data->pid = id;
-+ file_data->dir_pid = debugfs_create_dir(alloc_name,
-+ sm_state->dir_alloc);
-+#if 0
-+ /* TODO: fix this to support querying statistics per pid */
-+
-+ if (IS_ERR_OR_NULL(file_data->dir_pid)) {
-+ file_data->dir_pid = NULL;
-+ } else {
-+ struct dentry *dir_entry;
-+
-+ dir_entry = debugfs_create_file(VC_SM_RESOURCES, S_IRUGO,
-+ file_data->dir_pid, file_data,
-+ vc_sm_debug_fs_fops);
-+
-+ file_data->dir_res.dir_entry = dir_entry;
-+ file_data->dir_res.priv_data = file_data;
-+ file_data->dir_res.show = &vc_sm_alloc_show;
-+
-+ dir_entry = debugfs_create_file(VC_SM_STATS, S_IRUGO,
-+ file_data->dir_pid, file_data,
-+ vc_sm_debug_fs_fops);
-+
-+ file_data->dir_res.dir_entry = dir_entry;
-+ file_data->dir_res.priv_data = file_data;
-+ file_data->dir_res.show = &vc_sm_statistics_show;
-+ }
-+ pr_debug("[%s]: private data allocated %p\n", __func__, file_data);
-+
-+#endif
-+out:
-+ return file_data;
-+}
-+
-+/* Open the device. Creates a private state to help track all allocation
-+** associated with this device.
-+*/
-+static int vc_sm_open(struct inode *inode, struct file *file)
-+{
-+ int ret = 0;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if (!sm_state) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ file->private_data = vc_sm_create_priv_data(current->tgid);
-+ if (file->private_data == NULL) {
-+ pr_err("[%s]: failed to create data tracker\n", __func__);
-+
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/* Close the device. Free up all resources still associated with this device
-+** at the time.
-+*/
-+static int vc_sm_release(struct inode *inode, struct file *file)
-+{
-+ struct SM_PRIV_DATA_T *file_data =
-+ (struct SM_PRIV_DATA_T *)file->private_data;
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if (sm_state == NULL || file_data == NULL) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ pr_debug("[%s]: using private data %p\n", __func__, file_data);
-+
-+ if (file_data->restart_sys == -EINTR) {
-+ VC_SM_ACTION_CLEAN_T action_clean;
-+
-+ pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n",
-+ __func__, file_data->int_action,
-+ file_data->int_trans_id);
-+
-+ action_clean.res_action = file_data->int_action;
-+ action_clean.action_trans_id = file_data->int_trans_id;
-+
-+ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
-+ }
-+
-+ while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) {
-+ vmcs_sm_release_resource(resource, 0);
-+ vmcs_sm_release_resource(resource, 1);
-+ }
-+
-+ /* Remove the corresponding proc entry. */
-+ debugfs_remove_recursive(file_data->dir_pid);
-+
-+ /* Terminate the private data.
-+ */
-+ kfree(file_data);
-+
-+out:
-+ return ret;
-+}
-+
-+static void vcsm_vma_open(struct vm_area_struct *vma)
-+{
-+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+
-+ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
-+ __func__, vma->vm_start, vma->vm_end, (int)current->tgid,
-+ (int)vma->vm_pgoff);
-+
-+ map->ref_count++;
-+}
-+
-+static void vcsm_vma_close(struct vm_area_struct *vma)
-+{
-+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+
-+ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
-+ __func__, vma->vm_start, vma->vm_end, (int)current->tgid,
-+ (int)vma->vm_pgoff);
-+
-+ map->ref_count--;
-+
-+ /* Remove from the map table.
-+ */
-+ if (map->ref_count == 0)
-+ vmcs_sm_remove_map(sm_state, map->resource, map);
-+}
-+
-+static int vcsm_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
-+{
-+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+ struct SM_RESOURCE_T *resource = map->resource;
-+ pgoff_t page_offset;
-+ unsigned long pfn;
-+ int ret = 0;
-+
-+ /* Lock the resource if necessary.
-+ */
-+ if (!resource->lock_count) {
-+ VC_SM_LOCK_UNLOCK_T lock_unlock;
-+ VC_SM_LOCK_RESULT_T lock_result;
-+ int status;
-+
-+ lock_unlock.res_handle = resource->res_handle;
-+ lock_unlock.res_mem = resource->res_base_mem;
-+
-+ pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n",
-+ __func__, lock_unlock.res_handle, lock_unlock.res_mem);
-+
-+ /* Lock the videocore allocated resource.
-+ */
-+ status = vc_vchi_sm_lock(sm_state->sm_handle,
-+ &lock_unlock, &lock_result, 0);
-+ if ((status != 0) ||
-+ ((status == 0) && (lock_result.res_mem == NULL))) {
-+ pr_err("[%s]: failed to lock memory on videocore (status: %u)\n",
-+ __func__, status);
-+ resource->res_stats[LOCK_FAIL]++;
-+ return VM_FAULT_SIGBUS;
-+ }
-+
-+ pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem);
-+ outer_inv_range(__pfn_to_phys(pfn),
-+ __pfn_to_phys(pfn) + resource->res_size);
-+
-+ resource->res_stats[LOCK]++;
-+ resource->lock_count++;
-+
-+ /* Keep track of the new base memory.
-+ */
-+ if ((lock_result.res_mem != NULL) &&
-+ (lock_result.res_old_mem != NULL) &&
-+ (lock_result.res_mem != lock_result.res_old_mem)) {
-+ resource->res_base_mem = lock_result.res_mem;
-+ }
-+ }
-+
-+ /* We don't use vmf->pgoff since that has the fake offset */
-+ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start);
-+ pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF;
-+ pfn += mm_vc_mem_phys_addr;
-+ pfn += page_offset;
-+ pfn >>= PAGE_SHIFT;
-+
-+ /* Finally, remap it */
-+ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
-+
-+ switch (ret) {
-+ case 0:
-+ case -ERESTARTSYS:
-+ return VM_FAULT_NOPAGE;
-+ case -ENOMEM:
-+ case -EAGAIN:
-+ return VM_FAULT_OOM;
-+ default:
-+ return VM_FAULT_SIGBUS;
-+ }
-+}
-+
-+static struct vm_operations_struct vcsm_vm_ops = {
-+ .open = vcsm_vma_open,
-+ .close = vcsm_vma_close,
-+ .fault = vcsm_vma_fault,
-+};
-+
-+/* Walks a VMA and clean each valid page from the cache */
-+static void vcsm_vma_cache_clean_page_range(unsigned long addr,
-+ unsigned long end)
-+{
-+ pgd_t *pgd;
-+ pud_t *pud;
-+ pmd_t *pmd;
-+ pte_t *pte;
-+ unsigned long pgd_next, pud_next, pmd_next;
-+
-+ if (addr >= end)
-+ return;
-+
-+ /* Walk PGD */
-+ pgd = pgd_offset(current->mm, addr);
-+ do {
-+ pgd_next = pgd_addr_end(addr, end);
-+
-+ if (pgd_none(*pgd) || pgd_bad(*pgd))
-+ continue;
-+
-+ /* Walk PUD */
-+ pud = pud_offset(pgd, addr);
-+ do {
-+ pud_next = pud_addr_end(addr, pgd_next);
-+ if (pud_none(*pud) || pud_bad(*pud))
-+ continue;
-+
-+ /* Walk PMD */
-+ pmd = pmd_offset(pud, addr);
-+ do {
-+ pmd_next = pmd_addr_end(addr, pud_next);
-+ if (pmd_none(*pmd) || pmd_bad(*pmd))
-+ continue;
-+
-+ /* Walk PTE */
-+ pte = pte_offset_map(pmd, addr);
-+ do {
-+ if (pte_none(*pte)
-+ || !pte_present(*pte))
-+ continue;
-+
-+ /* Clean + invalidate */
-+ dmac_flush_range((const void *) addr,
-+ (const void *)
-+ (addr + PAGE_SIZE));
-+
-+ } while (pte++, addr +=
-+ PAGE_SIZE, addr != pmd_next);
-+ pte_unmap(pte);
-+
-+ } while (pmd++, addr = pmd_next, addr != pud_next);
-+
-+ } while (pud++, addr = pud_next, addr != pgd_next);
-+ } while (pgd++, addr = pgd_next, addr != end);
-+}
-+
-+/* Map an allocated data into something that the user space.
-+*/
-+static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma)
-+{
-+ int ret = 0;
-+ struct SM_PRIV_DATA_T *file_data =
-+ (struct SM_PRIV_DATA_T *)file->private_data;
-+ struct SM_RESOURCE_T *resource = NULL;
-+ struct sm_mmap *map = NULL;
-+
-+ /* Make sure the device was started properly.
-+ */
-+ if ((sm_state == NULL) || (file_data == NULL)) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data,
-+ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
-+
-+ /* We lookup to make sure that the data we are being asked to mmap is
-+ ** something that we allocated.
-+ **
-+ ** We use the offset information as the key to tell us which resource
-+ ** we are mapping.
-+ */
-+ resource = vmcs_sm_acquire_resource(file_data,
-+ ((unsigned int)vma->vm_pgoff <<
-+ PAGE_SHIFT));
-+ if (resource == NULL) {
-+ pr_err("[%s]: failed to locate resource for guid %x\n", __func__,
-+ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
-+ return -ENOMEM;
-+ }
-+
-+ pr_debug("[%s]: guid %x, tgid %u, %u, %u\n",
-+ __func__, resource->res_guid, current->tgid, resource->pid,
-+ file_data->pid);
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n",
-+ __func__, current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ /* Verify that what we are asked to mmap is proper.
-+ */
-+ if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) {
-+ pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n",
-+ __func__,
-+ resource->res_size,
-+ (unsigned int)(vma->vm_end - vma->vm_start));
-+
-+ ret = -EINVAL;
-+ goto error;
-+ }
-+
-+ /* Keep track of the tuple in the global resource list such that one
-+ * can do a mapping lookup for address/memory handle.
-+ */
-+ map = kzalloc(sizeof(*map), GFP_KERNEL);
-+ if (map == NULL) {
-+ pr_err("[%s]: failed to allocate global tracking resource\n",
-+ __func__);
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+
-+ map->res_pid = current->tgid;
-+ map->res_vc_hdl = resource->res_handle;
-+ map->res_usr_hdl = resource->res_guid;
-+ map->res_addr = (long unsigned int)vma->vm_start;
-+ map->resource = resource;
-+ map->vma = vma;
-+ vmcs_sm_add_map(sm_state, resource, map);
-+
-+ /* We are not actually mapping the pages, we just provide a fault
-+ ** handler to allow pages to be mapped when accessed
-+ */
-+ vma->vm_flags |=
-+ VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND;
-+ vma->vm_ops = &vcsm_vm_ops;
-+ vma->vm_private_data = map;
-+
-+ /* vm_pgoff is the first PFN of the mapped memory */
-+ vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF;
-+ vma->vm_pgoff += mm_vc_mem_phys_addr;
-+ vma->vm_pgoff >>= PAGE_SHIFT;
-+
-+ if ((resource->res_cached == VMCS_SM_CACHE_NONE) ||
-+ (resource->res_cached == VMCS_SM_CACHE_VC)) {
-+ /* Allocated non host cached memory, honour it.
-+ */
-+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+ }
-+
-+ pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n",
-+ __func__,
-+ resource, resource->res_guid, resource->lock_count,
-+ resource->res_base_mem, resource->res_handle,
-+ resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start),
-+ resource->res_cached);
-+
-+ pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n",
-+ __func__, resource, resource->res_base_mem,
-+ resource->res_handle, resource->map_count,
-+ (unsigned int)vma->vm_start);
-+
-+ vcsm_vma_open(vma);
-+ resource->res_stats[MAP]++;
-+ vmcs_sm_release_resource(resource, 0);
-+ return 0;
-+
-+error:
-+ vmcs_sm_release_resource(resource, 0);
-+ resource->res_stats[MAP_FAIL]++;
-+ return ret;
-+}
-+
-+/* Allocate a shared memory handle and block.
-+*/
-+int vc_sm_ioctl_alloc(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_alloc *ioparam)
-+{
-+ int ret = 0;
-+ int status;
-+ struct SM_RESOURCE_T *resource;
-+ VC_SM_ALLOC_T alloc = { 0 };
-+ VC_SM_ALLOC_RESULT_T result = { 0 };
-+
-+ /* Setup our allocation parameters */
-+ alloc.type = ((ioparam->cached == VMCS_SM_CACHE_VC)
-+ || (ioparam->cached ==
-+ VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED :
-+ VC_SM_ALLOC_NON_CACHED;
-+ alloc.base_unit = ioparam->size;
-+ alloc.num_unit = ioparam->num;
-+ alloc.allocator = current->tgid;
-+ /* Align to kernel page size */
-+ alloc.alignement = 4096;
-+ /* Align the size to the kernel page size */
-+ alloc.base_unit =
-+ (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1);
-+ if (*ioparam->name) {
-+ memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1);
-+ } else {
-+ memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT,
-+ sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT));
-+ }
-+
-+ pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n",
-+ __func__, alloc.name, alloc.type, ioparam->size,
-+ alloc.base_unit, alloc.num_unit, alloc.alignement);
-+
-+ /* Allocate local resource to track this allocation.
-+ */
-+ resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+ if (!resource) {
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+ INIT_LIST_HEAD(&resource->map_list);
-+ resource->ref_count++;
-+ resource->pid = current->tgid;
-+
-+ /* Allocate the videocore resource.
-+ */
-+ status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result,
-+ &private->int_trans_id);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+ ret = -ERESTARTSYS;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_ALLOC;
-+ goto error;
-+ } else if (status != 0 || (status == 0 && result.res_mem == NULL)) {
-+ pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ ret = -ENOMEM;
-+ resource->res_stats[ALLOC_FAIL]++;
-+ goto error;
-+ }
-+
-+ /* Keep track of the resource we created.
-+ */
-+ resource->private = private;
-+ resource->res_handle = result.res_handle;
-+ resource->res_base_mem = result.res_mem;
-+ resource->res_size = alloc.base_unit * alloc.num_unit;
-+ resource->res_cached = ioparam->cached;
-+
-+ /* Kernel/user GUID. This global identifier is used for mmap'ing the
-+ * allocated region from user space, it is passed as the mmap'ing
-+ * offset, we use it to 'hide' the videocore handle/address.
-+ */
-+ mutex_lock(&sm_state->lock);
-+ resource->res_guid = ++sm_state->guid;
-+ mutex_unlock(&sm_state->lock);
-+ resource->res_guid <<= PAGE_SHIFT;
-+
-+ vmcs_sm_add_resource(private, resource);
-+
-+ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem, resource->res_size,
-+ resource->res_cached);
-+
-+ /* We're done */
-+ resource->res_stats[ALLOC]++;
-+ ioparam->handle = resource->res_guid;
-+ return 0;
-+
-+error:
-+ pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n",
-+ __func__, alloc.name, ret, alloc.type, ioparam->size,
-+ alloc.base_unit, alloc.num_unit, alloc.alignement);
-+ if (resource != NULL) {
-+ vc_sm_resource_deceased(resource, 1);
-+ kfree(resource);
-+ }
-+ return ret;
-+}
-+
-+/* Share an allocate memory handle and block.
-+*/
-+int vc_sm_ioctl_alloc_share(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_alloc_share *ioparam)
-+{
-+ struct SM_RESOURCE_T *resource, *shared_resource;
-+ int ret = 0;
-+
-+ pr_debug("[%s]: attempt to share resource %u\n", __func__,
-+ ioparam->handle);
-+
-+ shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle);
-+ if (shared_resource == NULL) {
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+
-+ /* Allocate local resource to track this allocation.
-+ */
-+ resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+ if (resource == NULL) {
-+ pr_err("[%s]: failed to allocate local tracking resource\n",
-+ __func__);
-+ ret = -ENOMEM;
-+ goto error;
-+ }
-+ INIT_LIST_HEAD(&resource->map_list);
-+ resource->ref_count++;
-+ resource->pid = current->tgid;
-+
-+ /* Keep track of the resource we created.
-+ */
-+ resource->private = private;
-+ resource->res_handle = shared_resource->res_handle;
-+ resource->res_base_mem = shared_resource->res_base_mem;
-+ resource->res_size = shared_resource->res_size;
-+ resource->res_cached = shared_resource->res_cached;
-+ resource->res_shared = shared_resource;
-+
-+ mutex_lock(&sm_state->lock);
-+ resource->res_guid = ++sm_state->guid;
-+ mutex_unlock(&sm_state->lock);
-+ resource->res_guid <<= PAGE_SHIFT;
-+
-+ vmcs_sm_add_resource(private, resource);
-+
-+ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
-+ __func__, resource->res_guid, resource->res_handle,
-+ resource->res_base_mem, resource->res_size,
-+ resource->res_cached);
-+
-+ /* We're done */
-+ resource->res_stats[ALLOC]++;
-+ ioparam->handle = resource->res_guid;
-+ ioparam->size = resource->res_size;
-+ return 0;
-+
-+error:
-+ pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle);
-+ if (shared_resource != NULL)
-+ vmcs_sm_release_resource(shared_resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Free a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_free(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_free *ioparam)
-+{
-+ struct SM_RESOURCE_T *resource =
-+ vmcs_sm_acquire_resource(private, ioparam->handle);
-+
-+ if (resource == NULL) {
-+ pr_err("[%s]: resource for guid %u does not exist\n", __func__,
-+ ioparam->handle);
-+ return -EINVAL;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n",
-+ __func__, current->tgid, resource->pid);
-+ vmcs_sm_release_resource(resource, 0);
-+ return -EPERM;
-+ }
-+
-+ vmcs_sm_release_resource(resource, 0);
-+ vmcs_sm_release_resource(resource, 0);
-+ return 0;
-+}
-+
-+/* Resize a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_resize(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_resize *ioparam)
-+{
-+ int ret = 0;
-+ int status;
-+ VC_SM_RESIZE_T resize;
-+ struct SM_RESOURCE_T *resource;
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+ if (!resource) {
-+ pr_err("[%s]: failed resource - guid %x\n",
-+ __func__, ioparam->handle);
-+ ret = -EFAULT;
-+ goto error;
-+ }
-+
-+ /* If the resource is locked, its reference count will be not NULL,
-+ ** in which case we will not be allowed to resize it anyways, so
-+ ** reject the attempt here.
-+ */
-+ if (resource->lock_count != 0) {
-+ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
-+ __func__, ioparam->handle, resource->lock_count);
-+ ret = -EFAULT;
-+ goto error;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n", __func__,
-+ current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ if (resource->map_count != 0) {
-+ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
-+ __func__, ioparam->handle, resource->map_count);
-+ ret = -EFAULT;
-+ goto error;
-+ }
-+
-+ resize.res_handle = resource->res_handle;
-+ resize.res_mem = resource->res_base_mem;
-+ resize.res_new_size = ioparam->new_size;
-+
-+ pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n",
-+ __func__, ioparam->handle, resize.res_handle, resize.res_mem);
-+
-+ /* Resize the videocore allocated resource.
-+ */
-+ status = vc_vchi_sm_resize(sm_state->sm_handle, &resize,
-+ &private->int_trans_id);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+ ret = -ERESTARTSYS;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_RESIZE;
-+ goto error;
-+ } else if (status != 0) {
-+ pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n",
-+ __func__, resize.res_handle, resource->res_size,
-+ resize.res_new_size);
-+
-+ /* Successfully resized, save the information and inform the user.
-+ */
-+ ioparam->old_size = resource->res_size;
-+ resource->res_size = resize.res_new_size;
-+
-+error:
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Lock a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_lock(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_lock_unlock *ioparam,
-+ int change_cache, enum vmcs_sm_cache_e cache_type,
-+ unsigned int vc_addr)
-+{
-+ int status;
-+ VC_SM_LOCK_UNLOCK_T lock;
-+ VC_SM_LOCK_RESULT_T result;
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+ struct sm_mmap *map, *map_tmp;
-+ long unsigned int phys_addr;
-+
-+ map = NULL;
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+ if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto error;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n", __func__,
-+ current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ lock.res_handle = resource->res_handle;
-+ lock.res_mem = resource->res_base_mem;
-+
-+ /* Take the lock and get the address to be mapped.
-+ */
-+ if (vc_addr == 0) {
-+ pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n",
-+ __func__, ioparam->handle, lock.res_handle,
-+ lock.res_mem);
-+
-+ /* Lock the videocore allocated resource.
-+ */
-+ status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result,
-+ &private->int_trans_id);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+ ret = -ERESTARTSYS;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_LOCK;
-+ goto error;
-+ } else if (status != 0 ||
-+ (status == 0 && result.res_mem == NULL)) {
-+ pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+ ret = -EPERM;
-+ resource->res_stats[LOCK_FAIL]++;
-+ goto error;
-+ }
-+
-+ pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n",
-+ __func__, lock.res_handle, result.res_mem,
-+ lock.res_mem, resource->lock_count);
-+ }
-+ /* Lock assumed taken already, address to be mapped is known.
-+ */
-+ else
-+ resource->res_base_mem = (void *)vc_addr;
-+
-+ resource->res_stats[LOCK]++;
-+ resource->lock_count++;
-+
-+ /* Keep track of the new base memory allocation if it has changed.
-+ */
-+ if ((vc_addr == 0) &&
-+ (result.res_mem != NULL) &&
-+ (result.res_old_mem != NULL) &&
-+ (result.res_mem != result.res_old_mem)) {
-+ resource->res_base_mem = result.res_mem;
-+
-+ /* Kernel allocated resources.
-+ */
-+ if (resource->pid == 0) {
-+ if (!list_empty(&resource->map_list)) {
-+ list_for_each_entry_safe(map, map_tmp,
-+ &resource->map_list,
-+ resource_map_list) {
-+ if (map->res_addr) {
-+ iounmap((void *)map->res_addr);
-+ map->res_addr = 0;
-+
-+ vmcs_sm_remove_map(sm_state,
-+ map->resource,
-+ map);
-+ break;
-+ }
-+ }
-+ }
-+ }
-+ }
-+
-+ if (change_cache)
-+ resource->res_cached = cache_type;
-+
-+ if (resource->map_count) {
-+ ioparam->addr =
-+ vmcs_sm_usr_address_from_pid_and_usr_handle(
-+ current->tgid, ioparam->handle);
-+
-+ pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n",
-+ __func__, resource->map_count, private->pid,
-+ current->tgid, ioparam->handle, ioparam->addr);
-+ } else {
-+ /* Kernel allocated resources.
-+ */
-+ if (resource->pid == 0) {
-+ pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n",
-+ __func__, ioparam->handle, lock.res_handle);
-+
-+ ioparam->addr = 0;
-+
-+ map = kzalloc(sizeof(*map), GFP_KERNEL);
-+ if (map == NULL) {
-+ pr_err("[%s]: failed allocating tracker\n",
-+ __func__);
-+ ret = -ENOMEM;
-+ goto error;
-+ } else {
-+ phys_addr = (uint32_t)resource->res_base_mem &
-+ 0x3FFFFFFF;
-+ phys_addr += mm_vc_mem_phys_addr;
-+ if (resource->res_cached
-+ == VMCS_SM_CACHE_HOST) {
-+ ioparam->addr = (long unsigned int)
-+ /* TODO - make cached work */
-+ ioremap_nocache(phys_addr,
-+ resource->res_size);
-+
-+ pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n",
-+ __func__, ioparam->handle,
-+ lock.res_handle, ioparam->addr);
-+ } else {
-+ ioparam->addr = (long unsigned int)
-+ ioremap_nocache(phys_addr,
-+ resource->res_size);
-+
-+ pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n",
-+ __func__, ioparam->handle,
-+ lock.res_handle, ioparam->addr);
-+ }
-+
-+ map->res_pid = 0;
-+ map->res_vc_hdl = resource->res_handle;
-+ map->res_usr_hdl = resource->res_guid;
-+ map->res_addr = ioparam->addr;
-+ map->resource = resource;
-+ map->vma = NULL;
-+
-+ vmcs_sm_add_map(sm_state, resource, map);
-+ }
-+ } else
-+ ioparam->addr = 0;
-+ }
-+
-+error:
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Unlock a previously allocated shared memory handle and block.
-+*/
-+static int vc_sm_ioctl_unlock(struct SM_PRIV_DATA_T *private,
-+ struct vmcs_sm_ioctl_lock_unlock *ioparam,
-+ int flush, int wait_reply, int no_vc_unlock)
-+{
-+ int status;
-+ VC_SM_LOCK_UNLOCK_T unlock;
-+ struct sm_mmap *map, *map_tmp;
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+
-+ map = NULL;
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+ if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto error;
-+ }
-+
-+ /* Check permissions.
-+ */
-+ if (resource->pid && (resource->pid != current->tgid)) {
-+ pr_err("[%s]: current tgid %u != %u owner\n",
-+ __func__, current->tgid, resource->pid);
-+ ret = -EPERM;
-+ goto error;
-+ }
-+
-+ unlock.res_handle = resource->res_handle;
-+ unlock.res_mem = resource->res_base_mem;
-+
-+ pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n",
-+ __func__, ioparam->handle, unlock.res_handle, unlock.res_mem);
-+
-+ /* User space allocated resources.
-+ */
-+ if (resource->pid) {
-+ /* Flush if requested */
-+ if (resource->res_cached && flush) {
-+ dma_addr_t phys_addr = 0;
-+ resource->res_stats[FLUSH]++;
-+
-+ phys_addr =
-+ (dma_addr_t)((uint32_t)resource->res_base_mem &
-+ 0x3FFFFFFF);
-+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+ /* L1 cache flush */
-+ down_read(&current->mm->mmap_sem);
-+ list_for_each_entry(map, &resource->map_list,
-+ resource_map_list) {
-+ if (map->vma) {
-+ unsigned long start;
-+ unsigned long end;
-+ start = map->vma->vm_start;
-+ end = map->vma->vm_end;
-+
-+ vcsm_vma_cache_clean_page_range(
-+ start, end);
-+ }
-+ }
-+ up_read(&current->mm->mmap_sem);
-+
-+ /* L2 cache flush */
-+ outer_clean_range(phys_addr,
-+ phys_addr +
-+ (size_t) resource->res_size);
-+ }
-+
-+ /* We need to zap all the vmas associated with this resource */
-+ if (resource->lock_count == 1) {
-+ down_read(&current->mm->mmap_sem);
-+ list_for_each_entry(map, &resource->map_list,
-+ resource_map_list) {
-+ if (map->vma) {
-+ zap_vma_ptes(map->vma,
-+ map->vma->vm_start,
-+ map->vma->vm_end -
-+ map->vma->vm_start);
-+ }
-+ }
-+ up_read(&current->mm->mmap_sem);
-+ }
-+ }
-+ /* Kernel allocated resources. */
-+ else {
-+ /* Global + Taken in this context */
-+ if (resource->ref_count == 2) {
-+ if (!list_empty(&resource->map_list)) {
-+ list_for_each_entry_safe(map, map_tmp,
-+ &resource->map_list,
-+ resource_map_list) {
-+ if (map->res_addr) {
-+ if (flush &&
-+ (resource->res_cached ==
-+ VMCS_SM_CACHE_HOST)) {
-+ long unsigned int
-+ phys_addr;
-+ phys_addr = (uint32_t)
-+ resource->res_base_mem & 0x3FFFFFFF;
-+ phys_addr +=
-+ mm_vc_mem_phys_addr;
-+
-+ /* L1 cache flush */
-+ dmac_flush_range((const
-+ void
-+ *)
-+ map->res_addr, (const void *)
-+ (map->res_addr + resource->res_size));
-+
-+ /* L2 cache flush */
-+ outer_clean_range
-+ (phys_addr,
-+ phys_addr +
-+ (size_t)
-+ resource->res_size);
-+ }
-+
-+ iounmap((void *)map->res_addr);
-+ map->res_addr = 0;
-+
-+ vmcs_sm_remove_map(sm_state,
-+ map->resource,
-+ map);
-+ break;
-+ }
-+ }
-+ }
-+ }
-+ }
-+
-+ if (resource->lock_count) {
-+ /* Bypass the videocore unlock.
-+ */
-+ if (no_vc_unlock)
-+ status = 0;
-+ /* Unlock the videocore allocated resource.
-+ */
-+ else {
-+ status =
-+ vc_vchi_sm_unlock(sm_state->sm_handle, &unlock,
-+ &private->int_trans_id,
-+ wait_reply);
-+ if (status == -EINTR) {
-+ pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n",
-+ __func__, private->int_trans_id);
-+
-+ ret = -ERESTARTSYS;
-+ resource->res_stats[UNLOCK]--;
-+ private->restart_sys = -EINTR;
-+ private->int_action = VC_SM_MSG_TYPE_UNLOCK;
-+ goto error;
-+ } else if (status != 0) {
-+ pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n",
-+ __func__, status, private->int_trans_id);
-+
-+ ret = -EPERM;
-+ resource->res_stats[UNLOCK_FAIL]++;
-+ goto error;
-+ }
-+ }
-+
-+ resource->res_stats[UNLOCK]++;
-+ resource->lock_count--;
-+ }
-+
-+ pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n",
-+ __func__, unlock.res_handle, unlock.res_mem,
-+ resource->lock_count);
-+
-+error:
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ return ret;
-+}
-+
-+/* Handle control from host. */
-+static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ int ret = 0;
-+ unsigned int cmdnr = _IOC_NR(cmd);
-+ struct SM_PRIV_DATA_T *file_data =
-+ (struct SM_PRIV_DATA_T *)file->private_data;
-+ struct SM_RESOURCE_T *resource = NULL;
-+
-+ /* Validate we can work with this device. */
-+ if ((sm_state == NULL) || (file_data == NULL)) {
-+ pr_err("[%s]: invalid device\n", __func__);
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr,
-+ current->tgid, file_data->pid);
-+
-+ /* Action is a re-post of a previously interrupted action? */
-+ if (file_data->restart_sys == -EINTR) {
-+ VC_SM_ACTION_CLEAN_T action_clean;
-+
-+ pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n",
-+ __func__, file_data->int_action,
-+ file_data->int_trans_id);
-+
-+ action_clean.res_action = file_data->int_action;
-+ action_clean.action_trans_id = file_data->int_trans_id;
-+
-+ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
-+
-+ file_data->restart_sys = 0;
-+ }
-+
-+ /* Now process the command.
-+ */
-+ switch (cmdnr) {
-+ /* New memory allocation.
-+ */
-+ case VMCS_SM_CMD_ALLOC:
-+ {
-+ struct vmcs_sm_ioctl_alloc ioparam;
-+
-+ /* Get the parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_alloc(file_data, &ioparam);
-+ if (!ret &&
-+ (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0)) {
-+ struct vmcs_sm_ioctl_free freeparam = {
-+ ioparam.handle
-+ };
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ vc_sm_ioctl_free(file_data, &freeparam);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Share existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_ALLOC_SHARE:
-+ {
-+ struct vmcs_sm_ioctl_alloc_share ioparam;
-+
-+ /* Get the parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_alloc_share(file_data, &ioparam);
-+
-+ /* Copy result back to user.
-+ */
-+ if (!ret
-+ && copy_to_user((void *)arg, &ioparam,
-+ sizeof(ioparam)) != 0) {
-+ struct vmcs_sm_ioctl_free freeparam = {
-+ ioparam.handle
-+ };
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ vc_sm_ioctl_free(file_data, &freeparam);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Lock (attempt to) *and* register a cache behavior change.
-+ */
-+ case VMCS_SM_CMD_LOCK_CACHE:
-+ {
-+ struct vmcs_sm_ioctl_lock_cache ioparam;
-+ struct vmcs_sm_ioctl_lock_unlock lock;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ lock.handle = ioparam.handle;
-+ ret =
-+ vc_sm_ioctl_lock(file_data, &lock, 1,
-+ ioparam.cached, 0);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Lock (attempt to) existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_LOCK:
-+ {
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0);
-+
-+ /* Copy result back to user.
-+ */
-+ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
-+ != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Unlock (attempt to) existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_UNLOCK:
-+ {
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Resize (attempt to) existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_RESIZE:
-+ {
-+ struct vmcs_sm_ioctl_resize ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_resize(file_data, &ioparam);
-+
-+ /* Copy result back to user.
-+ */
-+ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
-+ != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Terminate existing memory allocation.
-+ */
-+ case VMCS_SM_CMD_FREE:
-+ {
-+ struct vmcs_sm_ioctl_free ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user
-+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ret = vc_sm_ioctl_free(file_data, &ioparam);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Walk allocation on videocore, information shows up in the
-+ ** videocore log.
-+ */
-+ case VMCS_SM_CMD_VC_WALK_ALLOC:
-+ {
-+ pr_debug("[%s]: invoking walk alloc\n", __func__);
-+
-+ if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0)
-+ pr_err("[%s]: failed to walk-alloc on videocore\n",
-+ __func__);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+/* Walk mapping table on host, information shows up in the
-+ ** kernel log.
-+ */
-+ case VMCS_SM_CMD_HOST_WALK_MAP:
-+ {
-+ /* Use pid of -1 to tell to walk the whole map. */
-+ vmcs_sm_host_walk_map_per_pid(-1);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Walk mapping table per process on host. */
-+ case VMCS_SM_CMD_HOST_WALK_PID_ALLOC:
-+ {
-+ struct vmcs_sm_ioctl_walk ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ vmcs_sm_host_walk_alloc(file_data);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Walk allocation per process on host. */
-+ case VMCS_SM_CMD_HOST_WALK_PID_MAP:
-+ {
-+ struct vmcs_sm_ioctl_walk ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ vmcs_sm_host_walk_map_per_pid(ioparam.pid);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Gets the size of the memory associated with a user handle. */
-+ case VMCS_SM_CMD_SIZE_USR_HANDLE:
-+ {
-+ struct vmcs_sm_ioctl_size ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource != NULL) {
-+ ioparam.size = resource->res_size;
-+ vmcs_sm_release_resource(resource, 0);
-+ } else {
-+ ioparam.size = 0;
-+ }
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Verify we are dealing with a valid resource. */
-+ case VMCS_SM_CMD_CHK_USR_HANDLE:
-+ {
-+ struct vmcs_sm_ioctl_chk ioparam;
-+
-+ /* Get parameter data.
-+ */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource == NULL)
-+ ret = -EINVAL;
-+ /* If the resource is cacheable, return additional
-+ * information that may be needed to flush the cache.
-+ */
-+ else if ((resource->res_cached == VMCS_SM_CACHE_HOST) ||
-+ (resource->res_cached == VMCS_SM_CACHE_BOTH)) {
-+ ioparam.addr =
-+ vmcs_sm_usr_address_from_pid_and_usr_handle
-+ (current->tgid, ioparam.handle);
-+ ioparam.size = resource->res_size;
-+ ioparam.cache = resource->res_cached;
-+ } else {
-+ ioparam.addr = 0;
-+ ioparam.size = 0;
-+ ioparam.cache = resource->res_cached;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /*
-+ * Maps a user handle given the process and the virtual address.
-+ */
-+ case VMCS_SM_CMD_MAPPED_USR_HANDLE:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ioparam.handle =
-+ vmcs_sm_usr_handle_from_pid_and_address(
-+ ioparam.pid, ioparam.addr);
-+
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if ((resource != NULL)
-+ && ((resource->res_cached == VMCS_SM_CACHE_HOST)
-+ || (resource->res_cached ==
-+ VMCS_SM_CACHE_BOTH))) {
-+ ioparam.size = resource->res_size;
-+ } else {
-+ ioparam.size = 0;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /*
-+ * Maps a videocore handle given process and virtual address.
-+ */
-+ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address(
-+ ioparam.pid, ioparam.addr);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Maps a videocore handle given process and user handle. */
-+ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource != NULL) {
-+ ioparam.handle = resource->res_handle;
-+ vmcs_sm_release_resource(resource, 0);
-+ } else {
-+ ioparam.handle = 0;
-+ }
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /*
-+ * Maps a videocore address given process and videocore handle.
-+ */
-+ case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+ if (resource != NULL) {
-+ ioparam.addr =
-+ (unsigned int)resource->res_base_mem;
-+ vmcs_sm_release_resource(resource, 0);
-+ } else {
-+ ioparam.addr = 0;
-+ }
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Maps a user address given process and vc handle.
-+ */
-+ case VMCS_SM_CMD_MAPPED_USR_ADDRESS:
-+ {
-+ struct vmcs_sm_ioctl_map ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /*
-+ * Return the address information from the mapping,
-+ * 0 (ie NULL) if it cannot locate the actual mapping.
-+ */
-+ ioparam.addr =
-+ vmcs_sm_usr_address_from_pid_and_usr_handle
-+ (ioparam.pid, ioparam.handle);
-+
-+ if (copy_to_user((void *)arg,
-+ &ioparam, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ }
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Flush the cache for a given mapping. */
-+ case VMCS_SM_CMD_FLUSH:
-+ {
-+ struct vmcs_sm_ioctl_cache ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID. */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+
-+ if ((resource != NULL) && resource->res_cached) {
-+ dma_addr_t phys_addr = 0;
-+
-+ resource->res_stats[FLUSH]++;
-+
-+ phys_addr =
-+ (dma_addr_t)((uint32_t)
-+ resource->res_base_mem &
-+ 0x3FFFFFFF);
-+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+ /* L1 cache flush */
-+ down_read(&current->mm->mmap_sem);
-+ vcsm_vma_cache_clean_page_range((unsigned long)
-+ ioparam.addr,
-+ (unsigned long)
-+ ioparam.addr +
-+ ioparam.size);
-+ up_read(&current->mm->mmap_sem);
-+
-+ /* L2 cache flush */
-+ outer_clean_range(phys_addr,
-+ phys_addr +
-+ (size_t) ioparam.size);
-+ } else if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ /* Done. */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Invalidate the cache for a given mapping. */
-+ case VMCS_SM_CMD_INVALID:
-+ {
-+ struct vmcs_sm_ioctl_cache ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+
-+ if ((resource != NULL) && resource->res_cached) {
-+ dma_addr_t phys_addr = 0;
-+
-+ resource->res_stats[INVALID]++;
-+
-+ phys_addr =
-+ (dma_addr_t)((uint32_t)
-+ resource->res_base_mem &
-+ 0x3FFFFFFF);
-+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+ /* L2 cache invalidate */
-+ outer_inv_range(phys_addr,
-+ phys_addr +
-+ (size_t) ioparam.size);
-+
-+ /* L1 cache invalidate */
-+ down_read(&current->mm->mmap_sem);
-+ vcsm_vma_cache_clean_page_range((unsigned long)
-+ ioparam.addr,
-+ (unsigned long)
-+ ioparam.addr +
-+ ioparam.size);
-+ up_read(&current->mm->mmap_sem);
-+ } else if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ /* Done.
-+ */
-+ goto out;
-+ }
-+ break;
-+
-+ /* Flush/Invalidate the cache for a given mapping. */
-+ case VMCS_SM_CMD_CLEAN_INVALID:
-+ {
-+ int i;
-+ struct vmcs_sm_ioctl_clean_invalid ioparam;
-+
-+ /* Get parameter data. */
-+ if (copy_from_user(&ioparam,
-+ (void *)arg, sizeof(ioparam)) != 0) {
-+ pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+ __func__, cmdnr);
-+ ret = -EFAULT;
-+ goto out;
-+ }
-+ for (i=0; i<sizeof ioparam.s/sizeof *ioparam.s; i++) {
-+ switch (ioparam.s[i].cmd) {
-+ default: case 0: break; /* NOOP */
-+ case 1: /* L1/L2 invalidate virtual range */
-+ case 2: /* L1/L2 clean physical range */
-+ case 3: /* L1/L2 clean+invalidate all */
-+ {
-+ /* Locate resource from GUID.
-+ */
-+ resource =
-+ vmcs_sm_acquire_resource(file_data, ioparam.s[i].handle);
-+
-+ if ((resource != NULL) && resource->res_cached) {
-+ unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE-1);
-+ unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE-1) & ~(PAGE_SIZE-1);
-+ resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID:FLUSH]++;
-+
-+ /* L1/L2 cache flush */
-+ down_read(&current->mm->mmap_sem);
-+ vcsm_vma_cache_clean_page_range(base, end);
-+ up_read(&current->mm->mmap_sem);
-+ } else if (resource == NULL) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ if (resource)
-+ vmcs_sm_release_resource(resource, 0);
-+ }
-+ break;
-+ }
-+ }
-+ }
-+ break;
-+
-+ default:
-+ {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ break;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/* Device operations that we managed in this driver.
-+*/
-+static const struct file_operations vmcs_sm_ops = {
-+ .owner = THIS_MODULE,
-+ .unlocked_ioctl = vc_sm_ioctl,
-+ .open = vc_sm_open,
-+ .release = vc_sm_release,
-+ .mmap = vc_sm_mmap,
-+};
-+
-+/* Creation of device.
-+*/
-+static int vc_sm_create_sharedmemory(void)
-+{
-+ int ret;
-+
-+ if (sm_state == NULL) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ /* Create a device class for creating dev nodes.
-+ */
-+ sm_state->sm_class = class_create(THIS_MODULE, "vc-sm");
-+ if (IS_ERR(sm_state->sm_class)) {
-+ pr_err("[%s]: unable to create device class\n", __func__);
-+ ret = PTR_ERR(sm_state->sm_class);
-+ goto out;
-+ }
-+
-+ /* Create a character driver.
-+ */
-+ ret = alloc_chrdev_region(&sm_state->sm_devid,
-+ DEVICE_MINOR, 1, DEVICE_NAME);
-+ if (ret != 0) {
-+ pr_err("[%s]: unable to allocate device number\n", __func__);
-+ goto out_dev_class_destroy;
-+ }
-+
-+ cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops);
-+ ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1);
-+ if (ret != 0) {
-+ pr_err("[%s]: unable to register device\n", __func__);
-+ goto out_chrdev_unreg;
-+ }
-+
-+ /* Create a device node.
-+ */
-+ sm_state->sm_dev = device_create(sm_state->sm_class,
-+ NULL,
-+ MKDEV(MAJOR(sm_state->sm_devid),
-+ DEVICE_MINOR), NULL,
-+ DEVICE_NAME);
-+ if (IS_ERR(sm_state->sm_dev)) {
-+ pr_err("[%s]: unable to create device node\n", __func__);
-+ ret = PTR_ERR(sm_state->sm_dev);
-+ goto out_chrdev_del;
-+ }
-+
-+ goto out;
-+
-+out_chrdev_del:
-+ cdev_del(&sm_state->sm_cdev);
-+out_chrdev_unreg:
-+ unregister_chrdev_region(sm_state->sm_devid, 1);
-+out_dev_class_destroy:
-+ class_destroy(sm_state->sm_class);
-+ sm_state->sm_class = NULL;
-+out:
-+ return ret;
-+}
-+
-+/* Termination of the device.
-+*/
-+static int vc_sm_remove_sharedmemory(void)
-+{
-+ int ret;
-+
-+ if (sm_state == NULL) {
-+ /* Nothing to do.
-+ */
-+ ret = 0;
-+ goto out;
-+ }
-+
-+ /* Remove the sharedmemory character driver.
-+ */
-+ cdev_del(&sm_state->sm_cdev);
-+
-+ /* Unregister region.
-+ */
-+ unregister_chrdev_region(sm_state->sm_devid, 1);
-+
-+ ret = 0;
-+ goto out;
-+
-+out:
-+ return ret;
-+}
-+
-+/* Videocore connected. */
-+static void vc_sm_connected_init(void)
-+{
-+ int ret;
-+ VCHI_INSTANCE_T vchi_instance;
-+ VCHI_CONNECTION_T *vchi_connection = NULL;
-+
-+ pr_info("[%s]: start\n", __func__);
-+
-+ /* Allocate memory for the state structure.
-+ */
-+ sm_state = kzalloc(sizeof(struct SM_STATE_T), GFP_KERNEL);
-+ if (sm_state == NULL) {
-+ pr_err("[%s]: failed to allocate memory\n", __func__);
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ mutex_init(&sm_state->lock);
-+ mutex_init(&sm_state->map_lock);
-+
-+ /* Initialize and create a VCHI connection for the shared memory service
-+ ** running on videocore.
-+ */
-+ ret = vchi_initialise(&vchi_instance);
-+ if (ret != 0) {
-+ pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+
-+ ret = vchi_connect(NULL, 0, vchi_instance);
-+ if (ret != 0) {
-+ pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+
-+ /* Initialize an instance of the shared memory service. */
-+ sm_state->sm_handle =
-+ vc_vchi_sm_init(vchi_instance, &vchi_connection, 1);
-+ if (sm_state->sm_handle == NULL) {
-+ pr_err("[%s]: failed to initialize shared memory service\n",
-+ __func__);
-+
-+ ret = -EPERM;
-+ goto err_free_mem;
-+ }
-+
-+ /* Create a debug fs directory entry (root). */
-+ sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL);
-+ if (!sm_state->dir_root) {
-+ pr_err("[%s]: failed to create \'%s\' directory entry\n",
-+ __func__, VC_SM_DIR_ROOT_NAME);
-+
-+ ret = -EPERM;
-+ goto err_stop_sm_service;
-+ }
-+
-+ sm_state->dir_state.show = &vc_sm_global_state_show;
-+ sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE,
-+ S_IRUGO, sm_state->dir_root, &sm_state->dir_state,
-+ &vc_sm_debug_fs_fops);
-+
-+ sm_state->dir_stats.show = &vc_sm_global_statistics_show;
-+ sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS,
-+ S_IRUGO, sm_state->dir_root, &sm_state->dir_stats,
-+ &vc_sm_debug_fs_fops);
-+
-+ /* Create the proc entry children. */
-+ sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME,
-+ sm_state->dir_root);
-+
-+ /* Create a shared memory device. */
-+ ret = vc_sm_create_sharedmemory();
-+ if (ret != 0) {
-+ pr_err("[%s]: failed to create shared memory device\n",
-+ __func__);
-+ goto err_remove_debugfs;
-+ }
-+
-+ INIT_LIST_HEAD(&sm_state->map_list);
-+ INIT_LIST_HEAD(&sm_state->resource_list);
-+
-+ sm_state->data_knl = vc_sm_create_priv_data(0);
-+ if (sm_state->data_knl == NULL) {
-+ pr_err("[%s]: failed to create kernel private data tracker\n",
-+ __func__);
-+ goto err_remove_shared_memory;
-+ }
-+
-+ /* Done!
-+ */
-+ sm_inited = 1;
-+ goto out;
-+
-+err_remove_shared_memory:
-+ vc_sm_remove_sharedmemory();
-+err_remove_debugfs:
-+ debugfs_remove_recursive(sm_state->dir_root);
-+err_stop_sm_service:
-+ vc_vchi_sm_stop(&sm_state->sm_handle);
-+err_free_mem:
-+ kfree(sm_state);
-+out:
-+ pr_info("[%s]: end - returning %d\n", __func__, ret);
-+}
-+
-+/* Driver loading. */
-+static int __init vc_sm_init(void)
-+{
-+ pr_info("vc-sm: Videocore shared memory driver\n");
-+ vchiq_add_connected_callback(vc_sm_connected_init);
-+ return 0;
-+}
-+
-+/* Driver unloading. */
-+static void __exit vc_sm_exit(void)
-+{
-+ pr_debug("[%s]: start\n", __func__);
-+ if (sm_inited) {
-+ /* Remove shared memory device.
-+ */
-+ vc_sm_remove_sharedmemory();
-+
-+ /* Remove all proc entries.
-+ */
-+ debugfs_remove_recursive(sm_state->dir_root);
-+
-+ /* Stop the videocore shared memory service.
-+ */
-+ vc_vchi_sm_stop(&sm_state->sm_handle);
-+
-+ /* Free the memory for the state structure.
-+ */
-+ mutex_destroy(&(sm_state->map_lock));
-+ kfree(sm_state);
-+ }
-+
-+ pr_debug("[%s]: end\n", __func__);
-+}
-+
-+#if defined(__KERNEL__)
-+/* Allocate a shared memory handle and block. */
-+int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle)
-+{
-+ struct vmcs_sm_ioctl_alloc ioparam = { 0 };
-+ int ret;
-+ struct SM_RESOURCE_T *resource;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || alloc == NULL || handle == NULL) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ ioparam.size = alloc->base_unit;
-+ ioparam.num = alloc->num_unit;
-+ ioparam.cached =
-+ alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0;
-+
-+ ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam);
-+
-+ if (ret == 0) {
-+ resource =
-+ vmcs_sm_acquire_resource(sm_state->data_knl,
-+ ioparam.handle);
-+ if (resource) {
-+ resource->pid = 0;
-+ vmcs_sm_release_resource(resource, 0);
-+
-+ /* Assign valid handle at this time.
-+ */
-+ *handle = ioparam.handle;
-+ } else {
-+ ret = -ENOMEM;
-+ }
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_alloc);
-+
-+/* Get an internal resource handle mapped from the external one.
-+*/
-+int vc_sm_int_handle(int handle)
-+{
-+ struct SM_RESOURCE_T *resource;
-+ int ret = 0;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return 0;
-+ }
-+
-+ /* Locate resource from GUID.
-+ */
-+ resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle);
-+ if (resource) {
-+ ret = resource->res_handle;
-+ vmcs_sm_release_resource(resource, 0);
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_int_handle);
-+
-+/* Free a previously allocated shared memory handle and block.
-+*/
-+int vc_sm_free(int handle)
-+{
-+ struct vmcs_sm_ioctl_free ioparam = { handle };
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ return vc_sm_ioctl_free(sm_state->data_knl, &ioparam);
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_free);
-+
-+/* Lock a memory handle for use by kernel.
-+*/
-+int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data)
-+{
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+ int ret;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0 || data == NULL) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ *data = 0;
-+
-+ ioparam.handle = handle;
-+ ret = vc_sm_ioctl_lock(sm_state->data_knl,
-+ &ioparam,
-+ 1,
-+ ((mode ==
-+ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
-+ VMCS_SM_CACHE_NONE), 0);
-+
-+ *data = ioparam.addr;
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_lock);
-+
-+/* Unlock a memory handle in use by kernel.
-+*/
-+int vc_sm_unlock(int handle, int flush, int no_vc_unlock)
-+{
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ ioparam.handle = handle;
-+ return vc_sm_ioctl_unlock(sm_state->data_knl,
-+ &ioparam, flush, 0, no_vc_unlock);
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_unlock);
-+
-+/* Map a shared memory region for use by kernel.
-+*/
-+int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode,
-+ long unsigned int *data)
-+{
-+ struct vmcs_sm_ioctl_lock_unlock ioparam;
-+ int ret;
-+
-+ /* Validate we can work with this device.
-+ */
-+ if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) {
-+ pr_err("[%s]: invalid input\n", __func__);
-+ return -EPERM;
-+ }
-+
-+ *data = 0;
-+
-+ ioparam.handle = handle;
-+ ret = vc_sm_ioctl_lock(sm_state->data_knl,
-+ &ioparam,
-+ 1,
-+ ((mode ==
-+ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
-+ VMCS_SM_CACHE_NONE), sm_addr);
-+
-+ *data = ioparam.addr;
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_map);
-+#endif
-+
-+late_initcall(vc_sm_init);
-+module_exit(vc_sm_exit);
-+
-+MODULE_AUTHOR("Broadcom");
-+MODULE_DESCRIPTION("VideoCore SharedMemory Driver");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/drivers/char/hw_random/bcm2708-rng.c linux-rpi/drivers/char/hw_random/bcm2708-rng.c
---- linux-3.18.14/drivers/char/hw_random/bcm2708-rng.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/char/hw_random/bcm2708-rng.c 2015-05-31 14:46:10.061660987 -0500
-@@ -0,0 +1,118 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/hw_random.h>
-+#include <linux/printk.h>
-+
-+#include <asm/io.h>
-+#include <mach/hardware.h>
-+#include <mach/platform.h>
-+
-+#define RNG_CTRL (0x0)
-+#define RNG_STATUS (0x4)
-+#define RNG_DATA (0x8)
-+#define RNG_FF_THRESHOLD (0xc)
-+
-+/* enable rng */
-+#define RNG_RBGEN 0x1
-+/* double speed, less random mode */
-+#define RNG_RBG2X 0x2
-+
-+/* the initial numbers generated are "less random" so will be discarded */
-+#define RNG_WARMUP_COUNT 0x40000
-+
-+static int bcm2708_rng_data_read(struct hwrng *rng, u32 *buffer)
-+{
-+ void __iomem *rng_base = (void __iomem *)rng->priv;
-+ unsigned words;
-+ /* wait for a random number to be in fifo */
-+ do {
-+ words = __raw_readl(rng_base + RNG_STATUS)>>24;
-+ }
-+ while (words == 0);
-+ /* read the random number */
-+ *buffer = __raw_readl(rng_base + RNG_DATA);
-+ return 4;
-+}
-+
-+static struct hwrng bcm2708_rng_ops = {
-+ .name = "bcm2708",
-+ .data_read = bcm2708_rng_data_read,
-+};
-+
-+static int __init bcm2708_rng_init(void)
-+{
-+ void __iomem *rng_base;
-+ int err;
-+
-+ /* map peripheral */
-+ rng_base = ioremap(RNG_BASE, 0x10);
-+ pr_info("bcm2708_rng_init=%p\n", rng_base);
-+ if (!rng_base) {
-+ pr_err("bcm2708_rng_init failed to ioremap\n");
-+ return -ENOMEM;
-+ }
-+ bcm2708_rng_ops.priv = (unsigned long)rng_base;
-+
-+ /* set warm-up count & enable */
-+ __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS);
-+ __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL);
-+
-+ /* register driver */
-+ err = hwrng_register(&bcm2708_rng_ops);
-+ if (err) {
-+ pr_err("bcm2708_rng_init hwrng_register()=%d\n", err);
-+ iounmap(rng_base);
-+ }
-+ return err;
-+}
-+
-+static void __exit bcm2708_rng_exit(void)
-+{
-+ void __iomem *rng_base = (void __iomem *)bcm2708_rng_ops.priv;
-+ pr_info("bcm2708_rng_exit\n");
-+ /* disable rng hardware */
-+ __raw_writel(0, rng_base + RNG_CTRL);
-+ /* unregister driver */
-+ hwrng_unregister(&bcm2708_rng_ops);
-+ iounmap(rng_base);
-+}
-+
-+module_init(bcm2708_rng_init);
-+module_exit(bcm2708_rng_exit);
-+
-+MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver");
-+MODULE_LICENSE("GPL and additional rights");
-diff -Nur linux-3.18.14/drivers/char/hw_random/Kconfig linux-rpi/drivers/char/hw_random/Kconfig
---- linux-3.18.14/drivers/char/hw_random/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/char/hw_random/Kconfig 2015-05-31 14:46:10.057660987 -0500
-@@ -320,6 +320,17 @@
-
- If unsure, say Y.
-
-+config HW_RANDOM_BCM2708
-+ tristate "BCM2708 generic true random number generator support"
-+ depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709)
-+ ---help---
-+ This driver provides the kernel-side support for the BCM2708 hardware.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called bcm2708-rng.
-+
-+ If unsure, say N.
-+
- config HW_RANDOM_MSM
- tristate "Qualcomm SoCs Random Number Generator support"
- depends on HW_RANDOM && ARCH_QCOM
-diff -Nur linux-3.18.14/drivers/char/hw_random/Makefile linux-rpi/drivers/char/hw_random/Makefile
---- linux-3.18.14/drivers/char/hw_random/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/char/hw_random/Makefile 2015-05-31 14:46:10.057660987 -0500
-@@ -28,5 +28,6 @@
- obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-rng.o
- obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
- obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
-+obj-$(CONFIG_HW_RANDOM_BCM2708) += bcm2708-rng.o
- obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
- obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
-diff -Nur linux-3.18.14/drivers/char/Kconfig linux-rpi/drivers/char/Kconfig
---- linux-3.18.14/drivers/char/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/char/Kconfig 2015-05-31 14:46:10.053660987 -0500
-@@ -581,6 +581,8 @@
-
- source "drivers/s390/char/Kconfig"
-
-+source "drivers/char/broadcom/Kconfig"
-+
- config MSM_SMD_PKT
- bool "Enable device interface for some SMD packet ports"
- default n
-diff -Nur linux-3.18.14/drivers/char/Makefile linux-rpi/drivers/char/Makefile
---- linux-3.18.14/drivers/char/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/char/Makefile 2015-05-31 14:46:10.053660987 -0500
-@@ -62,3 +62,4 @@
-
- obj-$(CONFIG_TILE_SROM) += tile-srom.o
- obj-$(CONFIG_XILLYBUS) += xillybus/
-+obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/
-diff -Nur linux-3.18.14/drivers/clocksource/arm_arch_timer.c linux-rpi/drivers/clocksource/arm_arch_timer.c
---- linux-3.18.14/drivers/clocksource/arm_arch_timer.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/clocksource/arm_arch_timer.c 2015-05-31 14:46:10.109660987 -0500
-@@ -795,3 +795,39 @@
- }
- CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
- arch_timer_mem_init);
-+
-+int __init dc4_arch_timer_init(void)
-+{
-+ if (arch_timers_present & ARCH_CP15_TIMER) {
-+ pr_warn("arch_timer: multiple nodes in dt, skipping\n");
-+ return -1;
-+ }
-+
-+ arch_timers_present |= ARCH_CP15_TIMER;
-+
-+ /* Try to determine the frequency from the device tree or CNTFRQ */
-+ arch_timer_rate = 19200000;
-+
-+ arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ;
-+ arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ;
-+ arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ;
-+ arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ;
-+
-+ /*
-+ * If HYP mode is available, we know that the physical timer
-+ * has been configured to be accessible from PL1. Use it, so
-+ * that a guest can use the virtual timer instead.
-+ *
-+ * If no interrupt provided for virtual timer, we'll have to
-+ * stick to the physical timer. It'd better be accessible...
-+ */
-+ if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
-+ arch_timer_use_virtual = false;
-+ }
-+
-+ arch_timer_c3stop = 0;
-+
-+ arch_timer_register();
-+ arch_timer_common_init();
-+ return 0;
-+}
-diff -Nur linux-3.18.14/drivers/cpufreq/bcm2835-cpufreq.c linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c
---- linux-3.18.14/drivers/cpufreq/bcm2835-cpufreq.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c 2015-05-31 14:46:10.117660987 -0500
-@@ -0,0 +1,224 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+/*****************************************************************************
-+* FILENAME: bcm2835-cpufreq.h
-+* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM
-+* processor. Messages are sent to Videocore either setting or requesting the
-+* frequency of the ARM in order to match an appropiate frequency to the current
-+* usage of the processor. The policy which selects the frequency to use is
-+* defined in the kernel .config file, but can be changed during runtime.
-+*****************************************************************************/
-+
-+/* ---------- INCLUDES ---------- */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <mach/vcio.h>
-+
-+/* ---------- DEFINES ---------- */
-+/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */
-+#define MODULE_NAME "bcm2835-cpufreq"
-+
-+#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */
-+
-+/* debug printk macros */
-+#ifdef CPUFREQ_DEBUG_ENABLE
-+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__)
-+
-+/* tag part of the message */
-+struct vc_msg_tag {
-+ uint32_t tag_id; /* the message id */
-+ uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */
-+ uint32_t data_size; /* amount of data being sent or received */
-+ uint32_t dev_id; /* the ID of the clock/voltage to get or set */
-+ uint32_t val; /* the value (e.g. rate (in Hz)) to set */
-+};
-+
-+/* message structure to be sent to videocore */
-+struct vc_msg {
-+ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */
-+ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */
-+ struct vc_msg_tag tag; /* the tag structure above to make */
-+ uint32_t end_tag; /* an end identifier, should be set to NULL */
-+};
-+
-+/* ---------- GLOBALS ---------- */
-+static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */
-+
-+static struct cpufreq_frequency_table bcm2835_freq_table[] = {
-+ {0, 0, 0},
-+ {0, 0, 0},
-+ {0, 0, CPUFREQ_TABLE_END},
-+};
-+
-+/*
-+ ===============================================
-+ clk_rate either gets or sets the clock rates.
-+ ===============================================
-+*/
-+static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate)
-+{
-+ int s, actual_rate=0;
-+ struct vc_msg msg;
-+
-+ /* wipe all previous message data */
-+ memset(&msg, 0, sizeof msg);
-+
-+ msg.msg_size = sizeof msg;
-+
-+ msg.tag.tag_id = VCMSG_SET_CLOCK_RATE;
-+ msg.tag.buffer_size = 8;
-+ msg.tag.data_size = 8; /* we're sending the clock ID and the new rates which is a total of 2 words */
-+ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK;
-+ msg.tag.val = arm_rate * 1000;
-+
-+ /* send the message */
-+ s = bcm_mailbox_property(&msg, sizeof msg);
-+
-+ /* check if it was all ok and return the rate in KHz */
-+ if (s == 0 && (msg.request_code & 0x80000000))
-+ actual_rate = msg.tag.val/1000;
-+
-+ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, actual_rate);
-+ return actual_rate;
-+}
-+
-+static uint32_t bcm2835_cpufreq_get_clock(int tag)
-+{
-+ int s;
-+ int arm_rate = 0;
-+ struct vc_msg msg;
-+
-+ /* wipe all previous message data */
-+ memset(&msg, 0, sizeof msg);
-+
-+ msg.msg_size = sizeof msg;
-+ msg.tag.tag_id = tag;
-+ msg.tag.buffer_size = 8;
-+ msg.tag.data_size = 4; /* we're just sending the clock ID which is one word long */
-+ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK;
-+
-+ /* send the message */
-+ s = bcm_mailbox_property(&msg, sizeof msg);
-+
-+ /* check if it was all ok and return the rate in KHz */
-+ if (s == 0 && (msg.request_code & 0x80000000))
-+ arm_rate = msg.tag.val/1000;
-+
-+ print_debug("%s frequency = %d\n",
-+ tag == VCMSG_GET_CLOCK_RATE ? "Current":
-+ tag == VCMSG_GET_MIN_CLOCK ? "Min":
-+ tag == VCMSG_GET_MAX_CLOCK ? "Max":
-+ "Unexpected", arm_rate);
-+
-+ return arm_rate;
-+}
-+
-+/*
-+ ====================================================
-+ Module Initialisation registers the cpufreq driver
-+ ====================================================
-+*/
-+static int __init bcm2835_cpufreq_module_init(void)
-+{
-+ print_debug("IN\n");
-+ return cpufreq_register_driver(&bcm2835_cpufreq_driver);
-+}
-+
-+/*
-+ =============
-+ Module exit
-+ =============
-+*/
-+static void __exit bcm2835_cpufreq_module_exit(void)
-+{
-+ print_debug("IN\n");
-+ cpufreq_unregister_driver(&bcm2835_cpufreq_driver);
-+ return;
-+}
-+
-+/*
-+ ==============================================================
-+ Initialisation function sets up the CPU policy for first use
-+ ==============================================================
-+*/
-+static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy)
-+{
-+ /* measured value of how long it takes to change frequency */
-+ const unsigned int transition_latency = 355000; /* ns */
-+
-+ /* now find out what the maximum and minimum frequencies are */
-+ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK);
-+ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK);
-+
-+ print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency);
-+ return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency);
-+}
-+
-+/*
-+ =====================================================================
-+ Target index function chooses the requested frequency from the table
-+ =====================================================================
-+*/
-+
-+static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state)
-+{
-+ unsigned int target_freq = bcm2835_freq_table[state].frequency;
-+ unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq);
-+
-+ if (!cur)
-+ {
-+ print_err("Error occurred setting a new frequency (%d)\n", target_freq);
-+ return -EINVAL;
-+ }
-+ print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur);
-+ return 0;
-+}
-+
-+/*
-+ ======================================================
-+ Get function returns the current frequency from table
-+ ======================================================
-+*/
-+
-+static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu)
-+{
-+ unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE);
-+ print_debug("%d: freq=%d\n", cpu, actual_rate);
-+ return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency;
-+}
-+
-+/* the CPUFreq driver */
-+static struct cpufreq_driver bcm2835_cpufreq_driver = {
-+ .name = "BCM2835 CPUFreq",
-+ .init = bcm2835_cpufreq_driver_init,
-+ .verify = cpufreq_generic_frequency_table_verify,
-+ .target_index = bcm2835_cpufreq_driver_target_index,
-+ .get = bcm2835_cpufreq_driver_get,
-+ .attr = cpufreq_generic_attr,
-+};
-+
-+MODULE_AUTHOR("Dorian Peake and Dom Cobley");
-+MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip");
-+MODULE_LICENSE("GPL");
-+
-+module_init(bcm2835_cpufreq_module_init);
-+module_exit(bcm2835_cpufreq_module_exit);
-diff -Nur linux-3.18.14/drivers/cpufreq/Kconfig.arm linux-rpi/drivers/cpufreq/Kconfig.arm
---- linux-3.18.14/drivers/cpufreq/Kconfig.arm 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/cpufreq/Kconfig.arm 2015-05-31 14:46:10.113660987 -0500
-@@ -241,6 +241,14 @@
- help
- This adds the CPUFreq driver support for SPEAr SOCs.
-
-+config ARM_BCM2835_CPUFREQ
-+ bool "BCM2835 Driver"
-+ default y
-+ help
-+ This adds the CPUFreq driver for BCM2835
-+
-+ If in doubt, say N.
-+
- config ARM_TEGRA_CPUFREQ
- bool "TEGRA CPUFreq support"
- depends on ARCH_TEGRA
-diff -Nur linux-3.18.14/drivers/cpufreq/Makefile linux-rpi/drivers/cpufreq/Makefile
---- linux-3.18.14/drivers/cpufreq/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/cpufreq/Makefile 2015-05-31 14:46:10.113660987 -0500
-@@ -75,6 +75,7 @@
- obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o
- obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
- obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
-+obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o
- obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
-
-diff -Nur linux-3.18.14/drivers/dma/bcm2708-dmaengine.c linux-rpi/drivers/dma/bcm2708-dmaengine.c
---- linux-3.18.14/drivers/dma/bcm2708-dmaengine.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/dma/bcm2708-dmaengine.c 2015-05-31 14:46:10.161660986 -0500
-@@ -0,0 +1,1060 @@
-+/*
-+ * BCM2835 DMA engine support
-+ *
-+ * This driver supports cyclic and scatter/gather DMA transfers.
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Gellert Weisz <gellert@raspberrypi.org>
-+ * Copyright 2013-2014
-+ *
-+ * Based on
-+ * OMAP DMAengine support by Russell King
-+ *
-+ * BCM2708 DMA Driver
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * Raspberry Pi PCM I2S ALSA Driver
-+ * Copyright (c) by Phil Poole 2013
-+ *
-+ * MARVELL MMP Peripheral DMA Driver
-+ * Copyright 2012 Marvell International Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/spinlock.h>
-+
-+#ifndef CONFIG_ARCH_BCM2835
-+
-+/* dma manager */
-+#include <mach/dma.h>
-+
-+//#define DMA_COMPLETE DMA_SUCCESS
-+
-+#endif
-+
-+#include <linux/of.h>
-+#include <linux/of_dma.h>
-+
-+#include "virt-dma.h"
-+
-+static unsigned dma_debug;
-+
-+struct bcm2835_dmadev {
-+ struct dma_device ddev;
-+ spinlock_t lock;
-+ void __iomem *base;
-+ struct device_dma_parameters dma_parms;
-+};
-+
-+struct bcm2835_dma_cb {
-+ uint32_t info;
-+ uint32_t src;
-+ uint32_t dst;
-+ uint32_t length;
-+ uint32_t stride;
-+ uint32_t next;
-+ uint32_t pad[2];
-+};
-+
-+struct bcm2835_chan {
-+ struct virt_dma_chan vc;
-+ struct list_head node;
-+
-+ struct dma_slave_config cfg;
-+ bool cyclic;
-+
-+ int ch;
-+ struct bcm2835_desc *desc;
-+
-+ void __iomem *chan_base;
-+ int irq_number;
-+
-+ unsigned int dreq;
-+};
-+
-+struct bcm2835_desc {
-+ struct virt_dma_desc vd;
-+ enum dma_transfer_direction dir;
-+
-+ unsigned int control_block_size;
-+ struct bcm2835_dma_cb *control_block_base;
-+ dma_addr_t control_block_base_phys;
-+
-+ unsigned int frames;
-+ size_t size;
-+};
-+
-+#define BCM2835_DMA_CS 0x00
-+#define BCM2835_DMA_ADDR 0x04
-+#define BCM2835_DMA_SOURCE_AD 0x0c
-+#define BCM2835_DMA_DEST_AD 0x10
-+#define BCM2835_DMA_NEXTCB 0x1C
-+
-+/* DMA CS Control and Status bits */
-+#define BCM2835_DMA_ACTIVE BIT(0)
-+#define BCM2835_DMA_INT BIT(2)
-+#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
-+#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
-+#define BCM2835_DMA_ERR BIT(8)
-+#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
-+#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
-+
-+#define BCM2835_DMA_INT_EN BIT(0)
-+#define BCM2835_DMA_WAIT_RESP BIT(3)
-+#define BCM2835_DMA_D_INC BIT(4)
-+#define BCM2835_DMA_D_WIDTH BIT(5)
-+#define BCM2835_DMA_D_DREQ BIT(6)
-+#define BCM2835_DMA_S_INC BIT(8)
-+#define BCM2835_DMA_S_WIDTH BIT(9)
-+#define BCM2835_DMA_S_DREQ BIT(10)
-+
-+#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
-+#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21)
-+
-+#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
-+
-+#define BCM2835_DMA_DATA_TYPE_S8 1
-+#define BCM2835_DMA_DATA_TYPE_S16 2
-+#define BCM2835_DMA_DATA_TYPE_S32 4
-+#define BCM2835_DMA_DATA_TYPE_S128 16
-+
-+#define BCM2835_DMA_BULK_MASK BIT(0)
-+#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
-+
-+
-+/* Valid only for channels 0 - 14, 15 has its own base address */
-+#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
-+#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
-+
-+#define MAX_LITE_TRANSFER 32768
-+#define MAX_NORMAL_TRANSFER 1073741824
-+
-+static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
-+{
-+ return container_of(d, struct bcm2835_dmadev, ddev);
-+}
-+
-+static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
-+{
-+ return container_of(c, struct bcm2835_chan, vc.chan);
-+}
-+
-+static inline struct bcm2835_desc *to_bcm2835_dma_desc(
-+ struct dma_async_tx_descriptor *t)
-+{
-+ return container_of(t, struct bcm2835_desc, vd.tx);
-+}
-+
-+static void dma_dumpregs(struct bcm2835_chan *c)
-+{
-+ pr_debug("-------------DMA DUMPREGS-------------\n");
-+ pr_debug("CS= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_CS));
-+ pr_debug("ADDR= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_ADDR));
-+ pr_debug("SOURCE_ADDR= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_SOURCE_AD));
-+ pr_debug("DEST_AD= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_DEST_AD));
-+ pr_debug("NEXTCB= %u\n",
-+ readl(c->chan_base + BCM2835_DMA_NEXTCB));
-+ pr_debug("--------------------------------------\n");
-+}
-+
-+static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
-+{
-+ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
-+ dma_free_coherent(desc->vd.tx.chan->device->dev,
-+ desc->control_block_size,
-+ desc->control_block_base,
-+ desc->control_block_base_phys);
-+ kfree(desc);
-+}
-+
-+static int bcm2835_dma_abort(void __iomem *chan_base)
-+{
-+ unsigned long cs;
-+ long int timeout = 10000;
-+
-+ cs = readl(chan_base + BCM2835_DMA_CS);
-+ if (!(cs & BCM2835_DMA_ACTIVE))
-+ return 0;
-+
-+ /* Write 0 to the active bit - Pause the DMA */
-+ writel(0, chan_base + BCM2835_DMA_CS);
-+
-+ /* Wait for any current AXI transfer to complete */
-+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
-+ cpu_relax();
-+ cs = readl(chan_base + BCM2835_DMA_CS);
-+ }
-+
-+ /* We'll un-pause when we set of our next DMA */
-+ if (!timeout)
-+ return -ETIMEDOUT;
-+
-+ if (!(cs & BCM2835_DMA_ACTIVE))
-+ return 0;
-+
-+ /* Terminate the control block chain */
-+ writel(0, chan_base + BCM2835_DMA_NEXTCB);
-+
-+ /* Abort the whole DMA */
-+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
-+ chan_base + BCM2835_DMA_CS);
-+
-+ return 0;
-+}
-+
-+
-+static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
-+{
-+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
-+ struct bcm2835_desc *d;
-+
-+ if (!vd) {
-+ c->desc = NULL;
-+ return;
-+ }
-+
-+ list_del(&vd->node);
-+
-+ c->desc = d = to_bcm2835_dma_desc(&vd->tx);
-+
-+ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
-+ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
-+
-+}
-+
-+static irqreturn_t bcm2835_dma_callback(int irq, void *data)
-+{
-+ struct bcm2835_chan *c = data;
-+ struct bcm2835_desc *d;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+
-+ /* Acknowledge interrupt */
-+ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
-+
-+ d = c->desc;
-+
-+ if (d) {
-+ if (c->cyclic) {
-+ vchan_cyclic_callback(&d->vd);
-+
-+ /* Keep the DMA engine running */
-+ writel(BCM2835_DMA_ACTIVE,
-+ c->chan_base + BCM2835_DMA_CS);
-+
-+ } else {
-+ vchan_cookie_complete(&c->desc->vd);
-+ bcm2835_dma_start_desc(c);
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ int ret;
-+
-+ dev_dbg(c->vc.chan.device->dev,
-+ "Allocating DMA channel %d\n", c->ch);
-+
-+ ret = request_irq(c->irq_number,
-+ bcm2835_dma_callback, 0, "DMA IRQ", c);
-+
-+ return ret;
-+}
-+
-+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+
-+ vchan_free_chan_resources(&c->vc);
-+ free_irq(c->irq_number, c);
-+
-+ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
-+}
-+
-+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
-+{
-+ return d->size;
-+}
-+
-+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
-+{
-+ unsigned int i;
-+ size_t size;
-+
-+ for (size = i = 0; i < d->frames; i++) {
-+ struct bcm2835_dma_cb *control_block =
-+ &d->control_block_base[i];
-+ size_t this_size = control_block->length;
-+ dma_addr_t dma;
-+
-+ if (d->dir == DMA_DEV_TO_MEM)
-+ dma = control_block->dst;
-+ else
-+ dma = control_block->src;
-+
-+ if (size)
-+ size += this_size;
-+ else if (addr >= dma && addr < dma + this_size)
-+ size += dma + this_size - addr;
-+ }
-+
-+ return size;
-+}
-+
-+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
-+ dma_cookie_t cookie, struct dma_tx_state *txstate)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ struct bcm2835_desc *d;
-+ struct virt_dma_desc *vd;
-+ enum dma_status ret;
-+ unsigned long flags;
-+ dma_addr_t pos;
-+
-+ ret = dma_cookie_status(chan, cookie, txstate);
-+ if (ret == DMA_COMPLETE || !txstate)
-+ return ret;
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+ vd = vchan_find_desc(&c->vc, cookie);
-+ if (vd) {
-+ txstate->residue =
-+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
-+ } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
-+ d = c->desc;
-+
-+ if (d->dir == DMA_MEM_TO_DEV)
-+ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
-+ else if (d->dir == DMA_DEV_TO_MEM)
-+ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
-+ else
-+ pos = 0;
-+
-+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
-+ } else {
-+ txstate->residue = 0;
-+ }
-+
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+
-+ return ret;
-+}
-+
-+static void bcm2835_dma_issue_pending(struct dma_chan *chan)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+ if (vchan_issue_pending(&c->vc) && !c->desc)
-+ bcm2835_dma_start_desc(c);
-+
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+}
-+
-+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
-+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
-+ size_t period_len, enum dma_transfer_direction direction,
-+ unsigned long flags)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ enum dma_slave_buswidth dev_width;
-+ struct bcm2835_desc *d;
-+ dma_addr_t dev_addr;
-+ unsigned int es, sync_type;
-+ unsigned int frame, max_size;
-+
-+ /* Grab configuration */
-+ if (!is_slave_direction(direction)) {
-+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
-+ return NULL;
-+ }
-+
-+ if (direction == DMA_DEV_TO_MEM) {
-+ dev_addr = c->cfg.src_addr;
-+ dev_width = c->cfg.src_addr_width;
-+ sync_type = BCM2835_DMA_S_DREQ;
-+ } else {
-+ dev_addr = c->cfg.dst_addr;
-+ dev_width = c->cfg.dst_addr_width;
-+ sync_type = BCM2835_DMA_D_DREQ;
-+ }
-+
-+ /* Bus width translates to the element size (ES) */
-+ switch (dev_width) {
-+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
-+ es = BCM2835_DMA_DATA_TYPE_S32;
-+ break;
-+ default:
-+ return NULL;
-+ }
-+
-+ /* Now allocate and setup the descriptor. */
-+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
-+ if (!d)
-+ return NULL;
-+
-+ d->dir = direction;
-+
-+ if (c->ch >= 8) /* we have a LITE channel */
-+ max_size = MAX_LITE_TRANSFER;
-+ else
-+ max_size = MAX_NORMAL_TRANSFER;
-+ period_len = min(period_len, max_size);
-+
-+ d->frames = (buf_len-1) / period_len + 1;
-+
-+ /* Allocate memory for control blocks */
-+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
-+ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
-+ d->control_block_size, &d->control_block_base_phys,
-+ GFP_NOWAIT);
-+
-+ if (!d->control_block_base) {
-+ kfree(d);
-+ return NULL;
-+ }
-+
-+ /*
-+ * Iterate over all frames, create a control block
-+ * for each frame and link them together.
-+ */
-+ for (frame = 0; frame < d->frames; frame++) {
-+ struct bcm2835_dma_cb *control_block =
-+ &d->control_block_base[frame];
-+
-+ /* Setup adresses */
-+ if (d->dir == DMA_DEV_TO_MEM) {
-+ control_block->info = BCM2835_DMA_D_INC;
-+ control_block->src = dev_addr;
-+ control_block->dst = buf_addr + frame * period_len;
-+ } else {
-+ control_block->info = BCM2835_DMA_S_INC;
-+ control_block->src = buf_addr + frame * period_len;
-+ control_block->dst = dev_addr;
-+ }
-+
-+ /* Enable interrupt */
-+ control_block->info |= BCM2835_DMA_INT_EN;
-+
-+ /* Setup synchronization */
-+ if (sync_type != 0)
-+ control_block->info |= sync_type;
-+
-+ /* Setup DREQ channel */
-+ if (c->cfg.slave_id != 0)
-+ control_block->info |=
-+ BCM2835_DMA_PER_MAP(c->cfg.slave_id);
-+
-+ /* Length of a frame */
-+ if (frame != d->frames-1)
-+ control_block->length = period_len;
-+ else
-+ control_block->length = buf_len - (d->frames - 1) * period_len;
-+
-+ d->size += control_block->length;
-+
-+ /*
-+ * Next block is the next frame.
-+ * This function is called on cyclic DMA transfers.
-+ * Therefore, wrap around at number of frames.
-+ */
-+ control_block->next = d->control_block_base_phys +
-+ sizeof(struct bcm2835_dma_cb)
-+ * ((frame + 1) % d->frames);
-+ }
-+
-+ c->cyclic = true;
-+
-+ return vchan_tx_prep(&c->vc, &d->vd, flags);
-+}
-+
-+
-+static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
-+ struct dma_chan *chan, struct scatterlist *sgl,
-+ unsigned int sg_len, enum dma_transfer_direction direction,
-+ unsigned long flags, void *context)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+ enum dma_slave_buswidth dev_width;
-+ struct bcm2835_desc *d;
-+ dma_addr_t dev_addr;
-+ struct scatterlist *sgent;
-+ unsigned int es, sync_type;
-+ unsigned int i, j, splitct, max_size;
-+
-+ if (!is_slave_direction(direction)) {
-+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
-+ return NULL;
-+ }
-+
-+ if (direction == DMA_DEV_TO_MEM) {
-+ dev_addr = c->cfg.src_addr;
-+ dev_width = c->cfg.src_addr_width;
-+ sync_type = BCM2835_DMA_S_DREQ;
-+ } else {
-+ dev_addr = c->cfg.dst_addr;
-+ dev_width = c->cfg.dst_addr_width;
-+ sync_type = BCM2835_DMA_D_DREQ;
-+ }
-+
-+ /* Bus width translates to the element size (ES) */
-+ switch (dev_width) {
-+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
-+ es = BCM2835_DMA_DATA_TYPE_S32;
-+ break;
-+ default:
-+ return NULL;
-+ }
-+
-+ /* Now allocate and setup the descriptor. */
-+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
-+ if (!d)
-+ return NULL;
-+
-+ d->dir = direction;
-+
-+ if (c->ch >= 8) /* we have a LITE channel */
-+ max_size = MAX_LITE_TRANSFER;
-+ else
-+ max_size = MAX_NORMAL_TRANSFER;
-+
-+ /* We store the length of the SG list in d->frames
-+ taking care to account for splitting up transfers
-+ too large for a LITE channel */
-+
-+ d->frames = 0;
-+ for_each_sg(sgl, sgent, sg_len, i) {
-+ uint32_t len = sg_dma_len(sgent);
-+ d->frames += 1 + len / max_size;
-+ }
-+
-+ /* Allocate memory for control blocks */
-+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
-+ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
-+ d->control_block_size, &d->control_block_base_phys,
-+ GFP_NOWAIT);
-+
-+ if (!d->control_block_base) {
-+ kfree(d);
-+ return NULL;
-+ }
-+
-+ /*
-+ * Iterate over all SG entries, create a control block
-+ * for each frame and link them together.
-+ */
-+
-+ /* we count the number of times an SG entry had to be splitct
-+ as a result of using a LITE channel */
-+ splitct = 0;
-+
-+ for_each_sg(sgl, sgent, sg_len, i) {
-+ dma_addr_t addr = sg_dma_address(sgent);
-+ uint32_t len = sg_dma_len(sgent);
-+
-+ for (j = 0; j < len; j += max_size) {
-+ u32 waits = SDHCI_BCM_DMA_WAITS;
-+ struct bcm2835_dma_cb *control_block =
-+ &d->control_block_base[i+splitct];
-+
-+ /* Setup adresses */
-+ if (d->dir == DMA_DEV_TO_MEM) {
-+ control_block->info = BCM2835_DMA_D_INC |
-+ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ;
-+ control_block->src = dev_addr;
-+ control_block->dst = addr + (dma_addr_t)j;
-+ } else {
-+ control_block->info = BCM2835_DMA_S_INC |
-+ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ;
-+ control_block->src = addr + (dma_addr_t)j;
-+ control_block->dst = dev_addr;
-+ }
-+
-+ /* Common part */
-+ if ((dma_debug >> 0) & 0x1f)
-+ waits = (dma_debug >> 0) & 0x1f;
-+ control_block->info |= BCM2835_DMA_WAITS(waits);
-+ control_block->info |= BCM2835_DMA_WAIT_RESP;
-+
-+ /* Enable */
-+ if (i == sg_len-1 && len-j <= max_size)
-+ control_block->info |= BCM2835_DMA_INT_EN;
-+
-+ /* Setup synchronization */
-+ if (sync_type != 0)
-+ control_block->info |= sync_type;
-+
-+ /* Setup DREQ channel */
-+ c->dreq = c->cfg.slave_id; /* DREQ loaded from config */
-+
-+ if (c->dreq != 0)
-+ control_block->info |=
-+ BCM2835_DMA_PER_MAP(c->dreq);
-+
-+ /* Length of a frame */
-+ control_block->length = min(len-j, max_size);
-+ d->size += control_block->length;
-+
-+ /*
-+ * Next block is the next frame.
-+ */
-+ if (i < sg_len-1 || len-j > max_size) {
-+ /* next block is the next frame. */
-+ control_block->next = d->control_block_base_phys +
-+ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1);
-+ } else {
-+ /* next block is empty. */
-+ control_block->next = 0;
-+ }
-+
-+ if (len-j > max_size)
-+ splitct++;
-+ }
-+ }
-+
-+ c->cyclic = false;
-+
-+ return vchan_tx_prep(&c->vc, &d->vd, flags);
-+}
-+
-+static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
-+ struct dma_slave_config *cfg)
-+{
-+ if ((cfg->direction == DMA_DEV_TO_MEM &&
-+ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
-+ (cfg->direction == DMA_MEM_TO_DEV &&
-+ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
-+ !is_slave_direction(cfg->direction)) {
-+ return -EINVAL;
-+ }
-+
-+ c->cfg = *cfg;
-+
-+ return 0;
-+}
-+
-+static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
-+{
-+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
-+ unsigned long flags;
-+ int timeout = 10000;
-+ LIST_HEAD(head);
-+
-+ spin_lock_irqsave(&c->vc.lock, flags);
-+
-+ /* Prevent this channel being scheduled */
-+ spin_lock(&d->lock);
-+ list_del_init(&c->node);
-+ spin_unlock(&d->lock);
-+
-+ /*
-+ * Stop DMA activity: we assume the callback will not be called
-+ * after bcm_dma_abort() returns (even if it does, it will see
-+ * c->desc is NULL and exit.)
-+ */
-+ if (c->desc) {
-+ c->desc = NULL;
-+ bcm2835_dma_abort(c->chan_base);
-+
-+ /* Wait for stopping */
-+ while (--timeout) {
-+ if (!(readl(c->chan_base + BCM2835_DMA_CS) &
-+ BCM2835_DMA_ACTIVE))
-+ break;
-+
-+ cpu_relax();
-+ }
-+
-+ if (!timeout)
-+ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
-+ }
-+
-+ vchan_get_all_descriptors(&c->vc, &head);
-+ spin_unlock_irqrestore(&c->vc.lock, flags);
-+ vchan_dma_desc_free_list(&c->vc, &head);
-+
-+ return 0;
-+}
-+
-+static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-+ unsigned long arg)
-+{
-+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
-+
-+ switch (cmd) {
-+ case DMA_SLAVE_CONFIG:
-+ return bcm2835_dma_slave_config(c,
-+ (struct dma_slave_config *)arg);
-+
-+ case DMA_TERMINATE_ALL:
-+ return bcm2835_dma_terminate_all(c);
-+
-+ default:
-+ return -ENXIO;
-+ }
-+}
-+
-+#ifdef CONFIG_ARCH_BCM2835
-+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
-+{
-+ struct bcm2835_chan *c;
-+
-+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
-+ if (!c)
-+ return -ENOMEM;
-+
-+ c->vc.desc_free = bcm2835_dma_desc_free;
-+ vchan_init(&c->vc, &d->ddev);
-+ INIT_LIST_HEAD(&c->node);
-+
-+ d->ddev.chancnt++;
-+
-+ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
-+ c->ch = chan_id;
-+ c->irq_number = irq;
-+
-+ return 0;
-+}
-+#endif
-+
-+static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d,
-+ void __iomem *chan_base, int chan_id, int irq)
-+{
-+ struct bcm2835_chan *c;
-+
-+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
-+ if (!c)
-+ return -ENOMEM;
-+
-+ c->vc.desc_free = bcm2835_dma_desc_free;
-+ vchan_init(&c->vc, &d->ddev);
-+ INIT_LIST_HEAD(&c->node);
-+
-+ d->ddev.chancnt++;
-+
-+ c->chan_base = chan_base;
-+ c->ch = chan_id;
-+ c->irq_number = irq;
-+
-+ return 0;
-+}
-+
-+
-+static void bcm2835_dma_free(struct bcm2835_dmadev *od)
-+{
-+ struct bcm2835_chan *c, *next;
-+
-+ list_for_each_entry_safe(c, next, &od->ddev.channels,
-+ vc.chan.device_node) {
-+ list_del(&c->vc.chan.device_node);
-+ tasklet_kill(&c->vc.task);
-+ }
-+}
-+
-+static const struct of_device_id bcm2835_dma_of_match[] = {
-+ { .compatible = "brcm,bcm2835-dma", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
-+
-+#ifdef CONFIG_ARCH_BCM2835
-+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
-+ struct of_dma *ofdma)
-+{
-+ struct bcm2835_dmadev *d = ofdma->of_dma_data;
-+ struct dma_chan *chan;
-+
-+ chan = dma_get_any_slave_channel(&d->ddev);
-+ if (!chan)
-+ return NULL;
-+
-+ /* Set DREQ from param */
-+ to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
-+
-+ return chan;
-+}
-+#endif
-+
-+static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
-+ struct dma_slave_caps *caps)
-+{
-+ caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
-+ caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
-+ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
-+ caps->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
-+ caps->cmd_pause = false;
-+ caps->cmd_terminate = true;
-+
-+ return 0;
-+}
-+
-+static int bcm2835_dma_probe(struct platform_device *pdev)
-+{
-+ struct bcm2835_dmadev *od;
-+#ifdef CONFIG_ARCH_BCM2835
-+ struct resource *res;
-+ void __iomem *base;
-+ uint32_t chans_available;
-+#endif
-+ int rc;
-+ int i;
-+ int irq;
-+
-+
-+ if (!pdev->dev.dma_mask)
-+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
-+
-+ /* If CONFIG_ARCH_BCM2835 is selected, device tree is used */
-+ /* hence the difference between probing */
-+
-+#ifndef CONFIG_ARCH_BCM2835
-+
-+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
-+ if (rc)
-+ return rc;
-+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-+
-+
-+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
-+ if (!od)
-+ return -ENOMEM;
-+
-+ pdev->dev.dma_parms = &od->dma_parms;
-+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
-+
-+
-+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
-+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
-+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
-+ od->ddev.device_tx_status = bcm2835_dma_tx_status;
-+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
-+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
-+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
-+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
-+ od->ddev.device_control = bcm2835_dma_control;
-+ od->ddev.dev = &pdev->dev;
-+ INIT_LIST_HEAD(&od->ddev.channels);
-+ spin_lock_init(&od->lock);
-+
-+ platform_set_drvdata(pdev, od);
-+
-+ for (i = 0; i < 5; i++) {
-+ void __iomem *chan_base;
-+ int chan_id;
-+
-+ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE,
-+ &chan_base,
-+ &irq);
-+
-+ if (chan_id < 0)
-+ break;
-+
-+ rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
-+ if (rc)
-+ goto err_no_dma;
-+ }
-+#else
-+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
-+ if (rc)
-+ return rc;
-+
-+
-+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
-+ if (!od)
-+ return -ENOMEM;
-+
-+ pdev->dev.dma_parms = &od->dma_parms;
-+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
-+
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ od->base = base;
-+
-+
-+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
-+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
-+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
-+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
-+ od->ddev.device_tx_status = bcm2835_dma_tx_status;
-+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
-+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
-+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
-+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
-+ od->ddev.device_control = bcm2835_dma_control;
-+ od->ddev.dev = &pdev->dev;
-+ INIT_LIST_HEAD(&od->ddev.channels);
-+ spin_lock_init(&od->lock);
-+
-+ platform_set_drvdata(pdev, od);
-+
-+
-+ /* Request DMA channel mask from device tree */
-+ if (of_property_read_u32(pdev->dev.of_node,
-+ "brcm,dma-channel-mask",
-+ &chans_available)) {
-+ dev_err(&pdev->dev, "Failed to get channel mask\n");
-+ rc = -EINVAL;
-+ goto err_no_dma;
-+ }
-+
-+
-+ /*
-+ * Do not use the FIQ and BULK channels,
-+ * because they are used by the GPU.
-+ */
-+ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
-+
-+
-+ for (i = 0; i < pdev->num_resources; i++) {
-+ irq = platform_get_irq(pdev, i);
-+ if (irq < 0)
-+ break;
-+
-+ if (chans_available & (1 << i)) {
-+ rc = bcm2835_dma_chan_init(od, i, irq);
-+ if (rc)
-+ goto err_no_dma;
-+ }
-+ }
-+
-+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
-+
-+ /* Device-tree DMA controller registration */
-+ rc = of_dma_controller_register(pdev->dev.of_node,
-+ bcm2835_dma_xlate, od);
-+ if (rc) {
-+ dev_err(&pdev->dev, "Failed to register DMA controller\n");
-+ goto err_no_dma;
-+ }
-+#endif
-+
-+ rc = dma_async_device_register(&od->ddev);
-+ if (rc) {
-+ dev_err(&pdev->dev,
-+ "Failed to register slave DMA engine device: %d\n", rc);
-+ goto err_no_dma;
-+ }
-+
-+ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n");
-+ if (dma_debug)
-+ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug);
-+
-+ return 0;
-+
-+err_no_dma:
-+ bcm2835_dma_free(od);
-+ return rc;
-+}
-+
-+static int bcm2835_dma_remove(struct platform_device *pdev)
-+{
-+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
-+
-+ dma_async_device_unregister(&od->ddev);
-+ bcm2835_dma_free(od);
-+
-+ return 0;
-+}
-+
-+#ifndef CONFIG_ARCH_BCM2835
-+
-+
-+static struct platform_driver bcm2835_dma_driver = {
-+ .probe = bcm2835_dma_probe,
-+ .remove = bcm2835_dma_remove,
-+ .driver = {
-+ .name = "bcm2708-dmaengine",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_device *pdev;
-+
-+static const struct platform_device_info bcm2835_dma_dev_info = {
-+ .name = "bcm2708-dmaengine",
-+ .id = -1,
-+};
-+
-+static int bcm2835_dma_init(void)
-+{
-+ int rc = platform_driver_register(&bcm2835_dma_driver);
-+
-+ if (rc == 0) {
-+ pdev = platform_device_register_full(&bcm2835_dma_dev_info);
-+ if (IS_ERR(pdev)) {
-+ platform_driver_unregister(&bcm2835_dma_driver);
-+ rc = PTR_ERR(pdev);
-+ }
-+ }
-+
-+ return rc;
-+}
-+module_init(bcm2835_dma_init); /* preferable to subsys_initcall */
-+
-+static void __exit bcm2835_dma_exit(void)
-+{
-+ platform_device_unregister(pdev);
-+ platform_driver_unregister(&bcm2835_dma_driver);
-+}
-+module_exit(bcm2835_dma_exit);
-+
-+#else
-+
-+static struct platform_driver bcm2835_dma_driver = {
-+ .probe = bcm2835_dma_probe,
-+ .remove = bcm2835_dma_remove,
-+ .driver = {
-+ .name = "bcm2835-dma",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(bcm2835_dma_of_match),
-+ },
-+};
-+
-+module_platform_driver(bcm2835_dma_driver);
-+
-+#endif
-+
-+module_param(dma_debug, uint, 0644);
-+MODULE_ALIAS("platform:bcm2835-dma");
-+MODULE_DESCRIPTION("BCM2835 DMA engine driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/drivers/dma/Kconfig linux-rpi/drivers/dma/Kconfig
---- linux-3.18.14/drivers/dma/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/dma/Kconfig 2015-05-31 14:46:10.157660987 -0500
-@@ -330,6 +330,12 @@
- select DMA_ENGINE
- select DMA_VIRTUAL_CHANNELS
-
-+config DMA_BCM2708
-+ tristate "BCM2708 DMA engine support"
-+ depends on MACH_BCM2708 || MACH_BCM2709
-+ select DMA_ENGINE
-+ select DMA_VIRTUAL_CHANNELS
-+
- config TI_CPPI41
- tristate "AM33xx CPPI41 DMA support"
- depends on ARCH_OMAP
-diff -Nur linux-3.18.14/drivers/dma/Makefile linux-rpi/drivers/dma/Makefile
---- linux-3.18.14/drivers/dma/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/dma/Makefile 2015-05-31 14:46:10.157660987 -0500
-@@ -38,6 +38,7 @@
- obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
- obj-$(CONFIG_DMA_OMAP) += omap-dma.o
- obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
-+obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
- obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
- obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
- obj-$(CONFIG_TI_CPPI41) += cppi41.o
-diff -Nur linux-3.18.14/drivers/hid/usbhid/hid-core.c linux-rpi/drivers/hid/usbhid/hid-core.c
---- linux-3.18.14/drivers/hid/usbhid/hid-core.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/hid/usbhid/hid-core.c 2015-05-31 14:46:10.457660983 -0500
-@@ -49,7 +49,7 @@
- * Module parameters.
- */
-
--static unsigned int hid_mousepoll_interval;
-+static unsigned int hid_mousepoll_interval = ~0;
- module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644);
- MODULE_PARM_DESC(mousepoll, "Polling interval of mice");
-
-@@ -1079,8 +1079,12 @@
- }
-
- /* Change the polling interval of mice. */
-- if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0)
-- interval = hid_mousepoll_interval;
-+ if (hid->collection->usage == HID_GD_MOUSE) {
-+ if (hid_mousepoll_interval == ~0 && interval < 16)
-+ interval = 16;
-+ else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0)
-+ interval = hid_mousepoll_interval;
-+ }
-
- ret = -ENOMEM;
- if (usb_endpoint_dir_in(endpoint)) {
-diff -Nur linux-3.18.14/drivers/hwmon/bcm2835-hwmon.c linux-rpi/drivers/hwmon/bcm2835-hwmon.c
---- linux-3.18.14/drivers/hwmon/bcm2835-hwmon.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/hwmon/bcm2835-hwmon.c 2015-05-31 14:46:10.469660984 -0500
-@@ -0,0 +1,219 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/hwmon.h>
-+#include <linux/hwmon-sysfs.h>
-+#include <linux/platform_device.h>
-+#include <linux/sysfs.h>
-+#include <mach/vcio.h>
-+#include <linux/slab.h>
-+#include <linux/err.h>
-+
-+#define MODULE_NAME "bcm2835_hwmon"
-+
-+/*#define HWMON_DEBUG_ENABLE*/
-+
-+#ifdef HWMON_DEBUG_ENABLE
-+#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+#define print_info(fmt,...) printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ##__VA_ARGS__)
-+
-+#define VC_TAG_GET_TEMP 0x00030006
-+#define VC_TAG_GET_MAX_TEMP 0x0003000A
-+
-+/* --- STRUCTS --- */
-+struct bcm2835_hwmon_data {
-+ struct device *hwmon_dev;
-+};
-+
-+/* tag part of the message */
-+struct vc_msg_tag {
-+ uint32_t tag_id; /* the tag ID for the temperature */
-+ uint32_t buffer_size; /* size of the buffer (should be 8) */
-+ uint32_t request_code; /* identifies message as a request (should be 0) */
-+ uint32_t id; /* extra ID field (should be 0) */
-+ uint32_t val; /* returned value of the temperature */
-+};
-+
-+/* message structure to be sent to videocore */
-+struct vc_msg {
-+ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */
-+ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */
-+ struct vc_msg_tag tag; /* the tag structure above to make */
-+ uint32_t end_tag; /* an end identifier, should be set to NULL */
-+};
-+
-+typedef enum {
-+ TEMP,
-+ MAX_TEMP,
-+} temp_type;
-+
-+/* --- PROTOTYPES --- */
-+static ssize_t bcm2835_get_temp(struct device *dev, struct device_attribute *attr, char *buf);
-+static ssize_t bcm2835_get_name(struct device *dev, struct device_attribute *attr, char *buf);
-+
-+/* --- GLOBALS --- */
-+
-+static struct bcm2835_hwmon_data *bcm2835_data;
-+static struct platform_driver bcm2835_hwmon_driver;
-+
-+static SENSOR_DEVICE_ATTR(name, S_IRUGO,bcm2835_get_name,NULL,0);
-+static SENSOR_DEVICE_ATTR(temp1_input,S_IRUGO,bcm2835_get_temp,NULL,TEMP);
-+static SENSOR_DEVICE_ATTR(temp1_max,S_IRUGO,bcm2835_get_temp,NULL,MAX_TEMP);
-+
-+static struct attribute* bcm2835_attributes[] = {
-+ &sensor_dev_attr_name.dev_attr.attr,
-+ &sensor_dev_attr_temp1_input.dev_attr.attr,
-+ &sensor_dev_attr_temp1_max.dev_attr.attr,
-+ NULL,
-+};
-+
-+static struct attribute_group bcm2835_attr_group = {
-+ .attrs = bcm2835_attributes,
-+};
-+
-+/* --- FUNCTIONS --- */
-+
-+static ssize_t bcm2835_get_name(struct device *dev, struct device_attribute *attr, char *buf)
-+{
-+ return sprintf(buf,"bcm2835_hwmon\n");
-+}
-+
-+static ssize_t bcm2835_get_temp(struct device *dev, struct device_attribute *attr, char *buf)
-+{
-+ struct vc_msg msg;
-+ int result;
-+ uint temp = 0;
-+ int index = ((struct sensor_device_attribute*)to_sensor_dev_attr(attr))->index;
-+
-+ print_debug("IN");
-+
-+ /* wipe all previous message data */
-+ memset(&msg, 0, sizeof msg);
-+
-+ /* determine the message type */
-+ if(index == TEMP)
-+ msg.tag.tag_id = VC_TAG_GET_TEMP;
-+ else if (index == MAX_TEMP)
-+ msg.tag.tag_id = VC_TAG_GET_MAX_TEMP;
-+ else
-+ {
-+ print_debug("Unknown temperature message!");
-+ return -EINVAL;
-+ }
-+
-+ msg.msg_size = sizeof msg;
-+ msg.tag.buffer_size = 8;
-+
-+ /* send the message */
-+ result = bcm_mailbox_property(&msg, sizeof msg);
-+
-+ /* check if it was all ok and return the rate in milli degrees C */
-+ if (result == 0 && (msg.request_code & 0x80000000))
-+ temp = (uint)msg.tag.val;
-+ #ifdef HWMON_DEBUG_ENABLE
-+ else
-+ print_debug("Failed to get temperature!");
-+ #endif
-+ print_debug("Got temperature as %u",temp);
-+ print_debug("OUT");
-+ return sprintf(buf, "%u\n", temp);
-+}
-+
-+
-+static int bcm2835_hwmon_probe(struct platform_device *pdev)
-+{
-+ int err;
-+
-+ print_debug("IN");
-+ print_debug("HWMON Driver has been probed!");
-+
-+ /* check that the device isn't null!*/
-+ if(pdev == NULL)
-+ {
-+ print_debug("Platform device is empty!");
-+ return -ENODEV;
-+ }
-+
-+ /* allocate memory for neccessary data */
-+ bcm2835_data = kzalloc(sizeof(struct bcm2835_hwmon_data),GFP_KERNEL);
-+ if(!bcm2835_data)
-+ {
-+ print_debug("Unable to allocate memory for hwmon data!");
-+ err = -ENOMEM;
-+ goto kzalloc_error;
-+ }
-+
-+ /* create the sysfs files */
-+ if(sysfs_create_group(&pdev->dev.kobj, &bcm2835_attr_group))
-+ {
-+ print_debug("Unable to create sysfs files!");
-+ err = -EFAULT;
-+ goto sysfs_error;
-+ }
-+
-+ /* register the hwmon device */
-+ bcm2835_data->hwmon_dev = hwmon_device_register(&pdev->dev);
-+ if (IS_ERR(bcm2835_data->hwmon_dev))
-+ {
-+ err = PTR_ERR(bcm2835_data->hwmon_dev);
-+ goto hwmon_error;
-+ }
-+ print_debug("OUT");
-+ return 0;
-+
-+ /* error goto's */
-+ hwmon_error:
-+ sysfs_remove_group(&pdev->dev.kobj, &bcm2835_attr_group);
-+
-+ sysfs_error:
-+ kfree(bcm2835_data);
-+
-+ kzalloc_error:
-+
-+ return err;
-+
-+}
-+
-+static int bcm2835_hwmon_remove(struct platform_device *pdev)
-+{
-+ print_debug("IN");
-+ hwmon_device_unregister(bcm2835_data->hwmon_dev);
-+
-+ sysfs_remove_group(&pdev->dev.kobj, &bcm2835_attr_group);
-+ print_debug("OUT");
-+ return 0;
-+}
-+
-+/* Hwmon Driver */
-+static struct platform_driver bcm2835_hwmon_driver = {
-+ .probe = bcm2835_hwmon_probe,
-+ .remove = bcm2835_hwmon_remove,
-+ .driver = {
-+ .name = "bcm2835_hwmon",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Dorian Peake");
-+MODULE_DESCRIPTION("HW Monitor driver for bcm2835 chip");
-+
-+module_platform_driver(bcm2835_hwmon_driver);
-diff -Nur linux-3.18.14/drivers/hwmon/Kconfig linux-rpi/drivers/hwmon/Kconfig
---- linux-3.18.14/drivers/hwmon/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/hwmon/Kconfig 2015-05-31 14:46:10.461660983 -0500
-@@ -1680,6 +1680,16 @@
- This driver provides support for the Ultra45 workstation environmental
- sensors.
-
-+config SENSORS_BCM2835
-+ depends on THERMAL_BCM2835=n
-+ tristate "Broadcom BCM2835 HWMON Driver"
-+ help
-+ If you say yes here you get support for the hardware
-+ monitoring features of the BCM2835 Chip
-+
-+ This driver can also be built as a module. If so, the module
-+ will be called bcm2835-hwmon.
-+
- if ACPI
-
- comment "ACPI drivers"
-diff -Nur linux-3.18.14/drivers/hwmon/Makefile linux-rpi/drivers/hwmon/Makefile
---- linux-3.18.14/drivers/hwmon/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/hwmon/Makefile 2015-05-31 14:46:10.461660983 -0500
-@@ -153,6 +153,7 @@
- obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
- obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o
- obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o
-+obj-$(CONFIG_SENSORS_BCM2835) += bcm2835-hwmon.o
-
- obj-$(CONFIG_PMBUS) += pmbus/
-
-diff -Nur linux-3.18.14/drivers/i2c/busses/i2c-bcm2708.c linux-rpi/drivers/i2c/busses/i2c-bcm2708.c
---- linux-3.18.14/drivers/i2c/busses/i2c-bcm2708.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/i2c/busses/i2c-bcm2708.c 2015-05-31 14:46:10.493660983 -0500
-@@ -0,0 +1,522 @@
-+/*
-+ * Driver for Broadcom BCM2708 BSC Controllers
-+ *
-+ * Copyright (C) 2012 Chris Boot & Frank Buss
-+ *
-+ * This driver is inspired by:
-+ * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/slab.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+
-+/* BSC register offsets */
-+#define BSC_C 0x00
-+#define BSC_S 0x04
-+#define BSC_DLEN 0x08
-+#define BSC_A 0x0c
-+#define BSC_FIFO 0x10
-+#define BSC_DIV 0x14
-+#define BSC_DEL 0x18
-+#define BSC_CLKT 0x1c
-+
-+/* Bitfields in BSC_C */
-+#define BSC_C_I2CEN 0x00008000
-+#define BSC_C_INTR 0x00000400
-+#define BSC_C_INTT 0x00000200
-+#define BSC_C_INTD 0x00000100
-+#define BSC_C_ST 0x00000080
-+#define BSC_C_CLEAR_1 0x00000020
-+#define BSC_C_CLEAR_2 0x00000010
-+#define BSC_C_READ 0x00000001
-+
-+/* Bitfields in BSC_S */
-+#define BSC_S_CLKT 0x00000200
-+#define BSC_S_ERR 0x00000100
-+#define BSC_S_RXF 0x00000080
-+#define BSC_S_TXE 0x00000040
-+#define BSC_S_RXD 0x00000020
-+#define BSC_S_TXD 0x00000010
-+#define BSC_S_RXR 0x00000008
-+#define BSC_S_TXW 0x00000004
-+#define BSC_S_DONE 0x00000002
-+#define BSC_S_TA 0x00000001
-+
-+#define I2C_TIMEOUT_MS 150
-+#define I2C_WAIT_LOOP_COUNT 40
-+
-+#define DRV_NAME "bcm2708_i2c"
-+
-+static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE;
-+module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(baudrate, "The I2C baudrate");
-+
-+static bool combined = false;
-+module_param(combined, bool, 0644);
-+MODULE_PARM_DESC(combined, "Use combined transactions");
-+
-+struct bcm2708_i2c {
-+ struct i2c_adapter adapter;
-+
-+ spinlock_t lock;
-+ void __iomem *base;
-+ int irq;
-+ struct clk *clk;
-+ u32 cdiv;
-+
-+ struct completion done;
-+
-+ struct i2c_msg *msg;
-+ int pos;
-+ int nmsgs;
-+ bool error;
-+};
-+
-+/*
-+ * This function sets the ALT mode on the I2C pins so that we can use them with
-+ * the BSC hardware.
-+ *
-+ * FIXME: This is a hack. Use pinmux / pinctrl.
-+ */
-+static void bcm2708_i2c_init_pinmode(int id)
-+{
-+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
-+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
-+
-+ int pin;
-+ u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
-+
-+ BUG_ON(id != 0 && id != 1);
-+ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */
-+ for (pin = id*2+0; pin <= id*2+1; pin++) {
-+ printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin);
-+ INP_GPIO(pin); /* set mode to GPIO input first */
-+ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
-+ }
-+
-+ iounmap(gpio);
-+
-+#undef INP_GPIO
-+#undef SET_GPIO_ALT
-+}
-+
-+static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
-+{
-+ return readl(bi->base + reg);
-+}
-+
-+static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
-+{
-+ writel(val, bi->base + reg);
-+}
-+
-+static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
-+{
-+ bcm2708_wr(bi, BSC_C, 0);
-+ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
-+}
-+
-+static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
-+{
-+ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len))
-+ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
-+}
-+
-+static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
-+{
-+ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len))
-+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
-+}
-+
-+static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi)
-+{
-+ u32 cdiv, s;
-+ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
-+ int wait_loops = I2C_WAIT_LOOP_COUNT;
-+
-+ /* Can't call clk_get_rate as it locks a mutex and here we are spinlocked.
-+ * Use the value that we cached in the probe.
-+ */
-+ cdiv = bi->cdiv;
-+
-+ if (bi->msg->flags & I2C_M_RD)
-+ c |= BSC_C_INTR | BSC_C_READ;
-+ else
-+ c |= BSC_C_INTT;
-+
-+ bcm2708_wr(bi, BSC_DIV, cdiv);
-+ bcm2708_wr(bi, BSC_A, bi->msg->addr);
-+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
-+ if (combined)
-+ {
-+ /* Do the next two messages meet combined transaction criteria?
-+ - Current message is a write, next message is a read
-+ - Both messages to same slave address
-+ - Write message can fit inside FIFO (16 bytes or less) */
-+ if ( (bi->nmsgs > 1) &&
-+ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) &&
-+ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) {
-+ /* Fill FIFO with entire write message (16 byte FIFO) */
-+ while (bi->pos < bi->msg->len) {
-+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
-+ }
-+ /* Start write transfer (no interrupts, don't clear FIFO) */
-+ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST);
-+
-+ /* poll for transfer start bit (should only take 1-20 polls) */
-+ do {
-+ s = bcm2708_rd(bi, BSC_S);
-+ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0);
-+
-+ /* did we time out or some error occured? */
-+ if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) {
-+ return -1;
-+ }
-+
-+ /* Send next read message before the write transfer finishes. */
-+ bi->nmsgs--;
-+ bi->msg++;
-+ bi->pos = 0;
-+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
-+ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ;
-+ }
-+ }
-+ bcm2708_wr(bi, BSC_C, c);
-+
-+ return 0;
-+}
-+
-+static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
-+{
-+ struct bcm2708_i2c *bi = dev_id;
-+ bool handled = true;
-+ u32 s;
-+ int ret;
-+
-+ spin_lock(&bi->lock);
-+
-+ /* we may see camera interrupts on the "other" I2C channel
-+ Just return if we've not sent anything */
-+ if (!bi->nmsgs || !bi->msg) {
-+ goto early_exit;
-+ }
-+
-+ s = bcm2708_rd(bi, BSC_S);
-+
-+ if (s & (BSC_S_CLKT | BSC_S_ERR)) {
-+ bcm2708_bsc_reset(bi);
-+ bi->error = true;
-+
-+ bi->msg = 0; /* to inform the that all work is done */
-+ bi->nmsgs = 0;
-+ /* wake up our bh */
-+ complete(&bi->done);
-+ } else if (s & BSC_S_DONE) {
-+ bi->nmsgs--;
-+
-+ if (bi->msg->flags & I2C_M_RD) {
-+ bcm2708_bsc_fifo_drain(bi);
-+ }
-+
-+ bcm2708_bsc_reset(bi);
-+
-+ if (bi->nmsgs) {
-+ /* advance to next message */
-+ bi->msg++;
-+ bi->pos = 0;
-+ ret = bcm2708_bsc_setup(bi);
-+ if (ret < 0) {
-+ bcm2708_bsc_reset(bi);
-+ bi->error = true;
-+ bi->msg = 0; /* to inform the that all work is done */
-+ bi->nmsgs = 0;
-+ /* wake up our bh */
-+ complete(&bi->done);
-+ goto early_exit;
-+ }
-+ } else {
-+ bi->msg = 0; /* to inform the that all work is done */
-+ bi->nmsgs = 0;
-+ /* wake up our bh */
-+ complete(&bi->done);
-+ }
-+ } else if (s & BSC_S_TXW) {
-+ bcm2708_bsc_fifo_fill(bi);
-+ } else if (s & BSC_S_RXR) {
-+ bcm2708_bsc_fifo_drain(bi);
-+ } else {
-+ handled = false;
-+ }
-+
-+early_exit:
-+ spin_unlock(&bi->lock);
-+
-+ return handled ? IRQ_HANDLED : IRQ_NONE;
-+}
-+
-+static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
-+ struct i2c_msg *msgs, int num)
-+{
-+ struct bcm2708_i2c *bi = adap->algo_data;
-+ unsigned long flags;
-+ int ret;
-+
-+ spin_lock_irqsave(&bi->lock, flags);
-+
-+ reinit_completion(&bi->done);
-+ bi->msg = msgs;
-+ bi->pos = 0;
-+ bi->nmsgs = num;
-+ bi->error = false;
-+
-+ ret = bcm2708_bsc_setup(bi);
-+
-+ spin_unlock_irqrestore(&bi->lock, flags);
-+
-+ /* check the result of the setup */
-+ if (ret < 0)
-+ {
-+ dev_err(&adap->dev, "transfer setup timed out\n");
-+ goto error_timeout;
-+ }
-+
-+ ret = wait_for_completion_timeout(&bi->done, msecs_to_jiffies(I2C_TIMEOUT_MS));
-+ if (ret == 0) {
-+ dev_err(&adap->dev, "transfer timed out\n");
-+ goto error_timeout;
-+ }
-+
-+ ret = bi->error ? -EIO : num;
-+ return ret;
-+
-+error_timeout:
-+ spin_lock_irqsave(&bi->lock, flags);
-+ bcm2708_bsc_reset(bi);
-+ bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */
-+ bi->nmsgs = 0;
-+ spin_unlock_irqrestore(&bi->lock, flags);
-+ return -ETIMEDOUT;
-+}
-+
-+static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
-+{
-+ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static struct i2c_algorithm bcm2708_i2c_algorithm = {
-+ .master_xfer = bcm2708_i2c_master_xfer,
-+ .functionality = bcm2708_i2c_functionality,
-+};
-+
-+static int bcm2708_i2c_probe(struct platform_device *pdev)
-+{
-+ struct resource *regs;
-+ int irq, err = -ENOMEM;
-+ struct clk *clk;
-+ struct bcm2708_i2c *bi;
-+ struct i2c_adapter *adap;
-+ unsigned long bus_hz;
-+ u32 cdiv;
-+
-+ if (pdev->dev.of_node) {
-+ u32 bus_clk_rate;
-+ pdev->id = of_alias_get_id(pdev->dev.of_node, "i2c");
-+ if (pdev->id < 0) {
-+ dev_err(&pdev->dev, "alias is missing\n");
-+ return -EINVAL;
-+ }
-+ if (!of_property_read_u32(pdev->dev.of_node,
-+ "clock-frequency", &bus_clk_rate))
-+ baudrate = bus_clk_rate;
-+ else
-+ dev_warn(&pdev->dev,
-+ "Could not read clock-frequency property\n");
-+ }
-+
-+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!regs) {
-+ dev_err(&pdev->dev, "could not get IO memory\n");
-+ return -ENXIO;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "could not get IRQ\n");
-+ return irq;
-+ }
-+
-+ clk = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
-+ return PTR_ERR(clk);
-+ }
-+
-+ err = clk_prepare_enable(clk);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not enable clk: %d\n", err);
-+ goto out_clk_put;
-+ }
-+
-+ if (!pdev->dev.of_node)
-+ bcm2708_i2c_init_pinmode(pdev->id);
-+
-+ bi = kzalloc(sizeof(*bi), GFP_KERNEL);
-+ if (!bi)
-+ goto out_clk_disable;
-+
-+ platform_set_drvdata(pdev, bi);
-+
-+ adap = &bi->adapter;
-+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
-+ adap->algo = &bcm2708_i2c_algorithm;
-+ adap->algo_data = bi;
-+ adap->dev.parent = &pdev->dev;
-+ adap->nr = pdev->id;
-+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+ adap->dev.of_node = pdev->dev.of_node;
-+
-+ switch (pdev->id) {
-+ case 0:
-+ adap->class = I2C_CLASS_HWMON;
-+ break;
-+ case 1:
-+ adap->class = I2C_CLASS_DDC;
-+ break;
-+ default:
-+ dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n");
-+ err = -ENXIO;
-+ goto out_free_bi;
-+ }
-+
-+ spin_lock_init(&bi->lock);
-+ init_completion(&bi->done);
-+
-+ bi->base = ioremap(regs->start, resource_size(regs));
-+ if (!bi->base) {
-+ dev_err(&pdev->dev, "could not remap memory\n");
-+ goto out_free_bi;
-+ }
-+
-+ bi->irq = irq;
-+ bi->clk = clk;
-+
-+ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
-+ dev_name(&pdev->dev), bi);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
-+ goto out_iounmap;
-+ }
-+
-+ bcm2708_bsc_reset(bi);
-+
-+ err = i2c_add_numbered_adapter(adap);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
-+ goto out_free_irq;
-+ }
-+
-+ bus_hz = clk_get_rate(bi->clk);
-+ cdiv = bus_hz / baudrate;
-+ if (cdiv > 0xffff) {
-+ cdiv = 0xffff;
-+ baudrate = bus_hz / cdiv;
-+ }
-+ bi->cdiv = cdiv;
-+
-+ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
-+ pdev->id, (unsigned long)regs->start, irq, baudrate);
-+
-+ return 0;
-+
-+out_free_irq:
-+ free_irq(bi->irq, bi);
-+out_iounmap:
-+ iounmap(bi->base);
-+out_free_bi:
-+ kfree(bi);
-+out_clk_disable:
-+ clk_disable_unprepare(clk);
-+out_clk_put:
-+ clk_put(clk);
-+ return err;
-+}
-+
-+static int bcm2708_i2c_remove(struct platform_device *pdev)
-+{
-+ struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
-+
-+ platform_set_drvdata(pdev, NULL);
-+
-+ i2c_del_adapter(&bi->adapter);
-+ free_irq(bi->irq, bi);
-+ iounmap(bi->base);
-+ clk_disable_unprepare(bi->clk);
-+ clk_put(bi->clk);
-+ kfree(bi);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id bcm2708_i2c_of_match[] = {
-+ { .compatible = "brcm,bcm2708-i2c" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match);
-+
-+static struct platform_driver bcm2708_i2c_driver = {
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcm2708_i2c_of_match,
-+ },
-+ .probe = bcm2708_i2c_probe,
-+ .remove = bcm2708_i2c_remove,
-+};
-+
-+// module_platform_driver(bcm2708_i2c_driver);
-+
-+
-+static int __init bcm2708_i2c_init(void)
-+{
-+ return platform_driver_register(&bcm2708_i2c_driver);
-+}
-+
-+static void __exit bcm2708_i2c_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_i2c_driver);
-+}
-+
-+module_init(bcm2708_i2c_init);
-+module_exit(bcm2708_i2c_exit);
-+
-+
-+
-+MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
-+MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRV_NAME);
-diff -Nur linux-3.18.14/drivers/i2c/busses/Kconfig linux-rpi/drivers/i2c/busses/Kconfig
---- linux-3.18.14/drivers/i2c/busses/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/i2c/busses/Kconfig 2015-05-31 14:46:10.489660983 -0500
-@@ -361,7 +361,7 @@
-
- config I2C_BCM2835
- tristate "Broadcom BCM2835 I2C controller"
-- depends on ARCH_BCM2835
-+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
- help
- If you say yes to this option, support will be included for the
- BCM2835 I2C controller.
-@@ -371,6 +371,25 @@
- This support is also available as a module. If so, the module
- will be called i2c-bcm2835.
-
-+config I2C_BCM2708
-+ tristate "BCM2708 BSC"
-+ depends on MACH_BCM2708 || MACH_BCM2709
-+ help
-+ Enabling this option will add BSC (Broadcom Serial Controller)
-+ support for the BCM2708. BSC is a Broadcom proprietary bus compatible
-+ with I2C/TWI/SMBus.
-+
-+config I2C_BCM2708_BAUDRATE
-+ prompt "BCM2708 I2C baudrate"
-+ depends on I2C_BCM2708
-+ int
-+ default 100000
-+ help
-+ Set the I2C baudrate. This will alter the default value. A
-+ different baudrate can be set by using a module parameter as well. If
-+ no parameter is provided when loading, this is the value that will be
-+ used.
-+
- config I2C_BCM_KONA
- tristate "BCM Kona I2C adapter"
- depends on ARCH_BCM_MOBILE
-diff -Nur linux-3.18.14/drivers/i2c/busses/Makefile linux-rpi/drivers/i2c/busses/Makefile
---- linux-3.18.14/drivers/i2c/busses/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/i2c/busses/Makefile 2015-05-31 14:46:10.489660983 -0500
-@@ -33,6 +33,7 @@
- obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
- obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o
- obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
-+obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o
- obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
- obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o
- obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
-diff -Nur linux-3.18.14/drivers/leds/trigger/Kconfig linux-rpi/drivers/leds/trigger/Kconfig
---- linux-3.18.14/drivers/leds/trigger/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/leds/trigger/Kconfig 2015-05-31 14:46:10.769660981 -0500
-@@ -108,4 +108,11 @@
- This enables direct flash/torch on/off by the driver, kernel space.
- If unsure, say Y.
-
-+config LEDS_TRIGGER_INPUT
-+ tristate "LED Input Trigger"
-+ depends on LEDS_TRIGGERS
-+ help
-+ This allows the GPIOs assigned to be LEDs to be initialised to inputs.
-+ If unsure, say Y.
-+
- endif # LEDS_TRIGGERS
-diff -Nur linux-3.18.14/drivers/leds/trigger/ledtrig-input.c linux-rpi/drivers/leds/trigger/ledtrig-input.c
---- linux-3.18.14/drivers/leds/trigger/ledtrig-input.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/leds/trigger/ledtrig-input.c 2015-05-31 14:46:10.769660981 -0500
-@@ -0,0 +1,65 @@
-+/*
-+ * Set LED GPIO to Input "Trigger"
-+ *
-+ * Copyright 2015 Phil Elwell <phil@raspberrypi.org>
-+ *
-+ * Based on Nick Forbes's ledtrig-default-on.c.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include "../leds.h"
-+
-+/* This is a hack to get at the private 'gpio' member */
-+
-+struct gpio_led_data {
-+ struct led_classdev cdev;
-+ unsigned gpio;
-+};
-+
-+static void input_trig_activate(struct led_classdev *led_cdev)
-+{
-+ struct gpio_led_data *led_dat =
-+ container_of(led_cdev, struct gpio_led_data, cdev);
-+ if (gpio_is_valid(led_dat->gpio))
-+ gpio_direction_input(led_dat->gpio);
-+}
-+
-+static void input_trig_deactivate(struct led_classdev *led_cdev)
-+{
-+ struct gpio_led_data *led_dat =
-+ container_of(led_cdev, struct gpio_led_data, cdev);
-+ if (gpio_is_valid(led_dat->gpio))
-+ gpio_direction_output(led_dat->gpio, 0);
-+}
-+
-+static struct led_trigger input_led_trigger = {
-+ .name = "input",
-+ .activate = input_trig_activate,
-+ .deactivate = input_trig_deactivate,
-+};
-+
-+static int __init input_trig_init(void)
-+{
-+ return led_trigger_register(&input_led_trigger);
-+}
-+
-+static void __exit input_trig_exit(void)
-+{
-+ led_trigger_unregister(&input_led_trigger);
-+}
-+
-+module_init(input_trig_init);
-+module_exit(input_trig_exit);
-+
-+MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.org>");
-+MODULE_DESCRIPTION("Set LED GPIO to Input \"trigger\"");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/leds/trigger/Makefile linux-rpi/drivers/leds/trigger/Makefile
---- linux-3.18.14/drivers/leds/trigger/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/leds/trigger/Makefile 2015-05-31 14:46:10.769660981 -0500
-@@ -8,3 +8,4 @@
- obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
- obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT) += ledtrig-transient.o
- obj-$(CONFIG_LEDS_TRIGGER_CAMERA) += ledtrig-camera.o
-+obj-$(CONFIG_LEDS_TRIGGER_INPUT) += ledtrig-input.o
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/bcm2835-camera.c linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c
---- linux-3.18.14/drivers/media/platform/bcm2835/bcm2835-camera.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,1828 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <media/videobuf2-vmalloc.h>
-+#include <media/videobuf2-dma-contig.h>
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-ioctl.h>
-+#include <media/v4l2-ctrls.h>
-+#include <media/v4l2-fh.h>
-+#include <media/v4l2-event.h>
-+#include <media/v4l2-common.h>
-+#include <linux/delay.h>
-+
-+#include "mmal-common.h"
-+#include "mmal-encodings.h"
-+#include "mmal-vchiq.h"
-+#include "mmal-msg.h"
-+#include "mmal-parameters.h"
-+#include "bcm2835-camera.h"
-+
-+#define BM2835_MMAL_VERSION "0.0.2"
-+#define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2"
-+#define MIN_WIDTH 16
-+#define MIN_HEIGHT 16
-+#define MAX_WIDTH 2592
-+#define MAX_HEIGHT 1944
-+#define MIN_BUFFER_SIZE (80*1024)
-+
-+#define MAX_VIDEO_MODE_WIDTH 1280
-+#define MAX_VIDEO_MODE_HEIGHT 720
-+
-+MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture");
-+MODULE_AUTHOR("Vincent Sanders");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(BM2835_MMAL_VERSION);
-+
-+int bcm2835_v4l2_debug;
-+module_param_named(debug, bcm2835_v4l2_debug, int, 0644);
-+MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2");
-+
-+int max_video_width = MAX_VIDEO_MODE_WIDTH;
-+int max_video_height = MAX_VIDEO_MODE_HEIGHT;
-+module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
-+MODULE_PARM_DESC(max_video_width, "Threshold for video mode");
-+module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
-+MODULE_PARM_DESC(max_video_height, "Threshold for video mode");
-+
-+/* Gstreamer bug https://bugzilla.gnome.org/show_bug.cgi?id=726521
-+ * v4l2src does bad (and actually wrong) things when the vidioc_enum_framesizes
-+ * function says type V4L2_FRMSIZE_TYPE_STEPWISE, which we do by default.
-+ * It's happier if we just don't say anything at all, when it then
-+ * sets up a load of defaults that it thinks might work.
-+ * If gst_v4l2src_is_broken is non-zero, then we remove the function from
-+ * our function table list (actually switch to an alternate set, but same
-+ * result).
-+ */
-+int gst_v4l2src_is_broken = 0;
-+module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
-+MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer");
-+
-+static struct bm2835_mmal_dev *gdev; /* global device data */
-+
-+#define FPS_MIN 1
-+#define FPS_MAX 90
-+
-+/* timeperframe: min/max and default */
-+static const struct v4l2_fract
-+ tpf_min = {.numerator = 1, .denominator = FPS_MAX},
-+ tpf_max = {.numerator = 1, .denominator = FPS_MIN},
-+ tpf_default = {.numerator = 1000, .denominator = 30000};
-+
-+/* video formats */
-+static struct mmal_fmt formats[] = {
-+ {
-+ .name = "4:2:0, packed YUV",
-+ .fourcc = V4L2_PIX_FMT_YUV420,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_I420,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:2, packed, YUYV",
-+ .fourcc = V4L2_PIX_FMT_YUYV,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_YUYV,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "RGB24 (LE)",
-+ .fourcc = V4L2_PIX_FMT_RGB24,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_BGR24,
-+ .depth = 24,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "JPEG",
-+ .fourcc = V4L2_PIX_FMT_JPEG,
-+ .flags = V4L2_FMT_FLAG_COMPRESSED,
-+ .mmal = MMAL_ENCODING_JPEG,
-+ .depth = 8,
-+ .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
-+ },
-+ {
-+ .name = "H264",
-+ .fourcc = V4L2_PIX_FMT_H264,
-+ .flags = V4L2_FMT_FLAG_COMPRESSED,
-+ .mmal = MMAL_ENCODING_H264,
-+ .depth = 8,
-+ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+ },
-+ {
-+ .name = "MJPEG",
-+ .fourcc = V4L2_PIX_FMT_MJPEG,
-+ .flags = V4L2_FMT_FLAG_COMPRESSED,
-+ .mmal = MMAL_ENCODING_MJPEG,
-+ .depth = 8,
-+ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+ },
-+ {
-+ .name = "4:2:2, packed, YVYU",
-+ .fourcc = V4L2_PIX_FMT_YVYU,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_YVYU,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:2, packed, VYUY",
-+ .fourcc = V4L2_PIX_FMT_VYUY,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_VYUY,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:2, packed, UYVY",
-+ .fourcc = V4L2_PIX_FMT_UYVY,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_UYVY,
-+ .depth = 16,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:0, packed, NV12",
-+ .fourcc = V4L2_PIX_FMT_NV12,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_NV12,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "RGB24 (BE)",
-+ .fourcc = V4L2_PIX_FMT_BGR24,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_RGB24,
-+ .depth = 24,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:0, packed YVU",
-+ .fourcc = V4L2_PIX_FMT_YVU420,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_YV12,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "4:2:0, packed, NV21",
-+ .fourcc = V4L2_PIX_FMT_NV21,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_NV21,
-+ .depth = 12,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+ {
-+ .name = "RGB32 (BE)",
-+ .fourcc = V4L2_PIX_FMT_BGR32,
-+ .flags = 0,
-+ .mmal = MMAL_ENCODING_BGRA,
-+ .depth = 32,
-+ .mmal_component = MMAL_COMPONENT_CAMERA,
-+ },
-+};
-+
-+static struct mmal_fmt *get_format(struct v4l2_format *f)
-+{
-+ struct mmal_fmt *fmt;
-+ unsigned int k;
-+
-+ for (k = 0; k < ARRAY_SIZE(formats); k++) {
-+ fmt = &formats[k];
-+ if (fmt->fourcc == f->fmt.pix.pixelformat)
-+ break;
-+ }
-+
-+ if (k == ARRAY_SIZE(formats))
-+ return NULL;
-+
-+ return &formats[k];
-+}
-+
-+/* ------------------------------------------------------------------
-+ Videobuf queue operations
-+ ------------------------------------------------------------------*/
-+
-+static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
-+ unsigned int *nbuffers, unsigned int *nplanes,
-+ unsigned int sizes[], void *alloc_ctxs[])
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ unsigned long size;
-+
-+ /* refuse queue setup if port is not configured */
-+ if (dev->capture.port == NULL) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: capture port not configured\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ size = dev->capture.port->current_buffer.size;
-+ if (size == 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: capture port buffer size is zero\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ if (*nbuffers < (dev->capture.port->current_buffer.num + 2))
-+ *nbuffers = (dev->capture.port->current_buffer.num + 2);
-+
-+ *nplanes = 1;
-+
-+ sizes[0] = size;
-+
-+ /*
-+ * videobuf2-vmalloc allocator is context-less so no need to set
-+ * alloc_ctxs array.
-+ */
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ return 0;
-+}
-+
-+static int buffer_prepare(struct vb2_buffer *vb)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-+ unsigned long size;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ BUG_ON(dev->capture.port == NULL);
-+ BUG_ON(dev->capture.fmt == NULL);
-+
-+ size = dev->capture.stride * dev->capture.height;
-+ if (vb2_plane_size(vb, 0) < size) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s data will not fit into plane (%lu < %lu)\n",
-+ __func__, vb2_plane_size(vb, 0), size);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static inline bool is_capturing(struct bm2835_mmal_dev *dev)
-+{
-+ return dev->capture.camera_port ==
-+ &dev->
-+ component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE];
-+}
-+
-+static void buffer_cb(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ int status,
-+ struct mmal_buffer *buf,
-+ unsigned long length, u32 mmal_flags, s64 dts, s64 pts)
-+{
-+ struct bm2835_mmal_dev *dev = port->cb_ctx;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\n",
-+ __func__, status, buf, length, mmal_flags, pts);
-+
-+ if (status != 0) {
-+ /* error in transfer */
-+ if (buf != NULL) {
-+ /* there was a buffer with the error so return it */
-+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
-+ }
-+ return;
-+ } else if (length == 0) {
-+ /* stream ended */
-+ if (buf != NULL) {
-+ /* this should only ever happen if the port is
-+ * disabled and there are buffers still queued
-+ */
-+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
-+ pr_debug("Empty buffer");
-+ } else if (dev->capture.frame_count) {
-+ /* grab another frame */
-+ if (is_capturing(dev)) {
-+ pr_debug("Grab another frame");
-+ vchiq_mmal_port_parameter_set(
-+ instance,
-+ dev->capture.
-+ camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.
-+ frame_count,
-+ sizeof(dev->capture.frame_count));
-+ }
-+ } else {
-+ /* signal frame completion */
-+ complete(&dev->capture.frame_cmplt);
-+ }
-+ } else {
-+ if (dev->capture.frame_count) {
-+ if (dev->capture.vc_start_timestamp != -1 &&
-+ pts != 0) {
-+ s64 runtime_us = pts -
-+ dev->capture.vc_start_timestamp;
-+ u32 div = 0;
-+ u32 rem = 0;
-+
-+ div =
-+ div_u64_rem(runtime_us, USEC_PER_SEC, &rem);
-+ buf->vb.v4l2_buf.timestamp.tv_sec =
-+ dev->capture.kernel_start_ts.tv_sec - 1 +
-+ div;
-+ buf->vb.v4l2_buf.timestamp.tv_usec =
-+ dev->capture.kernel_start_ts.tv_usec + rem;
-+
-+ if (buf->vb.v4l2_buf.timestamp.tv_usec >=
-+ USEC_PER_SEC) {
-+ buf->vb.v4l2_buf.timestamp.tv_sec++;
-+ buf->vb.v4l2_buf.timestamp.tv_usec -=
-+ USEC_PER_SEC;
-+ }
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Convert start time %d.%06d and %llu "
-+ "with offset %llu to %d.%06d\n",
-+ (int)dev->capture.kernel_start_ts.
-+ tv_sec,
-+ (int)dev->capture.kernel_start_ts.
-+ tv_usec,
-+ dev->capture.vc_start_timestamp, pts,
-+ (int)buf->vb.v4l2_buf.timestamp.tv_sec,
-+ (int)buf->vb.v4l2_buf.timestamp.
-+ tv_usec);
-+ } else {
-+ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp);
-+ }
-+
-+ vb2_set_plane_payload(&buf->vb, 0, length);
-+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE);
-+
-+ if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
-+ is_capturing(dev)) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Grab another frame as buffer has EOS");
-+ vchiq_mmal_port_parameter_set(
-+ instance,
-+ dev->capture.
-+ camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.
-+ frame_count,
-+ sizeof(dev->capture.frame_count));
-+ }
-+ } else {
-+ /* signal frame completion */
-+ complete(&dev->capture.frame_cmplt);
-+ }
-+ }
-+}
-+
-+static int enable_camera(struct bm2835_mmal_dev *dev)
-+{
-+ int ret;
-+ if (!dev->camera_use_count) {
-+ ret = vchiq_mmal_component_enable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed enabling camera, ret %d\n", ret);
-+ return -EINVAL;
-+ }
-+ }
-+ dev->camera_use_count++;
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev, "enabled camera (refcount %d)\n",
-+ dev->camera_use_count);
-+ return 0;
-+}
-+
-+static int disable_camera(struct bm2835_mmal_dev *dev)
-+{
-+ int ret;
-+ if (!dev->camera_use_count) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Disabled the camera when already disabled\n");
-+ return -EINVAL;
-+ }
-+ dev->camera_use_count--;
-+ if (!dev->camera_use_count) {
-+ unsigned int i = 0xFFFFFFFF;
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Disabling camera\n");
-+ ret =
-+ vchiq_mmal_component_disable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed disabling camera, ret %d\n", ret);
-+ return -EINVAL;
-+ }
-+ vchiq_mmal_port_parameter_set(
-+ dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->control,
-+ MMAL_PARAMETER_CAMERA_NUM, &i,
-+ sizeof(i));
-+ }
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Camera refcount now %d\n", dev->camera_use_count);
-+ return 0;
-+}
-+
-+static void buffer_queue(struct vb2_buffer *vb)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-+ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb);
-+ int ret;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: dev:%p buf:%p\n", __func__, dev, buf);
-+
-+ buf->buffer = vb2_plane_vaddr(&buf->vb, 0);
-+ buf->buffer_size = vb2_plane_size(&buf->vb, 0);
-+
-+ ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf);
-+ if (ret < 0)
-+ v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n",
-+ __func__);
-+}
-+
-+static int start_streaming(struct vb2_queue *vq, unsigned int count)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ int ret;
-+ int parameter_size;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ /* ensure a format has actually been set */
-+ if (dev->capture.port == NULL)
-+ return -EINVAL;
-+
-+ if (enable_camera(dev) < 0) {
-+ v4l2_err(&dev->v4l2_dev, "Failed to enable camera\n");
-+ return -EINVAL;
-+ }
-+
-+ /*init_completion(&dev->capture.frame_cmplt); */
-+
-+ /* enable frame capture */
-+ dev->capture.frame_count = 1;
-+
-+ /* if the preview is not already running, wait for a few frames for AGC
-+ * to settle down.
-+ */
-+ if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled)
-+ msleep(300);
-+
-+ /* enable the connection from camera to encoder (if applicable) */
-+ if (dev->capture.camera_port != dev->capture.port
-+ && dev->capture.camera_port) {
-+ ret = vchiq_mmal_port_enable(dev->instance,
-+ dev->capture.camera_port, NULL);
-+ if (ret) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to enable encode tunnel - error %d\n",
-+ ret);
-+ return -1;
-+ }
-+ }
-+
-+ /* Get VC timestamp at this point in time */
-+ parameter_size = sizeof(dev->capture.vc_start_timestamp);
-+ if (vchiq_mmal_port_parameter_get(dev->instance,
-+ dev->capture.camera_port,
-+ MMAL_PARAMETER_SYSTEM_TIME,
-+ &dev->capture.vc_start_timestamp,
-+ &parameter_size)) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to get VC start time - update your VC f/w\n");
-+
-+ /* Flag to indicate just to rely on kernel timestamps */
-+ dev->capture.vc_start_timestamp = -1;
-+ } else
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Start time %lld size %d\n",
-+ dev->capture.vc_start_timestamp, parameter_size);
-+
-+ v4l2_get_timestamp(&dev->capture.kernel_start_ts);
-+
-+ /* enable the camera port */
-+ dev->capture.port->cb_ctx = dev;
-+ ret =
-+ vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb);
-+ if (ret) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to enable capture port - error %d. "
-+ "Disabling camera port again\n", ret);
-+
-+ vchiq_mmal_port_disable(dev->instance,
-+ dev->capture.camera_port);
-+ if (disable_camera(dev) < 0) {
-+ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n");
-+ return -EINVAL;
-+ }
-+ return -1;
-+ }
-+
-+ /* capture the first frame */
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ dev->capture.camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.frame_count,
-+ sizeof(dev->capture.frame_count));
-+ return 0;
-+}
-+
-+/* abort streaming and wait for last buffer */
-+static void stop_streaming(struct vb2_queue *vq)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
-+ __func__, dev);
-+
-+ init_completion(&dev->capture.frame_cmplt);
-+ dev->capture.frame_count = 0;
-+
-+ /* ensure a format has actually been set */
-+ if (dev->capture.port == NULL) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "no capture port - stream not started?\n");
-+ return;
-+ }
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "stopping capturing\n");
-+
-+ /* stop capturing frames */
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ dev->capture.camera_port,
-+ MMAL_PARAMETER_CAPTURE,
-+ &dev->capture.frame_count,
-+ sizeof(dev->capture.frame_count));
-+
-+ /* wait for last frame to complete */
-+ ret = wait_for_completion_timeout(&dev->capture.frame_cmplt, HZ);
-+ if (ret <= 0)
-+ v4l2_err(&dev->v4l2_dev,
-+ "error %d waiting for frame completion\n", ret);
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "disabling connection\n");
-+
-+ /* disable the connection from camera to encoder */
-+ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.camera_port);
-+ if (!ret && dev->capture.camera_port != dev->capture.port) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "disabling port\n");
-+ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.port);
-+ } else if (dev->capture.camera_port != dev->capture.port) {
-+ v4l2_err(&dev->v4l2_dev, "port_disable failed, error %d\n",
-+ ret);
-+ }
-+
-+ if (disable_camera(dev) < 0)
-+ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n");
-+}
-+
-+static void bm2835_mmal_lock(struct vb2_queue *vq)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ mutex_lock(&dev->mutex);
-+}
-+
-+static void bm2835_mmal_unlock(struct vb2_queue *vq)
-+{
-+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+ mutex_unlock(&dev->mutex);
-+}
-+
-+static struct vb2_ops bm2835_mmal_video_qops = {
-+ .queue_setup = queue_setup,
-+ .buf_prepare = buffer_prepare,
-+ .buf_queue = buffer_queue,
-+ .start_streaming = start_streaming,
-+ .stop_streaming = stop_streaming,
-+ .wait_prepare = bm2835_mmal_unlock,
-+ .wait_finish = bm2835_mmal_lock,
-+};
-+
-+/* ------------------------------------------------------------------
-+ IOCTL operations
-+ ------------------------------------------------------------------*/
-+
-+/* overlay ioctl */
-+static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_fmtdesc *f)
-+{
-+ struct mmal_fmt *fmt;
-+
-+ if (f->index >= ARRAY_SIZE(formats))
-+ return -EINVAL;
-+
-+ fmt = &formats[f->index];
-+
-+ strlcpy(f->description, fmt->name, sizeof(f->description));
-+ f->pixelformat = fmt->fourcc;
-+ f->flags = fmt->flags;
-+
-+ return 0;
-+}
-+
-+static int vidioc_g_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ f->fmt.win = dev->overlay;
-+
-+ return 0;
-+}
-+
-+static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ /* Only support one format so get the current one. */
-+ vidioc_g_fmt_vid_overlay(file, priv, f);
-+
-+ /* todo: allow the size and/or offset to be changed. */
-+ return 0;
-+}
-+
-+static int vidioc_s_fmt_vid_overlay(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ vidioc_try_fmt_vid_overlay(file, priv, f);
-+
-+ dev->overlay = f->fmt.win;
-+
-+ /* todo: program the preview port parameters */
-+ return 0;
-+}
-+
-+static int vidioc_overlay(struct file *file, void *f, unsigned int on)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct vchiq_mmal_port *src;
-+ struct vchiq_mmal_port *dst;
-+ struct mmal_parameter_displayregion prev_config = {
-+ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA |
-+ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN,
-+ .layer = PREVIEW_LAYER,
-+ .alpha = 255,
-+ .fullscreen = 0,
-+ .dest_rect = {
-+ .x = dev->overlay.w.left,
-+ .y = dev->overlay.w.top,
-+ .width = dev->overlay.w.width,
-+ .height = dev->overlay.w.height,
-+ },
-+ };
-+
-+ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ||
-+ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled))
-+ return 0; /* already in requested state */
-+
-+ src =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW];
-+
-+ if (!on) {
-+ /* disconnect preview ports and disable component */
-+ ret = vchiq_mmal_port_disable(dev->instance, src);
-+ if (!ret)
-+ ret =
-+ vchiq_mmal_port_connect_tunnel(dev->instance, src,
-+ NULL);
-+ if (ret >= 0)
-+ ret = vchiq_mmal_component_disable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_PREVIEW]);
-+
-+ disable_camera(dev);
-+ return ret;
-+ }
-+
-+ /* set preview port format and connect it to output */
-+ dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0];
-+
-+ ret = vchiq_mmal_port_set_format(dev->instance, src);
-+ if (ret < 0)
-+ goto error;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, dst,
-+ MMAL_PARAMETER_DISPLAYREGION,
-+ &prev_config, sizeof(prev_config));
-+ if (ret < 0)
-+ goto error;
-+
-+ if (enable_camera(dev) < 0)
-+ goto error;
-+
-+ ret = vchiq_mmal_component_enable(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_PREVIEW]);
-+ if (ret < 0)
-+ goto error;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n",
-+ src, dst);
-+ ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst);
-+ if (!ret)
-+ ret = vchiq_mmal_port_enable(dev->instance, src, NULL);
-+error:
-+ return ret;
-+}
-+
-+static int vidioc_g_fbuf(struct file *file, void *fh,
-+ struct v4l2_framebuffer *a)
-+{
-+ /* The video overlay must stay within the framebuffer and can't be
-+ positioned independently. */
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct vchiq_mmal_port *preview_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW];
-+ a->flags = V4L2_FBUF_FLAG_OVERLAY;
-+ a->fmt.width = preview_port->es.video.width;
-+ a->fmt.height = preview_port->es.video.height;
-+ a->fmt.pixelformat = V4L2_PIX_FMT_YUV420;
-+ a->fmt.bytesperline = (preview_port->es.video.width * 3)>>1;
-+ a->fmt.sizeimage = (preview_port->es.video.width *
-+ preview_port->es.video.height * 3)>>1;
-+ a->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M;
-+
-+ return 0;
-+}
-+
-+/* input ioctls */
-+static int vidioc_enum_input(struct file *file, void *priv,
-+ struct v4l2_input *inp)
-+{
-+ /* only a single camera input */
-+ if (inp->index != 0)
-+ return -EINVAL;
-+
-+ inp->type = V4L2_INPUT_TYPE_CAMERA;
-+ sprintf(inp->name, "Camera %u", inp->index);
-+ return 0;
-+}
-+
-+static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
-+{
-+ *i = 0;
-+ return 0;
-+}
-+
-+static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
-+{
-+ if (i != 0)
-+ return -EINVAL;
-+
-+ return 0;
-+}
-+
-+/* capture ioctls */
-+static int vidioc_querycap(struct file *file, void *priv,
-+ struct v4l2_capability *cap)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ u32 major;
-+ u32 minor;
-+
-+ vchiq_mmal_version(dev->instance, &major, &minor);
-+
-+ strcpy(cap->driver, "bm2835 mmal");
-+ snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d",
-+ major, minor);
-+
-+ snprintf(cap->bus_info, sizeof(cap->bus_info),
-+ "platform:%s", dev->v4l2_dev.name);
-+ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY |
-+ V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
-+ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
-+
-+ return 0;
-+}
-+
-+static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_fmtdesc *f)
-+{
-+ struct mmal_fmt *fmt;
-+
-+ if (f->index >= ARRAY_SIZE(formats))
-+ return -EINVAL;
-+
-+ fmt = &formats[f->index];
-+
-+ strlcpy(f->description, fmt->name, sizeof(f->description));
-+ f->pixelformat = fmt->fourcc;
-+ f->flags = fmt->flags;
-+
-+ return 0;
-+}
-+
-+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ f->fmt.pix.width = dev->capture.width;
-+ f->fmt.pix.height = dev->capture.height;
-+ f->fmt.pix.field = V4L2_FIELD_NONE;
-+ f->fmt.pix.pixelformat = dev->capture.fmt->fourcc;
-+ f->fmt.pix.bytesperline = dev->capture.stride;
-+ f->fmt.pix.sizeimage = dev->capture.buffersize;
-+
-+ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24)
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
-+ else if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_JPEG)
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
-+ else
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
-+ f->fmt.pix.priv = 0;
-+
-+ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix,
-+ __func__);
-+ return 0;
-+}
-+
-+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct mmal_fmt *mfmt;
-+
-+ mfmt = get_format(f);
-+ if (!mfmt) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Fourcc format (0x%08x) unknown.\n",
-+ f->fmt.pix.pixelformat);
-+ f->fmt.pix.pixelformat = formats[0].fourcc;
-+ mfmt = get_format(f);
-+ }
-+
-+ f->fmt.pix.field = V4L2_FIELD_NONE;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Clipping/aligning %dx%d format %08X\n",
-+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
-+
-+ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1,
-+ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0);
-+ f->fmt.pix.bytesperline = (f->fmt.pix.width * mfmt->depth)>>3;
-+
-+ /* Image buffer has to be padded to allow for alignment, even though
-+ * we then remove that padding before delivering the buffer.
-+ */
-+ f->fmt.pix.sizeimage = ((f->fmt.pix.height+15)&~15) *
-+ (((f->fmt.pix.width+31)&~31) * mfmt->depth) >> 3;
-+
-+ if ((mfmt->flags & V4L2_FMT_FLAG_COMPRESSED) &&
-+ f->fmt.pix.sizeimage < MIN_BUFFER_SIZE)
-+ f->fmt.pix.sizeimage = MIN_BUFFER_SIZE;
-+
-+ if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
-+ else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG)
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
-+ else
-+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
-+ f->fmt.pix.priv = 0;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Now %dx%d format %08X\n",
-+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
-+
-+ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix,
-+ __func__);
-+ return 0;
-+}
-+
-+static int mmal_setup_components(struct bm2835_mmal_dev *dev,
-+ struct v4l2_format *f)
-+{
-+ int ret;
-+ struct vchiq_mmal_port *port = NULL, *camera_port = NULL;
-+ struct vchiq_mmal_component *encode_component = NULL;
-+ struct mmal_fmt *mfmt = get_format(f);
-+
-+ BUG_ON(!mfmt);
-+
-+ if (dev->capture.encode_component) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "vid_cap - disconnect previous tunnel\n");
-+
-+ /* Disconnect any previous connection */
-+ vchiq_mmal_port_connect_tunnel(dev->instance,
-+ dev->capture.camera_port, NULL);
-+ dev->capture.camera_port = NULL;
-+ ret = vchiq_mmal_component_disable(dev->instance,
-+ dev->capture.
-+ encode_component);
-+ if (ret)
-+ v4l2_err(&dev->v4l2_dev,
-+ "Failed to disable encode component %d\n",
-+ ret);
-+
-+ dev->capture.encode_component = NULL;
-+ }
-+ /* format dependant port setup */
-+ switch (mfmt->mmal_component) {
-+ case MMAL_COMPONENT_CAMERA:
-+ /* Make a further decision on port based on resolution */
-+ if (f->fmt.pix.width <= max_video_width
-+ && f->fmt.pix.height <= max_video_height)
-+ camera_port = port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO];
-+ else
-+ camera_port = port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE];
-+ break;
-+ case MMAL_COMPONENT_IMAGE_ENCODE:
-+ encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE];
-+ port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
-+ camera_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE];
-+ break;
-+ case MMAL_COMPONENT_VIDEO_ENCODE:
-+ encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE];
-+ port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+ camera_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO];
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (!port)
-+ return -EINVAL;
-+
-+ if (encode_component)
-+ camera_port->format.encoding = MMAL_ENCODING_OPAQUE;
-+ else
-+ camera_port->format.encoding = mfmt->mmal;
-+
-+ camera_port->format.encoding_variant = 0;
-+ camera_port->es.video.width = f->fmt.pix.width;
-+ camera_port->es.video.height = f->fmt.pix.height;
-+ camera_port->es.video.crop.x = 0;
-+ camera_port->es.video.crop.y = 0;
-+ camera_port->es.video.crop.width = f->fmt.pix.width;
-+ camera_port->es.video.crop.height = f->fmt.pix.height;
-+ camera_port->es.video.frame_rate.num = 0;
-+ camera_port->es.video.frame_rate.den = 1;
-+ camera_port->es.video.color_space = MMAL_COLOR_SPACE_JPEG_JFIF;
-+
-+ ret = vchiq_mmal_port_set_format(dev->instance, camera_port);
-+
-+ if (!ret
-+ && camera_port ==
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO]) {
-+ bool overlay_enabled =
-+ !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled;
-+ struct vchiq_mmal_port *preview_port =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW];
-+ /* Preview and encode ports need to match on resolution */
-+ if (overlay_enabled) {
-+ /* Need to disable the overlay before we can update
-+ * the resolution
-+ */
-+ ret =
-+ vchiq_mmal_port_disable(dev->instance,
-+ preview_port);
-+ if (!ret)
-+ ret =
-+ vchiq_mmal_port_connect_tunnel(
-+ dev->instance,
-+ preview_port,
-+ NULL);
-+ }
-+ preview_port->es.video.width = f->fmt.pix.width;
-+ preview_port->es.video.height = f->fmt.pix.height;
-+ preview_port->es.video.crop.x = 0;
-+ preview_port->es.video.crop.y = 0;
-+ preview_port->es.video.crop.width = f->fmt.pix.width;
-+ preview_port->es.video.crop.height = f->fmt.pix.height;
-+ preview_port->es.video.frame_rate.num =
-+ dev->capture.timeperframe.denominator;
-+ preview_port->es.video.frame_rate.den =
-+ dev->capture.timeperframe.numerator;
-+ ret = vchiq_mmal_port_set_format(dev->instance, preview_port);
-+ if (overlay_enabled) {
-+ ret = vchiq_mmal_port_connect_tunnel(
-+ dev->instance,
-+ preview_port,
-+ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]);
-+ if (!ret)
-+ ret = vchiq_mmal_port_enable(dev->instance,
-+ preview_port,
-+ NULL);
-+ }
-+ }
-+
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s failed to set format %dx%d %08X\n", __func__,
-+ f->fmt.pix.width, f->fmt.pix.height,
-+ f->fmt.pix.pixelformat);
-+ /* ensure capture is not going to be tried */
-+ dev->capture.port = NULL;
-+ } else {
-+ if (encode_component) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "vid_cap - set up encode comp\n");
-+
-+ /* configure buffering */
-+ camera_port->current_buffer.size =
-+ camera_port->recommended_buffer.size;
-+ camera_port->current_buffer.num =
-+ camera_port->recommended_buffer.num;
-+
-+ ret =
-+ vchiq_mmal_port_connect_tunnel(
-+ dev->instance,
-+ camera_port,
-+ &encode_component->input[0]);
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "%s failed to create connection\n",
-+ __func__);
-+ /* ensure capture is not going to be tried */
-+ dev->capture.port = NULL;
-+ } else {
-+ port->es.video.width = f->fmt.pix.width;
-+ port->es.video.height = f->fmt.pix.height;
-+ port->es.video.crop.x = 0;
-+ port->es.video.crop.y = 0;
-+ port->es.video.crop.width = f->fmt.pix.width;
-+ port->es.video.crop.height = f->fmt.pix.height;
-+ port->es.video.frame_rate.num =
-+ dev->capture.timeperframe.denominator;
-+ port->es.video.frame_rate.den =
-+ dev->capture.timeperframe.numerator;
-+
-+ port->format.encoding = mfmt->mmal;
-+ port->format.encoding_variant = 0;
-+ /* Set any encoding specific parameters */
-+ switch (mfmt->mmal_component) {
-+ case MMAL_COMPONENT_VIDEO_ENCODE:
-+ port->format.bitrate =
-+ dev->capture.encode_bitrate;
-+ break;
-+ case MMAL_COMPONENT_IMAGE_ENCODE:
-+ /* Could set EXIF parameters here */
-+ break;
-+ default:
-+ break;
-+ }
-+ ret = vchiq_mmal_port_set_format(dev->instance,
-+ port);
-+ if (ret)
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "%s failed to set format %dx%d fmt %08X\n",
-+ __func__,
-+ f->fmt.pix.width,
-+ f->fmt.pix.height,
-+ f->fmt.pix.pixelformat
-+ );
-+ }
-+
-+ if (!ret) {
-+ ret = vchiq_mmal_component_enable(
-+ dev->instance,
-+ encode_component);
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "%s Failed to enable encode components\n",
-+ __func__);
-+ }
-+ }
-+ if (!ret) {
-+ /* configure buffering */
-+ port->current_buffer.num = 1;
-+ port->current_buffer.size =
-+ f->fmt.pix.sizeimage;
-+ if (port->format.encoding ==
-+ MMAL_ENCODING_JPEG) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "JPG - buf size now %d was %d\n",
-+ f->fmt.pix.sizeimage,
-+ port->current_buffer.size);
-+ port->current_buffer.size =
-+ (f->fmt.pix.sizeimage <
-+ (100 << 10))
-+ ? (100 << 10) : f->fmt.pix.
-+ sizeimage;
-+ }
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "vid_cap - cur_buf.size set to %d\n",
-+ f->fmt.pix.sizeimage);
-+ port->current_buffer.alignment = 0;
-+ }
-+ } else {
-+ /* configure buffering */
-+ camera_port->current_buffer.num = 1;
-+ camera_port->current_buffer.size = f->fmt.pix.sizeimage;
-+ camera_port->current_buffer.alignment = 0;
-+ }
-+
-+ if (!ret) {
-+ dev->capture.fmt = mfmt;
-+ dev->capture.stride = f->fmt.pix.bytesperline;
-+ dev->capture.width = camera_port->es.video.crop.width;
-+ dev->capture.height = camera_port->es.video.crop.height;
-+ dev->capture.buffersize = port->current_buffer.size;
-+
-+ /* select port for capture */
-+ dev->capture.port = port;
-+ dev->capture.camera_port = camera_port;
-+ dev->capture.encode_component = encode_component;
-+ v4l2_dbg(1, bcm2835_v4l2_debug,
-+ &dev->v4l2_dev,
-+ "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d",
-+ port->format.encoding,
-+ dev->capture.width, dev->capture.height,
-+ dev->capture.stride, dev->capture.buffersize);
-+ }
-+ }
-+
-+ /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */
-+ return ret;
-+}
-+
-+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
-+ struct v4l2_format *f)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct mmal_fmt *mfmt;
-+
-+ /* try the format to set valid parameters */
-+ ret = vidioc_try_fmt_vid_cap(file, priv, f);
-+ if (ret) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "vid_cap - vidioc_try_fmt_vid_cap failed\n");
-+ return ret;
-+ }
-+
-+ /* if a capture is running refuse to set format */
-+ if (vb2_is_busy(&dev->capture.vb_vidq)) {
-+ v4l2_info(&dev->v4l2_dev, "%s device busy\n", __func__);
-+ return -EBUSY;
-+ }
-+
-+ /* If the format is unsupported v4l2 says we should switch to
-+ * a supported one and not return an error. */
-+ mfmt = get_format(f);
-+ if (!mfmt) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Fourcc format (0x%08x) unknown.\n",
-+ f->fmt.pix.pixelformat);
-+ f->fmt.pix.pixelformat = formats[0].fourcc;
-+ mfmt = get_format(f);
-+ }
-+
-+ ret = mmal_setup_components(dev, f);
-+ if (ret != 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: failed to setup mmal components: %d\n",
-+ __func__, ret);
-+ ret = -EINVAL;
-+ }
-+
-+ return ret;
-+}
-+
-+int vidioc_enum_framesizes(struct file *file, void *fh,
-+ struct v4l2_frmsizeenum *fsize)
-+{
-+ static const struct v4l2_frmsize_stepwise sizes = {
-+ MIN_WIDTH, MAX_WIDTH, 2,
-+ MIN_HEIGHT, MAX_HEIGHT, 2
-+ };
-+ int i;
-+
-+ if (fsize->index)
-+ return -EINVAL;
-+ for (i = 0; i < ARRAY_SIZE(formats); i++)
-+ if (formats[i].fourcc == fsize->pixel_format)
-+ break;
-+ if (i == ARRAY_SIZE(formats))
-+ return -EINVAL;
-+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
-+ fsize->stepwise = sizes;
-+ return 0;
-+}
-+
-+/* timeperframe is arbitrary and continous */
-+static int vidioc_enum_frameintervals(struct file *file, void *priv,
-+ struct v4l2_frmivalenum *fival)
-+{
-+ int i;
-+
-+ if (fival->index)
-+ return -EINVAL;
-+
-+ for (i = 0; i < ARRAY_SIZE(formats); i++)
-+ if (formats[i].fourcc == fival->pixel_format)
-+ break;
-+ if (i == ARRAY_SIZE(formats))
-+ return -EINVAL;
-+
-+ /* regarding width & height - we support any within range */
-+ if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH ||
-+ fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT)
-+ return -EINVAL;
-+
-+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
-+
-+ /* fill in stepwise (step=1.0 is requred by V4L2 spec) */
-+ fival->stepwise.min = tpf_min;
-+ fival->stepwise.max = tpf_max;
-+ fival->stepwise.step = (struct v4l2_fract) {1, 1};
-+
-+ return 0;
-+}
-+
-+static int vidioc_g_parm(struct file *file, void *priv,
-+ struct v4l2_streamparm *parm)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+
-+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
-+ return -EINVAL;
-+
-+ parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
-+ parm->parm.capture.timeperframe = dev->capture.timeperframe;
-+ parm->parm.capture.readbuffers = 1;
-+ return 0;
-+}
-+
-+#define FRACT_CMP(a, OP, b) \
-+ ((u64)(a).numerator * (b).denominator OP \
-+ (u64)(b).numerator * (a).denominator)
-+
-+static int vidioc_s_parm(struct file *file, void *priv,
-+ struct v4l2_streamparm *parm)
-+{
-+ struct bm2835_mmal_dev *dev = video_drvdata(file);
-+ struct v4l2_fract tpf;
-+ struct mmal_parameter_rational fps_param;
-+
-+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
-+ return -EINVAL;
-+
-+ tpf = parm->parm.capture.timeperframe;
-+
-+ /* tpf: {*, 0} resets timing; clip to [min, max]*/
-+ tpf = tpf.denominator ? tpf : tpf_default;
-+ tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf;
-+ tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf;
-+
-+ dev->capture.timeperframe = tpf;
-+ parm->parm.capture.timeperframe = tpf;
-+ parm->parm.capture.readbuffers = 1;
-+
-+ fps_param.num = 0; /* Select variable fps, and then use
-+ * FPS_RANGE to select the actual limits.
-+ */
-+ fps_param.den = 1;
-+ set_framerate_params(dev);
-+
-+ return 0;
-+}
-+
-+static const struct v4l2_ioctl_ops camera0_ioctl_ops = {
-+ /* overlay */
-+ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay,
-+ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay,
-+ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay,
-+ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay,
-+ .vidioc_overlay = vidioc_overlay,
-+ .vidioc_g_fbuf = vidioc_g_fbuf,
-+
-+ /* inputs */
-+ .vidioc_enum_input = vidioc_enum_input,
-+ .vidioc_g_input = vidioc_g_input,
-+ .vidioc_s_input = vidioc_s_input,
-+
-+ /* capture */
-+ .vidioc_querycap = vidioc_querycap,
-+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
-+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
-+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
-+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
-+
-+ /* buffer management */
-+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
-+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
-+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
-+ .vidioc_querybuf = vb2_ioctl_querybuf,
-+ .vidioc_qbuf = vb2_ioctl_qbuf,
-+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
-+ .vidioc_enum_framesizes = vidioc_enum_framesizes,
-+ .vidioc_enum_frameintervals = vidioc_enum_frameintervals,
-+ .vidioc_g_parm = vidioc_g_parm,
-+ .vidioc_s_parm = vidioc_s_parm,
-+ .vidioc_streamon = vb2_ioctl_streamon,
-+ .vidioc_streamoff = vb2_ioctl_streamoff,
-+
-+ .vidioc_log_status = v4l2_ctrl_log_status,
-+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
-+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
-+};
-+
-+static const struct v4l2_ioctl_ops camera0_ioctl_ops_gstreamer = {
-+ /* overlay */
-+ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay,
-+ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay,
-+ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay,
-+ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay,
-+ .vidioc_overlay = vidioc_overlay,
-+ .vidioc_g_fbuf = vidioc_g_fbuf,
-+
-+ /* inputs */
-+ .vidioc_enum_input = vidioc_enum_input,
-+ .vidioc_g_input = vidioc_g_input,
-+ .vidioc_s_input = vidioc_s_input,
-+
-+ /* capture */
-+ .vidioc_querycap = vidioc_querycap,
-+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
-+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
-+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
-+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
-+
-+ /* buffer management */
-+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
-+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
-+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
-+ .vidioc_querybuf = vb2_ioctl_querybuf,
-+ .vidioc_qbuf = vb2_ioctl_qbuf,
-+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
-+ /* Remove this function ptr to fix gstreamer bug
-+ .vidioc_enum_framesizes = vidioc_enum_framesizes, */
-+ .vidioc_enum_frameintervals = vidioc_enum_frameintervals,
-+ .vidioc_g_parm = vidioc_g_parm,
-+ .vidioc_s_parm = vidioc_s_parm,
-+ .vidioc_streamon = vb2_ioctl_streamon,
-+ .vidioc_streamoff = vb2_ioctl_streamoff,
-+
-+ .vidioc_log_status = v4l2_ctrl_log_status,
-+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
-+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
-+};
-+
-+/* ------------------------------------------------------------------
-+ Driver init/finalise
-+ ------------------------------------------------------------------*/
-+
-+static const struct v4l2_file_operations camera0_fops = {
-+ .owner = THIS_MODULE,
-+ .open = v4l2_fh_open,
-+ .release = vb2_fop_release,
-+ .read = vb2_fop_read,
-+ .poll = vb2_fop_poll,
-+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
-+ .mmap = vb2_fop_mmap,
-+};
-+
-+static struct video_device vdev_template = {
-+ .name = "camera0",
-+ .fops = &camera0_fops,
-+ .ioctl_ops = &camera0_ioctl_ops,
-+ .release = video_device_release_empty,
-+};
-+
-+static int set_camera_parameters(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *camera)
-+{
-+ int ret;
-+ struct mmal_parameter_camera_config cam_config = {
-+ .max_stills_w = MAX_WIDTH,
-+ .max_stills_h = MAX_HEIGHT,
-+ .stills_yuv422 = 1,
-+ .one_shot_stills = 1,
-+ .max_preview_video_w = (max_video_width > 1920) ?
-+ max_video_width : 1920,
-+ .max_preview_video_h = (max_video_height > 1088) ?
-+ max_video_height : 1088,
-+ .num_preview_video_frames = 3,
-+ .stills_capture_circular_buffer_height = 0,
-+ .fast_preview_resume = 0,
-+ .use_stc_timestamp = MMAL_PARAM_TIMESTAMP_MODE_RAW_STC
-+ };
-+
-+ ret = vchiq_mmal_port_parameter_set(instance, &camera->control,
-+ MMAL_PARAMETER_CAMERA_CONFIG,
-+ &cam_config, sizeof(cam_config));
-+ return ret;
-+}
-+
-+/* MMAL instance and component init */
-+static int __init mmal_init(struct bm2835_mmal_dev *dev)
-+{
-+ int ret;
-+ struct mmal_es_format *format;
-+ u32 bool_true = 1;
-+
-+ ret = vchiq_mmal_init(&dev->instance);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* get the camera component ready */
-+ ret = vchiq_mmal_component_init(dev->instance, "ril.camera",
-+ &dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0)
-+ goto unreg_mmal;
-+
-+ if (dev->component[MMAL_COMPONENT_CAMERA]->outputs <
-+ MMAL_CAMERA_PORT_COUNT) {
-+ ret = -EINVAL;
-+ goto unreg_camera;
-+ }
-+
-+ ret = set_camera_parameters(dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+ if (ret < 0)
-+ goto unreg_camera;
-+
-+ format =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW].format;
-+
-+ format->encoding = MMAL_ENCODING_OPAQUE;
-+ format->encoding_variant = MMAL_ENCODING_I420;
-+
-+ format->es->video.width = 1024;
-+ format->es->video.height = 768;
-+ format->es->video.crop.x = 0;
-+ format->es->video.crop.y = 0;
-+ format->es->video.crop.width = 1024;
-+ format->es->video.crop.height = 768;
-+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
-+ format->es->video.frame_rate.den = 1;
-+
-+ format =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO].format;
-+
-+ format->encoding = MMAL_ENCODING_OPAQUE;
-+ format->encoding_variant = MMAL_ENCODING_I420;
-+
-+ format->es->video.width = 1024;
-+ format->es->video.height = 768;
-+ format->es->video.crop.x = 0;
-+ format->es->video.crop.y = 0;
-+ format->es->video.crop.width = 1024;
-+ format->es->video.crop.height = 768;
-+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
-+ format->es->video.frame_rate.den = 1;
-+
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO],
-+ MMAL_PARAMETER_NO_IMAGE_PADDING,
-+ &bool_true, sizeof(bool_true));
-+
-+ format =
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE].format;
-+
-+ format->encoding = MMAL_ENCODING_OPAQUE;
-+
-+ format->es->video.width = 2592;
-+ format->es->video.height = 1944;
-+ format->es->video.crop.x = 0;
-+ format->es->video.crop.y = 0;
-+ format->es->video.crop.width = 2592;
-+ format->es->video.crop.height = 1944;
-+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */
-+ format->es->video.frame_rate.den = 1;
-+
-+ dev->capture.width = format->es->video.width;
-+ dev->capture.height = format->es->video.height;
-+ dev->capture.fmt = &formats[0];
-+ dev->capture.encode_component = NULL;
-+ dev->capture.timeperframe = tpf_default;
-+ dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
-+ dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
-+
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE],
-+ MMAL_PARAMETER_NO_IMAGE_PADDING,
-+ &bool_true, sizeof(bool_true));
-+
-+ /* get the preview component ready */
-+ ret = vchiq_mmal_component_init(
-+ dev->instance, "ril.video_render",
-+ &dev->component[MMAL_COMPONENT_PREVIEW]);
-+ if (ret < 0)
-+ goto unreg_camera;
-+
-+ if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) {
-+ ret = -EINVAL;
-+ pr_debug("too few input ports %d needed %d\n",
-+ dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1);
-+ goto unreg_preview;
-+ }
-+
-+ /* get the image encoder component ready */
-+ ret = vchiq_mmal_component_init(
-+ dev->instance, "ril.image_encode",
-+ &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+ if (ret < 0)
-+ goto unreg_preview;
-+
-+ if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) {
-+ ret = -EINVAL;
-+ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
-+ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs,
-+ 1);
-+ goto unreg_image_encoder;
-+ }
-+
-+ /* get the video encoder component ready */
-+ ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode",
-+ &dev->
-+ component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+ if (ret < 0)
-+ goto unreg_image_encoder;
-+
-+ if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) {
-+ ret = -EINVAL;
-+ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
-+ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs,
-+ 1);
-+ goto unreg_vid_encoder;
-+ }
-+
-+ {
-+ struct vchiq_mmal_port *encoder_port =
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+ encoder_port->format.encoding = MMAL_ENCODING_H264;
-+ ret = vchiq_mmal_port_set_format(dev->instance,
-+ encoder_port);
-+ }
-+
-+ {
-+ unsigned int enable = 1;
-+ vchiq_mmal_port_parameter_set(
-+ dev->instance,
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
-+ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
-+ &enable, sizeof(enable));
-+
-+ vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
-+ MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
-+ &enable,
-+ sizeof(enable));
-+ }
-+ ret = bm2835_mmal_set_all_camera_controls(dev);
-+ if (ret < 0)
-+ goto unreg_vid_encoder;
-+
-+ return 0;
-+
-+unreg_vid_encoder:
-+ pr_err("Cleanup: Destroy video encoder\n");
-+ vchiq_mmal_component_finalise(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+
-+unreg_image_encoder:
-+ pr_err("Cleanup: Destroy image encoder\n");
-+ vchiq_mmal_component_finalise(
-+ dev->instance,
-+ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+
-+unreg_preview:
-+ pr_err("Cleanup: Destroy video render\n");
-+ vchiq_mmal_component_finalise(dev->instance,
-+ dev->component[MMAL_COMPONENT_PREVIEW]);
-+
-+unreg_camera:
-+ pr_err("Cleanup: Destroy camera\n");
-+ vchiq_mmal_component_finalise(dev->instance,
-+ dev->component[MMAL_COMPONENT_CAMERA]);
-+
-+unreg_mmal:
-+ vchiq_mmal_finalise(dev->instance);
-+ return ret;
-+}
-+
-+static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev,
-+ struct video_device *vfd)
-+{
-+ int ret;
-+
-+ *vfd = vdev_template;
-+ if (gst_v4l2src_is_broken) {
-+ v4l2_info(&dev->v4l2_dev,
-+ "Work-around for gstreamer issue is active.\n");
-+ vfd->ioctl_ops = &camera0_ioctl_ops_gstreamer;
-+ }
-+
-+ vfd->v4l2_dev = &dev->v4l2_dev;
-+
-+ vfd->lock = &dev->mutex;
-+
-+ vfd->queue = &dev->capture.vb_vidq;
-+
-+ /* video device needs to be able to access instance data */
-+ video_set_drvdata(vfd, dev);
-+
-+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
-+ if (ret < 0)
-+ return ret;
-+
-+ v4l2_info(vfd->v4l2_dev,
-+ "V4L2 device registered as %s - stills mode > %dx%d\n",
-+ video_device_node_name(vfd), max_video_width, max_video_height);
-+
-+ return 0;
-+}
-+
-+static struct v4l2_format default_v4l2_format = {
-+ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG,
-+ .fmt.pix.width = 1024,
-+ .fmt.pix.bytesperline = 1024,
-+ .fmt.pix.height = 768,
-+ .fmt.pix.sizeimage = 1024*768,
-+};
-+
-+static int __init bm2835_mmal_init(void)
-+{
-+ int ret;
-+ struct bm2835_mmal_dev *dev;
-+ struct vb2_queue *q;
-+
-+ dev = kzalloc(sizeof(*gdev), GFP_KERNEL);
-+ if (!dev)
-+ return -ENOMEM;
-+
-+ /* setup device defaults */
-+ dev->overlay.w.left = 150;
-+ dev->overlay.w.top = 50;
-+ dev->overlay.w.width = 1024;
-+ dev->overlay.w.height = 768;
-+ dev->overlay.clipcount = 0;
-+ dev->overlay.field = V4L2_FIELD_NONE;
-+
-+ dev->capture.fmt = &formats[3]; /* JPEG */
-+
-+ /* v4l device registration */
-+ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
-+ "%s", BM2835_MMAL_MODULE_NAME);
-+ ret = v4l2_device_register(NULL, &dev->v4l2_dev);
-+ if (ret)
-+ goto free_dev;
-+
-+ /* setup v4l controls */
-+ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler);
-+ if (ret < 0)
-+ goto unreg_dev;
-+ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler;
-+
-+ /* mmal init */
-+ ret = mmal_init(dev);
-+ if (ret < 0)
-+ goto unreg_dev;
-+
-+ /* initialize queue */
-+ q = &dev->capture.vb_vidq;
-+ memset(q, 0, sizeof(*q));
-+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
-+ q->drv_priv = dev;
-+ q->buf_struct_size = sizeof(struct mmal_buffer);
-+ q->ops = &bm2835_mmal_video_qops;
-+ q->mem_ops = &vb2_vmalloc_memops;
-+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
-+ ret = vb2_queue_init(q);
-+ if (ret < 0)
-+ goto unreg_dev;
-+
-+ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */
-+ mutex_init(&dev->mutex);
-+
-+ /* initialise video devices */
-+ ret = bm2835_mmal_init_device(dev, &dev->vdev);
-+ if (ret < 0)
-+ goto unreg_dev;
-+
-+ /* Really want to call vidioc_s_fmt_vid_cap with the default
-+ * format, but currently the APIs don't join up.
-+ */
-+ ret = mmal_setup_components(dev, &default_v4l2_format);
-+ if (ret < 0) {
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: could not setup components\n", __func__);
-+ goto unreg_dev;
-+ }
-+
-+ v4l2_info(&dev->v4l2_dev,
-+ "Broadcom 2835 MMAL video capture ver %s loaded.\n",
-+ BM2835_MMAL_VERSION);
-+
-+ gdev = dev;
-+ return 0;
-+
-+unreg_dev:
-+ v4l2_ctrl_handler_free(&dev->ctrl_handler);
-+ v4l2_device_unregister(&dev->v4l2_dev);
-+
-+free_dev:
-+ kfree(dev);
-+
-+ v4l2_err(&dev->v4l2_dev,
-+ "%s: error %d while loading driver\n",
-+ BM2835_MMAL_MODULE_NAME, ret);
-+
-+ return ret;
-+}
-+
-+static void __exit bm2835_mmal_exit(void)
-+{
-+ if (!gdev)
-+ return;
-+
-+ v4l2_info(&gdev->v4l2_dev, "unregistering %s\n",
-+ video_device_node_name(&gdev->vdev));
-+
-+ video_unregister_device(&gdev->vdev);
-+
-+ if (gdev->capture.encode_component) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev,
-+ "mmal_exit - disconnect tunnel\n");
-+ vchiq_mmal_port_connect_tunnel(gdev->instance,
-+ gdev->capture.camera_port, NULL);
-+ vchiq_mmal_component_disable(gdev->instance,
-+ gdev->capture.encode_component);
-+ }
-+ vchiq_mmal_component_disable(gdev->instance,
-+ gdev->component[MMAL_COMPONENT_CAMERA]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->
-+ component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->
-+ component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->component[MMAL_COMPONENT_PREVIEW]);
-+
-+ vchiq_mmal_component_finalise(gdev->instance,
-+ gdev->component[MMAL_COMPONENT_CAMERA]);
-+
-+ vchiq_mmal_finalise(gdev->instance);
-+
-+ v4l2_ctrl_handler_free(&gdev->ctrl_handler);
-+
-+ v4l2_device_unregister(&gdev->v4l2_dev);
-+
-+ kfree(gdev);
-+}
-+
-+module_init(bm2835_mmal_init);
-+module_exit(bm2835_mmal_exit);
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/bcm2835-camera.h linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h
---- linux-3.18.14/drivers/media/platform/bcm2835/bcm2835-camera.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,126 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * core driver device
-+ */
-+
-+#define V4L2_CTRL_COUNT 28 /* number of v4l controls */
-+
-+enum {
-+ MMAL_COMPONENT_CAMERA = 0,
-+ MMAL_COMPONENT_PREVIEW,
-+ MMAL_COMPONENT_IMAGE_ENCODE,
-+ MMAL_COMPONENT_VIDEO_ENCODE,
-+ MMAL_COMPONENT_COUNT
-+};
-+
-+enum {
-+ MMAL_CAMERA_PORT_PREVIEW = 0,
-+ MMAL_CAMERA_PORT_VIDEO,
-+ MMAL_CAMERA_PORT_CAPTURE,
-+ MMAL_CAMERA_PORT_COUNT
-+};
-+
-+#define PREVIEW_LAYER 2
-+
-+extern int bcm2835_v4l2_debug;
-+
-+struct bm2835_mmal_dev {
-+ /* v4l2 devices */
-+ struct v4l2_device v4l2_dev;
-+ struct video_device vdev;
-+ struct mutex mutex;
-+
-+ /* controls */
-+ struct v4l2_ctrl_handler ctrl_handler;
-+ struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT];
-+ enum v4l2_scene_mode scene_mode;
-+ struct mmal_colourfx colourfx;
-+ int hflip;
-+ int vflip;
-+ int red_gain;
-+ int blue_gain;
-+ enum mmal_parameter_exposuremode exposure_mode_user;
-+ enum v4l2_exposure_auto_type exposure_mode_v4l2_user;
-+ /* active exposure mode may differ if selected via a scene mode */
-+ enum mmal_parameter_exposuremode exposure_mode_active;
-+ enum mmal_parameter_exposuremeteringmode metering_mode;
-+ unsigned int manual_shutter_speed;
-+ bool exp_auto_priority;
-+
-+ /* allocated mmal instance and components */
-+ struct vchiq_mmal_instance *instance;
-+ struct vchiq_mmal_component *component[MMAL_COMPONENT_COUNT];
-+ int camera_use_count;
-+
-+ struct v4l2_window overlay;
-+
-+ struct {
-+ unsigned int width; /* width */
-+ unsigned int height; /* height */
-+ unsigned int stride; /* stride */
-+ unsigned int buffersize; /* buffer size with padding */
-+ struct mmal_fmt *fmt;
-+ struct v4l2_fract timeperframe;
-+
-+ /* H264 encode bitrate */
-+ int encode_bitrate;
-+ /* H264 bitrate mode. CBR/VBR */
-+ int encode_bitrate_mode;
-+ /* H264 profile */
-+ enum v4l2_mpeg_video_h264_profile enc_profile;
-+ /* H264 level */
-+ enum v4l2_mpeg_video_h264_level enc_level;
-+ /* JPEG Q-factor */
-+ int q_factor;
-+
-+ struct vb2_queue vb_vidq;
-+
-+ /* VC start timestamp for streaming */
-+ s64 vc_start_timestamp;
-+ /* Kernel start timestamp for streaming */
-+ struct timeval kernel_start_ts;
-+
-+ struct vchiq_mmal_port *port; /* port being used for capture */
-+ /* camera port being used for capture */
-+ struct vchiq_mmal_port *camera_port;
-+ /* component being used for encode */
-+ struct vchiq_mmal_component *encode_component;
-+ /* number of frames remaining which driver should capture */
-+ unsigned int frame_count;
-+ /* last frame completion */
-+ struct completion frame_cmplt;
-+
-+ } capture;
-+
-+};
-+
-+int bm2835_mmal_init_controls(
-+ struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl_handler *hdl);
-+
-+int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev);
-+int set_framerate_params(struct bm2835_mmal_dev *dev);
-+
-+/* Debug helpers */
-+
-+#define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \
-+{ \
-+ v4l2_dbg(level, debug, dev, \
-+"%s: w %u h %u field %u pfmt 0x%x bpl %u sz_img %u colorspace 0x%x priv %u\n", \
-+ desc == NULL ? "" : desc, \
-+ (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \
-+ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
-+ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
-+}
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/controls.c linux-rpi/drivers/media/platform/bcm2835/controls.c
---- linux-3.18.14/drivers/media/platform/bcm2835/controls.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/controls.c 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,1322 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <media/videobuf2-vmalloc.h>
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-ioctl.h>
-+#include <media/v4l2-ctrls.h>
-+#include <media/v4l2-fh.h>
-+#include <media/v4l2-event.h>
-+#include <media/v4l2-common.h>
-+
-+#include "mmal-common.h"
-+#include "mmal-vchiq.h"
-+#include "mmal-parameters.h"
-+#include "bcm2835-camera.h"
-+
-+/* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0.
-+ * MMAL values are in 1/6th increments so the MMAL range is -24 to +24.
-+ * V4L2 docs say value "is expressed in terms of EV, drivers should interpret
-+ * the values as 0.001 EV units, where the value 1000 stands for +1 EV."
-+ * V4L2 is limited to a max of 32 values in a menu, so count in 1/3rds from
-+ * -4 to +4
-+ */
-+static const s64 ev_bias_qmenu[] = {
-+ -4000, -3667, -3333,
-+ -3000, -2667, -2333,
-+ -2000, -1667, -1333,
-+ -1000, -667, -333,
-+ 0, 333, 667,
-+ 1000, 1333, 1667,
-+ 2000, 2333, 2667,
-+ 3000, 3333, 3667,
-+ 4000
-+};
-+
-+/* Supported ISO values
-+ * ISOO = auto ISO
-+ */
-+static const s64 iso_qmenu[] = {
-+ 0, 100, 200, 400, 800,
-+};
-+
-+static const s64 mains_freq_qmenu[] = {
-+ V4L2_CID_POWER_LINE_FREQUENCY_DISABLED,
-+ V4L2_CID_POWER_LINE_FREQUENCY_50HZ,
-+ V4L2_CID_POWER_LINE_FREQUENCY_60HZ,
-+ V4L2_CID_POWER_LINE_FREQUENCY_AUTO
-+};
-+
-+/* Supported video encode modes */
-+static const s64 bitrate_mode_qmenu[] = {
-+ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
-+ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
-+};
-+
-+enum bm2835_mmal_ctrl_type {
-+ MMAL_CONTROL_TYPE_STD,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ MMAL_CONTROL_TYPE_INT_MENU,
-+ MMAL_CONTROL_TYPE_CLUSTER, /* special cluster entry */
-+};
-+
-+struct bm2835_mmal_v4l2_ctrl;
-+
-+typedef int(bm2835_mmal_v4l2_ctrl_cb)(
-+ struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl);
-+
-+struct bm2835_mmal_v4l2_ctrl {
-+ u32 id; /* v4l2 control identifier */
-+ enum bm2835_mmal_ctrl_type type;
-+ /* control minimum value or
-+ * mask for MMAL_CONTROL_TYPE_STD_MENU */
-+ s32 min;
-+ s32 max; /* maximum value of control */
-+ s32 def; /* default value of control */
-+ s32 step; /* step size of the control */
-+ const s64 *imenu; /* integer menu array */
-+ u32 mmal_id; /* mmal parameter id */
-+ bm2835_mmal_v4l2_ctrl_cb *setter;
-+ bool ignore_errors;
-+};
-+
-+struct v4l2_to_mmal_effects_setting {
-+ u32 v4l2_effect;
-+ u32 mmal_effect;
-+ s32 col_fx_enable;
-+ s32 col_fx_fixed_cbcr;
-+ u32 u;
-+ u32 v;
-+ u32 num_effect_params;
-+ u32 effect_params[MMAL_MAX_IMAGEFX_PARAMETERS];
-+};
-+
-+static const struct v4l2_to_mmal_effects_setting
-+ v4l2_to_mmal_effects_values[] = {
-+ { V4L2_COLORFX_NONE, MMAL_PARAM_IMAGEFX_NONE,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_BW, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 0, 128, 128, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SEPIA, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 0, 87, 151, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_NEGATIVE, MMAL_PARAM_IMAGEFX_NEGATIVE,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_EMBOSS, MMAL_PARAM_IMAGEFX_EMBOSS,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SKETCH, MMAL_PARAM_IMAGEFX_SKETCH,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SKY_BLUE, MMAL_PARAM_IMAGEFX_PASTEL,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_GRASS_GREEN, MMAL_PARAM_IMAGEFX_WATERCOLOUR,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SKIN_WHITEN, MMAL_PARAM_IMAGEFX_WASHEDOUT,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_VIVID, MMAL_PARAM_IMAGEFX_SATURATION,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_AQUA, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 0, 171, 121, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_ART_FREEZE, MMAL_PARAM_IMAGEFX_HATCH,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SILHOUETTE, MMAL_PARAM_IMAGEFX_FILM,
-+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} },
-+ { V4L2_COLORFX_SOLARIZATION, MMAL_PARAM_IMAGEFX_SOLARIZE,
-+ 0, 0, 0, 0, 5, {1, 128, 160, 160, 48} },
-+ { V4L2_COLORFX_ANTIQUE, MMAL_PARAM_IMAGEFX_COLOURBALANCE,
-+ 0, 0, 0, 0, 3, {108, 274, 238, 0, 0} },
-+ { V4L2_COLORFX_SET_CBCR, MMAL_PARAM_IMAGEFX_NONE,
-+ 1, 1, 0, 0, 0, {0, 0, 0, 0, 0} }
-+};
-+
-+struct v4l2_mmal_scene_config {
-+ enum v4l2_scene_mode v4l2_scene;
-+ enum mmal_parameter_exposuremode exposure_mode;
-+ enum mmal_parameter_exposuremeteringmode metering_mode;
-+};
-+
-+static const struct v4l2_mmal_scene_config scene_configs[] = {
-+ /* V4L2_SCENE_MODE_NONE automatically added */
-+ {
-+ V4L2_SCENE_MODE_NIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_NIGHT,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE
-+ },
-+ {
-+ V4L2_SCENE_MODE_SPORTS,
-+ MMAL_PARAM_EXPOSUREMODE_SPORTS,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE
-+ },
-+};
-+
-+/* control handlers*/
-+
-+static int ctrl_set_rational(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ struct mmal_parameter_rational rational_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ rational_value.num = ctrl->val;
-+ rational_value.den = 100;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &rational_value,
-+ sizeof(rational_value));
-+}
-+
-+static int ctrl_set_value(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ u32_value = ctrl->val;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min)
-+ return 1;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ u32_value = mmal_ctrl->imenu[ctrl->val];
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_value_ev(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ s32 s32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ s32_value = (ctrl->val-12)*2; /* Convert from index to 1/6ths */
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &s32_value, sizeof(s32_value));
-+}
-+
-+static int ctrl_set_rotate(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret;
-+ u32 u32_value;
-+ struct vchiq_mmal_component *camera;
-+
-+ camera = dev->component[MMAL_COMPONENT_CAMERA];
-+
-+ u32_value = ((ctrl->val % 360) / 90) * 90;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+
-+ return ret;
-+}
-+
-+static int ctrl_set_flip(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret;
-+ u32 u32_value;
-+ struct vchiq_mmal_component *camera;
-+
-+ if (ctrl->id == V4L2_CID_HFLIP)
-+ dev->hflip = ctrl->val;
-+ else
-+ dev->vflip = ctrl->val;
-+
-+ camera = dev->component[MMAL_COMPONENT_CAMERA];
-+
-+ if (dev->hflip && dev->vflip)
-+ u32_value = MMAL_PARAM_MIRROR_BOTH;
-+ else if (dev->hflip)
-+ u32_value = MMAL_PARAM_MIRROR_HORIZONTAL;
-+ else if (dev->vflip)
-+ u32_value = MMAL_PARAM_MIRROR_VERTICAL;
-+ else
-+ u32_value = MMAL_PARAM_MIRROR_NONE;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2],
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+
-+ return ret;
-+
-+}
-+
-+static int ctrl_set_exposure(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ enum mmal_parameter_exposuremode exp_mode = dev->exposure_mode_user;
-+ u32 shutter_speed = 0;
-+ struct vchiq_mmal_port *control;
-+ int ret = 0;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED) {
-+ /* V4L2 is in 100usec increments.
-+ * MMAL is 1usec.
-+ */
-+ dev->manual_shutter_speed = ctrl->val * 100;
-+ } else if (mmal_ctrl->mmal_id == MMAL_PARAMETER_EXPOSURE_MODE) {
-+ switch (ctrl->val) {
-+ case V4L2_EXPOSURE_AUTO:
-+ exp_mode = MMAL_PARAM_EXPOSUREMODE_AUTO;
-+ break;
-+
-+ case V4L2_EXPOSURE_MANUAL:
-+ exp_mode = MMAL_PARAM_EXPOSUREMODE_OFF;
-+ break;
-+ }
-+ dev->exposure_mode_user = exp_mode;
-+ dev->exposure_mode_v4l2_user = ctrl->val;
-+ } else if (mmal_ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {
-+ dev->exp_auto_priority = ctrl->val;
-+ }
-+
-+ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) {
-+ if (exp_mode == MMAL_PARAM_EXPOSUREMODE_OFF)
-+ shutter_speed = dev->manual_shutter_speed;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &shutter_speed,
-+ sizeof(shutter_speed));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &exp_mode,
-+ sizeof(u32));
-+ dev->exposure_mode_active = exp_mode;
-+ }
-+ /* exposure_dynamic_framerate (V4L2_CID_EXPOSURE_AUTO_PRIORITY) should
-+ * always apply irrespective of scene mode.
-+ */
-+ ret += set_framerate_params(dev);
-+
-+ return ret;
-+}
-+
-+static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ switch (ctrl->val) {
-+ case V4L2_EXPOSURE_METERING_AVERAGE:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE;
-+ break;
-+
-+ case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT;
-+ break;
-+
-+ case V4L2_EXPOSURE_METERING_SPOT:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT;
-+ break;
-+
-+ /* todo matrix weighting not added to Linux API till 3.9
-+ case V4L2_EXPOSURE_METERING_MATRIX:
-+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX;
-+ break;
-+ */
-+
-+ }
-+
-+ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) {
-+ struct vchiq_mmal_port *control;
-+ u32 u32_value = dev->metering_mode;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+ } else
-+ return 0;
-+}
-+
-+static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ switch (ctrl->val) {
-+ case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_OFF;
-+ break;
-+ case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_50HZ;
-+ break;
-+ case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_60HZ;
-+ break;
-+ case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
-+ u32_value = MMAL_PARAM_FLICKERAVOID_AUTO;
-+ break;
-+ }
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_awb_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ switch (ctrl->val) {
-+ case V4L2_WHITE_BALANCE_MANUAL:
-+ u32_value = MMAL_PARAM_AWBMODE_OFF;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_AUTO:
-+ u32_value = MMAL_PARAM_AWBMODE_AUTO;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_INCANDESCENT:
-+ u32_value = MMAL_PARAM_AWBMODE_INCANDESCENT;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_FLUORESCENT:
-+ u32_value = MMAL_PARAM_AWBMODE_FLUORESCENT;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_FLUORESCENT_H:
-+ u32_value = MMAL_PARAM_AWBMODE_TUNGSTEN;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_HORIZON:
-+ u32_value = MMAL_PARAM_AWBMODE_HORIZON;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_DAYLIGHT:
-+ u32_value = MMAL_PARAM_AWBMODE_SUNLIGHT;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_FLASH:
-+ u32_value = MMAL_PARAM_AWBMODE_FLASH;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_CLOUDY:
-+ u32_value = MMAL_PARAM_AWBMODE_CLOUDY;
-+ break;
-+
-+ case V4L2_WHITE_BALANCE_SHADE:
-+ u32_value = MMAL_PARAM_AWBMODE_SHADE;
-+ break;
-+
-+ }
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_awb_gains(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ struct vchiq_mmal_port *control;
-+ struct mmal_parameter_awbgains gains;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ if (ctrl->id == V4L2_CID_RED_BALANCE)
-+ dev->red_gain = ctrl->val;
-+ else if (ctrl->id == V4L2_CID_BLUE_BALANCE)
-+ dev->blue_gain = ctrl->val;
-+
-+ gains.r_gain.num = dev->red_gain;
-+ gains.b_gain.num = dev->blue_gain;
-+ gains.r_gain.den = gains.b_gain.den = 1000;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, control,
-+ mmal_ctrl->mmal_id,
-+ &gains, sizeof(gains));
-+}
-+
-+static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret = -EINVAL;
-+ int i, j;
-+ struct vchiq_mmal_port *control;
-+ struct mmal_parameter_imagefx_parameters imagefx;
-+
-+ for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) {
-+ if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) {
-+
-+ imagefx.effect =
-+ v4l2_to_mmal_effects_values[i].mmal_effect;
-+ imagefx.num_effect_params =
-+ v4l2_to_mmal_effects_values[i].num_effect_params;
-+
-+ if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS)
-+ imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS;
-+
-+ for (j = 0; j < imagefx.num_effect_params; j++)
-+ imagefx.effect_parameter[j] =
-+ v4l2_to_mmal_effects_values[i].effect_params[j];
-+
-+ dev->colourfx.enable =
-+ v4l2_to_mmal_effects_values[i].col_fx_enable;
-+ if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) {
-+ dev->colourfx.u =
-+ v4l2_to_mmal_effects_values[i].u;
-+ dev->colourfx.v =
-+ v4l2_to_mmal_effects_values[i].v;
-+ }
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ ret = vchiq_mmal_port_parameter_set(
-+ dev->instance, control,
-+ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
-+ &imagefx, sizeof(imagefx));
-+ if (ret)
-+ goto exit;
-+
-+ ret = vchiq_mmal_port_parameter_set(
-+ dev->instance, control,
-+ MMAL_PARAMETER_COLOUR_EFFECT,
-+ &dev->colourfx, sizeof(dev->colourfx));
-+ }
-+ }
-+
-+exit:
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "mmal_ctrl:%p ctrl id:0x%x ctrl val:%d imagefx:0x%x color_effect:%s u:%d v:%d ret %d(%d)\n",
-+ mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect,
-+ dev->colourfx.enable ? "true" : "false",
-+ dev->colourfx.u, dev->colourfx.v,
-+ ret, (ret == 0 ? 0 : -EINVAL));
-+ return (ret == 0 ? 0 : EINVAL);
-+}
-+
-+static int ctrl_set_colfx(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret = -EINVAL;
-+ struct vchiq_mmal_port *control;
-+
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ dev->colourfx.enable = (ctrl->val & 0xff00) >> 8;
-+ dev->colourfx.enable = ctrl->val & 0xff;
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_COLOUR_EFFECT,
-+ &dev->colourfx, sizeof(dev->colourfx));
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n",
-+ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret,
-+ (ret == 0 ? 0 : -EINVAL));
-+ return (ret == 0 ? 0 : EINVAL);
-+}
-+
-+static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret;
-+ struct vchiq_mmal_port *encoder_out;
-+
-+ dev->capture.encode_bitrate = ctrl->val;
-+
-+ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
-+ mmal_ctrl->mmal_id,
-+ &ctrl->val, sizeof(ctrl->val));
-+ ret = 0;
-+ return ret;
-+}
-+
-+static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 bitrate_mode;
-+ struct vchiq_mmal_port *encoder_out;
-+
-+ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+
-+ dev->capture.encode_bitrate_mode = ctrl->val;
-+ switch (ctrl->val) {
-+ default:
-+ case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
-+ bitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE;
-+ break;
-+ case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
-+ bitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT;
-+ break;
-+ }
-+
-+ vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
-+ mmal_ctrl->mmal_id,
-+ &bitrate_mode,
-+ sizeof(bitrate_mode));
-+ return 0;
-+}
-+
-+static int ctrl_set_image_encode_output(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *jpeg_out;
-+
-+ jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
-+
-+ u32_value = ctrl->val;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, jpeg_out,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_video_encode_param_output(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ u32 u32_value;
-+ struct vchiq_mmal_port *vid_enc_ctl;
-+
-+ vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+
-+ u32_value = ctrl->val;
-+
-+ return vchiq_mmal_port_parameter_set(dev->instance, vid_enc_ctl,
-+ mmal_ctrl->mmal_id,
-+ &u32_value, sizeof(u32_value));
-+}
-+
-+static int ctrl_set_video_encode_profile_level(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ struct mmal_parameter_video_profile param;
-+ int ret = 0;
-+
-+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) {
-+ switch (ctrl->val) {
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
-+ dev->capture.enc_profile = ctrl->val;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) {
-+ switch (ctrl->val) {
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
-+ dev->capture.enc_level = ctrl->val;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+ }
-+
-+ if (!ret) {
-+ switch (dev->capture.enc_profile) {
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
-+ param.profile = MMAL_VIDEO_PROFILE_H264_BASELINE;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
-+ param.profile =
-+ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
-+ param.profile = MMAL_VIDEO_PROFILE_H264_MAIN;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
-+ param.profile = MMAL_VIDEO_PROFILE_H264_HIGH;
-+ break;
-+ default:
-+ /* Should never get here */
-+ break;
-+ }
-+
-+ switch (dev->capture.enc_level) {
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_1;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
-+ param.level = MMAL_VIDEO_LEVEL_H264_1b;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
-+ param.level = MMAL_VIDEO_LEVEL_H264_11;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
-+ param.level = MMAL_VIDEO_LEVEL_H264_12;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
-+ param.level = MMAL_VIDEO_LEVEL_H264_13;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_2;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
-+ param.level = MMAL_VIDEO_LEVEL_H264_21;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
-+ param.level = MMAL_VIDEO_LEVEL_H264_22;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_3;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
-+ param.level = MMAL_VIDEO_LEVEL_H264_31;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
-+ param.level = MMAL_VIDEO_LEVEL_H264_32;
-+ break;
-+ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
-+ param.level = MMAL_VIDEO_LEVEL_H264_4;
-+ break;
-+ default:
-+ /* Should never get here */
-+ break;
-+ }
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0],
-+ mmal_ctrl->mmal_id,
-+ &param, sizeof(param));
-+ }
-+ return ret;
-+}
-+
-+static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl *ctrl,
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
-+{
-+ int ret = 0;
-+ int shutter_speed;
-+ struct vchiq_mmal_port *control;
-+
-+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "scene mode selected %d, was %d\n", ctrl->val,
-+ dev->scene_mode);
-+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+
-+ if (ctrl->val == dev->scene_mode)
-+ return 0;
-+
-+ if (ctrl->val == V4L2_SCENE_MODE_NONE) {
-+ /* Restore all user selections */
-+ dev->scene_mode = V4L2_SCENE_MODE_NONE;
-+
-+ if (dev->exposure_mode_user == MMAL_PARAM_EXPOSUREMODE_OFF)
-+ shutter_speed = dev->manual_shutter_speed;
-+ else
-+ shutter_speed = 0;
-+
-+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n",
-+ __func__, shutter_speed, dev->exposure_mode_user,
-+ dev->metering_mode);
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &shutter_speed,
-+ sizeof(shutter_speed));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &dev->exposure_mode_user,
-+ sizeof(u32));
-+ dev->exposure_mode_active = dev->exposure_mode_user;
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXP_METERING_MODE,
-+ &dev->metering_mode,
-+ sizeof(u32));
-+ ret += set_framerate_params(dev);
-+ } else {
-+ /* Set up scene mode */
-+ int i;
-+ const struct v4l2_mmal_scene_config *scene = NULL;
-+ int shutter_speed;
-+ enum mmal_parameter_exposuremode exposure_mode;
-+ enum mmal_parameter_exposuremeteringmode metering_mode;
-+
-+ for (i = 0; i < ARRAY_SIZE(scene_configs); i++) {
-+ if (scene_configs[i].v4l2_scene ==
-+ ctrl->val) {
-+ scene = &scene_configs[i];
-+ break;
-+ }
-+ }
-+ if (i >= ARRAY_SIZE(scene_configs))
-+ return -EINVAL;
-+
-+ /* Set all the values */
-+ dev->scene_mode = ctrl->val;
-+
-+ if (scene->exposure_mode == MMAL_PARAM_EXPOSUREMODE_OFF)
-+ shutter_speed = dev->manual_shutter_speed;
-+ else
-+ shutter_speed = 0;
-+ exposure_mode = scene->exposure_mode;
-+ metering_mode = scene->metering_mode;
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n",
-+ __func__, shutter_speed, exposure_mode, metering_mode);
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &shutter_speed,
-+ sizeof(shutter_speed));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &exposure_mode,
-+ sizeof(u32));
-+ dev->exposure_mode_active = exposure_mode;
-+ ret += vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &exposure_mode,
-+ sizeof(u32));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance, control,
-+ MMAL_PARAMETER_EXP_METERING_MODE,
-+ &metering_mode,
-+ sizeof(u32));
-+ ret += set_framerate_params(dev);
-+ }
-+ if (ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "%s: Setting scene to %d, ret=%d\n",
-+ __func__, ctrl->val, ret);
-+ ret = -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+static int bm2835_mmal_s_ctrl(struct v4l2_ctrl *ctrl)
-+{
-+ struct bm2835_mmal_dev *dev =
-+ container_of(ctrl->handler, struct bm2835_mmal_dev,
-+ ctrl_handler);
-+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl = ctrl->priv;
-+ int ret;
-+
-+ if ((mmal_ctrl == NULL) ||
-+ (mmal_ctrl->id != ctrl->id) ||
-+ (mmal_ctrl->setter == NULL)) {
-+ pr_warn("mmal_ctrl:%p ctrl id:%d\n", mmal_ctrl, ctrl->id);
-+ return -EINVAL;
-+ }
-+
-+ ret = mmal_ctrl->setter(dev, ctrl, mmal_ctrl);
-+ if (ret)
-+ pr_warn("ctrl id:%d/MMAL param %08X- returned ret %d\n",
-+ ctrl->id, mmal_ctrl->mmal_id, ret);
-+ if (mmal_ctrl->ignore_errors)
-+ ret = 0;
-+ return ret;
-+}
-+
-+static const struct v4l2_ctrl_ops bm2835_mmal_ctrl_ops = {
-+ .s_ctrl = bm2835_mmal_s_ctrl,
-+};
-+
-+
-+
-+static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = {
-+ {
-+ V4L2_CID_SATURATION, MMAL_CONTROL_TYPE_STD,
-+ -100, 100, 0, 1, NULL,
-+ MMAL_PARAMETER_SATURATION,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_SHARPNESS, MMAL_CONTROL_TYPE_STD,
-+ -100, 100, 0, 1, NULL,
-+ MMAL_PARAMETER_SHARPNESS,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_CONTRAST, MMAL_CONTROL_TYPE_STD,
-+ -100, 100, 0, 1, NULL,
-+ MMAL_PARAMETER_CONTRAST,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_BRIGHTNESS, MMAL_CONTROL_TYPE_STD,
-+ 0, 100, 50, 1, NULL,
-+ MMAL_PARAMETER_BRIGHTNESS,
-+ &ctrl_set_rational,
-+ false
-+ },
-+ {
-+ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU,
-+ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu,
-+ MMAL_PARAMETER_ISO,
-+ &ctrl_set_value_menu,
-+ false
-+ },
-+ {
-+ V4L2_CID_IMAGE_STABILIZATION, MMAL_CONTROL_TYPE_STD,
-+ 0, 1, 0, 1, NULL,
-+ MMAL_PARAMETER_VIDEO_STABILISATION,
-+ &ctrl_set_value,
-+ false
-+ },
-+/* {
-+ 0, MMAL_CONTROL_TYPE_CLUSTER, 3, 1, 0, NULL, 0, NULL
-+ }, */
-+ {
-+ V4L2_CID_EXPOSURE_AUTO, MMAL_CONTROL_TYPE_STD_MENU,
-+ ~0x03, 3, V4L2_EXPOSURE_AUTO, 0, NULL,
-+ MMAL_PARAMETER_EXPOSURE_MODE,
-+ &ctrl_set_exposure,
-+ false
-+ },
-+/* todo this needs mixing in with set exposure
-+ {
-+ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
-+ },
-+ */
-+ {
-+ V4L2_CID_EXPOSURE_ABSOLUTE, MMAL_CONTROL_TYPE_STD,
-+ /* Units of 100usecs */
-+ 1, 1*1000*10, 100*10, 1, NULL,
-+ MMAL_PARAMETER_SHUTTER_SPEED,
-+ &ctrl_set_exposure,
-+ false
-+ },
-+ {
-+ V4L2_CID_AUTO_EXPOSURE_BIAS, MMAL_CONTROL_TYPE_INT_MENU,
-+ 0, ARRAY_SIZE(ev_bias_qmenu) - 1,
-+ (ARRAY_SIZE(ev_bias_qmenu)+1)/2 - 1, 0, ev_bias_qmenu,
-+ MMAL_PARAMETER_EXPOSURE_COMP,
-+ &ctrl_set_value_ev,
-+ false
-+ },
-+ {
-+ V4L2_CID_EXPOSURE_AUTO_PRIORITY, MMAL_CONTROL_TYPE_STD,
-+ 0, 1,
-+ 0, 1, NULL,
-+ 0, /* Dummy MMAL ID as it gets mapped into FPS range*/
-+ &ctrl_set_exposure,
-+ false
-+ },
-+ {
-+ V4L2_CID_EXPOSURE_METERING,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ ~0x7, 2, V4L2_EXPOSURE_METERING_AVERAGE, 0, NULL,
-+ MMAL_PARAMETER_EXP_METERING_MODE,
-+ &ctrl_set_metering_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ ~0x3ff, 9, V4L2_WHITE_BALANCE_AUTO, 0, NULL,
-+ MMAL_PARAMETER_AWB_MODE,
-+ &ctrl_set_awb_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_RED_BALANCE, MMAL_CONTROL_TYPE_STD,
-+ 1, 7999, 1000, 1, NULL,
-+ MMAL_PARAMETER_CUSTOM_AWB_GAINS,
-+ &ctrl_set_awb_gains,
-+ false
-+ },
-+ {
-+ V4L2_CID_BLUE_BALANCE, MMAL_CONTROL_TYPE_STD,
-+ 1, 7999, 1000, 1, NULL,
-+ MMAL_PARAMETER_CUSTOM_AWB_GAINS,
-+ &ctrl_set_awb_gains,
-+ false
-+ },
-+ {
-+ V4L2_CID_COLORFX, MMAL_CONTROL_TYPE_STD_MENU,
-+ 0, 15, V4L2_COLORFX_NONE, 0, NULL,
-+ MMAL_PARAMETER_IMAGE_EFFECT,
-+ &ctrl_set_image_effect,
-+ false
-+ },
-+ {
-+ V4L2_CID_COLORFX_CBCR, MMAL_CONTROL_TYPE_STD,
-+ 0, 0xffff, 0x8080, 1, NULL,
-+ MMAL_PARAMETER_COLOUR_EFFECT,
-+ &ctrl_set_colfx,
-+ false
-+ },
-+ {
-+ V4L2_CID_ROTATE, MMAL_CONTROL_TYPE_STD,
-+ 0, 360, 0, 90, NULL,
-+ MMAL_PARAMETER_ROTATION,
-+ &ctrl_set_rotate,
-+ false
-+ },
-+ {
-+ V4L2_CID_HFLIP, MMAL_CONTROL_TYPE_STD,
-+ 0, 1, 0, 1, NULL,
-+ MMAL_PARAMETER_MIRROR,
-+ &ctrl_set_flip,
-+ false
-+ },
-+ {
-+ V4L2_CID_VFLIP, MMAL_CONTROL_TYPE_STD,
-+ 0, 1, 0, 1, NULL,
-+ MMAL_PARAMETER_MIRROR,
-+ &ctrl_set_flip,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_BITRATE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
-+ 0, ARRAY_SIZE(bitrate_mode_qmenu) - 1,
-+ 0, 0, bitrate_mode_qmenu,
-+ MMAL_PARAMETER_RATECONTROL,
-+ &ctrl_set_bitrate_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_BITRATE, MMAL_CONTROL_TYPE_STD,
-+ 25*1000, 25*1000*1000, 10*1000*1000, 25*1000, NULL,
-+ MMAL_PARAMETER_VIDEO_BIT_RATE,
-+ &ctrl_set_bitrate,
-+ false
-+ },
-+ {
-+ V4L2_CID_JPEG_COMPRESSION_QUALITY, MMAL_CONTROL_TYPE_STD,
-+ 1, 100,
-+ 30, 1, NULL,
-+ MMAL_PARAMETER_JPEG_Q_FACTOR,
-+ &ctrl_set_image_encode_output,
-+ false
-+ },
-+ {
-+ V4L2_CID_POWER_LINE_FREQUENCY, MMAL_CONTROL_TYPE_STD_MENU,
-+ 0, ARRAY_SIZE(mains_freq_qmenu) - 1,
-+ 1, 1, NULL,
-+ MMAL_PARAMETER_FLICKER_AVOID,
-+ &ctrl_set_flicker_avoidance,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER, MMAL_CONTROL_TYPE_STD,
-+ 0, 1,
-+ 0, 1, NULL,
-+ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER,
-+ &ctrl_set_video_encode_param_output,
-+ true /* Errors ignored as requires latest firmware to work */
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_H264_PROFILE,
-+ MMAL_CONTROL_TYPE_STD_MENU,
-+ ~((1<<V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
-+ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
-+ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
-+ (1<<V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
-+ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
-+ V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 1, NULL,
-+ MMAL_PARAMETER_PROFILE,
-+ &ctrl_set_video_encode_profile_level,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_H264_LEVEL, MMAL_CONTROL_TYPE_STD_MENU,
-+ ~((1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
-+ (1<<V4L2_MPEG_VIDEO_H264_LEVEL_4_0)),
-+ V4L2_MPEG_VIDEO_H264_LEVEL_4_0,
-+ V4L2_MPEG_VIDEO_H264_LEVEL_4_0, 1, NULL,
-+ MMAL_PARAMETER_PROFILE,
-+ &ctrl_set_video_encode_profile_level,
-+ false
-+ },
-+ {
-+ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU,
-+ -1, /* Min is computed at runtime */
-+ V4L2_SCENE_MODE_TEXT,
-+ V4L2_SCENE_MODE_NONE, 1, NULL,
-+ MMAL_PARAMETER_PROFILE,
-+ &ctrl_set_scene_mode,
-+ false
-+ },
-+ {
-+ V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, MMAL_CONTROL_TYPE_STD,
-+ 0, 0x7FFFFFFF, 60, 1, NULL,
-+ MMAL_PARAMETER_INTRAPERIOD,
-+ &ctrl_set_video_encode_param_output,
-+ false
-+ },
-+};
-+
-+int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev)
-+{
-+ int c;
-+ int ret = 0;
-+
-+ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
-+ if ((dev->ctrls[c]) && (v4l2_ctrls[c].setter)) {
-+ ret = v4l2_ctrls[c].setter(dev, dev->ctrls[c],
-+ &v4l2_ctrls[c]);
-+ if (!v4l2_ctrls[c].ignore_errors && ret) {
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Failed when setting default values for ctrl %d\n",
-+ c);
-+ break;
-+ }
-+ }
-+ }
-+ return ret;
-+}
-+
-+int set_framerate_params(struct bm2835_mmal_dev *dev)
-+{
-+ struct mmal_parameter_fps_range fps_range;
-+ int ret;
-+
-+ if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) &&
-+ (dev->exp_auto_priority)) {
-+ /* Variable FPS. Define min FPS as 1fps.
-+ * Max as max defined FPS.
-+ */
-+ fps_range.fps_low.num = 1;
-+ fps_range.fps_low.den = 1;
-+ fps_range.fps_high.num = dev->capture.timeperframe.denominator;
-+ fps_range.fps_high.den = dev->capture.timeperframe.numerator;
-+ } else {
-+ /* Fixed FPS - set min and max to be the same */
-+ fps_range.fps_low.num = fps_range.fps_high.num =
-+ dev->capture.timeperframe.denominator;
-+ fps_range.fps_low.den = fps_range.fps_high.den =
-+ dev->capture.timeperframe.numerator;
-+ }
-+
-+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Set fps range to %d/%d to %d/%d\n",
-+ fps_range.fps_low.num,
-+ fps_range.fps_low.den,
-+ fps_range.fps_high.num,
-+ fps_range.fps_high.den
-+ );
-+
-+ ret = vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_PREVIEW],
-+ MMAL_PARAMETER_FPS_RANGE,
-+ &fps_range, sizeof(fps_range));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_VIDEO],
-+ MMAL_PARAMETER_FPS_RANGE,
-+ &fps_range, sizeof(fps_range));
-+ ret += vchiq_mmal_port_parameter_set(dev->instance,
-+ &dev->component[MMAL_COMPONENT_CAMERA]->
-+ output[MMAL_CAMERA_PORT_CAPTURE],
-+ MMAL_PARAMETER_FPS_RANGE,
-+ &fps_range, sizeof(fps_range));
-+ if (ret)
-+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+ "Failed to set fps ret %d\n",
-+ ret);
-+
-+ return ret;
-+
-+}
-+
-+int bm2835_mmal_init_controls(struct bm2835_mmal_dev *dev,
-+ struct v4l2_ctrl_handler *hdl)
-+{
-+ int c;
-+ const struct bm2835_mmal_v4l2_ctrl *ctrl;
-+
-+ v4l2_ctrl_handler_init(hdl, V4L2_CTRL_COUNT);
-+
-+ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
-+ ctrl = &v4l2_ctrls[c];
-+
-+ switch (ctrl->type) {
-+ case MMAL_CONTROL_TYPE_STD:
-+ dev->ctrls[c] = v4l2_ctrl_new_std(hdl,
-+ &bm2835_mmal_ctrl_ops, ctrl->id,
-+ ctrl->min, ctrl->max, ctrl->step, ctrl->def);
-+ break;
-+
-+ case MMAL_CONTROL_TYPE_STD_MENU:
-+ {
-+ int mask = ctrl->min;
-+
-+ if (ctrl->id == V4L2_CID_SCENE_MODE) {
-+ /* Special handling to work out the mask
-+ * value based on the scene_configs array
-+ * at runtime. Reduces the chance of
-+ * mismatches.
-+ */
-+ int i;
-+ mask = 1<<V4L2_SCENE_MODE_NONE;
-+ for (i = 0;
-+ i < ARRAY_SIZE(scene_configs);
-+ i++) {
-+ mask |= 1<<scene_configs[i].v4l2_scene;
-+ }
-+ mask = ~mask;
-+ }
-+
-+ dev->ctrls[c] = v4l2_ctrl_new_std_menu(hdl,
-+ &bm2835_mmal_ctrl_ops, ctrl->id,
-+ ctrl->max, mask, ctrl->def);
-+ break;
-+ }
-+
-+ case MMAL_CONTROL_TYPE_INT_MENU:
-+ dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl,
-+ &bm2835_mmal_ctrl_ops, ctrl->id,
-+ ctrl->max, ctrl->def, ctrl->imenu);
-+ break;
-+
-+ case MMAL_CONTROL_TYPE_CLUSTER:
-+ /* skip this entry when constructing controls */
-+ continue;
-+ }
-+
-+ if (hdl->error)
-+ break;
-+
-+ dev->ctrls[c]->priv = (void *)ctrl;
-+ }
-+
-+ if (hdl->error) {
-+ pr_err("error adding control %d/%d id 0x%x\n", c,
-+ V4L2_CTRL_COUNT, ctrl->id);
-+ return hdl->error;
-+ }
-+
-+ for (c = 0; c < V4L2_CTRL_COUNT; c++) {
-+ ctrl = &v4l2_ctrls[c];
-+
-+ switch (ctrl->type) {
-+ case MMAL_CONTROL_TYPE_CLUSTER:
-+ v4l2_ctrl_auto_cluster(ctrl->min,
-+ &dev->ctrls[c+1],
-+ ctrl->max,
-+ ctrl->def);
-+ break;
-+
-+ case MMAL_CONTROL_TYPE_STD:
-+ case MMAL_CONTROL_TYPE_STD_MENU:
-+ case MMAL_CONTROL_TYPE_INT_MENU:
-+ break;
-+ }
-+
-+ }
-+
-+ return 0;
-+}
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/Kconfig linux-rpi/drivers/media/platform/bcm2835/Kconfig
---- linux-3.18.14/drivers/media/platform/bcm2835/Kconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/Kconfig 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,25 @@
-+# Broadcom VideoCore IV v4l2 camera support
-+
-+config VIDEO_BCM2835
-+ bool "Broadcom BCM2835 camera interface driver"
-+ depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709)
-+ ---help---
-+ Say Y here to enable camera host interface devices for
-+ Broadcom BCM2835 SoC. This operates over the VCHIQ interface
-+ to a service running on VideoCore.
-+
-+
-+if VIDEO_BCM2835
-+
-+config VIDEO_BCM2835_MMAL
-+ tristate "Broadcom BM2835 MMAL camera interface driver"
-+ depends on BCM2708_VCHIQ
-+ select VIDEOBUF2_VMALLOC
-+ ---help---
-+ This is a V4L2 driver for the Broadcom BCM2835 MMAL camera host interface
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called bcm2835-v4l2.o
-+
-+
-+endif # VIDEO_BM2835
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/Makefile linux-rpi/drivers/media/platform/bcm2835/Makefile
---- linux-3.18.14/drivers/media/platform/bcm2835/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/Makefile 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,5 @@
-+bcm2835-v4l2-objs := bcm2835-camera.o controls.o mmal-vchiq.o
-+
-+obj-$(CONFIG_VIDEO_BCM2835_MMAL) += bcm2835-v4l2.o
-+
-+ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-common.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-common.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-common.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,53 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * MMAL structures
-+ *
-+ */
-+
-+#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24))
-+#define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l')
-+
-+/** Special value signalling that time is not known */
-+#define MMAL_TIME_UNKNOWN (1LL<<63)
-+
-+/* mapping between v4l and mmal video modes */
-+struct mmal_fmt {
-+ char *name;
-+ u32 fourcc; /* v4l2 format id */
-+ int flags; /* v4l2 flags field */
-+ u32 mmal;
-+ int depth;
-+ u32 mmal_component; /* MMAL component index to be used to encode */
-+};
-+
-+/* buffer for one video frame */
-+struct mmal_buffer {
-+ /* v4l buffer data -- must be first */
-+ struct vb2_buffer vb;
-+
-+ /* list of buffers available */
-+ struct list_head list;
-+
-+ void *buffer; /* buffer pointer */
-+ unsigned long buffer_size; /* size of allocated buffer */
-+};
-+
-+/* */
-+struct mmal_colourfx {
-+ s32 enable;
-+ u32 u;
-+ u32 v;
-+};
-+
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-encodings.h linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-encodings.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,127 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+#ifndef MMAL_ENCODINGS_H
-+#define MMAL_ENCODINGS_H
-+
-+#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4')
-+#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3')
-+#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V')
-+#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V')
-+#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V')
-+#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3')
-+#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2')
-+#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1')
-+#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1')
-+#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ')
-+#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ')
-+#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ')
-+#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O')
-+#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K')
-+#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G')
-+
-+#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G')
-+#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ')
-+#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ')
-+#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ')
-+#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ')
-+#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ')
-+
-+#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0')
-+#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0')
-+#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2')
-+#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2')
-+#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2')
-+#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V')
-+#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U')
-+#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y')
-+#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y')
-+#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2')
-+#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1')
-+#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B')
-+#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A')
-+#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R')
-+#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A')
-+#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2')
-+#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3')
-+#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4')
-+#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2')
-+#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3')
-+#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4')
-+
-+/** SAND Video (YUVUV128) format, native format understood by VideoCore.
-+ * This format is *not* opaque - if requested you will receive full frames
-+ * of YUV_UV video.
-+ */
-+#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D')
-+
-+/** VideoCore opaque image format, image handles are returned to
-+ * the host but not the actual image data.
-+ */
-+#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V')
-+
-+/** An EGL image handle
-+ */
-+#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I')
-+
-+/* }@ */
-+
-+/** \name Pre-defined audio encodings */
-+/* @{ */
-+#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U')
-+#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u')
-+#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S')
-+#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's')
-+#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F')
-+#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f')
-+
-+/* Pre-defined H264 encoding variants */
-+
-+/** ISO 14496-10 Annex B byte stream format */
-+#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0
-+/** ISO 14496-15 AVC stream format */
-+#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1')
-+/** Implicitly delineated NAL units without emulation prevention */
-+#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ')
-+
-+
-+/** \defgroup MmalColorSpace List of pre-defined video color spaces
-+ * This defines a list of common color spaces. This list isn't exhaustive and
-+ * is only provided as a convenience to avoid clients having to use FourCC
-+ * codes directly. However components are allowed to define and use their own
-+ * FourCC codes.
-+ */
-+/* @{ */
-+
-+/** Unknown color space */
-+#define MMAL_COLOR_SPACE_UNKNOWN 0
-+/** ITU-R BT.601-5 [SDTV] */
-+#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1')
-+/** ITU-R BT.709-3 [HDTV] */
-+#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9')
-+/** JPEG JFIF */
-+#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I')
-+/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */
-+#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C')
-+/** Society of Motion Picture and Television Engineers 240M (1999) */
-+#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0')
-+/** ITU-R BT.470-2 System M */
-+#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M')
-+/** ITU-R BT.470-2 System BG */
-+#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G')
-+/** JPEG JFIF, but with 16..255 luma */
-+#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6')
-+/* @} MmalColorSpace List */
-+
-+#endif /* MMAL_ENCODINGS_H */
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg-common.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,50 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#ifndef MMAL_MSG_COMMON_H
-+#define MMAL_MSG_COMMON_H
-+
-+enum mmal_msg_status {
-+ MMAL_MSG_STATUS_SUCCESS = 0, /**< Success */
-+ MMAL_MSG_STATUS_ENOMEM, /**< Out of memory */
-+ MMAL_MSG_STATUS_ENOSPC, /**< Out of resources other than memory */
-+ MMAL_MSG_STATUS_EINVAL, /**< Argument is invalid */
-+ MMAL_MSG_STATUS_ENOSYS, /**< Function not implemented */
-+ MMAL_MSG_STATUS_ENOENT, /**< No such file or directory */
-+ MMAL_MSG_STATUS_ENXIO, /**< No such device or address */
-+ MMAL_MSG_STATUS_EIO, /**< I/O error */
-+ MMAL_MSG_STATUS_ESPIPE, /**< Illegal seek */
-+ MMAL_MSG_STATUS_ECORRUPT, /**< Data is corrupt \attention */
-+ MMAL_MSG_STATUS_ENOTREADY, /**< Component is not ready */
-+ MMAL_MSG_STATUS_ECONFIG, /**< Component is not configured */
-+ MMAL_MSG_STATUS_EISCONN, /**< Port is already connected */
-+ MMAL_MSG_STATUS_ENOTCONN, /**< Port is disconnected */
-+ MMAL_MSG_STATUS_EAGAIN, /**< Resource temporarily unavailable. */
-+ MMAL_MSG_STATUS_EFAULT, /**< Bad address */
-+};
-+
-+struct mmal_rect {
-+ s32 x; /**< x coordinate (from left) */
-+ s32 y; /**< y coordinate (from top) */
-+ s32 width; /**< width */
-+ s32 height; /**< height */
-+};
-+
-+struct mmal_rational {
-+ s32 num; /**< Numerator */
-+ s32 den; /**< Denominator */
-+};
-+
-+#endif /* MMAL_MSG_COMMON_H */
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg-format.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg-format.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,81 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+#ifndef MMAL_MSG_FORMAT_H
-+#define MMAL_MSG_FORMAT_H
-+
-+#include "mmal-msg-common.h"
-+
-+/* MMAL_ES_FORMAT_T */
-+
-+
-+struct mmal_audio_format {
-+ u32 channels; /**< Number of audio channels */
-+ u32 sample_rate; /**< Sample rate */
-+
-+ u32 bits_per_sample; /**< Bits per sample */
-+ u32 block_align; /**< Size of a block of data */
-+};
-+
-+struct mmal_video_format {
-+ u32 width; /**< Width of frame in pixels */
-+ u32 height; /**< Height of frame in rows of pixels */
-+ struct mmal_rect crop; /**< Visible region of the frame */
-+ struct mmal_rational frame_rate; /**< Frame rate */
-+ struct mmal_rational par; /**< Pixel aspect ratio */
-+
-+ /* FourCC specifying the color space of the video stream. See the
-+ * \ref MmalColorSpace "pre-defined color spaces" for some examples.
-+ */
-+ u32 color_space;
-+};
-+
-+struct mmal_subpicture_format {
-+ u32 x_offset;
-+ u32 y_offset;
-+};
-+
-+union mmal_es_specific_format {
-+ struct mmal_audio_format audio;
-+ struct mmal_video_format video;
-+ struct mmal_subpicture_format subpicture;
-+};
-+
-+/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
-+struct mmal_es_format {
-+ u32 type; /* enum mmal_es_type */
-+
-+ u32 encoding; /* FourCC specifying encoding of the elementary stream.*/
-+ u32 encoding_variant; /* FourCC specifying the specific
-+ * encoding variant of the elementary
-+ * stream.
-+ */
-+
-+ union mmal_es_specific_format *es; /* TODO: pointers in
-+ * message serialisation?!?
-+ */
-+ /* Type specific
-+ * information for the
-+ * elementary stream
-+ */
-+
-+ u32 bitrate; /**< Bitrate in bits per second */
-+ u32 flags; /**< Flags describing properties of the elementary stream. */
-+
-+ u32 extradata_size; /**< Size of the codec specific data */
-+ u8 *extradata; /**< Codec specific data */
-+};
-+
-+#endif /* MMAL_MSG_FORMAT_H */
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,404 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+/* all the data structures which serialise the MMAL protocol. note
-+ * these are directly mapped onto the recived message data.
-+ *
-+ * BEWARE: They seem to *assume* pointers are u32 and that there is no
-+ * structure padding!
-+ *
-+ * NOTE: this implementation uses kernel types to ensure sizes. Rather
-+ * than assigning values to enums to force their size the
-+ * implementation uses fixed size types and not the enums (though the
-+ * comments have the actual enum type
-+ */
-+
-+#define VC_MMAL_VER 15
-+#define VC_MMAL_MIN_VER 10
-+#define VC_MMAL_SERVER_NAME MAKE_FOURCC("mmal")
-+
-+/* max total message size is 512 bytes */
-+#define MMAL_MSG_MAX_SIZE 512
-+/* with six 32bit header elements max payload is therefore 488 bytes */
-+#define MMAL_MSG_MAX_PAYLOAD 488
-+
-+#include "mmal-msg-common.h"
-+#include "mmal-msg-format.h"
-+#include "mmal-msg-port.h"
-+
-+enum mmal_msg_type {
-+ MMAL_MSG_TYPE_QUIT = 1,
-+ MMAL_MSG_TYPE_SERVICE_CLOSED,
-+ MMAL_MSG_TYPE_GET_VERSION,
-+ MMAL_MSG_TYPE_COMPONENT_CREATE,
-+ MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */
-+ MMAL_MSG_TYPE_COMPONENT_ENABLE,
-+ MMAL_MSG_TYPE_COMPONENT_DISABLE,
-+ MMAL_MSG_TYPE_PORT_INFO_GET,
-+ MMAL_MSG_TYPE_PORT_INFO_SET,
-+ MMAL_MSG_TYPE_PORT_ACTION, /* 10 */
-+ MMAL_MSG_TYPE_BUFFER_FROM_HOST,
-+ MMAL_MSG_TYPE_BUFFER_TO_HOST,
-+ MMAL_MSG_TYPE_GET_STATS,
-+ MMAL_MSG_TYPE_PORT_PARAMETER_SET,
-+ MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */
-+ MMAL_MSG_TYPE_EVENT_TO_HOST,
-+ MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT,
-+ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR,
-+ MMAL_MSG_TYPE_CONSUME_MEM,
-+ MMAL_MSG_TYPE_LMK, /* 20 */
-+ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC,
-+ MMAL_MSG_TYPE_DRM_GET_LHS32,
-+ MMAL_MSG_TYPE_DRM_GET_TIME,
-+ MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN,
-+ MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */
-+ MMAL_MSG_TYPE_HOST_LOG,
-+ MMAL_MSG_TYPE_MSG_LAST
-+};
-+
-+/* port action request messages differ depending on the action type */
-+enum mmal_msg_port_action_type {
-+ MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0, /* Unkown action */
-+ MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */
-+ MMAL_MSG_PORT_ACTION_TYPE_DISABLE, /* Disable a port */
-+ MMAL_MSG_PORT_ACTION_TYPE_FLUSH, /* Flush a port */
-+ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, /* Connect ports */
-+ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, /* Disconnect ports */
-+ MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/
-+};
-+
-+struct mmal_msg_header {
-+ u32 magic;
-+ u32 type; /** enum mmal_msg_type */
-+
-+ /* Opaque handle to the control service */
-+ struct mmal_control_service *control_service;
-+
-+ struct mmal_msg_context *context; /** a u32 per message context */
-+ u32 status; /** The status of the vchiq operation */
-+ u32 padding;
-+};
-+
-+/* Send from VC to host to report version */
-+struct mmal_msg_version {
-+ u32 flags;
-+ u32 major;
-+ u32 minor;
-+ u32 minimum;
-+};
-+
-+/* request to VC to create component */
-+struct mmal_msg_component_create {
-+ void *client_component; /* component context */
-+ char name[128];
-+ u32 pid; /* For debug */
-+};
-+
-+/* reply from VC to component creation request */
-+struct mmal_msg_component_create_reply {
-+ u32 status; /** enum mmal_msg_status - how does this differ to
-+ * the one in the header?
-+ */
-+ u32 component_handle; /* VideoCore handle for component */
-+ u32 input_num; /* Number of input ports */
-+ u32 output_num; /* Number of output ports */
-+ u32 clock_num; /* Number of clock ports */
-+};
-+
-+/* request to VC to destroy a component */
-+struct mmal_msg_component_destroy {
-+ u32 component_handle;
-+};
-+
-+struct mmal_msg_component_destroy_reply {
-+ u32 status; /** The component destruction status */
-+};
-+
-+
-+/* request and reply to VC to enable a component */
-+struct mmal_msg_component_enable {
-+ u32 component_handle;
-+};
-+
-+struct mmal_msg_component_enable_reply {
-+ u32 status; /** The component enable status */
-+};
-+
-+
-+/* request and reply to VC to disable a component */
-+struct mmal_msg_component_disable {
-+ u32 component_handle;
-+};
-+
-+struct mmal_msg_component_disable_reply {
-+ u32 status; /** The component disable status */
-+};
-+
-+/* request to VC to get port information */
-+struct mmal_msg_port_info_get {
-+ u32 component_handle; /* component handle port is associated with */
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 index; /* port index to query */
-+};
-+
-+/* reply from VC to get port info request */
-+struct mmal_msg_port_info_get_reply {
-+ u32 status; /** enum mmal_msg_status */
-+ u32 component_handle; /* component handle port is associated with */
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 port_index; /* port indexed in query */
-+ s32 found; /* unused */
-+ u32 port_handle; /**< Handle to use for this port */
-+ struct mmal_port port;
-+ struct mmal_es_format format; /* elementry stream format */
-+ union mmal_es_specific_format es; /* es type specific data */
-+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; /* es extra data */
-+};
-+
-+/* request to VC to set port information */
-+struct mmal_msg_port_info_set {
-+ u32 component_handle;
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 port_index; /* port indexed in query */
-+ struct mmal_port port;
-+ struct mmal_es_format format;
-+ union mmal_es_specific_format es;
-+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];
-+};
-+
-+/* reply from VC to port info set request */
-+struct mmal_msg_port_info_set_reply {
-+ u32 status;
-+ u32 component_handle; /* component handle port is associated with */
-+ u32 port_type; /* enum mmal_msg_port_type */
-+ u32 index; /* port indexed in query */
-+ s32 found; /* unused */
-+ u32 port_handle; /**< Handle to use for this port */
-+ struct mmal_port port;
-+ struct mmal_es_format format;
-+ union mmal_es_specific_format es;
-+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];
-+};
-+
-+
-+/* port action requests that take a mmal_port as a parameter */
-+struct mmal_msg_port_action_port {
-+ u32 component_handle;
-+ u32 port_handle;
-+ u32 action; /* enum mmal_msg_port_action_type */
-+ struct mmal_port port;
-+};
-+
-+/* port action requests that take handles as a parameter */
-+struct mmal_msg_port_action_handle {
-+ u32 component_handle;
-+ u32 port_handle;
-+ u32 action; /* enum mmal_msg_port_action_type */
-+ u32 connect_component_handle;
-+ u32 connect_port_handle;
-+};
-+
-+struct mmal_msg_port_action_reply {
-+ u32 status; /** The port action operation status */
-+};
-+
-+
-+
-+
-+/* MMAL buffer transfer */
-+
-+/** Size of space reserved in a buffer message for short messages. */
-+#define MMAL_VC_SHORT_DATA 128
-+
-+/** Signals that the current payload is the end of the stream of data */
-+#define MMAL_BUFFER_HEADER_FLAG_EOS (1<<0)
-+/** Signals that the start of the current payload starts a frame */
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME_START (1<<1)
-+/** Signals that the end of the current payload ends a frame */
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME_END (1<<2)
-+/** Signals that the current payload contains only complete frames (>1) */
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME \
-+ (MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END)
-+/** Signals that the current payload is a keyframe (i.e. self decodable) */
-+#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME (1<<3)
-+/** Signals a discontinuity in the stream of data (e.g. after a seek).
-+ * Can be used for instance by a decoder to reset its state */
-+#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY (1<<4)
-+/** Signals a buffer containing some kind of config data for the component
-+ * (e.g. codec config data) */
-+#define MMAL_BUFFER_HEADER_FLAG_CONFIG (1<<5)
-+/** Signals an encrypted payload */
-+#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED (1<<6)
-+/** Signals a buffer containing side information */
-+#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO (1<<7)
-+/** Signals a buffer which is the snapshot/postview image from a stills
-+ * capture
-+ */
-+#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT (1<<8)
-+/** Signals a buffer which contains data known to be corrupted */
-+#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED (1<<9)
-+/** Signals that a buffer failed to be transmitted */
-+#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED (1<<10)
-+
-+struct mmal_driver_buffer {
-+ u32 magic;
-+ u32 component_handle;
-+ u32 port_handle;
-+ void *client_context;
-+};
-+
-+/* buffer header */
-+struct mmal_buffer_header {
-+ struct mmal_buffer_header *next; /* next header */
-+ void *priv; /* framework private data */
-+ u32 cmd;
-+ void *data;
-+ u32 alloc_size;
-+ u32 length;
-+ u32 offset;
-+ u32 flags;
-+ s64 pts;
-+ s64 dts;
-+ void *type;
-+ void *user_data;
-+};
-+
-+struct mmal_buffer_header_type_specific {
-+ union {
-+ struct {
-+ u32 planes;
-+ u32 offset[4];
-+ u32 pitch[4];
-+ u32 flags;
-+ } video;
-+ } u;
-+};
-+
-+struct mmal_msg_buffer_from_host {
-+ /* The front 32 bytes of the buffer header are copied
-+ * back to us in the reply to allow for context. This
-+ * area is used to store two mmal_driver_buffer structures to
-+ * allow for multiple concurrent service users.
-+ */
-+ /* control data */
-+ struct mmal_driver_buffer drvbuf;
-+
-+ /* referenced control data for passthrough buffer management */
-+ struct mmal_driver_buffer drvbuf_ref;
-+ struct mmal_buffer_header buffer_header; /* buffer header itself */
-+ struct mmal_buffer_header_type_specific buffer_header_type_specific;
-+ s32 is_zero_copy;
-+ s32 has_reference;
-+
-+ /** allows short data to be xfered in control message */
-+ u32 payload_in_message;
-+ u8 short_data[MMAL_VC_SHORT_DATA];
-+};
-+
-+
-+/* port parameter setting */
-+
-+#define MMAL_WORKER_PORT_PARAMETER_SPACE 96
-+
-+struct mmal_msg_port_parameter_set {
-+ u32 component_handle; /* component */
-+ u32 port_handle; /* port */
-+ u32 id; /* Parameter ID */
-+ u32 size; /* Parameter size */
-+ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
-+};
-+
-+struct mmal_msg_port_parameter_set_reply {
-+ u32 status; /** enum mmal_msg_status todo: how does this
-+ * differ to the one in the header?
-+ */
-+};
-+
-+/* port parameter getting */
-+
-+struct mmal_msg_port_parameter_get {
-+ u32 component_handle; /* component */
-+ u32 port_handle; /* port */
-+ u32 id; /* Parameter ID */
-+ u32 size; /* Parameter size */
-+};
-+
-+struct mmal_msg_port_parameter_get_reply {
-+ u32 status; /* Status of mmal_port_parameter_get call */
-+ u32 id; /* Parameter ID */
-+ u32 size; /* Parameter size */
-+ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
-+};
-+
-+/* event messages */
-+#define MMAL_WORKER_EVENT_SPACE 256
-+
-+struct mmal_msg_event_to_host {
-+ void *client_component; /* component context */
-+
-+ u32 port_type;
-+ u32 port_num;
-+
-+ u32 cmd;
-+ u32 length;
-+ u8 data[MMAL_WORKER_EVENT_SPACE];
-+ struct mmal_buffer_header *delayed_buffer;
-+};
-+
-+/* all mmal messages are serialised through this structure */
-+struct mmal_msg {
-+ /* header */
-+ struct mmal_msg_header h;
-+ /* payload */
-+ union {
-+ struct mmal_msg_version version;
-+
-+ struct mmal_msg_component_create component_create;
-+ struct mmal_msg_component_create_reply component_create_reply;
-+
-+ struct mmal_msg_component_destroy component_destroy;
-+ struct mmal_msg_component_destroy_reply component_destroy_reply;
-+
-+ struct mmal_msg_component_enable component_enable;
-+ struct mmal_msg_component_enable_reply component_enable_reply;
-+
-+ struct mmal_msg_component_disable component_disable;
-+ struct mmal_msg_component_disable_reply component_disable_reply;
-+
-+ struct mmal_msg_port_info_get port_info_get;
-+ struct mmal_msg_port_info_get_reply port_info_get_reply;
-+
-+ struct mmal_msg_port_info_set port_info_set;
-+ struct mmal_msg_port_info_set_reply port_info_set_reply;
-+
-+ struct mmal_msg_port_action_port port_action_port;
-+ struct mmal_msg_port_action_handle port_action_handle;
-+ struct mmal_msg_port_action_reply port_action_reply;
-+
-+ struct mmal_msg_buffer_from_host buffer_from_host;
-+
-+ struct mmal_msg_port_parameter_set port_parameter_set;
-+ struct mmal_msg_port_parameter_set_reply
-+ port_parameter_set_reply;
-+ struct mmal_msg_port_parameter_get
-+ port_parameter_get;
-+ struct mmal_msg_port_parameter_get_reply
-+ port_parameter_get_reply;
-+
-+ struct mmal_msg_event_to_host event_to_host;
-+
-+ u8 payload[MMAL_MSG_MAX_PAYLOAD];
-+ } u;
-+};
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg-port.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-msg-port.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,107 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+/* MMAL_PORT_TYPE_T */
-+enum mmal_port_type {
-+ MMAL_PORT_TYPE_UNKNOWN = 0, /**< Unknown port type */
-+ MMAL_PORT_TYPE_CONTROL, /**< Control port */
-+ MMAL_PORT_TYPE_INPUT, /**< Input port */
-+ MMAL_PORT_TYPE_OUTPUT, /**< Output port */
-+ MMAL_PORT_TYPE_CLOCK, /**< Clock port */
-+};
-+
-+/** The port is pass-through and doesn't need buffer headers allocated */
-+#define MMAL_PORT_CAPABILITY_PASSTHROUGH 0x01
-+/** The port wants to allocate the buffer payloads.
-+ * This signals a preference that payload allocation should be done
-+ * on this port for efficiency reasons. */
-+#define MMAL_PORT_CAPABILITY_ALLOCATION 0x02
-+/** The port supports format change events.
-+ * This applies to input ports and is used to let the client know
-+ * whether the port supports being reconfigured via a format
-+ * change event (i.e. without having to disable the port). */
-+#define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE 0x04
-+
-+/* mmal port structure (MMAL_PORT_T)
-+ *
-+ * most elements are informational only, the pointer values for
-+ * interogation messages are generally provided as additional
-+ * strucures within the message. When used to set values only teh
-+ * buffer_num, buffer_size and userdata parameters are writable.
-+ */
-+struct mmal_port {
-+ void *priv; /* Private member used by the framework */
-+ const char *name; /* Port name. Used for debugging purposes (RO) */
-+
-+ u32 type; /* Type of the port (RO) enum mmal_port_type */
-+ u16 index; /* Index of the port in its type list (RO) */
-+ u16 index_all; /* Index of the port in the list of all ports (RO) */
-+
-+ u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */
-+ struct mmal_es_format *format; /* Format of the elementary stream */
-+
-+ u32 buffer_num_min; /* Minimum number of buffers the port
-+ * requires (RO). This is set by the
-+ * component.
-+ */
-+
-+ u32 buffer_size_min; /* Minimum size of buffers the port
-+ * requires (RO). This is set by the
-+ * component.
-+ */
-+
-+ u32 buffer_alignment_min; /* Minimum alignment requirement for
-+ * the buffers (RO). A value of
-+ * zero means no special alignment
-+ * requirements. This is set by the
-+ * component.
-+ */
-+
-+ u32 buffer_num_recommended; /* Number of buffers the port
-+ * recommends for optimal
-+ * performance (RO). A value of
-+ * zero means no special
-+ * recommendation. This is set
-+ * by the component.
-+ */
-+
-+ u32 buffer_size_recommended; /* Size of buffers the port
-+ * recommends for optimal
-+ * performance (RO). A value of
-+ * zero means no special
-+ * recommendation. This is set
-+ * by the component.
-+ */
-+
-+ u32 buffer_num; /* Actual number of buffers the port will use.
-+ * This is set by the client.
-+ */
-+
-+ u32 buffer_size; /* Actual maximum size of the buffers that
-+ * will be sent to the port. This is set by
-+ * the client.
-+ */
-+
-+ void *component; /* Component this port belongs to (Read Only) */
-+
-+ void *userdata; /* Field reserved for use by the client */
-+
-+ u32 capabilities; /* Flags describing the capabilities of a
-+ * port (RO). Bitwise combination of \ref
-+ * portcapabilities "Port capabilities"
-+ * values.
-+ */
-+
-+};
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-parameters.h linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-parameters.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,656 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ */
-+
-+/* common parameters */
-+
-+/** @name Parameter groups
-+ * Parameters are divided into groups, and then allocated sequentially within
-+ * a group using an enum.
-+ * @{
-+ */
-+
-+/** Common parameter ID group, used with many types of component. */
-+#define MMAL_PARAMETER_GROUP_COMMON (0<<16)
-+/** Camera-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_CAMERA (1<<16)
-+/** Video-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_VIDEO (2<<16)
-+/** Audio-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_AUDIO (3<<16)
-+/** Clock-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_CLOCK (4<<16)
-+/** Miracast-specific parameter ID group. */
-+#define MMAL_PARAMETER_GROUP_MIRACAST (5<<16)
-+
-+/* Common parameters */
-+enum mmal_parameter_common_type {
-+ MMAL_PARAMETER_UNUSED /**< Never a valid parameter ID */
-+ = MMAL_PARAMETER_GROUP_COMMON,
-+ MMAL_PARAMETER_SUPPORTED_ENCODINGS, /**< MMAL_PARAMETER_ENCODING_T */
-+ MMAL_PARAMETER_URI, /**< MMAL_PARAMETER_URI_T */
-+
-+ /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */
-+ MMAL_PARAMETER_CHANGE_EVENT_REQUEST,
-+
-+ /** MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_ZERO_COPY,
-+
-+ /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */
-+ MMAL_PARAMETER_BUFFER_REQUIREMENTS,
-+
-+ MMAL_PARAMETER_STATISTICS, /**< MMAL_PARAMETER_STATISTICS_T */
-+ MMAL_PARAMETER_CORE_STATISTICS, /**< MMAL_PARAMETER_CORE_STATISTICS_T */
-+ MMAL_PARAMETER_MEM_USAGE, /**< MMAL_PARAMETER_MEM_USAGE_T */
-+ MMAL_PARAMETER_BUFFER_FLAG_FILTER, /**< MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_SEEK, /**< MMAL_PARAMETER_SEEK_T */
-+ MMAL_PARAMETER_POWERMON_ENABLE, /**< MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_LOGGING, /**< MMAL_PARAMETER_LOGGING_T */
-+ MMAL_PARAMETER_SYSTEM_TIME, /**< MMAL_PARAMETER_UINT64_T */
-+ MMAL_PARAMETER_NO_IMAGE_PADDING /**< MMAL_PARAMETER_BOOLEAN_T */
-+};
-+
-+/* camera parameters */
-+
-+enum mmal_parameter_camera_type {
-+ /* 0 */
-+ /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */
-+ MMAL_PARAMETER_THUMBNAIL_CONFIGURATION
-+ = MMAL_PARAMETER_GROUP_CAMERA,
-+ MMAL_PARAMETER_CAPTURE_QUALITY, /**< Unused? */
-+ MMAL_PARAMETER_ROTATION, /**< @ref MMAL_PARAMETER_INT32_T */
-+ MMAL_PARAMETER_EXIF_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_EXIF, /**< @ref MMAL_PARAMETER_EXIF_T */
-+ MMAL_PARAMETER_AWB_MODE, /**< @ref MMAL_PARAM_AWBMODE_T */
-+ MMAL_PARAMETER_IMAGE_EFFECT, /**< @ref MMAL_PARAMETER_IMAGEFX_T */
-+ MMAL_PARAMETER_COLOUR_EFFECT, /**< @ref MMAL_PARAMETER_COLOURFX_T */
-+ MMAL_PARAMETER_FLICKER_AVOID, /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */
-+ MMAL_PARAMETER_FLASH, /**< @ref MMAL_PARAMETER_FLASH_T */
-+ MMAL_PARAMETER_REDEYE, /**< @ref MMAL_PARAMETER_REDEYE_T */
-+ MMAL_PARAMETER_FOCUS, /**< @ref MMAL_PARAMETER_FOCUS_T */
-+ MMAL_PARAMETER_FOCAL_LENGTHS, /**< Unused? */
-+ MMAL_PARAMETER_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */
-+ MMAL_PARAMETER_ZOOM, /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */
-+ MMAL_PARAMETER_MIRROR, /**< @ref MMAL_PARAMETER_MIRROR_T */
-+
-+ /* 0x10 */
-+ MMAL_PARAMETER_CAMERA_NUM, /**< @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_EXPOSURE_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */
-+ MMAL_PARAMETER_EXP_METERING_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */
-+ MMAL_PARAMETER_FOCUS_STATUS, /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */
-+ MMAL_PARAMETER_CAMERA_CONFIG, /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */
-+ MMAL_PARAMETER_CAPTURE_STATUS, /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */
-+ MMAL_PARAMETER_FACE_TRACK, /**< @ref MMAL_PARAMETER_FACE_TRACK_T */
-+ MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_JPEG_Q_FACTOR, /**< @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_FRAME_RATE, /**< @ref MMAL_PARAMETER_FRAME_RATE_T */
-+ MMAL_PARAMETER_USE_STC, /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */
-+ MMAL_PARAMETER_CAMERA_INFO, /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */
-+ MMAL_PARAMETER_VIDEO_STABILISATION, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_FACE_TRACK_RESULTS, /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */
-+ MMAL_PARAMETER_ENABLE_RAW_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+
-+ /* 0x20 */
-+ MMAL_PARAMETER_DPF_FILE, /**< @ref MMAL_PARAMETER_URI_T */
-+ MMAL_PARAMETER_ENABLE_DPF_FILE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_DPF_FAIL_IS_FATAL, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_CAPTURE_MODE, /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */
-+ MMAL_PARAMETER_FOCUS_REGIONS, /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */
-+ MMAL_PARAMETER_INPUT_CROP, /**< @ref MMAL_PARAMETER_INPUT_CROP_T */
-+ MMAL_PARAMETER_SENSOR_INFORMATION, /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */
-+ MMAL_PARAMETER_FLASH_SELECT, /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */
-+ MMAL_PARAMETER_FIELD_OF_VIEW, /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */
-+ MMAL_PARAMETER_HIGH_DYNAMIC_RANGE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION, /**< @ref MMAL_PARAMETER_DRC_T */
-+ MMAL_PARAMETER_ALGORITHM_CONTROL, /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */
-+ MMAL_PARAMETER_SHARPNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+ MMAL_PARAMETER_CONTRAST, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+ MMAL_PARAMETER_BRIGHTNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+ MMAL_PARAMETER_SATURATION, /**< @ref MMAL_PARAMETER_RATIONAL_T */
-+
-+ /* 0x30 */
-+ MMAL_PARAMETER_ISO, /**< @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_ANTISHAKE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+
-+ /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */
-+ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_CAMERA_BURST_CAPTURE,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CAMERA_MIN_ISO,
-+
-+ /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */
-+ MMAL_PARAMETER_CAMERA_USE_CASE,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_CAPTURE_STATS_PASS,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_ENABLE_REGISTER_FILE,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL,
-+
-+ /** @ref MMAL_PARAMETER_CONFIGFILE_T */
-+ MMAL_PARAMETER_CONFIGFILE_REGISTERS,
-+
-+ /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */
-+ MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS,
-+ MMAL_PARAMETER_JPEG_ATTACH_LOG, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_ZERO_SHUTTER_LAG, /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */
-+ MMAL_PARAMETER_FPS_RANGE, /**< @ref MMAL_PARAMETER_FPS_RANGE_T */
-+ MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */
-+
-+ /* 0x40 */
-+ MMAL_PARAMETER_SW_SHARPEN_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_FLASH_REQUIRED, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_SW_SATURATION_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_SHUTTER_SPEED, /**< Takes a @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_CUSTOM_AWB_GAINS, /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */
-+};
-+
-+struct mmal_parameter_rational {
-+ s32 num; /**< Numerator */
-+ s32 den; /**< Denominator */
-+};
-+
-+enum mmal_parameter_camera_config_timestamp_mode {
-+ MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */
-+ MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value
-+ * for the frame timestamp
-+ */
-+ MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp
-+ * but subtract the
-+ * timestamp of the first
-+ * frame sent to give a
-+ * zero based timestamp.
-+ */
-+};
-+
-+struct mmal_parameter_fps_range {
-+ /**< Low end of the permitted framerate range */
-+ struct mmal_parameter_rational fps_low;
-+ /**< High end of the permitted framerate range */
-+ struct mmal_parameter_rational fps_high;
-+};
-+
-+
-+/* camera configuration parameter */
-+struct mmal_parameter_camera_config {
-+ /* Parameters for setting up the image pools */
-+ u32 max_stills_w; /* Max size of stills capture */
-+ u32 max_stills_h;
-+ u32 stills_yuv422; /* Allow YUV422 stills capture */
-+ u32 one_shot_stills; /* Continuous or one shot stills captures. */
-+
-+ u32 max_preview_video_w; /* Max size of the preview or video
-+ * capture frames
-+ */
-+ u32 max_preview_video_h;
-+ u32 num_preview_video_frames;
-+
-+ /** Sets the height of the circular buffer for stills capture. */
-+ u32 stills_capture_circular_buffer_height;
-+
-+ /** Allows preview/encode to resume as fast as possible after the stills
-+ * input frame has been received, and then processes the still frame in
-+ * the background whilst preview/encode has resumed.
-+ * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE.
-+ */
-+ u32 fast_preview_resume;
-+
-+ /** Selects algorithm for timestamping frames if
-+ * there is no clock component connected.
-+ * enum mmal_parameter_camera_config_timestamp_mode
-+ */
-+ s32 use_stc_timestamp;
-+};
-+
-+
-+enum mmal_parameter_exposuremode {
-+ MMAL_PARAM_EXPOSUREMODE_OFF,
-+ MMAL_PARAM_EXPOSUREMODE_AUTO,
-+ MMAL_PARAM_EXPOSUREMODE_NIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW,
-+ MMAL_PARAM_EXPOSUREMODE_BACKLIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT,
-+ MMAL_PARAM_EXPOSUREMODE_SPORTS,
-+ MMAL_PARAM_EXPOSUREMODE_SNOW,
-+ MMAL_PARAM_EXPOSUREMODE_BEACH,
-+ MMAL_PARAM_EXPOSUREMODE_VERYLONG,
-+ MMAL_PARAM_EXPOSUREMODE_FIXEDFPS,
-+ MMAL_PARAM_EXPOSUREMODE_ANTISHAKE,
-+ MMAL_PARAM_EXPOSUREMODE_FIREWORKS,
-+};
-+
-+enum mmal_parameter_exposuremeteringmode {
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT,
-+ MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX,
-+};
-+
-+enum mmal_parameter_awbmode {
-+ MMAL_PARAM_AWBMODE_OFF,
-+ MMAL_PARAM_AWBMODE_AUTO,
-+ MMAL_PARAM_AWBMODE_SUNLIGHT,
-+ MMAL_PARAM_AWBMODE_CLOUDY,
-+ MMAL_PARAM_AWBMODE_SHADE,
-+ MMAL_PARAM_AWBMODE_TUNGSTEN,
-+ MMAL_PARAM_AWBMODE_FLUORESCENT,
-+ MMAL_PARAM_AWBMODE_INCANDESCENT,
-+ MMAL_PARAM_AWBMODE_FLASH,
-+ MMAL_PARAM_AWBMODE_HORIZON,
-+};
-+
-+enum mmal_parameter_imagefx {
-+ MMAL_PARAM_IMAGEFX_NONE,
-+ MMAL_PARAM_IMAGEFX_NEGATIVE,
-+ MMAL_PARAM_IMAGEFX_SOLARIZE,
-+ MMAL_PARAM_IMAGEFX_POSTERIZE,
-+ MMAL_PARAM_IMAGEFX_WHITEBOARD,
-+ MMAL_PARAM_IMAGEFX_BLACKBOARD,
-+ MMAL_PARAM_IMAGEFX_SKETCH,
-+ MMAL_PARAM_IMAGEFX_DENOISE,
-+ MMAL_PARAM_IMAGEFX_EMBOSS,
-+ MMAL_PARAM_IMAGEFX_OILPAINT,
-+ MMAL_PARAM_IMAGEFX_HATCH,
-+ MMAL_PARAM_IMAGEFX_GPEN,
-+ MMAL_PARAM_IMAGEFX_PASTEL,
-+ MMAL_PARAM_IMAGEFX_WATERCOLOUR,
-+ MMAL_PARAM_IMAGEFX_FILM,
-+ MMAL_PARAM_IMAGEFX_BLUR,
-+ MMAL_PARAM_IMAGEFX_SATURATION,
-+ MMAL_PARAM_IMAGEFX_COLOURSWAP,
-+ MMAL_PARAM_IMAGEFX_WASHEDOUT,
-+ MMAL_PARAM_IMAGEFX_POSTERISE,
-+ MMAL_PARAM_IMAGEFX_COLOURPOINT,
-+ MMAL_PARAM_IMAGEFX_COLOURBALANCE,
-+ MMAL_PARAM_IMAGEFX_CARTOON,
-+};
-+
-+enum MMAL_PARAM_FLICKERAVOID_T {
-+ MMAL_PARAM_FLICKERAVOID_OFF,
-+ MMAL_PARAM_FLICKERAVOID_AUTO,
-+ MMAL_PARAM_FLICKERAVOID_50HZ,
-+ MMAL_PARAM_FLICKERAVOID_60HZ,
-+ MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF
-+};
-+
-+struct mmal_parameter_awbgains {
-+ struct mmal_parameter_rational r_gain; /**< Red gain */
-+ struct mmal_parameter_rational b_gain; /**< Blue gain */
-+};
-+
-+/** Manner of video rate control */
-+enum mmal_parameter_rate_control_mode {
-+ MMAL_VIDEO_RATECONTROL_DEFAULT,
-+ MMAL_VIDEO_RATECONTROL_VARIABLE,
-+ MMAL_VIDEO_RATECONTROL_CONSTANT,
-+ MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES,
-+ MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES
-+};
-+
-+enum mmal_video_profile {
-+ MMAL_VIDEO_PROFILE_H263_BASELINE,
-+ MMAL_VIDEO_PROFILE_H263_H320CODING,
-+ MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE,
-+ MMAL_VIDEO_PROFILE_H263_ISWV2,
-+ MMAL_VIDEO_PROFILE_H263_ISWV3,
-+ MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION,
-+ MMAL_VIDEO_PROFILE_H263_INTERNET,
-+ MMAL_VIDEO_PROFILE_H263_INTERLACE,
-+ MMAL_VIDEO_PROFILE_H263_HIGHLATENCY,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLE,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE,
-+ MMAL_VIDEO_PROFILE_MP4V_CORE,
-+ MMAL_VIDEO_PROFILE_MP4V_MAIN,
-+ MMAL_VIDEO_PROFILE_MP4V_NBIT,
-+ MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE,
-+ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA,
-+ MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED,
-+ MMAL_VIDEO_PROFILE_MP4V_HYBRID,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME,
-+ MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE,
-+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE,
-+ MMAL_VIDEO_PROFILE_H264_BASELINE,
-+ MMAL_VIDEO_PROFILE_H264_MAIN,
-+ MMAL_VIDEO_PROFILE_H264_EXTENDED,
-+ MMAL_VIDEO_PROFILE_H264_HIGH,
-+ MMAL_VIDEO_PROFILE_H264_HIGH10,
-+ MMAL_VIDEO_PROFILE_H264_HIGH422,
-+ MMAL_VIDEO_PROFILE_H264_HIGH444,
-+ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE,
-+ MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF
-+};
-+
-+enum mmal_video_level {
-+ MMAL_VIDEO_LEVEL_H263_10,
-+ MMAL_VIDEO_LEVEL_H263_20,
-+ MMAL_VIDEO_LEVEL_H263_30,
-+ MMAL_VIDEO_LEVEL_H263_40,
-+ MMAL_VIDEO_LEVEL_H263_45,
-+ MMAL_VIDEO_LEVEL_H263_50,
-+ MMAL_VIDEO_LEVEL_H263_60,
-+ MMAL_VIDEO_LEVEL_H263_70,
-+ MMAL_VIDEO_LEVEL_MP4V_0,
-+ MMAL_VIDEO_LEVEL_MP4V_0b,
-+ MMAL_VIDEO_LEVEL_MP4V_1,
-+ MMAL_VIDEO_LEVEL_MP4V_2,
-+ MMAL_VIDEO_LEVEL_MP4V_3,
-+ MMAL_VIDEO_LEVEL_MP4V_4,
-+ MMAL_VIDEO_LEVEL_MP4V_4a,
-+ MMAL_VIDEO_LEVEL_MP4V_5,
-+ MMAL_VIDEO_LEVEL_MP4V_6,
-+ MMAL_VIDEO_LEVEL_H264_1,
-+ MMAL_VIDEO_LEVEL_H264_1b,
-+ MMAL_VIDEO_LEVEL_H264_11,
-+ MMAL_VIDEO_LEVEL_H264_12,
-+ MMAL_VIDEO_LEVEL_H264_13,
-+ MMAL_VIDEO_LEVEL_H264_2,
-+ MMAL_VIDEO_LEVEL_H264_21,
-+ MMAL_VIDEO_LEVEL_H264_22,
-+ MMAL_VIDEO_LEVEL_H264_3,
-+ MMAL_VIDEO_LEVEL_H264_31,
-+ MMAL_VIDEO_LEVEL_H264_32,
-+ MMAL_VIDEO_LEVEL_H264_4,
-+ MMAL_VIDEO_LEVEL_H264_41,
-+ MMAL_VIDEO_LEVEL_H264_42,
-+ MMAL_VIDEO_LEVEL_H264_5,
-+ MMAL_VIDEO_LEVEL_H264_51,
-+ MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF
-+};
-+
-+struct mmal_parameter_video_profile {
-+ enum mmal_video_profile profile;
-+ enum mmal_video_level level;
-+};
-+
-+/* video parameters */
-+
-+enum mmal_parameter_video_type {
-+ /** @ref MMAL_DISPLAYREGION_T */
-+ MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
-+ MMAL_PARAMETER_SUPPORTED_PROFILES,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */
-+ MMAL_PARAMETER_PROFILE,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_INTRAPERIOD,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */
-+ MMAL_PARAMETER_RATECONTROL,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */
-+ MMAL_PARAMETER_NALUNITFORMAT,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T.
-+ * Setting the value to zero resets to the default (one slice per frame).
-+ */
-+ MMAL_PARAMETER_MB_ROWS_PER_SLICE,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */
-+ MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */
-+ MMAL_PARAMETER_VIDEO_EEDE_ENABLE,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */
-+ MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */
-+ MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME,
-+ /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */
-+ MMAL_PARAMETER_VIDEO_INTRA_REFRESH,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */
-+ MMAL_PARAMETER_VIDEO_BIT_RATE,
-+
-+ /** @ref MMAL_PARAMETER_FRAME_RATE_T */
-+ MMAL_PARAMETER_VIDEO_FRAME_RATE,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL,
-+
-+ MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */
-+ /** @ref MMAL_PARAMETER_UINT32_T.
-+ * Changing this parameter from the default can reduce frame rate
-+ * because image buffers need to be re-pitched.
-+ */
-+ MMAL_PARAMETER_VIDEO_ALIGN_HORIZ,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T.
-+ * Changing this parameter from the default can reduce frame rate
-+ * because image buffers need to be re-pitched.
-+ */
-+ MMAL_PARAMETER_VIDEO_ALIGN_VERT,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT,
-+
-+ /**< @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_QP_P,
-+
-+ /**< @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE,
-+
-+ /* H264 specific parameters */
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS,
-+
-+ /** @ref MMAL_PARAMETER_UINT32_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */
-+ MMAL_PARAMETER_VIDEO_DRM_INIT_INFO,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO,
-+
-+ /** @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT,
-+
-+ /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */
-+ MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER,
-+
-+ /** @ref MMAL_PARAMETER_BYTES_T */
-+ MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG,
-+
-+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */
-+ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER
-+};
-+
-+/** Valid mirror modes */
-+enum mmal_parameter_mirror {
-+ MMAL_PARAM_MIRROR_NONE,
-+ MMAL_PARAM_MIRROR_VERTICAL,
-+ MMAL_PARAM_MIRROR_HORIZONTAL,
-+ MMAL_PARAM_MIRROR_BOTH,
-+};
-+
-+enum mmal_parameter_displaytransform {
-+ MMAL_DISPLAY_ROT0 = 0,
-+ MMAL_DISPLAY_MIRROR_ROT0 = 1,
-+ MMAL_DISPLAY_MIRROR_ROT180 = 2,
-+ MMAL_DISPLAY_ROT180 = 3,
-+ MMAL_DISPLAY_MIRROR_ROT90 = 4,
-+ MMAL_DISPLAY_ROT270 = 5,
-+ MMAL_DISPLAY_ROT90 = 6,
-+ MMAL_DISPLAY_MIRROR_ROT270 = 7,
-+};
-+
-+enum mmal_parameter_displaymode {
-+ MMAL_DISPLAY_MODE_FILL = 0,
-+ MMAL_DISPLAY_MODE_LETTERBOX = 1,
-+};
-+
-+enum mmal_parameter_displayset {
-+ MMAL_DISPLAY_SET_NONE = 0,
-+ MMAL_DISPLAY_SET_NUM = 1,
-+ MMAL_DISPLAY_SET_FULLSCREEN = 2,
-+ MMAL_DISPLAY_SET_TRANSFORM = 4,
-+ MMAL_DISPLAY_SET_DEST_RECT = 8,
-+ MMAL_DISPLAY_SET_SRC_RECT = 0x10,
-+ MMAL_DISPLAY_SET_MODE = 0x20,
-+ MMAL_DISPLAY_SET_PIXEL = 0x40,
-+ MMAL_DISPLAY_SET_NOASPECT = 0x80,
-+ MMAL_DISPLAY_SET_LAYER = 0x100,
-+ MMAL_DISPLAY_SET_COPYPROTECT = 0x200,
-+ MMAL_DISPLAY_SET_ALPHA = 0x400,
-+};
-+
-+struct mmal_parameter_displayregion {
-+ /** Bitfield that indicates which fields are set and should be
-+ * used. All other fields will maintain their current value.
-+ * \ref MMAL_DISPLAYSET_T defines the bits that can be
-+ * combined.
-+ */
-+ u32 set;
-+
-+ /** Describes the display output device, with 0 typically
-+ * being a directly connected LCD display. The actual values
-+ * will depend on the hardware. Code using hard-wired numbers
-+ * (e.g. 2) is certain to fail.
-+ */
-+
-+ u32 display_num;
-+ /** Indicates that we are using the full device screen area,
-+ * rather than a window of the display. If zero, then
-+ * dest_rect is used to specify a region of the display to
-+ * use.
-+ */
-+
-+ s32 fullscreen;
-+ /** Indicates any rotation or flipping used to map frames onto
-+ * the natural display orientation.
-+ */
-+ u32 transform; /* enum mmal_parameter_displaytransform */
-+
-+ /** Where to display the frame within the screen, if
-+ * fullscreen is zero.
-+ */
-+ struct vchiq_mmal_rect dest_rect;
-+
-+ /** Indicates which area of the frame to display. If all
-+ * values are zero, the whole frame will be used.
-+ */
-+ struct vchiq_mmal_rect src_rect;
-+
-+ /** If set to non-zero, indicates that any display scaling
-+ * should disregard the aspect ratio of the frame region being
-+ * displayed.
-+ */
-+ s32 noaspect;
-+
-+ /** Indicates how the image should be scaled to fit the
-+ * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates
-+ * that the image should fill the screen by potentially
-+ * cropping the frames. Setting \code mode \endcode to \code
-+ * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the
-+ * source region should be displayed and black bars added if
-+ * necessary.
-+ */
-+ u32 mode; /* enum mmal_parameter_displaymode */
-+
-+ /** If non-zero, defines the width of a source pixel relative
-+ * to \code pixel_y \endcode. If zero, then pixels default to
-+ * being square.
-+ */
-+ u32 pixel_x;
-+
-+ /** If non-zero, defines the height of a source pixel relative
-+ * to \code pixel_x \endcode. If zero, then pixels default to
-+ * being square.
-+ */
-+ u32 pixel_y;
-+
-+ /** Sets the relative depth of the images, with greater values
-+ * being in front of smaller values.
-+ */
-+ u32 layer;
-+
-+ /** Set to non-zero to ensure copy protection is used on
-+ * output.
-+ */
-+ s32 copyprotect_required;
-+
-+ /** Level of opacity of the layer, where zero is fully
-+ * transparent and 255 is fully opaque.
-+ */
-+ u32 alpha;
-+};
-+
-+#define MMAL_MAX_IMAGEFX_PARAMETERS 5
-+
-+struct mmal_parameter_imagefx_parameters {
-+ enum mmal_parameter_imagefx effect;
-+ u32 num_effect_params;
-+ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS];
-+};
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-vchiq.c linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-vchiq.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,1916 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * V4L2 driver MMAL vchiq interface code
-+ */
-+
-+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/mutex.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/completion.h>
-+#include <linux/vmalloc.h>
-+#include <asm/cacheflush.h>
-+#include <media/videobuf2-vmalloc.h>
-+
-+#include "mmal-common.h"
-+#include "mmal-vchiq.h"
-+#include "mmal-msg.h"
-+
-+#define USE_VCHIQ_ARM
-+#include "interface/vchi/vchi.h"
-+
-+/* maximum number of components supported */
-+#define VCHIQ_MMAL_MAX_COMPONENTS 4
-+
-+/*#define FULL_MSG_DUMP 1*/
-+
-+#ifdef DEBUG
-+static const char *const msg_type_names[] = {
-+ "UNKNOWN",
-+ "QUIT",
-+ "SERVICE_CLOSED",
-+ "GET_VERSION",
-+ "COMPONENT_CREATE",
-+ "COMPONENT_DESTROY",
-+ "COMPONENT_ENABLE",
-+ "COMPONENT_DISABLE",
-+ "PORT_INFO_GET",
-+ "PORT_INFO_SET",
-+ "PORT_ACTION",
-+ "BUFFER_FROM_HOST",
-+ "BUFFER_TO_HOST",
-+ "GET_STATS",
-+ "PORT_PARAMETER_SET",
-+ "PORT_PARAMETER_GET",
-+ "EVENT_TO_HOST",
-+ "GET_CORE_STATS_FOR_PORT",
-+ "OPAQUE_ALLOCATOR",
-+ "CONSUME_MEM",
-+ "LMK",
-+ "OPAQUE_ALLOCATOR_DESC",
-+ "DRM_GET_LHS32",
-+ "DRM_GET_TIME",
-+ "BUFFER_FROM_HOST_ZEROLEN",
-+ "PORT_FLUSH",
-+ "HOST_LOG",
-+};
-+#endif
-+
-+static const char *const port_action_type_names[] = {
-+ "UNKNOWN",
-+ "ENABLE",
-+ "DISABLE",
-+ "FLUSH",
-+ "CONNECT",
-+ "DISCONNECT",
-+ "SET_REQUIREMENTS",
-+};
-+
-+#if defined(DEBUG)
-+#if defined(FULL_MSG_DUMP)
-+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \
-+ do { \
-+ pr_debug(TITLE" type:%s(%d) length:%d\n", \
-+ msg_type_names[(MSG)->h.type], \
-+ (MSG)->h.type, (MSG_LEN)); \
-+ print_hex_dump(KERN_DEBUG, "<<h: ", DUMP_PREFIX_OFFSET, \
-+ 16, 4, (MSG), \
-+ sizeof(struct mmal_msg_header), 1); \
-+ print_hex_dump(KERN_DEBUG, "<<p: ", DUMP_PREFIX_OFFSET, \
-+ 16, 4, \
-+ ((u8 *)(MSG)) + sizeof(struct mmal_msg_header),\
-+ (MSG_LEN) - sizeof(struct mmal_msg_header), 1); \
-+ } while (0)
-+#else
-+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \
-+ { \
-+ pr_debug(TITLE" type:%s(%d) length:%d\n", \
-+ msg_type_names[(MSG)->h.type], \
-+ (MSG)->h.type, (MSG_LEN)); \
-+ }
-+#endif
-+#else
-+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE)
-+#endif
-+
-+/* normal message context */
-+struct mmal_msg_context {
-+ union {
-+ struct {
-+ /* work struct for defered callback - must come first */
-+ struct work_struct work;
-+ /* mmal instance */
-+ struct vchiq_mmal_instance *instance;
-+ /* mmal port */
-+ struct vchiq_mmal_port *port;
-+ /* actual buffer used to store bulk reply */
-+ struct mmal_buffer *buffer;
-+ /* amount of buffer used */
-+ unsigned long buffer_used;
-+ /* MMAL buffer flags */
-+ u32 mmal_flags;
-+ /* Presentation and Decode timestamps */
-+ s64 pts;
-+ s64 dts;
-+
-+ int status; /* context status */
-+
-+ } bulk; /* bulk data */
-+
-+ struct {
-+ /* message handle to release */
-+ VCHI_HELD_MSG_T msg_handle;
-+ /* pointer to received message */
-+ struct mmal_msg *msg;
-+ /* received message length */
-+ u32 msg_len;
-+ /* completion upon reply */
-+ struct completion cmplt;
-+ } sync; /* synchronous response */
-+ } u;
-+
-+};
-+
-+struct vchiq_mmal_instance {
-+ VCHI_SERVICE_HANDLE_T handle;
-+
-+ /* ensure serialised access to service */
-+ struct mutex vchiq_mutex;
-+
-+ /* ensure serialised access to bulk operations */
-+ struct mutex bulk_mutex;
-+
-+ /* vmalloc page to receive scratch bulk xfers into */
-+ void *bulk_scratch;
-+
-+ /* component to use next */
-+ int component_idx;
-+ struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS];
-+};
-+
-+static struct mmal_msg_context *get_msg_context(struct vchiq_mmal_instance
-+ *instance)
-+{
-+ struct mmal_msg_context *msg_context;
-+
-+ /* todo: should this be allocated from a pool to avoid kmalloc */
-+ msg_context = kmalloc(sizeof(*msg_context), GFP_KERNEL);
-+ memset(msg_context, 0, sizeof(*msg_context));
-+
-+ return msg_context;
-+}
-+
-+static void release_msg_context(struct mmal_msg_context *msg_context)
-+{
-+ kfree(msg_context);
-+}
-+
-+/* deals with receipt of event to host message */
-+static void event_to_host_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg, u32 msg_len)
-+{
-+ pr_debug("unhandled event\n");
-+ pr_debug("component:%p port type:%d num:%d cmd:0x%x length:%d\n",
-+ msg->u.event_to_host.client_component,
-+ msg->u.event_to_host.port_type,
-+ msg->u.event_to_host.port_num,
-+ msg->u.event_to_host.cmd, msg->u.event_to_host.length);
-+}
-+
-+/* workqueue scheduled callback
-+ *
-+ * we do this because it is important we do not call any other vchiq
-+ * sync calls from witin the message delivery thread
-+ */
-+static void buffer_work_cb(struct work_struct *work)
-+{
-+ struct mmal_msg_context *msg_context = (struct mmal_msg_context *)work;
-+
-+ msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance,
-+ msg_context->u.bulk.port,
-+ msg_context->u.bulk.status,
-+ msg_context->u.bulk.buffer,
-+ msg_context->u.bulk.buffer_used,
-+ msg_context->u.bulk.mmal_flags,
-+ msg_context->u.bulk.dts,
-+ msg_context->u.bulk.pts);
-+
-+ /* release message context */
-+ release_msg_context(msg_context);
-+}
-+
-+/* enqueue a bulk receive for a given message context */
-+static int bulk_receive(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg,
-+ struct mmal_msg_context *msg_context)
-+{
-+ unsigned long rd_len;
-+ unsigned long flags = 0;
-+ int ret;
-+
-+ /* bulk mutex stops other bulk operations while we have a
-+ * receive in progress - released in callback
-+ */
-+ ret = mutex_lock_interruptible(&instance->bulk_mutex);
-+ if (ret != 0)
-+ return ret;
-+
-+ rd_len = msg->u.buffer_from_host.buffer_header.length;
-+
-+ /* take buffer from queue */
-+ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
-+ if (list_empty(&msg_context->u.bulk.port->buffers)) {
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+ pr_err("buffer list empty trying to submit bulk receive\n");
-+
-+ /* todo: this is a serious error, we should never have
-+ * commited a buffer_to_host operation to the mmal
-+ * port without the buffer to back it up (underflow
-+ * handling) and there is no obvious way to deal with
-+ * this - how is the mmal servie going to react when
-+ * we fail to do the xfer and reschedule a buffer when
-+ * it arrives? perhaps a starved flag to indicate a
-+ * waiting bulk receive?
-+ */
-+
-+ mutex_unlock(&instance->bulk_mutex);
-+
-+ return -EINVAL;
-+ }
-+
-+ msg_context->u.bulk.buffer =
-+ list_entry(msg_context->u.bulk.port->buffers.next,
-+ struct mmal_buffer, list);
-+ list_del(&msg_context->u.bulk.buffer->list);
-+
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+
-+ /* ensure we do not overrun the available buffer */
-+ if (rd_len > msg_context->u.bulk.buffer->buffer_size) {
-+ rd_len = msg_context->u.bulk.buffer->buffer_size;
-+ pr_warn("short read as not enough receive buffer space\n");
-+ /* todo: is this the correct response, what happens to
-+ * the rest of the message data?
-+ */
-+ }
-+
-+ /* store length */
-+ msg_context->u.bulk.buffer_used = rd_len;
-+ msg_context->u.bulk.mmal_flags =
-+ msg->u.buffer_from_host.buffer_header.flags;
-+ msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts;
-+ msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts;
-+
-+ // only need to flush L1 cache here, as VCHIQ takes care of the L2
-+ // cache.
-+ __cpuc_flush_dcache_area(msg_context->u.bulk.buffer->buffer, rd_len);
-+
-+ /* queue the bulk submission */
-+ vchi_service_use(instance->handle);
-+ ret = vchi_bulk_queue_receive(instance->handle,
-+ msg_context->u.bulk.buffer->buffer,
-+ /* Actual receive needs to be a multiple
-+ * of 4 bytes
-+ */
-+ (rd_len + 3) & ~3,
-+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
-+ msg_context);
-+
-+ vchi_service_release(instance->handle);
-+
-+ if (ret != 0) {
-+ /* callback will not be clearing the mutex */
-+ mutex_unlock(&instance->bulk_mutex);
-+ }
-+
-+ return ret;
-+}
-+
-+/* enque a dummy bulk receive for a given message context */
-+static int dummy_bulk_receive(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg_context *msg_context)
-+{
-+ int ret;
-+
-+ /* bulk mutex stops other bulk operations while we have a
-+ * receive in progress - released in callback
-+ */
-+ ret = mutex_lock_interruptible(&instance->bulk_mutex);
-+ if (ret != 0)
-+ return ret;
-+
-+ /* zero length indicates this was a dummy transfer */
-+ msg_context->u.bulk.buffer_used = 0;
-+
-+ /* queue the bulk submission */
-+ vchi_service_use(instance->handle);
-+
-+ ret = vchi_bulk_queue_receive(instance->handle,
-+ instance->bulk_scratch,
-+ 8,
-+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
-+ msg_context);
-+
-+ vchi_service_release(instance->handle);
-+
-+ if (ret != 0) {
-+ /* callback will not be clearing the mutex */
-+ mutex_unlock(&instance->bulk_mutex);
-+ }
-+
-+ return ret;
-+}
-+
-+/* data in message, memcpy from packet into output buffer */
-+static int inline_receive(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg,
-+ struct mmal_msg_context *msg_context)
-+{
-+ unsigned long flags = 0;
-+
-+ /* take buffer from queue */
-+ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
-+ if (list_empty(&msg_context->u.bulk.port->buffers)) {
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+ pr_err("buffer list empty trying to receive inline\n");
-+
-+ /* todo: this is a serious error, we should never have
-+ * commited a buffer_to_host operation to the mmal
-+ * port without the buffer to back it up (with
-+ * underflow handling) and there is no obvious way to
-+ * deal with this. Less bad than the bulk case as we
-+ * can just drop this on the floor but...unhelpful
-+ */
-+ return -EINVAL;
-+ }
-+
-+ msg_context->u.bulk.buffer =
-+ list_entry(msg_context->u.bulk.port->buffers.next,
-+ struct mmal_buffer, list);
-+ list_del(&msg_context->u.bulk.buffer->list);
-+
-+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
-+
-+ memcpy(msg_context->u.bulk.buffer->buffer,
-+ msg->u.buffer_from_host.short_data,
-+ msg->u.buffer_from_host.payload_in_message);
-+
-+ msg_context->u.bulk.buffer_used =
-+ msg->u.buffer_from_host.payload_in_message;
-+
-+ return 0;
-+}
-+
-+/* queue the buffer availability with MMAL_MSG_TYPE_BUFFER_FROM_HOST */
-+static int
-+buffer_from_host(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port, struct mmal_buffer *buf)
-+{
-+ struct mmal_msg_context *msg_context;
-+ struct mmal_msg m;
-+ int ret;
-+
-+ pr_debug("instance:%p buffer:%p\n", instance->handle, buf);
-+
-+ /* bulk mutex stops other bulk operations while we
-+ * have a receive in progress
-+ */
-+ if (mutex_lock_interruptible(&instance->bulk_mutex))
-+ return -EINTR;
-+
-+ /* get context */
-+ msg_context = get_msg_context(instance);
-+ if (msg_context == NULL)
-+ return -ENOMEM;
-+
-+ /* store bulk message context for when data arrives */
-+ msg_context->u.bulk.instance = instance;
-+ msg_context->u.bulk.port = port;
-+ msg_context->u.bulk.buffer = NULL; /* not valid until bulk xfer */
-+ msg_context->u.bulk.buffer_used = 0;
-+
-+ /* initialise work structure ready to schedule callback */
-+ INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb);
-+
-+ /* prep the buffer from host message */
-+ memset(&m, 0xbc, sizeof(m)); /* just to make debug clearer */
-+
-+ m.h.type = MMAL_MSG_TYPE_BUFFER_FROM_HOST;
-+ m.h.magic = MMAL_MAGIC;
-+ m.h.context = msg_context;
-+ m.h.status = 0;
-+
-+ /* drvbuf is our private data passed back */
-+ m.u.buffer_from_host.drvbuf.magic = MMAL_MAGIC;
-+ m.u.buffer_from_host.drvbuf.component_handle = port->component->handle;
-+ m.u.buffer_from_host.drvbuf.port_handle = port->handle;
-+ m.u.buffer_from_host.drvbuf.client_context = msg_context;
-+
-+ /* buffer header */
-+ m.u.buffer_from_host.buffer_header.cmd = 0;
-+ m.u.buffer_from_host.buffer_header.data = buf->buffer;
-+ m.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size;
-+ m.u.buffer_from_host.buffer_header.length = 0; /* nothing used yet */
-+ m.u.buffer_from_host.buffer_header.offset = 0; /* no offset */
-+ m.u.buffer_from_host.buffer_header.flags = 0; /* no flags */
-+ m.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN;
-+ m.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN;
-+
-+ /* clear buffer type sepecific data */
-+ memset(&m.u.buffer_from_host.buffer_header_type_specific, 0,
-+ sizeof(m.u.buffer_from_host.buffer_header_type_specific));
-+
-+ /* no payload in message */
-+ m.u.buffer_from_host.payload_in_message = 0;
-+
-+ vchi_service_use(instance->handle);
-+
-+ ret = vchi_msg_queue(instance->handle, &m,
-+ sizeof(struct mmal_msg_header) +
-+ sizeof(m.u.buffer_from_host),
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (ret != 0) {
-+ release_msg_context(msg_context);
-+ /* todo: is this correct error value? */
-+ }
-+
-+ vchi_service_release(instance->handle);
-+
-+ mutex_unlock(&instance->bulk_mutex);
-+
-+ return ret;
-+}
-+
-+/* submit a buffer to the mmal sevice
-+ *
-+ * the buffer_from_host uses size data from the ports next available
-+ * mmal_buffer and deals with there being no buffer available by
-+ * incrementing the underflow for later
-+ */
-+static int port_buffer_from_host(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct mmal_buffer *buf;
-+ unsigned long flags = 0;
-+
-+ if (!port->enabled)
-+ return -EINVAL;
-+
-+ /* peek buffer from queue */
-+ spin_lock_irqsave(&port->slock, flags);
-+ if (list_empty(&port->buffers)) {
-+ port->buffer_underflow++;
-+ spin_unlock_irqrestore(&port->slock, flags);
-+ return -ENOSPC;
-+ }
-+
-+ buf = list_entry(port->buffers.next, struct mmal_buffer, list);
-+
-+ spin_unlock_irqrestore(&port->slock, flags);
-+
-+ /* issue buffer to mmal service */
-+ ret = buffer_from_host(instance, port, buf);
-+ if (ret) {
-+ pr_err("adding buffer header failed\n");
-+ /* todo: how should this be dealt with */
-+ }
-+
-+ return ret;
-+}
-+
-+/* deals with receipt of buffer to host message */
-+static void buffer_to_host_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg, u32 msg_len)
-+{
-+ struct mmal_msg_context *msg_context;
-+
-+ pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n",
-+ instance, msg, msg_len);
-+
-+ if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) {
-+ msg_context = msg->u.buffer_from_host.drvbuf.client_context;
-+ } else {
-+ pr_err("MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\n");
-+ return;
-+ }
-+
-+ if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) {
-+ /* message reception had an error */
-+ pr_warn("error %d in reply\n", msg->h.status);
-+
-+ msg_context->u.bulk.status = msg->h.status;
-+
-+ } else if (msg->u.buffer_from_host.buffer_header.length == 0) {
-+ /* empty buffer */
-+ if (msg->u.buffer_from_host.buffer_header.flags &
-+ MMAL_BUFFER_HEADER_FLAG_EOS) {
-+ msg_context->u.bulk.status =
-+ dummy_bulk_receive(instance, msg_context);
-+ if (msg_context->u.bulk.status == 0)
-+ return; /* successful bulk submission, bulk
-+ * completion will trigger callback
-+ */
-+ } else {
-+ /* do callback with empty buffer - not EOS though */
-+ msg_context->u.bulk.status = 0;
-+ msg_context->u.bulk.buffer_used = 0;
-+ }
-+ } else if (msg->u.buffer_from_host.payload_in_message == 0) {
-+ /* data is not in message, queue a bulk receive */
-+ msg_context->u.bulk.status =
-+ bulk_receive(instance, msg, msg_context);
-+ if (msg_context->u.bulk.status == 0)
-+ return; /* successful bulk submission, bulk
-+ * completion will trigger callback
-+ */
-+
-+ /* failed to submit buffer, this will end badly */
-+ pr_err("error %d on bulk submission\n",
-+ msg_context->u.bulk.status);
-+
-+ } else if (msg->u.buffer_from_host.payload_in_message <=
-+ MMAL_VC_SHORT_DATA) {
-+ /* data payload within message */
-+ msg_context->u.bulk.status = inline_receive(instance, msg,
-+ msg_context);
-+ } else {
-+ pr_err("message with invalid short payload\n");
-+
-+ /* signal error */
-+ msg_context->u.bulk.status = -EINVAL;
-+ msg_context->u.bulk.buffer_used =
-+ msg->u.buffer_from_host.payload_in_message;
-+ }
-+
-+ /* replace the buffer header */
-+ port_buffer_from_host(instance, msg_context->u.bulk.port);
-+
-+ /* schedule the port callback */
-+ schedule_work(&msg_context->u.bulk.work);
-+}
-+
-+static void bulk_receive_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg_context *msg_context)
-+{
-+ /* bulk receive operation complete */
-+ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
-+
-+ /* replace the buffer header */
-+ port_buffer_from_host(msg_context->u.bulk.instance,
-+ msg_context->u.bulk.port);
-+
-+ msg_context->u.bulk.status = 0;
-+
-+ /* schedule the port callback */
-+ schedule_work(&msg_context->u.bulk.work);
-+}
-+
-+static void bulk_abort_cb(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg_context *msg_context)
-+{
-+ pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context);
-+
-+ /* bulk receive operation complete */
-+ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
-+
-+ /* replace the buffer header */
-+ port_buffer_from_host(msg_context->u.bulk.instance,
-+ msg_context->u.bulk.port);
-+
-+ msg_context->u.bulk.status = -EINTR;
-+
-+ schedule_work(&msg_context->u.bulk.work);
-+}
-+
-+/* incoming event service callback */
-+static void service_callback(void *param,
-+ const VCHI_CALLBACK_REASON_T reason,
-+ void *bulk_ctx)
-+{
-+ struct vchiq_mmal_instance *instance = param;
-+ int status;
-+ u32 msg_len;
-+ struct mmal_msg *msg;
-+ VCHI_HELD_MSG_T msg_handle;
-+
-+ if (!instance) {
-+ pr_err("Message callback passed NULL instance\n");
-+ return;
-+ }
-+
-+ switch (reason) {
-+ case VCHI_CALLBACK_MSG_AVAILABLE:
-+ status = vchi_msg_hold(instance->handle, (void **)&msg,
-+ &msg_len, VCHI_FLAGS_NONE, &msg_handle);
-+ if (status) {
-+ pr_err("Unable to dequeue a message (%d)\n", status);
-+ break;
-+ }
-+
-+ DBG_DUMP_MSG(msg, msg_len, "<<< reply message");
-+
-+ /* handling is different for buffer messages */
-+ switch (msg->h.type) {
-+
-+ case MMAL_MSG_TYPE_BUFFER_FROM_HOST:
-+ vchi_held_msg_release(&msg_handle);
-+ break;
-+
-+ case MMAL_MSG_TYPE_EVENT_TO_HOST:
-+ event_to_host_cb(instance, msg, msg_len);
-+ vchi_held_msg_release(&msg_handle);
-+
-+ break;
-+
-+ case MMAL_MSG_TYPE_BUFFER_TO_HOST:
-+ buffer_to_host_cb(instance, msg, msg_len);
-+ vchi_held_msg_release(&msg_handle);
-+ break;
-+
-+ default:
-+ /* messages dependant on header context to complete */
-+
-+ /* todo: the msg.context really ought to be sanity
-+ * checked before we just use it, afaict it comes back
-+ * and is used raw from the videocore. Perhaps it
-+ * should be verified the address lies in the kernel
-+ * address space.
-+ */
-+ if (msg->h.context == NULL) {
-+ pr_err("received message context was null!\n");
-+ vchi_held_msg_release(&msg_handle);
-+ break;
-+ }
-+
-+ /* fill in context values */
-+ msg->h.context->u.sync.msg_handle = msg_handle;
-+ msg->h.context->u.sync.msg = msg;
-+ msg->h.context->u.sync.msg_len = msg_len;
-+
-+ /* todo: should this check (completion_done()
-+ * == 1) for no one waiting? or do we need a
-+ * flag to tell us the completion has been
-+ * interrupted so we can free the message and
-+ * its context. This probably also solves the
-+ * message arriving after interruption todo
-+ * below
-+ */
-+
-+ /* complete message so caller knows it happened */
-+ complete(&msg->h.context->u.sync.cmplt);
-+ break;
-+ }
-+
-+ break;
-+
-+ case VCHI_CALLBACK_BULK_RECEIVED:
-+ bulk_receive_cb(instance, bulk_ctx);
-+ break;
-+
-+ case VCHI_CALLBACK_BULK_RECEIVE_ABORTED:
-+ bulk_abort_cb(instance, bulk_ctx);
-+ break;
-+
-+ case VCHI_CALLBACK_SERVICE_CLOSED:
-+ /* TODO: consider if this requires action if received when
-+ * driver is not explicitly closing the service
-+ */
-+ break;
-+
-+ default:
-+ pr_err("Received unhandled message reason %d\n", reason);
-+ break;
-+ }
-+}
-+
-+static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance,
-+ struct mmal_msg *msg,
-+ unsigned int payload_len,
-+ struct mmal_msg **msg_out,
-+ VCHI_HELD_MSG_T *msg_handle_out)
-+{
-+ struct mmal_msg_context msg_context;
-+ int ret;
-+
-+ /* payload size must not cause message to exceed max size */
-+ if (payload_len >
-+ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) {
-+ pr_err("payload length %d exceeds max:%d\n", payload_len,
-+ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header)));
-+ return -EINVAL;
-+ }
-+
-+ init_completion(&msg_context.u.sync.cmplt);
-+
-+ msg->h.magic = MMAL_MAGIC;
-+ msg->h.context = &msg_context;
-+ msg->h.status = 0;
-+
-+ DBG_DUMP_MSG(msg, (sizeof(struct mmal_msg_header) + payload_len),
-+ ">>> sync message");
-+
-+ vchi_service_use(instance->handle);
-+
-+ ret = vchi_msg_queue(instance->handle,
-+ msg,
-+ sizeof(struct mmal_msg_header) + payload_len,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ vchi_service_release(instance->handle);
-+
-+ if (ret) {
-+ pr_err("error %d queuing message\n", ret);
-+ return ret;
-+ }
-+
-+ ret = wait_for_completion_timeout(&msg_context.u.sync.cmplt, 3*HZ);
-+ if (ret <= 0) {
-+ pr_err("error %d waiting for sync completion\n", ret);
-+ if (ret == 0)
-+ ret = -ETIME;
-+ /* todo: what happens if the message arrives after aborting */
-+ return ret;
-+ }
-+
-+ *msg_out = msg_context.u.sync.msg;
-+ *msg_handle_out = msg_context.u.sync.msg_handle;
-+
-+ return 0;
-+}
-+
-+static void dump_port_info(struct vchiq_mmal_port *port)
-+{
-+ pr_debug("port handle:0x%x enabled:%d\n", port->handle, port->enabled);
-+
-+ pr_debug("buffer minimum num:%d size:%d align:%d\n",
-+ port->minimum_buffer.num,
-+ port->minimum_buffer.size, port->minimum_buffer.alignment);
-+
-+ pr_debug("buffer recommended num:%d size:%d align:%d\n",
-+ port->recommended_buffer.num,
-+ port->recommended_buffer.size,
-+ port->recommended_buffer.alignment);
-+
-+ pr_debug("buffer current values num:%d size:%d align:%d\n",
-+ port->current_buffer.num,
-+ port->current_buffer.size, port->current_buffer.alignment);
-+
-+ pr_debug("elementry stream: type:%d encoding:0x%x varient:0x%x\n",
-+ port->format.type,
-+ port->format.encoding, port->format.encoding_variant);
-+
-+ pr_debug(" bitrate:%d flags:0x%x\n",
-+ port->format.bitrate, port->format.flags);
-+
-+ if (port->format.type == MMAL_ES_TYPE_VIDEO) {
-+ pr_debug
-+ ("es video format: width:%d height:%d colourspace:0x%x\n",
-+ port->es.video.width, port->es.video.height,
-+ port->es.video.color_space);
-+
-+ pr_debug(" : crop xywh %d,%d,%d,%d\n",
-+ port->es.video.crop.x,
-+ port->es.video.crop.y,
-+ port->es.video.crop.width, port->es.video.crop.height);
-+ pr_debug(" : framerate %d/%d aspect %d/%d\n",
-+ port->es.video.frame_rate.num,
-+ port->es.video.frame_rate.den,
-+ port->es.video.par.num, port->es.video.par.den);
-+ }
-+}
-+
-+static void port_to_mmal_msg(struct vchiq_mmal_port *port, struct mmal_port *p)
-+{
-+
-+ /* todo do readonly fields need setting at all? */
-+ p->type = port->type;
-+ p->index = port->index;
-+ p->index_all = 0;
-+ p->is_enabled = port->enabled;
-+ p->buffer_num_min = port->minimum_buffer.num;
-+ p->buffer_size_min = port->minimum_buffer.size;
-+ p->buffer_alignment_min = port->minimum_buffer.alignment;
-+ p->buffer_num_recommended = port->recommended_buffer.num;
-+ p->buffer_size_recommended = port->recommended_buffer.size;
-+
-+ /* only three writable fields in a port */
-+ p->buffer_num = port->current_buffer.num;
-+ p->buffer_size = port->current_buffer.size;
-+ p->userdata = port;
-+}
-+
-+static int port_info_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ pr_debug("setting port info port %p\n", port);
-+ if (!port)
-+ return -1;
-+ dump_port_info(port);
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_INFO_SET;
-+
-+ m.u.port_info_set.component_handle = port->component->handle;
-+ m.u.port_info_set.port_type = port->type;
-+ m.u.port_info_set.port_index = port->index;
-+
-+ port_to_mmal_msg(port, &m.u.port_info_set.port);
-+
-+ /* elementry stream format setup */
-+ m.u.port_info_set.format.type = port->format.type;
-+ m.u.port_info_set.format.encoding = port->format.encoding;
-+ m.u.port_info_set.format.encoding_variant =
-+ port->format.encoding_variant;
-+ m.u.port_info_set.format.bitrate = port->format.bitrate;
-+ m.u.port_info_set.format.flags = port->format.flags;
-+
-+ memcpy(&m.u.port_info_set.es, &port->es,
-+ sizeof(union mmal_es_specific_format));
-+
-+ m.u.port_info_set.format.extradata_size = port->format.extradata_size;
-+ memcpy(rmsg->u.port_info_set.extradata, port->format.extradata,
-+ port->format.extradata_size);
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_info_set),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_SET) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ /* return operation status */
-+ ret = -rmsg->u.port_info_get_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d\n", __func__, ret,
-+ port->component->handle, port->handle);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+
-+}
-+
-+/* use port info get message to retrive port information */
-+static int port_info_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ /* port info time */
-+ m.h.type = MMAL_MSG_TYPE_PORT_INFO_GET;
-+ m.u.port_info_get.component_handle = port->component->handle;
-+ m.u.port_info_get.port_type = port->type;
-+ m.u.port_info_get.index = port->index;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_info_get),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_GET) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ /* return operation status */
-+ ret = -rmsg->u.port_info_get_reply.status;
-+ if (ret != MMAL_MSG_STATUS_SUCCESS)
-+ goto release_msg;
-+
-+ if (rmsg->u.port_info_get_reply.port.is_enabled == 0)
-+ port->enabled = false;
-+ else
-+ port->enabled = true;
-+
-+ /* copy the values out of the message */
-+ port->handle = rmsg->u.port_info_get_reply.port_handle;
-+
-+ /* port type and index cached to use on port info set becuase
-+ * it does not use a port handle
-+ */
-+ port->type = rmsg->u.port_info_get_reply.port_type;
-+ port->index = rmsg->u.port_info_get_reply.port_index;
-+
-+ port->minimum_buffer.num =
-+ rmsg->u.port_info_get_reply.port.buffer_num_min;
-+ port->minimum_buffer.size =
-+ rmsg->u.port_info_get_reply.port.buffer_size_min;
-+ port->minimum_buffer.alignment =
-+ rmsg->u.port_info_get_reply.port.buffer_alignment_min;
-+
-+ port->recommended_buffer.alignment =
-+ rmsg->u.port_info_get_reply.port.buffer_alignment_min;
-+ port->recommended_buffer.num =
-+ rmsg->u.port_info_get_reply.port.buffer_num_recommended;
-+
-+ port->current_buffer.num = rmsg->u.port_info_get_reply.port.buffer_num;
-+ port->current_buffer.size =
-+ rmsg->u.port_info_get_reply.port.buffer_size;
-+
-+ /* stream format */
-+ port->format.type = rmsg->u.port_info_get_reply.format.type;
-+ port->format.encoding = rmsg->u.port_info_get_reply.format.encoding;
-+ port->format.encoding_variant =
-+ rmsg->u.port_info_get_reply.format.encoding_variant;
-+ port->format.bitrate = rmsg->u.port_info_get_reply.format.bitrate;
-+ port->format.flags = rmsg->u.port_info_get_reply.format.flags;
-+
-+ /* elementry stream format */
-+ memcpy(&port->es,
-+ &rmsg->u.port_info_get_reply.es,
-+ sizeof(union mmal_es_specific_format));
-+ port->format.es = &port->es;
-+
-+ port->format.extradata_size =
-+ rmsg->u.port_info_get_reply.format.extradata_size;
-+ memcpy(port->format.extradata,
-+ rmsg->u.port_info_get_reply.extradata,
-+ port->format.extradata_size);
-+
-+ pr_debug("received port info\n");
-+ dump_port_info(port);
-+
-+release_msg:
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d\n",
-+ __func__, ret, port->component->handle, port->handle);
-+
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* create comonent on vc */
-+static int create_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component,
-+ const char *name)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ /* build component create message */
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_CREATE;
-+ m.u.component_create.client_component = component;
-+ strncpy(m.u.component_create.name, name,
-+ sizeof(m.u.component_create.name));
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_create),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_create_reply.status;
-+ if (ret != MMAL_MSG_STATUS_SUCCESS)
-+ goto release_msg;
-+
-+ /* a valid component response received */
-+ component->handle = rmsg->u.component_create_reply.component_handle;
-+ component->inputs = rmsg->u.component_create_reply.input_num;
-+ component->outputs = rmsg->u.component_create_reply.output_num;
-+ component->clocks = rmsg->u.component_create_reply.clock_num;
-+
-+ pr_debug("Component handle:0x%x in:%d out:%d clock:%d\n",
-+ component->handle,
-+ component->inputs, component->outputs, component->clocks);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* destroys a component on vc */
-+static int destroy_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_DESTROY;
-+ m.u.component_destroy.component_handle = component->handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_destroy),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_destroy_reply.status;
-+
-+release_msg:
-+
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* enable a component on vc */
-+static int enable_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_ENABLE;
-+ m.u.component_enable.component_handle = component->handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_enable),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_enable_reply.status;
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* disable a component on vc */
-+static int disable_component(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_COMPONENT_DISABLE;
-+ m.u.component_disable.component_handle = component->handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.component_disable),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.component_disable_reply.status;
-+
-+release_msg:
-+
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* get version of mmal implementation */
-+static int get_version(struct vchiq_mmal_instance *instance,
-+ u32 *major_out, u32 *minor_out)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_GET_VERSION;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.version),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != m.h.type) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ *major_out = rmsg->u.version.major;
-+ *minor_out = rmsg->u.version.minor;
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* do a port action with a port as a parameter */
-+static int port_action_port(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ enum mmal_msg_port_action_type action_type)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_ACTION;
-+ m.u.port_action_port.component_handle = port->component->handle;
-+ m.u.port_action_port.port_handle = port->handle;
-+ m.u.port_action_port.action = action_type;
-+
-+ port_to_mmal_msg(port, &m.u.port_action_port.port);
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_action_port),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_action_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)\n",
-+ __func__,
-+ ret, port->component->handle, port->handle,
-+ port_action_type_names[action_type], action_type);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* do a port action with handles as parameters */
-+static int port_action_handle(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ enum mmal_msg_port_action_type action_type,
-+ u32 connect_component_handle,
-+ u32 connect_port_handle)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_ACTION;
-+
-+ m.u.port_action_handle.component_handle = port->component->handle;
-+ m.u.port_action_handle.port_handle = port->handle;
-+ m.u.port_action_handle.action = action_type;
-+
-+ m.u.port_action_handle.connect_component_handle =
-+ connect_component_handle;
-+ m.u.port_action_handle.connect_port_handle = connect_port_handle;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(m.u.port_action_handle),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_action_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \
-+ " connect component:0x%x connect port:%d\n",
-+ __func__,
-+ ret, port->component->handle, port->handle,
-+ port_action_type_names[action_type],
-+ action_type, connect_component_handle, connect_port_handle);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+static int port_parameter_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter_id, void *value, u32 value_size)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_SET;
-+
-+ m.u.port_parameter_set.component_handle = port->component->handle;
-+ m.u.port_parameter_set.port_handle = port->handle;
-+ m.u.port_parameter_set.id = parameter_id;
-+ m.u.port_parameter_set.size = (2 * sizeof(u32)) + value_size;
-+ memcpy(&m.u.port_parameter_set.value, value, value_size);
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ (4 * sizeof(u32)) + value_size,
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_SET) {
-+ /* got an unexpected message type in reply */
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_parameter_set_reply.status;
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n",
-+ __func__,
-+ ret, port->component->handle, port->handle, parameter_id);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+static int port_parameter_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter_id, void *value, u32 *value_size)
-+{
-+ int ret;
-+ struct mmal_msg m;
-+ struct mmal_msg *rmsg;
-+ VCHI_HELD_MSG_T rmsg_handle;
-+
-+ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_GET;
-+
-+ m.u.port_parameter_get.component_handle = port->component->handle;
-+ m.u.port_parameter_get.port_handle = port->handle;
-+ m.u.port_parameter_get.id = parameter_id;
-+ m.u.port_parameter_get.size = (2 * sizeof(u32)) + *value_size;
-+
-+ ret = send_synchronous_mmal_msg(instance, &m,
-+ sizeof(struct
-+ mmal_msg_port_parameter_get),
-+ &rmsg, &rmsg_handle);
-+ if (ret)
-+ return ret;
-+
-+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_GET) {
-+ /* got an unexpected message type in reply */
-+ pr_err("Incorrect reply type %d\n", rmsg->h.type);
-+ ret = -EINVAL;
-+ goto release_msg;
-+ }
-+
-+ ret = -rmsg->u.port_parameter_get_reply.status;
-+ if (ret) {
-+ /* Copy only as much as we have space for
-+ * but report true size of parameter
-+ */
-+ memcpy(value, &rmsg->u.port_parameter_get_reply.value,
-+ *value_size);
-+ *value_size = rmsg->u.port_parameter_get_reply.size;
-+ } else
-+ memcpy(value, &rmsg->u.port_parameter_get_reply.value,
-+ rmsg->u.port_parameter_get_reply.size);
-+
-+ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__,
-+ ret, port->component->handle, port->handle, parameter_id);
-+
-+release_msg:
-+ vchi_held_msg_release(&rmsg_handle);
-+
-+ return ret;
-+}
-+
-+/* disables a port and drains buffers from it */
-+static int port_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+ struct list_head *q, *buf_head;
-+ unsigned long flags = 0;
-+
-+ if (!port->enabled)
-+ return 0;
-+
-+ port->enabled = false;
-+
-+ ret = port_action_port(instance, port,
-+ MMAL_MSG_PORT_ACTION_TYPE_DISABLE);
-+ if (ret == 0) {
-+
-+ /* drain all queued buffers on port */
-+ spin_lock_irqsave(&port->slock, flags);
-+
-+ list_for_each_safe(buf_head, q, &port->buffers) {
-+ struct mmal_buffer *mmalbuf;
-+ mmalbuf = list_entry(buf_head, struct mmal_buffer,
-+ list);
-+ list_del(buf_head);
-+ if (port->buffer_cb)
-+ port->buffer_cb(instance,
-+ port, 0, mmalbuf, 0, 0,
-+ MMAL_TIME_UNKNOWN,
-+ MMAL_TIME_UNKNOWN);
-+ }
-+
-+ spin_unlock_irqrestore(&port->slock, flags);
-+
-+ ret = port_info_get(instance, port);
-+ }
-+
-+ return ret;
-+}
-+
-+/* enable a port */
-+static int port_enable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ unsigned int hdr_count;
-+ struct list_head *buf_head;
-+ int ret;
-+
-+ if (port->enabled)
-+ return 0;
-+
-+ /* ensure there are enough buffers queued to cover the buffer headers */
-+ if (port->buffer_cb != NULL) {
-+ hdr_count = 0;
-+ list_for_each(buf_head, &port->buffers) {
-+ hdr_count++;
-+ }
-+ if (hdr_count < port->current_buffer.num)
-+ return -ENOSPC;
-+ }
-+
-+ ret = port_action_port(instance, port,
-+ MMAL_MSG_PORT_ACTION_TYPE_ENABLE);
-+ if (ret)
-+ goto done;
-+
-+ port->enabled = true;
-+
-+ if (port->buffer_cb) {
-+ /* send buffer headers to videocore */
-+ hdr_count = 1;
-+ list_for_each(buf_head, &port->buffers) {
-+ struct mmal_buffer *mmalbuf;
-+ mmalbuf = list_entry(buf_head, struct mmal_buffer,
-+ list);
-+ ret = buffer_from_host(instance, port, mmalbuf);
-+ if (ret)
-+ goto done;
-+
-+ hdr_count++;
-+ if (hdr_count > port->current_buffer.num)
-+ break;
-+ }
-+ }
-+
-+ ret = port_info_get(instance, port);
-+
-+done:
-+ return ret;
-+}
-+
-+/* ------------------------------------------------------------------
-+ * Exported API
-+ *------------------------------------------------------------------*/
-+
-+int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = port_info_set(instance, port);
-+ if (ret)
-+ goto release_unlock;
-+
-+ /* read what has actually been set */
-+ ret = port_info_get(instance, port);
-+
-+release_unlock:
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+
-+}
-+
-+int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter, void *value, u32 value_size)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = port_parameter_set(instance, port, parameter, value, value_size);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter, void *value, u32 *value_size)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = port_parameter_get(instance, port, parameter, value, value_size);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/* enable a port
-+ *
-+ * enables a port and queues buffers for satisfying callbacks if we
-+ * provide a callback handler
-+ */
-+int vchiq_mmal_port_enable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ vchiq_mmal_buffer_cb buffer_cb)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ /* already enabled - noop */
-+ if (port->enabled) {
-+ ret = 0;
-+ goto unlock;
-+ }
-+
-+ port->buffer_cb = buffer_cb;
-+
-+ ret = port_enable(instance, port);
-+
-+unlock:
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (!port->enabled) {
-+ mutex_unlock(&instance->vchiq_mutex);
-+ return 0;
-+ }
-+
-+ ret = port_disable(instance, port);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/* ports will be connected in a tunneled manner so data buffers
-+ * are not handled by client.
-+ */
-+int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *src,
-+ struct vchiq_mmal_port *dst)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ /* disconnect ports if connected */
-+ if (src->connected != NULL) {
-+ ret = port_disable(instance, src);
-+ if (ret) {
-+ pr_err("failed disabling src port(%d)\n", ret);
-+ goto release_unlock;
-+ }
-+
-+ /* do not need to disable the destination port as they
-+ * are connected and it is done automatically
-+ */
-+
-+ ret = port_action_handle(instance, src,
-+ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT,
-+ src->connected->component->handle,
-+ src->connected->handle);
-+ if (ret < 0) {
-+ pr_err("failed disconnecting src port\n");
-+ goto release_unlock;
-+ }
-+ src->connected->enabled = false;
-+ src->connected = NULL;
-+ }
-+
-+ if (dst == NULL) {
-+ /* do not make new connection */
-+ ret = 0;
-+ pr_debug("not making new connection\n");
-+ goto release_unlock;
-+ }
-+
-+ /* copy src port format to dst */
-+ dst->format.encoding = src->format.encoding;
-+ dst->es.video.width = src->es.video.width;
-+ dst->es.video.height = src->es.video.height;
-+ dst->es.video.crop.x = src->es.video.crop.x;
-+ dst->es.video.crop.y = src->es.video.crop.y;
-+ dst->es.video.crop.width = src->es.video.crop.width;
-+ dst->es.video.crop.height = src->es.video.crop.height;
-+ dst->es.video.frame_rate.num = src->es.video.frame_rate.num;
-+ dst->es.video.frame_rate.den = src->es.video.frame_rate.den;
-+
-+ /* set new format */
-+ ret = port_info_set(instance, dst);
-+ if (ret) {
-+ pr_debug("setting port info failed\n");
-+ goto release_unlock;
-+ }
-+
-+ /* read what has actually been set */
-+ ret = port_info_get(instance, dst);
-+ if (ret) {
-+ pr_debug("read back port info failed\n");
-+ goto release_unlock;
-+ }
-+
-+ /* connect two ports together */
-+ ret = port_action_handle(instance, src,
-+ MMAL_MSG_PORT_ACTION_TYPE_CONNECT,
-+ dst->component->handle, dst->handle);
-+ if (ret < 0) {
-+ pr_debug("connecting port %d:%d to %d:%d failed\n",
-+ src->component->handle, src->handle,
-+ dst->component->handle, dst->handle);
-+ goto release_unlock;
-+ }
-+ src->connected = dst;
-+
-+release_unlock:
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ struct mmal_buffer *buffer)
-+{
-+ unsigned long flags = 0;
-+
-+ spin_lock_irqsave(&port->slock, flags);
-+ list_add_tail(&buffer->list, &port->buffers);
-+ spin_unlock_irqrestore(&port->slock, flags);
-+
-+ /* the port previously underflowed because it was missing a
-+ * mmal_buffer which has just been added, submit that buffer
-+ * to the mmal service.
-+ */
-+ if (port->buffer_underflow) {
-+ port_buffer_from_host(instance, port);
-+ port->buffer_underflow--;
-+ }
-+
-+ return 0;
-+}
-+
-+/* Initialise a mmal component and its ports
-+ *
-+ */
-+int vchiq_mmal_component_init(struct vchiq_mmal_instance *instance,
-+ const char *name,
-+ struct vchiq_mmal_component **component_out)
-+{
-+ int ret;
-+ int idx; /* port index */
-+ struct vchiq_mmal_component *component;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (instance->component_idx == VCHIQ_MMAL_MAX_COMPONENTS) {
-+ ret = -EINVAL; /* todo is this correct error? */
-+ goto unlock;
-+ }
-+
-+ component = &instance->component[instance->component_idx];
-+
-+ ret = create_component(instance, component, name);
-+ if (ret < 0)
-+ goto unlock;
-+
-+ /* ports info needs gathering */
-+ component->control.type = MMAL_PORT_TYPE_CONTROL;
-+ component->control.index = 0;
-+ component->control.component = component;
-+ spin_lock_init(&component->control.slock);
-+ INIT_LIST_HEAD(&component->control.buffers);
-+ ret = port_info_get(instance, &component->control);
-+ if (ret < 0)
-+ goto release_component;
-+
-+ for (idx = 0; idx < component->inputs; idx++) {
-+ component->input[idx].type = MMAL_PORT_TYPE_INPUT;
-+ component->input[idx].index = idx;
-+ component->input[idx].component = component;
-+ spin_lock_init(&component->input[idx].slock);
-+ INIT_LIST_HEAD(&component->input[idx].buffers);
-+ ret = port_info_get(instance, &component->input[idx]);
-+ if (ret < 0)
-+ goto release_component;
-+ }
-+
-+ for (idx = 0; idx < component->outputs; idx++) {
-+ component->output[idx].type = MMAL_PORT_TYPE_OUTPUT;
-+ component->output[idx].index = idx;
-+ component->output[idx].component = component;
-+ spin_lock_init(&component->output[idx].slock);
-+ INIT_LIST_HEAD(&component->output[idx].buffers);
-+ ret = port_info_get(instance, &component->output[idx]);
-+ if (ret < 0)
-+ goto release_component;
-+ }
-+
-+ for (idx = 0; idx < component->clocks; idx++) {
-+ component->clock[idx].type = MMAL_PORT_TYPE_CLOCK;
-+ component->clock[idx].index = idx;
-+ component->clock[idx].component = component;
-+ spin_lock_init(&component->clock[idx].slock);
-+ INIT_LIST_HEAD(&component->clock[idx].buffers);
-+ ret = port_info_get(instance, &component->clock[idx]);
-+ if (ret < 0)
-+ goto release_component;
-+ }
-+
-+ instance->component_idx++;
-+
-+ *component_out = component;
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return 0;
-+
-+release_component:
-+ destroy_component(instance, component);
-+unlock:
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/*
-+ * cause a mmal component to be destroyed
-+ */
-+int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (component->enabled)
-+ ret = disable_component(instance, component);
-+
-+ ret = destroy_component(instance, component);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/*
-+ * cause a mmal component to be enabled
-+ */
-+int vchiq_mmal_component_enable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (component->enabled) {
-+ mutex_unlock(&instance->vchiq_mutex);
-+ return 0;
-+ }
-+
-+ ret = enable_component(instance, component);
-+ if (ret == 0)
-+ component->enabled = true;
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+/*
-+ * cause a mmal component to be enabled
-+ */
-+int vchiq_mmal_component_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ if (!component->enabled) {
-+ mutex_unlock(&instance->vchiq_mutex);
-+ return 0;
-+ }
-+
-+ ret = disable_component(instance, component);
-+ if (ret == 0)
-+ component->enabled = false;
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
-+ u32 *major_out, u32 *minor_out)
-+{
-+ int ret;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ ret = get_version(instance, major_out, minor_out);
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ return ret;
-+}
-+
-+int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance)
-+{
-+ int status = 0;
-+
-+ if (instance == NULL)
-+ return -EINVAL;
-+
-+ if (mutex_lock_interruptible(&instance->vchiq_mutex))
-+ return -EINTR;
-+
-+ vchi_service_use(instance->handle);
-+
-+ status = vchi_service_close(instance->handle);
-+ if (status != 0)
-+ pr_err("mmal-vchiq: VCHIQ close failed");
-+
-+ mutex_unlock(&instance->vchiq_mutex);
-+
-+ vfree(instance->bulk_scratch);
-+
-+ kfree(instance);
-+
-+ return status;
-+}
-+
-+int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance)
-+{
-+ int status;
-+ struct vchiq_mmal_instance *instance;
-+ static VCHI_CONNECTION_T *vchi_connection;
-+ static VCHI_INSTANCE_T vchi_instance;
-+ SERVICE_CREATION_T params = {
-+ VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER),
-+ VC_MMAL_SERVER_NAME,
-+ vchi_connection,
-+ 0, /* rx fifo size (unused) */
-+ 0, /* tx fifo size (unused) */
-+ service_callback,
-+ NULL, /* service callback parameter */
-+ 1, /* unaligned bulk receives */
-+ 1, /* unaligned bulk transmits */
-+ 0 /* want crc check on bulk transfers */
-+ };
-+
-+ /* compile time checks to ensure structure size as they are
-+ * directly (de)serialised from memory.
-+ */
-+
-+ /* ensure the header structure has packed to the correct size */
-+ BUILD_BUG_ON(sizeof(struct mmal_msg_header) != 24);
-+
-+ /* ensure message structure does not exceed maximum length */
-+ BUILD_BUG_ON(sizeof(struct mmal_msg) > MMAL_MSG_MAX_SIZE);
-+
-+ /* mmal port struct is correct size */
-+ BUILD_BUG_ON(sizeof(struct mmal_port) != 64);
-+
-+ /* create a vchi instance */
-+ status = vchi_initialise(&vchi_instance);
-+ if (status) {
-+ pr_err("Failed to initialise VCHI instance (status=%d)\n",
-+ status);
-+ return -EIO;
-+ }
-+
-+ status = vchi_connect(NULL, 0, vchi_instance);
-+ if (status) {
-+ pr_err("Failed to connect VCHI instance (status=%d)\n", status);
-+ return -EIO;
-+ }
-+
-+ instance = kmalloc(sizeof(*instance), GFP_KERNEL);
-+ memset(instance, 0, sizeof(*instance));
-+
-+ mutex_init(&instance->vchiq_mutex);
-+ mutex_init(&instance->bulk_mutex);
-+
-+ instance->bulk_scratch = vmalloc(PAGE_SIZE);
-+
-+ params.callback_param = instance;
-+
-+ status = vchi_service_open(vchi_instance, &params, &instance->handle);
-+ if (status) {
-+ pr_err("Failed to open VCHI service connection (status=%d)\n",
-+ status);
-+ goto err_close_services;
-+ }
-+
-+ vchi_service_release(instance->handle);
-+
-+ *out_instance = instance;
-+
-+ return 0;
-+
-+err_close_services:
-+
-+ vchi_service_close(instance->handle);
-+ vfree(instance->bulk_scratch);
-+ kfree(instance);
-+ return -ENODEV;
-+}
-diff -Nur linux-3.18.14/drivers/media/platform/bcm2835/mmal-vchiq.h linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h
---- linux-3.18.14/drivers/media/platform/bcm2835/mmal-vchiq.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h 2015-05-31 14:46:10.937660979 -0500
-@@ -0,0 +1,178 @@
-+/*
-+ * Broadcom BM2835 V4L2 driver
-+ *
-+ * Copyright © 2013 Raspberry Pi (Trading) Ltd.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-+ * Dave Stevenson <dsteve@broadcom.com>
-+ * Simon Mellor <simellor@broadcom.com>
-+ * Luke Diamand <luked@broadcom.com>
-+ *
-+ * MMAL interface to VCHIQ message passing
-+ */
-+
-+#ifndef MMAL_VCHIQ_H
-+#define MMAL_VCHIQ_H
-+
-+#include "mmal-msg-format.h"
-+
-+#define MAX_PORT_COUNT 4
-+
-+/* Maximum size of the format extradata. */
-+#define MMAL_FORMAT_EXTRADATA_MAX_SIZE 128
-+
-+struct vchiq_mmal_instance;
-+
-+enum vchiq_mmal_es_type {
-+ MMAL_ES_TYPE_UNKNOWN, /**< Unknown elementary stream type */
-+ MMAL_ES_TYPE_CONTROL, /**< Elementary stream of control commands */
-+ MMAL_ES_TYPE_AUDIO, /**< Audio elementary stream */
-+ MMAL_ES_TYPE_VIDEO, /**< Video elementary stream */
-+ MMAL_ES_TYPE_SUBPICTURE /**< Sub-picture elementary stream */
-+};
-+
-+/* rectangle, used lots so it gets its own struct */
-+struct vchiq_mmal_rect {
-+ s32 x;
-+ s32 y;
-+ s32 width;
-+ s32 height;
-+};
-+
-+struct vchiq_mmal_port_buffer {
-+ unsigned int num; /* number of buffers */
-+ u32 size; /* size of buffers */
-+ u32 alignment; /* alignment of buffers */
-+};
-+
-+struct vchiq_mmal_port;
-+
-+typedef void (*vchiq_mmal_buffer_cb)(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ int status, struct mmal_buffer *buffer,
-+ unsigned long length, u32 mmal_flags, s64 dts, s64 pts);
-+
-+struct vchiq_mmal_port {
-+ bool enabled;
-+ u32 handle;
-+ u32 type; /* port type, cached to use on port info set */
-+ u32 index; /* port index, cached to use on port info set */
-+
-+ /* component port belongs to, allows simple deref */
-+ struct vchiq_mmal_component *component;
-+
-+ struct vchiq_mmal_port *connected; /* port conencted to */
-+
-+ /* buffer info */
-+ struct vchiq_mmal_port_buffer minimum_buffer;
-+ struct vchiq_mmal_port_buffer recommended_buffer;
-+ struct vchiq_mmal_port_buffer current_buffer;
-+
-+ /* stream format */
-+ struct mmal_es_format format;
-+ /* elementry stream format */
-+ union mmal_es_specific_format es;
-+
-+ /* data buffers to fill */
-+ struct list_head buffers;
-+ /* lock to serialise adding and removing buffers from list */
-+ spinlock_t slock;
-+ /* count of how many buffer header refils have failed because
-+ * there was no buffer to satisfy them
-+ */
-+ int buffer_underflow;
-+ /* callback on buffer completion */
-+ vchiq_mmal_buffer_cb buffer_cb;
-+ /* callback context */
-+ void *cb_ctx;
-+};
-+
-+struct vchiq_mmal_component {
-+ bool enabled;
-+ u32 handle; /* VideoCore handle for component */
-+ u32 inputs; /* Number of input ports */
-+ u32 outputs; /* Number of output ports */
-+ u32 clocks; /* Number of clock ports */
-+ struct vchiq_mmal_port control; /* control port */
-+ struct vchiq_mmal_port input[MAX_PORT_COUNT]; /* input ports */
-+ struct vchiq_mmal_port output[MAX_PORT_COUNT]; /* output ports */
-+ struct vchiq_mmal_port clock[MAX_PORT_COUNT]; /* clock ports */
-+};
-+
-+
-+int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance);
-+int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance);
-+
-+/* Initialise a mmal component and its ports
-+*
-+*/
-+int vchiq_mmal_component_init(
-+ struct vchiq_mmal_instance *instance,
-+ const char *name,
-+ struct vchiq_mmal_component **component_out);
-+
-+int vchiq_mmal_component_finalise(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component);
-+
-+int vchiq_mmal_component_enable(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component);
-+
-+int vchiq_mmal_component_disable(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_component *component);
-+
-+
-+
-+/* enable a mmal port
-+ *
-+ * enables a port and if a buffer callback provided enque buffer
-+ * headers as apropriate for the port.
-+ */
-+int vchiq_mmal_port_enable(
-+ struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ vchiq_mmal_buffer_cb buffer_cb);
-+
-+/* disable a port
-+ *
-+ * disable a port will dequeue any pending buffers
-+ */
-+int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port);
-+
-+
-+int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter,
-+ void *value,
-+ u32 value_size);
-+
-+int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ u32 parameter,
-+ void *value,
-+ u32 *value_size);
-+
-+int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port);
-+
-+int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *src,
-+ struct vchiq_mmal_port *dst);
-+
-+int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
-+ u32 *major_out,
-+ u32 *minor_out);
-+
-+int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance,
-+ struct vchiq_mmal_port *port,
-+ struct mmal_buffer *buf);
-+
-+#endif /* MMAL_VCHIQ_H */
-diff -Nur linux-3.18.14/drivers/media/platform/Kconfig linux-rpi/drivers/media/platform/Kconfig
---- linux-3.18.14/drivers/media/platform/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/media/platform/Kconfig 2015-05-31 14:46:10.937660979 -0500
-@@ -124,6 +124,7 @@
- source "drivers/media/platform/soc_camera/Kconfig"
- source "drivers/media/platform/exynos4-is/Kconfig"
- source "drivers/media/platform/s5p-tv/Kconfig"
-+source "drivers/media/platform/bcm2835/Kconfig"
-
- endif # V4L_PLATFORM_DRIVERS
-
-diff -Nur linux-3.18.14/drivers/media/platform/Makefile linux-rpi/drivers/media/platform/Makefile
---- linux-3.18.14/drivers/media/platform/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/media/platform/Makefile 2015-05-31 14:46:10.937660979 -0500
-@@ -49,4 +49,6 @@
-
- obj-y += omap/
-
-+obj-$(CONFIG_VIDEO_BCM2835) += bcm2835/
-+
- ccflags-y += -I$(srctree)/drivers/media/i2c
-diff -Nur linux-3.18.14/drivers/media/usb/dvb-usb-v2/rtl28xxu.c linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
---- linux-3.18.14/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-05-31 14:46:11.029660978 -0500
-@@ -1531,6 +1531,10 @@
- &rtl2832u_props, "Compro VideoMate U620F", NULL) },
- { DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394,
- &rtl2832u_props, "MaxMedia HU394-T", NULL) },
-+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/,
-+ &rtl2832u_props, "August DVB-T 205", NULL) },
-+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/,
-+ &rtl2832u_props, "August DVB-T 205", NULL) },
- { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03,
- &rtl2832u_props, "Leadtek WinFast DTV Dongle mini", NULL) },
- { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A,
-diff -Nur linux-3.18.14/drivers/misc/Kconfig linux-rpi/drivers/misc/Kconfig
---- linux-3.18.14/drivers/misc/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/misc/Kconfig 2015-05-31 14:46:11.133660977 -0500
-@@ -524,6 +524,7 @@
- source "drivers/misc/altera-stapl/Kconfig"
- source "drivers/misc/mei/Kconfig"
- source "drivers/misc/vmw_vmci/Kconfig"
-+source "drivers/misc/vc04_services/Kconfig"
- source "drivers/misc/mic/Kconfig"
- source "drivers/misc/genwqe/Kconfig"
- source "drivers/misc/echo/Kconfig"
-diff -Nur linux-3.18.14/drivers/misc/Makefile linux-rpi/drivers/misc/Makefile
---- linux-3.18.14/drivers/misc/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/misc/Makefile 2015-05-31 14:46:11.133660977 -0500
-@@ -51,6 +51,7 @@
- obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/
- obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o
- obj-$(CONFIG_SRAM) += sram.o
-+obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/
- obj-y += mic/
- obj-$(CONFIG_GENWQE) += genwqe/
- obj-$(CONFIG_ECHO) += echo/
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/connections/connection.h linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/connections/connection.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,328 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef CONNECTION_H_
-+#define CONNECTION_H_
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/semaphore.h>
-+
-+#include "interface/vchi/vchi_cfg_internal.h"
-+#include "interface/vchi/vchi_common.h"
-+#include "interface/vchi/message_drivers/message.h"
-+
-+/******************************************************************************
-+ Global defs
-+ *****************************************************************************/
-+
-+// Opaque handle for a connection / service pair
-+typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T;
-+
-+// opaque handle to the connection state information
-+typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T;
-+
-+typedef struct vchi_connection_t VCHI_CONNECTION_T;
-+
-+
-+/******************************************************************************
-+ API
-+ *****************************************************************************/
-+
-+// Routine to init a connection with a particular low level driver
-+typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection,
-+ const VCHI_MESSAGE_DRIVER_T * driver );
-+
-+// Routine to control CRC enabling at a connection level
-+typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle,
-+ VCHI_CRC_CONTROL_T control );
-+
-+// Routine to create a service
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle,
-+ int32_t service_id,
-+ uint32_t rx_fifo_size,
-+ uint32_t tx_fifo_size,
-+ int server,
-+ VCHI_CALLBACK_T callback,
-+ void *callback_param,
-+ int32_t want_crc,
-+ int32_t want_unaligned_bulk_rx,
-+ int32_t want_unaligned_bulk_tx,
-+ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle );
-+
-+// Routine to close a service
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle );
-+
-+// Routine to queue a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ const void *data,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// scatter-gather (vector) message queueing
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ VCHI_MSG_VECTOR_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// Routine to dequeue a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *data,
-+ uint32_t max_data_size_to_read,
-+ uint32_t *actual_msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to peek at a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to hold a message
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags,
-+ void **message_handle );
-+
-+// Routine to initialise a received message iterator
-+typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ VCHI_MSG_ITER_T *iter,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to release a held message
-+typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *message_handle );
-+
-+// Routine to get info on a held message
-+typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *message_handle,
-+ void **data,
-+ int32_t *msg_size,
-+ uint32_t *tx_timestamp,
-+ uint32_t *rx_timestamp );
-+
-+// Routine to check whether the iterator has a next message
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ const VCHI_MSG_ITER_T *iter );
-+
-+// Routine to advance the iterator
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ VCHI_MSG_ITER_T *iter,
-+ void **data,
-+ uint32_t *msg_size );
-+
-+// Routine to remove the last message returned by the iterator
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ VCHI_MSG_ITER_T *iter );
-+
-+// Routine to hold the last message returned by the iterator
-+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service,
-+ VCHI_MSG_ITER_T *iter,
-+ void **msg_handle );
-+
-+// Routine to transmit bulk data
-+typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ const void *data_src,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle );
-+
-+// Routine to receive data
-+typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle,
-+ void *data_dst,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle );
-+
-+// Routine to report if a server is available
-+typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags );
-+
-+// Routine to report the number of RX slots available
-+typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state );
-+
-+// Routine to report the RX slot size
-+typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state );
-+
-+// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO
-+typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state,
-+ int32_t service,
-+ uint32_t length,
-+ MESSAGE_TX_CHANNEL_T channel,
-+ uint32_t channel_params,
-+ uint32_t data_length,
-+ uint32_t data_offset);
-+
-+// Callback to inform a service that a Xon or Xoff message has been received
-+typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff);
-+
-+// Callback to inform a service that a server available reply message has been received
-+typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags);
-+
-+// Callback to indicate that bulk auxiliary messages have arrived
-+typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state);
-+
-+// Callback to indicate that bulk auxiliary messages have arrived
-+typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle);
-+
-+// Callback with all the connection info you require
-+typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size);
-+
-+// Callback to inform of a disconnect
-+typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags);
-+
-+// Callback to inform of a power control request
-+typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable);
-+
-+// allocate memory suitably aligned for this connection
-+typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length);
-+
-+// free memory allocated by buffer_allocate
-+typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address);
-+
-+
-+/******************************************************************************
-+ System driver struct
-+ *****************************************************************************/
-+
-+struct opaque_vchi_connection_api_t
-+{
-+ // Routine to init the connection
-+ VCHI_CONNECTION_INIT_T init;
-+
-+ // Connection-level CRC control
-+ VCHI_CONNECTION_CRC_CONTROL_T crc_control;
-+
-+ // Routine to connect to or create service
-+ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect;
-+
-+ // Routine to disconnect from a service
-+ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect;
-+
-+ // Routine to queue a message
-+ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg;
-+
-+ // scatter-gather (vector) message queue
-+ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv;
-+
-+ // Routine to dequeue a message
-+ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg;
-+
-+ // Routine to peek at a message
-+ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg;
-+
-+ // Routine to hold a message
-+ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg;
-+
-+ // Routine to initialise a received message iterator
-+ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg;
-+
-+ // Routine to release a message
-+ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release;
-+
-+ // Routine to get information on a held message
-+ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info;
-+
-+ // Routine to check for next message on iterator
-+ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next;
-+
-+ // Routine to get next message on iterator
-+ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next;
-+
-+ // Routine to remove the last message returned by iterator
-+ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove;
-+
-+ // Routine to hold the last message returned by iterator
-+ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold;
-+
-+ // Routine to transmit bulk data
-+ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit;
-+
-+ // Routine to receive data
-+ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive;
-+
-+ // Routine to report the available servers
-+ VCHI_CONNECTION_SERVER_PRESENT server_present;
-+
-+ // Routine to report the number of RX slots available
-+ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available;
-+
-+ // Routine to report the RX slot size
-+ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size;
-+
-+ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO
-+ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added;
-+
-+ // Callback to inform a service that a Xon or Xoff message has been received
-+ VCHI_CONNECTION_FLOW_CONTROL flow_control;
-+
-+ // Callback to inform a service that a server available reply message has been received
-+ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply;
-+
-+ // Callback to indicate that bulk auxiliary messages have arrived
-+ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received;
-+
-+ // Callback to indicate that a bulk auxiliary message has been transmitted
-+ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted;
-+
-+ // Callback to provide information about the connection
-+ VCHI_CONNECTION_INFO connection_info;
-+
-+ // Callback to notify that peer has requested disconnect
-+ VCHI_CONNECTION_DISCONNECT disconnect;
-+
-+ // Callback to notify that peer has requested power change
-+ VCHI_CONNECTION_POWER_CONTROL power_control;
-+
-+ // allocate memory suitably aligned for this connection
-+ VCHI_BUFFER_ALLOCATE buffer_allocate;
-+
-+ // free memory allocated by buffer_allocate
-+ VCHI_BUFFER_FREE buffer_free;
-+
-+};
-+
-+struct vchi_connection_t {
-+ const VCHI_CONNECTION_API_T *api;
-+ VCHI_CONNECTION_STATE_T *state;
-+#ifdef VCHI_COARSE_LOCKING
-+ struct semaphore sem;
-+#endif
-+};
-+
-+
-+#endif /* CONNECTION_H_ */
-+
-+/****************************** End of file **********************************/
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,204 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef _VCHI_MESSAGE_H_
-+#define _VCHI_MESSAGE_H_
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/semaphore.h>
-+
-+#include "interface/vchi/vchi_cfg_internal.h"
-+#include "interface/vchi/vchi_common.h"
-+
-+
-+typedef enum message_event_type {
-+ MESSAGE_EVENT_NONE,
-+ MESSAGE_EVENT_NOP,
-+ MESSAGE_EVENT_MESSAGE,
-+ MESSAGE_EVENT_SLOT_COMPLETE,
-+ MESSAGE_EVENT_RX_BULK_PAUSED,
-+ MESSAGE_EVENT_RX_BULK_COMPLETE,
-+ MESSAGE_EVENT_TX_COMPLETE,
-+ MESSAGE_EVENT_MSG_DISCARDED
-+} MESSAGE_EVENT_TYPE_T;
-+
-+typedef enum vchi_msg_flags
-+{
-+ VCHI_MSG_FLAGS_NONE = 0x0,
-+ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1
-+} VCHI_MSG_FLAGS_T;
-+
-+typedef enum message_tx_channel
-+{
-+ MESSAGE_TX_CHANNEL_MESSAGE = 0,
-+ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards
-+} MESSAGE_TX_CHANNEL_T;
-+
-+// Macros used for cycling through bulk channels
-+#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION)
-+#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION)
-+
-+typedef enum message_rx_channel
-+{
-+ MESSAGE_RX_CHANNEL_MESSAGE = 0,
-+ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards
-+} MESSAGE_RX_CHANNEL_T;
-+
-+// Message receive slot information
-+typedef struct rx_msg_slot_info {
-+
-+ struct rx_msg_slot_info *next;
-+ //struct slot_info *prev;
-+#if !defined VCHI_COARSE_LOCKING
-+ struct semaphore sem;
-+#endif
-+
-+ uint8_t *addr; // base address of slot
-+ uint32_t len; // length of slot in bytes
-+
-+ uint32_t write_ptr; // hardware causes this to advance
-+ uint32_t read_ptr; // this module does the reading
-+ int active; // is this slot in the hardware dma fifo?
-+ uint32_t msgs_parsed; // count how many messages are in this slot
-+ uint32_t msgs_released; // how many messages have been released
-+ void *state; // connection state information
-+ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services
-+} RX_MSG_SLOTINFO_T;
-+
-+// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out.
-+// In particular, it mustn't use addr and len - they're the client buffer, but the message
-+// driver will be tasked with sending the aligned core section.
-+typedef struct rx_bulk_slotinfo_t {
-+ struct rx_bulk_slotinfo_t *next;
-+
-+ struct semaphore *blocking;
-+
-+ // needed by DMA
-+ void *addr;
-+ uint32_t len;
-+
-+ // needed for the callback
-+ void *service;
-+ void *handle;
-+ VCHI_FLAGS_T flags;
-+} RX_BULK_SLOTINFO_T;
-+
-+
-+/* ----------------------------------------------------------------------
-+ * each connection driver will have a pool of the following struct.
-+ *
-+ * the pool will be managed by vchi_qman_*
-+ * this means there will be multiple queues (single linked lists)
-+ * a given struct message_info will be on exactly one of these queues
-+ * at any one time
-+ * -------------------------------------------------------------------- */
-+typedef struct rx_message_info {
-+
-+ struct message_info *next;
-+ //struct message_info *prev;
-+
-+ uint8_t *addr;
-+ uint32_t len;
-+ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message
-+ uint32_t tx_timestamp;
-+ uint32_t rx_timestamp;
-+
-+} RX_MESSAGE_INFO_T;
-+
-+typedef struct {
-+ MESSAGE_EVENT_TYPE_T type;
-+
-+ struct {
-+ // for messages
-+ void *addr; // address of message
-+ uint16_t slot_delta; // whether this message indicated slot delta
-+ uint32_t len; // length of message
-+ RX_MSG_SLOTINFO_T *slot; // slot this message is in
-+ int32_t service; // service id this message is destined for
-+ uint32_t tx_timestamp; // timestamp from the header
-+ uint32_t rx_timestamp; // timestamp when we parsed it
-+ } message;
-+
-+ // FIXME: cleanup slot reporting...
-+ RX_MSG_SLOTINFO_T *rx_msg;
-+ RX_BULK_SLOTINFO_T *rx_bulk;
-+ void *tx_handle;
-+ MESSAGE_TX_CHANNEL_T tx_channel;
-+
-+} MESSAGE_EVENT_T;
-+
-+
-+// callbacks
-+typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state );
-+
-+typedef struct {
-+ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback;
-+} VCHI_MESSAGE_DRIVER_OPEN_T;
-+
-+
-+// handle to this instance of message driver (as returned by ->open)
-+typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T;
-+
-+struct opaque_vchi_message_driver_t {
-+ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state );
-+ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle );
-+ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle );
-+ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable );
-+ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message
-+ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk)
-+ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk)
-+ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver
-+ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle );
-+ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void
-+ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial );
-+
-+ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count );
-+ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length );
-+ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length );
-+ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address );
-+ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size );
-+ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size );
-+
-+ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
-+ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
-+ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel );
-+ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel );
-+ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len );
-+ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle );
-+};
-+
-+
-+#endif // _VCHI_MESSAGE_H_
-+
-+/****************************** End of file ***********************************/
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,224 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_CFG_H_
-+#define VCHI_CFG_H_
-+
-+/****************************************************************************************
-+ * Defines in this first section are part of the VCHI API and may be examined by VCHI
-+ * services.
-+ ***************************************************************************************/
-+
-+/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */
-+/* Really determined by the message driver, and should be available from a run-time call. */
-+#ifndef VCHI_BULK_ALIGN
-+# if __VCCOREVER__ >= 0x04000000
-+# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans
-+# else
-+# define VCHI_BULK_ALIGN 16
-+# endif
-+#endif
-+
-+/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */
-+/* May be less than or greater than VCHI_BULK_ALIGN */
-+/* Really determined by the message driver, and should be available from a run-time call. */
-+#ifndef VCHI_BULK_GRANULARITY
-+# if __VCCOREVER__ >= 0x04000000
-+# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans
-+# else
-+# define VCHI_BULK_GRANULARITY 16
-+# endif
-+#endif
-+
-+/* The largest possible message to be queued with vchi_msg_queue. */
-+#ifndef VCHI_MAX_MSG_SIZE
-+# if defined VCHI_LOCAL_HOST_PORT
-+# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk?
-+# else
-+# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!!
-+# endif
-+#endif
-+
-+/******************************************************************************************
-+ * Defines below are system configuration options, and should not be used by VCHI services.
-+ *****************************************************************************************/
-+
-+/* How many connections can we support? A localhost implementation uses 2 connections,
-+ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW
-+ * driver. */
-+#ifndef VCHI_MAX_NUM_CONNECTIONS
-+# define VCHI_MAX_NUM_CONNECTIONS 3
-+#endif
-+
-+/* How many services can we open per connection? Extending this doesn't cost processing time, just a small
-+ * amount of static memory. */
-+#ifndef VCHI_MAX_SERVICES_PER_CONNECTION
-+# define VCHI_MAX_SERVICES_PER_CONNECTION 36
-+#endif
-+
-+/* Adjust if using a message driver that supports more logical TX channels */
-+#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION
-+# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels
-+#endif
-+
-+/* Adjust if using a message driver that supports more logical RX channels */
-+#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION
-+# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI
-+#endif
-+
-+/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective
-+ * receive queue space, less message headers. */
-+#ifndef VCHI_NUM_READ_SLOTS
-+# if defined(VCHI_LOCAL_HOST_PORT)
-+# define VCHI_NUM_READ_SLOTS 4
-+# else
-+# define VCHI_NUM_READ_SLOTS 48
-+# endif
-+#endif
-+
-+/* Do we utilise overrun facility for receive message slots? Can aid peer transmit
-+ * performance. Only define on VideoCore end, talking to host.
-+ */
-+//#define VCHI_MSG_RX_OVERRUN
-+
-+/* How many transmit slots do we use. Generally don't need many, as the hardware driver
-+ * underneath VCHI will usually have its own buffering. */
-+#ifndef VCHI_NUM_WRITE_SLOTS
-+# define VCHI_NUM_WRITE_SLOTS 4
-+#endif
-+
-+/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots,
-+ * then it's taking up too much buffer space, and the peer service will be told to stop
-+ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS
-+ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency
-+ * is too high. */
-+#ifndef VCHI_XOFF_THRESHOLD
-+# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2)
-+#endif
-+
-+/* After we've sent an XOFF, the peer will be told to resume transmission once the local
-+ * service has dequeued/released enough messages that it's now occupying
-+ * VCHI_XON_THRESHOLD slots or fewer. */
-+#ifndef VCHI_XON_THRESHOLD
-+# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4)
-+#endif
-+
-+/* A size below which a bulk transfer omits the handshake completely and always goes
-+ * via the message channel, if bulk auxiliary is being sent on that service. (The user
-+ * can guarantee this by enabling unaligned transmits).
-+ * Not API. */
-+#ifndef VCHI_MIN_BULK_SIZE
-+# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 )
-+#endif
-+
-+/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between
-+ * speed and latency; the smaller the chunk size the better change of messages and other
-+ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not
-+ * break transmissions into chunks.
-+ */
-+#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI
-+# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024)
-+#endif
-+
-+/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode
-+ * with multiple-line frames. Only use if the receiver can cope. */
-+#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2
-+# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0
-+#endif
-+
-+/* How many TX messages can we have pending in our transmit slots. Once exhausted,
-+ * vchi_msg_queue will be blocked. */
-+#ifndef VCHI_TX_MSG_QUEUE_SIZE
-+# define VCHI_TX_MSG_QUEUE_SIZE 256
-+#endif
-+
-+/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing
-+ * will be suspended until older messages are dequeued/released. */
-+#ifndef VCHI_RX_MSG_QUEUE_SIZE
-+# define VCHI_RX_MSG_QUEUE_SIZE 256
-+#endif
-+
-+/* Really should be able to cope if we run out of received message descriptors, by
-+ * suspending parsing as the comment above says, but we don't. This sweeps the issue
-+ * under the carpet. */
-+#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS
-+# undef VCHI_RX_MSG_QUEUE_SIZE
-+# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS
-+#endif
-+
-+/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit
-+ * will be blocked. */
-+#ifndef VCHI_TX_BULK_QUEUE_SIZE
-+# define VCHI_TX_BULK_QUEUE_SIZE 64
-+#endif
-+
-+/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive
-+ * will be blocked. */
-+#ifndef VCHI_RX_BULK_QUEUE_SIZE
-+# define VCHI_RX_BULK_QUEUE_SIZE 64
-+#endif
-+
-+/* A limit on how many outstanding bulk requests we expect the peer to give us. If
-+ * the peer asks for more than this, VCHI will fail and assert. The number is determined
-+ * by the peer's hardware - it's the number of outstanding requests that can be queued
-+ * on all bulk channels. VC3's MPHI peripheral allows 16. */
-+#ifndef VCHI_MAX_PEER_BULK_REQUESTS
-+# define VCHI_MAX_PEER_BULK_REQUESTS 32
-+#endif
-+
-+/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2
-+ * transmitter on and off.
-+ */
-+/*#define VCHI_CCP2TX_MANUAL_POWER*/
-+
-+#ifndef VCHI_CCP2TX_MANUAL_POWER
-+
-+/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set
-+ * negative for no IDLE.
-+ */
-+# ifndef VCHI_CCP2TX_IDLE_TIMEOUT
-+# define VCHI_CCP2TX_IDLE_TIMEOUT 5
-+# endif
-+
-+/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set
-+ * negative for no OFF.
-+ */
-+# ifndef VCHI_CCP2TX_OFF_TIMEOUT
-+# define VCHI_CCP2TX_OFF_TIMEOUT 1000
-+# endif
-+
-+#endif /* VCHI_CCP2TX_MANUAL_POWER */
-+
-+#endif /* VCHI_CFG_H_ */
-+
-+/****************************** End of file **********************************/
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,71 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_CFG_INTERNAL_H_
-+#define VCHI_CFG_INTERNAL_H_
-+
-+/****************************************************************************************
-+ * Control optimisation attempts.
-+ ***************************************************************************************/
-+
-+// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second
-+#define VCHI_COARSE_LOCKING
-+
-+// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx)
-+// (only relevant if VCHI_COARSE_LOCKING)
-+#define VCHI_ELIDE_BLOCK_EXIT_LOCK
-+
-+// Avoid lock on non-blocking peek
-+// (only relevant if VCHI_COARSE_LOCKING)
-+#define VCHI_AVOID_PEEK_LOCK
-+
-+// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation.
-+#define VCHI_MULTIPLE_HANDLER_THREADS
-+
-+// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash
-+// our way through the pool of descriptors.
-+#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD
-+
-+// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING.
-+#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS
-+
-+// Don't use message descriptors for TX messages that don't need them
-+#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS
-+
-+// Nano-locks for multiqueue
-+//#define VCHI_MQUEUE_NANOLOCKS
-+
-+// Lock-free(er) dequeuing
-+//#define VCHI_RX_NANOLOCKS
-+
-+#endif /*VCHI_CFG_INTERNAL_H_*/
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_common.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_common.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,175 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_COMMON_H_
-+#define VCHI_COMMON_H_
-+
-+
-+//flags used when sending messages (must be bitmapped)
-+typedef enum
-+{
-+ VCHI_FLAGS_NONE = 0x0,
-+ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side)
-+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go
-+ VCHI_FLAGS_ALLOW_PARTIAL = 0x8,
-+ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10,
-+ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20,
-+
-+ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only
-+ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only
-+ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only
-+ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only
-+ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only
-+ VCHI_FLAGS_INTERNAL = 0xFF0000
-+} VCHI_FLAGS_T;
-+
-+// constants for vchi_crc_control()
-+typedef enum {
-+ VCHI_CRC_NOTHING = -1,
-+ VCHI_CRC_PER_SERVICE = 0,
-+ VCHI_CRC_EVERYTHING = 1,
-+} VCHI_CRC_CONTROL_T;
-+
-+//callback reasons when an event occurs on a service
-+typedef enum
-+{
-+ VCHI_CALLBACK_REASON_MIN,
-+
-+ //This indicates that there is data available
-+ //handle is the msg id that was transmitted with the data
-+ // When a message is received and there was no FULL message available previously, send callback
-+ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails
-+ VCHI_CALLBACK_MSG_AVAILABLE,
-+ VCHI_CALLBACK_MSG_SENT,
-+ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented
-+
-+ // This indicates that a transfer from the other side has completed
-+ VCHI_CALLBACK_BULK_RECEIVED,
-+ //This indicates that data queued up to be sent has now gone
-+ //handle is the msg id that was used when sending the data
-+ VCHI_CALLBACK_BULK_SENT,
-+ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented
-+ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented
-+
-+ VCHI_CALLBACK_SERVICE_CLOSED,
-+
-+ // this side has sent XOFF to peer due to lack of data consumption by service
-+ // (suggests the service may need to take some recovery action if it has
-+ // been deliberately holding off consuming data)
-+ VCHI_CALLBACK_SENT_XOFF,
-+ VCHI_CALLBACK_SENT_XON,
-+
-+ // indicates that a bulk transfer has finished reading the source buffer
-+ VCHI_CALLBACK_BULK_DATA_READ,
-+
-+ // power notification events (currently host side only)
-+ VCHI_CALLBACK_PEER_OFF,
-+ VCHI_CALLBACK_PEER_SUSPENDED,
-+ VCHI_CALLBACK_PEER_ON,
-+ VCHI_CALLBACK_PEER_RESUMED,
-+ VCHI_CALLBACK_FORCED_POWER_OFF,
-+
-+#ifdef USE_VCHIQ_ARM
-+ // some extra notifications provided by vchiq_arm
-+ VCHI_CALLBACK_SERVICE_OPENED,
-+ VCHI_CALLBACK_BULK_RECEIVE_ABORTED,
-+ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED,
-+#endif
-+
-+ VCHI_CALLBACK_REASON_MAX
-+} VCHI_CALLBACK_REASON_T;
-+
-+// service control options
-+typedef enum
-+{
-+ VCHI_SERVICE_OPTION_MIN,
-+
-+ VCHI_SERVICE_OPTION_TRACE,
-+ VCHI_SERVICE_OPTION_SYNCHRONOUS,
-+
-+ VCHI_SERVICE_OPTION_MAX
-+} VCHI_SERVICE_OPTION_T;
-+
-+
-+//Callback used by all services / bulk transfers
-+typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param
-+ VCHI_CALLBACK_REASON_T reason,
-+ void *handle ); //for transmitting msg's only
-+
-+
-+
-+/*
-+ * Define vector struct for scatter-gather (vector) operations
-+ * Vectors can be nested - if a vector element has negative length, then
-+ * the data pointer is treated as pointing to another vector array, with
-+ * '-vec_len' elements. Thus to append a header onto an existing vector,
-+ * you can do this:
-+ *
-+ * void foo(const VCHI_MSG_VECTOR_T *v, int n)
-+ * {
-+ * VCHI_MSG_VECTOR_T nv[2];
-+ * nv[0].vec_base = my_header;
-+ * nv[0].vec_len = sizeof my_header;
-+ * nv[1].vec_base = v;
-+ * nv[1].vec_len = -n;
-+ * ...
-+ *
-+ */
-+typedef struct vchi_msg_vector {
-+ const void *vec_base;
-+ int32_t vec_len;
-+} VCHI_MSG_VECTOR_T;
-+
-+// Opaque type for a connection API
-+typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T;
-+
-+// Opaque type for a message driver
-+typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T;
-+
-+
-+// Iterator structure for reading ahead through received message queue. Allocated by client,
-+// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only.
-+// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead -
-+// will not proceed to messages received since. Behaviour is undefined if an iterator
-+// is used again after messages for that service are removed/dequeued by any
-+// means other than vchi_msg_iter_... calls on the iterator itself.
-+typedef struct {
-+ struct opaque_vchi_service_t *service;
-+ void *last;
-+ void *next;
-+ void *remove;
-+} VCHI_MSG_ITER_T;
-+
-+
-+#endif // VCHI_COMMON_H_
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,378 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_H_
-+#define VCHI_H_
-+
-+#include "interface/vchi/vchi_cfg.h"
-+#include "interface/vchi/vchi_common.h"
-+#include "interface/vchi/connections/connection.h"
-+#include "vchi_mh.h"
-+
-+
-+/******************************************************************************
-+ Global defs
-+ *****************************************************************************/
-+
-+#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1))
-+#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1))
-+#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1))))
-+
-+#ifdef USE_VCHIQ_ARM
-+#define VCHI_BULK_ALIGNED(x) 1
-+#else
-+#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0)
-+#endif
-+
-+struct vchi_version {
-+ uint32_t version;
-+ uint32_t version_min;
-+};
-+#define VCHI_VERSION(v_) { v_, v_ }
-+#define VCHI_VERSION_EX(v_, m_) { v_, m_ }
-+
-+typedef enum
-+{
-+ VCHI_VEC_POINTER,
-+ VCHI_VEC_HANDLE,
-+ VCHI_VEC_LIST
-+} VCHI_MSG_VECTOR_TYPE_T;
-+
-+typedef struct vchi_msg_vector_ex {
-+
-+ VCHI_MSG_VECTOR_TYPE_T type;
-+ union
-+ {
-+ // a memory handle
-+ struct
-+ {
-+ VCHI_MEM_HANDLE_T handle;
-+ uint32_t offset;
-+ int32_t vec_len;
-+ } handle;
-+
-+ // an ordinary data pointer
-+ struct
-+ {
-+ const void *vec_base;
-+ int32_t vec_len;
-+ } ptr;
-+
-+ // a nested vector list
-+ struct
-+ {
-+ struct vchi_msg_vector_ex *vec;
-+ uint32_t vec_len;
-+ } list;
-+ } u;
-+} VCHI_MSG_VECTOR_EX_T;
-+
-+
-+// Construct an entry in a msg vector for a pointer (p) of length (l)
-+#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } }
-+
-+// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l)
-+#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } }
-+
-+// Macros to manipulate 'FOURCC' values
-+#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] ))
-+#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF
-+
-+
-+// Opaque service information
-+struct opaque_vchi_service_t;
-+
-+// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold,
-+// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only.
-+typedef struct
-+{
-+ struct opaque_vchi_service_t *service;
-+ void *message;
-+} VCHI_HELD_MSG_T;
-+
-+
-+
-+// structure used to provide the information needed to open a server or a client
-+typedef struct {
-+ struct vchi_version version;
-+ int32_t service_id;
-+ VCHI_CONNECTION_T *connection;
-+ uint32_t rx_fifo_size;
-+ uint32_t tx_fifo_size;
-+ VCHI_CALLBACK_T callback;
-+ void *callback_param;
-+ /* client intends to receive bulk transfers of
-+ odd lengths or into unaligned buffers */
-+ int32_t want_unaligned_bulk_rx;
-+ /* client intends to transmit bulk transfers of
-+ odd lengths or out of unaligned buffers */
-+ int32_t want_unaligned_bulk_tx;
-+ /* client wants to check CRCs on (bulk) xfers.
-+ Only needs to be set at 1 end - will do both directions. */
-+ int32_t want_crc;
-+} SERVICE_CREATION_T;
-+
-+// Opaque handle for a VCHI instance
-+typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T;
-+
-+// Opaque handle for a server or client
-+typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T;
-+
-+// Service registration & startup
-+typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections);
-+
-+typedef struct service_info_tag {
-+ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */
-+ VCHI_SERVICE_INIT init; /* Service initialisation function */
-+ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */
-+} SERVICE_INFO_T;
-+
-+/******************************************************************************
-+ Global funcs - implementation is specific to which side you are on (local / remote)
-+ *****************************************************************************/
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table,
-+ const VCHI_MESSAGE_DRIVER_T * low_level);
-+
-+
-+// Routine used to initialise the vchi on both local + remote connections
-+extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle );
-+
-+extern int32_t vchi_exit( void );
-+
-+extern int32_t vchi_connect( VCHI_CONNECTION_T **connections,
-+ const uint32_t num_connections,
-+ VCHI_INSTANCE_T instance_handle );
-+
-+//When this is called, ensure that all services have no data pending.
-+//Bulk transfers can remain 'queued'
-+extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle );
-+
-+// Global control over bulk CRC checking
-+extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection,
-+ VCHI_CRC_CONTROL_T control );
-+
-+// helper functions
-+extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length);
-+extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address);
-+extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle);
-+
-+
-+/******************************************************************************
-+ Global service API
-+ *****************************************************************************/
-+// Routine to create a named service
-+extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle );
-+
-+// Routine to destory a service
-+extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to open a named service
-+extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle);
-+
-+extern int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle,
-+ short *peer_version );
-+
-+// Routine to close a named service
-+extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to increment ref count on a named service
-+extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to decrement ref count on a named service
-+extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to set a control option for a named service
-+extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_SERVICE_OPTION_T option,
-+ int value);
-+
-+// Routine to send a message across a service
-+extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle,
-+ const void *data,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// scatter-gather (vector) and send message
-+int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_VECTOR_EX_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// legacy scatter-gather (vector) and send message, only handles pointers
-+int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_VECTOR_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle );
-+
-+// Routine to receive a msg from a service
-+// Dequeue is equivalent to hold, copy into client buffer, release
-+extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle,
-+ void *data,
-+ uint32_t max_data_size_to_read,
-+ uint32_t *actual_msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to look at a message in place.
-+// The message is not dequeued, so a subsequent call to peek or dequeue
-+// will return the same message.
-+extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags );
-+
-+// Routine to remove a message after it has been read in place with peek
-+// The first message on the queue is dequeued.
-+extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle );
-+
-+// Routine to look at a message in place.
-+// The message is dequeued, so the caller is left holding it; the descriptor is
-+// filled in and must be released when the user has finished with the message.
-+extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle,
-+ void **data, // } may be NULL, as info can be
-+ uint32_t *msg_size, // } obtained from HELD_MSG_T
-+ VCHI_FLAGS_T flags,
-+ VCHI_HELD_MSG_T *message_descriptor );
-+
-+// Initialise an iterator to look through messages in place
-+extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_ITER_T *iter,
-+ VCHI_FLAGS_T flags );
-+
-+/******************************************************************************
-+ Global service support API - operations on held messages and message iterators
-+ *****************************************************************************/
-+
-+// Routine to get the address of a held message
-+extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to get the size of a held message
-+extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to get the transmit timestamp as written into the header by the peer
-+extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to get the reception timestamp, written as we parsed the header
-+extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message );
-+
-+// Routine to release a held message after it has been processed
-+extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message );
-+
-+// Indicates whether the iterator has a next message.
-+extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter );
-+
-+// Return the pointer and length for the next message and advance the iterator.
-+extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter,
-+ void **data,
-+ uint32_t *msg_size );
-+
-+// Remove the last message returned by vchi_msg_iter_next.
-+// Can only be called once after each call to vchi_msg_iter_next.
-+extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter );
-+
-+// Hold the last message returned by vchi_msg_iter_next.
-+// Can only be called once after each call to vchi_msg_iter_next.
-+extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter,
-+ VCHI_HELD_MSG_T *message );
-+
-+// Return information for the next message, and hold it, advancing the iterator.
-+extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter,
-+ void **data, // } may be NULL
-+ uint32_t *msg_size, // }
-+ VCHI_HELD_MSG_T *message );
-+
-+
-+/******************************************************************************
-+ Global bulk API
-+ *****************************************************************************/
-+
-+// Routine to prepare interface for a transfer from the other side
-+extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle,
-+ void *data_dst,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *transfer_handle );
-+
-+
-+// Prepare interface for a transfer from the other side into relocatable memory.
-+int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T h_dst,
-+ uint32_t offset,
-+ uint32_t data_size,
-+ const VCHI_FLAGS_T flags,
-+ void * const bulk_handle );
-+
-+// Routine to queue up data ready for transfer to the other (once they have signalled they are ready)
-+extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle,
-+ const void *data_src,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *transfer_handle );
-+
-+
-+/******************************************************************************
-+ Configuration plumbing
-+ *****************************************************************************/
-+
-+// function prototypes for the different mid layers (the state info gives the different physical connections)
-+extern const VCHI_CONNECTION_API_T *single_get_func_table( void );
-+//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void );
-+//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void );
-+
-+// declare all message drivers here
-+const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void );
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T h_src,
-+ uint32_t offset,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *transfer_handle );
-+#endif /* VCHI_H_ */
-+
-+/****************************** End of file **********************************/
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_mh.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,42 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHI_MH_H_
-+#define VCHI_MH_H_
-+
-+#include <linux/types.h>
-+
-+typedef int32_t VCHI_MEM_HANDLE_T;
-+#define VCHI_MEM_HANDLE_INVALID 0
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,562 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/pagemap.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/version.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <asm/pgtable.h>
-+
-+#include <mach/irqs.h>
-+
-+#include <mach/platform.h>
-+#include <mach/vcio.h>
-+
-+#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32)
-+
-+#define VCHIQ_DOORBELL_IRQ IRQ_ARM_DOORBELL_0
-+#define VCHIQ_ARM_ADDRESS(x) ((void *)__virt_to_bus((unsigned)x))
-+
-+#include "vchiq_arm.h"
-+#include "vchiq_2835.h"
-+#include "vchiq_connected.h"
-+#include "vchiq_killable.h"
-+
-+#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2)
-+
-+typedef struct vchiq_2835_state_struct {
-+ int inited;
-+ VCHIQ_ARM_STATE_T arm_state;
-+} VCHIQ_2835_ARM_STATE_T;
-+
-+static char *g_slot_mem;
-+static int g_slot_mem_size;
-+dma_addr_t g_slot_phys;
-+static FRAGMENTS_T *g_fragments_base;
-+static FRAGMENTS_T *g_free_fragments;
-+struct semaphore g_free_fragments_sema;
-+
-+extern int vchiq_arm_log_level;
-+
-+static DEFINE_SEMAPHORE(g_free_fragments_mutex);
-+
-+static irqreturn_t
-+vchiq_doorbell_irq(int irq, void *dev_id);
-+
-+static int
-+create_pagelist(char __user *buf, size_t count, unsigned short type,
-+ struct task_struct *task, PAGELIST_T ** ppagelist);
-+
-+static void
-+free_pagelist(PAGELIST_T *pagelist, int actual);
-+
-+int __init
-+vchiq_platform_init(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero;
-+ int frag_mem_size;
-+ int err;
-+ int i;
-+
-+ /* Allocate space for the channels in coherent memory */
-+ g_slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE);
-+ frag_mem_size = PAGE_ALIGN(sizeof(FRAGMENTS_T) * MAX_FRAGMENTS);
-+
-+ g_slot_mem = dma_alloc_coherent(NULL, g_slot_mem_size + frag_mem_size,
-+ &g_slot_phys, GFP_KERNEL);
-+
-+ if (!g_slot_mem) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to allocate channel memory");
-+ err = -ENOMEM;
-+ goto failed_alloc;
-+ }
-+
-+ WARN_ON(((int)g_slot_mem & (PAGE_SIZE - 1)) != 0);
-+
-+ vchiq_slot_zero = vchiq_init_slots(g_slot_mem, g_slot_mem_size);
-+ if (!vchiq_slot_zero) {
-+ err = -EINVAL;
-+ goto failed_init_slots;
-+ }
-+
-+ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] =
-+ (int)g_slot_phys + g_slot_mem_size;
-+ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] =
-+ MAX_FRAGMENTS;
-+
-+ g_fragments_base = (FRAGMENTS_T *)(g_slot_mem + g_slot_mem_size);
-+ g_slot_mem_size += frag_mem_size;
-+
-+ g_free_fragments = g_fragments_base;
-+ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) {
-+ *(FRAGMENTS_T **)&g_fragments_base[i] =
-+ &g_fragments_base[i + 1];
-+ }
-+ *(FRAGMENTS_T **)&g_fragments_base[i] = NULL;
-+ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS);
-+
-+ if (vchiq_init_state(state, vchiq_slot_zero, 0/*slave*/) !=
-+ VCHIQ_SUCCESS) {
-+ err = -EINVAL;
-+ goto failed_vchiq_init;
-+ }
-+
-+ err = request_irq(VCHIQ_DOORBELL_IRQ, vchiq_doorbell_irq,
-+ IRQF_IRQPOLL, "VCHIQ doorbell",
-+ state);
-+ if (err < 0) {
-+ vchiq_log_error(vchiq_arm_log_level, "%s: failed to register "
-+ "irq=%d err=%d", __func__,
-+ VCHIQ_DOORBELL_IRQ, err);
-+ goto failed_request_irq;
-+ }
-+
-+ /* Send the base address of the slots to VideoCore */
-+
-+ dsb(); /* Ensure all writes have completed */
-+
-+ bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)g_slot_phys);
-+
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "vchiq_init - done (slots %x, phys %x)",
-+ (unsigned int)vchiq_slot_zero, g_slot_phys);
-+
-+ vchiq_call_connected_callbacks();
-+
-+ return 0;
-+
-+failed_request_irq:
-+failed_vchiq_init:
-+failed_init_slots:
-+ dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys);
-+
-+failed_alloc:
-+ return err;
-+}
-+
-+void __exit
-+vchiq_platform_exit(VCHIQ_STATE_T *state)
-+{
-+ free_irq(VCHIQ_DOORBELL_IRQ, state);
-+ dma_free_coherent(NULL, g_slot_mem_size,
-+ g_slot_mem, g_slot_phys);
-+}
-+
-+
-+VCHIQ_STATUS_T
-+vchiq_platform_init_state(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL);
-+ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1;
-+ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state);
-+ if(status != VCHIQ_SUCCESS)
-+ {
-+ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0;
-+ }
-+ return status;
-+}
-+
-+VCHIQ_ARM_STATE_T*
-+vchiq_platform_get_arm_state(VCHIQ_STATE_T *state)
-+{
-+ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited)
-+ {
-+ BUG();
-+ }
-+ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state;
-+}
-+
-+void
-+remote_event_signal(REMOTE_EVENT_T *event)
-+{
-+ wmb();
-+
-+ event->fired = 1;
-+
-+ dsb(); /* data barrier operation */
-+
-+ if (event->armed) {
-+ /* trigger vc interrupt */
-+
-+ writel(0, __io_address(ARM_0_BELL2));
-+ }
-+}
-+
-+int
-+vchiq_copy_from_user(void *dst, const void *src, int size)
-+{
-+ if ((uint32_t)src < TASK_SIZE) {
-+ return copy_from_user(dst, src, size);
-+ } else {
-+ memcpy(dst, src, size);
-+ return 0;
-+ }
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle,
-+ void *offset, int size, int dir)
-+{
-+ PAGELIST_T *pagelist;
-+ int ret;
-+
-+ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID);
-+
-+ ret = create_pagelist((char __user *)offset, size,
-+ (dir == VCHIQ_BULK_RECEIVE)
-+ ? PAGELIST_READ
-+ : PAGELIST_WRITE,
-+ current,
-+ &pagelist);
-+ if (ret != 0)
-+ return VCHIQ_ERROR;
-+
-+ bulk->handle = memhandle;
-+ bulk->data = VCHIQ_ARM_ADDRESS(pagelist);
-+
-+ /* Store the pagelist address in remote_data, which isn't used by the
-+ slave. */
-+ bulk->remote_data = pagelist;
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+void
-+vchiq_complete_bulk(VCHIQ_BULK_T *bulk)
-+{
-+ if (bulk && bulk->remote_data && bulk->actual)
-+ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual);
-+}
-+
-+void
-+vchiq_transfer_bulk(VCHIQ_BULK_T *bulk)
-+{
-+ /*
-+ * This should only be called on the master (VideoCore) side, but
-+ * provide an implementation to avoid the need for ifdefery.
-+ */
-+ BUG();
-+}
-+
-+void
-+vchiq_dump_platform_state(void *dump_context)
-+{
-+ char buf[80];
-+ int len;
-+ len = snprintf(buf, sizeof(buf),
-+ " Platform: 2835 (VC master)");
-+ vchiq_dump(dump_context, buf, len + 1);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_platform_suspend(VCHIQ_STATE_T *state)
-+{
-+ return VCHIQ_ERROR;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_platform_resume(VCHIQ_STATE_T *state)
-+{
-+ return VCHIQ_SUCCESS;
-+}
-+
-+void
-+vchiq_platform_paused(VCHIQ_STATE_T *state)
-+{
-+}
-+
-+void
-+vchiq_platform_resumed(VCHIQ_STATE_T *state)
-+{
-+}
-+
-+int
-+vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state)
-+{
-+ return 1; // autosuspend not supported - videocore always wanted
-+}
-+
-+int
-+vchiq_platform_use_suspend_timer(void)
-+{
-+ return 0;
-+}
-+void
-+vchiq_dump_platform_use_state(VCHIQ_STATE_T *state)
-+{
-+ vchiq_log_info((vchiq_arm_log_level>=VCHIQ_LOG_INFO),"Suspend timer not in use");
-+}
-+void
-+vchiq_platform_handle_timeout(VCHIQ_STATE_T *state)
-+{
-+ (void)state;
-+}
-+/*
-+ * Local functions
-+ */
-+
-+static irqreturn_t
-+vchiq_doorbell_irq(int irq, void *dev_id)
-+{
-+ VCHIQ_STATE_T *state = dev_id;
-+ irqreturn_t ret = IRQ_NONE;
-+ unsigned int status;
-+
-+ /* Read (and clear) the doorbell */
-+ status = readl(__io_address(ARM_0_BELL0));
-+
-+ if (status & 0x4) { /* Was the doorbell rung? */
-+ remote_event_pollall(state);
-+ ret = IRQ_HANDLED;
-+ }
-+
-+ return ret;
-+}
-+
-+/* There is a potential problem with partial cache lines (pages?)
-+** at the ends of the block when reading. If the CPU accessed anything in
-+** the same line (page?) then it may have pulled old data into the cache,
-+** obscuring the new data underneath. We can solve this by transferring the
-+** partial cache lines separately, and allowing the ARM to copy into the
-+** cached area.
-+
-+** N.B. This implementation plays slightly fast and loose with the Linux
-+** driver programming rules, e.g. its use of __virt_to_bus instead of
-+** dma_map_single, but it isn't a multi-platform driver and it benefits
-+** from increased speed as a result.
-+*/
-+
-+static int
-+create_pagelist(char __user *buf, size_t count, unsigned short type,
-+ struct task_struct *task, PAGELIST_T ** ppagelist)
-+{
-+ PAGELIST_T *pagelist;
-+ struct page **pages;
-+ struct page *page;
-+ unsigned long *addrs;
-+ unsigned int num_pages, offset, i;
-+ char *addr, *base_addr, *next_addr;
-+ int run, addridx, actual_pages;
-+ unsigned long *need_release;
-+
-+ offset = (unsigned int)buf & (PAGE_SIZE - 1);
-+ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE;
-+
-+ *ppagelist = NULL;
-+
-+ /* Allocate enough storage to hold the page pointers and the page
-+ ** list
-+ */
-+ pagelist = kmalloc(sizeof(PAGELIST_T) +
-+ (num_pages * sizeof(unsigned long)) +
-+ sizeof(unsigned long) +
-+ (num_pages * sizeof(pages[0])),
-+ GFP_KERNEL);
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "create_pagelist - %x", (unsigned int)pagelist);
-+ if (!pagelist)
-+ return -ENOMEM;
-+
-+ addrs = pagelist->addrs;
-+ need_release = (unsigned long *)(addrs + num_pages);
-+ pages = (struct page **)(addrs + num_pages + 1);
-+
-+ if (is_vmalloc_addr(buf)) {
-+ for (actual_pages = 0; actual_pages < num_pages; actual_pages++) {
-+ pages[actual_pages] = vmalloc_to_page(buf + (actual_pages * PAGE_SIZE));
-+ }
-+ *need_release = 0; /* do not try and release vmalloc pages */
-+ } else {
-+ down_read(&task->mm->mmap_sem);
-+ actual_pages = get_user_pages(task, task->mm,
-+ (unsigned long)buf & ~(PAGE_SIZE - 1),
-+ num_pages,
-+ (type == PAGELIST_READ) /*Write */ ,
-+ 0 /*Force */ ,
-+ pages,
-+ NULL /*vmas */);
-+ up_read(&task->mm->mmap_sem);
-+
-+ if (actual_pages != num_pages) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "create_pagelist - only %d/%d pages locked",
-+ actual_pages,
-+ num_pages);
-+
-+ /* This is probably due to the process being killed */
-+ while (actual_pages > 0)
-+ {
-+ actual_pages--;
-+ page_cache_release(pages[actual_pages]);
-+ }
-+ kfree(pagelist);
-+ if (actual_pages == 0)
-+ actual_pages = -ENOMEM;
-+ return actual_pages;
-+ }
-+ *need_release = 1; /* release user pages */
-+ }
-+
-+ pagelist->length = count;
-+ pagelist->type = type;
-+ pagelist->offset = offset;
-+
-+ /* Group the pages into runs of contiguous pages */
-+
-+ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0]));
-+ next_addr = base_addr + PAGE_SIZE;
-+ addridx = 0;
-+ run = 0;
-+
-+ for (i = 1; i < num_pages; i++) {
-+ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i]));
-+ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) {
-+ next_addr += PAGE_SIZE;
-+ run++;
-+ } else {
-+ addrs[addridx] = (unsigned long)base_addr + run;
-+ addridx++;
-+ base_addr = addr;
-+ next_addr = addr + PAGE_SIZE;
-+ run = 0;
-+ }
-+ }
-+
-+ addrs[addridx] = (unsigned long)base_addr + run;
-+ addridx++;
-+
-+ /* Partial cache lines (fragments) require special measures */
-+ if ((type == PAGELIST_READ) &&
-+ ((pagelist->offset & (CACHE_LINE_SIZE - 1)) ||
-+ ((pagelist->offset + pagelist->length) &
-+ (CACHE_LINE_SIZE - 1)))) {
-+ FRAGMENTS_T *fragments;
-+
-+ if (down_interruptible(&g_free_fragments_sema) != 0) {
-+ kfree(pagelist);
-+ return -EINTR;
-+ }
-+
-+ WARN_ON(g_free_fragments == NULL);
-+
-+ down(&g_free_fragments_mutex);
-+ fragments = (FRAGMENTS_T *) g_free_fragments;
-+ WARN_ON(fragments == NULL);
-+ g_free_fragments = *(FRAGMENTS_T **) g_free_fragments;
-+ up(&g_free_fragments_mutex);
-+ pagelist->type =
-+ PAGELIST_READ_WITH_FRAGMENTS + (fragments -
-+ g_fragments_base);
-+ }
-+
-+ for (page = virt_to_page(pagelist);
-+ page <= virt_to_page(addrs + num_pages - 1); page++) {
-+ flush_dcache_page(page);
-+ }
-+
-+ *ppagelist = pagelist;
-+
-+ return 0;
-+}
-+
-+static void
-+free_pagelist(PAGELIST_T *pagelist, int actual)
-+{
-+ unsigned long *need_release;
-+ struct page **pages;
-+ unsigned int num_pages, i;
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "free_pagelist - %x, %d", (unsigned int)pagelist, actual);
-+
-+ num_pages =
-+ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) /
-+ PAGE_SIZE;
-+
-+ need_release = (unsigned long *)(pagelist->addrs + num_pages);
-+ pages = (struct page **)(pagelist->addrs + num_pages + 1);
-+
-+ /* Deal with any partial cache lines (fragments) */
-+ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) {
-+ FRAGMENTS_T *fragments = g_fragments_base +
-+ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS);
-+ int head_bytes, tail_bytes;
-+ head_bytes = (CACHE_LINE_SIZE - pagelist->offset) &
-+ (CACHE_LINE_SIZE - 1);
-+ tail_bytes = (pagelist->offset + actual) &
-+ (CACHE_LINE_SIZE - 1);
-+
-+ if ((actual >= 0) && (head_bytes != 0)) {
-+ if (head_bytes > actual)
-+ head_bytes = actual;
-+
-+ memcpy((char *)page_address(pages[0]) +
-+ pagelist->offset,
-+ fragments->headbuf,
-+ head_bytes);
-+ }
-+ if ((actual >= 0) && (head_bytes < actual) &&
-+ (tail_bytes != 0)) {
-+ memcpy((char *)page_address(pages[num_pages - 1]) +
-+ ((pagelist->offset + actual) &
-+ (PAGE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1)),
-+ fragments->tailbuf, tail_bytes);
-+ }
-+
-+ down(&g_free_fragments_mutex);
-+ *(FRAGMENTS_T **) fragments = g_free_fragments;
-+ g_free_fragments = fragments;
-+ up(&g_free_fragments_mutex);
-+ up(&g_free_fragments_sema);
-+ }
-+
-+ if (*need_release) {
-+ for (i = 0; i < num_pages; i++) {
-+ if (pagelist->type != PAGELIST_WRITE)
-+ set_page_dirty(pages[i]);
-+
-+ page_cache_release(pages[i]);
-+ }
-+ }
-+
-+ kfree(pagelist);
-+}
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,42 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_2835_H
-+#define VCHIQ_2835_H
-+
-+#include "vchiq_pagelist.h"
-+
-+#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0
-+#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1
-+
-+#endif /* VCHIQ_2835_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,2884 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/cdev.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/mm.h>
-+#include <linux/highmem.h>
-+#include <linux/pagemap.h>
-+#include <linux/bug.h>
-+#include <linux/semaphore.h>
-+#include <linux/list.h>
-+
-+#include "vchiq_core.h"
-+#include "vchiq_ioctl.h"
-+#include "vchiq_arm.h"
-+#include "vchiq_debugfs.h"
-+#include "vchiq_killable.h"
-+
-+#define DEVICE_NAME "vchiq"
-+
-+/* Override the default prefix, which would be vchiq_arm (from the filename) */
-+#undef MODULE_PARAM_PREFIX
-+#define MODULE_PARAM_PREFIX DEVICE_NAME "."
-+
-+#define VCHIQ_MINOR 0
-+
-+/* Some per-instance constants */
-+#define MAX_COMPLETIONS 16
-+#define MAX_SERVICES 64
-+#define MAX_ELEMENTS 8
-+#define MSG_QUEUE_SIZE 64
-+
-+#define KEEPALIVE_VER 1
-+#define KEEPALIVE_VER_MIN KEEPALIVE_VER
-+
-+/* Run time control of log level, based on KERN_XXX level. */
-+int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT;
-+int vchiq_susp_log_level = VCHIQ_LOG_ERROR;
-+
-+#define SUSPEND_TIMER_TIMEOUT_MS 100
-+#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000
-+
-+#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */
-+static const char *const suspend_state_names[] = {
-+ "VC_SUSPEND_FORCE_CANCELED",
-+ "VC_SUSPEND_REJECTED",
-+ "VC_SUSPEND_FAILED",
-+ "VC_SUSPEND_IDLE",
-+ "VC_SUSPEND_REQUESTED",
-+ "VC_SUSPEND_IN_PROGRESS",
-+ "VC_SUSPEND_SUSPENDED"
-+};
-+#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */
-+static const char *const resume_state_names[] = {
-+ "VC_RESUME_FAILED",
-+ "VC_RESUME_IDLE",
-+ "VC_RESUME_REQUESTED",
-+ "VC_RESUME_IN_PROGRESS",
-+ "VC_RESUME_RESUMED"
-+};
-+/* The number of times we allow force suspend to timeout before actually
-+** _forcing_ suspend. This is to cater for SW which fails to release vchiq
-+** correctly - we don't want to prevent ARM suspend indefinitely in this case.
-+*/
-+#define FORCE_SUSPEND_FAIL_MAX 8
-+
-+/* The time in ms allowed for videocore to go idle when force suspend has been
-+ * requested */
-+#define FORCE_SUSPEND_TIMEOUT_MS 200
-+
-+
-+static void suspend_timer_callback(unsigned long context);
-+
-+
-+typedef struct user_service_struct {
-+ VCHIQ_SERVICE_T *service;
-+ void *userdata;
-+ VCHIQ_INSTANCE_T instance;
-+ char is_vchi;
-+ char dequeue_pending;
-+ char close_pending;
-+ int message_available_pos;
-+ int msg_insert;
-+ int msg_remove;
-+ struct semaphore insert_event;
-+ struct semaphore remove_event;
-+ struct semaphore close_event;
-+ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE];
-+} USER_SERVICE_T;
-+
-+struct bulk_waiter_node {
-+ struct bulk_waiter bulk_waiter;
-+ int pid;
-+ struct list_head list;
-+};
-+
-+struct vchiq_instance_struct {
-+ VCHIQ_STATE_T *state;
-+ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS];
-+ int completion_insert;
-+ int completion_remove;
-+ struct semaphore insert_event;
-+ struct semaphore remove_event;
-+ struct mutex completion_mutex;
-+
-+ int connected;
-+ int closing;
-+ int pid;
-+ int mark;
-+ int use_close_delivered;
-+ int trace;
-+
-+ struct list_head bulk_waiter_list;
-+ struct mutex bulk_waiter_list_mutex;
-+
-+ VCHIQ_DEBUGFS_NODE_T debugfs_node;
-+};
-+
-+typedef struct dump_context_struct {
-+ char __user *buf;
-+ size_t actual;
-+ size_t space;
-+ loff_t offset;
-+} DUMP_CONTEXT_T;
-+
-+static struct cdev vchiq_cdev;
-+static dev_t vchiq_devid;
-+static VCHIQ_STATE_T g_state;
-+static struct class *vchiq_class;
-+static struct device *vchiq_dev;
-+static DEFINE_SPINLOCK(msg_queue_spinlock);
-+
-+static const char *const ioctl_names[] = {
-+ "CONNECT",
-+ "SHUTDOWN",
-+ "CREATE_SERVICE",
-+ "REMOVE_SERVICE",
-+ "QUEUE_MESSAGE",
-+ "QUEUE_BULK_TRANSMIT",
-+ "QUEUE_BULK_RECEIVE",
-+ "AWAIT_COMPLETION",
-+ "DEQUEUE_MESSAGE",
-+ "GET_CLIENT_ID",
-+ "GET_CONFIG",
-+ "CLOSE_SERVICE",
-+ "USE_SERVICE",
-+ "RELEASE_SERVICE",
-+ "SET_SERVICE_OPTION",
-+ "DUMP_PHYS_MEM",
-+ "LIB_VERSION",
-+ "CLOSE_DELIVERED"
-+};
-+
-+vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) ==
-+ (VCHIQ_IOC_MAX + 1));
-+
-+static void
-+dump_phys_mem(void *virt_addr, uint32_t num_bytes);
-+
-+/****************************************************************************
-+*
-+* add_completion
-+*
-+***************************************************************************/
-+
-+static VCHIQ_STATUS_T
-+add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service,
-+ void *bulk_userdata)
-+{
-+ VCHIQ_COMPLETION_DATA_T *completion;
-+ DEBUG_INITIALISE(g_state.local)
-+
-+ while (instance->completion_insert ==
-+ (instance->completion_remove + MAX_COMPLETIONS)) {
-+ /* Out of space - wait for the client */
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "add_completion - completion queue full");
-+ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT);
-+ if (down_interruptible(&instance->remove_event) != 0) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback interrupted");
-+ return VCHIQ_RETRY;
-+ } else if (instance->closing) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback closing");
-+ return VCHIQ_ERROR;
-+ }
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ }
-+
-+ completion =
-+ &instance->completions[instance->completion_insert &
-+ (MAX_COMPLETIONS - 1)];
-+
-+ completion->header = header;
-+ completion->reason = reason;
-+ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */
-+ completion->service_userdata = user_service->service;
-+ completion->bulk_userdata = bulk_userdata;
-+
-+ if (reason == VCHIQ_SERVICE_CLOSED) {
-+ /* Take an extra reference, to be held until
-+ this CLOSED notification is delivered. */
-+ lock_service(user_service->service);
-+ if (instance->use_close_delivered)
-+ user_service->close_pending = 1;
-+ }
-+
-+ /* A write barrier is needed here to ensure that the entire completion
-+ record is written out before the insert point. */
-+ wmb();
-+
-+ if (reason == VCHIQ_MESSAGE_AVAILABLE)
-+ user_service->message_available_pos =
-+ instance->completion_insert;
-+ instance->completion_insert++;
-+
-+ up(&instance->insert_event);
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+/****************************************************************************
-+*
-+* service_callback
-+*
-+***************************************************************************/
-+
-+static VCHIQ_STATUS_T
-+service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header,
-+ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata)
-+{
-+ /* How do we ensure the callback goes to the right client?
-+ ** The service_user data points to a USER_SERVICE_T record containing
-+ ** the original callback and the user state structure, which contains a
-+ ** circular buffer for completion records.
-+ */
-+ USER_SERVICE_T *user_service;
-+ VCHIQ_SERVICE_T *service;
-+ VCHIQ_INSTANCE_T instance;
-+ DEBUG_INITIALISE(g_state.local)
-+
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+
-+ service = handle_to_service(handle);
-+ BUG_ON(!service);
-+ user_service = (USER_SERVICE_T *)service->base.userdata;
-+ instance = user_service->instance;
-+
-+ if (!instance || instance->closing)
-+ return VCHIQ_SUCCESS;
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "service_callback - service %lx(%d,%p), reason %d, header %lx, "
-+ "instance %lx, bulk_userdata %lx",
-+ (unsigned long)user_service,
-+ service->localport, user_service->userdata,
-+ reason, (unsigned long)header,
-+ (unsigned long)instance, (unsigned long)bulk_userdata);
-+
-+ if (header && user_service->is_vchi) {
-+ spin_lock(&msg_queue_spinlock);
-+ while (user_service->msg_insert ==
-+ (user_service->msg_remove + MSG_QUEUE_SIZE)) {
-+ spin_unlock(&msg_queue_spinlock);
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT);
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "service_callback - msg queue full");
-+ /* If there is no MESSAGE_AVAILABLE in the completion
-+ ** queue, add one
-+ */
-+ if ((user_service->message_available_pos -
-+ instance->completion_remove) < 0) {
-+ VCHIQ_STATUS_T status;
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "Inserting extra MESSAGE_AVAILABLE");
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ status = add_completion(instance, reason,
-+ NULL, user_service, bulk_userdata);
-+ if (status != VCHIQ_SUCCESS) {
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ return status;
-+ }
-+ }
-+
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ if (down_interruptible(&user_service->remove_event)
-+ != 0) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback interrupted");
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ return VCHIQ_RETRY;
-+ } else if (instance->closing) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "service_callback closing");
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ return VCHIQ_ERROR;
-+ }
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ spin_lock(&msg_queue_spinlock);
-+ }
-+
-+ user_service->msg_queue[user_service->msg_insert &
-+ (MSG_QUEUE_SIZE - 1)] = header;
-+ user_service->msg_insert++;
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ up(&user_service->insert_event);
-+
-+ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if
-+ ** there is a MESSAGE_AVAILABLE in the completion queue then
-+ ** bypass the completion queue.
-+ */
-+ if (((user_service->message_available_pos -
-+ instance->completion_remove) >= 0) ||
-+ user_service->dequeue_pending) {
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+ user_service->dequeue_pending = 0;
-+ return VCHIQ_SUCCESS;
-+ }
-+
-+ header = NULL;
-+ }
-+ DEBUG_TRACE(SERVICE_CALLBACK_LINE);
-+
-+ return add_completion(instance, reason, header, user_service,
-+ bulk_userdata);
-+}
-+
-+/****************************************************************************
-+*
-+* user_service_free
-+*
-+***************************************************************************/
-+static void
-+user_service_free(void *userdata)
-+{
-+ kfree(userdata);
-+}
-+
-+/****************************************************************************
-+*
-+* close_delivered
-+*
-+***************************************************************************/
-+static void close_delivered(USER_SERVICE_T *user_service)
-+{
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "close_delivered(handle=%x)",
-+ user_service->service->handle);
-+
-+ if (user_service->close_pending) {
-+ /* Allow the underlying service to be culled */
-+ unlock_service(user_service->service);
-+
-+ /* Wake the user-thread blocked in close_ or remove_service */
-+ up(&user_service->close_event);
-+
-+ user_service->close_pending = 0;
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_ioctl
-+*
-+***************************************************************************/
-+static long
-+vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ VCHIQ_INSTANCE_T instance = file->private_data;
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ VCHIQ_SERVICE_T *service = NULL;
-+ long ret = 0;
-+ int i, rc;
-+ DEBUG_INITIALISE(g_state.local)
-+
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ "vchiq_ioctl - instance %x, cmd %s, arg %lx",
-+ (unsigned int)instance,
-+ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) &&
-+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ?
-+ ioctl_names[_IOC_NR(cmd)] : "<invalid>", arg);
-+
-+ switch (cmd) {
-+ case VCHIQ_IOC_SHUTDOWN:
-+ if (!instance->connected)
-+ break;
-+
-+ /* Remove all services */
-+ i = 0;
-+ while ((service = next_service_by_instance(instance->state,
-+ instance, &i)) != NULL) {
-+ status = vchiq_remove_service(service->handle);
-+ unlock_service(service);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+ service = NULL;
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ /* Wake the completion thread and ask it to exit */
-+ instance->closing = 1;
-+ up(&instance->insert_event);
-+ }
-+
-+ break;
-+
-+ case VCHIQ_IOC_CONNECT:
-+ if (instance->connected) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+ rc = mutex_lock_interruptible(&instance->state->mutex);
-+ if (rc != 0) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "vchiq: connect: could not lock mutex for "
-+ "state %d: %d",
-+ instance->state->id, rc);
-+ ret = -EINTR;
-+ break;
-+ }
-+ status = vchiq_connect_internal(instance->state, instance);
-+ mutex_unlock(&instance->state->mutex);
-+
-+ if (status == VCHIQ_SUCCESS)
-+ instance->connected = 1;
-+ else
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "vchiq: could not connect: %d", status);
-+ break;
-+
-+ case VCHIQ_IOC_CREATE_SERVICE: {
-+ VCHIQ_CREATE_SERVICE_T args;
-+ USER_SERVICE_T *user_service = NULL;
-+ void *userdata;
-+ int srvstate;
-+
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL);
-+ if (!user_service) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+
-+ if (args.is_open) {
-+ if (!instance->connected) {
-+ ret = -ENOTCONN;
-+ kfree(user_service);
-+ break;
-+ }
-+ srvstate = VCHIQ_SRVSTATE_OPENING;
-+ } else {
-+ srvstate =
-+ instance->connected ?
-+ VCHIQ_SRVSTATE_LISTENING :
-+ VCHIQ_SRVSTATE_HIDDEN;
-+ }
-+
-+ userdata = args.params.userdata;
-+ args.params.callback = service_callback;
-+ args.params.userdata = user_service;
-+ service = vchiq_add_service_internal(
-+ instance->state,
-+ &args.params, srvstate,
-+ instance, user_service_free);
-+
-+ if (service != NULL) {
-+ user_service->service = service;
-+ user_service->userdata = userdata;
-+ user_service->instance = instance;
-+ user_service->is_vchi = (args.is_vchi != 0);
-+ user_service->dequeue_pending = 0;
-+ user_service->close_pending = 0;
-+ user_service->message_available_pos =
-+ instance->completion_remove - 1;
-+ user_service->msg_insert = 0;
-+ user_service->msg_remove = 0;
-+ sema_init(&user_service->insert_event, 0);
-+ sema_init(&user_service->remove_event, 0);
-+ sema_init(&user_service->close_event, 0);
-+
-+ if (args.is_open) {
-+ status = vchiq_open_service_internal
-+ (service, instance->pid);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_remove_service(service->handle);
-+ service = NULL;
-+ ret = (status == VCHIQ_RETRY) ?
-+ -EINTR : -EIO;
-+ break;
-+ }
-+ }
-+
-+ if (copy_to_user((void __user *)
-+ &(((VCHIQ_CREATE_SERVICE_T __user *)
-+ arg)->handle),
-+ (const void *)&service->handle,
-+ sizeof(service->handle)) != 0) {
-+ ret = -EFAULT;
-+ vchiq_remove_service(service->handle);
-+ }
-+
-+ service = NULL;
-+ } else {
-+ ret = -EEXIST;
-+ kfree(user_service);
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_CLOSE_SERVICE: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ USER_SERVICE_T *user_service =
-+ (USER_SERVICE_T *)service->base.userdata;
-+ /* close_pending is false on first entry, and when the
-+ wait in vchiq_close_service has been interrupted. */
-+ if (!user_service->close_pending) {
-+ status = vchiq_close_service(service->handle);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+
-+ /* close_pending is true once the underlying service
-+ has been closed until the client library calls the
-+ CLOSE_DELIVERED ioctl, signalling close_event. */
-+ if (user_service->close_pending &&
-+ down_interruptible(&user_service->close_event))
-+ status = VCHIQ_RETRY;
-+ }
-+ else
-+ ret = -EINVAL;
-+ } break;
-+
-+ case VCHIQ_IOC_REMOVE_SERVICE: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ USER_SERVICE_T *user_service =
-+ (USER_SERVICE_T *)service->base.userdata;
-+ /* close_pending is false on first entry, and when the
-+ wait in vchiq_close_service has been interrupted. */
-+ if (!user_service->close_pending) {
-+ status = vchiq_remove_service(service->handle);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+
-+ /* close_pending is true once the underlying service
-+ has been closed until the client library calls the
-+ CLOSE_DELIVERED ioctl, signalling close_event. */
-+ if (user_service->close_pending &&
-+ down_interruptible(&user_service->close_event))
-+ status = VCHIQ_RETRY;
-+ }
-+ else
-+ ret = -EINVAL;
-+ } break;
-+
-+ case VCHIQ_IOC_USE_SERVICE:
-+ case VCHIQ_IOC_RELEASE_SERVICE: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ status = (cmd == VCHIQ_IOC_USE_SERVICE) ?
-+ vchiq_use_service_internal(service) :
-+ vchiq_release_service_internal(service);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s: cmd %s returned error %d for "
-+ "service %c%c%c%c:%03d",
-+ __func__,
-+ (cmd == VCHIQ_IOC_USE_SERVICE) ?
-+ "VCHIQ_IOC_USE_SERVICE" :
-+ "VCHIQ_IOC_RELEASE_SERVICE",
-+ status,
-+ VCHIQ_FOURCC_AS_4CHARS(
-+ service->base.fourcc),
-+ service->client_id);
-+ ret = -EINVAL;
-+ }
-+ } else
-+ ret = -EINVAL;
-+ } break;
-+
-+ case VCHIQ_IOC_QUEUE_MESSAGE: {
-+ VCHIQ_QUEUE_MESSAGE_T args;
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ service = find_service_for_instance(instance, args.handle);
-+
-+ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) {
-+ /* Copy elements into kernel space */
-+ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS];
-+ if (copy_from_user(elements, args.elements,
-+ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0)
-+ status = vchiq_queue_message
-+ (args.handle,
-+ elements, args.count);
-+ else
-+ ret = -EFAULT;
-+ } else {
-+ ret = -EINVAL;
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT:
-+ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: {
-+ VCHIQ_QUEUE_BULK_TRANSFER_T args;
-+ struct bulk_waiter_node *waiter = NULL;
-+ VCHIQ_BULK_DIR_T dir =
-+ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ?
-+ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE;
-+
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ service = find_service_for_instance(instance, args.handle);
-+ if (!service) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) {
-+ waiter = kzalloc(sizeof(struct bulk_waiter_node),
-+ GFP_KERNEL);
-+ if (!waiter) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+ args.userdata = &waiter->bulk_waiter;
-+ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) {
-+ struct list_head *pos;
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_for_each(pos, &instance->bulk_waiter_list) {
-+ if (list_entry(pos, struct bulk_waiter_node,
-+ list)->pid == current->pid) {
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ break;
-+ }
-+
-+ }
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+ if (!waiter) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "no bulk_waiter found for pid %d",
-+ current->pid);
-+ ret = -ESRCH;
-+ break;
-+ }
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "found bulk_waiter %x for pid %d",
-+ (unsigned int)waiter, current->pid);
-+ args.userdata = &waiter->bulk_waiter;
-+ }
-+ status = vchiq_bulk_transfer
-+ (args.handle,
-+ VCHI_MEM_HANDLE_INVALID,
-+ args.data, args.size,
-+ args.userdata, args.mode,
-+ dir);
-+ if (!waiter)
-+ break;
-+ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) ||
-+ !waiter->bulk_waiter.bulk) {
-+ if (waiter->bulk_waiter.bulk) {
-+ /* Cancel the signal when the transfer
-+ ** completes. */
-+ spin_lock(&bulk_waiter_spinlock);
-+ waiter->bulk_waiter.bulk->userdata = NULL;
-+ spin_unlock(&bulk_waiter_spinlock);
-+ }
-+ kfree(waiter);
-+ } else {
-+ const VCHIQ_BULK_MODE_T mode_waiting =
-+ VCHIQ_BULK_MODE_WAITING;
-+ waiter->pid = current->pid;
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_add(&waiter->list, &instance->bulk_waiter_list);
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "saved bulk_waiter %x for pid %d",
-+ (unsigned int)waiter, current->pid);
-+
-+ if (copy_to_user((void __user *)
-+ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *)
-+ arg)->mode),
-+ (const void *)&mode_waiting,
-+ sizeof(mode_waiting)) != 0)
-+ ret = -EFAULT;
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_AWAIT_COMPLETION: {
-+ VCHIQ_AWAIT_COMPLETION_T args;
-+
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ if (!instance->connected) {
-+ ret = -ENOTCONN;
-+ break;
-+ }
-+
-+ if (copy_from_user(&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ mutex_lock(&instance->completion_mutex);
-+
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ while ((instance->completion_remove ==
-+ instance->completion_insert)
-+ && !instance->closing) {
-+ int rc;
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ mutex_unlock(&instance->completion_mutex);
-+ rc = down_interruptible(&instance->insert_event);
-+ mutex_lock(&instance->completion_mutex);
-+ if (rc != 0) {
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "AWAIT_COMPLETION interrupted");
-+ ret = -EINTR;
-+ break;
-+ }
-+ }
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+
-+ /* A read memory barrier is needed to stop prefetch of a stale
-+ ** completion record
-+ */
-+ rmb();
-+
-+ if (ret == 0) {
-+ int msgbufcount = args.msgbufcount;
-+ for (ret = 0; ret < args.count; ret++) {
-+ VCHIQ_COMPLETION_DATA_T *completion;
-+ VCHIQ_SERVICE_T *service;
-+ USER_SERVICE_T *user_service;
-+ VCHIQ_HEADER_T *header;
-+ if (instance->completion_remove ==
-+ instance->completion_insert)
-+ break;
-+ completion = &instance->completions[
-+ instance->completion_remove &
-+ (MAX_COMPLETIONS - 1)];
-+
-+ service = completion->service_userdata;
-+ user_service = service->base.userdata;
-+ completion->service_userdata =
-+ user_service->userdata;
-+
-+ header = completion->header;
-+ if (header) {
-+ void __user *msgbuf;
-+ int msglen;
-+
-+ msglen = header->size +
-+ sizeof(VCHIQ_HEADER_T);
-+ /* This must be a VCHIQ-style service */
-+ if (args.msgbufsize < msglen) {
-+ vchiq_log_error(
-+ vchiq_arm_log_level,
-+ "header %x: msgbufsize"
-+ " %x < msglen %x",
-+ (unsigned int)header,
-+ args.msgbufsize,
-+ msglen);
-+ WARN(1, "invalid message "
-+ "size\n");
-+ if (ret == 0)
-+ ret = -EMSGSIZE;
-+ break;
-+ }
-+ if (msgbufcount <= 0)
-+ /* Stall here for lack of a
-+ ** buffer for the message. */
-+ break;
-+ /* Get the pointer from user space */
-+ msgbufcount--;
-+ if (copy_from_user(&msgbuf,
-+ (const void __user *)
-+ &args.msgbufs[msgbufcount],
-+ sizeof(msgbuf)) != 0) {
-+ if (ret == 0)
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ /* Copy the message to user space */
-+ if (copy_to_user(msgbuf, header,
-+ msglen) != 0) {
-+ if (ret == 0)
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ /* Now it has been copied, the message
-+ ** can be released. */
-+ vchiq_release_message(service->handle,
-+ header);
-+
-+ /* The completion must point to the
-+ ** msgbuf. */
-+ completion->header = msgbuf;
-+ }
-+
-+ if ((completion->reason ==
-+ VCHIQ_SERVICE_CLOSED) &&
-+ !instance->use_close_delivered)
-+ unlock_service(service);
-+
-+ if (copy_to_user((void __user *)(
-+ (size_t)args.buf +
-+ ret * sizeof(VCHIQ_COMPLETION_DATA_T)),
-+ completion,
-+ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) {
-+ if (ret == 0)
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ instance->completion_remove++;
-+ }
-+
-+ if (msgbufcount != args.msgbufcount) {
-+ if (copy_to_user((void __user *)
-+ &((VCHIQ_AWAIT_COMPLETION_T *)arg)->
-+ msgbufcount,
-+ &msgbufcount,
-+ sizeof(msgbufcount)) != 0) {
-+ ret = -EFAULT;
-+ }
-+ }
-+ }
-+
-+ if (ret != 0)
-+ up(&instance->remove_event);
-+ mutex_unlock(&instance->completion_mutex);
-+ DEBUG_TRACE(AWAIT_COMPLETION_LINE);
-+ } break;
-+
-+ case VCHIQ_IOC_DEQUEUE_MESSAGE: {
-+ VCHIQ_DEQUEUE_MESSAGE_T args;
-+ USER_SERVICE_T *user_service;
-+ VCHIQ_HEADER_T *header;
-+
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ service = find_service_for_instance(instance, args.handle);
-+ if (!service) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+ user_service = (USER_SERVICE_T *)service->base.userdata;
-+ if (user_service->is_vchi == 0) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ spin_lock(&msg_queue_spinlock);
-+ if (user_service->msg_remove == user_service->msg_insert) {
-+ if (!args.blocking) {
-+ spin_unlock(&msg_queue_spinlock);
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ ret = -EWOULDBLOCK;
-+ break;
-+ }
-+ user_service->dequeue_pending = 1;
-+ do {
-+ spin_unlock(&msg_queue_spinlock);
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ if (down_interruptible(
-+ &user_service->insert_event) != 0) {
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "DEQUEUE_MESSAGE interrupted");
-+ ret = -EINTR;
-+ break;
-+ }
-+ spin_lock(&msg_queue_spinlock);
-+ } while (user_service->msg_remove ==
-+ user_service->msg_insert);
-+
-+ if (ret)
-+ break;
-+ }
-+
-+ BUG_ON((int)(user_service->msg_insert -
-+ user_service->msg_remove) < 0);
-+
-+ header = user_service->msg_queue[user_service->msg_remove &
-+ (MSG_QUEUE_SIZE - 1)];
-+ user_service->msg_remove++;
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ up(&user_service->remove_event);
-+ if (header == NULL)
-+ ret = -ENOTCONN;
-+ else if (header->size <= args.bufsize) {
-+ /* Copy to user space if msgbuf is not NULL */
-+ if ((args.buf == NULL) ||
-+ (copy_to_user((void __user *)args.buf,
-+ header->data,
-+ header->size) == 0)) {
-+ ret = header->size;
-+ vchiq_release_message(
-+ service->handle,
-+ header);
-+ } else
-+ ret = -EFAULT;
-+ } else {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "header %x: bufsize %x < size %x",
-+ (unsigned int)header, args.bufsize,
-+ header->size);
-+ WARN(1, "invalid size\n");
-+ ret = -EMSGSIZE;
-+ }
-+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE);
-+ } break;
-+
-+ case VCHIQ_IOC_GET_CLIENT_ID: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ ret = vchiq_get_client_id(handle);
-+ } break;
-+
-+ case VCHIQ_IOC_GET_CONFIG: {
-+ VCHIQ_GET_CONFIG_T args;
-+ VCHIQ_CONFIG_T config;
-+
-+ if (copy_from_user(&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ if (args.config_size > sizeof(config)) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+ status = vchiq_get_config(instance, args.config_size, &config);
-+ if (status == VCHIQ_SUCCESS) {
-+ if (copy_to_user((void __user *)args.pconfig,
-+ &config, args.config_size) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ }
-+ } break;
-+
-+ case VCHIQ_IOC_SET_SERVICE_OPTION: {
-+ VCHIQ_SET_SERVICE_OPTION_T args;
-+
-+ if (copy_from_user(
-+ &args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+
-+ service = find_service_for_instance(instance, args.handle);
-+ if (!service) {
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ status = vchiq_set_service_option(
-+ args.handle, args.option, args.value);
-+ } break;
-+
-+ case VCHIQ_IOC_DUMP_PHYS_MEM: {
-+ VCHIQ_DUMP_MEM_T args;
-+
-+ if (copy_from_user
-+ (&args, (const void __user *)arg,
-+ sizeof(args)) != 0) {
-+ ret = -EFAULT;
-+ break;
-+ }
-+ dump_phys_mem(args.virt_addr, args.num_bytes);
-+ } break;
-+
-+ case VCHIQ_IOC_LIB_VERSION: {
-+ unsigned int lib_version = (unsigned int)arg;
-+
-+ if (lib_version < VCHIQ_VERSION_MIN)
-+ ret = -EINVAL;
-+ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED)
-+ instance->use_close_delivered = 1;
-+ } break;
-+
-+ case VCHIQ_IOC_CLOSE_DELIVERED: {
-+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg;
-+
-+ service = find_closed_service_for_instance(instance, handle);
-+ if (service != NULL) {
-+ USER_SERVICE_T *user_service =
-+ (USER_SERVICE_T *)service->base.userdata;
-+ close_delivered(user_service);
-+ }
-+ else
-+ ret = -EINVAL;
-+ } break;
-+
-+ default:
-+ ret = -ENOTTY;
-+ break;
-+ }
-+
-+ if (service)
-+ unlock_service(service);
-+
-+ if (ret == 0) {
-+ if (status == VCHIQ_ERROR)
-+ ret = -EIO;
-+ else if (status == VCHIQ_RETRY)
-+ ret = -EINTR;
-+ }
-+
-+ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) &&
-+ (ret != -EWOULDBLOCK))
-+ vchiq_log_info(vchiq_arm_log_level,
-+ " ioctl instance %lx, cmd %s -> status %d, %ld",
-+ (unsigned long)instance,
-+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ?
-+ ioctl_names[_IOC_NR(cmd)] :
-+ "<invalid>",
-+ status, ret);
-+ else
-+ vchiq_log_trace(vchiq_arm_log_level,
-+ " ioctl instance %lx, cmd %s -> status %d, %ld",
-+ (unsigned long)instance,
-+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ?
-+ ioctl_names[_IOC_NR(cmd)] :
-+ "<invalid>",
-+ status, ret);
-+
-+ return ret;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_open
-+*
-+***************************************************************************/
-+
-+static int
-+vchiq_open(struct inode *inode, struct file *file)
-+{
-+ int dev = iminor(inode) & 0x0f;
-+ vchiq_log_info(vchiq_arm_log_level, "vchiq_open");
-+ switch (dev) {
-+ case VCHIQ_MINOR: {
-+ int ret;
-+ VCHIQ_STATE_T *state = vchiq_get_state();
-+ VCHIQ_INSTANCE_T instance;
-+
-+ if (!state) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "vchiq has no connection to VideoCore");
-+ return -ENOTCONN;
-+ }
-+
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+ if (!instance)
-+ return -ENOMEM;
-+
-+ instance->state = state;
-+ instance->pid = current->tgid;
-+
-+ ret = vchiq_debugfs_add_instance(instance);
-+ if (ret != 0) {
-+ kfree(instance);
-+ return ret;
-+ }
-+
-+ sema_init(&instance->insert_event, 0);
-+ sema_init(&instance->remove_event, 0);
-+ mutex_init(&instance->completion_mutex);
-+ mutex_init(&instance->bulk_waiter_list_mutex);
-+ INIT_LIST_HEAD(&instance->bulk_waiter_list);
-+
-+ file->private_data = instance;
-+ } break;
-+
-+ default:
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unknown minor device: %d", dev);
-+ return -ENXIO;
-+ }
-+
-+ return 0;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_release
-+*
-+***************************************************************************/
-+
-+static int
-+vchiq_release(struct inode *inode, struct file *file)
-+{
-+ int dev = iminor(inode) & 0x0f;
-+ int ret = 0;
-+ switch (dev) {
-+ case VCHIQ_MINOR: {
-+ VCHIQ_INSTANCE_T instance = file->private_data;
-+ VCHIQ_STATE_T *state = vchiq_get_state();
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "vchiq_release: instance=%lx",
-+ (unsigned long)instance);
-+
-+ if (!state) {
-+ ret = -EPERM;
-+ goto out;
-+ }
-+
-+ /* Ensure videocore is awake to allow termination. */
-+ vchiq_use_internal(instance->state, NULL,
-+ USE_TYPE_VCHIQ);
-+
-+ mutex_lock(&instance->completion_mutex);
-+
-+ /* Wake the completion thread and ask it to exit */
-+ instance->closing = 1;
-+ up(&instance->insert_event);
-+
-+ mutex_unlock(&instance->completion_mutex);
-+
-+ /* Wake the slot handler if the completion queue is full. */
-+ up(&instance->remove_event);
-+
-+ /* Mark all services for termination... */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance,
-+ &i)) != NULL) {
-+ USER_SERVICE_T *user_service = service->base.userdata;
-+
-+ /* Wake the slot handler if the msg queue is full. */
-+ up(&user_service->remove_event);
-+
-+ vchiq_terminate_service_internal(service);
-+ unlock_service(service);
-+ }
-+
-+ /* ...and wait for them to die */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance, &i))
-+ != NULL) {
-+ USER_SERVICE_T *user_service = service->base.userdata;
-+
-+ down(&service->remove_event);
-+
-+ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE);
-+
-+ spin_lock(&msg_queue_spinlock);
-+
-+ while (user_service->msg_remove !=
-+ user_service->msg_insert) {
-+ VCHIQ_HEADER_T *header = user_service->
-+ msg_queue[user_service->msg_remove &
-+ (MSG_QUEUE_SIZE - 1)];
-+ user_service->msg_remove++;
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ if (header)
-+ vchiq_release_message(
-+ service->handle,
-+ header);
-+ spin_lock(&msg_queue_spinlock);
-+ }
-+
-+ spin_unlock(&msg_queue_spinlock);
-+
-+ unlock_service(service);
-+ }
-+
-+ /* Release any closed services */
-+ while (instance->completion_remove !=
-+ instance->completion_insert) {
-+ VCHIQ_COMPLETION_DATA_T *completion;
-+ VCHIQ_SERVICE_T *service;
-+ completion = &instance->completions[
-+ instance->completion_remove &
-+ (MAX_COMPLETIONS - 1)];
-+ service = completion->service_userdata;
-+ if (completion->reason == VCHIQ_SERVICE_CLOSED)
-+ {
-+ USER_SERVICE_T *user_service =
-+ service->base.userdata;
-+
-+ /* Wake any blocked user-thread */
-+ if (instance->use_close_delivered)
-+ up(&user_service->close_event);
-+ unlock_service(service);
-+ }
-+ instance->completion_remove++;
-+ }
-+
-+ /* Release the PEER service count. */
-+ vchiq_release_internal(instance->state, NULL);
-+
-+ {
-+ struct list_head *pos, *next;
-+ list_for_each_safe(pos, next,
-+ &instance->bulk_waiter_list) {
-+ struct bulk_waiter_node *waiter;
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "bulk_waiter - cleaned up %x "
-+ "for pid %d",
-+ (unsigned int)waiter, waiter->pid);
-+ kfree(waiter);
-+ }
-+ }
-+
-+ vchiq_debugfs_remove_instance(instance);
-+
-+ kfree(instance);
-+ file->private_data = NULL;
-+ } break;
-+
-+ default:
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unknown minor device: %d", dev);
-+ ret = -ENXIO;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_dump
-+*
-+***************************************************************************/
-+
-+void
-+vchiq_dump(void *dump_context, const char *str, int len)
-+{
-+ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context;
-+
-+ if (context->actual < context->space) {
-+ int copy_bytes;
-+ if (context->offset > 0) {
-+ int skip_bytes = min(len, (int)context->offset);
-+ str += skip_bytes;
-+ len -= skip_bytes;
-+ context->offset -= skip_bytes;
-+ if (context->offset > 0)
-+ return;
-+ }
-+ copy_bytes = min(len, (int)(context->space - context->actual));
-+ if (copy_bytes == 0)
-+ return;
-+ if (copy_to_user(context->buf + context->actual, str,
-+ copy_bytes))
-+ context->actual = -EFAULT;
-+ context->actual += copy_bytes;
-+ len -= copy_bytes;
-+
-+ /* If tne terminating NUL is included in the length, then it
-+ ** marks the end of a line and should be replaced with a
-+ ** carriage return. */
-+ if ((len == 0) && (str[copy_bytes - 1] == '\0')) {
-+ char cr = '\n';
-+ if (copy_to_user(context->buf + context->actual - 1,
-+ &cr, 1))
-+ context->actual = -EFAULT;
-+ }
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_dump_platform_instance_state
-+*
-+***************************************************************************/
-+
-+void
-+vchiq_dump_platform_instances(void *dump_context)
-+{
-+ VCHIQ_STATE_T *state = vchiq_get_state();
-+ char buf[80];
-+ int len;
-+ int i;
-+
-+ /* There is no list of instances, so instead scan all services,
-+ marking those that have been dumped. */
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ VCHIQ_INSTANCE_T instance;
-+
-+ if (service && (service->base.callback == service_callback)) {
-+ instance = service->instance;
-+ if (instance)
-+ instance->mark = 0;
-+ }
-+ }
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ VCHIQ_INSTANCE_T instance;
-+
-+ if (service && (service->base.callback == service_callback)) {
-+ instance = service->instance;
-+ if (instance && !instance->mark) {
-+ len = snprintf(buf, sizeof(buf),
-+ "Instance %x: pid %d,%s completions "
-+ "%d/%d",
-+ (unsigned int)instance, instance->pid,
-+ instance->connected ? " connected, " :
-+ "",
-+ instance->completion_insert -
-+ instance->completion_remove,
-+ MAX_COMPLETIONS);
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ instance->mark = 1;
-+ }
-+ }
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_dump_platform_service_state
-+*
-+***************************************************************************/
-+
-+void
-+vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service)
-+{
-+ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata;
-+ char buf[80];
-+ int len;
-+
-+ len = snprintf(buf, sizeof(buf), " instance %x",
-+ (unsigned int)service->instance);
-+
-+ if ((service->base.callback == service_callback) &&
-+ user_service->is_vchi) {
-+ len += snprintf(buf + len, sizeof(buf) - len,
-+ ", %d/%d messages",
-+ user_service->msg_insert - user_service->msg_remove,
-+ MSG_QUEUE_SIZE);
-+
-+ if (user_service->dequeue_pending)
-+ len += snprintf(buf + len, sizeof(buf) - len,
-+ " (dequeue pending)");
-+ }
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+}
-+
-+/****************************************************************************
-+*
-+* dump_user_mem
-+*
-+***************************************************************************/
-+
-+static void
-+dump_phys_mem(void *virt_addr, uint32_t num_bytes)
-+{
-+ int rc;
-+ uint8_t *end_virt_addr = virt_addr + num_bytes;
-+ int num_pages;
-+ int offset;
-+ int end_offset;
-+ int page_idx;
-+ int prev_idx;
-+ struct page *page;
-+ struct page **pages;
-+ uint8_t *kmapped_virt_ptr;
-+
-+ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */
-+
-+ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL);
-+ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) &
-+ ~0x0fuL);
-+
-+ offset = (int)(long)virt_addr & (PAGE_SIZE - 1);
-+ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1);
-+
-+ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
-+
-+ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL);
-+ if (pages == NULL) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to allocation memory for %d pages\n",
-+ num_pages);
-+ return;
-+ }
-+
-+ down_read(&current->mm->mmap_sem);
-+ rc = get_user_pages(current, /* task */
-+ current->mm, /* mm */
-+ (unsigned long)virt_addr, /* start */
-+ num_pages, /* len */
-+ 0, /* write */
-+ 0, /* force */
-+ pages, /* pages (array of page pointers) */
-+ NULL); /* vmas */
-+ up_read(&current->mm->mmap_sem);
-+
-+ prev_idx = -1;
-+ page = NULL;
-+
-+ while (offset < end_offset) {
-+
-+ int page_offset = offset % PAGE_SIZE;
-+ page_idx = offset / PAGE_SIZE;
-+
-+ if (page_idx != prev_idx) {
-+
-+ if (page != NULL)
-+ kunmap(page);
-+ page = pages[page_idx];
-+ kmapped_virt_ptr = kmap(page);
-+
-+ prev_idx = page_idx;
-+ }
-+
-+ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE)
-+ vchiq_log_dump_mem("ph",
-+ (uint32_t)(unsigned long)&kmapped_virt_ptr[
-+ page_offset],
-+ &kmapped_virt_ptr[page_offset], 16);
-+
-+ offset += 16;
-+ }
-+ if (page != NULL)
-+ kunmap(page);
-+
-+ for (page_idx = 0; page_idx < num_pages; page_idx++)
-+ page_cache_release(pages[page_idx]);
-+
-+ kfree(pages);
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_read
-+*
-+***************************************************************************/
-+
-+static ssize_t
-+vchiq_read(struct file *file, char __user *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ DUMP_CONTEXT_T context;
-+ context.buf = buf;
-+ context.actual = 0;
-+ context.space = count;
-+ context.offset = *ppos;
-+
-+ vchiq_dump_state(&context, &g_state);
-+
-+ *ppos += context.actual;
-+
-+ return context.actual;
-+}
-+
-+VCHIQ_STATE_T *
-+vchiq_get_state(void)
-+{
-+
-+ if (g_state.remote == NULL)
-+ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__);
-+ else if (g_state.remote->initialised != 1)
-+ printk(KERN_NOTICE "%s: g_state.remote->initialised != 1 (%d)\n",
-+ __func__, g_state.remote->initialised);
-+
-+ return ((g_state.remote != NULL) &&
-+ (g_state.remote->initialised == 1)) ? &g_state : NULL;
-+}
-+
-+static const struct file_operations
-+vchiq_fops = {
-+ .owner = THIS_MODULE,
-+ .unlocked_ioctl = vchiq_ioctl,
-+ .open = vchiq_open,
-+ .release = vchiq_release,
-+ .read = vchiq_read
-+};
-+
-+/*
-+ * Autosuspend related functionality
-+ */
-+
-+int
-+vchiq_videocore_wanted(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ if (!arm_state)
-+ /* autosuspend not supported - always return wanted */
-+ return 1;
-+ else if (arm_state->blocked_count)
-+ return 1;
-+ else if (!arm_state->videocore_use_count)
-+ /* usage count zero - check for override unless we're forcing */
-+ if (arm_state->resume_blocked)
-+ return 0;
-+ else
-+ return vchiq_platform_videocore_wanted(state);
-+ else
-+ /* non-zero usage count - videocore still required */
-+ return 1;
-+}
-+
-+static VCHIQ_STATUS_T
-+vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header,
-+ VCHIQ_SERVICE_HANDLE_T service_user,
-+ void *bulk_user)
-+{
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s callback reason %d", __func__, reason);
-+ return 0;
-+}
-+
-+static int
-+vchiq_keepalive_thread_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_INSTANCE_T instance;
-+ VCHIQ_SERVICE_HANDLE_T ka_handle;
-+
-+ VCHIQ_SERVICE_PARAMS_T params = {
-+ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'),
-+ .callback = vchiq_keepalive_vchiq_callback,
-+ .version = KEEPALIVE_VER,
-+ .version_min = KEEPALIVE_VER_MIN
-+ };
-+
-+ status = vchiq_initialise(&instance);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_initialise failed %d", __func__, status);
-+ goto exit;
-+ }
-+
-+ status = vchiq_connect(instance);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_connect failed %d", __func__, status);
-+ goto shutdown;
-+ }
-+
-+ status = vchiq_add_service(instance, &params, &ka_handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_open_service failed %d", __func__, status);
-+ goto shutdown;
-+ }
-+
-+ while (1) {
-+ long rc = 0, uc = 0;
-+ if (wait_for_completion_interruptible(&arm_state->ka_evt)
-+ != 0) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s interrupted", __func__);
-+ flush_signals(current);
-+ continue;
-+ }
-+
-+ /* read and clear counters. Do release_count then use_count to
-+ * prevent getting more releases than uses */
-+ rc = atomic_xchg(&arm_state->ka_release_count, 0);
-+ uc = atomic_xchg(&arm_state->ka_use_count, 0);
-+
-+ /* Call use/release service the requisite number of times.
-+ * Process use before release so use counts don't go negative */
-+ while (uc--) {
-+ atomic_inc(&arm_state->ka_use_ack_count);
-+ status = vchiq_use_service(ka_handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_use_service error %d",
-+ __func__, status);
-+ }
-+ }
-+ while (rc--) {
-+ status = vchiq_release_service(ka_handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s vchiq_release_service error %d",
-+ __func__, status);
-+ }
-+ }
-+ }
-+
-+shutdown:
-+ vchiq_shutdown(instance);
-+exit:
-+ return 0;
-+}
-+
-+
-+
-+VCHIQ_STATUS_T
-+vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (arm_state) {
-+ rwlock_init(&arm_state->susp_res_lock);
-+
-+ init_completion(&arm_state->ka_evt);
-+ atomic_set(&arm_state->ka_use_count, 0);
-+ atomic_set(&arm_state->ka_use_ack_count, 0);
-+ atomic_set(&arm_state->ka_release_count, 0);
-+
-+ init_completion(&arm_state->vc_suspend_complete);
-+
-+ init_completion(&arm_state->vc_resume_complete);
-+ /* Initialise to 'done' state. We only want to block on resume
-+ * completion while videocore is suspended. */
-+ set_resume_state(arm_state, VC_RESUME_RESUMED);
-+
-+ init_completion(&arm_state->resume_blocker);
-+ /* Initialise to 'done' state. We only want to block on this
-+ * completion while resume is blocked */
-+ complete_all(&arm_state->resume_blocker);
-+
-+ init_completion(&arm_state->blocked_blocker);
-+ /* Initialise to 'done' state. We only want to block on this
-+ * completion while things are waiting on the resume blocker */
-+ complete_all(&arm_state->blocked_blocker);
-+
-+ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS;
-+ arm_state->suspend_timer_running = 0;
-+ init_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer.data = (unsigned long)(state);
-+ arm_state->suspend_timer.function = suspend_timer_callback;
-+
-+ arm_state->first_connect = 0;
-+
-+ }
-+ return status;
-+}
-+
-+/*
-+** Functions to modify the state variables;
-+** set_suspend_state
-+** set_resume_state
-+**
-+** There are more state variables than we might like, so ensure they remain in
-+** step. Suspend and resume state are maintained separately, since most of
-+** these state machines can operate independently. However, there are a few
-+** states where state transitions in one state machine cause a reset to the
-+** other state machine. In addition, there are some completion events which
-+** need to occur on state machine reset and end-state(s), so these are also
-+** dealt with in these functions.
-+**
-+** In all states we set the state variable according to the input, but in some
-+** cases we perform additional steps outlined below;
-+**
-+** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time.
-+** The suspend completion is completed after any suspend
-+** attempt. When we reset the state machine we also reset
-+** the completion. This reset occurs when videocore is
-+** resumed, and also if we initiate suspend after a suspend
-+** failure.
-+**
-+** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for
-+** suspend - ie from this point on we must try to suspend
-+** before resuming can occur. We therefore also reset the
-+** resume state machine to VC_RESUME_IDLE in this state.
-+**
-+** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call
-+** complete_all on the suspend completion to notify
-+** anything waiting for suspend to happen.
-+**
-+** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also
-+** initiate resume, so no need to alter resume state.
-+** We call complete_all on the suspend completion to notify
-+** of suspend rejection.
-+**
-+** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the
-+** suspend completion and reset the resume state machine.
-+**
-+** VC_RESUME_IDLE - Initialise the resume completion at the same time. The
-+** resume completion is in it's 'done' state whenever
-+** videcore is running. Therfore, the VC_RESUME_IDLE state
-+** implies that videocore is suspended.
-+** Hence, any thread which needs to wait until videocore is
-+** running can wait on this completion - it will only block
-+** if videocore is suspended.
-+**
-+** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running.
-+** Call complete_all on the resume completion to unblock
-+** any threads waiting for resume. Also reset the suspend
-+** state machine to it's idle state.
-+**
-+** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists.
-+*/
-+
-+void
-+set_suspend_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_suspend_status new_state)
-+{
-+ /* set the state in all cases */
-+ arm_state->vc_suspend_state = new_state;
-+
-+ /* state specific additional actions */
-+ switch (new_state) {
-+ case VC_SUSPEND_FORCE_CANCELED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ break;
-+ case VC_SUSPEND_REJECTED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ break;
-+ case VC_SUSPEND_FAILED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ arm_state->vc_resume_state = VC_RESUME_RESUMED;
-+ complete_all(&arm_state->vc_resume_complete);
-+ break;
-+ case VC_SUSPEND_IDLE:
-+ reinit_completion(&arm_state->vc_suspend_complete);
-+ break;
-+ case VC_SUSPEND_REQUESTED:
-+ break;
-+ case VC_SUSPEND_IN_PROGRESS:
-+ set_resume_state(arm_state, VC_RESUME_IDLE);
-+ break;
-+ case VC_SUSPEND_SUSPENDED:
-+ complete_all(&arm_state->vc_suspend_complete);
-+ break;
-+ default:
-+ BUG();
-+ break;
-+ }
-+}
-+
-+void
-+set_resume_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_resume_status new_state)
-+{
-+ /* set the state in all cases */
-+ arm_state->vc_resume_state = new_state;
-+
-+ /* state specific additional actions */
-+ switch (new_state) {
-+ case VC_RESUME_FAILED:
-+ break;
-+ case VC_RESUME_IDLE:
-+ reinit_completion(&arm_state->vc_resume_complete);
-+ break;
-+ case VC_RESUME_REQUESTED:
-+ break;
-+ case VC_RESUME_IN_PROGRESS:
-+ break;
-+ case VC_RESUME_RESUMED:
-+ complete_all(&arm_state->vc_resume_complete);
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+ break;
-+ default:
-+ BUG();
-+ break;
-+ }
-+}
-+
-+
-+/* should be called with the write lock held */
-+inline void
-+start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ del_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer.expires = jiffies +
-+ msecs_to_jiffies(arm_state->
-+ suspend_timer_timeout);
-+ add_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer_running = 1;
-+}
-+
-+/* should be called with the write lock held */
-+static inline void
-+stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ if (arm_state->suspend_timer_running) {
-+ del_timer(&arm_state->suspend_timer);
-+ arm_state->suspend_timer_running = 0;
-+ }
-+}
-+
-+static inline int
-+need_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) &&
-+ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) &&
-+ vchiq_videocore_wanted(state);
-+}
-+
-+static int
-+block_resume(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ int status = VCHIQ_SUCCESS;
-+ const unsigned long timeout_val =
-+ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS);
-+ int resume_count = 0;
-+
-+ /* Allow any threads which were blocked by the last force suspend to
-+ * complete if they haven't already. Only give this one shot; if
-+ * blocked_count is incremented after blocked_blocker is completed
-+ * (which only happens when blocked_count hits 0) then those threads
-+ * will have to wait until next time around */
-+ if (arm_state->blocked_count) {
-+ reinit_completion(&arm_state->blocked_blocker);
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously "
-+ "blocked clients", __func__);
-+ if (wait_for_completion_interruptible_timeout(
-+ &arm_state->blocked_blocker, timeout_val)
-+ <= 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s wait for "
-+ "previously blocked clients failed" , __func__);
-+ status = VCHIQ_ERROR;
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked "
-+ "clients resumed", __func__);
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ }
-+
-+ /* We need to wait for resume to complete if it's in process */
-+ while (arm_state->vc_resume_state != VC_RESUME_RESUMED &&
-+ arm_state->vc_resume_state > VC_RESUME_IDLE) {
-+ if (resume_count > 1) {
-+ status = VCHIQ_ERROR;
-+ vchiq_log_error(vchiq_susp_log_level, "%s waited too "
-+ "many times for resume" , __func__);
-+ goto out;
-+ }
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ vchiq_log_info(vchiq_susp_log_level, "%s wait for resume",
-+ __func__);
-+ if (wait_for_completion_interruptible_timeout(
-+ &arm_state->vc_resume_complete, timeout_val)
-+ <= 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s wait for "
-+ "resume failed (%s)", __func__,
-+ resume_state_names[arm_state->vc_resume_state +
-+ VC_RESUME_NUM_OFFSET]);
-+ status = VCHIQ_ERROR;
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s resumed", __func__);
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ resume_count++;
-+ }
-+ reinit_completion(&arm_state->resume_blocker);
-+ arm_state->resume_blocked = 1;
-+
-+out:
-+ return status;
-+}
-+
-+static inline void
-+unblock_resume(VCHIQ_ARM_STATE_T *arm_state)
-+{
-+ complete_all(&arm_state->resume_blocker);
-+ arm_state->resume_blocked = 0;
-+}
-+
-+/* Initiate suspend via slot handler. Should be called with the write lock
-+ * held */
-+VCHIQ_STATUS_T
-+vchiq_arm_vcsuspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+ status = VCHIQ_SUCCESS;
-+
-+
-+ switch (arm_state->vc_suspend_state) {
-+ case VC_SUSPEND_REQUESTED:
-+ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already "
-+ "requested", __func__);
-+ break;
-+ case VC_SUSPEND_IN_PROGRESS:
-+ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in "
-+ "progress", __func__);
-+ break;
-+
-+ default:
-+ /* We don't expect to be in other states, so log but continue
-+ * anyway */
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s unexpected suspend state %s", __func__,
-+ suspend_state_names[arm_state->vc_suspend_state +
-+ VC_SUSPEND_NUM_OFFSET]);
-+ /* fall through */
-+ case VC_SUSPEND_REJECTED:
-+ case VC_SUSPEND_FAILED:
-+ /* Ensure any idle state actions have been run */
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+ /* fall through */
-+ case VC_SUSPEND_IDLE:
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: suspending", __func__);
-+ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED);
-+ /* kick the slot handler thread to initiate suspend */
-+ request_poll(state, NULL, 0);
-+ break;
-+ }
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status);
-+ return status;
-+}
-+
-+void
-+vchiq_platform_check_suspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int susp = 0;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED &&
-+ arm_state->vc_resume_state == VC_RESUME_RESUMED) {
-+ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS);
-+ susp = 1;
-+ }
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (susp)
-+ vchiq_platform_suspend(state);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return;
-+}
-+
-+
-+static void
-+output_timeout_error(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ char service_err[50] = "";
-+ int vc_use_count = arm_state->videocore_use_count;
-+ int active_services = state->unused_service;
-+ int i;
-+
-+ if (!arm_state->videocore_use_count) {
-+ snprintf(service_err, 50, " Videocore usecount is 0");
-+ goto output_msg;
-+ }
-+ for (i = 0; i < active_services; i++) {
-+ VCHIQ_SERVICE_T *service_ptr = state->services[i];
-+ if (service_ptr && service_ptr->service_use_count &&
-+ (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) {
-+ snprintf(service_err, 50, " %c%c%c%c(%d) service has "
-+ "use count %d%s", VCHIQ_FOURCC_AS_4CHARS(
-+ service_ptr->base.fourcc),
-+ service_ptr->client_id,
-+ service_ptr->service_use_count,
-+ service_ptr->service_use_count ==
-+ vc_use_count ? "" : " (+ more)");
-+ break;
-+ }
-+ }
-+
-+output_msg:
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "timed out waiting for vc suspend (%d).%s",
-+ arm_state->autosuspend_override, service_err);
-+
-+}
-+
-+/* Try to get videocore into suspended state, regardless of autosuspend state.
-+** We don't actually force suspend, since videocore may get into a bad state
-+** if we force suspend at a bad time. Instead, we wait for autosuspend to
-+** determine a good point to suspend. If this doesn't happen within 100ms we
-+** report failure.
-+**
-+** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if
-+** videocore failed to suspend in time or VCHIQ_ERROR if interrupted.
-+*/
-+VCHIQ_STATUS_T
-+vchiq_arm_force_suspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ long rc = 0;
-+ int repeat = -1;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+
-+ status = block_resume(arm_state);
-+ if (status != VCHIQ_SUCCESS)
-+ goto unlock;
-+ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) {
-+ /* Already suspended - just block resume and exit */
-+ vchiq_log_info(vchiq_susp_log_level, "%s already suspended",
-+ __func__);
-+ status = VCHIQ_SUCCESS;
-+ goto unlock;
-+ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) {
-+ /* initiate suspend immediately in the case that we're waiting
-+ * for the timeout */
-+ stop_suspend_timer(arm_state);
-+ if (!vchiq_videocore_wanted(state)) {
-+ vchiq_log_info(vchiq_susp_log_level, "%s videocore "
-+ "idle, initiating suspend", __func__);
-+ status = vchiq_arm_vcsuspend(state);
-+ } else if (arm_state->autosuspend_override <
-+ FORCE_SUSPEND_FAIL_MAX) {
-+ vchiq_log_info(vchiq_susp_log_level, "%s letting "
-+ "videocore go idle", __func__);
-+ status = VCHIQ_SUCCESS;
-+ } else {
-+ vchiq_log_warning(vchiq_susp_log_level, "%s failed too "
-+ "many times - attempting suspend", __func__);
-+ status = vchiq_arm_vcsuspend(state);
-+ }
-+ } else {
-+ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend "
-+ "in progress - wait for completion", __func__);
-+ status = VCHIQ_SUCCESS;
-+ }
-+
-+ /* Wait for suspend to happen due to system idle (not forced..) */
-+ if (status != VCHIQ_SUCCESS)
-+ goto unblock_resume;
-+
-+ do {
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ rc = wait_for_completion_interruptible_timeout(
-+ &arm_state->vc_suspend_complete,
-+ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS));
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (rc < 0) {
-+ vchiq_log_warning(vchiq_susp_log_level, "%s "
-+ "interrupted waiting for suspend", __func__);
-+ status = VCHIQ_ERROR;
-+ goto unblock_resume;
-+ } else if (rc == 0) {
-+ if (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) {
-+ /* Repeat timeout once if in progress */
-+ if (repeat < 0) {
-+ repeat = 1;
-+ continue;
-+ }
-+ }
-+ arm_state->autosuspend_override++;
-+ output_timeout_error(state);
-+
-+ status = VCHIQ_RETRY;
-+ goto unblock_resume;
-+ }
-+ } while (0 < (repeat--));
-+
-+ /* Check and report state in case we need to abort ARM suspend */
-+ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) {
-+ status = VCHIQ_RETRY;
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s videocore suspend failed (state %s)", __func__,
-+ suspend_state_names[arm_state->vc_suspend_state +
-+ VC_SUSPEND_NUM_OFFSET]);
-+ /* Reset the state only if it's still in an error state.
-+ * Something could have already initiated another suspend. */
-+ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE)
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+
-+ goto unblock_resume;
-+ }
-+
-+ /* successfully suspended - unlock and exit */
-+ goto unlock;
-+
-+unblock_resume:
-+ /* all error states need to unblock resume before exit */
-+ unblock_resume(arm_state);
-+
-+unlock:
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status);
-+ return status;
-+}
-+
-+void
-+vchiq_check_suspend(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED &&
-+ arm_state->first_connect &&
-+ !vchiq_videocore_wanted(state)) {
-+ vchiq_arm_vcsuspend(state);
-+ }
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return;
-+}
-+
-+
-+int
-+vchiq_arm_allow_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int resume = 0;
-+ int ret = -1;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ unblock_resume(arm_state);
-+ resume = vchiq_check_resume(state);
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (resume) {
-+ if (wait_for_completion_interruptible(
-+ &arm_state->vc_resume_complete) < 0) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s interrupted", __func__);
-+ /* failed, cannot accurately derive suspend
-+ * state, so exit early. */
-+ goto out;
-+ }
-+ }
-+
-+ read_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: Videocore remains suspended", __func__);
-+ } else {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: Videocore resumed", __func__);
-+ ret = 0;
-+ }
-+ read_unlock_bh(&arm_state->susp_res_lock);
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
-+ return ret;
-+}
-+
-+/* This function should be called with the write lock held */
-+int
-+vchiq_check_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int resume = 0;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ if (need_resume(state)) {
-+ set_resume_state(arm_state, VC_RESUME_REQUESTED);
-+ request_poll(state, NULL, 0);
-+ resume = 1;
-+ }
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return resume;
-+}
-+
-+void
-+vchiq_platform_check_resume(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int res = 0;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (arm_state->wake_address == 0) {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: already awake", __func__);
-+ goto unlock;
-+ }
-+ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s: already resuming", __func__);
-+ goto unlock;
-+ }
-+
-+ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) {
-+ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS);
-+ res = 1;
-+ } else
-+ vchiq_log_trace(vchiq_susp_log_level,
-+ "%s: not resuming (resume state %s)", __func__,
-+ resume_state_names[arm_state->vc_resume_state +
-+ VC_RESUME_NUM_OFFSET]);
-+
-+unlock:
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (res)
-+ vchiq_platform_resume(state);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__);
-+ return;
-+
-+}
-+
-+
-+
-+VCHIQ_STATUS_T
-+vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ enum USE_TYPE_E use_type)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS;
-+ char entity[16];
-+ int *entity_uc;
-+ int local_uc, local_entity_uc;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ if (use_type == USE_TYPE_VCHIQ) {
-+ sprintf(entity, "VCHIQ: ");
-+ entity_uc = &arm_state->peer_use_count;
-+ } else if (service) {
-+ sprintf(entity, "%c%c%c%c:%03d",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->client_id);
-+ entity_uc = &service->service_use_count;
-+ } else {
-+ vchiq_log_error(vchiq_susp_log_level, "%s null service "
-+ "ptr", __func__);
-+ ret = VCHIQ_ERROR;
-+ goto out;
-+ }
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ while (arm_state->resume_blocked) {
-+ /* If we call 'use' while force suspend is waiting for suspend,
-+ * then we're about to block the thread which the force is
-+ * waiting to complete, so we're bound to just time out. In this
-+ * case, set the suspend state such that the wait will be
-+ * canceled, so we can complete as quickly as possible. */
-+ if (arm_state->resume_blocked && arm_state->vc_suspend_state ==
-+ VC_SUSPEND_IDLE) {
-+ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED);
-+ break;
-+ }
-+ /* If suspend is already in progress then we need to block */
-+ if (!try_wait_for_completion(&arm_state->resume_blocker)) {
-+ /* Indicate that there are threads waiting on the resume
-+ * blocker. These need to be allowed to complete before
-+ * a _second_ call to force suspend can complete,
-+ * otherwise low priority threads might never actually
-+ * continue */
-+ arm_state->blocked_count++;
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s resume "
-+ "blocked - waiting...", __func__, entity);
-+ if (wait_for_completion_killable(
-+ &arm_state->resume_blocker) != 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s %s "
-+ "wait for resume blocker interrupted",
-+ __func__, entity);
-+ ret = VCHIQ_ERROR;
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ arm_state->blocked_count--;
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s resume "
-+ "unblocked", __func__, entity);
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (--arm_state->blocked_count == 0)
-+ complete_all(&arm_state->blocked_blocker);
-+ }
-+ }
-+
-+ stop_suspend_timer(arm_state);
-+
-+ local_uc = ++arm_state->videocore_use_count;
-+ local_entity_uc = ++(*entity_uc);
-+
-+ /* If there's a pending request which hasn't yet been serviced then
-+ * just clear it. If we're past VC_SUSPEND_REQUESTED state then
-+ * vc_resume_complete will block until we either resume or fail to
-+ * suspend */
-+ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED)
-+ set_suspend_state(arm_state, VC_SUSPEND_IDLE);
-+
-+ if ((use_type != USE_TYPE_SERVICE_NO_RESUME) && need_resume(state)) {
-+ set_resume_state(arm_state, VC_RESUME_REQUESTED);
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d",
-+ __func__, entity, local_entity_uc, local_uc);
-+ request_poll(state, NULL, 0);
-+ } else
-+ vchiq_log_trace(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d",
-+ __func__, entity, *entity_uc, local_uc);
-+
-+
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+ /* Completion is in a done state when we're not suspended, so this won't
-+ * block for the non-suspended case. */
-+ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) {
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume",
-+ __func__, entity);
-+ if (wait_for_completion_killable(
-+ &arm_state->vc_resume_complete) != 0) {
-+ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for "
-+ "resume interrupted", __func__, entity);
-+ ret = VCHIQ_ERROR;
-+ goto out;
-+ }
-+ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__,
-+ entity);
-+ }
-+
-+ if (ret == VCHIQ_SUCCESS) {
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0);
-+ while (ack_cnt && (status == VCHIQ_SUCCESS)) {
-+ /* Send the use notify to videocore */
-+ status = vchiq_send_remote_use_active(state);
-+ if (status == VCHIQ_SUCCESS)
-+ ack_cnt--;
-+ else
-+ atomic_add(ack_cnt,
-+ &arm_state->ka_use_ack_count);
-+ }
-+ }
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
-+ return ret;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS;
-+ char entity[16];
-+ int *entity_uc;
-+ int local_uc, local_entity_uc;
-+
-+ if (!arm_state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ if (service) {
-+ sprintf(entity, "%c%c%c%c:%03d",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->client_id);
-+ entity_uc = &service->service_use_count;
-+ } else {
-+ sprintf(entity, "PEER: ");
-+ entity_uc = &arm_state->peer_use_count;
-+ }
-+
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (!arm_state->videocore_use_count || !(*entity_uc)) {
-+ /* Don't use BUG_ON - don't allow user thread to crash kernel */
-+ WARN_ON(!arm_state->videocore_use_count);
-+ WARN_ON(!(*entity_uc));
-+ ret = VCHIQ_ERROR;
-+ goto unlock;
-+ }
-+ local_uc = --arm_state->videocore_use_count;
-+ local_entity_uc = --(*entity_uc);
-+
-+ if (!vchiq_videocore_wanted(state)) {
-+ if (vchiq_platform_use_suspend_timer() &&
-+ !arm_state->resume_blocked) {
-+ /* Only use the timer if we're not trying to force
-+ * suspend (=> resume_blocked) */
-+ start_suspend_timer(arm_state);
-+ } else {
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d - suspending",
-+ __func__, entity, *entity_uc,
-+ arm_state->videocore_use_count);
-+ vchiq_arm_vcsuspend(state);
-+ }
-+ } else
-+ vchiq_log_trace(vchiq_susp_log_level,
-+ "%s %s count %d, state count %d",
-+ __func__, entity, *entity_uc,
-+ arm_state->videocore_use_count);
-+
-+unlock:
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+
-+out:
-+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret);
-+ return ret;
-+}
-+
-+void
-+vchiq_on_remote_use(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+ atomic_inc(&arm_state->ka_use_count);
-+ complete(&arm_state->ka_evt);
-+}
-+
-+void
-+vchiq_on_remote_release(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+ atomic_inc(&arm_state->ka_release_count);
-+ complete(&arm_state->ka_evt);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_use_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_release_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ return vchiq_release_internal(service->state, service);
-+}
-+
-+VCHIQ_DEBUGFS_NODE_T *
-+vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance)
-+{
-+ return &instance->debugfs_node;
-+}
-+
-+int
-+vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int use_count = 0, i;
-+ i = 0;
-+ while ((service = next_service_by_instance(instance->state,
-+ instance, &i)) != NULL) {
-+ use_count += service->service_use_count;
-+ unlock_service(service);
-+ }
-+ return use_count;
-+}
-+
-+int
-+vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance)
-+{
-+ return instance->pid;
-+}
-+
-+int
-+vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance)
-+{
-+ return instance->trace;
-+}
-+
-+void
-+vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+ i = 0;
-+ while ((service = next_service_by_instance(instance->state,
-+ instance, &i)) != NULL) {
-+ service->trace = trace;
-+ unlock_service(service);
-+ }
-+ instance->trace = (trace != 0);
-+}
-+
-+static void suspend_timer_callback(unsigned long context)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context;
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ if (!arm_state)
-+ goto out;
-+ vchiq_log_info(vchiq_susp_log_level,
-+ "%s - suspend timer expired - check suspend", __func__);
-+ vchiq_check_suspend(state);
-+out:
-+ return;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_use_service_no_resume(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ if (service) {
-+ ret = vchiq_use_internal(service->state, service,
-+ USE_TYPE_SERVICE_NO_RESUME);
-+ unlock_service(service);
-+ }
-+ return ret;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ if (service) {
-+ ret = vchiq_use_internal(service->state, service,
-+ USE_TYPE_SERVICE);
-+ unlock_service(service);
-+ }
-+ return ret;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ if (service) {
-+ ret = vchiq_release_internal(service->state, service);
-+ unlock_service(service);
-+ }
-+ return ret;
-+}
-+
-+void
-+vchiq_dump_service_use_state(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ int i, j = 0;
-+ /* Only dump 64 services */
-+ static const int local_max_services = 64;
-+ /* If there's more than 64 services, only dump ones with
-+ * non-zero counts */
-+ int only_nonzero = 0;
-+ static const char *nz = "<-- preventing suspend";
-+
-+ enum vc_suspend_status vc_suspend_state;
-+ enum vc_resume_status vc_resume_state;
-+ int peer_count;
-+ int vc_use_count;
-+ int active_services;
-+ struct service_data_struct {
-+ int fourcc;
-+ int clientid;
-+ int use_count;
-+ } service_data[local_max_services];
-+
-+ if (!arm_state)
-+ return;
-+
-+ read_lock_bh(&arm_state->susp_res_lock);
-+ vc_suspend_state = arm_state->vc_suspend_state;
-+ vc_resume_state = arm_state->vc_resume_state;
-+ peer_count = arm_state->peer_use_count;
-+ vc_use_count = arm_state->videocore_use_count;
-+ active_services = state->unused_service;
-+ if (active_services > local_max_services)
-+ only_nonzero = 1;
-+
-+ for (i = 0; (i < active_services) && (j < local_max_services); i++) {
-+ VCHIQ_SERVICE_T *service_ptr = state->services[i];
-+ if (!service_ptr)
-+ continue;
-+
-+ if (only_nonzero && !service_ptr->service_use_count)
-+ continue;
-+
-+ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) {
-+ service_data[j].fourcc = service_ptr->base.fourcc;
-+ service_data[j].clientid = service_ptr->client_id;
-+ service_data[j++].use_count = service_ptr->
-+ service_use_count;
-+ }
-+ }
-+
-+ read_unlock_bh(&arm_state->susp_res_lock);
-+
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "-- Videcore suspend state: %s --",
-+ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]);
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "-- Videcore resume state: %s --",
-+ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]);
-+
-+ if (only_nonzero)
-+ vchiq_log_warning(vchiq_susp_log_level, "Too many active "
-+ "services (%d). Only dumping up to first %d services "
-+ "with non-zero use-count", active_services,
-+ local_max_services);
-+
-+ for (i = 0; i < j; i++) {
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "----- %c%c%c%c:%d service count %d %s",
-+ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc),
-+ service_data[i].clientid,
-+ service_data[i].use_count,
-+ service_data[i].use_count ? nz : "");
-+ }
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "----- VCHIQ use count count %d", peer_count);
-+ vchiq_log_warning(vchiq_susp_log_level,
-+ "--- Overall vchiq instance use count %d", vc_use_count);
-+
-+ vchiq_dump_platform_use_state(state);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_check_service(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state;
-+ VCHIQ_STATUS_T ret = VCHIQ_ERROR;
-+
-+ if (!service || !service->state)
-+ goto out;
-+
-+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
-+
-+ arm_state = vchiq_platform_get_arm_state(service->state);
-+
-+ read_lock_bh(&arm_state->susp_res_lock);
-+ if (service->service_use_count)
-+ ret = VCHIQ_SUCCESS;
-+ read_unlock_bh(&arm_state->susp_res_lock);
-+
-+ if (ret == VCHIQ_ERROR) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "%s ERROR - %c%c%c%c:%d service count %d, "
-+ "state count %d, videocore suspend state %s", __func__,
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->client_id, service->service_use_count,
-+ arm_state->videocore_use_count,
-+ suspend_state_names[arm_state->vc_suspend_state +
-+ VC_SUSPEND_NUM_OFFSET]);
-+ vchiq_dump_service_use_state(service->state);
-+ }
-+out:
-+ return ret;
-+}
-+
-+/* stub functions */
-+void vchiq_on_remote_use_active(VCHIQ_STATE_T *state)
-+{
-+ (void)state;
-+}
-+
-+void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state,
-+ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate)
-+{
-+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state);
-+ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id,
-+ get_conn_state_name(oldstate), get_conn_state_name(newstate));
-+ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) {
-+ write_lock_bh(&arm_state->susp_res_lock);
-+ if (!arm_state->first_connect) {
-+ char threadname[10];
-+ arm_state->first_connect = 1;
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ snprintf(threadname, sizeof(threadname), "VCHIQka-%d",
-+ state->id);
-+ arm_state->ka_thread = kthread_create(
-+ &vchiq_keepalive_thread_func,
-+ (void *)state,
-+ threadname);
-+ if (arm_state->ka_thread == NULL) {
-+ vchiq_log_error(vchiq_susp_log_level,
-+ "vchiq: FATAL: couldn't create thread %s",
-+ threadname);
-+ } else {
-+ wake_up_process(arm_state->ka_thread);
-+ }
-+ } else
-+ write_unlock_bh(&arm_state->susp_res_lock);
-+ }
-+}
-+
-+
-+/****************************************************************************
-+*
-+* vchiq_init - called when the module is loaded.
-+*
-+***************************************************************************/
-+
-+static int __init
-+vchiq_init(void)
-+{
-+ int err;
-+ void *ptr_err;
-+
-+ /* create debugfs entries */
-+ err = vchiq_debugfs_init();
-+ if (err != 0)
-+ goto failed_debugfs_init;
-+
-+ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME);
-+ if (err != 0) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to allocate device number");
-+ goto failed_alloc_chrdev;
-+ }
-+ cdev_init(&vchiq_cdev, &vchiq_fops);
-+ vchiq_cdev.owner = THIS_MODULE;
-+ err = cdev_add(&vchiq_cdev, vchiq_devid, 1);
-+ if (err != 0) {
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "Unable to register device");
-+ goto failed_cdev_add;
-+ }
-+
-+ /* create sysfs entries */
-+ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME);
-+ ptr_err = vchiq_class;
-+ if (IS_ERR(ptr_err))
-+ goto failed_class_create;
-+
-+ vchiq_dev = device_create(vchiq_class, NULL,
-+ vchiq_devid, NULL, "vchiq");
-+ ptr_err = vchiq_dev;
-+ if (IS_ERR(ptr_err))
-+ goto failed_device_create;
-+
-+ err = vchiq_platform_init(&g_state);
-+ if (err != 0)
-+ goto failed_platform_init;
-+
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "vchiq: initialised - version %d (min %d), device %d.%d",
-+ VCHIQ_VERSION, VCHIQ_VERSION_MIN,
-+ MAJOR(vchiq_devid), MINOR(vchiq_devid));
-+
-+ return 0;
-+
-+failed_platform_init:
-+ device_destroy(vchiq_class, vchiq_devid);
-+failed_device_create:
-+ class_destroy(vchiq_class);
-+failed_class_create:
-+ cdev_del(&vchiq_cdev);
-+ err = PTR_ERR(ptr_err);
-+failed_cdev_add:
-+ unregister_chrdev_region(vchiq_devid, 1);
-+failed_alloc_chrdev:
-+ vchiq_debugfs_deinit();
-+failed_debugfs_init:
-+ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq");
-+ return err;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_exit - called when the module is unloaded.
-+*
-+***************************************************************************/
-+
-+static void __exit
-+vchiq_exit(void)
-+{
-+ vchiq_platform_exit(&g_state);
-+ device_destroy(vchiq_class, vchiq_devid);
-+ class_destroy(vchiq_class);
-+ cdev_del(&vchiq_cdev);
-+ unregister_chrdev_region(vchiq_devid, 1);
-+}
-+
-+module_init(vchiq_init);
-+module_exit(vchiq_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,223 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_ARM_H
-+#define VCHIQ_ARM_H
-+
-+#include <linux/mutex.h>
-+#include <linux/semaphore.h>
-+#include <linux/atomic.h>
-+#include "vchiq_core.h"
-+#include "vchiq_debugfs.h"
-+
-+
-+enum vc_suspend_status {
-+ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */
-+ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */
-+ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */
-+ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */
-+ VC_SUSPEND_REQUESTED, /* User has requested suspend */
-+ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */
-+ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */
-+};
-+
-+enum vc_resume_status {
-+ VC_RESUME_FAILED = -1, /* Videocore resume failed */
-+ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */
-+ VC_RESUME_REQUESTED, /* User has requested resume */
-+ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */
-+ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */
-+};
-+
-+
-+enum USE_TYPE_E {
-+ USE_TYPE_SERVICE,
-+ USE_TYPE_SERVICE_NO_RESUME,
-+ USE_TYPE_VCHIQ
-+};
-+
-+
-+
-+typedef struct vchiq_arm_state_struct {
-+ /* Keepalive-related data */
-+ struct task_struct *ka_thread;
-+ struct completion ka_evt;
-+ atomic_t ka_use_count;
-+ atomic_t ka_use_ack_count;
-+ atomic_t ka_release_count;
-+
-+ struct completion vc_suspend_complete;
-+ struct completion vc_resume_complete;
-+
-+ rwlock_t susp_res_lock;
-+ enum vc_suspend_status vc_suspend_state;
-+ enum vc_resume_status vc_resume_state;
-+
-+ unsigned int wake_address;
-+
-+ struct timer_list suspend_timer;
-+ int suspend_timer_timeout;
-+ int suspend_timer_running;
-+
-+ /* Global use count for videocore.
-+ ** This is equal to the sum of the use counts for all services. When
-+ ** this hits zero the videocore suspend procedure will be initiated.
-+ */
-+ int videocore_use_count;
-+
-+ /* Use count to track requests from videocore peer.
-+ ** This use count is not associated with a service, so needs to be
-+ ** tracked separately with the state.
-+ */
-+ int peer_use_count;
-+
-+ /* Flag to indicate whether resume is blocked. This happens when the
-+ ** ARM is suspending
-+ */
-+ struct completion resume_blocker;
-+ int resume_blocked;
-+ struct completion blocked_blocker;
-+ int blocked_count;
-+
-+ int autosuspend_override;
-+
-+ /* Flag to indicate that the first vchiq connect has made it through.
-+ ** This means that both sides should be fully ready, and we should
-+ ** be able to suspend after this point.
-+ */
-+ int first_connect;
-+
-+ unsigned long long suspend_start_time;
-+ unsigned long long sleep_start_time;
-+ unsigned long long resume_start_time;
-+ unsigned long long last_wake_time;
-+
-+} VCHIQ_ARM_STATE_T;
-+
-+extern int vchiq_arm_log_level;
-+extern int vchiq_susp_log_level;
-+
-+extern int __init
-+vchiq_platform_init(VCHIQ_STATE_T *state);
-+
-+extern void __exit
-+vchiq_platform_exit(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATE_T *
-+vchiq_get_state(void);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_vcsuspend(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_force_suspend(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_arm_allow_resume(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_vcresume(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state);
-+
-+extern int
-+vchiq_check_resume(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_check_suspend(VCHIQ_STATE_T *state);
-+ VCHIQ_STATUS_T
-+vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_check_service(VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_platform_suspend(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_platform_use_suspend_timer(void);
-+
-+extern void
-+vchiq_dump_platform_use_state(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_dump_service_use_state(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_ARM_STATE_T*
-+vchiq_platform_get_arm_state(VCHIQ_STATE_T *state);
-+
-+extern int
-+vchiq_videocore_wanted(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ enum USE_TYPE_E use_type);
-+extern VCHIQ_STATUS_T
-+vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_DEBUGFS_NODE_T *
-+vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance);
-+
-+extern int
-+vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance);
-+
-+extern int
-+vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance);
-+
-+extern int
-+vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance);
-+
-+extern void
-+vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace);
-+
-+extern void
-+set_suspend_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_suspend_status new_state);
-+
-+extern void
-+set_resume_state(VCHIQ_ARM_STATE_T *arm_state,
-+ enum vc_resume_status new_state);
-+
-+extern void
-+start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state);
-+
-+
-+#endif /* VCHIQ_ARM_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,37 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+const char *vchiq_get_build_hostname(void);
-+const char *vchiq_get_build_version(void);
-+const char *vchiq_get_build_time(void);
-+const char *vchiq_get_build_date(void);
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,69 @@
-+/**
-+ * Copyright (c) 2010-2014 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_CFG_H
-+#define VCHIQ_CFG_H
-+
-+#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I')
-+/* The version of VCHIQ - change with any non-trivial change */
-+#define VCHIQ_VERSION 8
-+/* The minimum compatible version - update to match VCHIQ_VERSION with any
-+** incompatible change */
-+#define VCHIQ_VERSION_MIN 3
-+
-+/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */
-+#define VCHIQ_VERSION_LIB_VERSION 7
-+
-+/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */
-+#define VCHIQ_VERSION_CLOSE_DELIVERED 7
-+
-+/* The version that made it safe to use SYNCHRONOUS mode */
-+#define VCHIQ_VERSION_SYNCHRONOUS_MODE 8
-+
-+#define VCHIQ_MAX_STATES 1
-+#define VCHIQ_MAX_SERVICES 4096
-+#define VCHIQ_MAX_SLOTS 128
-+#define VCHIQ_MAX_SLOTS_PER_SIDE 64
-+
-+#define VCHIQ_NUM_CURRENT_BULKS 32
-+#define VCHIQ_NUM_SERVICE_BULKS 4
-+
-+#ifndef VCHIQ_ENABLE_DEBUG
-+#define VCHIQ_ENABLE_DEBUG 1
-+#endif
-+
-+#ifndef VCHIQ_ENABLE_STATS
-+#define VCHIQ_ENABLE_STATS 1
-+#endif
-+
-+#endif /* VCHIQ_CFG_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,120 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "vchiq_connected.h"
-+#include "vchiq_core.h"
-+#include "vchiq_killable.h"
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+
-+#define MAX_CALLBACKS 10
-+
-+static int g_connected;
-+static int g_num_deferred_callbacks;
-+static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS];
-+static int g_once_init;
-+static struct mutex g_connected_mutex;
-+
-+/****************************************************************************
-+*
-+* Function to initialize our lock.
-+*
-+***************************************************************************/
-+
-+static void connected_init(void)
-+{
-+ if (!g_once_init) {
-+ mutex_init(&g_connected_mutex);
-+ g_once_init = 1;
-+ }
-+}
-+
-+/****************************************************************************
-+*
-+* This function is used to defer initialization until the vchiq stack is
-+* initialized. If the stack is already initialized, then the callback will
-+* be made immediately, otherwise it will be deferred until
-+* vchiq_call_connected_callbacks is called.
-+*
-+***************************************************************************/
-+
-+void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback)
-+{
-+ connected_init();
-+
-+ if (mutex_lock_interruptible(&g_connected_mutex) != 0)
-+ return;
-+
-+ if (g_connected)
-+ /* We're already connected. Call the callback immediately. */
-+
-+ callback();
-+ else {
-+ if (g_num_deferred_callbacks >= MAX_CALLBACKS)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "There already %d callback registered - "
-+ "please increase MAX_CALLBACKS",
-+ g_num_deferred_callbacks);
-+ else {
-+ g_deferred_callback[g_num_deferred_callbacks] =
-+ callback;
-+ g_num_deferred_callbacks++;
-+ }
-+ }
-+ mutex_unlock(&g_connected_mutex);
-+}
-+
-+/****************************************************************************
-+*
-+* This function is called by the vchiq stack once it has been connected to
-+* the videocore and clients can start to use the stack.
-+*
-+***************************************************************************/
-+
-+void vchiq_call_connected_callbacks(void)
-+{
-+ int i;
-+
-+ connected_init();
-+
-+ if (mutex_lock_interruptible(&g_connected_mutex) != 0)
-+ return;
-+
-+ for (i = 0; i < g_num_deferred_callbacks; i++)
-+ g_deferred_callback[i]();
-+
-+ g_num_deferred_callbacks = 0;
-+ g_connected = 1;
-+ mutex_unlock(&g_connected_mutex);
-+}
-+EXPORT_SYMBOL(vchiq_add_connected_callback);
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,50 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_CONNECTED_H
-+#define VCHIQ_CONNECTED_H
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void);
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback);
-+void vchiq_call_connected_callbacks(void);
-+
-+#endif /* VCHIQ_CONNECTED_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,3934 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "vchiq_core.h"
-+#include "vchiq_killable.h"
-+
-+#define VCHIQ_SLOT_HANDLER_STACK 8192
-+
-+#define HANDLE_STATE_SHIFT 12
-+
-+#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index))
-+#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index))
-+#define SLOT_INDEX_FROM_DATA(state, data) \
-+ (((unsigned int)((char *)data - (char *)state->slot_data)) / \
-+ VCHIQ_SLOT_SIZE)
-+#define SLOT_INDEX_FROM_INFO(state, info) \
-+ ((unsigned int)(info - state->slot_info))
-+#define SLOT_QUEUE_INDEX_FROM_POS(pos) \
-+ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE))
-+
-+#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1))
-+
-+#define SRVTRACE_LEVEL(srv) \
-+ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level)
-+#define SRVTRACE_ENABLED(srv, lev) \
-+ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev)))
-+
-+struct vchiq_open_payload {
-+ int fourcc;
-+ int client_id;
-+ short version;
-+ short version_min;
-+};
-+
-+struct vchiq_openack_payload {
-+ short version;
-+};
-+
-+enum
-+{
-+ QMFLAGS_IS_BLOCKING = (1 << 0),
-+ QMFLAGS_NO_MUTEX_LOCK = (1 << 1),
-+ QMFLAGS_NO_MUTEX_UNLOCK = (1 << 2)
-+};
-+
-+/* we require this for consistency between endpoints */
-+vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8);
-+vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T)));
-+vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS));
-+vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS));
-+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES));
-+vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN);
-+
-+/* Run time control of log level, based on KERN_XXX level. */
-+int vchiq_core_log_level = VCHIQ_LOG_DEFAULT;
-+int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT;
-+int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT;
-+
-+static atomic_t pause_bulks_count = ATOMIC_INIT(0);
-+
-+static DEFINE_SPINLOCK(service_spinlock);
-+DEFINE_SPINLOCK(bulk_waiter_spinlock);
-+DEFINE_SPINLOCK(quota_spinlock);
-+
-+VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES];
-+static unsigned int handle_seq;
-+
-+static const char *const srvstate_names[] = {
-+ "FREE",
-+ "HIDDEN",
-+ "LISTENING",
-+ "OPENING",
-+ "OPEN",
-+ "OPENSYNC",
-+ "CLOSESENT",
-+ "CLOSERECVD",
-+ "CLOSEWAIT",
-+ "CLOSED"
-+};
-+
-+static const char *const reason_names[] = {
-+ "SERVICE_OPENED",
-+ "SERVICE_CLOSED",
-+ "MESSAGE_AVAILABLE",
-+ "BULK_TRANSMIT_DONE",
-+ "BULK_RECEIVE_DONE",
-+ "BULK_TRANSMIT_ABORTED",
-+ "BULK_RECEIVE_ABORTED"
-+};
-+
-+static const char *const conn_state_names[] = {
-+ "DISCONNECTED",
-+ "CONNECTING",
-+ "CONNECTED",
-+ "PAUSING",
-+ "PAUSE_SENT",
-+ "PAUSED",
-+ "RESUMING",
-+ "PAUSE_TIMEOUT",
-+ "RESUME_TIMEOUT"
-+};
-+
-+
-+static void
-+release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header);
-+
-+static const char *msg_type_str(unsigned int msg_type)
-+{
-+ switch (msg_type) {
-+ case VCHIQ_MSG_PADDING: return "PADDING";
-+ case VCHIQ_MSG_CONNECT: return "CONNECT";
-+ case VCHIQ_MSG_OPEN: return "OPEN";
-+ case VCHIQ_MSG_OPENACK: return "OPENACK";
-+ case VCHIQ_MSG_CLOSE: return "CLOSE";
-+ case VCHIQ_MSG_DATA: return "DATA";
-+ case VCHIQ_MSG_BULK_RX: return "BULK_RX";
-+ case VCHIQ_MSG_BULK_TX: return "BULK_TX";
-+ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE";
-+ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE";
-+ case VCHIQ_MSG_PAUSE: return "PAUSE";
-+ case VCHIQ_MSG_RESUME: return "RESUME";
-+ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE";
-+ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE";
-+ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE";
-+ }
-+ return "???";
-+}
-+
-+static inline void
-+vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate)
-+{
-+ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s",
-+ service->state->id, service->localport,
-+ srvstate_names[service->srvstate],
-+ srvstate_names[newstate]);
-+ service->srvstate = newstate;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service;
-+
-+ spin_lock(&service_spinlock);
-+ service = handle_to_service(handle);
-+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (service->handle == handle)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid service handle 0x%x", handle);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_service_by_port(VCHIQ_STATE_T *state, int localport)
-+{
-+ VCHIQ_SERVICE_T *service = NULL;
-+ if ((unsigned int)localport <= VCHIQ_PORT_MAX) {
-+ spin_lock(&service_spinlock);
-+ service = state->services[localport];
-+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+ }
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid port %d", localport);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle) {
-+ VCHIQ_SERVICE_T *service;
-+
-+ spin_lock(&service_spinlock);
-+ service = handle_to_service(handle);
-+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (service->handle == handle) &&
-+ (service->instance == instance)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid service handle 0x%x", handle);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle) {
-+ VCHIQ_SERVICE_T *service;
-+
-+ spin_lock(&service_spinlock);
-+ service = handle_to_service(handle);
-+ if (service &&
-+ ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) &&
-+ (service->handle == handle) &&
-+ (service->instance == instance)) {
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ } else
-+ service = NULL;
-+ spin_unlock(&service_spinlock);
-+
-+ if (!service)
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Invalid service handle 0x%x", handle);
-+
-+ return service;
-+}
-+
-+VCHIQ_SERVICE_T *
-+next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance,
-+ int *pidx)
-+{
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int idx = *pidx;
-+
-+ spin_lock(&service_spinlock);
-+ while (idx < state->unused_service) {
-+ VCHIQ_SERVICE_T *srv = state->services[idx++];
-+ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (srv->instance == instance)) {
-+ service = srv;
-+ BUG_ON(service->ref_count == 0);
-+ service->ref_count++;
-+ break;
-+ }
-+ }
-+ spin_unlock(&service_spinlock);
-+
-+ *pidx = idx;
-+
-+ return service;
-+}
-+
-+void
-+lock_service(VCHIQ_SERVICE_T *service)
-+{
-+ spin_lock(&service_spinlock);
-+ BUG_ON(!service || (service->ref_count == 0));
-+ if (service)
-+ service->ref_count++;
-+ spin_unlock(&service_spinlock);
-+}
-+
-+void
-+unlock_service(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ spin_lock(&service_spinlock);
-+ BUG_ON(!service || (service->ref_count == 0));
-+ if (service && service->ref_count) {
-+ service->ref_count--;
-+ if (!service->ref_count) {
-+ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE);
-+ state->services[service->localport] = NULL;
-+ } else
-+ service = NULL;
-+ }
-+ spin_unlock(&service_spinlock);
-+
-+ if (service && service->userdata_term)
-+ service->userdata_term(service->base.userdata);
-+
-+ kfree(service);
-+}
-+
-+int
-+vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ int id;
-+
-+ id = service ? service->client_id : 0;
-+ if (service)
-+ unlock_service(service);
-+
-+ return id;
-+}
-+
-+void *
-+vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service = handle_to_service(handle);
-+
-+ return service ? service->base.userdata : NULL;
-+}
-+
-+int
-+vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_SERVICE_T *service = handle_to_service(handle);
-+
-+ return service ? service->base.fourcc : 0;
-+}
-+
-+static void
-+mark_service_closing_internal(VCHIQ_SERVICE_T *service, int sh_thread)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ VCHIQ_SERVICE_QUOTA_T *service_quota;
-+
-+ service->closing = 1;
-+
-+ /* Synchronise with other threads. */
-+ mutex_lock(&state->recycle_mutex);
-+ mutex_unlock(&state->recycle_mutex);
-+ if (!sh_thread || (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT)) {
-+ /* If we're pausing then the slot_mutex is held until resume
-+ * by the slot handler. Therefore don't try to acquire this
-+ * mutex if we're the slot handler and in the pause sent state.
-+ * We don't need to in this case anyway. */
-+ mutex_lock(&state->slot_mutex);
-+ mutex_unlock(&state->slot_mutex);
-+ }
-+
-+ /* Unblock any sending thread. */
-+ service_quota = &state->service_quotas[service->localport];
-+ up(&service_quota->quota_event);
-+}
-+
-+static void
-+mark_service_closing(VCHIQ_SERVICE_T *service)
-+{
-+ mark_service_closing_internal(service, 0);
-+}
-+
-+static inline VCHIQ_STATUS_T
-+make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header, void *bulk_userdata)
-+{
-+ VCHIQ_STATUS_T status;
-+ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)",
-+ service->state->id, service->localport, reason_names[reason],
-+ (unsigned int)header, (unsigned int)bulk_userdata);
-+ status = service->base.callback(reason, header, service->handle,
-+ bulk_userdata);
-+ if (status == VCHIQ_ERROR) {
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: ignoring ERROR from callback to service %x",
-+ service->state->id, service->handle);
-+ status = VCHIQ_SUCCESS;
-+ }
-+ return status;
-+}
-+
-+inline void
-+vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate)
-+{
-+ VCHIQ_CONNSTATE_T oldstate = state->conn_state;
-+ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id,
-+ conn_state_names[oldstate],
-+ conn_state_names[newstate]);
-+ state->conn_state = newstate;
-+ vchiq_platform_conn_state_changed(state, oldstate, newstate);
-+}
-+
-+static inline void
-+remote_event_create(REMOTE_EVENT_T *event)
-+{
-+ event->armed = 0;
-+ /* Don't clear the 'fired' flag because it may already have been set
-+ ** by the other side. */
-+ sema_init(event->event, 0);
-+}
-+
-+static inline void
-+remote_event_destroy(REMOTE_EVENT_T *event)
-+{
-+ (void)event;
-+}
-+
-+static inline int
-+remote_event_wait(REMOTE_EVENT_T *event)
-+{
-+ if (!event->fired) {
-+ event->armed = 1;
-+ dsb();
-+ if (!event->fired) {
-+ if (down_interruptible(event->event) != 0) {
-+ event->armed = 0;
-+ return 0;
-+ }
-+ }
-+ event->armed = 0;
-+ wmb();
-+ }
-+
-+ event->fired = 0;
-+ return 1;
-+}
-+
-+static inline void
-+remote_event_signal_local(REMOTE_EVENT_T *event)
-+{
-+ event->armed = 0;
-+ up(event->event);
-+}
-+
-+static inline void
-+remote_event_poll(REMOTE_EVENT_T *event)
-+{
-+ if (event->fired && event->armed)
-+ remote_event_signal_local(event);
-+}
-+
-+void
-+remote_event_pollall(VCHIQ_STATE_T *state)
-+{
-+ remote_event_poll(&state->local->sync_trigger);
-+ remote_event_poll(&state->local->sync_release);
-+ remote_event_poll(&state->local->trigger);
-+ remote_event_poll(&state->local->recycle);
-+}
-+
-+/* Round up message sizes so that any space at the end of a slot is always big
-+** enough for a header. This relies on header size being a power of two, which
-+** has been verified earlier by a static assertion. */
-+
-+static inline unsigned int
-+calc_stride(unsigned int size)
-+{
-+ /* Allow room for the header */
-+ size += sizeof(VCHIQ_HEADER_T);
-+
-+ /* Round up */
-+ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T)
-+ - 1);
-+}
-+
-+/* Called by the slot handler thread */
-+static VCHIQ_SERVICE_T *
-+get_listening_service(VCHIQ_STATE_T *state, int fourcc)
-+{
-+ int i;
-+
-+ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID);
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ if (service &&
-+ (service->public_fourcc == fourcc) &&
-+ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
-+ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) &&
-+ (service->remoteport == VCHIQ_PORT_FREE)))) {
-+ lock_service(service);
-+ return service;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+/* Called by the slot handler thread */
-+static VCHIQ_SERVICE_T *
-+get_connected_service(VCHIQ_STATE_T *state, unsigned int port)
-+{
-+ int i;
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN)
-+ && (service->remoteport == port)) {
-+ lock_service(service);
-+ return service;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+inline void
-+request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type)
-+{
-+ uint32_t value;
-+
-+ if (service) {
-+ do {
-+ value = atomic_read(&service->poll_flags);
-+ } while (atomic_cmpxchg(&service->poll_flags, value,
-+ value | (1 << poll_type)) != value);
-+
-+ do {
-+ value = atomic_read(&state->poll_services[
-+ service->localport>>5]);
-+ } while (atomic_cmpxchg(
-+ &state->poll_services[service->localport>>5],
-+ value, value | (1 << (service->localport & 0x1f)))
-+ != value);
-+ }
-+
-+ state->poll_needed = 1;
-+ wmb();
-+
-+ /* ... and ensure the slot handler runs. */
-+ remote_event_signal_local(&state->local->trigger);
-+}
-+
-+/* Called from queue_message, by the slot handler and application threads,
-+** with slot_mutex held */
-+static VCHIQ_HEADER_T *
-+reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking)
-+{
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ int tx_pos = state->local_tx_pos;
-+ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK);
-+
-+ if (space > slot_space) {
-+ VCHIQ_HEADER_T *header;
-+ /* Fill the remaining space with padding */
-+ WARN_ON(state->tx_data == NULL);
-+ header = (VCHIQ_HEADER_T *)
-+ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK));
-+ header->msgid = VCHIQ_MSGID_PADDING;
-+ header->size = slot_space - sizeof(VCHIQ_HEADER_T);
-+
-+ tx_pos += slot_space;
-+ }
-+
-+ /* If necessary, get the next slot. */
-+ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) {
-+ int slot_index;
-+
-+ /* If there is no free slot... */
-+
-+ if (down_trylock(&state->slot_available_event) != 0) {
-+ /* ...wait for one. */
-+
-+ VCHIQ_STATS_INC(state, slot_stalls);
-+
-+ /* But first, flush through the last slot. */
-+ state->local_tx_pos = tx_pos;
-+ local->tx_pos = tx_pos;
-+ remote_event_signal(&state->remote->trigger);
-+
-+ if (!is_blocking ||
-+ (down_interruptible(
-+ &state->slot_available_event) != 0))
-+ return NULL; /* No space available */
-+ }
-+
-+ BUG_ON(tx_pos ==
-+ (state->slot_queue_available * VCHIQ_SLOT_SIZE));
-+
-+ slot_index = local->slot_queue[
-+ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) &
-+ VCHIQ_SLOT_QUEUE_MASK];
-+ state->tx_data =
-+ (char *)SLOT_DATA_FROM_INDEX(state, slot_index);
-+ }
-+
-+ state->local_tx_pos = tx_pos + space;
-+
-+ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK));
-+}
-+
-+/* Called by the recycle thread. */
-+static void
-+process_free_queue(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)];
-+ int slot_queue_available;
-+
-+ /* Use a read memory barrier to ensure that any state that may have
-+ ** been modified by another thread is not masked by stale prefetched
-+ ** values. */
-+ rmb();
-+
-+ /* Find slots which have been freed by the other side, and return them
-+ ** to the available queue. */
-+ slot_queue_available = state->slot_queue_available;
-+
-+ while (slot_queue_available != local->slot_queue_recycle) {
-+ unsigned int pos;
-+ int slot_index = local->slot_queue[slot_queue_available++ &
-+ VCHIQ_SLOT_QUEUE_MASK];
-+ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index);
-+ int data_found = 0;
-+
-+ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x",
-+ state->id, slot_index, (unsigned int)data,
-+ local->slot_queue_recycle, slot_queue_available);
-+
-+ /* Initialise the bitmask for services which have used this
-+ ** slot */
-+ BITSET_ZERO(service_found);
-+
-+ pos = 0;
-+
-+ while (pos < VCHIQ_SLOT_SIZE) {
-+ VCHIQ_HEADER_T *header =
-+ (VCHIQ_HEADER_T *)(data + pos);
-+ int msgid = header->msgid;
-+ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) {
-+ int port = VCHIQ_MSG_SRCPORT(msgid);
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &state->service_quotas[port];
-+ int count;
-+ spin_lock(&quota_spinlock);
-+ count = service_quota->message_use_count;
-+ if (count > 0)
-+ service_quota->message_use_count =
-+ count - 1;
-+ spin_unlock(&quota_spinlock);
-+
-+ if (count == service_quota->message_quota)
-+ /* Signal the service that it
-+ ** has dropped below its quota
-+ */
-+ up(&service_quota->quota_event);
-+ else if (count == 0) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "service %d "
-+ "message_use_count=%d "
-+ "(header %x, msgid %x, "
-+ "header->msgid %x, "
-+ "header->size %x)",
-+ port,
-+ service_quota->
-+ message_use_count,
-+ (unsigned int)header, msgid,
-+ header->msgid,
-+ header->size);
-+ WARN(1, "invalid message use count\n");
-+ }
-+ if (!BITSET_IS_SET(service_found, port)) {
-+ /* Set the found bit for this service */
-+ BITSET_SET(service_found, port);
-+
-+ spin_lock(&quota_spinlock);
-+ count = service_quota->slot_use_count;
-+ if (count > 0)
-+ service_quota->slot_use_count =
-+ count - 1;
-+ spin_unlock(&quota_spinlock);
-+
-+ if (count > 0) {
-+ /* Signal the service in case
-+ ** it has dropped below its
-+ ** quota */
-+ up(&service_quota->quota_event);
-+ vchiq_log_trace(
-+ vchiq_core_log_level,
-+ "%d: pfq:%d %x@%x - "
-+ "slot_use->%d",
-+ state->id, port,
-+ header->size,
-+ (unsigned int)header,
-+ count - 1);
-+ } else {
-+ vchiq_log_error(
-+ vchiq_core_log_level,
-+ "service %d "
-+ "slot_use_count"
-+ "=%d (header %x"
-+ ", msgid %x, "
-+ "header->msgid"
-+ " %x, header->"
-+ "size %x)",
-+ port, count,
-+ (unsigned int)header,
-+ msgid,
-+ header->msgid,
-+ header->size);
-+ WARN(1, "bad slot use count\n");
-+ }
-+ }
-+
-+ data_found = 1;
-+ }
-+
-+ pos += calc_stride(header->size);
-+ if (pos > VCHIQ_SLOT_SIZE) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "pfq - pos %x: header %x, msgid %x, "
-+ "header->msgid %x, header->size %x",
-+ pos, (unsigned int)header, msgid,
-+ header->msgid, header->size);
-+ WARN(1, "invalid slot position\n");
-+ }
-+ }
-+
-+ if (data_found) {
-+ int count;
-+ spin_lock(&quota_spinlock);
-+ count = state->data_use_count;
-+ if (count > 0)
-+ state->data_use_count =
-+ count - 1;
-+ spin_unlock(&quota_spinlock);
-+ if (count == state->data_quota)
-+ up(&state->data_quota_event);
-+ }
-+
-+ state->slot_queue_available = slot_queue_available;
-+ up(&state->slot_available_event);
-+ }
-+}
-+
-+/* Called by the slot handler and application threads */
-+static VCHIQ_STATUS_T
-+queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ int msgid, const VCHIQ_ELEMENT_T *elements,
-+ int count, int size, int flags)
-+{
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL;
-+ VCHIQ_HEADER_T *header;
-+ int type = VCHIQ_MSG_TYPE(msgid);
-+
-+ unsigned int stride;
-+
-+ local = state->local;
-+
-+ stride = calc_stride(size);
-+
-+ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE));
-+
-+ if (!(flags & QMFLAGS_NO_MUTEX_LOCK) &&
-+ (mutex_lock_interruptible(&state->slot_mutex) != 0))
-+ return VCHIQ_RETRY;
-+
-+ if (type == VCHIQ_MSG_DATA) {
-+ int tx_end_index;
-+
-+ BUG_ON(!service);
-+ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK |
-+ QMFLAGS_NO_MUTEX_UNLOCK)) != 0);
-+
-+ if (service->closing) {
-+ /* The service has been closed */
-+ mutex_unlock(&state->slot_mutex);
-+ return VCHIQ_ERROR;
-+ }
-+
-+ service_quota = &state->service_quotas[service->localport];
-+
-+ spin_lock(&quota_spinlock);
-+
-+ /* Ensure this service doesn't use more than its quota of
-+ ** messages or slots */
-+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
-+ state->local_tx_pos + stride - 1);
-+
-+ /* Ensure data messages don't use more than their quota of
-+ ** slots */
-+ while ((tx_end_index != state->previous_data_index) &&
-+ (state->data_use_count == state->data_quota)) {
-+ VCHIQ_STATS_INC(state, data_stalls);
-+ spin_unlock(&quota_spinlock);
-+ mutex_unlock(&state->slot_mutex);
-+
-+ if (down_interruptible(&state->data_quota_event)
-+ != 0)
-+ return VCHIQ_RETRY;
-+
-+ mutex_lock(&state->slot_mutex);
-+ spin_lock(&quota_spinlock);
-+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
-+ state->local_tx_pos + stride - 1);
-+ if ((tx_end_index == state->previous_data_index) ||
-+ (state->data_use_count < state->data_quota)) {
-+ /* Pass the signal on to other waiters */
-+ up(&state->data_quota_event);
-+ break;
-+ }
-+ }
-+
-+ while ((service_quota->message_use_count ==
-+ service_quota->message_quota) ||
-+ ((tx_end_index != service_quota->previous_tx_index) &&
-+ (service_quota->slot_use_count ==
-+ service_quota->slot_quota))) {
-+ spin_unlock(&quota_spinlock);
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: qm:%d %s,%x - quota stall "
-+ "(msg %d, slot %d)",
-+ state->id, service->localport,
-+ msg_type_str(type), size,
-+ service_quota->message_use_count,
-+ service_quota->slot_use_count);
-+ VCHIQ_SERVICE_STATS_INC(service, quota_stalls);
-+ mutex_unlock(&state->slot_mutex);
-+ if (down_interruptible(&service_quota->quota_event)
-+ != 0)
-+ return VCHIQ_RETRY;
-+ if (service->closing)
-+ return VCHIQ_ERROR;
-+ if (mutex_lock_interruptible(&state->slot_mutex) != 0)
-+ return VCHIQ_RETRY;
-+ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) {
-+ /* The service has been closed */
-+ mutex_unlock(&state->slot_mutex);
-+ return VCHIQ_ERROR;
-+ }
-+ spin_lock(&quota_spinlock);
-+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(
-+ state->local_tx_pos + stride - 1);
-+ }
-+
-+ spin_unlock(&quota_spinlock);
-+ }
-+
-+ header = reserve_space(state, stride, flags & QMFLAGS_IS_BLOCKING);
-+
-+ if (!header) {
-+ if (service)
-+ VCHIQ_SERVICE_STATS_INC(service, slot_stalls);
-+ /* In the event of a failure, return the mutex to the
-+ state it was in */
-+ if (!(flags & QMFLAGS_NO_MUTEX_LOCK))
-+ mutex_unlock(&state->slot_mutex);
-+ return VCHIQ_RETRY;
-+ }
-+
-+ if (type == VCHIQ_MSG_DATA) {
-+ int i, pos;
-+ int tx_end_index;
-+ int slot_use_count;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: qm %s@%x,%x (%d->%d)",
-+ state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+
-+ BUG_ON(!service);
-+ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK |
-+ QMFLAGS_NO_MUTEX_UNLOCK)) != 0);
-+
-+ for (i = 0, pos = 0; i < (unsigned int)count;
-+ pos += elements[i++].size)
-+ if (elements[i].size) {
-+ if (vchiq_copy_from_user
-+ (header->data + pos, elements[i].data,
-+ (size_t) elements[i].size) !=
-+ VCHIQ_SUCCESS) {
-+ mutex_unlock(&state->slot_mutex);
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ error_count);
-+ return VCHIQ_ERROR;
-+ }
-+ if (i == 0) {
-+ if (SRVTRACE_ENABLED(service,
-+ VCHIQ_LOG_INFO))
-+ vchiq_log_dump_mem("Sent", 0,
-+ header->data + pos,
-+ min(64u,
-+ elements[0].size));
-+ }
-+ }
-+
-+ spin_lock(&quota_spinlock);
-+ service_quota->message_use_count++;
-+
-+ tx_end_index =
-+ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1);
-+
-+ /* If this transmission can't fit in the last slot used by any
-+ ** service, the data_use_count must be increased. */
-+ if (tx_end_index != state->previous_data_index) {
-+ state->previous_data_index = tx_end_index;
-+ state->data_use_count++;
-+ }
-+
-+ /* If this isn't the same slot last used by this service,
-+ ** the service's slot_use_count must be increased. */
-+ if (tx_end_index != service_quota->previous_tx_index) {
-+ service_quota->previous_tx_index = tx_end_index;
-+ slot_use_count = ++service_quota->slot_use_count;
-+ } else {
-+ slot_use_count = 0;
-+ }
-+
-+ spin_unlock(&quota_spinlock);
-+
-+ if (slot_use_count)
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)",
-+ state->id, service->localport,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size,
-+ slot_use_count, header);
-+
-+ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
-+ } else {
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: qm %s@%x,%x (%d->%d)", state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+ if (size != 0) {
-+ WARN_ON(!((count == 1) && (size == elements[0].size)));
-+ memcpy(header->data, elements[0].data,
-+ elements[0].size);
-+ }
-+ VCHIQ_STATS_INC(state, ctrl_tx_count);
-+ }
-+
-+ header->msgid = msgid;
-+ header->size = size;
-+
-+ {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d",
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ VCHIQ_MSG_TYPE(msgid),
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid),
-+ size);
-+ }
-+
-+ /* Make sure the new header is visible to the peer. */
-+ wmb();
-+
-+ /* Make the new tx_pos visible to the peer. */
-+ local->tx_pos = state->local_tx_pos;
-+ wmb();
-+
-+ if (service && (type == VCHIQ_MSG_CLOSE))
-+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT);
-+
-+ if (!(flags & QMFLAGS_NO_MUTEX_UNLOCK))
-+ mutex_unlock(&state->slot_mutex);
-+
-+ remote_event_signal(&state->remote->trigger);
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+/* Called by the slot handler and application threads */
-+static VCHIQ_STATUS_T
-+queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service,
-+ int msgid, const VCHIQ_ELEMENT_T *elements,
-+ int count, int size, int is_blocking)
-+{
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_HEADER_T *header;
-+
-+ local = state->local;
-+
-+ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) &&
-+ (mutex_lock_interruptible(&state->sync_mutex) != 0))
-+ return VCHIQ_RETRY;
-+
-+ remote_event_wait(&local->sync_release);
-+
-+ rmb();
-+
-+ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
-+ local->slot_sync);
-+
-+ {
-+ int oldmsgid = header->msgid;
-+ if (oldmsgid != VCHIQ_MSGID_PADDING)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: qms - msgid %x, not PADDING",
-+ state->id, oldmsgid);
-+ }
-+
-+ if (service) {
-+ int i, pos;
-+
-+ vchiq_log_info(vchiq_sync_log_level,
-+ "%d: qms %s@%x,%x (%d->%d)", state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+
-+ for (i = 0, pos = 0; i < (unsigned int)count;
-+ pos += elements[i++].size)
-+ if (elements[i].size) {
-+ if (vchiq_copy_from_user
-+ (header->data + pos, elements[i].data,
-+ (size_t) elements[i].size) !=
-+ VCHIQ_SUCCESS) {
-+ mutex_unlock(&state->sync_mutex);
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ error_count);
-+ return VCHIQ_ERROR;
-+ }
-+ if (i == 0) {
-+ if (vchiq_sync_log_level >=
-+ VCHIQ_LOG_TRACE)
-+ vchiq_log_dump_mem("Sent Sync",
-+ 0, header->data + pos,
-+ min(64u,
-+ elements[0].size));
-+ }
-+ }
-+
-+ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size);
-+ } else {
-+ vchiq_log_info(vchiq_sync_log_level,
-+ "%d: qms %s@%x,%x (%d->%d)", state->id,
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ (unsigned int)header, size,
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid));
-+ if (size != 0) {
-+ WARN_ON(!((count == 1) && (size == elements[0].size)));
-+ memcpy(header->data, elements[0].data,
-+ elements[0].size);
-+ }
-+ VCHIQ_STATS_INC(state, ctrl_tx_count);
-+ }
-+
-+ header->size = size;
-+ header->msgid = msgid;
-+
-+ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+
-+ vchiq_log_trace(vchiq_sync_log_level,
-+ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d",
-+ msg_type_str(VCHIQ_MSG_TYPE(msgid)),
-+ VCHIQ_MSG_TYPE(msgid),
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ VCHIQ_MSG_SRCPORT(msgid),
-+ VCHIQ_MSG_DSTPORT(msgid),
-+ size);
-+ }
-+
-+ /* Make sure the new header is visible to the peer. */
-+ wmb();
-+
-+ remote_event_signal(&state->remote->sync_trigger);
-+
-+ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE)
-+ mutex_unlock(&state->sync_mutex);
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+static inline void
-+claim_slot(VCHIQ_SLOT_INFO_T *slot)
-+{
-+ slot->use_count++;
-+}
-+
-+static void
-+release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info,
-+ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service)
-+{
-+ int release_count;
-+
-+ mutex_lock(&state->recycle_mutex);
-+
-+ if (header) {
-+ int msgid = header->msgid;
-+ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) ||
-+ (service && service->closing)) {
-+ mutex_unlock(&state->recycle_mutex);
-+ return;
-+ }
-+
-+ /* Rewrite the message header to prevent a double
-+ ** release */
-+ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED;
-+ }
-+
-+ release_count = slot_info->release_count;
-+ slot_info->release_count = ++release_count;
-+
-+ if (release_count == slot_info->use_count) {
-+ int slot_queue_recycle;
-+ /* Add to the freed queue */
-+
-+ /* A read barrier is necessary here to prevent speculative
-+ ** fetches of remote->slot_queue_recycle from overtaking the
-+ ** mutex. */
-+ rmb();
-+
-+ slot_queue_recycle = state->remote->slot_queue_recycle;
-+ state->remote->slot_queue[slot_queue_recycle &
-+ VCHIQ_SLOT_QUEUE_MASK] =
-+ SLOT_INDEX_FROM_INFO(state, slot_info);
-+ state->remote->slot_queue_recycle = slot_queue_recycle + 1;
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: release_slot %d - recycle->%x",
-+ state->id, SLOT_INDEX_FROM_INFO(state, slot_info),
-+ state->remote->slot_queue_recycle);
-+
-+ /* A write barrier is necessary, but remote_event_signal
-+ ** contains one. */
-+ remote_event_signal(&state->remote->recycle);
-+ }
-+
-+ mutex_unlock(&state->recycle_mutex);
-+}
-+
-+/* Called by the slot handler - don't hold the bulk mutex */
-+static VCHIQ_STATUS_T
-+notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue,
-+ int retry_poll)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: nb:%d %cx - p=%x rn=%x r=%x",
-+ service->state->id, service->localport,
-+ (queue == &service->bulk_tx) ? 't' : 'r',
-+ queue->process, queue->remote_notify, queue->remove);
-+
-+ if (service->state->is_master) {
-+ while (queue->remote_notify != queue->process) {
-+ VCHIQ_BULK_T *bulk =
-+ &queue->bulks[BULK_INDEX(queue->remote_notify)];
-+ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ?
-+ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE;
-+ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport,
-+ service->remoteport);
-+ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 };
-+ /* Only reply to non-dummy bulk requests */
-+ if (bulk->remote_data) {
-+ status = queue_message(service->state, NULL,
-+ msgid, &element, 1, 4, 0);
-+ if (status != VCHIQ_SUCCESS)
-+ break;
-+ }
-+ queue->remote_notify++;
-+ }
-+ } else {
-+ queue->remote_notify = queue->process;
-+ }
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ while (queue->remove != queue->remote_notify) {
-+ VCHIQ_BULK_T *bulk =
-+ &queue->bulks[BULK_INDEX(queue->remove)];
-+
-+ /* Only generate callbacks for non-dummy bulk
-+ ** requests, and non-terminated services */
-+ if (bulk->data && service->instance) {
-+ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) {
-+ if (bulk->dir == VCHIQ_BULK_TRANSMIT) {
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ bulk_tx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service,
-+ bulk_tx_bytes,
-+ bulk->actual);
-+ } else {
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ bulk_rx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service,
-+ bulk_rx_bytes,
-+ bulk->actual);
-+ }
-+ } else {
-+ VCHIQ_SERVICE_STATS_INC(service,
-+ bulk_aborted_count);
-+ }
-+ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) {
-+ struct bulk_waiter *waiter;
-+ spin_lock(&bulk_waiter_spinlock);
-+ waiter = bulk->userdata;
-+ if (waiter) {
-+ waiter->actual = bulk->actual;
-+ up(&waiter->event);
-+ }
-+ spin_unlock(&bulk_waiter_spinlock);
-+ } else if (bulk->mode ==
-+ VCHIQ_BULK_MODE_CALLBACK) {
-+ VCHIQ_REASON_T reason = (bulk->dir ==
-+ VCHIQ_BULK_TRANSMIT) ?
-+ ((bulk->actual ==
-+ VCHIQ_BULK_ACTUAL_ABORTED) ?
-+ VCHIQ_BULK_TRANSMIT_ABORTED :
-+ VCHIQ_BULK_TRANSMIT_DONE) :
-+ ((bulk->actual ==
-+ VCHIQ_BULK_ACTUAL_ABORTED) ?
-+ VCHIQ_BULK_RECEIVE_ABORTED :
-+ VCHIQ_BULK_RECEIVE_DONE);
-+ status = make_service_callback(service,
-+ reason, NULL, bulk->userdata);
-+ if (status == VCHIQ_RETRY)
-+ break;
-+ }
-+ }
-+
-+ queue->remove++;
-+ up(&service->bulk_remove_event);
-+ }
-+ if (!retry_poll)
-+ status = VCHIQ_SUCCESS;
-+ }
-+
-+ if (status == VCHIQ_RETRY)
-+ request_poll(service->state, service,
-+ (queue == &service->bulk_tx) ?
-+ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
-+
-+ return status;
-+}
-+
-+/* Called by the slot handler thread */
-+static void
-+poll_services(VCHIQ_STATE_T *state)
-+{
-+ int group, i;
-+
-+ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) {
-+ uint32_t flags;
-+ flags = atomic_xchg(&state->poll_services[group], 0);
-+ for (i = 0; flags; i++) {
-+ if (flags & (1 << i)) {
-+ VCHIQ_SERVICE_T *service =
-+ find_service_by_port(state,
-+ (group<<5) + i);
-+ uint32_t service_flags;
-+ flags &= ~(1 << i);
-+ if (!service)
-+ continue;
-+ service_flags =
-+ atomic_xchg(&service->poll_flags, 0);
-+ if (service_flags &
-+ (1 << VCHIQ_POLL_REMOVE)) {
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: ps - remove %d<->%d",
-+ state->id, service->localport,
-+ service->remoteport);
-+
-+ /* Make it look like a client, because
-+ it must be removed and not left in
-+ the LISTENING state. */
-+ service->public_fourcc =
-+ VCHIQ_FOURCC_INVALID;
-+
-+ if (vchiq_close_service_internal(
-+ service, 0/*!close_recvd*/) !=
-+ VCHIQ_SUCCESS)
-+ request_poll(state, service,
-+ VCHIQ_POLL_REMOVE);
-+ } else if (service_flags &
-+ (1 << VCHIQ_POLL_TERMINATE)) {
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: ps - terminate %d<->%d",
-+ state->id, service->localport,
-+ service->remoteport);
-+ if (vchiq_close_service_internal(
-+ service, 0/*!close_recvd*/) !=
-+ VCHIQ_SUCCESS)
-+ request_poll(state, service,
-+ VCHIQ_POLL_TERMINATE);
-+ }
-+ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY))
-+ notify_bulks(service,
-+ &service->bulk_tx,
-+ 1/*retry_poll*/);
-+ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY))
-+ notify_bulks(service,
-+ &service->bulk_rx,
-+ 1/*retry_poll*/);
-+ unlock_service(service);
-+ }
-+ }
-+ }
-+}
-+
-+/* Called by the slot handler or application threads, holding the bulk mutex. */
-+static int
-+resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ int resolved = 0;
-+ int rc;
-+
-+ while ((queue->process != queue->local_insert) &&
-+ (queue->process != queue->remote_insert)) {
-+ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)];
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: rb:%d %cx - li=%x ri=%x p=%x",
-+ state->id, service->localport,
-+ (queue == &service->bulk_tx) ? 't' : 'r',
-+ queue->local_insert, queue->remote_insert,
-+ queue->process);
-+
-+ WARN_ON(!((int)(queue->local_insert - queue->process) > 0));
-+ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0));
-+
-+ rc = mutex_lock_interruptible(&state->bulk_transfer_mutex);
-+ if (rc != 0)
-+ break;
-+
-+ vchiq_transfer_bulk(bulk);
-+ mutex_unlock(&state->bulk_transfer_mutex);
-+
-+ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) {
-+ const char *header = (queue == &service->bulk_tx) ?
-+ "Send Bulk to" : "Recv Bulk from";
-+ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED)
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "%s %c%c%c%c d:%d len:%d %x<->%x",
-+ header,
-+ VCHIQ_FOURCC_AS_4CHARS(
-+ service->base.fourcc),
-+ service->remoteport,
-+ bulk->size,
-+ (unsigned int)bulk->data,
-+ (unsigned int)bulk->remote_data);
-+ else
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "%s %c%c%c%c d:%d ABORTED - tx len:%d,"
-+ " rx len:%d %x<->%x",
-+ header,
-+ VCHIQ_FOURCC_AS_4CHARS(
-+ service->base.fourcc),
-+ service->remoteport,
-+ bulk->size,
-+ bulk->remote_size,
-+ (unsigned int)bulk->data,
-+ (unsigned int)bulk->remote_data);
-+ }
-+
-+ vchiq_complete_bulk(bulk);
-+ queue->process++;
-+ resolved++;
-+ }
-+ return resolved;
-+}
-+
-+/* Called with the bulk_mutex held */
-+static void
-+abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue)
-+{
-+ int is_tx = (queue == &service->bulk_tx);
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: aob:%d %cx - li=%x ri=%x p=%x",
-+ service->state->id, service->localport, is_tx ? 't' : 'r',
-+ queue->local_insert, queue->remote_insert, queue->process);
-+
-+ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0));
-+ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0));
-+
-+ while ((queue->process != queue->local_insert) ||
-+ (queue->process != queue->remote_insert)) {
-+ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)];
-+
-+ if (queue->process == queue->remote_insert) {
-+ /* fabricate a matching dummy bulk */
-+ bulk->remote_data = NULL;
-+ bulk->remote_size = 0;
-+ queue->remote_insert++;
-+ }
-+
-+ if (queue->process != queue->local_insert) {
-+ vchiq_complete_bulk(bulk);
-+
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "%s %c%c%c%c d:%d ABORTED - tx len:%d, "
-+ "rx len:%d",
-+ is_tx ? "Send Bulk to" : "Recv Bulk from",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->remoteport,
-+ bulk->size,
-+ bulk->remote_size);
-+ } else {
-+ /* fabricate a matching dummy bulk */
-+ bulk->data = NULL;
-+ bulk->size = 0;
-+ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED;
-+ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT :
-+ VCHIQ_BULK_RECEIVE;
-+ queue->local_insert++;
-+ }
-+
-+ queue->process++;
-+ }
-+}
-+
-+/* Called from the slot handler thread */
-+static void
-+pause_bulks(VCHIQ_STATE_T *state)
-+{
-+ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) {
-+ WARN_ON_ONCE(1);
-+ atomic_set(&pause_bulks_count, 1);
-+ return;
-+ }
-+
-+ /* Block bulk transfers from all services */
-+ mutex_lock(&state->bulk_transfer_mutex);
-+}
-+
-+/* Called from the slot handler thread */
-+static void
-+resume_bulks(VCHIQ_STATE_T *state)
-+{
-+ int i;
-+ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) {
-+ WARN_ON_ONCE(1);
-+ atomic_set(&pause_bulks_count, 0);
-+ return;
-+ }
-+
-+ /* Allow bulk transfers from all services */
-+ mutex_unlock(&state->bulk_transfer_mutex);
-+
-+ if (state->deferred_bulks == 0)
-+ return;
-+
-+ /* Deal with any bulks which had to be deferred due to being in
-+ * paused state. Don't try to match up to number of deferred bulks
-+ * in case we've had something come and close the service in the
-+ * interim - just process all bulk queues for all services */
-+ vchiq_log_info(vchiq_core_log_level, "%s: processing %d deferred bulks",
-+ __func__, state->deferred_bulks);
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = state->services[i];
-+ int resolved_rx = 0;
-+ int resolved_tx = 0;
-+ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN))
-+ continue;
-+
-+ mutex_lock(&service->bulk_mutex);
-+ resolved_rx = resolve_bulks(service, &service->bulk_rx);
-+ resolved_tx = resolve_bulks(service, &service->bulk_tx);
-+ mutex_unlock(&service->bulk_mutex);
-+ if (resolved_rx)
-+ notify_bulks(service, &service->bulk_rx, 1);
-+ if (resolved_tx)
-+ notify_bulks(service, &service->bulk_tx, 1);
-+ }
-+ state->deferred_bulks = 0;
-+}
-+
-+static int
-+parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
-+{
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int msgid, size;
-+ int type;
-+ unsigned int localport, remoteport;
-+
-+ msgid = header->msgid;
-+ size = header->size;
-+ type = VCHIQ_MSG_TYPE(msgid);
-+ localport = VCHIQ_MSG_DSTPORT(msgid);
-+ remoteport = VCHIQ_MSG_SRCPORT(msgid);
-+ if (size >= sizeof(struct vchiq_open_payload)) {
-+ const struct vchiq_open_payload *payload =
-+ (struct vchiq_open_payload *)header->data;
-+ unsigned int fourcc;
-+
-+ fourcc = payload->fourcc;
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs OPEN@%x (%d->'%c%c%c%c')",
-+ state->id, (unsigned int)header,
-+ localport,
-+ VCHIQ_FOURCC_AS_4CHARS(fourcc));
-+
-+ service = get_listening_service(state, fourcc);
-+
-+ if (service) {
-+ /* A matching service exists */
-+ short version = payload->version;
-+ short version_min = payload->version_min;
-+ if ((service->version < version_min) ||
-+ (version < service->version_min)) {
-+ /* Version mismatch */
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("%d: service %d (%c%c%c%c) "
-+ "version mismatch - local (%d, min %d)"
-+ " vs. remote (%d, min %d)",
-+ state->id, service->localport,
-+ VCHIQ_FOURCC_AS_4CHARS(fourcc),
-+ service->version, service->version_min,
-+ version, version_min);
-+ vchiq_loud_error_footer();
-+ unlock_service(service);
-+ service = NULL;
-+ goto fail_open;
-+ }
-+ service->peer_version = version;
-+
-+ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) {
-+ struct vchiq_openack_payload ack_payload = {
-+ service->version
-+ };
-+ VCHIQ_ELEMENT_T body = {
-+ &ack_payload,
-+ sizeof(ack_payload)
-+ };
-+
-+ if (state->version_common <
-+ VCHIQ_VERSION_SYNCHRONOUS_MODE)
-+ service->sync = 0;
-+
-+ /* Acknowledge the OPEN */
-+ if (service->sync &&
-+ (state->version_common >=
-+ VCHIQ_VERSION_SYNCHRONOUS_MODE)) {
-+ if (queue_message_sync(state, NULL,
-+ VCHIQ_MAKE_MSG(
-+ VCHIQ_MSG_OPENACK,
-+ service->localport,
-+ remoteport),
-+ &body, 1, sizeof(ack_payload),
-+ 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+ } else {
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(
-+ VCHIQ_MSG_OPENACK,
-+ service->localport,
-+ remoteport),
-+ &body, 1, sizeof(ack_payload),
-+ 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+ }
-+
-+ /* The service is now open */
-+ vchiq_set_service_state(service,
-+ service->sync ? VCHIQ_SRVSTATE_OPENSYNC
-+ : VCHIQ_SRVSTATE_OPEN);
-+ }
-+
-+ service->remoteport = remoteport;
-+ service->client_id = ((int *)header->data)[1];
-+ if (make_service_callback(service, VCHIQ_SERVICE_OPENED,
-+ NULL, NULL) == VCHIQ_RETRY) {
-+ /* Bail out if not ready */
-+ service->remoteport = VCHIQ_PORT_FREE;
-+ goto bail_not_ready;
-+ }
-+
-+ /* Success - the message has been dealt with */
-+ unlock_service(service);
-+ return 1;
-+ }
-+ }
-+
-+fail_open:
-+ /* No available service, or an invalid request - send a CLOSE */
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)),
-+ NULL, 0, 0, 0) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+
-+ return 1;
-+
-+bail_not_ready:
-+ if (service)
-+ unlock_service(service);
-+
-+ return 0;
-+}
-+
-+/* Called by the slot handler thread */
-+static void
-+parse_rx_slots(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_SHARED_STATE_T *remote = state->remote;
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int tx_pos;
-+ DEBUG_INITIALISE(state->local)
-+
-+ tx_pos = remote->tx_pos;
-+
-+ while (state->rx_pos != tx_pos) {
-+ VCHIQ_HEADER_T *header;
-+ int msgid, size;
-+ int type;
-+ unsigned int localport, remoteport;
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (!state->rx_data) {
-+ int rx_index;
-+ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0));
-+ rx_index = remote->slot_queue[
-+ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) &
-+ VCHIQ_SLOT_QUEUE_MASK];
-+ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state,
-+ rx_index);
-+ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index);
-+
-+ /* Initialise use_count to one, and increment
-+ ** release_count at the end of the slot to avoid
-+ ** releasing the slot prematurely. */
-+ state->rx_info->use_count = 1;
-+ state->rx_info->release_count = 0;
-+ }
-+
-+ header = (VCHIQ_HEADER_T *)(state->rx_data +
-+ (state->rx_pos & VCHIQ_SLOT_MASK));
-+ DEBUG_VALUE(PARSE_HEADER, (int)header);
-+ msgid = header->msgid;
-+ DEBUG_VALUE(PARSE_MSGID, msgid);
-+ size = header->size;
-+ type = VCHIQ_MSG_TYPE(msgid);
-+ localport = VCHIQ_MSG_DSTPORT(msgid);
-+ remoteport = VCHIQ_MSG_SRCPORT(msgid);
-+
-+ if (type != VCHIQ_MSG_DATA)
-+ VCHIQ_STATS_INC(state, ctrl_rx_count);
-+
-+ switch (type) {
-+ case VCHIQ_MSG_OPENACK:
-+ case VCHIQ_MSG_CLOSE:
-+ case VCHIQ_MSG_DATA:
-+ case VCHIQ_MSG_BULK_RX:
-+ case VCHIQ_MSG_BULK_TX:
-+ case VCHIQ_MSG_BULK_RX_DONE:
-+ case VCHIQ_MSG_BULK_TX_DONE:
-+ service = find_service_by_port(state, localport);
-+ if ((!service ||
-+ ((service->remoteport != remoteport) &&
-+ (service->remoteport != VCHIQ_PORT_FREE))) &&
-+ (localport == 0) &&
-+ (type == VCHIQ_MSG_CLOSE)) {
-+ /* This could be a CLOSE from a client which
-+ hadn't yet received the OPENACK - look for
-+ the connected service */
-+ if (service)
-+ unlock_service(service);
-+ service = get_connected_service(state,
-+ remoteport);
-+ if (service)
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) - "
-+ "found connected service %d",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ service->localport);
-+ }
-+
-+ if (!service) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) - "
-+ "invalid/closed service %d",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport, localport);
-+ goto skip_message;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+ vchiq_log_info(SRVTRACE_LEVEL(service),
-+ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d "
-+ "len:%d",
-+ msg_type_str(type), type,
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ remoteport, localport, size);
-+ if (size > 0)
-+ vchiq_log_dump_mem("Rcvd", 0, header->data,
-+ min(64, size));
-+ }
-+
-+ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size)
-+ > VCHIQ_SLOT_SIZE) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "header %x (msgid %x) - size %x too big for "
-+ "slot",
-+ (unsigned int)header, (unsigned int)msgid,
-+ (unsigned int)size);
-+ WARN(1, "oversized for slot\n");
-+ }
-+
-+ switch (type) {
-+ case VCHIQ_MSG_OPEN:
-+ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0));
-+ if (!parse_open(state, header))
-+ goto bail_not_ready;
-+ break;
-+ case VCHIQ_MSG_OPENACK:
-+ if (size >= sizeof(struct vchiq_openack_payload)) {
-+ const struct vchiq_openack_payload *payload =
-+ (struct vchiq_openack_payload *)
-+ header->data;
-+ service->peer_version = payload->version;
-+ }
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs OPENACK@%x,%x (%d->%d) v:%d",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport, service->peer_version);
-+ if (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPENING) {
-+ service->remoteport = remoteport;
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_OPEN);
-+ up(&service->remove_event);
-+ } else
-+ vchiq_log_error(vchiq_core_log_level,
-+ "OPENACK received in state %s",
-+ srvstate_names[service->srvstate]);
-+ break;
-+ case VCHIQ_MSG_CLOSE:
-+ WARN_ON(size != 0); /* There should be no data */
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs CLOSE@%x (%d->%d)",
-+ state->id, (unsigned int)header,
-+ remoteport, localport);
-+
-+ mark_service_closing_internal(service, 1);
-+
-+ if (vchiq_close_service_internal(service,
-+ 1/*close_recvd*/) == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "Close Service %c%c%c%c s:%u d:%d",
-+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc),
-+ service->localport,
-+ service->remoteport);
-+ break;
-+ case VCHIQ_MSG_DATA:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs DATA@%x,%x (%d->%d)",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport);
-+
-+ if ((service->remoteport == remoteport)
-+ && (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPEN)) {
-+ header->msgid = msgid | VCHIQ_MSGID_CLAIMED;
-+ claim_slot(state->rx_info);
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (make_service_callback(service,
-+ VCHIQ_MESSAGE_AVAILABLE, header,
-+ NULL) == VCHIQ_RETRY) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ goto bail_not_ready;
-+ }
-+ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count);
-+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes,
-+ size);
-+ } else {
-+ VCHIQ_STATS_INC(state, error_count);
-+ }
-+ break;
-+ case VCHIQ_MSG_CONNECT:
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs CONNECT@%x",
-+ state->id, (unsigned int)header);
-+ state->version_common = ((VCHIQ_SLOT_ZERO_T *)
-+ state->slot_data)->version;
-+ up(&state->connect);
-+ break;
-+ case VCHIQ_MSG_BULK_RX:
-+ case VCHIQ_MSG_BULK_TX: {
-+ VCHIQ_BULK_QUEUE_T *queue;
-+ WARN_ON(!state->is_master);
-+ queue = (type == VCHIQ_MSG_BULK_RX) ?
-+ &service->bulk_tx : &service->bulk_rx;
-+ if ((service->remoteport == remoteport)
-+ && (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPEN)) {
-+ VCHIQ_BULK_T *bulk;
-+ int resolved = 0;
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (mutex_lock_interruptible(
-+ &service->bulk_mutex) != 0) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ goto bail_not_ready;
-+ }
-+
-+ WARN_ON(!(queue->remote_insert < queue->remove +
-+ VCHIQ_NUM_SERVICE_BULKS));
-+ bulk = &queue->bulks[
-+ BULK_INDEX(queue->remote_insert)];
-+ bulk->remote_data =
-+ (void *)((int *)header->data)[0];
-+ bulk->remote_size = ((int *)header->data)[1];
-+ wmb();
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) %x@%x",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ bulk->remote_size,
-+ (unsigned int)bulk->remote_data);
-+
-+ queue->remote_insert++;
-+
-+ if (atomic_read(&pause_bulks_count)) {
-+ state->deferred_bulks++;
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%s: deferring bulk (%d)",
-+ __func__,
-+ state->deferred_bulks);
-+ if (state->conn_state !=
-+ VCHIQ_CONNSTATE_PAUSE_SENT)
-+ vchiq_log_error(
-+ vchiq_core_log_level,
-+ "%s: bulks paused in "
-+ "unexpected state %s",
-+ __func__,
-+ conn_state_names[
-+ state->conn_state]);
-+ } else if (state->conn_state ==
-+ VCHIQ_CONNSTATE_CONNECTED) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ resolved = resolve_bulks(service,
-+ queue);
-+ }
-+
-+ mutex_unlock(&service->bulk_mutex);
-+ if (resolved)
-+ notify_bulks(service, queue,
-+ 1/*retry_poll*/);
-+ }
-+ } break;
-+ case VCHIQ_MSG_BULK_RX_DONE:
-+ case VCHIQ_MSG_BULK_TX_DONE:
-+ WARN_ON(state->is_master);
-+ if ((service->remoteport == remoteport)
-+ && (service->srvstate !=
-+ VCHIQ_SRVSTATE_FREE)) {
-+ VCHIQ_BULK_QUEUE_T *queue;
-+ VCHIQ_BULK_T *bulk;
-+
-+ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ?
-+ &service->bulk_rx : &service->bulk_tx;
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ if (mutex_lock_interruptible(
-+ &service->bulk_mutex) != 0) {
-+ DEBUG_TRACE(PARSE_LINE);
-+ goto bail_not_ready;
-+ }
-+ if ((int)(queue->remote_insert -
-+ queue->local_insert) >= 0) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) "
-+ "unexpected (ri=%d,li=%d)",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ queue->remote_insert,
-+ queue->local_insert);
-+ mutex_unlock(&service->bulk_mutex);
-+ break;
-+ }
-+
-+ BUG_ON(queue->process == queue->local_insert);
-+ BUG_ON(queue->process != queue->remote_insert);
-+
-+ bulk = &queue->bulks[
-+ BULK_INDEX(queue->remote_insert)];
-+ bulk->actual = *(int *)header->data;
-+ queue->remote_insert++;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: prs %s@%x (%d->%d) %x@%x",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport,
-+ bulk->actual, (unsigned int)bulk->data);
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs:%d %cx li=%x ri=%x p=%x",
-+ state->id, localport,
-+ (type == VCHIQ_MSG_BULK_RX_DONE) ?
-+ 'r' : 't',
-+ queue->local_insert,
-+ queue->remote_insert, queue->process);
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ WARN_ON(queue->process == queue->local_insert);
-+ vchiq_complete_bulk(bulk);
-+ queue->process++;
-+ mutex_unlock(&service->bulk_mutex);
-+ DEBUG_TRACE(PARSE_LINE);
-+ notify_bulks(service, queue, 1/*retry_poll*/);
-+ DEBUG_TRACE(PARSE_LINE);
-+ }
-+ break;
-+ case VCHIQ_MSG_PADDING:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs PADDING@%x,%x",
-+ state->id, (unsigned int)header, size);
-+ break;
-+ case VCHIQ_MSG_PAUSE:
-+ /* If initiated, signal the application thread */
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs PAUSE@%x,%x",
-+ state->id, (unsigned int)header, size);
-+ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: PAUSE received in state PAUSED",
-+ state->id);
-+ break;
-+ }
-+ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) {
-+ /* Send a PAUSE in response */
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0),
-+ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK)
-+ == VCHIQ_RETRY)
-+ goto bail_not_ready;
-+ if (state->is_master)
-+ pause_bulks(state);
-+ }
-+ /* At this point slot_mutex is held */
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED);
-+ vchiq_platform_paused(state);
-+ break;
-+ case VCHIQ_MSG_RESUME:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: prs RESUME@%x,%x",
-+ state->id, (unsigned int)header, size);
-+ /* Release the slot mutex */
-+ mutex_unlock(&state->slot_mutex);
-+ if (state->is_master)
-+ resume_bulks(state);
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED);
-+ vchiq_platform_resumed(state);
-+ break;
-+
-+ case VCHIQ_MSG_REMOTE_USE:
-+ vchiq_on_remote_use(state);
-+ break;
-+ case VCHIQ_MSG_REMOTE_RELEASE:
-+ vchiq_on_remote_release(state);
-+ break;
-+ case VCHIQ_MSG_REMOTE_USE_ACTIVE:
-+ vchiq_on_remote_use_active(state);
-+ break;
-+
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: prs invalid msgid %x@%x,%x",
-+ state->id, msgid, (unsigned int)header, size);
-+ WARN(1, "invalid message\n");
-+ break;
-+ }
-+
-+skip_message:
-+ if (service) {
-+ unlock_service(service);
-+ service = NULL;
-+ }
-+
-+ state->rx_pos += calc_stride(size);
-+
-+ DEBUG_TRACE(PARSE_LINE);
-+ /* Perform some housekeeping when the end of the slot is
-+ ** reached. */
-+ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) {
-+ /* Remove the extra reference count. */
-+ release_slot(state, state->rx_info, NULL, NULL);
-+ state->rx_data = NULL;
-+ }
-+ }
-+
-+bail_not_ready:
-+ if (service)
-+ unlock_service(service);
-+}
-+
-+/* Called by the slot handler thread */
-+static int
-+slot_handler_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ DEBUG_INITIALISE(local)
-+
-+ while (1) {
-+ DEBUG_COUNT(SLOT_HANDLER_COUNT);
-+ DEBUG_TRACE(SLOT_HANDLER_LINE);
-+ remote_event_wait(&local->trigger);
-+
-+ rmb();
-+
-+ DEBUG_TRACE(SLOT_HANDLER_LINE);
-+ if (state->poll_needed) {
-+ /* Check if we need to suspend - may change our
-+ * conn_state */
-+ vchiq_platform_check_suspend(state);
-+
-+ state->poll_needed = 0;
-+
-+ /* Handle service polling and other rare conditions here
-+ ** out of the mainline code */
-+ switch (state->conn_state) {
-+ case VCHIQ_CONNSTATE_CONNECTED:
-+ /* Poll the services as requested */
-+ poll_services(state);
-+ break;
-+
-+ case VCHIQ_CONNSTATE_PAUSING:
-+ if (state->is_master)
-+ pause_bulks(state);
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0),
-+ NULL, 0, 0,
-+ QMFLAGS_NO_MUTEX_UNLOCK)
-+ != VCHIQ_RETRY) {
-+ vchiq_set_conn_state(state,
-+ VCHIQ_CONNSTATE_PAUSE_SENT);
-+ } else {
-+ if (state->is_master)
-+ resume_bulks(state);
-+ /* Retry later */
-+ state->poll_needed = 1;
-+ }
-+ break;
-+
-+ case VCHIQ_CONNSTATE_PAUSED:
-+ vchiq_platform_resume(state);
-+ break;
-+
-+ case VCHIQ_CONNSTATE_RESUMING:
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0),
-+ NULL, 0, 0, QMFLAGS_NO_MUTEX_LOCK)
-+ != VCHIQ_RETRY) {
-+ if (state->is_master)
-+ resume_bulks(state);
-+ vchiq_set_conn_state(state,
-+ VCHIQ_CONNSTATE_CONNECTED);
-+ vchiq_platform_resumed(state);
-+ } else {
-+ /* This should really be impossible,
-+ ** since the PAUSE should have flushed
-+ ** through outstanding messages. */
-+ vchiq_log_error(vchiq_core_log_level,
-+ "Failed to send RESUME "
-+ "message");
-+ BUG();
-+ }
-+ break;
-+
-+ case VCHIQ_CONNSTATE_PAUSE_TIMEOUT:
-+ case VCHIQ_CONNSTATE_RESUME_TIMEOUT:
-+ vchiq_platform_handle_timeout(state);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+
-+ }
-+
-+ DEBUG_TRACE(SLOT_HANDLER_LINE);
-+ parse_rx_slots(state);
-+ }
-+ return 0;
-+}
-+
-+
-+/* Called by the recycle thread */
-+static int
-+recycle_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+
-+ while (1) {
-+ remote_event_wait(&local->recycle);
-+
-+ process_free_queue(state);
-+ }
-+ return 0;
-+}
-+
-+
-+/* Called by the sync thread */
-+static int
-+sync_func(void *v)
-+{
-+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v;
-+ VCHIQ_SHARED_STATE_T *local = state->local;
-+ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
-+ state->remote->slot_sync);
-+
-+ while (1) {
-+ VCHIQ_SERVICE_T *service;
-+ int msgid, size;
-+ int type;
-+ unsigned int localport, remoteport;
-+
-+ remote_event_wait(&local->sync_trigger);
-+
-+ rmb();
-+
-+ msgid = header->msgid;
-+ size = header->size;
-+ type = VCHIQ_MSG_TYPE(msgid);
-+ localport = VCHIQ_MSG_DSTPORT(msgid);
-+ remoteport = VCHIQ_MSG_SRCPORT(msgid);
-+
-+ service = find_service_by_port(state, localport);
-+
-+ if (!service) {
-+ vchiq_log_error(vchiq_sync_log_level,
-+ "%d: sf %s@%x (%d->%d) - "
-+ "invalid/closed service %d",
-+ state->id, msg_type_str(type),
-+ (unsigned int)header,
-+ remoteport, localport, localport);
-+ release_message_sync(state, header);
-+ continue;
-+ }
-+
-+ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) {
-+ int svc_fourcc;
-+
-+ svc_fourcc = service
-+ ? service->base.fourcc
-+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?');
-+ vchiq_log_trace(vchiq_sync_log_level,
-+ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d",
-+ msg_type_str(type),
-+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc),
-+ remoteport, localport, size);
-+ if (size > 0)
-+ vchiq_log_dump_mem("Rcvd", 0, header->data,
-+ min(64, size));
-+ }
-+
-+ switch (type) {
-+ case VCHIQ_MSG_OPENACK:
-+ if (size >= sizeof(struct vchiq_openack_payload)) {
-+ const struct vchiq_openack_payload *payload =
-+ (struct vchiq_openack_payload *)
-+ header->data;
-+ service->peer_version = payload->version;
-+ }
-+ vchiq_log_info(vchiq_sync_log_level,
-+ "%d: sf OPENACK@%x,%x (%d->%d) v:%d",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport, service->peer_version);
-+ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) {
-+ service->remoteport = remoteport;
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_OPENSYNC);
-+ service->sync = 1;
-+ up(&service->remove_event);
-+ }
-+ release_message_sync(state, header);
-+ break;
-+
-+ case VCHIQ_MSG_DATA:
-+ vchiq_log_trace(vchiq_sync_log_level,
-+ "%d: sf DATA@%x,%x (%d->%d)",
-+ state->id, (unsigned int)header, size,
-+ remoteport, localport);
-+
-+ if ((service->remoteport == remoteport) &&
-+ (service->srvstate ==
-+ VCHIQ_SRVSTATE_OPENSYNC)) {
-+ if (make_service_callback(service,
-+ VCHIQ_MESSAGE_AVAILABLE, header,
-+ NULL) == VCHIQ_RETRY)
-+ vchiq_log_error(vchiq_sync_log_level,
-+ "synchronous callback to "
-+ "service %d returns "
-+ "VCHIQ_RETRY",
-+ localport);
-+ }
-+ break;
-+
-+ default:
-+ vchiq_log_error(vchiq_sync_log_level,
-+ "%d: sf unexpected msgid %x@%x,%x",
-+ state->id, msgid, (unsigned int)header, size);
-+ release_message_sync(state, header);
-+ break;
-+ }
-+
-+ unlock_service(service);
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static void
-+init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue)
-+{
-+ queue->local_insert = 0;
-+ queue->remote_insert = 0;
-+ queue->process = 0;
-+ queue->remote_notify = 0;
-+ queue->remove = 0;
-+}
-+
-+
-+inline const char *
-+get_conn_state_name(VCHIQ_CONNSTATE_T conn_state)
-+{
-+ return conn_state_names[conn_state];
-+}
-+
-+
-+VCHIQ_SLOT_ZERO_T *
-+vchiq_init_slots(void *mem_base, int mem_size)
-+{
-+ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK;
-+ VCHIQ_SLOT_ZERO_T *slot_zero =
-+ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align);
-+ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE;
-+ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS;
-+
-+ /* Ensure there is enough memory to run an absolutely minimum system */
-+ num_slots -= first_data_slot;
-+
-+ if (num_slots < 4) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_init_slots - insufficient memory %x bytes",
-+ mem_size);
-+ return NULL;
-+ }
-+
-+ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T));
-+
-+ slot_zero->magic = VCHIQ_MAGIC;
-+ slot_zero->version = VCHIQ_VERSION;
-+ slot_zero->version_min = VCHIQ_VERSION_MIN;
-+ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T);
-+ slot_zero->slot_size = VCHIQ_SLOT_SIZE;
-+ slot_zero->max_slots = VCHIQ_MAX_SLOTS;
-+ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE;
-+
-+ slot_zero->master.slot_sync = first_data_slot;
-+ slot_zero->master.slot_first = first_data_slot + 1;
-+ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1;
-+ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2);
-+ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1;
-+ slot_zero->slave.slot_last = first_data_slot + num_slots - 1;
-+
-+ return slot_zero;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero,
-+ int is_master)
-+{
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_SHARED_STATE_T *remote;
-+ VCHIQ_STATUS_T status;
-+ char threadname[10];
-+ static int id;
-+ int i;
-+
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%s: slot_zero = 0x%08lx, is_master = %d",
-+ __func__, (unsigned long)slot_zero, is_master);
-+
-+ /* Check the input configuration */
-+
-+ if (slot_zero->magic != VCHIQ_MAGIC) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("Invalid VCHIQ magic value found.");
-+ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)",
-+ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if (slot_zero->version < VCHIQ_VERSION_MIN) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("Incompatible VCHIQ versions found.");
-+ vchiq_loud_error("slot_zero=%x: VideoCore version=%d "
-+ "(minimum %d)",
-+ (unsigned int)slot_zero, slot_zero->version,
-+ VCHIQ_VERSION_MIN);
-+ vchiq_loud_error("Restart with a newer VideoCore image.");
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if (VCHIQ_VERSION < slot_zero->version_min) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("Incompatible VCHIQ versions found.");
-+ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore "
-+ "minimum %d)",
-+ (unsigned int)slot_zero, VCHIQ_VERSION,
-+ slot_zero->version_min);
-+ vchiq_loud_error("Restart with a newer kernel.");
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ||
-+ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ||
-+ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ||
-+ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) {
-+ vchiq_loud_error_header();
-+ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T))
-+ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x "
-+ "(expected %x)",
-+ (unsigned int)slot_zero,
-+ slot_zero->slot_zero_size,
-+ sizeof(VCHIQ_SLOT_ZERO_T));
-+ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE)
-+ vchiq_loud_error("slot_zero=%x: slot_size=%d "
-+ "(expected %d",
-+ (unsigned int)slot_zero, slot_zero->slot_size,
-+ VCHIQ_SLOT_SIZE);
-+ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS)
-+ vchiq_loud_error("slot_zero=%x: max_slots=%d "
-+ "(expected %d)",
-+ (unsigned int)slot_zero, slot_zero->max_slots,
-+ VCHIQ_MAX_SLOTS);
-+ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)
-+ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d "
-+ "(expected %d)",
-+ (unsigned int)slot_zero,
-+ slot_zero->max_slots_per_side,
-+ VCHIQ_MAX_SLOTS_PER_SIDE);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ if (VCHIQ_VERSION < slot_zero->version)
-+ slot_zero->version = VCHIQ_VERSION;
-+
-+ if (is_master) {
-+ local = &slot_zero->master;
-+ remote = &slot_zero->slave;
-+ } else {
-+ local = &slot_zero->slave;
-+ remote = &slot_zero->master;
-+ }
-+
-+ if (local->initialised) {
-+ vchiq_loud_error_header();
-+ if (remote->initialised)
-+ vchiq_loud_error("local state has already been "
-+ "initialised");
-+ else
-+ vchiq_loud_error("master/slave mismatch - two %ss",
-+ is_master ? "master" : "slave");
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+
-+ memset(state, 0, sizeof(VCHIQ_STATE_T));
-+
-+ state->id = id++;
-+ state->is_master = is_master;
-+
-+ /*
-+ initialize shared state pointers
-+ */
-+
-+ state->local = local;
-+ state->remote = remote;
-+ state->slot_data = (VCHIQ_SLOT_T *)slot_zero;
-+
-+ /*
-+ initialize events and mutexes
-+ */
-+
-+ sema_init(&state->connect, 0);
-+ mutex_init(&state->mutex);
-+ sema_init(&state->trigger_event, 0);
-+ sema_init(&state->recycle_event, 0);
-+ sema_init(&state->sync_trigger_event, 0);
-+ sema_init(&state->sync_release_event, 0);
-+
-+ mutex_init(&state->slot_mutex);
-+ mutex_init(&state->recycle_mutex);
-+ mutex_init(&state->sync_mutex);
-+ mutex_init(&state->bulk_transfer_mutex);
-+
-+ sema_init(&state->slot_available_event, 0);
-+ sema_init(&state->slot_remove_event, 0);
-+ sema_init(&state->data_quota_event, 0);
-+
-+ state->slot_queue_available = 0;
-+
-+ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &state->service_quotas[i];
-+ sema_init(&service_quota->quota_event, 0);
-+ }
-+
-+ for (i = local->slot_first; i <= local->slot_last; i++) {
-+ local->slot_queue[state->slot_queue_available++] = i;
-+ up(&state->slot_available_event);
-+ }
-+
-+ state->default_slot_quota = state->slot_queue_available/2;
-+ state->default_message_quota =
-+ min((unsigned short)(state->default_slot_quota * 256),
-+ (unsigned short)~0);
-+
-+ state->previous_data_index = -1;
-+ state->data_use_count = 0;
-+ state->data_quota = state->slot_queue_available - 1;
-+
-+ local->trigger.event = &state->trigger_event;
-+ remote_event_create(&local->trigger);
-+ local->tx_pos = 0;
-+
-+ local->recycle.event = &state->recycle_event;
-+ remote_event_create(&local->recycle);
-+ local->slot_queue_recycle = state->slot_queue_available;
-+
-+ local->sync_trigger.event = &state->sync_trigger_event;
-+ remote_event_create(&local->sync_trigger);
-+
-+ local->sync_release.event = &state->sync_release_event;
-+ remote_event_create(&local->sync_release);
-+
-+ /* At start-of-day, the slot is empty and available */
-+ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid
-+ = VCHIQ_MSGID_PADDING;
-+ remote_event_signal_local(&local->sync_release);
-+
-+ local->debug[DEBUG_ENTRIES] = DEBUG_MAX;
-+
-+ status = vchiq_platform_init_state(state);
-+
-+ /*
-+ bring up slot handler thread
-+ */
-+ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id);
-+ state->slot_handler_thread = kthread_create(&slot_handler_func,
-+ (void *)state,
-+ threadname);
-+
-+ if (state->slot_handler_thread == NULL) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("couldn't create thread %s", threadname);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+ set_user_nice(state->slot_handler_thread, -19);
-+ wake_up_process(state->slot_handler_thread);
-+
-+ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id);
-+ state->recycle_thread = kthread_create(&recycle_func,
-+ (void *)state,
-+ threadname);
-+ if (state->recycle_thread == NULL) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("couldn't create thread %s", threadname);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+ set_user_nice(state->recycle_thread, -19);
-+ wake_up_process(state->recycle_thread);
-+
-+ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id);
-+ state->sync_thread = kthread_create(&sync_func,
-+ (void *)state,
-+ threadname);
-+ if (state->sync_thread == NULL) {
-+ vchiq_loud_error_header();
-+ vchiq_loud_error("couldn't create thread %s", threadname);
-+ vchiq_loud_error_footer();
-+ return VCHIQ_ERROR;
-+ }
-+ set_user_nice(state->sync_thread, -20);
-+ wake_up_process(state->sync_thread);
-+
-+ BUG_ON(state->id >= VCHIQ_MAX_STATES);
-+ vchiq_states[state->id] = state;
-+
-+ /* Indicate readiness to the other side */
-+ local->initialised = 1;
-+
-+ return status;
-+}
-+
-+/* Called from application thread when a client or server service is created. */
-+VCHIQ_SERVICE_T *
-+vchiq_add_service_internal(VCHIQ_STATE_T *state,
-+ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate,
-+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term)
-+{
-+ VCHIQ_SERVICE_T *service;
-+
-+ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL);
-+ if (service) {
-+ service->base.fourcc = params->fourcc;
-+ service->base.callback = params->callback;
-+ service->base.userdata = params->userdata;
-+ service->handle = VCHIQ_SERVICE_HANDLE_INVALID;
-+ service->ref_count = 1;
-+ service->srvstate = VCHIQ_SRVSTATE_FREE;
-+ service->userdata_term = userdata_term;
-+ service->localport = VCHIQ_PORT_FREE;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+
-+ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ?
-+ VCHIQ_FOURCC_INVALID : params->fourcc;
-+ service->client_id = 0;
-+ service->auto_close = 1;
-+ service->sync = 0;
-+ service->closing = 0;
-+ service->trace = 0;
-+ atomic_set(&service->poll_flags, 0);
-+ service->version = params->version;
-+ service->version_min = params->version_min;
-+ service->state = state;
-+ service->instance = instance;
-+ service->service_use_count = 0;
-+ init_bulk_queue(&service->bulk_tx);
-+ init_bulk_queue(&service->bulk_rx);
-+ sema_init(&service->remove_event, 0);
-+ sema_init(&service->bulk_remove_event, 0);
-+ mutex_init(&service->bulk_mutex);
-+ memset(&service->stats, 0, sizeof(service->stats));
-+ } else {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "Out of memory");
-+ }
-+
-+ if (service) {
-+ VCHIQ_SERVICE_T **pservice = NULL;
-+ int i;
-+
-+ /* Although it is perfectly possible to use service_spinlock
-+ ** to protect the creation of services, it is overkill as it
-+ ** disables interrupts while the array is searched.
-+ ** The only danger is of another thread trying to create a
-+ ** service - service deletion is safe.
-+ ** Therefore it is preferable to use state->mutex which,
-+ ** although slower to claim, doesn't block interrupts while
-+ ** it is held.
-+ */
-+
-+ mutex_lock(&state->mutex);
-+
-+ /* Prepare to use a previously unused service */
-+ if (state->unused_service < VCHIQ_MAX_SERVICES)
-+ pservice = &state->services[state->unused_service];
-+
-+ if (srvstate == VCHIQ_SRVSTATE_OPENING) {
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *srv = state->services[i];
-+ if (!srv) {
-+ pservice = &state->services[i];
-+ break;
-+ }
-+ }
-+ } else {
-+ for (i = (state->unused_service - 1); i >= 0; i--) {
-+ VCHIQ_SERVICE_T *srv = state->services[i];
-+ if (!srv)
-+ pservice = &state->services[i];
-+ else if ((srv->public_fourcc == params->fourcc)
-+ && ((srv->instance != instance) ||
-+ (srv->base.callback !=
-+ params->callback))) {
-+ /* There is another server using this
-+ ** fourcc which doesn't match. */
-+ pservice = NULL;
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (pservice) {
-+ service->localport = (pservice - state->services);
-+ if (!handle_seq)
-+ handle_seq = VCHIQ_MAX_STATES *
-+ VCHIQ_MAX_SERVICES;
-+ service->handle = handle_seq |
-+ (state->id * VCHIQ_MAX_SERVICES) |
-+ service->localport;
-+ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES;
-+ *pservice = service;
-+ if (pservice == &state->services[state->unused_service])
-+ state->unused_service++;
-+ }
-+
-+ mutex_unlock(&state->mutex);
-+
-+ if (!pservice) {
-+ kfree(service);
-+ service = NULL;
-+ }
-+ }
-+
-+ if (service) {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &state->service_quotas[service->localport];
-+ service_quota->slot_quota = state->default_slot_quota;
-+ service_quota->message_quota = state->default_message_quota;
-+ if (service_quota->slot_use_count == 0)
-+ service_quota->previous_tx_index =
-+ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos)
-+ - 1;
-+
-+ /* Bring this service online */
-+ vchiq_set_service_state(service, srvstate);
-+
-+ vchiq_log_info(vchiq_core_msg_log_level,
-+ "%s Service %c%c%c%c SrcPort:%d",
-+ (srvstate == VCHIQ_SRVSTATE_OPENING)
-+ ? "Open" : "Add",
-+ VCHIQ_FOURCC_AS_4CHARS(params->fourcc),
-+ service->localport);
-+ }
-+
-+ /* Don't unlock the service - leave it with a ref_count of 1. */
-+
-+ return service;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id)
-+{
-+ struct vchiq_open_payload payload = {
-+ service->base.fourcc,
-+ client_id,
-+ service->version,
-+ service->version_min
-+ };
-+ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) };
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ service->client_id = client_id;
-+ vchiq_use_service_internal(service);
-+ status = queue_message(service->state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0),
-+ &body, 1, sizeof(payload), QMFLAGS_IS_BLOCKING);
-+ if (status == VCHIQ_SUCCESS) {
-+ /* Wait for the ACK/NAK */
-+ if (down_interruptible(&service->remove_event) != 0) {
-+ status = VCHIQ_RETRY;
-+ vchiq_release_service_internal(service);
-+ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) {
-+ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: osi - srvstate = %s (ref %d)",
-+ service->state->id,
-+ srvstate_names[service->srvstate],
-+ service->ref_count);
-+ status = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_STATS_INC(service, error_count);
-+ vchiq_release_service_internal(service);
-+ }
-+ }
-+ return status;
-+}
-+
-+static void
-+release_service_messages(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ int slot_last = state->remote->slot_last;
-+ int i;
-+
-+ /* Release any claimed messages aimed at this service */
-+
-+ if (service->sync) {
-+ VCHIQ_HEADER_T *header =
-+ (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state,
-+ state->remote->slot_sync);
-+ if (VCHIQ_MSG_DSTPORT(header->msgid) == service->localport)
-+ release_message_sync(state, header);
-+
-+ return;
-+ }
-+
-+ for (i = state->remote->slot_first; i <= slot_last; i++) {
-+ VCHIQ_SLOT_INFO_T *slot_info =
-+ SLOT_INFO_FROM_INDEX(state, i);
-+ if (slot_info->release_count != slot_info->use_count) {
-+ char *data =
-+ (char *)SLOT_DATA_FROM_INDEX(state, i);
-+ unsigned int pos, end;
-+
-+ end = VCHIQ_SLOT_SIZE;
-+ if (data == state->rx_data)
-+ /* This buffer is still being read from - stop
-+ ** at the current read position */
-+ end = state->rx_pos & VCHIQ_SLOT_MASK;
-+
-+ pos = 0;
-+
-+ while (pos < end) {
-+ VCHIQ_HEADER_T *header =
-+ (VCHIQ_HEADER_T *)(data + pos);
-+ int msgid = header->msgid;
-+ int port = VCHIQ_MSG_DSTPORT(msgid);
-+ if ((port == service->localport) &&
-+ (msgid & VCHIQ_MSGID_CLAIMED)) {
-+ vchiq_log_info(vchiq_core_log_level,
-+ " fsi - hdr %x",
-+ (unsigned int)header);
-+ release_slot(state, slot_info, header,
-+ NULL);
-+ }
-+ pos += calc_stride(header->size);
-+ if (pos > VCHIQ_SLOT_SIZE) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "fsi - pos %x: header %x, "
-+ "msgid %x, header->msgid %x, "
-+ "header->size %x",
-+ pos, (unsigned int)header,
-+ msgid, header->msgid,
-+ header->size);
-+ WARN(1, "invalid slot position\n");
-+ }
-+ }
-+ }
-+ }
-+}
-+
-+static int
-+do_abort_bulks(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATUS_T status;
-+
-+ /* Abort any outstanding bulk transfers */
-+ if (mutex_lock_interruptible(&service->bulk_mutex) != 0)
-+ return 0;
-+ abort_outstanding_bulks(service, &service->bulk_tx);
-+ abort_outstanding_bulks(service, &service->bulk_rx);
-+ mutex_unlock(&service->bulk_mutex);
-+
-+ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/);
-+ if (status == VCHIQ_SUCCESS)
-+ status = notify_bulks(service, &service->bulk_rx,
-+ 0/*!retry_poll*/);
-+ return (status == VCHIQ_SUCCESS);
-+}
-+
-+static VCHIQ_STATUS_T
-+close_service_complete(VCHIQ_SERVICE_T *service, int failstate)
-+{
-+ VCHIQ_STATUS_T status;
-+ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID);
-+ int newstate;
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_OPEN:
-+ case VCHIQ_SRVSTATE_CLOSESENT:
-+ case VCHIQ_SRVSTATE_CLOSERECVD:
-+ if (is_server) {
-+ if (service->auto_close) {
-+ service->client_id = 0;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+ newstate = VCHIQ_SRVSTATE_LISTENING;
-+ } else
-+ newstate = VCHIQ_SRVSTATE_CLOSEWAIT;
-+ } else
-+ newstate = VCHIQ_SRVSTATE_CLOSED;
-+ vchiq_set_service_state(service, newstate);
-+ break;
-+ case VCHIQ_SRVSTATE_LISTENING:
-+ break;
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "close_service_complete(%x) called in state %s",
-+ service->handle, srvstate_names[service->srvstate]);
-+ WARN(1, "close_service_complete in unexpected state\n");
-+ return VCHIQ_ERROR;
-+ }
-+
-+ status = make_service_callback(service,
-+ VCHIQ_SERVICE_CLOSED, NULL, NULL);
-+
-+ if (status != VCHIQ_RETRY) {
-+ int uc = service->service_use_count;
-+ int i;
-+ /* Complete the close process */
-+ for (i = 0; i < uc; i++)
-+ /* cater for cases where close is forced and the
-+ ** client may not close all it's handles */
-+ vchiq_release_service_internal(service);
-+
-+ service->client_id = 0;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+
-+ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED)
-+ vchiq_free_service_internal(service);
-+ else if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) {
-+ if (is_server)
-+ service->closing = 0;
-+
-+ up(&service->remove_event);
-+ }
-+ } else
-+ vchiq_set_service_state(service, failstate);
-+
-+ return status;
-+}
-+
-+/* Called by the slot handler */
-+VCHIQ_STATUS_T
-+vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID);
-+
-+ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)",
-+ service->state->id, service->localport, close_recvd,
-+ srvstate_names[service->srvstate]);
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_CLOSED:
-+ case VCHIQ_SRVSTATE_HIDDEN:
-+ case VCHIQ_SRVSTATE_LISTENING:
-+ case VCHIQ_SRVSTATE_CLOSEWAIT:
-+ if (close_recvd)
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_close_service_internal(1) called "
-+ "in state %s",
-+ srvstate_names[service->srvstate]);
-+ else if (is_server) {
-+ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) {
-+ status = VCHIQ_ERROR;
-+ } else {
-+ service->client_id = 0;
-+ service->remoteport = VCHIQ_PORT_FREE;
-+ if (service->srvstate ==
-+ VCHIQ_SRVSTATE_CLOSEWAIT)
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_LISTENING);
-+ }
-+ up(&service->remove_event);
-+ } else
-+ vchiq_free_service_internal(service);
-+ break;
-+ case VCHIQ_SRVSTATE_OPENING:
-+ if (close_recvd) {
-+ /* The open was rejected - tell the user */
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_CLOSEWAIT);
-+ up(&service->remove_event);
-+ } else {
-+ /* Shutdown mid-open - let the other side know */
-+ status = queue_message(state, service,
-+ VCHIQ_MAKE_MSG
-+ (VCHIQ_MSG_CLOSE,
-+ service->localport,
-+ VCHIQ_MSG_DSTPORT(service->remoteport)),
-+ NULL, 0, 0, 0);
-+ }
-+ break;
-+
-+ case VCHIQ_SRVSTATE_OPENSYNC:
-+ mutex_lock(&state->sync_mutex);
-+ /* Drop through */
-+
-+ case VCHIQ_SRVSTATE_OPEN:
-+ if (state->is_master || close_recvd) {
-+ if (!do_abort_bulks(service))
-+ status = VCHIQ_RETRY;
-+ }
-+
-+ release_service_messages(service);
-+
-+ if (status == VCHIQ_SUCCESS)
-+ status = queue_message(state, service,
-+ VCHIQ_MAKE_MSG
-+ (VCHIQ_MSG_CLOSE,
-+ service->localport,
-+ VCHIQ_MSG_DSTPORT(service->remoteport)),
-+ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK);
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ if (!close_recvd) {
-+ /* Change the state while the mutex is
-+ still held */
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_CLOSESENT);
-+ mutex_unlock(&state->slot_mutex);
-+ if (service->sync)
-+ mutex_unlock(&state->sync_mutex);
-+ break;
-+ }
-+ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) {
-+ mutex_unlock(&state->sync_mutex);
-+ break;
-+ } else
-+ break;
-+
-+ /* Change the state while the mutex is still held */
-+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSERECVD);
-+ mutex_unlock(&state->slot_mutex);
-+ if (service->sync)
-+ mutex_unlock(&state->sync_mutex);
-+
-+ status = close_service_complete(service,
-+ VCHIQ_SRVSTATE_CLOSERECVD);
-+ break;
-+
-+ case VCHIQ_SRVSTATE_CLOSESENT:
-+ if (!close_recvd)
-+ /* This happens when a process is killed mid-close */
-+ break;
-+
-+ if (!state->is_master) {
-+ if (!do_abort_bulks(service)) {
-+ status = VCHIQ_RETRY;
-+ break;
-+ }
-+ }
-+
-+ if (status == VCHIQ_SUCCESS)
-+ status = close_service_complete(service,
-+ VCHIQ_SRVSTATE_CLOSERECVD);
-+ break;
-+
-+ case VCHIQ_SRVSTATE_CLOSERECVD:
-+ if (!close_recvd && is_server)
-+ /* Force into LISTENING mode */
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_LISTENING);
-+ status = close_service_complete(service,
-+ VCHIQ_SRVSTATE_CLOSERECVD);
-+ break;
-+
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_close_service_internal(%d) called in state %s",
-+ close_recvd, srvstate_names[service->srvstate]);
-+ break;
-+ }
-+
-+ return status;
-+}
-+
-+/* Called from the application process upon process death */
-+void
-+vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+
-+ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)",
-+ state->id, service->localport, service->remoteport);
-+
-+ mark_service_closing(service);
-+
-+ /* Mark the service for removal by the slot handler */
-+ request_poll(state, service, VCHIQ_POLL_REMOVE);
-+}
-+
-+/* Called from the slot handler */
-+void
-+vchiq_free_service_internal(VCHIQ_SERVICE_T *service)
-+{
-+ VCHIQ_STATE_T *state = service->state;
-+
-+ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)",
-+ state->id, service->localport);
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_OPENING:
-+ case VCHIQ_SRVSTATE_CLOSED:
-+ case VCHIQ_SRVSTATE_HIDDEN:
-+ case VCHIQ_SRVSTATE_LISTENING:
-+ case VCHIQ_SRVSTATE_CLOSEWAIT:
-+ break;
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%d: fsi - (%d) in state %s",
-+ state->id, service->localport,
-+ srvstate_names[service->srvstate]);
-+ return;
-+ }
-+
-+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE);
-+
-+ up(&service->remove_event);
-+
-+ /* Release the initial lock */
-+ unlock_service(service);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+
-+ /* Find all services registered to this client and enable them. */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance,
-+ &i)) != NULL) {
-+ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)
-+ vchiq_set_service_state(service,
-+ VCHIQ_SRVSTATE_LISTENING);
-+ unlock_service(service);
-+ }
-+
-+ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) {
-+ if (queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0,
-+ 0, QMFLAGS_IS_BLOCKING) == VCHIQ_RETRY)
-+ return VCHIQ_RETRY;
-+
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING);
-+ }
-+
-+ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) {
-+ if (down_interruptible(&state->connect) != 0)
-+ return VCHIQ_RETRY;
-+
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED);
-+ up(&state->connect);
-+ }
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_SERVICE_T *service;
-+ int i;
-+
-+ /* Find all services registered to this client and enable them. */
-+ i = 0;
-+ while ((service = next_service_by_instance(state, instance,
-+ &i)) != NULL) {
-+ (void)vchiq_remove_service(service->handle);
-+ unlock_service(service);
-+ }
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_pause_internal(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ switch (state->conn_state) {
-+ case VCHIQ_CONNSTATE_CONNECTED:
-+ /* Request a pause */
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING);
-+ request_poll(state, NULL, 0);
-+ break;
-+ default:
-+ vchiq_log_error(vchiq_core_log_level,
-+ "vchiq_pause_internal in state %s\n",
-+ conn_state_names[state->conn_state]);
-+ status = VCHIQ_ERROR;
-+ VCHIQ_STATS_INC(state, error_count);
-+ break;
-+ }
-+
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_resume_internal(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) {
-+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING);
-+ request_poll(state, NULL, 0);
-+ } else {
-+ status = VCHIQ_ERROR;
-+ VCHIQ_STATS_INC(state, error_count);
-+ }
-+
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ /* Unregister the service */
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (!service)
-+ return VCHIQ_ERROR;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: close_service:%d",
-+ service->state->id, service->localport);
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) {
-+ unlock_service(service);
-+ return VCHIQ_ERROR;
-+ }
-+
-+ mark_service_closing(service);
-+
-+ if (current == service->state->slot_handler_thread) {
-+ status = vchiq_close_service_internal(service,
-+ 0/*!close_recvd*/);
-+ BUG_ON(status == VCHIQ_RETRY);
-+ } else {
-+ /* Mark the service for termination by the slot handler */
-+ request_poll(service->state, service, VCHIQ_POLL_TERMINATE);
-+ }
-+
-+ while (1) {
-+ if (down_interruptible(&service->remove_event) != 0) {
-+ status = VCHIQ_RETRY;
-+ break;
-+ }
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_OPEN))
-+ break;
-+
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: close_service:%d - waiting in state %s",
-+ service->state->id, service->localport,
-+ srvstate_names[service->srvstate]);
-+ }
-+
-+ if ((status == VCHIQ_SUCCESS) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_FREE) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_LISTENING))
-+ status = VCHIQ_ERROR;
-+
-+ unlock_service(service);
-+
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ /* Unregister the service */
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS;
-+
-+ if (!service)
-+ return VCHIQ_ERROR;
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: remove_service:%d",
-+ service->state->id, service->localport);
-+
-+ if (service->srvstate == VCHIQ_SRVSTATE_FREE) {
-+ unlock_service(service);
-+ return VCHIQ_ERROR;
-+ }
-+
-+ mark_service_closing(service);
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ||
-+ (current == service->state->slot_handler_thread)) {
-+ /* Make it look like a client, because it must be removed and
-+ not left in the LISTENING state. */
-+ service->public_fourcc = VCHIQ_FOURCC_INVALID;
-+
-+ status = vchiq_close_service_internal(service,
-+ 0/*!close_recvd*/);
-+ BUG_ON(status == VCHIQ_RETRY);
-+ } else {
-+ /* Mark the service for removal by the slot handler */
-+ request_poll(service->state, service, VCHIQ_POLL_REMOVE);
-+ }
-+ while (1) {
-+ if (down_interruptible(&service->remove_event) != 0) {
-+ status = VCHIQ_RETRY;
-+ break;
-+ }
-+
-+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) ||
-+ (service->srvstate == VCHIQ_SRVSTATE_OPEN))
-+ break;
-+
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%d: remove_service:%d - waiting in state %s",
-+ service->state->id, service->localport,
-+ srvstate_names[service->srvstate]);
-+ }
-+
-+ if ((status == VCHIQ_SUCCESS) &&
-+ (service->srvstate != VCHIQ_SRVSTATE_FREE))
-+ status = VCHIQ_ERROR;
-+
-+ unlock_service(service);
-+
-+ return status;
-+}
-+
-+
-+/* This function may be called by kernel threads or user threads.
-+ * User threads may receive VCHIQ_RETRY to indicate that a signal has been
-+ * received and the call should be retried after being returned to user
-+ * context.
-+ * When called in blocking mode, the userdata field points to a bulk_waiter
-+ * structure.
-+ */
-+VCHIQ_STATUS_T
-+vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_BULK_QUEUE_T *queue;
-+ VCHIQ_BULK_T *bulk;
-+ VCHIQ_STATE_T *state;
-+ struct bulk_waiter *bulk_waiter = NULL;
-+ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r';
-+ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ?
-+ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX;
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+
-+ if (!service ||
-+ (service->srvstate != VCHIQ_SRVSTATE_OPEN) ||
-+ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) ||
-+ (vchiq_check_service(service) != VCHIQ_SUCCESS))
-+ goto error_exit;
-+
-+ switch (mode) {
-+ case VCHIQ_BULK_MODE_NOCALLBACK:
-+ case VCHIQ_BULK_MODE_CALLBACK:
-+ break;
-+ case VCHIQ_BULK_MODE_BLOCKING:
-+ bulk_waiter = (struct bulk_waiter *)userdata;
-+ sema_init(&bulk_waiter->event, 0);
-+ bulk_waiter->actual = 0;
-+ bulk_waiter->bulk = NULL;
-+ break;
-+ case VCHIQ_BULK_MODE_WAITING:
-+ bulk_waiter = (struct bulk_waiter *)userdata;
-+ bulk = bulk_waiter->bulk;
-+ goto waiting;
-+ default:
-+ goto error_exit;
-+ }
-+
-+ state = service->state;
-+
-+ queue = (dir == VCHIQ_BULK_TRANSMIT) ?
-+ &service->bulk_tx : &service->bulk_rx;
-+
-+ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) {
-+ status = VCHIQ_RETRY;
-+ goto error_exit;
-+ }
-+
-+ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) {
-+ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls);
-+ do {
-+ mutex_unlock(&service->bulk_mutex);
-+ if (down_interruptible(&service->bulk_remove_event)
-+ != 0) {
-+ status = VCHIQ_RETRY;
-+ goto error_exit;
-+ }
-+ if (mutex_lock_interruptible(&service->bulk_mutex)
-+ != 0) {
-+ status = VCHIQ_RETRY;
-+ goto error_exit;
-+ }
-+ } while (queue->local_insert == queue->remove +
-+ VCHIQ_NUM_SERVICE_BULKS);
-+ }
-+
-+ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)];
-+
-+ bulk->mode = mode;
-+ bulk->dir = dir;
-+ bulk->userdata = userdata;
-+ bulk->size = size;
-+ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED;
-+
-+ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) !=
-+ VCHIQ_SUCCESS)
-+ goto unlock_error_exit;
-+
-+ wmb();
-+
-+ vchiq_log_info(vchiq_core_log_level,
-+ "%d: bt (%d->%d) %cx %x@%x %x",
-+ state->id,
-+ service->localport, service->remoteport, dir_char,
-+ size, (unsigned int)bulk->data, (unsigned int)userdata);
-+
-+ /* The slot mutex must be held when the service is being closed, so
-+ claim it here to ensure that isn't happening */
-+ if (mutex_lock_interruptible(&state->slot_mutex) != 0) {
-+ status = VCHIQ_RETRY;
-+ goto cancel_bulk_error_exit;
-+ }
-+
-+ if (service->srvstate != VCHIQ_SRVSTATE_OPEN)
-+ goto unlock_both_error_exit;
-+
-+ if (state->is_master) {
-+ queue->local_insert++;
-+ if (resolve_bulks(service, queue))
-+ request_poll(state, service,
-+ (dir == VCHIQ_BULK_TRANSMIT) ?
-+ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY);
-+ } else {
-+ int payload[2] = { (int)bulk->data, bulk->size };
-+ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) };
-+
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(dir_msgtype,
-+ service->localport, service->remoteport),
-+ &element, 1, sizeof(payload),
-+ QMFLAGS_IS_BLOCKING |
-+ QMFLAGS_NO_MUTEX_LOCK |
-+ QMFLAGS_NO_MUTEX_UNLOCK);
-+ if (status != VCHIQ_SUCCESS) {
-+ goto unlock_both_error_exit;
-+ }
-+ queue->local_insert++;
-+ }
-+
-+ mutex_unlock(&state->slot_mutex);
-+ mutex_unlock(&service->bulk_mutex);
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%d: bt:%d %cx li=%x ri=%x p=%x",
-+ state->id,
-+ service->localport, dir_char,
-+ queue->local_insert, queue->remote_insert, queue->process);
-+
-+waiting:
-+ unlock_service(service);
-+
-+ status = VCHIQ_SUCCESS;
-+
-+ if (bulk_waiter) {
-+ bulk_waiter->bulk = bulk;
-+ if (down_interruptible(&bulk_waiter->event) != 0)
-+ status = VCHIQ_RETRY;
-+ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED)
-+ status = VCHIQ_ERROR;
-+ }
-+
-+ return status;
-+
-+unlock_both_error_exit:
-+ mutex_unlock(&state->slot_mutex);
-+cancel_bulk_error_exit:
-+ vchiq_complete_bulk(bulk);
-+unlock_error_exit:
-+ mutex_unlock(&service->bulk_mutex);
-+
-+error_exit:
-+ if (service)
-+ unlock_service(service);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle,
-+ const VCHIQ_ELEMENT_T *elements, unsigned int count)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+
-+ unsigned int size = 0;
-+ unsigned int i;
-+
-+ if (!service ||
-+ (vchiq_check_service(service) != VCHIQ_SUCCESS))
-+ goto error_exit;
-+
-+ for (i = 0; i < (unsigned int)count; i++) {
-+ if (elements[i].size) {
-+ if (elements[i].data == NULL) {
-+ VCHIQ_SERVICE_STATS_INC(service, error_count);
-+ goto error_exit;
-+ }
-+ size += elements[i].size;
-+ }
-+ }
-+
-+ if (size > VCHIQ_MAX_MSG_SIZE) {
-+ VCHIQ_SERVICE_STATS_INC(service, error_count);
-+ goto error_exit;
-+ }
-+
-+ switch (service->srvstate) {
-+ case VCHIQ_SRVSTATE_OPEN:
-+ status = queue_message(service->state, service,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
-+ service->localport,
-+ service->remoteport),
-+ elements, count, size, 1);
-+ break;
-+ case VCHIQ_SRVSTATE_OPENSYNC:
-+ status = queue_message_sync(service->state, service,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA,
-+ service->localport,
-+ service->remoteport),
-+ elements, count, size, 1);
-+ break;
-+ default:
-+ status = VCHIQ_ERROR;
-+ break;
-+ }
-+
-+error_exit:
-+ if (service)
-+ unlock_service(service);
-+
-+ return status;
-+}
-+
-+void
-+vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_SHARED_STATE_T *remote;
-+ VCHIQ_STATE_T *state;
-+ int slot_index;
-+
-+ if (!service)
-+ return;
-+
-+ state = service->state;
-+ remote = state->remote;
-+
-+ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header);
-+
-+ if ((slot_index >= remote->slot_first) &&
-+ (slot_index <= remote->slot_last)) {
-+ int msgid = header->msgid;
-+ if (msgid & VCHIQ_MSGID_CLAIMED) {
-+ VCHIQ_SLOT_INFO_T *slot_info =
-+ SLOT_INFO_FROM_INDEX(state, slot_index);
-+
-+ release_slot(state, slot_info, header, service);
-+ }
-+ } else if (slot_index == remote->slot_sync)
-+ release_message_sync(state, header);
-+
-+ unlock_service(service);
-+}
-+
-+static void
-+release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header)
-+{
-+ header->msgid = VCHIQ_MSGID_PADDING;
-+ wmb();
-+ remote_event_signal(&state->remote->sync_release);
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, short *peer_version)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+
-+ if (!service ||
-+ (vchiq_check_service(service) != VCHIQ_SUCCESS) ||
-+ !peer_version)
-+ goto exit;
-+ *peer_version = service->peer_version;
-+ status = VCHIQ_SUCCESS;
-+
-+exit:
-+ if (service)
-+ unlock_service(service);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_get_config(VCHIQ_INSTANCE_T instance,
-+ int config_size, VCHIQ_CONFIG_T *pconfig)
-+{
-+ VCHIQ_CONFIG_T config;
-+
-+ (void)instance;
-+
-+ config.max_msg_size = VCHIQ_MAX_MSG_SIZE;
-+ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE;
-+ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS;
-+ config.max_services = VCHIQ_MAX_SERVICES;
-+ config.version = VCHIQ_VERSION;
-+ config.version_min = VCHIQ_VERSION_MIN;
-+
-+ if (config_size > sizeof(VCHIQ_CONFIG_T))
-+ return VCHIQ_ERROR;
-+
-+ memcpy(pconfig, &config,
-+ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T))));
-+
-+ return VCHIQ_SUCCESS;
-+}
-+
-+VCHIQ_STATUS_T
-+vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle,
-+ VCHIQ_SERVICE_OPTION_T option, int value)
-+{
-+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle);
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+
-+ if (service) {
-+ switch (option) {
-+ case VCHIQ_SERVICE_OPTION_AUTOCLOSE:
-+ service->auto_close = value;
-+ status = VCHIQ_SUCCESS;
-+ break;
-+
-+ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &service->state->service_quotas[
-+ service->localport];
-+ if (value == 0)
-+ value = service->state->default_slot_quota;
-+ if ((value >= service_quota->slot_use_count) &&
-+ (value < (unsigned short)~0)) {
-+ service_quota->slot_quota = value;
-+ if ((value >= service_quota->slot_use_count) &&
-+ (service_quota->message_quota >=
-+ service_quota->message_use_count)) {
-+ /* Signal the service that it may have
-+ ** dropped below its quota */
-+ up(&service_quota->quota_event);
-+ }
-+ status = VCHIQ_SUCCESS;
-+ }
-+ } break;
-+
-+ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: {
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &service->state->service_quotas[
-+ service->localport];
-+ if (value == 0)
-+ value = service->state->default_message_quota;
-+ if ((value >= service_quota->message_use_count) &&
-+ (value < (unsigned short)~0)) {
-+ service_quota->message_quota = value;
-+ if ((value >=
-+ service_quota->message_use_count) &&
-+ (service_quota->slot_quota >=
-+ service_quota->slot_use_count))
-+ /* Signal the service that it may have
-+ ** dropped below its quota */
-+ up(&service_quota->quota_event);
-+ status = VCHIQ_SUCCESS;
-+ }
-+ } break;
-+
-+ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS:
-+ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ||
-+ (service->srvstate ==
-+ VCHIQ_SRVSTATE_LISTENING)) {
-+ service->sync = value;
-+ status = VCHIQ_SUCCESS;
-+ }
-+ break;
-+
-+ case VCHIQ_SERVICE_OPTION_TRACE:
-+ service->trace = value;
-+ status = VCHIQ_SUCCESS;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ unlock_service(service);
-+ }
-+
-+ return status;
-+}
-+
-+void
-+vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state,
-+ VCHIQ_SHARED_STATE_T *shared, const char *label)
-+{
-+ static const char *const debug_names[] = {
-+ "<entries>",
-+ "SLOT_HANDLER_COUNT",
-+ "SLOT_HANDLER_LINE",
-+ "PARSE_LINE",
-+ "PARSE_HEADER",
-+ "PARSE_MSGID",
-+ "AWAIT_COMPLETION_LINE",
-+ "DEQUEUE_MESSAGE_LINE",
-+ "SERVICE_CALLBACK_LINE",
-+ "MSG_QUEUE_FULL_COUNT",
-+ "COMPLETION_QUEUE_FULL_COUNT"
-+ };
-+ int i;
-+
-+ char buf[80];
-+ int len;
-+ len = snprintf(buf, sizeof(buf),
-+ " %s: slots %d-%d tx_pos=%x recycle=%x",
-+ label, shared->slot_first, shared->slot_last,
-+ shared->tx_pos, shared->slot_queue_recycle);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Slots claimed:");
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ for (i = shared->slot_first; i <= shared->slot_last; i++) {
-+ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i);
-+ if (slot_info.use_count != slot_info.release_count) {
-+ len = snprintf(buf, sizeof(buf),
-+ " %d: %d/%d", i, slot_info.use_count,
-+ slot_info.release_count);
-+ vchiq_dump(dump_context, buf, len + 1);
-+ }
-+ }
-+
-+ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) {
-+ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)",
-+ debug_names[i], shared->debug[i], shared->debug[i]);
-+ vchiq_dump(dump_context, buf, len + 1);
-+ }
-+}
-+
-+void
-+vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state)
-+{
-+ char buf[80];
-+ int len;
-+ int i;
-+
-+ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id,
-+ conn_state_names[state->conn_state]);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " tx_pos=%x(@%x), rx_pos=%x(@%x)",
-+ state->local->tx_pos,
-+ (uint32_t)state->tx_data +
-+ (state->local_tx_pos & VCHIQ_SLOT_MASK),
-+ state->rx_pos,
-+ (uint32_t)state->rx_data +
-+ (state->rx_pos & VCHIQ_SLOT_MASK));
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Version: %d (min %d)",
-+ VCHIQ_VERSION, VCHIQ_VERSION_MIN);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ if (VCHIQ_ENABLE_STATS) {
-+ len = snprintf(buf, sizeof(buf),
-+ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, "
-+ "error_count=%d",
-+ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count,
-+ state->stats.error_count);
-+ vchiq_dump(dump_context, buf, len + 1);
-+ }
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Slots: %d available (%d data), %d recyclable, %d stalls "
-+ "(%d data)",
-+ ((state->slot_queue_available * VCHIQ_SLOT_SIZE) -
-+ state->local_tx_pos) / VCHIQ_SLOT_SIZE,
-+ state->data_quota - state->data_use_count,
-+ state->local->slot_queue_recycle - state->slot_queue_available,
-+ state->stats.slot_stalls, state->stats.data_stalls);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ vchiq_dump_platform_state(dump_context);
-+
-+ vchiq_dump_shared_state(dump_context, state, state->local, "Local");
-+ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote");
-+
-+ vchiq_dump_platform_instances(dump_context);
-+
-+ for (i = 0; i < state->unused_service; i++) {
-+ VCHIQ_SERVICE_T *service = find_service_by_port(state, i);
-+
-+ if (service) {
-+ vchiq_dump_service_state(dump_context, service);
-+ unlock_service(service);
-+ }
-+ }
-+}
-+
-+void
-+vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service)
-+{
-+ char buf[80];
-+ int len;
-+
-+ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)",
-+ service->localport, srvstate_names[service->srvstate],
-+ service->ref_count - 1); /*Don't include the lock just taken*/
-+
-+ if (service->srvstate != VCHIQ_SRVSTATE_FREE) {
-+ char remoteport[30];
-+ VCHIQ_SERVICE_QUOTA_T *service_quota =
-+ &service->state->service_quotas[service->localport];
-+ int fourcc = service->base.fourcc;
-+ int tx_pending, rx_pending;
-+ if (service->remoteport != VCHIQ_PORT_FREE) {
-+ int len2 = snprintf(remoteport, sizeof(remoteport),
-+ "%d", service->remoteport);
-+ if (service->public_fourcc != VCHIQ_FOURCC_INVALID)
-+ snprintf(remoteport + len2,
-+ sizeof(remoteport) - len2,
-+ " (client %x)", service->client_id);
-+ } else
-+ strcpy(remoteport, "n/a");
-+
-+ len += snprintf(buf + len, sizeof(buf) - len,
-+ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)",
-+ VCHIQ_FOURCC_AS_4CHARS(fourcc),
-+ remoteport,
-+ service_quota->message_use_count,
-+ service_quota->message_quota,
-+ service_quota->slot_use_count,
-+ service_quota->slot_quota);
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ tx_pending = service->bulk_tx.local_insert -
-+ service->bulk_tx.remote_insert;
-+
-+ rx_pending = service->bulk_rx.local_insert -
-+ service->bulk_rx.remote_insert;
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Bulk: tx_pending=%d (size %d),"
-+ " rx_pending=%d (size %d)",
-+ tx_pending,
-+ tx_pending ? service->bulk_tx.bulks[
-+ BULK_INDEX(service->bulk_tx.remove)].size : 0,
-+ rx_pending,
-+ rx_pending ? service->bulk_rx.bulks[
-+ BULK_INDEX(service->bulk_rx.remove)].size : 0);
-+
-+ if (VCHIQ_ENABLE_STATS) {
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Ctrl: tx_count=%d, tx_bytes=%llu, "
-+ "rx_count=%d, rx_bytes=%llu",
-+ service->stats.ctrl_tx_count,
-+ service->stats.ctrl_tx_bytes,
-+ service->stats.ctrl_rx_count,
-+ service->stats.ctrl_rx_bytes);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " Bulk: tx_count=%d, tx_bytes=%llu, "
-+ "rx_count=%d, rx_bytes=%llu",
-+ service->stats.bulk_tx_count,
-+ service->stats.bulk_tx_bytes,
-+ service->stats.bulk_rx_count,
-+ service->stats.bulk_rx_bytes);
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ len = snprintf(buf, sizeof(buf),
-+ " %d quota stalls, %d slot stalls, "
-+ "%d bulk stalls, %d aborted, %d errors",
-+ service->stats.quota_stalls,
-+ service->stats.slot_stalls,
-+ service->stats.bulk_stalls,
-+ service->stats.bulk_aborted_count,
-+ service->stats.error_count);
-+ }
-+ }
-+
-+ vchiq_dump(dump_context, buf, len + 1);
-+
-+ if (service->srvstate != VCHIQ_SRVSTATE_FREE)
-+ vchiq_dump_platform_service_state(dump_context, service);
-+}
-+
-+
-+void
-+vchiq_loud_error_header(void)
-+{
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+ vchiq_log_error(vchiq_core_log_level, "=====");
-+}
-+
-+void
-+vchiq_loud_error_footer(void)
-+{
-+ vchiq_log_error(vchiq_core_log_level, "=====");
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+ vchiq_log_error(vchiq_core_log_level,
-+ "============================================================"
-+ "================");
-+}
-+
-+
-+VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_RETRY;
-+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0),
-+ NULL, 0, 0, 0);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_RETRY;
-+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0),
-+ NULL, 0, 0, 0);
-+ return status;
-+}
-+
-+VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_RETRY;
-+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED)
-+ status = queue_message(state, NULL,
-+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0),
-+ NULL, 0, 0, 0);
-+ return status;
-+}
-+
-+void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem,
-+ size_t numBytes)
-+{
-+ const uint8_t *mem = (const uint8_t *)voidMem;
-+ size_t offset;
-+ char lineBuf[100];
-+ char *s;
-+
-+ while (numBytes > 0) {
-+ s = lineBuf;
-+
-+ for (offset = 0; offset < 16; offset++) {
-+ if (offset < numBytes)
-+ s += snprintf(s, 4, "%02x ", mem[offset]);
-+ else
-+ s += snprintf(s, 4, " ");
-+ }
-+
-+ for (offset = 0; offset < 16; offset++) {
-+ if (offset < numBytes) {
-+ uint8_t ch = mem[offset];
-+
-+ if ((ch < ' ') || (ch > '~'))
-+ ch = '.';
-+ *s++ = (char)ch;
-+ }
-+ }
-+ *s++ = '\0';
-+
-+ if ((label != NULL) && (*label != '\0'))
-+ vchiq_log_trace(VCHIQ_LOG_TRACE,
-+ "%s: %08x: %s", label, addr, lineBuf);
-+ else
-+ vchiq_log_trace(VCHIQ_LOG_TRACE,
-+ "%08x: %s", addr, lineBuf);
-+
-+ addr += 16;
-+ mem += 16;
-+ if (numBytes > 16)
-+ numBytes -= 16;
-+ else
-+ numBytes = 0;
-+ }
-+}
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,712 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_CORE_H
-+#define VCHIQ_CORE_H
-+
-+#include <linux/mutex.h>
-+#include <linux/semaphore.h>
-+#include <linux/kthread.h>
-+
-+#include "vchiq_cfg.h"
-+
-+#include "vchiq.h"
-+
-+/* Run time control of log level, based on KERN_XXX level. */
-+#define VCHIQ_LOG_DEFAULT 4
-+#define VCHIQ_LOG_ERROR 3
-+#define VCHIQ_LOG_WARNING 4
-+#define VCHIQ_LOG_INFO 6
-+#define VCHIQ_LOG_TRACE 7
-+
-+#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: "
-+
-+#ifndef vchiq_log_error
-+#define vchiq_log_error(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_ERROR) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+#ifndef vchiq_log_warning
-+#define vchiq_log_warning(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_WARNING) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+#ifndef vchiq_log_info
-+#define vchiq_log_info(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_INFO) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+#ifndef vchiq_log_trace
-+#define vchiq_log_trace(cat, fmt, ...) \
-+ do { if (cat >= VCHIQ_LOG_TRACE) \
-+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0)
-+#endif
-+
-+#define vchiq_loud_error(...) \
-+ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__)
-+
-+#ifndef vchiq_static_assert
-+#define vchiq_static_assert(cond) __attribute__((unused)) \
-+ extern int vchiq_static_assert[(cond) ? 1 : -1]
-+#endif
-+
-+#define IS_POW2(x) (x && ((x & (x - 1)) == 0))
-+
-+/* Ensure that the slot size and maximum number of slots are powers of 2 */
-+vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE));
-+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS));
-+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE));
-+
-+#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1)
-+#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1)
-+#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \
-+ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE)
-+
-+#define VCHIQ_MSG_PADDING 0 /* - */
-+#define VCHIQ_MSG_CONNECT 1 /* - */
-+#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */
-+#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */
-+#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */
-+#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */
-+#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */
-+#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */
-+#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */
-+#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */
-+#define VCHIQ_MSG_PAUSE 10 /* - */
-+#define VCHIQ_MSG_RESUME 11 /* - */
-+#define VCHIQ_MSG_REMOTE_USE 12 /* - */
-+#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */
-+#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */
-+
-+#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1)
-+#define VCHIQ_PORT_FREE 0x1000
-+#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE)
-+#define VCHIQ_MAKE_MSG(type, srcport, dstport) \
-+ ((type<<24) | (srcport<<12) | (dstport<<0))
-+#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24)
-+#define VCHIQ_MSG_SRCPORT(msgid) \
-+ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff)
-+#define VCHIQ_MSG_DSTPORT(msgid) \
-+ ((unsigned short)msgid & 0xfff)
-+
-+#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \
-+ ((fourcc) >> 24) & 0xff, \
-+ ((fourcc) >> 16) & 0xff, \
-+ ((fourcc) >> 8) & 0xff, \
-+ (fourcc) & 0xff
-+
-+/* Ensure the fields are wide enough */
-+vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX))
-+ == 0);
-+vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0);
-+vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX <
-+ (unsigned int)VCHIQ_PORT_FREE);
-+
-+#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0)
-+#define VCHIQ_MSGID_CLAIMED 0x40000000
-+
-+#define VCHIQ_FOURCC_INVALID 0x00000000
-+#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID)
-+
-+#define VCHIQ_BULK_ACTUAL_ABORTED -1
-+
-+typedef uint32_t BITSET_T;
-+
-+vchiq_static_assert((sizeof(BITSET_T) * 8) == 32);
-+
-+#define BITSET_SIZE(b) ((b + 31) >> 5)
-+#define BITSET_WORD(b) (b >> 5)
-+#define BITSET_BIT(b) (1 << (b & 31))
-+#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs))
-+#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b))
-+#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b))
-+#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b))
-+
-+#if VCHIQ_ENABLE_STATS
-+#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++)
-+#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++)
-+#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \
-+ (service->stats. stat += addend)
-+#else
-+#define VCHIQ_STATS_INC(state, stat) ((void)0)
-+#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0)
-+#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0)
-+#endif
-+
-+enum {
-+ DEBUG_ENTRIES,
-+#if VCHIQ_ENABLE_DEBUG
-+ DEBUG_SLOT_HANDLER_COUNT,
-+ DEBUG_SLOT_HANDLER_LINE,
-+ DEBUG_PARSE_LINE,
-+ DEBUG_PARSE_HEADER,
-+ DEBUG_PARSE_MSGID,
-+ DEBUG_AWAIT_COMPLETION_LINE,
-+ DEBUG_DEQUEUE_MESSAGE_LINE,
-+ DEBUG_SERVICE_CALLBACK_LINE,
-+ DEBUG_MSG_QUEUE_FULL_COUNT,
-+ DEBUG_COMPLETION_QUEUE_FULL_COUNT,
-+#endif
-+ DEBUG_MAX
-+};
-+
-+#if VCHIQ_ENABLE_DEBUG
-+
-+#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug;
-+#define DEBUG_TRACE(d) \
-+ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0)
-+#define DEBUG_VALUE(d, v) \
-+ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0)
-+#define DEBUG_COUNT(d) \
-+ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0)
-+
-+#else /* VCHIQ_ENABLE_DEBUG */
-+
-+#define DEBUG_INITIALISE(local)
-+#define DEBUG_TRACE(d)
-+#define DEBUG_VALUE(d, v)
-+#define DEBUG_COUNT(d)
-+
-+#endif /* VCHIQ_ENABLE_DEBUG */
-+
-+typedef enum {
-+ VCHIQ_CONNSTATE_DISCONNECTED,
-+ VCHIQ_CONNSTATE_CONNECTING,
-+ VCHIQ_CONNSTATE_CONNECTED,
-+ VCHIQ_CONNSTATE_PAUSING,
-+ VCHIQ_CONNSTATE_PAUSE_SENT,
-+ VCHIQ_CONNSTATE_PAUSED,
-+ VCHIQ_CONNSTATE_RESUMING,
-+ VCHIQ_CONNSTATE_PAUSE_TIMEOUT,
-+ VCHIQ_CONNSTATE_RESUME_TIMEOUT
-+} VCHIQ_CONNSTATE_T;
-+
-+enum {
-+ VCHIQ_SRVSTATE_FREE,
-+ VCHIQ_SRVSTATE_HIDDEN,
-+ VCHIQ_SRVSTATE_LISTENING,
-+ VCHIQ_SRVSTATE_OPENING,
-+ VCHIQ_SRVSTATE_OPEN,
-+ VCHIQ_SRVSTATE_OPENSYNC,
-+ VCHIQ_SRVSTATE_CLOSESENT,
-+ VCHIQ_SRVSTATE_CLOSERECVD,
-+ VCHIQ_SRVSTATE_CLOSEWAIT,
-+ VCHIQ_SRVSTATE_CLOSED
-+};
-+
-+enum {
-+ VCHIQ_POLL_TERMINATE,
-+ VCHIQ_POLL_REMOVE,
-+ VCHIQ_POLL_TXNOTIFY,
-+ VCHIQ_POLL_RXNOTIFY,
-+ VCHIQ_POLL_COUNT
-+};
-+
-+typedef enum {
-+ VCHIQ_BULK_TRANSMIT,
-+ VCHIQ_BULK_RECEIVE
-+} VCHIQ_BULK_DIR_T;
-+
-+typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata);
-+
-+typedef struct vchiq_bulk_struct {
-+ short mode;
-+ short dir;
-+ void *userdata;
-+ VCHI_MEM_HANDLE_T handle;
-+ void *data;
-+ int size;
-+ void *remote_data;
-+ int remote_size;
-+ int actual;
-+} VCHIQ_BULK_T;
-+
-+typedef struct vchiq_bulk_queue_struct {
-+ int local_insert; /* Where to insert the next local bulk */
-+ int remote_insert; /* Where to insert the next remote bulk (master) */
-+ int process; /* Bulk to transfer next */
-+ int remote_notify; /* Bulk to notify the remote client of next (mstr) */
-+ int remove; /* Bulk to notify the local client of, and remove,
-+ ** next */
-+ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS];
-+} VCHIQ_BULK_QUEUE_T;
-+
-+typedef struct remote_event_struct {
-+ int armed;
-+ int fired;
-+ struct semaphore *event;
-+} REMOTE_EVENT_T;
-+
-+typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T;
-+
-+typedef struct vchiq_state_struct VCHIQ_STATE_T;
-+
-+typedef struct vchiq_slot_struct {
-+ char data[VCHIQ_SLOT_SIZE];
-+} VCHIQ_SLOT_T;
-+
-+typedef struct vchiq_slot_info_struct {
-+ /* Use two counters rather than one to avoid the need for a mutex. */
-+ short use_count;
-+ short release_count;
-+} VCHIQ_SLOT_INFO_T;
-+
-+typedef struct vchiq_service_struct {
-+ VCHIQ_SERVICE_BASE_T base;
-+ VCHIQ_SERVICE_HANDLE_T handle;
-+ unsigned int ref_count;
-+ int srvstate;
-+ VCHIQ_USERDATA_TERM_T userdata_term;
-+ unsigned int localport;
-+ unsigned int remoteport;
-+ int public_fourcc;
-+ int client_id;
-+ char auto_close;
-+ char sync;
-+ char closing;
-+ char trace;
-+ atomic_t poll_flags;
-+ short version;
-+ short version_min;
-+ short peer_version;
-+
-+ VCHIQ_STATE_T *state;
-+ VCHIQ_INSTANCE_T instance;
-+
-+ int service_use_count;
-+
-+ VCHIQ_BULK_QUEUE_T bulk_tx;
-+ VCHIQ_BULK_QUEUE_T bulk_rx;
-+
-+ struct semaphore remove_event;
-+ struct semaphore bulk_remove_event;
-+ struct mutex bulk_mutex;
-+
-+ struct service_stats_struct {
-+ int quota_stalls;
-+ int slot_stalls;
-+ int bulk_stalls;
-+ int error_count;
-+ int ctrl_tx_count;
-+ int ctrl_rx_count;
-+ int bulk_tx_count;
-+ int bulk_rx_count;
-+ int bulk_aborted_count;
-+ uint64_t ctrl_tx_bytes;
-+ uint64_t ctrl_rx_bytes;
-+ uint64_t bulk_tx_bytes;
-+ uint64_t bulk_rx_bytes;
-+ } stats;
-+} VCHIQ_SERVICE_T;
-+
-+/* The quota information is outside VCHIQ_SERVICE_T so that it can be
-+ statically allocated, since for accounting reasons a service's slot
-+ usage is carried over between users of the same port number.
-+ */
-+typedef struct vchiq_service_quota_struct {
-+ unsigned short slot_quota;
-+ unsigned short slot_use_count;
-+ unsigned short message_quota;
-+ unsigned short message_use_count;
-+ struct semaphore quota_event;
-+ int previous_tx_index;
-+} VCHIQ_SERVICE_QUOTA_T;
-+
-+typedef struct vchiq_shared_state_struct {
-+
-+ /* A non-zero value here indicates that the content is valid. */
-+ int initialised;
-+
-+ /* The first and last (inclusive) slots allocated to the owner. */
-+ int slot_first;
-+ int slot_last;
-+
-+ /* The slot allocated to synchronous messages from the owner. */
-+ int slot_sync;
-+
-+ /* Signalling this event indicates that owner's slot handler thread
-+ ** should run. */
-+ REMOTE_EVENT_T trigger;
-+
-+ /* Indicates the byte position within the stream where the next message
-+ ** will be written. The least significant bits are an index into the
-+ ** slot. The next bits are the index of the slot in slot_queue. */
-+ int tx_pos;
-+
-+ /* This event should be signalled when a slot is recycled. */
-+ REMOTE_EVENT_T recycle;
-+
-+ /* The slot_queue index where the next recycled slot will be written. */
-+ int slot_queue_recycle;
-+
-+ /* This event should be signalled when a synchronous message is sent. */
-+ REMOTE_EVENT_T sync_trigger;
-+
-+ /* This event should be signalled when a synchronous message has been
-+ ** released. */
-+ REMOTE_EVENT_T sync_release;
-+
-+ /* A circular buffer of slot indexes. */
-+ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE];
-+
-+ /* Debugging state */
-+ int debug[DEBUG_MAX];
-+} VCHIQ_SHARED_STATE_T;
-+
-+typedef struct vchiq_slot_zero_struct {
-+ int magic;
-+ short version;
-+ short version_min;
-+ int slot_zero_size;
-+ int slot_size;
-+ int max_slots;
-+ int max_slots_per_side;
-+ int platform_data[2];
-+ VCHIQ_SHARED_STATE_T master;
-+ VCHIQ_SHARED_STATE_T slave;
-+ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS];
-+} VCHIQ_SLOT_ZERO_T;
-+
-+struct vchiq_state_struct {
-+ int id;
-+ int initialised;
-+ VCHIQ_CONNSTATE_T conn_state;
-+ int is_master;
-+ short version_common;
-+
-+ VCHIQ_SHARED_STATE_T *local;
-+ VCHIQ_SHARED_STATE_T *remote;
-+ VCHIQ_SLOT_T *slot_data;
-+
-+ unsigned short default_slot_quota;
-+ unsigned short default_message_quota;
-+
-+ /* Event indicating connect message received */
-+ struct semaphore connect;
-+
-+ /* Mutex protecting services */
-+ struct mutex mutex;
-+ VCHIQ_INSTANCE_T *instance;
-+
-+ /* Processes incoming messages */
-+ struct task_struct *slot_handler_thread;
-+
-+ /* Processes recycled slots */
-+ struct task_struct *recycle_thread;
-+
-+ /* Processes synchronous messages */
-+ struct task_struct *sync_thread;
-+
-+ /* Local implementation of the trigger remote event */
-+ struct semaphore trigger_event;
-+
-+ /* Local implementation of the recycle remote event */
-+ struct semaphore recycle_event;
-+
-+ /* Local implementation of the sync trigger remote event */
-+ struct semaphore sync_trigger_event;
-+
-+ /* Local implementation of the sync release remote event */
-+ struct semaphore sync_release_event;
-+
-+ char *tx_data;
-+ char *rx_data;
-+ VCHIQ_SLOT_INFO_T *rx_info;
-+
-+ struct mutex slot_mutex;
-+
-+ struct mutex recycle_mutex;
-+
-+ struct mutex sync_mutex;
-+
-+ struct mutex bulk_transfer_mutex;
-+
-+ /* Indicates the byte position within the stream from where the next
-+ ** message will be read. The least significant bits are an index into
-+ ** the slot.The next bits are the index of the slot in
-+ ** remote->slot_queue. */
-+ int rx_pos;
-+
-+ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read
-+ from remote->tx_pos. */
-+ int local_tx_pos;
-+
-+ /* The slot_queue index of the slot to become available next. */
-+ int slot_queue_available;
-+
-+ /* A flag to indicate if any poll has been requested */
-+ int poll_needed;
-+
-+ /* Ths index of the previous slot used for data messages. */
-+ int previous_data_index;
-+
-+ /* The number of slots occupied by data messages. */
-+ unsigned short data_use_count;
-+
-+ /* The maximum number of slots to be occupied by data messages. */
-+ unsigned short data_quota;
-+
-+ /* An array of bit sets indicating which services must be polled. */
-+ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)];
-+
-+ /* The number of the first unused service */
-+ int unused_service;
-+
-+ /* Signalled when a free slot becomes available. */
-+ struct semaphore slot_available_event;
-+
-+ struct semaphore slot_remove_event;
-+
-+ /* Signalled when a free data slot becomes available. */
-+ struct semaphore data_quota_event;
-+
-+ /* Incremented when there are bulk transfers which cannot be processed
-+ * whilst paused and must be processed on resume */
-+ int deferred_bulks;
-+
-+ struct state_stats_struct {
-+ int slot_stalls;
-+ int data_stalls;
-+ int ctrl_tx_count;
-+ int ctrl_rx_count;
-+ int error_count;
-+ } stats;
-+
-+ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES];
-+ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES];
-+ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS];
-+
-+ VCHIQ_PLATFORM_STATE_T platform_state;
-+};
-+
-+struct bulk_waiter {
-+ VCHIQ_BULK_T *bulk;
-+ struct semaphore event;
-+ int actual;
-+};
-+
-+extern spinlock_t bulk_waiter_spinlock;
-+
-+extern int vchiq_core_log_level;
-+extern int vchiq_core_msg_log_level;
-+extern int vchiq_sync_log_level;
-+
-+extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES];
-+
-+extern const char *
-+get_conn_state_name(VCHIQ_CONNSTATE_T conn_state);
-+
-+extern VCHIQ_SLOT_ZERO_T *
-+vchiq_init_slots(void *mem_base, int mem_size);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero,
-+ int is_master);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance);
-+
-+extern VCHIQ_SERVICE_T *
-+vchiq_add_service_internal(VCHIQ_STATE_T *state,
-+ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate,
-+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd);
-+
-+extern void
-+vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_free_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_pause_internal(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_resume_internal(VCHIQ_STATE_T *state);
-+
-+extern void
-+remote_event_pollall(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle,
-+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir);
-+
-+extern void
-+vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_loud_error_header(void);
-+
-+extern void
-+vchiq_loud_error_footer(void);
-+
-+extern void
-+request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type);
-+
-+static inline VCHIQ_SERVICE_T *
-+handle_to_service(VCHIQ_SERVICE_HANDLE_T handle)
-+{
-+ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) &
-+ (VCHIQ_MAX_STATES - 1)];
-+ if (!state)
-+ return NULL;
-+
-+ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)];
-+}
-+
-+extern VCHIQ_SERVICE_T *
-+find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_SERVICE_T *
-+find_service_by_port(VCHIQ_STATE_T *state, int localport);
-+
-+extern VCHIQ_SERVICE_T *
-+find_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_SERVICE_T *
-+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_SERVICE_HANDLE_T handle);
-+
-+extern VCHIQ_SERVICE_T *
-+next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance,
-+ int *pidx);
-+
-+extern void
-+lock_service(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+unlock_service(VCHIQ_SERVICE_T *service);
-+
-+/* The following functions are called from vchiq_core, and external
-+** implementations must be provided. */
-+
-+extern VCHIQ_STATUS_T
-+vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk,
-+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir);
-+
-+extern void
-+vchiq_transfer_bulk(VCHIQ_BULK_T *bulk);
-+
-+extern void
-+vchiq_complete_bulk(VCHIQ_BULK_T *bulk);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_copy_from_user(void *dst, const void *src, int size);
-+
-+extern void
-+remote_event_signal(REMOTE_EVENT_T *event);
-+
-+void
-+vchiq_platform_check_suspend(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_platform_paused(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_platform_resume(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_platform_resumed(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_dump(void *dump_context, const char *str, int len);
-+
-+extern void
-+vchiq_dump_platform_state(void *dump_context);
-+
-+extern void
-+vchiq_dump_platform_instances(void *dump_context);
-+
-+extern void
-+vchiq_dump_platform_service_state(void *dump_context,
-+ VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_use_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_release_service_internal(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_on_remote_use(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_on_remote_release(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_platform_init_state(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_check_service(VCHIQ_SERVICE_T *service);
-+
-+extern void
-+vchiq_on_remote_use_active(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_send_remote_use(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_send_remote_release(VCHIQ_STATE_T *state);
-+
-+extern VCHIQ_STATUS_T
-+vchiq_send_remote_use_active(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state,
-+ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate);
-+
-+extern void
-+vchiq_platform_handle_timeout(VCHIQ_STATE_T *state);
-+
-+extern void
-+vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate);
-+
-+
-+extern void
-+vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem,
-+ size_t numBytes);
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,383 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+#include <linux/debugfs.h>
-+#include "vchiq_core.h"
-+#include "vchiq_arm.h"
-+#include "vchiq_debugfs.h"
-+
-+#ifdef CONFIG_DEBUG_FS
-+
-+/****************************************************************************
-+*
-+* log category entries
-+*
-+***************************************************************************/
-+#define DEBUGFS_WRITE_BUF_SIZE 256
-+
-+#define VCHIQ_LOG_ERROR_STR "error"
-+#define VCHIQ_LOG_WARNING_STR "warning"
-+#define VCHIQ_LOG_INFO_STR "info"
-+#define VCHIQ_LOG_TRACE_STR "trace"
-+
-+
-+/* Top-level debug info */
-+struct vchiq_debugfs_info {
-+ /* Global 'vchiq' debugfs entry used by all instances */
-+ struct dentry *vchiq_cfg_dir;
-+
-+ /* one entry per client process */
-+ struct dentry *clients;
-+
-+ /* log categories */
-+ struct dentry *log_categories;
-+};
-+
-+static struct vchiq_debugfs_info debugfs_info;
-+
-+/* Log category debugfs entries */
-+struct vchiq_debugfs_log_entry {
-+ const char *name;
-+ int *plevel;
-+ struct dentry *dir;
-+};
-+
-+static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = {
-+ { "core", &vchiq_core_log_level },
-+ { "msg", &vchiq_core_msg_log_level },
-+ { "sync", &vchiq_sync_log_level },
-+ { "susp", &vchiq_susp_log_level },
-+ { "arm", &vchiq_arm_log_level },
-+};
-+static int n_log_entries =
-+ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]);
-+
-+
-+static struct dentry *vchiq_clients_top(void);
-+static struct dentry *vchiq_debugfs_top(void);
-+
-+static int debugfs_log_show(struct seq_file *f, void *offset)
-+{
-+ int *levp = f->private;
-+ char *log_value = NULL;
-+
-+ switch (*levp) {
-+ case VCHIQ_LOG_ERROR:
-+ log_value = VCHIQ_LOG_ERROR_STR;
-+ break;
-+ case VCHIQ_LOG_WARNING:
-+ log_value = VCHIQ_LOG_WARNING_STR;
-+ break;
-+ case VCHIQ_LOG_INFO:
-+ log_value = VCHIQ_LOG_INFO_STR;
-+ break;
-+ case VCHIQ_LOG_TRACE:
-+ log_value = VCHIQ_LOG_TRACE_STR;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ seq_printf(f, "%s\n", log_value ? log_value : "(null)");
-+
-+ return 0;
-+}
-+
-+static int debugfs_log_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, debugfs_log_show, inode->i_private);
-+}
-+
-+static int debugfs_log_write(struct file *file,
-+ const char __user *buffer,
-+ size_t count, loff_t *ppos)
-+{
-+ struct seq_file *f = (struct seq_file *)file->private_data;
-+ int *levp = f->private;
-+ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1];
-+
-+ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1);
-+ if (count >= DEBUGFS_WRITE_BUF_SIZE)
-+ count = DEBUGFS_WRITE_BUF_SIZE;
-+
-+ if (copy_from_user(kbuf, buffer, count) != 0)
-+ return -EFAULT;
-+ kbuf[count - 1] = 0;
-+
-+ if (strncmp("error", kbuf, strlen("error")) == 0)
-+ *levp = VCHIQ_LOG_ERROR;
-+ else if (strncmp("warning", kbuf, strlen("warning")) == 0)
-+ *levp = VCHIQ_LOG_WARNING;
-+ else if (strncmp("info", kbuf, strlen("info")) == 0)
-+ *levp = VCHIQ_LOG_INFO;
-+ else if (strncmp("trace", kbuf, strlen("trace")) == 0)
-+ *levp = VCHIQ_LOG_TRACE;
-+ else
-+ *levp = VCHIQ_LOG_DEFAULT;
-+
-+ *ppos += count;
-+
-+ return count;
-+}
-+
-+static const struct file_operations debugfs_log_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debugfs_log_open,
-+ .write = debugfs_log_write,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+/* create an entry under <debugfs>/vchiq/log for each log category */
-+static int vchiq_debugfs_create_log_entries(struct dentry *top)
-+{
-+ struct dentry *dir;
-+ size_t i;
-+ int ret = 0;
-+ dir = debugfs_create_dir("log", vchiq_debugfs_top());
-+ if (!dir)
-+ return -ENOMEM;
-+ debugfs_info.log_categories = dir;
-+
-+ for (i = 0; i < n_log_entries; i++) {
-+ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel;
-+ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name,
-+ 0644,
-+ debugfs_info.log_categories,
-+ levp,
-+ &debugfs_log_fops);
-+ if (!dir) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+
-+ vchiq_debugfs_log_entries[i].dir = dir;
-+ }
-+ return ret;
-+}
-+
-+static int debugfs_usecount_show(struct seq_file *f, void *offset)
-+{
-+ VCHIQ_INSTANCE_T instance = f->private;
-+ int use_count;
-+
-+ use_count = vchiq_instance_get_use_count(instance);
-+ seq_printf(f, "%d\n", use_count);
-+
-+ return 0;
-+}
-+
-+static int debugfs_usecount_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, debugfs_usecount_show, inode->i_private);
-+}
-+
-+static const struct file_operations debugfs_usecount_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debugfs_usecount_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+static int debugfs_trace_show(struct seq_file *f, void *offset)
-+{
-+ VCHIQ_INSTANCE_T instance = f->private;
-+ int trace;
-+
-+ trace = vchiq_instance_get_trace(instance);
-+ seq_printf(f, "%s\n", trace ? "Y" : "N");
-+
-+ return 0;
-+}
-+
-+static int debugfs_trace_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, debugfs_trace_show, inode->i_private);
-+}
-+
-+static int debugfs_trace_write(struct file *file,
-+ const char __user *buffer,
-+ size_t count, loff_t *ppos)
-+{
-+ struct seq_file *f = (struct seq_file *)file->private_data;
-+ VCHIQ_INSTANCE_T instance = f->private;
-+ char firstchar;
-+
-+ if (copy_from_user(&firstchar, buffer, 1) != 0)
-+ return -EFAULT;
-+
-+ switch (firstchar) {
-+ case 'Y':
-+ case 'y':
-+ case '1':
-+ vchiq_instance_set_trace(instance, 1);
-+ break;
-+ case 'N':
-+ case 'n':
-+ case '0':
-+ vchiq_instance_set_trace(instance, 0);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ *ppos += count;
-+
-+ return count;
-+}
-+
-+static const struct file_operations debugfs_trace_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debugfs_trace_open,
-+ .write = debugfs_trace_write,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+/* add an instance (process) to the debugfs entries */
-+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
-+{
-+ char pidstr[16];
-+ struct dentry *top, *use_count, *trace;
-+ struct dentry *clients = vchiq_clients_top();
-+
-+ snprintf(pidstr, sizeof(pidstr), "%d",
-+ vchiq_instance_get_pid(instance));
-+
-+ top = debugfs_create_dir(pidstr, clients);
-+ if (!top)
-+ goto fail_top;
-+
-+ use_count = debugfs_create_file("use_count",
-+ 0444, top,
-+ instance,
-+ &debugfs_usecount_fops);
-+ if (!use_count)
-+ goto fail_use_count;
-+
-+ trace = debugfs_create_file("trace",
-+ 0644, top,
-+ instance,
-+ &debugfs_trace_fops);
-+ if (!trace)
-+ goto fail_trace;
-+
-+ vchiq_instance_get_debugfs_node(instance)->dentry = top;
-+
-+ return 0;
-+
-+fail_trace:
-+ debugfs_remove(use_count);
-+fail_use_count:
-+ debugfs_remove(top);
-+fail_top:
-+ return -ENOMEM;
-+}
-+
-+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance);
-+ debugfs_remove_recursive(node->dentry);
-+}
-+
-+
-+int vchiq_debugfs_init(void)
-+{
-+ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL);
-+
-+ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL);
-+ if (debugfs_info.vchiq_cfg_dir == NULL)
-+ goto fail;
-+
-+ debugfs_info.clients = debugfs_create_dir("clients",
-+ vchiq_debugfs_top());
-+ if (!debugfs_info.clients)
-+ goto fail;
-+
-+ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0)
-+ goto fail;
-+
-+ return 0;
-+
-+fail:
-+ vchiq_debugfs_deinit();
-+ vchiq_log_error(vchiq_arm_log_level,
-+ "%s: failed to create debugfs directory",
-+ __func__);
-+
-+ return -ENOMEM;
-+}
-+
-+/* remove all the debugfs entries */
-+void vchiq_debugfs_deinit(void)
-+{
-+ debugfs_remove_recursive(vchiq_debugfs_top());
-+}
-+
-+static struct dentry *vchiq_clients_top(void)
-+{
-+ return debugfs_info.clients;
-+}
-+
-+static struct dentry *vchiq_debugfs_top(void)
-+{
-+ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL);
-+ return debugfs_info.vchiq_cfg_dir;
-+}
-+
-+#else /* CONFIG_DEBUG_FS */
-+
-+int vchiq_debugfs_init(void)
-+{
-+ return 0;
-+}
-+
-+void vchiq_debugfs_deinit(void)
-+{
-+}
-+
-+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
-+{
-+ return 0;
-+}
-+
-+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
-+{
-+}
-+
-+#endif /* CONFIG_DEBUG_FS */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,52 @@
-+/**
-+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_DEBUGFS_H
-+#define VCHIQ_DEBUGFS_H
-+
-+#include "vchiq_core.h"
-+
-+typedef struct vchiq_debugfs_node_struct
-+{
-+ struct dentry *dentry;
-+} VCHIQ_DEBUGFS_NODE_T;
-+
-+int vchiq_debugfs_init(void);
-+
-+void vchiq_debugfs_deinit(void);
-+
-+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance);
-+
-+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance);
-+
-+#endif /* VCHIQ_DEBUGFS_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,87 @@
-+#!/usr/bin/perl -w
-+
-+use strict;
-+
-+#
-+# Generate a version from available information
-+#
-+
-+my $prefix = shift @ARGV;
-+my $root = shift @ARGV;
-+
-+
-+if ( not defined $root ) {
-+ die "usage: $0 prefix root-dir\n";
-+}
-+
-+if ( ! -d $root ) {
-+ die "root directory $root not found\n";
-+}
-+
-+my $version = "unknown";
-+my $tainted = "";
-+
-+if ( -d "$root/.git" ) {
-+ # attempt to work out git version. only do so
-+ # on a linux build host, as cygwin builds are
-+ # already slow enough
-+
-+ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) {
-+ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) {
-+ $version = "no git version";
-+ }
-+ else {
-+ $version = <F>;
-+ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
-+ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
-+ }
-+
-+ if (open(G, "git --git-dir $root/.git status --porcelain|")) {
-+ $tainted = <G>;
-+ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
-+ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
-+ if (length $tainted) {
-+ $version = join ' ', $version, "(tainted)";
-+ }
-+ else {
-+ $version = join ' ', $version, "(clean)";
-+ }
-+ }
-+ }
-+}
-+
-+my $hostname = `hostname`;
-+$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin).
-+$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin).
-+
-+
-+print STDERR "Version $version\n";
-+print <<EOF;
-+#include "${prefix}_build_info.h"
-+#include <linux/broadcom/vc_debug_sym.h>
-+
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" );
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" );
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ );
-+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ );
-+
-+const char *vchiq_get_build_hostname( void )
-+{
-+ return vchiq_build_hostname;
-+}
-+
-+const char *vchiq_get_build_version( void )
-+{
-+ return vchiq_build_version;
-+}
-+
-+const char *vchiq_get_build_date( void )
-+{
-+ return vchiq_build_date;
-+}
-+
-+const char *vchiq_get_build_time( void )
-+{
-+ return vchiq_build_time;
-+}
-+EOF
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,40 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_VCHIQ_H
-+#define VCHIQ_VCHIQ_H
-+
-+#include "vchiq_if.h"
-+#include "vchiq_util.h"
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,189 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_IF_H
-+#define VCHIQ_IF_H
-+
-+#include "interface/vchi/vchi_mh.h"
-+
-+#define VCHIQ_SERVICE_HANDLE_INVALID 0
-+
-+#define VCHIQ_SLOT_SIZE 4096
-+#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T))
-+#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */
-+
-+#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \
-+ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3))
-+#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service)
-+#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service)
-+
-+typedef enum {
-+ VCHIQ_SERVICE_OPENED, /* service, -, - */
-+ VCHIQ_SERVICE_CLOSED, /* service, -, - */
-+ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */
-+ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */
-+ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */
-+ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */
-+ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */
-+} VCHIQ_REASON_T;
-+
-+typedef enum {
-+ VCHIQ_ERROR = -1,
-+ VCHIQ_SUCCESS = 0,
-+ VCHIQ_RETRY = 1
-+} VCHIQ_STATUS_T;
-+
-+typedef enum {
-+ VCHIQ_BULK_MODE_CALLBACK,
-+ VCHIQ_BULK_MODE_BLOCKING,
-+ VCHIQ_BULK_MODE_NOCALLBACK,
-+ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */
-+} VCHIQ_BULK_MODE_T;
-+
-+typedef enum {
-+ VCHIQ_SERVICE_OPTION_AUTOCLOSE,
-+ VCHIQ_SERVICE_OPTION_SLOT_QUOTA,
-+ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA,
-+ VCHIQ_SERVICE_OPTION_SYNCHRONOUS,
-+ VCHIQ_SERVICE_OPTION_TRACE
-+} VCHIQ_SERVICE_OPTION_T;
-+
-+typedef struct vchiq_header_struct {
-+ /* The message identifier - opaque to applications. */
-+ int msgid;
-+
-+ /* Size of message data. */
-+ unsigned int size;
-+
-+ char data[0]; /* message */
-+} VCHIQ_HEADER_T;
-+
-+typedef struct {
-+ const void *data;
-+ unsigned int size;
-+} VCHIQ_ELEMENT_T;
-+
-+typedef unsigned int VCHIQ_SERVICE_HANDLE_T;
-+
-+typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *,
-+ VCHIQ_SERVICE_HANDLE_T, void *);
-+
-+typedef struct vchiq_service_base_struct {
-+ int fourcc;
-+ VCHIQ_CALLBACK_T callback;
-+ void *userdata;
-+} VCHIQ_SERVICE_BASE_T;
-+
-+typedef struct vchiq_service_params_struct {
-+ int fourcc;
-+ VCHIQ_CALLBACK_T callback;
-+ void *userdata;
-+ short version; /* Increment for non-trivial changes */
-+ short version_min; /* Update for incompatible changes */
-+} VCHIQ_SERVICE_PARAMS_T;
-+
-+typedef struct vchiq_config_struct {
-+ unsigned int max_msg_size;
-+ unsigned int bulk_threshold; /* The message size above which it
-+ is better to use a bulk transfer
-+ (<= max_msg_size) */
-+ unsigned int max_outstanding_bulks;
-+ unsigned int max_services;
-+ short version; /* The version of VCHIQ */
-+ short version_min; /* The minimum compatible version of VCHIQ */
-+} VCHIQ_CONFIG_T;
-+
-+typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T;
-+typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg);
-+
-+extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance);
-+extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance);
-+extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance);
-+extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *pservice);
-+extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *pservice);
-+extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_use_service_no_resume(
-+ VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service);
-+
-+extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service,
-+ const VCHIQ_ELEMENT_T *elements, unsigned int count);
-+extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHIQ_HEADER_T *header);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
-+ const void *data, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service,
-+ void *data, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle(
-+ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle,
-+ const void *offset, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle(
-+ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle,
-+ void *offset, unsigned int size, void *userdata);
-+extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service,
-+ const void *data, unsigned int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode);
-+extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service,
-+ void *data, unsigned int size, void *userdata,
-+ VCHIQ_BULK_MODE_T mode);
-+extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHI_MEM_HANDLE_T handle, const void *offset, unsigned int size,
-+ void *userdata, VCHIQ_BULK_MODE_T mode);
-+extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHI_MEM_HANDLE_T handle, void *offset, unsigned int size,
-+ void *userdata, VCHIQ_BULK_MODE_T mode);
-+extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service);
-+extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service);
-+extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service);
-+extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance,
-+ int config_size, VCHIQ_CONFIG_T *pconfig);
-+extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service,
-+ VCHIQ_SERVICE_OPTION_T option, int value);
-+
-+extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance,
-+ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg);
-+extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance);
-+
-+extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service,
-+ void *ptr, size_t num_bytes);
-+
-+extern VCHIQ_STATUS_T vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle,
-+ short *peer_version);
-+
-+#endif /* VCHIQ_IF_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,131 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_IOCTLS_H
-+#define VCHIQ_IOCTLS_H
-+
-+#include <linux/ioctl.h>
-+#include "vchiq_if.h"
-+
-+#define VCHIQ_IOC_MAGIC 0xc4
-+#define VCHIQ_INVALID_HANDLE (~0)
-+
-+typedef struct {
-+ VCHIQ_SERVICE_PARAMS_T params;
-+ int is_open;
-+ int is_vchi;
-+ unsigned int handle; /* OUT */
-+} VCHIQ_CREATE_SERVICE_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ unsigned int count;
-+ const VCHIQ_ELEMENT_T *elements;
-+} VCHIQ_QUEUE_MESSAGE_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ void *data;
-+ unsigned int size;
-+ void *userdata;
-+ VCHIQ_BULK_MODE_T mode;
-+} VCHIQ_QUEUE_BULK_TRANSFER_T;
-+
-+typedef struct {
-+ VCHIQ_REASON_T reason;
-+ VCHIQ_HEADER_T *header;
-+ void *service_userdata;
-+ void *bulk_userdata;
-+} VCHIQ_COMPLETION_DATA_T;
-+
-+typedef struct {
-+ unsigned int count;
-+ VCHIQ_COMPLETION_DATA_T *buf;
-+ unsigned int msgbufsize;
-+ unsigned int msgbufcount; /* IN/OUT */
-+ void **msgbufs;
-+} VCHIQ_AWAIT_COMPLETION_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ int blocking;
-+ unsigned int bufsize;
-+ void *buf;
-+} VCHIQ_DEQUEUE_MESSAGE_T;
-+
-+typedef struct {
-+ unsigned int config_size;
-+ VCHIQ_CONFIG_T *pconfig;
-+} VCHIQ_GET_CONFIG_T;
-+
-+typedef struct {
-+ unsigned int handle;
-+ VCHIQ_SERVICE_OPTION_T option;
-+ int value;
-+} VCHIQ_SET_SERVICE_OPTION_T;
-+
-+typedef struct {
-+ void *virt_addr;
-+ size_t num_bytes;
-+} VCHIQ_DUMP_MEM_T;
-+
-+#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0)
-+#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1)
-+#define VCHIQ_IOC_CREATE_SERVICE \
-+ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T)
-+#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3)
-+#define VCHIQ_IOC_QUEUE_MESSAGE \
-+ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T)
-+#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \
-+ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T)
-+#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \
-+ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T)
-+#define VCHIQ_IOC_AWAIT_COMPLETION \
-+ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T)
-+#define VCHIQ_IOC_DEQUEUE_MESSAGE \
-+ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T)
-+#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9)
-+#define VCHIQ_IOC_GET_CONFIG \
-+ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T)
-+#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11)
-+#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12)
-+#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13)
-+#define VCHIQ_IOC_SET_SERVICE_OPTION \
-+ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T)
-+#define VCHIQ_IOC_DUMP_PHYS_MEM \
-+ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T)
-+#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16)
-+#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17)
-+#define VCHIQ_IOC_MAX 17
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,458 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+/* ---- Include Files ---------------------------------------------------- */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+
-+#include "vchiq_core.h"
-+#include "vchiq_arm.h"
-+#include "vchiq_killable.h"
-+
-+/* ---- Public Variables ------------------------------------------------- */
-+
-+/* ---- Private Constants and Types -------------------------------------- */
-+
-+struct bulk_waiter_node {
-+ struct bulk_waiter bulk_waiter;
-+ int pid;
-+ struct list_head list;
-+};
-+
-+struct vchiq_instance_struct {
-+ VCHIQ_STATE_T *state;
-+
-+ int connected;
-+
-+ struct list_head bulk_waiter_list;
-+ struct mutex bulk_waiter_list_mutex;
-+};
-+
-+static VCHIQ_STATUS_T
-+vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, VCHIQ_BULK_DIR_T dir);
-+
-+/****************************************************************************
-+*
-+* vchiq_initialise
-+*
-+***************************************************************************/
-+#define VCHIQ_INIT_RETRIES 10
-+VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_STATE_T *state;
-+ VCHIQ_INSTANCE_T instance = NULL;
-+ int i;
-+
-+ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__);
-+
-+ /* VideoCore may not be ready due to boot up timing.
-+ It may never be ready if kernel and firmware are mismatched, so don't block forever. */
-+ for (i=0; i<VCHIQ_INIT_RETRIES; i++) {
-+ state = vchiq_get_state();
-+ if (state)
-+ break;
-+ udelay(500);
-+ }
-+ if (i==VCHIQ_INIT_RETRIES) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%s: videocore not initialized\n", __func__);
-+ goto failed;
-+ } else if (i>0) {
-+ vchiq_log_warning(vchiq_core_log_level,
-+ "%s: videocore initialized after %d retries\n", __func__, i);
-+ }
-+
-+ instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+ if (!instance) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%s: error allocating vchiq instance\n", __func__);
-+ goto failed;
-+ }
-+
-+ instance->connected = 0;
-+ instance->state = state;
-+ mutex_init(&instance->bulk_waiter_list_mutex);
-+ INIT_LIST_HEAD(&instance->bulk_waiter_list);
-+
-+ *instanceOut = instance;
-+
-+ status = VCHIQ_SUCCESS;
-+
-+failed:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_initialise);
-+
-+/****************************************************************************
-+*
-+* vchiq_shutdown
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_STATE_T *state = instance->state;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ if (mutex_lock_interruptible(&state->mutex) != 0)
-+ return VCHIQ_RETRY;
-+
-+ /* Remove all services */
-+ status = vchiq_shutdown_internal(state, instance);
-+
-+ mutex_unlock(&state->mutex);
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ if (status == VCHIQ_SUCCESS) {
-+ struct list_head *pos, *next;
-+ list_for_each_safe(pos, next,
-+ &instance->bulk_waiter_list) {
-+ struct bulk_waiter_node *waiter;
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "bulk_waiter - cleaned up %x "
-+ "for pid %d",
-+ (unsigned int)waiter, waiter->pid);
-+ kfree(waiter);
-+ }
-+ kfree(instance);
-+ }
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_shutdown);
-+
-+/****************************************************************************
-+*
-+* vchiq_is_connected
-+*
-+***************************************************************************/
-+
-+int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
-+{
-+ return instance->connected;
-+}
-+
-+/****************************************************************************
-+*
-+* vchiq_connect
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
-+{
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_STATE_T *state = instance->state;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ if (mutex_lock_interruptible(&state->mutex) != 0) {
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s: call to mutex_lock failed", __func__);
-+ status = VCHIQ_RETRY;
-+ goto failed;
-+ }
-+ status = vchiq_connect_internal(state, instance);
-+
-+ if (status == VCHIQ_SUCCESS)
-+ instance->connected = 1;
-+
-+ mutex_unlock(&state->mutex);
-+
-+failed:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_connect);
-+
-+/****************************************************************************
-+*
-+* vchiq_add_service
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_add_service(
-+ VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *phandle)
-+{
-+ VCHIQ_STATUS_T status;
-+ VCHIQ_STATE_T *state = instance->state;
-+ VCHIQ_SERVICE_T *service = NULL;
-+ int srvstate;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
-+
-+ srvstate = vchiq_is_connected(instance)
-+ ? VCHIQ_SRVSTATE_LISTENING
-+ : VCHIQ_SRVSTATE_HIDDEN;
-+
-+ service = vchiq_add_service_internal(
-+ state,
-+ params,
-+ srvstate,
-+ instance,
-+ NULL);
-+
-+ if (service) {
-+ *phandle = service->handle;
-+ status = VCHIQ_SUCCESS;
-+ } else
-+ status = VCHIQ_ERROR;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_add_service);
-+
-+/****************************************************************************
-+*
-+* vchiq_open_service
-+*
-+***************************************************************************/
-+
-+VCHIQ_STATUS_T vchiq_open_service(
-+ VCHIQ_INSTANCE_T instance,
-+ const VCHIQ_SERVICE_PARAMS_T *params,
-+ VCHIQ_SERVICE_HANDLE_T *phandle)
-+{
-+ VCHIQ_STATUS_T status = VCHIQ_ERROR;
-+ VCHIQ_STATE_T *state = instance->state;
-+ VCHIQ_SERVICE_T *service = NULL;
-+
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p) called", __func__, instance);
-+
-+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
-+
-+ if (!vchiq_is_connected(instance))
-+ goto failed;
-+
-+ service = vchiq_add_service_internal(state,
-+ params,
-+ VCHIQ_SRVSTATE_OPENING,
-+ instance,
-+ NULL);
-+
-+ if (service) {
-+ *phandle = service->handle;
-+ status = vchiq_open_service_internal(service, current->pid);
-+ if (status != VCHIQ_SUCCESS) {
-+ vchiq_remove_service(service->handle);
-+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID;
-+ }
-+ }
-+
-+failed:
-+ vchiq_log_trace(vchiq_core_log_level,
-+ "%s(%p): returning %d", __func__, instance, status);
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_open_service);
-+
-+VCHIQ_STATUS_T
-+vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle,
-+ const void *data, unsigned int size, void *userdata)
-+{
-+ return vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata,
-+ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT);
-+}
-+EXPORT_SYMBOL(vchiq_queue_bulk_transmit);
-+
-+VCHIQ_STATUS_T
-+vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, void *userdata)
-+{
-+ return vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, data, size, userdata,
-+ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE);
-+}
-+EXPORT_SYMBOL(vchiq_queue_bulk_receive);
-+
-+VCHIQ_STATUS_T
-+vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data,
-+ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode)
-+{
-+ VCHIQ_STATUS_T status;
-+
-+ switch (mode) {
-+ case VCHIQ_BULK_MODE_NOCALLBACK:
-+ case VCHIQ_BULK_MODE_CALLBACK:
-+ status = vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata,
-+ mode, VCHIQ_BULK_TRANSMIT);
-+ break;
-+ case VCHIQ_BULK_MODE_BLOCKING:
-+ status = vchiq_blocking_bulk_transfer(handle,
-+ (void *)data, size, VCHIQ_BULK_TRANSMIT);
-+ break;
-+ default:
-+ return VCHIQ_ERROR;
-+ }
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_bulk_transmit);
-+
-+VCHIQ_STATUS_T
-+vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode)
-+{
-+ VCHIQ_STATUS_T status;
-+
-+ switch (mode) {
-+ case VCHIQ_BULK_MODE_NOCALLBACK:
-+ case VCHIQ_BULK_MODE_CALLBACK:
-+ status = vchiq_bulk_transfer(handle,
-+ VCHI_MEM_HANDLE_INVALID, data, size, userdata,
-+ mode, VCHIQ_BULK_RECEIVE);
-+ break;
-+ case VCHIQ_BULK_MODE_BLOCKING:
-+ status = vchiq_blocking_bulk_transfer(handle,
-+ (void *)data, size, VCHIQ_BULK_RECEIVE);
-+ break;
-+ default:
-+ return VCHIQ_ERROR;
-+ }
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(vchiq_bulk_receive);
-+
-+static VCHIQ_STATUS_T
-+vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
-+ unsigned int size, VCHIQ_BULK_DIR_T dir)
-+{
-+ VCHIQ_INSTANCE_T instance;
-+ VCHIQ_SERVICE_T *service;
-+ VCHIQ_STATUS_T status;
-+ struct bulk_waiter_node *waiter = NULL;
-+ struct list_head *pos;
-+
-+ service = find_service_by_handle(handle);
-+ if (!service)
-+ return VCHIQ_ERROR;
-+
-+ instance = service->instance;
-+
-+ unlock_service(service);
-+
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_for_each(pos, &instance->bulk_waiter_list) {
-+ if (list_entry(pos, struct bulk_waiter_node,
-+ list)->pid == current->pid) {
-+ waiter = list_entry(pos,
-+ struct bulk_waiter_node,
-+ list);
-+ list_del(pos);
-+ break;
-+ }
-+ }
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+
-+ if (waiter) {
-+ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk;
-+ if (bulk) {
-+ /* This thread has an outstanding bulk transfer. */
-+ if ((bulk->data != data) ||
-+ (bulk->size != size)) {
-+ /* This is not a retry of the previous one.
-+ ** Cancel the signal when the transfer
-+ ** completes. */
-+ spin_lock(&bulk_waiter_spinlock);
-+ bulk->userdata = NULL;
-+ spin_unlock(&bulk_waiter_spinlock);
-+ }
-+ }
-+ }
-+
-+ if (!waiter) {
-+ waiter = kzalloc(sizeof(struct bulk_waiter_node), GFP_KERNEL);
-+ if (!waiter) {
-+ vchiq_log_error(vchiq_core_log_level,
-+ "%s - out of memory", __func__);
-+ return VCHIQ_ERROR;
-+ }
-+ }
-+
-+ status = vchiq_bulk_transfer(handle, VCHI_MEM_HANDLE_INVALID,
-+ data, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING,
-+ dir);
-+ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) ||
-+ !waiter->bulk_waiter.bulk) {
-+ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk;
-+ if (bulk) {
-+ /* Cancel the signal when the transfer
-+ ** completes. */
-+ spin_lock(&bulk_waiter_spinlock);
-+ bulk->userdata = NULL;
-+ spin_unlock(&bulk_waiter_spinlock);
-+ }
-+ kfree(waiter);
-+ } else {
-+ waiter->pid = current->pid;
-+ mutex_lock(&instance->bulk_waiter_list_mutex);
-+ list_add(&waiter->list, &instance->bulk_waiter_list);
-+ mutex_unlock(&instance->bulk_waiter_list_mutex);
-+ vchiq_log_info(vchiq_arm_log_level,
-+ "saved bulk_waiter %x for pid %d",
-+ (unsigned int)waiter, current->pid);
-+ }
-+
-+ return status;
-+}
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,69 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_KILLABLE_H
-+#define VCHIQ_KILLABLE_H
-+
-+#include <linux/mutex.h>
-+#include <linux/semaphore.h>
-+
-+#define SHUTDOWN_SIGS (sigmask(SIGKILL) | sigmask(SIGINT) | sigmask(SIGQUIT) | sigmask(SIGTRAP) | sigmask(SIGSTOP) | sigmask(SIGCONT))
-+
-+static inline int __must_check down_interruptible_killable(struct semaphore *sem)
-+{
-+ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */
-+ int ret;
-+ sigset_t blocked, oldset;
-+ siginitsetinv(&blocked, SHUTDOWN_SIGS);
-+ sigprocmask(SIG_SETMASK, &blocked, &oldset);
-+ ret = down_interruptible(sem);
-+ sigprocmask(SIG_SETMASK, &oldset, NULL);
-+ return ret;
-+}
-+#define down_interruptible down_interruptible_killable
-+
-+
-+static inline int __must_check mutex_lock_interruptible_killable(struct mutex *lock)
-+{
-+ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */
-+ int ret;
-+ sigset_t blocked, oldset;
-+ siginitsetinv(&blocked, SHUTDOWN_SIGS);
-+ sigprocmask(SIG_SETMASK, &blocked, &oldset);
-+ ret = mutex_lock_interruptible(lock);
-+ sigprocmask(SIG_SETMASK, &oldset, NULL);
-+ return ret;
-+}
-+#define mutex_lock_interruptible mutex_lock_interruptible_killable
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,71 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_MEMDRV_H
-+#define VCHIQ_MEMDRV_H
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+#include <linux/kernel.h>
-+#include "vchiq_if.h"
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+typedef struct {
-+ void *armSharedMemVirt;
-+ dma_addr_t armSharedMemPhys;
-+ size_t armSharedMemSize;
-+
-+ void *vcSharedMemVirt;
-+ dma_addr_t vcSharedMemPhys;
-+ size_t vcSharedMemSize;
-+} VCHIQ_SHARED_MEM_INFO_T;
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info);
-+
-+VCHIQ_STATUS_T vchiq_memdrv_initialise(void);
-+
-+VCHIQ_STATUS_T vchiq_userdrv_create_instance(
-+ const VCHIQ_PLATFORM_DATA_T * platform_data);
-+
-+VCHIQ_STATUS_T vchiq_userdrv_suspend(
-+ const VCHIQ_PLATFORM_DATA_T * platform_data);
-+
-+VCHIQ_STATUS_T vchiq_userdrv_resume(
-+ const VCHIQ_PLATFORM_DATA_T * platform_data);
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,58 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_PAGELIST_H
-+#define VCHIQ_PAGELIST_H
-+
-+#ifndef PAGE_SIZE
-+#define PAGE_SIZE 4096
-+#endif
-+#define CACHE_LINE_SIZE 32
-+#define PAGELIST_WRITE 0
-+#define PAGELIST_READ 1
-+#define PAGELIST_READ_WITH_FRAGMENTS 2
-+
-+typedef struct pagelist_struct {
-+ unsigned long length;
-+ unsigned short type;
-+ unsigned short offset;
-+ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following
-+ pages at consecutive addresses. */
-+} PAGELIST_T;
-+
-+typedef struct fragments_struct {
-+ char headbuf[CACHE_LINE_SIZE];
-+ char tailbuf[CACHE_LINE_SIZE];
-+} FRAGMENTS_T;
-+
-+#endif /* VCHIQ_PAGELIST_H */
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,860 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include <linux/module.h>
-+#include <linux/types.h>
-+
-+#include "interface/vchi/vchi.h"
-+#include "vchiq.h"
-+#include "vchiq_core.h"
-+
-+#include "vchiq_util.h"
-+
-+#include <stddef.h>
-+
-+#define vchiq_status_to_vchi(status) ((int32_t)status)
-+
-+typedef struct {
-+ VCHIQ_SERVICE_HANDLE_T handle;
-+
-+ VCHIU_QUEUE_T queue;
-+
-+ VCHI_CALLBACK_T callback;
-+ void *callback_param;
-+} SHIM_SERVICE_T;
-+
-+/* ----------------------------------------------------------------------
-+ * return pointer to the mphi message driver function table
-+ * -------------------------------------------------------------------- */
-+const VCHI_MESSAGE_DRIVER_T *
-+vchi_mphi_message_driver_func_table(void)
-+{
-+ return NULL;
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * return a pointer to the 'single' connection driver fops
-+ * -------------------------------------------------------------------- */
-+const VCHI_CONNECTION_API_T *
-+single_get_func_table(void)
-+{
-+ return NULL;
-+}
-+
-+VCHI_CONNECTION_T *vchi_create_connection(
-+ const VCHI_CONNECTION_API_T *function_table,
-+ const VCHI_MESSAGE_DRIVER_T *low_level)
-+{
-+ (void)function_table;
-+ (void)low_level;
-+ return NULL;
-+}
-+
-+/***********************************************************
-+ * Name: vchi_msg_peek
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle,
-+ * void **data,
-+ * uint32_t *msg_size,
-+
-+
-+ * VCHI_FLAGS_T flags
-+ *
-+ * Description: Routine to return a pointer to the current message (to allow in
-+ * place processing). The message can be removed using
-+ * vchi_msg_remove when you're finished
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ WARN_ON((flags != VCHI_FLAGS_NONE) &&
-+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
-+
-+ if (flags == VCHI_FLAGS_NONE)
-+ if (vchiu_queue_is_empty(&service->queue))
-+ return -1;
-+
-+ header = vchiu_queue_peek(&service->queue);
-+
-+ *data = header->data;
-+ *msg_size = header->size;
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_peek);
-+
-+/***********************************************************
-+ * Name: vchi_msg_remove
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle,
-+ *
-+ * Description: Routine to remove a message (after it has been read with
-+ * vchi_msg_peek)
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ header = vchiu_queue_pop(&service->queue);
-+
-+ vchiq_release_message(service->handle, header);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_remove);
-+
-+/***********************************************************
-+ * Name: vchi_msg_queue
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * const void *data,
-+ * uint32_t data_size,
-+ * VCHI_FLAGS_T flags,
-+ * void *msg_handle,
-+ *
-+ * Description: Thin wrapper to queue a message onto a connection
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
-+ const void *data,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_ELEMENT_T element = {data, data_size};
-+ VCHIQ_STATUS_T status;
-+
-+ (void)msg_handle;
-+
-+ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
-+
-+ status = vchiq_queue_message(service->handle, &element, 1);
-+
-+ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to
-+ ** implement a retry mechanism since this function is supposed
-+ ** to block until queued
-+ */
-+ while (status == VCHIQ_RETRY) {
-+ msleep(1);
-+ status = vchiq_queue_message(service->handle, &element, 1);
-+ }
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_msg_queue);
-+
-+/***********************************************************
-+ * Name: vchi_bulk_queue_receive
-+ *
-+ * Arguments: VCHI_BULK_HANDLE_T handle,
-+ * void *data_dst,
-+ * const uint32_t data_size,
-+ * VCHI_FLAGS_T flags
-+ * void *bulk_handle
-+ *
-+ * Description: Routine to setup a rcv buffer
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle,
-+ void *data_dst,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_BULK_MODE_T mode;
-+ VCHIQ_STATUS_T status;
-+
-+ switch ((int)flags) {
-+ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
-+ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ WARN_ON(!service->callback);
-+ mode = VCHIQ_BULK_MODE_CALLBACK;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE:
-+ mode = VCHIQ_BULK_MODE_BLOCKING;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ case VCHI_FLAGS_NONE:
-+ mode = VCHIQ_BULK_MODE_NOCALLBACK;
-+ break;
-+ default:
-+ WARN(1, "unsupported message\n");
-+ return vchiq_status_to_vchi(VCHIQ_ERROR);
-+ }
-+
-+ status = vchiq_bulk_receive(service->handle, data_dst, data_size,
-+ bulk_handle, mode);
-+
-+ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to
-+ ** implement a retry mechanism since this function is supposed
-+ ** to block until queued
-+ */
-+ while (status == VCHIQ_RETRY) {
-+ msleep(1);
-+ status = vchiq_bulk_receive(service->handle, data_dst,
-+ data_size, bulk_handle, mode);
-+ }
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_bulk_queue_receive);
-+
-+/***********************************************************
-+ * Name: vchi_bulk_queue_transmit
-+ *
-+ * Arguments: VCHI_BULK_HANDLE_T handle,
-+ * const void *data_src,
-+ * uint32_t data_size,
-+ * VCHI_FLAGS_T flags,
-+ * void *bulk_handle
-+ *
-+ * Description: Routine to transmit some data
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle,
-+ const void *data_src,
-+ uint32_t data_size,
-+ VCHI_FLAGS_T flags,
-+ void *bulk_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_BULK_MODE_T mode;
-+ VCHIQ_STATUS_T status;
-+
-+ switch ((int)flags) {
-+ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
-+ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ WARN_ON(!service->callback);
-+ mode = VCHIQ_BULK_MODE_CALLBACK;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ:
-+ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE:
-+ mode = VCHIQ_BULK_MODE_BLOCKING;
-+ break;
-+ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED:
-+ case VCHI_FLAGS_NONE:
-+ mode = VCHIQ_BULK_MODE_NOCALLBACK;
-+ break;
-+ default:
-+ WARN(1, "unsupported message\n");
-+ return vchiq_status_to_vchi(VCHIQ_ERROR);
-+ }
-+
-+ status = vchiq_bulk_transmit(service->handle, data_src, data_size,
-+ bulk_handle, mode);
-+
-+ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to
-+ ** implement a retry mechanism since this function is supposed
-+ ** to block until queued
-+ */
-+ while (status == VCHIQ_RETRY) {
-+ msleep(1);
-+ status = vchiq_bulk_transmit(service->handle, data_src,
-+ data_size, bulk_handle, mode);
-+ }
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_bulk_queue_transmit);
-+
-+/***********************************************************
-+ * Name: vchi_msg_dequeue
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * void *data,
-+ * uint32_t max_data_size_to_read,
-+ * uint32_t *actual_msg_size
-+ * VCHI_FLAGS_T flags
-+ *
-+ * Description: Routine to dequeue a message into the supplied buffer
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle,
-+ void *data,
-+ uint32_t max_data_size_to_read,
-+ uint32_t *actual_msg_size,
-+ VCHI_FLAGS_T flags)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ WARN_ON((flags != VCHI_FLAGS_NONE) &&
-+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
-+
-+ if (flags == VCHI_FLAGS_NONE)
-+ if (vchiu_queue_is_empty(&service->queue))
-+ return -1;
-+
-+ header = vchiu_queue_pop(&service->queue);
-+
-+ memcpy(data, header->data, header->size < max_data_size_to_read ?
-+ header->size : max_data_size_to_read);
-+
-+ *actual_msg_size = header->size;
-+
-+ vchiq_release_message(service->handle, header);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_dequeue);
-+
-+/***********************************************************
-+ * Name: vchi_msg_queuev
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * VCHI_MSG_VECTOR_T *vector,
-+ * uint32_t count,
-+ * VCHI_FLAGS_T flags,
-+ * void *msg_handle
-+ *
-+ * Description: Thin wrapper to queue a message onto a connection
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+
-+vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T));
-+vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) ==
-+ offsetof(VCHIQ_ELEMENT_T, data));
-+vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) ==
-+ offsetof(VCHIQ_ELEMENT_T, size));
-+
-+int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_MSG_VECTOR_T *vector,
-+ uint32_t count,
-+ VCHI_FLAGS_T flags,
-+ void *msg_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+
-+ (void)msg_handle;
-+
-+ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED);
-+
-+ return vchiq_status_to_vchi(vchiq_queue_message(service->handle,
-+ (const VCHIQ_ELEMENT_T *)vector, count));
-+}
-+EXPORT_SYMBOL(vchi_msg_queuev);
-+
-+/***********************************************************
-+ * Name: vchi_held_msg_release
-+ *
-+ * Arguments: VCHI_HELD_MSG_T *message
-+ *
-+ * Description: Routine to release a held message (after it has been read with
-+ * vchi_msg_hold)
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message)
-+{
-+ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service,
-+ (VCHIQ_HEADER_T *)message->message);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_held_msg_release);
-+
-+/***********************************************************
-+ * Name: vchi_msg_hold
-+ *
-+ * Arguments: VCHI_SERVICE_HANDLE_T handle,
-+ * void **data,
-+ * uint32_t *msg_size,
-+ * VCHI_FLAGS_T flags,
-+ * VCHI_HELD_MSG_T *message_handle
-+ *
-+ * Description: Routine to return a pointer to the current message (to allow
-+ * in place processing). The message is dequeued - don't forget
-+ * to release the message using vchi_held_msg_release when you're
-+ * finished.
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle,
-+ void **data,
-+ uint32_t *msg_size,
-+ VCHI_FLAGS_T flags,
-+ VCHI_HELD_MSG_T *message_handle)
-+{
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_HEADER_T *header;
-+
-+ WARN_ON((flags != VCHI_FLAGS_NONE) &&
-+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE));
-+
-+ if (flags == VCHI_FLAGS_NONE)
-+ if (vchiu_queue_is_empty(&service->queue))
-+ return -1;
-+
-+ header = vchiu_queue_pop(&service->queue);
-+
-+ *data = header->data;
-+ *msg_size = header->size;
-+
-+ message_handle->service =
-+ (struct opaque_vchi_service_t *)service->handle;
-+ message_handle->message = header;
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(vchi_msg_hold);
-+
-+/***********************************************************
-+ * Name: vchi_initialise
-+ *
-+ * Arguments: VCHI_INSTANCE_T *instance_handle
-+ *
-+ * Description: Initialises the hardware but does not transmit anything
-+ * When run as a Host App this will be called twice hence the need
-+ * to malloc the state information
-+ *
-+ * Returns: 0 if successful, failure otherwise
-+ *
-+ ***********************************************************/
-+
-+int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle)
-+{
-+ VCHIQ_INSTANCE_T instance;
-+ VCHIQ_STATUS_T status;
-+
-+ status = vchiq_initialise(&instance);
-+
-+ *instance_handle = (VCHI_INSTANCE_T)instance;
-+
-+ return vchiq_status_to_vchi(status);
-+}
-+EXPORT_SYMBOL(vchi_initialise);
-+
-+/***********************************************************
-+ * Name: vchi_connect
-+ *
-+ * Arguments: VCHI_CONNECTION_T **connections
-+ * const uint32_t num_connections
-+ * VCHI_INSTANCE_T instance_handle)
-+ *
-+ * Description: Starts the command service on each connection,
-+ * causing INIT messages to be pinged back and forth
-+ *
-+ * Returns: 0 if successful, failure otherwise
-+ *
-+ ***********************************************************/
-+int32_t vchi_connect(VCHI_CONNECTION_T **connections,
-+ const uint32_t num_connections,
-+ VCHI_INSTANCE_T instance_handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+
-+ (void)connections;
-+ (void)num_connections;
-+
-+ return vchiq_connect(instance);
-+}
-+EXPORT_SYMBOL(vchi_connect);
-+
-+
-+/***********************************************************
-+ * Name: vchi_disconnect
-+ *
-+ * Arguments: VCHI_INSTANCE_T instance_handle
-+ *
-+ * Description: Stops the command service on each connection,
-+ * causing DE-INIT messages to be pinged back and forth
-+ *
-+ * Returns: 0 if successful, failure otherwise
-+ *
-+ ***********************************************************/
-+int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+ return vchiq_status_to_vchi(vchiq_shutdown(instance));
-+}
-+EXPORT_SYMBOL(vchi_disconnect);
-+
-+
-+/***********************************************************
-+ * Name: vchi_service_open
-+ * Name: vchi_service_create
-+ *
-+ * Arguments: VCHI_INSTANCE_T *instance_handle
-+ * SERVICE_CREATION_T *setup,
-+ * VCHI_SERVICE_HANDLE_T *handle
-+ *
-+ * Description: Routine to open a service
-+ *
-+ * Returns: int32_t - success == 0
-+ *
-+ ***********************************************************/
-+
-+static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason,
-+ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user)
-+{
-+ SHIM_SERVICE_T *service =
-+ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle);
-+
-+ if (!service->callback)
-+ goto release;
-+
-+ switch (reason) {
-+ case VCHIQ_MESSAGE_AVAILABLE:
-+ vchiu_queue_push(&service->queue, header);
-+
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_MSG_AVAILABLE, NULL);
-+
-+ goto done;
-+ break;
-+
-+ case VCHIQ_BULK_TRANSMIT_DONE:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_SENT, bulk_user);
-+ break;
-+
-+ case VCHIQ_BULK_RECEIVE_DONE:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_RECEIVED, bulk_user);
-+ break;
-+
-+ case VCHIQ_SERVICE_CLOSED:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_SERVICE_CLOSED, NULL);
-+ break;
-+
-+ case VCHIQ_SERVICE_OPENED:
-+ /* No equivalent VCHI reason */
-+ break;
-+
-+ case VCHIQ_BULK_TRANSMIT_ABORTED:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED,
-+ bulk_user);
-+ break;
-+
-+ case VCHIQ_BULK_RECEIVE_ABORTED:
-+ service->callback(service->callback_param,
-+ VCHI_CALLBACK_BULK_RECEIVE_ABORTED,
-+ bulk_user);
-+ break;
-+
-+ default:
-+ WARN(1, "not supported\n");
-+ break;
-+ }
-+
-+release:
-+ vchiq_release_message(service->handle, header);
-+done:
-+ return VCHIQ_SUCCESS;
-+}
-+
-+static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance,
-+ SERVICE_CREATION_T *setup)
-+{
-+ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL);
-+
-+ (void)instance;
-+
-+ if (service) {
-+ if (vchiu_queue_init(&service->queue, 64)) {
-+ service->callback = setup->callback;
-+ service->callback_param = setup->callback_param;
-+ } else {
-+ kfree(service);
-+ service = NULL;
-+ }
-+ }
-+
-+ return service;
-+}
-+
-+static void service_free(SHIM_SERVICE_T *service)
-+{
-+ if (service) {
-+ vchiu_queue_delete(&service->queue);
-+ kfree(service);
-+ }
-+}
-+
-+int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+ SHIM_SERVICE_T *service = service_alloc(instance, setup);
-+
-+ *handle = (VCHI_SERVICE_HANDLE_T)service;
-+
-+ if (service) {
-+ VCHIQ_SERVICE_PARAMS_T params;
-+ VCHIQ_STATUS_T status;
-+
-+ memset(&params, 0, sizeof(params));
-+ params.fourcc = setup->service_id;
-+ params.callback = shim_callback;
-+ params.userdata = service;
-+ params.version = setup->version.version;
-+ params.version_min = setup->version.version_min;
-+
-+ status = vchiq_open_service(instance, &params,
-+ &service->handle);
-+ if (status != VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ *handle = NULL;
-+ }
-+ }
-+
-+ return (service != NULL) ? 0 : -1;
-+}
-+EXPORT_SYMBOL(vchi_service_open);
-+
-+int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle,
-+ SERVICE_CREATION_T *setup,
-+ VCHI_SERVICE_HANDLE_T *handle)
-+{
-+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle;
-+ SHIM_SERVICE_T *service = service_alloc(instance, setup);
-+
-+ *handle = (VCHI_SERVICE_HANDLE_T)service;
-+
-+ if (service) {
-+ VCHIQ_SERVICE_PARAMS_T params;
-+ VCHIQ_STATUS_T status;
-+
-+ memset(&params, 0, sizeof(params));
-+ params.fourcc = setup->service_id;
-+ params.callback = shim_callback;
-+ params.userdata = service;
-+ params.version = setup->version.version;
-+ params.version_min = setup->version.version_min;
-+ status = vchiq_add_service(instance, &params, &service->handle);
-+
-+ if (status != VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ *handle = NULL;
-+ }
-+ }
-+
-+ return (service != NULL) ? 0 : -1;
-+}
-+EXPORT_SYMBOL(vchi_service_create);
-+
-+int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service) {
-+ VCHIQ_STATUS_T status = vchiq_close_service(service->handle);
-+ if (status == VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ }
-+
-+ ret = vchiq_status_to_vchi(status);
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_close);
-+
-+int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service) {
-+ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle);
-+ if (status == VCHIQ_SUCCESS) {
-+ service_free(service);
-+ service = NULL;
-+ }
-+
-+ ret = vchiq_status_to_vchi(status);
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_destroy);
-+
-+int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle,
-+ VCHI_SERVICE_OPTION_T option,
-+ int value)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ VCHIQ_SERVICE_OPTION_T vchiq_option;
-+ switch (option) {
-+ case VCHI_SERVICE_OPTION_TRACE:
-+ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE;
-+ break;
-+ case VCHI_SERVICE_OPTION_SYNCHRONOUS:
-+ vchiq_option = VCHIQ_SERVICE_OPTION_SYNCHRONOUS;
-+ break;
-+ default:
-+ service = NULL;
-+ break;
-+ }
-+ if (service) {
-+ VCHIQ_STATUS_T status =
-+ vchiq_set_service_option(service->handle,
-+ vchiq_option,
-+ value);
-+
-+ ret = vchiq_status_to_vchi(status);
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_set_option);
-+
-+int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version )
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if(service)
-+ {
-+ VCHIQ_STATUS_T status = vchiq_get_peer_version(service->handle, peer_version);
-+ ret = vchiq_status_to_vchi( status );
-+ }
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_get_peer_version);
-+
-+/* ----------------------------------------------------------------------
-+ * read a uint32_t from buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+uint32_t
-+vchi_readbuf_uint32(const void *_ptr)
-+{
-+ const unsigned char *ptr = _ptr;
-+ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * write a uint32_t to buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+void
-+vchi_writebuf_uint32(void *_ptr, uint32_t value)
-+{
-+ unsigned char *ptr = _ptr;
-+ ptr[0] = (unsigned char)((value >> 0) & 0xFF);
-+ ptr[1] = (unsigned char)((value >> 8) & 0xFF);
-+ ptr[2] = (unsigned char)((value >> 16) & 0xFF);
-+ ptr[3] = (unsigned char)((value >> 24) & 0xFF);
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * read a uint16_t from buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+uint16_t
-+vchi_readbuf_uint16(const void *_ptr)
-+{
-+ const unsigned char *ptr = _ptr;
-+ return ptr[0] | (ptr[1] << 8);
-+}
-+
-+/* ----------------------------------------------------------------------
-+ * write a uint16_t into the buffer.
-+ * network format is defined to be little endian
-+ * -------------------------------------------------------------------- */
-+void
-+vchi_writebuf_uint16(void *_ptr, uint16_t value)
-+{
-+ unsigned char *ptr = _ptr;
-+ ptr[0] = (value >> 0) & 0xFF;
-+ ptr[1] = (value >> 8) & 0xFF;
-+}
-+
-+/***********************************************************
-+ * Name: vchi_service_use
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle
-+ *
-+ * Description: Routine to increment refcount on a service
-+ *
-+ * Returns: void
-+ *
-+ ***********************************************************/
-+int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service)
-+ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle));
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_use);
-+
-+/***********************************************************
-+ * Name: vchi_service_release
-+ *
-+ * Arguments: const VCHI_SERVICE_HANDLE_T handle
-+ *
-+ * Description: Routine to decrement refcount on a service
-+ *
-+ * Returns: void
-+ *
-+ ***********************************************************/
-+int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle)
-+{
-+ int32_t ret = -1;
-+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle;
-+ if (service)
-+ ret = vchiq_status_to_vchi(
-+ vchiq_release_service(service->handle));
-+ return ret;
-+}
-+EXPORT_SYMBOL(vchi_service_release);
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,152 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "vchiq_util.h"
-+#include "vchiq_killable.h"
-+
-+static inline int is_pow2(int i)
-+{
-+ return i && !(i & (i - 1));
-+}
-+
-+int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size)
-+{
-+ WARN_ON(!is_pow2(size));
-+
-+ queue->size = size;
-+ queue->read = 0;
-+ queue->write = 0;
-+
-+ sema_init(&queue->pop, 0);
-+ sema_init(&queue->push, 0);
-+
-+ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL);
-+ if (queue->storage == NULL) {
-+ vchiu_queue_delete(queue);
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+void vchiu_queue_delete(VCHIU_QUEUE_T *queue)
-+{
-+ if (queue->storage != NULL)
-+ kfree(queue->storage);
-+}
-+
-+int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue)
-+{
-+ return queue->read == queue->write;
-+}
-+
-+int vchiu_queue_is_full(VCHIU_QUEUE_T *queue)
-+{
-+ return queue->write == queue->read + queue->size;
-+}
-+
-+void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header)
-+{
-+ while (queue->write == queue->read + queue->size) {
-+ if (down_interruptible(&queue->pop) != 0) {
-+ flush_signals(current);
-+ }
-+ }
-+
-+ /*
-+ * Write to queue->storage must be visible after read from
-+ * queue->read
-+ */
-+ smp_mb();
-+
-+ queue->storage[queue->write & (queue->size - 1)] = header;
-+
-+ /*
-+ * Write to queue->storage must be visible before write to
-+ * queue->write
-+ */
-+ smp_wmb();
-+
-+ queue->write++;
-+
-+ up(&queue->push);
-+}
-+
-+VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue)
-+{
-+ while (queue->write == queue->read) {
-+ if (down_interruptible(&queue->push) != 0) {
-+ flush_signals(current);
-+ }
-+ }
-+
-+ up(&queue->push); // We haven't removed anything from the queue.
-+
-+ /*
-+ * Read from queue->storage must be visible after read from
-+ * queue->write
-+ */
-+ smp_rmb();
-+
-+ return queue->storage[queue->read & (queue->size - 1)];
-+}
-+
-+VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue)
-+{
-+ VCHIQ_HEADER_T *header;
-+
-+ while (queue->write == queue->read) {
-+ if (down_interruptible(&queue->push) != 0) {
-+ flush_signals(current);
-+ }
-+ }
-+
-+ /*
-+ * Read from queue->storage must be visible after read from
-+ * queue->write
-+ */
-+ smp_rmb();
-+
-+ header = queue->storage[queue->read & (queue->size - 1)];
-+
-+ /*
-+ * Read from queue->storage must be visible before write to
-+ * queue->read
-+ */
-+ smp_mb();
-+
-+ queue->read++;
-+
-+ up(&queue->pop);
-+
-+ return header;
-+}
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,81 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef VCHIQ_UTIL_H
-+#define VCHIQ_UTIL_H
-+
-+#include <linux/types.h>
-+#include <linux/semaphore.h>
-+#include <linux/mutex.h>
-+#include <linux/bitops.h>
-+#include <linux/kthread.h>
-+#include <linux/wait.h>
-+#include <linux/vmalloc.h>
-+#include <linux/jiffies.h>
-+#include <linux/delay.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/random.h>
-+#include <linux/sched.h>
-+#include <linux/ctype.h>
-+#include <linux/uaccess.h>
-+#include <linux/time.h> /* for time_t */
-+#include <linux/slab.h>
-+#include <linux/vmalloc.h>
-+
-+#include "vchiq_if.h"
-+
-+typedef struct {
-+ int size;
-+ int read;
-+ int write;
-+
-+ struct semaphore pop;
-+ struct semaphore push;
-+
-+ VCHIQ_HEADER_T **storage;
-+} VCHIU_QUEUE_T;
-+
-+extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size);
-+extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue);
-+
-+extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue);
-+extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue);
-+
-+extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header);
-+
-+extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue);
-+extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue);
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c
---- linux-3.18.14/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2015-05-31 14:46:11.157660977 -0500
-@@ -0,0 +1,59 @@
-+/**
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include "vchiq_build_info.h"
-+#include <linux/broadcom/vc_debug_sym.h>
-+
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" );
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" );
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ );
-+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ );
-+
-+const char *vchiq_get_build_hostname( void )
-+{
-+ return vchiq_build_hostname;
-+}
-+
-+const char *vchiq_get_build_version( void )
-+{
-+ return vchiq_build_version;
-+}
-+
-+const char *vchiq_get_build_date( void )
-+{
-+ return vchiq_build_date;
-+}
-+
-+const char *vchiq_get_build_time( void )
-+{
-+ return vchiq_build_time;
-+}
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/Kconfig linux-rpi/drivers/misc/vc04_services/Kconfig
---- linux-3.18.14/drivers/misc/vc04_services/Kconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/Kconfig 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,9 @@
-+config BCM2708_VCHIQ
-+ tristate "Videocore VCHIQ"
-+ depends on MACH_BCM2708 || MACH_BCM2709
-+ default y
-+ help
-+ Kernel to VideoCore communication interface for the
-+ BCM2708 family of products.
-+ Defaults to Y when the Broadcom Videocore services
-+ are included in the build, N otherwise.
-diff -Nur linux-3.18.14/drivers/misc/vc04_services/Makefile linux-rpi/drivers/misc/vc04_services/Makefile
---- linux-3.18.14/drivers/misc/vc04_services/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/misc/vc04_services/Makefile 2015-05-31 14:46:11.153660977 -0500
-@@ -0,0 +1,14 @@
-+obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o
-+
-+vchiq-objs := \
-+ interface/vchiq_arm/vchiq_core.o \
-+ interface/vchiq_arm/vchiq_arm.o \
-+ interface/vchiq_arm/vchiq_kern_lib.o \
-+ interface/vchiq_arm/vchiq_2835_arm.o \
-+ interface/vchiq_arm/vchiq_debugfs.o \
-+ interface/vchiq_arm/vchiq_shim.o \
-+ interface/vchiq_arm/vchiq_util.o \
-+ interface/vchiq_arm/vchiq_connected.o \
-+
-+ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000
-+
-diff -Nur linux-3.18.14/drivers/mmc/card/block.c linux-rpi/drivers/mmc/card/block.c
---- linux-3.18.14/drivers/mmc/card/block.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/card/block.c 2015-05-31 14:46:11.157660977 -0500
-@@ -1406,6 +1406,7 @@
- brq->data.blocks = card->host->ops->multi_io_quirk(card,
- (rq_data_dir(req) == READ) ?
- MMC_DATA_READ : MMC_DATA_WRITE,
-+ blk_rq_pos(req),
- brq->data.blocks);
- }
-
-diff -Nur linux-3.18.14/drivers/mmc/core/quirks.c linux-rpi/drivers/mmc/core/quirks.c
---- linux-3.18.14/drivers/mmc/core/quirks.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/core/quirks.c 2015-05-31 14:46:11.161660977 -0500
-@@ -71,6 +71,7 @@
-
- void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
- {
-+ extern unsigned mmc_debug;
- const struct mmc_fixup *f;
- u64 rev = cid_rev_card(card);
-
-@@ -95,5 +96,10 @@
- f->vendor_fixup(card, f->data);
- }
- }
-+ /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail.
-+ * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers).
-+ */
-+ if (mmc_debug & (1<<13))
-+ card->quirks |= MMC_QUIRK_BLK_NO_CMD23;
- }
- EXPORT_SYMBOL(mmc_fixup_device);
-diff -Nur linux-3.18.14/drivers/mmc/host/bcm2835-mmc.c linux-rpi/drivers/mmc/host/bcm2835-mmc.c
---- linux-3.18.14/drivers/mmc/host/bcm2835-mmc.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/mmc/host/bcm2835-mmc.c 2015-05-31 14:46:11.165660977 -0500
-@@ -0,0 +1,1563 @@
-+/*
-+ * BCM2835 MMC host driver.
-+ *
-+ * Author: Gellert Weisz <gellert@raspberrypi.org>
-+ * Copyright 2014
-+ *
-+ * Based on
-+ * sdhci-bcm2708.c by Broadcom
-+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
-+ * sdhci.c and sdhci-pci.c by Pierre Ossman
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/scatterlist.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/blkdev.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of_dma.h>
-+
-+#include "sdhci.h"
-+
-+
-+#define DRIVER_NAME "mmc-bcm2835"
-+
-+#define DBG(f, x...) \
-+pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
-+
-+#ifndef CONFIG_MMC_BCM2835_DMA
-+ #define FORCE_PIO
-+#endif
-+
-+
-+/* the inclusive limit in bytes under which PIO will be used instead of DMA */
-+#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
-+#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
-+#else
-+#define PIO_DMA_BARRIER 00
-+#endif
-+
-+#define MIN_FREQ 400000
-+#define TIMEOUT_VAL 0xE
-+#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
-+
-+#ifndef BCM2708_PERI_BASE
-+ #define BCM2708_PERI_BASE 0x20000000
-+#endif
-+
-+/* FIXME: Needs IOMMU support */
-+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE)
-+
-+
-+/*static */unsigned mmc_debug;
-+/*static */unsigned mmc_debug2;
-+
-+struct bcm2835_host {
-+ spinlock_t lock;
-+
-+ void __iomem *ioaddr;
-+ u32 phys_addr;
-+
-+ struct mmc_host *mmc;
-+
-+ u32 timeout;
-+
-+ int clock; /* Current clock speed */
-+ u8 pwr; /* Current voltage */
-+
-+ unsigned int max_clk; /* Max possible freq */
-+ unsigned int timeout_clk; /* Timeout freq (KHz) */
-+ unsigned int clk_mul; /* Clock Muliplier value */
-+
-+ struct tasklet_struct finish_tasklet; /* Tasklet structures */
-+
-+ struct timer_list timer; /* Timer for timeouts */
-+
-+ struct sg_mapping_iter sg_miter; /* SG state for PIO */
-+ unsigned int blocks; /* remaining PIO blocks */
-+
-+ int irq; /* Device IRQ */
-+
-+
-+ u32 ier; /* cached registers */
-+
-+ struct mmc_request *mrq; /* Current request */
-+ struct mmc_command *cmd; /* Current command */
-+ struct mmc_data *data; /* Current data request */
-+ unsigned int data_early:1; /* Data finished before cmd */
-+
-+ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
-+
-+ u32 thread_isr;
-+
-+ u32 shadow;
-+
-+ /*DMA part*/
-+ struct dma_chan *dma_chan_rx; /* DMA channel for reads */
-+ struct dma_chan *dma_chan_tx; /* DMA channel for writes */
-+ struct dma_async_tx_descriptor *tx_desc; /* descriptor */
-+
-+ bool have_dma;
-+ bool use_dma;
-+ /*end of DMA part*/
-+
-+ int max_delay; /* maximum length of time spent waiting */
-+
-+ int flags; /* Host attributes */
-+#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
-+#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
-+#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
-+#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
-+#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
-+#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
-+#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
-+#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
-+#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
-+
-+ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
-+ u32 max_overclock; /* Highest reported */
-+};
-+
-+
-+static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)
-+{
-+ u32 delay;
-+ lockdep_assert_held_once(&host->lock);
-+ writel(val, host->ioaddr + reg);
-+ udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
-+
-+ delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);
-+ if (delay && !((1<<from) & mmc_debug2))
-+ udelay(delay);
-+}
-+
-+static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
-+{
-+ u32 delay;
-+ lockdep_assert_held_once(&host->lock);
-+ writel(val, host->ioaddr + reg);
-+
-+ delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);
-+ if (delay)
-+ udelay(delay);
-+}
-+
-+static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
-+{
-+ lockdep_assert_held_once(&host->lock);
-+ return readl(host->ioaddr + reg);
-+}
-+
-+static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
-+{
-+ u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
-+ bcm2835_mmc_readl(host, reg & ~3);
-+ u32 word_num = (reg >> 1) & 1;
-+ u32 word_shift = word_num * 16;
-+ u32 mask = 0xffff << word_shift;
-+ u32 newval = (oldval & ~mask) | (val << word_shift);
-+
-+ if (reg == SDHCI_TRANSFER_MODE)
-+ host->shadow = newval;
-+ else
-+ bcm2835_mmc_writel(host, newval, reg & ~3, 0);
-+
-+}
-+
-+static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
-+{
-+ u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
-+ u32 byte_num = reg & 3;
-+ u32 byte_shift = byte_num * 8;
-+ u32 mask = 0xff << byte_shift;
-+ u32 newval = (oldval & ~mask) | (val << byte_shift);
-+
-+ bcm2835_mmc_writel(host, newval, reg & ~3, 1);
-+}
-+
-+
-+static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
-+{
-+ u32 val = bcm2835_mmc_readl(host, (reg & ~3));
-+ u32 word_num = (reg >> 1) & 1;
-+ u32 word_shift = word_num * 16;
-+ u32 word = (val >> word_shift) & 0xffff;
-+
-+ return word;
-+}
-+
-+static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
-+{
-+ u32 val = bcm2835_mmc_readl(host, (reg & ~3));
-+ u32 byte_num = reg & 3;
-+ u32 byte_shift = byte_num * 8;
-+ u32 byte = (val >> byte_shift) & 0xff;
-+
-+ return byte;
-+}
-+
-+static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
-+{
-+ u32 ier;
-+
-+ ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
-+ ier &= ~clear;
-+ /* change which requests generate IRQs - makes no difference to
-+ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
-+ bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);
-+}
-+
-+
-+static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
-+{
-+ pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
-+ mmc_hostname(host->mmc));
-+
-+ pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
-+ bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
-+ pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
-+ bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
-+ pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
-+ bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
-+ pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
-+ bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
-+ pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
-+ bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
-+ bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
-+ pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
-+ bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
-+ bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
-+ pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
-+ bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
-+ bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
-+ pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
-+ bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
-+ pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
-+ bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
-+ pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
-+ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
-+ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
-+ pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_COMMAND),
-+ bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
-+ pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
-+ bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
-+
-+ pr_debug(DRIVER_NAME ": ===========================================\n");
-+}
-+
-+
-+static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
-+{
-+ unsigned long timeout;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
-+
-+ if (mask & SDHCI_RESET_ALL)
-+ host->clock = 0;
-+
-+ /* Wait max 100 ms */
-+ timeout = 100;
-+
-+ /* hw clears the bit when it's done */
-+ while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
-+ if (timeout == 0) {
-+ pr_err("%s: Reset 0x%x never completed.\n",
-+ mmc_hostname(host->mmc), (int)mask);
-+ bcm2835_mmc_dumpregs(host);
-+ return;
-+ }
-+ timeout--;
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ mdelay(1);
-+ spin_lock_irqsave(&host->lock, flags);
-+ }
-+
-+ if (100-timeout > 10 && 100-timeout > host->max_delay) {
-+ host->max_delay = 100-timeout;
-+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+ }
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
-+
-+static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
-+{
-+ unsigned long flags;
-+ if (soft)
-+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
-+ else
-+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
-+ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
-+ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
-+ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
-+ SDHCI_INT_RESPONSE;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (soft) {
-+ /* force clock reconfiguration */
-+ host->clock = 0;
-+ bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
-+ }
-+}
-+
-+
-+
-+static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
-+
-+static void bcm2835_mmc_dma_complete(void *param)
-+{
-+ struct bcm2835_host *host = param;
-+ struct dma_chan *dma_chan;
-+ unsigned long flags;
-+ u32 dir_data;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
-+ /* otherwise handled in SDHCI IRQ */
-+ dma_chan = host->dma_chan_rx;
-+ dir_data = DMA_FROM_DEVICE;
-+
-+ dma_unmap_sg(dma_chan->device->dev,
-+ host->data->sg, host->data->sg_len,
-+ dir_data);
-+
-+ bcm2835_mmc_finish_data(host);
-+ }
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
-+{
-+ unsigned long flags;
-+ size_t blksize, len, chunk;
-+
-+ u32 uninitialized_var(scratch);
-+ u8 *buf;
-+
-+ blksize = host->data->blksz;
-+ chunk = 0;
-+
-+ local_irq_save(flags);
-+
-+ while (blksize) {
-+ if (!sg_miter_next(&host->sg_miter))
-+ BUG();
-+
-+ len = min(host->sg_miter.length, blksize);
-+
-+ blksize -= len;
-+ host->sg_miter.consumed = len;
-+
-+ buf = host->sg_miter.addr;
-+
-+ while (len) {
-+ if (chunk == 0) {
-+ scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
-+ chunk = 4;
-+ }
-+
-+ *buf = scratch & 0xFF;
-+
-+ buf++;
-+ scratch >>= 8;
-+ chunk--;
-+ len--;
-+ }
-+ }
-+
-+ sg_miter_stop(&host->sg_miter);
-+
-+ local_irq_restore(flags);
-+}
-+
-+static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
-+{
-+ unsigned long flags;
-+ size_t blksize, len, chunk;
-+ u32 scratch;
-+ u8 *buf;
-+
-+ blksize = host->data->blksz;
-+ chunk = 0;
-+ chunk = 0;
-+ scratch = 0;
-+
-+ local_irq_save(flags);
-+
-+ while (blksize) {
-+ if (!sg_miter_next(&host->sg_miter))
-+ BUG();
-+
-+ len = min(host->sg_miter.length, blksize);
-+
-+ blksize -= len;
-+ host->sg_miter.consumed = len;
-+
-+ buf = host->sg_miter.addr;
-+
-+ while (len) {
-+ scratch |= (u32)*buf << (chunk * 8);
-+
-+ buf++;
-+ chunk++;
-+ len--;
-+
-+ if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
-+ mmc_raw_writel(host, scratch, SDHCI_BUFFER);
-+ chunk = 0;
-+ scratch = 0;
-+ }
-+ }
-+ }
-+
-+ sg_miter_stop(&host->sg_miter);
-+
-+ local_irq_restore(flags);
-+}
-+
-+
-+static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
-+{
-+ u32 mask;
-+
-+ BUG_ON(!host->data);
-+
-+ if (host->blocks == 0)
-+ return;
-+
-+ if (host->data->flags & MMC_DATA_READ)
-+ mask = SDHCI_DATA_AVAILABLE;
-+ else
-+ mask = SDHCI_SPACE_AVAILABLE;
-+
-+ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+
-+ if (host->data->flags & MMC_DATA_READ)
-+ bcm2835_bcm2835_mmc_read_block_pio(host);
-+ else
-+ bcm2835_bcm2835_mmc_write_block_pio(host);
-+
-+ host->blocks--;
-+
-+ /* QUIRK used in sdhci.c removes the 'if' */
-+ /* but it seems this is unnecessary */
-+ if (host->blocks == 0)
-+ break;
-+
-+
-+ }
-+}
-+
-+
-+static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
-+{
-+ u32 len, dir_data, dir_slave;
-+ struct dma_async_tx_descriptor *desc = NULL;
-+ struct dma_chan *dma_chan;
-+
-+
-+ WARN_ON(!host->data);
-+
-+ if (!host->data)
-+ return;
-+
-+ if (host->blocks == 0)
-+ return;
-+
-+ if (host->data->flags & MMC_DATA_READ) {
-+ dma_chan = host->dma_chan_rx;
-+ dir_data = DMA_FROM_DEVICE;
-+ dir_slave = DMA_DEV_TO_MEM;
-+ } else {
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ dir_slave = DMA_MEM_TO_DEV;
-+ }
-+
-+ BUG_ON(!dma_chan->device);
-+ BUG_ON(!dma_chan->device->dev);
-+ BUG_ON(!host->data->sg);
-+
-+ len = dma_map_sg(dma_chan->device->dev, host->data->sg,
-+ host->data->sg_len, dir_data);
-+ if (len > 0) {
-+ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
-+ len, dir_slave,
-+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+ } else {
-+ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
-+ }
-+ if (desc) {
-+ unsigned long flags;
-+ spin_lock_irqsave(&host->lock, flags);
-+ bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+ SDHCI_INT_SPACE_AVAIL);
-+ host->tx_desc = desc;
-+ desc->callback = bcm2835_mmc_dma_complete;
-+ desc->callback_param = host;
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ dmaengine_submit(desc);
-+ dma_async_issue_pending(dma_chan);
-+ }
-+
-+}
-+
-+
-+
-+static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
-+{
-+ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
-+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
-+
-+ if (host->use_dma)
-+ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
-+ else
-+ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
-+
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);
-+}
-+
-+
-+static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+ u8 count;
-+ struct mmc_data *data = cmd->data;
-+
-+ WARN_ON(host->data);
-+
-+ if (data || (cmd->flags & MMC_RSP_BUSY)) {
-+ count = TIMEOUT_VAL;
-+ bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
-+ }
-+
-+ if (!data)
-+ return;
-+
-+ /* Sanity checks */
-+ BUG_ON(data->blksz * data->blocks > 524288);
-+ BUG_ON(data->blksz > host->mmc->max_blk_size);
-+ BUG_ON(data->blocks > 65535);
-+
-+ host->data = data;
-+ host->data_early = 0;
-+ host->data->bytes_xfered = 0;
-+
-+
-+ if (!(host->flags & SDHCI_REQ_USE_DMA)) {
-+ int flags;
-+
-+ flags = SG_MITER_ATOMIC;
-+ if (host->data->flags & MMC_DATA_READ)
-+ flags |= SG_MITER_TO_SG;
-+ else
-+ flags |= SG_MITER_FROM_SG;
-+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
-+ host->blocks = data->blocks;
-+ }
-+
-+ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
-+
-+ bcm2835_mmc_set_transfer_irqs(host);
-+
-+ /* Set the DMA boundary value and block size */
-+ bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
-+ data->blksz), SDHCI_BLOCK_SIZE);
-+ bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
-+
-+ BUG_ON(!host->data);
-+}
-+
-+static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
-+ struct mmc_command *cmd)
-+{
-+ u16 mode;
-+ struct mmc_data *data = cmd->data;
-+
-+ if (data == NULL) {
-+ /* clear Auto CMD settings for no data CMDs */
-+ mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
-+ bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
-+ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
-+ return;
-+ }
-+
-+ WARN_ON(!host->data);
-+
-+ mode = SDHCI_TRNS_BLK_CNT_EN;
-+
-+ if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
-+ mode |= SDHCI_TRNS_MULTI;
-+
-+ /*
-+ * If we are sending CMD23, CMD12 never gets sent
-+ * on successful completion (so no Auto-CMD12).
-+ */
-+ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
-+ mode |= SDHCI_TRNS_AUTO_CMD12;
-+ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
-+ mode |= SDHCI_TRNS_AUTO_CMD23;
-+ bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);
-+ }
-+ }
-+
-+ if (data->flags & MMC_DATA_READ)
-+ mode |= SDHCI_TRNS_READ;
-+ if (host->flags & SDHCI_REQ_USE_DMA)
-+ mode |= SDHCI_TRNS_DMA;
-+
-+ bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
-+}
-+
-+void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+ int flags;
-+ u32 mask;
-+ unsigned long timeout;
-+
-+ WARN_ON(host->cmd);
-+
-+ /* Wait max 10 ms */
-+ timeout = 1000;
-+
-+ mask = SDHCI_CMD_INHIBIT;
-+ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
-+ mask |= SDHCI_DATA_INHIBIT;
-+
-+ /* We shouldn't wait for data inihibit for stop commands, even
-+ though they might use busy signaling */
-+ if (host->mrq->data && (cmd == host->mrq->data->stop))
-+ mask &= ~SDHCI_DATA_INHIBIT;
-+
-+ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+ if (timeout == 0) {
-+ pr_err("%s: Controller never released inhibit bit(s).\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_mmc_dumpregs(host);
-+ cmd->error = -EIO;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+ timeout--;
-+ udelay(10);
-+ }
-+
-+ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
-+ host->max_delay = (1000-timeout)/100;
-+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+ }
-+
-+ timeout = jiffies;
-+#ifdef CONFIG_ARCH_BCM2835
-+ if (!cmd->data && cmd->busy_timeout > 9000)
-+ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
-+ else
-+#endif
-+ timeout += 10 * HZ;
-+ mod_timer(&host->timer, timeout);
-+
-+ host->cmd = cmd;
-+
-+ bcm2835_mmc_prepare_data(host, cmd);
-+
-+ bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);
-+
-+ bcm2835_mmc_set_transfer_mode(host, cmd);
-+
-+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
-+ pr_err("%s: Unsupported response type!\n",
-+ mmc_hostname(host->mmc));
-+ cmd->error = -EINVAL;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ if (!(cmd->flags & MMC_RSP_PRESENT))
-+ flags = SDHCI_CMD_RESP_NONE;
-+ else if (cmd->flags & MMC_RSP_136)
-+ flags = SDHCI_CMD_RESP_LONG;
-+ else if (cmd->flags & MMC_RSP_BUSY)
-+ flags = SDHCI_CMD_RESP_SHORT_BUSY;
-+ else
-+ flags = SDHCI_CMD_RESP_SHORT;
-+
-+ if (cmd->flags & MMC_RSP_CRC)
-+ flags |= SDHCI_CMD_CRC;
-+ if (cmd->flags & MMC_RSP_OPCODE)
-+ flags |= SDHCI_CMD_INDEX;
-+
-+ if (cmd->data)
-+ flags |= SDHCI_CMD_DATA;
-+
-+ bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
-+}
-+
-+
-+static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
-+{
-+ struct mmc_data *data;
-+
-+ BUG_ON(!host->data);
-+
-+ data = host->data;
-+ host->data = NULL;
-+
-+ if (data->error)
-+ data->bytes_xfered = 0;
-+ else
-+ data->bytes_xfered = data->blksz * data->blocks;
-+
-+ /*
-+ * Need to send CMD12 if -
-+ * a) open-ended multiblock transfer (no CMD23)
-+ * b) error in multiblock transfer
-+ */
-+ if (data->stop &&
-+ (data->error ||
-+ !host->mrq->sbc)) {
-+
-+ /*
-+ * The controller needs a reset of internal state machines
-+ * upon error conditions.
-+ */
-+ if (data->error) {
-+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
-+ bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
-+ }
-+
-+ bcm2835_mmc_send_command(host, data->stop);
-+ } else
-+ tasklet_schedule(&host->finish_tasklet);
-+}
-+
-+static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
-+{
-+ int i;
-+
-+ BUG_ON(host->cmd == NULL);
-+
-+ if (host->cmd->flags & MMC_RSP_PRESENT) {
-+ if (host->cmd->flags & MMC_RSP_136) {
-+ /* CRC is stripped so we need to do some shifting. */
-+ for (i = 0; i < 4; i++) {
-+ host->cmd->resp[i] = bcm2835_mmc_readl(host,
-+ SDHCI_RESPONSE + (3-i)*4) << 8;
-+ if (i != 3)
-+ host->cmd->resp[i] |=
-+ bcm2835_mmc_readb(host,
-+ SDHCI_RESPONSE + (3-i)*4-1);
-+ }
-+ } else {
-+ host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
-+ }
-+ }
-+
-+ host->cmd->error = 0;
-+
-+ /* Finished CMD23, now send actual command. */
-+ if (host->cmd == host->mrq->sbc) {
-+ host->cmd = NULL;
-+ bcm2835_mmc_send_command(host, host->mrq->cmd);
-+
-+ if (host->mrq->cmd->data && host->use_dma) {
-+ /* DMA transfer starts now, PIO starts after interrupt */
-+ bcm2835_mmc_transfer_dma(host);
-+ }
-+ } else {
-+
-+ /* Processed actual command. */
-+ if (host->data && host->data_early)
-+ bcm2835_mmc_finish_data(host);
-+
-+ if (!host->cmd->data)
-+ tasklet_schedule(&host->finish_tasklet);
-+
-+ host->cmd = NULL;
-+ }
-+}
-+
-+
-+static void bcm2835_mmc_timeout_timer(unsigned long data)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+
-+ host = (struct bcm2835_host *)data;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host->mrq) {
-+ pr_err("%s: Timeout waiting for hardware interrupt.\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_mmc_dumpregs(host);
-+
-+ if (host->data) {
-+ host->data->error = -ETIMEDOUT;
-+ bcm2835_mmc_finish_data(host);
-+ } else {
-+ if (host->cmd)
-+ host->cmd->error = -ETIMEDOUT;
-+ else
-+ host->mrq->cmd->error = -ETIMEDOUT;
-+
-+ tasklet_schedule(&host->finish_tasklet);
-+ }
-+ }
-+
-+ mmiowb();
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
-+{
-+ if (!(host->flags & SDHCI_DEVICE_DEAD)) {
-+ if (enable)
-+ host->ier |= SDHCI_INT_CARD_INT;
-+ else
-+ host->ier &= ~SDHCI_INT_CARD_INT;
-+
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);
-+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);
-+ mmiowb();
-+ }
-+}
-+
-+static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+ struct bcm2835_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ if (enable)
-+ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
-+ else
-+ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
-+
-+ bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+
-+ BUG_ON(intmask == 0);
-+
-+ if (!host->cmd) {
-+ pr_err("%s: Got command interrupt 0x%08x even "
-+ "though no command operation was in progress.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_mmc_dumpregs(host);
-+ return;
-+ }
-+
-+ if (intmask & SDHCI_INT_TIMEOUT)
-+ host->cmd->error = -ETIMEDOUT;
-+ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
-+ SDHCI_INT_INDEX)) {
-+ host->cmd->error = -EILSEQ;
-+ }
-+
-+ if (host->cmd->error) {
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ if (intmask & SDHCI_INT_RESPONSE)
-+ bcm2835_mmc_finish_command(host);
-+
-+}
-+
-+static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+ struct dma_chan *dma_chan;
-+ u32 dir_data;
-+
-+ BUG_ON(intmask == 0);
-+
-+ if (!host->data) {
-+ /*
-+ * The "data complete" interrupt is also used to
-+ * indicate that a busy state has ended. See comment
-+ * above in sdhci_cmd_irq().
-+ */
-+ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
-+ if (intmask & SDHCI_INT_DATA_END) {
-+ bcm2835_mmc_finish_command(host);
-+ return;
-+ }
-+ }
-+
-+ pr_debug("%s: Got data interrupt 0x%08x even "
-+ "though no data operation was in progress.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_mmc_dumpregs(host);
-+
-+ return;
-+ }
-+
-+ if (intmask & SDHCI_INT_DATA_TIMEOUT)
-+ host->data->error = -ETIMEDOUT;
-+ else if (intmask & SDHCI_INT_DATA_END_BIT)
-+ host->data->error = -EILSEQ;
-+ else if ((intmask & SDHCI_INT_DATA_CRC) &&
-+ SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
-+ != MMC_BUS_TEST_R)
-+ host->data->error = -EILSEQ;
-+
-+ if (host->use_dma) {
-+ if (host->data->flags & MMC_DATA_WRITE) {
-+ /* IRQ handled here */
-+
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ dma_unmap_sg(dma_chan->device->dev,
-+ host->data->sg, host->data->sg_len,
-+ dir_data);
-+
-+ bcm2835_mmc_finish_data(host);
-+ }
-+
-+ } else {
-+ if (host->data->error)
-+ bcm2835_mmc_finish_data(host);
-+ else {
-+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
-+ bcm2835_mmc_transfer_pio(host);
-+
-+ if (intmask & SDHCI_INT_DATA_END) {
-+ if (host->cmd) {
-+ /*
-+ * Data managed to finish before the
-+ * command completed. Make sure we do
-+ * things in the proper order.
-+ */
-+ host->data_early = 1;
-+ } else {
-+ bcm2835_mmc_finish_data(host);
-+ }
-+ }
-+ }
-+ }
-+}
-+
-+
-+static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
-+{
-+ irqreturn_t result = IRQ_NONE;
-+ struct bcm2835_host *host = dev_id;
-+ u32 intmask, mask, unexpected = 0;
-+ int max_loops = 16;
-+#ifndef CONFIG_ARCH_BCM2835
-+ int cardint = 0;
-+#endif
-+
-+ spin_lock(&host->lock);
-+
-+ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+
-+ if (!intmask || intmask == 0xffffffff) {
-+ result = IRQ_NONE;
-+ goto out;
-+ }
-+
-+ do {
-+ /* Clear selected interrupts. */
-+ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
-+ SDHCI_INT_BUS_POWER);
-+ bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);
-+
-+
-+ if (intmask & SDHCI_INT_CMD_MASK)
-+ bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
-+
-+ if (intmask & SDHCI_INT_DATA_MASK)
-+ bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
-+
-+ if (intmask & SDHCI_INT_BUS_POWER)
-+ pr_err("%s: Card is consuming too much power!\n",
-+ mmc_hostname(host->mmc));
-+
-+ if (intmask & SDHCI_INT_CARD_INT) {
-+#ifndef CONFIG_ARCH_BCM2835
-+ cardint = 1;
-+#else
-+ bcm2835_mmc_enable_sdio_irq_nolock(host, false);
-+ host->thread_isr |= SDHCI_INT_CARD_INT;
-+ result = IRQ_WAKE_THREAD;
-+#endif
-+ }
-+
-+ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
-+ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
-+ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
-+ SDHCI_INT_CARD_INT);
-+
-+ if (intmask) {
-+ unexpected |= intmask;
-+ bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);
-+ }
-+
-+ if (result == IRQ_NONE)
-+ result = IRQ_HANDLED;
-+
-+ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+ } while (intmask && --max_loops);
-+out:
-+ spin_unlock(&host->lock);
-+
-+ if (unexpected) {
-+ pr_err("%s: Unexpected interrupt 0x%08x.\n",
-+ mmc_hostname(host->mmc), unexpected);
-+ bcm2835_mmc_dumpregs(host);
-+ }
-+
-+#ifndef CONFIG_ARCH_BCM2835
-+ if (cardint)
-+ mmc_signal_sdio_irq(host->mmc);
-+#endif
-+
-+ return result;
-+}
-+
-+#ifdef CONFIG_ARCH_BCM2835
-+static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
-+{
-+ struct bcm2835_host *host = dev_id;
-+ unsigned long flags;
-+ u32 isr;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ isr = host->thread_isr;
-+ host->thread_isr = 0;
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (isr & SDHCI_INT_CARD_INT) {
-+ sdio_run_irqs(host->mmc);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
-+ bcm2835_mmc_enable_sdio_irq_nolock(host, true);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ }
-+
-+ return isr ? IRQ_HANDLED : IRQ_NONE;
-+}
-+#endif
-+
-+
-+
-+void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
-+{
-+ int div = 0; /* Initialized for compiler warning */
-+ int real_div = div, clk_mul = 1;
-+ u16 clk = 0;
-+ unsigned long timeout;
-+ unsigned int input_clock = clock;
-+
-+ if (host->overclock_50 && (clock == 50000000))
-+ clock = host->overclock_50 * 1000000 + 999999;
-+
-+ host->mmc->actual_clock = 0;
-+
-+ bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
-+
-+ if (clock == 0)
-+ return;
-+
-+ /* Version 3.00 divisors must be a multiple of 2. */
-+ if (host->max_clk <= clock)
-+ div = 1;
-+ else {
-+ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
-+ div += 2) {
-+ if ((host->max_clk / div) <= clock)
-+ break;
-+ }
-+ }
-+
-+ real_div = div;
-+ div >>= 1;
-+
-+ if (real_div)
-+ clock = (host->max_clk * clk_mul) / real_div;
-+ host->mmc->actual_clock = clock;
-+
-+ if ((clock > input_clock) && (clock > host->max_overclock)) {
-+ pr_warn("%s: Overclocking to %dHz\n",
-+ mmc_hostname(host->mmc), clock);
-+ host->max_overclock = clock;
-+ }
-+
-+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
-+ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
-+ << SDHCI_DIVIDER_HI_SHIFT;
-+ clk |= SDHCI_CLOCK_INT_EN;
-+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+
-+ /* Wait max 20 ms */
-+ timeout = 20;
-+ while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
-+ & SDHCI_CLOCK_INT_STABLE)) {
-+ if (timeout == 0) {
-+ pr_err("%s: Internal clock never "
-+ "stabilised.\n", mmc_hostname(host->mmc));
-+ bcm2835_mmc_dumpregs(host);
-+ return;
-+ }
-+ timeout--;
-+ mdelay(1);
-+ }
-+
-+ if (20-timeout > 10 && 20-timeout > host->max_delay) {
-+ host->max_delay = 20-timeout;
-+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+ }
-+
-+ clk |= SDHCI_CLOCK_CARD_EN;
-+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+}
-+
-+static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+
-+ host = mmc_priv(mmc);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ WARN_ON(host->mrq != NULL);
-+
-+ host->mrq = mrq;
-+
-+ if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
-+ bcm2835_mmc_send_command(host, mrq->sbc);
-+ else
-+ bcm2835_mmc_send_command(host, mrq->cmd);
-+
-+ mmiowb();
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {
-+ /* DMA transfer starts now, PIO starts after interrupt */
-+ bcm2835_mmc_transfer_dma(host);
-+ }
-+}
-+
-+
-+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+
-+ struct bcm2835_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+ u8 ctrl;
-+ u16 clk, ctrl_2;
-+
-+ pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
-+ ios->clock, ios->power_mode, ios->bus_width,
-+ ios->timing, ios->signal_voltage, ios->drv_type);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (!ios->clock || ios->clock != host->clock) {
-+ bcm2835_mmc_set_clock(host, ios->clock);
-+ host->clock = ios->clock;
-+ }
-+
-+ if (host->pwr != SDHCI_POWER_330) {
-+ host->pwr = SDHCI_POWER_330;
-+ bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
-+ }
-+
-+ ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
-+
-+ /* set bus width */
-+ ctrl &= ~SDHCI_CTRL_8BITBUS;
-+ if (ios->bus_width == MMC_BUS_WIDTH_4)
-+ ctrl |= SDHCI_CTRL_4BITBUS;
-+ else
-+ ctrl &= ~SDHCI_CTRL_4BITBUS;
-+
-+ ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
-+
-+
-+ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-+ /*
-+ * We only need to set Driver Strength if the
-+ * preset value enable is not set.
-+ */
-+ ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
-+ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
-+ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
-+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
-+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
-+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
-+
-+ bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
-+
-+ /* Reset SD Clock Enable */
-+ clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
-+ clk &= ~SDHCI_CLOCK_CARD_EN;
-+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+
-+ /* Re-enable SD Clock */
-+ bcm2835_mmc_set_clock(host, host->clock);
-+ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-+
-+ mmiowb();
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static struct mmc_host_ops bcm2835_ops = {
-+ .request = bcm2835_mmc_request,
-+ .set_ios = bcm2835_mmc_set_ios,
-+ .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
-+};
-+
-+
-+static void bcm2835_mmc_tasklet_finish(unsigned long param)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+ struct mmc_request *mrq;
-+
-+ host = (struct bcm2835_host *)param;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ /*
-+ * If this tasklet gets rescheduled while running, it will
-+ * be run again afterwards but without any active request.
-+ */
-+ if (!host->mrq) {
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ return;
-+ }
-+
-+ del_timer(&host->timer);
-+
-+ mrq = host->mrq;
-+
-+ /*
-+ * The controller needs a reset of internal state machines
-+ * upon error conditions.
-+ */
-+ if (!(host->flags & SDHCI_DEVICE_DEAD) &&
-+ ((mrq->cmd && mrq->cmd->error) ||
-+ (mrq->data && (mrq->data->error ||
-+ (mrq->data->stop && mrq->data->stop->error))))) {
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
-+ bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
-+ spin_lock_irqsave(&host->lock, flags);
-+ }
-+
-+ host->mrq = NULL;
-+ host->cmd = NULL;
-+ host->data = NULL;
-+
-+ mmiowb();
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ mmc_request_done(host->mmc, mrq);
-+}
-+
-+
-+
-+static int bcm2835_mmc_add_host(struct bcm2835_host *host)
-+{
-+ struct mmc_host *mmc = host->mmc;
-+ struct device *dev = mmc->parent;
-+#ifndef FORCE_PIO
-+ struct dma_slave_config cfg;
-+#endif
-+ int ret;
-+
-+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+ host->clk_mul = 0;
-+
-+ mmc->f_max = host->max_clk;
-+ mmc->f_max = host->max_clk;
-+ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
-+
-+ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
-+ host->timeout_clk = mmc->f_max / 1000;
-+#ifdef CONFIG_ARCH_BCM2835
-+ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
-+#endif
-+ /* host controller capabilities */
-+ mmc->caps = MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ |
-+ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA;
-+
-+ host->flags = SDHCI_AUTO_CMD23;
-+
-+ if (mmc_debug || mmc_debug2)
-+ pr_info("mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2);
-+#ifdef FORCE_PIO
-+ dev_info(dev, "Forcing PIO mode\n");
-+ host->have_dma = false;
-+#else
-+ if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
-+ IS_ERR_OR_NULL(host->dma_chan_rx)) {
-+ dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n",
-+ DRIVER_NAME);
-+ host->have_dma = false;
-+ } else {
-+ dev_info(dev, "DMA channels allocated");
-+ host->have_dma = true;
-+
-+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.slave_id = 11; /* DREQ channel */
-+
-+ cfg.direction = DMA_MEM_TO_DEV;
-+ cfg.src_addr = 0;
-+ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER;
-+ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
-+
-+ cfg.direction = DMA_DEV_TO_MEM;
-+ cfg.src_addr = host->phys_addr + SDHCI_BUFFER;
-+ cfg.dst_addr = 0;
-+ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
-+ }
-+#endif
-+ mmc->max_segs = 128;
-+ mmc->max_req_size = 524288;
-+ mmc->max_seg_size = mmc->max_req_size;
-+ mmc->max_blk_size = 512;
-+ mmc->max_blk_count = 65535;
-+
-+ /* report supported voltage ranges */
-+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+ tasklet_init(&host->finish_tasklet,
-+ bcm2835_mmc_tasklet_finish, (unsigned long)host);
-+
-+ setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
-+ init_waitqueue_head(&host->buf_ready_int);
-+
-+ bcm2835_mmc_init(host, 0);
-+#ifndef CONFIG_ARCH_BCM2835
-+ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0,
-+ mmc_hostname(mmc), host);
-+#else
-+ ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq,
-+ bcm2835_mmc_thread_irq, IRQF_SHARED,
-+ mmc_hostname(mmc), host);
-+#endif
-+ if (ret) {
-+ dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret);
-+ goto untasklet;
-+ }
-+
-+ mmiowb();
-+ mmc_add_host(mmc);
-+
-+ return 0;
-+
-+untasklet:
-+ tasklet_kill(&host->finish_tasklet);
-+
-+ return ret;
-+}
-+
-+static int bcm2835_mmc_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *node = dev->of_node;
-+ struct clk *clk;
-+ struct resource *iomem;
-+ struct bcm2835_host *host;
-+ struct mmc_host *mmc;
-+ int ret;
-+
-+ mmc = mmc_alloc_host(sizeof(*host), dev);
-+ if (!mmc)
-+ return -ENOMEM;
-+
-+ mmc->ops = &bcm2835_ops;
-+ host = mmc_priv(mmc);
-+ host->mmc = mmc;
-+ host->timeout = msecs_to_jiffies(1000);
-+ spin_lock_init(&host->lock);
-+
-+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ host->ioaddr = devm_ioremap_resource(dev, iomem);
-+ if (IS_ERR(host->ioaddr)) {
-+ ret = PTR_ERR(host->ioaddr);
-+ goto err;
-+ }
-+
-+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT;
-+
-+#ifndef FORCE_PIO
-+ if (node && of_property_read_bool(node, "dmas")) {
-+ host->dma_chan_tx = of_dma_request_slave_channel(node, "tx");
-+ host->dma_chan_rx = of_dma_request_slave_channel(node, "rx");
-+ } else {
-+ dma_cap_mask_t mask;
-+
-+ dma_cap_zero(mask);
-+ /* we don't care about the channel, any would work */
-+ dma_cap_set(DMA_SLAVE, mask);
-+ host->dma_chan_tx = dma_request_channel(mask, NULL, NULL);
-+ host->dma_chan_rx = dma_request_channel(mask, NULL, NULL);
-+ }
-+#endif
-+ clk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(dev, "could not get clk\n");
-+ ret = PTR_ERR(clk);
-+ goto err;
-+ }
-+
-+ host->max_clk = clk_get_rate(clk);
-+
-+ host->irq = platform_get_irq(pdev, 0);
-+ if (host->irq <= 0) {
-+ dev_err(dev, "get IRQ failed\n");
-+ ret = -EINVAL;
-+ goto err;
-+ }
-+
-+ if (node) {
-+ mmc_of_parse(mmc);
-+
-+ /* Read any custom properties */
-+ of_property_read_u32(node,
-+ "brcm,overclock-50",
-+ &host->overclock_50);
-+ } else {
-+ mmc->caps |= MMC_CAP_4_BIT_DATA;
-+ }
-+
-+ ret = bcm2835_mmc_add_host(host);
-+ if (ret)
-+ goto err;
-+
-+ platform_set_drvdata(pdev, host);
-+
-+ return 0;
-+err:
-+ mmc_free_host(mmc);
-+
-+ return ret;
-+}
-+
-+static int bcm2835_mmc_remove(struct platform_device *pdev)
-+{
-+ struct bcm2835_host *host = platform_get_drvdata(pdev);
-+ unsigned long flags;
-+ int dead;
-+ u32 scratch;
-+
-+ dead = 0;
-+ scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+ if (scratch == (u32)-1)
-+ dead = 1;
-+
-+
-+ if (dead) {
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ host->flags |= SDHCI_DEVICE_DEAD;
-+
-+ if (host->mrq) {
-+ pr_err("%s: Controller removed during "
-+ " transfer!\n", mmc_hostname(host->mmc));
-+
-+ host->mrq->cmd->error = -ENOMEDIUM;
-+ tasklet_schedule(&host->finish_tasklet);
-+ }
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ }
-+
-+ mmc_remove_host(host->mmc);
-+
-+ if (!dead)
-+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+ free_irq(host->irq, host);
-+
-+ del_timer_sync(&host->timer);
-+
-+ tasklet_kill(&host->finish_tasklet);
-+
-+ mmc_free_host(host->mmc);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+
-+static const struct of_device_id bcm2835_mmc_match[] = {
-+ { .compatible = "brcm,bcm2835-mmc" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
-+
-+
-+
-+static struct platform_driver bcm2835_mmc_driver = {
-+ .probe = bcm2835_mmc_probe,
-+ .remove = bcm2835_mmc_remove,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcm2835_mmc_match,
-+ },
-+};
-+module_platform_driver(bcm2835_mmc_driver);
-+
-+module_param(mmc_debug, uint, 0644);
-+module_param(mmc_debug2, uint, 0644);
-+MODULE_ALIAS("platform:mmc-bcm2835");
-+MODULE_DESCRIPTION("BCM2835 SDHCI driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Gellert Weisz");
-diff -Nur linux-3.18.14/drivers/mmc/host/bcm2835-sdhost.c linux-rpi/drivers/mmc/host/bcm2835-sdhost.c
---- linux-3.18.14/drivers/mmc/host/bcm2835-sdhost.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/mmc/host/bcm2835-sdhost.c 2015-05-31 14:46:11.165660977 -0500
-@@ -0,0 +1,1706 @@
-+/*
-+ * BCM2835 SD host driver.
-+ *
-+ * Author: Phil Elwell <phil@raspberrypi.org>
-+ * Copyright 2015
-+ *
-+ * Based on
-+ * mmc-bcm2835.c by Gellert Weisz
-+ * which is, in turn, based on
-+ * sdhci-bcm2708.c by Broadcom
-+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
-+ * sdhci.c and sdhci-pci.c by Pierre Ossman
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define SAFE_READ_THRESHOLD 4
-+#define SAFE_WRITE_THRESHOLD 4
-+#define ALLOW_DMA 1
-+#define ALLOW_CMD23 0
-+#define ALLOW_FAST 1
-+#define USE_BLOCK_IRQ 1
-+
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/scatterlist.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/blkdev.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of_dma.h>
-+#include <linux/time.h>
-+
-+#define DRIVER_NAME "sdhost-bcm2835"
-+
-+#define SDCMD 0x00 /* Command to SD card - 16 R/W */
-+#define SDARG 0x04 /* Argument to SD card - 32 R/W */
-+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
-+#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
-+#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
-+#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
-+#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
-+#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
-+#define SDHSTS 0x20 /* SD host status - 11 R */
-+#define SDVDD 0x30 /* SD card power control - 1 R/W */
-+#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
-+#define SDHCFG 0x38 /* Host configuration - 2 R/W */
-+#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
-+#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
-+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
-+
-+#define SDCMD_NEW_FLAG 0x8000
-+#define SDCMD_FAIL_FLAG 0x4000
-+#define SDCMD_BUSYWAIT 0x800
-+#define SDCMD_NO_RESPONSE 0x400
-+#define SDCMD_LONG_RESPONSE 0x200
-+#define SDCMD_WRITE_CMD 0x80
-+#define SDCMD_READ_CMD 0x40
-+#define SDCMD_CMD_MASK 0x3f
-+
-+#define SDCDIV_MAX_CDIV 0x7ff
-+
-+#define SDHSTS_BUSY_IRPT 0x400
-+#define SDHSTS_BLOCK_IRPT 0x200
-+#define SDHSTS_SDIO_IRPT 0x100
-+#define SDHSTS_REW_TIME_OUT 0x80
-+#define SDHSTS_CMD_TIME_OUT 0x40
-+#define SDHSTS_CRC16_ERROR 0x20
-+#define SDHSTS_CRC7_ERROR 0x10
-+#define SDHSTS_FIFO_ERROR 0x08
-+/* Reserved */
-+/* Reserved */
-+#define SDHSTS_DATA_FLAG 0x01
-+
-+#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)
-+#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)
-+/* SDHSTS_CRC7_ERROR - ignore this as MMC cards generate this spuriously */
-+
-+#define SDHCFG_BUSY_IRPT_EN (1<<10)
-+#define SDHCFG_BLOCK_IRPT_EN (1<<8)
-+#define SDHCFG_SDIO_IRPT_EN (1<<5)
-+#define SDHCFG_DATA_IRPT_EN (1<<4)
-+#define SDHCFG_SLOW_CARD (1<<3)
-+#define SDHCFG_WIDE_EXT_BUS (1<<2)
-+#define SDHCFG_WIDE_INT_BUS (1<<1)
-+#define SDHCFG_REL_CMD_LINE (1<<0)
-+
-+#define SDEDM_FORCE_DATA_MODE (1<<19)
-+#define SDEDM_CLOCK_PULSE (1<<20)
-+#define SDEDM_BYPASS (1<<21)
-+
-+#define SDEDM_WRITE_THRESHOLD_SHIFT 9
-+#define SDEDM_READ_THRESHOLD_SHIFT 14
-+#define SDEDM_THRESHOLD_MASK 0x1f
-+
-+/* the inclusive limit in bytes under which PIO will be used instead of DMA */
-+#ifdef CONFIG_MMC_BCM2835_SDHOST_PIO_DMA_BARRIER
-+#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_SDHOST_PIO_DMA_BARRIER
-+#else
-+#define PIO_DMA_BARRIER 0
-+#endif
-+
-+#define MIN_FREQ 400000
-+#define TIMEOUT_VAL 0xE
-+#define BCM2835_SDHOST_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
-+
-+#ifndef BCM2708_PERI_BASE
-+ #define BCM2708_PERI_BASE 0x20000000
-+#endif
-+
-+/* FIXME: Needs IOMMU support */
-+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE)
-+
-+
-+struct bcm2835_host {
-+ spinlock_t lock;
-+
-+ void __iomem *ioaddr;
-+ u32 phys_addr;
-+
-+ struct mmc_host *mmc;
-+
-+ u32 timeout;
-+
-+ int clock; /* Current clock speed */
-+
-+ bool slow_card; /* Force 11-bit divisor */
-+
-+ unsigned int max_clk; /* Max possible freq */
-+ unsigned int timeout_clk; /* Timeout freq (KHz) */
-+
-+ struct tasklet_struct finish_tasklet; /* Tasklet structures */
-+
-+ struct timer_list timer; /* Timer for timeouts */
-+
-+ struct sg_mapping_iter sg_miter; /* SG state for PIO */
-+ unsigned int blocks; /* remaining PIO blocks */
-+
-+ int irq; /* Device IRQ */
-+
-+
-+ /* cached registers */
-+ u32 hcfg;
-+ u32 cdiv;
-+
-+ struct mmc_request *mrq; /* Current request */
-+ struct mmc_command *cmd; /* Current command */
-+ struct mmc_data *data; /* Current data request */
-+ unsigned int data_complete:1; /* Data finished before cmd */
-+
-+ unsigned int flush_fifo:1; /* Drain the fifo when finishing */
-+
-+ unsigned int use_busy:1; /* Wait for busy interrupt */
-+
-+ u32 thread_isr;
-+
-+ /*DMA part*/
-+ struct dma_chan *dma_chan_rx; /* DMA channel for reads */
-+ struct dma_chan *dma_chan_tx; /* DMA channel for writes */
-+
-+ bool allow_dma;
-+ bool have_dma;
-+ bool use_dma;
-+ /*end of DMA part*/
-+
-+ int max_delay; /* maximum length of time spent waiting */
-+ struct timeval stop_time; /* when the last stop was issued */
-+ u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */
-+ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
-+ u32 max_overclock; /* Highest reported */
-+};
-+
-+
-+static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg)
-+{
-+ writel(val, host->ioaddr + reg);
-+}
-+
-+static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg)
-+{
-+ return readl(host->ioaddr + reg);
-+}
-+
-+static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg)
-+{
-+ return readl_relaxed(host->ioaddr + reg);
-+}
-+
-+static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host)
-+{
-+ pr_info(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
-+ mmc_hostname(host->mmc));
-+
-+ pr_info(DRIVER_NAME ": SDCMD 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDCMD));
-+ pr_info(DRIVER_NAME ": SDARG 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDARG));
-+ pr_info(DRIVER_NAME ": SDTOUT 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDTOUT));
-+ pr_info(DRIVER_NAME ": SDCDIV 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDCDIV));
-+ pr_info(DRIVER_NAME ": SDRSP0 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDRSP0));
-+ pr_info(DRIVER_NAME ": SDRSP1 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDRSP1));
-+ pr_info(DRIVER_NAME ": SDRSP2 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDRSP2));
-+ pr_info(DRIVER_NAME ": SDRSP3 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDRSP3));
-+ pr_info(DRIVER_NAME ": SDHSTS 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDHSTS));
-+ pr_info(DRIVER_NAME ": SDVDD 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDVDD));
-+ pr_info(DRIVER_NAME ": SDEDM 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDEDM));
-+ pr_info(DRIVER_NAME ": SDHCFG 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDHCFG));
-+ pr_info(DRIVER_NAME ": SDHBCT 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDHBCT));
-+ pr_info(DRIVER_NAME ": SDHBLC 0x%08x\n",
-+ bcm2835_sdhost_read(host, SDHBLC));
-+
-+ pr_debug(DRIVER_NAME ": ===========================================\n");
-+}
-+
-+
-+static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
-+{
-+ bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
-+}
-+
-+
-+static void bcm2835_sdhost_reset(struct bcm2835_host *host)
-+{
-+ u32 temp;
-+
-+ pr_debug("bcm2835_sdhost_reset\n");
-+
-+ bcm2835_sdhost_set_power(host, false);
-+
-+ bcm2835_sdhost_write(host, 0, SDCMD);
-+ bcm2835_sdhost_write(host, 0, SDARG);
-+ bcm2835_sdhost_write(host, 0xf00000, SDTOUT);
-+ bcm2835_sdhost_write(host, 0, SDCDIV);
-+ bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */
-+ bcm2835_sdhost_write(host, 0, SDHCFG);
-+ bcm2835_sdhost_write(host, 0, SDHBCT);
-+ bcm2835_sdhost_write(host, 0, SDHBLC);
-+
-+ /* Limit fifo usage due to silicon bug */
-+ temp = bcm2835_sdhost_read(host, SDEDM);
-+ temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |
-+ (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));
-+ temp |= (SAFE_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
-+ (SAFE_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
-+ bcm2835_sdhost_write(host, temp, SDEDM);
-+ mdelay(10);
-+ bcm2835_sdhost_set_power(host, true);
-+ mdelay(10);
-+ host->clock = 0;
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
-+ mmiowb();
-+}
-+
-+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
-+
-+static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft)
-+{
-+ pr_debug("bcm2835_sdhost_init(%d)\n", soft);
-+
-+ /* Set interrupt enables */
-+ host->hcfg = SDHCFG_BUSY_IRPT_EN;
-+
-+ bcm2835_sdhost_reset(host);
-+
-+ if (soft) {
-+ /* force clock reconfiguration */
-+ host->clock = 0;
-+ bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios);
-+ }
-+}
-+
-+static bool bcm2835_sdhost_is_write_complete(struct bcm2835_host *host)
-+{
-+ bool write_complete = ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1);
-+
-+ if (!write_complete) {
-+ /* Request an IRQ for the last block */
-+ host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+ if ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1) {
-+ /* The write has now completed. Disable the interrupt
-+ and clear the status flag */
-+ host->hcfg &= ~SDHCFG_BLOCK_IRPT_EN;
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+ bcm2835_sdhost_write(host, SDHSTS_BLOCK_IRPT, SDHSTS);
-+ write_complete = true;
-+ }
-+ }
-+
-+ return write_complete;
-+}
-+
-+static void bcm2835_sdhost_wait_write_complete(struct bcm2835_host *host)
-+{
-+ int timediff;
-+#ifdef DEBUG
-+ static struct timeval start_time;
-+ static int max_stall_time = 0;
-+ static int total_stall_time = 0;
-+ struct timeval before, after;
-+
-+ do_gettimeofday(&before);
-+ if (max_stall_time == 0)
-+ start_time = before;
-+#endif
-+
-+ timediff = 0;
-+
-+ while (1) {
-+ u32 edm = bcm2835_sdhost_read(host, SDEDM);
-+ if ((edm & 0xf) == 1)
-+ break;
-+ timediff++;
-+ if (timediff > 5000000) {
-+#ifdef DEBUG
-+ do_gettimeofday(&after);
-+ timediff = (after.tv_sec - before.tv_sec)*1000000 +
-+ (after.tv_usec - before.tv_usec);
-+
-+ pr_err(" wait_write_complete - still waiting after %dus\n",
-+ timediff);
-+#else
-+ pr_err(" wait_write_complete - still waiting after %d retries\n",
-+ timediff);
-+#endif
-+ bcm2835_sdhost_dumpregs(host);
-+ host->data->error = -ETIMEDOUT;
-+ return;
-+ }
-+ }
-+
-+#ifdef DEBUG
-+ do_gettimeofday(&after);
-+ timediff = (after.tv_sec - before.tv_sec)*1000000 + (after.tv_usec - before.tv_usec);
-+
-+ total_stall_time += timediff;
-+ if (timediff > max_stall_time)
-+ max_stall_time = timediff;
-+
-+ if ((after.tv_sec - start_time.tv_sec) > 10) {
-+ pr_debug(" wait_write_complete - max wait %dus, total %dus\n",
-+ max_stall_time, total_stall_time);
-+ start_time = after;
-+ max_stall_time = 0;
-+ total_stall_time = 0;
-+ }
-+#endif
-+}
-+
-+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host);
-+
-+static void bcm2835_sdhost_dma_complete(void *param)
-+{
-+ struct bcm2835_host *host = param;
-+ struct dma_chan *dma_chan;
-+ unsigned long flags;
-+ u32 dir_data;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host->data) {
-+ bool write_complete;
-+ if (USE_BLOCK_IRQ)
-+ write_complete = bcm2835_sdhost_is_write_complete(host);
-+ else {
-+ bcm2835_sdhost_wait_write_complete(host);
-+ write_complete = true;
-+ }
-+ pr_debug("dma_complete() - write_complete=%d\n",
-+ write_complete);
-+
-+ if (write_complete || (host->data->flags & MMC_DATA_READ))
-+ {
-+ if (write_complete) {
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ } else {
-+ dma_chan = host->dma_chan_rx;
-+ dir_data = DMA_FROM_DEVICE;
-+ }
-+
-+ dma_unmap_sg(dma_chan->device->dev,
-+ host->data->sg, host->data->sg_len,
-+ dir_data);
-+
-+ bcm2835_sdhost_finish_data(host);
-+ }
-+ }
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host)
-+{
-+ unsigned long flags;
-+ size_t blksize, len;
-+ u32 *buf;
-+
-+ blksize = host->data->blksz;
-+
-+ local_irq_save(flags);
-+
-+ while (blksize) {
-+ if (!sg_miter_next(&host->sg_miter))
-+ BUG();
-+
-+ len = min(host->sg_miter.length, blksize);
-+ BUG_ON(len % 4);
-+
-+ blksize -= len;
-+ host->sg_miter.consumed = len;
-+
-+ buf = (u32 *)host->sg_miter.addr;
-+
-+ while (len) {
-+ while (1) {
-+ u32 hsts;
-+ hsts = bcm2835_sdhost_read(host, SDHSTS);
-+ if (hsts & SDHSTS_DATA_FLAG)
-+ break;
-+
-+ if (hsts & SDHSTS_ERROR_MASK) {
-+ pr_err("%s: Transfer error - HSTS %x, HBCT %x - %x left\n",
-+ mmc_hostname(host->mmc),
-+ hsts,
-+ bcm2835_sdhost_read(host, SDHBCT),
-+ blksize + len);
-+ if (hsts & SDHSTS_REW_TIME_OUT)
-+ host->data->error = -ETIMEDOUT;
-+ else if (hsts & (SDHSTS_CRC16_ERROR ||
-+ SDHSTS_CRC7_ERROR))
-+ host->data->error = -EILSEQ;
-+ else {
-+ pr_err("%s: unexpected data error\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_sdhost_dumpregs(host);
-+ host->cmd->error = -EIO;
-+ }
-+ }
-+ }
-+
-+ *(buf++) = bcm2835_sdhost_read(host, SDDATA);
-+ len -= 4;
-+ }
-+ }
-+
-+ sg_miter_stop(&host->sg_miter);
-+
-+ local_irq_restore(flags);
-+}
-+
-+static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host)
-+{
-+ unsigned long flags;
-+ size_t blksize, len;
-+ u32 *buf;
-+
-+ blksize = host->data->blksz;
-+
-+ local_irq_save(flags);
-+
-+ while (blksize) {
-+ if (!sg_miter_next(&host->sg_miter))
-+ BUG();
-+
-+ len = min(host->sg_miter.length, blksize);
-+ BUG_ON(len % 4);
-+
-+ blksize -= len;
-+ host->sg_miter.consumed = len;
-+
-+ buf = host->sg_miter.addr;
-+
-+ while (len) {
-+ while (!(bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG))
-+ continue;
-+ bcm2835_sdhost_write(host, *(buf++), SDDATA);
-+ len -= 4;
-+ }
-+ }
-+
-+ sg_miter_stop(&host->sg_miter);
-+
-+ local_irq_restore(flags);
-+}
-+
-+
-+static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host)
-+{
-+ BUG_ON(!host->data);
-+
-+ if (host->data->flags & MMC_DATA_READ)
-+ bcm2835_sdhost_read_block_pio(host);
-+ else
-+ bcm2835_sdhost_write_block_pio(host);
-+}
-+
-+
-+static void bcm2835_sdhost_transfer_dma(struct bcm2835_host *host)
-+{
-+ u32 len, dir_data, dir_slave;
-+ struct dma_async_tx_descriptor *desc = NULL;
-+ struct dma_chan *dma_chan;
-+
-+ pr_debug("bcm2835_sdhost_transfer_dma()\n");
-+
-+ WARN_ON(!host->data);
-+
-+ if (!host->data)
-+ return;
-+
-+ if (host->data->flags & MMC_DATA_READ) {
-+ dma_chan = host->dma_chan_rx;
-+ dir_data = DMA_FROM_DEVICE;
-+ dir_slave = DMA_DEV_TO_MEM;
-+ } else {
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ dir_slave = DMA_MEM_TO_DEV;
-+ }
-+
-+ BUG_ON(!dma_chan->device);
-+ BUG_ON(!dma_chan->device->dev);
-+ BUG_ON(!host->data->sg);
-+
-+ len = dma_map_sg(dma_chan->device->dev, host->data->sg,
-+ host->data->sg_len, dir_data);
-+ if (len > 0) {
-+ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
-+ len, dir_slave,
-+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+ } else {
-+ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
-+ }
-+ if (desc) {
-+ desc->callback = bcm2835_sdhost_dma_complete;
-+ desc->callback_param = host;
-+ dmaengine_submit(desc);
-+ dma_async_issue_pending(dma_chan);
-+ }
-+
-+}
-+
-+
-+static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host)
-+{
-+ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
-+ SDHCFG_BUSY_IRPT_EN;
-+ if (host->use_dma)
-+ host->hcfg = (host->hcfg & ~all_irqs) |
-+ SDHCFG_BUSY_IRPT_EN;
-+ else
-+ host->hcfg = (host->hcfg & ~all_irqs) |
-+ SDHCFG_DATA_IRPT_EN |
-+ SDHCFG_BUSY_IRPT_EN;
-+
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+}
-+
-+
-+static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+ struct mmc_data *data = cmd->data;
-+
-+ WARN_ON(host->data);
-+
-+ if (!data)
-+ return;
-+
-+ /* Sanity checks */
-+ BUG_ON(data->blksz * data->blocks > 524288);
-+ BUG_ON(data->blksz > host->mmc->max_blk_size);
-+ BUG_ON(data->blocks > 65535);
-+
-+ host->data = data;
-+ host->data_complete = 0;
-+ host->flush_fifo = 0;
-+ host->data->bytes_xfered = 0;
-+
-+ if (!host->use_dma) {
-+ int flags;
-+
-+ flags = SG_MITER_ATOMIC;
-+ if (data->flags & MMC_DATA_READ)
-+ flags |= SG_MITER_TO_SG;
-+ else
-+ flags |= SG_MITER_FROM_SG;
-+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
-+ host->blocks = data->blocks;
-+ }
-+
-+ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
-+
-+ bcm2835_sdhost_set_transfer_irqs(host);
-+
-+ bcm2835_sdhost_write(host, data->blksz, SDHBCT);
-+ if (host->use_dma)
-+ bcm2835_sdhost_write(host, data->blocks, SDHBLC);
-+
-+ BUG_ON(!host->data);
-+}
-+
-+
-+void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+ u32 sdcmd;
-+ unsigned long timeout;
-+
-+ WARN_ON(host->cmd);
-+
-+ if (1) {
-+ pr_debug("bcm2835_sdhost_send_command: %08x %08x (flags %x)\n",
-+ cmd->opcode, cmd->arg, (cmd->flags & 0xff) | (cmd->data ? cmd->data->flags : 0));
-+ if (cmd->data)
-+ pr_debug("bcm2835_sdhost_send_command: %s %d*%x\n",
-+ (cmd->data->flags & MMC_DATA_READ) ?
-+ "read" : "write", cmd->data->blocks,
-+ cmd->data->blksz);
-+ }
-+
-+ /* Wait max 10 ms */
-+ timeout = 1000;
-+
-+ while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) {
-+ if (timeout == 0) {
-+ pr_err("%s: Previous command never completed.\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_sdhost_dumpregs(host);
-+ cmd->error = -EIO;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+ timeout--;
-+ udelay(10);
-+ }
-+
-+ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
-+ host->max_delay = (1000-timeout)/100;
-+ pr_warning("Warning: SDHost controller hung for %d ms\n", host->max_delay);
-+ }
-+
-+ timeout = jiffies;
-+#ifdef CONFIG_ARCH_BCM2835
-+ if (!cmd->data && cmd->busy_timeout > 9000)
-+ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
-+ else
-+#endif
-+ timeout += 10 * HZ;
-+ mod_timer(&host->timer, timeout);
-+
-+ host->cmd = cmd;
-+
-+ bcm2835_sdhost_prepare_data(host, cmd);
-+
-+ bcm2835_sdhost_write(host, cmd->arg, SDARG);
-+
-+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
-+ pr_err("%s: Unsupported response type!\n",
-+ mmc_hostname(host->mmc));
-+ cmd->error = -EINVAL;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ sdcmd = cmd->opcode & SDCMD_CMD_MASK;
-+
-+ if (!(cmd->flags & MMC_RSP_PRESENT))
-+ sdcmd |= SDCMD_NO_RESPONSE;
-+ else {
-+ if (cmd->flags & MMC_RSP_136)
-+ sdcmd |= SDCMD_LONG_RESPONSE;
-+ if (cmd->flags & MMC_RSP_BUSY) {
-+ sdcmd |= SDCMD_BUSYWAIT;
-+ host->use_busy = 1;
-+ }
-+ }
-+
-+ if (cmd->data) {
-+ if (host->delay_after_stop) {
-+ struct timeval now;
-+ int time_since_stop;
-+ do_gettimeofday(&now);
-+ time_since_stop = (now.tv_sec - host->stop_time.tv_sec);
-+ if (time_since_stop < 2) {
-+ /* Possibly less than one second */
-+ time_since_stop = time_since_stop * 1000000 +
-+ (now.tv_usec - host->stop_time.tv_usec);
-+ if (time_since_stop < host->delay_after_stop)
-+ udelay(host->delay_after_stop -
-+ time_since_stop);
-+ }
-+ }
-+
-+ if (cmd->data->flags & MMC_DATA_WRITE)
-+ sdcmd |= SDCMD_WRITE_CMD;
-+ if (cmd->data->flags & MMC_DATA_READ)
-+ sdcmd |= SDCMD_READ_CMD;
-+ }
-+
-+ bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD);
-+}
-+
-+
-+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host);
-+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host);
-+
-+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host)
-+{
-+ struct mmc_data *data;
-+
-+ data = host->data;
-+ BUG_ON(!data);
-+
-+ pr_debug("finish_data(error %d, stop %d, sbc %d)\n",
-+ data->error, data->stop ? 1 : 0,
-+ host->mrq->sbc ? 1 : 0);
-+
-+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+
-+ if (data->error) {
-+ data->bytes_xfered = 0;
-+ } else
-+ data->bytes_xfered = data->blksz * data->blocks;
-+
-+ host->data_complete = 1;
-+
-+ if (host->cmd) {
-+ /*
-+ * Data managed to finish before the
-+ * command completed. Make sure we do
-+ * things in the proper order.
-+ */
-+ pr_debug("Finished early - HSTS %x\n",
-+ bcm2835_sdhost_read(host, SDHSTS));
-+ }
-+ else
-+ bcm2835_sdhost_transfer_complete(host);
-+}
-+
-+
-+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host)
-+{
-+ struct mmc_data *data;
-+
-+ BUG_ON(host->cmd);
-+ BUG_ON(!host->data);
-+ BUG_ON(!host->data_complete);
-+
-+ data = host->data;
-+ host->data = NULL;
-+
-+ pr_debug("transfer_complete(error %d, stop %d)\n",
-+ data->error, data->stop ? 1 : 0);
-+
-+ if (data->error)
-+ /*
-+ * The controller needs a reset of internal state machines
-+ * upon error conditions.
-+ */
-+ bcm2835_sdhost_reset(host);
-+
-+ /*
-+ * Need to send CMD12 if -
-+ * a) open-ended multiblock transfer (no CMD23)
-+ * b) error in multiblock transfer
-+ */
-+ if (data->stop &&
-+ (data->error ||
-+ !host->mrq->sbc)) {
-+ host->flush_fifo = 1;
-+ bcm2835_sdhost_send_command(host, data->stop);
-+ if (host->delay_after_stop)
-+ do_gettimeofday(&host->stop_time);
-+ if (!host->use_busy)
-+ bcm2835_sdhost_finish_command(host);
-+ } else {
-+ tasklet_schedule(&host->finish_tasklet);
-+ }
-+}
-+
-+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host)
-+{
-+ u32 sdcmd;
-+ int timeout = 1000;
-+#ifdef DEBUG
-+ struct timeval before, after;
-+ int timediff = 0;
-+#endif
-+
-+ pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD));
-+
-+ BUG_ON(!host->cmd || !host->mrq);
-+
-+#ifdef DEBUG
-+ do_gettimeofday(&before);
-+#endif
-+ for (sdcmd = bcm2835_sdhost_read(host, SDCMD);
-+ (sdcmd & SDCMD_NEW_FLAG) && timeout;
-+ timeout--) {
-+ if (host->flush_fifo) {
-+ while (bcm2835_sdhost_read(host, SDHSTS) &
-+ SDHSTS_DATA_FLAG)
-+ (void)bcm2835_sdhost_read(host, SDDATA);
-+ }
-+ udelay(10);
-+ sdcmd = bcm2835_sdhost_read(host, SDCMD);
-+ }
-+#ifdef DEBUG
-+ do_gettimeofday(&after);
-+ timediff = (after.tv_sec - before.tv_sec)*1000000 +
-+ (after.tv_usec - before.tv_usec);
-+
-+ pr_debug(" finish_command - waited %dus\n", timediff);
-+#endif
-+
-+ if (timeout == 0) {
-+ pr_err("%s: Command never completed.\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_sdhost_dumpregs(host);
-+ host->cmd->error = -EIO;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ if (host->flush_fifo) {
-+ for (timeout = 100;
-+ (bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG) && timeout;
-+ timeout--) {
-+ (void)bcm2835_sdhost_read(host, SDDATA);
-+ }
-+ host->flush_fifo = 0;
-+ if (timeout == 0) {
-+ pr_err("%s: FIFO never drained.\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_sdhost_dumpregs(host);
-+ host->cmd->error = -EIO;
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+ }
-+
-+ /* Check for errors */
-+ if (sdcmd & SDCMD_FAIL_FLAG)
-+ {
-+ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
-+
-+ pr_debug("%s: error detected - CMD %x, HSTS %03x, EDM %x\n",
-+ mmc_hostname(host->mmc), sdcmd, sdhsts,
-+ bcm2835_sdhost_read(host, SDEDM));
-+
-+ if (sdhsts & SDHSTS_CMD_TIME_OUT)
-+ host->cmd->error = -ETIMEDOUT;
-+ else
-+ {
-+ pr_err("%s: unexpected command error\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_sdhost_dumpregs(host);
-+ host->cmd->error = -EIO;
-+ }
-+ tasklet_schedule(&host->finish_tasklet);
-+ return;
-+ }
-+
-+ if (host->cmd->flags & MMC_RSP_PRESENT) {
-+ if (host->cmd->flags & MMC_RSP_136) {
-+ int i;
-+ for (i = 0; i < 4; i++)
-+ host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4);
-+ pr_debug("bcm2835_sdhost_finish_command: %08x %08x %08x %08x\n",
-+ host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]);
-+ } else {
-+ host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0);
-+ pr_debug("bcm2835_sdhost_finish_command: %08x\n",
-+ host->cmd->resp[0]);
-+ }
-+ }
-+
-+ host->cmd->error = 0;
-+
-+ if (host->cmd == host->mrq->sbc) {
-+ /* Finished CMD23, now send actual command. */
-+ host->cmd = NULL;
-+ bcm2835_sdhost_send_command(host, host->mrq->cmd);
-+
-+ if (host->cmd->data && host->use_dma)
-+ /* DMA transfer starts now, PIO starts after irq */
-+ bcm2835_sdhost_transfer_dma(host);
-+
-+ if (!host->use_busy)
-+ bcm2835_sdhost_finish_command(host);
-+ } else if (host->cmd == host->mrq->stop)
-+ /* Finished CMD12 */
-+ tasklet_schedule(&host->finish_tasklet);
-+ else {
-+ /* Processed actual command. */
-+ host->cmd = NULL;
-+ if (!host->data)
-+ tasklet_schedule(&host->finish_tasklet);
-+ else if (host->data_complete)
-+ bcm2835_sdhost_transfer_complete(host);
-+ }
-+}
-+
-+static void bcm2835_sdhost_timeout_timer(unsigned long data)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+
-+ host = (struct bcm2835_host *)data;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (host->mrq) {
-+ pr_err("%s: Timeout waiting for hardware interrupt.\n",
-+ mmc_hostname(host->mmc));
-+ bcm2835_sdhost_dumpregs(host);
-+
-+ if (host->data) {
-+ host->data->error = -ETIMEDOUT;
-+ bcm2835_sdhost_finish_data(host);
-+ } else {
-+ if (host->cmd)
-+ host->cmd->error = -ETIMEDOUT;
-+ else
-+ host->mrq->cmd->error = -ETIMEDOUT;
-+
-+ pr_debug("timeout_timer tasklet_schedule\n");
-+ tasklet_schedule(&host->finish_tasklet);
-+ }
-+ }
-+
-+ mmiowb();
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
-+{
-+ if (enable)
-+ host->hcfg |= SDHCFG_SDIO_IRPT_EN;
-+ else
-+ host->hcfg &= ~SDHCFG_SDIO_IRPT_EN;
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+ mmiowb();
-+}
-+
-+static void bcm2835_sdhost_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+ struct bcm2835_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+
-+ pr_debug("bcm2835_sdhost_enable_sdio_irq(%d)\n", enable);
-+ spin_lock_irqsave(&host->lock, flags);
-+ bcm2835_sdhost_enable_sdio_irq_nolock(host, enable);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+ const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR |
-+ SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR);
-+
-+ if (!host->cmd) {
-+ pr_err("%s: Got command busy interrupt 0x%08x even "
-+ "though no command operation was in progress.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_sdhost_dumpregs(host);
-+ return 0;
-+ }
-+
-+ if (!host->use_busy) {
-+ pr_err("%s: Got command busy interrupt 0x%08x even "
-+ "though not expecting one.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_sdhost_dumpregs(host);
-+ return 0;
-+ }
-+ host->use_busy = 0;
-+
-+ if (intmask & SDHSTS_CMD_TIME_OUT)
-+ host->cmd->error = -ETIMEDOUT;
-+ else if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR |
-+ SDHSTS_FIFO_ERROR))
-+ host->cmd->error = -EILSEQ;
-+
-+ if (host->cmd->error)
-+ tasklet_schedule(&host->finish_tasklet);
-+ else
-+ bcm2835_sdhost_finish_command(host);
-+
-+ return handled;
-+}
-+
-+static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+ const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR |
-+ SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR);
-+
-+ /* There are no dedicated data/space available interrupt
-+ status bits, so it is necessary to use the single shared
-+ data/space available FIFO status bits. It is therefore not
-+ an error to get here when there is no data transfer in
-+ progress. */
-+ if (!host->data)
-+ return 0;
-+
-+ // XXX FIFO_ERROR
-+ if (intmask & SDHSTS_CMD_TIME_OUT)
-+ host->cmd->error = -ETIMEDOUT;
-+ else if ((intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR)) &&
-+ ((bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK)
-+ != MMC_BUS_TEST_R))
-+ host->cmd->error = -EILSEQ;
-+
-+ /* Use the block interrupt for writes after the first block */
-+ if (host->data->flags & MMC_DATA_WRITE) {
-+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
-+ host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+ if (host->data->error)
-+ bcm2835_sdhost_finish_data(host);
-+ else
-+ bcm2835_sdhost_transfer_pio(host);
-+ } else {
-+ if (!host->data->error) {
-+ bcm2835_sdhost_transfer_pio(host);
-+ host->blocks--;
-+ }
-+ if ((host->blocks == 0) || host->data->error)
-+ bcm2835_sdhost_finish_data(host);
-+ }
-+
-+ return handled;
-+}
-+
-+static u32 bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+ struct dma_chan *dma_chan;
-+ u32 dir_data;
-+ const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR |
-+ SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR);
-+
-+ if (!host->data) {
-+ pr_err("%s: Got block interrupt 0x%08x even "
-+ "though no data operation was in progress.\n",
-+ mmc_hostname(host->mmc), (unsigned)intmask);
-+ bcm2835_sdhost_dumpregs(host);
-+ return handled;
-+ }
-+
-+ if (intmask & SDHSTS_CMD_TIME_OUT)
-+ host->cmd->error = -ETIMEDOUT;
-+ else if ((intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR)) &&
-+ ((bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK)
-+ != MMC_BUS_TEST_R))
-+ host->cmd->error = -EILSEQ;
-+
-+ if (!host->use_dma) {
-+ BUG_ON(!host->blocks);
-+ host->blocks--;
-+ if ((host->blocks == 0) || host->data->error)
-+ bcm2835_sdhost_finish_data(host);
-+ else
-+ bcm2835_sdhost_transfer_pio(host);
-+ } else if (host->data->flags & MMC_DATA_WRITE) {
-+ dma_chan = host->dma_chan_tx;
-+ dir_data = DMA_TO_DEVICE;
-+ dma_unmap_sg(dma_chan->device->dev,
-+ host->data->sg, host->data->sg_len,
-+ dir_data);
-+
-+ bcm2835_sdhost_finish_data(host);
-+ }
-+
-+ return handled;
-+}
-+
-+
-+static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id)
-+{
-+ irqreturn_t result = IRQ_NONE;
-+ struct bcm2835_host *host = dev_id;
-+ u32 unexpected = 0, early = 0;
-+ int loops = 0;
-+#ifndef CONFIG_ARCH_BCM2835
-+ int cardint = 0;
-+#endif
-+ spin_lock(&host->lock);
-+
-+ for (loops = 0; loops < 1; loops++) {
-+ u32 intmask, handled;
-+
-+ intmask = bcm2835_sdhost_read(host, SDHSTS);
-+ handled = intmask & (SDHSTS_BUSY_IRPT |
-+ SDHSTS_BLOCK_IRPT |
-+ SDHSTS_SDIO_IRPT |
-+ SDHSTS_DATA_FLAG);
-+ if ((handled == SDHSTS_DATA_FLAG) && // XXX
-+ (loops == 0) && !host->data) {
-+ pr_err("%s: sdhost_irq data interrupt 0x%08x even "
-+ "though no data operation was in progress.\n",
-+ mmc_hostname(host->mmc),
-+ (unsigned)intmask);
-+
-+ bcm2835_sdhost_dumpregs(host);
-+ }
-+
-+ if (!handled)
-+ break;
-+
-+ if (loops)
-+ early |= handled;
-+
-+ result = IRQ_HANDLED;
-+
-+ /* Clear all interrupts and notifications */
-+ bcm2835_sdhost_write(host, intmask, SDHSTS);
-+
-+ if (intmask & SDHSTS_BUSY_IRPT)
-+ handled |= bcm2835_sdhost_busy_irq(host, intmask);
-+
-+ /* There is no true data interrupt status bit, so it is
-+ necessary to qualify the data flag with the interrupt
-+ enable bit */
-+ if ((intmask & SDHSTS_DATA_FLAG) &&
-+ (host->hcfg & SDHCFG_DATA_IRPT_EN))
-+ handled |= bcm2835_sdhost_data_irq(host, intmask);
-+
-+ if (intmask & SDHSTS_BLOCK_IRPT)
-+ handled |= bcm2835_sdhost_block_irq(host, intmask);
-+
-+ if (intmask & SDHSTS_SDIO_IRPT) {
-+#ifndef CONFIG_ARCH_BCM2835
-+ cardint = 1;
-+#else
-+ bcm2835_sdhost_enable_sdio_irq_nolock(host, false);
-+ host->thread_isr |= SDHSTS_SDIO_IRPT;
-+ result = IRQ_WAKE_THREAD;
-+#endif
-+ }
-+
-+ unexpected |= (intmask & ~handled);
-+ }
-+
-+ mmiowb();
-+
-+ spin_unlock(&host->lock);
-+
-+ if (early)
-+ pr_debug("%s: early %x (loops %d)\n", mmc_hostname(host->mmc), early, loops);
-+
-+ if (unexpected) {
-+ pr_err("%s: Unexpected interrupt 0x%08x.\n",
-+ mmc_hostname(host->mmc), unexpected);
-+ bcm2835_sdhost_dumpregs(host);
-+ }
-+
-+#ifndef CONFIG_ARCH_BCM2835
-+ if (cardint)
-+ mmc_signal_sdio_irq(host->mmc);
-+#endif
-+
-+ return result;
-+}
-+
-+#ifdef CONFIG_ARCH_BCM2835
-+static irqreturn_t bcm2835_sdhost_thread_irq(int irq, void *dev_id)
-+{
-+ struct bcm2835_host *host = dev_id;
-+ unsigned long flags;
-+ u32 isr;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ isr = host->thread_isr;
-+ host->thread_isr = 0;
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (isr & SDHSTS_SDIO_IRPT) {
-+ sdio_run_irqs(host->mmc);
-+
-+/* Is this necessary? Why re-enable an interrupt which is enabled?
-+ spin_lock_irqsave(&host->lock, flags);
-+ if (host->flags & SDHSTS_SDIO_IRPT_ENABLED)
-+ bcm2835_sdhost_enable_sdio_irq_nolock(host, true);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+*/
-+ }
-+
-+ return isr ? IRQ_HANDLED : IRQ_NONE;
-+}
-+#endif
-+
-+
-+
-+void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock)
-+{
-+ int div = 0; /* Initialized for compiler warning */
-+ unsigned int input_clock = clock;
-+
-+ if (host->overclock_50 && (clock == 50000000))
-+ clock = host->overclock_50 * 1000000 + 999999;
-+
-+ /* The SDCDIV register has 11 bits, and holds (div - 2).
-+ But in data mode the max is 50MHz wihout a minimum, and only the
-+ bottom 3 bits are used. Since the switch over is automatic (unless
-+ we have marked the card as slow...), chosen values have to make
-+ sense in both modes.
-+ Ident mode must be 100-400KHz, so can range check the requested
-+ clock. CMD15 must be used to return to data mode, so this can be
-+ monitored.
-+
-+ clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
-+ 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
-+
-+ 623->400KHz/27.8MHz
-+ reset value (507)->491159/50MHz
-+
-+ BUT, the 3-bit clock divisor in data mode is too small if the
-+ core clock is higher than 250MHz, so instead use the SLOW_CARD
-+ configuration bit to force the use of the ident clock divisor
-+ at all times.
-+ */
-+
-+ host->mmc->actual_clock = 0;
-+
-+ if (clock < 100000) {
-+ /* Can't stop the clock, but make it as slow as possible
-+ * to show willing
-+ */
-+ host->cdiv = SDCDIV_MAX_CDIV;
-+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
-+ return;
-+ }
-+
-+ div = host->max_clk / clock;
-+ if (div < 2)
-+ div = 2;
-+ if ((host->max_clk / div) > clock)
-+ div++;
-+ div -= 2;
-+
-+ if (div > SDCDIV_MAX_CDIV)
-+ div = SDCDIV_MAX_CDIV;
-+
-+ clock = host->max_clk / (div + 2);
-+ host->mmc->actual_clock = clock;
-+
-+ if ((clock > input_clock) && (clock > host->max_overclock)) {
-+ pr_warn("%s: Overclocking to %dHz\n",
-+ mmc_hostname(host->mmc), clock);
-+ host->max_overclock = clock;
-+ }
-+
-+ host->cdiv = div;
-+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
-+
-+ pr_debug(DRIVER_NAME ": clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n",
-+ input_clock, host->max_clk, host->cdiv, host->mmc->actual_clock);
-+}
-+
-+static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+
-+ if (1) {
-+ struct mmc_command *cmd = mrq->cmd;
-+ const char *src = "cmd";
-+ BUG_ON(!cmd);
-+ pr_debug("bcm2835_sdhost_request: %s %08x %08x (flags %x)\n",
-+ src, cmd->opcode, cmd->arg, cmd->flags);
-+ if (cmd->data)
-+ pr_debug("bcm2835_sdhost_request: %s %d*%d\n",
-+ (cmd->data->flags & MMC_DATA_READ) ?
-+ "read" : "write", cmd->data->blocks,
-+ cmd->data->blksz);
-+ }
-+
-+ if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
-+ pr_err("%s: Unsupported block size (%d bytes)\n",
-+ mmc_hostname(mmc), mrq->data->blksz);
-+ mrq->cmd->error = -EINVAL;
-+ mmc_request_done(mmc, mrq);
-+ return;
-+ }
-+
-+ host = mmc_priv(mmc);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ WARN_ON(host->mrq != NULL);
-+
-+ host->mrq = mrq;
-+
-+ if (mrq->sbc)
-+ bcm2835_sdhost_send_command(host, mrq->sbc);
-+ else
-+ bcm2835_sdhost_send_command(host, mrq->cmd);
-+
-+ mmiowb();
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (!mrq->sbc && mrq->cmd->data && host->use_dma)
-+ /* DMA transfer starts now, PIO starts after irq */
-+ bcm2835_sdhost_transfer_dma(host);
-+
-+ if (!host->use_busy)
-+ bcm2835_sdhost_finish_command(host);
-+}
-+
-+
-+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+
-+ struct bcm2835_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+
-+ pr_debug("bcm2835_sdhost_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
-+ ios->clock, ios->power_mode, ios->bus_width,
-+ ios->timing, ios->signal_voltage, ios->drv_type);
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ if (!ios->clock || ios->clock != host->clock) {
-+ bcm2835_sdhost_set_clock(host, ios->clock);
-+ host->clock = ios->clock;
-+ }
-+
-+ /* set bus width */
-+ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
-+ if (ios->bus_width == MMC_BUS_WIDTH_4)
-+ host->hcfg |= SDHCFG_WIDE_EXT_BUS;
-+
-+ host->hcfg |= SDHCFG_WIDE_INT_BUS;
-+
-+ /* Disable clever clock switching, to cope with fast core clocks */
-+ host->hcfg |= SDHCFG_SLOW_CARD;
-+
-+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+
-+ mmiowb();
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static int bcm2835_sdhost_multi_io_quirk(struct mmc_card *card,
-+ unsigned int direction,
-+ u32 blk_pos, int blk_size)
-+{
-+ /* There is a bug in the host controller hardware that makes
-+ reading the final sector of the card as part of a multiple read
-+ problematic. Detect that case and shorten the read accordingly.
-+ */
-+ /* csd.capacity is in weird units - convert to sectors */
-+ u32 card_sectors = (card->csd.capacity << (card->csd.read_blkbits - 9));
-+
-+ if ((direction == MMC_DATA_READ) &&
-+ ((blk_pos + blk_size) == card_sectors))
-+ blk_size--;
-+
-+ return blk_size;
-+}
-+
-+
-+static struct mmc_host_ops bcm2835_sdhost_ops = {
-+ .request = bcm2835_sdhost_request,
-+ .set_ios = bcm2835_sdhost_set_ios,
-+ .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq,
-+ .multi_io_quirk = bcm2835_sdhost_multi_io_quirk,
-+};
-+
-+
-+static void bcm2835_sdhost_tasklet_finish(unsigned long param)
-+{
-+ struct bcm2835_host *host;
-+ unsigned long flags;
-+ struct mmc_request *mrq;
-+
-+ host = (struct bcm2835_host *)param;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+
-+ /*
-+ * If this tasklet gets rescheduled while running, it will
-+ * be run again afterwards but without any active request.
-+ */
-+ if (!host->mrq) {
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ return;
-+ }
-+
-+ del_timer(&host->timer);
-+
-+ mrq = host->mrq;
-+
-+ /*
-+ * The controller needs a reset of internal state machines
-+ * upon error conditions.
-+ */
-+ if (((mrq->cmd && mrq->cmd->error) ||
-+ (mrq->data && (mrq->data->error ||
-+ (mrq->data->stop && mrq->data->stop->error))))) {
-+
-+ bcm2835_sdhost_reset(host);
-+ }
-+
-+ host->mrq = NULL;
-+ host->cmd = NULL;
-+ host->data = NULL;
-+
-+ mmiowb();
-+
-+ spin_unlock_irqrestore(&host->lock, flags);
-+ mmc_request_done(host->mmc, mrq);
-+}
-+
-+
-+
-+int bcm2835_sdhost_add_host(struct bcm2835_host *host)
-+{
-+ struct mmc_host *mmc;
-+ struct dma_slave_config cfg;
-+ int ret;
-+
-+ mmc = host->mmc;
-+
-+ bcm2835_sdhost_reset(host);
-+
-+ mmc->f_max = host->max_clk;
-+ mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
-+
-+ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
-+ host->timeout_clk = mmc->f_max / 1000;
-+#ifdef CONFIG_ARCH_BCM2835
-+ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
-+#endif
-+ /* host controller capabilities */
-+ mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA |
-+ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
-+ MMC_CAP_NEEDS_POLL |
-+ (ALLOW_CMD23 * MMC_CAP_CMD23);
-+
-+ spin_lock_init(&host->lock);
-+
-+ if (host->allow_dma) {
-+ if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
-+ IS_ERR_OR_NULL(host->dma_chan_rx)) {
-+ pr_err("%s: Unable to initialise DMA channels. Falling back to PIO\n", DRIVER_NAME);
-+ host->have_dma = false;
-+ } else {
-+ pr_info("DMA channels allocated for the SDHost driver");
-+ host->have_dma = true;
-+
-+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ cfg.slave_id = 13; /* DREQ channel */
-+
-+ cfg.direction = DMA_MEM_TO_DEV;
-+ cfg.src_addr = 0;
-+ cfg.dst_addr = host->phys_addr + SDDATA;
-+ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
-+
-+ cfg.direction = DMA_DEV_TO_MEM;
-+ cfg.src_addr = host->phys_addr + SDDATA;
-+ cfg.dst_addr = 0;
-+ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
-+ }
-+ } else {
-+ pr_info("Forcing PIO mode\n");
-+ host->have_dma = false;
-+ }
-+
-+ mmc->max_segs = 128;
-+ mmc->max_req_size = 524288;
-+ mmc->max_seg_size = mmc->max_req_size;
-+ mmc->max_blk_size = 512;
-+ mmc->max_blk_count = 65535;
-+
-+ /* report supported voltage ranges */
-+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+ tasklet_init(&host->finish_tasklet,
-+ bcm2835_sdhost_tasklet_finish, (unsigned long)host);
-+
-+ setup_timer(&host->timer, bcm2835_sdhost_timeout_timer, (unsigned long)host);
-+
-+ bcm2835_sdhost_init(host, 0);
-+#ifndef CONFIG_ARCH_BCM2835
-+ ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/,
-+ mmc_hostname(mmc), host);
-+#else
-+ ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq, bcm2835_sdhost_thread_irq,
-+ IRQF_SHARED, mmc_hostname(mmc), host);
-+#endif
-+ if (ret) {
-+ pr_err("%s: Failed to request IRQ %d: %d\n",
-+ mmc_hostname(mmc), host->irq, ret);
-+ goto untasklet;
-+ }
-+
-+ mmiowb();
-+ mmc_add_host(mmc);
-+
-+ pr_info("Load BCM2835 SDHost driver\n");
-+ if (host->delay_after_stop)
-+ pr_info("BCM2835 SDHost: delay_after_stop=%dus\n",
-+ host->delay_after_stop);
-+
-+ return 0;
-+
-+untasklet:
-+ tasklet_kill(&host->finish_tasklet);
-+
-+ return ret;
-+}
-+
-+static int bcm2835_sdhost_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct device_node *node = dev->of_node;
-+ struct clk *clk;
-+ struct resource *iomem;
-+ struct bcm2835_host *host;
-+ struct mmc_host *mmc;
-+ int ret;
-+
-+ pr_debug("bcm2835_sdhost_probe\n");
-+ mmc = mmc_alloc_host(sizeof(*host), dev);
-+ if (!mmc)
-+ return -ENOMEM;
-+
-+ mmc->ops = &bcm2835_sdhost_ops;
-+ host = mmc_priv(mmc);
-+ host->mmc = mmc;
-+ host->timeout = msecs_to_jiffies(1000);
-+ spin_lock_init(&host->lock);
-+
-+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ host->ioaddr = devm_ioremap_resource(dev, iomem);
-+ if (IS_ERR(host->ioaddr)) {
-+ ret = PTR_ERR(host->ioaddr);
-+ goto err;
-+ }
-+
-+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT;
-+ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n",
-+ (unsigned long)host->ioaddr,
-+ (unsigned long)iomem->start,
-+ (unsigned long)host->phys_addr);
-+
-+ host->allow_dma = ALLOW_DMA;
-+
-+ if (node) {
-+ /* Read any custom properties */
-+ of_property_read_u32(node,
-+ "brcm,delay-after-stop",
-+ &host->delay_after_stop);
-+ of_property_read_u32(node,
-+ "brcm,overclock-50",
-+ &host->overclock_50);
-+ host->allow_dma = ALLOW_DMA &&
-+ !of_property_read_bool(node, "brcm,force-pio");
-+ }
-+
-+ if (host->allow_dma) {
-+ dma_cap_mask_t mask;
-+
-+ dma_cap_zero(mask);
-+ /* we don't care about the channel, any would work */
-+ dma_cap_set(DMA_SLAVE, mask);
-+
-+ if (node) {
-+ host->dma_chan_tx =
-+ dma_request_slave_channel(dev, "tx");
-+ host->dma_chan_rx =
-+ dma_request_slave_channel(dev, "rx");
-+ }
-+
-+ if (!host->dma_chan_tx)
-+ host->dma_chan_tx =
-+ dma_request_channel(mask, NULL, NULL);
-+
-+ if (!host->dma_chan_rx)
-+ host->dma_chan_rx =
-+ dma_request_channel(mask, NULL, NULL);
-+ }
-+
-+ clk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(dev, "could not get clk\n");
-+ ret = PTR_ERR(clk);
-+ goto err;
-+ }
-+
-+ host->max_clk = clk_get_rate(clk);
-+
-+ host->irq = platform_get_irq(pdev, 0);
-+ if (host->irq <= 0) {
-+ dev_err(dev, "get IRQ failed\n");
-+ ret = -EINVAL;
-+ goto err;
-+ }
-+
-+ pr_debug(" - max_clk %lx, irq %d\n",
-+ (unsigned long)host->max_clk,
-+ (int)host->irq);
-+
-+ if (node)
-+ mmc_of_parse(mmc);
-+ else
-+ mmc->caps |= MMC_CAP_4_BIT_DATA;
-+
-+ ret = bcm2835_sdhost_add_host(host);
-+ if (ret)
-+ goto err;
-+
-+ platform_set_drvdata(pdev, host);
-+
-+ pr_debug("bcm2835_sdhost_probe -> OK\n");
-+
-+ return 0;
-+
-+err:
-+ pr_debug("bcm2835_sdhost_probe -> err %d\n", ret);
-+ mmc_free_host(mmc);
-+
-+ return ret;
-+}
-+
-+static int bcm2835_sdhost_remove(struct platform_device *pdev)
-+{
-+ struct bcm2835_host *host = platform_get_drvdata(pdev);
-+
-+ pr_debug("bcm2835_sdhost_remove\n");
-+
-+ mmc_remove_host(host->mmc);
-+
-+ bcm2835_sdhost_set_power(host, false);
-+
-+ free_irq(host->irq, host);
-+
-+ del_timer_sync(&host->timer);
-+
-+ tasklet_kill(&host->finish_tasklet);
-+
-+ mmc_free_host(host->mmc);
-+ platform_set_drvdata(pdev, NULL);
-+
-+ pr_debug("bcm2835_sdhost_remove - OK\n");
-+ return 0;
-+}
-+
-+
-+static const struct of_device_id bcm2835_sdhost_match[] = {
-+ { .compatible = "brcm,bcm2835-sdhost" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match);
-+
-+
-+
-+static struct platform_driver bcm2835_sdhost_driver = {
-+ .probe = bcm2835_sdhost_probe,
-+ .remove = bcm2835_sdhost_remove,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcm2835_sdhost_match,
-+ },
-+};
-+module_platform_driver(bcm2835_sdhost_driver);
-+
-+MODULE_ALIAS("platform:sdhost-bcm2835");
-+MODULE_DESCRIPTION("BCM2835 SDHost driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Phil Elwell");
-diff -Nur linux-3.18.14/drivers/mmc/host/Kconfig linux-rpi/drivers/mmc/host/Kconfig
---- linux-3.18.14/drivers/mmc/host/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/host/Kconfig 2015-05-31 14:46:11.161660977 -0500
-@@ -4,6 +4,45 @@
-
- comment "MMC/SD/SDIO Host Controller Drivers"
-
-+config MMC_BCM2835
-+ tristate "MMC support on BCM2835"
-+ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
-+ help
-+ This selects the MMC Interface on BCM2835.
-+
-+ If you have a controller with this interface, say Y or M here.
-+
-+ If unsure, say N.
-+
-+config MMC_BCM2835_DMA
-+ bool "DMA support on BCM2835 Arasan controller"
-+ depends on MMC_BCM2835
-+ help
-+ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
-+ based chips.
-+
-+ If unsure, say N.
-+
-+config MMC_BCM2835_PIO_DMA_BARRIER
-+ int "Block count limit for PIO transfers"
-+ depends on MMC_BCM2835 && MMC_BCM2835_DMA
-+ range 0 256
-+ default 2
-+ help
-+ The inclusive limit in bytes under which PIO will be used instead of DMA
-+
-+ If unsure, say 2 here.
-+
-+config MMC_BCM2835_SDHOST
-+ tristate "Support for the SDHost controller on BCM2708/9"
-+ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
-+ help
-+ This selects the SDHost controller on BCM2835/6.
-+
-+ If you have a controller with this interface, say Y or M here.
-+
-+ If unsure, say N.
-+
- config MMC_ARMMMCI
- tristate "ARM AMBA Multimedia Card Interface support"
- depends on ARM_AMBA
-@@ -281,17 +320,6 @@
-
- If you have a controller with this interface, say Y or M here.
-
--config MMC_SDHCI_BCM2835
-- tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
-- depends on ARCH_BCM2835
-- depends on MMC_SDHCI_PLTFM
-- select MMC_SDHCI_IO_ACCESSORS
-- help
-- This selects the BCM2835 SD/MMC controller. If you have a BCM2835
-- platform with SD or MMC devices, say Y or M here.
--
-- If unsure, say N.
--
- config MMC_MOXART
- tristate "MOXART SD/MMC Host Controller support"
- depends on ARCH_MOXART && MMC
-diff -Nur linux-3.18.14/drivers/mmc/host/Makefile linux-rpi/drivers/mmc/host/Makefile
---- linux-3.18.14/drivers/mmc/host/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/host/Makefile 2015-05-31 14:46:11.161660977 -0500
-@@ -17,6 +17,8 @@
- obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
- obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
- obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
-+obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o
-+obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
- obj-$(CONFIG_MMC_WBSD) += wbsd.o
- obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
- obj-$(CONFIG_MMC_OMAP) += omap.o
-diff -Nur linux-3.18.14/drivers/mmc/host/omap_hsmmc.c linux-rpi/drivers/mmc/host/omap_hsmmc.c
---- linux-3.18.14/drivers/mmc/host/omap_hsmmc.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/host/omap_hsmmc.c 2015-05-31 14:46:11.169660977 -0500
-@@ -1832,7 +1832,9 @@
- }
-
- static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
-- unsigned int direction, int blk_size)
-+ unsigned int direction,
-+ u32 blk_pos,
-+ int blk_size)
- {
- /* This controller can't do multiblock reads due to hw bugs */
- if (direction == MMC_DATA_READ)
-diff -Nur linux-3.18.14/drivers/mmc/host/sh_mobile_sdhi.c linux-rpi/drivers/mmc/host/sh_mobile_sdhi.c
---- linux-3.18.14/drivers/mmc/host/sh_mobile_sdhi.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/host/sh_mobile_sdhi.c 2015-05-31 14:46:11.181660977 -0500
-@@ -139,7 +139,9 @@
- }
-
- static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card,
-- unsigned int direction, int blk_size)
-+ unsigned int direction,
-+ u32 blk_pos,
-+ int blk_size)
- {
- /*
- * In Renesas controllers, when performing a
-diff -Nur linux-3.18.14/drivers/mmc/host/tmio_mmc_pio.c linux-rpi/drivers/mmc/host/tmio_mmc_pio.c
---- linux-3.18.14/drivers/mmc/host/tmio_mmc_pio.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/mmc/host/tmio_mmc_pio.c 2015-05-31 14:46:11.181660977 -0500
-@@ -1002,7 +1002,9 @@
- }
-
- static int tmio_multi_io_quirk(struct mmc_card *card,
-- unsigned int direction, int blk_size)
-+ unsigned int direction,
-+ u32 blk_pos,
-+ int blk_size)
- {
- struct tmio_mmc_host *host = mmc_priv(card->host);
- struct tmio_mmc_data *pdata = host->pdata;
-diff -Nur linux-3.18.14/drivers/net/ethernet/microchip/enc28j60.c linux-rpi/drivers/net/ethernet/microchip/enc28j60.c
---- linux-3.18.14/drivers/net/ethernet/microchip/enc28j60.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/net/ethernet/microchip/enc28j60.c 2015-05-31 14:46:11.465660974 -0500
-@@ -1630,10 +1630,21 @@
- return 0;
- }
-
-+#ifdef CONFIG_OF
-+static const struct of_device_id enc28j60_of_match[] = {
-+ { .compatible = "microchip,enc28j60", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, enc28j60_of_match);
-+#endif
-+
- static struct spi_driver enc28j60_driver = {
- .driver = {
- .name = DRV_NAME,
- .owner = THIS_MODULE,
-+#ifdef CONFIG_OF
-+ .of_match_table = enc28j60_of_match,
-+#endif
- },
- .probe = enc28j60_probe,
- .remove = enc28j60_remove,
-diff -Nur linux-3.18.14/drivers/net/usb/smsc95xx.c linux-rpi/drivers/net/usb/smsc95xx.c
---- linux-3.18.14/drivers/net/usb/smsc95xx.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/net/usb/smsc95xx.c 2015-05-31 14:46:11.597660973 -0500
-@@ -59,6 +59,7 @@
- #define SUSPEND_SUSPEND3 (0x08)
- #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
- SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
-+#define MAC_ADDR_LEN (6)
-
- struct smsc95xx_priv {
- u32 mac_cr;
-@@ -70,10 +71,14 @@
- u8 suspend_flags;
- };
-
--static bool turbo_mode = true;
-+static bool turbo_mode = false;
- module_param(turbo_mode, bool, 0644);
- MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
-
-+static char *macaddr = ":";
-+module_param(macaddr, charp, 0);
-+MODULE_PARM_DESC(macaddr, "MAC address");
-+
- static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
- u32 *data, int in_pm)
- {
-@@ -763,8 +768,59 @@
- return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
- }
-
-+/* Check the macaddr module parameter for a MAC address */
-+static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac)
-+{
-+ int i, j, got_num, num;
-+ u8 mtbl[MAC_ADDR_LEN];
-+
-+ if (macaddr[0] == ':')
-+ return 0;
-+
-+ i = 0;
-+ j = 0;
-+ num = 0;
-+ got_num = 0;
-+ while (j < MAC_ADDR_LEN) {
-+ if (macaddr[i] && macaddr[i] != ':') {
-+ got_num++;
-+ if ('0' <= macaddr[i] && macaddr[i] <= '9')
-+ num = num * 16 + macaddr[i] - '0';
-+ else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
-+ num = num * 16 + 10 + macaddr[i] - 'A';
-+ else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
-+ num = num * 16 + 10 + macaddr[i] - 'a';
-+ else
-+ break;
-+ i++;
-+ } else if (got_num == 2) {
-+ mtbl[j++] = (u8) num;
-+ num = 0;
-+ got_num = 0;
-+ i++;
-+ } else {
-+ break;
-+ }
-+ }
-+
-+ if (j == MAC_ADDR_LEN) {
-+ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: "
-+ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2],
-+ mtbl[3], mtbl[4], mtbl[5]);
-+ for (i = 0; i < MAC_ADDR_LEN; i++)
-+ dev_mac[i] = mtbl[i];
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+}
-+
- static void smsc95xx_init_mac_address(struct usbnet *dev)
- {
-+ /* Check module parameters */
-+ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr))
-+ return;
-+
- /* try reading mac address from EEPROM */
- if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
- dev->net->dev_addr) == 0) {
-@@ -1783,7 +1839,6 @@
- if (dev->net->features & NETIF_F_RXCSUM)
- smsc95xx_rx_csum_offload(skb);
- skb_trim(skb, skb->len - 4); /* remove fcs */
-- skb->truesize = size + sizeof(struct sk_buff);
-
- return 1;
- }
-@@ -1801,7 +1856,6 @@
- if (dev->net->features & NETIF_F_RXCSUM)
- smsc95xx_rx_csum_offload(ax_skb);
- skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
-- ax_skb->truesize = size + sizeof(struct sk_buff);
-
- usbnet_skb_return(dev, ax_skb);
- }
-diff -Nur linux-3.18.14/drivers/of/fdt.c linux-rpi/drivers/of/fdt.c
---- linux-3.18.14/drivers/of/fdt.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/of/fdt.c 2015-05-31 14:46:11.969660970 -0500
-@@ -901,19 +901,38 @@
-
- /* Retrieve command line */
- p = of_get_flat_dt_prop(node, "bootargs", &l);
-- if (p != NULL && l > 0)
-- strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
-
- /*
- * CONFIG_CMDLINE is meant to be a default in case nothing else
- * managed to set the command line, unless CONFIG_CMDLINE_FORCE
- * is set in which case we override whatever was found earlier.
-+ *
-+ * However, it can be useful to be able to treat the default as
-+ * a starting point to be extended using CONFIG_CMDLINE_EXTEND.
- */
-+ ((char *)data)[0] = '\0';
-+
- #ifdef CONFIG_CMDLINE
--#ifndef CONFIG_CMDLINE_FORCE
-- if (!((char *)data)[0])
-+ strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
-+
-+ if (p != NULL && l > 0) {
-+#if defined(CONFIG_CMDLINE_EXTEND)
-+ int len = strlen(data);
-+ if (len > 0) {
-+ strlcat(data, " ", COMMAND_LINE_SIZE);
-+ len++;
-+ }
-+ strlcpy((char *)data + len, p, min((int)l, COMMAND_LINE_SIZE - len));
-+#elif defined(CONFIG_CMDLINE_FORCE)
-+ pr_warning("Ignoring bootargs property (using the default kernel command line)\n");
-+#else
-+ /* Neither extend nor force - just override */
-+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
- #endif
-- strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
-+ }
-+#else /* CONFIG_CMDLINE */
-+ if (p != NULL && l > 0) {
-+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
- #endif /* CONFIG_CMDLINE */
-
- pr_debug("Command line is: %s\n", (char*)data);
-@@ -1083,8 +1102,12 @@
-
- static int __init of_flat_dt_debugfs_export_fdt(void)
- {
-- struct dentry *d = debugfs_create_dir("device-tree", NULL);
-+ struct dentry *d;
-+
-+ if (!initial_boot_params)
-+ return -ENOENT;
-
-+ d = debugfs_create_dir("device-tree", NULL);
- if (!d)
- return -ENOENT;
-
-diff -Nur linux-3.18.14/drivers/pinctrl/pinctrl-bcm2835.c linux-rpi/drivers/pinctrl/pinctrl-bcm2835.c
---- linux-3.18.14/drivers/pinctrl/pinctrl-bcm2835.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/pinctrl/pinctrl-bcm2835.c 2015-05-31 14:46:12.077660969 -0500
-@@ -47,6 +47,7 @@
- #define MODULE_NAME "pinctrl-bcm2835"
- #define BCM2835_NUM_GPIOS 54
- #define BCM2835_NUM_BANKS 2
-+#define BCM2835_NUM_IRQS 3
-
- #define BCM2835_PIN_BITMAP_SZ \
- DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
-@@ -88,13 +89,13 @@
-
- struct bcm2835_gpio_irqdata {
- struct bcm2835_pinctrl *pc;
-- int bank;
-+ int irqgroup;
- };
-
- struct bcm2835_pinctrl {
- struct device *dev;
- void __iomem *base;
-- int irq[BCM2835_NUM_BANKS];
-+ int irq[BCM2835_NUM_IRQS];
-
- /* note: locking assumes each bank will have its own unsigned long */
- unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
-@@ -105,7 +106,7 @@
- struct gpio_chip gpio_chip;
- struct pinctrl_gpio_range gpio_range;
-
-- struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
-+ struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
- spinlock_t irq_lock[BCM2835_NUM_BANKS];
- };
-
-@@ -355,7 +356,14 @@
- static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
- {
-- return pinctrl_gpio_direction_output(chip->base + offset);
-+ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
-+ int ret;
-+
-+ ret = pinctrl_gpio_direction_output(chip->base + offset);
-+ if (ret >= 0)
-+ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
-+
-+ return ret;
- }
-
- static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-@@ -382,22 +390,21 @@
- .get = bcm2835_gpio_get,
- .set = bcm2835_gpio_set,
- .to_irq = bcm2835_gpio_to_irq,
-- .base = -1,
-+ .base = 0,
- .ngpio = BCM2835_NUM_GPIOS,
- .can_sleep = false,
- };
-
--static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
-+static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
-+ unsigned int bank, u32 mask)
- {
-- struct bcm2835_gpio_irqdata *irqdata = dev_id;
-- struct bcm2835_pinctrl *pc = irqdata->pc;
-- int bank = irqdata->bank;
- unsigned long events;
- unsigned offset;
- unsigned gpio;
- unsigned int type;
-
- events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
-+ events &= mask;
- events &= pc->enabled_irq_map[bank];
- for_each_set_bit(offset, &events, 32) {
- gpio = (32 * bank) + offset;
-@@ -413,7 +420,30 @@
- if (type & IRQ_TYPE_LEVEL_MASK)
- bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
- }
-- return events ? IRQ_HANDLED : IRQ_NONE;
-+
-+ return (events != 0);
-+}
-+
-+static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
-+{
-+ struct bcm2835_gpio_irqdata *irqdata = dev_id;
-+ struct bcm2835_pinctrl *pc = irqdata->pc;
-+ int handled = 0;
-+
-+ switch (irqdata->irqgroup) {
-+ case 0: /* IRQ0 covers GPIOs 0-27 */
-+ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
-+ break;
-+ case 1: /* IRQ1 covers GPIOs 28-45 */
-+ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
-+ bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
-+ break;
-+ case 2: /* IRQ2 covers GPIOs 46-53 */
-+ handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
-+ break;
-+ }
-+
-+ return handled ? IRQ_HANDLED : IRQ_NONE;
- }
-
- static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
-@@ -985,8 +1015,6 @@
- for (i = 0; i < BCM2835_NUM_BANKS; i++) {
- unsigned long events;
- unsigned offset;
-- int len;
-- char *name;
-
- /* clear event detection flags */
- bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
-@@ -1001,10 +1029,17 @@
- for_each_set_bit(offset, &events, 32)
- bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
-
-+ spin_lock_init(&pc->irq_lock[i]);
-+ }
-+
-+ for (i = 0; i < BCM2835_NUM_IRQS; i++) {
-+ int len;
-+ char *name;
- pc->irq[i] = irq_of_parse_and_map(np, i);
-+ if (pc->irq[i] == 0)
-+ break;
- pc->irq_data[i].pc = pc;
-- pc->irq_data[i].bank = i;
-- spin_lock_init(&pc->irq_lock[i]);
-+ pc->irq_data[i].irqgroup = i;
-
- len = strlen(dev_name(pc->dev)) + 16;
- name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
-diff -Nur linux-3.18.14/drivers/rtc/rtc-ds1307.c linux-rpi/drivers/rtc/rtc-ds1307.c
---- linux-3.18.14/drivers/rtc/rtc-ds1307.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/rtc/rtc-ds1307.c 2015-05-31 14:46:12.229660968 -0500
-@@ -1241,6 +1241,14 @@
- return 0;
- }
-
-+#ifdef CONFIG_OF
-+static const struct of_device_id ds1307_of_match[] = {
-+ { .compatible = "maxim,ds1307" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, ds1307_of_match);
-+#endif
-+
- static struct i2c_driver ds1307_driver = {
- .driver = {
- .name = "rtc-ds1307",
-diff -Nur linux-3.18.14/drivers/spi/Kconfig linux-rpi/drivers/spi/Kconfig
---- linux-3.18.14/drivers/spi/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/spi/Kconfig 2015-05-31 14:46:12.493660965 -0500
-@@ -77,7 +77,7 @@
-
- config SPI_BCM2835
- tristate "BCM2835 SPI controller"
-- depends on ARCH_BCM2835 || COMPILE_TEST
-+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST
- help
- This selects a driver for the Broadcom BCM2835 SPI master.
-
-@@ -86,6 +86,14 @@
- is for the regular SPI controller. Slave mode operation is not also
- not supported.
-
-+config SPI_BCM2708
-+ tristate "BCM2708 SPI controller driver (SPI0)"
-+ depends on MACH_BCM2708 || MACH_BCM2709
-+ help
-+ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
-+ driver is not compatible with the "Universal SPI Master" or the SPI slave
-+ device.
-+
- config SPI_BFIN5XX
- tristate "SPI controller driver for ADI Blackfin5xx"
- depends on BLACKFIN && !BF60x
-diff -Nur linux-3.18.14/drivers/spi/Makefile linux-rpi/drivers/spi/Makefile
---- linux-3.18.14/drivers/spi/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/spi/Makefile 2015-05-31 14:46:12.493660965 -0500
-@@ -20,6 +20,7 @@
- obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
- obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
- obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
-+obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o
- obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
- obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
- obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
-diff -Nur linux-3.18.14/drivers/spi/spi-bcm2708.c linux-rpi/drivers/spi/spi-bcm2708.c
---- linux-3.18.14/drivers/spi/spi-bcm2708.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/spi/spi-bcm2708.c 2015-05-31 14:46:12.493660965 -0500
-@@ -0,0 +1,635 @@
-+/*
-+ * Driver for Broadcom BCM2708 SPI Controllers
-+ *
-+ * Copyright (C) 2012 Chris Boot
-+ *
-+ * This driver is inspired by:
-+ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/spi/spi.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/log2.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+
-+/* SPI register offsets */
-+#define SPI_CS 0x00
-+#define SPI_FIFO 0x04
-+#define SPI_CLK 0x08
-+#define SPI_DLEN 0x0c
-+#define SPI_LTOH 0x10
-+#define SPI_DC 0x14
-+
-+/* Bitfields in CS */
-+#define SPI_CS_LEN_LONG 0x02000000
-+#define SPI_CS_DMA_LEN 0x01000000
-+#define SPI_CS_CSPOL2 0x00800000
-+#define SPI_CS_CSPOL1 0x00400000
-+#define SPI_CS_CSPOL0 0x00200000
-+#define SPI_CS_RXF 0x00100000
-+#define SPI_CS_RXR 0x00080000
-+#define SPI_CS_TXD 0x00040000
-+#define SPI_CS_RXD 0x00020000
-+#define SPI_CS_DONE 0x00010000
-+#define SPI_CS_LEN 0x00002000
-+#define SPI_CS_REN 0x00001000
-+#define SPI_CS_ADCS 0x00000800
-+#define SPI_CS_INTR 0x00000400
-+#define SPI_CS_INTD 0x00000200
-+#define SPI_CS_DMAEN 0x00000100
-+#define SPI_CS_TA 0x00000080
-+#define SPI_CS_CSPOL 0x00000040
-+#define SPI_CS_CLEAR_RX 0x00000020
-+#define SPI_CS_CLEAR_TX 0x00000010
-+#define SPI_CS_CPOL 0x00000008
-+#define SPI_CS_CPHA 0x00000004
-+#define SPI_CS_CS_10 0x00000002
-+#define SPI_CS_CS_01 0x00000001
-+
-+#define SPI_TIMEOUT_MS 150
-+
-+#define DRV_NAME "bcm2708_spi"
-+
-+struct bcm2708_spi {
-+ spinlock_t lock;
-+ void __iomem *base;
-+ int irq;
-+ struct clk *clk;
-+ bool stopping;
-+
-+ struct list_head queue;
-+ struct workqueue_struct *workq;
-+ struct work_struct work;
-+ struct completion done;
-+
-+ const u8 *tx_buf;
-+ u8 *rx_buf;
-+ int len;
-+};
-+
-+struct bcm2708_spi_state {
-+ u32 cs;
-+ u16 cdiv;
-+};
-+
-+/*
-+ * This function sets the ALT mode on the SPI pins so that we can use them with
-+ * the SPI hardware.
-+ *
-+ * FIXME: This is a hack. Use pinmux / pinctrl.
-+ */
-+static void bcm2708_init_pinmode(void)
-+{
-+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
-+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
-+
-+ int pin;
-+ u32 *gpio = ioremap(GPIO_BASE, SZ_16K);
-+
-+ /* SPI is on GPIO 7..11 */
-+ for (pin = 7; pin <= 11; pin++) {
-+ INP_GPIO(pin); /* set mode to GPIO input first */
-+ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
-+ }
-+
-+ iounmap(gpio);
-+
-+#undef INP_GPIO
-+#undef SET_GPIO_ALT
-+}
-+
-+static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg)
-+{
-+ return readl(bs->base + reg);
-+}
-+
-+static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val)
-+{
-+ writel(val, bs->base + reg);
-+}
-+
-+static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len)
-+{
-+ u8 byte;
-+
-+ while (len--) {
-+ byte = bcm2708_rd(bs, SPI_FIFO);
-+ if (bs->rx_buf)
-+ *bs->rx_buf++ = byte;
-+ }
-+}
-+
-+static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len)
-+{
-+ u8 byte;
-+ u16 val;
-+
-+ if (len > bs->len)
-+ len = bs->len;
-+
-+ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) {
-+ /* LoSSI mode */
-+ if (unlikely(len % 2)) {
-+ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n");
-+ bs->len = 0;
-+ return;
-+ }
-+ while (len) {
-+ if (bs->tx_buf) {
-+ val = *(const u16 *)bs->tx_buf;
-+ bs->tx_buf += 2;
-+ } else
-+ val = 0;
-+ bcm2708_wr(bs, SPI_FIFO, val);
-+ bs->len -= 2;
-+ len -= 2;
-+ }
-+ return;
-+ }
-+
-+ while (len--) {
-+ byte = bs->tx_buf ? *bs->tx_buf++ : 0;
-+ bcm2708_wr(bs, SPI_FIFO, byte);
-+ bs->len--;
-+ }
-+}
-+
-+static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id)
-+{
-+ struct spi_master *master = dev_id;
-+ struct bcm2708_spi *bs = spi_master_get_devdata(master);
-+ u32 cs;
-+
-+ spin_lock(&bs->lock);
-+
-+ cs = bcm2708_rd(bs, SPI_CS);
-+
-+ if (cs & SPI_CS_DONE) {
-+ if (bs->len) { /* first interrupt in a transfer */
-+ /* fill the TX fifo with up to 16 bytes */
-+ bcm2708_wr_fifo(bs, 16);
-+ } else { /* transfer complete */
-+ /* disable interrupts */
-+ cs &= ~(SPI_CS_INTR | SPI_CS_INTD);
-+ bcm2708_wr(bs, SPI_CS, cs);
-+
-+ /* drain RX FIFO */
-+ while (cs & SPI_CS_RXD) {
-+ bcm2708_rd_fifo(bs, 1);
-+ cs = bcm2708_rd(bs, SPI_CS);
-+ }
-+
-+ /* wake up our bh */
-+ complete(&bs->done);
-+ }
-+ } else if (cs & SPI_CS_RXR) {
-+ /* read 12 bytes of data */
-+ bcm2708_rd_fifo(bs, 12);
-+
-+ /* write up to 12 bytes */
-+ bcm2708_wr_fifo(bs, 12);
-+ }
-+
-+ spin_unlock(&bs->lock);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int bcm2708_setup_state(struct spi_master *master,
-+ struct device *dev, struct bcm2708_spi_state *state,
-+ u32 hz, u8 csel, u8 mode, u8 bpw)
-+{
-+ struct bcm2708_spi *bs = spi_master_get_devdata(master);
-+ int cdiv;
-+ unsigned long bus_hz;
-+ u32 cs = 0;
-+
-+ bus_hz = clk_get_rate(bs->clk);
-+
-+ if (hz >= bus_hz) {
-+ cdiv = 2; /* bus_hz / 2 is as fast as we can go */
-+ } else if (hz) {
-+ cdiv = DIV_ROUND_UP(bus_hz, hz);
-+
-+ /* CDIV must be a power of 2, so round up */
-+ cdiv = roundup_pow_of_two(cdiv);
-+
-+ if (cdiv > 65536) {
-+ dev_dbg(dev,
-+ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n",
-+ hz, cdiv, bus_hz / 65536);
-+ return -EINVAL;
-+ } else if (cdiv == 65536) {
-+ cdiv = 0;
-+ } else if (cdiv == 1) {
-+ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */
-+ }
-+ } else {
-+ cdiv = 0;
-+ }
-+
-+ switch (bpw) {
-+ case 8:
-+ break;
-+ case 9:
-+ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */
-+ cs |= SPI_CS_LEN;
-+ break;
-+ default:
-+ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n",
-+ bpw);
-+ return -EINVAL;
-+ }
-+
-+ if (mode & SPI_CPOL)
-+ cs |= SPI_CS_CPOL;
-+ if (mode & SPI_CPHA)
-+ cs |= SPI_CS_CPHA;
-+
-+ if (!(mode & SPI_NO_CS)) {
-+ if (mode & SPI_CS_HIGH) {
-+ cs |= SPI_CS_CSPOL;
-+ cs |= SPI_CS_CSPOL0 << csel;
-+ }
-+
-+ cs |= csel;
-+ } else {
-+ cs |= SPI_CS_CS_10 | SPI_CS_CS_01;
-+ }
-+
-+ if (state) {
-+ state->cs = cs;
-+ state->cdiv = cdiv;
-+ dev_dbg(dev, "setup: want %d Hz; "
-+ "bus_hz=%lu / cdiv=%u == %lu Hz; "
-+ "mode %u: cs 0x%08X\n",
-+ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs);
-+ }
-+
-+ return 0;
-+}
-+
-+static int bcm2708_process_transfer(struct bcm2708_spi *bs,
-+ struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+ struct spi_device *spi = msg->spi;
-+ struct bcm2708_spi_state state, *stp;
-+ int ret;
-+ u32 cs;
-+
-+ if (bs->stopping)
-+ return -ESHUTDOWN;
-+
-+ if (xfer->bits_per_word || xfer->speed_hz) {
-+ ret = bcm2708_setup_state(spi->master, &spi->dev, &state,
-+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
-+ spi->chip_select, spi->mode,
-+ xfer->bits_per_word ? xfer->bits_per_word :
-+ spi->bits_per_word);
-+ if (ret)
-+ return ret;
-+
-+ stp = &state;
-+ } else {
-+ stp = spi->controller_state;
-+ }
-+
-+ reinit_completion(&bs->done);
-+ bs->tx_buf = xfer->tx_buf;
-+ bs->rx_buf = xfer->rx_buf;
-+ bs->len = xfer->len;
-+
-+ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA;
-+
-+ bcm2708_wr(bs, SPI_CLK, stp->cdiv);
-+ bcm2708_wr(bs, SPI_CS, cs);
-+
-+ ret = wait_for_completion_timeout(&bs->done,
-+ msecs_to_jiffies(SPI_TIMEOUT_MS));
-+ if (ret == 0) {
-+ dev_err(&spi->dev, "transfer timed out\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ if (xfer->delay_usecs)
-+ udelay(xfer->delay_usecs);
-+
-+ if (list_is_last(&xfer->transfer_list, &msg->transfers) ||
-+ xfer->cs_change) {
-+ /* clear TA and interrupt flags */
-+ bcm2708_wr(bs, SPI_CS, stp->cs);
-+ }
-+
-+ msg->actual_length += (xfer->len - bs->len);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_work(struct work_struct *work)
-+{
-+ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work);
-+ unsigned long flags;
-+ struct spi_message *msg;
-+ struct spi_transfer *xfer;
-+ int status = 0;
-+
-+ spin_lock_irqsave(&bs->lock, flags);
-+ while (!list_empty(&bs->queue)) {
-+ msg = list_first_entry(&bs->queue, struct spi_message, queue);
-+ list_del_init(&msg->queue);
-+ spin_unlock_irqrestore(&bs->lock, flags);
-+
-+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+ status = bcm2708_process_transfer(bs, msg, xfer);
-+ if (status)
-+ break;
-+ }
-+
-+ msg->status = status;
-+ msg->complete(msg->context);
-+
-+ spin_lock_irqsave(&bs->lock, flags);
-+ }
-+ spin_unlock_irqrestore(&bs->lock, flags);
-+}
-+
-+static int bcm2708_spi_setup(struct spi_device *spi)
-+{
-+ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
-+ struct bcm2708_spi_state *state;
-+ int ret;
-+
-+ if (bs->stopping)
-+ return -ESHUTDOWN;
-+
-+ if (!(spi->mode & SPI_NO_CS) &&
-+ (spi->chip_select > spi->master->num_chipselect)) {
-+ dev_dbg(&spi->dev,
-+ "setup: invalid chipselect %u (%u defined)\n",
-+ spi->chip_select, spi->master->num_chipselect);
-+ return -EINVAL;
-+ }
-+
-+ state = spi->controller_state;
-+ if (!state) {
-+ state = kzalloc(sizeof(*state), GFP_KERNEL);
-+ if (!state)
-+ return -ENOMEM;
-+
-+ spi->controller_state = state;
-+ }
-+
-+ ret = bcm2708_setup_state(spi->master, &spi->dev, state,
-+ spi->max_speed_hz, spi->chip_select, spi->mode,
-+ spi->bits_per_word);
-+ if (ret < 0) {
-+ kfree(state);
-+ spi->controller_state = NULL;
-+ return ret;
-+ }
-+
-+ dev_dbg(&spi->dev,
-+ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n",
-+ spi->chip_select, spi->max_speed_hz, spi->bits_per_word,
-+ spi->mode, state->cs, state->cdiv);
-+
-+ return 0;
-+}
-+
-+static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg)
-+{
-+ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
-+ struct spi_transfer *xfer;
-+ int ret;
-+ unsigned long flags;
-+
-+ if (unlikely(list_empty(&msg->transfers)))
-+ return -EINVAL;
-+
-+ if (bs->stopping)
-+ return -ESHUTDOWN;
-+
-+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
-+ dev_dbg(&spi->dev, "missing rx or tx buf\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!xfer->bits_per_word || xfer->speed_hz)
-+ continue;
-+
-+ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL,
-+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
-+ spi->chip_select, spi->mode,
-+ xfer->bits_per_word ? xfer->bits_per_word :
-+ spi->bits_per_word);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ msg->status = -EINPROGRESS;
-+ msg->actual_length = 0;
-+
-+ spin_lock_irqsave(&bs->lock, flags);
-+ list_add_tail(&msg->queue, &bs->queue);
-+ queue_work(bs->workq, &bs->work);
-+ spin_unlock_irqrestore(&bs->lock, flags);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_spi_cleanup(struct spi_device *spi)
-+{
-+ if (spi->controller_state) {
-+ kfree(spi->controller_state);
-+ spi->controller_state = NULL;
-+ }
-+}
-+
-+static int bcm2708_spi_probe(struct platform_device *pdev)
-+{
-+ struct resource *regs;
-+ int irq, err = -ENOMEM;
-+ struct clk *clk;
-+ struct spi_master *master;
-+ struct bcm2708_spi *bs;
-+
-+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!regs) {
-+ dev_err(&pdev->dev, "could not get IO memory\n");
-+ return -ENXIO;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "could not get IRQ\n");
-+ return irq;
-+ }
-+
-+ clk = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
-+ return PTR_ERR(clk);
-+ }
-+
-+ bcm2708_init_pinmode();
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(*bs));
-+ if (!master) {
-+ dev_err(&pdev->dev, "spi_alloc_master() failed\n");
-+ goto out_clk_put;
-+ }
-+
-+ /* the spi->mode bits understood by this driver: */
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS;
-+
-+ master->bus_num = pdev->id;
-+ master->num_chipselect = 3;
-+ master->setup = bcm2708_spi_setup;
-+ master->transfer = bcm2708_spi_transfer;
-+ master->cleanup = bcm2708_spi_cleanup;
-+ master->dev.of_node = pdev->dev.of_node;
-+ platform_set_drvdata(pdev, master);
-+
-+ bs = spi_master_get_devdata(master);
-+
-+ spin_lock_init(&bs->lock);
-+ INIT_LIST_HEAD(&bs->queue);
-+ init_completion(&bs->done);
-+ INIT_WORK(&bs->work, bcm2708_work);
-+
-+ bs->base = ioremap(regs->start, resource_size(regs));
-+ if (!bs->base) {
-+ dev_err(&pdev->dev, "could not remap memory\n");
-+ goto out_master_put;
-+ }
-+
-+ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev));
-+ if (!bs->workq) {
-+ dev_err(&pdev->dev, "could not create workqueue\n");
-+ goto out_iounmap;
-+ }
-+
-+ bs->irq = irq;
-+ bs->clk = clk;
-+ bs->stopping = false;
-+
-+ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev),
-+ master);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
-+ goto out_workqueue;
-+ }
-+
-+ /* initialise the hardware */
-+ clk_prepare_enable(clk);
-+ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
-+
-+ err = spi_register_master(master);
-+ if (err) {
-+ dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
-+ goto out_free_irq;
-+ }
-+
-+ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n",
-+ (unsigned long)regs->start, irq);
-+
-+ return 0;
-+
-+out_free_irq:
-+ free_irq(bs->irq, master);
-+ clk_disable_unprepare(bs->clk);
-+out_workqueue:
-+ destroy_workqueue(bs->workq);
-+out_iounmap:
-+ iounmap(bs->base);
-+out_master_put:
-+ spi_master_put(master);
-+out_clk_put:
-+ clk_put(clk);
-+ return err;
-+}
-+
-+static int bcm2708_spi_remove(struct platform_device *pdev)
-+{
-+ struct spi_master *master = platform_get_drvdata(pdev);
-+ struct bcm2708_spi *bs = spi_master_get_devdata(master);
-+
-+ /* reset the hardware and block queue progress */
-+ spin_lock_irq(&bs->lock);
-+ bs->stopping = true;
-+ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
-+ spin_unlock_irq(&bs->lock);
-+
-+ flush_work(&bs->work);
-+
-+ clk_disable_unprepare(bs->clk);
-+ clk_put(bs->clk);
-+ free_irq(bs->irq, master);
-+ iounmap(bs->base);
-+
-+ spi_unregister_master(master);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id bcm2708_spi_match[] = {
-+ { .compatible = "brcm,bcm2708-spi", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, bcm2708_spi_match);
-+
-+static struct platform_driver bcm2708_spi_driver = {
-+ .driver = {
-+ .name = DRV_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcm2708_spi_match,
-+ },
-+ .probe = bcm2708_spi_probe,
-+ .remove = bcm2708_spi_remove,
-+};
-+
-+
-+static int __init bcm2708_spi_init(void)
-+{
-+ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe);
-+}
-+module_init(bcm2708_spi_init);
-+
-+static void __exit bcm2708_spi_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_spi_driver);
-+}
-+module_exit(bcm2708_spi_exit);
-+
-+
-+//module_platform_driver(bcm2708_spi_driver);
-+
-+MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708");
-+MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRV_NAME);
-diff -Nur linux-3.18.14/drivers/spi/spi-bcm2835.c linux-rpi/drivers/spi/spi-bcm2835.c
---- linux-3.18.14/drivers/spi/spi-bcm2835.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/spi/spi-bcm2835.c 2015-05-31 14:46:12.493660965 -0500
-@@ -3,6 +3,7 @@
- *
- * Copyright (C) 2012 Chris Boot
- * Copyright (C) 2013 Stephen Warren
-+ * Copyright (C) 2015 Martin Sperl
- *
- * This driver is inspired by:
- * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-@@ -33,6 +34,7 @@
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_irq.h>
-+#include <linux/of_gpio.h>
- #include <linux/of_device.h>
- #include <linux/spi/spi.h>
-
-@@ -70,8 +72,10 @@
- #define BCM2835_SPI_CS_CS_10 0x00000002
- #define BCM2835_SPI_CS_CS_01 0x00000001
-
--#define BCM2835_SPI_TIMEOUT_MS 30000
--#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS)
-+#define BCM2835_SPI_POLLING_LIMIT_US 30
-+#define BCM2835_SPI_TIMEOUT_MS 30000
-+#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
-+ | SPI_NO_CS | SPI_3WIRE)
-
- #define DRV_NAME "spi-bcm2835"
-
-@@ -79,10 +83,10 @@
- void __iomem *regs;
- struct clk *clk;
- int irq;
-- struct completion done;
- const u8 *tx_buf;
- u8 *rx_buf;
-- int len;
-+ int tx_len;
-+ int rx_len;
- };
-
- static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
-@@ -95,205 +99,314 @@
- writel(val, bs->regs + reg);
- }
-
--static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs, int len)
-+static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
- {
- u8 byte;
-
-- while (len--) {
-+ while ((bs->rx_len) &&
-+ (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
- byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
- if (bs->rx_buf)
- *bs->rx_buf++ = byte;
-+ bs->rx_len--;
- }
- }
-
--static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs, int len)
-+static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
- {
- u8 byte;
-
-- if (len > bs->len)
-- len = bs->len;
--
-- while (len--) {
-+ while ((bs->tx_len) &&
-+ (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
- byte = bs->tx_buf ? *bs->tx_buf++ : 0;
- bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
-- bs->len--;
-+ bs->tx_len--;
- }
- }
-
-+static void bcm2835_spi_reset_hw(struct spi_master *master)
-+{
-+ struct bcm2835_spi *bs = spi_master_get_devdata(master);
-+ u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
-+
-+ /* Disable SPI interrupts and transfer */
-+ cs &= ~(BCM2835_SPI_CS_INTR |
-+ BCM2835_SPI_CS_INTD |
-+ BCM2835_SPI_CS_TA);
-+ /* and reset RX/TX FIFOS */
-+ cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
-+
-+ /* and reset the SPI_HW */
-+ bcm2835_wr(bs, BCM2835_SPI_CS, cs);
-+}
-+
- static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
- {
- struct spi_master *master = dev_id;
- struct bcm2835_spi *bs = spi_master_get_devdata(master);
-- u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
-
-- /*
-- * RXR - RX needs Reading. This means 12 (or more) bytes have been
-- * transmitted and hence 12 (or more) bytes have been received.
-- *
-- * The FIFO is 16-bytes deep. We check for this interrupt to keep the
-- * FIFO full; we have a 4-byte-time buffer for IRQ latency. We check
-- * this before DONE (TX empty) just in case we delayed processing this
-- * interrupt for some reason.
-- *
-- * We only check for this case if we have more bytes to TX; at the end
-- * of the transfer, we ignore this pipelining optimization, and let
-- * bcm2835_spi_finish_transfer() drain the RX FIFO.
-+ /* Read as many bytes as possible from FIFO */
-+ bcm2835_rd_fifo(bs);
-+ /* Write as many bytes as possible to FIFO */
-+ bcm2835_wr_fifo(bs);
-+
-+ /* based on flags decide if we can finish the transfer */
-+ if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
-+ /* Transfer complete - reset SPI HW */
-+ bcm2835_spi_reset_hw(master);
-+ /* wake up the framework */
-+ complete(&master->xfer_completion);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr,
-+ u32 cs,
-+ unsigned long xfer_time_us)
-+{
-+ struct bcm2835_spi *bs = spi_master_get_devdata(master);
-+ /* set timeout to 1 second of maximum polling */
-+ unsigned long timeout = jiffies + HZ;
-+
-+ /* enable HW block without interrupts */
-+ bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
-+
-+ /* loop until finished the transfer */
-+ while (bs->rx_len) {
-+ /* read from fifo as much as possible */
-+ bcm2835_rd_fifo(bs);
-+ /* fill in tx fifo as much as possible */
-+ bcm2835_wr_fifo(bs);
-+ /* if we still expect some data after the read,
-+ * check for a possible timeout
-+ */
-+ if (bs->rx_len && time_after(jiffies, timeout)) {
-+ /* Transfer complete - reset SPI HW */
-+ bcm2835_spi_reset_hw(master);
-+ /* and return timeout */
-+ return -ETIMEDOUT;
-+ }
-+ }
-+
-+ /* Transfer complete - reset SPI HW */
-+ bcm2835_spi_reset_hw(master);
-+ /* and return without waiting for completion */
-+ return 0;
-+}
-+
-+static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr,
-+ u32 cs)
-+{
-+ struct bcm2835_spi *bs = spi_master_get_devdata(master);
-+
-+ /* fill in fifo if we have gpio-cs
-+ * note that there have been rare events where the native-CS
-+ * flapped for <1us which may change the behaviour
-+ * with gpio-cs this does not happen, so it is implemented
-+ * only for this case
- */
-- if (bs->len && (cs & BCM2835_SPI_CS_RXR)) {
-- /* Read 12 bytes of data */
-- bcm2835_rd_fifo(bs, 12);
--
-- /* Write up to 12 bytes */
-- bcm2835_wr_fifo(bs, 12);
--
-- /*
-- * We must have written something to the TX FIFO due to the
-- * bs->len check above, so cannot be DONE. Hence, return
-- * early. Note that DONE could also be set if we serviced an
-- * RXR interrupt really late.
-+ if (gpio_is_valid(spi->cs_gpio)) {
-+ /* enable HW block, but without interrupts enabled
-+ * this would triggern an immediate interrupt
- */
-- return IRQ_HANDLED;
-+ bcm2835_wr(bs, BCM2835_SPI_CS,
-+ cs | BCM2835_SPI_CS_TA);
-+ /* fill in tx fifo as much as possible */
-+ bcm2835_wr_fifo(bs);
- }
-
- /*
-- * DONE - TX empty. This occurs when we first enable the transfer
-- * since we do not pre-fill the TX FIFO. At any other time, given that
-- * we refill the TX FIFO above based on RXR, and hence ignore DONE if
-- * RXR is set, DONE really does mean end-of-transfer.
-+ * Enable the HW block. This will immediately trigger a DONE (TX
-+ * empty) interrupt, upon which we will fill the TX FIFO with the
-+ * first TX bytes. Pre-filling the TX FIFO here to avoid the
-+ * interrupt doesn't work:-(
- */
-- if (cs & BCM2835_SPI_CS_DONE) {
-- if (bs->len) { /* First interrupt in a transfer */
-- bcm2835_wr_fifo(bs, 16);
-- } else { /* Transfer complete */
-- /* Disable SPI interrupts */
-- cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
-- bcm2835_wr(bs, BCM2835_SPI_CS, cs);
--
-- /*
-- * Wake up bcm2835_spi_transfer_one(), which will call
-- * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
-- */
-- complete(&bs->done);
-- }
--
-- return IRQ_HANDLED;
-- }
-+ cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
-+ bcm2835_wr(bs, BCM2835_SPI_CS, cs);
-
-- return IRQ_NONE;
-+ /* signal that we need to wait for completion */
-+ return 1;
- }
-
--static int bcm2835_spi_start_transfer(struct spi_device *spi,
-- struct spi_transfer *tfr)
-+static int bcm2835_spi_transfer_one(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr)
- {
-- struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
-+ struct bcm2835_spi *bs = spi_master_get_devdata(master);
- unsigned long spi_hz, clk_hz, cdiv;
-- u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
-+ unsigned long spi_used_hz, xfer_time_us;
-+ u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
-
-+ /* set clock */
- spi_hz = tfr->speed_hz;
- clk_hz = clk_get_rate(bs->clk);
-
- if (spi_hz >= clk_hz / 2) {
- cdiv = 2; /* clk_hz/2 is the fastest we can go */
- } else if (spi_hz) {
-- /* CDIV must be a power of two */
-- cdiv = roundup_pow_of_two(DIV_ROUND_UP(clk_hz, spi_hz));
-+ /* CDIV must be a multiple of two */
-+ cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
-+ cdiv += (cdiv % 2);
-
- if (cdiv >= 65536)
- cdiv = 0; /* 0 is the slowest we can go */
-- } else
-+ } else {
- cdiv = 0; /* 0 is the slowest we can go */
-+ }
-+ spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
-+ bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
-
-+ /* handle all the modes */
-+ if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
-+ cs |= BCM2835_SPI_CS_REN;
- if (spi->mode & SPI_CPOL)
- cs |= BCM2835_SPI_CS_CPOL;
- if (spi->mode & SPI_CPHA)
- cs |= BCM2835_SPI_CS_CPHA;
-
-- if (!(spi->mode & SPI_NO_CS)) {
-- if (spi->mode & SPI_CS_HIGH) {
-- cs |= BCM2835_SPI_CS_CSPOL;
-- cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
-- }
--
-- cs |= spi->chip_select;
-- }
-+ /* for gpio_cs set dummy CS so that no HW-CS get changed
-+ * we can not run this in bcm2835_spi_set_cs, as it does
-+ * not get called for cs_gpio cases, so we need to do it here
-+ */
-+ if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
-+ cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
-
-- reinit_completion(&bs->done);
-+ /* set transmit buffers and length */
- bs->tx_buf = tfr->tx_buf;
- bs->rx_buf = tfr->rx_buf;
-- bs->len = tfr->len;
-+ bs->tx_len = tfr->len;
-+ bs->rx_len = tfr->len;
-
-- bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
-- /*
-- * Enable the HW block. This will immediately trigger a DONE (TX
-- * empty) interrupt, upon which we will fill the TX FIFO with the
-- * first TX bytes. Pre-filling the TX FIFO here to avoid the
-- * interrupt doesn't work:-(
-- */
-- bcm2835_wr(bs, BCM2835_SPI_CS, cs);
-+ /* calculate the estimated time in us the transfer runs */
-+ xfer_time_us = tfr->len
-+ * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
-+ * 1000000 / spi_used_hz;
-+
-+ /* for short requests run polling*/
-+ if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
-+ return bcm2835_spi_transfer_one_poll(master, spi, tfr,
-+ cs, xfer_time_us);
-
-- return 0;
-+ return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
- }
-
--static int bcm2835_spi_finish_transfer(struct spi_device *spi,
-- struct spi_transfer *tfr, bool cs_change)
-+static void bcm2835_spi_handle_err(struct spi_master *master,
-+ struct spi_message *msg)
- {
-- struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
-- u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
--
-- /* Drain RX FIFO */
-- while (cs & BCM2835_SPI_CS_RXD) {
-- bcm2835_rd_fifo(bs, 1);
-- cs = bcm2835_rd(bs, BCM2835_SPI_CS);
-- }
--
-- if (tfr->delay_usecs)
-- udelay(tfr->delay_usecs);
--
-- if (cs_change)
-- /* Clear TA flag */
-- bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
--
-- return 0;
-+ bcm2835_spi_reset_hw(master);
- }
-
--static int bcm2835_spi_transfer_one(struct spi_master *master,
-- struct spi_message *mesg)
-+static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
- {
-- struct bcm2835_spi *bs = spi_master_get_devdata(master);
-- struct spi_transfer *tfr;
-- struct spi_device *spi = mesg->spi;
-- int err = 0;
-- unsigned int timeout;
-- bool cs_change;
--
-- list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
-- err = bcm2835_spi_start_transfer(spi, tfr);
-- if (err)
-- goto out;
--
-- timeout = wait_for_completion_timeout(&bs->done,
-- msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS));
-- if (!timeout) {
-- err = -ETIMEDOUT;
-- goto out;
-- }
-+ /*
-+ * we can assume that we are "native" as per spi_set_cs
-+ * calling us ONLY when cs_gpio is not set
-+ * we can also assume that we are CS < 3 as per bcm2835_spi_setup
-+ * we would not get called because of error handling there.
-+ * the level passed is the electrical level not enabled/disabled
-+ * so it has to get translated back to enable/disable
-+ * see spi_set_cs in spi.c for the implementation
-+ */
-
-- cs_change = tfr->cs_change ||
-- list_is_last(&tfr->transfer_list, &mesg->transfers);
-+ struct spi_master *master = spi->master;
-+ struct bcm2835_spi *bs = spi_master_get_devdata(master);
-+ u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
-+ bool enable;
-
-- err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
-- if (err)
-- goto out;
-+ /* calculate the enable flag from the passed gpio_level */
-+ enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
-
-- mesg->actual_length += (tfr->len - bs->len);
-+ /* set flags for "reverse" polarity in the registers */
-+ if (spi->mode & SPI_CS_HIGH) {
-+ /* set the correct CS-bits */
-+ cs |= BCM2835_SPI_CS_CSPOL;
-+ cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
-+ } else {
-+ /* clean the CS-bits */
-+ cs &= ~BCM2835_SPI_CS_CSPOL;
-+ cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
-+ }
-+
-+ /* select the correct chip_select depending on disabled/enabled */
-+ if (enable) {
-+ /* set cs correctly */
-+ if (spi->mode & SPI_NO_CS) {
-+ /* use the "undefined" chip-select */
-+ cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
-+ } else {
-+ /* set the chip select */
-+ cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
-+ cs |= spi->chip_select;
-+ }
-+ } else {
-+ /* disable CSPOL which puts HW-CS into deselected state */
-+ cs &= ~BCM2835_SPI_CS_CSPOL;
-+ /* use the "undefined" chip-select as precaution */
-+ cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
- }
-
--out:
-- /* Clear FIFOs, and disable the HW block */
-- bcm2835_wr(bs, BCM2835_SPI_CS,
-- BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
-- mesg->status = err;
-- spi_finalize_current_message(master);
-+ /* finally set the calculated flags in SPI_CS */
-+ bcm2835_wr(bs, BCM2835_SPI_CS, cs);
-+}
-+
-+static int chip_match_name(struct gpio_chip *chip, void *data)
-+{
-+ return !strcmp(chip->label, data);
-+}
-+
-+static int bcm2835_spi_setup(struct spi_device *spi)
-+{
-+ int err;
-+ struct gpio_chip *chip;
-+ /*
-+ * sanity checking the native-chipselects
-+ */
-+ if (spi->mode & SPI_NO_CS)
-+ return 0;
-+ if (gpio_is_valid(spi->cs_gpio))
-+ return 0;
-+ if (spi->chip_select > 1) {
-+ /* error in the case of native CS requested with CS > 1
-+ * officially there is a CS2, but it is not documented
-+ * which GPIO is connected with that...
-+ */
-+ dev_err(&spi->dev,
-+ "setup: only two native chip-selects are supported\n");
-+ return -EINVAL;
-+ }
-+ /* now translate native cs to GPIO */
-+
-+ /* get the gpio chip for the base */
-+ chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
-+ if (!chip)
-+ return 0;
-+
-+ /* and calculate the real CS */
-+ spi->cs_gpio = chip->base + 8 - spi->chip_select;
-+
-+ /* and set up the "mode" and level */
-+ dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
-+ spi->chip_select, spi->cs_gpio);
-+
-+ /* set up GPIO as output and pull to the correct level */
-+ err = gpio_direction_output(spi->cs_gpio,
-+ (spi->mode & SPI_CS_HIGH) ? 0 : 1);
-+ if (err) {
-+ dev_err(&spi->dev,
-+ "could not set CS%i gpio %i as output: %i",
-+ spi->chip_select, spi->cs_gpio, err);
-+ return err;
-+ }
-+ /* the implementation of pinctrl-bcm2835 currently does not
-+ * set the GPIO value when using gpio_direction_output
-+ * so we are setting it here explicitly
-+ */
-+ gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
-
- return 0;
- }
-@@ -316,13 +429,14 @@
- master->mode_bits = BCM2835_SPI_MODE_BITS;
- master->bits_per_word_mask = SPI_BPW_MASK(8);
- master->num_chipselect = 3;
-- master->transfer_one_message = bcm2835_spi_transfer_one;
-+ master->setup = bcm2835_spi_setup;
-+ master->set_cs = bcm2835_spi_set_cs;
-+ master->transfer_one = bcm2835_spi_transfer_one;
-+ //master->handle_err = bcm2835_spi_handle_err;
- master->dev.of_node = pdev->dev.of_node;
-
- bs = spi_master_get_devdata(master);
-
-- init_completion(&bs->done);
--
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- bs->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(bs->regs)) {
-@@ -347,13 +461,13 @@
- clk_prepare_enable(bs->clk);
-
- err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
-- dev_name(&pdev->dev), master);
-+ dev_name(&pdev->dev), master);
- if (err) {
- dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
- goto out_clk_disable;
- }
-
-- /* initialise the hardware */
-+ /* initialise the hardware with the default polarities */
- bcm2835_wr(bs, BCM2835_SPI_CS,
- BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
-
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_agm1264k-fl.c linux-rpi/drivers/staging/fbtft/fb_agm1264k-fl.c
---- linux-3.18.14/drivers/staging/fbtft/fb_agm1264k-fl.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_agm1264k-fl.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,462 @@
-+/*
-+ * FB driver for Two KS0108 LCD controllers in AGM1264K-FL display
-+ *
-+ * Copyright (C) 2014 ololoshka2871
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+
-+#include "fbtft.h"
-+
-+/* Uncomment text line to use negative image on display */
-+/*#define NEGATIVE*/
-+
-+#define WHITE 0xff
-+#define BLACK 0
-+
-+#define DRVNAME "fb_agm1264k-fl"
-+#define WIDTH 64
-+#define HEIGHT 64
-+#define TOTALWIDTH (WIDTH * 2) /* because 2 x ks0108 in one display */
-+#define FPS 20
-+
-+#define EPIN gpio.wr
-+#define RS gpio.dc
-+#define RW gpio.aux[2]
-+#define CS0 gpio.aux[0]
-+#define CS1 gpio.aux[1]
-+
-+
-+/* diffusing error (“Floyd-Steinberg”) */
-+#define DIFFUSING_MATRIX_WIDTH 2
-+#define DIFFUSING_MATRIX_HEIGHT 2
-+
-+static const signed char
-+diffusing_matrix[DIFFUSING_MATRIX_WIDTH][DIFFUSING_MATRIX_HEIGHT] = {
-+ {-1, 3},
-+ {3, 2},
-+};
-+
-+static const unsigned char gamma_correction_table[] = {
-+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
-+1, 1, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6,
-+6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 11, 12, 12, 13,
-+13, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 21,
-+22, 22, 23, 23, 24, 25, 25, 26, 26, 27, 28, 28, 29, 30, 30, 31, 32,
-+33, 33, 34, 35, 35, 36, 37, 38, 39, 39, 40, 41, 42, 43, 43, 44, 45,
-+46, 47, 48, 49, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
-+62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 73, 74, 75, 76, 77, 78, 79, 81,
-+82, 83, 84, 85, 87, 88, 89, 90, 91, 93, 94, 95, 97, 98, 99, 100, 102,
-+103, 105, 106, 107, 109, 110, 111, 113, 114, 116, 117, 119, 120, 121,
-+123, 124, 126, 127, 129, 130, 132, 133, 135, 137, 138, 140, 141, 143,
-+145, 146, 148, 149, 151, 153, 154, 156, 158, 159, 161, 163, 165, 166,
-+168, 170, 172, 173, 175, 177, 179, 181, 182, 184, 186, 188, 190, 192,
-+194, 196, 197, 199, 201, 203, 205, 207, 209, 211, 213, 215, 217, 219,
-+221, 223, 225, 227, 229, 231, 234, 236, 238, 240, 242, 244, 246, 248,
-+251, 253, 255
-+};
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ u8 i;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ for (i = 0; i < 2; ++i) {
-+ write_reg(par, i, 0x3f); /* display on */
-+ write_reg(par, i, 0x40); /* set x to 0 */
-+ write_reg(par, i, 0xb0); /* set page to 0 */
-+ write_reg(par, i, 0xc0); /* set start line to 0 */
-+ }
-+
-+ return 0;
-+}
-+
-+static void reset(struct fbtft_par *par)
-+{
-+ if (par->gpio.reset == -1)
-+ return;
-+
-+ fbtft_dev_dbg(DEBUG_RESET, par, par->info->device, "%s()\n", __func__);
-+
-+ gpio_set_value(par->gpio.reset, 0);
-+ udelay(20);
-+ gpio_set_value(par->gpio.reset, 1);
-+ mdelay(120);
-+}
-+
-+/* Check if all necessary GPIOS defined */
-+static int verify_gpios(struct fbtft_par *par)
-+{
-+ int i;
-+
-+ fbtft_dev_dbg(DEBUG_VERIFY_GPIOS, par, par->info->device,
-+ "%s()\n", __func__);
-+
-+ if (par->EPIN < 0) {
-+ dev_err(par->info->device,
-+ "Missing info about 'wr' (aka E) gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ for (i = 0; i < 8; ++i) {
-+ if (par->gpio.db[i] < 0) {
-+ dev_err(par->info->device,
-+ "Missing info about 'db[%i]' gpio. Aborting.\n",
-+ i);
-+ return -EINVAL;
-+ }
-+ }
-+ if (par->CS0 < 0) {
-+ dev_err(par->info->device,
-+ "Missing info about 'cs0' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ if (par->CS1 < 0) {
-+ dev_err(par->info->device,
-+ "Missing info about 'cs1' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ if (par->RW < 0) {
-+ dev_err(par->info->device,
-+ "Missing info about 'rw' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static unsigned long
-+request_gpios_match(struct fbtft_par *par, const struct fbtft_gpio *gpio)
-+{
-+ fbtft_dev_dbg(DEBUG_REQUEST_GPIOS_MATCH, par, par->info->device,
-+ "%s('%s')\n", __func__, gpio->name);
-+
-+ if (strcasecmp(gpio->name, "wr") == 0) {
-+ /* left ks0108 E pin */
-+ par->EPIN = gpio->gpio;
-+ return GPIOF_OUT_INIT_LOW;
-+ } else if (strcasecmp(gpio->name, "cs0") == 0) {
-+ /* left ks0108 controller pin */
-+ par->CS0 = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ } else if (strcasecmp(gpio->name, "cs1") == 0) {
-+ /* right ks0108 controller pin */
-+ par->CS1 = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ }
-+
-+ /* if write (rw = 0) e(1->0) perform write */
-+ /* if read (rw = 1) e(0->1) set data on D0-7*/
-+ else if (strcasecmp(gpio->name, "rw") == 0) {
-+ par->RW = gpio->gpio;
-+ return GPIOF_OUT_INIT_LOW;
-+ }
-+
-+ return FBTFT_GPIO_NO_MATCH;
-+}
-+
-+/* This function oses to enter commands
-+ * first byte - destination controller 0 or 1
-+ * folowing - commands
-+ */
-+static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
-+{
-+ va_list args;
-+ int i, ret;
-+ u8 *buf = (u8 *)par->buf;
-+
-+ if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
-+ va_start(args, len);
-+ for (i = 0; i < len; i++)
-+ buf[i] = (u8)va_arg(args, unsigned int);
-+
-+ va_end(args);
-+ fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par,
-+ par->info->device, u8, buf, len, "%s: ", __func__);
-+ }
-+
-+ va_start(args, len);
-+
-+ *buf = (u8)va_arg(args, unsigned int);
-+
-+ if (*buf > 1) {
-+ va_end(args);
-+ dev_err(par->info->device, "%s: Incorrect chip sellect request (%d)\n",
-+ __func__, *buf);
-+ return;
-+ }
-+
-+ /* select chip */
-+ if (*buf) {
-+ /* cs1 */
-+ gpio_set_value(par->CS0, 1);
-+ gpio_set_value(par->CS1, 0);
-+ } else {
-+ /* cs0 */
-+ gpio_set_value(par->CS0, 0);
-+ gpio_set_value(par->CS1, 1);
-+ }
-+
-+ gpio_set_value(par->RS, 0); /* RS->0 (command mode) */
-+ len--;
-+
-+ if (len) {
-+ i = len;
-+ while (i--)
-+ *buf++ = (u8)va_arg(args, unsigned int);
-+ ret = par->fbtftops.write(par, par->buf, len * (sizeof(u8)));
-+ if (ret < 0) {
-+ va_end(args);
-+ dev_err(par->info->device, "%s: write() failed and returned %d\n",
-+ __func__, ret);
-+ return;
-+ }
-+ }
-+
-+ va_end(args);
-+}
-+
-+static struct
-+{
-+ int xs, ys_page, xe, ye_page;
-+} addr_win;
-+
-+/* save display writing zone */
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ addr_win.xs = xs;
-+ addr_win.ys_page = ys / 8;
-+ addr_win.xe = xe;
-+ addr_win.ye_page = ye / 8;
-+
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys_page=%d, xe=%d, ye_page=%d)\n", __func__,
-+ addr_win.xs, addr_win.ys_page, addr_win.xe, addr_win.ye_page);
-+}
-+
-+static void
-+construct_line_bitmap(struct fbtft_par *par, u8 *dest, signed short *src,
-+ int xs, int xe, int y)
-+{
-+ int x, i;
-+
-+ for (x = xs; x < xe; ++x) {
-+ u8 res = 0;
-+
-+ for (i = 0; i < 8; i++)
-+ if (src[(y * 8 + i) * par->info->var.xres + x])
-+ res |= 1 << i;
-+#ifdef NEGATIVE
-+ *dest++ = res;
-+#else
-+ *dest++ = ~res;
-+#endif
-+ }
-+}
-+
-+static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16 = (u16 *)par->info->screen_base;
-+ u8 *buf = par->txbuf.buf;
-+ int x, y;
-+ int ret = 0;
-+
-+ /* buffer to convert RGB565 -> grayscale16 -> Ditherd image 1bpp */
-+ signed short *convert_buf = kmalloc(par->info->var.xres *
-+ par->info->var.yres * sizeof(signed short), GFP_NOIO);
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ /* converting to grayscale16 */
-+ for (x = 0; x < par->info->var.xres; ++x)
-+ for (y = 0; y < par->info->var.yres; ++y) {
-+ u16 pixel = vmem16[y * par->info->var.xres + x];
-+ u16 b = pixel & 0x1f;
-+ u16 g = (pixel & (0x3f << 5)) >> 5;
-+ u16 r = (pixel & (0x1f << (5 + 6))) >> (5 + 6);
-+
-+ pixel = (299 * r + 587 * g + 114 * b) / 200;
-+ if (pixel > 255)
-+ pixel = 255;
-+
-+ /* gamma-correction by table */
-+ convert_buf[y * par->info->var.xres + x] =
-+ (signed short)gamma_correction_table[pixel];
-+ }
-+
-+ /* Image Dithering */
-+ for (x = 0; x < par->info->var.xres; ++x)
-+ for (y = 0; y < par->info->var.yres; ++y) {
-+ signed short pixel =
-+ convert_buf[y * par->info->var.xres + x];
-+ signed short error_b = pixel - BLACK;
-+ signed short error_w = pixel - WHITE;
-+ signed short error;
-+ u16 i, j;
-+
-+ /* what color close? */
-+ if (abs(error_b) >= abs(error_w)) {
-+ /* white */
-+ error = error_w;
-+ pixel = 0xff;
-+ } else {
-+ /* black */
-+ error = error_b;
-+ pixel = 0;
-+ }
-+
-+ error /= 8;
-+
-+ /* diffusion matrix row */
-+ for (i = 0; i < DIFFUSING_MATRIX_WIDTH; ++i)
-+ /* diffusion matrix column */
-+ for (j = 0; j < DIFFUSING_MATRIX_HEIGHT; ++j) {
-+ signed short *write_pos;
-+ signed char coeff;
-+
-+ /* skip pixels out of zone */
-+ if (x + i < 0 ||
-+ x + i >= par->info->var.xres
-+ || y + j >= par->info->var.yres)
-+ continue;
-+ write_pos = &convert_buf[
-+ (y + j) * par->info->var.xres +
-+ x + i];
-+ coeff = diffusing_matrix[i][j];
-+ if (coeff == -1)
-+ /* pixel itself */
-+ *write_pos = pixel;
-+ else {
-+ signed short p = *write_pos +
-+ error * coeff;
-+
-+ if (p > WHITE)
-+ p = WHITE;
-+ if (p < BLACK)
-+ p = BLACK;
-+ *write_pos = p;
-+ }
-+ }
-+ }
-+
-+ /* 1 string = 2 pages */
-+ for (y = addr_win.ys_page; y <= addr_win.ye_page; ++y) {
-+ /* left half of display */
-+ if (addr_win.xs < par->info->var.xres / 2) {
-+ construct_line_bitmap(par, buf, convert_buf,
-+ addr_win.xs, par->info->var.xres / 2, y);
-+
-+ len = par->info->var.xres / 2 - addr_win.xs;
-+
-+ /* select left side (sc0)
-+ * set addr
-+ */
-+ write_reg(par, 0x00, (1 << 6) | (u8)addr_win.xs);
-+ write_reg(par, 0x00, (0x17 << 3) | (u8)y);
-+
-+ /* write bitmap */
-+ gpio_set_value(par->RS, 1); /* RS->1 (data mode) */
-+ ret = par->fbtftops.write(par, buf, len);
-+ if (ret < 0)
-+ dev_err(par->info->device,
-+ "%s: write failed and returned: %d\n",
-+ __func__, ret);
-+ }
-+ /* right half of display */
-+ if (addr_win.xe >= par->info->var.xres / 2) {
-+ construct_line_bitmap(par, buf,
-+ convert_buf, par->info->var.xres / 2,
-+ addr_win.xe + 1, y);
-+
-+ len = addr_win.xe + 1 - par->info->var.xres / 2;
-+
-+ /* select right side (sc1)
-+ * set addr
-+ */
-+ write_reg(par, 0x01, (1 << 6));
-+ write_reg(par, 0x01, (0x17 << 3) | (u8)y);
-+
-+ /* write bitmap */
-+ gpio_set_value(par->RS, 1); /* RS->1 (data mode) */
-+ par->fbtftops.write(par, buf, len);
-+ if (ret < 0)
-+ dev_err(par->info->device,
-+ "%s: write failed and returned: %d\n",
-+ __func__, ret);
-+ }
-+ }
-+ kfree(convert_buf);
-+
-+ gpio_set_value(par->CS0, 1);
-+ gpio_set_value(par->CS1, 1);
-+
-+ return ret;
-+}
-+
-+static int write(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ gpio_set_value(par->RW, 0); /* set write mode */
-+
-+
-+ while (len--) {
-+ u8 i, data;
-+
-+ data = *(u8 *) buf++;
-+
-+ /* set data bus */
-+ for (i = 0; i < 8; ++i)
-+ gpio_set_value(par->gpio.db[i], data & (1 << i));
-+ /* set E */
-+ gpio_set_value(par->EPIN, 1);
-+ udelay(5);
-+ /* unset E - write */
-+ gpio_set_value(par->EPIN, 0);
-+ udelay(1);
-+ }
-+
-+ return 0;
-+}
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = TOTALWIDTH,
-+ .height = HEIGHT,
-+ .fps = FPS,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .verify_gpios = verify_gpios,
-+ .request_gpios_match = request_gpios_match,
-+ .reset = reset,
-+ .write = write,
-+ .write_register = write_reg8_bus8,
-+ .write_vmem = write_vmem,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "displaytronic,fb_agm1264k-fl", &display);
-+
-+MODULE_ALIAS("platform:" DRVNAME);
-+
-+MODULE_DESCRIPTION("Two KS0108 LCD controllers in AGM1264K-FL display");
-+MODULE_AUTHOR("ololoshka2871");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_bd663474.c linux-rpi/drivers/staging/fbtft/fb_bd663474.c
---- linux-3.18.14/drivers/staging/fbtft/fb_bd663474.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_bd663474.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,193 @@
-+/*
-+ * FB driver for the uPD161704 LCD Controller
-+ *
-+ * Copyright (C) 2014 Seong-Woo Kim
-+ *
-+ * Based on fb_ili9325.c by Noralf Tronnes
-+ * Based on ili9325.c by Jeroen Domburg
-+ * Init code from UTFT library by Henning Karlsen
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_bd663474"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define BPP 16
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ if (par->gpio.cs != -1)
-+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */
-+
-+ par->fbtftops.reset(par);
-+
-+ /* Initialization sequence from Lib_UTFT */
-+
-+ /* oscillator start */
-+ write_reg(par, 0x000,0x0001); /*oscillator 0: stop, 1: operation */
-+ mdelay(10);
-+
-+ /* Power settings */
-+ write_reg(par, 0x100, 0x0000 ); /* power supply setup */
-+ write_reg(par, 0x101, 0x0000 );
-+ write_reg(par, 0x102, 0x3110 );
-+ write_reg(par, 0x103, 0xe200 );
-+ write_reg(par, 0x110, 0x009d );
-+ write_reg(par, 0x111, 0x0022 );
-+ write_reg(par, 0x100, 0x0120 );
-+ mdelay( 20 );
-+
-+ write_reg(par, 0x100, 0x3120 );
-+ mdelay( 80 );
-+ /* Display control */
-+ write_reg(par, 0x001, 0x0100 );
-+ write_reg(par, 0x002, 0x0000 );
-+ write_reg(par, 0x003, 0x1230 );
-+ write_reg(par, 0x006, 0x0000 );
-+ write_reg(par, 0x007, 0x0101 );
-+ write_reg(par, 0x008, 0x0808 );
-+ write_reg(par, 0x009, 0x0000 );
-+ write_reg(par, 0x00b, 0x0000 );
-+ write_reg(par, 0x00c, 0x0000 );
-+ write_reg(par, 0x00d, 0x0018 );
-+ /* LTPS control settings */
-+ write_reg(par, 0x012, 0x0000 );
-+ write_reg(par, 0x013, 0x0000 );
-+ write_reg(par, 0x018, 0x0000 );
-+ write_reg(par, 0x019, 0x0000 );
-+
-+ write_reg(par, 0x203, 0x0000 );
-+ write_reg(par, 0x204, 0x0000 );
-+
-+ write_reg(par, 0x210, 0x0000 );
-+ write_reg(par, 0x211, 0x00ef );
-+ write_reg(par, 0x212, 0x0000 );
-+ write_reg(par, 0x213, 0x013f );
-+ write_reg(par, 0x214, 0x0000 );
-+ write_reg(par, 0x215, 0x0000 );
-+ write_reg(par, 0x216, 0x0000 );
-+ write_reg(par, 0x217, 0x0000 );
-+
-+ /* Gray scale settings */
-+ write_reg(par, 0x300, 0x5343);
-+ write_reg(par, 0x301, 0x1021);
-+ write_reg(par, 0x302, 0x0003);
-+ write_reg(par, 0x303, 0x0011);
-+ write_reg(par, 0x304, 0x050a);
-+ write_reg(par, 0x305, 0x4342);
-+ write_reg(par, 0x306, 0x1100);
-+ write_reg(par, 0x307, 0x0003);
-+ write_reg(par, 0x308, 0x1201);
-+ write_reg(par, 0x309, 0x050a);
-+
-+ /* RAM access settings */
-+ write_reg(par, 0x400, 0x4027 );
-+ write_reg(par, 0x401, 0x0000 );
-+ write_reg(par, 0x402, 0x0000 ); /* First screen drive position (1) */
-+ write_reg(par, 0x403, 0x013f ); /* First screen drive position (2) */
-+ write_reg(par, 0x404, 0x0000 );
-+
-+ write_reg(par, 0x200, 0x0000 );
-+ write_reg(par, 0x201, 0x0000 );
-+ write_reg(par, 0x100, 0x7120 );
-+ write_reg(par, 0x007, 0x0103 );
-+ mdelay( 10 );
-+ write_reg(par, 0x007, 0x0113 );
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+ switch (par->info->var.rotate) {
-+ /* R200h = Horizontal GRAM Start Address */
-+ /* R201h = Vertical GRAM Start Address */
-+ case 0:
-+ write_reg(par, 0x0200, xs);
-+ write_reg(par, 0x0201, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x0200, WIDTH - 1 - xs);
-+ write_reg(par, 0x0201, HEIGHT - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x0200, WIDTH - 1 - ys);
-+ write_reg(par, 0x0201, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x0200, ys);
-+ write_reg(par, 0x0201, HEIGHT - 1 - xs);
-+ break;
-+ }
-+ write_reg(par, 0x202); /* Write Data to GRAM */
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ /* AM: GRAM update direction */
-+ case 0:
-+ write_reg(par, 0x003, 0x1230);
-+ break;
-+ case 180:
-+ write_reg(par, 0x003, 0x1200);
-+ break;
-+ case 270:
-+ write_reg(par, 0x003, 0x1228);
-+ break;
-+ case 90:
-+ write_reg(par, 0x003, 0x1218);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct fbtft_display display = {
-+ .regwidth = 16,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .bpp = BPP,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:bd663474");
-+MODULE_ALIAS("platform:bd663474");
-+
-+MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
-+MODULE_AUTHOR("Seong-Woo Kim");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_hx8340bn.c linux-rpi/drivers/staging/fbtft/fb_hx8340bn.c
---- linux-3.18.14/drivers/staging/fbtft/fb_hx8340bn.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_hx8340bn.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,229 @@
-+/*
-+ * FB driver for the HX8340BN LCD Controller
-+ *
-+ * This display uses 9-bit SPI: Data/Command bit + 8 data bits
-+ * For platforms that doesn't support 9-bit, the driver is capable
-+ * of emulating this using 8-bit transfer.
-+ * This is done by transfering eight 9-bit words in 9 bytes.
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/vmalloc.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_hx8340bn"
-+#define WIDTH 176
-+#define HEIGHT 220
-+#define TXBUFLEN (4 * PAGE_SIZE)
-+#define DEFAULT_GAMMA "1 3 0E 5 0 2 09 0 6 1 7 1 0 2 2\n" \
-+ "3 3 17 8 4 7 05 7 6 0 3 1 6 0 0 "
-+
-+
-+static bool emulate;
-+module_param(emulate, bool, 0);
-+MODULE_PARM_DESC(emulate, "Force emulation in 9-bit mode");
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ /* BTL221722-276L startup sequence, from datasheet */
-+
-+ /* SETEXTCOM: Set extended command set (C1h)
-+ This command is used to set extended command set access enable.
-+ Enable: After command (C1h), must write: ffh,83h,40h */
-+ write_reg(par, 0xC1, 0xFF, 0x83, 0x40);
-+
-+ /* Sleep out
-+ This command turns off sleep mode.
-+ In this mode the DC/DC converter is enabled, Internal oscillator
-+ is started, and panel scanning is started. */
-+ write_reg(par, 0x11);
-+ mdelay(150);
-+
-+ /* Undoc'd register? */
-+ write_reg(par, 0xCA, 0x70, 0x00, 0xD9);
-+
-+ /* SETOSC: Set Internal Oscillator (B0h)
-+ This command is used to set internal oscillator related settings */
-+ /* OSC_EN: Enable internal oscillator */
-+ /* Internal oscillator frequency: 125% x 2.52MHz */
-+ write_reg(par, 0xB0, 0x01, 0x11);
-+
-+ /* Drive ability setting */
-+ write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06);
-+ mdelay(20);
-+
-+ /* SETPWCTR5: Set Power Control 5(B5h)
-+ This command is used to set VCOM Low and VCOM High Voltage */
-+ /* VCOMH 0110101 : 3.925 */
-+ /* VCOML 0100000 : -1.700 */
-+ /* 45h=69 VCOMH: "VMH" + 5d VCOML: "VMH" + 5d */
-+ write_reg(par, 0xB5, 0x35, 0x20, 0x45);
-+
-+ /* SETPWCTR4: Set Power Control 4(B4h)
-+ VRH[4:0]: Specify the VREG1 voltage adjusting.
-+ VREG1 voltage is for gamma voltage setting.
-+ BT[2:0]: Switch the output factor of step-up circuit 2
-+ for VGH and VGL voltage generation. */
-+ write_reg(par, 0xB4, 0x33, 0x25, 0x4C);
-+ mdelay(10);
-+
-+ /* Interface Pixel Format (3Ah)
-+ This command is used to define the format of RGB picture data,
-+ which is to be transfer via the system and RGB interface. */
-+ /* RGB interface: 16 Bit/Pixel */
-+ write_reg(par, 0x3A, 0x05);
-+
-+ /* Display on (29h)
-+ This command is used to recover from DISPLAY OFF mode.
-+ Output from the Frame Memory is enabled. */
-+ write_reg(par, 0x29);
-+ mdelay(10);
-+
-+ return 0;
-+}
-+
-+void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ write_reg(par, FBTFT_CASET, 0x00, xs, 0x00, xe);
-+ write_reg(par, FBTFT_RASET, 0x00, ys, 0x00, ye);
-+ write_reg(par, FBTFT_RAMWR);
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* MADCTL - Memory data access control */
-+ /* RGB/BGR can be set with H/W pin SRGB and MADCTL BGR bit */
-+#define MY (1 << 7)
-+#define MX (1 << 6)
-+#define MV (1 << 5)
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x36, (par->bgr << 3));
-+ break;
-+ case 270:
-+ write_reg(par, 0x36, MX | MV | (par->bgr << 3));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, MX | MY | (par->bgr << 3));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, MY | MV | (par->bgr << 3));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Gamma Curve selection, GC (only GC0 can be customized):
-+ 0 = 2.2, 1 = 1.8, 2 = 2.5, 3 = 1.0
-+ Gamma string format:
-+ OP0 OP1 CP0 CP1 CP2 CP3 CP4 MP0 MP1 MP2 MP3 MP4 MP5 CGM0 CGM1
-+ ON0 ON1 CN0 CN1 CN2 CN3 CN4 MN0 MN1 MN2 MN3 MN4 MN5 XXXX GC
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long mask[] = {
-+ 0b1111, 0b1111, 0b11111, 0b1111, 0b1111, 0b1111, 0b11111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111, 0b111, 0b11, 0b11,
-+ 0b1111, 0b1111, 0b11111, 0b1111, 0b1111, 0b1111, 0b11111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111, 0b111, 0b0, 0b0 };
-+ int i, j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < par->gamma.num_curves; i++)
-+ for (j = 0; j < par->gamma.num_values; j++)
-+ CURVE(i, j) &= mask[i * par->gamma.num_values + j];
-+
-+ write_reg(par, 0x26, 1 << CURVE(1, 14)); /* Gamma Set (26h) */
-+
-+ if (CURVE(1, 14))
-+ return 0; /* only GC0 can be customized */
-+
-+ write_reg(par, 0xC2,
-+ (CURVE(0, 8) << 4) | CURVE(0, 7),
-+ (CURVE(0, 10) << 4) | CURVE(0, 9),
-+ (CURVE(0, 12) << 4) | CURVE(0, 11),
-+ CURVE(0, 2),
-+ (CURVE(0, 4) << 4) | CURVE(0, 3),
-+ CURVE(0, 5),
-+ CURVE(0, 6),
-+ (CURVE(0, 1) << 4) | CURVE(0, 0),
-+ (CURVE(0, 14) << 2) | CURVE(0, 13));
-+
-+ write_reg(par, 0xC3,
-+ (CURVE(1, 8) << 4) | CURVE(1, 7),
-+ (CURVE(1, 10) << 4) | CURVE(1, 9),
-+ (CURVE(1, 12) << 4) | CURVE(1, 11),
-+ CURVE(1, 2),
-+ (CURVE(1, 4) << 4) | CURVE(1, 3),
-+ CURVE(1, 5),
-+ CURVE(1, 6),
-+ (CURVE(1, 1) << 4) | CURVE(1, 0));
-+
-+ mdelay(10);
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .txbuflen = TXBUFLEN,
-+ .gamma_num = 2,
-+ .gamma_len = 15,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8340bn", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:hx8340bn");
-+MODULE_ALIAS("platform:hx8340bn");
-+
-+MODULE_DESCRIPTION("FB driver for the HX8340BN LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_hx8347d.c linux-rpi/drivers/staging/fbtft/fb_hx8347d.c
---- linux-3.18.14/drivers/staging/fbtft/fb_hx8347d.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_hx8347d.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,181 @@
-+/*
-+ * FB driver for the HX8347D LCD Controller
-+ *
-+ * Copyright (C) 2013 Christian Vogelgsang
-+ *
-+ * Based on driver code found here: https://github.com/watterott/r61505u-Adapter
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_hx8347d"
-+#define WIDTH 320
-+#define HEIGHT 240
-+#define DEFAULT_GAMMA "0 0 0 0 0 0 0 0 0 0 0 0 0 0\n" \
-+ "0 0 0 0 0 0 0 0 0 0 0 0 0 0"
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ /* driving ability */
-+ write_reg(par, 0xEA, 0x00);
-+ write_reg(par, 0xEB, 0x20);
-+ write_reg(par, 0xEC, 0x0C);
-+ write_reg(par, 0xED, 0xC4);
-+ write_reg(par, 0xE8, 0x40);
-+ write_reg(par, 0xE9, 0x38);
-+ write_reg(par, 0xF1, 0x01);
-+ write_reg(par, 0xF2, 0x10);
-+ write_reg(par, 0x27, 0xA3);
-+
-+ /* power voltage */
-+ write_reg(par, 0x1B, 0x1B);
-+ write_reg(par, 0x1A, 0x01);
-+ write_reg(par, 0x24, 0x2F);
-+ write_reg(par, 0x25, 0x57);
-+
-+ /* VCOM offset */
-+ write_reg(par, 0x23, 0x8D); /* for flicker adjust */
-+
-+ /* power on */
-+ write_reg(par, 0x18, 0x36);
-+ write_reg(par, 0x19, 0x01); /* start osc */
-+ write_reg(par, 0x01, 0x00); /* wakeup */
-+ write_reg(par, 0x1F, 0x88);
-+ mdelay(5);
-+ write_reg(par, 0x1F, 0x80);
-+ mdelay(5);
-+ write_reg(par, 0x1F, 0x90);
-+ mdelay(5);
-+ write_reg(par, 0x1F, 0xD0);
-+ mdelay(5);
-+
-+ /* color selection */
-+ write_reg(par, 0x17, 0x05); /* 65k */
-+
-+ /*panel characteristic */
-+ write_reg(par, 0x36, 0x00);
-+
-+ /*display on */
-+ write_reg(par, 0x28, 0x38);
-+ mdelay(40);
-+ write_reg(par, 0x28, 0x3C);
-+
-+ /* orientation */
-+ write_reg(par, 0x16, 0x60 | (par->bgr << 3));
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ write_reg(par, 0x02, (xs >> 8) & 0xFF);
-+ write_reg(par, 0x03, xs & 0xFF);
-+ write_reg(par, 0x04, (xe >> 8) & 0xFF);
-+ write_reg(par, 0x05, xe & 0xFF);
-+ write_reg(par, 0x06, (ys >> 8) & 0xFF);
-+ write_reg(par, 0x07, ys & 0xFF);
-+ write_reg(par, 0x08, (ye >> 8) & 0xFF);
-+ write_reg(par, 0x09, ye & 0xFF);
-+ write_reg(par, 0x22);
-+}
-+
-+/*
-+ Gamma string format:
-+ VRP0 VRP1 VRP2 VRP3 VRP4 VRP5 PRP0 PRP1 PKP0 PKP1 PKP2 PKP3 PKP4 CGM
-+ VRN0 VRN1 VRN2 VRN3 VRN4 VRN5 PRN0 PRN1 PKN0 PKN1 PKN2 PKN3 PKN4 CGM
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long mask[] = {
-+ 0b111111, 0b111111, 0b111111, 0b111111, 0b111111, 0b111111,
-+ 0b1111111, 0b1111111,
-+ 0b11111, 0b11111, 0b11111, 0b11111, 0b11111,
-+ 0b1111};
-+ int i, j;
-+ int acc = 0;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < par->gamma.num_curves; i++)
-+ for (j = 0; j < par->gamma.num_values; j++) {
-+ acc += CURVE(i, j);
-+ CURVE(i, j) &= mask[j];
-+ }
-+
-+ if (acc == 0) /* skip if all values are zero */
-+ return 0;
-+
-+ for (i = 0; i < par->gamma.num_curves; i++) {
-+ write_reg(par, 0x40 + (i * 0x10), CURVE(i, 0));
-+ write_reg(par, 0x41 + (i * 0x10), CURVE(i, 1));
-+ write_reg(par, 0x42 + (i * 0x10), CURVE(i, 2));
-+ write_reg(par, 0x43 + (i * 0x10), CURVE(i, 3));
-+ write_reg(par, 0x44 + (i * 0x10), CURVE(i, 4));
-+ write_reg(par, 0x45 + (i * 0x10), CURVE(i, 5));
-+ write_reg(par, 0x46 + (i * 0x10), CURVE(i, 6));
-+ write_reg(par, 0x47 + (i * 0x10), CURVE(i, 7));
-+ write_reg(par, 0x48 + (i * 0x10), CURVE(i, 8));
-+ write_reg(par, 0x49 + (i * 0x10), CURVE(i, 9));
-+ write_reg(par, 0x4A + (i * 0x10), CURVE(i, 10));
-+ write_reg(par, 0x4B + (i * 0x10), CURVE(i, 11));
-+ write_reg(par, 0x4C + (i * 0x10), CURVE(i, 12));
-+ }
-+ write_reg(par, 0x5D, (CURVE(1, 0) << 4) | CURVE(0, 0));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .gamma_num = 2,
-+ .gamma_len = 14,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8347d", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:hx8347d");
-+MODULE_ALIAS("platform:hx8347d");
-+
-+MODULE_DESCRIPTION("FB driver for the HX8347D LCD Controller");
-+MODULE_AUTHOR("Christian Vogelgsang");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_hx8353d.c linux-rpi/drivers/staging/fbtft/fb_hx8353d.c
---- linux-3.18.14/drivers/staging/fbtft/fb_hx8353d.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_hx8353d.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,166 @@
-+/*
-+ * FB driver for the HX8353D LCD Controller
-+ *
-+ * Copyright (c) 2014 Petr Olivka
-+ * Copyright (c) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_hx8353d"
-+#define DEFAULT_GAMMA "50 77 40 08 BF 00 03 0F 00 01 73 00 72 03 B0 0F 08 00 0F"
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+ mdelay(150);
-+
-+ /* SETEXTC */
-+ write_reg(par, 0xB9, 0xFF, 0x83, 0x53);
-+
-+ /* RADJ */
-+ write_reg(par, 0xB0, 0x3C, 0x01);
-+
-+ /* VCOM */
-+ write_reg(par, 0xB6, 0x94, 0x6C, 0x50);
-+
-+ /* PWR */
-+ write_reg(par, 0xB1, 0x00, 0x01, 0x1B, 0x03, 0x01, 0x08, 0x77, 0x89);
-+
-+ /* COLMOD */
-+ write_reg(par, 0x3A, 0x05);
-+
-+ /* MEM ACCESS */
-+ write_reg(par, 0x36, 0xC0);
-+
-+ /* SLPOUT - Sleep out & booster on */
-+ write_reg(par, 0x11);
-+ mdelay(150);
-+
-+ /* DISPON - Display On */
-+ write_reg(par, 0x29);
-+
-+ /* RGBSET */
-+ write_reg(par, 0x2D,
-+ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
-+ 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62,
-+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
-+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
-+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
-+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
-+ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
-+ 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62);
-+
-+ return 0;
-+};
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* column address */
-+ write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff);
-+
-+ /* row adress */
-+ write_reg(par, 0x2b, ys >> 8, ys & 0xff, ye >> 8, ye & 0xff);
-+
-+ /* memory write */
-+ write_reg(par, 0x2c);
-+}
-+
-+#define my (1 << 7)
-+#define mx (1 << 6)
-+#define mv (1 << 5)
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* madctl - memory data access control
-+ rgb/bgr:
-+ 1. mode selection pin srgb
-+ rgb h/w pin for color filter setting: 0=rgb, 1=bgr
-+ 2. madctl rgb bit
-+ rgb-bgr order color filter panel: 0=rgb, 1=bgr */
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x36, mx | my | (par->bgr << 3));
-+ break;
-+ case 270:
-+ write_reg(par, 0x36, my | mv | (par->bgr << 3));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, (par->bgr << 3));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, mx | mv | (par->bgr << 3));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ gamma string format:
-+*/
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ write_reg(par, 0xE0,
-+ curves[0], curves[1], curves[2], curves[3],
-+ curves[4], curves[5], curves[6], curves[7],
-+ curves[8], curves[9], curves[10], curves[11],
-+ curves[12], curves[13], curves[14], curves[15],
-+ curves[16], curves[17], curves[18]);
-+
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = 128,
-+ .height = 160,
-+ .gamma_num = 1,
-+ .gamma_len = 19,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8353d", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:hx8353d");
-+MODULE_ALIAS("platform:hx8353d");
-+
-+MODULE_DESCRIPTION("FB driver for the HX8353D LCD Controller");
-+MODULE_AUTHOR("Petr Olivka");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ili9320.c linux-rpi/drivers/staging/fbtft/fb_ili9320.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ili9320.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ili9320.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,234 @@
-+/*
-+ * FB driver for the ILI9320 LCD Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ili9320"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \
-+ "07 08 4 7 5 1 2 0 7 7"
-+
-+
-+static unsigned read_devicecode(struct fbtft_par *par)
-+{
-+ int ret;
-+ u8 rxbuf[8] = {0, };
-+
-+ write_reg(par, 0x0000);
-+ ret = par->fbtftops.read(par, rxbuf, 4);
-+ return (rxbuf[2] << 8) | rxbuf[3];
-+}
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ unsigned devcode;
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ devcode = read_devicecode(par);
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n",
-+ devcode);
-+ if ((devcode != 0x0000) && (devcode != 0x9320))
-+ dev_warn(par->info->device,
-+ "Unrecognized Device code: 0x%04X (expected 0x9320)\n",
-+ devcode);
-+
-+ /* Initialization sequence from ILI9320 Application Notes */
-+
-+ /* *********** Start Initial Sequence ********* */
-+ write_reg(par, 0x00E5, 0x8000); /* Set the Vcore voltage and this setting is must. */
-+ write_reg(par, 0x0000, 0x0001); /* Start internal OSC. */
-+ write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */
-+ write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */
-+ write_reg(par, 0x0004, 0x0000); /* Resize register */
-+ write_reg(par, 0x0008, 0x0202); /* set the back and front porch */
-+ write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */
-+ write_reg(par, 0x000A, 0x0000); /* FMARK function */
-+ write_reg(par, 0x000C, 0x0000); /* RGB interface setting */
-+ write_reg(par, 0x000D, 0x0000); /* Frame marker Position */
-+ write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */
-+
-+ /* ***********Power On sequence *************** */
-+ write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-+ write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
-+ write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */
-+ write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */
-+ mdelay(200); /* Dis-charge capacitor power voltage */
-+ write_reg(par, 0x0010, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-+ write_reg(par, 0x0011, 0x0031); /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
-+ mdelay(50);
-+ write_reg(par, 0x0012, 0x0138); /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
-+ mdelay(50);
-+ write_reg(par, 0x0013, 0x1800); /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
-+ write_reg(par, 0x0029, 0x0008); /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
-+ mdelay(50);
-+ write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */
-+ write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */
-+
-+ /* ------------------ Set GRAM area --------------- */
-+ write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */
-+ write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */
-+ write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */
-+ write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */
-+ write_reg(par, 0x0060, 0x2700); /* Gate Scan Line */
-+ write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */
-+ write_reg(par, 0x006A, 0x0000); /* set scrolling line */
-+
-+ /* -------------- Partial Display Control --------- */
-+ write_reg(par, 0x0080, 0x0000);
-+ write_reg(par, 0x0081, 0x0000);
-+ write_reg(par, 0x0082, 0x0000);
-+ write_reg(par, 0x0083, 0x0000);
-+ write_reg(par, 0x0084, 0x0000);
-+ write_reg(par, 0x0085, 0x0000);
-+
-+ /* -------------- Panel Control ------------------- */
-+ write_reg(par, 0x0090, 0x0010);
-+ write_reg(par, 0x0092, 0x0000);
-+ write_reg(par, 0x0093, 0x0003);
-+ write_reg(par, 0x0095, 0x0110);
-+ write_reg(par, 0x0097, 0x0000);
-+ write_reg(par, 0x0098, 0x0000);
-+ write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ switch (par->info->var.rotate) {
-+ /* R20h = Horizontal GRAM Start Address */
-+ /* R21h = Vertical GRAM Start Address */
-+ case 0:
-+ write_reg(par, 0x0020, xs);
-+ write_reg(par, 0x0021, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x0020, WIDTH - 1 - xs);
-+ write_reg(par, 0x0021, HEIGHT - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x0020, WIDTH - 1 - ys);
-+ write_reg(par, 0x0021, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x0020, ys);
-+ write_reg(par, 0x0021, HEIGHT - 1 - xs);
-+ break;
-+ }
-+ write_reg(par, 0x0022); /* Write Data to GRAM */
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x3, (par->bgr << 12) | 0x30);
-+ break;
-+ case 270:
-+ write_reg(par, 0x3, (par->bgr << 12) | 0x28);
-+ break;
-+ case 180:
-+ write_reg(par, 0x3, (par->bgr << 12) | 0x00);
-+ break;
-+ case 90:
-+ write_reg(par, 0x3, (par->bgr << 12) | 0x18);
-+ break;
-+ }
-+ return 0;
-+}
-+
-+/*
-+ Gamma string format:
-+ VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
-+ VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long mask[] = {
-+ 0b11111, 0b11111, 0b111, 0b111, 0b111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111,
-+ 0b11111, 0b11111, 0b111, 0b111, 0b111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111 };
-+ int i, j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < 2; i++)
-+ for (j = 0; j < 10; j++)
-+ CURVE(i, j) &= mask[i*par->gamma.num_values + j];
-+
-+ write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
-+ write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
-+ write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
-+ write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
-+ write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
-+
-+ write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
-+ write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
-+ write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
-+ write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
-+ write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 16,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .gamma_num = 2,
-+ .gamma_len = 10,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ili9320");
-+MODULE_ALIAS("platform:ili9320");
-+
-+MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ili9325.c linux-rpi/drivers/staging/fbtft/fb_ili9325.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ili9325.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ili9325.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,291 @@
-+/*
-+ * FB driver for the ILI9325 LCD Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * Based on ili9325.c by Jeroen Domburg
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ili9325"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define BPP 16
-+#define FPS 20
-+#define DEFAULT_GAMMA "0F 00 7 2 0 0 6 5 4 1\n" \
-+ "04 16 2 7 6 3 2 1 7 7"
-+
-+
-+static unsigned bt = 6; /* VGL=Vci*4 , VGH=Vci*4 */
-+module_param(bt, uint, 0);
-+MODULE_PARM_DESC(bt, "Sets the factor used in the step-up circuits");
-+
-+static unsigned vc = 0b011; /* Vci1=Vci*0.80 */
-+module_param(vc, uint, 0);
-+MODULE_PARM_DESC(vc,
-+"Sets the ratio factor of Vci to generate the reference voltages Vci1");
-+
-+static unsigned vrh = 0b1101; /* VREG1OUT=Vci*1.85 */
-+module_param(vrh, uint, 0);
-+MODULE_PARM_DESC(vrh,
-+"Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT");
-+
-+static unsigned vdv = 0b10010; /* VCOMH amplitude=VREG1OUT*0.98 */
-+module_param(vdv, uint, 0);
-+MODULE_PARM_DESC(vdv,
-+"Select the factor of VREG1OUT to set the amplitude of Vcom");
-+
-+static unsigned vcm = 0b001010; /* VCOMH=VREG1OUT*0.735 */
-+module_param(vcm, uint, 0);
-+MODULE_PARM_DESC(vcm, "Set the internal VcomH voltage");
-+
-+
-+/*
-+Verify that this configuration is within the Voltage limits
-+
-+Display module configuration: Vcc = IOVcc = Vci = 3.3V
-+
-+ Voltages
-+----------
-+Vci = 3.3
-+Vci1 = Vci * 0.80 = 2.64
-+DDVDH = Vci1 * 2 = 5.28
-+VCL = -Vci1 = -2.64
-+VREG1OUT = Vci * 1.85 = 4.88
-+VCOMH = VREG1OUT * 0.735 = 3.59
-+VCOM amplitude = VREG1OUT * 0.98 = 4.79
-+VGH = Vci * 4 = 13.2
-+VGL = -Vci * 4 = -13.2
-+
-+ Limits
-+--------
-+Power supplies
-+1.65 < IOVcc < 3.30 => 1.65 < 3.3 < 3.30
-+2.40 < Vcc < 3.30 => 2.40 < 3.3 < 3.30
-+2.50 < Vci < 3.30 => 2.50 < 3.3 < 3.30
-+
-+Source/VCOM power supply voltage
-+ 4.50 < DDVDH < 6.0 => 4.50 < 5.28 < 6.0
-+-3.0 < VCL < -2.0 => -3.0 < -2.64 < -2.0
-+VCI - VCL < 6.0 => 5.94 < 6.0
-+
-+Gate driver output voltage
-+ 10 < VGH < 20 => 10 < 13.2 < 20
-+-15 < VGL < -5 => -15 < -13.2 < -5
-+VGH - VGL < 32 => 26.4 < 32
-+
-+VCOM driver output voltage
-+VCOMH - VCOML < 6.0 => 4.79 < 6.0
-+*/
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ if (par->gpio.cs != -1)
-+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */
-+
-+ bt &= 0b111;
-+ vc &= 0b111;
-+ vrh &= 0b1111;
-+ vdv &= 0b11111;
-+ vcm &= 0b111111;
-+
-+ /* Initialization sequence from ILI9325 Application Notes */
-+
-+ /* ----------- Start Initial Sequence ----------- */
-+ write_reg(par, 0x00E3, 0x3008); /* Set internal timing */
-+ write_reg(par, 0x00E7, 0x0012); /* Set internal timing */
-+ write_reg(par, 0x00EF, 0x1231); /* Set internal timing */
-+ write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */
-+ write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */
-+ write_reg(par, 0x0004, 0x0000); /* Resize register */
-+ write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */
-+ write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */
-+ write_reg(par, 0x000A, 0x0000); /* FMARK function */
-+ write_reg(par, 0x000C, 0x0000); /* RGB interface setting */
-+ write_reg(par, 0x000D, 0x0000); /* Frame marker Position */
-+ write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */
-+
-+ /* ----------- Power On sequence ----------- */
-+ write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-+ write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
-+ write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */
-+ write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */
-+ mdelay(200); /* Dis-charge capacitor power voltage */
-+ write_reg(par, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-+ (1 << 12) | (bt << 8) | (1 << 7) | (0b001 << 4));
-+ write_reg(par, 0x0011, 0x220 | vc); /* DC1[2:0], DC0[2:0], VC[2:0] */
-+ mdelay(50); /* Delay 50ms */
-+ write_reg(par, 0x0012, vrh); /* Internal reference voltage= Vci; */
-+ mdelay(50); /* Delay 50ms */
-+ write_reg(par, 0x0013, vdv << 8); /* Set VDV[4:0] for VCOM amplitude */
-+ write_reg(par, 0x0029, vcm); /* Set VCM[5:0] for VCOMH */
-+ write_reg(par, 0x002B, 0x000C); /* Set Frame Rate */
-+ mdelay(50); /* Delay 50ms */
-+ write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */
-+ write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */
-+
-+ /*------------------ Set GRAM area --------------- */
-+ write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */
-+ write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */
-+ write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */
-+ write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */
-+ write_reg(par, 0x0060, 0xA700); /* Gate Scan Line */
-+ write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */
-+ write_reg(par, 0x006A, 0x0000); /* set scrolling line */
-+
-+ /*-------------- Partial Display Control --------- */
-+ write_reg(par, 0x0080, 0x0000);
-+ write_reg(par, 0x0081, 0x0000);
-+ write_reg(par, 0x0082, 0x0000);
-+ write_reg(par, 0x0083, 0x0000);
-+ write_reg(par, 0x0084, 0x0000);
-+ write_reg(par, 0x0085, 0x0000);
-+
-+ /*-------------- Panel Control ------------------- */
-+ write_reg(par, 0x0090, 0x0010);
-+ write_reg(par, 0x0092, 0x0600);
-+ write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+ switch (par->info->var.rotate) {
-+ /* R20h = Horizontal GRAM Start Address */
-+ /* R21h = Vertical GRAM Start Address */
-+ case 0:
-+ write_reg(par, 0x0020, xs);
-+ write_reg(par, 0x0021, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x0020, WIDTH - 1 - xs);
-+ write_reg(par, 0x0021, HEIGHT - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x0020, WIDTH - 1 - ys);
-+ write_reg(par, 0x0021, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x0020, ys);
-+ write_reg(par, 0x0021, HEIGHT - 1 - xs);
-+ break;
-+ }
-+ write_reg(par, 0x0022); /* Write Data to GRAM */
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ /* AM: GRAM update direction */
-+ case 0:
-+ write_reg(par, 0x03, 0x0030 | (par->bgr << 12));
-+ break;
-+ case 180:
-+ write_reg(par, 0x03, 0x0000 | (par->bgr << 12));
-+ break;
-+ case 270:
-+ write_reg(par, 0x03, 0x0028 | (par->bgr << 12));
-+ break;
-+ case 90:
-+ write_reg(par, 0x03, 0x0018 | (par->bgr << 12));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Gamma string format:
-+ VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
-+ VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long mask[] = {
-+ 0b11111, 0b11111, 0b111, 0b111, 0b111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111,
-+ 0b11111, 0b11111, 0b111, 0b111, 0b111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111 };
-+ int i, j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < 2; i++)
-+ for (j = 0; j < 10; j++)
-+ CURVE(i, j) &= mask[i*par->gamma.num_values + j];
-+
-+ write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
-+ write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
-+ write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
-+ write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
-+ write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
-+
-+ write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
-+ write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
-+ write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
-+ write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
-+ write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 16,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .bpp = BPP,
-+ .fps = FPS,
-+ .gamma_num = 2,
-+ .gamma_len = 10,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ili9325");
-+MODULE_ALIAS("platform:ili9325");
-+
-+MODULE_DESCRIPTION("FB driver for the ILI9325 LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ili9340.c linux-rpi/drivers/staging/fbtft/fb_ili9340.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ili9340.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ili9340.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,163 @@
-+/*
-+ * FB driver for the ILI9340 LCD Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ili9340"
-+#define WIDTH 240
-+#define HEIGHT 320
-+
-+
-+/* Init sequence taken from: Arduino Library for the Adafruit 2.2" display */
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ write_reg(par, 0xEF, 0x03, 0x80, 0x02);
-+ write_reg(par, 0xCF, 0x00 , 0XC1 , 0X30);
-+ write_reg(par, 0xED, 0x64 , 0x03 , 0X12 , 0X81);
-+ write_reg(par, 0xE8, 0x85 , 0x00 , 0x78);
-+ write_reg(par, 0xCB, 0x39 , 0x2C , 0x00 , 0x34 , 0x02);
-+ write_reg(par, 0xF7, 0x20);
-+ write_reg(par, 0xEA, 0x00 , 0x00);
-+
-+ /* Power Control 1 */
-+ write_reg(par, 0xC0, 0x23);
-+
-+ /* Power Control 2 */
-+ write_reg(par, 0xC1, 0x10);
-+
-+ /* VCOM Control 1 */
-+ write_reg(par, 0xC5, 0x3e, 0x28);
-+
-+ /* VCOM Control 2 */
-+ write_reg(par, 0xC7, 0x86);
-+
-+ /* COLMOD: Pixel Format Set */
-+ /* 16 bits/pixel */
-+ write_reg(par, 0x3A, 0x55);
-+
-+ /* Frame Rate Control */
-+ /* Division ratio = fosc, Frame Rate = 79Hz */
-+ write_reg(par, 0xB1, 0x00, 0x18);
-+
-+ /* Display Function Control */
-+ write_reg(par, 0xB6, 0x08, 0x82, 0x27);
-+
-+ /* Gamma Function Disable */
-+ write_reg(par, 0xF2, 0x00);
-+
-+ /* Gamma curve selected */
-+ write_reg(par, 0x26, 0x01);
-+
-+ /* Positive Gamma Correction */
-+ write_reg(par, 0xE0,
-+ 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, 0x4E, 0xF1,
-+ 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00);
-+
-+ /* Negative Gamma Correction */
-+ write_reg(par, 0xE1,
-+ 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1,
-+ 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F);
-+
-+ /* Sleep OUT */
-+ write_reg(par, 0x11);
-+
-+ mdelay(120);
-+
-+ /* Display ON */
-+ write_reg(par, 0x29);
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address */
-+ write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
-+
-+ /* Row adress */
-+ write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+#define ILI9340_MADCTL_MV 0x20
-+#define ILI9340_MADCTL_MX 0x40
-+#define ILI9340_MADCTL_MY 0x80
-+static int set_var(struct fbtft_par *par)
-+{
-+ u8 val;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ case 270:
-+ val = ILI9340_MADCTL_MV;
-+ break;
-+ case 180:
-+ val = ILI9340_MADCTL_MY;
-+ break;
-+ case 90:
-+ val = ILI9340_MADCTL_MV | ILI9340_MADCTL_MY | ILI9340_MADCTL_MX;
-+ break;
-+ default:
-+ val = ILI9340_MADCTL_MX;
-+ break;
-+ }
-+ /* Memory Access Control */
-+ write_reg(par, 0x36, val | (par->bgr << 3));
-+
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9340", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ili9340");
-+MODULE_ALIAS("platform:ili9340");
-+
-+MODULE_DESCRIPTION("FB driver for the ILI9340 LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ili9341.c linux-rpi/drivers/staging/fbtft/fb_ili9341.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ili9341.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ili9341.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,179 @@
-+/*
-+ * FB driver for the ILI9341 LCD display controller
-+ *
-+ * This display uses 9-bit SPI: Data/Command bit + 8 data bits
-+ * For platforms that doesn't support 9-bit, the driver is capable
-+ * of emulating this using 8-bit transfer.
-+ * This is done by transfering eight 9-bit words in 9 bytes.
-+ *
-+ * Copyright (C) 2013 Christian Vogelgsang
-+ * Based on adafruit22fb.c by Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ili9341"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define TXBUFLEN (4 * PAGE_SIZE)
-+#define DEFAULT_GAMMA "1F 1A 18 0A 0F 06 45 87 32 0A 07 02 07 05 00\n" \
-+ "00 25 27 05 10 09 3A 78 4D 05 18 0D 38 3A 1F"
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ /* startup sequence for MI0283QT-9A */
-+ write_reg(par, 0x01); /* software reset */
-+ mdelay(5);
-+ write_reg(par, 0x28); /* display off */
-+ /* --------------------------------------------------------- */
-+ write_reg(par, 0xCF, 0x00, 0x83, 0x30);
-+ write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81);
-+ write_reg(par, 0xE8, 0x85, 0x01, 0x79);
-+ write_reg(par, 0xCB, 0x39, 0X2C, 0x00, 0x34, 0x02);
-+ write_reg(par, 0xF7, 0x20);
-+ write_reg(par, 0xEA, 0x00, 0x00);
-+ /* ------------power control-------------------------------- */
-+ write_reg(par, 0xC0, 0x26);
-+ write_reg(par, 0xC1, 0x11);
-+ /* ------------VCOM --------- */
-+ write_reg(par, 0xC5, 0x35, 0x3E);
-+ write_reg(par, 0xC7, 0xBE);
-+ /* ------------memory access control------------------------ */
-+ write_reg(par, 0x3A, 0x55); /* 16bit pixel */
-+ /* ------------frame rate----------------------------------- */
-+ write_reg(par, 0xB1, 0x00, 0x1B);
-+ /* ------------Gamma---------------------------------------- */
-+ /* write_reg(par, 0xF2, 0x08); */ /* Gamma Function Disable */
-+ write_reg(par, 0x26, 0x01);
-+ /* ------------display-------------------------------------- */
-+ write_reg(par, 0xB7, 0x07); /* entry mode set */
-+ write_reg(par, 0xB6, 0x0A, 0x82, 0x27, 0x00);
-+ write_reg(par, 0x11); /* sleep out */
-+ mdelay(100);
-+ write_reg(par, 0x29); /* display on */
-+ mdelay(20);
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address set */
-+ write_reg(par, 0x2A,
-+ (xs >> 8) & 0xFF, xs & 0xFF, (xe >> 8) & 0xFF, xe & 0xFF);
-+
-+ /* Row adress set */
-+ write_reg(par, 0x2B,
-+ (ys >> 8) & 0xFF, ys & 0xFF, (ye >> 8) & 0xFF, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+#define MEM_Y (7) /* MY row address order */
-+#define MEM_X (6) /* MX column address order */
-+#define MEM_V (5) /* MV row / column exchange */
-+#define MEM_L (4) /* ML vertical refresh order */
-+#define MEM_H (2) /* MH horizontal refresh order */
-+#define MEM_BGR (3) /* RGB-BGR Order */
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x36, (1 << MEM_X) | (par->bgr << MEM_BGR));
-+ break;
-+ case 270:
-+ write_reg(par, 0x36,
-+ (1<<MEM_V) | (1 << MEM_L) | (par->bgr << MEM_BGR));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, (1 << MEM_Y) | (par->bgr << MEM_BGR));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, (1 << MEM_Y) | (1 << MEM_X) |
-+ (1 << MEM_V) | (par->bgr << MEM_BGR));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Gamma string format:
-+ Positive: Par1 Par2 [...] Par15
-+ Negative: Par1 Par2 [...] Par15
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ int i;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ for (i = 0; i < par->gamma.num_curves; i++)
-+ write_reg(par, 0xE0 + i,
-+ CURVE(i, 0), CURVE(i, 1), CURVE(i, 2),
-+ CURVE(i, 3), CURVE(i, 4), CURVE(i, 5),
-+ CURVE(i, 6), CURVE(i, 7), CURVE(i, 8),
-+ CURVE(i, 9), CURVE(i, 10), CURVE(i, 11),
-+ CURVE(i, 12), CURVE(i, 13), CURVE(i, 14));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .txbuflen = TXBUFLEN,
-+ .gamma_num = 2,
-+ .gamma_len = 15,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9341", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ili9341");
-+MODULE_ALIAS("platform:ili9341");
-+
-+MODULE_DESCRIPTION("FB driver for the ILI9341 LCD display controller");
-+MODULE_AUTHOR("Christian Vogelgsang");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ili9481.c linux-rpi/drivers/staging/fbtft/fb_ili9481.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ili9481.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ili9481.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,117 @@
-+/*
-+ * FB driver for the ILI9481 LCD Controller
-+ *
-+ * Copyright (c) 2014 Petr Olivka
-+ * Copyright (c) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ili9481"
-+#define WIDTH 320
-+#define HEIGHT 480
-+
-+static int default_init_sequence[] = {
-+
-+ /* SLP_OUT - Sleep out */
-+ -1, 0x11,
-+ -2, 50,
-+ /* Power setting */
-+ -1, 0xD0, 0x07, 0x42, 0x18,
-+ /* VCOM */
-+ -1, 0xD1, 0x00, 0x07, 0x10,
-+ /* Power setting for norm. mode */
-+ -1, 0xD2, 0x01, 0x02,
-+ /* Panel driving setting */
-+ -1, 0xC0, 0x10, 0x3B, 0x00, 0x02, 0x11,
-+ /* Frame rate & inv. */
-+ -1, 0xC5, 0x03,
-+ /* Pixel format */
-+ -1, 0x3A, 0x55,
-+ /* Gamma */
-+ -1, 0xC8, 0x00, 0x32, 0x36, 0x45, 0x06, 0x16,
-+ 0x37, 0x75, 0x77, 0x54, 0x0C, 0x00,
-+ /* DISP_ON */
-+ -1, 0x29,
-+ -3
-+};
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* column address */
-+ write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff);
-+
-+ /* row adress */
-+ write_reg(par, 0x2b, ys >> 8, ys & 0xff, ye >> 8, ye & 0xff);
-+
-+ /* memory write */
-+ write_reg(par, 0x2c);
-+}
-+
-+#define HFLIP 0x01
-+#define VFLIP 0x02
-+#define ROWxCOL 0x20
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ case 270:
-+ write_reg(par, 0x36, ROWxCOL | HFLIP | VFLIP | (par->bgr << 3));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, VFLIP | (par->bgr << 3));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, ROWxCOL | (par->bgr << 3));
-+ break;
-+ default:
-+ write_reg(par, 0x36, HFLIP | (par->bgr << 3));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .init_sequence = default_init_sequence,
-+ .fbtftops = {
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9481", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ili9481");
-+MODULE_ALIAS("platform:ili9481");
-+
-+MODULE_DESCRIPTION("FB driver for the ILI9481 LCD Controller");
-+MODULE_AUTHOR("Petr Olivka");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ili9486.c linux-rpi/drivers/staging/fbtft/fb_ili9486.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ili9486.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ili9486.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,121 @@
-+/*
-+ * FB driver for the ILI9486 LCD Controller
-+ *
-+ * Copyright (C) 2014 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ili9486"
-+#define WIDTH 320
-+#define HEIGHT 480
-+
-+
-+/* this init sequence matches PiScreen */
-+static int default_init_sequence[] = {
-+ /* Interface Mode Control */
-+ -1, 0xb0, 0x0,
-+ /* Sleep OUT */
-+ -1, 0x11,
-+ -2, 250,
-+ /* Interface Pixel Format */
-+ -1, 0x3A, 0x55,
-+ /* Power Control 3 */
-+ -1, 0xC2, 0x44,
-+ /* VCOM Control 1 */
-+ -1, 0xC5, 0x00, 0x00, 0x00, 0x00,
-+ /* PGAMCTRL(Positive Gamma Control) */
-+ -1, 0xE0, 0x0F, 0x1F, 0x1C, 0x0C, 0x0F, 0x08, 0x48, 0x98,
-+ 0x37, 0x0A, 0x13, 0x04, 0x11, 0x0D, 0x00,
-+ /* NGAMCTRL(Negative Gamma Control) */
-+ -1, 0xE1, 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
-+ 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00,
-+ /* Digital Gamma Control 1 */
-+ -1, 0xE2, 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
-+ 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00,
-+ /* Sleep OUT */
-+ -1, 0x11,
-+ /* Display ON */
-+ -1, 0x29,
-+ /* end marker */
-+ -3
-+};
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address */
-+ write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
-+
-+ /* Row adress */
-+ write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x36, 0x80 | (par->bgr << 3));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, 0x20 | (par->bgr << 3));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, 0x40 | (par->bgr << 3));
-+ break;
-+ case 270:
-+ write_reg(par, 0x36, 0xE0 | (par->bgr << 3));
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .init_sequence = default_init_sequence,
-+ .fbtftops = {
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9486", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ili9486");
-+MODULE_ALIAS("platform:ili9486");
-+
-+MODULE_DESCRIPTION("FB driver for the ILI9486 LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_pcd8544.c linux-rpi/drivers/staging/fbtft/fb_pcd8544.c
---- linux-3.18.14/drivers/staging/fbtft/fb_pcd8544.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_pcd8544.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,177 @@
-+/*
-+ * FB driver for the PCD8544 LCD Controller
-+ *
-+ * The display is monochrome and the video memory is RGB565.
-+ * Any pixel value except 0 turns the pixel on.
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_pcd8544"
-+#define WIDTH 84
-+#define HEIGHT 48
-+#define TXBUFLEN (84*6)
-+#define DEFAULT_GAMMA "40" /* gamma is used to control contrast in this driver */
-+
-+static unsigned tc;
-+module_param(tc, uint, 0);
-+MODULE_PARM_DESC(tc, "TC[1:0] Temperature coefficient: 0-3 (default: 0)");
-+
-+static unsigned bs = 4;
-+module_param(bs, uint, 0);
-+MODULE_PARM_DESC(bs, "BS[2:0] Bias voltage level: 0-7 (default: 4)");
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ /* Function set */
-+ write_reg(par, 0x21); /* 5:1 1
-+ 2:0 PD - Powerdown control: chip is active
-+ 1:0 V - Entry mode: horizontal addressing
-+ 0:1 H - Extended instruction set control: extended
-+ */
-+
-+ /* H=1 Temperature control */
-+ write_reg(par, 0x04 | (tc & 0x3)); /*
-+ 2:1 1
-+ 1:x TC1 - Temperature Coefficient: 0x10
-+ 0:x TC0
-+ */
-+
-+ /* H=1 Bias system */
-+ write_reg(par, 0x10 | (bs & 0x7)); /*
-+ 4:1 1
-+ 3:0 0
-+ 2:x BS2 - Bias System
-+ 1:x BS1
-+ 0:x BS0
-+ */
-+
-+ /* Function set */
-+ write_reg(par, 0x22); /* 5:1 1
-+ 2:0 PD - Powerdown control: chip is active
-+ 1:1 V - Entry mode: vertical addressing
-+ 0:0 H - Extended instruction set control: basic
-+ */
-+
-+ /* H=0 Display control */
-+ write_reg(par, 0x08 | 4); /*
-+ 3:1 1
-+ 2:1 D - DE: 10=normal mode
-+ 1:0 0
-+ 0:0 E
-+ */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* H=0 Set X address of RAM */
-+ write_reg(par, 0x80); /* 7:1 1
-+ 6-0: X[6:0] - 0x00
-+ */
-+
-+ /* H=0 Set Y address of RAM */
-+ write_reg(par, 0x40); /* 7:0 0
-+ 6:1 1
-+ 2-0: Y[2:0] - 0x0
-+ */
-+}
-+
-+static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16 = (u16 *)par->info->screen_base;
-+ u8 *buf = par->txbuf.buf;
-+ int x, y, i;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ for (x = 0; x < 84; x++) {
-+ for (y = 0; y < 6; y++) {
-+ *buf = 0x00;
-+ for (i = 0; i < 8; i++) {
-+ *buf |= (vmem16[(y*8+i)*84+x] ? 1 : 0) << i;
-+ }
-+ buf++;
-+ }
-+ }
-+
-+ /* Write data */
-+ gpio_set_value(par->gpio.dc, 1);
-+ ret = par->fbtftops.write(par, par->txbuf.buf, 6*84);
-+ if (ret < 0)
-+ dev_err(par->info->device, "%s: write failed and returned: %d\n", __func__, ret);
-+
-+ return ret;
-+}
-+
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ curves[0] &= 0x7F;
-+
-+ write_reg(par, 0x23); /* turn on extended instruction set */
-+ write_reg(par, 0x80 | curves[0]);
-+ write_reg(par, 0x22); /* turn off extended instruction set */
-+
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .txbuflen = TXBUFLEN,
-+ .gamma_num = 1,
-+ .gamma_len = 1,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .write_vmem = write_vmem,
-+ .set_gamma = set_gamma,
-+ },
-+ .backlight = 1,
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "philips,pdc8544", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("spi:pdc8544");
-+
-+MODULE_DESCRIPTION("FB driver for the PCD8544 LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ra8875.c linux-rpi/drivers/staging/fbtft/fb_ra8875.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ra8875.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ra8875.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,331 @@
-+/******************************************************************************
-+
-+ ProjectName: FBTFT driver ***** *****
-+ for the RA8875 LCD Controller * * ************
-+ * ** ** * *
-+ Copyright © by Pf@nne & NOTRO * * * * * **** *
-+ * * * * * * *
-+ Last modification by: * * * * **** *
-+ - Pf@nne (pf@nne-mail.de) * * ***** *
-+ * * * *******
-+ ***** * *
-+ Date : 10.06.2014 * *
-+ Version : V1.13 *****
-+ Revison : 5
-+
-+*******************************************************************************
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+
-+#include <linux/gpio.h>
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ra8875"
-+
-+static int write_spi(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ struct spi_transfer t = {
-+ .tx_buf = buf,
-+ .len = len,
-+ .speed_hz = 1000000,
-+ };
-+ struct spi_message m;
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ if (!par->spi) {
-+ dev_err(par->info->device,
-+ "%s: par->spi is unexpectedly NULL\n", __func__);
-+ return -1;
-+ }
-+
-+ spi_message_init(&m);
-+ if (par->txbuf.dma && buf == par->txbuf.buf) {
-+ t.tx_dma = par->txbuf.dma;
-+ m.is_dma_mapped = 1;
-+ }
-+ spi_message_add_tail(&t, &m);
-+ return spi_sync(par->spi, &m);
-+}
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ gpio_set_value(par->gpio.dc, 1);
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "%s()\n", __func__);
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "display size %dx%d\n", par->info->var.xres, par->info->var.yres);
-+
-+ par->fbtftops.reset(par);
-+
-+ if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
-+ /* PLL clock frequency */
-+ write_reg(par, 0x88 , 0x0A);
-+ write_reg(par, 0x89 , 0x02);
-+ mdelay(10);
-+ /* color deep / MCU Interface */
-+ write_reg(par, 0x10 , 0x0C);
-+ /* pixel clock period */
-+ write_reg(par, 0x04 , 0x03);
-+ mdelay(1);
-+ /* horizontal settings */
-+ write_reg(par, 0x14 , 0x27);
-+ write_reg(par, 0x15 , 0x00);
-+ write_reg(par, 0x16 , 0x05);
-+ write_reg(par, 0x17 , 0x04);
-+ write_reg(par, 0x18 , 0x03);
-+ /* vertical settings */
-+ write_reg(par, 0x19 , 0xEF);
-+ write_reg(par, 0x1A , 0x00);
-+ write_reg(par, 0x1B , 0x05);
-+ write_reg(par, 0x1C , 0x00);
-+ write_reg(par, 0x1D , 0x0E);
-+ write_reg(par, 0x1E , 0x00);
-+ write_reg(par, 0x1F , 0x02);
-+ } else if ((par->info->var.xres == 480) && (par->info->var.yres == 272)) {
-+ /* PLL clock frequency */
-+ write_reg(par, 0x88 , 0x0A);
-+ write_reg(par, 0x89 , 0x02);
-+ mdelay(10);
-+ /* color deep / MCU Interface */
-+ write_reg(par, 0x10 , 0x0C);
-+ /* pixel clock period */
-+ write_reg(par, 0x04 , 0x82);
-+ mdelay(1);
-+ /* horizontal settings */
-+ write_reg(par, 0x14 , 0x3B);
-+ write_reg(par, 0x15 , 0x00);
-+ write_reg(par, 0x16 , 0x01);
-+ write_reg(par, 0x17 , 0x00);
-+ write_reg(par, 0x18 , 0x05);
-+ /* vertical settings */
-+ write_reg(par, 0x19 , 0x0F);
-+ write_reg(par, 0x1A , 0x01);
-+ write_reg(par, 0x1B , 0x02);
-+ write_reg(par, 0x1C , 0x00);
-+ write_reg(par, 0x1D , 0x07);
-+ write_reg(par, 0x1E , 0x00);
-+ write_reg(par, 0x1F , 0x09);
-+ } else if ((par->info->var.xres == 640) && (par->info->var.yres == 480)) {
-+ /* PLL clock frequency */
-+ write_reg(par, 0x88 , 0x0B);
-+ write_reg(par, 0x89 , 0x02);
-+ mdelay(10);
-+ /* color deep / MCU Interface */
-+ write_reg(par, 0x10 , 0x0C);
-+ /* pixel clock period */
-+ write_reg(par, 0x04 , 0x01);
-+ mdelay(1);
-+ /* horizontal settings */
-+ write_reg(par, 0x14 , 0x4F);
-+ write_reg(par, 0x15 , 0x05);
-+ write_reg(par, 0x16 , 0x0F);
-+ write_reg(par, 0x17 , 0x01);
-+ write_reg(par, 0x18 , 0x00);
-+ /* vertical settings */
-+ write_reg(par, 0x19 , 0xDF);
-+ write_reg(par, 0x1A , 0x01);
-+ write_reg(par, 0x1B , 0x0A);
-+ write_reg(par, 0x1C , 0x00);
-+ write_reg(par, 0x1D , 0x0E);
-+ write_reg(par, 0x1E , 0x00);
-+ write_reg(par, 0x1F , 0x01);
-+ } else if ((par->info->var.xres == 800) && (par->info->var.yres == 480)) {
-+ /* PLL clock frequency */
-+ write_reg(par, 0x88 , 0x0B);
-+ write_reg(par, 0x89 , 0x02);
-+ mdelay(10);
-+ /* color deep / MCU Interface */
-+ write_reg(par, 0x10 , 0x0C);
-+ /* pixel clock period */
-+ write_reg(par, 0x04 , 0x81);
-+ mdelay(1);
-+ /* horizontal settings */
-+ write_reg(par, 0x14 , 0x63);
-+ write_reg(par, 0x15 , 0x03);
-+ write_reg(par, 0x16 , 0x03);
-+ write_reg(par, 0x17 , 0x02);
-+ write_reg(par, 0x18 , 0x00);
-+ /* vertical settings */
-+ write_reg(par, 0x19 , 0xDF);
-+ write_reg(par, 0x1A , 0x01);
-+ write_reg(par, 0x1B , 0x14);
-+ write_reg(par, 0x1C , 0x00);
-+ write_reg(par, 0x1D , 0x06);
-+ write_reg(par, 0x1E , 0x00);
-+ write_reg(par, 0x1F , 0x01);
-+ } else {
-+ dev_err(par->info->device, "display size is not supported!!");
-+ return -1;
-+ }
-+
-+ /* PWM clock */
-+ write_reg(par, 0x8a , 0x81);
-+ write_reg(par, 0x8b , 0xFF);
-+ mdelay(10);
-+
-+ /* Display ON */
-+ write_reg(par, 0x01 , 0x80);
-+ mdelay(10);
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Set_Active_Window */
-+ write_reg(par, 0x30 , xs & 0x00FF);
-+ write_reg(par, 0x31 , (xs & 0xFF00) >> 8);
-+ write_reg(par, 0x32 , ys & 0x00FF);
-+ write_reg(par, 0x33 , (ys & 0xFF00) >> 8);
-+ write_reg(par, 0x34 , (xs+xe) & 0x00FF);
-+ write_reg(par, 0x35 , ((xs+xe) & 0xFF00) >> 8);
-+ write_reg(par, 0x36 , (ys+ye) & 0x00FF);
-+ write_reg(par, 0x37 , ((ys+ye) & 0xFF00) >> 8);
-+
-+ /* Set_Memory_Write_Cursor */
-+ write_reg(par, 0x46, xs & 0xff);
-+ write_reg(par, 0x47, (xs >> 8) & 0x03);
-+ write_reg(par, 0x48, ys & 0xff);
-+ write_reg(par, 0x49, (ys >> 8) & 0x01);
-+
-+ write_reg(par, 0x02);
-+}
-+
-+static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
-+{
-+ va_list args;
-+ int i, ret;
-+ u8 *buf = (u8 *)par->buf;
-+
-+ /* slow down spi-speed for writing registers */
-+ par->fbtftops.write = write_spi;
-+
-+ if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
-+ va_start(args, len);
-+ for (i = 0; i < len; i++)
-+ buf[i] = (u8)va_arg(args, unsigned int);
-+ va_end(args);
-+ fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device,
-+ u8, buf, len, "%s: ", __func__);
-+ }
-+
-+ va_start(args, len);
-+ *buf++ = 0x80;
-+ *buf = (u8)va_arg(args, unsigned int);
-+ ret = par->fbtftops.write(par, par->buf, 2);
-+ if (ret < 0) {
-+ va_end(args);
-+ dev_err(par->info->device, "%s: write() failed and returned %dn",
-+ __func__, ret);
-+ return;
-+ }
-+ len--;
-+
-+ udelay(100);
-+
-+ if (len) {
-+ buf = (u8 *)par->buf;
-+ *buf++ = 0x00;
-+ i = len;
-+ while (i--)
-+ *buf++ = (u8)va_arg(args, unsigned int);
-+
-+ ret = par->fbtftops.write(par, par->buf, len + 1);
-+ if (ret < 0) {
-+ va_end(args);
-+ dev_err(par->info->device, "%s: write() failed and returned %dn",
-+ __func__, ret);
-+ return;
-+ }
-+ }
-+ va_end(args);
-+
-+ /* restore user spi-speed */
-+ par->fbtftops.write = fbtft_write_spi;
-+ udelay(100);
-+}
-+
-+static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16;
-+ u16 *txbuf16 = (u16 *)par->txbuf.buf;
-+ size_t remain;
-+ size_t to_copy;
-+ size_t tx_array_size;
-+ int i;
-+ int ret = 0;
-+ size_t startbyte_size = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
-+ __func__, offset, len);
-+
-+ remain = len / 2;
-+ vmem16 = (u16 *)(par->info->screen_base + offset);
-+ tx_array_size = par->txbuf.len / 2;
-+ txbuf16 = (u16 *)(par->txbuf.buf + 1);
-+ tx_array_size -= 2;
-+ *(u8 *)(par->txbuf.buf) = 0x00;
-+ startbyte_size = 1;
-+
-+ while (remain) {
-+ to_copy = remain > tx_array_size ? tx_array_size : remain;
-+ dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n",
-+ to_copy, remain - to_copy);
-+
-+ for (i = 0; i < to_copy; i++)
-+ txbuf16[i] = cpu_to_be16(vmem16[i]);
-+
-+ vmem16 = vmem16 + to_copy;
-+ ret = par->fbtftops.write(par, par->txbuf.buf,
-+ startbyte_size + to_copy * 2);
-+ if (ret < 0)
-+ return ret;
-+ remain -= to_copy;
-+ }
-+
-+ return ret;
-+}
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .write_register = write_reg8_bus8,
-+ .write_vmem = write_vmem16_bus8,
-+ .write = write_spi,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ra8875");
-+MODULE_ALIAS("platform:ra8875");
-+
-+MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller");
-+MODULE_AUTHOR("Pf@nne");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_s6d02a1.c linux-rpi/drivers/staging/fbtft/fb_s6d02a1.c
---- linux-3.18.14/drivers/staging/fbtft/fb_s6d02a1.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_s6d02a1.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,168 @@
-+/*
-+ * FB driver for the S6D02A1 LCD Controller
-+ *
-+ * Based on fb_st7735r.c by Noralf Tronnes
-+ * Init code from UTFT library by Henning Karlsen
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_s6d02a1"
-+
-+static int default_init_sequence[] = {
-+
-+ -1, 0xf0, 0x5a, 0x5a,
-+
-+ -1, 0xfc, 0x5a, 0x5a,
-+
-+ -1, 0xfa, 0x02, 0x1f, 0x00, 0x10, 0x22, 0x30, 0x38, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A, 0x3d, 0x02, 0x01,
-+
-+ -1, 0xfb, 0x21, 0x00, 0x02, 0x04, 0x07, 0x0a, 0x0b, 0x0c, 0x0c, 0x16, 0x1e, 0x30, 0x3f, 0x01, 0x02,
-+
-+ /* power setting sequence */
-+ -1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x01, 0x01, 0x00, 0x1f, 0x1f,
-+
-+ -1, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
-+
-+ -1, 0xf5, 0x00, 0x70, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x66, 0x06,
-+
-+ -1, 0xf6, 0x02, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x06, 0x01, 0x00,
-+
-+ -1, 0xf2, 0x00, 0x01, 0x03, 0x08, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x08, 0x08,
-+
-+ -1, 0xf8, 0x11,
-+
-+ -1, 0xf7, 0xc8, 0x20, 0x00, 0x00,
-+
-+ -1, 0xf3, 0x00, 0x00,
-+
-+ -1, 0x11,
-+ -2, 50,
-+
-+ -1, 0xf3, 0x00, 0x01,
-+ -2, 50,
-+ -1, 0xf3, 0x00, 0x03,
-+ -2, 50,
-+ -1, 0xf3, 0x00, 0x07,
-+ -2, 50,
-+ -1, 0xf3, 0x00, 0x0f,
-+ -2, 50,
-+
-+ -1, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
-+ -2, 50,
-+
-+ -1, 0xf3, 0x00, 0x1f,
-+ -2, 50,
-+ -1, 0xf3, 0x00, 0x7f,
-+ -2, 50,
-+
-+ -1, 0xf3, 0x00, 0xff,
-+ -2, 50,
-+
-+ -1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x00, 0x01, 0x00, 0x16, 0x16,
-+
-+ -1, 0xf4, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00,
-+
-+ /* initializing sequence */
-+
-+ -1, 0x36, 0x08,
-+
-+ -1, 0x35, 0x00,
-+
-+ -1, 0x3a, 0x05,
-+
-+ /* gamma setting sequence */
-+ -1, 0x26, 0x01, /* preset gamma curves, possible values 0x01, 0x02, 0x04, 0x08 */
-+
-+ -2, 150,
-+ -1, 0x29,
-+ -1, 0x2c,
-+ /* end marker */
-+ -3
-+
-+};
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address */
-+ write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
-+
-+ /* Row adress */
-+ write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+#define MY (1 << 7)
-+#define MX (1 << 6)
-+#define MV (1 << 5)
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* MADCTL - Memory data access control
-+ RGB/BGR:
-+ 1. Mode selection pin SRGB
-+ RGB H/W pin for color filter setting: 0=RGB, 1=BGR
-+ 2. MADCTL RGB bit
-+ RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR */
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x36, MX | MY | (par->bgr << 3));
-+ break;
-+ case 270:
-+ write_reg(par, 0x36, MY | MV | (par->bgr << 3));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, (par->bgr << 3));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, MX | MV | (par->bgr << 3));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = 128,
-+ .height = 160,
-+ .init_sequence = default_init_sequence,
-+ .fbtftops = {
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d02a1", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:s6d02a1");
-+MODULE_ALIAS("platform:s6d02a1");
-+
-+MODULE_DESCRIPTION("FB driver for the S6D02A1 LCD Controller");
-+MODULE_AUTHOR("WOLFGANG BUENING");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_s6d1121.c linux-rpi/drivers/staging/fbtft/fb_s6d1121.c
---- linux-3.18.14/drivers/staging/fbtft/fb_s6d1121.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_s6d1121.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,208 @@
-+/*
-+ * FB driver for the S6D1121 LCD Controller
-+ *
-+ * Copyright (C) 2013 Roman Rolinsky
-+ *
-+ * Based on fb_ili9325.c by Noralf Tronnes
-+ * Based on ili9325.c by Jeroen Domburg
-+ * Init code from UTFT library by Henning Karlsen
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_s6d1121"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define BPP 16
-+#define FPS 20
-+#define DEFAULT_GAMMA "26 09 24 2C 1F 23 24 25 22 26 25 23 0D 00\n" \
-+ "1C 1A 13 1D 0B 11 12 10 13 15 36 19 00 0D"
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ if (par->gpio.cs != -1)
-+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */
-+
-+ /* Initialization sequence from Lib_UTFT */
-+
-+ write_reg(par, 0x0011, 0x2004);
-+ write_reg(par, 0x0013, 0xCC00);
-+ write_reg(par, 0x0015, 0x2600);
-+ write_reg(par, 0x0014, 0x252A);
-+ write_reg(par, 0x0012, 0x0033);
-+ write_reg(par, 0x0013, 0xCC04);
-+ write_reg(par, 0x0013, 0xCC06);
-+ write_reg(par, 0x0013, 0xCC4F);
-+ write_reg(par, 0x0013, 0x674F);
-+ write_reg(par, 0x0011, 0x2003);
-+ write_reg(par, 0x0016, 0x0007);
-+ write_reg(par, 0x0002, 0x0013);
-+ write_reg(par, 0x0003, 0x0003);
-+ write_reg(par, 0x0001, 0x0127);
-+ write_reg(par, 0x0008, 0x0303);
-+ write_reg(par, 0x000A, 0x000B);
-+ write_reg(par, 0x000B, 0x0003);
-+ write_reg(par, 0x000C, 0x0000);
-+ write_reg(par, 0x0041, 0x0000);
-+ write_reg(par, 0x0050, 0x0000);
-+ write_reg(par, 0x0060, 0x0005);
-+ write_reg(par, 0x0070, 0x000B);
-+ write_reg(par, 0x0071, 0x0000);
-+ write_reg(par, 0x0078, 0x0000);
-+ write_reg(par, 0x007A, 0x0000);
-+ write_reg(par, 0x0079, 0x0007);
-+ write_reg(par, 0x0007, 0x0051);
-+ write_reg(par, 0x0007, 0x0053);
-+ write_reg(par, 0x0079, 0x0000);
-+
-+ write_reg(par, 0x0022); /* Write Data to GRAM */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+ switch (par->info->var.rotate) {
-+ /* R20h = Horizontal GRAM Start Address */
-+ /* R21h = Vertical GRAM Start Address */
-+ case 0:
-+ write_reg(par, 0x0020, xs);
-+ write_reg(par, 0x0021, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x0020, WIDTH - 1 - xs);
-+ write_reg(par, 0x0021, HEIGHT - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x0020, WIDTH - 1 - ys);
-+ write_reg(par, 0x0021, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x0020, ys);
-+ write_reg(par, 0x0021, HEIGHT - 1 - xs);
-+ break;
-+ }
-+ write_reg(par, 0x0022); /* Write Data to GRAM */
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ /* AM: GRAM update direction */
-+ case 0:
-+ write_reg(par, 0x03, 0x0003 | (par->bgr << 12));
-+ break;
-+ case 180:
-+ write_reg(par, 0x03, 0x0000 | (par->bgr << 12));
-+ break;
-+ case 270:
-+ write_reg(par, 0x03, 0x000A | (par->bgr << 12));
-+ break;
-+ case 90:
-+ write_reg(par, 0x03, 0x0009 | (par->bgr << 12));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Gamma string format:
-+ PKP0 PKP1 PKP2 PKP3 PKP4 PKP5 PKP6 PKP7 PKP8 PKP9 PKP10 PKP11 VRP0 VRP1
-+ PKN0 PKN1 PKN2 PKN3 PKN4 PKN5 PKN6 PKN7 PRN8 PRN9 PRN10 PRN11 VRN0 VRN1
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long mask[] = {
-+ 0b111111, 0b111111, 0b111111, 0b111111, 0b111111, 0b111111,
-+ 0b111111, 0b111111, 0b111111, 0b111111, 0b111111, 0b111111,
-+ 0b11111, 0b11111,
-+ 0b111111, 0b111111, 0b111111, 0b111111, 0b111111, 0b111111,
-+ 0b111111, 0b111111, 0b111111, 0b111111, 0b111111, 0b111111,
-+ 0b11111, 0b11111 };
-+ int i, j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < 2; i++)
-+ for (j = 0; j < 14; j++)
-+ CURVE(i, j) &= mask[i*par->gamma.num_values + j];
-+
-+ write_reg(par, 0x0030, CURVE(0, 1) << 8 | CURVE(0, 0));
-+ write_reg(par, 0x0031, CURVE(0, 3) << 8 | CURVE(0, 2));
-+ write_reg(par, 0x0032, CURVE(0, 5) << 8 | CURVE(0, 3));
-+ write_reg(par, 0x0033, CURVE(0, 7) << 8 | CURVE(0, 6));
-+ write_reg(par, 0x0034, CURVE(0, 9) << 8 | CURVE(0, 8));
-+ write_reg(par, 0x0035, CURVE(0, 11) << 8 | CURVE(0, 10));
-+
-+ write_reg(par, 0x0036, CURVE(1, 1) << 8 | CURVE(1, 0));
-+ write_reg(par, 0x0037, CURVE(1, 3) << 8 | CURVE(1, 2));
-+ write_reg(par, 0x0038, CURVE(1, 5) << 8 | CURVE(1, 4));
-+ write_reg(par, 0x0039, CURVE(1, 7) << 8 | CURVE(1, 6));
-+ write_reg(par, 0x003A, CURVE(1, 9) << 8 | CURVE(1, 8));
-+ write_reg(par, 0x003B, CURVE(1, 11) << 8 | CURVE(1, 10));
-+
-+ write_reg(par, 0x003C, CURVE(0, 13) << 8 | CURVE(0, 12));
-+ write_reg(par, 0x003D, CURVE(1, 13) << 8 | CURVE(1, 12));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 16,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .bpp = BPP,
-+ .fps = FPS,
-+ .gamma_num = 2,
-+ .gamma_len = 14,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d1121", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:s6d1121");
-+MODULE_ALIAS("platform:s6d1121");
-+
-+MODULE_DESCRIPTION("FB driver for the S6D1121 LCD Controller");
-+MODULE_AUTHOR("Roman Rolinsky");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ssd1289.c linux-rpi/drivers/staging/fbtft/fb_ssd1289.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ssd1289.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ssd1289.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,206 @@
-+/*
-+ * FB driver for the SSD1289 LCD Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * Init sequence taken from ITDB02_Graph16.cpp - (C)2010-2011 Henning Karlsen
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ssd1289"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define DEFAULT_GAMMA "02 03 2 5 7 7 4 2 4 2\n" \
-+ "02 03 2 5 7 5 4 2 4 2"
-+
-+static unsigned reg11 = 0x6040;
-+module_param(reg11, uint, 0);
-+MODULE_PARM_DESC(reg11, "Register 11h value");
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ if (par->gpio.cs != -1)
-+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */
-+
-+ write_reg(par, 0x00, 0x0001);
-+ write_reg(par, 0x03, 0xA8A4);
-+ write_reg(par, 0x0C, 0x0000);
-+ write_reg(par, 0x0D, 0x080C);
-+ write_reg(par, 0x0E, 0x2B00);
-+ write_reg(par, 0x1E, 0x00B7);
-+ write_reg(par, 0x01,
-+ (1 << 13) | (par->bgr << 11) | (1 << 9) | (HEIGHT - 1));
-+ write_reg(par, 0x02, 0x0600);
-+ write_reg(par, 0x10, 0x0000);
-+ write_reg(par, 0x05, 0x0000);
-+ write_reg(par, 0x06, 0x0000);
-+ write_reg(par, 0x16, 0xEF1C);
-+ write_reg(par, 0x17, 0x0003);
-+ write_reg(par, 0x07, 0x0233);
-+ write_reg(par, 0x0B, 0x0000);
-+ write_reg(par, 0x0F, 0x0000);
-+ write_reg(par, 0x41, 0x0000);
-+ write_reg(par, 0x42, 0x0000);
-+ write_reg(par, 0x48, 0x0000);
-+ write_reg(par, 0x49, 0x013F);
-+ write_reg(par, 0x4A, 0x0000);
-+ write_reg(par, 0x4B, 0x0000);
-+ write_reg(par, 0x44, 0xEF00);
-+ write_reg(par, 0x45, 0x0000);
-+ write_reg(par, 0x46, 0x013F);
-+ write_reg(par, 0x23, 0x0000);
-+ write_reg(par, 0x24, 0x0000);
-+ write_reg(par, 0x25, 0x8000);
-+ write_reg(par, 0x4f, 0x0000);
-+ write_reg(par, 0x4e, 0x0000);
-+ write_reg(par, 0x22);
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ switch (par->info->var.rotate) {
-+ /* R4Eh - Set GDDRAM X address counter */
-+ /* R4Fh - Set GDDRAM Y address counter */
-+ case 0:
-+ write_reg(par, 0x4e, xs);
-+ write_reg(par, 0x4f, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x4e, par->info->var.xres - 1 - xs);
-+ write_reg(par, 0x4f, par->info->var.yres - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x4e, par->info->var.yres - 1 - ys);
-+ write_reg(par, 0x4f, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x4e, ys);
-+ write_reg(par, 0x4f, par->info->var.xres - 1 - xs);
-+ break;
-+ }
-+
-+ /* R22h - RAM data write */
-+ write_reg(par, 0x22);
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ if (par->fbtftops.init_display != init_display) {
-+ /* don't risk messing up register 11h */
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "%s: skipping since custom init_display() is used\n",
-+ __func__);
-+ return 0;
-+ }
-+
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x11, reg11 | 0b110000);
-+ break;
-+ case 270:
-+ write_reg(par, 0x11, reg11 | 0b101000);
-+ break;
-+ case 180:
-+ write_reg(par, 0x11, reg11 | 0b000000);
-+ break;
-+ case 90:
-+ write_reg(par, 0x11, reg11 | 0b011000);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Gamma string format:
-+ VRP0 VRP1 PRP0 PRP1 PKP0 PKP1 PKP2 PKP3 PKP4 PKP5
-+ VRN0 VRN1 PRN0 PRN1 PKN0 PKN1 PKN2 PKN3 PKN4 PKN5
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long mask[] = {
-+ 0b11111, 0b11111, 0b111, 0b111, 0b111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111,
-+ 0b11111, 0b11111, 0b111, 0b111, 0b111,
-+ 0b111, 0b111, 0b111, 0b111, 0b111 };
-+ int i, j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < 2; i++)
-+ for (j = 0; j < 10; j++)
-+ CURVE(i, j) &= mask[i*par->gamma.num_values + j];
-+
-+ write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
-+ write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
-+ write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
-+ write_reg(par, 0x0033, CURVE(0, 3) << 8 | CURVE(0, 2));
-+ write_reg(par, 0x0034, CURVE(1, 5) << 8 | CURVE(1, 4));
-+ write_reg(par, 0x0035, CURVE(1, 7) << 8 | CURVE(1, 6));
-+ write_reg(par, 0x0036, CURVE(1, 9) << 8 | CURVE(1, 8));
-+ write_reg(par, 0x0037, CURVE(1, 3) << 8 | CURVE(1, 2));
-+ write_reg(par, 0x003A, CURVE(0, 1) << 8 | CURVE(0, 0));
-+ write_reg(par, 0x003B, CURVE(1, 1) << 8 | CURVE(1, 0));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 16,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .gamma_num = 2,
-+ .gamma_len = 10,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1289", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ssd1289");
-+MODULE_ALIAS("platform:ssd1289");
-+
-+MODULE_DESCRIPTION("FB driver for the SSD1289 LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ssd1306.c linux-rpi/drivers/staging/fbtft/fb_ssd1306.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ssd1306.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ssd1306.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,229 @@
-+/*
-+ * FB driver for the SSD1306 OLED Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ssd1306"
-+#define WIDTH 128
-+#define HEIGHT 64
-+
-+
-+/*
-+ write_reg() caveat:
-+
-+ This doesn't work because D/C has to be LOW for both values:
-+ write_reg(par, val1, val2);
-+
-+ Do it like this:
-+ write_reg(par, val1);
-+ write_reg(par, val2);
-+*/
-+
-+/* Init sequence taken from the Adafruit SSD1306 Arduino library */
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ if (par->gamma.curves[0] == 0) {
-+ mutex_lock(&par->gamma.lock);
-+ if (par->info->var.yres == 64)
-+ par->gamma.curves[0] = 0xCF;
-+ else
-+ par->gamma.curves[0] = 0x8F;
-+ mutex_unlock(&par->gamma.lock);
-+ }
-+
-+ /* Set Display OFF */
-+ write_reg(par, 0xAE);
-+
-+ /* Set Display Clock Divide Ratio/ Oscillator Frequency */
-+ write_reg(par, 0xD5);
-+ write_reg(par, 0x80);
-+
-+ /* Set Multiplex Ratio */
-+ write_reg(par, 0xA8);
-+ if (par->info->var.yres == 64)
-+ write_reg(par, 0x3F);
-+ else
-+ write_reg(par, 0x1F);
-+
-+ /* Set Display Offset */
-+ write_reg(par, 0xD3);
-+ write_reg(par, 0x0);
-+
-+ /* Set Display Start Line */
-+ write_reg(par, 0x40 | 0x0);
-+
-+ /* Charge Pump Setting */
-+ write_reg(par, 0x8D);
-+ /* A[2] = 1b, Enable charge pump during display on */
-+ write_reg(par, 0x14);
-+
-+ /* Set Memory Addressing Mode */
-+ write_reg(par, 0x20);
-+ /* Vertical addressing mode */
-+ write_reg(par, 0x01);
-+
-+ /*Set Segment Re-map */
-+ /* column address 127 is mapped to SEG0 */
-+ write_reg(par, 0xA0 | 0x1);
-+
-+ /* Set COM Output Scan Direction */
-+ /* remapped mode. Scan from COM[N-1] to COM0 */
-+ write_reg(par, 0xC8);
-+
-+ /* Set COM Pins Hardware Configuration */
-+ write_reg(par, 0xDA);
-+ if (par->info->var.yres == 64)
-+ /* A[4]=1b, Alternative COM pin configuration */
-+ write_reg(par, 0x12);
-+ else
-+ /* A[4]=0b, Sequential COM pin configuration */
-+ write_reg(par, 0x02);
-+
-+ /* Set Pre-charge Period */
-+ write_reg(par, 0xD9);
-+ write_reg(par, 0xF1);
-+
-+ /* Set VCOMH Deselect Level */
-+ write_reg(par, 0xDB);
-+ /* according to the datasheet, this value is out of bounds */
-+ write_reg(par, 0x40);
-+
-+ /* Entire Display ON */
-+ /* Resume to RAM content display. Output follows RAM content */
-+ write_reg(par, 0xA4);
-+
-+ /* Set Normal Display
-+ 0 in RAM: OFF in display panel
-+ 1 in RAM: ON in display panel */
-+ write_reg(par, 0xA6);
-+
-+ /* Set Display ON */
-+ write_reg(par, 0xAF);
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Set Lower Column Start Address for Page Addressing Mode */
-+ write_reg(par, 0x00 | 0x0);
-+ /* Set Higher Column Start Address for Page Addressing Mode */
-+ write_reg(par, 0x10 | 0x0);
-+ /* Set Display Start Line */
-+ write_reg(par, 0x40 | 0x0);
-+}
-+
-+static int blank(struct fbtft_par *par, bool on)
-+{
-+ fbtft_par_dbg(DEBUG_BLANK, par, "%s(blank=%s)\n",
-+ __func__, on ? "true" : "false");
-+
-+ if (on)
-+ write_reg(par, 0xAE);
-+ else
-+ write_reg(par, 0xAF);
-+ return 0;
-+}
-+
-+/* Gamma is used to control Contrast */
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ curves[0] &= 0xFF;
-+
-+ /* Set Contrast Control for BANK0 */
-+ write_reg(par, 0x81);
-+ write_reg(par, curves[0]);
-+
-+ return 0;
-+}
-+
-+static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16 = (u16 *)par->info->screen_base;
-+ u8 *buf = par->txbuf.buf;
-+ int x, y, i;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ for (x = 0; x < par->info->var.xres; x++) {
-+ for (y = 0; y < par->info->var.yres/8; y++) {
-+ *buf = 0x00;
-+ for (i = 0; i < 8; i++)
-+ *buf |= (vmem16[(y*8+i)*par->info->var.xres+x] ? 1 : 0) << i;
-+ buf++;
-+ }
-+ }
-+
-+ /* Write data */
-+ gpio_set_value(par->gpio.dc, 1);
-+ ret = par->fbtftops.write(par, par->txbuf.buf,
-+ par->info->var.xres*par->info->var.yres/8);
-+ if (ret < 0)
-+ dev_err(par->info->device,
-+ "%s: write failed and returned: %d\n", __func__, ret);
-+
-+ return ret;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .gamma_num = 1,
-+ .gamma_len = 1,
-+ .gamma = "00",
-+ .fbtftops = {
-+ .write_vmem = write_vmem,
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .blank = blank,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+
-+
-+FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1306", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ssd1306");
-+MODULE_ALIAS("platform:ssd1306");
-+
-+MODULE_DESCRIPTION("SSD1306 OLED Driver");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ssd1331.c linux-rpi/drivers/staging/fbtft/fb_ssd1331.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ssd1331.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ssd1331.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,205 @@
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ssd1331"
-+#define WIDTH 96
-+#define HEIGHT 64
-+#define GAMMA_NUM 1
-+#define GAMMA_LEN 63
-+#define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2" \
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ write_reg(par, 0xae); /* Display Off */
-+ write_reg(par, 0xa0, 0x70 | (par->bgr << 2)); /* Set Colour Depth */
-+ write_reg(par, 0x72); // RGB colour
-+ write_reg(par, 0xa1, 0x00); /* Set Display Start Line */
-+ write_reg(par, 0xa2, 0x00); /* Set Display Offset */
-+ write_reg(par, 0xa4); /* NORMALDISPLAY */
-+ write_reg(par, 0xa8, 0x3f); // Set multiplex
-+ write_reg(par, 0xad, 0x8e); // Set master
-+ // write_reg(par, 0xb0, 0x0b); // Set power mode
-+ write_reg(par, 0xb1, 0x31); // Precharge
-+ write_reg(par, 0xb3, 0xf0); // Clock div
-+ write_reg(par, 0x8a, 0x64); // Precharge A
-+ write_reg(par, 0x8b, 0x78); // Precharge B
-+ write_reg(par, 0x8c, 0x64); // Precharge C
-+ write_reg(par, 0xbb, 0x3a); // Precharge level
-+ write_reg(par, 0xbe, 0x3e); // vcomh
-+ write_reg(par, 0x87, 0x06); // Master current
-+ write_reg(par, 0x81, 0x91); // Contrast A
-+ write_reg(par, 0x82, 0x50); // Contrast B
-+ write_reg(par, 0x83, 0x7d); // Contrast C
-+ write_reg(par, 0xaf); /* Set Sleep Mode Display On */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ write_reg(par, 0x15, xs, xe);
-+ write_reg(par, 0x75, ys, ye);
-+}
-+
-+static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
-+{
-+ va_list args;
-+ int i, ret;
-+ u8 *buf = (u8 *)par->buf;
-+
-+ if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
-+ va_start(args, len);
-+ for (i = 0; i < len; i++) {
-+ buf[i] = (u8)va_arg(args, unsigned int);
-+ }
-+ va_end(args);
-+ fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device, u8, buf, len, "%s: ", __func__);
-+ }
-+
-+ va_start(args, len);
-+
-+ *buf = (u8)va_arg(args, unsigned int);
-+ if (par->gpio.dc != -1)
-+ gpio_set_value(par->gpio.dc, 0);
-+ ret = par->fbtftops.write(par, par->buf, sizeof(u8));
-+ if (ret < 0) {
-+ va_end(args);
-+ dev_err(par->info->device, "%s: write() failed and returned %d\n", __func__, ret);
-+ return;
-+ }
-+ len--;
-+
-+ if (len) {
-+ i = len;
-+ while (i--) {
-+ *buf++ = (u8)va_arg(args, unsigned int);
-+ }
-+ ret = par->fbtftops.write(par, par->buf, len * (sizeof(u8)));
-+ if (ret < 0) {
-+ va_end(args);
-+ dev_err(par->info->device, "%s: write() failed and returned %d\n", __func__, ret);
-+ return;
-+ }
-+ }
-+ if (par->gpio.dc != -1)
-+ gpio_set_value(par->gpio.dc, 1);
-+ va_end(args);
-+}
-+
-+/*
-+ Grayscale Lookup Table
-+ GS1 - GS63
-+ The driver Gamma curve contains the relative values between the entries
-+ in the Lookup table.
-+
-+ From datasheet:
-+ 8.8 Gray Scale Decoder
-+
-+ there are total 180 Gamma Settings (Setting 0 to Setting 180)
-+ available for the Gray Scale table.
-+
-+ The gray scale is defined in incremental way, with reference
-+ to the length of previous table entry:
-+ Setting of GS1 has to be >= 0
-+ Setting of GS2 has to be > Setting of GS1 +1
-+ Setting of GS3 has to be > Setting of GS2 +1
-+ :
-+ Setting of GS63 has to be > Setting of GS62 +1
-+
-+
-+*/
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long tmp[GAMMA_NUM * GAMMA_LEN];
-+ int i, acc = 0;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ for (i = 0; i < 63; i++) {
-+ if (i > 0 && curves[i] < 2) {
-+ dev_err(par->info->device,
-+ "Illegal value in Grayscale Lookup Table at index %d. " \
-+ "Must be greater than 1\n", i);
-+ return -EINVAL;
-+ }
-+ acc += curves[i];
-+ tmp[i] = acc;
-+ if (acc > 180) {
-+ dev_err(par->info->device,
-+ "Illegal value(s) in Grayscale Lookup Table. " \
-+ "At index=%d, the accumulated value has exceeded 180\n", i);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ write_reg(par, 0xB8,
-+ tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], tmp[7],
-+ tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], tmp[14], tmp[15],
-+ tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], tmp[21], tmp[22], tmp[23],
-+ tmp[24], tmp[25], tmp[26], tmp[27], tmp[28], tmp[29], tmp[30], tmp[31],
-+ tmp[32], tmp[33], tmp[34], tmp[35], tmp[36], tmp[37], tmp[38], tmp[39],
-+ tmp[40], tmp[41], tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47],
-+ tmp[48], tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55],
-+ tmp[56], tmp[57], tmp[58], tmp[59], tmp[60], tmp[61], tmp[62]);
-+
-+ return 0;
-+}
-+
-+static int blank(struct fbtft_par *par, bool on)
-+{
-+ fbtft_par_dbg(DEBUG_BLANK, par, "%s(blank=%s)\n",
-+ __func__, on ? "true" : "false");
-+ if (on)
-+ write_reg(par, 0xAE);
-+ else
-+ write_reg(par, 0xAF);
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .gamma_num = GAMMA_NUM,
-+ .gamma_len = GAMMA_LEN,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .write_register = write_reg8_bus8,
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_gamma = set_gamma,
-+ .blank = blank,
-+ },
-+};
-+
-+FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1331", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ssd1331");
-+MODULE_ALIAS("platform:ssd1331");
-+
-+MODULE_DESCRIPTION("SSD1331 OLED Driver");
-+MODULE_AUTHOR("Alec Smecher (adapted from SSD1351 by James Davies)");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_ssd1351.c linux-rpi/drivers/staging/fbtft/fb_ssd1351.c
---- linux-3.18.14/drivers/staging/fbtft/fb_ssd1351.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_ssd1351.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,258 @@
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_ssd1351"
-+#define WIDTH 128
-+#define HEIGHT 128
-+#define GAMMA_NUM 1
-+#define GAMMA_LEN 63
-+#define DEFAULT_GAMMA "0 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2" \
-+
-+static void register_onboard_backlight(struct fbtft_par *par);
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ if (par->pdata
-+ && par->pdata->display.backlight == FBTFT_ONBOARD_BACKLIGHT) {
-+ /* module uses onboard GPIO for panel power */
-+ par->fbtftops.register_backlight = register_onboard_backlight;
-+ }
-+
-+ par->fbtftops.reset(par);
-+
-+ write_reg(par, 0xfd, 0x12); /* Command Lock */
-+ write_reg(par, 0xfd, 0xb1); /* Command Lock */
-+ write_reg(par, 0xae); /* Display Off */
-+ write_reg(par, 0xb3, 0xf1); /* Front Clock Div */
-+ write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */
-+ write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */
-+ write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */
-+ write_reg(par, 0xa1, 0x00); /* Set Display Start Line */
-+ write_reg(par, 0xa2, 0x00); /* Set Display Offset */
-+ write_reg(par, 0xb5, 0x00); /* Set GPIO */
-+ write_reg(par, 0xab, 0x01); /* Set Function Selection */
-+ write_reg(par, 0xb1, 0x32); /* Set Phase Length */
-+ write_reg(par, 0xb4, 0xa0, 0xb5, 0x55); /* Set Segment Low Voltage */
-+ write_reg(par, 0xbb, 0x17); /* Set Precharge Voltage */
-+ write_reg(par, 0xbe, 0x05); /* Set VComH Voltage */
-+ write_reg(par, 0xc1, 0xc8, 0x80, 0xc8); /* Set Contrast */
-+ write_reg(par, 0xc7, 0x0f); /* Set Master Contrast */
-+ write_reg(par, 0xb6, 0x01); /* Set Second Precharge Period */
-+ write_reg(par, 0xa6); /* Set Display Mode Reset */
-+ write_reg(par, 0xaf); /* Set Sleep Mode Display On */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ write_reg(par, 0x15, xs, xe);
-+ write_reg(par, 0x75, ys, ye);
-+ write_reg(par, 0x5c);
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ unsigned remap;
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ if (par->fbtftops.init_display != init_display) {
-+ /* don't risk messing up register A0h */
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "%s: skipping since custom init_display() is used\n",
-+ __func__);
-+ return 0;
-+ }
-+
-+ remap = 0x60 | (par->bgr << 2); /* Set Colour Depth */
-+
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0xA0, remap | 0b00 | 1<<4);
-+ break;
-+ case 270:
-+ write_reg(par, 0xA0, remap | 0b11 | 1<<4);
-+ break;
-+ case 180:
-+ write_reg(par, 0xA0, remap | 0b10);
-+ break;
-+ case 90:
-+ write_reg(par, 0xA0, remap | 0b01);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Grayscale Lookup Table
-+ GS1 - GS63
-+ The driver Gamma curve contains the relative values between the entries
-+ in the Lookup table.
-+
-+ From datasheet:
-+ 8.8 Gray Scale Decoder
-+
-+ there are total 180 Gamma Settings (Setting 0 to Setting 180)
-+ available for the Gray Scale table.
-+
-+ The gray scale is defined in incremental way, with reference
-+ to the length of previous table entry:
-+ Setting of GS1 has to be >= 0
-+ Setting of GS2 has to be > Setting of GS1 +1
-+ Setting of GS3 has to be > Setting of GS2 +1
-+ :
-+ Setting of GS63 has to be > Setting of GS62 +1
-+
-+
-+*/
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ unsigned long tmp[GAMMA_NUM * GAMMA_LEN];
-+ int i, acc = 0;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ for (i = 0; i < 63; i++) {
-+ if (i > 0 && curves[i] < 2) {
-+ dev_err(par->info->device,
-+ "Illegal value in Grayscale Lookup Table at index %d. " \
-+ "Must be greater than 1\n", i);
-+ return -EINVAL;
-+ }
-+ acc += curves[i];
-+ tmp[i] = acc;
-+ if (acc > 180) {
-+ dev_err(par->info->device,
-+ "Illegal value(s) in Grayscale Lookup Table. " \
-+ "At index=%d, the accumulated value has exceeded 180\n", i);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ write_reg(par, 0xB8,
-+ tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], tmp[7],
-+ tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], tmp[14], tmp[15],
-+ tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], tmp[21], tmp[22], tmp[23],
-+ tmp[24], tmp[25], tmp[26], tmp[27], tmp[28], tmp[29], tmp[30], tmp[31],
-+ tmp[32], tmp[33], tmp[34], tmp[35], tmp[36], tmp[37], tmp[38], tmp[39],
-+ tmp[40], tmp[41], tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47],
-+ tmp[48], tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55],
-+ tmp[56], tmp[57], tmp[58], tmp[59], tmp[60], tmp[61], tmp[62]);
-+
-+ return 0;
-+}
-+
-+static int blank(struct fbtft_par *par, bool on)
-+{
-+ fbtft_par_dbg(DEBUG_BLANK, par, "%s(blank=%s)\n",
-+ __func__, on ? "true" : "false");
-+ if (on)
-+ write_reg(par, 0xAE);
-+ else
-+ write_reg(par, 0xAF);
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .gamma_num = GAMMA_NUM,
-+ .gamma_len = GAMMA_LEN,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ .blank = blank,
-+ },
-+};
-+
-+#ifdef CONFIG_FB_BACKLIGHT
-+static int update_onboard_backlight(struct backlight_device *bd)
-+{
-+ struct fbtft_par *par = bl_get_data(bd);
-+ bool on;
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par,
-+ "%s: power=%d, fb_blank=%d\n",
-+ __func__, bd->props.power, bd->props.fb_blank);
-+
-+ on = (bd->props.power == FB_BLANK_UNBLANK)
-+ && (bd->props.fb_blank == FB_BLANK_UNBLANK);
-+ /* Onboard backlight connected to GPIO0 on SSD1351, GPIO1 unused */
-+ write_reg(par, 0xB5, on ? 0x03 : 0x02);
-+
-+ return 0;
-+}
-+
-+static void register_onboard_backlight(struct fbtft_par *par)
-+{
-+ struct backlight_device *bd;
-+ struct backlight_properties bl_props = { 0, };
-+ struct backlight_ops *bl_ops;
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par, "%s()\n", __func__);
-+
-+ bl_ops = devm_kzalloc(par->info->device, sizeof(struct backlight_ops),
-+ GFP_KERNEL);
-+ if (!bl_ops) {
-+ dev_err(par->info->device,
-+ "%s: could not allocate memory for backlight operations.\n",
-+ __func__);
-+ return;
-+ }
-+
-+ bl_ops->update_status = update_onboard_backlight;
-+ bl_props.type = BACKLIGHT_RAW;
-+ bl_props.power = FB_BLANK_POWERDOWN;
-+
-+ bd = backlight_device_register(dev_driver_string(par->info->device),
-+ par->info->device, par, bl_ops, &bl_props);
-+ if (IS_ERR(bd)) {
-+ dev_err(par->info->device,
-+ "cannot register backlight device (%ld)\n",
-+ PTR_ERR(bd));
-+ return;
-+ }
-+ par->info->bl_dev = bd;
-+
-+ if (!par->fbtftops.unregister_backlight)
-+ par->fbtftops.unregister_backlight = fbtft_unregister_backlight;
-+}
-+#else
-+static void register_onboard_backlight(struct fbtft_par *par) { };
-+#endif
-+
-+
-+FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1351", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:ssd1351");
-+MODULE_ALIAS("platform:ssd1351");
-+
-+MODULE_DESCRIPTION("SSD1351 OLED Driver");
-+MODULE_AUTHOR("James Davies");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_st7735r.c linux-rpi/drivers/staging/fbtft/fb_st7735r.c
---- linux-3.18.14/drivers/staging/fbtft/fb_st7735r.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_st7735r.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,195 @@
-+/*
-+ * FB driver for the ST7735R LCD Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_st7735r"
-+#define DEFAULT_GAMMA "0F 1A 0F 18 2F 28 20 22 1F 1B 23 37 00 07 02 10\n" \
-+ "0F 1B 0F 17 33 2C 29 2E 30 30 39 3F 00 07 03 10"
-+
-+
-+static int default_init_sequence[] = {
-+ /* SWRESET - Software reset */
-+ -1, 0x01,
-+ -2, 150, /* delay */
-+
-+ /* SLPOUT - Sleep out & booster on */
-+ -1, 0x11,
-+ -2, 500, /* delay */
-+
-+ /* FRMCTR1 - frame rate control: normal mode
-+ frame rate = fosc / (1 x 2 + 40) * (LINE + 2C + 2D) */
-+ -1, 0xB1, 0x01, 0x2C, 0x2D,
-+
-+ /* FRMCTR2 - frame rate control: idle mode
-+ frame rate = fosc / (1 x 2 + 40) * (LINE + 2C + 2D) */
-+ -1, 0xB2, 0x01, 0x2C, 0x2D,
-+
-+ /* FRMCTR3 - frame rate control - partial mode
-+ dot inversion mode, line inversion mode */
-+ -1, 0xB3, 0x01, 0x2C, 0x2D, 0x01, 0x2C, 0x2D,
-+
-+ /* INVCTR - display inversion control
-+ no inversion */
-+ -1, 0xB4, 0x07,
-+
-+ /* PWCTR1 - Power Control
-+ -4.6V, AUTO mode */
-+ -1, 0xC0, 0xA2, 0x02, 0x84,
-+
-+ /* PWCTR2 - Power Control
-+ VGH25 = 2.4C VGSEL = -10 VGH = 3 * AVDD */
-+ -1, 0xC1, 0xC5,
-+
-+ /* PWCTR3 - Power Control
-+ Opamp current small, Boost frequency */
-+ -1, 0xC2, 0x0A, 0x00,
-+
-+ /* PWCTR4 - Power Control
-+ BCLK/2, Opamp current small & Medium low */
-+ -1, 0xC3,0x8A,0x2A,
-+
-+ /* PWCTR5 - Power Control */
-+ -1, 0xC4, 0x8A, 0xEE,
-+
-+ /* VMCTR1 - Power Control */
-+ -1, 0xC5, 0x0E,
-+
-+ /* INVOFF - Display inversion off */
-+ -1, 0x20,
-+
-+ /* COLMOD - Interface pixel format */
-+ -1, 0x3A, 0x05,
-+
-+ /* DISPON - Display On */
-+ -1, 0x29,
-+ -2, 100, /* delay */
-+
-+ /* NORON - Partial off (Normal) */
-+ -1, 0x13,
-+ -2, 10, /* delay */
-+
-+ /* end marker */
-+ -3
-+};
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address */
-+ write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
-+
-+ /* Row adress */
-+ write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+#define MY (1 << 7)
-+#define MX (1 << 6)
-+#define MV (1 << 5)
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* MADCTL - Memory data access control
-+ RGB/BGR:
-+ 1. Mode selection pin SRGB
-+ RGB H/W pin for color filter setting: 0=RGB, 1=BGR
-+ 2. MADCTL RGB bit
-+ RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR */
-+ switch (par->info->var.rotate) {
-+ case 0:
-+ write_reg(par, 0x36, MX | MY | (par->bgr << 3));
-+ break;
-+ case 270:
-+ write_reg(par, 0x36, MY | MV | (par->bgr << 3));
-+ break;
-+ case 180:
-+ write_reg(par, 0x36, (par->bgr << 3));
-+ break;
-+ case 90:
-+ write_reg(par, 0x36, MX | MV | (par->bgr << 3));
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/*
-+ Gamma string format:
-+ VRF0P VOS0P PK0P PK1P PK2P PK3P PK4P PK5P PK6P PK7P PK8P PK9P SELV0P SELV1P SELV62P SELV63P
-+ VRF0N VOS0N PK0N PK1N PK2N PK3N PK4N PK5N PK6N PK7N PK8N PK9N SELV0N SELV1N SELV62N SELV63N
-+*/
-+#define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ int i,j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ for (i = 0; i < par->gamma.num_curves; i++)
-+ for (j = 0; j < par->gamma.num_values; j++)
-+ CURVE(i,j) &= 0b111111;
-+
-+ for (i = 0; i < par->gamma.num_curves; i++)
-+ write_reg(par, 0xE0 + i,
-+ CURVE(i, 0), CURVE(i, 1), CURVE(i, 2), CURVE(i, 3),
-+ CURVE(i, 4), CURVE(i, 5), CURVE(i, 6), CURVE(i, 7),
-+ CURVE(i, 8), CURVE(i, 9), CURVE(i, 10), CURVE(i, 11),
-+ CURVE(i, 12), CURVE(i, 13), CURVE(i, 14), CURVE(i,15));
-+
-+ return 0;
-+}
-+#undef CURVE
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = 128,
-+ .height = 160,
-+ .init_sequence = default_init_sequence,
-+ .gamma_num = 2,
-+ .gamma_len = 16,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .set_gamma = set_gamma,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7735r", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:st7735r");
-+MODULE_ALIAS("platform:st7735r");
-+
-+MODULE_DESCRIPTION("FB driver for the ST7735R LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fbtft-bus.c linux-rpi/drivers/staging/fbtft/fbtft-bus.c
---- linux-3.18.14/drivers/staging/fbtft/fbtft-bus.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fbtft-bus.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,256 @@
-+#include <linux/export.h>
-+#include <linux/errno.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include "fbtft.h"
-+
-+
-+
-+
-+/*****************************************************************************
-+ *
-+ * void (*write_reg)(struct fbtft_par *par, int len, ...);
-+ *
-+ *****************************************************************************/
-+
-+#define define_fbtft_write_reg(func, type, modifier) \
-+void func(struct fbtft_par *par, int len, ...) \
-+{ \
-+ va_list args; \
-+ int i, ret; \
-+ int offset = 0; \
-+ type *buf = (type *)par->buf; \
-+ \
-+ if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) { \
-+ va_start(args, len); \
-+ for (i = 0; i < len; i++) { \
-+ buf[i] = (type)va_arg(args, unsigned int); \
-+ } \
-+ va_end(args); \
-+ fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device, type, buf, len, "%s: ", __func__); \
-+ } \
-+ \
-+ va_start(args, len); \
-+ \
-+ if (par->startbyte) { \
-+ *(u8 *)par->buf = par->startbyte; \
-+ buf = (type *)(par->buf + 1); \
-+ offset = 1; \
-+ } \
-+ \
-+ *buf = modifier((type)va_arg(args, unsigned int)); \
-+ if (par->gpio.dc != -1) \
-+ gpio_set_value(par->gpio.dc, 0); \
-+ ret = par->fbtftops.write(par, par->buf, sizeof(type)+offset); \
-+ if (ret < 0) { \
-+ va_end(args); \
-+ dev_err(par->info->device, "%s: write() failed and returned %d\n", __func__, ret); \
-+ return; \
-+ } \
-+ len--; \
-+ \
-+ if (par->startbyte) \
-+ *(u8 *)par->buf = par->startbyte | 0x2; \
-+ \
-+ if (len) { \
-+ i = len; \
-+ while (i--) { \
-+ *buf++ = modifier((type)va_arg(args, unsigned int)); \
-+ } \
-+ if (par->gpio.dc != -1) \
-+ gpio_set_value(par->gpio.dc, 1); \
-+ ret = par->fbtftops.write(par, par->buf, len * (sizeof(type)+offset)); \
-+ if (ret < 0) { \
-+ va_end(args); \
-+ dev_err(par->info->device, "%s: write() failed and returned %d\n", __func__, ret); \
-+ return; \
-+ } \
-+ } \
-+ va_end(args); \
-+} \
-+EXPORT_SYMBOL(func);
-+
-+define_fbtft_write_reg(fbtft_write_reg8_bus8, u8, )
-+define_fbtft_write_reg(fbtft_write_reg16_bus8, u16, cpu_to_be16)
-+define_fbtft_write_reg(fbtft_write_reg16_bus16, u16, )
-+
-+void fbtft_write_reg8_bus9(struct fbtft_par *par, int len, ...)
-+{
-+ va_list args;
-+ int i, ret;
-+ int pad = 0;
-+ u16 *buf = (u16 *)par->buf;
-+
-+ if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
-+ va_start(args, len);
-+ for (i = 0; i < len; i++)
-+ *(((u8 *)buf) + i) = (u8)va_arg(args, unsigned int);
-+ va_end(args);
-+ fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par,
-+ par->info->device, u8, buf, len, "%s: ", __func__);
-+ }
-+ if (len <= 0)
-+ return;
-+
-+ if (par->spi && (par->spi->bits_per_word == 8)) {
-+ /* we're emulating 9-bit, pad start of buffer with no-ops
-+ (assuming here that zero is a no-op) */
-+ pad = (len % 4) ? 4 - (len % 4) : 0;
-+ for (i = 0; i < pad; i++)
-+ *buf++ = 0x000;
-+ }
-+
-+ va_start(args, len);
-+ *buf++ = (u8)va_arg(args, unsigned int);
-+ i = len - 1;
-+ while (i--) {
-+ *buf = (u8)va_arg(args, unsigned int);
-+ *buf++ |= 0x100; /* dc=1 */
-+ }
-+ va_end(args);
-+ ret = par->fbtftops.write(par, par->buf, (len + pad) * sizeof(u16));
-+ if (ret < 0) {
-+ dev_err(par->info->device,
-+ "%s: write() failed and returned %d\n", __func__, ret);
-+ return;
-+ }
-+}
-+EXPORT_SYMBOL(fbtft_write_reg8_bus9);
-+
-+
-+
-+
-+/*****************************************************************************
-+ *
-+ * int (*write_vmem)(struct fbtft_par *par);
-+ *
-+ *****************************************************************************/
-+
-+/* 16 bit pixel over 8-bit databus */
-+int fbtft_write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16;
-+ u16 *txbuf16 = (u16 *)par->txbuf.buf;
-+ size_t remain;
-+ size_t to_copy;
-+ size_t tx_array_size;
-+ int i;
-+ int ret = 0;
-+ size_t startbyte_size = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
-+ __func__, offset, len);
-+
-+ remain = len / 2;
-+ vmem16 = (u16 *)(par->info->screen_base + offset);
-+
-+ if (par->gpio.dc != -1)
-+ gpio_set_value(par->gpio.dc, 1);
-+
-+ /* non buffered write */
-+ if (!par->txbuf.buf)
-+ return par->fbtftops.write(par, vmem16, len);
-+
-+ /* buffered write */
-+ tx_array_size = par->txbuf.len / 2;
-+
-+ if (par->startbyte) {
-+ txbuf16 = (u16 *)(par->txbuf.buf + 1);
-+ tx_array_size -= 2;
-+ *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2;
-+ startbyte_size = 1;
-+ }
-+
-+ while (remain) {
-+ to_copy = remain > tx_array_size ? tx_array_size : remain;
-+ dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n",
-+ to_copy, remain - to_copy);
-+
-+ for (i = 0; i < to_copy; i++)
-+ txbuf16[i] = cpu_to_be16(vmem16[i]);
-+
-+ vmem16 = vmem16 + to_copy;
-+ ret = par->fbtftops.write(par, par->txbuf.buf,
-+ startbyte_size + to_copy * 2);
-+ if (ret < 0)
-+ return ret;
-+ remain -= to_copy;
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(fbtft_write_vmem16_bus8);
-+
-+/* 16 bit pixel over 9-bit SPI bus: dc + high byte, dc + low byte */
-+int fbtft_write_vmem16_bus9(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u8 *vmem8;
-+ u16 *txbuf16 = par->txbuf.buf;
-+ size_t remain;
-+ size_t to_copy;
-+ size_t tx_array_size;
-+ int i;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
-+ __func__, offset, len);
-+
-+ if (!par->txbuf.buf) {
-+ dev_err(par->info->device, "%s: txbuf.buf is NULL\n", __func__);
-+ return -1;
-+ }
-+
-+ remain = len;
-+ vmem8 = par->info->screen_base + offset;
-+
-+ tx_array_size = par->txbuf.len / 2;
-+
-+ while (remain) {
-+ to_copy = remain > tx_array_size ? tx_array_size : remain;
-+ dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n",
-+ to_copy, remain - to_copy);
-+
-+#ifdef __LITTLE_ENDIAN
-+ for (i = 0; i < to_copy; i += 2) {
-+ txbuf16[i] = 0x0100 | vmem8[i+1];
-+ txbuf16[i+1] = 0x0100 | vmem8[i];
-+ }
-+#else
-+ for (i = 0; i < to_copy; i++)
-+ txbuf16[i] = 0x0100 | vmem8[i];
-+#endif
-+ vmem8 = vmem8 + to_copy;
-+ ret = par->fbtftops.write(par, par->txbuf.buf, to_copy*2);
-+ if (ret < 0)
-+ return ret;
-+ remain -= to_copy;
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(fbtft_write_vmem16_bus9);
-+
-+int fbtft_write_vmem8_bus8(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ dev_err(par->info->device, "%s: function not implemented\n", __func__);
-+ return -1;
-+}
-+EXPORT_SYMBOL(fbtft_write_vmem8_bus8);
-+
-+/* 16 bit pixel over 16-bit databus */
-+int fbtft_write_vmem16_bus16(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
-+ __func__, offset, len);
-+
-+ vmem16 = (u16 *)(par->info->screen_base + offset);
-+
-+ if (par->gpio.dc != -1)
-+ gpio_set_value(par->gpio.dc, 1);
-+
-+ /* no need for buffered write with 16-bit bus */
-+ return par->fbtftops.write(par, vmem16, len);
-+}
-+EXPORT_SYMBOL(fbtft_write_vmem16_bus16);
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fbtft-core.c linux-rpi/drivers/staging/fbtft/fbtft-core.c
---- linux-3.18.14/drivers/staging/fbtft/fbtft-core.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fbtft-core.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,1521 @@
-+/*
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This driver is inspired by:
-+ * st7735fb.c, Copyright (C) 2011, Matt Porter
-+ * broadsheetfb.c, Copyright (C) 2008, Jaya Kumar
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/vmalloc.h>
-+#include <linux/slab.h>
-+#include <linux/init.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+#include <linux/uaccess.h>
-+#include <linux/backlight.h>
-+#include <linux/platform_device.h>
-+#include <linux/spinlock.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of.h>
-+#include <linux/of_gpio.h>
-+
-+#include "fbtft.h"
-+
-+extern void fbtft_sysfs_init(struct fbtft_par *par);
-+extern void fbtft_sysfs_exit(struct fbtft_par *par);
-+extern void fbtft_expand_debug_value(unsigned long *debug);
-+extern int fbtft_gamma_parse_str(struct fbtft_par *par, unsigned long *curves,
-+ const char *str, int size);
-+
-+static unsigned long debug;
-+module_param(debug, ulong , 0);
-+MODULE_PARM_DESC(debug, "override device debug level");
-+
-+static bool dma = true;
-+module_param(dma, bool, 0);
-+MODULE_PARM_DESC(dma, "Use DMA buffer");
-+
-+
-+void fbtft_dbg_hex(const struct device *dev, int groupsize,
-+ void *buf, size_t len, const char *fmt, ...)
-+{
-+ va_list args;
-+ static char textbuf[512];
-+ char *text = textbuf;
-+ size_t text_len;
-+
-+ va_start(args, fmt);
-+ text_len = vscnprintf(text, sizeof(textbuf), fmt, args);
-+ va_end(args);
-+
-+ hex_dump_to_buffer(buf, len, 32, groupsize, text + text_len,
-+ 512 - text_len, false);
-+
-+ if (len > 32)
-+ dev_info(dev, "%s ...\n", text);
-+ else
-+ dev_info(dev, "%s\n", text);
-+}
-+EXPORT_SYMBOL(fbtft_dbg_hex);
-+
-+static unsigned long fbtft_request_gpios_match(struct fbtft_par *par,
-+ const struct fbtft_gpio *gpio)
-+{
-+ int ret;
-+ long val;
-+
-+ fbtft_par_dbg(DEBUG_REQUEST_GPIOS_MATCH, par, "%s('%s')\n",
-+ __func__, gpio->name);
-+
-+ if (strcasecmp(gpio->name, "reset") == 0) {
-+ par->gpio.reset = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ } else if (strcasecmp(gpio->name, "dc") == 0) {
-+ par->gpio.dc = gpio->gpio;
-+ return GPIOF_OUT_INIT_LOW;
-+ } else if (strcasecmp(gpio->name, "cs") == 0) {
-+ par->gpio.cs = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ } else if (strcasecmp(gpio->name, "wr") == 0) {
-+ par->gpio.wr = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ } else if (strcasecmp(gpio->name, "rd") == 0) {
-+ par->gpio.rd = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ } else if (strcasecmp(gpio->name, "latch") == 0) {
-+ par->gpio.latch = gpio->gpio;
-+ return GPIOF_OUT_INIT_LOW;
-+ } else if (gpio->name[0] == 'd' && gpio->name[1] == 'b') {
-+ ret = kstrtol(&gpio->name[2], 10, &val);
-+ if (ret == 0 && val < 16) {
-+ par->gpio.db[val] = gpio->gpio;
-+ return GPIOF_OUT_INIT_LOW;
-+ }
-+ } else if (strcasecmp(gpio->name, "led") == 0) {
-+ par->gpio.led[0] = gpio->gpio;
-+ return GPIOF_OUT_INIT_LOW;
-+ } else if (strcasecmp(gpio->name, "led_") == 0) {
-+ par->gpio.led[0] = gpio->gpio;
-+ return GPIOF_OUT_INIT_HIGH;
-+ }
-+
-+ return FBTFT_GPIO_NO_MATCH;
-+}
-+
-+static int fbtft_request_gpios(struct fbtft_par *par)
-+{
-+ struct fbtft_platform_data *pdata = par->pdata;
-+ const struct fbtft_gpio *gpio;
-+ unsigned long flags;
-+ int ret;
-+
-+ if (pdata && pdata->gpios) {
-+ gpio = pdata->gpios;
-+ while (gpio->name[0]) {
-+ flags = FBTFT_GPIO_NO_MATCH;
-+ /* if driver provides match function, try it first,
-+ if no match use our own */
-+ if (par->fbtftops.request_gpios_match)
-+ flags = par->fbtftops.request_gpios_match(par, gpio);
-+ if (flags == FBTFT_GPIO_NO_MATCH)
-+ flags = fbtft_request_gpios_match(par, gpio);
-+ if (flags != FBTFT_GPIO_NO_MATCH) {
-+ ret = devm_gpio_request_one(par->info->device,
-+ gpio->gpio, flags,
-+ par->info->device->driver->name);
-+ if (ret < 0) {
-+ dev_err(par->info->device,
-+ "%s: gpio_request_one('%s'=%d) failed with %d\n",
-+ __func__, gpio->name,
-+ gpio->gpio, ret);
-+ return ret;
-+ }
-+ fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par,
-+ "%s: '%s' = GPIO%d\n",
-+ __func__, gpio->name, gpio->gpio);
-+ }
-+ gpio++;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static int fbtft_request_one_gpio(struct fbtft_par *par,
-+ const char *name, int index, int *gpiop)
-+{
-+ struct device *dev = par->info->device;
-+ struct device_node *node = dev->of_node;
-+ int gpio, flags, ret = 0;
-+ enum of_gpio_flags of_flags;
-+
-+ if (of_find_property(node, name, NULL)) {
-+ gpio = of_get_named_gpio_flags(node, name, index, &of_flags);
-+ if (gpio == -ENOENT)
-+ return 0;
-+ if (gpio == -EPROBE_DEFER)
-+ return gpio;
-+ if (gpio < 0) {
-+ dev_err(dev,
-+ "failed to get '%s' from DT\n", name);
-+ return gpio;
-+ }
-+
-+ /* active low translates to initially low */
-+ flags = (of_flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_LOW :
-+ GPIOF_OUT_INIT_HIGH;
-+ ret = devm_gpio_request_one(dev, gpio, flags,
-+ dev->driver->name);
-+ if (ret) {
-+ dev_err(dev,
-+ "gpio_request_one('%s'=%d) failed with %d\n",
-+ name, gpio, ret);
-+ return ret;
-+ }
-+ if (gpiop)
-+ *gpiop = gpio;
-+ fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par, "%s: '%s' = GPIO%d\n",
-+ __func__, name, gpio);
-+ }
-+
-+ return ret;
-+}
-+
-+static int fbtft_request_gpios_dt(struct fbtft_par *par)
-+{
-+ int i;
-+ int ret;
-+
-+ if (!par->info->device->of_node)
-+ return -EINVAL;
-+
-+ ret = fbtft_request_one_gpio(par, "reset-gpios", 0, &par->gpio.reset);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "dc-gpios", 0, &par->gpio.dc);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "rd-gpios", 0, &par->gpio.rd);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "wr-gpios", 0, &par->gpio.wr);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "cs-gpios", 0, &par->gpio.cs);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "latch-gpios", 0, &par->gpio.latch);
-+ if (ret)
-+ return ret;
-+ for (i = 0; i < 16; i++) {
-+ ret = fbtft_request_one_gpio(par, "db-gpios", i,
-+ &par->gpio.db[i]);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "led-gpios", i,
-+ &par->gpio.led[i]);
-+ if (ret)
-+ return ret;
-+ ret = fbtft_request_one_gpio(par, "aux-gpios", i,
-+ &par->gpio.aux[i]);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+#endif
-+
-+#ifdef CONFIG_FB_BACKLIGHT
-+static int fbtft_backlight_update_status(struct backlight_device *bd)
-+{
-+ struct fbtft_par *par = bl_get_data(bd);
-+ bool polarity = !!(bd->props.state & BL_CORE_DRIVER1);
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par,
-+ "%s: polarity=%d, power=%d, fb_blank=%d\n",
-+ __func__, polarity, bd->props.power, bd->props.fb_blank);
-+
-+ if ((bd->props.power == FB_BLANK_UNBLANK) && (bd->props.fb_blank == FB_BLANK_UNBLANK))
-+ gpio_set_value(par->gpio.led[0], polarity);
-+ else
-+ gpio_set_value(par->gpio.led[0], !polarity);
-+
-+ return 0;
-+}
-+
-+static int fbtft_backlight_get_brightness(struct backlight_device *bd)
-+{
-+ return bd->props.brightness;
-+}
-+
-+void fbtft_unregister_backlight(struct fbtft_par *par)
-+{
-+ const struct backlight_ops *bl_ops;
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par, "%s()\n", __func__);
-+
-+ if (par->info->bl_dev) {
-+ par->info->bl_dev->props.power = FB_BLANK_POWERDOWN;
-+ backlight_update_status(par->info->bl_dev);
-+ bl_ops = par->info->bl_dev->ops;
-+ backlight_device_unregister(par->info->bl_dev);
-+ par->info->bl_dev = NULL;
-+ }
-+}
-+
-+void fbtft_register_backlight(struct fbtft_par *par)
-+{
-+ struct backlight_device *bd;
-+ struct backlight_properties bl_props = { 0, };
-+ struct backlight_ops *bl_ops;
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par, "%s()\n", __func__);
-+
-+ if (par->gpio.led[0] == -1) {
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par,
-+ "%s(): led pin not set, exiting.\n", __func__);
-+ return;
-+ }
-+
-+ bl_ops = devm_kzalloc(par->info->device, sizeof(struct backlight_ops),
-+ GFP_KERNEL);
-+ if (!bl_ops) {
-+ dev_err(par->info->device,
-+ "%s: could not allocate memeory for backlight operations.\n",
-+ __func__);
-+ return;
-+ }
-+
-+ bl_ops->get_brightness = fbtft_backlight_get_brightness;
-+ bl_ops->update_status = fbtft_backlight_update_status;
-+ bl_props.type = BACKLIGHT_RAW;
-+ /* Assume backlight is off, get polarity from current state of pin */
-+ bl_props.power = FB_BLANK_POWERDOWN;
-+ if (!gpio_get_value(par->gpio.led[0]))
-+ bl_props.state |= BL_CORE_DRIVER1;
-+
-+ bd = backlight_device_register(dev_driver_string(par->info->device),
-+ par->info->device, par, bl_ops, &bl_props);
-+ if (IS_ERR(bd)) {
-+ dev_err(par->info->device,
-+ "cannot register backlight device (%ld)\n",
-+ PTR_ERR(bd));
-+ return;
-+ }
-+ par->info->bl_dev = bd;
-+
-+ if (!par->fbtftops.unregister_backlight)
-+ par->fbtftops.unregister_backlight = fbtft_unregister_backlight;
-+}
-+#else
-+void fbtft_register_backlight(struct fbtft_par *par) { };
-+void fbtft_unregister_backlight(struct fbtft_par *par) { };
-+#endif
-+EXPORT_SYMBOL(fbtft_register_backlight);
-+EXPORT_SYMBOL(fbtft_unregister_backlight);
-+
-+static void fbtft_set_addr_win(struct fbtft_par *par, int xs, int ys, int xe,
-+ int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address set */
-+ write_reg(par, 0x2A,
-+ (xs >> 8) & 0xFF, xs & 0xFF, (xe >> 8) & 0xFF, xe & 0xFF);
-+
-+ /* Row adress set */
-+ write_reg(par, 0x2B,
-+ (ys >> 8) & 0xFF, ys & 0xFF, (ye >> 8) & 0xFF, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+
-+static void fbtft_reset(struct fbtft_par *par)
-+{
-+ if (par->gpio.reset == -1)
-+ return;
-+ fbtft_par_dbg(DEBUG_RESET, par, "%s()\n", __func__);
-+ gpio_set_value(par->gpio.reset, 0);
-+ udelay(20);
-+ gpio_set_value(par->gpio.reset, 1);
-+ mdelay(120);
-+}
-+
-+
-+static void fbtft_update_display(struct fbtft_par *par, unsigned start_line,
-+ unsigned end_line)
-+{
-+ size_t offset, len;
-+ struct timespec ts_start, ts_end, ts_fps, ts_duration;
-+ long fps_ms, fps_us, duration_ms, duration_us;
-+ long fps, throughput;
-+ bool timeit = false;
-+ int ret = 0;
-+
-+ if (unlikely(par->debug & (DEBUG_TIME_FIRST_UPDATE | DEBUG_TIME_EACH_UPDATE))) {
-+ if ((par->debug & DEBUG_TIME_EACH_UPDATE) || \
-+ ((par->debug & DEBUG_TIME_FIRST_UPDATE) && !par->first_update_done)) {
-+ getnstimeofday(&ts_start);
-+ timeit = true;
-+ }
-+ }
-+
-+ /* Sanity checks */
-+ if (start_line > end_line) {
-+ dev_warn(par->info->device,
-+ "%s: start_line=%u is larger than end_line=%u. Shouldn't happen, will do full display update\n",
-+ __func__, start_line, end_line);
-+ start_line = 0;
-+ end_line = par->info->var.yres - 1;
-+ }
-+ if (start_line > par->info->var.yres - 1 || end_line > par->info->var.yres - 1) {
-+ dev_warn(par->info->device,
-+ "%s: start_line=%u or end_line=%u is larger than max=%d. Shouldn't happen, will do full display update\n",
-+ __func__, start_line, end_line, par->info->var.yres - 1);
-+ start_line = 0;
-+ end_line = par->info->var.yres - 1;
-+ }
-+
-+ fbtft_par_dbg(DEBUG_UPDATE_DISPLAY, par, "%s(start_line=%u, end_line=%u)\n",
-+ __func__, start_line, end_line);
-+
-+ if (par->fbtftops.set_addr_win)
-+ par->fbtftops.set_addr_win(par, 0, start_line,
-+ par->info->var.xres-1, end_line);
-+
-+ offset = start_line * par->info->fix.line_length;
-+ len = (end_line - start_line + 1) * par->info->fix.line_length;
-+ ret = par->fbtftops.write_vmem(par, offset, len);
-+ if (ret < 0)
-+ dev_err(par->info->device,
-+ "%s: write_vmem failed to update display buffer\n",
-+ __func__);
-+
-+ if (unlikely(timeit)) {
-+ getnstimeofday(&ts_end);
-+ if (par->update_time.tv_nsec == 0 && par->update_time.tv_sec == 0) {
-+ par->update_time.tv_sec = ts_start.tv_sec;
-+ par->update_time.tv_nsec = ts_start.tv_nsec;
-+ }
-+ ts_fps = timespec_sub(ts_start, par->update_time);
-+ par->update_time.tv_sec = ts_start.tv_sec;
-+ par->update_time.tv_nsec = ts_start.tv_nsec;
-+ fps_ms = (ts_fps.tv_sec * 1000) + ((ts_fps.tv_nsec / 1000000) % 1000);
-+ fps_us = (ts_fps.tv_nsec / 1000) % 1000;
-+ fps = fps_ms * 1000 + fps_us;
-+ fps = fps ? 1000000 / fps : 0;
-+
-+ ts_duration = timespec_sub(ts_end, ts_start);
-+ duration_ms = (ts_duration.tv_sec * 1000) + ((ts_duration.tv_nsec / 1000000) % 1000);
-+ duration_us = (ts_duration.tv_nsec / 1000) % 1000;
-+ throughput = duration_ms * 1000 + duration_us;
-+ throughput = throughput ? (len * 1000) / throughput : 0;
-+ throughput = throughput * 1000 / 1024;
-+
-+ dev_info(par->info->device,
-+ "Display update: %ld kB/s (%ld.%.3ld ms), fps=%ld (%ld.%.3ld ms)\n",
-+ throughput, duration_ms, duration_us,
-+ fps, fps_ms, fps_us);
-+ par->first_update_done = true;
-+ }
-+}
-+
-+
-+static void fbtft_mkdirty(struct fb_info *info, int y, int height)
-+{
-+ struct fbtft_par *par = info->par;
-+ struct fb_deferred_io *fbdefio = info->fbdefio;
-+
-+ /* special case, needed ? */
-+ if (y == -1) {
-+ y = 0;
-+ height = info->var.yres - 1;
-+ }
-+
-+ /* Mark display lines/area as dirty */
-+ spin_lock(&par->dirty_lock);
-+ if (y < par->dirty_lines_start)
-+ par->dirty_lines_start = y;
-+ if (y + height - 1 > par->dirty_lines_end)
-+ par->dirty_lines_end = y + height - 1;
-+ spin_unlock(&par->dirty_lock);
-+
-+ /* Schedule deferred_io to update display (no-op if already on queue)*/
-+ schedule_delayed_work(&info->deferred_work, fbdefio->delay);
-+}
-+
-+static void fbtft_deferred_io(struct fb_info *info, struct list_head *pagelist)
-+{
-+ struct fbtft_par *par = info->par;
-+ unsigned dirty_lines_start, dirty_lines_end;
-+ struct page *page;
-+ unsigned long index;
-+ unsigned y_low = 0, y_high = 0;
-+ int count = 0;
-+
-+ spin_lock(&par->dirty_lock);
-+ dirty_lines_start = par->dirty_lines_start;
-+ dirty_lines_end = par->dirty_lines_end;
-+ /* set display line markers as clean */
-+ par->dirty_lines_start = par->info->var.yres - 1;
-+ par->dirty_lines_end = 0;
-+ spin_unlock(&par->dirty_lock);
-+
-+ /* Mark display lines as dirty */
-+ list_for_each_entry(page, pagelist, lru) {
-+ count++;
-+ index = page->index << PAGE_SHIFT;
-+ y_low = index / info->fix.line_length;
-+ y_high = (index + PAGE_SIZE - 1) / info->fix.line_length;
-+ fbtft_dev_dbg(DEBUG_DEFERRED_IO, par, info->device,
-+ "page->index=%lu y_low=%d y_high=%d\n",
-+ page->index, y_low, y_high);
-+ if (y_high > info->var.yres - 1)
-+ y_high = info->var.yres - 1;
-+ if (y_low < dirty_lines_start)
-+ dirty_lines_start = y_low;
-+ if (y_high > dirty_lines_end)
-+ dirty_lines_end = y_high;
-+ }
-+
-+ par->fbtftops.update_display(info->par,
-+ dirty_lines_start, dirty_lines_end);
-+}
-+
-+
-+static void fbtft_fb_fillrect(struct fb_info *info,
-+ const struct fb_fillrect *rect)
-+{
-+ struct fbtft_par *par = info->par;
-+
-+ fbtft_dev_dbg(DEBUG_FB_FILLRECT, par, info->dev,
-+ "%s: dx=%d, dy=%d, width=%d, height=%d\n",
-+ __func__, rect->dx, rect->dy, rect->width, rect->height);
-+ sys_fillrect(info, rect);
-+
-+ par->fbtftops.mkdirty(info, rect->dy, rect->height);
-+}
-+
-+static void fbtft_fb_copyarea(struct fb_info *info,
-+ const struct fb_copyarea *area)
-+{
-+ struct fbtft_par *par = info->par;
-+
-+ fbtft_dev_dbg(DEBUG_FB_COPYAREA, par, info->dev,
-+ "%s: dx=%d, dy=%d, width=%d, height=%d\n",
-+ __func__, area->dx, area->dy, area->width, area->height);
-+ sys_copyarea(info, area);
-+
-+ par->fbtftops.mkdirty(info, area->dy, area->height);
-+}
-+
-+static void fbtft_fb_imageblit(struct fb_info *info,
-+ const struct fb_image *image)
-+{
-+ struct fbtft_par *par = info->par;
-+
-+ fbtft_dev_dbg(DEBUG_FB_IMAGEBLIT, par, info->dev,
-+ "%s: dx=%d, dy=%d, width=%d, height=%d\n",
-+ __func__, image->dx, image->dy, image->width, image->height);
-+ sys_imageblit(info, image);
-+
-+ par->fbtftops.mkdirty(info, image->dy, image->height);
-+}
-+
-+static ssize_t fbtft_fb_write(struct fb_info *info, const char __user *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct fbtft_par *par = info->par;
-+ ssize_t res;
-+
-+ fbtft_dev_dbg(DEBUG_FB_WRITE, par, info->dev,
-+ "%s: count=%zd, ppos=%llu\n", __func__, count, *ppos);
-+ res = fb_sys_write(info, buf, count, ppos);
-+
-+ /* TODO: only mark changed area
-+ update all for now */
-+ par->fbtftops.mkdirty(info, -1, 0);
-+
-+ return res;
-+}
-+
-+/* from pxafb.c */
-+static unsigned int chan_to_field(unsigned chan, struct fb_bitfield *bf)
-+{
-+ chan &= 0xffff;
-+ chan >>= 16 - bf->length;
-+ return chan << bf->offset;
-+}
-+
-+static int fbtft_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
-+ unsigned blue, unsigned transp,
-+ struct fb_info *info)
-+{
-+ struct fbtft_par *par = info->par;
-+ unsigned val;
-+ int ret = 1;
-+
-+ fbtft_dev_dbg(DEBUG_FB_SETCOLREG, par, info->dev,
-+ "%s(regno=%u, red=0x%X, green=0x%X, blue=0x%X, trans=0x%X)\n",
-+ __func__, regno, red, green, blue, transp);
-+
-+ switch (info->fix.visual) {
-+ case FB_VISUAL_TRUECOLOR:
-+ if (regno < 16) {
-+ u32 *pal = info->pseudo_palette;
-+
-+ val = chan_to_field(red, &info->var.red);
-+ val |= chan_to_field(green, &info->var.green);
-+ val |= chan_to_field(blue, &info->var.blue);
-+
-+ pal[regno] = val;
-+ ret = 0;
-+ }
-+ break;
-+
-+ }
-+ return ret;
-+}
-+
-+static int fbtft_fb_blank(int blank, struct fb_info *info)
-+{
-+ struct fbtft_par *par = info->par;
-+ int ret = -EINVAL;
-+
-+ fbtft_dev_dbg(DEBUG_FB_BLANK, par, info->dev, "%s(blank=%d)\n",
-+ __func__, blank);
-+
-+ if (!par->fbtftops.blank)
-+ return ret;
-+
-+ switch (blank) {
-+ case FB_BLANK_POWERDOWN:
-+ case FB_BLANK_VSYNC_SUSPEND:
-+ case FB_BLANK_HSYNC_SUSPEND:
-+ case FB_BLANK_NORMAL:
-+ ret = par->fbtftops.blank(par, true);
-+ break;
-+ case FB_BLANK_UNBLANK:
-+ ret = par->fbtftops.blank(par, false);
-+ break;
-+ }
-+ return ret;
-+}
-+
-+static void fbtft_merge_fbtftops(struct fbtft_ops *dst, struct fbtft_ops *src)
-+{
-+ if (src->write)
-+ dst->write = src->write;
-+ if (src->read)
-+ dst->read = src->read;
-+ if (src->write_vmem)
-+ dst->write_vmem = src->write_vmem;
-+ if (src->write_register)
-+ dst->write_register = src->write_register;
-+ if (src->set_addr_win)
-+ dst->set_addr_win = src->set_addr_win;
-+ if (src->reset)
-+ dst->reset = src->reset;
-+ if (src->mkdirty)
-+ dst->mkdirty = src->mkdirty;
-+ if (src->update_display)
-+ dst->update_display = src->update_display;
-+ if (src->init_display)
-+ dst->init_display = src->init_display;
-+ if (src->blank)
-+ dst->blank = src->blank;
-+ if (src->request_gpios_match)
-+ dst->request_gpios_match = src->request_gpios_match;
-+ if (src->request_gpios)
-+ dst->request_gpios = src->request_gpios;
-+ if (src->verify_gpios)
-+ dst->verify_gpios = src->verify_gpios;
-+ if (src->register_backlight)
-+ dst->register_backlight = src->register_backlight;
-+ if (src->unregister_backlight)
-+ dst->unregister_backlight = src->unregister_backlight;
-+ if (src->set_var)
-+ dst->set_var = src->set_var;
-+ if (src->set_gamma)
-+ dst->set_gamma = src->set_gamma;
-+}
-+
-+/**
-+ * fbtft_framebuffer_alloc - creates a new frame buffer info structure
-+ *
-+ * @display: pointer to structure describing the display
-+ * @dev: pointer to the device for this fb, this can be NULL
-+ *
-+ * Creates a new frame buffer info structure.
-+ *
-+ * Also creates and populates the following structures:
-+ * info->fbops
-+ * info->fbdefio
-+ * info->pseudo_palette
-+ * par->fbtftops
-+ * par->txbuf
-+ *
-+ * Returns the new structure, or NULL if an error occurred.
-+ *
-+ */
-+struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,
-+ struct device *dev)
-+{
-+ struct fb_info *info;
-+ struct fbtft_par *par;
-+ struct fb_ops *fbops = NULL;
-+ struct fb_deferred_io *fbdefio = NULL;
-+ struct fbtft_platform_data *pdata = dev->platform_data;
-+ u8 *vmem = NULL;
-+ void *txbuf = NULL;
-+ void *buf = NULL;
-+ unsigned width;
-+ unsigned height;
-+ int txbuflen = display->txbuflen;
-+ unsigned bpp = display->bpp;
-+ unsigned fps = display->fps;
-+ int vmem_size, i;
-+ int *init_sequence = display->init_sequence;
-+ char *gamma = display->gamma;
-+ unsigned long *gamma_curves = NULL;
-+
-+ /* sanity check */
-+ if (display->gamma_num * display->gamma_len > FBTFT_GAMMA_MAX_VALUES_TOTAL) {
-+ dev_err(dev,
-+ "%s: FBTFT_GAMMA_MAX_VALUES_TOTAL=%d is exceeded\n",
-+ __func__, FBTFT_GAMMA_MAX_VALUES_TOTAL);
-+ return NULL;
-+ }
-+
-+ /* defaults */
-+ if (!fps)
-+ fps = 20;
-+ if (!bpp)
-+ bpp = 16;
-+
-+ if (!pdata) {
-+ dev_err(dev, "platform data is missing\n");
-+ return NULL;
-+ }
-+
-+ /* override driver values? */
-+ if (pdata->fps)
-+ fps = pdata->fps;
-+ if (pdata->txbuflen)
-+ txbuflen = pdata->txbuflen;
-+ if (pdata->display.init_sequence)
-+ init_sequence = pdata->display.init_sequence;
-+ if (pdata->gamma)
-+ gamma = pdata->gamma;
-+ if (pdata->display.debug)
-+ display->debug = pdata->display.debug;
-+ if (pdata->display.backlight)
-+ display->backlight = pdata->display.backlight;
-+ if (pdata->display.width)
-+ display->width = pdata->display.width;
-+ if (pdata->display.height)
-+ display->height = pdata->display.height;
-+ if (pdata->display.buswidth)
-+ display->buswidth = pdata->display.buswidth;
-+ if (pdata->display.regwidth)
-+ display->regwidth = pdata->display.regwidth;
-+
-+ display->debug |= debug;
-+ fbtft_expand_debug_value(&display->debug);
-+
-+ switch (pdata->rotate) {
-+ case 90:
-+ case 270:
-+ width = display->height;
-+ height = display->width;
-+ break;
-+ default:
-+ width = display->width;
-+ height = display->height;
-+ }
-+
-+ vmem_size = display->width * display->height * bpp / 8;
-+ vmem = vzalloc(vmem_size);
-+ if (!vmem)
-+ goto alloc_fail;
-+
-+ fbops = devm_kzalloc(dev, sizeof(struct fb_ops), GFP_KERNEL);
-+ if (!fbops)
-+ goto alloc_fail;
-+
-+ fbdefio = devm_kzalloc(dev, sizeof(struct fb_deferred_io), GFP_KERNEL);
-+ if (!fbdefio)
-+ goto alloc_fail;
-+
-+ buf = devm_kzalloc(dev, 128, GFP_KERNEL);
-+ if (!buf)
-+ goto alloc_fail;
-+
-+ if (display->gamma_num && display->gamma_len) {
-+ gamma_curves = devm_kzalloc(dev, display->gamma_num * display->gamma_len * sizeof(gamma_curves[0]),
-+ GFP_KERNEL);
-+ if (!gamma_curves)
-+ goto alloc_fail;
-+ }
-+
-+ info = framebuffer_alloc(sizeof(struct fbtft_par), dev);
-+ if (!info)
-+ goto alloc_fail;
-+
-+ info->screen_base = (u8 __force __iomem *)vmem;
-+ info->fbops = fbops;
-+ info->fbdefio = fbdefio;
-+
-+ fbops->owner = dev->driver->owner;
-+ fbops->fb_read = fb_sys_read;
-+ fbops->fb_write = fbtft_fb_write;
-+ fbops->fb_fillrect = fbtft_fb_fillrect;
-+ fbops->fb_copyarea = fbtft_fb_copyarea;
-+ fbops->fb_imageblit = fbtft_fb_imageblit;
-+ fbops->fb_setcolreg = fbtft_fb_setcolreg;
-+ fbops->fb_blank = fbtft_fb_blank;
-+
-+ fbdefio->delay = HZ/fps;
-+ fbdefio->deferred_io = fbtft_deferred_io;
-+ fb_deferred_io_init(info);
-+
-+ strncpy(info->fix.id, dev->driver->name, 16);
-+ info->fix.type = FB_TYPE_PACKED_PIXELS;
-+ info->fix.visual = FB_VISUAL_TRUECOLOR;
-+ info->fix.xpanstep = 0;
-+ info->fix.ypanstep = 0;
-+ info->fix.ywrapstep = 0;
-+ info->fix.line_length = width*bpp/8;
-+ info->fix.accel = FB_ACCEL_NONE;
-+ info->fix.smem_len = vmem_size;
-+
-+ info->var.rotate = pdata->rotate;
-+ info->var.xres = width;
-+ info->var.yres = height;
-+ info->var.xres_virtual = info->var.xres;
-+ info->var.yres_virtual = info->var.yres;
-+ info->var.bits_per_pixel = bpp;
-+ info->var.nonstd = 1;
-+
-+ /* RGB565 */
-+ info->var.red.offset = 11;
-+ info->var.red.length = 5;
-+ info->var.green.offset = 5;
-+ info->var.green.length = 6;
-+ info->var.blue.offset = 0;
-+ info->var.blue.length = 5;
-+ info->var.transp.offset = 0;
-+ info->var.transp.length = 0;
-+
-+ info->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB;
-+
-+ par = info->par;
-+ par->info = info;
-+ par->pdata = dev->platform_data;
-+ par->debug = display->debug;
-+ par->buf = buf;
-+ spin_lock_init(&par->dirty_lock);
-+ par->bgr = pdata->bgr;
-+ par->startbyte = pdata->startbyte;
-+ par->init_sequence = init_sequence;
-+ par->gamma.curves = gamma_curves;
-+ par->gamma.num_curves = display->gamma_num;
-+ par->gamma.num_values = display->gamma_len;
-+ mutex_init(&par->gamma.lock);
-+ info->pseudo_palette = par->pseudo_palette;
-+
-+ if (par->gamma.curves && gamma) {
-+ if (fbtft_gamma_parse_str(par,
-+ par->gamma.curves, gamma, strlen(gamma)))
-+ goto alloc_fail;
-+ }
-+
-+ /* Transmit buffer */
-+ if (txbuflen == -1)
-+ txbuflen = vmem_size + 2; /* add in case startbyte is used */
-+
-+#ifdef __LITTLE_ENDIAN
-+ if ((!txbuflen) && (bpp > 8))
-+ txbuflen = PAGE_SIZE; /* need buffer for byteswapping */
-+#endif
-+
-+ if (txbuflen > 0) {
-+ if (dma) {
-+ dev->coherent_dma_mask = ~0;
-+ txbuf = dmam_alloc_coherent(dev, txbuflen, &par->txbuf.dma, GFP_DMA);
-+ } else {
-+ txbuf = devm_kzalloc(par->info->device, txbuflen, GFP_KERNEL);
-+ }
-+ if (!txbuf)
-+ goto alloc_fail;
-+ par->txbuf.buf = txbuf;
-+ par->txbuf.len = txbuflen;
-+ }
-+
-+ /* Initialize gpios to disabled */
-+ par->gpio.reset = -1;
-+ par->gpio.dc = -1;
-+ par->gpio.rd = -1;
-+ par->gpio.wr = -1;
-+ par->gpio.cs = -1;
-+ par->gpio.latch = -1;
-+ for (i = 0; i < 16; i++) {
-+ par->gpio.db[i] = -1;
-+ par->gpio.led[i] = -1;
-+ par->gpio.aux[i] = -1;
-+ }
-+
-+ /* default fbtft operations */
-+ par->fbtftops.write = fbtft_write_spi;
-+ par->fbtftops.read = fbtft_read_spi;
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus8;
-+ par->fbtftops.write_register = fbtft_write_reg8_bus8;
-+ par->fbtftops.set_addr_win = fbtft_set_addr_win;
-+ par->fbtftops.reset = fbtft_reset;
-+ par->fbtftops.mkdirty = fbtft_mkdirty;
-+ par->fbtftops.update_display = fbtft_update_display;
-+ par->fbtftops.request_gpios = fbtft_request_gpios;
-+ if (display->backlight)
-+ par->fbtftops.register_backlight = fbtft_register_backlight;
-+
-+ /* use driver provided functions */
-+ fbtft_merge_fbtftops(&par->fbtftops, &display->fbtftops);
-+
-+ return info;
-+
-+alloc_fail:
-+ vfree(vmem);
-+
-+ return NULL;
-+}
-+EXPORT_SYMBOL(fbtft_framebuffer_alloc);
-+
-+/**
-+ * fbtft_framebuffer_release - frees up all memory used by the framebuffer
-+ *
-+ * @info: frame buffer info structure
-+ *
-+ */
-+void fbtft_framebuffer_release(struct fb_info *info)
-+{
-+ fb_deferred_io_cleanup(info);
-+ vfree(info->screen_base);
-+ framebuffer_release(info);
-+}
-+EXPORT_SYMBOL(fbtft_framebuffer_release);
-+
-+/**
-+ * fbtft_register_framebuffer - registers a tft frame buffer device
-+ * @fb_info: frame buffer info structure
-+ *
-+ * Sets SPI driverdata if needed
-+ * Requests needed gpios.
-+ * Initializes display
-+ * Updates display.
-+ * Registers a frame buffer device @fb_info.
-+ *
-+ * Returns negative errno on error, or zero for success.
-+ *
-+ */
-+int fbtft_register_framebuffer(struct fb_info *fb_info)
-+{
-+ int ret;
-+ char text1[50] = "";
-+ char text2[50] = "";
-+ struct fbtft_par *par = fb_info->par;
-+ struct spi_device *spi = par->spi;
-+
-+ /* sanity checks */
-+ if (!par->fbtftops.init_display) {
-+ dev_err(fb_info->device, "missing fbtftops.init_display()\n");
-+ return -EINVAL;
-+ }
-+
-+ if (spi)
-+ spi_set_drvdata(spi, fb_info);
-+ if (par->pdev)
-+ platform_set_drvdata(par->pdev, fb_info);
-+
-+ ret = par->fbtftops.request_gpios(par);
-+ if (ret < 0)
-+ goto reg_fail;
-+
-+ if (par->fbtftops.verify_gpios) {
-+ ret = par->fbtftops.verify_gpios(par);
-+ if (ret < 0)
-+ goto reg_fail;
-+ }
-+
-+ ret = par->fbtftops.init_display(par);
-+ if (ret < 0)
-+ goto reg_fail;
-+ if (par->fbtftops.set_var) {
-+ ret = par->fbtftops.set_var(par);
-+ if (ret < 0)
-+ goto reg_fail;
-+ }
-+
-+ /* update the entire display */
-+ par->fbtftops.update_display(par, 0, par->info->var.yres - 1);
-+
-+ if (par->fbtftops.set_gamma && par->gamma.curves) {
-+ ret = par->fbtftops.set_gamma(par, par->gamma.curves);
-+ if (ret)
-+ goto reg_fail;
-+ }
-+
-+ if (par->fbtftops.register_backlight)
-+ par->fbtftops.register_backlight(par);
-+
-+ ret = register_framebuffer(fb_info);
-+ if (ret < 0)
-+ goto reg_fail;
-+
-+ fbtft_sysfs_init(par);
-+
-+ if (par->txbuf.buf)
-+ sprintf(text1, ", %d KiB %sbuffer memory",
-+ par->txbuf.len >> 10, par->txbuf.dma ? "DMA " : "");
-+ if (spi)
-+ sprintf(text2, ", spi%d.%d at %d MHz", spi->master->bus_num,
-+ spi->chip_select, spi->max_speed_hz/1000000);
-+ dev_info(fb_info->dev,
-+ "%s frame buffer, %dx%d, %d KiB video memory%s, fps=%lu%s\n",
-+ fb_info->fix.id, fb_info->var.xres, fb_info->var.yres,
-+ fb_info->fix.smem_len >> 10, text1,
-+ HZ/fb_info->fbdefio->delay, text2);
-+
-+#ifdef CONFIG_FB_BACKLIGHT
-+ /* Turn on backlight if available */
-+ if (fb_info->bl_dev) {
-+ fb_info->bl_dev->props.power = FB_BLANK_UNBLANK;
-+ fb_info->bl_dev->ops->update_status(fb_info->bl_dev);
-+ }
-+#endif
-+
-+ return 0;
-+
-+reg_fail:
-+ if (par->fbtftops.unregister_backlight)
-+ par->fbtftops.unregister_backlight(par);
-+ if (spi)
-+ spi_set_drvdata(spi, NULL);
-+ if (par->pdev)
-+ platform_set_drvdata(par->pdev, NULL);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(fbtft_register_framebuffer);
-+
-+/**
-+ * fbtft_unregister_framebuffer - releases a tft frame buffer device
-+ * @fb_info: frame buffer info structure
-+ *
-+ * Frees SPI driverdata if needed
-+ * Frees gpios.
-+ * Unregisters frame buffer device.
-+ *
-+ */
-+int fbtft_unregister_framebuffer(struct fb_info *fb_info)
-+{
-+ struct fbtft_par *par = fb_info->par;
-+ struct spi_device *spi = par->spi;
-+ int ret;
-+
-+ if (spi)
-+ spi_set_drvdata(spi, NULL);
-+ if (par->pdev)
-+ platform_set_drvdata(par->pdev, NULL);
-+ if (par->fbtftops.unregister_backlight)
-+ par->fbtftops.unregister_backlight(par);
-+ fbtft_sysfs_exit(par);
-+ ret = unregister_framebuffer(fb_info);
-+ return ret;
-+}
-+EXPORT_SYMBOL(fbtft_unregister_framebuffer);
-+
-+#ifdef CONFIG_OF
-+/**
-+ * fbtft_init_display_dt() - Device Tree init_display() function
-+ * @par: Driver data
-+ *
-+ * Return: 0 if successful, negative if error
-+ */
-+static int fbtft_init_display_dt(struct fbtft_par *par)
-+{
-+ struct device_node *node = par->info->device->of_node;
-+ struct property *prop;
-+ const __be32 *p;
-+ u32 val;
-+ int buf[64], i, j;
-+ char msg[128];
-+ char str[16];
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ if (!node)
-+ return -EINVAL;
-+
-+ prop = of_find_property(node, "init", NULL);
-+ p = of_prop_next_u32(prop, NULL, &val);
-+ if (!p)
-+ return -EINVAL;
-+ while (p) {
-+ if (val & FBTFT_OF_INIT_CMD) {
-+ val &= 0xFFFF;
-+ i = 0;
-+ while (p && !(val & 0xFFFF0000)) {
-+ if (i > 63) {
-+ dev_err(par->info->device,
-+ "%s: Maximum register values exceeded\n",
-+ __func__);
-+ return -EINVAL;
-+ }
-+ buf[i++] = val;
-+ p = of_prop_next_u32(prop, p, &val);
-+ }
-+ /* make debug message */
-+ msg[0] = '\0';
-+ for (j = 0; j < i; j++) {
-+ snprintf(str, 128, " %02X", buf[j]);
-+ strcat(msg, str);
-+ }
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "init: write_register:%s\n", msg);
-+
-+ par->fbtftops.write_register(par, i,
-+ buf[0], buf[1], buf[2], buf[3],
-+ buf[4], buf[5], buf[6], buf[7],
-+ buf[8], buf[9], buf[10], buf[11],
-+ buf[12], buf[13], buf[14], buf[15],
-+ buf[16], buf[17], buf[18], buf[19],
-+ buf[20], buf[21], buf[22], buf[23],
-+ buf[24], buf[25], buf[26], buf[27],
-+ buf[28], buf[29], buf[30], buf[31],
-+ buf[32], buf[33], buf[34], buf[35],
-+ buf[36], buf[37], buf[38], buf[39],
-+ buf[40], buf[41], buf[42], buf[43],
-+ buf[44], buf[45], buf[46], buf[47],
-+ buf[48], buf[49], buf[50], buf[51],
-+ buf[52], buf[53], buf[54], buf[55],
-+ buf[56], buf[57], buf[58], buf[59],
-+ buf[60], buf[61], buf[62], buf[63]);
-+ } else if (val & FBTFT_OF_INIT_DELAY) {
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "init: msleep(%u)\n", val & 0xFFFF);
-+ msleep(val & 0xFFFF);
-+ p = of_prop_next_u32(prop, p, &val);
-+ } else {
-+ dev_err(par->info->device, "illegal init value 0x%X\n",
-+ val);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ return 0;
-+}
-+#endif
-+
-+/**
-+ * fbtft_init_display() - Generic init_display() function
-+ * @par: Driver data
-+ *
-+ * Uses par->init_sequence to do the initialization
-+ *
-+ * Return: 0 if successful, negative if error
-+ */
-+int fbtft_init_display(struct fbtft_par *par)
-+{
-+ int buf[64];
-+ char msg[128];
-+ char str[16];
-+ int i = 0;
-+ int j;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* sanity check */
-+ if (!par->init_sequence) {
-+ dev_err(par->info->device,
-+ "error: init_sequence is not set\n");
-+ return -EINVAL;
-+ }
-+
-+ /* make sure stop marker exists */
-+ for (i = 0; i < FBTFT_MAX_INIT_SEQUENCE; i++)
-+ if (par->init_sequence[i] == -3)
-+ break;
-+ if (i == FBTFT_MAX_INIT_SEQUENCE) {
-+ dev_err(par->info->device,
-+ "missing stop marker at end of init sequence\n");
-+ return -EINVAL;
-+ }
-+
-+ par->fbtftops.reset(par);
-+ if (par->gpio.cs != -1)
-+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */
-+
-+ i = 0;
-+ while (i < FBTFT_MAX_INIT_SEQUENCE) {
-+ if (par->init_sequence[i] == -3) {
-+ /* done */
-+ return 0;
-+ }
-+ if (par->init_sequence[i] >= 0) {
-+ dev_err(par->info->device,
-+ "missing delimiter at position %d\n", i);
-+ return -EINVAL;
-+ }
-+ if (par->init_sequence[i+1] < 0) {
-+ dev_err(par->info->device,
-+ "missing value after delimiter %d at position %d\n",
-+ par->init_sequence[i], i);
-+ return -EINVAL;
-+ }
-+ switch (par->init_sequence[i]) {
-+ case -1:
-+ i++;
-+ /* make debug message */
-+ strcpy(msg, "");
-+ j = i + 1;
-+ while (par->init_sequence[j] >= 0) {
-+ sprintf(str, "0x%02X ", par->init_sequence[j]);
-+ strcat(msg, str);
-+ j++;
-+ }
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "init: write(0x%02X) %s\n",
-+ par->init_sequence[i], msg);
-+
-+ /* Write */
-+ j = 0;
-+ while (par->init_sequence[i] >= 0) {
-+ if (j > 63) {
-+ dev_err(par->info->device,
-+ "%s: Maximum register values exceeded\n",
-+ __func__);
-+ return -EINVAL;
-+ }
-+ buf[j++] = par->init_sequence[i++];
-+ }
-+ par->fbtftops.write_register(par, j,
-+ buf[0], buf[1], buf[2], buf[3],
-+ buf[4], buf[5], buf[6], buf[7],
-+ buf[8], buf[9], buf[10], buf[11],
-+ buf[12], buf[13], buf[14], buf[15],
-+ buf[16], buf[17], buf[18], buf[19],
-+ buf[20], buf[21], buf[22], buf[23],
-+ buf[24], buf[25], buf[26], buf[27],
-+ buf[28], buf[29], buf[30], buf[31],
-+ buf[32], buf[33], buf[34], buf[35],
-+ buf[36], buf[37], buf[38], buf[39],
-+ buf[40], buf[41], buf[42], buf[43],
-+ buf[44], buf[45], buf[46], buf[47],
-+ buf[48], buf[49], buf[50], buf[51],
-+ buf[52], buf[53], buf[54], buf[55],
-+ buf[56], buf[57], buf[58], buf[59],
-+ buf[60], buf[61], buf[62], buf[63]);
-+ break;
-+ case -2:
-+ i++;
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
-+ "init: mdelay(%d)\n", par->init_sequence[i]);
-+ mdelay(par->init_sequence[i++]);
-+ break;
-+ default:
-+ dev_err(par->info->device,
-+ "unknown delimiter %d at position %d\n",
-+ par->init_sequence[i], i);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ dev_err(par->info->device,
-+ "%s: something is wrong. Shouldn't get here.\n", __func__);
-+ return -EINVAL;
-+}
-+EXPORT_SYMBOL(fbtft_init_display);
-+
-+/**
-+ * fbtft_verify_gpios() - Generic verify_gpios() function
-+ * @par: Driver data
-+ *
-+ * Uses @spi, @pdev and @buswidth to determine which GPIOs is needed
-+ *
-+ * Return: 0 if successful, negative if error
-+ */
-+static int fbtft_verify_gpios(struct fbtft_par *par)
-+{
-+ struct fbtft_platform_data *pdata;
-+ int i;
-+
-+ fbtft_par_dbg(DEBUG_VERIFY_GPIOS, par, "%s()\n", __func__);
-+
-+ pdata = par->info->device->platform_data;
-+ if (pdata->display.buswidth != 9 && par->startbyte == 0 && \
-+ par->gpio.dc < 0) {
-+ dev_err(par->info->device,
-+ "Missing info about 'dc' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!par->pdev)
-+ return 0;
-+
-+ if (par->gpio.wr < 0) {
-+ dev_err(par->info->device, "Missing 'wr' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ for (i = 0; i < pdata->display.buswidth; i++) {
-+ if (par->gpio.db[i] < 0) {
-+ dev_err(par->info->device,
-+ "Missing 'db%02d' gpio. Aborting.\n", i);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+/* returns 0 if the property is not present */
-+static u32 fbtft_of_value(struct device_node *node, const char *propname)
-+{
-+ int ret;
-+ u32 val = 0;
-+
-+ ret = of_property_read_u32(node, propname, &val);
-+ if (ret == 0)
-+ pr_info("%s: %s = %u\n", __func__, propname, val);
-+
-+ return val;
-+}
-+
-+static struct fbtft_platform_data *fbtft_probe_dt(struct device *dev)
-+{
-+ struct device_node *node = dev->of_node;
-+ struct fbtft_platform_data *pdata;
-+
-+ if (!node) {
-+ dev_err(dev, "Missing platform data or DT\n");
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
-+ if (!pdata)
-+ return ERR_PTR(-ENOMEM);
-+
-+ pdata->display.width = fbtft_of_value(node, "width");
-+ pdata->display.height = fbtft_of_value(node, "height");
-+ pdata->display.regwidth = fbtft_of_value(node, "regwidth");
-+ pdata->display.buswidth = fbtft_of_value(node, "buswidth");
-+ pdata->display.backlight = fbtft_of_value(node, "backlight");
-+ pdata->display.bpp = fbtft_of_value(node, "bpp");
-+ pdata->display.debug = fbtft_of_value(node, "debug");
-+ pdata->rotate = fbtft_of_value(node, "rotate");
-+ pdata->bgr = of_property_read_bool(node, "bgr");
-+ pdata->fps = fbtft_of_value(node, "fps");
-+ pdata->txbuflen = fbtft_of_value(node, "txbuflen");
-+ pdata->startbyte = fbtft_of_value(node, "startbyte");
-+ of_property_read_string(node, "gamma", (const char **)&pdata->gamma);
-+
-+ if (of_find_property(node, "led-gpios", NULL))
-+ pdata->display.backlight = 1;
-+ if (of_find_property(node, "init", NULL))
-+ pdata->display.fbtftops.init_display = fbtft_init_display_dt;
-+ pdata->display.fbtftops.request_gpios = fbtft_request_gpios_dt;
-+
-+ return pdata;
-+}
-+#else
-+static struct fbtft_platform_data *fbtft_probe_dt(struct device *dev)
-+{
-+ dev_err(dev, "Missing platform data\n");
-+ return ERR_PTR(-EINVAL);
-+}
-+#endif
-+
-+/**
-+ * fbtft_probe_common() - Generic device probe() helper function
-+ * @display: Display properties
-+ * @sdev: SPI device
-+ * @pdev: Platform device
-+ *
-+ * Allocates, initializes and registers a framebuffer
-+ *
-+ * Either @sdev or @pdev should be NULL
-+ *
-+ * Return: 0 if successful, negative if error
-+ */
-+int fbtft_probe_common(struct fbtft_display *display,
-+ struct spi_device *sdev, struct platform_device *pdev)
-+{
-+ struct device *dev;
-+ struct fb_info *info;
-+ struct fbtft_par *par;
-+ struct fbtft_platform_data *pdata;
-+ int ret;
-+
-+ if (sdev)
-+ dev = &sdev->dev;
-+ else
-+ dev = &pdev->dev;
-+
-+ if (unlikely(display->debug & DEBUG_DRIVER_INIT_FUNCTIONS))
-+ dev_info(dev, "%s()\n", __func__);
-+
-+ pdata = dev->platform_data;
-+ if (!pdata) {
-+ pdata = fbtft_probe_dt(dev);
-+ if (IS_ERR(pdata))
-+ return PTR_ERR(pdata);
-+ dev->platform_data = pdata;
-+ }
-+
-+ info = fbtft_framebuffer_alloc(display, dev);
-+ if (!info)
-+ return -ENOMEM;
-+
-+ par = info->par;
-+ par->spi = sdev;
-+ par->pdev = pdev;
-+
-+ if (display->buswidth == 0) {
-+ dev_err(dev, "buswidth is not set\n");
-+ return -EINVAL;
-+ }
-+
-+ /* write register functions */
-+ if (display->regwidth == 8 && display->buswidth == 8) {
-+ par->fbtftops.write_register = fbtft_write_reg8_bus8;
-+ } else
-+ if (display->regwidth == 8 && display->buswidth == 9 && par->spi) {
-+ par->fbtftops.write_register = fbtft_write_reg8_bus9;
-+ } else if (display->regwidth == 16 && display->buswidth == 8) {
-+ par->fbtftops.write_register = fbtft_write_reg16_bus8;
-+ } else if (display->regwidth == 16 && display->buswidth == 16) {
-+ par->fbtftops.write_register = fbtft_write_reg16_bus16;
-+ } else {
-+ dev_warn(dev,
-+ "no default functions for regwidth=%d and buswidth=%d\n",
-+ display->regwidth, display->buswidth);
-+ }
-+
-+ /* write_vmem() functions */
-+ if (display->buswidth == 8)
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus8;
-+ else if (display->buswidth == 9)
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus9;
-+ else if (display->buswidth == 16)
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus16;
-+
-+ /* GPIO write() functions */
-+ if (par->pdev) {
-+ if (display->buswidth == 8)
-+ par->fbtftops.write = fbtft_write_gpio8_wr;
-+ else if (display->buswidth == 16)
-+ par->fbtftops.write = fbtft_write_gpio16_wr;
-+ }
-+
-+ /* 9-bit SPI setup */
-+ if (par->spi && display->buswidth == 9) {
-+ par->spi->bits_per_word = 9;
-+ ret = par->spi->master->setup(par->spi);
-+ if (ret) {
-+ dev_warn(&par->spi->dev,
-+ "9-bit SPI not available, emulating using 8-bit.\n");
-+ par->spi->bits_per_word = 8;
-+ ret = par->spi->master->setup(par->spi);
-+ if (ret)
-+ goto out_release;
-+ /* allocate buffer with room for dc bits */
-+ par->extra = devm_kzalloc(par->info->device,
-+ par->txbuf.len + (par->txbuf.len / 8) + 8,
-+ GFP_KERNEL);
-+ if (!par->extra) {
-+ ret = -ENOMEM;
-+ goto out_release;
-+ }
-+ par->fbtftops.write = fbtft_write_spi_emulate_9;
-+ }
-+ }
-+
-+ if (!par->fbtftops.verify_gpios)
-+ par->fbtftops.verify_gpios = fbtft_verify_gpios;
-+
-+ /* make sure we still use the driver provided functions */
-+ fbtft_merge_fbtftops(&par->fbtftops, &display->fbtftops);
-+
-+ /* use init_sequence if provided */
-+ if (par->init_sequence)
-+ par->fbtftops.init_display = fbtft_init_display;
-+
-+ /* use platform_data provided functions above all */
-+ fbtft_merge_fbtftops(&par->fbtftops, &pdata->display.fbtftops);
-+
-+ ret = fbtft_register_framebuffer(info);
-+ if (ret < 0)
-+ goto out_release;
-+
-+ return 0;
-+
-+out_release:
-+ fbtft_framebuffer_release(info);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(fbtft_probe_common);
-+
-+/**
-+ * fbtft_remove_common() - Generic device remove() helper function
-+ * @dev: Device
-+ * @info: Framebuffer
-+ *
-+ * Unregisters and releases the framebuffer
-+ *
-+ * Return: 0 if successful, negative if error
-+ */
-+int fbtft_remove_common(struct device *dev, struct fb_info *info)
-+{
-+ struct fbtft_par *par;
-+
-+ if (!info)
-+ return -EINVAL;
-+ par = info->par;
-+ if (par)
-+ fbtft_par_dbg(DEBUG_DRIVER_INIT_FUNCTIONS, par,
-+ "%s()\n", __func__);
-+ fbtft_unregister_framebuffer(info);
-+ fbtft_framebuffer_release(info);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(fbtft_remove_common);
-+
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fbtft_device.c linux-rpi/drivers/staging/fbtft/fbtft_device.c
---- linux-3.18.14/drivers/staging/fbtft/fbtft_device.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fbtft_device.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,1444 @@
-+/*
-+ *
-+ * Copyright (C) 2013, Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fbtft_device"
-+
-+#define MAX_GPIOS 32
-+
-+struct spi_device *spi_device;
-+struct platform_device *p_device;
-+
-+static char *name;
-+module_param(name, charp, 0);
-+MODULE_PARM_DESC(name, "Devicename (required). " \
-+"name=list => list all supported devices.");
-+
-+static unsigned rotate;
-+module_param(rotate, uint, 0);
-+MODULE_PARM_DESC(rotate,
-+"Angle to rotate display counter clockwise: 0, 90, 180, 270");
-+
-+static unsigned busnum;
-+module_param(busnum, uint, 0);
-+MODULE_PARM_DESC(busnum, "SPI bus number (default=0)");
-+
-+static unsigned cs;
-+module_param(cs, uint, 0);
-+MODULE_PARM_DESC(cs, "SPI chip select (default=0)");
-+
-+static unsigned speed;
-+module_param(speed, uint, 0);
-+MODULE_PARM_DESC(speed, "SPI speed (override device default)");
-+
-+static int mode = -1;
-+module_param(mode, int, 0);
-+MODULE_PARM_DESC(mode, "SPI mode (override device default)");
-+
-+static char *gpios;
-+module_param(gpios, charp, 0);
-+MODULE_PARM_DESC(gpios,
-+"List of gpios. Comma separated with the form: reset:23,dc:24 " \
-+"(when overriding the default, all gpios must be specified)");
-+
-+static unsigned fps;
-+module_param(fps, uint, 0);
-+MODULE_PARM_DESC(fps, "Frames per second (override driver default)");
-+
-+static char *gamma;
-+module_param(gamma, charp, 0);
-+MODULE_PARM_DESC(gamma,
-+"String representation of Gamma Curve(s). Driver specific.");
-+
-+static int txbuflen;
-+module_param(txbuflen, int, 0);
-+MODULE_PARM_DESC(txbuflen, "txbuflen (override driver default)");
-+
-+static int bgr = -1;
-+module_param(bgr, int, 0);
-+MODULE_PARM_DESC(bgr,
-+"BGR bit (supported by some drivers).");
-+
-+static unsigned startbyte;
-+module_param(startbyte, uint, 0);
-+MODULE_PARM_DESC(startbyte, "Sets the Start byte used by some SPI displays.");
-+
-+static bool custom;
-+module_param(custom, bool, 0);
-+MODULE_PARM_DESC(custom, "Add a custom display device. " \
-+"Use speed= argument to make it a SPI device, else platform_device");
-+
-+static unsigned width;
-+module_param(width, uint, 0);
-+MODULE_PARM_DESC(width, "Display width, used with the custom argument");
-+
-+static unsigned height;
-+module_param(height, uint, 0);
-+MODULE_PARM_DESC(height, "Display height, used with the custom argument");
-+
-+static unsigned buswidth = 8;
-+module_param(buswidth, uint, 0);
-+MODULE_PARM_DESC(buswidth, "Display bus width, used with the custom argument");
-+
-+static int init[FBTFT_MAX_INIT_SEQUENCE];
-+static int init_num;
-+module_param_array(init, int, &init_num, 0);
-+MODULE_PARM_DESC(init, "Init sequence, used with the custom argument");
-+
-+static unsigned long debug;
-+module_param(debug, ulong , 0);
-+MODULE_PARM_DESC(debug,
-+"level: 0-7 (the remaining 29 bits is for advanced usage)");
-+
-+static unsigned verbose = 3;
-+module_param(verbose, uint, 0);
-+MODULE_PARM_DESC(verbose,
-+"0 silent, >0 show gpios, >1 show devices, >2 show devices before (default=3)");
-+
-+
-+struct fbtft_device_display {
-+ char *name;
-+ struct spi_board_info *spi;
-+ struct platform_device *pdev;
-+};
-+
-+static void fbtft_device_pdev_release(struct device *dev);
-+
-+static int write_gpio16_wr_slow(struct fbtft_par *par, void *buf, size_t len);
-+static void adafruit18_green_tab_set_addr_win(struct fbtft_par *par,
-+ int xs, int ys, int xe, int ye);
-+
-+#define ADAFRUIT18_GAMMA \
-+ "02 1c 07 12 37 32 29 2d 29 25 2B 39 00 01 03 10\n" \
-+ "03 1d 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10"
-+
-+static int hy28b_init_sequence[] = {
-+ -1,0x00e7,0x0010,-1,0x0000,0x0001,-1,0x0001,0x0100,-1,0x0002,0x0700,
-+ -1,0x0003,0x1030,-1,0x0004,0x0000,-1,0x0008,0x0207,-1,0x0009,0x0000,
-+ -1,0x000a,0x0000,-1,0x000c,0x0001,-1,0x000d,0x0000,-1,0x000f,0x0000,
-+ -1,0x0010,0x0000,-1,0x0011,0x0007,-1,0x0012,0x0000,-1,0x0013,0x0000,
-+ -2,50,-1,0x0010,0x1590,-1,0x0011,0x0227,-2,50,-1,0x0012,0x009c,-2,50,
-+ -1,0x0013,0x1900,-1,0x0029,0x0023,-1,0x002b,0x000e,-2,50,
-+ -1,0x0020,0x0000,-1,0x0021,0x0000,-2,50,-1,0x0050,0x0000,
-+ -1,0x0051,0x00ef,-1,0x0052,0x0000,-1,0x0053,0x013f,-1,0x0060,0xa700,
-+ -1,0x0061,0x0001,-1,0x006a,0x0000,-1,0x0080,0x0000,-1,0x0081,0x0000,
-+ -1,0x0082,0x0000,-1,0x0083,0x0000,-1,0x0084,0x0000,-1,0x0085,0x0000,
-+ -1,0x0090,0x0010,-1,0x0092,0x0000,-1,0x0093,0x0003,-1,0x0095,0x0110,
-+ -1,0x0097,0x0000,-1,0x0098,0x0000,-1,0x0007,0x0133,-1,0x0020,0x0000,
-+ -1,0x0021,0x0000,-2,100,-3 };
-+
-+#define HY28B_GAMMA \
-+ "04 1F 4 7 7 0 7 7 6 0\n" \
-+ "0F 00 1 7 4 0 0 0 6 7"
-+
-+static int pitft_init_sequence[] = {
-+ -1,0x01,-2,5,-1,0x28,-1,0xEF,0x03,0x80,0x02,-1,0xCF,0x00,0xC1,0x30,
-+ -1,0xED,0x64,0x03,0x12,0x81,-1,0xE8,0x85,0x00,0x78,
-+ -1,0xCB,0x39,0x2C,0x00,0x34,0x02,-1,0xF7,0x20,-1,0xEA,0x00,0x00,
-+ -1,0xC0,0x23,-1,0xC1,0x10,-1,0xC5,0x3e,0x28,-1,0xC7,0x86,-1,0x3A,0x55,
-+ -1,0xB1,0x00,0x18,-1,0xB6,0x08,0x82,0x27,-1,0xF2,0x00,-1,0x26,0x01,
-+ -1,0xE0,0x0F,0x31,0x2B,0x0C,0x0E,0x08,0x4E,0xF1,0x37,0x07,0x10,0x03,
-+ 0x0E,0x09,0x00,-1,0xE1,0x00,0x0E,0x14,0x03,0x11,0x07,0x31,0xC1,0x48,
-+ 0x08,0x0F,0x0C,0x31,0x36,0x0F,-1,0x11,-2,100,-1,0x29,-2,20,-3 };
-+
-+static int waveshare32b_init_sequence[] = {
-+ -1,0xCB,0x39,0x2C,0x00,0x34,0x02,-1,0xCF,0x00,0xC1,0x30,
-+ -1,0xE8,0x85,0x00,0x78,-1,0xEA,0x00,0x00,-1,0xED,0x64,0x03,0x12,0x81,
-+ -1,0xF7,0x20,-1,0xC0,0x23,-1,0xC1,0x10,-1,0xC5,0x3e,0x28,-1,0xC7,0x86,
-+ -1,0x36,0x28,-1,0x3A,0x55,-1,0xB1,0x00,0x18,-1,0xB6,0x08,0x82,0x27,
-+ -1,0xF2,0x00,-1,0x26,0x01,
-+ -1,0xE0,0x0F,0x31,0x2B,0x0C,0x0E,0x08,0x4E,0xF1,0x37,0x07,0x10,0x03,0x0E,0x09,0x00,
-+ -1,0xE1,0x00,0x0E,0x14,0x03,0x11,0x07,0x31,0xC1,0x48,0x08,0x0F,0x0C,0x31,0x36,0x0F,
-+ -1,0x11,-2,120,-1,0x29,-1,0x2c,-3 };
-+
-+/* Supported displays in alphabetical order */
-+static struct fbtft_device_display displays[] = {
-+ {
-+ .name = "adafruit18",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_st7735r",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ .gamma = ADAFRUIT18_GAMMA,
-+ }
-+ }
-+ }, {
-+ .name = "adafruit18_green",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_st7735r",
-+ .max_speed_hz = 4000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ .fbtftops.set_addr_win = \
-+ adafruit18_green_tab_set_addr_win,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ .gamma = ADAFRUIT18_GAMMA,
-+ }
-+ }
-+ }, {
-+ .name = "adafruit22",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_hx8340bn",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 9,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "led", 23 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "adafruit22a",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9340",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "adafruit28",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9341",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "adafruit13m",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ssd1306",
-+ .max_speed_hz = 16000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "agm1264k-fl",
-+ .pdev = &(struct platform_device) {
-+ .name = "fb_agm1264k-fl",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = FBTFT_ONBOARD_BACKLIGHT,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "dogs102",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_uc1701",
-+ .max_speed_hz = 8000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 13 },
-+ { "dc", 6 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "er_tftm050_2",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ra8875",
-+ .max_speed_hz = 5000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ .width = 480,
-+ .height = 272,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "er_tftm070_5",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ra8875",
-+ .max_speed_hz = 5000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ .width = 800,
-+ .height = 480,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "flexfb",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "flexfb",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "flexpfb",
-+ .pdev = &(struct platform_device) {
-+ .name = "flexpfb",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 17 },
-+ { "dc", 1 },
-+ { "wr", 0 },
-+ { "cs", 21 },
-+ { "db00", 9 },
-+ { "db01", 11 },
-+ { "db02", 18 },
-+ { "db03", 23 },
-+ { "db04", 24 },
-+ { "db05", 25 },
-+ { "db06", 8 },
-+ { "db07", 7 },
-+ { "led", 4 },
-+ {},
-+ },
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "freetronicsoled128",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ssd1351",
-+ .max_speed_hz = 20000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = FBTFT_ONBOARD_BACKLIGHT,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 24 },
-+ { "dc", 25 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "hx8353d",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_hx8353d",
-+ .max_speed_hz = 16000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 23 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "hy28a",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9320",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .startbyte = 0b01110000,
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "hy28b",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9325",
-+ .max_speed_hz = 48000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ .init_sequence = hy28b_init_sequence,
-+ },
-+ .startbyte = 0b01110000,
-+ .bgr = true,
-+ .fps= 50,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "led", 18 },
-+ {},
-+ },
-+ .gamma = HY28B_GAMMA,
-+ }
-+ }
-+ }, {
-+ .name = "ili9481",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9481",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .regwidth = 16,
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 22 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "itdb24",
-+ .pdev = &(struct platform_device) {
-+ .name = "fb_s6d1121",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = false,
-+ .gpios = (const struct fbtft_gpio []) {
-+ /* Wiring for LCD adapter kit */
-+ { "reset", 7 },
-+ { "dc", 0 }, /* rev 2: 2 */
-+ { "wr", 1 }, /* rev 2: 3 */
-+ { "cs", 8 },
-+ { "db00", 17 },
-+ { "db01", 18 },
-+ { "db02", 21 }, /* rev 2: 27 */
-+ { "db03", 22 },
-+ { "db04", 23 },
-+ { "db05", 24 },
-+ { "db06", 25 },
-+ { "db07", 4 },
-+ {}
-+ },
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "itdb28",
-+ .pdev = &(struct platform_device) {
-+ .name = "fb_ili9325",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "itdb28_spi",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9325",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "mi0283qt-2",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_hx8347d",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .startbyte = 0b01110000,
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "mi0283qt-9a",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9341",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 9,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "mi0283qt-v2",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_watterott",
-+ .max_speed_hz = 4000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "nokia3310",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_pcd8544",
-+ .max_speed_hz = 400000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 23 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "nokia3310a",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_tls8204",
-+ .max_speed_hz = 1000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 23 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "piscreen",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9486",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .regwidth = 16,
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 22 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "pitft",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9340",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .chip_select = 0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ .init_sequence = pitft_init_sequence,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "dc", 25 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "pioled",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ssd1351",
-+ .max_speed_hz = 20000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 24 },
-+ { "dc", 25 },
-+ {},
-+ },
-+ .gamma = "0 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 2 " \
-+ "2 2 2 2 2 2 2 3 " \
-+ "3 3 3 3 3 3 3 3 " \
-+ "3 3 3 3 3 3 3 3 " \
-+ "3 3 3 4 4 4 4 4 " \
-+ "4 4 4 4 4 4 4"
-+ }
-+ }
-+ }, {
-+ .name = "rpi-display",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9341",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 23 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "s6d02a1",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_s6d02a1",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 23 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "sainsmart18",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_st7735r",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "sainsmart32",
-+ .pdev = &(struct platform_device) {
-+ .name = "fb_ssd1289",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 16,
-+ .txbuflen = -2, /* disable buffer */
-+ .backlight = 1,
-+ .fbtftops.write = write_gpio16_wr_slow,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ },
-+ },
-+ }
-+ }, {
-+ .name = "sainsmart32_fast",
-+ .pdev = &(struct platform_device) {
-+ .name = "fb_ssd1289",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 16,
-+ .txbuflen = -2, /* disable buffer */
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ },
-+ },
-+ }
-+ }, {
-+ .name = "sainsmart32_latched",
-+ .pdev = &(struct platform_device) {
-+ .name = "fb_ssd1289",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 16,
-+ .txbuflen = -2, /* disable buffer */
-+ .backlight = 1,
-+ .fbtftops.write = \
-+ fbtft_write_gpio16_wr_latched,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ },
-+ },
-+ }
-+ }, {
-+ .name = "sainsmart32_spi",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ssd1289",
-+ .max_speed_hz = 16000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "spidev",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "spidev",
-+ .max_speed_hz = 500000,
-+ .bus_num = 0,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "ssd1331",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ssd1331",
-+ .max_speed_hz = 20000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 24 },
-+ { "dc", 25 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "tinylcd35",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_tinylcd",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "tm022hdh26",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9341",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 25 },
-+ { "dc", 24 },
-+ { "led", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "tontec35_9481", /* boards before 02 July 2014 */
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9481",
-+ .max_speed_hz = 128000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 15 },
-+ { "dc", 25 },
-+ { "led_", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "tontec35_9486", /* boards after 02 July 2014 */
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9486",
-+ .max_speed_hz = 128000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 15 },
-+ { "dc", 25 },
-+ { "led_", 18 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "upd161704",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_upd161704",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 24 },
-+ { "dc", 25 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "waveshare32b",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_ili9340",
-+ .max_speed_hz = 48000000,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ .backlight = 1,
-+ .init_sequence = waveshare32b_init_sequence,
-+ },
-+ .bgr = true,
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 27 },
-+ { "dc", 22 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ .name = "waveshare22",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "fb_bd663474",
-+ .max_speed_hz = 32000000,
-+ .mode = SPI_MODE_3,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .display = {
-+ .buswidth = 8,
-+ },
-+ .gpios = (const struct fbtft_gpio []) {
-+ { "reset", 24 },
-+ { "dc", 25 },
-+ {},
-+ },
-+ }
-+ }
-+ }, {
-+ /* This should be the last item.
-+ Used with the custom argument */
-+ .name = "",
-+ .spi = &(struct spi_board_info) {
-+ .modalias = "",
-+ .max_speed_hz = 0,
-+ .mode = SPI_MODE_0,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ }
-+ },
-+ .pdev = &(struct platform_device) {
-+ .name = "",
-+ .id = 0,
-+ .dev = {
-+ .release = fbtft_device_pdev_release,
-+ .platform_data = &(struct fbtft_platform_data) {
-+ .gpios = (const struct fbtft_gpio []) {
-+ {},
-+ },
-+ },
-+ },
-+ },
-+ }
-+};
-+
-+static int write_gpio16_wr_slow(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ u16 data;
-+ int i;
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ static u16 prev_data;
-+#endif
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ while (len) {
-+ data = *(u16 *) buf;
-+
-+ /* Start writing by pulling down /WR */
-+ gpio_set_value(par->gpio.wr, 0);
-+
-+ /* Set data */
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ if (data == prev_data) {
-+ gpio_set_value(par->gpio.wr, 0); /* used as delay */
-+ } else {
-+ for (i = 0; i < 16; i++) {
-+ if ((data & 1) != (prev_data & 1))
-+ gpio_set_value(par->gpio.db[i],
-+ (data & 1));
-+ data >>= 1;
-+ prev_data >>= 1;
-+ }
-+ }
-+#else
-+ for (i = 0; i < 16; i++) {
-+ gpio_set_value(par->gpio.db[i], (data & 1));
-+ data >>= 1;
-+ }
-+#endif
-+
-+ /* Pullup /WR */
-+ gpio_set_value(par->gpio.wr, 1);
-+
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ prev_data = *(u16 *) buf;
-+#endif
-+ buf += 2;
-+ len -= 2;
-+ }
-+
-+ return 0;
-+}
-+
-+static void adafruit18_green_tab_set_addr_win(struct fbtft_par *par,
-+ int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+ write_reg(par, 0x2A, 0, xs + 2, 0, xe + 2);
-+ write_reg(par, 0x2B, 0, ys + 1, 0, ye + 1);
-+ write_reg(par, 0x2C);
-+}
-+
-+/* used if gpios parameter is present */
-+static struct fbtft_gpio fbtft_device_param_gpios[MAX_GPIOS+1] = { };
-+
-+static void fbtft_device_pdev_release(struct device *dev)
-+{
-+/* Needed to silence this message:
-+Device 'xxx' does not have a release() function, it is broken and must be fixed
-+*/
-+}
-+
-+static int spi_device_found(struct device *dev, void *data)
-+{
-+ struct spi_device *spi = container_of(dev, struct spi_device, dev);
-+
-+ pr_info(DRVNAME": %s %s %dkHz %d bits mode=0x%02X\n",
-+ spi->modalias, dev_name(dev), spi->max_speed_hz/1000,
-+ spi->bits_per_word, spi->mode);
-+
-+ return 0;
-+}
-+
-+static void pr_spi_devices(void)
-+{
-+ pr_info(DRVNAME": SPI devices registered:\n");
-+ bus_for_each_dev(&spi_bus_type, NULL, NULL, spi_device_found);
-+}
-+
-+static int p_device_found(struct device *dev, void *data)
-+{
-+ struct platform_device
-+ *pdev = container_of(dev, struct platform_device, dev);
-+
-+ if (strstr(pdev->name, "fb"))
-+ pr_info(DRVNAME": %s id=%d pdata? %s\n",
-+ pdev->name, pdev->id,
-+ pdev->dev.platform_data ? "yes" : "no");
-+
-+ return 0;
-+}
-+
-+static void pr_p_devices(void)
-+{
-+ pr_info(DRVNAME": 'fb' Platform devices registered:\n");
-+ bus_for_each_dev(&platform_bus_type, NULL, NULL, p_device_found);
-+}
-+
-+#ifdef MODULE
-+static void fbtft_device_spi_delete(struct spi_master *master, unsigned cs)
-+{
-+ struct device *dev;
-+ char str[32];
-+
-+ snprintf(str, sizeof(str), "%s.%u", dev_name(&master->dev), cs);
-+
-+ dev = bus_find_device_by_name(&spi_bus_type, NULL, str);
-+ if (dev) {
-+ if (verbose)
-+ pr_info(DRVNAME": Deleting %s\n", str);
-+ device_del(dev);
-+ }
-+}
-+
-+static int fbtft_device_spi_device_register(struct spi_board_info *spi)
-+{
-+ struct spi_master *master;
-+
-+ master = spi_busnum_to_master(spi->bus_num);
-+ if (!master) {
-+ pr_err(DRVNAME ": spi_busnum_to_master(%d) returned NULL\n",
-+ spi->bus_num);
-+ return -EINVAL;
-+ }
-+ /* make sure it's available */
-+ fbtft_device_spi_delete(master, spi->chip_select);
-+ spi_device = spi_new_device(master, spi);
-+ put_device(&master->dev);
-+ if (!spi_device) {
-+ pr_err(DRVNAME ": spi_new_device() returned NULL\n");
-+ return -EPERM;
-+ }
-+ return 0;
-+}
-+#else
-+static int fbtft_device_spi_device_register(struct spi_board_info *spi)
-+{
-+ return spi_register_board_info(spi, 1);
-+}
-+#endif
-+
-+static int __init fbtft_device_init(void)
-+{
-+ struct spi_board_info *spi = NULL;
-+ struct fbtft_platform_data *pdata;
-+ const struct fbtft_gpio *gpio = NULL;
-+ char *p_gpio, *p_name, *p_num;
-+ bool found = false;
-+ int i = 0;
-+ long val;
-+ int ret = 0;
-+
-+ pr_debug("\n\n"DRVNAME": init\n");
-+
-+ if (name == NULL) {
-+#ifdef MODULE
-+ pr_err(DRVNAME": missing module parameter: 'name'\n");
-+ return -EINVAL;
-+#else
-+ return 0;
-+#endif
-+ }
-+
-+ if (init_num > FBTFT_MAX_INIT_SEQUENCE) {
-+ pr_err(DRVNAME \
-+ ": init parameter: exceeded max array size: %d\n",
-+ FBTFT_MAX_INIT_SEQUENCE);
-+ return -EINVAL;
-+ }
-+
-+ /* parse module parameter: gpios */
-+ while ((p_gpio = strsep(&gpios, ","))) {
-+ if (strchr(p_gpio, ':') == NULL) {
-+ pr_err(DRVNAME \
-+ ": error: missing ':' in gpios parameter: %s\n",
-+ p_gpio);
-+ return -EINVAL;
-+ }
-+ p_num = p_gpio;
-+ p_name = strsep(&p_num, ":");
-+ if (p_name == NULL || p_num == NULL) {
-+ pr_err(DRVNAME \
-+ ": something bad happened parsing gpios parameter: %s\n",
-+ p_gpio);
-+ return -EINVAL;
-+ }
-+ ret = kstrtol(p_num, 10, &val);
-+ if (ret) {
-+ pr_err(DRVNAME \
-+ ": could not parse number in gpios parameter: %s:%s\n",
-+ p_name, p_num);
-+ return -EINVAL;
-+ }
-+ strcpy(fbtft_device_param_gpios[i].name, p_name);
-+ fbtft_device_param_gpios[i++].gpio = (int) val;
-+ if (i == MAX_GPIOS) {
-+ pr_err(DRVNAME \
-+ ": gpios parameter: exceeded max array size: %d\n",
-+ MAX_GPIOS);
-+ return -EINVAL;
-+ }
-+ }
-+ if (fbtft_device_param_gpios[0].name[0])
-+ gpio = fbtft_device_param_gpios;
-+
-+ if (verbose > 2)
-+ pr_spi_devices(); /* print list of registered SPI devices */
-+
-+ if (verbose > 2)
-+ pr_p_devices(); /* print list of 'fb' platform devices */
-+
-+ pr_debug(DRVNAME": name='%s', busnum=%d, cs=%d\n", name, busnum, cs);
-+
-+ if (rotate > 0 && rotate < 4) {
-+ rotate = (4 - rotate) * 90;
-+ pr_warn("argument 'rotate' should be an angle. Values 1-3 is deprecated. Setting it to %d.\n",
-+ rotate);
-+ }
-+ if (rotate != 0 && rotate != 90 && rotate != 180 && rotate != 270) {
-+ pr_warn("argument 'rotate' illegal value: %d. Setting it to 0.\n",
-+ rotate);
-+ rotate = 0;
-+ }
-+
-+ /* name=list lists all supported displays */
-+ if (strncmp(name, "list", 32) == 0) {
-+ pr_info(DRVNAME": Supported displays:\n");
-+
-+ for (i = 0; i < ARRAY_SIZE(displays); i++)
-+ pr_info(DRVNAME": %s\n", displays[i].name);
-+ return -ECANCELED;
-+ }
-+
-+ if (custom) {
-+ i = ARRAY_SIZE(displays) - 1;
-+ displays[i].name = name;
-+ if (speed == 0) {
-+ displays[i].pdev->name = name;
-+ displays[i].spi = NULL;
-+ } else {
-+ strncpy(displays[i].spi->modalias, name, SPI_NAME_SIZE);
-+ displays[i].pdev = NULL;
-+ }
-+ }
-+
-+ for (i = 0; i < ARRAY_SIZE(displays); i++) {
-+ if (strncmp(name, displays[i].name, 32) == 0) {
-+ if (displays[i].spi) {
-+ spi = displays[i].spi;
-+ spi->chip_select = cs;
-+ spi->bus_num = busnum;
-+ if (speed)
-+ spi->max_speed_hz = speed;
-+ if (mode != -1)
-+ spi->mode = mode;
-+ pdata = (void *)spi->platform_data;
-+ } else if (displays[i].pdev) {
-+ p_device = displays[i].pdev;
-+ pdata = p_device->dev.platform_data;
-+ } else {
-+ pr_err(DRVNAME": broken displays array\n");
-+ return -EINVAL;
-+ }
-+
-+ pdata->rotate = rotate;
-+ if (bgr == 0)
-+ pdata->bgr = false;
-+ else if (bgr == 1)
-+ pdata->bgr = true;
-+ if (startbyte)
-+ pdata->startbyte = startbyte;
-+ if (gamma)
-+ pdata->gamma = gamma;
-+ pdata->display.debug = debug;
-+ if (fps)
-+ pdata->fps = fps;
-+ if (txbuflen)
-+ pdata->txbuflen = txbuflen;
-+ if (init_num)
-+ pdata->display.init_sequence = init;
-+ if (gpio)
-+ pdata->gpios = gpio;
-+ if (custom) {
-+ pdata->display.width = width;
-+ pdata->display.height = height;
-+ pdata->display.buswidth = buswidth;
-+ pdata->display.backlight = 1;
-+ }
-+
-+ if (displays[i].spi) {
-+ ret = fbtft_device_spi_device_register(spi);
-+ if (ret) {
-+ pr_err(DRVNAME \
-+ ": failed to register SPI device\n");
-+ return ret;
-+ }
-+ found = true;
-+ break;
-+ } else {
-+ ret = platform_device_register(p_device);
-+ if (ret < 0) {
-+ pr_err(DRVNAME \
-+ ": platform_device_register() returned %d\n",
-+ ret);
-+ return ret;
-+ }
-+ found = true;
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (!found) {
-+ pr_err(DRVNAME": display not supported: '%s'\n", name);
-+ return -EINVAL;
-+ }
-+
-+ if (verbose && pdata && pdata->gpios) {
-+ gpio = pdata->gpios;
-+ pr_info(DRVNAME": GPIOS used by '%s':\n", name);
-+ found = false;
-+ while (verbose && gpio->name[0]) {
-+ pr_info(DRVNAME": '%s' = GPIO%d\n",
-+ gpio->name, gpio->gpio);
-+ gpio++;
-+ found = true;
-+ }
-+ if (!found)
-+ pr_info(DRVNAME": (none)\n");
-+ }
-+
-+ if (spi_device && (verbose > 1))
-+ pr_spi_devices();
-+ if (p_device && (verbose > 1))
-+ pr_p_devices();
-+
-+ return 0;
-+}
-+
-+static void __exit fbtft_device_exit(void)
-+{
-+ pr_debug(DRVNAME" - exit\n");
-+
-+ if (spi_device) {
-+ device_del(&spi_device->dev);
-+ kfree(spi_device);
-+ }
-+
-+ if (p_device)
-+ platform_device_unregister(p_device);
-+
-+}
-+
-+arch_initcall(fbtft_device_init);
-+module_exit(fbtft_device_exit);
-+
-+MODULE_DESCRIPTION("Add a FBTFT device.");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fbtft.h linux-rpi/drivers/staging/fbtft/fbtft.h
---- linux-3.18.14/drivers/staging/fbtft/fbtft.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fbtft.h 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,447 @@
-+/*
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#ifndef __LINUX_FBTFT_H
-+#define __LINUX_FBTFT_H
-+
-+#include <linux/fb.h>
-+#include <linux/spinlock.h>
-+#include <linux/spi/spi.h>
-+#include <linux/platform_device.h>
-+
-+
-+#define FBTFT_NOP 0x00
-+#define FBTFT_SWRESET 0x01
-+#define FBTFT_RDDID 0x04
-+#define FBTFT_RDDST 0x09
-+#define FBTFT_CASET 0x2A
-+#define FBTFT_RASET 0x2B
-+#define FBTFT_RAMWR 0x2C
-+
-+#define FBTFT_ONBOARD_BACKLIGHT 2
-+
-+#define FBTFT_GPIO_NO_MATCH 0xFFFF
-+#define FBTFT_GPIO_NAME_SIZE 32
-+#define FBTFT_MAX_INIT_SEQUENCE 512
-+#define FBTFT_GAMMA_MAX_VALUES_TOTAL 128
-+
-+#define FBTFT_OF_INIT_CMD BIT(24)
-+#define FBTFT_OF_INIT_DELAY BIT(25)
-+
-+/**
-+ * struct fbtft_gpio - Structure that holds one pinname to gpio mapping
-+ * @name: pinname (reset, dc, etc.)
-+ * @gpio: GPIO number
-+ *
-+ */
-+struct fbtft_gpio {
-+ char name[FBTFT_GPIO_NAME_SIZE];
-+ unsigned gpio;
-+};
-+
-+struct fbtft_par;
-+
-+/**
-+ * struct fbtft_ops - FBTFT operations structure
-+ * @write: Writes to interface bus
-+ * @read: Reads from interface bus
-+ * @write_vmem: Writes video memory to display
-+ * @write_reg: Writes to controller register
-+ * @set_addr_win: Set the GRAM update window
-+ * @reset: Reset the LCD controller
-+ * @mkdirty: Marks display lines for update
-+ * @update_display: Updates the display
-+ * @init_display: Initializes the display
-+ * @blank: Blank the display (optional)
-+ * @request_gpios_match: Do pinname to gpio matching
-+ * @request_gpios: Request gpios from the kernel
-+ * @free_gpios: Free previously requested gpios
-+ * @verify_gpios: Verify that necessary gpios is present (optional)
-+ * @register_backlight: Used to register backlight device (optional)
-+ * @unregister_backlight: Unregister backlight device (optional)
-+ * @set_var: Configure LCD with values from variables like @rotate and @bgr
-+ * (optional)
-+ * @set_gamma: Set Gamma curve (optional)
-+ *
-+ * Most of these operations have default functions assigned to them in
-+ * fbtft_framebuffer_alloc()
-+ */
-+struct fbtft_ops {
-+ int (*write)(struct fbtft_par *par, void *buf, size_t len);
-+ int (*read)(struct fbtft_par *par, void *buf, size_t len);
-+ int (*write_vmem)(struct fbtft_par *par, size_t offset, size_t len);
-+ void (*write_register)(struct fbtft_par *par, int len, ...);
-+
-+ void (*set_addr_win)(struct fbtft_par *par,
-+ int xs, int ys, int xe, int ye);
-+ void (*reset)(struct fbtft_par *par);
-+ void (*mkdirty)(struct fb_info *info, int from, int to);
-+ void (*update_display)(struct fbtft_par *par,
-+ unsigned start_line, unsigned end_line);
-+ int (*init_display)(struct fbtft_par *par);
-+ int (*blank)(struct fbtft_par *par, bool on);
-+
-+ unsigned long (*request_gpios_match)(struct fbtft_par *par,
-+ const struct fbtft_gpio *gpio);
-+ int (*request_gpios)(struct fbtft_par *par);
-+ int (*verify_gpios)(struct fbtft_par *par);
-+
-+ void (*register_backlight)(struct fbtft_par *par);
-+ void (*unregister_backlight)(struct fbtft_par *par);
-+
-+ int (*set_var)(struct fbtft_par *par);
-+ int (*set_gamma)(struct fbtft_par *par, unsigned long *curves);
-+};
-+
-+/**
-+ * struct fbtft_display - Describes the display properties
-+ * @width: Width of display in pixels
-+ * @height: Height of display in pixels
-+ * @regwidth: LCD Controller Register width in bits
-+ * @buswidth: Display interface bus width in bits
-+ * @backlight: Backlight type.
-+ * @fbtftops: FBTFT operations provided by driver or device (platform_data)
-+ * @bpp: Bits per pixel
-+ * @fps: Frames per second
-+ * @txbuflen: Size of transmit buffer
-+ * @init_sequence: Pointer to LCD initialization array
-+ * @gamma: String representation of Gamma curve(s)
-+ * @gamma_num: Number of Gamma curves
-+ * @gamma_len: Number of values per Gamma curve
-+ * @debug: Initial debug value
-+ *
-+ * This structure is not stored by FBTFT except for init_sequence.
-+ */
-+struct fbtft_display {
-+ unsigned width;
-+ unsigned height;
-+ unsigned regwidth;
-+ unsigned buswidth;
-+ unsigned backlight;
-+ struct fbtft_ops fbtftops;
-+ unsigned bpp;
-+ unsigned fps;
-+ int txbuflen;
-+ int *init_sequence;
-+ char *gamma;
-+ int gamma_num;
-+ int gamma_len;
-+ unsigned long debug;
-+};
-+
-+/**
-+ * struct fbtft_platform_data - Passes display specific data to the driver
-+ * @display: Display properties
-+ * @gpios: Pointer to an array of piname to gpio mappings
-+ * @rotate: Display rotation angle
-+ * @bgr: LCD Controller BGR bit
-+ * @fps: Frames per second (this will go away, use @fps in @fbtft_display)
-+ * @txbuflen: Size of transmit buffer
-+ * @startbyte: When set, enables use of Startbyte in transfers
-+ * @gamma: String representation of Gamma curve(s)
-+ * @extra: A way to pass extra info
-+ */
-+struct fbtft_platform_data {
-+ struct fbtft_display display;
-+ const struct fbtft_gpio *gpios;
-+ unsigned rotate;
-+ bool bgr;
-+ unsigned fps;
-+ int txbuflen;
-+ u8 startbyte;
-+ char *gamma;
-+ void *extra;
-+};
-+
-+/**
-+ * struct fbtft_par - Main FBTFT data structure
-+ *
-+ * This structure holds all relevant data to operate the display
-+ *
-+ * See sourcefile for documentation since nested structs is not
-+ * supported by kernel-doc.
-+ *
-+ */
-+/* @spi: Set if it is a SPI device
-+ * @pdev: Set if it is a platform device
-+ * @info: Pointer to framebuffer fb_info structure
-+ * @pdata: Pointer to platform data
-+ * @ssbuf: Not used
-+ * @pseudo_palette: Used by fb_set_colreg()
-+ * @txbuf.buf: Transmit buffer
-+ * @txbuf.len: Transmit buffer length
-+ * @buf: Small buffer used when writing init data over SPI
-+ * @startbyte: Used by some controllers when in SPI mode.
-+ * Format: 6 bit Device id + RS bit + RW bit
-+ * @fbtftops: FBTFT operations provided by driver or device (platform_data)
-+ * @dirty_lock: Protects dirty_lines_start and dirty_lines_end
-+ * @dirty_lines_start: Where to begin updating display
-+ * @dirty_lines_end: Where to end updating display
-+ * @gpio.reset: GPIO used to reset display
-+ * @gpio.dc: Data/Command signal, also known as RS
-+ * @gpio.rd: Read latching signal
-+ * @gpio.wr: Write latching signal
-+ * @gpio.latch: Bus latch signal, eg. 16->8 bit bus latch
-+ * @gpio.cs: LCD Chip Select with parallel interface bus
-+ * @gpio.db[16]: Parallel databus
-+ * @gpio.led[16]: Led control signals
-+ * @gpio.aux[16]: Auxillary signals, not used by core
-+ * @init_sequence: Pointer to LCD initialization array
-+ * @gamma.lock: Mutex for Gamma curve locking
-+ * @gamma.curves: Pointer to Gamma curve array
-+ * @gamma.num_values: Number of values per Gamma curve
-+ * @gamma.num_curves: Number of Gamma curves
-+ * @debug: Pointer to debug value
-+ * @current_debug:
-+ * @first_update_done: Used to only time the first display update
-+ * @update_time: Used to calculate 'fps' in debug output
-+ * @bgr: BGR mode/\n
-+ * @extra: Extra info needed by driver
-+ */
-+struct fbtft_par {
-+ struct spi_device *spi;
-+ struct platform_device *pdev;
-+ struct fb_info *info;
-+ struct fbtft_platform_data *pdata;
-+ u16 *ssbuf;
-+ u32 pseudo_palette[16];
-+ struct {
-+ void *buf;
-+ dma_addr_t dma;
-+ size_t len;
-+ } txbuf;
-+ u8 *buf;
-+ u8 startbyte;
-+ struct fbtft_ops fbtftops;
-+ spinlock_t dirty_lock;
-+ unsigned dirty_lines_start;
-+ unsigned dirty_lines_end;
-+ struct {
-+ int reset;
-+ int dc;
-+ int rd;
-+ int wr;
-+ int latch;
-+ int cs;
-+ int db[16];
-+ int led[16];
-+ int aux[16];
-+ } gpio;
-+ int *init_sequence;
-+ struct {
-+ struct mutex lock;
-+ unsigned long *curves;
-+ int num_values;
-+ int num_curves;
-+ } gamma;
-+ unsigned long debug;
-+ bool first_update_done;
-+ struct timespec update_time;
-+ bool bgr;
-+ void *extra;
-+};
-+
-+#define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int))
-+
-+#define write_reg(par, ...) \
-+do { \
-+ par->fbtftops.write_register(par, NUMARGS(__VA_ARGS__), __VA_ARGS__); \
-+} while (0)
-+
-+/* fbtft-core.c */
-+extern void fbtft_dbg_hex(const struct device *dev,
-+ int groupsize, void *buf, size_t len, const char *fmt, ...);
-+extern struct fb_info *fbtft_framebuffer_alloc(struct fbtft_display *display,
-+ struct device *dev);
-+extern void fbtft_framebuffer_release(struct fb_info *info);
-+extern int fbtft_register_framebuffer(struct fb_info *fb_info);
-+extern int fbtft_unregister_framebuffer(struct fb_info *fb_info);
-+extern void fbtft_register_backlight(struct fbtft_par *par);
-+extern void fbtft_unregister_backlight(struct fbtft_par *par);
-+extern int fbtft_init_display(struct fbtft_par *par);
-+extern int fbtft_probe_common(struct fbtft_display *display,
-+ struct spi_device *sdev, struct platform_device *pdev);
-+extern int fbtft_remove_common(struct device *dev, struct fb_info *info);
-+
-+/* fbtft-io.c */
-+extern int fbtft_write_spi(struct fbtft_par *par, void *buf, size_t len);
-+extern int fbtft_write_spi_emulate_9(struct fbtft_par *par,
-+ void *buf, size_t len);
-+extern int fbtft_read_spi(struct fbtft_par *par, void *buf, size_t len);
-+extern int fbtft_write_gpio8_wr(struct fbtft_par *par, void *buf, size_t len);
-+extern int fbtft_write_gpio16_wr(struct fbtft_par *par, void *buf, size_t len);
-+extern int fbtft_write_gpio16_wr_latched(struct fbtft_par *par,
-+ void *buf, size_t len);
-+
-+/* fbtft-bus.c */
-+extern int fbtft_write_vmem8_bus8(struct fbtft_par *par, size_t offset, size_t len);
-+extern int fbtft_write_vmem16_bus16(struct fbtft_par *par, size_t offset, size_t len);
-+extern int fbtft_write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len);
-+extern int fbtft_write_vmem16_bus9(struct fbtft_par *par, size_t offset, size_t len);
-+extern void fbtft_write_reg8_bus8(struct fbtft_par *par, int len, ...);
-+extern void fbtft_write_reg8_bus9(struct fbtft_par *par, int len, ...);
-+extern void fbtft_write_reg16_bus8(struct fbtft_par *par, int len, ...);
-+extern void fbtft_write_reg16_bus16(struct fbtft_par *par, int len, ...);
-+
-+
-+#define FBTFT_REGISTER_DRIVER(_name, _compatible, _display) \
-+ \
-+static int fbtft_driver_probe_spi(struct spi_device *spi) \
-+{ \
-+ return fbtft_probe_common(_display, spi, NULL); \
-+} \
-+ \
-+static int fbtft_driver_remove_spi(struct spi_device *spi) \
-+{ \
-+ struct fb_info *info = spi_get_drvdata(spi); \
-+ \
-+ return fbtft_remove_common(&spi->dev, info); \
-+} \
-+ \
-+static int fbtft_driver_probe_pdev(struct platform_device *pdev) \
-+{ \
-+ return fbtft_probe_common(_display, NULL, pdev); \
-+} \
-+ \
-+static int fbtft_driver_remove_pdev(struct platform_device *pdev) \
-+{ \
-+ struct fb_info *info = platform_get_drvdata(pdev); \
-+ \
-+ return fbtft_remove_common(&pdev->dev, info); \
-+} \
-+ \
-+static const struct of_device_id dt_ids[] = { \
-+ { .compatible = _compatible }, \
-+ {}, \
-+}; \
-+ \
-+MODULE_DEVICE_TABLE(of, dt_ids); \
-+ \
-+ \
-+static struct spi_driver fbtft_driver_spi_driver = { \
-+ .driver = { \
-+ .name = _name, \
-+ .owner = THIS_MODULE, \
-+ .of_match_table = of_match_ptr(dt_ids), \
-+ }, \
-+ .probe = fbtft_driver_probe_spi, \
-+ .remove = fbtft_driver_remove_spi, \
-+}; \
-+ \
-+static struct platform_driver fbtft_driver_platform_driver = { \
-+ .driver = { \
-+ .name = _name, \
-+ .owner = THIS_MODULE, \
-+ .of_match_table = of_match_ptr(dt_ids), \
-+ }, \
-+ .probe = fbtft_driver_probe_pdev, \
-+ .remove = fbtft_driver_remove_pdev, \
-+}; \
-+ \
-+static int __init fbtft_driver_module_init(void) \
-+{ \
-+ int ret; \
-+ \
-+ ret = spi_register_driver(&fbtft_driver_spi_driver); \
-+ if (ret < 0) \
-+ return ret; \
-+ return platform_driver_register(&fbtft_driver_platform_driver); \
-+} \
-+ \
-+static void __exit fbtft_driver_module_exit(void) \
-+{ \
-+ spi_unregister_driver(&fbtft_driver_spi_driver); \
-+ platform_driver_unregister(&fbtft_driver_platform_driver); \
-+} \
-+ \
-+module_init(fbtft_driver_module_init); \
-+module_exit(fbtft_driver_module_exit);
-+
-+
-+/* Debug macros */
-+
-+/* shorthand debug levels */
-+#define DEBUG_LEVEL_1 DEBUG_REQUEST_GPIOS
-+#define DEBUG_LEVEL_2 (DEBUG_LEVEL_1 | DEBUG_DRIVER_INIT_FUNCTIONS | DEBUG_TIME_FIRST_UPDATE)
-+#define DEBUG_LEVEL_3 (DEBUG_LEVEL_2 | DEBUG_RESET | DEBUG_INIT_DISPLAY | DEBUG_BLANK | DEBUG_REQUEST_GPIOS | DEBUG_FREE_GPIOS | DEBUG_VERIFY_GPIOS | DEBUG_BACKLIGHT | DEBUG_SYSFS)
-+#define DEBUG_LEVEL_4 (DEBUG_LEVEL_2 | DEBUG_FB_READ | DEBUG_FB_WRITE | DEBUG_FB_FILLRECT | DEBUG_FB_COPYAREA | DEBUG_FB_IMAGEBLIT | DEBUG_FB_BLANK)
-+#define DEBUG_LEVEL_5 (DEBUG_LEVEL_3 | DEBUG_UPDATE_DISPLAY)
-+#define DEBUG_LEVEL_6 (DEBUG_LEVEL_4 | DEBUG_LEVEL_5)
-+#define DEBUG_LEVEL_7 0xFFFFFFFF
-+
-+#define DEBUG_DRIVER_INIT_FUNCTIONS (1<<3)
-+#define DEBUG_TIME_FIRST_UPDATE (1<<4)
-+#define DEBUG_TIME_EACH_UPDATE (1<<5)
-+#define DEBUG_DEFERRED_IO (1<<6)
-+#define DEBUG_FBTFT_INIT_FUNCTIONS (1<<7)
-+
-+/* fbops */
-+#define DEBUG_FB_READ (1<<8)
-+#define DEBUG_FB_WRITE (1<<9)
-+#define DEBUG_FB_FILLRECT (1<<10)
-+#define DEBUG_FB_COPYAREA (1<<11)
-+#define DEBUG_FB_IMAGEBLIT (1<<12)
-+#define DEBUG_FB_SETCOLREG (1<<13)
-+#define DEBUG_FB_BLANK (1<<14)
-+
-+#define DEBUG_SYSFS (1<<16)
-+
-+/* fbtftops */
-+#define DEBUG_BACKLIGHT (1<<17)
-+#define DEBUG_READ (1<<18)
-+#define DEBUG_WRITE (1<<19)
-+#define DEBUG_WRITE_VMEM (1<<20)
-+#define DEBUG_WRITE_REGISTER (1<<21)
-+#define DEBUG_SET_ADDR_WIN (1<<22)
-+#define DEBUG_RESET (1<<23)
-+#define DEBUG_MKDIRTY (1<<24)
-+#define DEBUG_UPDATE_DISPLAY (1<<25)
-+#define DEBUG_INIT_DISPLAY (1<<26)
-+#define DEBUG_BLANK (1<<27)
-+#define DEBUG_REQUEST_GPIOS (1<<28)
-+#define DEBUG_FREE_GPIOS (1<<29)
-+#define DEBUG_REQUEST_GPIOS_MATCH (1<<30)
-+#define DEBUG_VERIFY_GPIOS (1<<31)
-+
-+
-+#define fbtft_init_dbg(dev, format, arg...) \
-+do { \
-+ if (unlikely((dev)->platform_data && \
-+ (((struct fbtft_platform_data *)(dev)->platform_data)->display.debug & DEBUG_DRIVER_INIT_FUNCTIONS))) \
-+ dev_info(dev, format, ##arg); \
-+} while (0)
-+
-+#define fbtft_par_dbg(level, par, format, arg...) \
-+do { \
-+ if (unlikely(par->debug & level)) \
-+ dev_info(par->info->device, format, ##arg); \
-+} while (0)
-+
-+#define fbtft_dev_dbg(level, par, dev, format, arg...) \
-+do { \
-+ if (unlikely(par->debug & level)) \
-+ dev_info(dev, format, ##arg); \
-+} while (0)
-+
-+#define fbtft_par_dbg_hex(level, par, dev, type, buf, num, format, arg...) \
-+do { \
-+ if (unlikely(par->debug & level)) \
-+ fbtft_dbg_hex(dev, sizeof(type), buf, num * sizeof(type), format, ##arg); \
-+} while (0)
-+
-+#endif /* __LINUX_FBTFT_H */
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fbtft-io.c linux-rpi/drivers/staging/fbtft/fbtft-io.c
---- linux-3.18.14/drivers/staging/fbtft/fbtft-io.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fbtft-io.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,239 @@
-+#include <linux/export.h>
-+#include <linux/errno.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include "fbtft.h"
-+
-+int fbtft_write_spi(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ struct spi_transfer t = {
-+ .tx_buf = buf,
-+ .len = len,
-+ };
-+ struct spi_message m;
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ if (!par->spi) {
-+ dev_err(par->info->device,
-+ "%s: par->spi is unexpectedly NULL\n", __func__);
-+ return -1;
-+ }
-+
-+ spi_message_init(&m);
-+ if (par->txbuf.dma && buf == par->txbuf.buf) {
-+ t.tx_dma = par->txbuf.dma;
-+ m.is_dma_mapped = 1;
-+ }
-+ spi_message_add_tail(&t, &m);
-+ return spi_sync(par->spi, &m);
-+}
-+EXPORT_SYMBOL(fbtft_write_spi);
-+
-+/**
-+ * fbtft_write_spi_emulate_9() - write SPI emulating 9-bit
-+ * @par: Driver data
-+ * @buf: Buffer to write
-+ * @len: Length of buffer (must be divisible by 8)
-+ *
-+ * When 9-bit SPI is not available, this function can be used to emulate that.
-+ * par->extra must hold a transformation buffer used for transfer.
-+ */
-+int fbtft_write_spi_emulate_9(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ u16 *src = buf;
-+ u8 *dst = par->extra;
-+ size_t size = len / 2;
-+ size_t added = 0;
-+ int bits, i, j;
-+ u64 val, dc, tmp;
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ if (!par->extra) {
-+ dev_err(par->info->device, "%s: error: par->extra is NULL\n",
-+ __func__);
-+ return -EINVAL;
-+ }
-+ if ((len % 8) != 0) {
-+ dev_err(par->info->device,
-+ "%s: error: len=%d must be divisible by 8\n",
-+ __func__, len);
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < size; i += 8) {
-+ tmp = 0;
-+ bits = 63;
-+ for (j = 0; j < 7; j++) {
-+ dc = (*src & 0x0100) ? 1 : 0;
-+ val = *src & 0x00FF;
-+ tmp |= dc << bits;
-+ bits -= 8;
-+ tmp |= val << bits--;
-+ src++;
-+ }
-+ tmp |= ((*src & 0x0100) ? 1 : 0);
-+ *(u64 *)dst = cpu_to_be64(tmp);
-+ dst += 8;
-+ *dst++ = (u8)(*src++ & 0x00FF);
-+ added++;
-+ }
-+
-+ return spi_write(par->spi, par->extra, size + added);
-+}
-+EXPORT_SYMBOL(fbtft_write_spi_emulate_9);
-+
-+int fbtft_read_spi(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ int ret;
-+ u8 txbuf[32] = { 0, };
-+ struct spi_transfer t = {
-+ .speed_hz = 2000000,
-+ .rx_buf = buf,
-+ .len = len,
-+ };
-+ struct spi_message m;
-+
-+ if (!par->spi) {
-+ dev_err(par->info->device,
-+ "%s: par->spi is unexpectedly NULL\n", __func__);
-+ return -ENODEV;
-+ }
-+
-+ if (par->startbyte) {
-+ if (len > 32) {
-+ dev_err(par->info->device,
-+ "%s: len=%d can't be larger than 32 when using 'startbyte'\n",
-+ __func__, len);
-+ return -EINVAL;
-+ }
-+ txbuf[0] = par->startbyte | 0x3;
-+ t.tx_buf = txbuf;
-+ fbtft_par_dbg_hex(DEBUG_READ, par, par->info->device, u8,
-+ txbuf, len, "%s(len=%d) txbuf => ", __func__, len);
-+ }
-+
-+ spi_message_init(&m);
-+ spi_message_add_tail(&t, &m);
-+ ret = spi_sync(par->spi, &m);
-+ fbtft_par_dbg_hex(DEBUG_READ, par, par->info->device, u8, buf, len,
-+ "%s(len=%d) buf <= ", __func__, len);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(fbtft_read_spi);
-+
-+/*
-+ * Optimized use of gpiolib is twice as fast as no optimization
-+ * only one driver can use the optimized version at a time
-+ */
-+int fbtft_write_gpio8_wr(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ u8 data;
-+ int i;
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ static u8 prev_data;
-+#endif
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ while (len--) {
-+ data = *(u8 *) buf;
-+
-+ /* Start writing by pulling down /WR */
-+ gpio_set_value(par->gpio.wr, 0);
-+
-+ /* Set data */
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ if (data == prev_data) {
-+ gpio_set_value(par->gpio.wr, 0); /* used as delay */
-+ } else {
-+ for (i = 0; i < 8; i++) {
-+ if ((data & 1) != (prev_data & 1))
-+ gpio_set_value(par->gpio.db[i],
-+ (data & 1));
-+ data >>= 1;
-+ prev_data >>= 1;
-+ }
-+ }
-+#else
-+ for (i = 0; i < 8; i++) {
-+ gpio_set_value(par->gpio.db[i], (data & 1));
-+ data >>= 1;
-+ }
-+#endif
-+
-+ /* Pullup /WR */
-+ gpio_set_value(par->gpio.wr, 1);
-+
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ prev_data = *(u8 *) buf;
-+#endif
-+ buf++;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(fbtft_write_gpio8_wr);
-+
-+int fbtft_write_gpio16_wr(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ u16 data;
-+ int i;
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ static u16 prev_data;
-+#endif
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
-+ "%s(len=%d): ", __func__, len);
-+
-+ while (len) {
-+ data = *(u16 *) buf;
-+
-+ /* Start writing by pulling down /WR */
-+ gpio_set_value(par->gpio.wr, 0);
-+
-+ /* Set data */
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ if (data == prev_data) {
-+ gpio_set_value(par->gpio.wr, 0); /* used as delay */
-+ } else {
-+ for (i = 0; i < 16; i++) {
-+ if ((data & 1) != (prev_data & 1))
-+ gpio_set_value(par->gpio.db[i],
-+ (data & 1));
-+ data >>= 1;
-+ prev_data >>= 1;
-+ }
-+ }
-+#else
-+ for (i = 0; i < 16; i++) {
-+ gpio_set_value(par->gpio.db[i], (data & 1));
-+ data >>= 1;
-+ }
-+#endif
-+
-+ /* Pullup /WR */
-+ gpio_set_value(par->gpio.wr, 1);
-+
-+#ifndef DO_NOT_OPTIMIZE_FBTFT_WRITE_GPIO
-+ prev_data = *(u16 *) buf;
-+#endif
-+ buf += 2;
-+ len -= 2;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(fbtft_write_gpio16_wr);
-+
-+int fbtft_write_gpio16_wr_latched(struct fbtft_par *par, void *buf, size_t len)
-+{
-+ dev_err(par->info->device, "%s: function not implemented\n", __func__);
-+ return -1;
-+}
-+EXPORT_SYMBOL(fbtft_write_gpio16_wr_latched);
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fbtft-sysfs.c linux-rpi/drivers/staging/fbtft/fbtft-sysfs.c
---- linux-3.18.14/drivers/staging/fbtft/fbtft-sysfs.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fbtft-sysfs.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,222 @@
-+#include "fbtft.h"
-+
-+
-+static int get_next_ulong(char **str_p, unsigned long *val, char *sep, int base)
-+{
-+ char *p_val;
-+ int ret;
-+
-+ if (!str_p || !(*str_p))
-+ return -EINVAL;
-+
-+ p_val = strsep(str_p, sep);
-+
-+ if (!p_val)
-+ return -EINVAL;
-+
-+ ret = kstrtoul(p_val, base, val);
-+ if (ret)
-+ return -EINVAL;
-+
-+ return 0;
-+}
-+
-+int fbtft_gamma_parse_str(struct fbtft_par *par, unsigned long *curves,
-+ const char *str, int size)
-+{
-+ char *str_p, *curve_p = NULL;
-+ char *tmp;
-+ unsigned long val = 0;
-+ int ret = 0;
-+ int curve_counter, value_counter;
-+
-+ fbtft_par_dbg(DEBUG_SYSFS, par, "%s() str=\n", __func__);
-+
-+ if (!str || !curves)
-+ return -EINVAL;
-+
-+ fbtft_par_dbg(DEBUG_SYSFS, par, "%s\n", str);
-+
-+ tmp = kmalloc(size+1, GFP_KERNEL);
-+ if (!tmp)
-+ return -ENOMEM;
-+ memcpy(tmp, str, size+1);
-+
-+ /* replace optional separators */
-+ str_p = tmp;
-+ while (*str_p) {
-+ if (*str_p == ',')
-+ *str_p = ' ';
-+ if (*str_p == ';')
-+ *str_p = '\n';
-+ str_p++;
-+ }
-+
-+ str_p = strim(tmp);
-+
-+ curve_counter = 0;
-+ while (str_p) {
-+ if (curve_counter == par->gamma.num_curves) {
-+ dev_err(par->info->device, "Gamma: Too many curves\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ curve_p = strsep(&str_p, "\n");
-+ value_counter = 0;
-+ while (curve_p) {
-+ if (value_counter == par->gamma.num_values) {
-+ dev_err(par->info->device,
-+ "Gamma: Too many values\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ ret = get_next_ulong(&curve_p, &val, " ", 16);
-+ if (ret)
-+ goto out;
-+ curves[curve_counter * par->gamma.num_values + value_counter] = val;
-+ value_counter++;
-+ }
-+ if (value_counter != par->gamma.num_values) {
-+ dev_err(par->info->device, "Gamma: Too few values\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ curve_counter++;
-+ }
-+ if (curve_counter != par->gamma.num_curves) {
-+ dev_err(par->info->device, "Gamma: Too few curves\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+out:
-+ kfree(tmp);
-+ return ret;
-+}
-+
-+static ssize_t
-+sprintf_gamma(struct fbtft_par *par, unsigned long *curves, char *buf)
-+{
-+ ssize_t len = 0;
-+ unsigned int i, j;
-+
-+ mutex_lock(&par->gamma.lock);
-+ for (i = 0; i < par->gamma.num_curves; i++) {
-+ for (j = 0; j < par->gamma.num_values; j++)
-+ len += scnprintf(&buf[len], PAGE_SIZE,
-+ "%04lx ", curves[i*par->gamma.num_values + j]);
-+ buf[len-1] = '\n';
-+ }
-+ mutex_unlock(&par->gamma.lock);
-+
-+ return len;
-+}
-+
-+static ssize_t store_gamma_curve(struct device *device,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct fb_info *fb_info = dev_get_drvdata(device);
-+ struct fbtft_par *par = fb_info->par;
-+ unsigned long tmp_curves[FBTFT_GAMMA_MAX_VALUES_TOTAL];
-+ int ret;
-+
-+ ret = fbtft_gamma_parse_str(par, tmp_curves, buf, count);
-+ if (ret)
-+ return ret;
-+
-+ ret = par->fbtftops.set_gamma(par, tmp_curves);
-+ if (ret)
-+ return ret;
-+
-+ mutex_lock(&par->gamma.lock);
-+ memcpy(par->gamma.curves, tmp_curves,
-+ par->gamma.num_curves * par->gamma.num_values * sizeof(tmp_curves[0]));
-+ mutex_unlock(&par->gamma.lock);
-+
-+ return count;
-+}
-+
-+static ssize_t show_gamma_curve(struct device *device,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fb_info = dev_get_drvdata(device);
-+ struct fbtft_par *par = fb_info->par;
-+
-+ return sprintf_gamma(par, par->gamma.curves, buf);
-+}
-+
-+static struct device_attribute gamma_device_attrs[] = {
-+ __ATTR(gamma, 0660, show_gamma_curve, store_gamma_curve),
-+};
-+
-+
-+void fbtft_expand_debug_value(unsigned long *debug)
-+{
-+ switch (*debug & 0b111) {
-+ case 1:
-+ *debug |= DEBUG_LEVEL_1;
-+ break;
-+ case 2:
-+ *debug |= DEBUG_LEVEL_2;
-+ break;
-+ case 3:
-+ *debug |= DEBUG_LEVEL_3;
-+ break;
-+ case 4:
-+ *debug |= DEBUG_LEVEL_4;
-+ break;
-+ case 5:
-+ *debug |= DEBUG_LEVEL_5;
-+ break;
-+ case 6:
-+ *debug |= DEBUG_LEVEL_6;
-+ break;
-+ case 7:
-+ *debug = 0xFFFFFFFF;
-+ break;
-+ }
-+}
-+
-+static ssize_t store_debug(struct device *device,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct fb_info *fb_info = dev_get_drvdata(device);
-+ struct fbtft_par *par = fb_info->par;
-+ int ret;
-+
-+ ret = kstrtoul(buf, 10, &par->debug);
-+ if (ret)
-+ return ret;
-+ fbtft_expand_debug_value(&par->debug);
-+
-+ return count;
-+}
-+
-+static ssize_t show_debug(struct device *device,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fb_info *fb_info = dev_get_drvdata(device);
-+ struct fbtft_par *par = fb_info->par;
-+
-+ return snprintf(buf, PAGE_SIZE, "%lu\n", par->debug);
-+}
-+
-+static struct device_attribute debug_device_attr = \
-+ __ATTR(debug, 0660, show_debug, store_debug);
-+
-+
-+void fbtft_sysfs_init(struct fbtft_par *par)
-+{
-+ device_create_file(par->info->dev, &debug_device_attr);
-+ if (par->gamma.curves && par->fbtftops.set_gamma)
-+ device_create_file(par->info->dev, &gamma_device_attrs[0]);
-+}
-+
-+void fbtft_sysfs_exit(struct fbtft_par *par)
-+{
-+ device_remove_file(par->info->dev, &debug_device_attr);
-+ if (par->gamma.curves && par->fbtftops.set_gamma)
-+ device_remove_file(par->info->dev, &gamma_device_attrs[0]);
-+}
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_tinylcd.c linux-rpi/drivers/staging/fbtft/fb_tinylcd.c
---- linux-3.18.14/drivers/staging/fbtft/fb_tinylcd.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_tinylcd.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,124 @@
-+/*
-+ * Custom FB driver for tinylcd.com display
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_tinylcd"
-+#define WIDTH 320
-+#define HEIGHT 480
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ write_reg(par, 0xB0, 0x80);
-+ write_reg(par, 0xC0, 0x0A, 0x0A);
-+ write_reg(par, 0xC1, 0x45, 0x07);
-+ write_reg(par, 0xC2, 0x33);
-+ write_reg(par, 0xC5, 0x00, 0x42, 0x80);
-+ write_reg(par, 0xB1, 0xD0, 0x11);
-+ write_reg(par, 0xB4, 0x02);
-+ write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
-+ write_reg(par, 0xB7, 0x07);
-+ write_reg(par, 0x36, 0x58);
-+ write_reg(par, 0xF0, 0x36, 0xA5, 0xD3);
-+ write_reg(par, 0xE5, 0x80);
-+ write_reg(par, 0xE5, 0x01);
-+ write_reg(par, 0xB3, 0x00);
-+ write_reg(par, 0xE5, 0x00);
-+ write_reg(par, 0xF0, 0x36, 0xA5, 0x53);
-+ write_reg(par, 0xE0, 0x00, 0x35, 0x33, 0x00, 0x00, 0x00,
-+ 0x00, 0x35, 0x33, 0x00, 0x00, 0x00);
-+ write_reg(par, 0x3A, 0x55);
-+ write_reg(par, 0x11);
-+ udelay(250);
-+ write_reg(par, 0x29);
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* Column address */
-+ write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
-+
-+ /* Row adress */
-+ write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
-+
-+ /* Memory write */
-+ write_reg(par, 0x2C);
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ case 270:
-+ write_reg(par, 0xB6, 0x00, 0x02, 0x3B);
-+ write_reg(par, 0x36, 0x28);
-+ break;
-+ case 180:
-+ write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
-+ write_reg(par, 0x36, 0x58);
-+ break;
-+ case 90:
-+ write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
-+ write_reg(par, 0x36, 0x38);
-+ break;
-+ default:
-+ write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
-+ write_reg(par, 0x36, 0x08);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "neosec,tinylcd", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("spi:tinylcd");
-+
-+MODULE_DESCRIPTION("Custom FB driver for tinylcd.com display");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_tls8204.c linux-rpi/drivers/staging/fbtft/fb_tls8204.c
---- linux-3.18.14/drivers/staging/fbtft/fb_tls8204.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_tls8204.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,176 @@
-+/*
-+ * FB driver for the TLS8204 LCD Controller
-+ *
-+ * The display is monochrome and the video memory is RGB565.
-+ * Any pixel value except 0 turns the pixel on.
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ * Copyright (C) 2014 Michael Hope (adapted for the TLS8204)
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_tls8204"
-+#define WIDTH 84
-+#define HEIGHT 48
-+#define TXBUFLEN WIDTH
-+#define DEFAULT_GAMMA "40" /* gamma is used to control contrast in this driver */
-+
-+static unsigned bs = 4;
-+module_param(bs, uint, 0);
-+MODULE_PARM_DESC(bs, "BS[2:0] Bias voltage level: 0-7 (default: 4)");
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ /* Enter extended command mode */
-+ write_reg(par, 0x21); /* 5:1 1
-+ 2:0 PD - Powerdown control: chip is active
-+ 1:0 V - Entry mode: horizontal addressing
-+ 0:1 H - Extended instruction set control: extended
-+ */
-+
-+ /* H=1 Bias system */
-+ write_reg(par, 0x10 | (bs & 0x7)); /*
-+ 4:1 1
-+ 3:0 0
-+ 2:x BS2 - Bias System
-+ 1:x BS1
-+ 0:x BS0
-+ */
-+
-+ /* Set the address of the first display line. */
-+ write_reg(par, 0x04 | (64 >> 6));
-+ write_reg(par, 0x40 | (64 & 0x3F));
-+
-+ /* Enter H=0 standard command mode */
-+ write_reg(par, 0x20);
-+
-+ /* H=0 Display control */
-+ write_reg(par, 0x08 | 4); /*
-+ 3:1 1
-+ 2:1 D - DE: 10=normal mode
-+ 1:0 0
-+ 0:0 E
-+ */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* H=0 Set X address of RAM */
-+ write_reg(par, 0x80); /* 7:1 1
-+ 6-0: X[6:0] - 0x00
-+ */
-+
-+ /* H=0 Set Y address of RAM */
-+ write_reg(par, 0x40); /* 7:0 0
-+ 6:1 1
-+ 2-0: Y[2:0] - 0x0
-+ */
-+}
-+
-+static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16 = (u16 *)par->info->screen_base;
-+ int x, y, i;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ for (y = 0; y < HEIGHT/8; y++) {
-+ u8 *buf = par->txbuf.buf;
-+ /* The display is 102x68 but the LCD is 84x48. Set
-+ the write pointer at the start of each row. */
-+ gpio_set_value(par->gpio.dc, 0);
-+ write_reg(par, 0x80 | 0);
-+ write_reg(par, 0x40 | y);
-+
-+ for (x = 0; x < WIDTH; x++) {
-+ u8 ch = 0;
-+ for (i = 0; i < 8*WIDTH; i += WIDTH) {
-+ ch >>= 1;
-+ if (vmem16[(y*8*WIDTH)+i+x])
-+ ch |= 0x80;
-+ }
-+ *buf++ = ch;
-+ }
-+ /* Write the row */
-+ gpio_set_value(par->gpio.dc, 1);
-+ ret = par->fbtftops.write(par, par->txbuf.buf, WIDTH);
-+ if (ret < 0) {
-+ dev_err(par->info->device,
-+ "%s: write failed and returned: %d\n", __func__, ret);
-+ break;
-+ }
-+ }
-+
-+ return ret;
-+}
-+
-+static int set_gamma(struct fbtft_par *par, unsigned long *curves)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* apply mask */
-+ curves[0] &= 0x7F;
-+
-+ write_reg(par, 0x21); /* turn on extended instruction set */
-+ write_reg(par, 0x80 | curves[0]);
-+ write_reg(par, 0x20); /* turn off extended instruction set */
-+
-+ return 0;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .txbuflen = TXBUFLEN,
-+ .gamma_num = 1,
-+ .gamma_len = 1,
-+ .gamma = DEFAULT_GAMMA,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .write_vmem = write_vmem,
-+ .set_gamma = set_gamma,
-+ },
-+ .backlight = 1,
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "teralane,tls8204", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("spi:tls8204");
-+
-+MODULE_DESCRIPTION("FB driver for the TLS8204 LCD Controller");
-+MODULE_AUTHOR("Michael Hope");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_uc1701.c linux-rpi/drivers/staging/fbtft/fb_uc1701.c
---- linux-3.18.14/drivers/staging/fbtft/fb_uc1701.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_uc1701.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,210 @@
-+/*
-+ * FB driver for the UC1701 LCD Controller
-+ *
-+ * The display is monochrome and the video memory is RGB565.
-+ * Any pixel value except 0 turns the pixel on.
-+ *
-+ * Copyright (C) 2014 Juergen Holzmann
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_uc1701"
-+#define WIDTH 102
-+#define HEIGHT 64
-+#define PAGES (HEIGHT/8)
-+
-+/* 1: Display on/off */
-+#define LCD_DISPLAY_ENABLE 0xAE
-+/* 2: display start line set */
-+#define LCD_START_LINE 0x40
-+/* 3: Page address set (lower 4 bits select one of the pages) */
-+#define LCD_PAGE_ADDRESS 0xB0
-+/* 4: column address */
-+#define LCD_COL_ADDRESS 0x10
-+/* 8: select orientation */
-+#define LCD_BOTTOMVIEW 0xA0
-+/* 9: inverted display */
-+#define LCD_DISPLAY_INVERT 0xA6
-+/* 10: show memory content or switch all pixels on */
-+#define LCD_ALL_PIXEL 0xA4
-+/* 11: lcd bias set */
-+#define LCD_BIAS 0xA2
-+/* 14: Reset Controller */
-+#define LCD_RESET_CMD 0xE2
-+/* 15: output mode select (turns display upside-down) */
-+#define LCD_SCAN_DIR 0xC0
-+/* 16: power control set */
-+#define LCD_POWER_CONTROL 0x28
-+/* 17: voltage regulator resistor ratio set */
-+#define LCD_VOLTAGE 0x20
-+/* 18: Volume mode set */
-+#define LCD_VOLUME_MODE 0x81
-+/* 22: NOP command */
-+#define LCD_NO_OP 0xE3
-+/* 25: advanced program control */
-+#define LCD_ADV_PROG_CTRL 0xFA
-+/* 25: advanced program control2 */
-+#define LCD_ADV_PROG_CTRL2 0x10
-+#define LCD_TEMPCOMP_HIGH 0x80
-+/* column offset for normal orientation */
-+#define SHIFT_ADDR_NORMAL 0
-+/* column offset for bottom view orientation */
-+#define SHIFT_ADDR_TOPVIEW 30
-+
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ /* softreset of LCD */
-+ write_reg(par, LCD_RESET_CMD);
-+ mdelay(10);
-+
-+ /* set startpoint */
-+ /* LCD_START_LINE | (pos & 0x3F) */
-+ write_reg(par, LCD_START_LINE);
-+
-+ /* select orientation BOTTOMVIEW */
-+ write_reg(par, LCD_BOTTOMVIEW | 1);
-+ /* output mode select (turns display upside-down) */
-+ write_reg(par, LCD_SCAN_DIR | 0x00);
-+
-+ /* Normal Pixel mode */
-+ write_reg(par, LCD_ALL_PIXEL | 0);
-+
-+ /* positive display */
-+ write_reg(par, LCD_DISPLAY_INVERT | 0);
-+
-+ /* bias 1/9 */
-+ write_reg(par, LCD_BIAS | 0);
-+
-+ /* power control mode: all features on */
-+ /* LCD_POWER_CONTROL | (val&0x07) */
-+ write_reg(par, LCD_POWER_CONTROL | 0x07);
-+
-+ /* set voltage regulator R/R */
-+ /* LCD_VOLTAGE | (val&0x07) */
-+ write_reg(par, LCD_VOLTAGE | 0x07);
-+
-+ /* volume mode set */
-+ /* LCD_VOLUME_MODE,val&0x3f,LCD_NO_OP */
-+ write_reg(par, LCD_VOLUME_MODE);
-+ /* LCD_VOLUME_MODE,val&0x3f,LCD_NO_OP */
-+ write_reg(par, 0x09);
-+ /* ???? */
-+ /* LCD_VOLUME_MODE,val&0x3f,LCD_NO_OP */
-+ write_reg(par, LCD_NO_OP);
-+
-+ /* advanced program control */
-+ write_reg(par, LCD_ADV_PROG_CTRL);
-+ write_reg(par, LCD_ADV_PROG_CTRL2|LCD_TEMPCOMP_HIGH);
-+
-+ /* enable display */
-+ write_reg(par, LCD_DISPLAY_ENABLE | 1);
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ /* goto address */
-+ /* LCD_PAGE_ADDRESS | ((page) & 0x1F),
-+ (((col)+SHIFT_ADDR_NORMAL) & 0x0F),
-+ LCD_COL_ADDRESS | ((((col)+SHIFT_ADDR_NORMAL)>>4) & 0x0F) */
-+ write_reg(par, LCD_PAGE_ADDRESS);
-+ /* LCD_PAGE_ADDRESS | ((page) & 0x1F),
-+ (((col)+SHIFT_ADDR_NORMAL) & 0x0F),
-+ LCD_COL_ADDRESS | ((((col)+SHIFT_ADDR_NORMAL)>>4) & 0x0F) */
-+ write_reg(par, 0x00);
-+ /* LCD_PAGE_ADDRESS | ((page) & 0x1F),
-+ (((col)+SHIFT_ADDR_NORMAL) & 0x0F),
-+ LCD_COL_ADDRESS | ((((col)+SHIFT_ADDR_NORMAL)>>4) & 0x0F) */
-+ write_reg(par, LCD_COL_ADDRESS);
-+}
-+
-+static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ u16 *vmem16 = (u16 *)par->info->screen_base;
-+ u8 *buf = par->txbuf.buf;
-+ int x, y, i;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ for (y = 0; y < PAGES; y++) {
-+ buf = par->txbuf.buf;
-+ for (x = 0; x < WIDTH; x++) {
-+ *buf = 0x00;
-+ for (i = 0; i < 8; i++)
-+ *buf |= (vmem16[((y*8*WIDTH)+(i*WIDTH))+x] ? 1 : 0) << i;
-+ buf++;
-+ }
-+ /* LCD_PAGE_ADDRESS | ((page) & 0x1F),
-+ (((col)+SHIFT_ADDR_NORMAL) & 0x0F),
-+ LCD_COL_ADDRESS | ((((col)+SHIFT_ADDR_NORMAL)>>4) & 0x0F) */
-+ write_reg(par, LCD_PAGE_ADDRESS|(u8)y);
-+ /* LCD_PAGE_ADDRESS | ((page) & 0x1F),
-+ (((col)+SHIFT_ADDR_NORMAL) & 0x0F),
-+ LCD_COL_ADDRESS | ((((col)+SHIFT_ADDR_NORMAL)>>4) & 0x0F) */
-+ write_reg(par, 0x00);
-+ /* LCD_PAGE_ADDRESS | ((page) & 0x1F),
-+ (((col)+SHIFT_ADDR_NORMAL) & 0x0F),
-+ LCD_COL_ADDRESS | ((((col)+SHIFT_ADDR_NORMAL)>>4) & 0x0F) */
-+ write_reg(par, LCD_COL_ADDRESS);
-+ gpio_set_value(par->gpio.dc, 1);
-+ ret = par->fbtftops.write(par, par->txbuf.buf, WIDTH);
-+ gpio_set_value(par->gpio.dc, 0);
-+ }
-+
-+ if (ret < 0)
-+ dev_err(par->info->device, "%s: write failed and returned: %d\n", __func__, ret);
-+
-+ return ret;
-+}
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .write_vmem = write_vmem,
-+ },
-+ .backlight = 1,
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "UltraChip,uc1701", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("spi:uc1701");
-+
-+MODULE_DESCRIPTION("FB driver for the UC1701 LCD Controller");
-+MODULE_AUTHOR("Juergen Holzmann");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_upd161704.c linux-rpi/drivers/staging/fbtft/fb_upd161704.c
---- linux-3.18.14/drivers/staging/fbtft/fb_upd161704.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_upd161704.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,206 @@
-+/*
-+ * FB driver for the uPD161704 LCD Controller
-+ *
-+ * Copyright (C) 2014 Seong-Woo Kim
-+ *
-+ * Based on fb_ili9325.c by Noralf Tronnes
-+ * Based on ili9325.c by Jeroen Domburg
-+ * Init code from UTFT library by Henning Karlsen
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_upd161704"
-+#define WIDTH 240
-+#define HEIGHT 320
-+#define BPP 16
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ par->fbtftops.reset(par);
-+
-+ if (par->gpio.cs != -1)
-+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */
-+
-+ /* Initialization sequence from Lib_UTFT */
-+
-+ /* register reset */
-+ write_reg(par, 0x0003,0x0001); /* Soft reset */
-+
-+ /* oscillator start */
-+ write_reg(par, 0x003A,0x0001); /*Oscillator 0: stop, 1: operation */
-+ udelay(100);
-+
-+ /* y-setting */
-+ write_reg(par, 0x0024,0x007B); /* amplitude setting */
-+ udelay(10);
-+ write_reg(par, 0x0025,0x003B); /* amplitude setting */
-+ write_reg(par, 0x0026,0x0034); /* amplitude setting */
-+ udelay(10);
-+ write_reg(par, 0x0027,0x0004); /* amplitude setting */
-+ write_reg(par, 0x0052,0x0025); /* circuit setting 1 */
-+ udelay(10);
-+ write_reg(par, 0x0053,0x0033); /* circuit setting 2 */
-+ write_reg(par, 0x0061,0x001C); /* adjustment V10 positive polarity */
-+ udelay(10);
-+ write_reg(par, 0x0062,0x002C); /* adjustment V9 negative polarity */
-+ write_reg(par, 0x0063,0x0022); /* adjustment V34 positive polarity */
-+ udelay(10);
-+ write_reg(par, 0x0064,0x0027); /* adjustment V31 negative polarity */
-+ udelay(10);
-+ write_reg(par, 0x0065,0x0014); /* adjustment V61 negative polarity */
-+ udelay(10);
-+ write_reg(par, 0x0066,0x0010); /* adjustment V61 negative polarity */
-+
-+ /* Basical clock for 1 line (BASECOUNT[7:0]) number specified */
-+ write_reg(par, 0x002E,0x002D);
-+
-+ /* Power supply setting */
-+ write_reg(par, 0x0019,0x0000); /* DC/DC output setting */
-+ udelay(200);
-+ write_reg(par, 0x001A,0x1000); /* DC/DC frequency setting */
-+ write_reg(par, 0x001B,0x0023); /* DC/DC rising setting */
-+ write_reg(par, 0x001C,0x0C01); /* Regulator voltage setting */
-+ write_reg(par, 0x001D,0x0000); /* Regulator current setting */
-+ write_reg(par, 0x001E,0x0009); /* VCOM output setting */
-+ write_reg(par, 0x001F,0x0035); /* VCOM amplitude setting */
-+ write_reg(par, 0x0020,0x0015); /* VCOMM cencter setting */
-+ write_reg(par, 0x0018,0x1E7B); /* DC/DC operation setting */
-+
-+ /* windows setting */
-+ write_reg(par, 0x0008,0x0000); /* Minimum X address */
-+ write_reg(par, 0x0009,0x00EF); /* Maximum X address */
-+ write_reg(par, 0x000a,0x0000); /* Minimum Y address */
-+ write_reg(par, 0x000b,0x013F); /* Maximum Y address */
-+
-+ /* LCD display area setting */
-+ write_reg(par, 0x0029,0x0000); /* [LCDSIZE] X MIN. size set */
-+ write_reg(par, 0x002A,0x0000); /* [LCDSIZE] Y MIN. size set */
-+ write_reg(par, 0x002B,0x00EF); /* [LCDSIZE] X MAX. size set */
-+ write_reg(par, 0x002C,0x013F); /* [LCDSIZE] Y MAX. size set */
-+
-+ /* Gate scan setting */
-+ write_reg(par, 0x0032,0x0002);
-+
-+ /* n line inversion line number */
-+ write_reg(par, 0x0033,0x0000);
-+
-+ /* Line inversion/frame inversion/interlace setting */
-+ write_reg(par, 0x0037,0x0000);
-+
-+ /* Gate scan operation setting register */
-+ write_reg(par, 0x003B,0x0001);
-+
-+ /* Color mode */
-+ /*GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) */
-+ write_reg(par, 0x0004,0x0000);
-+
-+ /* RAM control register */
-+ write_reg(par, 0x0005,0x0000); /*Window access 00:Normal, 10:Window */
-+
-+ /* Display setting register 2 */
-+ write_reg(par, 0x0001,0x0000);
-+
-+ /* display setting */
-+ write_reg(par, 0x0000,0x0000); /* display on */
-+
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
-+ "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+ switch (par->info->var.rotate) {
-+ /* R20h = Horizontal GRAM Start Address */
-+ /* R21h = Vertical GRAM Start Address */
-+ case 0:
-+ write_reg(par, 0x0006, xs);
-+ write_reg(par, 0x0007, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x0006, WIDTH - 1 - xs);
-+ write_reg(par, 0x0007, HEIGHT - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x0006, WIDTH - 1 - ys);
-+ write_reg(par, 0x0007, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x0006, ys);
-+ write_reg(par, 0x0007, HEIGHT - 1 - xs);
-+ break;
-+ }
-+
-+ write_reg(par, 0x0e); /* Write Data to GRAM */
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ switch (par->info->var.rotate) {
-+ /* AM: GRAM update direction */
-+ case 0:
-+ write_reg(par, 0x01, 0x0000);
-+ write_reg(par, 0x05, 0x0000);
-+ break;
-+ case 180:
-+ write_reg(par, 0x01, 0x00C0);
-+ write_reg(par, 0x05, 0x0000);
-+ break;
-+ case 270:
-+ write_reg(par, 0x01, 0x0080);
-+ write_reg(par, 0x05, 0x0001);
-+ break;
-+ case 90:
-+ write_reg(par, 0x01, 0x0040);
-+ write_reg(par, 0x05, 0x0001);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct fbtft_display display = {
-+ .regwidth = 16,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .fbtftops = {
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+MODULE_ALIAS("platform:" DRVNAME);
-+MODULE_ALIAS("spi:upd161704");
-+MODULE_ALIAS("platform:upd161704");
-+
-+MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
-+MODULE_AUTHOR("Seong-Woo Kim");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/fb_watterott.c linux-rpi/drivers/staging/fbtft/fb_watterott.c
---- linux-3.18.14/drivers/staging/fbtft/fb_watterott.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/fb_watterott.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,324 @@
-+/*
-+ * FB driver for the Watterott LCD Controller
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/gpio.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "fb_watterott"
-+#define WIDTH 320
-+#define HEIGHT 240
-+#define FPS 5
-+#define TXBUFLEN 1024
-+#define DEFAULT_BRIGHTNESS 50
-+
-+#define CMD_VERSION 0x01
-+#define CMD_LCD_LED 0x10
-+#define CMD_LCD_RESET 0x11
-+#define CMD_LCD_ORIENTATION 0x20
-+#define CMD_LCD_DRAWIMAGE 0x27
-+#define COLOR_RGB323 8
-+#define COLOR_RGB332 9
-+#define COLOR_RGB233 10
-+#define COLOR_RGB565 16
-+
-+
-+static short mode = 565;
-+module_param(mode, short, 0);
-+MODULE_PARM_DESC(mode, "RGB color transfer mode: 332, 565 (default)");
-+
-+static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
-+{
-+ va_list args;
-+ int i, ret;
-+ u8 *buf = par->buf;
-+
-+ va_start(args, len);
-+ for (i = 0; i < len; i++)
-+ *buf++ = (u8)va_arg(args, unsigned int);
-+ va_end(args);
-+
-+ fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par,
-+ par->info->device, u8, par->buf, len, "%s: ", __func__);
-+
-+ ret = par->fbtftops.write(par, par->buf, len);
-+ if (ret < 0) {
-+ dev_err(par->info->device,
-+ "%s: write() failed and returned %d\n", __func__, ret);
-+ return;
-+ }
-+}
-+
-+static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ unsigned start_line, end_line;
-+ u16 *vmem16 = (u16 *)(par->info->screen_base + offset);
-+ u16 *pos = par->txbuf.buf + 1;
-+ u16 *buf16 = par->txbuf.buf + 10;
-+ int i, j;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ start_line = offset / par->info->fix.line_length;
-+ end_line = start_line + (len / par->info->fix.line_length) - 1;
-+
-+ /* Set command header. pos: x, y, w, h */
-+ ((u8 *)par->txbuf.buf)[0] = CMD_LCD_DRAWIMAGE;
-+ pos[0] = 0;
-+ pos[2] = cpu_to_be16(par->info->var.xres);
-+ pos[3] = cpu_to_be16(1);
-+ ((u8 *)par->txbuf.buf)[9] = COLOR_RGB565;
-+
-+ for (i = start_line; i <= end_line; i++) {
-+ pos[1] = cpu_to_be16(i);
-+ for (j = 0; j < par->info->var.xres; j++)
-+ buf16[j] = cpu_to_be16(*vmem16++);
-+ ret = par->fbtftops.write(par,
-+ par->txbuf.buf, 10 + par->info->fix.line_length);
-+ if (ret < 0)
-+ return ret;
-+ udelay(300);
-+ }
-+
-+ return 0;
-+}
-+
-+#define RGB565toRGB323(c) (((c&0xE000)>>8) | ((c&0600)>>6) | ((c&0x001C)>>2))
-+#define RGB565toRGB332(c) (((c&0xE000)>>8) | ((c&0700)>>6) | ((c&0x0018)>>3))
-+#define RGB565toRGB233(c) (((c&0xC000)>>8) | ((c&0700)>>5) | ((c&0x001C)>>2))
-+
-+static int write_vmem_8bit(struct fbtft_par *par, size_t offset, size_t len)
-+{
-+ unsigned start_line, end_line;
-+ u16 *vmem16 = (u16 *)(par->info->screen_base + offset);
-+ u16 *pos = par->txbuf.buf + 1;
-+ u8 *buf8 = par->txbuf.buf + 10;
-+ int i, j;
-+ int ret = 0;
-+
-+ fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s()\n", __func__);
-+
-+ start_line = offset / par->info->fix.line_length;
-+ end_line = start_line + (len / par->info->fix.line_length) - 1;
-+
-+ /* Set command header. pos: x, y, w, h */
-+ ((u8 *)par->txbuf.buf)[0] = CMD_LCD_DRAWIMAGE;
-+ pos[0] = 0;
-+ pos[2] = cpu_to_be16(par->info->var.xres);
-+ pos[3] = cpu_to_be16(1);
-+ ((u8 *)par->txbuf.buf)[9] = COLOR_RGB332;
-+
-+ for (i = start_line; i <= end_line; i++) {
-+ pos[1] = cpu_to_be16(i);
-+ for (j = 0; j < par->info->var.xres; j++) {
-+ buf8[j] = RGB565toRGB332(*vmem16);
-+ vmem16++;
-+ }
-+ ret = par->fbtftops.write(par,
-+ par->txbuf.buf, 10 + par->info->var.xres);
-+ if (ret < 0)
-+ return ret;
-+ udelay(700);
-+ }
-+
-+ return 0;
-+}
-+
-+static unsigned firmware_version(struct fbtft_par *par)
-+{
-+ u8 rxbuf[4] = {0, };
-+
-+ write_reg(par, CMD_VERSION);
-+ par->fbtftops.read(par, rxbuf, 4);
-+ if (rxbuf[1] != '.')
-+ return 0;
-+
-+ return (rxbuf[0] - '0') << 8 | (rxbuf[2] - '0') << 4 | (rxbuf[3] - '0');
-+}
-+
-+static int init_display(struct fbtft_par *par)
-+{
-+ int ret;
-+ unsigned version;
-+ u8 save_mode;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* enable SPI interface by having CS and MOSI low during reset */
-+ save_mode = par->spi->mode;
-+ par->spi->mode |= SPI_CS_HIGH;
-+ ret = par->spi->master->setup(par->spi); /* set CS inactive low */
-+ if (ret) {
-+ dev_err(par->info->device, "Could not set SPI_CS_HIGH\n");
-+ return ret;
-+ }
-+ write_reg(par, 0x00); /* make sure mode is set */
-+
-+ mdelay(50);
-+ par->fbtftops.reset(par);
-+ mdelay(1000);
-+ par->spi->mode = save_mode;
-+ ret = par->spi->master->setup(par->spi);
-+ if (ret) {
-+ dev_err(par->info->device, "Could not restore SPI mode\n");
-+ return ret;
-+ }
-+ write_reg(par, 0x00);
-+
-+ version = firmware_version(par);
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Firmware version: %x.%02x\n",
-+ version >> 8, version & 0xFF);
-+
-+ if (mode == 332)
-+ par->fbtftops.write_vmem = write_vmem_8bit;
-+ return 0;
-+}
-+
-+static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ /* not used on this controller */
-+}
-+
-+static int set_var(struct fbtft_par *par)
-+{
-+ u8 rotate;
-+
-+ fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
-+
-+ /* this controller rotates clock wise */
-+ switch (par->info->var.rotate) {
-+ case 90:
-+ rotate = 27;
-+ break;
-+ case 180:
-+ rotate = 18;
-+ break;
-+ case 270:
-+ rotate = 9;
-+ break;
-+ default:
-+ rotate = 0;
-+ }
-+ write_reg(par, CMD_LCD_ORIENTATION, rotate);
-+
-+ return 0;
-+}
-+
-+static int verify_gpios(struct fbtft_par *par)
-+{
-+ if (par->gpio.reset < 0) {
-+ dev_err(par->info->device, "Missing 'reset' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+#ifdef CONFIG_FB_BACKLIGHT
-+static int backlight_chip_update_status(struct backlight_device *bd)
-+{
-+ struct fbtft_par *par = bl_get_data(bd);
-+ int brightness = bd->props.brightness;
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par,
-+ "%s: brightness=%d, power=%d, fb_blank=%d\n",
-+ __func__, bd->props.brightness, bd->props.power,
-+ bd->props.fb_blank);
-+
-+ if (bd->props.power != FB_BLANK_UNBLANK)
-+ brightness = 0;
-+
-+ if (bd->props.fb_blank != FB_BLANK_UNBLANK)
-+ brightness = 0;
-+
-+ write_reg(par, CMD_LCD_LED, brightness);
-+
-+ return 0;
-+}
-+
-+static void register_chip_backlight(struct fbtft_par *par)
-+{
-+ struct backlight_device *bd;
-+ struct backlight_properties bl_props = { 0, };
-+ struct backlight_ops *bl_ops;
-+
-+ fbtft_par_dbg(DEBUG_BACKLIGHT, par, "%s()\n", __func__);
-+
-+ bl_ops = devm_kzalloc(par->info->device, sizeof(struct backlight_ops),
-+ GFP_KERNEL);
-+ if (!bl_ops) {
-+ dev_err(par->info->device,
-+ "%s: could not allocate memory for backlight operations.\n",
-+ __func__);
-+ return;
-+ }
-+
-+ bl_ops->update_status = backlight_chip_update_status;
-+ bl_props.type = BACKLIGHT_RAW;
-+ bl_props.power = FB_BLANK_POWERDOWN;
-+ bl_props.max_brightness = 100;
-+ bl_props.brightness = DEFAULT_BRIGHTNESS;
-+
-+ bd = backlight_device_register(dev_driver_string(par->info->device),
-+ par->info->device, par, bl_ops, &bl_props);
-+ if (IS_ERR(bd)) {
-+ dev_err(par->info->device,
-+ "cannot register backlight device (%ld)\n",
-+ PTR_ERR(bd));
-+ return;
-+ }
-+ par->info->bl_dev = bd;
-+
-+ if (!par->fbtftops.unregister_backlight)
-+ par->fbtftops.unregister_backlight = fbtft_unregister_backlight;
-+}
-+#else
-+#define register_chip_backlight NULL
-+#endif
-+
-+
-+static struct fbtft_display display = {
-+ .regwidth = 8,
-+ .buswidth = 8,
-+ .width = WIDTH,
-+ .height = HEIGHT,
-+ .fps = FPS,
-+ .txbuflen = TXBUFLEN,
-+ .fbtftops = {
-+ .write_register = write_reg8_bus8,
-+ .write_vmem = write_vmem,
-+ .init_display = init_display,
-+ .set_addr_win = set_addr_win,
-+ .set_var = set_var,
-+ .verify_gpios = verify_gpios,
-+ .register_backlight = register_chip_backlight,
-+ },
-+};
-+FBTFT_REGISTER_DRIVER(DRVNAME, "watterott,openlcd", &display);
-+
-+MODULE_ALIAS("spi:" DRVNAME);
-+
-+MODULE_DESCRIPTION("FB driver for the Watterott LCD Controller");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/flexfb.c linux-rpi/drivers/staging/fbtft/flexfb.c
---- linux-3.18.14/drivers/staging/fbtft/flexfb.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/flexfb.c 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,592 @@
-+/*
-+ * Generic FB driver for TFT LCD displays
-+ *
-+ * Copyright (C) 2013 Noralf Tronnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/vmalloc.h>
-+#include <linux/gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+
-+#include "fbtft.h"
-+
-+#define DRVNAME "flexfb"
-+
-+
-+static char *chip;
-+module_param(chip, charp, 0);
-+MODULE_PARM_DESC(chip, "LCD controller");
-+
-+static unsigned int width;
-+module_param(width, uint, 0);
-+MODULE_PARM_DESC(width, "Display width");
-+
-+static unsigned int height;
-+module_param(height, uint, 0);
-+MODULE_PARM_DESC(height, "Display height");
-+
-+static int init[512];
-+static int init_num;
-+module_param_array(init, int, &init_num, 0);
-+MODULE_PARM_DESC(init, "Init sequence");
-+
-+static unsigned int setaddrwin;
-+module_param(setaddrwin, uint, 0);
-+MODULE_PARM_DESC(setaddrwin, "Which set_addr_win() implementation to use");
-+
-+static unsigned int buswidth = 8;
-+module_param(buswidth, uint, 0);
-+MODULE_PARM_DESC(buswidth, "Width of databus (default: 8)");
-+
-+static unsigned int regwidth = 8;
-+module_param(regwidth, uint, 0);
-+MODULE_PARM_DESC(regwidth, "Width of controller register (default: 8)");
-+
-+static bool nobacklight;
-+module_param(nobacklight, bool, 0);
-+MODULE_PARM_DESC(nobacklight, "Turn off backlight functionality.");
-+
-+static bool latched;
-+module_param(latched, bool, 0);
-+MODULE_PARM_DESC(latched, "Use with latched 16-bit databus");
-+
-+
-+static int *initp;
-+static int initp_num;
-+
-+/* default init sequences */
-+static int st7735r_init[] = { \
-+-1,0x01,-2,150,-1,0x11,-2,500,-1,0xB1,0x01,0x2C,0x2D,-1,0xB2,0x01,0x2C,0x2D,-1,0xB3,0x01,0x2C,0x2D,0x01,0x2C,0x2D, \
-+-1,0xB4,0x07,-1,0xC0,0xA2,0x02,0x84,-1,0xC1,0xC5,-1,0xC2,0x0A,0x00,-1,0xC3,0x8A,0x2A,-1,0xC4,0x8A,0xEE,-1,0xC5,0x0E, \
-+-1,0x20,-1,0x36,0xC0,-1,0x3A,0x05,-1,0xE0,0x0f,0x1a,0x0f,0x18,0x2f,0x28,0x20,0x22,0x1f,0x1b,0x23,0x37,0x00,0x07,0x02,0x10, \
-+-1,0xE1,0x0f,0x1b,0x0f,0x17,0x33,0x2c,0x29,0x2e,0x30,0x30,0x39,0x3f,0x00,0x07,0x03,0x10,-1,0x29,-2,100,-1,0x13,-2,10,-3 };
-+
-+static int ssd1289_init[] = { \
-+-1,0x00,0x0001,-1,0x03,0xA8A4,-1,0x0C,0x0000,-1,0x0D,0x080C,-1,0x0E,0x2B00,-1,0x1E,0x00B7,-1,0x01,0x2B3F,-1,0x02,0x0600, \
-+-1,0x10,0x0000,-1,0x11,0x6070,-1,0x05,0x0000,-1,0x06,0x0000,-1,0x16,0xEF1C,-1,0x17,0x0003,-1,0x07,0x0233,-1,0x0B,0x0000, \
-+-1,0x0F,0x0000,-1,0x41,0x0000,-1,0x42,0x0000,-1,0x48,0x0000,-1,0x49,0x013F,-1,0x4A,0x0000,-1,0x4B,0x0000,-1,0x44,0xEF00, \
-+-1,0x45,0x0000,-1,0x46,0x013F,-1,0x30,0x0707,-1,0x31,0x0204,-1,0x32,0x0204,-1,0x33,0x0502,-1,0x34,0x0507,-1,0x35,0x0204, \
-+-1,0x36,0x0204,-1,0x37,0x0502,-1,0x3A,0x0302,-1,0x3B,0x0302,-1,0x23,0x0000,-1,0x24,0x0000,-1,0x25,0x8000,-1,0x4f,0x0000, \
-+-1,0x4e,0x0000,-1,0x22,-3 };
-+
-+static int hx8340bn_init[] = { \
-+-1,0xC1,0xFF,0x83,0x40,-1,0x11,-2,150,-1,0xCA,0x70,0x00,0xD9,-1,0xB0,0x01,0x11, \
-+-1,0xC9,0x90,0x49,0x10,0x28,0x28,0x10,0x00,0x06,-2,20,-1,0xC2,0x60,0x71,0x01,0x0E,0x05,0x02,0x09,0x31,0x0A, \
-+-1,0xC3,0x67,0x30,0x61,0x17,0x48,0x07,0x05,0x33,-2,10,-1,0xB5,0x35,0x20,0x45,-1,0xB4,0x33,0x25,0x4C,-2,10, \
-+-1,0x3A,0x05,-1,0x29,-2,10,-3 };
-+
-+static int ili9225_init[] = { \
-+-1,0x0001,0x011C,-1,0x0002,0x0100,-1,0x0003,0x1030,-1,0x0008,0x0808,-1,0x000C,0x0000,-1,0x000F,0x0A01,-1,0x0020,0x0000, \
-+-1,0x0021,0x0000,-2,50,-1,0x0010,0x0A00,-1,0x0011,0x1038,-2,50,-1,0x0012,0x1121,-1,0x0013,0x004E,-1,0x0014,0x676F, \
-+-1,0x0030,0x0000,-1,0x0031,0x00DB,-1,0x0032,0x0000,-1,0x0033,0x0000,-1,0x0034,0x00DB,-1,0x0035,0x0000,-1,0x0036,0x00AF, \
-+-1,0x0037,0x0000,-1,0x0038,0x00DB,-1,0x0039,0x0000,-1,0x0050,0x0000,-1,0x0051,0x060A,-1,0x0052,0x0D0A,-1,0x0053,0x0303, \
-+-1,0x0054,0x0A0D,-1,0x0055,0x0A06,-1,0x0056,0x0000,-1,0x0057,0x0303,-1,0x0058,0x0000,-1,0x0059,0x0000,-2,50, \
-+-1,0x0007,0x1017,-2,50,-3 };
-+
-+static int ili9320_init[] = { \
-+-1,0x00E5,0x8000,-1,0x0000,0x0001,-1,0x0001,0x0100,-1,0x0002,0x0700,-1,0x0003,0x1030,-1,0x0004,0x0000,-1,0x0008,0x0202, \
-+-1,0x0009,0x0000,-1,0x000A,0x0000,-1,0x000C,0x0000,-1,0x000D,0x0000,-1,0x000F,0x0000,-1,0x0010,0x0000,-1,0x0011,0x0007, \
-+-1,0x0012,0x0000,-1,0x0013,0x0000,-2,200,-1,0x0010,0x17B0,-1,0x0011,0x0031,-2,50,-1,0x0012,0x0138,-2,50,-1,0x0013,0x1800, \
-+-1,0x0029,0x0008,-2,50,-1,0x0020,0x0000,-1,0x0021,0x0000,-1,0x0030,0x0000,-1,0x0031,0x0505,-1,0x0032,0x0004, \
-+-1,0x0035,0x0006,-1,0x0036,0x0707,-1,0x0037,0x0105,-1,0x0038,0x0002,-1,0x0039,0x0707,-1,0x003C,0x0704,-1,0x003D,0x0807, \
-+-1,0x0050,0x0000,-1,0x0051,0x00EF,-1,0x0052,0x0000,-1,0x0053,0x013F,-1,0x0060,0x2700,-1,0x0061,0x0001,-1,0x006A,0x0000, \
-+-1,0x0080,0x0000,-1,0x0081,0x0000,-1,0x0082,0x0000,-1,0x0083,0x0000,-1,0x0084,0x0000,-1,0x0085,0x0000,-1,0x0090,0x0010, \
-+-1,0x0092,0x0000,-1,0x0093,0x0003,-1,0x0095,0x0110,-1,0x0097,0x0000,-1,0x0098,0x0000,-1,0x0007,0x0173,-3 };
-+
-+static int ili9325_init[] = { \
-+-1,0x00E3,0x3008,-1,0x00E7,0x0012,-1,0x00EF,0x1231,-1,0x0001,0x0100,-1,0x0002,0x0700,-1,0x0003,0x1030,-1,0x0004,0x0000, \
-+-1,0x0008,0x0207,-1,0x0009,0x0000,-1,0x000A,0x0000,-1,0x000C,0x0000,-1,0x000D,0x0000,-1,0x000F,0x0000,-1,0x0010,0x0000, \
-+-1,0x0011,0x0007,-1,0x0012,0x0000,-1,0x0013,0x0000,-2,200,-1,0x0010,0x1690,-1,0x0011,0x0223,-2,50,-1,0x0012,0x000D,-2,50, \
-+-1,0x0013,0x1200,-1,0x0029,0x000A,-1,0x002B,0x000C,-2,50,-1,0x0020,0x0000,-1,0x0021,0x0000,-1,0x0030,0x0000, \
-+-1,0x0031,0x0506,-1,0x0032,0x0104,-1,0x0035,0x0207,-1,0x0036,0x000F,-1,0x0037,0x0306,-1,0x0038,0x0102,-1,0x0039,0x0707, \
-+-1,0x003C,0x0702,-1,0x003D,0x1604,-1,0x0050,0x0000,-1,0x0051,0x00EF,-1,0x0052,0x0000,-1,0x0053,0x013F,-1,0x0060,0xA700, \
-+-1,0x0061,0x0001,-1,0x006A,0x0000,-1,0x0080,0x0000,-1,0x0081,0x0000,-1,0x0082,0x0000,-1,0x0083,0x0000,-1,0x0084,0x0000, \
-+-1,0x0085,0x0000,-1,0x0090,0x0010,-1,0x0092,0x0600,-1,0x0007,0x0133,-3 };
-+
-+static int ili9341_init[] = { \
-+-1,0x28,-2,20,-1,0xCF,0x00,0x83,0x30,-1,0xED,0x64,0x03,0x12,0x81,-1,0xE8,0x85,0x01,0x79, \
-+-1,0xCB,0x39,0x2c,0x00,0x34,0x02,-1,0xF7,0x20,-1,0xEA,0x00,0x00,-1,0xC0,0x26,-1,0xC1,0x11, \
-+-1,0xC5,0x35,0x3E,-1,0xC7,0xBE,-1,0xB1,0x00,0x1B,-1,0xB6,0x0a,0x82,0x27,0x00,-1,0xB7,0x07, \
-+-1,0x3A,0x55,-1,0x36,0x48,-1,0x11,-2,120,-1,0x29,-2,20,-3 };
-+
-+static int ssd1351_init[] = { -1,0xfd,0x12,-1,0xfd,0xb1,-1,0xae,-1,0xb3,0xf1,-1,0xca,0x7f,-1,0xa0,0x74, \
-+ -1,0x15,0x00,0x7f,-1,0x75,0x00,0x7f,-1,0xa1,0x00,-1,0xa2,0x00,-1,0xb5,0x00, \
-+ -1,0xab,0x01,-1,0xb1,0x32,-1,0xb4,0xa0,0xb5,0x55,-1,0xbb,0x17,-1,0xbe,0x05, \
-+ -1,0xc1,0xc8,0x80,0xc8,-1,0xc7,0x0f,-1,0xb6,0x01,-1,0xa6,-1,0xaf,-3 };
-+
-+
-+/* ili9320, ili9325 */
-+static void flexfb_set_addr_win_1(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+ switch (par->info->var.rotate) {
-+ /* R20h = Horizontal GRAM Start Address */
-+ /* R21h = Vertical GRAM Start Address */
-+ case 0:
-+ write_reg(par, 0x0020, xs);
-+ write_reg(par, 0x0021, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x0020, width - 1 - xs);
-+ write_reg(par, 0x0021, height - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x0020, width - 1 - ys);
-+ write_reg(par, 0x0021, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x0020, ys);
-+ write_reg(par, 0x0021, height - 1 - xs);
-+ break;
-+ }
-+ write_reg(par, 0x0022); /* Write Data to GRAM */
-+}
-+
-+/* ssd1289 */
-+static void flexfb_set_addr_win_2(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ switch (par->info->var.rotate) {
-+ /* R4Eh - Set GDDRAM X address counter */
-+ /* R4Fh - Set GDDRAM Y address counter */
-+ case 0:
-+ write_reg(par, 0x4e, xs);
-+ write_reg(par, 0x4f, ys);
-+ break;
-+ case 180:
-+ write_reg(par, 0x4e, par->info->var.xres - 1 - xs);
-+ write_reg(par, 0x4f, par->info->var.yres - 1 - ys);
-+ break;
-+ case 270:
-+ write_reg(par, 0x4e, par->info->var.yres - 1 - ys);
-+ write_reg(par, 0x4f, xs);
-+ break;
-+ case 90:
-+ write_reg(par, 0x4e, ys);
-+ write_reg(par, 0x4f, par->info->var.xres - 1 - xs);
-+ break;
-+ }
-+
-+ /* R22h - RAM data write */
-+ write_reg(par, 0x22, 0);
-+}
-+
-+/* ssd1351 */
-+static void set_addr_win_3(struct fbtft_par *par, int xs, int ys, int xe, int ye)
-+{
-+ fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
-+
-+ write_reg(par, 0x15, xs, xe);
-+ write_reg(par, 0x75, ys, ye);
-+ write_reg(par, 0x5C);
-+}
-+
-+static int flexfb_verify_gpios_dc(struct fbtft_par *par)
-+{
-+ fbtft_par_dbg(DEBUG_VERIFY_GPIOS, par, "%s()\n", __func__);
-+
-+ if (par->gpio.dc < 0) {
-+ dev_err(par->info->device, "Missing info about 'dc' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int flexfb_verify_gpios_db(struct fbtft_par *par)
-+{
-+ int i;
-+ int num_db = buswidth;
-+
-+ fbtft_par_dbg(DEBUG_VERIFY_GPIOS, par, "%s()\n", __func__);
-+
-+ if (par->gpio.dc < 0) {
-+ dev_err(par->info->device, "Missing info about 'dc' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ if (par->gpio.wr < 0) {
-+ dev_err(par->info->device, "Missing info about 'wr' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ if (latched && (par->gpio.latch < 0)) {
-+ dev_err(par->info->device, "Missing info about 'latch' gpio. Aborting.\n");
-+ return -EINVAL;
-+ }
-+ if (latched)
-+ num_db=buswidth/2;
-+ for (i=0;i < num_db;i++) {
-+ if (par->gpio.db[i] < 0) {
-+ dev_err(par->info->device, "Missing info about 'db%02d' gpio. Aborting.\n", i);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static struct fbtft_display flex_display = { };
-+
-+static int flexfb_probe_common(struct spi_device *sdev, struct platform_device *pdev)
-+{
-+ struct device *dev;
-+ struct fb_info *info;
-+ struct fbtft_par *par;
-+ int ret;
-+
-+ initp = init;
-+ initp_num = init_num;
-+
-+ if (sdev)
-+ dev = &sdev->dev;
-+ else
-+ dev = &pdev->dev;
-+
-+ fbtft_init_dbg(dev, "%s(%s)\n", __func__, sdev ? "'SPI device'" : "'Platform device'");
-+
-+ if (chip) {
-+
-+ if (!strcmp(chip, "st7735r")) {
-+ if (!width)
-+ width = 128;
-+ if (!height)
-+ height = 160;
-+ if (init_num == 0) {
-+ initp = st7735r_init;
-+ initp_num = ARRAY_SIZE(st7735r_init);
-+ }
-+
-+
-+ } else if (!strcmp(chip, "hx8340bn")) {
-+ if (!width)
-+ width = 176;
-+ if (!height)
-+ height = 220;
-+ setaddrwin = 0;
-+ if (init_num == 0) {
-+ initp = hx8340bn_init;
-+ initp_num = ARRAY_SIZE(hx8340bn_init);
-+ }
-+
-+
-+ } else if (!strcmp(chip, "ili9225")) {
-+ if (!width)
-+ width = 176;
-+ if (!height)
-+ height = 220;
-+ setaddrwin = 0;
-+ regwidth = 16;
-+ if (init_num == 0) {
-+ initp = ili9225_init;
-+ initp_num = ARRAY_SIZE(ili9225_init);
-+ }
-+
-+
-+
-+ } else if (!strcmp(chip, "ili9320")) {
-+ if (!width)
-+ width = 240;
-+ if (!height)
-+ height = 320;
-+ setaddrwin = 1;
-+ regwidth = 16;
-+ if (init_num == 0) {
-+ initp = ili9320_init;
-+ initp_num = ARRAY_SIZE(ili9320_init);
-+ }
-+
-+
-+ } else if (!strcmp(chip, "ili9325")) {
-+ if (!width)
-+ width = 240;
-+ if (!height)
-+ height = 320;
-+ setaddrwin = 1;
-+ regwidth = 16;
-+ if (init_num == 0) {
-+ initp = ili9325_init;
-+ initp_num = ARRAY_SIZE(ili9325_init);
-+ }
-+
-+ } else if (!strcmp(chip, "ili9341")) {
-+ if (!width)
-+ width = 240;
-+ if (!height)
-+ height = 320;
-+ setaddrwin = 0;
-+ regwidth = 8;
-+ if (init_num == 0) {
-+ initp = ili9341_init;
-+ initp_num = ARRAY_SIZE(ili9341_init);
-+ }
-+
-+
-+ } else if (!strcmp(chip, "ssd1289")) {
-+ if (!width)
-+ width = 240;
-+ if (!height)
-+ height = 320;
-+ setaddrwin = 2;
-+ regwidth = 16;
-+ if (init_num == 0) {
-+ initp = ssd1289_init;
-+ initp_num = ARRAY_SIZE(ssd1289_init);
-+ }
-+
-+
-+
-+ } else if (!strcmp(chip, "ssd1351")) {
-+ if (!width)
-+ width = 128;
-+ if (!height)
-+ height = 128;
-+ setaddrwin = 3;
-+ if (init_num == 0) {
-+ initp = ssd1351_init;
-+ initp_num = ARRAY_SIZE(ssd1351_init);
-+ }
-+ } else {
-+ dev_err(dev, "chip=%s is not supported\n", chip);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ if (width == 0 || height == 0) {
-+ dev_err(dev, "argument(s) missing: width and height has to be set.\n");
-+ return -EINVAL;
-+ }
-+ flex_display.width = width;
-+ flex_display.height = height;
-+ fbtft_init_dbg(dev, "Display resolution: %dx%d\n", width, height);
-+ fbtft_init_dbg(dev, "chip = %s\n", chip ? chip : "not set");
-+ fbtft_init_dbg(dev, "setaddrwin = %d\n", setaddrwin);
-+ fbtft_init_dbg(dev, "regwidth = %d\n", regwidth);
-+ fbtft_init_dbg(dev, "buswidth = %d\n", buswidth);
-+
-+ info = fbtft_framebuffer_alloc(&flex_display, dev);
-+ if (!info)
-+ return -ENOMEM;
-+
-+ par = info->par;
-+ if (sdev)
-+ par->spi = sdev;
-+ else
-+ par->pdev = pdev;
-+ if (!par->init_sequence)
-+ par->init_sequence = initp;
-+ par->fbtftops.init_display = fbtft_init_display;
-+
-+ /* registerwrite functions */
-+ switch (regwidth) {
-+ case 8:
-+ par->fbtftops.write_register = fbtft_write_reg8_bus8;
-+ break;
-+ case 16:
-+ par->fbtftops.write_register = fbtft_write_reg16_bus8;
-+ break;
-+ default:
-+ dev_err(dev, "argument 'regwidth': %d is not supported.\n", regwidth);
-+ return -EINVAL;
-+ }
-+
-+ /* bus functions */
-+ if (sdev) {
-+ par->fbtftops.write = fbtft_write_spi;
-+ switch (buswidth) {
-+ case 8:
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus8;
-+ if (!par->startbyte)
-+ par->fbtftops.verify_gpios = flexfb_verify_gpios_dc;
-+ break;
-+ case 9:
-+ if (regwidth == 16) {
-+ dev_err(dev, "argument 'regwidth': %d is not supported with buswidth=%d and SPI.\n", regwidth, buswidth);
-+ return -EINVAL;
-+ }
-+ par->fbtftops.write_register = fbtft_write_reg8_bus9;
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus9;
-+ sdev->bits_per_word=9;
-+ ret = sdev->master->setup(sdev);
-+ if (ret) {
-+ dev_warn(dev,
-+ "9-bit SPI not available, emulating using 8-bit.\n");
-+ sdev->bits_per_word = 8;
-+ ret = sdev->master->setup(sdev);
-+ if (ret)
-+ goto out_release;
-+ /* allocate buffer with room for dc bits */
-+ par->extra = devm_kzalloc(par->info->device,
-+ par->txbuf.len + (par->txbuf.len / 8) + 8,
-+ GFP_KERNEL);
-+ if (!par->extra) {
-+ ret = -ENOMEM;
-+ goto out_release;
-+ }
-+ par->fbtftops.write = fbtft_write_spi_emulate_9;
-+ }
-+ break;
-+ default:
-+ dev_err(dev, "argument 'buswidth': %d is not supported with SPI.\n", buswidth);
-+ return -EINVAL;
-+ }
-+ } else {
-+ par->fbtftops.verify_gpios = flexfb_verify_gpios_db;
-+ switch (buswidth) {
-+ case 8:
-+ par->fbtftops.write = fbtft_write_gpio8_wr;
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus8;
-+ break;
-+ case 16:
-+ par->fbtftops.write_register = fbtft_write_reg16_bus16;
-+ if (latched)
-+ par->fbtftops.write = fbtft_write_gpio16_wr_latched;
-+ else
-+ par->fbtftops.write = fbtft_write_gpio16_wr;
-+ par->fbtftops.write_vmem = fbtft_write_vmem16_bus16;
-+ break;
-+ default:
-+ dev_err(dev, "argument 'buswidth': %d is not supported with parallel.\n", buswidth);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* set_addr_win function */
-+ switch (setaddrwin) {
-+ case 0:
-+ /* use default */
-+ break;
-+ case 1:
-+ par->fbtftops.set_addr_win = flexfb_set_addr_win_1;
-+ break;
-+ case 2:
-+ par->fbtftops.set_addr_win = flexfb_set_addr_win_2;
-+ break;
-+ case 3:
-+ par->fbtftops.set_addr_win = set_addr_win_3;
-+ break;
-+ default:
-+ dev_err(dev, "argument 'setaddrwin': unknown value %d.\n", setaddrwin);
-+ return -EINVAL;
-+ }
-+
-+ if (!nobacklight)
-+ par->fbtftops.register_backlight = fbtft_register_backlight;
-+
-+ ret = fbtft_register_framebuffer(info);
-+ if (ret < 0)
-+ goto out_release;
-+
-+ return 0;
-+
-+out_release:
-+ fbtft_framebuffer_release(info);
-+
-+ return ret;
-+}
-+
-+static int flexfb_remove_common(struct device *dev, struct fb_info *info)
-+{
-+ struct fbtft_par *par;
-+
-+ if (!info)
-+ return -EINVAL;
-+ par = info->par;
-+ if (par)
-+ fbtft_par_dbg(DEBUG_DRIVER_INIT_FUNCTIONS, par,
-+ "%s()\n", __func__);
-+ fbtft_unregister_framebuffer(info);
-+ fbtft_framebuffer_release(info);
-+
-+ return 0;
-+}
-+
-+static int flexfb_probe_spi(struct spi_device *spi)
-+{
-+ return flexfb_probe_common(spi, NULL);
-+}
-+
-+static int flexfb_remove_spi(struct spi_device *spi)
-+{
-+ struct fb_info *info = spi_get_drvdata(spi);
-+
-+ return flexfb_remove_common(&spi->dev, info);
-+}
-+
-+static int flexfb_probe_pdev(struct platform_device *pdev)
-+{
-+ return flexfb_probe_common(NULL, pdev);
-+}
-+
-+static int flexfb_remove_pdev(struct platform_device *pdev)
-+{
-+ struct fb_info *info = platform_get_drvdata(pdev);
-+
-+ return flexfb_remove_common(&pdev->dev, info);
-+}
-+
-+static struct spi_driver flexfb_spi_driver = {
-+ .driver = {
-+ .name = DRVNAME,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = flexfb_probe_spi,
-+ .remove = flexfb_remove_spi,
-+};
-+
-+static const struct platform_device_id flexfb_platform_ids[] = {
-+ { "flexpfb", 0 },
-+ { },
-+};
-+
-+static struct platform_driver flexfb_platform_driver = {
-+ .driver = {
-+ .name = DRVNAME,
-+ },
-+ .id_table = flexfb_platform_ids,
-+ .probe = flexfb_probe_pdev,
-+ .remove = flexfb_remove_pdev,
-+};
-+
-+static int __init flexfb_init(void)
-+{
-+ int ret, ret2;
-+
-+ ret = spi_register_driver(&flexfb_spi_driver);
-+ ret2 = platform_driver_register(&flexfb_platform_driver);
-+ if (ret < 0)
-+ return ret;
-+ return ret2;
-+}
-+
-+static void __exit flexfb_exit(void)
-+{
-+ spi_unregister_driver(&flexfb_spi_driver);
-+ platform_driver_unregister(&flexfb_platform_driver);
-+}
-+
-+/* ------------------------------------------------------------------------- */
-+
-+module_init(flexfb_init);
-+module_exit(flexfb_exit);
-+
-+MODULE_DESCRIPTION("Generic FB driver for TFT LCD displays");
-+MODULE_AUTHOR("Noralf Tronnes");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/staging/fbtft/Kconfig linux-rpi/drivers/staging/fbtft/Kconfig
---- linux-3.18.14/drivers/staging/fbtft/Kconfig 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/Kconfig 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,169 @@
-+menuconfig FB_TFT
-+ tristate "Support for small TFT LCD display modules"
-+ depends on FB && SPI && GPIOLIB
-+ select FB_SYS_FILLRECT
-+ select FB_SYS_COPYAREA
-+ select FB_SYS_IMAGEBLIT
-+ select FB_SYS_FOPS
-+ select FB_DEFERRED_IO
-+ select FB_BACKLIGHT
-+
-+config FB_TFT_AGM1264K_FL
-+ tristate "FB driver for the AGM1264K-FL LCD display"
-+ depends on FB_TFT
-+ help
-+ Framebuffer support for the AGM1264K-FL LCD display (two Samsung KS0108 compatable chips)
-+
-+config FB_TFT_BD663474
-+ tristate "FB driver for the BD663474 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for BD663474
-+
-+config FB_TFT_HX8340BN
-+ tristate "FB driver for the HX8340BN LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for HX8340BN
-+
-+config FB_TFT_HX8347D
-+ tristate "FB driver for the HX8347D LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for HX8347D
-+
-+config FB_TFT_HX8353D
-+ tristate "FB driver for the HX8353D LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for HX8353D
-+
-+config FB_TFT_ILI9320
-+ tristate "FB driver for the ILI9320 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ILI9320
-+
-+config FB_TFT_ILI9325
-+ tristate "FB driver for the ILI9325 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ILI9325
-+
-+config FB_TFT_ILI9340
-+ tristate "FB driver for the ILI9340 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ILI9340
-+
-+config FB_TFT_ILI9341
-+ tristate "FB driver for the ILI9341 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ILI9341
-+
-+config FB_TFT_ILI9481
-+ tristate "FB driver for the ILI9481 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ILI9481
-+
-+config FB_TFT_ILI9486
-+ tristate "FB driver for the ILI9486 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ILI9486
-+
-+config FB_TFT_PCD8544
-+ tristate "FB driver for the PCD8544 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for PCD8544
-+
-+config FB_TFT_RA8875
-+ tristate "FB driver for the RA8875 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for RA8875
-+
-+config FB_TFT_S6D02A1
-+ tristate "FB driver for the S6D02A1 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for S6D02A1
-+
-+config FB_TFT_S6D1121
-+ tristate "FB driver for the S6D1211 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for S6D1121
-+
-+config FB_TFT_SSD1289
-+ tristate "FB driver for the SSD1289 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Framebuffer support for SSD1289
-+
-+config FB_TFT_SSD1306
-+ tristate "FB driver for the SSD1306 OLED Controller"
-+ depends on FB_TFT
-+ help
-+ Framebuffer support for SSD1306
-+
-+config FB_TFT_SSD1331
-+ tristate "FB driver for the SSD1331 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Framebuffer support for SSD1331
-+
-+config FB_TFT_SSD1351
-+ tristate "FB driver for the SSD1351 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Framebuffer support for SSD1351
-+
-+config FB_TFT_ST7735R
-+ tristate "FB driver for the ST7735R LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for ST7735R
-+
-+config FB_TFT_TINYLCD
-+ tristate "FB driver for tinylcd.com display"
-+ depends on FB_TFT
-+ help
-+ Custom Framebuffer support for tinylcd.com display
-+
-+config FB_TFT_TLS8204
-+ tristate "FB driver for the TLS8204 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for TLS8204
-+
-+config FB_TFT_UC1701
-+ tristate "FB driver for the UC1701 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for UC1701
-+
-+config FB_TFT_UPD161704
-+ tristate "FB driver for the uPD161704 LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for uPD161704
-+
-+config FB_TFT_WATTEROTT
-+ tristate "FB driver for the WATTEROTT LCD Controller"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for WATTEROTT
-+
-+config FB_FLEX
-+ tristate "Generic FB driver for TFT LCD displays"
-+ depends on FB_TFT
-+ help
-+ Generic Framebuffer support for TFT LCD displays.
-+
-+config FB_TFT_FBTFT_DEVICE
-+ tristate "Module to for adding FBTFT devices"
-+ depends on FB_TFT
-diff -Nur linux-3.18.14/drivers/staging/fbtft/Makefile linux-rpi/drivers/staging/fbtft/Makefile
---- linux-3.18.14/drivers/staging/fbtft/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/Makefile 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,34 @@
-+# Core module
-+obj-$(CONFIG_FB_TFT) += fbtft.o
-+fbtft-y += fbtft-core.o fbtft-sysfs.o fbtft-bus.o fbtft-io.o
-+
-+# drivers
-+obj-$(CONFIG_FB_TFT_AGM1264K_FL) += fb_agm1264k-fl.o
-+obj-$(CONFIG_FB_TFT_BD663474) += fb_bd663474.o
-+obj-$(CONFIG_FB_TFT_HX8340BN) += fb_hx8340bn.o
-+obj-$(CONFIG_FB_TFT_HX8347D) += fb_hx8347d.o
-+obj-$(CONFIG_FB_TFT_HX8353D) += fb_hx8353d.o
-+obj-$(CONFIG_FB_TFT_ILI9320) += fb_ili9320.o
-+obj-$(CONFIG_FB_TFT_ILI9325) += fb_ili9325.o
-+obj-$(CONFIG_FB_TFT_ILI9340) += fb_ili9340.o
-+obj-$(CONFIG_FB_TFT_ILI9341) += fb_ili9341.o
-+obj-$(CONFIG_FB_TFT_ILI9481) += fb_ili9481.o
-+obj-$(CONFIG_FB_TFT_ILI9486) += fb_ili9486.o
-+obj-$(CONFIG_FB_TFT_PCD8544) += fb_pcd8544.o
-+obj-$(CONFIG_FB_TFT_RA8875) += fb_ra8875.o
-+obj-$(CONFIG_FB_TFT_S6D02A1) += fb_s6d02a1.o
-+obj-$(CONFIG_FB_TFT_S6D1121) += fb_s6d1121.o
-+obj-$(CONFIG_FB_TFT_SSD1289) += fb_ssd1289.o
-+obj-$(CONFIG_FB_TFT_SSD1306) += fb_ssd1306.o
-+obj-$(CONFIG_FB_TFT_SSD1331) += fb_ssd1331.o
-+obj-$(CONFIG_FB_TFT_SSD1351) += fb_ssd1351.o
-+obj-$(CONFIG_FB_TFT_ST7735R) += fb_st7735r.o
-+obj-$(CONFIG_FB_TFT_TINYLCD) += fb_tinylcd.o
-+obj-$(CONFIG_FB_TFT_TLS8204) += fb_tls8204.o
-+obj-$(CONFIG_FB_TFT_UC1701) += fb_uc1701.o
-+obj-$(CONFIG_FB_TFT_UPD161704) += fb_upd161704.o
-+obj-$(CONFIG_FB_TFT_WATTEROTT) += fb_watterott.o
-+obj-$(CONFIG_FB_FLEX) += flexfb.o
-+
-+# Device modules
-+obj-$(CONFIG_FB_TFT_FBTFT_DEVICE) += fbtft_device.o
-diff -Nur linux-3.18.14/drivers/staging/fbtft/README linux-rpi/drivers/staging/fbtft/README
---- linux-3.18.14/drivers/staging/fbtft/README 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/fbtft/README 2015-05-31 14:46:12.565660964 -0500
-@@ -0,0 +1,32 @@
-+ FBTFT
-+=========
-+
-+Linux Framebuffer drivers for small TFT LCD display modules.
-+The module 'fbtft' makes writing drivers for some of these displays very easy.
-+
-+Development is done on a Raspberry Pi running the Raspbian "wheezy" distribution.
-+
-+INSTALLATION
-+ Download kernel sources
-+
-+ From Linux 3.15
-+ cd drivers/video/fbdev/fbtft
-+ git clone https://github.com/notro/fbtft.git
-+
-+ Add to drivers/video/fbdev/Kconfig: source "drivers/video/fbdev/fbtft/Kconfig"
-+ Add to drivers/video/fbdev/Makefile: obj-y += fbtft/
-+
-+ Before Linux 3.15
-+ cd drivers/video
-+ git clone https://github.com/notro/fbtft.git
-+
-+ Add to drivers/video/Kconfig: source "drivers/video/fbtft/Kconfig"
-+ Add to drivers/video/Makefile: obj-y += fbtft/
-+
-+ Enable driver(s) in menuconfig and build the kernel
-+
-+
-+See wiki for more information: https://github.com/notro/fbtft/wiki
-+
-+
-+Source: https://github.com/notro/fbtft/
-diff -Nur linux-3.18.14/drivers/staging/Kconfig linux-rpi/drivers/staging/Kconfig
---- linux-3.18.14/drivers/staging/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/staging/Kconfig 2015-05-31 14:46:12.505660965 -0500
-@@ -108,4 +108,6 @@
-
- source "drivers/staging/unisys/Kconfig"
-
-+source "drivers/staging/fbtft/Kconfig"
-+
- endif # STAGING
-diff -Nur linux-3.18.14/drivers/staging/Makefile linux-rpi/drivers/staging/Makefile
---- linux-3.18.14/drivers/staging/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/staging/Makefile 2015-05-31 14:46:12.505660965 -0500
-@@ -46,3 +46,4 @@
- obj-$(CONFIG_GS_FPGABOOT) += gs_fpgaboot/
- obj-$(CONFIG_CRYPTO_SKEIN) += skein/
- obj-$(CONFIG_UNISYSSPAR) += unisys/
-+obj-$(CONFIG_FB_TFT) += fbtft/
-diff -Nur linux-3.18.14/drivers/staging/media/lirc/Kconfig linux-rpi/drivers/staging/media/lirc/Kconfig
---- linux-3.18.14/drivers/staging/media/lirc/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/staging/media/lirc/Kconfig 2015-05-31 14:46:12.665660964 -0500
-@@ -38,6 +38,12 @@
- help
- Driver for Homebrew Parallel Port Receivers
-
-+config LIRC_RPI
-+ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi"
-+ depends on LIRC
-+ help
-+ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi
-+
- config LIRC_SASEM
- tristate "Sasem USB IR Remote"
- depends on LIRC && USB
-diff -Nur linux-3.18.14/drivers/staging/media/lirc/lirc_rpi.c linux-rpi/drivers/staging/media/lirc/lirc_rpi.c
---- linux-3.18.14/drivers/staging/media/lirc/lirc_rpi.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/staging/media/lirc/lirc_rpi.c 2015-05-31 14:46:12.665660964 -0500
-@@ -0,0 +1,765 @@
-+/*
-+ * lirc_rpi.c
-+ *
-+ * lirc_rpi - Device driver that records pulse- and pause-lengths
-+ * (space-lengths) (just like the lirc_serial driver does)
-+ * between GPIO interrupt events on the Raspberry Pi.
-+ * Lots of code has been taken from the lirc_serial module,
-+ * so I would like say thanks to the authors.
-+ *
-+ * Copyright (C) 2012 Aron Robert Szabo <aron@reon.hu>,
-+ * Michael Bishop <cleverca22@gmail.com>
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/time.h>
-+#include <linux/timex.h>
-+#include <linux/timekeeping.h>
-+#include <linux/string.h>
-+#include <linux/delay.h>
-+#include <linux/platform_device.h>
-+#include <linux/irq.h>
-+#include <linux/spinlock.h>
-+#include <media/lirc.h>
-+#include <media/lirc_dev.h>
-+#include <mach/gpio.h>
-+#include <linux/gpio.h>
-+#include <linux/of_platform.h>
-+
-+#include <linux/platform_data/bcm2708.h>
-+
-+#define LIRC_DRIVER_NAME "lirc_rpi"
-+#define RBUF_LEN 256
-+#define LIRC_TRANSMITTER_LATENCY 50
-+
-+#ifndef MAX_UDELAY_MS
-+#define MAX_UDELAY_US 5000
-+#else
-+#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
-+#endif
-+
-+#define dprintk(fmt, args...) \
-+ do { \
-+ if (debug) \
-+ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
-+ fmt, ## args); \
-+ } while (0)
-+
-+/* module parameters */
-+
-+/* set the default GPIO input pin */
-+static int gpio_in_pin = 18;
-+/* set the default pull behaviour for input pin */
-+static int gpio_in_pull = BCM2708_PULL_DOWN;
-+/* set the default GPIO output pin */
-+static int gpio_out_pin = 17;
-+/* enable debugging messages */
-+static bool debug;
-+/* -1 = auto, 0 = active high, 1 = active low */
-+static int sense = -1;
-+/* use softcarrier by default */
-+static bool softcarrier = 1;
-+/* 0 = do not invert output, 1 = invert output */
-+static bool invert = 0;
-+
-+struct gpio_chip *gpiochip;
-+static int irq_num;
-+
-+/* forward declarations */
-+static long send_pulse(unsigned long length);
-+static void send_space(long length);
-+static void lirc_rpi_exit(void);
-+
-+static struct platform_device *lirc_rpi_dev;
-+static struct timeval lasttv = { 0, 0 };
-+static struct lirc_buffer rbuf;
-+static spinlock_t lock;
-+
-+/* initialized/set in init_timing_params() */
-+static unsigned int freq = 38000;
-+static unsigned int duty_cycle = 50;
-+static unsigned long period;
-+static unsigned long pulse_width;
-+static unsigned long space_width;
-+
-+static void safe_udelay(unsigned long usecs)
-+{
-+ while (usecs > MAX_UDELAY_US) {
-+ udelay(MAX_UDELAY_US);
-+ usecs -= MAX_UDELAY_US;
-+ }
-+ udelay(usecs);
-+}
-+
-+static unsigned long read_current_us(void)
-+{
-+ struct timespec now;
-+ getnstimeofday(&now);
-+ return (now.tv_sec * 1000000) + (now.tv_nsec/1000);
-+}
-+
-+static int init_timing_params(unsigned int new_duty_cycle,
-+ unsigned int new_freq)
-+{
-+ if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <=
-+ LIRC_TRANSMITTER_LATENCY)
-+ return -EINVAL;
-+ if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <=
-+ LIRC_TRANSMITTER_LATENCY)
-+ return -EINVAL;
-+ duty_cycle = new_duty_cycle;
-+ freq = new_freq;
-+ period = 1000 * 1000000L / freq;
-+ pulse_width = period * duty_cycle / 100;
-+ space_width = period - pulse_width;
-+ dprintk("in init_timing_params, freq=%d pulse=%ld, "
-+ "space=%ld\n", freq, pulse_width, space_width);
-+ return 0;
-+}
-+
-+static long send_pulse_softcarrier(unsigned long length)
-+{
-+ int flag;
-+ unsigned long actual, target;
-+ unsigned long actual_us, initial_us, target_us;
-+
-+ length *= 1000;
-+
-+ actual = 0; target = 0; flag = 0;
-+ actual_us = read_current_us();
-+
-+ while (actual < length) {
-+ if (flag) {
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+ target += space_width;
-+ } else {
-+ gpiochip->set(gpiochip, gpio_out_pin, !invert);
-+ target += pulse_width;
-+ }
-+ initial_us = actual_us;
-+ target_us = actual_us + (target - actual) / 1000;
-+ /*
-+ * Note - we've checked in ioctl that the pulse/space
-+ * widths are big enough so that d is > 0
-+ */
-+ if ((int)(target_us - actual_us) > 0)
-+ udelay(target_us - actual_us);
-+ actual_us = read_current_us();
-+ actual += (actual_us - initial_us) * 1000;
-+ flag = !flag;
-+ }
-+ return (actual-length) / 1000;
-+}
-+
-+static long send_pulse(unsigned long length)
-+{
-+ if (length <= 0)
-+ return 0;
-+
-+ if (softcarrier) {
-+ return send_pulse_softcarrier(length);
-+ } else {
-+ gpiochip->set(gpiochip, gpio_out_pin, !invert);
-+ safe_udelay(length);
-+ return 0;
-+ }
-+}
-+
-+static void send_space(long length)
-+{
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+ if (length <= 0)
-+ return;
-+ safe_udelay(length);
-+}
-+
-+static void rbwrite(int l)
-+{
-+ if (lirc_buffer_full(&rbuf)) {
-+ /* no new signals will be accepted */
-+ dprintk("Buffer overrun\n");
-+ return;
-+ }
-+ lirc_buffer_write(&rbuf, (void *)&l);
-+}
-+
-+static void frbwrite(int l)
-+{
-+ /* simple noise filter */
-+ static int pulse, space;
-+ static unsigned int ptr;
-+
-+ if (ptr > 0 && (l & PULSE_BIT)) {
-+ pulse += l & PULSE_MASK;
-+ if (pulse > 250) {
-+ rbwrite(space);
-+ rbwrite(pulse | PULSE_BIT);
-+ ptr = 0;
-+ pulse = 0;
-+ }
-+ return;
-+ }
-+ if (!(l & PULSE_BIT)) {
-+ if (ptr == 0) {
-+ if (l > 20000) {
-+ space = l;
-+ ptr++;
-+ return;
-+ }
-+ } else {
-+ if (l > 20000) {
-+ space += pulse;
-+ if (space > PULSE_MASK)
-+ space = PULSE_MASK;
-+ space += l;
-+ if (space > PULSE_MASK)
-+ space = PULSE_MASK;
-+ pulse = 0;
-+ return;
-+ }
-+ rbwrite(space);
-+ rbwrite(pulse | PULSE_BIT);
-+ ptr = 0;
-+ pulse = 0;
-+ }
-+ }
-+ rbwrite(l);
-+}
-+
-+static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs)
-+{
-+ struct timeval tv;
-+ long deltv;
-+ int data;
-+ int signal;
-+
-+ /* use the GPIO signal level */
-+ signal = gpiochip->get(gpiochip, gpio_in_pin);
-+
-+ if (sense != -1) {
-+ /* get current time */
-+ do_gettimeofday(&tv);
-+
-+ /* calc time since last interrupt in microseconds */
-+ deltv = tv.tv_sec-lasttv.tv_sec;
-+ if (tv.tv_sec < lasttv.tv_sec ||
-+ (tv.tv_sec == lasttv.tv_sec &&
-+ tv.tv_usec < lasttv.tv_usec)) {
-+ printk(KERN_WARNING LIRC_DRIVER_NAME
-+ ": AIEEEE: your clock just jumped backwards\n");
-+ printk(KERN_WARNING LIRC_DRIVER_NAME
-+ ": %d %d %lx %lx %lx %lx\n", signal, sense,
-+ tv.tv_sec, lasttv.tv_sec,
-+ tv.tv_usec, lasttv.tv_usec);
-+ data = PULSE_MASK;
-+ } else if (deltv > 15) {
-+ data = PULSE_MASK; /* really long time */
-+ if (!(signal^sense)) {
-+ /* sanity check */
-+ printk(KERN_WARNING LIRC_DRIVER_NAME
-+ ": AIEEEE: %d %d %lx %lx %lx %lx\n",
-+ signal, sense, tv.tv_sec, lasttv.tv_sec,
-+ tv.tv_usec, lasttv.tv_usec);
-+ /*
-+ * detecting pulse while this
-+ * MUST be a space!
-+ */
-+ sense = sense ? 0 : 1;
-+ }
-+ } else {
-+ data = (int) (deltv*1000000 +
-+ (tv.tv_usec - lasttv.tv_usec));
-+ }
-+ frbwrite(signal^sense ? data : (data|PULSE_BIT));
-+ lasttv = tv;
-+ wake_up_interruptible(&rbuf.wait_poll);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int is_right_chip(struct gpio_chip *chip, void *data)
-+{
-+ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label));
-+
-+ if (strcmp(data, chip->label) == 0)
-+ return 1;
-+ return 0;
-+}
-+
-+static inline int read_bool_property(const struct device_node *np,
-+ const char *propname,
-+ bool *out_value)
-+{
-+ u32 value = 0;
-+ int err = of_property_read_u32(np, propname, &value);
-+ if (err == 0)
-+ *out_value = (value != 0);
-+ return err;
-+}
-+
-+static void read_pin_settings(struct device_node *node)
-+{
-+ u32 pin;
-+ int index;
-+
-+ for (index = 0;
-+ of_property_read_u32_index(
-+ node,
-+ "brcm,pins",
-+ index,
-+ &pin) == 0;
-+ index++) {
-+ u32 function;
-+ int err;
-+ err = of_property_read_u32_index(
-+ node,
-+ "brcm,function",
-+ index,
-+ &function);
-+ if (err == 0) {
-+ if (function == 1) /* Output */
-+ gpio_out_pin = pin;
-+ else if (function == 0) /* Input */
-+ gpio_in_pin = pin;
-+ }
-+ }
-+}
-+
-+static int init_port(void)
-+{
-+ int i, nlow, nhigh, ret;
-+ struct device_node *node;
-+
-+ node = lirc_rpi_dev->dev.of_node;
-+
-+ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip);
-+
-+ /*
-+ * Because of the lack of a setpull function, only support
-+ * pinctrl-bcm2835 if using device tree.
-+ */
-+ if (!gpiochip && node)
-+ gpiochip = gpiochip_find("pinctrl-bcm2835", is_right_chip);
-+
-+ if (!gpiochip) {
-+ pr_err(LIRC_DRIVER_NAME ": gpio chip not found!\n");
-+ return -ENODEV;
-+ }
-+
-+ if (node) {
-+ struct device_node *pins_node;
-+
-+ pins_node = of_parse_phandle(node, "pinctrl-0", 0);
-+ if (!pins_node) {
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": pinctrl settings not found!\n");
-+ ret = -EINVAL;
-+ goto exit_init_port;
-+ }
-+
-+ read_pin_settings(pins_node);
-+
-+ of_property_read_u32(node, "rpi,sense", &sense);
-+
-+ read_bool_property(node, "rpi,softcarrier", &softcarrier);
-+
-+ read_bool_property(node, "rpi,invert", &invert);
-+
-+ read_bool_property(node, "rpi,debug", &debug);
-+
-+ }
-+ else
-+ {
-+ if (gpio_in_pin >= BCM2708_NR_GPIOS ||
-+ gpio_out_pin >= BCM2708_NR_GPIOS) {
-+ ret = -EINVAL;
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": invalid GPIO pin(s) specified!\n");
-+ goto exit_init_port;
-+ }
-+
-+ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) {
-+ printk(KERN_ALERT LIRC_DRIVER_NAME
-+ ": cant claim gpio pin %d\n", gpio_out_pin);
-+ ret = -ENODEV;
-+ goto exit_init_port;
-+ }
-+
-+ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) {
-+ printk(KERN_ALERT LIRC_DRIVER_NAME
-+ ": cant claim gpio pin %d\n", gpio_in_pin);
-+ ret = -ENODEV;
-+ goto exit_gpio_free_out_pin;
-+ }
-+
-+ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull);
-+ gpiochip->direction_input(gpiochip, gpio_in_pin);
-+ gpiochip->direction_output(gpiochip, gpio_out_pin, 1);
-+ }
-+
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+
-+ irq_num = gpiochip->to_irq(gpiochip, gpio_in_pin);
-+ dprintk("to_irq %d\n", irq_num);
-+
-+ /* if pin is high, then this must be an active low receiver. */
-+ if (sense == -1) {
-+ /* wait 1/2 sec for the power supply */
-+ msleep(500);
-+
-+ /*
-+ * probe 9 times every 0.04s, collect "votes" for
-+ * active high/low
-+ */
-+ nlow = 0;
-+ nhigh = 0;
-+ for (i = 0; i < 9; i++) {
-+ if (gpiochip->get(gpiochip, gpio_in_pin))
-+ nlow++;
-+ else
-+ nhigh++;
-+ msleep(40);
-+ }
-+ sense = (nlow >= nhigh ? 1 : 0);
-+ printk(KERN_INFO LIRC_DRIVER_NAME
-+ ": auto-detected active %s receiver on GPIO pin %d\n",
-+ sense ? "low" : "high", gpio_in_pin);
-+ } else {
-+ printk(KERN_INFO LIRC_DRIVER_NAME
-+ ": manually using active %s receiver on GPIO pin %d\n",
-+ sense ? "low" : "high", gpio_in_pin);
-+ }
-+
-+ return 0;
-+
-+ exit_gpio_free_out_pin:
-+ gpio_free(gpio_out_pin);
-+
-+ exit_init_port:
-+ return ret;
-+}
-+
-+// called when the character device is opened
-+static int set_use_inc(void *data)
-+{
-+ int result;
-+
-+ /* initialize timestamp */
-+ do_gettimeofday(&lasttv);
-+
-+ result = request_irq(irq_num,
-+ (irq_handler_t) irq_handler,
-+ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
-+ LIRC_DRIVER_NAME, (void*) 0);
-+
-+ switch (result) {
-+ case -EBUSY:
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": IRQ %d is busy\n",
-+ irq_num);
-+ return -EBUSY;
-+ case -EINVAL:
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": Bad irq number or handler\n");
-+ return -EINVAL;
-+ default:
-+ dprintk("Interrupt %d obtained\n",
-+ irq_num);
-+ break;
-+ };
-+
-+ /* initialize pulse/space widths */
-+ init_timing_params(duty_cycle, freq);
-+
-+ return 0;
-+}
-+
-+static void set_use_dec(void *data)
-+{
-+ /* GPIO Pin Falling/Rising Edge Detect Disable */
-+ irq_set_irq_type(irq_num, 0);
-+ disable_irq(irq_num);
-+
-+ free_irq(irq_num, (void *) 0);
-+
-+ dprintk(KERN_INFO LIRC_DRIVER_NAME
-+ ": freed IRQ %d\n", irq_num);
-+}
-+
-+static ssize_t lirc_write(struct file *file, const char *buf,
-+ size_t n, loff_t *ppos)
-+{
-+ int i, count;
-+ unsigned long flags;
-+ long delta = 0;
-+ int *wbuf;
-+
-+ count = n / sizeof(int);
-+ if (n % sizeof(int) || count % 2 == 0)
-+ return -EINVAL;
-+ wbuf = memdup_user(buf, n);
-+ if (IS_ERR(wbuf))
-+ return PTR_ERR(wbuf);
-+ spin_lock_irqsave(&lock, flags);
-+
-+ for (i = 0; i < count; i++) {
-+ if (i%2)
-+ send_space(wbuf[i] - delta);
-+ else
-+ delta = send_pulse(wbuf[i]);
-+ }
-+ gpiochip->set(gpiochip, gpio_out_pin, invert);
-+
-+ spin_unlock_irqrestore(&lock, flags);
-+ kfree(wbuf);
-+ return n;
-+}
-+
-+static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
-+{
-+ int result;
-+ __u32 value;
-+
-+ switch (cmd) {
-+ case LIRC_GET_SEND_MODE:
-+ return -ENOIOCTLCMD;
-+ break;
-+
-+ case LIRC_SET_SEND_MODE:
-+ result = get_user(value, (__u32 *) arg);
-+ if (result)
-+ return result;
-+ /* only LIRC_MODE_PULSE supported */
-+ if (value != LIRC_MODE_PULSE)
-+ return -ENOSYS;
-+ break;
-+
-+ case LIRC_GET_LENGTH:
-+ return -ENOSYS;
-+ break;
-+
-+ case LIRC_SET_SEND_DUTY_CYCLE:
-+ dprintk("SET_SEND_DUTY_CYCLE\n");
-+ result = get_user(value, (__u32 *) arg);
-+ if (result)
-+ return result;
-+ if (value <= 0 || value > 100)
-+ return -EINVAL;
-+ return init_timing_params(value, freq);
-+ break;
-+
-+ case LIRC_SET_SEND_CARRIER:
-+ dprintk("SET_SEND_CARRIER\n");
-+ result = get_user(value, (__u32 *) arg);
-+ if (result)
-+ return result;
-+ if (value > 500000 || value < 20000)
-+ return -EINVAL;
-+ return init_timing_params(duty_cycle, value);
-+ break;
-+
-+ default:
-+ return lirc_dev_fop_ioctl(filep, cmd, arg);
-+ }
-+ return 0;
-+}
-+
-+static const struct file_operations lirc_fops = {
-+ .owner = THIS_MODULE,
-+ .write = lirc_write,
-+ .unlocked_ioctl = lirc_ioctl,
-+ .read = lirc_dev_fop_read,
-+ .poll = lirc_dev_fop_poll,
-+ .open = lirc_dev_fop_open,
-+ .release = lirc_dev_fop_close,
-+ .llseek = no_llseek,
-+};
-+
-+static struct lirc_driver driver = {
-+ .name = LIRC_DRIVER_NAME,
-+ .minor = -1,
-+ .code_length = 1,
-+ .sample_rate = 0,
-+ .data = NULL,
-+ .add_to_buf = NULL,
-+ .rbuf = &rbuf,
-+ .set_use_inc = set_use_inc,
-+ .set_use_dec = set_use_dec,
-+ .fops = &lirc_fops,
-+ .dev = NULL,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct of_device_id lirc_rpi_of_match[] = {
-+ { .compatible = "rpi,lirc-rpi", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, lirc_rpi_of_match);
-+
-+static struct platform_driver lirc_rpi_driver = {
-+ .driver = {
-+ .name = LIRC_DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(lirc_rpi_of_match),
-+ },
-+};
-+
-+static int __init lirc_rpi_init(void)
-+{
-+ struct device_node *node;
-+ int result;
-+
-+ /* Init read buffer. */
-+ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN);
-+ if (result < 0)
-+ return -ENOMEM;
-+
-+ result = platform_driver_register(&lirc_rpi_driver);
-+ if (result) {
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": lirc register returned %d\n", result);
-+ goto exit_buffer_free;
-+ }
-+
-+ node = of_find_compatible_node(NULL, NULL,
-+ lirc_rpi_of_match[0].compatible);
-+
-+ if (node) {
-+ /* DT-enabled */
-+ lirc_rpi_dev = of_find_device_by_node(node);
-+ WARN_ON(lirc_rpi_dev->dev.of_node != node);
-+ of_node_put(node);
-+ }
-+ else {
-+ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0);
-+ if (!lirc_rpi_dev) {
-+ result = -ENOMEM;
-+ goto exit_driver_unregister;
-+ }
-+
-+ result = platform_device_add(lirc_rpi_dev);
-+ if (result)
-+ goto exit_device_put;
-+ }
-+
-+ return 0;
-+
-+ exit_device_put:
-+ platform_device_put(lirc_rpi_dev);
-+
-+ exit_driver_unregister:
-+ platform_driver_unregister(&lirc_rpi_driver);
-+
-+ exit_buffer_free:
-+ lirc_buffer_free(&rbuf);
-+
-+ return result;
-+}
-+
-+static void lirc_rpi_exit(void)
-+{
-+ if (!lirc_rpi_dev->dev.of_node)
-+ platform_device_unregister(lirc_rpi_dev);
-+ platform_driver_unregister(&lirc_rpi_driver);
-+ lirc_buffer_free(&rbuf);
-+}
-+
-+static int __init lirc_rpi_init_module(void)
-+{
-+ int result;
-+
-+ result = lirc_rpi_init();
-+ if (result)
-+ return result;
-+
-+ result = init_port();
-+ if (result < 0)
-+ goto exit_rpi;
-+
-+ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE |
-+ LIRC_CAN_SET_SEND_CARRIER |
-+ LIRC_CAN_SEND_PULSE |
-+ LIRC_CAN_REC_MODE2;
-+
-+ driver.dev = &lirc_rpi_dev->dev;
-+ driver.minor = lirc_register_driver(&driver);
-+
-+ if (driver.minor < 0) {
-+ printk(KERN_ERR LIRC_DRIVER_NAME
-+ ": device registration failed with %d\n", result);
-+ result = -EIO;
-+ goto exit_rpi;
-+ }
-+
-+ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n");
-+
-+ return 0;
-+
-+ exit_rpi:
-+ lirc_rpi_exit();
-+
-+ return result;
-+}
-+
-+static void __exit lirc_rpi_exit_module(void)
-+{
-+ lirc_unregister_driver(driver.minor);
-+
-+ gpio_free(gpio_out_pin);
-+ gpio_free(gpio_in_pin);
-+
-+ lirc_rpi_exit();
-+
-+ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n");
-+}
-+
-+module_init(lirc_rpi_init_module);
-+module_exit(lirc_rpi_exit_module);
-+
-+MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO.");
-+MODULE_AUTHOR("Aron Robert Szabo <aron@reon.hu>");
-+MODULE_AUTHOR("Michael Bishop <cleverca22@gmail.com>");
-+MODULE_LICENSE("GPL");
-+
-+module_param(gpio_out_pin, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM"
-+ " processor. (default 17");
-+
-+module_param(gpio_in_pin, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor."
-+ " (default 18");
-+
-+module_param(gpio_in_pull, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration."
-+ " (0 = off, 1 = up, 2 = down, default down)");
-+
-+module_param(sense, int, S_IRUGO);
-+MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit"
-+ " (0 = active high, 1 = active low )");
-+
-+module_param(softcarrier, bool, S_IRUGO);
-+MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)");
-+
-+module_param(invert, bool, S_IRUGO);
-+MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off");
-+
-+module_param(debug, bool, S_IRUGO | S_IWUSR);
-+MODULE_PARM_DESC(debug, "Enable debugging messages");
-diff -Nur linux-3.18.14/drivers/staging/media/lirc/Makefile linux-rpi/drivers/staging/media/lirc/Makefile
---- linux-3.18.14/drivers/staging/media/lirc/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/staging/media/lirc/Makefile 2015-05-31 14:46:12.665660964 -0500
-@@ -7,6 +7,7 @@
- obj-$(CONFIG_LIRC_IGORPLUGUSB) += lirc_igorplugusb.o
- obj-$(CONFIG_LIRC_IMON) += lirc_imon.o
- obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o
-+obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o
- obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o
- obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o
- obj-$(CONFIG_LIRC_SIR) += lirc_sir.o
-diff -Nur linux-3.18.14/drivers/thermal/bcm2835-thermal.c linux-rpi/drivers/thermal/bcm2835-thermal.c
---- linux-3.18.14/drivers/thermal/bcm2835-thermal.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/thermal/bcm2835-thermal.c 2015-05-31 14:46:12.801660962 -0500
-@@ -0,0 +1,184 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/sysfs.h>
-+#include <mach/vcio.h>
-+#include <linux/thermal.h>
-+
-+
-+/* --- DEFINITIONS --- */
-+#define MODULE_NAME "bcm2835_thermal"
-+
-+/*#define THERMAL_DEBUG_ENABLE*/
-+
-+#ifdef THERMAL_DEBUG_ENABLE
-+#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+
-+#define VC_TAG_GET_TEMP 0x00030006
-+#define VC_TAG_GET_MAX_TEMP 0x0003000A
-+
-+typedef enum {
-+ TEMP,
-+ MAX_TEMP,
-+} temp_type;
-+
-+/* --- STRUCTS --- */
-+/* tag part of the message */
-+struct vc_msg_tag {
-+ uint32_t tag_id; /* the tag ID for the temperature */
-+ uint32_t buffer_size; /* size of the buffer (should be 8) */
-+ uint32_t request_code; /* identifies message as a request (should be 0) */
-+ uint32_t id; /* extra ID field (should be 0) */
-+ uint32_t val; /* returned value of the temperature */
-+};
-+
-+/* message structure to be sent to videocore */
-+struct vc_msg {
-+ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */
-+ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */
-+ struct vc_msg_tag tag; /* the tag structure above to make */
-+ uint32_t end_tag; /* an end identifier, should be set to NULL */
-+};
-+
-+struct bcm2835_thermal_data {
-+ struct thermal_zone_device *thermal_dev;
-+ struct vc_msg msg;
-+};
-+
-+/* --- GLOBALS --- */
-+static struct bcm2835_thermal_data bcm2835_data;
-+
-+/* Thermal Device Operations */
-+static struct thermal_zone_device_ops ops;
-+
-+/* --- FUNCTIONS --- */
-+
-+static int bcm2835_get_temp_or_max(struct thermal_zone_device *thermal_dev, unsigned long *temp, unsigned tag_id)
-+{
-+ int result = -1, retry = 3;
-+ print_debug("IN");
-+
-+ *temp = 0;
-+ while (result != 0 && retry-- > 0) {
-+ /* wipe all previous message data */
-+ memset(&bcm2835_data.msg, 0, sizeof bcm2835_data.msg);
-+
-+ /* prepare message */
-+ bcm2835_data.msg.msg_size = sizeof bcm2835_data.msg;
-+ bcm2835_data.msg.tag.buffer_size = 8;
-+ bcm2835_data.msg.tag.tag_id = tag_id;
-+
-+ /* send the message */
-+ result = bcm_mailbox_property(&bcm2835_data.msg, sizeof bcm2835_data.msg);
-+ print_debug("Got %stemperature as %u (%d,%x)\n", tag_id==VC_TAG_GET_MAX_TEMP ? "max ":"", (uint)bcm2835_data.msg.tag.val, result, bcm2835_data.msg.request_code);
-+ if (!(bcm2835_data.msg.request_code & 0x80000000))
-+ result = -1;
-+ }
-+
-+ /* check if it was all ok and return the rate in milli degrees C */
-+ if (result == 0)
-+ *temp = (uint)bcm2835_data.msg.tag.val;
-+ else
-+ print_err("Failed to get temperature! (%x:%d)\n", tag_id, result);
-+ print_debug("OUT");
-+ return result;
-+}
-+
-+static int bcm2835_get_temp(struct thermal_zone_device *thermal_dev, unsigned long *temp)
-+{
-+ return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_TEMP);
-+}
-+
-+static int bcm2835_get_max_temp(struct thermal_zone_device *thermal_dev, int trip_num, unsigned long *temp)
-+{
-+ return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_MAX_TEMP);
-+}
-+
-+static int bcm2835_get_trip_type(struct thermal_zone_device * thermal_dev, int trip_num, enum thermal_trip_type *trip_type)
-+{
-+ *trip_type = THERMAL_TRIP_HOT;
-+ return 0;
-+}
-+
-+
-+static int bcm2835_get_mode(struct thermal_zone_device *thermal_dev, enum thermal_device_mode *dev_mode)
-+{
-+ *dev_mode = THERMAL_DEVICE_ENABLED;
-+ return 0;
-+}
-+
-+
-+static int bcm2835_thermal_probe(struct platform_device *pdev)
-+{
-+ print_debug("IN");
-+ print_debug("THERMAL Driver has been probed!");
-+
-+ /* check that the device isn't null!*/
-+ if(pdev == NULL)
-+ {
-+ print_debug("Platform device is empty!");
-+ return -ENODEV;
-+ }
-+
-+ if(!(bcm2835_data.thermal_dev = thermal_zone_device_register("bcm2835_thermal", 1, 0, NULL, &ops, NULL, 0, 0)))
-+ {
-+ print_debug("Unable to register the thermal device!");
-+ return -EFAULT;
-+ }
-+ return 0;
-+}
-+
-+
-+static int bcm2835_thermal_remove(struct platform_device *pdev)
-+{
-+ print_debug("IN");
-+
-+ thermal_zone_device_unregister(bcm2835_data.thermal_dev);
-+
-+ print_debug("OUT");
-+
-+ return 0;
-+}
-+
-+static struct thermal_zone_device_ops ops = {
-+ .get_temp = bcm2835_get_temp,
-+ .get_trip_temp = bcm2835_get_max_temp,
-+ .get_trip_type = bcm2835_get_trip_type,
-+ .get_mode = bcm2835_get_mode,
-+};
-+
-+/* Thermal Driver */
-+static struct platform_driver bcm2835_thermal_driver = {
-+ .probe = bcm2835_thermal_probe,
-+ .remove = bcm2835_thermal_remove,
-+ .driver = {
-+ .name = "bcm2835_thermal",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Dorian Peake");
-+MODULE_DESCRIPTION("Thermal driver for bcm2835 chip");
-+
-+module_platform_driver(bcm2835_thermal_driver);
-diff -Nur linux-3.18.14/drivers/thermal/Kconfig linux-rpi/drivers/thermal/Kconfig
---- linux-3.18.14/drivers/thermal/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/thermal/Kconfig 2015-05-31 14:46:12.801660962 -0500
-@@ -206,6 +206,12 @@
- enforce idle time which results in more package C-state residency. The
- user interface is exposed via generic thermal framework.
-
-+config THERMAL_BCM2835
-+ tristate "BCM2835 Thermal Driver"
-+ help
-+ This will enable temperature monitoring for the Broadcom BCM2835
-+ chip. If built as a module, it will be called 'bcm2835-thermal'.
-+
- config X86_PKG_TEMP_THERMAL
- tristate "X86 package temperature thermal driver"
- depends on X86_THERMAL_VECTOR
-diff -Nur linux-3.18.14/drivers/thermal/Makefile linux-rpi/drivers/thermal/Makefile
---- linux-3.18.14/drivers/thermal/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/thermal/Makefile 2015-05-31 14:46:12.801660962 -0500
-@@ -29,6 +29,7 @@
- obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
- obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
- obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
-+obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o
- obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
- obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o
- obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
-diff -Nur linux-3.18.14/drivers/tty/serial/amba-pl011.c linux-rpi/drivers/tty/serial/amba-pl011.c
---- linux-3.18.14/drivers/tty/serial/amba-pl011.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/tty/serial/amba-pl011.c 2015-05-31 14:46:12.821660962 -0500
-@@ -84,7 +84,7 @@
-
- static unsigned int get_fifosize_arm(struct amba_device *dev)
- {
-- return amba_rev(dev) < 3 ? 16 : 32;
-+ return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
- }
-
- static struct vendor_data vendor_arm = {
-@@ -408,8 +408,9 @@
- dma_release_channel(uap->dmarx.chan);
- }
-
--/* Forward declare this for the refill routine */
-+/* Forward declare these for the refill routine */
- static int pl011_dma_tx_refill(struct uart_amba_port *uap);
-+static void pl011_start_tx_pio(struct uart_amba_port *uap);
-
- /*
- * The current DMA TX buffer has been sent.
-@@ -447,14 +448,13 @@
- return;
- }
-
-- if (pl011_dma_tx_refill(uap) <= 0) {
-+ if (pl011_dma_tx_refill(uap) <= 0)
- /*
- * We didn't queue a DMA buffer for some reason, but we
- * have data pending to be sent. Re-enable the TX IRQ.
- */
-- uap->im |= UART011_TXIM;
-- writew(uap->im, uap->port.membase + UART011_IMSC);
-- }
-+ pl011_start_tx_pio(uap);
-+
- spin_unlock_irqrestore(&uap->port.lock, flags);
- }
-
-@@ -628,12 +628,10 @@
- if (!uap->dmatx.queued) {
- if (pl011_dma_tx_refill(uap) > 0) {
- uap->im &= ~UART011_TXIM;
-- ret = true;
-- } else {
-- uap->im |= UART011_TXIM;
-+ writew(uap->im, uap->port.membase +
-+ UART011_IMSC);
-+ } else
- ret = false;
-- }
-- writew(uap->im, uap->port.membase + UART011_IMSC);
- } else if (!(uap->dmacr & UART011_TXDMAE)) {
- uap->dmacr |= UART011_TXDMAE;
- writew(uap->dmacr,
-@@ -1172,15 +1170,23 @@
- pl011_dma_tx_stop(uap);
- }
-
-+static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
-+
-+/* Start TX with programmed I/O only (no DMA) */
-+static void pl011_start_tx_pio(struct uart_amba_port *uap)
-+{
-+ uap->im |= UART011_TXIM;
-+ writew(uap->im, uap->port.membase + UART011_IMSC);
-+ pl011_tx_chars(uap, false);
-+}
-+
- static void pl011_start_tx(struct uart_port *port)
- {
- struct uart_amba_port *uap =
- container_of(port, struct uart_amba_port, port);
-
-- if (!pl011_dma_tx_start(uap)) {
-- uap->im |= UART011_TXIM;
-- writew(uap->im, uap->port.membase + UART011_IMSC);
-- }
-+ if (!pl011_dma_tx_start(uap))
-+ pl011_start_tx_pio(uap);
- }
-
- static void pl011_stop_rx(struct uart_port *port)
-@@ -1238,16 +1244,29 @@
- spin_lock(&uap->port.lock);
- }
-
--static void pl011_tx_chars(struct uart_amba_port *uap)
-+static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
-+ bool from_irq)
-+{
-+ if (unlikely(!from_irq) &&
-+ readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
-+ return false; /* unable to transmit character */
-+
-+ writew(c, uap->port.membase + UART01x_DR);
-+ uap->port.icount.tx++;
-+
-+ return true;
-+}
-+
-+static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
- {
- struct circ_buf *xmit = &uap->port.state->xmit;
-- int count;
-+ int count = uap->fifosize >> 1;
-
- if (uap->port.x_char) {
-- writew(uap->port.x_char, uap->port.membase + UART01x_DR);
-- uap->port.icount.tx++;
-+ if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
-+ return;
- uap->port.x_char = 0;
-- return;
-+ --count;
- }
- if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
- pl011_stop_tx(&uap->port);
-@@ -1258,14 +1277,15 @@
- if (pl011_dma_tx_irq(uap))
- return;
-
-- count = uap->fifosize >> 1;
- do {
-- writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
-- xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-- uap->port.icount.tx++;
-- if (uart_circ_empty(xmit))
-+ if (likely(from_irq) && count-- == 0)
- break;
-- } while (--count > 0);
-+
-+ if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
-+ break;
-+
-+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-+ } while (!uart_circ_empty(xmit));
-
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(&uap->port);
-@@ -1337,7 +1357,7 @@
- UART011_CTSMIS|UART011_RIMIS))
- pl011_modem_status(uap);
- if (status & UART011_TXIS)
-- pl011_tx_chars(uap);
-+ pl011_tx_chars(uap, true);
-
- if (pass_counter-- == 0)
- break;
-@@ -1541,7 +1561,7 @@
- {
- struct uart_amba_port *uap =
- container_of(port, struct uart_amba_port, port);
-- unsigned int cr, lcr_h, fbrd, ibrd;
-+ unsigned int cr;
- int retval;
-
- retval = pl011_hwinit(port);
-@@ -1559,30 +1579,8 @@
-
- writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
-
-- /*
-- * Provoke TX FIFO interrupt into asserting. Taking care to preserve
-- * baud rate and data format specified by FBRD, IBRD and LCRH as the
-- * UART may already be in use as a console.
-- */
- spin_lock_irq(&uap->port.lock);
-
-- fbrd = readw(uap->port.membase + UART011_FBRD);
-- ibrd = readw(uap->port.membase + UART011_IBRD);
-- lcr_h = readw(uap->port.membase + uap->lcrh_rx);
--
-- cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
-- writew(cr, uap->port.membase + UART011_CR);
-- writew(0, uap->port.membase + UART011_FBRD);
-- writew(1, uap->port.membase + UART011_IBRD);
-- pl011_write_lcr_h(uap, 0);
-- writew(0, uap->port.membase + UART01x_DR);
-- while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
-- barrier();
--
-- writew(fbrd, uap->port.membase + UART011_FBRD);
-- writew(ibrd, uap->port.membase + UART011_IBRD);
-- pl011_write_lcr_h(uap, lcr_h);
--
- /* restore RTS and DTR */
- cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
- cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
-diff -Nur linux-3.18.14/drivers/usb/core/generic.c linux-rpi/drivers/usb/core/generic.c
---- linux-3.18.14/drivers/usb/core/generic.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/core/generic.c 2015-05-31 14:46:12.853660962 -0500
-@@ -152,6 +152,7 @@
- dev_warn(&udev->dev,
- "no configuration chosen from %d choice%s\n",
- num_configs, plural(num_configs));
-+ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
- }
- return i;
- }
-diff -Nur linux-3.18.14/drivers/usb/core/hub.c linux-rpi/drivers/usb/core/hub.c
---- linux-3.18.14/drivers/usb/core/hub.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/core/hub.c 2015-05-31 14:46:12.857660962 -0500
-@@ -4923,7 +4923,7 @@
- if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
- u16 status = 0, unused;
-
-- dev_dbg(&port_dev->dev, "over-current change\n");
-+ dev_notice(&port_dev->dev, "over-current change\n");
- usb_clear_port_feature(hdev, port1,
- USB_PORT_FEAT_C_OVER_CURRENT);
- msleep(100); /* Cool down */
-diff -Nur linux-3.18.14/drivers/usb/core/message.c linux-rpi/drivers/usb/core/message.c
---- linux-3.18.14/drivers/usb/core/message.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/core/message.c 2015-05-31 14:46:12.857660962 -0500
-@@ -1872,6 +1872,85 @@
- if (cp->string == NULL &&
- !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
- cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
-+/* Uncomment this define to enable the HS Electrical Test support */
-+#define DWC_HS_ELECT_TST 1
-+#ifdef DWC_HS_ELECT_TST
-+ /* Here we implement the HS Electrical Test support. The
-+ * tester uses a vendor ID of 0x1A0A to indicate we should
-+ * run a special test sequence. The product ID tells us
-+ * which sequence to run. We invoke the test sequence by
-+ * sending a non-standard SetFeature command to our root
-+ * hub port. Our dwc_otg_hcd_hub_control() routine will
-+ * recognize the command and perform the desired test
-+ * sequence.
-+ */
-+ if (dev->descriptor.idVendor == 0x1A0A) {
-+ /* HSOTG Electrical Test */
-+ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
-+
-+ if (dev->bus && dev->bus->root_hub) {
-+ struct usb_device *hdev = dev->bus->root_hub;
-+ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
-+
-+ switch (dev->descriptor.idProduct) {
-+ case 0x0101: /* TEST_SE0_NAK */
-+ dev_warn(&dev->dev, "TEST_SE0_NAK\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0102: /* TEST_J */
-+ dev_warn(&dev->dev, "TEST_J\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0103: /* TEST_K */
-+ dev_warn(&dev->dev, "TEST_K\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0104: /* TEST_PACKET */
-+ dev_warn(&dev->dev, "TEST_PACKET\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0105: /* TEST_FORCE_ENABLE */
-+ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
-+ break;
-+
-+ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */
-+ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
-+ break;
-+
-+ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
-+ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
-+ break;
-+
-+ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
-+ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
-+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+ USB_REQ_SET_FEATURE, USB_RT_PORT,
-+ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
-+ }
-+ }
-+ }
-+#endif /* DWC_HS_ELECT_TST */
-
- /* Now that the interfaces are installed, re-enable LPM. */
- usb_unlocked_enable_lpm(dev);
-diff -Nur linux-3.18.14/drivers/usb/core/otg_whitelist.h linux-rpi/drivers/usb/core/otg_whitelist.h
---- linux-3.18.14/drivers/usb/core/otg_whitelist.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/core/otg_whitelist.h 2015-05-31 14:46:12.857660962 -0500
-@@ -19,33 +19,82 @@
- static struct usb_device_id whitelist_table [] = {
-
- /* hubs are optional in OTG, but very handy ... */
-+#define CERT_WITHOUT_HUBS
-+#if defined(CERT_WITHOUT_HUBS)
-+{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
-+#else
- { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
- { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
-+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
-+#endif
-
- #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
- /* FIXME actually, printers are NOT supposed to use device classes;
- * they're supposed to use interface classes...
- */
--{ USB_DEVICE_INFO(7, 1, 1) },
--{ USB_DEVICE_INFO(7, 1, 2) },
--{ USB_DEVICE_INFO(7, 1, 3) },
-+//{ USB_DEVICE_INFO(7, 1, 1) },
-+//{ USB_DEVICE_INFO(7, 1, 2) },
-+//{ USB_DEVICE_INFO(7, 1, 3) },
- #endif
-
- #ifdef CONFIG_USB_NET_CDCETHER
- /* Linux-USB CDC Ethernet gadget */
--{ USB_DEVICE(0x0525, 0xa4a1), },
-+//{ USB_DEVICE(0x0525, 0xa4a1), },
- /* Linux-USB CDC Ethernet + RNDIS gadget */
--{ USB_DEVICE(0x0525, 0xa4a2), },
-+//{ USB_DEVICE(0x0525, 0xa4a2), },
- #endif
-
- #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
- /* gadget zero, for testing */
--{ USB_DEVICE(0x0525, 0xa4a0), },
-+//{ USB_DEVICE(0x0525, 0xa4a0), },
- #endif
-
-+/* OPT Tester */
-+{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
-+{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
-+{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
-+{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
-+{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
-+{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */
-+{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
-+{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
-+
-+/* Sony cameras */
-+{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
-+
-+/* Memory Devices */
-+//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
-+//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
-+//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
-+//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */
-+{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
-+//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
-+
-+/* HP Printers */
-+//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
-+//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
-+
-+/* Speakers */
-+//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
-+//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
-+
- { } /* Terminating entry */
- };
-
-+static inline void report_errors(struct usb_device *dev)
-+{
-+ /* OTG MESSAGE: report errors here, customize to match your product */
-+ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
-+ le16_to_cpu(dev->descriptor.idVendor),
-+ le16_to_cpu(dev->descriptor.idProduct));
-+ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
-+ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
-+ } else {
-+ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
-+ }
-+}
-+
-+
- static int is_targeted(struct usb_device *dev)
- {
- struct usb_device_id *id = whitelist_table;
-@@ -95,16 +144,57 @@
- continue;
-
- return 1;
-- }
-+ /* NOTE: can't use usb_match_id() since interface caches
-+ * aren't set up yet. this is cut/paste from that code.
-+ */
-+ for (id = whitelist_table; id->match_flags; id++) {
-+#ifdef DEBUG
-+ dev_dbg(&dev->dev,
-+ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
-+ id->idVendor,
-+ id->idProduct,
-+ id->bDeviceClass,
-+ id->bDeviceSubClass,
-+ id->bDeviceProtocol);
-+#endif
-
-- /* add other match criteria here ... */
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
-+ id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
-+ id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
-+ continue;
-+
-+ /* No need to test id->bcdDevice_lo != 0, since 0 is never
-+ greater than any unsigned number. */
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
-+ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
-+ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
-+ (id->bDeviceClass != dev->descriptor.bDeviceClass))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
-+ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
-+ continue;
-+
-+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
-+ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
-+ continue;
-
-+ return 1;
-+ }
-+ }
-
-- /* OTG MESSAGE: report errors here, customize to match your product */
-- dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
-- le16_to_cpu(dev->descriptor.idVendor),
-- le16_to_cpu(dev->descriptor.idProduct));
-+ /* add other match criteria here ... */
-
-+ report_errors(dev);
- return 0;
- }
-
-diff -Nur linux-3.18.14/drivers/usb/gadget/file_storage.c linux-rpi/drivers/usb/gadget/file_storage.c
---- linux-3.18.14/drivers/usb/gadget/file_storage.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/gadget/file_storage.c 2015-05-31 14:46:12.865660961 -0500
-@@ -0,0 +1,3676 @@
-+/*
-+ * file_storage.c -- File-backed USB Storage Gadget, for USB development
-+ *
-+ * Copyright (C) 2003-2008 Alan Stern
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * The File-backed Storage Gadget acts as a USB Mass Storage device,
-+ * appearing to the host as a disk drive or as a CD-ROM drive. In addition
-+ * to providing an example of a genuinely useful gadget driver for a USB
-+ * device, it also illustrates a technique of double-buffering for increased
-+ * throughput. Last but not least, it gives an easy way to probe the
-+ * behavior of the Mass Storage drivers in a USB host.
-+ *
-+ * Backing storage is provided by a regular file or a block device, specified
-+ * by the "file" module parameter. Access can be limited to read-only by
-+ * setting the optional "ro" module parameter. (For CD-ROM emulation,
-+ * access is always read-only.) The gadget will indicate that it has
-+ * removable media if the optional "removable" module parameter is set.
-+ *
-+ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
-+ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
-+ * by the optional "transport" module parameter. It also supports the
-+ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
-+ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
-+ * the optional "protocol" module parameter. In addition, the default
-+ * Vendor ID, Product ID, release number and serial number can be overridden.
-+ *
-+ * There is support for multiple logical units (LUNs), each of which has
-+ * its own backing file. The number of LUNs can be set using the optional
-+ * "luns" module parameter (anywhere from 1 to 8), and the corresponding
-+ * files are specified using comma-separated lists for "file" and "ro".
-+ * The default number of LUNs is taken from the number of "file" elements;
-+ * it is 1 if "file" is not given. If "removable" is not set then a backing
-+ * file must be specified for each LUN. If it is set, then an unspecified
-+ * or empty backing filename means the LUN's medium is not loaded. Ideally
-+ * each LUN would be settable independently as a disk drive or a CD-ROM
-+ * drive, but currently all LUNs have to be the same type. The CD-ROM
-+ * emulation includes a single data track and no audio tracks; hence there
-+ * need be only one backing file per LUN.
-+ *
-+ * Requirements are modest; only a bulk-in and a bulk-out endpoint are
-+ * needed (an interrupt-out endpoint is also needed for CBI). The memory
-+ * requirement amounts to two 16K buffers, size configurable by a parameter.
-+ * Support is included for both full-speed and high-speed operation.
-+ *
-+ * Note that the driver is slightly non-portable in that it assumes a
-+ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
-+ * interrupt-in endpoints. With most device controllers this isn't an
-+ * issue, but there may be some with hardware restrictions that prevent
-+ * a buffer from being used by more than one endpoint.
-+ *
-+ * Module options:
-+ *
-+ * file=filename[,filename...]
-+ * Required if "removable" is not set, names of
-+ * the files or block devices used for
-+ * backing storage
-+ * serial=HHHH... Required serial number (string of hex chars)
-+ * ro=b[,b...] Default false, booleans for read-only access
-+ * removable Default false, boolean for removable media
-+ * luns=N Default N = number of filenames, number of
-+ * LUNs to support
-+ * nofua=b[,b...] Default false, booleans for ignore FUA flag
-+ * in SCSI WRITE(10,12) commands
-+ * stall Default determined according to the type of
-+ * USB device controller (usually true),
-+ * boolean to permit the driver to halt
-+ * bulk endpoints
-+ * cdrom Default false, boolean for whether to emulate
-+ * a CD-ROM drive
-+ * transport=XXX Default BBB, transport name (CB, CBI, or BBB)
-+ * protocol=YYY Default SCSI, protocol name (RBC, 8020 or
-+ * ATAPI, QIC, UFI, 8070, or SCSI;
-+ * also 1 - 6)
-+ * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID
-+ * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID
-+ * release=0xRRRR Override the USB release number (bcdDevice)
-+ * buflen=N Default N=16384, buffer size used (will be
-+ * rounded down to a multiple of
-+ * PAGE_CACHE_SIZE)
-+ *
-+ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
-+ * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
-+ * default values are used for everything else.
-+ *
-+ * The pathnames of the backing files and the ro settings are available in
-+ * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
-+ * the gadget's sysfs directory. If the "removable" option is set, writing to
-+ * these files will simulate ejecting/loading the medium (writing an empty
-+ * line means eject) and adjusting a write-enable tab. Changes to the ro
-+ * setting are not allowed when the medium is loaded or if CD-ROM emulation
-+ * is being used.
-+ *
-+ * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
-+ * The driver's SCSI command interface was based on the "Information
-+ * technology - Small Computer System Interface - 2" document from
-+ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
-+ * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. The single exception
-+ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
-+ * "Universal Serial Bus Mass Storage Class UFI Command Specification"
-+ * document, Revision 1.0, December 14, 1998, available at
-+ * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
-+ */
-+
-+
-+/*
-+ * Driver Design
-+ *
-+ * The FSG driver is fairly straightforward. There is a main kernel
-+ * thread that handles most of the work. Interrupt routines field
-+ * callbacks from the controller driver: bulk- and interrupt-request
-+ * completion notifications, endpoint-0 events, and disconnect events.
-+ * Completion events are passed to the main thread by wakeup calls. Many
-+ * ep0 requests are handled at interrupt time, but SetInterface,
-+ * SetConfiguration, and device reset requests are forwarded to the
-+ * thread in the form of "exceptions" using SIGUSR1 signals (since they
-+ * should interrupt any ongoing file I/O operations).
-+ *
-+ * The thread's main routine implements the standard command/data/status
-+ * parts of a SCSI interaction. It and its subroutines are full of tests
-+ * for pending signals/exceptions -- all this polling is necessary since
-+ * the kernel has no setjmp/longjmp equivalents. (Maybe this is an
-+ * indication that the driver really wants to be running in userspace.)
-+ * An important point is that so long as the thread is alive it keeps an
-+ * open reference to the backing file. This will prevent unmounting
-+ * the backing file's underlying filesystem and could cause problems
-+ * during system shutdown, for example. To prevent such problems, the
-+ * thread catches INT, TERM, and KILL signals and converts them into
-+ * an EXIT exception.
-+ *
-+ * In normal operation the main thread is started during the gadget's
-+ * fsg_bind() callback and stopped during fsg_unbind(). But it can also
-+ * exit when it receives a signal, and there's no point leaving the
-+ * gadget running when the thread is dead. So just before the thread
-+ * exits, it deregisters the gadget driver. This makes things a little
-+ * tricky: The driver is deregistered at two places, and the exiting
-+ * thread can indirectly call fsg_unbind() which in turn can tell the
-+ * thread to exit. The first problem is resolved through the use of the
-+ * REGISTERED atomic bitflag; the driver will only be deregistered once.
-+ * The second problem is resolved by having fsg_unbind() check
-+ * fsg->state; it won't try to stop the thread if the state is already
-+ * FSG_STATE_TERMINATED.
-+ *
-+ * To provide maximum throughput, the driver uses a circular pipeline of
-+ * buffer heads (struct fsg_buffhd). In principle the pipeline can be
-+ * arbitrarily long; in practice the benefits don't justify having more
-+ * than 2 stages (i.e., double buffering). But it helps to think of the
-+ * pipeline as being a long one. Each buffer head contains a bulk-in and
-+ * a bulk-out request pointer (since the buffer can be used for both
-+ * output and input -- directions always are given from the host's
-+ * point of view) as well as a pointer to the buffer and various state
-+ * variables.
-+ *
-+ * Use of the pipeline follows a simple protocol. There is a variable
-+ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
-+ * At any time that buffer head may still be in use from an earlier
-+ * request, so each buffer head has a state variable indicating whether
-+ * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the
-+ * buffer head to be EMPTY, filling the buffer either by file I/O or by
-+ * USB I/O (during which the buffer head is BUSY), and marking the buffer
-+ * head FULL when the I/O is complete. Then the buffer will be emptied
-+ * (again possibly by USB I/O, during which it is marked BUSY) and
-+ * finally marked EMPTY again (possibly by a completion routine).
-+ *
-+ * A module parameter tells the driver to avoid stalling the bulk
-+ * endpoints wherever the transport specification allows. This is
-+ * necessary for some UDCs like the SuperH, which cannot reliably clear a
-+ * halt on a bulk endpoint. However, under certain circumstances the
-+ * Bulk-only specification requires a stall. In such cases the driver
-+ * will halt the endpoint and set a flag indicating that it should clear
-+ * the halt in software during the next device reset. Hopefully this
-+ * will permit everything to work correctly. Furthermore, although the
-+ * specification allows the bulk-out endpoint to halt when the host sends
-+ * too much data, implementing this would cause an unavoidable race.
-+ * The driver will always use the "no-stall" approach for OUT transfers.
-+ *
-+ * One subtle point concerns sending status-stage responses for ep0
-+ * requests. Some of these requests, such as device reset, can involve
-+ * interrupting an ongoing file I/O operation, which might take an
-+ * arbitrarily long time. During that delay the host might give up on
-+ * the original ep0 request and issue a new one. When that happens the
-+ * driver should not notify the host about completion of the original
-+ * request, as the host will no longer be waiting for it. So the driver
-+ * assigns to each ep0 request a unique tag, and it keeps track of the
-+ * tag value of the request associated with a long-running exception
-+ * (device-reset, interface-change, or configuration-change). When the
-+ * exception handler is finished, the status-stage response is submitted
-+ * only if the current ep0 request tag is equal to the exception request
-+ * tag. Thus only the most recently received ep0 request will get a
-+ * status-stage response.
-+ *
-+ * Warning: This driver source file is too long. It ought to be split up
-+ * into a header file plus about 3 separate .c files, to handle the details
-+ * of the Gadget, USB Mass Storage, and SCSI protocols.
-+ */
-+
-+
-+/* #define VERBOSE_DEBUG */
-+/* #define DUMP_MSGS */
-+
-+
-+#include <linux/blkdev.h>
-+#include <linux/completion.h>
-+#include <linux/dcache.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/fcntl.h>
-+#include <linux/file.h>
-+#include <linux/fs.h>
-+#include <linux/kref.h>
-+#include <linux/kthread.h>
-+#include <linux/limits.h>
-+#include <linux/module.h>
-+#include <linux/rwsem.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/string.h>
-+#include <linux/freezer.h>
-+#include <linux/utsname.h>
-+
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+
-+#include "gadget_chips.h"
-+
-+
-+
-+/*
-+ * Kbuild is not very cooperative with respect to linking separately
-+ * compiled library objects into one module. So for now we won't use
-+ * separate compilation ... ensuring init/exit sections work to shrink
-+ * the runtime footprint, and giving us at least some parts of what
-+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
-+ */
-+#include "usbstring.c"
-+#include "config.c"
-+#include "epautoconf.c"
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_DESC "File-backed Storage Gadget"
-+#define DRIVER_NAME "g_file_storage"
-+#define DRIVER_VERSION "1 September 2010"
-+
-+static char fsg_string_manufacturer[64];
-+static const char fsg_string_product[] = DRIVER_DESC;
-+static const char fsg_string_config[] = "Self-powered";
-+static const char fsg_string_interface[] = "Mass Storage";
-+
-+
-+#include "storage_common.c"
-+
-+
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_AUTHOR("Alan Stern");
-+MODULE_LICENSE("Dual BSD/GPL");
-+
-+/*
-+ * This driver assumes self-powered hardware and has no way for users to
-+ * trigger remote wakeup. It uses autoconfiguration to select endpoints
-+ * and endpoint addresses.
-+ */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/* Encapsulate the module parameter settings */
-+
-+static struct {
-+ char *file[FSG_MAX_LUNS];
-+ char *serial;
-+ bool ro[FSG_MAX_LUNS];
-+ bool nofua[FSG_MAX_LUNS];
-+ unsigned int num_filenames;
-+ unsigned int num_ros;
-+ unsigned int num_nofuas;
-+ unsigned int nluns;
-+
-+ bool removable;
-+ bool can_stall;
-+ bool cdrom;
-+
-+ char *transport_parm;
-+ char *protocol_parm;
-+ unsigned short vendor;
-+ unsigned short product;
-+ unsigned short release;
-+ unsigned int buflen;
-+
-+ int transport_type;
-+ char *transport_name;
-+ int protocol_type;
-+ char *protocol_name;
-+
-+} mod_data = { // Default values
-+ .transport_parm = "BBB",
-+ .protocol_parm = "SCSI",
-+ .removable = 0,
-+ .can_stall = 1,
-+ .cdrom = 0,
-+ .vendor = FSG_VENDOR_ID,
-+ .product = FSG_PRODUCT_ID,
-+ .release = 0xffff, // Use controller chip type
-+ .buflen = 16384,
-+ };
-+
-+
-+module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
-+ S_IRUGO);
-+MODULE_PARM_DESC(file, "names of backing files or devices");
-+
-+module_param_named(serial, mod_data.serial, charp, S_IRUGO);
-+MODULE_PARM_DESC(serial, "USB serial number");
-+
-+module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
-+MODULE_PARM_DESC(ro, "true to force read-only");
-+
-+module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
-+ S_IRUGO);
-+MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
-+
-+module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
-+MODULE_PARM_DESC(luns, "number of LUNs");
-+
-+module_param_named(removable, mod_data.removable, bool, S_IRUGO);
-+MODULE_PARM_DESC(removable, "true to simulate removable media");
-+
-+module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
-+MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
-+
-+module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
-+MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
-+
-+/* In the non-TEST version, only the module parameters listed above
-+ * are available. */
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+
-+module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
-+MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
-+
-+module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
-+MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
-+ "8070, or SCSI)");
-+
-+module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
-+MODULE_PARM_DESC(vendor, "USB Vendor ID");
-+
-+module_param_named(product, mod_data.product, ushort, S_IRUGO);
-+MODULE_PARM_DESC(product, "USB Product ID");
-+
-+module_param_named(release, mod_data.release, ushort, S_IRUGO);
-+MODULE_PARM_DESC(release, "USB release number");
-+
-+module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
-+MODULE_PARM_DESC(buflen, "I/O buffer size");
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*
-+ * These definitions will permit the compiler to avoid generating code for
-+ * parts of the driver that aren't used in the non-TEST version. Even gcc
-+ * can recognize when a test of a constant expression yields a dead code
-+ * path.
-+ */
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+
-+#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK)
-+#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI)
-+#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI)
-+
-+#else
-+
-+#define transport_is_bbb() 1
-+#define transport_is_cbi() 0
-+#define protocol_is_scsi() 1
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+struct fsg_dev {
-+ /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
-+ spinlock_t lock;
-+ struct usb_gadget *gadget;
-+
-+ /* filesem protects: backing files in use */
-+ struct rw_semaphore filesem;
-+
-+ /* reference counting: wait until all LUNs are released */
-+ struct kref ref;
-+
-+ struct usb_ep *ep0; // Handy copy of gadget->ep0
-+ struct usb_request *ep0req; // For control responses
-+ unsigned int ep0_req_tag;
-+ const char *ep0req_name;
-+
-+ struct usb_request *intreq; // For interrupt responses
-+ int intreq_busy;
-+ struct fsg_buffhd *intr_buffhd;
-+
-+ unsigned int bulk_out_maxpacket;
-+ enum fsg_state state; // For exception handling
-+ unsigned int exception_req_tag;
-+
-+ u8 config, new_config;
-+
-+ unsigned int running : 1;
-+ unsigned int bulk_in_enabled : 1;
-+ unsigned int bulk_out_enabled : 1;
-+ unsigned int intr_in_enabled : 1;
-+ unsigned int phase_error : 1;
-+ unsigned int short_packet_received : 1;
-+ unsigned int bad_lun_okay : 1;
-+
-+ unsigned long atomic_bitflags;
-+#define REGISTERED 0
-+#define IGNORE_BULK_OUT 1
-+#define SUSPENDED 2
-+
-+ struct usb_ep *bulk_in;
-+ struct usb_ep *bulk_out;
-+ struct usb_ep *intr_in;
-+
-+ struct fsg_buffhd *next_buffhd_to_fill;
-+ struct fsg_buffhd *next_buffhd_to_drain;
-+
-+ int thread_wakeup_needed;
-+ struct completion thread_notifier;
-+ struct task_struct *thread_task;
-+
-+ int cmnd_size;
-+ u8 cmnd[MAX_COMMAND_SIZE];
-+ enum data_direction data_dir;
-+ u32 data_size;
-+ u32 data_size_from_cmnd;
-+ u32 tag;
-+ unsigned int lun;
-+ u32 residue;
-+ u32 usb_amount_left;
-+
-+ /* The CB protocol offers no way for a host to know when a command
-+ * has completed. As a result the next command may arrive early,
-+ * and we will still have to handle it. For that reason we need
-+ * a buffer to store new commands when using CB (or CBI, which
-+ * does not oblige a host to wait for command completion either). */
-+ int cbbuf_cmnd_size;
-+ u8 cbbuf_cmnd[MAX_COMMAND_SIZE];
-+
-+ unsigned int nluns;
-+ struct fsg_lun *luns;
-+ struct fsg_lun *curlun;
-+ /* Must be the last entry */
-+ struct fsg_buffhd buffhds[];
-+};
-+
-+typedef void (*fsg_routine_t)(struct fsg_dev *);
-+
-+static int exception_in_progress(struct fsg_dev *fsg)
-+{
-+ return (fsg->state > FSG_STATE_IDLE);
-+}
-+
-+/* Make bulk-out requests be divisible by the maxpacket size */
-+static void set_bulk_out_req_length(struct fsg_dev *fsg,
-+ struct fsg_buffhd *bh, unsigned int length)
-+{
-+ unsigned int rem;
-+
-+ bh->bulk_out_intended_length = length;
-+ rem = length % fsg->bulk_out_maxpacket;
-+ if (rem > 0)
-+ length += fsg->bulk_out_maxpacket - rem;
-+ bh->outreq->length = length;
-+}
-+
-+static struct fsg_dev *the_fsg;
-+static struct usb_gadget_driver fsg_driver;
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
-+{
-+ const char *name;
-+
-+ if (ep == fsg->bulk_in)
-+ name = "bulk-in";
-+ else if (ep == fsg->bulk_out)
-+ name = "bulk-out";
-+ else
-+ name = ep->name;
-+ DBG(fsg, "%s set halt\n", name);
-+ return usb_ep_set_halt(ep);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full) configuration
-+ * descriptors are built on demand. Also the (static) config and interface
-+ * descriptors are adjusted during fsg_bind().
-+ */
-+
-+/* There is only one configuration. */
-+#define CONFIG_VALUE 1
-+
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+
-+ .bcdUSB = cpu_to_le16(0x0200),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+
-+ /* The next three values can be overridden by module parameters */
-+ .idVendor = cpu_to_le16(FSG_VENDOR_ID),
-+ .idProduct = cpu_to_le16(FSG_PRODUCT_ID),
-+ .bcdDevice = cpu_to_le16(0xffff),
-+
-+ .iManufacturer = FSG_STRING_MANUFACTURER,
-+ .iProduct = FSG_STRING_PRODUCT,
-+ .iSerialNumber = FSG_STRING_SERIAL,
-+ .bNumConfigurations = 1,
-+};
-+
-+static struct usb_config_descriptor
-+config_desc = {
-+ .bLength = sizeof config_desc,
-+ .bDescriptorType = USB_DT_CONFIG,
-+
-+ /* wTotalLength computed by usb_gadget_config_buf() */
-+ .bNumInterfaces = 1,
-+ .bConfigurationValue = CONFIG_VALUE,
-+ .iConfiguration = FSG_STRING_CONFIG,
-+ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
-+ .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2,
-+};
-+
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+ .bLength = sizeof dev_qualifier,
-+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
-+
-+ .bcdUSB = cpu_to_le16(0x0200),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+
-+ .bNumConfigurations = 1,
-+};
-+
-+static int populate_bos(struct fsg_dev *fsg, u8 *buf)
-+{
-+ memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
-+ buf += USB_DT_BOS_SIZE;
-+
-+ memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
-+ buf += USB_DT_USB_EXT_CAP_SIZE;
-+
-+ memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
-+
-+ return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
-+ + USB_DT_USB_EXT_CAP_SIZE;
-+}
-+
-+/*
-+ * Config descriptors must agree with the code that sets configurations
-+ * and with code managing interfaces and their altsettings. They must
-+ * also handle different speeds and other-speed requests.
-+ */
-+static int populate_config_buf(struct usb_gadget *gadget,
-+ u8 *buf, u8 type, unsigned index)
-+{
-+ enum usb_device_speed speed = gadget->speed;
-+ int len;
-+ const struct usb_descriptor_header **function;
-+
-+ if (index > 0)
-+ return -EINVAL;
-+
-+ if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
-+ speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
-+ function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
-+ ? (const struct usb_descriptor_header **)fsg_hs_function
-+ : (const struct usb_descriptor_header **)fsg_fs_function;
-+
-+ /* for now, don't advertise srp-only devices */
-+ if (!gadget_is_otg(gadget))
-+ function++;
-+
-+ len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
-+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+ return len;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* These routines may be called in process context or in_irq */
-+
-+/* Caller must hold fsg->lock */
-+static void wakeup_thread(struct fsg_dev *fsg)
-+{
-+ /* Tell the main thread that something has happened */
-+ fsg->thread_wakeup_needed = 1;
-+ if (fsg->thread_task)
-+ wake_up_process(fsg->thread_task);
-+}
-+
-+
-+static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
-+{
-+ unsigned long flags;
-+
-+ /* Do nothing if a higher-priority exception is already in progress.
-+ * If a lower-or-equal priority exception is in progress, preempt it
-+ * and notify the main thread by sending it a signal. */
-+ spin_lock_irqsave(&fsg->lock, flags);
-+ if (fsg->state <= new_state) {
-+ fsg->exception_req_tag = fsg->ep0_req_tag;
-+ fsg->state = new_state;
-+ if (fsg->thread_task)
-+ send_sig_info(SIGUSR1, SEND_SIG_FORCED,
-+ fsg->thread_task);
-+ }
-+ spin_unlock_irqrestore(&fsg->lock, flags);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* The disconnect callback and ep0 routines. These always run in_irq,
-+ * except that ep0_queue() is called in the main thread to acknowledge
-+ * completion of various requests: set config, set interface, and
-+ * Bulk-only device reset. */
-+
-+static void fsg_disconnect(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+
-+ DBG(fsg, "disconnect or port reset\n");
-+ raise_exception(fsg, FSG_STATE_DISCONNECT);
-+}
-+
-+
-+static int ep0_queue(struct fsg_dev *fsg)
-+{
-+ int rc;
-+
-+ rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
-+ if (rc != 0 && rc != -ESHUTDOWN) {
-+
-+ /* We can't do much more than wait for a reset */
-+ WARNING(fsg, "error in submission: %s --> %d\n",
-+ fsg->ep0->name, rc);
-+ }
-+ return rc;
-+}
-+
-+static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+
-+ if (req->actual > 0)
-+ dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
-+ if (req->status || req->actual != req->length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual, req->length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ if (req->status == 0 && req->context)
-+ ((fsg_routine_t) (req->context))(fsg);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Bulk and interrupt endpoint completion handlers.
-+ * These always run in_irq. */
-+
-+static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+ struct fsg_buffhd *bh = req->context;
-+
-+ if (req->status || req->actual != req->length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual, req->length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ /* Hold the lock while we update the request and buffer states */
-+ smp_wmb();
-+ spin_lock(&fsg->lock);
-+ bh->inreq_busy = 0;
-+ bh->state = BUF_STATE_EMPTY;
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+ struct fsg_buffhd *bh = req->context;
-+
-+ dump_msg(fsg, "bulk-out", req->buf, req->actual);
-+ if (req->status || req->actual != bh->bulk_out_intended_length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual,
-+ bh->bulk_out_intended_length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ /* Hold the lock while we update the request and buffer states */
-+ smp_wmb();
-+ spin_lock(&fsg->lock);
-+ bh->outreq_busy = 0;
-+ bh->state = BUF_STATE_FULL;
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct fsg_dev *fsg = ep->driver_data;
-+ struct fsg_buffhd *bh = req->context;
-+
-+ if (req->status || req->actual != req->length)
-+ DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+ req->status, req->actual, req->length);
-+ if (req->status == -ECONNRESET) // Request was cancelled
-+ usb_ep_fifo_flush(ep);
-+
-+ /* Hold the lock while we update the request and buffer states */
-+ smp_wmb();
-+ spin_lock(&fsg->lock);
-+ fsg->intreq_busy = 0;
-+ bh->state = BUF_STATE_EMPTY;
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+#else
-+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{}
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Ep0 class-specific handlers. These always run in_irq. */
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct usb_request *req = fsg->ep0req;
-+ static u8 cbi_reset_cmnd[6] = {
-+ SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
-+
-+ /* Error in command transfer? */
-+ if (req->status || req->length != req->actual ||
-+ req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
-+
-+ /* Not all controllers allow a protocol stall after
-+ * receiving control-out data, but we'll try anyway. */
-+ fsg_set_halt(fsg, fsg->ep0);
-+ return; // Wait for reset
-+ }
-+
-+ /* Is it the special reset command? */
-+ if (req->actual >= sizeof cbi_reset_cmnd &&
-+ memcmp(req->buf, cbi_reset_cmnd,
-+ sizeof cbi_reset_cmnd) == 0) {
-+
-+ /* Raise an exception to stop the current operation
-+ * and reinitialize our state. */
-+ DBG(fsg, "cbi reset request\n");
-+ raise_exception(fsg, FSG_STATE_RESET);
-+ return;
-+ }
-+
-+ VDBG(fsg, "CB[I] accept device-specific command\n");
-+ spin_lock(&fsg->lock);
-+
-+ /* Save the command for later */
-+ if (fsg->cbbuf_cmnd_size)
-+ WARNING(fsg, "CB[I] overwriting previous command\n");
-+ fsg->cbbuf_cmnd_size = req->actual;
-+ memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
-+
-+ wakeup_thread(fsg);
-+ spin_unlock(&fsg->lock);
-+}
-+
-+#else
-+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{}
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+static int class_setup_req(struct fsg_dev *fsg,
-+ const struct usb_ctrlrequest *ctrl)
-+{
-+ struct usb_request *req = fsg->ep0req;
-+ int value = -EOPNOTSUPP;
-+ u16 w_index = le16_to_cpu(ctrl->wIndex);
-+ u16 w_value = le16_to_cpu(ctrl->wValue);
-+ u16 w_length = le16_to_cpu(ctrl->wLength);
-+
-+ if (!fsg->config)
-+ return value;
-+
-+ /* Handle Bulk-only class-specific requests */
-+ if (transport_is_bbb()) {
-+ switch (ctrl->bRequest) {
-+
-+ case US_BULK_RESET_REQUEST:
-+ if (ctrl->bRequestType != (USB_DIR_OUT |
-+ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+ break;
-+ if (w_index != 0 || w_value != 0 || w_length != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+
-+ /* Raise an exception to stop the current operation
-+ * and reinitialize our state. */
-+ DBG(fsg, "bulk reset request\n");
-+ raise_exception(fsg, FSG_STATE_RESET);
-+ value = DELAYED_STATUS;
-+ break;
-+
-+ case US_BULK_GET_MAX_LUN:
-+ if (ctrl->bRequestType != (USB_DIR_IN |
-+ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+ break;
-+ if (w_index != 0 || w_value != 0 || w_length != 1) {
-+ value = -EDOM;
-+ break;
-+ }
-+ VDBG(fsg, "get max LUN\n");
-+ *(u8 *) req->buf = fsg->nluns - 1;
-+ value = 1;
-+ break;
-+ }
-+ }
-+
-+ /* Handle CBI class-specific requests */
-+ else {
-+ switch (ctrl->bRequest) {
-+
-+ case USB_CBI_ADSC_REQUEST:
-+ if (ctrl->bRequestType != (USB_DIR_OUT |
-+ USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+ break;
-+ if (w_index != 0 || w_value != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ if (w_length > MAX_COMMAND_SIZE) {
-+ value = -EOVERFLOW;
-+ break;
-+ }
-+ value = w_length;
-+ fsg->ep0req->context = received_cbi_adsc;
-+ break;
-+ }
-+ }
-+
-+ if (value == -EOPNOTSUPP)
-+ VDBG(fsg,
-+ "unknown class-specific control req "
-+ "%02x.%02x v%04x i%04x l%u\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ le16_to_cpu(ctrl->wValue), w_index, w_length);
-+ return value;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Ep0 standard request handlers. These always run in_irq. */
-+
-+static int standard_setup_req(struct fsg_dev *fsg,
-+ const struct usb_ctrlrequest *ctrl)
-+{
-+ struct usb_request *req = fsg->ep0req;
-+ int value = -EOPNOTSUPP;
-+ u16 w_index = le16_to_cpu(ctrl->wIndex);
-+ u16 w_value = le16_to_cpu(ctrl->wValue);
-+
-+ /* Usually this just stores reply data in the pre-allocated ep0 buffer,
-+ * but config change events will also reconfigure hardware. */
-+ switch (ctrl->bRequest) {
-+
-+ case USB_REQ_GET_DESCRIPTOR:
-+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+ USB_RECIP_DEVICE))
-+ break;
-+ switch (w_value >> 8) {
-+
-+ case USB_DT_DEVICE:
-+ VDBG(fsg, "get device descriptor\n");
-+ device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
-+ value = sizeof device_desc;
-+ memcpy(req->buf, &device_desc, value);
-+ break;
-+ case USB_DT_DEVICE_QUALIFIER:
-+ VDBG(fsg, "get device qualifier\n");
-+ if (!gadget_is_dualspeed(fsg->gadget) ||
-+ fsg->gadget->speed == USB_SPEED_SUPER)
-+ break;
-+ /*
-+ * Assume ep0 uses the same maxpacket value for both
-+ * speeds
-+ */
-+ dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
-+ value = sizeof dev_qualifier;
-+ memcpy(req->buf, &dev_qualifier, value);
-+ break;
-+
-+ case USB_DT_OTHER_SPEED_CONFIG:
-+ VDBG(fsg, "get other-speed config descriptor\n");
-+ if (!gadget_is_dualspeed(fsg->gadget) ||
-+ fsg->gadget->speed == USB_SPEED_SUPER)
-+ break;
-+ goto get_config;
-+ case USB_DT_CONFIG:
-+ VDBG(fsg, "get configuration descriptor\n");
-+get_config:
-+ value = populate_config_buf(fsg->gadget,
-+ req->buf,
-+ w_value >> 8,
-+ w_value & 0xff);
-+ break;
-+
-+ case USB_DT_STRING:
-+ VDBG(fsg, "get string descriptor\n");
-+
-+ /* wIndex == language code */
-+ value = usb_gadget_get_string(&fsg_stringtab,
-+ w_value & 0xff, req->buf);
-+ break;
-+
-+ case USB_DT_BOS:
-+ VDBG(fsg, "get bos descriptor\n");
-+
-+ if (gadget_is_superspeed(fsg->gadget))
-+ value = populate_bos(fsg, req->buf);
-+ break;
-+ }
-+
-+ break;
-+
-+ /* One config, two speeds */
-+ case USB_REQ_SET_CONFIGURATION:
-+ if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
-+ USB_RECIP_DEVICE))
-+ break;
-+ VDBG(fsg, "set configuration\n");
-+ if (w_value == CONFIG_VALUE || w_value == 0) {
-+ fsg->new_config = w_value;
-+
-+ /* Raise an exception to wipe out previous transaction
-+ * state (queued bufs, etc) and set the new config. */
-+ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
-+ value = DELAYED_STATUS;
-+ }
-+ break;
-+ case USB_REQ_GET_CONFIGURATION:
-+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+ USB_RECIP_DEVICE))
-+ break;
-+ VDBG(fsg, "get configuration\n");
-+ *(u8 *) req->buf = fsg->config;
-+ value = 1;
-+ break;
-+
-+ case USB_REQ_SET_INTERFACE:
-+ if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
-+ USB_RECIP_INTERFACE))
-+ break;
-+ if (fsg->config && w_index == 0) {
-+
-+ /* Raise an exception to wipe out previous transaction
-+ * state (queued bufs, etc) and install the new
-+ * interface altsetting. */
-+ raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
-+ value = DELAYED_STATUS;
-+ }
-+ break;
-+ case USB_REQ_GET_INTERFACE:
-+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+ USB_RECIP_INTERFACE))
-+ break;
-+ if (!fsg->config)
-+ break;
-+ if (w_index != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ VDBG(fsg, "get interface\n");
-+ *(u8 *) req->buf = 0;
-+ value = 1;
-+ break;
-+
-+ default:
-+ VDBG(fsg,
-+ "unknown control req %02x.%02x v%04x i%04x l%u\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ w_value, w_index, le16_to_cpu(ctrl->wLength));
-+ }
-+
-+ return value;
-+}
-+
-+
-+static int fsg_setup(struct usb_gadget *gadget,
-+ const struct usb_ctrlrequest *ctrl)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+ int rc;
-+ int w_length = le16_to_cpu(ctrl->wLength);
-+
-+ ++fsg->ep0_req_tag; // Record arrival of a new request
-+ fsg->ep0req->context = NULL;
-+ fsg->ep0req->length = 0;
-+ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
-+
-+ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
-+ rc = class_setup_req(fsg, ctrl);
-+ else
-+ rc = standard_setup_req(fsg, ctrl);
-+
-+ /* Respond with data/status or defer until later? */
-+ if (rc >= 0 && rc != DELAYED_STATUS) {
-+ rc = min(rc, w_length);
-+ fsg->ep0req->length = rc;
-+ fsg->ep0req->zero = rc < w_length;
-+ fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
-+ "ep0-in" : "ep0-out");
-+ rc = ep0_queue(fsg);
-+ }
-+
-+ /* Device either stalls (rc < 0) or reports success */
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* All the following routines run in process context */
-+
-+
-+/* Use this for bulk or interrupt transfers, not ep0 */
-+static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
-+ struct usb_request *req, int *pbusy,
-+ enum fsg_buffer_state *state)
-+{
-+ int rc;
-+
-+ if (ep == fsg->bulk_in)
-+ dump_msg(fsg, "bulk-in", req->buf, req->length);
-+ else if (ep == fsg->intr_in)
-+ dump_msg(fsg, "intr-in", req->buf, req->length);
-+
-+ spin_lock_irq(&fsg->lock);
-+ *pbusy = 1;
-+ *state = BUF_STATE_BUSY;
-+ spin_unlock_irq(&fsg->lock);
-+ rc = usb_ep_queue(ep, req, GFP_KERNEL);
-+ if (rc != 0) {
-+ *pbusy = 0;
-+ *state = BUF_STATE_EMPTY;
-+
-+ /* We can't do much more than wait for a reset */
-+
-+ /* Note: currently the net2280 driver fails zero-length
-+ * submissions if DMA is enabled. */
-+ if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
-+ req->length == 0))
-+ WARNING(fsg, "error in submission: %s --> %d\n",
-+ ep->name, rc);
-+ }
-+}
-+
-+
-+static int sleep_thread(struct fsg_dev *fsg)
-+{
-+ int rc = 0;
-+
-+ /* Wait until a signal arrives or we are woken up */
-+ for (;;) {
-+ try_to_freeze();
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ if (signal_pending(current)) {
-+ rc = -EINTR;
-+ break;
-+ }
-+ if (fsg->thread_wakeup_needed)
-+ break;
-+ schedule();
-+ }
-+ __set_current_state(TASK_RUNNING);
-+ fsg->thread_wakeup_needed = 0;
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_read(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba;
-+ struct fsg_buffhd *bh;
-+ int rc;
-+ u32 amount_left;
-+ loff_t file_offset, file_offset_tmp;
-+ unsigned int amount;
-+ ssize_t nread;
-+
-+ /* Get the starting Logical Block Address and check that it's
-+ * not too big */
-+ if (fsg->cmnd[0] == READ_6)
-+ lba = get_unaligned_be24(&fsg->cmnd[1]);
-+ else {
-+ lba = get_unaligned_be32(&fsg->cmnd[2]);
-+
-+ /* We allow DPO (Disable Page Out = don't save data in the
-+ * cache) and FUA (Force Unit Access = don't read from the
-+ * cache), but we don't implement them. */
-+ if ((fsg->cmnd[1] & ~0x18) != 0) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ }
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+ file_offset = ((loff_t) lba) << curlun->blkbits;
-+
-+ /* Carry out the file reads */
-+ amount_left = fsg->data_size_from_cmnd;
-+ if (unlikely(amount_left == 0))
-+ return -EIO; // No default reply
-+
-+ for (;;) {
-+
-+ /* Figure out how much we need to read:
-+ * Try to read the remaining amount.
-+ * But don't read more than the buffer size.
-+ * And don't try to read past the end of the file.
-+ */
-+ amount = min((unsigned int) amount_left, mod_data.buflen);
-+ amount = min((loff_t) amount,
-+ curlun->file_length - file_offset);
-+
-+ /* Wait for the next buffer to become available */
-+ bh = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ /* If we were asked to read past the end of file,
-+ * end with an empty buffer. */
-+ if (amount == 0) {
-+ curlun->sense_data =
-+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ bh->inreq->length = 0;
-+ bh->state = BUF_STATE_FULL;
-+ break;
-+ }
-+
-+ /* Perform the read */
-+ file_offset_tmp = file_offset;
-+ nread = vfs_read(curlun->filp,
-+ (char __user *) bh->buf,
-+ amount, &file_offset_tmp);
-+ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
-+ (unsigned long long) file_offset,
-+ (int) nread);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ if (nread < 0) {
-+ LDBG(curlun, "error in file read: %d\n",
-+ (int) nread);
-+ nread = 0;
-+ } else if (nread < amount) {
-+ LDBG(curlun, "partial file read: %d/%u\n",
-+ (int) nread, amount);
-+ nread = round_down(nread, curlun->blksize);
-+ }
-+ file_offset += nread;
-+ amount_left -= nread;
-+ fsg->residue -= nread;
-+
-+ /* Except at the end of the transfer, nread will be
-+ * equal to the buffer size, which is divisible by the
-+ * bulk-in maxpacket size.
-+ */
-+ bh->inreq->length = nread;
-+ bh->state = BUF_STATE_FULL;
-+
-+ /* If an error occurred, report it and its position */
-+ if (nread < amount) {
-+ curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ if (amount_left == 0)
-+ break; // No more left to read
-+
-+ /* Send this buffer and go read some more */
-+ bh->inreq->zero = 0;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ }
-+
-+ return -EIO; // No default reply
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_write(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba;
-+ struct fsg_buffhd *bh;
-+ int get_some_more;
-+ u32 amount_left_to_req, amount_left_to_write;
-+ loff_t usb_offset, file_offset, file_offset_tmp;
-+ unsigned int amount;
-+ ssize_t nwritten;
-+ int rc;
-+
-+ if (curlun->ro) {
-+ curlun->sense_data = SS_WRITE_PROTECTED;
-+ return -EINVAL;
-+ }
-+ spin_lock(&curlun->filp->f_lock);
-+ curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait
-+ spin_unlock(&curlun->filp->f_lock);
-+
-+ /* Get the starting Logical Block Address and check that it's
-+ * not too big */
-+ if (fsg->cmnd[0] == WRITE_6)
-+ lba = get_unaligned_be24(&fsg->cmnd[1]);
-+ else {
-+ lba = get_unaligned_be32(&fsg->cmnd[2]);
-+
-+ /* We allow DPO (Disable Page Out = don't save data in the
-+ * cache) and FUA (Force Unit Access = write directly to the
-+ * medium). We don't implement DPO; we implement FUA by
-+ * performing synchronous output. */
-+ if ((fsg->cmnd[1] & ~0x18) != 0) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ /* FUA */
-+ if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
-+ spin_lock(&curlun->filp->f_lock);
-+ curlun->filp->f_flags |= O_DSYNC;
-+ spin_unlock(&curlun->filp->f_lock);
-+ }
-+ }
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+
-+ /* Carry out the file writes */
-+ get_some_more = 1;
-+ file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
-+ amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
-+
-+ while (amount_left_to_write > 0) {
-+
-+ /* Queue a request for more data from the host */
-+ bh = fsg->next_buffhd_to_fill;
-+ if (bh->state == BUF_STATE_EMPTY && get_some_more) {
-+
-+ /* Figure out how much we want to get:
-+ * Try to get the remaining amount,
-+ * but not more than the buffer size.
-+ */
-+ amount = min(amount_left_to_req, mod_data.buflen);
-+
-+ /* Beyond the end of the backing file? */
-+ if (usb_offset >= curlun->file_length) {
-+ get_some_more = 0;
-+ curlun->sense_data =
-+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ curlun->sense_data_info = usb_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ continue;
-+ }
-+
-+ /* Get the next buffer */
-+ usb_offset += amount;
-+ fsg->usb_amount_left -= amount;
-+ amount_left_to_req -= amount;
-+ if (amount_left_to_req == 0)
-+ get_some_more = 0;
-+
-+ /* Except at the end of the transfer, amount will be
-+ * equal to the buffer size, which is divisible by
-+ * the bulk-out maxpacket size.
-+ */
-+ set_bulk_out_req_length(fsg, bh, amount);
-+ start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+ &bh->outreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ continue;
-+ }
-+
-+ /* Write the received data to the backing file */
-+ bh = fsg->next_buffhd_to_drain;
-+ if (bh->state == BUF_STATE_EMPTY && !get_some_more)
-+ break; // We stopped early
-+ if (bh->state == BUF_STATE_FULL) {
-+ smp_rmb();
-+ fsg->next_buffhd_to_drain = bh->next;
-+ bh->state = BUF_STATE_EMPTY;
-+
-+ /* Did something go wrong with the transfer? */
-+ if (bh->outreq->status != 0) {
-+ curlun->sense_data = SS_COMMUNICATION_FAILURE;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ amount = bh->outreq->actual;
-+ if (curlun->file_length - file_offset < amount) {
-+ LERROR(curlun,
-+ "write %u @ %llu beyond end %llu\n",
-+ amount, (unsigned long long) file_offset,
-+ (unsigned long long) curlun->file_length);
-+ amount = curlun->file_length - file_offset;
-+ }
-+
-+ /* Don't accept excess data. The spec doesn't say
-+ * what to do in this case. We'll ignore the error.
-+ */
-+ amount = min(amount, bh->bulk_out_intended_length);
-+
-+ /* Don't write a partial block */
-+ amount = round_down(amount, curlun->blksize);
-+ if (amount == 0)
-+ goto empty_write;
-+
-+ /* Perform the write */
-+ file_offset_tmp = file_offset;
-+ nwritten = vfs_write(curlun->filp,
-+ (char __user *) bh->buf,
-+ amount, &file_offset_tmp);
-+ VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
-+ (unsigned long long) file_offset,
-+ (int) nwritten);
-+ if (signal_pending(current))
-+ return -EINTR; // Interrupted!
-+
-+ if (nwritten < 0) {
-+ LDBG(curlun, "error in file write: %d\n",
-+ (int) nwritten);
-+ nwritten = 0;
-+ } else if (nwritten < amount) {
-+ LDBG(curlun, "partial file write: %d/%u\n",
-+ (int) nwritten, amount);
-+ nwritten = round_down(nwritten, curlun->blksize);
-+ }
-+ file_offset += nwritten;
-+ amount_left_to_write -= nwritten;
-+ fsg->residue -= nwritten;
-+
-+ /* If an error occurred, report it and its position */
-+ if (nwritten < amount) {
-+ curlun->sense_data = SS_WRITE_ERROR;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ empty_write:
-+ /* Did the host decide to stop early? */
-+ if (bh->outreq->actual < bh->bulk_out_intended_length) {
-+ fsg->short_packet_received = 1;
-+ break;
-+ }
-+ continue;
-+ }
-+
-+ /* Wait for something to happen */
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ return -EIO; // No default reply
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_synchronize_cache(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int rc;
-+
-+ /* We ignore the requested LBA and write out all file's
-+ * dirty data buffers. */
-+ rc = fsg_lun_fsync_sub(curlun);
-+ if (rc)
-+ curlun->sense_data = SS_WRITE_ERROR;
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void invalidate_sub(struct fsg_lun *curlun)
-+{
-+ struct file *filp = curlun->filp;
-+ struct inode *inode = filp->f_path.dentry->d_inode;
-+ unsigned long rc;
-+
-+ rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
-+ VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
-+}
-+
-+static int do_verify(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba;
-+ u32 verification_length;
-+ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
-+ loff_t file_offset, file_offset_tmp;
-+ u32 amount_left;
-+ unsigned int amount;
-+ ssize_t nread;
-+
-+ /* Get the starting Logical Block Address and check that it's
-+ * not too big */
-+ lba = get_unaligned_be32(&fsg->cmnd[2]);
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+
-+ /* We allow DPO (Disable Page Out = don't save data in the
-+ * cache) but we don't implement it. */
-+ if ((fsg->cmnd[1] & ~0x10) != 0) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ verification_length = get_unaligned_be16(&fsg->cmnd[7]);
-+ if (unlikely(verification_length == 0))
-+ return -EIO; // No default reply
-+
-+ /* Prepare to carry out the file verify */
-+ amount_left = verification_length << curlun->blkbits;
-+ file_offset = ((loff_t) lba) << curlun->blkbits;
-+
-+ /* Write out all the dirty buffers before invalidating them */
-+ fsg_lun_fsync_sub(curlun);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ invalidate_sub(curlun);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ /* Just try to read the requested blocks */
-+ while (amount_left > 0) {
-+
-+ /* Figure out how much we need to read:
-+ * Try to read the remaining amount, but not more than
-+ * the buffer size.
-+ * And don't try to read past the end of the file.
-+ */
-+ amount = min((unsigned int) amount_left, mod_data.buflen);
-+ amount = min((loff_t) amount,
-+ curlun->file_length - file_offset);
-+ if (amount == 0) {
-+ curlun->sense_data =
-+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+
-+ /* Perform the read */
-+ file_offset_tmp = file_offset;
-+ nread = vfs_read(curlun->filp,
-+ (char __user *) bh->buf,
-+ amount, &file_offset_tmp);
-+ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
-+ (unsigned long long) file_offset,
-+ (int) nread);
-+ if (signal_pending(current))
-+ return -EINTR;
-+
-+ if (nread < 0) {
-+ LDBG(curlun, "error in file verify: %d\n",
-+ (int) nread);
-+ nread = 0;
-+ } else if (nread < amount) {
-+ LDBG(curlun, "partial file verify: %d/%u\n",
-+ (int) nread, amount);
-+ nread = round_down(nread, curlun->blksize);
-+ }
-+ if (nread == 0) {
-+ curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
-+ curlun->sense_data_info = file_offset >> curlun->blkbits;
-+ curlun->info_valid = 1;
-+ break;
-+ }
-+ file_offset += nread;
-+ amount_left -= nread;
-+ }
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ static char vendor_id[] = "Linux ";
-+ static char product_disk_id[] = "File-Stor Gadget";
-+ static char product_cdrom_id[] = "File-CD Gadget ";
-+
-+ if (!fsg->curlun) { // Unsupported LUNs are okay
-+ fsg->bad_lun_okay = 1;
-+ memset(buf, 0, 36);
-+ buf[0] = 0x7f; // Unsupported, no device-type
-+ buf[4] = 31; // Additional length
-+ return 36;
-+ }
-+
-+ memset(buf, 0, 8);
-+ buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
-+ if (mod_data.removable)
-+ buf[1] = 0x80;
-+ buf[2] = 2; // ANSI SCSI level 2
-+ buf[3] = 2; // SCSI-2 INQUIRY data format
-+ buf[4] = 31; // Additional length
-+ // No special options
-+ sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
-+ (mod_data.cdrom ? product_cdrom_id :
-+ product_disk_id),
-+ mod_data.release);
-+ return 36;
-+}
-+
-+
-+static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u8 *buf = (u8 *) bh->buf;
-+ u32 sd, sdinfo;
-+ int valid;
-+
-+ /*
-+ * From the SCSI-2 spec., section 7.9 (Unit attention condition):
-+ *
-+ * If a REQUEST SENSE command is received from an initiator
-+ * with a pending unit attention condition (before the target
-+ * generates the contingent allegiance condition), then the
-+ * target shall either:
-+ * a) report any pending sense data and preserve the unit
-+ * attention condition on the logical unit, or,
-+ * b) report the unit attention condition, may discard any
-+ * pending sense data, and clear the unit attention
-+ * condition on the logical unit for that initiator.
-+ *
-+ * FSG normally uses option a); enable this code to use option b).
-+ */
-+#if 0
-+ if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
-+ curlun->sense_data = curlun->unit_attention_data;
-+ curlun->unit_attention_data = SS_NO_SENSE;
-+ }
-+#endif
-+
-+ if (!curlun) { // Unsupported LUNs are okay
-+ fsg->bad_lun_okay = 1;
-+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-+ sdinfo = 0;
-+ valid = 0;
-+ } else {
-+ sd = curlun->sense_data;
-+ sdinfo = curlun->sense_data_info;
-+ valid = curlun->info_valid << 7;
-+ curlun->sense_data = SS_NO_SENSE;
-+ curlun->sense_data_info = 0;
-+ curlun->info_valid = 0;
-+ }
-+
-+ memset(buf, 0, 18);
-+ buf[0] = valid | 0x70; // Valid, current error
-+ buf[2] = SK(sd);
-+ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
-+ buf[7] = 18 - 8; // Additional sense length
-+ buf[12] = ASC(sd);
-+ buf[13] = ASCQ(sd);
-+ return 18;
-+}
-+
-+
-+static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
-+ int pmi = fsg->cmnd[8];
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ /* Check the PMI and LBA fields */
-+ if (pmi > 1 || (pmi == 0 && lba != 0)) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
-+ /* Max logical block */
-+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
-+ return 8;
-+}
-+
-+
-+static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int msf = fsg->cmnd[1] & 0x02;
-+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ if (lba >= curlun->num_sectors) {
-+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+ return -EINVAL;
-+ }
-+
-+ memset(buf, 0, 8);
-+ buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */
-+ store_cdrom_address(&buf[4], msf, lba);
-+ return 8;
-+}
-+
-+
-+static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int msf = fsg->cmnd[1] & 0x02;
-+ int start_track = fsg->cmnd[6];
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */
-+ start_track > 1) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ memset(buf, 0, 20);
-+ buf[1] = (20-2); /* TOC data length */
-+ buf[2] = 1; /* First track number */
-+ buf[3] = 1; /* Last track number */
-+ buf[5] = 0x16; /* Data track, copying allowed */
-+ buf[6] = 0x01; /* Only track is number 1 */
-+ store_cdrom_address(&buf[8], msf, 0);
-+
-+ buf[13] = 0x16; /* Lead-out track is data */
-+ buf[14] = 0xAA; /* Lead-out track number */
-+ store_cdrom_address(&buf[16], msf, curlun->num_sectors);
-+ return 20;
-+}
-+
-+
-+static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int mscmnd = fsg->cmnd[0];
-+ u8 *buf = (u8 *) bh->buf;
-+ u8 *buf0 = buf;
-+ int pc, page_code;
-+ int changeable_values, all_pages;
-+ int valid_page = 0;
-+ int len, limit;
-+
-+ if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ pc = fsg->cmnd[2] >> 6;
-+ page_code = fsg->cmnd[2] & 0x3f;
-+ if (pc == 3) {
-+ curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
-+ return -EINVAL;
-+ }
-+ changeable_values = (pc == 1);
-+ all_pages = (page_code == 0x3f);
-+
-+ /* Write the mode parameter header. Fixed values are: default
-+ * medium type, no cache control (DPOFUA), and no block descriptors.
-+ * The only variable value is the WriteProtect bit. We will fill in
-+ * the mode data length later. */
-+ memset(buf, 0, 8);
-+ if (mscmnd == MODE_SENSE) {
-+ buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
-+ buf += 4;
-+ limit = 255;
-+ } else { // MODE_SENSE_10
-+ buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
-+ buf += 8;
-+ limit = 65535; // Should really be mod_data.buflen
-+ }
-+
-+ /* No block descriptors */
-+
-+ /* The mode pages, in numerical order. The only page we support
-+ * is the Caching page. */
-+ if (page_code == 0x08 || all_pages) {
-+ valid_page = 1;
-+ buf[0] = 0x08; // Page code
-+ buf[1] = 10; // Page length
-+ memset(buf+2, 0, 10); // None of the fields are changeable
-+
-+ if (!changeable_values) {
-+ buf[2] = 0x04; // Write cache enable,
-+ // Read cache not disabled
-+ // No cache retention priorities
-+ put_unaligned_be16(0xffff, &buf[4]);
-+ /* Don't disable prefetch */
-+ /* Minimum prefetch = 0 */
-+ put_unaligned_be16(0xffff, &buf[8]);
-+ /* Maximum prefetch */
-+ put_unaligned_be16(0xffff, &buf[10]);
-+ /* Maximum prefetch ceiling */
-+ }
-+ buf += 12;
-+ }
-+
-+ /* Check that a valid page was requested and the mode data length
-+ * isn't too long. */
-+ len = buf - buf0;
-+ if (!valid_page || len > limit) {
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ /* Store the mode data length */
-+ if (mscmnd == MODE_SENSE)
-+ buf0[0] = len - 1;
-+ else
-+ put_unaligned_be16(len - 2, buf0);
-+ return len;
-+}
-+
-+
-+static int do_start_stop(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int loej, start;
-+
-+ if (!mod_data.removable) {
-+ curlun->sense_data = SS_INVALID_COMMAND;
-+ return -EINVAL;
-+ }
-+
-+ // int immed = fsg->cmnd[1] & 0x01;
-+ loej = fsg->cmnd[4] & 0x02;
-+ start = fsg->cmnd[4] & 0x01;
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+ if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed
-+ (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ if (!start) {
-+
-+ /* Are we allowed to unload the media? */
-+ if (curlun->prevent_medium_removal) {
-+ LDBG(curlun, "unload attempt prevented\n");
-+ curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
-+ return -EINVAL;
-+ }
-+ if (loej) { // Simulate an unload/eject
-+ up_read(&fsg->filesem);
-+ down_write(&fsg->filesem);
-+ fsg_lun_close(curlun);
-+ up_write(&fsg->filesem);
-+ down_read(&fsg->filesem);
-+ }
-+ } else {
-+
-+ /* Our emulation doesn't support mounting; the medium is
-+ * available for use as soon as it is loaded. */
-+ if (!fsg_lun_is_open(curlun)) {
-+ curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
-+ return -EINVAL;
-+ }
-+ }
-+#endif
-+ return 0;
-+}
-+
-+
-+static int do_prevent_allow(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ int prevent;
-+
-+ if (!mod_data.removable) {
-+ curlun->sense_data = SS_INVALID_COMMAND;
-+ return -EINVAL;
-+ }
-+
-+ prevent = fsg->cmnd[4] & 0x01;
-+ if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+
-+ if (curlun->prevent_medium_removal && !prevent)
-+ fsg_lun_fsync_sub(curlun);
-+ curlun->prevent_medium_removal = prevent;
-+ return 0;
-+}
-+
-+
-+static int do_read_format_capacities(struct fsg_dev *fsg,
-+ struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ u8 *buf = (u8 *) bh->buf;
-+
-+ buf[0] = buf[1] = buf[2] = 0;
-+ buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
-+ buf += 4;
-+
-+ put_unaligned_be32(curlun->num_sectors, &buf[0]);
-+ /* Number of blocks */
-+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
-+ buf[4] = 0x02; /* Current capacity */
-+ return 12;
-+}
-+
-+
-+static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+
-+ /* We don't support MODE SELECT */
-+ curlun->sense_data = SS_INVALID_COMMAND;
-+ return -EINVAL;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
-+{
-+ int rc;
-+
-+ rc = fsg_set_halt(fsg, fsg->bulk_in);
-+ if (rc == -EAGAIN)
-+ VDBG(fsg, "delayed bulk-in endpoint halt\n");
-+ while (rc != 0) {
-+ if (rc != -EAGAIN) {
-+ WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
-+ rc = 0;
-+ break;
-+ }
-+
-+ /* Wait for a short time and then try again */
-+ if (msleep_interruptible(100) != 0)
-+ return -EINTR;
-+ rc = usb_ep_set_halt(fsg->bulk_in);
-+ }
-+ return rc;
-+}
-+
-+static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
-+{
-+ int rc;
-+
-+ DBG(fsg, "bulk-in set wedge\n");
-+ rc = usb_ep_set_wedge(fsg->bulk_in);
-+ if (rc == -EAGAIN)
-+ VDBG(fsg, "delayed bulk-in endpoint wedge\n");
-+ while (rc != 0) {
-+ if (rc != -EAGAIN) {
-+ WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
-+ rc = 0;
-+ break;
-+ }
-+
-+ /* Wait for a short time and then try again */
-+ if (msleep_interruptible(100) != 0)
-+ return -EINTR;
-+ rc = usb_ep_set_wedge(fsg->bulk_in);
-+ }
-+ return rc;
-+}
-+
-+static int throw_away_data(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh;
-+ u32 amount;
-+ int rc;
-+
-+ while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
-+ fsg->usb_amount_left > 0) {
-+
-+ /* Throw away the data in a filled buffer */
-+ if (bh->state == BUF_STATE_FULL) {
-+ smp_rmb();
-+ bh->state = BUF_STATE_EMPTY;
-+ fsg->next_buffhd_to_drain = bh->next;
-+
-+ /* A short packet or an error ends everything */
-+ if (bh->outreq->actual < bh->bulk_out_intended_length ||
-+ bh->outreq->status != 0) {
-+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+ return -EINTR;
-+ }
-+ continue;
-+ }
-+
-+ /* Try to submit another request if we need one */
-+ bh = fsg->next_buffhd_to_fill;
-+ if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
-+ amount = min(fsg->usb_amount_left,
-+ (u32) mod_data.buflen);
-+
-+ /* Except at the end of the transfer, amount will be
-+ * equal to the buffer size, which is divisible by
-+ * the bulk-out maxpacket size.
-+ */
-+ set_bulk_out_req_length(fsg, bh, amount);
-+ start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+ &bh->outreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ fsg->usb_amount_left -= amount;
-+ continue;
-+ }
-+
-+ /* Otherwise wait for something to happen */
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+ return 0;
-+}
-+
-+
-+static int finish_reply(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
-+ int rc = 0;
-+
-+ switch (fsg->data_dir) {
-+ case DATA_DIR_NONE:
-+ break; // Nothing to send
-+
-+ /* If we don't know whether the host wants to read or write,
-+ * this must be CB or CBI with an unknown command. We mustn't
-+ * try to send or receive any data. So stall both bulk pipes
-+ * if we can and wait for a reset. */
-+ case DATA_DIR_UNKNOWN:
-+ if (mod_data.can_stall) {
-+ fsg_set_halt(fsg, fsg->bulk_out);
-+ rc = halt_bulk_in_endpoint(fsg);
-+ }
-+ break;
-+
-+ /* All but the last buffer of data must have already been sent */
-+ case DATA_DIR_TO_HOST:
-+ if (fsg->data_size == 0)
-+ ; // Nothing to send
-+
-+ /* If there's no residue, simply send the last buffer */
-+ else if (fsg->residue == 0) {
-+ bh->inreq->zero = 0;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ }
-+
-+ /* There is a residue. For CB and CBI, simply mark the end
-+ * of the data with a short packet. However, if we are
-+ * allowed to stall, there was no data at all (residue ==
-+ * data_size), and the command failed (invalid LUN or
-+ * sense data is set), then halt the bulk-in endpoint
-+ * instead. */
-+ else if (!transport_is_bbb()) {
-+ if (mod_data.can_stall &&
-+ fsg->residue == fsg->data_size &&
-+ (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
-+ bh->state = BUF_STATE_EMPTY;
-+ rc = halt_bulk_in_endpoint(fsg);
-+ } else {
-+ bh->inreq->zero = 1;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ }
-+ }
-+
-+ /*
-+ * For Bulk-only, mark the end of the data with a short
-+ * packet. If we are allowed to stall, halt the bulk-in
-+ * endpoint. (Note: This violates the Bulk-Only Transport
-+ * specification, which requires us to pad the data if we
-+ * don't halt the endpoint. Presumably nobody will mind.)
-+ */
-+ else {
-+ bh->inreq->zero = 1;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+ fsg->next_buffhd_to_fill = bh->next;
-+ if (mod_data.can_stall)
-+ rc = halt_bulk_in_endpoint(fsg);
-+ }
-+ break;
-+
-+ /* We have processed all we want from the data the host has sent.
-+ * There may still be outstanding bulk-out requests. */
-+ case DATA_DIR_FROM_HOST:
-+ if (fsg->residue == 0)
-+ ; // Nothing to receive
-+
-+ /* Did the host stop sending unexpectedly early? */
-+ else if (fsg->short_packet_received) {
-+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+ rc = -EINTR;
-+ }
-+
-+ /* We haven't processed all the incoming data. Even though
-+ * we may be allowed to stall, doing so would cause a race.
-+ * The controller may already have ACK'ed all the remaining
-+ * bulk-out packets, in which case the host wouldn't see a
-+ * STALL. Not realizing the endpoint was halted, it wouldn't
-+ * clear the halt -- leading to problems later on. */
-+#if 0
-+ else if (mod_data.can_stall) {
-+ fsg_set_halt(fsg, fsg->bulk_out);
-+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+ rc = -EINTR;
-+ }
-+#endif
-+
-+ /* We can't stall. Read in the excess data and throw it
-+ * all away. */
-+ else
-+ rc = throw_away_data(fsg);
-+ break;
-+ }
-+ return rc;
-+}
-+
-+
-+static int send_status(struct fsg_dev *fsg)
-+{
-+ struct fsg_lun *curlun = fsg->curlun;
-+ struct fsg_buffhd *bh;
-+ int rc;
-+ u8 status = US_BULK_STAT_OK;
-+ u32 sd, sdinfo = 0;
-+
-+ /* Wait for the next buffer to become available */
-+ bh = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ if (curlun) {
-+ sd = curlun->sense_data;
-+ sdinfo = curlun->sense_data_info;
-+ } else if (fsg->bad_lun_okay)
-+ sd = SS_NO_SENSE;
-+ else
-+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-+
-+ if (fsg->phase_error) {
-+ DBG(fsg, "sending phase-error status\n");
-+ status = US_BULK_STAT_PHASE;
-+ sd = SS_INVALID_COMMAND;
-+ } else if (sd != SS_NO_SENSE) {
-+ DBG(fsg, "sending command-failure status\n");
-+ status = US_BULK_STAT_FAIL;
-+ VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
-+ " info x%x\n",
-+ SK(sd), ASC(sd), ASCQ(sd), sdinfo);
-+ }
-+
-+ if (transport_is_bbb()) {
-+ struct bulk_cs_wrap *csw = bh->buf;
-+
-+ /* Store and send the Bulk-only CSW */
-+ csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
-+ csw->Tag = fsg->tag;
-+ csw->Residue = cpu_to_le32(fsg->residue);
-+ csw->Status = status;
-+
-+ bh->inreq->length = US_BULK_CS_WRAP_LEN;
-+ bh->inreq->zero = 0;
-+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+ &bh->inreq_busy, &bh->state);
-+
-+ } else if (mod_data.transport_type == USB_PR_CB) {
-+
-+ /* Control-Bulk transport has no status phase! */
-+ return 0;
-+
-+ } else { // USB_PR_CBI
-+ struct interrupt_data *buf = bh->buf;
-+
-+ /* Store and send the Interrupt data. UFI sends the ASC
-+ * and ASCQ bytes. Everything else sends a Type (which
-+ * is always 0) and the status Value. */
-+ if (mod_data.protocol_type == USB_SC_UFI) {
-+ buf->bType = ASC(sd);
-+ buf->bValue = ASCQ(sd);
-+ } else {
-+ buf->bType = 0;
-+ buf->bValue = status;
-+ }
-+ fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
-+
-+ fsg->intr_buffhd = bh; // Point to the right buffhd
-+ fsg->intreq->buf = bh->inreq->buf;
-+ fsg->intreq->context = bh;
-+ start_transfer(fsg, fsg->intr_in, fsg->intreq,
-+ &fsg->intreq_busy, &bh->state);
-+ }
-+
-+ fsg->next_buffhd_to_fill = bh->next;
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Check whether the command is properly formed and whether its data size
-+ * and direction agree with the values we already have. */
-+static int check_command(struct fsg_dev *fsg, int cmnd_size,
-+ enum data_direction data_dir, unsigned int mask,
-+ int needs_medium, const char *name)
-+{
-+ int i;
-+ int lun = fsg->cmnd[1] >> 5;
-+ static const char dirletter[4] = {'u', 'o', 'i', 'n'};
-+ char hdlen[20];
-+ struct fsg_lun *curlun;
-+
-+ /* Adjust the expected cmnd_size for protocol encapsulation padding.
-+ * Transparent SCSI doesn't pad. */
-+ if (protocol_is_scsi())
-+ ;
-+
-+ /* There's some disagreement as to whether RBC pads commands or not.
-+ * We'll play it safe and accept either form. */
-+ else if (mod_data.protocol_type == USB_SC_RBC) {
-+ if (fsg->cmnd_size == 12)
-+ cmnd_size = 12;
-+
-+ /* All the other protocols pad to 12 bytes */
-+ } else
-+ cmnd_size = 12;
-+
-+ hdlen[0] = 0;
-+ if (fsg->data_dir != DATA_DIR_UNKNOWN)
-+ sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
-+ fsg->data_size);
-+ VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n",
-+ name, cmnd_size, dirletter[(int) data_dir],
-+ fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
-+
-+ /* We can't reply at all until we know the correct data direction
-+ * and size. */
-+ if (fsg->data_size_from_cmnd == 0)
-+ data_dir = DATA_DIR_NONE;
-+ if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI
-+ fsg->data_dir = data_dir;
-+ fsg->data_size = fsg->data_size_from_cmnd;
-+
-+ } else { // Bulk-only
-+ if (fsg->data_size < fsg->data_size_from_cmnd) {
-+
-+ /* Host data size < Device data size is a phase error.
-+ * Carry out the command, but only transfer as much
-+ * as we are allowed. */
-+ fsg->data_size_from_cmnd = fsg->data_size;
-+ fsg->phase_error = 1;
-+ }
-+ }
-+ fsg->residue = fsg->usb_amount_left = fsg->data_size;
-+
-+ /* Conflicting data directions is a phase error */
-+ if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
-+ fsg->phase_error = 1;
-+ return -EINVAL;
-+ }
-+
-+ /* Verify the length of the command itself */
-+ if (cmnd_size != fsg->cmnd_size) {
-+
-+ /* Special case workaround: There are plenty of buggy SCSI
-+ * implementations. Many have issues with cbw->Length
-+ * field passing a wrong command size. For those cases we
-+ * always try to work around the problem by using the length
-+ * sent by the host side provided it is at least as large
-+ * as the correct command length.
-+ * Examples of such cases would be MS-Windows, which issues
-+ * REQUEST SENSE with cbw->Length == 12 where it should
-+ * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
-+ * REQUEST SENSE with cbw->Length == 10 where it should
-+ * be 6 as well.
-+ */
-+ if (cmnd_size <= fsg->cmnd_size) {
-+ DBG(fsg, "%s is buggy! Expected length %d "
-+ "but we got %d\n", name,
-+ cmnd_size, fsg->cmnd_size);
-+ cmnd_size = fsg->cmnd_size;
-+ } else {
-+ fsg->phase_error = 1;
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* Check that the LUN values are consistent */
-+ if (transport_is_bbb()) {
-+ if (fsg->lun != lun)
-+ DBG(fsg, "using LUN %d from CBW, "
-+ "not LUN %d from CDB\n",
-+ fsg->lun, lun);
-+ }
-+
-+ /* Check the LUN */
-+ curlun = fsg->curlun;
-+ if (curlun) {
-+ if (fsg->cmnd[0] != REQUEST_SENSE) {
-+ curlun->sense_data = SS_NO_SENSE;
-+ curlun->sense_data_info = 0;
-+ curlun->info_valid = 0;
-+ }
-+ } else {
-+ fsg->bad_lun_okay = 0;
-+
-+ /* INQUIRY and REQUEST SENSE commands are explicitly allowed
-+ * to use unsupported LUNs; all others may not. */
-+ if (fsg->cmnd[0] != INQUIRY &&
-+ fsg->cmnd[0] != REQUEST_SENSE) {
-+ DBG(fsg, "unsupported LUN %d\n", fsg->lun);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* If a unit attention condition exists, only INQUIRY and
-+ * REQUEST SENSE commands are allowed; anything else must fail. */
-+ if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
-+ fsg->cmnd[0] != INQUIRY &&
-+ fsg->cmnd[0] != REQUEST_SENSE) {
-+ curlun->sense_data = curlun->unit_attention_data;
-+ curlun->unit_attention_data = SS_NO_SENSE;
-+ return -EINVAL;
-+ }
-+
-+ /* Check that only command bytes listed in the mask are non-zero */
-+ fsg->cmnd[1] &= 0x1f; // Mask away the LUN
-+ for (i = 1; i < cmnd_size; ++i) {
-+ if (fsg->cmnd[i] && !(mask & (1 << i))) {
-+ if (curlun)
-+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* If the medium isn't mounted and the command needs to access
-+ * it, return an error. */
-+ if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
-+ curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/* wrapper of check_command for data size in blocks handling */
-+static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
-+ enum data_direction data_dir, unsigned int mask,
-+ int needs_medium, const char *name)
-+{
-+ if (fsg->curlun)
-+ fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
-+ return check_command(fsg, cmnd_size, data_dir,
-+ mask, needs_medium, name);
-+}
-+
-+static int do_scsi_command(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh;
-+ int rc;
-+ int reply = -EINVAL;
-+ int i;
-+ static char unknown[16];
-+
-+ dump_cdb(fsg);
-+
-+ /* Wait for the next buffer to become available for data or status */
-+ bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+ fsg->phase_error = 0;
-+ fsg->short_packet_received = 0;
-+
-+ down_read(&fsg->filesem); // We're using the backing file
-+ switch (fsg->cmnd[0]) {
-+
-+ case INQUIRY:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+ (1<<4), 0,
-+ "INQUIRY")) == 0)
-+ reply = do_inquiry(fsg, bh);
-+ break;
-+
-+ case MODE_SELECT:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
-+ (1<<1) | (1<<4), 0,
-+ "MODE SELECT(6)")) == 0)
-+ reply = do_mode_select(fsg, bh);
-+ break;
-+
-+ case MODE_SELECT_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
-+ (1<<1) | (3<<7), 0,
-+ "MODE SELECT(10)")) == 0)
-+ reply = do_mode_select(fsg, bh);
-+ break;
-+
-+ case MODE_SENSE:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+ (1<<1) | (1<<2) | (1<<4), 0,
-+ "MODE SENSE(6)")) == 0)
-+ reply = do_mode_sense(fsg, bh);
-+ break;
-+
-+ case MODE_SENSE_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (1<<1) | (1<<2) | (3<<7), 0,
-+ "MODE SENSE(10)")) == 0)
-+ reply = do_mode_sense(fsg, bh);
-+ break;
-+
-+ case ALLOW_MEDIUM_REMOVAL:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
-+ (1<<4), 0,
-+ "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
-+ reply = do_prevent_allow(fsg);
-+ break;
-+
-+ case READ_6:
-+ i = fsg->cmnd[4];
-+ fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
-+ if ((reply = check_command_size_in_blocks(fsg, 6,
-+ DATA_DIR_TO_HOST,
-+ (7<<1) | (1<<4), 1,
-+ "READ(6)")) == 0)
-+ reply = do_read(fsg);
-+ break;
-+
-+ case READ_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command_size_in_blocks(fsg, 10,
-+ DATA_DIR_TO_HOST,
-+ (1<<1) | (0xf<<2) | (3<<7), 1,
-+ "READ(10)")) == 0)
-+ reply = do_read(fsg);
-+ break;
-+
-+ case READ_12:
-+ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
-+ if ((reply = check_command_size_in_blocks(fsg, 12,
-+ DATA_DIR_TO_HOST,
-+ (1<<1) | (0xf<<2) | (0xf<<6), 1,
-+ "READ(12)")) == 0)
-+ reply = do_read(fsg);
-+ break;
-+
-+ case READ_CAPACITY:
-+ fsg->data_size_from_cmnd = 8;
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (0xf<<2) | (1<<8), 1,
-+ "READ CAPACITY")) == 0)
-+ reply = do_read_capacity(fsg, bh);
-+ break;
-+
-+ case READ_HEADER:
-+ if (!mod_data.cdrom)
-+ goto unknown_cmnd;
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (3<<7) | (0x1f<<1), 1,
-+ "READ HEADER")) == 0)
-+ reply = do_read_header(fsg, bh);
-+ break;
-+
-+ case READ_TOC:
-+ if (!mod_data.cdrom)
-+ goto unknown_cmnd;
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (7<<6) | (1<<1), 1,
-+ "READ TOC")) == 0)
-+ reply = do_read_toc(fsg, bh);
-+ break;
-+
-+ case READ_FORMAT_CAPACITIES:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+ (3<<7), 1,
-+ "READ FORMAT CAPACITIES")) == 0)
-+ reply = do_read_format_capacities(fsg, bh);
-+ break;
-+
-+ case REQUEST_SENSE:
-+ fsg->data_size_from_cmnd = fsg->cmnd[4];
-+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+ (1<<4), 0,
-+ "REQUEST SENSE")) == 0)
-+ reply = do_request_sense(fsg, bh);
-+ break;
-+
-+ case START_STOP:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
-+ (1<<1) | (1<<4), 0,
-+ "START-STOP UNIT")) == 0)
-+ reply = do_start_stop(fsg);
-+ break;
-+
-+ case SYNCHRONIZE_CACHE:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
-+ (0xf<<2) | (3<<7), 1,
-+ "SYNCHRONIZE CACHE")) == 0)
-+ reply = do_synchronize_cache(fsg);
-+ break;
-+
-+ case TEST_UNIT_READY:
-+ fsg->data_size_from_cmnd = 0;
-+ reply = check_command(fsg, 6, DATA_DIR_NONE,
-+ 0, 1,
-+ "TEST UNIT READY");
-+ break;
-+
-+ /* Although optional, this command is used by MS-Windows. We
-+ * support a minimal version: BytChk must be 0. */
-+ case VERIFY:
-+ fsg->data_size_from_cmnd = 0;
-+ if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
-+ (1<<1) | (0xf<<2) | (3<<7), 1,
-+ "VERIFY")) == 0)
-+ reply = do_verify(fsg);
-+ break;
-+
-+ case WRITE_6:
-+ i = fsg->cmnd[4];
-+ fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
-+ if ((reply = check_command_size_in_blocks(fsg, 6,
-+ DATA_DIR_FROM_HOST,
-+ (7<<1) | (1<<4), 1,
-+ "WRITE(6)")) == 0)
-+ reply = do_write(fsg);
-+ break;
-+
-+ case WRITE_10:
-+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+ if ((reply = check_command_size_in_blocks(fsg, 10,
-+ DATA_DIR_FROM_HOST,
-+ (1<<1) | (0xf<<2) | (3<<7), 1,
-+ "WRITE(10)")) == 0)
-+ reply = do_write(fsg);
-+ break;
-+
-+ case WRITE_12:
-+ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
-+ if ((reply = check_command_size_in_blocks(fsg, 12,
-+ DATA_DIR_FROM_HOST,
-+ (1<<1) | (0xf<<2) | (0xf<<6), 1,
-+ "WRITE(12)")) == 0)
-+ reply = do_write(fsg);
-+ break;
-+
-+ /* Some mandatory commands that we recognize but don't implement.
-+ * They don't mean much in this setting. It's left as an exercise
-+ * for anyone interested to implement RESERVE and RELEASE in terms
-+ * of Posix locks. */
-+ case FORMAT_UNIT:
-+ case RELEASE:
-+ case RESERVE:
-+ case SEND_DIAGNOSTIC:
-+ // Fall through
-+
-+ default:
-+ unknown_cmnd:
-+ fsg->data_size_from_cmnd = 0;
-+ sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
-+ if ((reply = check_command(fsg, fsg->cmnd_size,
-+ DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
-+ fsg->curlun->sense_data = SS_INVALID_COMMAND;
-+ reply = -EINVAL;
-+ }
-+ break;
-+ }
-+ up_read(&fsg->filesem);
-+
-+ if (reply == -EINTR || signal_pending(current))
-+ return -EINTR;
-+
-+ /* Set up the single reply buffer for finish_reply() */
-+ if (reply == -EINVAL)
-+ reply = 0; // Error reply length
-+ if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
-+ reply = min((u32) reply, fsg->data_size_from_cmnd);
-+ bh->inreq->length = reply;
-+ bh->state = BUF_STATE_FULL;
-+ fsg->residue -= reply;
-+ } // Otherwise it's already set
-+
-+ return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+ struct usb_request *req = bh->outreq;
-+ struct bulk_cb_wrap *cbw = req->buf;
-+
-+ /* Was this a real packet? Should it be ignored? */
-+ if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-+ return -EINVAL;
-+
-+ /* Is the CBW valid? */
-+ if (req->actual != US_BULK_CB_WRAP_LEN ||
-+ cbw->Signature != cpu_to_le32(
-+ US_BULK_CB_SIGN)) {
-+ DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
-+ req->actual,
-+ le32_to_cpu(cbw->Signature));
-+
-+ /* The Bulk-only spec says we MUST stall the IN endpoint
-+ * (6.6.1), so it's unavoidable. It also says we must
-+ * retain this state until the next reset, but there's
-+ * no way to tell the controller driver it should ignore
-+ * Clear-Feature(HALT) requests.
-+ *
-+ * We aren't required to halt the OUT endpoint; instead
-+ * we can simply accept and discard any data received
-+ * until the next reset. */
-+ wedge_bulk_in_endpoint(fsg);
-+ set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
-+ return -EINVAL;
-+ }
-+
-+ /* Is the CBW meaningful? */
-+ if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
-+ cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
-+ DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
-+ "cmdlen %u\n",
-+ cbw->Lun, cbw->Flags, cbw->Length);
-+
-+ /* We can do anything we want here, so let's stall the
-+ * bulk pipes if we are allowed to. */
-+ if (mod_data.can_stall) {
-+ fsg_set_halt(fsg, fsg->bulk_out);
-+ halt_bulk_in_endpoint(fsg);
-+ }
-+ return -EINVAL;
-+ }
-+
-+ /* Save the command for later */
-+ fsg->cmnd_size = cbw->Length;
-+ memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
-+ if (cbw->Flags & US_BULK_FLAG_IN)
-+ fsg->data_dir = DATA_DIR_TO_HOST;
-+ else
-+ fsg->data_dir = DATA_DIR_FROM_HOST;
-+ fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
-+ if (fsg->data_size == 0)
-+ fsg->data_dir = DATA_DIR_NONE;
-+ fsg->lun = cbw->Lun;
-+ fsg->tag = cbw->Tag;
-+ return 0;
-+}
-+
-+
-+static int get_next_command(struct fsg_dev *fsg)
-+{
-+ struct fsg_buffhd *bh;
-+ int rc = 0;
-+
-+ if (transport_is_bbb()) {
-+
-+ /* Wait for the next buffer to become available */
-+ bh = fsg->next_buffhd_to_fill;
-+ while (bh->state != BUF_STATE_EMPTY) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ /* Queue a request to read a Bulk-only CBW */
-+ set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
-+ start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+ &bh->outreq_busy, &bh->state);
-+
-+ /* We will drain the buffer in software, which means we
-+ * can reuse it for the next filling. No need to advance
-+ * next_buffhd_to_fill. */
-+
-+ /* Wait for the CBW to arrive */
-+ while (bh->state != BUF_STATE_FULL) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+ smp_rmb();
-+ rc = received_cbw(fsg, bh);
-+ bh->state = BUF_STATE_EMPTY;
-+
-+ } else { // USB_PR_CB or USB_PR_CBI
-+
-+ /* Wait for the next command to arrive */
-+ while (fsg->cbbuf_cmnd_size == 0) {
-+ rc = sleep_thread(fsg);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ /* Is the previous status interrupt request still busy?
-+ * The host is allowed to skip reading the status,
-+ * so we must cancel it. */
-+ if (fsg->intreq_busy)
-+ usb_ep_dequeue(fsg->intr_in, fsg->intreq);
-+
-+ /* Copy the command and mark the buffer empty */
-+ fsg->data_dir = DATA_DIR_UNKNOWN;
-+ spin_lock_irq(&fsg->lock);
-+ fsg->cmnd_size = fsg->cbbuf_cmnd_size;
-+ memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
-+ fsg->cbbuf_cmnd_size = 0;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ /* Use LUN from the command */
-+ fsg->lun = fsg->cmnd[1] >> 5;
-+ }
-+
-+ /* Update current lun */
-+ if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
-+ fsg->curlun = &fsg->luns[fsg->lun];
-+ else
-+ fsg->curlun = NULL;
-+
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
-+ const struct usb_endpoint_descriptor *d)
-+{
-+ int rc;
-+
-+ ep->driver_data = fsg;
-+ ep->desc = d;
-+ rc = usb_ep_enable(ep);
-+ if (rc)
-+ ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
-+ return rc;
-+}
-+
-+static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
-+ struct usb_request **preq)
-+{
-+ *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
-+ if (*preq)
-+ return 0;
-+ ERROR(fsg, "can't allocate request for %s\n", ep->name);
-+ return -ENOMEM;
-+}
-+
-+/*
-+ * Reset interface setting and re-init endpoint state (toggle etc).
-+ * Call with altsetting < 0 to disable the interface. The only other
-+ * available altsetting is 0, which enables the interface.
-+ */
-+static int do_set_interface(struct fsg_dev *fsg, int altsetting)
-+{
-+ int rc = 0;
-+ int i;
-+ const struct usb_endpoint_descriptor *d;
-+
-+ if (fsg->running)
-+ DBG(fsg, "reset interface\n");
-+
-+reset:
-+ /* Deallocate the requests */
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+ if (bh->inreq) {
-+ usb_ep_free_request(fsg->bulk_in, bh->inreq);
-+ bh->inreq = NULL;
-+ }
-+ if (bh->outreq) {
-+ usb_ep_free_request(fsg->bulk_out, bh->outreq);
-+ bh->outreq = NULL;
-+ }
-+ }
-+ if (fsg->intreq) {
-+ usb_ep_free_request(fsg->intr_in, fsg->intreq);
-+ fsg->intreq = NULL;
-+ }
-+
-+ /* Disable the endpoints */
-+ if (fsg->bulk_in_enabled) {
-+ usb_ep_disable(fsg->bulk_in);
-+ fsg->bulk_in_enabled = 0;
-+ }
-+ if (fsg->bulk_out_enabled) {
-+ usb_ep_disable(fsg->bulk_out);
-+ fsg->bulk_out_enabled = 0;
-+ }
-+ if (fsg->intr_in_enabled) {
-+ usb_ep_disable(fsg->intr_in);
-+ fsg->intr_in_enabled = 0;
-+ }
-+
-+ fsg->running = 0;
-+ if (altsetting < 0 || rc != 0)
-+ return rc;
-+
-+ DBG(fsg, "set interface %d\n", altsetting);
-+
-+ /* Enable the endpoints */
-+ d = fsg_ep_desc(fsg->gadget,
-+ &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
-+ &fsg_ss_bulk_in_desc);
-+ if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
-+ goto reset;
-+ fsg->bulk_in_enabled = 1;
-+
-+ d = fsg_ep_desc(fsg->gadget,
-+ &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
-+ &fsg_ss_bulk_out_desc);
-+ if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
-+ goto reset;
-+ fsg->bulk_out_enabled = 1;
-+ fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
-+ clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
-+
-+ if (transport_is_cbi()) {
-+ d = fsg_ep_desc(fsg->gadget,
-+ &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
-+ &fsg_ss_intr_in_desc);
-+ if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
-+ goto reset;
-+ fsg->intr_in_enabled = 1;
-+ }
-+
-+ /* Allocate the requests */
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+ if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
-+ goto reset;
-+ if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
-+ goto reset;
-+ bh->inreq->buf = bh->outreq->buf = bh->buf;
-+ bh->inreq->context = bh->outreq->context = bh;
-+ bh->inreq->complete = bulk_in_complete;
-+ bh->outreq->complete = bulk_out_complete;
-+ }
-+ if (transport_is_cbi()) {
-+ if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
-+ goto reset;
-+ fsg->intreq->complete = intr_in_complete;
-+ }
-+
-+ fsg->running = 1;
-+ for (i = 0; i < fsg->nluns; ++i)
-+ fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
-+ return rc;
-+}
-+
-+
-+/*
-+ * Change our operational configuration. This code must agree with the code
-+ * that returns config descriptors, and with interface altsetting code.
-+ *
-+ * It's also responsible for power management interactions. Some
-+ * configurations might not work with our current power sources.
-+ * For now we just assume the gadget is always self-powered.
-+ */
-+static int do_set_config(struct fsg_dev *fsg, u8 new_config)
-+{
-+ int rc = 0;
-+
-+ /* Disable the single interface */
-+ if (fsg->config != 0) {
-+ DBG(fsg, "reset config\n");
-+ fsg->config = 0;
-+ rc = do_set_interface(fsg, -1);
-+ }
-+
-+ /* Enable the interface */
-+ if (new_config != 0) {
-+ fsg->config = new_config;
-+ if ((rc = do_set_interface(fsg, 0)) != 0)
-+ fsg->config = 0; // Reset on errors
-+ else
-+ INFO(fsg, "%s config #%d\n",
-+ usb_speed_string(fsg->gadget->speed),
-+ fsg->config);
-+ }
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void handle_exception(struct fsg_dev *fsg)
-+{
-+ siginfo_t info;
-+ int sig;
-+ int i;
-+ int num_active;
-+ struct fsg_buffhd *bh;
-+ enum fsg_state old_state;
-+ u8 new_config;
-+ struct fsg_lun *curlun;
-+ unsigned int exception_req_tag;
-+ int rc;
-+
-+ /* Clear the existing signals. Anything but SIGUSR1 is converted
-+ * into a high-priority EXIT exception. */
-+ for (;;) {
-+ sig = dequeue_signal_lock(current, &current->blocked, &info);
-+ if (!sig)
-+ break;
-+ if (sig != SIGUSR1) {
-+ if (fsg->state < FSG_STATE_EXIT)
-+ DBG(fsg, "Main thread exiting on signal\n");
-+ raise_exception(fsg, FSG_STATE_EXIT);
-+ }
-+ }
-+
-+ /* Cancel all the pending transfers */
-+ if (fsg->intreq_busy)
-+ usb_ep_dequeue(fsg->intr_in, fsg->intreq);
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ bh = &fsg->buffhds[i];
-+ if (bh->inreq_busy)
-+ usb_ep_dequeue(fsg->bulk_in, bh->inreq);
-+ if (bh->outreq_busy)
-+ usb_ep_dequeue(fsg->bulk_out, bh->outreq);
-+ }
-+
-+ /* Wait until everything is idle */
-+ for (;;) {
-+ num_active = fsg->intreq_busy;
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ bh = &fsg->buffhds[i];
-+ num_active += bh->inreq_busy + bh->outreq_busy;
-+ }
-+ if (num_active == 0)
-+ break;
-+ if (sleep_thread(fsg))
-+ return;
-+ }
-+
-+ /* Clear out the controller's fifos */
-+ if (fsg->bulk_in_enabled)
-+ usb_ep_fifo_flush(fsg->bulk_in);
-+ if (fsg->bulk_out_enabled)
-+ usb_ep_fifo_flush(fsg->bulk_out);
-+ if (fsg->intr_in_enabled)
-+ usb_ep_fifo_flush(fsg->intr_in);
-+
-+ /* Reset the I/O buffer states and pointers, the SCSI
-+ * state, and the exception. Then invoke the handler. */
-+ spin_lock_irq(&fsg->lock);
-+
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ bh = &fsg->buffhds[i];
-+ bh->state = BUF_STATE_EMPTY;
-+ }
-+ fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
-+ &fsg->buffhds[0];
-+
-+ exception_req_tag = fsg->exception_req_tag;
-+ new_config = fsg->new_config;
-+ old_state = fsg->state;
-+
-+ if (old_state == FSG_STATE_ABORT_BULK_OUT)
-+ fsg->state = FSG_STATE_STATUS_PHASE;
-+ else {
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ curlun->prevent_medium_removal = 0;
-+ curlun->sense_data = curlun->unit_attention_data =
-+ SS_NO_SENSE;
-+ curlun->sense_data_info = 0;
-+ curlun->info_valid = 0;
-+ }
-+ fsg->state = FSG_STATE_IDLE;
-+ }
-+ spin_unlock_irq(&fsg->lock);
-+
-+ /* Carry out any extra actions required for the exception */
-+ switch (old_state) {
-+ default:
-+ break;
-+
-+ case FSG_STATE_ABORT_BULK_OUT:
-+ send_status(fsg);
-+ spin_lock_irq(&fsg->lock);
-+ if (fsg->state == FSG_STATE_STATUS_PHASE)
-+ fsg->state = FSG_STATE_IDLE;
-+ spin_unlock_irq(&fsg->lock);
-+ break;
-+
-+ case FSG_STATE_RESET:
-+ /* In case we were forced against our will to halt a
-+ * bulk endpoint, clear the halt now. (The SuperH UDC
-+ * requires this.) */
-+ if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-+ usb_ep_clear_halt(fsg->bulk_in);
-+
-+ if (transport_is_bbb()) {
-+ if (fsg->ep0_req_tag == exception_req_tag)
-+ ep0_queue(fsg); // Complete the status stage
-+
-+ } else if (transport_is_cbi())
-+ send_status(fsg); // Status by interrupt pipe
-+
-+ /* Technically this should go here, but it would only be
-+ * a waste of time. Ditto for the INTERFACE_CHANGE and
-+ * CONFIG_CHANGE cases. */
-+ // for (i = 0; i < fsg->nluns; ++i)
-+ // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
-+ break;
-+
-+ case FSG_STATE_INTERFACE_CHANGE:
-+ rc = do_set_interface(fsg, 0);
-+ if (fsg->ep0_req_tag != exception_req_tag)
-+ break;
-+ if (rc != 0) // STALL on errors
-+ fsg_set_halt(fsg, fsg->ep0);
-+ else // Complete the status stage
-+ ep0_queue(fsg);
-+ break;
-+
-+ case FSG_STATE_CONFIG_CHANGE:
-+ rc = do_set_config(fsg, new_config);
-+ if (fsg->ep0_req_tag != exception_req_tag)
-+ break;
-+ if (rc != 0) // STALL on errors
-+ fsg_set_halt(fsg, fsg->ep0);
-+ else // Complete the status stage
-+ ep0_queue(fsg);
-+ break;
-+
-+ case FSG_STATE_DISCONNECT:
-+ for (i = 0; i < fsg->nluns; ++i)
-+ fsg_lun_fsync_sub(fsg->luns + i);
-+ do_set_config(fsg, 0); // Unconfigured state
-+ break;
-+
-+ case FSG_STATE_EXIT:
-+ case FSG_STATE_TERMINATED:
-+ do_set_config(fsg, 0); // Free resources
-+ spin_lock_irq(&fsg->lock);
-+ fsg->state = FSG_STATE_TERMINATED; // Stop the thread
-+ spin_unlock_irq(&fsg->lock);
-+ break;
-+ }
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int fsg_main_thread(void *fsg_)
-+{
-+ struct fsg_dev *fsg = fsg_;
-+
-+ /* Allow the thread to be killed by a signal, but set the signal mask
-+ * to block everything but INT, TERM, KILL, and USR1. */
-+ allow_signal(SIGINT);
-+ allow_signal(SIGTERM);
-+ allow_signal(SIGKILL);
-+ allow_signal(SIGUSR1);
-+
-+ /* Allow the thread to be frozen */
-+ set_freezable();
-+
-+ /* Arrange for userspace references to be interpreted as kernel
-+ * pointers. That way we can pass a kernel pointer to a routine
-+ * that expects a __user pointer and it will work okay. */
-+ set_fs(get_ds());
-+
-+ /* The main loop */
-+ while (fsg->state != FSG_STATE_TERMINATED) {
-+ if (exception_in_progress(fsg) || signal_pending(current)) {
-+ handle_exception(fsg);
-+ continue;
-+ }
-+
-+ if (!fsg->running) {
-+ sleep_thread(fsg);
-+ continue;
-+ }
-+
-+ if (get_next_command(fsg))
-+ continue;
-+
-+ spin_lock_irq(&fsg->lock);
-+ if (!exception_in_progress(fsg))
-+ fsg->state = FSG_STATE_DATA_PHASE;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ if (do_scsi_command(fsg) || finish_reply(fsg))
-+ continue;
-+
-+ spin_lock_irq(&fsg->lock);
-+ if (!exception_in_progress(fsg))
-+ fsg->state = FSG_STATE_STATUS_PHASE;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ if (send_status(fsg))
-+ continue;
-+
-+ spin_lock_irq(&fsg->lock);
-+ if (!exception_in_progress(fsg))
-+ fsg->state = FSG_STATE_IDLE;
-+ spin_unlock_irq(&fsg->lock);
-+ }
-+
-+ spin_lock_irq(&fsg->lock);
-+ fsg->thread_task = NULL;
-+ spin_unlock_irq(&fsg->lock);
-+
-+ /* If we are exiting because of a signal, unregister the
-+ * gadget driver. */
-+ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
-+ usb_gadget_unregister_driver(&fsg_driver);
-+
-+ /* Let the unbind and cleanup routines know the thread has exited */
-+ complete_and_exit(&fsg->thread_notifier, 0);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/* The write permissions and store_xxx pointers are set in fsg_bind() */
-+static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
-+static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
-+static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void fsg_release(struct kref *ref)
-+{
-+ struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref);
-+
-+ kfree(fsg->luns);
-+ kfree(fsg);
-+}
-+
-+static void lun_release(struct device *dev)
-+{
-+ struct rw_semaphore *filesem = dev_get_drvdata(dev);
-+ struct fsg_dev *fsg =
-+ container_of(filesem, struct fsg_dev, filesem);
-+
-+ kref_put(&fsg->ref, fsg_release);
-+}
-+
-+static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+ int i;
-+ struct fsg_lun *curlun;
-+ struct usb_request *req = fsg->ep0req;
-+
-+ DBG(fsg, "unbind\n");
-+ clear_bit(REGISTERED, &fsg->atomic_bitflags);
-+
-+ /* If the thread isn't already dead, tell it to exit now */
-+ if (fsg->state != FSG_STATE_TERMINATED) {
-+ raise_exception(fsg, FSG_STATE_EXIT);
-+ wait_for_completion(&fsg->thread_notifier);
-+
-+ /* The cleanup routine waits for this completion also */
-+ complete(&fsg->thread_notifier);
-+ }
-+
-+ /* Unregister the sysfs attribute files and the LUNs */
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ if (curlun->registered) {
-+ device_remove_file(&curlun->dev, &dev_attr_nofua);
-+ device_remove_file(&curlun->dev, &dev_attr_ro);
-+ device_remove_file(&curlun->dev, &dev_attr_file);
-+ fsg_lun_close(curlun);
-+ device_unregister(&curlun->dev);
-+ curlun->registered = 0;
-+ }
-+ }
-+
-+ /* Free the data buffers */
-+ for (i = 0; i < fsg_num_buffers; ++i)
-+ kfree(fsg->buffhds[i].buf);
-+
-+ /* Free the request and buffer for endpoint 0 */
-+ if (req) {
-+ kfree(req->buf);
-+ usb_ep_free_request(fsg->ep0, req);
-+ }
-+
-+ set_gadget_data(gadget, NULL);
-+}
-+
-+
-+static int __init check_parameters(struct fsg_dev *fsg)
-+{
-+ int prot;
-+ int gcnum;
-+
-+ /* Store the default values */
-+ mod_data.transport_type = USB_PR_BULK;
-+ mod_data.transport_name = "Bulk-only";
-+ mod_data.protocol_type = USB_SC_SCSI;
-+ mod_data.protocol_name = "Transparent SCSI";
-+
-+ /* Some peripheral controllers are known not to be able to
-+ * halt bulk endpoints correctly. If one of them is present,
-+ * disable stalls.
-+ */
-+ if (gadget_is_at91(fsg->gadget))
-+ mod_data.can_stall = 0;
-+
-+ if (mod_data.release == 0xffff) { // Parameter wasn't set
-+ gcnum = usb_gadget_controller_number(fsg->gadget);
-+ if (gcnum >= 0)
-+ mod_data.release = 0x0300 + gcnum;
-+ else {
-+ WARNING(fsg, "controller '%s' not recognized\n",
-+ fsg->gadget->name);
-+ mod_data.release = 0x0399;
-+ }
-+ }
-+
-+ prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+ if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
-+ ; // Use default setting
-+ } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
-+ mod_data.transport_type = USB_PR_CB;
-+ mod_data.transport_name = "Control-Bulk";
-+ } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
-+ mod_data.transport_type = USB_PR_CBI;
-+ mod_data.transport_name = "Control-Bulk-Interrupt";
-+ } else {
-+ ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
-+ return -EINVAL;
-+ }
-+
-+ if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
-+ prot == USB_SC_SCSI) {
-+ ; // Use default setting
-+ } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
-+ prot == USB_SC_RBC) {
-+ mod_data.protocol_type = USB_SC_RBC;
-+ mod_data.protocol_name = "RBC";
-+ } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
-+ strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
-+ prot == USB_SC_8020) {
-+ mod_data.protocol_type = USB_SC_8020;
-+ mod_data.protocol_name = "8020i (ATAPI)";
-+ } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
-+ prot == USB_SC_QIC) {
-+ mod_data.protocol_type = USB_SC_QIC;
-+ mod_data.protocol_name = "QIC-157";
-+ } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
-+ prot == USB_SC_UFI) {
-+ mod_data.protocol_type = USB_SC_UFI;
-+ mod_data.protocol_name = "UFI";
-+ } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
-+ prot == USB_SC_8070) {
-+ mod_data.protocol_type = USB_SC_8070;
-+ mod_data.protocol_name = "8070i";
-+ } else {
-+ ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
-+ return -EINVAL;
-+ }
-+
-+ mod_data.buflen &= PAGE_CACHE_MASK;
-+ if (mod_data.buflen <= 0) {
-+ ERROR(fsg, "invalid buflen\n");
-+ return -ETOOSMALL;
-+ }
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+ /* Serial string handling.
-+ * On a real device, the serial string would be loaded
-+ * from permanent storage. */
-+ if (mod_data.serial) {
-+ const char *ch;
-+ unsigned len = 0;
-+
-+ /* Sanity check :
-+ * The CB[I] specification limits the serial string to
-+ * 12 uppercase hexadecimal characters.
-+ * BBB need at least 12 uppercase hexadecimal characters,
-+ * with a maximum of 126. */
-+ for (ch = mod_data.serial; *ch; ++ch) {
-+ ++len;
-+ if ((*ch < '0' || *ch > '9') &&
-+ (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
-+ WARNING(fsg,
-+ "Invalid serial string character: %c\n",
-+ *ch);
-+ goto no_serial;
-+ }
-+ }
-+ if (len > 126 ||
-+ (mod_data.transport_type == USB_PR_BULK && len < 12) ||
-+ (mod_data.transport_type != USB_PR_BULK && len > 12)) {
-+ WARNING(fsg, "Invalid serial string length!\n");
-+ goto no_serial;
-+ }
-+ fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
-+ } else {
-+ WARNING(fsg, "No serial-number string provided!\n");
-+ no_serial:
-+ device_desc.iSerialNumber = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+static int __init fsg_bind(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = the_fsg;
-+ int rc;
-+ int i;
-+ struct fsg_lun *curlun;
-+ struct usb_ep *ep;
-+ struct usb_request *req;
-+ char *pathbuf, *p;
-+
-+ fsg->gadget = gadget;
-+ set_gadget_data(gadget, fsg);
-+ fsg->ep0 = gadget->ep0;
-+ fsg->ep0->driver_data = fsg;
-+
-+ if ((rc = check_parameters(fsg)) != 0)
-+ goto out;
-+
-+ if (mod_data.removable) { // Enable the store_xxx attributes
-+ dev_attr_file.attr.mode = 0644;
-+ dev_attr_file.store = fsg_store_file;
-+ if (!mod_data.cdrom) {
-+ dev_attr_ro.attr.mode = 0644;
-+ dev_attr_ro.store = fsg_store_ro;
-+ }
-+ }
-+
-+ /* Only for removable media? */
-+ dev_attr_nofua.attr.mode = 0644;
-+ dev_attr_nofua.store = fsg_store_nofua;
-+
-+ /* Find out how many LUNs there should be */
-+ i = mod_data.nluns;
-+ if (i == 0)
-+ i = max(mod_data.num_filenames, 1u);
-+ if (i > FSG_MAX_LUNS) {
-+ ERROR(fsg, "invalid number of LUNs: %d\n", i);
-+ rc = -EINVAL;
-+ goto out;
-+ }
-+
-+ /* Create the LUNs, open their backing files, and register the
-+ * LUN devices in sysfs. */
-+ fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
-+ if (!fsg->luns) {
-+ rc = -ENOMEM;
-+ goto out;
-+ }
-+ fsg->nluns = i;
-+
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ curlun->cdrom = !!mod_data.cdrom;
-+ curlun->ro = mod_data.cdrom || mod_data.ro[i];
-+ curlun->initially_ro = curlun->ro;
-+ curlun->removable = mod_data.removable;
-+ curlun->nofua = mod_data.nofua[i];
-+ curlun->dev.release = lun_release;
-+ curlun->dev.parent = &gadget->dev;
-+ curlun->dev.driver = &fsg_driver.driver;
-+ dev_set_drvdata(&curlun->dev, &fsg->filesem);
-+ dev_set_name(&curlun->dev,"%s-lun%d",
-+ dev_name(&gadget->dev), i);
-+
-+ kref_get(&fsg->ref);
-+ rc = device_register(&curlun->dev);
-+ if (rc) {
-+ INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
-+ put_device(&curlun->dev);
-+ goto out;
-+ }
-+ curlun->registered = 1;
-+
-+ rc = device_create_file(&curlun->dev, &dev_attr_ro);
-+ if (rc)
-+ goto out;
-+ rc = device_create_file(&curlun->dev, &dev_attr_nofua);
-+ if (rc)
-+ goto out;
-+ rc = device_create_file(&curlun->dev, &dev_attr_file);
-+ if (rc)
-+ goto out;
-+
-+ if (mod_data.file[i] && *mod_data.file[i]) {
-+ rc = fsg_lun_open(curlun, mod_data.file[i]);
-+ if (rc)
-+ goto out;
-+ } else if (!mod_data.removable) {
-+ ERROR(fsg, "no file given for LUN%d\n", i);
-+ rc = -EINVAL;
-+ goto out;
-+ }
-+ }
-+
-+ /* Find all the endpoints we will use */
-+ usb_ep_autoconfig_reset(gadget);
-+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
-+ if (!ep)
-+ goto autoconf_fail;
-+ ep->driver_data = fsg; // claim the endpoint
-+ fsg->bulk_in = ep;
-+
-+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
-+ if (!ep)
-+ goto autoconf_fail;
-+ ep->driver_data = fsg; // claim the endpoint
-+ fsg->bulk_out = ep;
-+
-+ if (transport_is_cbi()) {
-+ ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
-+ if (!ep)
-+ goto autoconf_fail;
-+ ep->driver_data = fsg; // claim the endpoint
-+ fsg->intr_in = ep;
-+ }
-+
-+ /* Fix up the descriptors */
-+ device_desc.idVendor = cpu_to_le16(mod_data.vendor);
-+ device_desc.idProduct = cpu_to_le16(mod_data.product);
-+ device_desc.bcdDevice = cpu_to_le16(mod_data.release);
-+
-+ i = (transport_is_cbi() ? 3 : 2); // Number of endpoints
-+ fsg_intf_desc.bNumEndpoints = i;
-+ fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
-+ fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
-+ fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+ if (gadget_is_dualspeed(gadget)) {
-+ fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+ /* Assume endpoint addresses are the same for both speeds */
-+ fsg_hs_bulk_in_desc.bEndpointAddress =
-+ fsg_fs_bulk_in_desc.bEndpointAddress;
-+ fsg_hs_bulk_out_desc.bEndpointAddress =
-+ fsg_fs_bulk_out_desc.bEndpointAddress;
-+ fsg_hs_intr_in_desc.bEndpointAddress =
-+ fsg_fs_intr_in_desc.bEndpointAddress;
-+ }
-+
-+ if (gadget_is_superspeed(gadget)) {
-+ unsigned max_burst;
-+
-+ fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+ /* Calculate bMaxBurst, we know packet size is 1024 */
-+ max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
-+
-+ /* Assume endpoint addresses are the same for both speeds */
-+ fsg_ss_bulk_in_desc.bEndpointAddress =
-+ fsg_fs_bulk_in_desc.bEndpointAddress;
-+ fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
-+
-+ fsg_ss_bulk_out_desc.bEndpointAddress =
-+ fsg_fs_bulk_out_desc.bEndpointAddress;
-+ fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
-+ }
-+
-+ if (gadget_is_otg(gadget))
-+ fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
-+
-+ rc = -ENOMEM;
-+
-+ /* Allocate the request and buffer for endpoint 0 */
-+ fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
-+ if (!req)
-+ goto out;
-+ req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
-+ if (!req->buf)
-+ goto out;
-+ req->complete = ep0_complete;
-+
-+ /* Allocate the data buffers */
-+ for (i = 0; i < fsg_num_buffers; ++i) {
-+ struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+ /* Allocate for the bulk-in endpoint. We assume that
-+ * the buffer will also work with the bulk-out (and
-+ * interrupt-in) endpoint. */
-+ bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
-+ if (!bh->buf)
-+ goto out;
-+ bh->next = bh + 1;
-+ }
-+ fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
-+
-+ /* This should reflect the actual gadget power source */
-+ usb_gadget_set_selfpowered(gadget);
-+
-+ snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
-+ "%s %s with %s",
-+ init_utsname()->sysname, init_utsname()->release,
-+ gadget->name);
-+
-+ fsg->thread_task = kthread_create(fsg_main_thread, fsg,
-+ "file-storage-gadget");
-+ if (IS_ERR(fsg->thread_task)) {
-+ rc = PTR_ERR(fsg->thread_task);
-+ goto out;
-+ }
-+
-+ INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
-+ INFO(fsg, "NOTE: This driver is deprecated. "
-+ "Consider using g_mass_storage instead.\n");
-+ INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
-+
-+ pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
-+ for (i = 0; i < fsg->nluns; ++i) {
-+ curlun = &fsg->luns[i];
-+ if (fsg_lun_is_open(curlun)) {
-+ p = NULL;
-+ if (pathbuf) {
-+ p = d_path(&curlun->filp->f_path,
-+ pathbuf, PATH_MAX);
-+ if (IS_ERR(p))
-+ p = NULL;
-+ }
-+ LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
-+ curlun->ro, curlun->nofua, (p ? p : "(error)"));
-+ }
-+ }
-+ kfree(pathbuf);
-+
-+ DBG(fsg, "transport=%s (x%02x)\n",
-+ mod_data.transport_name, mod_data.transport_type);
-+ DBG(fsg, "protocol=%s (x%02x)\n",
-+ mod_data.protocol_name, mod_data.protocol_type);
-+ DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
-+ mod_data.vendor, mod_data.product, mod_data.release);
-+ DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
-+ mod_data.removable, mod_data.can_stall,
-+ mod_data.cdrom, mod_data.buflen);
-+ DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
-+
-+ set_bit(REGISTERED, &fsg->atomic_bitflags);
-+
-+ /* Tell the thread to start working */
-+ wake_up_process(fsg->thread_task);
-+ return 0;
-+
-+autoconf_fail:
-+ ERROR(fsg, "unable to autoconfigure all endpoints\n");
-+ rc = -ENOTSUPP;
-+
-+out:
-+ fsg->state = FSG_STATE_TERMINATED; // The thread is dead
-+ fsg_unbind(gadget);
-+ complete(&fsg->thread_notifier);
-+ return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void fsg_suspend(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+
-+ DBG(fsg, "suspend\n");
-+ set_bit(SUSPENDED, &fsg->atomic_bitflags);
-+}
-+
-+static void fsg_resume(struct usb_gadget *gadget)
-+{
-+ struct fsg_dev *fsg = get_gadget_data(gadget);
-+
-+ DBG(fsg, "resume\n");
-+ clear_bit(SUSPENDED, &fsg->atomic_bitflags);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver fsg_driver = {
-+ .max_speed = USB_SPEED_SUPER,
-+ .function = (char *) fsg_string_product,
-+ .unbind = fsg_unbind,
-+ .disconnect = fsg_disconnect,
-+ .setup = fsg_setup,
-+ .suspend = fsg_suspend,
-+ .resume = fsg_resume,
-+
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ // .release = ...
-+ // .suspend = ...
-+ // .resume = ...
-+ },
-+};
-+
-+
-+static int __init fsg_alloc(void)
-+{
-+ struct fsg_dev *fsg;
-+
-+ fsg = kzalloc(sizeof *fsg +
-+ fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
-+
-+ if (!fsg)
-+ return -ENOMEM;
-+ spin_lock_init(&fsg->lock);
-+ init_rwsem(&fsg->filesem);
-+ kref_init(&fsg->ref);
-+ init_completion(&fsg->thread_notifier);
-+
-+ the_fsg = fsg;
-+ return 0;
-+}
-+
-+
-+static int __init fsg_init(void)
-+{
-+ int rc;
-+ struct fsg_dev *fsg;
-+
-+ rc = fsg_num_buffers_validate();
-+ if (rc != 0)
-+ return rc;
-+
-+ if ((rc = fsg_alloc()) != 0)
-+ return rc;
-+ fsg = the_fsg;
-+ if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
-+ kref_put(&fsg->ref, fsg_release);
-+ return rc;
-+}
-+module_init(fsg_init);
-+
-+
-+static void __exit fsg_cleanup(void)
-+{
-+ struct fsg_dev *fsg = the_fsg;
-+
-+ /* Unregister the driver iff the thread hasn't already done so */
-+ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
-+ usb_gadget_unregister_driver(&fsg_driver);
-+
-+ /* Wait for the thread to finish up */
-+ wait_for_completion(&fsg->thread_notifier);
-+
-+ kref_put(&fsg->ref, fsg_release);
-+}
-+module_exit(fsg_cleanup);
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/changes.txt linux-rpi/drivers/usb/host/dwc_common_port/changes.txt
---- linux-3.18.14/drivers/usb/host/dwc_common_port/changes.txt 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/changes.txt 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,174 @@
-+
-+dwc_read_reg32() and friends now take an additional parameter, a pointer to an
-+IO context struct. The IO context struct should live in an os-dependent struct
-+in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
-+named 'os_dep' embedded in the main device struct. So there these calls look
-+like this:
-+
-+ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
-+
-+ dwc_write_reg32(&usb3_dev->os_dep.ioctx,
-+ &pcd->dev_global_regs->dcfg, 0);
-+
-+Note that for the existing Linux driver ports, it is not necessary to actually
-+define the 'ioctx' member in the os-dependent struct. Since Linux does not
-+require an IO context, its macros for dwc_read_reg32() and friends do not
-+use the context pointer, so it is optimized away by the compiler. But it is
-+necessary to add the pointer parameter to all of the call sites, to be ready
-+for any future ports (such as FreeBSD) which do require an IO context.
-+
-+
-+Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
-+take an additional parameter, a pointer to a memory context. Examples:
-+
-+ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
-+
-+ dwc_free(&usb3_dev->os_dep.memctx, addr);
-+
-+Again, for the Linux ports, it is not necessary to actually define the memctx
-+member, but it is necessary to add the pointer parameter to all of the call
-+sites.
-+
-+
-+Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
-+
-+ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
-+
-+ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
-+
-+
-+Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
-+
-+ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
-+
-+ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
-+
-+
-+Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
-+
-+ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
-+
-+ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
-+
-+
-+Same for dwc_timer_alloc(). Example:
-+
-+ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
-+ cb_func, cb_data);
-+
-+
-+Same for dwc_waitq_alloc(). Example:
-+
-+ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
-+
-+
-+Same for dwc_thread_run(). Example:
-+
-+ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
-+ "dwc_usb3_thd1", data);
-+
-+
-+Same for dwc_workq_alloc(). Example:
-+
-+ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
-+
-+
-+Same for dwc_task_alloc(). Example:
-+
-+ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
-+ cb_func, cb_data);
-+
-+
-+In addition to the context pointer additions, a few core functions have had
-+other changes made to their parameters:
-+
-+The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
-+has been changed from a uint64_t to a dwc_irqflags_t.
-+
-+dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
-+FreeBSD equivalent of that function requires it.
-+
-+And, in addition to the context pointer, dwc_task_alloc() also adds a
-+'char *name' parameter, to be consistent with dwc_thread_run() and
-+dwc_workq_alloc(), and because the FreeBSD equivalent of that function
-+requires a unique name.
-+
-+
-+Here is a complete list of the core functions that now take a pointer to a
-+context as their first parameter:
-+
-+ dwc_read_reg32
-+ dwc_read_reg64
-+ dwc_write_reg32
-+ dwc_write_reg64
-+ dwc_modify_reg32
-+ dwc_modify_reg64
-+ dwc_alloc
-+ dwc_alloc_atomic
-+ dwc_strdup
-+ dwc_free
-+ dwc_dma_alloc
-+ dwc_dma_free
-+ dwc_mutex_alloc
-+ dwc_mutex_free
-+ dwc_spinlock_alloc
-+ dwc_spinlock_free
-+ dwc_timer_alloc
-+ dwc_waitq_alloc
-+ dwc_thread_run
-+ dwc_workq_alloc
-+ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter
-+
-+And here are the core functions that have other changes to their parameters:
-+
-+ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *'
-+ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
-+ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter
-+
-+
-+
-+The changes to the core functions also require some of the other library
-+functions to change:
-+
-+ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
-+ (for memory allocation) as the 1st param and a 'void *mtxctx'
-+ (for mutex allocation) as the 2nd param.
-+
-+ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
-+ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
-+ 'void *memctx' as the 1st param.
-+
-+ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
-+ 'void *memctx' as the 1st param.
-+
-+ dwc_modpow() now takes a 'void *memctx' as the 1st param.
-+
-+ dwc_alloc_notification_manager() now takes a 'void *memctx' as the
-+ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
-+ param, and also now returns an integer value that is non-zero if
-+ allocation of its data structures or work queue fails.
-+
-+ dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
-+
-+ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
-+ param, and also now returns an integer value that is non-zero if
-+ allocation of its data structures fails.
-+
-+
-+
-+Other miscellaneous changes:
-+
-+The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
-+DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
-+
-+The following #define's have been added to allow selectively compiling library
-+features:
-+
-+ DWC_CCLIB
-+ DWC_CRYPTOLIB
-+ DWC_NOTIFYLIB
-+ DWC_UTFLIB
-+
-+A DWC_LIBMODULE #define has also been added. If this is not defined, then the
-+module code in dwc_common_linux.c is not compiled in. This allows linking the
-+library code directly into a driver module, instead of as a standalone module.
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
---- linux-3.18.14/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,270 @@
-+# Doxyfile 1.4.5
-+
-+#---------------------------------------------------------------------------
-+# Project related configuration options
-+#---------------------------------------------------------------------------
-+PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB"
-+PROJECT_NUMBER =
-+OUTPUT_DIRECTORY = doc
-+CREATE_SUBDIRS = NO
-+OUTPUT_LANGUAGE = English
-+BRIEF_MEMBER_DESC = YES
-+REPEAT_BRIEF = YES
-+ABBREVIATE_BRIEF = "The $name class" \
-+ "The $name widget" \
-+ "The $name file" \
-+ is \
-+ provides \
-+ specifies \
-+ contains \
-+ represents \
-+ a \
-+ an \
-+ the
-+ALWAYS_DETAILED_SEC = YES
-+INLINE_INHERITED_MEMB = NO
-+FULL_PATH_NAMES = NO
-+STRIP_FROM_PATH = ..
-+STRIP_FROM_INC_PATH =
-+SHORT_NAMES = NO
-+JAVADOC_AUTOBRIEF = YES
-+MULTILINE_CPP_IS_BRIEF = NO
-+DETAILS_AT_TOP = YES
-+INHERIT_DOCS = YES
-+SEPARATE_MEMBER_PAGES = NO
-+TAB_SIZE = 8
-+ALIASES =
-+OPTIMIZE_OUTPUT_FOR_C = YES
-+OPTIMIZE_OUTPUT_JAVA = NO
-+BUILTIN_STL_SUPPORT = NO
-+DISTRIBUTE_GROUP_DOC = NO
-+SUBGROUPING = NO
-+#---------------------------------------------------------------------------
-+# Build related configuration options
-+#---------------------------------------------------------------------------
-+EXTRACT_ALL = NO
-+EXTRACT_PRIVATE = NO
-+EXTRACT_STATIC = YES
-+EXTRACT_LOCAL_CLASSES = NO
-+EXTRACT_LOCAL_METHODS = NO
-+HIDE_UNDOC_MEMBERS = NO
-+HIDE_UNDOC_CLASSES = NO
-+HIDE_FRIEND_COMPOUNDS = NO
-+HIDE_IN_BODY_DOCS = NO
-+INTERNAL_DOCS = NO
-+CASE_SENSE_NAMES = YES
-+HIDE_SCOPE_NAMES = NO
-+SHOW_INCLUDE_FILES = NO
-+INLINE_INFO = YES
-+SORT_MEMBER_DOCS = NO
-+SORT_BRIEF_DOCS = NO
-+SORT_BY_SCOPE_NAME = NO
-+GENERATE_TODOLIST = YES
-+GENERATE_TESTLIST = YES
-+GENERATE_BUGLIST = YES
-+GENERATE_DEPRECATEDLIST= YES
-+ENABLED_SECTIONS =
-+MAX_INITIALIZER_LINES = 30
-+SHOW_USED_FILES = YES
-+SHOW_DIRECTORIES = YES
-+FILE_VERSION_FILTER =
-+#---------------------------------------------------------------------------
-+# configuration options related to warning and progress messages
-+#---------------------------------------------------------------------------
-+QUIET = YES
-+WARNINGS = YES
-+WARN_IF_UNDOCUMENTED = NO
-+WARN_IF_DOC_ERROR = YES
-+WARN_NO_PARAMDOC = YES
-+WARN_FORMAT = "$file:$line: $text"
-+WARN_LOGFILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the input files
-+#---------------------------------------------------------------------------
-+INPUT = .
-+FILE_PATTERNS = *.c \
-+ *.cc \
-+ *.cxx \
-+ *.cpp \
-+ *.c++ \
-+ *.d \
-+ *.java \
-+ *.ii \
-+ *.ixx \
-+ *.ipp \
-+ *.i++ \
-+ *.inl \
-+ *.h \
-+ *.hh \
-+ *.hxx \
-+ *.hpp \
-+ *.h++ \
-+ *.idl \
-+ *.odl \
-+ *.cs \
-+ *.php \
-+ *.php3 \
-+ *.inc \
-+ *.m \
-+ *.mm \
-+ *.dox \
-+ *.py \
-+ *.C \
-+ *.CC \
-+ *.C++ \
-+ *.II \
-+ *.I++ \
-+ *.H \
-+ *.HH \
-+ *.H++ \
-+ *.CS \
-+ *.PHP \
-+ *.PHP3 \
-+ *.M \
-+ *.MM \
-+ *.PY
-+RECURSIVE = NO
-+EXCLUDE =
-+EXCLUDE_SYMLINKS = NO
-+EXCLUDE_PATTERNS =
-+EXAMPLE_PATH =
-+EXAMPLE_PATTERNS = *
-+EXAMPLE_RECURSIVE = NO
-+IMAGE_PATH =
-+INPUT_FILTER =
-+FILTER_PATTERNS =
-+FILTER_SOURCE_FILES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to source browsing
-+#---------------------------------------------------------------------------
-+SOURCE_BROWSER = NO
-+INLINE_SOURCES = NO
-+STRIP_CODE_COMMENTS = YES
-+REFERENCED_BY_RELATION = YES
-+REFERENCES_RELATION = YES
-+USE_HTAGS = NO
-+VERBATIM_HEADERS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the alphabetical class index
-+#---------------------------------------------------------------------------
-+ALPHABETICAL_INDEX = NO
-+COLS_IN_ALPHA_INDEX = 5
-+IGNORE_PREFIX =
-+#---------------------------------------------------------------------------
-+# configuration options related to the HTML output
-+#---------------------------------------------------------------------------
-+GENERATE_HTML = YES
-+HTML_OUTPUT = html
-+HTML_FILE_EXTENSION = .html
-+HTML_HEADER =
-+HTML_FOOTER =
-+HTML_STYLESHEET =
-+HTML_ALIGN_MEMBERS = YES
-+GENERATE_HTMLHELP = NO
-+CHM_FILE =
-+HHC_LOCATION =
-+GENERATE_CHI = NO
-+BINARY_TOC = NO
-+TOC_EXPAND = NO
-+DISABLE_INDEX = NO
-+ENUM_VALUES_PER_LINE = 4
-+GENERATE_TREEVIEW = YES
-+TREEVIEW_WIDTH = 250
-+#---------------------------------------------------------------------------
-+# configuration options related to the LaTeX output
-+#---------------------------------------------------------------------------
-+GENERATE_LATEX = NO
-+LATEX_OUTPUT = latex
-+LATEX_CMD_NAME = latex
-+MAKEINDEX_CMD_NAME = makeindex
-+COMPACT_LATEX = NO
-+PAPER_TYPE = a4wide
-+EXTRA_PACKAGES =
-+LATEX_HEADER =
-+PDF_HYPERLINKS = NO
-+USE_PDFLATEX = NO
-+LATEX_BATCHMODE = NO
-+LATEX_HIDE_INDICES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the RTF output
-+#---------------------------------------------------------------------------
-+GENERATE_RTF = NO
-+RTF_OUTPUT = rtf
-+COMPACT_RTF = NO
-+RTF_HYPERLINKS = NO
-+RTF_STYLESHEET_FILE =
-+RTF_EXTENSIONS_FILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the man page output
-+#---------------------------------------------------------------------------
-+GENERATE_MAN = NO
-+MAN_OUTPUT = man
-+MAN_EXTENSION = .3
-+MAN_LINKS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the XML output
-+#---------------------------------------------------------------------------
-+GENERATE_XML = NO
-+XML_OUTPUT = xml
-+XML_SCHEMA =
-+XML_DTD =
-+XML_PROGRAMLISTING = YES
-+#---------------------------------------------------------------------------
-+# configuration options for the AutoGen Definitions output
-+#---------------------------------------------------------------------------
-+GENERATE_AUTOGEN_DEF = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the Perl module output
-+#---------------------------------------------------------------------------
-+GENERATE_PERLMOD = NO
-+PERLMOD_LATEX = NO
-+PERLMOD_PRETTY = YES
-+PERLMOD_MAKEVAR_PREFIX =
-+#---------------------------------------------------------------------------
-+# Configuration options related to the preprocessor
-+#---------------------------------------------------------------------------
-+ENABLE_PREPROCESSING = YES
-+MACRO_EXPANSION = NO
-+EXPAND_ONLY_PREDEF = NO
-+SEARCH_INCLUDES = YES
-+INCLUDE_PATH =
-+INCLUDE_FILE_PATTERNS =
-+PREDEFINED = DEBUG DEBUG_MEMORY
-+EXPAND_AS_DEFINED =
-+SKIP_FUNCTION_MACROS = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to external references
-+#---------------------------------------------------------------------------
-+TAGFILES =
-+GENERATE_TAGFILE =
-+ALLEXTERNALS = NO
-+EXTERNAL_GROUPS = YES
-+PERL_PATH = /usr/bin/perl
-+#---------------------------------------------------------------------------
-+# Configuration options related to the dot tool
-+#---------------------------------------------------------------------------
-+CLASS_DIAGRAMS = YES
-+HIDE_UNDOC_RELATIONS = YES
-+HAVE_DOT = NO
-+CLASS_GRAPH = YES
-+COLLABORATION_GRAPH = YES
-+GROUP_GRAPHS = YES
-+UML_LOOK = NO
-+TEMPLATE_RELATIONS = NO
-+INCLUDE_GRAPH = NO
-+INCLUDED_BY_GRAPH = YES
-+CALL_GRAPH = NO
-+GRAPHICAL_HIERARCHY = YES
-+DIRECTORY_GRAPH = YES
-+DOT_IMAGE_FORMAT = png
-+DOT_PATH =
-+DOTFILE_DIRS =
-+MAX_DOT_GRAPH_DEPTH = 1000
-+DOT_TRANSPARENT = NO
-+DOT_MULTI_TARGETS = NO
-+GENERATE_LEGEND = YES
-+DOT_CLEANUP = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to the search engine
-+#---------------------------------------------------------------------------
-+SEARCHENGINE = NO
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_cc.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_cc.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,532 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
-+ * $Revision: #4 $
-+ * $Date: 2010/11/04 $
-+ * $Change: 1621692 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifdef DWC_CCLIB
-+
-+#include "dwc_cc.h"
-+
-+typedef struct dwc_cc
-+{
-+ uint32_t uid;
-+ uint8_t chid[16];
-+ uint8_t cdid[16];
-+ uint8_t ck[16];
-+ uint8_t *name;
-+ uint8_t length;
-+ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
-+} dwc_cc_t;
-+
-+DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
-+
-+/** The main structure for CC management. */
-+struct dwc_cc_if
-+{
-+ dwc_mutex_t *mutex;
-+ char *filename;
-+
-+ unsigned is_host:1;
-+
-+ dwc_notifier_t *notifier;
-+
-+ struct context_list list;
-+};
-+
-+#ifdef DEBUG
-+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
-+{
-+ int i;
-+ DWC_PRINTF("%s: ", name);
-+ for (i=0; i<len; i++) {
-+ DWC_PRINTF("%02x ", bytes[i]);
-+ }
-+ DWC_PRINTF("\n");
-+}
-+#else
-+#define dump_bytes(x...)
-+#endif
-+
-+static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
-+{
-+ dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
-+ if (!cc) {
-+ return NULL;
-+ }
-+ DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
-+
-+ if (name) {
-+ cc->length = length;
-+ cc->name = dwc_alloc(mem_ctx, length);
-+ if (!cc->name) {
-+ dwc_free(mem_ctx, cc);
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(cc->name, name, length);
-+ }
-+
-+ return cc;
-+}
-+
-+static void free_cc(void *mem_ctx, dwc_cc_t *cc)
-+{
-+ if (cc->name) {
-+ dwc_free(mem_ctx, cc->name);
-+ }
-+ dwc_free(mem_ctx, cc);
-+}
-+
-+static uint32_t next_uid(dwc_cc_if_t *cc_if)
-+{
-+ uint32_t uid = 0;
-+ dwc_cc_t *cc;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (cc->uid > uid) {
-+ uid = cc->uid;
-+ }
-+ }
-+
-+ if (uid == 0) {
-+ uid = 255;
-+ }
-+
-+ return uid + 1;
-+}
-+
-+static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
-+{
-+ dwc_cc_t *cc;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (cc->uid == uid) {
-+ return cc;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
-+{
-+ unsigned int size = 0;
-+ dwc_cc_t *cc;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ size += (48 + 1);
-+ if (cc->name) {
-+ size += cc->length;
-+ }
-+ }
-+ return size;
-+}
-+
-+static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
-+{
-+ uint32_t uid = 0;
-+ dwc_cc_t *cc;
-+
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
-+ uid = cc->uid;
-+ break;
-+ }
-+ }
-+ return uid;
-+}
-+static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
-+{
-+ uint32_t uid = 0;
-+ dwc_cc_t *cc;
-+
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
-+ uid = cc->uid;
-+ break;
-+ }
-+ }
-+ return uid;
-+}
-+
-+/* Internal cc_add */
-+static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+ dwc_cc_t *cc;
-+ uint32_t uid;
-+
-+ if (cc_if->is_host) {
-+ uid = cc_match_cdid(cc_if, cdid);
-+ }
-+ else {
-+ uid = cc_match_chid(cc_if, chid);
-+ }
-+
-+ if (uid) {
-+ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
-+ cc = cc_find(cc_if, uid);
-+ }
-+ else {
-+ cc = alloc_cc(mem_ctx, name, length);
-+ cc->uid = next_uid(cc_if);
-+ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
-+ }
-+
-+ DWC_MEMCPY(&(cc->chid[0]), chid, 16);
-+ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
-+ DWC_MEMCPY(&(cc->ck[0]), ck, 16);
-+
-+ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
-+ dump_bytes("CHID", cc->chid, 16);
-+ dump_bytes("CDID", cc->cdid, 16);
-+ dump_bytes("CK", cc->ck, 16);
-+ return cc->uid;
-+}
-+
-+/* Internal cc_clear */
-+static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
-+{
-+ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
-+ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
-+ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
-+ free_cc(mem_ctx, cc);
-+ }
-+}
-+
-+dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
-+ dwc_notifier_t *notifier, unsigned is_host)
-+{
-+ dwc_cc_if_t *cc_if = NULL;
-+
-+ /* Allocate a common_cc_if structure */
-+ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
-+
-+ if (!cc_if)
-+ return NULL;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
-+#else
-+ cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
-+#endif
-+ if (!cc_if->mutex) {
-+ dwc_free(mem_ctx, cc_if);
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&cc_if->list);
-+ cc_if->is_host = is_host;
-+ cc_if->notifier = notifier;
-+ return cc_if;
-+}
-+
-+void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
-+{
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+ DWC_MUTEX_FREE(cc_if->mutex);
-+#else
-+ dwc_mutex_free(mtx_ctx, cc_if->mutex);
-+#endif
-+ cc_clear(mem_ctx, cc_if);
-+ dwc_free(mem_ctx, cc_if);
-+}
-+
-+static void cc_changed(dwc_cc_if_t *cc_if)
-+{
-+ if (cc_if->notifier) {
-+ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
-+ }
-+}
-+
-+void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
-+{
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc_clear(mem_ctx, cc_if);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ cc_changed(cc_if);
-+}
-+
-+int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+ uint32_t uid;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ cc_changed(cc_if);
-+
-+ return uid;
-+}
-+
-+void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+ dwc_cc_t* cc;
-+
-+ DWC_DEBUGC("Change connection context %d", id);
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (!cc) {
-+ DWC_ERROR("Uid %d not found in cc list\n", id);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return;
-+ }
-+
-+ if (chid) {
-+ DWC_MEMCPY(&(cc->chid[0]), chid, 16);
-+ }
-+ if (cdid) {
-+ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
-+ }
-+ if (ck) {
-+ DWC_MEMCPY(&(cc->ck[0]), ck, 16);
-+ }
-+
-+ if (name) {
-+ if (cc->name) {
-+ dwc_free(mem_ctx, cc->name);
-+ }
-+ cc->name = dwc_alloc(mem_ctx, length);
-+ if (!cc->name) {
-+ DWC_ERROR("Out of memory in dwc_cc_change()\n");
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return;
-+ }
-+ cc->length = length;
-+ DWC_MEMCPY(cc->name, name, length);
-+ }
-+
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ cc_changed(cc_if);
-+
-+ DWC_DEBUGC("Changed connection context id=%d\n", id);
-+ dump_bytes("New CHID", cc->chid, 16);
-+ dump_bytes("New CDID", cc->cdid, 16);
-+ dump_bytes("New CK", cc->ck, 16);
-+}
-+
-+void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ dwc_cc_t *cc;
-+
-+ DWC_DEBUGC("Removing connection context %d", id);
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (!cc) {
-+ DWC_ERROR("Uid %d not found in cc list\n", id);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ free_cc(mem_ctx, cc);
-+
-+ cc_changed(cc_if);
-+}
-+
-+uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
-+{
-+ uint8_t *buf, *x;
-+ uint8_t zero = 0;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ *length = cc_data_size(cc_if);
-+ if (!(*length)) {
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return NULL;
-+ }
-+
-+ DWC_DEBUGC("Creating data for saving (length=%d)", *length);
-+
-+ buf = dwc_alloc(mem_ctx, *length);
-+ if (!buf) {
-+ *length = 0;
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return NULL;
-+ }
-+
-+ x = buf;
-+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+ DWC_MEMCPY(x, cc->chid, 16);
-+ x += 16;
-+ DWC_MEMCPY(x, cc->cdid, 16);
-+ x += 16;
-+ DWC_MEMCPY(x, cc->ck, 16);
-+ x += 16;
-+ if (cc->name) {
-+ DWC_MEMCPY(x, &cc->length, 1);
-+ x += 1;
-+ DWC_MEMCPY(x, cc->name, cc->length);
-+ x += cc->length;
-+ }
-+ else {
-+ DWC_MEMCPY(x, &zero, 1);
-+ x += 1;
-+ }
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return buf;
-+}
-+
-+void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
-+{
-+ uint8_t name_length;
-+ uint8_t *name;
-+ uint8_t *chid;
-+ uint8_t *cdid;
-+ uint8_t *ck;
-+ uint32_t i = 0;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc_clear(mem_ctx, cc_if);
-+
-+ while (i < length) {
-+ chid = &data[i];
-+ i += 16;
-+ cdid = &data[i];
-+ i += 16;
-+ ck = &data[i];
-+ i += 16;
-+
-+ name_length = data[i];
-+ i ++;
-+
-+ if (name_length) {
-+ name = &data[i];
-+ i += name_length;
-+ }
-+ else {
-+ name = NULL;
-+ }
-+
-+ /* check to see if we haven't overflown the buffer */
-+ if (i > length) {
-+ DWC_ERROR("Data format error while attempting to load CCs "
-+ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
-+ break;
-+ }
-+
-+ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ cc_changed(cc_if);
-+}
-+
-+uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
-+{
-+ uint32_t uid = 0;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ uid = cc_match_chid(cc_if, chid);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return uid;
-+}
-+uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
-+{
-+ uint32_t uid = 0;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ uid = cc_match_cdid(cc_if, cdid);
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+ return uid;
-+}
-+
-+uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ uint8_t *ck = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ ck = cc->ck;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return ck;
-+
-+}
-+
-+uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ uint8_t *retval = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ retval = cc->chid;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return retval;
-+}
-+
-+uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+ uint8_t *retval = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ retval = cc->cdid;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return retval;
-+}
-+
-+uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
-+{
-+ uint8_t *retval = NULL;
-+ dwc_cc_t *cc;
-+
-+ DWC_MUTEX_LOCK(cc_if->mutex);
-+ *length = 0;
-+ cc = cc_find(cc_if, id);
-+ if (cc) {
-+ *length = cc->length;
-+ retval = cc->name;
-+ }
-+ DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+ return retval;
-+}
-+
-+#endif /* DWC_CCLIB */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_cc.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_cc.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,224 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
-+ * $Revision: #4 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_CC_H_
-+#define _DWC_CC_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file defines the Context Context library.
-+ *
-+ * The main data structure is dwc_cc_if_t which is returned by either the
-+ * dwc_cc_if_alloc function or returned by the module to the user via a provided
-+ * function. The data structure is opaque and should only be manipulated via the
-+ * functions provied in this API.
-+ *
-+ * It manages a list of connection contexts and operations can be performed to
-+ * add, remove, query, search, and change, those contexts. Additionally,
-+ * a dwc_notifier_t object can be requested from the manager so that
-+ * the user can be notified whenever the context list has changed.
-+ */
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+#include "dwc_notifier.h"
-+
-+
-+/* Notifications */
-+#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
-+
-+struct dwc_cc_if;
-+typedef struct dwc_cc_if dwc_cc_if_t;
-+
-+
-+/** @name Connection Context Operations */
-+/** @{ */
-+
-+/** This function allocates memory for a dwc_cc_if_t structure, initializes
-+ * fields to default values, and returns a pointer to the structure or NULL on
-+ * error. */
-+extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
-+ dwc_notifier_t *notifier, unsigned is_host);
-+
-+/** Frees the memory for the specified CC structure allocated from
-+ * dwc_cc_if_alloc(). */
-+extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
-+
-+/** Removes all contexts from the connection context list */
-+extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
-+
-+/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
-+ * If a CHID already exists, the CK and name are overwritten. Statistics are
-+ * not overwritten.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param chid A pointer to the 16-byte CHID. This value will be copied.
-+ * @param ck A pointer to the 16-byte CK. This value will be copied.
-+ * @param cdid A pointer to the 16-byte CDID. This value will be copied.
-+ * @param name An optional host friendly name as defined in the association model
-+ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
-+ * @param length The length othe unicode string.
-+ * @return A unique identifier used to refer to this context that is valid for
-+ * as long as this context is still in the list. */
-+extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+ uint8_t *cdid, uint8_t *ck, uint8_t *name,
-+ uint8_t length);
-+
-+/** Changes the CHID, CK, CDID, or Name values of a connection context in the
-+ * list, preserving any accumulated statistics. This would typically be called
-+ * if the host decideds to change the context with a SET_CONNECTION request.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL
-+ * indicates no change.
-+ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL
-+ * indicates no change.
-+ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL
-+ * indicates no change.
-+ * @param name Host friendly name UTF16-LE. NULL indicates no change.
-+ * @param length Length of name. */
-+extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
-+ uint8_t *chid, uint8_t *cdid, uint8_t *ck,
-+ uint8_t *name, uint8_t length);
-+
-+/** Remove the specified connection context.
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context to remove. */
-+extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Get a binary block of data for the connection context list and attributes.
-+ * This data can be used by the OS specific driver to save the connection
-+ * context list into non-volatile memory.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param length Return the length of the data buffer.
-+ * @return A pointer to the data buffer. The memory for this buffer should be
-+ * freed with DWC_FREE() after use. */
-+extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
-+ unsigned int *length);
-+
-+/** Restore the connection context list from the binary data that was previously
-+ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific
-+ * driver to load a connection context list from non-volatile memory.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param data The data bytes as returned from dwc_cc_data_for_save.
-+ * @param length The length of the data. */
-+extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
-+ uint8_t *data, unsigned int length);
-+
-+/** Find the connection context from the specified CHID.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param chid A pointer to the CHID data.
-+ * @return A non-zero identifier of the connection context if the CHID matches.
-+ * Otherwise returns 0. */
-+extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
-+
-+/** Find the connection context from the specified CDID.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param cdid A pointer to the CDID data.
-+ * @return A non-zero identifier of the connection context if the CHID matches.
-+ * Otherwise returns 0. */
-+extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
-+
-+/** Retrieve the CK from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CK data. The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Retrieve the CHID from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CHID data. The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Retrieve the CDID from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CDID data. The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
-+
-+extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
-+
-+/** Checks a buffer for non-zero.
-+ * @param id A pointer to a 16 byte buffer.
-+ * @return true if the 16 byte value is non-zero. */
-+static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
-+ int i;
-+ for (i=0; i<16; i++) {
-+ if (id[i]) return 1;
-+ }
-+ return 0;
-+}
-+
-+/** Checks a buffer for zero.
-+ * @param id A pointer to a 16 byte buffer.
-+ * @return true if the 16 byte value is zero. */
-+static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
-+ return !dwc_assoc_is_not_zero_id(id);
-+}
-+
-+/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
-+ * buffer. */
-+static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
-+ char *ptr = buffer;
-+ int i;
-+ for (i=0; i<16; i++) {
-+ ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
-+ if (i < 15) {
-+ ptr += DWC_SPRINTF(ptr, " ");
-+ }
-+ }
-+ return ptr - buffer;
-+}
-+
-+/** @} */
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_CC_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,1308 @@
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+ return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+ return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+ bcopy(src, dest, size);
-+ return dest;
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+ return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+ return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+ return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+ return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+ return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+ int len = DWC_STRLEN(str) + 1;
-+ char *new = DWC_ALLOC_ATOMIC(len);
-+
-+ if (!new) {
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(new, str, len);
-+ return new;
-+}
-+
-+int DWC_ATOI(char *str, int32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = strtol(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+int DWC_ATOUI(char *str, uint32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+#endif /* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+// return in_irq();
-+ return 0;
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+// return in_softirq();
-+ return 0;
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+ vprintf(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+ return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsprintf(buffer, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsnprintf(buffer, size, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+// BUG_ON(1); ???
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+ uint32_t align,
-+ uint32_t alloc)
-+{
-+ struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+ size, align, alloc);
-+ return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+ dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+ memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+ dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
-+{
-+ if (error)
-+ return;
-+ *(bus_addr_t *)arg = segs[0].ds_addr;
-+}
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+ int error;
-+
-+ error = bus_dma_tag_create(
-+#if __FreeBSD_version >= 700000
-+ bus_get_dma_tag(dma->dev), /* parent */
-+#else
-+ NULL, /* parent */
-+#endif
-+ 4, 0, /* alignment, bounds */
-+ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
-+ BUS_SPACE_MAXADDR, /* highaddr */
-+ NULL, NULL, /* filter, filterarg */
-+ size, /* maxsize */
-+ 1, /* nsegments */
-+ size, /* maxsegsize */
-+ 0, /* flags */
-+ NULL, /* lockfunc */
-+ NULL, /* lockarg */
-+ &dma->dma_tag);
-+ if (error) {
-+ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
-+ __func__, error);
-+ goto fail_0;
-+ }
-+
-+ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
-+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
-+ if (error) {
-+ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
-+ __func__, (uintmax_t)size, error);
-+ goto fail_1;
-+ }
-+
-+ dma->dma_paddr = 0;
-+ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
-+ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
-+ if (error || dma->dma_paddr == 0) {
-+ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
-+ __func__, error);
-+ goto fail_2;
-+ }
-+
-+ *dma_addr = dma->dma_paddr;
-+ return dma->dma_vaddr;
-+
-+fail_2:
-+ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+fail_1:
-+ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
-+ bus_dma_tag_destroy(dma->dma_tag);
-+fail_0:
-+ dma->dma_map = NULL;
-+ dma->dma_tag = NULL;
-+
-+ return NULL;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+
-+ if (dma->dma_tag == NULL)
-+ return;
-+ if (dma->dma_map != NULL) {
-+ bus_dmamap_sync(dma->dma_tag, dma->dma_map,
-+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-+ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
-+ dma->dma_map = NULL;
-+ }
-+
-+ bus_dma_tag_destroy(dma->dma_tag);
-+ dma->dma_tag = NULL;
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+ free(addr, M_DEVBUF);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+ get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+ struct crypto_blkcipher *tfm;
-+ struct blkcipher_desc desc;
-+ struct scatterlist sgd;
-+ struct scatterlist sgs;
-+
-+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+ if (tfm == NULL) {
-+ printk("failed to load transform for aes CBC\n");
-+ return -1;
-+ }
-+
-+ crypto_blkcipher_setkey(tfm, key, keylen);
-+ crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+ sg_init_one(&sgd, out, messagelen);
-+ sg_init_one(&sgs, message, messagelen);
-+
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+ crypto_free_blkcipher(tfm);
-+ DWC_ERROR("AES CBC encryption failed");
-+ return -1;
-+ }
-+
-+ crypto_free_blkcipher(tfm);
-+ return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, len);
-+ crypto_hash_digest(&desc, &sg, len, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, messagelen);
-+ crypto_hash_setkey(tfm, key, keylen);
-+ crypto_hash_digest(&desc, &sg, messagelen, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_4(io->iot, io->ioh, ior);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_8(io->iot, io->ioh, ior);
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior, value);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior, value);
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
-+ uint32_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior,
-+ (bus_space_read_4(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
-+ uint64_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior,
-+ (bus_space_read_8(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+ struct mtx *sl = DWC_ALLOC(sizeof(*sl));
-+
-+ if (!sl) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ return NULL;
-+ }
-+
-+ mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
-+ return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+ struct mtx *sl = (struct mtx *)lock;
-+
-+ mtx_destroy(sl);
-+ DWC_FREE(sl);
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+ mtx_lock_spin((struct mtx *)lock); // ???
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+ mtx_unlock_spin((struct mtx *)lock); // ???
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+ mtx_lock_spin((struct mtx *)lock);
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+ mtx_unlock_spin((struct mtx *)lock);
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+ struct mtx *m;
-+ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
-+
-+ if (!mutex) {
-+ DWC_ERROR("Cannot allocate memory for mutex");
-+ return NULL;
-+ }
-+
-+ m = (struct mtx *)mutex;
-+ mtx_init(m, "dw3mtx", NULL, MTX_DEF);
-+ return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+ mtx_destroy((struct mtx *)mutex);
-+ DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+ struct mtx *m = (struct mtx *)mutex;
-+
-+ mtx_lock(m);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mtx *m = (struct mtx *)mutex;
-+
-+ return mtx_trylock(m);
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mtx *m = (struct mtx *)mutex;
-+
-+ mtx_unlock(m);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+ DELAY(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+ do {
-+ DELAY(1000);
-+ } while (--msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+ pause("dw3slp", tvtohz(&tv));
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+ struct timeval tv;
-+
-+ microuptime(&tv); // or getmicrouptime? (less precise, but faster)
-+ return tv.tv_sec * 1000 + tv.tv_usec / 1000;
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+ struct callout t;
-+ char *name;
-+ dwc_spinlock_t *lock;
-+ dwc_timer_callback_t cb;
-+ void *data;
-+};
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (!t) {
-+ DWC_ERROR("Cannot allocate memory for timer");
-+ return NULL;
-+ }
-+
-+ callout_init(&t->t, 1);
-+
-+ t->name = DWC_STRDUP(name);
-+ if (!t->name) {
-+ DWC_ERROR("Cannot allocate memory for timer->name");
-+ goto no_name;
-+ }
-+
-+ t->lock = DWC_SPINLOCK_ALLOC();
-+ if (!t->lock) {
-+ DWC_ERROR("Cannot allocate memory for lock");
-+ goto no_lock;
-+ }
-+
-+ t->cb = cb;
-+ t->data = data;
-+
-+ return t;
-+
-+ no_lock:
-+ DWC_FREE(t->name);
-+ no_name:
-+ DWC_FREE(t);
-+
-+ return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+ DWC_SPINLOCK_FREE(timer->lock);
-+ DWC_FREE(timer->name);
-+ DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+ struct mtx lock;
-+ int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ return NULL;
-+ }
-+
-+ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
-+ wq->abort = 0;
-+
-+ return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+ mtx_destroy(&wq->lock);
-+ DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+// intrmask_t ipl;
-+ int result = 0;
-+
-+ mtx_lock(&wq->lock);
-+// ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+// splx(ipl);
-+ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
-+// ipl = splbio();
-+ }
-+
-+ if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+
-+ } else if (result == EINTR) { // signaled - interrupt
-+ result = -DWC_E_ABORT;
-+
-+ } else if (wq->abort) {
-+ result = -DWC_E_ABORT;
-+
-+ } else {
-+ result = 0;
-+ }
-+
-+ wq->abort = 0;
-+// splx(ipl);
-+ mtx_unlock(&wq->lock);
-+ return result;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs)
-+{
-+ struct timeval tv, tv1, tv2;
-+// intrmask_t ipl;
-+ int result = 0;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+
-+ mtx_lock(&wq->lock);
-+// ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+// splx(ipl);
-+ getmicrouptime(&tv1);
-+ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
-+ getmicrouptime(&tv2);
-+// ipl = splbio();
-+ }
-+
-+ if (result == 0) { // awoken
-+ if (wq->abort) {
-+ result = -DWC_E_ABORT;
-+ } else {
-+ tv2.tv_usec -= tv1.tv_usec;
-+ if (tv2.tv_usec < 0) {
-+ tv2.tv_usec += 1000000;
-+ tv2.tv_sec--;
-+ }
-+
-+ tv2.tv_sec -= tv1.tv_sec;
-+ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
-+ result = msecs - result;
-+ if (result <= 0)
-+ result = 1;
-+ }
-+ } else if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+
-+ } else if (result == EINTR) { // signaled - interrupt
-+ result = -DWC_E_ABORT;
-+
-+ } else { // timed out
-+ result = -DWC_E_TIMEOUT;
-+ }
-+
-+ wq->abort = 0;
-+// splx(ipl);
-+ mtx_unlock(&wq->lock);
-+ return result;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+ wakeup(wq);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+// intrmask_t ipl;
-+
-+ mtx_lock(&wq->lock);
-+// ipl = splbio();
-+ wq->abort = 1;
-+ wakeup(wq);
-+// splx(ipl);
-+ mtx_unlock(&wq->lock);
-+}
-+
-+
-+/* Threading */
-+
-+struct dwc_thread {
-+ struct proc *proc;
-+ int abort;
-+};
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+ int retval;
-+ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
-+
-+ if (!thread) {
-+ return NULL;
-+ }
-+
-+ thread->abort = 0;
-+ retval = kthread_create((void (*)(void *))func, data, &thread->proc,
-+ RFPROC | RFNOWAIT, 0, "%s", name);
-+ if (retval) {
-+ DWC_FREE(thread);
-+ return NULL;
-+ }
-+
-+ return thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+ int retval;
-+
-+ thread->abort = 1;
-+ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
-+
-+ if (retval == 0) {
-+ /* DWC_THREAD_EXIT() will free the thread struct */
-+ return 0;
-+ }
-+
-+ /* NOTE: We leak the thread struct if thread doesn't die */
-+
-+ if (retval == EWOULDBLOCK) {
-+ return -DWC_E_TIMEOUT;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
-+{
-+ return thread->abort;
-+}
-+
-+void DWC_THREAD_EXIT(dwc_thread_t *thread)
-+{
-+ wakeup(&thread->abort);
-+ DWC_FREE(thread);
-+ kthread_exit(0);
-+}
-+
-+
-+/* tasklets
-+ - Runs in interrupt context (cannot sleep)
-+ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
-+ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
-+ */
-+struct dwc_tasklet {
-+ struct task t;
-+ dwc_tasklet_callback_t cb;
-+ void *data;
-+};
-+
-+static void tasklet_callback(void *data, int pending) // what to do with pending ???
-+{
-+ dwc_tasklet_t *task = (dwc_tasklet_t *)data;
-+
-+ task->cb(task->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
-+
-+ if (task) {
-+ task->cb = cb;
-+ task->data = data;
-+ TASK_INIT(&task->t, 0, tasklet_callback, task);
-+ } else {
-+ DWC_ERROR("Cannot allocate memory for tasklet");
-+ }
-+
-+ return task;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+ taskqueue_drain(taskqueue_fast, &task->t); // ???
-+ DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ /* Uses predefined system queue */
-+ taskqueue_enqueue_fast(taskqueue_fast, &task->t);
-+}
-+
-+
-+/* workqueues
-+ - Runs in process context (can sleep)
-+ */
-+typedef struct work_container {
-+ dwc_work_callback_t cb;
-+ void *data;
-+ dwc_workq_t *wq;
-+ char *name;
-+ int hz;
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_ENTRY(work_container) entry;
-+#endif
-+ struct task task;
-+} work_container_t;
-+
-+#ifdef DEBUG
-+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
-+#endif
-+
-+struct dwc_workq {
-+ struct taskqueue *taskq;
-+ dwc_spinlock_t *lock;
-+ dwc_waitq_t *waitq;
-+ int pending;
-+
-+#ifdef DEBUG
-+ struct work_container_queue entries;
-+#endif
-+};
-+
-+static void do_work(void *data, int pending) // what to do with pending ???
-+{
-+ work_container_t *container = (work_container_t *)data;
-+ dwc_workq_t *wq = container->wq;
-+ dwc_irqflags_t flags;
-+
-+ if (container->hz) {
-+ pause("dw3wrk", container->hz);
-+ }
-+
-+ container->cb(container->data);
-+ DWC_DEBUG("Work done: %s, container=%p", container->name, container);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
-+#endif
-+ if (container->name)
-+ DWC_FREE(container->name);
-+ DWC_FREE(container);
-+ wq->pending--;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+ dwc_workq_t *workq = (dwc_workq_t *)data;
-+
-+ return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for workqueue");
-+ return NULL;
-+ }
-+
-+ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
-+ if (!wq->taskq) {
-+ DWC_ERROR("Cannot allocate memory for taskqueue");
-+ goto no_taskq;
-+ }
-+
-+ wq->pending = 0;
-+
-+ wq->lock = DWC_SPINLOCK_ALLOC();
-+ if (!wq->lock) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ goto no_lock;
-+ }
-+
-+ wq->waitq = DWC_WAITQ_ALLOC();
-+ if (!wq->waitq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ goto no_waitq;
-+ }
-+
-+ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INIT(&wq->entries);
-+#endif
-+ return wq;
-+
-+ no_waitq:
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+ taskqueue_free(wq->taskq);
-+ no_taskq:
-+ DWC_FREE(wq);
-+
-+ return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+ if (wq->pending != 0) {
-+ struct work_container *container;
-+
-+ DWC_ERROR("Destroying work queue with pending work");
-+
-+ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
-+ DWC_ERROR("Work %s still pending", container->name);
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+#endif
-+ DWC_WAITQ_FREE(wq->waitq);
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ taskqueue_free(wq->taskq);
-+ DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+ char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ container->hz = 0;
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+
-+ TASK_INIT(&container->task, 0, do_work, container);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ taskqueue_enqueue_fast(wq->taskq, &container->task);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ struct timeval tv;
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ container->hz = tvtohz(&tv);
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+
-+ TASK_INIT(&container->task, 0, do_work, container);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ taskqueue_enqueue_fast(wq->taskq, &container->task);
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+ return wq->pending;
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_common_linux.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_common_linux.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,1434 @@
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kthread.h>
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the Linux kernel implementation of the DWC platform library. */
-+#include <linux/moduleparam.h>
-+#include <linux/ctype.h>
-+#include <linux/crypto.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/cdev.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/jiffies.h>
-+#include <linux/list.h>
-+#include <linux/pci.h>
-+#include <linux/random.h>
-+#include <linux/scatterlist.h>
-+#include <linux/slab.h>
-+#include <linux/stat.h>
-+#include <linux/string.h>
-+#include <linux/timer.h>
-+#include <linux/usb.h>
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+# include <linux/usb/gadget.h>
-+#else
-+# include <linux/usb_gadget.h>
-+#endif
-+
-+#include <asm/io.h>
-+#include <asm/page.h>
-+#include <asm/uaccess.h>
-+#include <asm/unaligned.h>
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+ return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+ return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+ return memmove(dest, src, size);
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+ return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+ return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+ return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+ return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+ return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+ int len = DWC_STRLEN(str) + 1;
-+ char *new = DWC_ALLOC_ATOMIC(len);
-+
-+ if (!new) {
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(new, str, len);
-+ return new;
-+}
-+
-+int DWC_ATOI(const char *str, int32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = simple_strtol(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+int DWC_ATOUI(const char *str, uint32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = simple_strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+#endif /* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+ return in_irq();
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+ return in_softirq();
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+ vprintk(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+ return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsprintf(buffer, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsnprintf(buffer, size, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_WARNING);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_ERR);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_ERR);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+ BUG_ON(1);
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_PRINTF(KERN_DEBUG);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+ uint32_t align,
-+ uint32_t alloc)
-+{
-+ struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+ size, align, alloc);
-+ return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+ dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+ memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+ dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+#ifdef xxCOSIM /* Only works for 32-bit cosim */
-+ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL);
-+#else
-+ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32);
-+#endif
-+ if (!buf) {
-+ return NULL;
-+ }
-+
-+ memset(buf, 0, (size_t)size);
-+ return buf;
-+}
-+
-+void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
-+ if (!buf) {
-+ return NULL;
-+ }
-+ memset(buf, 0, (size_t)size);
-+ return buf;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+ return kzalloc(size, GFP_KERNEL);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+ return kzalloc(size, GFP_ATOMIC);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+ kfree(addr);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+ get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+ struct crypto_blkcipher *tfm;
-+ struct blkcipher_desc desc;
-+ struct scatterlist sgd;
-+ struct scatterlist sgs;
-+
-+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+ if (tfm == NULL) {
-+ printk("failed to load transform for aes CBC\n");
-+ return -1;
-+ }
-+
-+ crypto_blkcipher_setkey(tfm, key, keylen);
-+ crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+ sg_init_one(&sgd, out, messagelen);
-+ sg_init_one(&sgs, message, messagelen);
-+
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+ crypto_free_blkcipher(tfm);
-+ DWC_ERROR("AES CBC encryption failed");
-+ return -1;
-+ }
-+
-+ crypto_free_blkcipher(tfm);
-+ return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, len);
-+ crypto_hash_digest(&desc, &sg, len, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, messagelen);
-+ crypto_hash_setkey(tfm, key, keylen);
-+ crypto_hash_digest(&desc, &sg, messagelen, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(uint32_t volatile *reg)
-+{
-+ return readl(reg);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(uint64_t volatile *reg)
-+{
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
-+{
-+ writel(value, reg);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
-+{
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
-+{
-+ writel((readl(reg) & ~clear_mask) | set_mask, reg);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
-+{
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+ spinlock_t *sl = (spinlock_t *)1;
-+
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ sl = DWC_ALLOC(sizeof(*sl));
-+ if (!sl) {
-+ DWC_ERROR("Cannot allocate memory for spinlock\n");
-+ return NULL;
-+ }
-+
-+ spin_lock_init(sl);
-+#endif
-+ return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ DWC_FREE(lock);
-+#endif
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_lock((spinlock_t *)lock);
-+#endif
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_unlock((spinlock_t *)lock);
-+#endif
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+ dwc_irqflags_t f;
-+
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_lock_irqsave((spinlock_t *)lock, f);
-+#else
-+ local_irq_save(f);
-+#endif
-+ *flags = f;
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+ spin_unlock_irqrestore((spinlock_t *)lock, flags);
-+#else
-+ local_irq_restore(flags);
-+#endif
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+ struct mutex *m;
-+ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
-+
-+ if (!mutex) {
-+ DWC_ERROR("Cannot allocate memory for mutex\n");
-+ return NULL;
-+ }
-+
-+ m = (struct mutex *)mutex;
-+ mutex_init(m);
-+ return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+ mutex_destroy((struct mutex *)mutex);
-+ DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+ struct mutex *m = (struct mutex *)mutex;
-+ mutex_lock(m);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mutex *m = (struct mutex *)mutex;
-+ return mutex_trylock(m);
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+ struct mutex *m = (struct mutex *)mutex;
-+ mutex_unlock(m);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+ udelay(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+ mdelay(msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+ msleep(msecs);
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+ return jiffies_to_msecs(jiffies);
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+ struct timer_list *t;
-+ char *name;
-+ dwc_timer_callback_t cb;
-+ void *data;
-+ uint8_t scheduled;
-+ dwc_spinlock_t *lock;
-+};
-+
-+static void timer_callback(unsigned long data)
-+{
-+ dwc_timer_t *timer = (dwc_timer_t *)data;
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+ timer->scheduled = 0;
-+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+ DWC_DEBUGC("Timer %s callback", timer->name);
-+ timer->cb(timer->data);
-+}
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (!t) {
-+ DWC_ERROR("Cannot allocate memory for timer");
-+ return NULL;
-+ }
-+
-+ t->t = DWC_ALLOC(sizeof(*t->t));
-+ if (!t->t) {
-+ DWC_ERROR("Cannot allocate memory for timer->t");
-+ goto no_timer;
-+ }
-+
-+ t->name = DWC_STRDUP(name);
-+ if (!t->name) {
-+ DWC_ERROR("Cannot allocate memory for timer->name");
-+ goto no_name;
-+ }
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);
-+#else
-+ t->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+ if (!t->lock) {
-+ DWC_ERROR("Cannot allocate memory for lock");
-+ goto no_lock;
-+ }
-+
-+ t->scheduled = 0;
-+ t->t->base = &boot_tvec_bases;
-+ t->t->expires = jiffies;
-+ setup_timer(t->t, timer_callback, (unsigned long)t);
-+
-+ t->cb = cb;
-+ t->data = data;
-+
-+ return t;
-+
-+ no_lock:
-+ DWC_FREE(t->name);
-+ no_name:
-+ DWC_FREE(t->t);
-+ no_timer:
-+ DWC_FREE(t);
-+ return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+
-+ if (timer->scheduled) {
-+ del_timer(timer->t);
-+ timer->scheduled = 0;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+ DWC_SPINLOCK_FREE(timer->lock);
-+ DWC_FREE(timer->t);
-+ DWC_FREE(timer->name);
-+ DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+
-+ if (!timer->scheduled) {
-+ timer->scheduled = 1;
-+ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
-+ timer->t->expires = jiffies + msecs_to_jiffies(time);
-+ add_timer(timer->t);
-+ } else {
-+ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
-+ mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+ del_timer(timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+ wait_queue_head_t queue;
-+ int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue\n");
-+ return NULL;
-+ }
-+
-+ init_waitqueue_head(&wq->queue);
-+ wq->abort = 0;
-+ return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+ DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+ int result = wait_event_interruptible(wq->queue,
-+ cond(data) || wq->abort);
-+ if (result == -ERESTARTSYS) {
-+ wq->abort = 0;
-+ return -DWC_E_RESTART;
-+ }
-+
-+ if (wq->abort == 1) {
-+ wq->abort = 0;
-+ return -DWC_E_ABORT;
-+ }
-+
-+ wq->abort = 0;
-+
-+ if (result == 0) {
-+ return 0;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs)
-+{
-+ int32_t tmsecs;
-+ int result = wait_event_interruptible_timeout(wq->queue,
-+ cond(data) || wq->abort,
-+ msecs_to_jiffies(msecs));
-+ if (result == -ERESTARTSYS) {
-+ wq->abort = 0;
-+ return -DWC_E_RESTART;
-+ }
-+
-+ if (wq->abort == 1) {
-+ wq->abort = 0;
-+ return -DWC_E_ABORT;
-+ }
-+
-+ wq->abort = 0;
-+
-+ if (result > 0) {
-+ tmsecs = jiffies_to_msecs(result);
-+ if (!tmsecs) {
-+ return 1;
-+ }
-+
-+ return tmsecs;
-+ }
-+
-+ if (result == 0) {
-+ return -DWC_E_TIMEOUT;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+ wq->abort = 0;
-+ wake_up_interruptible(&wq->queue);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+ wq->abort = 1;
-+ wake_up_interruptible(&wq->queue);
-+}
-+
-+
-+/* Threading */
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+ struct task_struct *thread = kthread_run(func, data, name);
-+
-+ if (thread == ERR_PTR(-ENOMEM)) {
-+ return NULL;
-+ }
-+
-+ return (dwc_thread_t *)thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+ return kthread_stop((struct task_struct *)thread);
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
-+{
-+ return kthread_should_stop();
-+}
-+
-+
-+/* tasklets
-+ - run in interrupt context (cannot sleep)
-+ - each tasklet runs on a single CPU
-+ - different tasklets can be running simultaneously on different CPUs
-+ */
-+struct dwc_tasklet {
-+ struct tasklet_struct t;
-+ dwc_tasklet_callback_t cb;
-+ void *data;
-+};
-+
-+static void tasklet_callback(unsigned long data)
-+{
-+ dwc_tasklet_t *t = (dwc_tasklet_t *)data;
-+ t->cb(t->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (t) {
-+ t->cb = cb;
-+ t->data = data;
-+ tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
-+ } else {
-+ DWC_ERROR("Cannot allocate memory for tasklet\n");
-+ }
-+
-+ return t;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+ DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ tasklet_schedule(&task->t);
-+}
-+
-+void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ tasklet_hi_schedule(&task->t);
-+}
-+
-+
-+/* workqueues
-+ - run in process context (can sleep)
-+ */
-+typedef struct work_container {
-+ dwc_work_callback_t cb;
-+ void *data;
-+ dwc_workq_t *wq;
-+ char *name;
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_ENTRY(work_container) entry;
-+#endif
-+ struct delayed_work work;
-+} work_container_t;
-+
-+#ifdef DEBUG
-+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
-+#endif
-+
-+struct dwc_workq {
-+ struct workqueue_struct *wq;
-+ dwc_spinlock_t *lock;
-+ dwc_waitq_t *waitq;
-+ int pending;
-+
-+#ifdef DEBUG
-+ struct work_container_queue entries;
-+#endif
-+};
-+
-+static void do_work(struct work_struct *work)
-+{
-+ dwc_irqflags_t flags;
-+ struct delayed_work *dw = container_of(work, struct delayed_work, work);
-+ work_container_t *container = container_of(dw, struct work_container, work);
-+ dwc_workq_t *wq = container->wq;
-+
-+ container->cb(container->data);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
-+#endif
-+ DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
-+ if (container->name) {
-+ DWC_FREE(container->name);
-+ }
-+ DWC_FREE(container);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending--;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+ dwc_workq_t *workq = (dwc_workq_t *)data;
-+ return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ return NULL;
-+ }
-+
-+ wq->wq = create_singlethread_workqueue(name);
-+ if (!wq->wq) {
-+ goto no_wq;
-+ }
-+
-+ wq->pending = 0;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);
-+#else
-+ wq->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+ if (!wq->lock) {
-+ goto no_lock;
-+ }
-+
-+ wq->waitq = DWC_WAITQ_ALLOC();
-+ if (!wq->waitq) {
-+ goto no_waitq;
-+ }
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INIT(&wq->entries);
-+#endif
-+ return wq;
-+
-+ no_waitq:
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+ destroy_workqueue(wq->wq);
-+ no_wq:
-+ DWC_FREE(wq);
-+
-+ return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+ if (wq->pending != 0) {
-+ struct work_container *wc;
-+ DWC_ERROR("Destroying work queue with pending work");
-+ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
-+ DWC_ERROR("Work %s still pending", wc->name);
-+ }
-+ }
-+#endif
-+ destroy_workqueue(wq->wq);
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ DWC_WAITQ_FREE(wq->waitq);
-+ DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+ char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container\n");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name\n");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
-+ INIT_WORK(&container->work.work, do_work);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ queue_work(wq->wq, &container->work.work);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container\n");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name\n");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
-+ INIT_DELAYED_WORK(&container->work, do_work);
-+
-+#ifdef DEBUG
-+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+ return wq->pending;
-+}
-+
-+
-+#ifdef DWC_LIBMODULE
-+
-+#ifdef DWC_CCLIB
-+/* CC */
-+EXPORT_SYMBOL(dwc_cc_if_alloc);
-+EXPORT_SYMBOL(dwc_cc_if_free);
-+EXPORT_SYMBOL(dwc_cc_clear);
-+EXPORT_SYMBOL(dwc_cc_add);
-+EXPORT_SYMBOL(dwc_cc_remove);
-+EXPORT_SYMBOL(dwc_cc_change);
-+EXPORT_SYMBOL(dwc_cc_data_for_save);
-+EXPORT_SYMBOL(dwc_cc_restore_from_data);
-+EXPORT_SYMBOL(dwc_cc_match_chid);
-+EXPORT_SYMBOL(dwc_cc_match_cdid);
-+EXPORT_SYMBOL(dwc_cc_ck);
-+EXPORT_SYMBOL(dwc_cc_chid);
-+EXPORT_SYMBOL(dwc_cc_cdid);
-+EXPORT_SYMBOL(dwc_cc_name);
-+#endif /* DWC_CCLIB */
-+
-+#ifdef DWC_CRYPTOLIB
-+# ifndef CONFIG_MACH_IPMATE
-+/* Modpow */
-+EXPORT_SYMBOL(dwc_modpow);
-+
-+/* DH */
-+EXPORT_SYMBOL(dwc_dh_modpow);
-+EXPORT_SYMBOL(dwc_dh_derive_keys);
-+EXPORT_SYMBOL(dwc_dh_pk);
-+# endif /* CONFIG_MACH_IPMATE */
-+
-+/* Crypto */
-+EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
-+EXPORT_SYMBOL(dwc_wusb_cmf);
-+EXPORT_SYMBOL(dwc_wusb_prf);
-+EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
-+EXPORT_SYMBOL(dwc_wusb_gen_nonce);
-+EXPORT_SYMBOL(dwc_wusb_gen_key);
-+EXPORT_SYMBOL(dwc_wusb_gen_mic);
-+#endif /* DWC_CRYPTOLIB */
-+
-+/* Notification */
-+#ifdef DWC_NOTIFYLIB
-+EXPORT_SYMBOL(dwc_alloc_notification_manager);
-+EXPORT_SYMBOL(dwc_free_notification_manager);
-+EXPORT_SYMBOL(dwc_register_notifier);
-+EXPORT_SYMBOL(dwc_unregister_notifier);
-+EXPORT_SYMBOL(dwc_add_observer);
-+EXPORT_SYMBOL(dwc_remove_observer);
-+EXPORT_SYMBOL(dwc_notify);
-+#endif
-+
-+/* Memory Debugging Routines */
-+#ifdef DWC_DEBUG_MEMORY
-+EXPORT_SYMBOL(dwc_alloc_debug);
-+EXPORT_SYMBOL(dwc_alloc_atomic_debug);
-+EXPORT_SYMBOL(dwc_free_debug);
-+EXPORT_SYMBOL(dwc_dma_alloc_debug);
-+EXPORT_SYMBOL(dwc_dma_free_debug);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_MEMSET);
-+EXPORT_SYMBOL(DWC_MEMCPY);
-+EXPORT_SYMBOL(DWC_MEMMOVE);
-+EXPORT_SYMBOL(DWC_MEMCMP);
-+EXPORT_SYMBOL(DWC_STRNCMP);
-+EXPORT_SYMBOL(DWC_STRCMP);
-+EXPORT_SYMBOL(DWC_STRLEN);
-+EXPORT_SYMBOL(DWC_STRCPY);
-+EXPORT_SYMBOL(DWC_STRDUP);
-+EXPORT_SYMBOL(DWC_ATOI);
-+EXPORT_SYMBOL(DWC_ATOUI);
-+
-+#ifdef DWC_UTFLIB
-+EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
-+#endif /* DWC_UTFLIB */
-+
-+EXPORT_SYMBOL(DWC_IN_IRQ);
-+EXPORT_SYMBOL(DWC_IN_BH);
-+EXPORT_SYMBOL(DWC_VPRINTF);
-+EXPORT_SYMBOL(DWC_VSNPRINTF);
-+EXPORT_SYMBOL(DWC_PRINTF);
-+EXPORT_SYMBOL(DWC_SPRINTF);
-+EXPORT_SYMBOL(DWC_SNPRINTF);
-+EXPORT_SYMBOL(__DWC_WARN);
-+EXPORT_SYMBOL(__DWC_ERROR);
-+EXPORT_SYMBOL(DWC_EXCEPTION);
-+
-+#ifdef DEBUG
-+EXPORT_SYMBOL(__DWC_DEBUG);
-+#endif
-+
-+EXPORT_SYMBOL(__DWC_DMA_ALLOC);
-+EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
-+EXPORT_SYMBOL(__DWC_DMA_FREE);
-+EXPORT_SYMBOL(__DWC_ALLOC);
-+EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
-+EXPORT_SYMBOL(__DWC_FREE);
-+
-+#ifdef DWC_CRYPTOLIB
-+EXPORT_SYMBOL(DWC_RANDOM_BYTES);
-+EXPORT_SYMBOL(DWC_AES_CBC);
-+EXPORT_SYMBOL(DWC_SHA256);
-+EXPORT_SYMBOL(DWC_HMAC_SHA256);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_CPU_TO_LE32);
-+EXPORT_SYMBOL(DWC_CPU_TO_BE32);
-+EXPORT_SYMBOL(DWC_LE32_TO_CPU);
-+EXPORT_SYMBOL(DWC_BE32_TO_CPU);
-+EXPORT_SYMBOL(DWC_CPU_TO_LE16);
-+EXPORT_SYMBOL(DWC_CPU_TO_BE16);
-+EXPORT_SYMBOL(DWC_LE16_TO_CPU);
-+EXPORT_SYMBOL(DWC_BE16_TO_CPU);
-+EXPORT_SYMBOL(DWC_READ_REG32);
-+EXPORT_SYMBOL(DWC_WRITE_REG32);
-+EXPORT_SYMBOL(DWC_MODIFY_REG32);
-+
-+#if 0
-+EXPORT_SYMBOL(DWC_READ_REG64);
-+EXPORT_SYMBOL(DWC_WRITE_REG64);
-+EXPORT_SYMBOL(DWC_MODIFY_REG64);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
-+EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
-+EXPORT_SYMBOL(DWC_SPINLOCK);
-+EXPORT_SYMBOL(DWC_SPINUNLOCK);
-+EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
-+EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
-+EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
-+
-+#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
-+EXPORT_SYMBOL(DWC_MUTEX_FREE);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_MUTEX_LOCK);
-+EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
-+EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
-+EXPORT_SYMBOL(DWC_UDELAY);
-+EXPORT_SYMBOL(DWC_MDELAY);
-+EXPORT_SYMBOL(DWC_MSLEEP);
-+EXPORT_SYMBOL(DWC_TIME);
-+EXPORT_SYMBOL(DWC_TIMER_ALLOC);
-+EXPORT_SYMBOL(DWC_TIMER_FREE);
-+EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
-+EXPORT_SYMBOL(DWC_TIMER_CANCEL);
-+EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
-+EXPORT_SYMBOL(DWC_WAITQ_FREE);
-+EXPORT_SYMBOL(DWC_WAITQ_WAIT);
-+EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
-+EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
-+EXPORT_SYMBOL(DWC_WAITQ_ABORT);
-+EXPORT_SYMBOL(DWC_THREAD_RUN);
-+EXPORT_SYMBOL(DWC_THREAD_STOP);
-+EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
-+EXPORT_SYMBOL(DWC_TASK_ALLOC);
-+EXPORT_SYMBOL(DWC_TASK_FREE);
-+EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
-+EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
-+EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
-+EXPORT_SYMBOL(DWC_WORKQ_FREE);
-+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
-+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
-+EXPORT_SYMBOL(DWC_WORKQ_PENDING);
-+
-+static int dwc_common_port_init_module(void)
-+{
-+ int result = 0;
-+
-+ printk(KERN_DEBUG "Module dwc_common_port init\n" );
-+
-+#ifdef DWC_DEBUG_MEMORY
-+ result = dwc_memory_debug_start(NULL);
-+ if (result) {
-+ printk(KERN_ERR
-+ "dwc_memory_debug_start() failed with error %d\n",
-+ result);
-+ return result;
-+ }
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+ result = dwc_alloc_notification_manager(NULL, NULL);
-+ if (result) {
-+ printk(KERN_ERR
-+ "dwc_alloc_notification_manager() failed with error %d\n",
-+ result);
-+ return result;
-+ }
-+#endif
-+ return result;
-+}
-+
-+static void dwc_common_port_exit_module(void)
-+{
-+ printk(KERN_DEBUG "Module dwc_common_port exit\n" );
-+
-+#ifdef DWC_NOTIFYLIB
-+ dwc_free_notification_manager();
-+#endif
-+
-+#ifdef DWC_DEBUG_MEMORY
-+ dwc_memory_debug_stop();
-+#endif
-+}
-+
-+module_init(dwc_common_port_init_module);
-+module_exit(dwc_common_port_exit_module);
-+
-+MODULE_DESCRIPTION("DWC Common Library - Portable version");
-+MODULE_AUTHOR("Synopsys Inc.");
-+MODULE_LICENSE ("GPL");
-+
-+#endif /* DWC_LIBMODULE */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,1275 @@
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+ return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+ return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+ bcopy(src, dest, size);
-+ return dest;
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+ return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+ return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+ return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+ return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+ return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+ int len = DWC_STRLEN(str) + 1;
-+ char *new = DWC_ALLOC_ATOMIC(len);
-+
-+ if (!new) {
-+ return NULL;
-+ }
-+
-+ DWC_MEMCPY(new, str, len);
-+ return new;
-+}
-+
-+int DWC_ATOI(char *str, int32_t *value)
-+{
-+ char *end = NULL;
-+
-+ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
-+ * should be equivalent on 2's complement machines
-+ */
-+ *value = strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+int DWC_ATOUI(char *str, uint32_t *value)
-+{
-+ char *end = NULL;
-+
-+ *value = strtoul(str, &end, 0);
-+ if (*end == '\0') {
-+ return 0;
-+ }
-+
-+ return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+#endif /* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+// return in_irq();
-+ return 0;
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+// return in_softirq();
-+ return 0;
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+ vprintf(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+ return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsprintf(buffer, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+ int retval;
-+ va_list args;
-+
-+ va_start(args, format);
-+ retval = vsnprintf(buffer, size, format, args);
-+ va_end(args);
-+ return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+// BUG_ON(1); ???
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VPRINTF(format, args);
-+ va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+ uint32_t align,
-+ uint32_t alloc)
-+{
-+ struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+ size, align, alloc);
-+ return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+ dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+ memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+ dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+ int error;
-+
-+ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
-+ sizeof(dma->segs) / sizeof(dma->segs[0]),
-+ &dma->nsegs, BUS_DMA_NOWAIT);
-+ if (error) {
-+ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
-+ (uintmax_t)size, error);
-+ goto fail_0;
-+ }
-+
-+ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
-+ (caddr_t *)&dma->dma_vaddr,
-+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
-+ if (error) {
-+ printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
-+ goto fail_1;
-+ }
-+
-+ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
-+ BUS_DMA_NOWAIT, &dma->dma_map);
-+ if (error) {
-+ printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
-+ goto fail_2;
-+ }
-+
-+ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
-+ size, NULL, BUS_DMA_NOWAIT);
-+ if (error) {
-+ printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
-+ goto fail_3;
-+ }
-+
-+ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
-+ *dma_addr = dma->dma_paddr;
-+ return dma->dma_vaddr;
-+
-+fail_3:
-+ bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
-+fail_2:
-+ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
-+fail_1:
-+ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
-+fail_0:
-+ dma->dma_map = NULL;
-+ dma->dma_vaddr = NULL;
-+ dma->nsegs = 0;
-+
-+ return NULL;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+
-+ if (dma->dma_map != NULL) {
-+ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
-+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-+ bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+ bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
-+ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
-+ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
-+ dma->dma_paddr = 0;
-+ dma->dma_map = NULL;
-+ dma->dma_vaddr = NULL;
-+ dma->nsegs = 0;
-+ }
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+ free(addr, M_DEVBUF);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+ get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+ struct crypto_blkcipher *tfm;
-+ struct blkcipher_desc desc;
-+ struct scatterlist sgd;
-+ struct scatterlist sgs;
-+
-+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+ if (tfm == NULL) {
-+ printk("failed to load transform for aes CBC\n");
-+ return -1;
-+ }
-+
-+ crypto_blkcipher_setkey(tfm, key, keylen);
-+ crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+ sg_init_one(&sgd, out, messagelen);
-+ sg_init_one(&sgs, message, messagelen);
-+
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+ crypto_free_blkcipher(tfm);
-+ DWC_ERROR("AES CBC encryption failed");
-+ return -1;
-+ }
-+
-+ crypto_free_blkcipher(tfm);
-+ return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, len);
-+ crypto_hash_digest(&desc, &sg, len, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+ struct crypto_hash *tfm;
-+ struct hash_desc desc;
-+ struct scatterlist sg;
-+
-+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+ if (IS_ERR(tfm)) {
-+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
-+ return 0;
-+ }
-+ desc.tfm = tfm;
-+ desc.flags = 0;
-+
-+ sg_init_one(&sg, message, messagelen);
-+ crypto_hash_setkey(tfm, key, keylen);
-+ crypto_hash_digest(&desc, &sg, messagelen, out);
-+ crypto_free_hash(tfm);
-+
-+ return 1;
-+}
-+
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+
-+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+ return *p;
-+#else
-+ uint8_t *u_p = (uint8_t *)p;
-+ return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_4(io->iot, io->ioh, ior);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ return bus_space_read_8(io->iot, io->ioh, ior);
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior, value);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior, value);
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
-+ uint32_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_4(io->iot, io->ioh, ior,
-+ (bus_space_read_4(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
-+ uint64_t set_mask)
-+{
-+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+ bus_size_t ior = (bus_size_t)reg;
-+
-+ bus_space_write_8(io->iot, io->ioh, ior,
-+ (bus_space_read_8(io->iot, io->ioh, ior) &
-+ ~clear_mask) | set_mask);
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+ struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
-+
-+ if (!sl) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ return NULL;
-+ }
-+
-+ simple_lock_init(sl);
-+ return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+ struct simplelock *sl = (struct simplelock *)lock;
-+
-+ DWC_FREE(sl);
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+ simple_lock((struct simplelock *)lock);
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+ simple_unlock((struct simplelock *)lock);
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+ simple_lock((struct simplelock *)lock);
-+ *flags = splbio();
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+ splx(flags);
-+ simple_unlock((struct simplelock *)lock);
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
-+
-+ if (!mutex) {
-+ DWC_ERROR("Cannot allocate memory for mutex");
-+ return NULL;
-+ }
-+
-+ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
-+ return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+ DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+ int status;
-+
-+ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
-+ return status == 0;
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+ lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+ DELAY(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+ do {
-+ DELAY(1000);
-+ } while (--msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+ tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+ struct timeval tv;
-+
-+ microuptime(&tv); // or getmicrouptime? (less precise, but faster)
-+ return tv.tv_sec * 1000 + tv.tv_usec / 1000;
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+ struct callout t;
-+ char *name;
-+ dwc_spinlock_t *lock;
-+ dwc_timer_callback_t cb;
-+ void *data;
-+};
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+ if (!t) {
-+ DWC_ERROR("Cannot allocate memory for timer");
-+ return NULL;
-+ }
-+
-+ callout_init(&t->t);
-+
-+ t->name = DWC_STRDUP(name);
-+ if (!t->name) {
-+ DWC_ERROR("Cannot allocate memory for timer->name");
-+ goto no_name;
-+ }
-+
-+ t->lock = DWC_SPINLOCK_ALLOC();
-+ if (!t->lock) {
-+ DWC_ERROR("Cannot allocate memory for timer->lock");
-+ goto no_lock;
-+ }
-+
-+ t->cb = cb;
-+ t->data = data;
-+
-+ return t;
-+
-+ no_lock:
-+ DWC_FREE(t->name);
-+ no_name:
-+ DWC_FREE(t);
-+
-+ return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+ DWC_SPINLOCK_FREE(timer->lock);
-+ DWC_FREE(timer->name);
-+ DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+ struct timeval tv;
-+
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+ callout_stop(&timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+ struct simplelock lock;
-+ int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ return NULL;
-+ }
-+
-+ simple_lock_init(&wq->lock);
-+ wq->abort = 0;
-+
-+ return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+ DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+ int ipl;
-+ int result = 0;
-+
-+ simple_lock(&wq->lock);
-+ ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+ splx(ipl);
-+ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
-+ ipl = splbio();
-+ }
-+
-+ if (result == 0) { // awoken
-+ if (wq->abort) {
-+ wq->abort = 0;
-+ result = -DWC_E_ABORT;
-+ } else {
-+ result = 0;
-+ }
-+
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+ } else {
-+ wq->abort = 0;
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+
-+ if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+ } else { // signaled - must be EINTR
-+ result = -DWC_E_ABORT;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs)
-+{
-+ struct timeval tv, tv1, tv2;
-+ int ipl;
-+ int result = 0;
-+
-+ tv.tv_sec = msecs / 1000;
-+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+
-+ simple_lock(&wq->lock);
-+ ipl = splbio();
-+
-+ /* Skip the sleep if already aborted or triggered */
-+ if (!wq->abort && !cond(data)) {
-+ splx(ipl);
-+ getmicrouptime(&tv1);
-+ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
-+ getmicrouptime(&tv2);
-+ ipl = splbio();
-+ }
-+
-+ if (result == 0) { // awoken
-+ if (wq->abort) {
-+ wq->abort = 0;
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+ result = -DWC_E_ABORT;
-+ } else {
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+
-+ tv2.tv_usec -= tv1.tv_usec;
-+ if (tv2.tv_usec < 0) {
-+ tv2.tv_usec += 1000000;
-+ tv2.tv_sec--;
-+ }
-+
-+ tv2.tv_sec -= tv1.tv_sec;
-+ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
-+ result = msecs - result;
-+ if (result <= 0)
-+ result = 1;
-+ }
-+ } else {
-+ wq->abort = 0;
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+
-+ if (result == ERESTART) { // signaled - restart
-+ result = -DWC_E_RESTART;
-+
-+ } else if (result == EINTR) { // signaled - interrupt
-+ result = -DWC_E_ABORT;
-+
-+ } else { // timed out
-+ result = -DWC_E_TIMEOUT;
-+ }
-+ }
-+
-+ return result;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+ wakeup(wq);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+ int ipl;
-+
-+ simple_lock(&wq->lock);
-+ ipl = splbio();
-+ wq->abort = 1;
-+ wakeup(wq);
-+ splx(ipl);
-+ simple_unlock(&wq->lock);
-+}
-+
-+
-+/* Threading */
-+
-+struct dwc_thread {
-+ struct proc *proc;
-+ int abort;
-+};
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+ int retval;
-+ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
-+
-+ if (!thread) {
-+ return NULL;
-+ }
-+
-+ thread->abort = 0;
-+ retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
-+ "%s", name);
-+ if (retval) {
-+ DWC_FREE(thread);
-+ return NULL;
-+ }
-+
-+ return thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+ int retval;
-+
-+ thread->abort = 1;
-+ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
-+
-+ if (retval == 0) {
-+ /* DWC_THREAD_EXIT() will free the thread struct */
-+ return 0;
-+ }
-+
-+ /* NOTE: We leak the thread struct if thread doesn't die */
-+
-+ if (retval == EWOULDBLOCK) {
-+ return -DWC_E_TIMEOUT;
-+ }
-+
-+ return -DWC_E_UNKNOWN;
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
-+{
-+ return thread->abort;
-+}
-+
-+void DWC_THREAD_EXIT(dwc_thread_t *thread)
-+{
-+ wakeup(&thread->abort);
-+ DWC_FREE(thread);
-+ kthread_exit(0);
-+}
-+
-+/* tasklets
-+ - Runs in interrupt context (cannot sleep)
-+ - Each tasklet runs on a single CPU
-+ - Different tasklets can be running simultaneously on different CPUs
-+ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
-+ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
-+ */
-+struct dwc_tasklet {
-+ dwc_tasklet_callback_t cb;
-+ void *data;
-+};
-+
-+static void tasklet_callback(void *data)
-+{
-+ dwc_tasklet_t *task = (dwc_tasklet_t *)data;
-+
-+ task->cb(task->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
-+
-+ if (task) {
-+ task->cb = cb;
-+ task->data = data;
-+ } else {
-+ DWC_ERROR("Cannot allocate memory for tasklet");
-+ }
-+
-+ return task;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+ DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+ tasklet_callback(task);
-+}
-+
-+
-+/* workqueues
-+ - Runs in process context (can sleep)
-+ */
-+typedef struct work_container {
-+ dwc_work_callback_t cb;
-+ void *data;
-+ dwc_workq_t *wq;
-+ char *name;
-+ int hz;
-+ struct work task;
-+} work_container_t;
-+
-+struct dwc_workq {
-+ struct workqueue *taskq;
-+ dwc_spinlock_t *lock;
-+ dwc_waitq_t *waitq;
-+ int pending;
-+ struct work_container *container;
-+};
-+
-+static void do_work(struct work *task, void *data)
-+{
-+ dwc_workq_t *wq = (dwc_workq_t *)data;
-+ work_container_t *container = wq->container;
-+ dwc_irqflags_t flags;
-+
-+ if (container->hz) {
-+ tsleep(container, 0, "dw3wrk", container->hz);
-+ }
-+
-+ container->cb(container->data);
-+ DWC_DEBUG("Work done: %s, container=%p", container->name, container);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ if (container->name)
-+ DWC_FREE(container->name);
-+ DWC_FREE(container);
-+ wq->pending--;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+ dwc_workq_t *workq = (dwc_workq_t *)data;
-+
-+ return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+ int result;
-+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+ if (!wq) {
-+ DWC_ERROR("Cannot allocate memory for workqueue");
-+ return NULL;
-+ }
-+
-+ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
-+ IPL_BIO, 0);
-+ if (result) {
-+ DWC_ERROR("Cannot create workqueue");
-+ goto no_taskq;
-+ }
-+
-+ wq->pending = 0;
-+
-+ wq->lock = DWC_SPINLOCK_ALLOC();
-+ if (!wq->lock) {
-+ DWC_ERROR("Cannot allocate memory for spinlock");
-+ goto no_lock;
-+ }
-+
-+ wq->waitq = DWC_WAITQ_ALLOC();
-+ if (!wq->waitq) {
-+ DWC_ERROR("Cannot allocate memory for waitqueue");
-+ goto no_waitq;
-+ }
-+
-+ return wq;
-+
-+ no_waitq:
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+ workqueue_destroy(wq->taskq);
-+ no_taskq:
-+ DWC_FREE(wq);
-+
-+ return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+ dwc_irqflags_t flags;
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+ if (wq->pending != 0) {
-+ struct work_container *container = wq->container;
-+
-+ DWC_ERROR("Destroying work queue with pending work");
-+
-+ if (container && container->name) {
-+ DWC_ERROR("Work %s still pending", container->name);
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+#endif
-+ DWC_WAITQ_FREE(wq->waitq);
-+ DWC_SPINLOCK_FREE(wq->lock);
-+ workqueue_destroy(wq->taskq);
-+ DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+ char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ container->hz = 0;
-+ wq->container = container;
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+ workqueue_enqueue(wq->taskq, &container->task);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+{
-+ dwc_irqflags_t flags;
-+ work_container_t *container;
-+ static char name[128];
-+ struct timeval tv;
-+ va_list args;
-+
-+ va_start(args, format);
-+ DWC_VSNPRINTF(name, 128, format, args);
-+ va_end(args);
-+
-+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+ wq->pending++;
-+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+ DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+ container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+ if (!container) {
-+ DWC_ERROR("Cannot allocate memory for container");
-+ return;
-+ }
-+
-+ container->name = DWC_STRDUP(name);
-+ if (!container->name) {
-+ DWC_ERROR("Cannot allocate memory for container->name");
-+ DWC_FREE(container);
-+ return;
-+ }
-+
-+ container->cb = cb;
-+ container->data = data;
-+ container->wq = wq;
-+ tv.tv_sec = time / 1000;
-+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+ container->hz = tvtohz(&tv);
-+ wq->container = container;
-+
-+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+ workqueue_enqueue(wq->taskq, &container->task);
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+ return wq->pending;
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_crypto.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_crypto.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,308 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
-+ * $Revision: #5 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+
-+/** @file
-+ * This file contains the WUSB cryptographic routines.
-+ */
-+
-+#ifdef DWC_CRYPTOLIB
-+
-+#include "dwc_crypto.h"
-+#include "usb.h"
-+
-+#ifdef DEBUG
-+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
-+{
-+ int i;
-+ DWC_PRINTF("%s: ", name);
-+ for (i=0; i<len; i++) {
-+ DWC_PRINTF("%02x ", bytes[i]);
-+ }
-+ DWC_PRINTF("\n");
-+}
-+#else
-+#define dump_bytes(x...)
-+#endif
-+
-+/* Display a block */
-+void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
-+{
-+#ifdef DWC_DEBUG_CRYPTO
-+ int i, blksize = 16;
-+
-+ DWC_DEBUG("%s", prefix);
-+
-+ if (suffix == NULL) {
-+ suffix = "\n";
-+ blksize = a;
-+ }
-+
-+ for (i = 0; i < blksize; i++)
-+ DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? " " : " ");
-+ DWC_PRINT(suffix);
-+#endif
-+}
-+
-+/**
-+ * Encrypts an array of bytes using the AES encryption engine.
-+ * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
-+ * in-place.
-+ *
-+ * @return 0 on success, negative error code on error.
-+ */
-+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
-+{
-+ u8 block_t[16];
-+ DWC_MEMSET(block_t, 0, 16);
-+
-+ return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
-+}
-+
-+/**
-+ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
-+ * This function takes a data string and returns the encrypted CBC
-+ * Counter-mode MIC.
-+ *
-+ * @param key The 128-bit symmetric key.
-+ * @param nonce The CCM nonce.
-+ * @param label The unique 14-byte ASCII text label.
-+ * @param bytes The byte array to be encrypted.
-+ * @param len Length of the byte array.
-+ * @param result Byte array to receive the 8-byte encrypted MIC.
-+ */
-+void dwc_wusb_cmf(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ u8 block_m[16];
-+ u8 block_x[16];
-+ u8 block_t[8];
-+ int idx, blkNum;
-+ u16 la = (u16)(len + 14);
-+
-+ /* Set the AES-128 key */
-+ //dwc_aes_setkey(tfm, key, 16);
-+
-+ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
-+ block_m[0] = 0x59;
-+ for (idx = 0; idx < 13; idx++)
-+ block_m[idx + 1] = nonce[idx];
-+ block_m[14] = 0;
-+ block_m[15] = 0;
-+
-+ /* Produce the CBC IV */
-+ dwc_wusb_aes_encrypt(block_m, key, block_x);
-+ show_block(block_m, "CBC IV in: ", "\n", 0);
-+ show_block(block_x, "CBC IV out:", "\n", 0);
-+
-+ /* Fill block B1 from l(a) = Blen + 14, and A */
-+ block_x[0] ^= (u8)(la >> 8);
-+ block_x[1] ^= (u8)la;
-+ for (idx = 0; idx < 14; idx++)
-+ block_x[idx + 2] ^= label[idx];
-+ show_block(block_x, "After xor: ", "b1\n", 16);
-+
-+ dwc_wusb_aes_encrypt(block_x, key, block_x);
-+ show_block(block_x, "After AES: ", "b1\n", 16);
-+
-+ idx = 0;
-+ blkNum = 0;
-+
-+ /* Fill remaining blocks with B */
-+ while (len-- > 0) {
-+ block_x[idx] ^= *bytes++;
-+ if (++idx >= 16) {
-+ idx = 0;
-+ show_block(block_x, "After xor: ", "\n", blkNum);
-+ dwc_wusb_aes_encrypt(block_x, key, block_x);
-+ show_block(block_x, "After AES: ", "\n", blkNum);
-+ blkNum++;
-+ }
-+ }
-+
-+ /* Handle partial last block */
-+ if (idx > 0) {
-+ show_block(block_x, "After xor: ", "\n", blkNum);
-+ dwc_wusb_aes_encrypt(block_x, key, block_x);
-+ show_block(block_x, "After AES: ", "\n", blkNum);
-+ }
-+
-+ /* Save the MIC tag */
-+ DWC_MEMCPY(block_t, block_x, 8);
-+ show_block(block_t, "MIC tag : ", NULL, 8);
-+
-+ /* Fill block A0 from flags = 0x01, N, and counter = 0 */
-+ block_m[0] = 0x01;
-+ block_m[14] = 0;
-+ block_m[15] = 0;
-+
-+ /* Encrypt the counter */
-+ dwc_wusb_aes_encrypt(block_m, key, block_x);
-+ show_block(block_x, "CTR[MIC] : ", NULL, 8);
-+
-+ /* XOR with MIC tag */
-+ for (idx = 0; idx < 8; idx++) {
-+ block_t[idx] ^= block_x[idx];
-+ }
-+
-+ /* Return result to caller */
-+ DWC_MEMCPY(result, block_t, 8);
-+ show_block(result, "CCM-MIC : ", NULL, 8);
-+
-+}
-+
-+/**
-+ * The PRF function described in section 6.5 of the WUSB spec. This function
-+ * concatenates MIC values returned from dwc_cmf() to create a value of
-+ * the requested length.
-+ *
-+ * @param prf_len Length of the PRF function in bits (64, 128, or 256).
-+ * @param key, nonce, label, bytes, len Same as for dwc_cmf().
-+ * @param result Byte array to receive the result.
-+ */
-+void dwc_wusb_prf(int prf_len, u8 *key,
-+ u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
-+{
-+ int i;
-+
-+ nonce[0] = 0;
-+ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
-+ dwc_wusb_cmf(key, nonce, label, bytes, len, result);
-+ result += 8;
-+ }
-+}
-+
-+/**
-+ * Fills in CCM Nonce per the WUSB spec.
-+ *
-+ * @param[in] haddr Host address.
-+ * @param[in] daddr Device address.
-+ * @param[in] tkid Session Key(PTK) identifier.
-+ * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
-+ */
-+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
-+ uint8_t *nonce)
-+{
-+
-+ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
-+
-+ DWC_MEMSET(&nonce[0], 0, 16);
-+
-+ DWC_MEMCPY(&nonce[6], tkid, 3);
-+ nonce[9] = daddr & 0xFF;
-+ nonce[10] = (daddr >> 8) & 0xFF;
-+ nonce[11] = haddr & 0xFF;
-+ nonce[12] = (haddr >> 8) & 0xFF;
-+
-+ dump_bytes("CCM nonce", nonce, 16);
-+}
-+
-+/**
-+ * Generates a 16-byte cryptographic-grade random number for the Host/Device
-+ * Nonce.
-+ */
-+void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
-+{
-+ uint8_t inonce[16];
-+ uint32_t temp[4];
-+
-+ /* Fill in the Nonce */
-+ DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
-+ inonce[9] = addr & 0xFF;
-+ inonce[10] = (addr >> 8) & 0xFF;
-+ inonce[11] = inonce[9];
-+ inonce[12] = inonce[10];
-+
-+ /* Collect "randomness samples" */
-+ DWC_RANDOM_BYTES((uint8_t *)temp, 16);
-+
-+ dwc_wusb_prf_128((uint8_t *)temp, nonce,
-+ "Random Numbers", (uint8_t *)temp, sizeof(temp),
-+ nonce);
-+}
-+
-+/**
-+ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
-+ * WUSB spec.
-+ *
-+ * @param[in] ccm_nonce Pointer to CCM Nonce.
-+ * @param[in] mk Master Key to derive the session from
-+ * @param[in] hnonce Pointer to Host Nonce.
-+ * @param[in] dnonce Pointer to Device Nonce.
-+ * @param[out] kck Pointer to where the KCK output is to be written.
-+ * @param[out] ptk Pointer to where the PTK output is to be written.
-+ */
-+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
-+ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
-+{
-+ uint8_t idata[32];
-+ uint8_t odata[32];
-+
-+ dump_bytes("ck", mk, 16);
-+ dump_bytes("hnonce", hnonce, 16);
-+ dump_bytes("dnonce", dnonce, 16);
-+
-+ /* The data is the HNonce and DNonce concatenated */
-+ DWC_MEMCPY(&idata[0], hnonce, 16);
-+ DWC_MEMCPY(&idata[16], dnonce, 16);
-+
-+ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
-+
-+ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
-+ DWC_MEMCPY(kck, &odata[0], 16);
-+ DWC_MEMCPY(ptk, &odata[16], 16);
-+
-+ dump_bytes("kck", kck, 16);
-+ dump_bytes("ptk", ptk, 16);
-+}
-+
-+/**
-+ * Generates the Message Integrity Code over the Handshake data per the
-+ * WUSB spec.
-+ *
-+ * @param ccm_nonce Pointer to CCM Nonce.
-+ * @param kck Pointer to Key Confirmation Key.
-+ * @param data Pointer to Handshake data to be checked.
-+ * @param mic Pointer to where the MIC output is to be written.
-+ */
-+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
-+ uint8_t *data, uint8_t *mic)
-+{
-+
-+ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
-+ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
-+}
-+
-+#endif /* DWC_CRYPTOLIB */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_crypto.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_crypto.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,111 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
-+ * $Revision: #3 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+
-+#ifndef _DWC_CRYPTO_H_
-+#define _DWC_CRYPTO_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file contains declarations for the WUSB Cryptographic routines as
-+ * defined in the WUSB spec. They are only to be used internally by the DWC UWB
-+ * modules.
-+ */
-+
-+#include "dwc_os.h"
-+
-+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
-+
-+void dwc_wusb_cmf(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result);
-+void dwc_wusb_prf(int prf_len, u8 *key,
-+ u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
-+
-+/**
-+ * The PRF-64 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
-+}
-+
-+/**
-+ * The PRF-128 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
-+}
-+
-+/**
-+ * The PRF-256 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
-+ char *label, u8 *bytes, int len, u8 *result)
-+{
-+ dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
-+}
-+
-+
-+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
-+ uint8_t *nonce);
-+void dwc_wusb_gen_nonce(uint16_t addr,
-+ uint8_t *nonce);
-+
-+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
-+ uint8_t *hnonce, uint8_t *dnonce,
-+ uint8_t *kck, uint8_t *ptk);
-+
-+
-+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
-+ *kck, uint8_t *data, uint8_t *mic);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_CRYPTO_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_dh.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_dh.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,291 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
-+ * $Revision: #3 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifdef DWC_CRYPTOLIB
-+
-+#ifndef CONFIG_MACH_IPMATE
-+
-+#include "dwc_dh.h"
-+#include "dwc_modpow.h"
-+
-+#ifdef DEBUG
-+/* This function prints out a buffer in the format described in the Association
-+ * Model specification. */
-+static void dh_dump(char *str, void *_num, int len)
-+{
-+ uint8_t *num = _num;
-+ int i;
-+ DWC_PRINTF("%s\n", str);
-+ for (i = 0; i < len; i ++) {
-+ DWC_PRINTF("%02x", num[i]);
-+ if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
-+ if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
-+ }
-+
-+ DWC_PRINTF("\n");
-+}
-+#else
-+#define dh_dump(_x...) do {; } while(0)
-+#endif
-+
-+/* Constant g value */
-+static __u32 dh_g[] = {
-+ 0x02000000,
-+};
-+
-+/* Constant p value */
-+static __u32 dh_p[] = {
-+ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
-+ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
-+ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
-+ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
-+ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
-+ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
-+ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
-+ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
-+ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
-+ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
-+ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
-+ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
-+};
-+
-+static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
-+{
-+ uint8_t *in = _in;
-+ uint8_t *out = _out;
-+ int i;
-+ for (i=0; i<len; i++) {
-+ out[i] = in[len-1-i];
-+ }
-+}
-+
-+/* Computes the modular exponentiation (num^exp % mod). num, exp, and mod are
-+ * big endian numbers of size len, in bytes. Each len value must be a multiple
-+ * of 4. */
-+int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
-+ void *exp, uint32_t exp_len,
-+ void *mod, uint32_t mod_len,
-+ void *out)
-+{
-+ /* modpow() takes little endian numbers. AM uses big-endian. This
-+ * function swaps bytes of numbers before passing onto modpow. */
-+
-+ int retval = 0;
-+ uint32_t *result;
-+
-+ uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
-+ uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
-+ uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
-+
-+ dh_swap_bytes(num, &bignum_num[1], num_len);
-+ bignum_num[0] = num_len / 4;
-+
-+ dh_swap_bytes(exp, &bignum_exp[1], exp_len);
-+ bignum_exp[0] = exp_len / 4;
-+
-+ dh_swap_bytes(mod, &bignum_mod[1], mod_len);
-+ bignum_mod[0] = mod_len / 4;
-+
-+ result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
-+ if (!result) {
-+ retval = -1;
-+ goto dh_modpow_nomem;
-+ }
-+
-+ dh_swap_bytes(&result[1], out, result[0] * 4);
-+ dwc_free(mem_ctx, result);
-+
-+ dh_modpow_nomem:
-+ dwc_free(mem_ctx, bignum_num);
-+ dwc_free(mem_ctx, bignum_exp);
-+ dwc_free(mem_ctx, bignum_mod);
-+ return retval;
-+}
-+
-+
-+int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
-+{
-+ int retval;
-+ uint8_t m3[385];
-+
-+#ifndef DH_TEST_VECTORS
-+ DWC_RANDOM_BYTES(exp, 32);
-+#endif
-+
-+ /* Compute the pkd */
-+ if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
-+ exp, 32,
-+ dh_p, 384, pk))) {
-+ return retval;
-+ }
-+
-+ m3[384] = nd;
-+ DWC_MEMCPY(&m3[0], pk, 384);
-+ DWC_SHA256(m3, 385, hash);
-+
-+ dh_dump("PK", pk, 384);
-+ dh_dump("SHA-256(M3)", hash, 32);
-+ return 0;
-+}
-+
-+int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
-+ uint8_t *exp, int is_host,
-+ char *dd, uint8_t *ck, uint8_t *kdk)
-+{
-+ int retval;
-+ uint8_t mv[784];
-+ uint8_t sha_result[32];
-+ uint8_t dhkey[384];
-+ uint8_t shared_secret[384];
-+ char *message;
-+ uint32_t vd;
-+
-+ uint8_t *pk;
-+
-+ if (is_host) {
-+ pk = pkd;
-+ }
-+ else {
-+ pk = pkh;
-+ }
-+
-+ if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
-+ exp, 32,
-+ dh_p, 384, shared_secret))) {
-+ return retval;
-+ }
-+ dh_dump("Shared Secret", shared_secret, 384);
-+
-+ DWC_SHA256(shared_secret, 384, dhkey);
-+ dh_dump("DHKEY", dhkey, 384);
-+
-+ DWC_MEMCPY(&mv[0], pkd, 384);
-+ DWC_MEMCPY(&mv[384], pkh, 384);
-+ DWC_MEMCPY(&mv[768], "displayed digest", 16);
-+ dh_dump("MV", mv, 784);
-+
-+ DWC_SHA256(mv, 784, sha_result);
-+ dh_dump("SHA-256(MV)", sha_result, 32);
-+ dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
-+
-+ dh_swap_bytes(sha_result, &vd, 4);
-+#ifdef DEBUG
-+ DWC_PRINTF("Vd (decimal) = %d\n", vd);
-+#endif
-+
-+ switch (nd) {
-+ case 2:
-+ vd = vd % 100;
-+ DWC_SPRINTF(dd, "%02d", vd);
-+ break;
-+ case 3:
-+ vd = vd % 1000;
-+ DWC_SPRINTF(dd, "%03d", vd);
-+ break;
-+ case 4:
-+ vd = vd % 10000;
-+ DWC_SPRINTF(dd, "%04d", vd);
-+ break;
-+ }
-+#ifdef DEBUG
-+ DWC_PRINTF("Display Digits: %s\n", dd);
-+#endif
-+
-+ message = "connection key";
-+ DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
-+ dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
-+ DWC_MEMCPY(ck, sha_result, 16);
-+
-+ message = "key derivation key";
-+ DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
-+ dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
-+ DWC_MEMCPY(kdk, sha_result, 32);
-+
-+ return 0;
-+}
-+
-+
-+#ifdef DH_TEST_VECTORS
-+
-+static __u8 dh_a[] = {
-+ 0x44, 0x00, 0x51, 0xd6,
-+ 0xf0, 0xb5, 0x5e, 0xa9,
-+ 0x67, 0xab, 0x31, 0xc6,
-+ 0x8a, 0x8b, 0x5e, 0x37,
-+ 0xd9, 0x10, 0xda, 0xe0,
-+ 0xe2, 0xd4, 0x59, 0xa4,
-+ 0x86, 0x45, 0x9c, 0xaa,
-+ 0xdf, 0x36, 0x75, 0x16,
-+};
-+
-+static __u8 dh_b[] = {
-+ 0x5d, 0xae, 0xc7, 0x86,
-+ 0x79, 0x80, 0xa3, 0x24,
-+ 0x8c, 0xe3, 0x57, 0x8f,
-+ 0xc7, 0x5f, 0x1b, 0x0f,
-+ 0x2d, 0xf8, 0x9d, 0x30,
-+ 0x6f, 0xa4, 0x52, 0xcd,
-+ 0xe0, 0x7a, 0x04, 0x8a,
-+ 0xde, 0xd9, 0x26, 0x56,
-+};
-+
-+void dwc_run_dh_test_vectors(void *mem_ctx)
-+{
-+ uint8_t pkd[384];
-+ uint8_t pkh[384];
-+ uint8_t hashd[32];
-+ uint8_t hashh[32];
-+ uint8_t ck[16];
-+ uint8_t kdk[32];
-+ char dd[5];
-+
-+ DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
-+
-+ /* compute the PKd and SHA-256(PKd || Nd) */
-+ DWC_PRINTF("Computing PKd\n");
-+ dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
-+
-+ /* compute the PKd and SHA-256(PKh || Nd) */
-+ DWC_PRINTF("Computing PKh\n");
-+ dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
-+
-+ /* compute the dhkey */
-+ dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
-+}
-+#endif /* DH_TEST_VECTORS */
-+
-+#endif /* !CONFIG_MACH_IPMATE */
-+
-+#endif /* DWC_CRYPTOLIB */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_dh.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_dh.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.h 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,106 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
-+ * $Revision: #4 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_DH_H_
-+#define _DWC_DH_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * This file defines the common functions on device and host for performing
-+ * numeric association as defined in the WUSB spec. They are only to be
-+ * used internally by the DWC UWB modules. */
-+
-+extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
-+extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
-+ uint8_t *key, uint32_t keylen,
-+ uint8_t *out);
-+extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
-+ void *exp, uint32_t exp_len,
-+ void *mod, uint32_t mod_len,
-+ void *out);
-+
-+/** Computes PKD or PKH, and SHA-256(PKd || Nd)
-+ *
-+ * PK = g^exp mod p.
-+ *
-+ * Input:
-+ * Nd = Number of digits on the device.
-+ *
-+ * Output:
-+ * exp = A 32-byte buffer to be filled with a randomly generated number.
-+ * used as either A or B.
-+ * pk = A 384-byte buffer to be filled with the PKH or PKD.
-+ * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
-+ */
-+extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
-+
-+/** Computes the DHKEY, and VD.
-+ *
-+ * If called from host, then it will comput DHKEY=PKD^exp % p.
-+ * If called from device, then it will comput DHKEY=PKH^exp % p.
-+ *
-+ * Input:
-+ * pkd = The PKD value.
-+ * pkh = The PKH value.
-+ * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
-+ * is_host = Set to non zero if a WUSB host is calling this function.
-+ *
-+ * Output:
-+
-+ * dd = A pointer to an buffer to be set to the displayed digits string to be shown
-+ * to the user. This buffer should be at 5 bytes long to hold 4 digits plus a
-+ * null termination character. This buffer can be used directly for display.
-+ * ck = A 16-byte buffer to be filled with the CK.
-+ * kdk = A 32-byte buffer to be filled with the KDK.
-+ */
-+extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
-+ uint8_t *exp, int is_host,
-+ char *dd, uint8_t *ck, uint8_t *kdk);
-+
-+#ifdef DH_TEST_VECTORS
-+extern void dwc_run_dh_test_vectors(void);
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_DH_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_list.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_list.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_list.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_list.h 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,594 @@
-+/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
-+/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
-+
-+/*
-+ * Copyright (c) 1991, 1993
-+ * The Regents of the University of California. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. Neither the name of the University nor the names of its contributors
-+ * may be used to endorse or promote products derived from this software
-+ * without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
-+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-+ * SUCH DAMAGE.
-+ *
-+ * @(#)queue.h 8.5 (Berkeley) 8/20/94
-+ */
-+
-+#ifndef _DWC_LIST_H_
-+#define _DWC_LIST_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file defines linked list operations. It is derived from BSD with
-+ * only the MACRO names being prefixed with DWC_. This is because a few of
-+ * these names conflict with those on Linux. For documentation on use, see the
-+ * inline comments in the source code. The original license for this source
-+ * code applies and is preserved in the dwc_list.h source file.
-+ */
-+
-+/*
-+ * This file defines five types of data structures: singly-linked lists,
-+ * lists, simple queues, tail queues, and circular queues.
-+ *
-+ *
-+ * A singly-linked list is headed by a single forward pointer. The elements
-+ * are singly linked for minimum space and pointer manipulation overhead at
-+ * the expense of O(n) removal for arbitrary elements. New elements can be
-+ * added to the list after an existing element or at the head of the list.
-+ * Elements being removed from the head of the list should use the explicit
-+ * macro for this purpose for optimum efficiency. A singly-linked list may
-+ * only be traversed in the forward direction. Singly-linked lists are ideal
-+ * for applications with large datasets and few or no removals or for
-+ * implementing a LIFO queue.
-+ *
-+ * A list is headed by a single forward pointer (or an array of forward
-+ * pointers for a hash table header). The elements are doubly linked
-+ * so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before
-+ * or after an existing element or at the head of the list. A list
-+ * may only be traversed in the forward direction.
-+ *
-+ * A simple queue is headed by a pair of pointers, one the head of the
-+ * list and the other to the tail of the list. The elements are singly
-+ * linked to save space, so elements can only be removed from the
-+ * head of the list. New elements can be added to the list before or after
-+ * an existing element, at the head of the list, or at the end of the
-+ * list. A simple queue may only be traversed in the forward direction.
-+ *
-+ * A tail queue is headed by a pair of pointers, one to the head of the
-+ * list and the other to the tail of the list. The elements are doubly
-+ * linked so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before or
-+ * after an existing element, at the head of the list, or at the end of
-+ * the list. A tail queue may be traversed in either direction.
-+ *
-+ * A circle queue is headed by a pair of pointers, one to the head of the
-+ * list and the other to the tail of the list. The elements are doubly
-+ * linked so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before or after
-+ * an existing element, at the head of the list, or at the end of the list.
-+ * A circle queue may be traversed in either direction, but has a more
-+ * complex end of list detection.
-+ *
-+ * For details on the use of these macros, see the queue(3) manual page.
-+ */
-+
-+/*
-+ * Double-linked List.
-+ */
-+
-+typedef struct dwc_list_link {
-+ struct dwc_list_link *next;
-+ struct dwc_list_link *prev;
-+} dwc_list_link_t;
-+
-+#define DWC_LIST_INIT(link) do { \
-+ (link)->next = (link); \
-+ (link)->prev = (link); \
-+} while (0)
-+
-+#define DWC_LIST_FIRST(link) ((link)->next)
-+#define DWC_LIST_LAST(link) ((link)->prev)
-+#define DWC_LIST_END(link) (link)
-+#define DWC_LIST_NEXT(link) ((link)->next)
-+#define DWC_LIST_PREV(link) ((link)->prev)
-+#define DWC_LIST_EMPTY(link) \
-+ (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
-+#define DWC_LIST_ENTRY(link, type, field) \
-+ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
-+
-+#if 0
-+#define DWC_LIST_INSERT_HEAD(list, link) do { \
-+ (link)->next = (list)->next; \
-+ (link)->prev = (list); \
-+ (list)->next->prev = (link); \
-+ (list)->next = (link); \
-+} while (0)
-+
-+#define DWC_LIST_INSERT_TAIL(list, link) do { \
-+ (link)->next = (list); \
-+ (link)->prev = (list)->prev; \
-+ (list)->prev->next = (link); \
-+ (list)->prev = (link); \
-+} while (0)
-+#else
-+#define DWC_LIST_INSERT_HEAD(list, link) do { \
-+ dwc_list_link_t *__next__ = (list)->next; \
-+ __next__->prev = (link); \
-+ (link)->next = __next__; \
-+ (link)->prev = (list); \
-+ (list)->next = (link); \
-+} while (0)
-+
-+#define DWC_LIST_INSERT_TAIL(list, link) do { \
-+ dwc_list_link_t *__prev__ = (list)->prev; \
-+ (list)->prev = (link); \
-+ (link)->next = (list); \
-+ (link)->prev = __prev__; \
-+ __prev__->next = (link); \
-+} while (0)
-+#endif
-+
-+#if 0
-+static inline void __list_add(struct list_head *new,
-+ struct list_head *prev,
-+ struct list_head *next)
-+{
-+ next->prev = new;
-+ new->next = next;
-+ new->prev = prev;
-+ prev->next = new;
-+}
-+
-+static inline void list_add(struct list_head *new, struct list_head *head)
-+{
-+ __list_add(new, head, head->next);
-+}
-+
-+static inline void list_add_tail(struct list_head *new, struct list_head *head)
-+{
-+ __list_add(new, head->prev, head);
-+}
-+
-+static inline void __list_del(struct list_head * prev, struct list_head * next)
-+{
-+ next->prev = prev;
-+ prev->next = next;
-+}
-+
-+static inline void list_del(struct list_head *entry)
-+{
-+ __list_del(entry->prev, entry->next);
-+ entry->next = LIST_POISON1;
-+ entry->prev = LIST_POISON2;
-+}
-+#endif
-+
-+#define DWC_LIST_REMOVE(link) do { \
-+ (link)->next->prev = (link)->prev; \
-+ (link)->prev->next = (link)->next; \
-+} while (0)
-+
-+#define DWC_LIST_REMOVE_INIT(link) do { \
-+ DWC_LIST_REMOVE(link); \
-+ DWC_LIST_INIT(link); \
-+} while (0)
-+
-+#define DWC_LIST_MOVE_HEAD(list, link) do { \
-+ DWC_LIST_REMOVE(link); \
-+ DWC_LIST_INSERT_HEAD(list, link); \
-+} while (0)
-+
-+#define DWC_LIST_MOVE_TAIL(list, link) do { \
-+ DWC_LIST_REMOVE(link); \
-+ DWC_LIST_INSERT_TAIL(list, link); \
-+} while (0)
-+
-+#define DWC_LIST_FOREACH(var, list) \
-+ for((var) = DWC_LIST_FIRST(list); \
-+ (var) != DWC_LIST_END(list); \
-+ (var) = DWC_LIST_NEXT(var))
-+
-+#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
-+ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
-+ (var) != DWC_LIST_END(list); \
-+ (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
-+
-+#define DWC_LIST_FOREACH_REVERSE(var, list) \
-+ for((var) = DWC_LIST_LAST(list); \
-+ (var) != DWC_LIST_END(list); \
-+ (var) = DWC_LIST_PREV(var))
-+
-+/*
-+ * Singly-linked List definitions.
-+ */
-+#define DWC_SLIST_HEAD(name, type) \
-+struct name { \
-+ struct type *slh_first; /* first element */ \
-+}
-+
-+#define DWC_SLIST_HEAD_INITIALIZER(head) \
-+ { NULL }
-+
-+#define DWC_SLIST_ENTRY(type) \
-+struct { \
-+ struct type *sle_next; /* next element */ \
-+}
-+
-+/*
-+ * Singly-linked List access methods.
-+ */
-+#define DWC_SLIST_FIRST(head) ((head)->slh_first)
-+#define DWC_SLIST_END(head) NULL
-+#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
-+#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
-+
-+#define DWC_SLIST_FOREACH(var, head, field) \
-+ for((var) = SLIST_FIRST(head); \
-+ (var) != SLIST_END(head); \
-+ (var) = SLIST_NEXT(var, field))
-+
-+#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
-+ for((varp) = &SLIST_FIRST((head)); \
-+ ((var) = *(varp)) != SLIST_END(head); \
-+ (varp) = &SLIST_NEXT((var), field))
-+
-+/*
-+ * Singly-linked List functions.
-+ */
-+#define DWC_SLIST_INIT(head) { \
-+ SLIST_FIRST(head) = SLIST_END(head); \
-+}
-+
-+#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
-+ (elm)->field.sle_next = (slistelm)->field.sle_next; \
-+ (slistelm)->field.sle_next = (elm); \
-+} while (0)
-+
-+#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
-+ (elm)->field.sle_next = (head)->slh_first; \
-+ (head)->slh_first = (elm); \
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
-+ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
-+ (head)->slh_first = (head)->slh_first->field.sle_next; \
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
-+ if ((head)->slh_first == (elm)) { \
-+ SLIST_REMOVE_HEAD((head), field); \
-+ } \
-+ else { \
-+ struct type *curelm = (head)->slh_first; \
-+ while( curelm->field.sle_next != (elm) ) \
-+ curelm = curelm->field.sle_next; \
-+ curelm->field.sle_next = \
-+ curelm->field.sle_next->field.sle_next; \
-+ } \
-+} while (0)
-+
-+/*
-+ * Simple queue definitions.
-+ */
-+#define DWC_SIMPLEQ_HEAD(name, type) \
-+struct name { \
-+ struct type *sqh_first; /* first element */ \
-+ struct type **sqh_last; /* addr of last next element */ \
-+}
-+
-+#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
-+ { NULL, &(head).sqh_first }
-+
-+#define DWC_SIMPLEQ_ENTRY(type) \
-+struct { \
-+ struct type *sqe_next; /* next element */ \
-+}
-+
-+/*
-+ * Simple queue access methods.
-+ */
-+#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
-+#define DWC_SIMPLEQ_END(head) NULL
-+#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
-+#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
-+
-+#define DWC_SIMPLEQ_FOREACH(var, head, field) \
-+ for((var) = SIMPLEQ_FIRST(head); \
-+ (var) != SIMPLEQ_END(head); \
-+ (var) = SIMPLEQ_NEXT(var, field))
-+
-+/*
-+ * Simple queue functions.
-+ */
-+#define DWC_SIMPLEQ_INIT(head) do { \
-+ (head)->sqh_first = NULL; \
-+ (head)->sqh_last = &(head)->sqh_first; \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
-+ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
-+ (head)->sqh_last = &(elm)->field.sqe_next; \
-+ (head)->sqh_first = (elm); \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
-+ (elm)->field.sqe_next = NULL; \
-+ *(head)->sqh_last = (elm); \
-+ (head)->sqh_last = &(elm)->field.sqe_next; \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
-+ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
-+ (head)->sqh_last = &(elm)->field.sqe_next; \
-+ (listelm)->field.sqe_next = (elm); \
-+} while (0)
-+
-+#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
-+ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
-+ (head)->sqh_last = &(head)->sqh_first; \
-+} while (0)
-+
-+/*
-+ * Tail queue definitions.
-+ */
-+#define DWC_TAILQ_HEAD(name, type) \
-+struct name { \
-+ struct type *tqh_first; /* first element */ \
-+ struct type **tqh_last; /* addr of last next element */ \
-+}
-+
-+#define DWC_TAILQ_HEAD_INITIALIZER(head) \
-+ { NULL, &(head).tqh_first }
-+
-+#define DWC_TAILQ_ENTRY(type) \
-+struct { \
-+ struct type *tqe_next; /* next element */ \
-+ struct type **tqe_prev; /* address of previous next element */ \
-+}
-+
-+/*
-+ * tail queue access methods
-+ */
-+#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
-+#define DWC_TAILQ_END(head) NULL
-+#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-+#define DWC_TAILQ_LAST(head, headname) \
-+ (*(((struct headname *)((head)->tqh_last))->tqh_last))
-+/* XXX */
-+#define DWC_TAILQ_PREV(elm, headname, field) \
-+ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-+#define DWC_TAILQ_EMPTY(head) \
-+ (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
-+
-+#define DWC_TAILQ_FOREACH(var, head, field) \
-+ for ((var) = DWC_TAILQ_FIRST(head); \
-+ (var) != DWC_TAILQ_END(head); \
-+ (var) = DWC_TAILQ_NEXT(var, field))
-+
-+#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
-+ for ((var) = DWC_TAILQ_LAST(head, headname); \
-+ (var) != DWC_TAILQ_END(head); \
-+ (var) = DWC_TAILQ_PREV(var, headname, field))
-+
-+/*
-+ * Tail queue functions.
-+ */
-+#define DWC_TAILQ_INIT(head) do { \
-+ (head)->tqh_first = NULL; \
-+ (head)->tqh_last = &(head)->tqh_first; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
-+ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
-+ (head)->tqh_first->field.tqe_prev = \
-+ &(elm)->field.tqe_next; \
-+ else \
-+ (head)->tqh_last = &(elm)->field.tqe_next; \
-+ (head)->tqh_first = (elm); \
-+ (elm)->field.tqe_prev = &(head)->tqh_first; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
-+ (elm)->field.tqe_next = NULL; \
-+ (elm)->field.tqe_prev = (head)->tqh_last; \
-+ *(head)->tqh_last = (elm); \
-+ (head)->tqh_last = &(elm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
-+ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
-+ (elm)->field.tqe_next->field.tqe_prev = \
-+ &(elm)->field.tqe_next; \
-+ else \
-+ (head)->tqh_last = &(elm)->field.tqe_next; \
-+ (listelm)->field.tqe_next = (elm); \
-+ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
-+ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
-+ (elm)->field.tqe_next = (listelm); \
-+ *(listelm)->field.tqe_prev = (elm); \
-+ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_REMOVE(head, elm, field) do { \
-+ if (((elm)->field.tqe_next) != NULL) \
-+ (elm)->field.tqe_next->field.tqe_prev = \
-+ (elm)->field.tqe_prev; \
-+ else \
-+ (head)->tqh_last = (elm)->field.tqe_prev; \
-+ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
-+} while (0)
-+
-+#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
-+ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
-+ (elm2)->field.tqe_next->field.tqe_prev = \
-+ &(elm2)->field.tqe_next; \
-+ else \
-+ (head)->tqh_last = &(elm2)->field.tqe_next; \
-+ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
-+ *(elm2)->field.tqe_prev = (elm2); \
-+} while (0)
-+
-+/*
-+ * Circular queue definitions.
-+ */
-+#define DWC_CIRCLEQ_HEAD(name, type) \
-+struct name { \
-+ struct type *cqh_first; /* first element */ \
-+ struct type *cqh_last; /* last element */ \
-+}
-+
-+#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
-+ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
-+
-+#define DWC_CIRCLEQ_ENTRY(type) \
-+struct { \
-+ struct type *cqe_next; /* next element */ \
-+ struct type *cqe_prev; /* previous element */ \
-+}
-+
-+/*
-+ * Circular queue access methods
-+ */
-+#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
-+#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
-+#define DWC_CIRCLEQ_END(head) ((void *)(head))
-+#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
-+#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
-+#define DWC_CIRCLEQ_EMPTY(head) \
-+ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
-+
-+#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
-+
-+#define DWC_CIRCLEQ_FOREACH(var, head, field) \
-+ for((var) = DWC_CIRCLEQ_FIRST(head); \
-+ (var) != DWC_CIRCLEQ_END(head); \
-+ (var) = DWC_CIRCLEQ_NEXT(var, field))
-+
-+#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
-+ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
-+ (var) != DWC_CIRCLEQ_END(head); \
-+ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
-+
-+#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
-+ for((var) = DWC_CIRCLEQ_LAST(head); \
-+ (var) != DWC_CIRCLEQ_END(head); \
-+ (var) = DWC_CIRCLEQ_PREV(var, field))
-+
-+/*
-+ * Circular queue functions.
-+ */
-+#define DWC_CIRCLEQ_INIT(head) do { \
-+ (head)->cqh_first = DWC_CIRCLEQ_END(head); \
-+ (head)->cqh_last = DWC_CIRCLEQ_END(head); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
-+ (elm)->field.cqe_next = NULL; \
-+ (elm)->field.cqe_prev = NULL; \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
-+ (elm)->field.cqe_next = (listelm)->field.cqe_next; \
-+ (elm)->field.cqe_prev = (listelm); \
-+ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_last = (elm); \
-+ else \
-+ (listelm)->field.cqe_next->field.cqe_prev = (elm); \
-+ (listelm)->field.cqe_next = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
-+ (elm)->field.cqe_next = (listelm); \
-+ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
-+ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_first = (elm); \
-+ else \
-+ (listelm)->field.cqe_prev->field.cqe_next = (elm); \
-+ (listelm)->field.cqe_prev = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
-+ (elm)->field.cqe_next = (head)->cqh_first; \
-+ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
-+ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_last = (elm); \
-+ else \
-+ (head)->cqh_first->field.cqe_prev = (elm); \
-+ (head)->cqh_first = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
-+ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
-+ (elm)->field.cqe_prev = (head)->cqh_last; \
-+ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_first = (elm); \
-+ else \
-+ (head)->cqh_last->field.cqe_next = (elm); \
-+ (head)->cqh_last = (elm); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
-+ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_last = (elm)->field.cqe_prev; \
-+ else \
-+ (elm)->field.cqe_next->field.cqe_prev = \
-+ (elm)->field.cqe_prev; \
-+ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
-+ (head)->cqh_first = (elm)->field.cqe_next; \
-+ else \
-+ (elm)->field.cqe_prev->field.cqe_next = \
-+ (elm)->field.cqe_next; \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
-+ DWC_CIRCLEQ_REMOVE(head, elm, field); \
-+ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
-+ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
-+ DWC_CIRCLEQ_END(head)) \
-+ (head).cqh_last = (elm2); \
-+ else \
-+ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \
-+ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
-+ DWC_CIRCLEQ_END(head)) \
-+ (head).cqh_first = (elm2); \
-+ else \
-+ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \
-+} while (0)
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_LIST_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_mem.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_mem.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,245 @@
-+/* Memory Debugging */
-+#ifdef DWC_DEBUG_MEMORY
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+struct allocation {
-+ void *addr;
-+ void *ctx;
-+ char *func;
-+ int line;
-+ uint32_t size;
-+ int dma;
-+ DWC_CIRCLEQ_ENTRY(allocation) entry;
-+};
-+
-+DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
-+
-+struct allocation_manager {
-+ void *mem_ctx;
-+ struct allocation_queue allocations;
-+
-+ /* statistics */
-+ int num;
-+ int num_freed;
-+ int num_active;
-+ uint32_t total;
-+ uint32_t cur;
-+ uint32_t max;
-+};
-+
-+static struct allocation_manager *manager = NULL;
-+
-+static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
-+ int dma)
-+{
-+ struct allocation *a;
-+
-+ DWC_ASSERT(manager != NULL, "manager not allocated");
-+
-+ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
-+ if (!a) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
-+ if (!a->func) {
-+ __DWC_FREE(manager->mem_ctx, a);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
-+ a->addr = addr;
-+ a->ctx = ctx;
-+ a->line = line;
-+ a->size = size;
-+ a->dma = dma;
-+ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
-+
-+ /* Update stats */
-+ manager->num++;
-+ manager->num_active++;
-+ manager->total += size;
-+ manager->cur += size;
-+
-+ if (manager->max < manager->cur) {
-+ manager->max = manager->cur;
-+ }
-+
-+ return 0;
-+}
-+
-+static struct allocation *find_allocation(void *ctx, void *addr)
-+{
-+ struct allocation *a;
-+
-+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+ if (a->ctx == ctx && a->addr == addr) {
-+ return a;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+static void free_allocation(void *ctx, void *addr, char const *func, int line)
-+{
-+ struct allocation *a = find_allocation(ctx, addr);
-+
-+ if (!a) {
-+ DWC_ASSERT(0,
-+ "Free of address %p that was never allocated or already freed %s:%d",
-+ addr, func, line);
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
-+
-+ manager->num_active--;
-+ manager->num_freed++;
-+ manager->cur -= a->size;
-+ __DWC_FREE(manager->mem_ctx, a->func);
-+ __DWC_FREE(manager->mem_ctx, a);
-+}
-+
-+int dwc_memory_debug_start(void *mem_ctx)
-+{
-+ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
-+
-+ if (manager) {
-+ return -DWC_E_BUSY;
-+ }
-+
-+ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
-+ if (!manager) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&manager->allocations);
-+ manager->mem_ctx = mem_ctx;
-+ manager->num = 0;
-+ manager->num_freed = 0;
-+ manager->num_active = 0;
-+ manager->total = 0;
-+ manager->cur = 0;
-+ manager->max = 0;
-+
-+ return 0;
-+}
-+
-+void dwc_memory_debug_stop(void)
-+{
-+ struct allocation *a;
-+
-+ dwc_memory_debug_report();
-+
-+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
-+ free_allocation(a->ctx, a->addr, NULL, -1);
-+ }
-+
-+ __DWC_FREE(manager->mem_ctx, manager);
-+}
-+
-+void dwc_memory_debug_report(void)
-+{
-+ struct allocation *a;
-+
-+ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
-+ DWC_PRINTF("Num Allocations = %d\n", manager->num);
-+ DWC_PRINTF("Freed = %d\n", manager->num_freed);
-+ DWC_PRINTF("Active = %d\n", manager->num_active);
-+ DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
-+ DWC_PRINTF("Total Memory Used = %d\n", manager->total);
-+ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
-+ DWC_PRINTF("Unfreed allocations:\n");
-+
-+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n",
-+ a->addr, a->size, a->func, a->line, a->dma);
-+ }
-+}
-+
-+/* The replacement functions */
-+void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
-+{
-+ void *addr = __DWC_ALLOC(mem_ctx, size);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
-+ __DWC_FREE(mem_ctx, addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
-+ int line)
-+{
-+ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
-+ __DWC_FREE(mem_ctx, addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
-+{
-+ free_allocation(mem_ctx, addr, func, line);
-+ __DWC_FREE(mem_ctx, addr);
-+}
-+
-+void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+ char const *func, int line)
-+{
-+ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
-+ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
-+ dwc_dma_t *dma_addr, char const *func, int line)
-+{
-+ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
-+
-+ if (!addr) {
-+ return NULL;
-+ }
-+
-+ if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
-+ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
-+ return NULL;
-+ }
-+
-+ return addr;
-+}
-+
-+void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
-+ dwc_dma_t dma_addr, char const *func, int line)
-+{
-+ free_allocation(dma_ctx, virt_addr, func, line);
-+ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
-+}
-+
-+#endif /* DWC_DEBUG_MEMORY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_modpow.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_modpow.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,636 @@
-+/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows.
-+ *
-+ * PuTTY is copyright 1997-2007 Simon Tatham.
-+ *
-+ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
-+ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
-+ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
-+ * Kuhn, and CORE SDI S.A.
-+ *
-+ * Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation files
-+ * (the "Software"), to deal in the Software without restriction,
-+ * including without limitation the rights to use, copy, modify, merge,
-+ * publish, distribute, sublicense, and/or sell copies of the Software,
-+ * and to permit persons to whom the Software is furnished to do so,
-+ * subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
-+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
-+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifdef DWC_CRYPTOLIB
-+
-+#ifndef CONFIG_MACH_IPMATE
-+
-+#include "dwc_modpow.h"
-+
-+#define BIGNUM_INT_MASK 0xFFFFFFFFUL
-+#define BIGNUM_TOP_BIT 0x80000000UL
-+#define BIGNUM_INT_BITS 32
-+
-+
-+static void *snmalloc(void *mem_ctx, size_t n, size_t size)
-+{
-+ void *p;
-+ size *= n;
-+ if (size == 0) size = 1;
-+ p = dwc_alloc(mem_ctx, size);
-+ return p;
-+}
-+
-+#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
-+#define sfree dwc_free
-+
-+/*
-+ * Usage notes:
-+ * * Do not call the DIVMOD_WORD macro with expressions such as array
-+ * subscripts, as some implementations object to this (see below).
-+ * * Note that none of the division methods below will cope if the
-+ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
-+ * to avoid this case.
-+ * If this condition occurs, in the case of the x86 DIV instruction,
-+ * an overflow exception will occur, which (according to a correspondent)
-+ * will manifest on Windows as something like
-+ * 0xC0000095: Integer overflow
-+ * The C variant won't give the right answer, either.
-+ */
-+
-+#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
-+
-+#if defined __GNUC__ && defined __i386__
-+#define DIVMOD_WORD(q, r, hi, lo, w) \
-+ __asm__("div %2" : \
-+ "=d" (r), "=a" (q) : \
-+ "r" (w), "d" (hi), "a" (lo))
-+#else
-+#define DIVMOD_WORD(q, r, hi, lo, w) do { \
-+ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
-+ q = n / w; \
-+ r = n % w; \
-+} while (0)
-+#endif
-+
-+// q = n / w;
-+// r = n % w;
-+
-+#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
-+
-+#define BIGNUM_INTERNAL
-+
-+static Bignum newbn(void *mem_ctx, int length)
-+{
-+ Bignum b = snewn(mem_ctx, length + 1, BignumInt);
-+ //if (!b)
-+ //abort(); /* FIXME */
-+ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
-+ b[0] = length;
-+ return b;
-+}
-+
-+void freebn(void *mem_ctx, Bignum b)
-+{
-+ /*
-+ * Burn the evidence, just in case.
-+ */
-+ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
-+ sfree(mem_ctx, b);
-+}
-+
-+/*
-+ * Compute c = a * b.
-+ * Input is in the first len words of a and b.
-+ * Result is returned in the first 2*len words of c.
-+ */
-+static void internal_mul(BignumInt *a, BignumInt *b,
-+ BignumInt *c, int len)
-+{
-+ int i, j;
-+ BignumDblInt t;
-+
-+ for (j = 0; j < 2 * len; j++)
-+ c[j] = 0;
-+
-+ for (i = len - 1; i >= 0; i--) {
-+ t = 0;
-+ for (j = len - 1; j >= 0; j--) {
-+ t += MUL_WORD(a[i], (BignumDblInt) b[j]);
-+ t += (BignumDblInt) c[i + j + 1];
-+ c[i + j + 1] = (BignumInt) t;
-+ t = t >> BIGNUM_INT_BITS;
-+ }
-+ c[i] = (BignumInt) t;
-+ }
-+}
-+
-+static void internal_add_shifted(BignumInt *number,
-+ unsigned n, int shift)
-+{
-+ int word = 1 + (shift / BIGNUM_INT_BITS);
-+ int bshift = shift % BIGNUM_INT_BITS;
-+ BignumDblInt addend;
-+
-+ addend = (BignumDblInt)n << bshift;
-+
-+ while (addend) {
-+ addend += number[word];
-+ number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
-+ addend >>= BIGNUM_INT_BITS;
-+ word++;
-+ }
-+}
-+
-+/*
-+ * Compute a = a % m.
-+ * Input in first alen words of a and first mlen words of m.
-+ * Output in first alen words of a
-+ * (of which first alen-mlen words will be zero).
-+ * The MSW of m MUST have its high bit set.
-+ * Quotient is accumulated in the `quotient' array, which is a Bignum
-+ * rather than the internal bigendian format. Quotient parts are shifted
-+ * left by `qshift' before adding into quot.
-+ */
-+static void internal_mod(BignumInt *a, int alen,
-+ BignumInt *m, int mlen,
-+ BignumInt *quot, int qshift)
-+{
-+ BignumInt m0, m1;
-+ unsigned int h;
-+ int i, k;
-+
-+ m0 = m[0];
-+ if (mlen > 1)
-+ m1 = m[1];
-+ else
-+ m1 = 0;
-+
-+ for (i = 0; i <= alen - mlen; i++) {
-+ BignumDblInt t;
-+ unsigned int q, r, c, ai1;
-+
-+ if (i == 0) {
-+ h = 0;
-+ } else {
-+ h = a[i - 1];
-+ a[i - 1] = 0;
-+ }
-+
-+ if (i == alen - 1)
-+ ai1 = 0;
-+ else
-+ ai1 = a[i + 1];
-+
-+ /* Find q = h:a[i] / m0 */
-+ if (h >= m0) {
-+ /*
-+ * Special case.
-+ *
-+ * To illustrate it, suppose a BignumInt is 8 bits, and
-+ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
-+ * our initial division will be 0xA123 / 0xA1, which
-+ * will give a quotient of 0x100 and a divide overflow.
-+ * However, the invariants in this division algorithm
-+ * are not violated, since the full number A1:23:... is
-+ * _less_ than the quotient prefix A1:B2:... and so the
-+ * following correction loop would have sorted it out.
-+ *
-+ * In this situation we set q to be the largest
-+ * quotient we _can_ stomach (0xFF, of course).
-+ */
-+ q = BIGNUM_INT_MASK;
-+ } else {
-+ /* Macro doesn't want an array subscript expression passed
-+ * into it (see definition), so use a temporary. */
-+ BignumInt tmplo = a[i];
-+ DIVMOD_WORD(q, r, h, tmplo, m0);
-+
-+ /* Refine our estimate of q by looking at
-+ h:a[i]:a[i+1] / m0:m1 */
-+ t = MUL_WORD(m1, q);
-+ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
-+ q--;
-+ t -= m1;
-+ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */
-+ if (r >= (BignumDblInt) m0 &&
-+ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
-+ }
-+ }
-+
-+ /* Subtract q * m from a[i...] */
-+ c = 0;
-+ for (k = mlen - 1; k >= 0; k--) {
-+ t = MUL_WORD(q, m[k]);
-+ t += c;
-+ c = (unsigned)(t >> BIGNUM_INT_BITS);
-+ if ((BignumInt) t > a[i + k])
-+ c++;
-+ a[i + k] -= (BignumInt) t;
-+ }
-+
-+ /* Add back m in case of borrow */
-+ if (c != h) {
-+ t = 0;
-+ for (k = mlen - 1; k >= 0; k--) {
-+ t += m[k];
-+ t += a[i + k];
-+ a[i + k] = (BignumInt) t;
-+ t = t >> BIGNUM_INT_BITS;
-+ }
-+ q--;
-+ }
-+ if (quot)
-+ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
-+ }
-+}
-+
-+/*
-+ * Compute p % mod.
-+ * The most significant word of mod MUST be non-zero.
-+ * We assume that the result array is the same size as the mod array.
-+ * We optionally write out a quotient if `quotient' is non-NULL.
-+ * We can avoid writing out the result if `result' is NULL.
-+ */
-+void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
-+{
-+ BignumInt *n, *m;
-+ int mshift;
-+ int plen, mlen, i, j;
-+
-+ /* Allocate m of size mlen, copy mod to m */
-+ /* We use big endian internally */
-+ mlen = mod[0];
-+ m = snewn(mem_ctx, mlen, BignumInt);
-+ //if (!m)
-+ //abort(); /* FIXME */
-+ for (j = 0; j < mlen; j++)
-+ m[j] = mod[mod[0] - j];
-+
-+ /* Shift m left to make msb bit set */
-+ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
-+ if ((m[0] << mshift) & BIGNUM_TOP_BIT)
-+ break;
-+ if (mshift) {
-+ for (i = 0; i < mlen - 1; i++)
-+ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
-+ m[mlen - 1] = m[mlen - 1] << mshift;
-+ }
-+
-+ plen = p[0];
-+ /* Ensure plen > mlen */
-+ if (plen <= mlen)
-+ plen = mlen + 1;
-+
-+ /* Allocate n of size plen, copy p to n */
-+ n = snewn(mem_ctx, plen, BignumInt);
-+ //if (!n)
-+ //abort(); /* FIXME */
-+ for (j = 0; j < plen; j++)
-+ n[j] = 0;
-+ for (j = 1; j <= (int)p[0]; j++)
-+ n[plen - j] = p[j];
-+
-+ /* Main computation */
-+ internal_mod(n, plen, m, mlen, quotient, mshift);
-+
-+ /* Fixup result in case the modulus was shifted */
-+ if (mshift) {
-+ for (i = plen - mlen - 1; i < plen - 1; i++)
-+ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
-+ n[plen - 1] = n[plen - 1] << mshift;
-+ internal_mod(n, plen, m, mlen, quotient, 0);
-+ for (i = plen - 1; i >= plen - mlen; i--)
-+ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
-+ }
-+
-+ /* Copy result to buffer */
-+ if (result) {
-+ for (i = 1; i <= (int)result[0]; i++) {
-+ int j = plen - i;
-+ result[i] = j >= 0 ? n[j] : 0;
-+ }
-+ }
-+
-+ /* Free temporary arrays */
-+ for (i = 0; i < mlen; i++)
-+ m[i] = 0;
-+ sfree(mem_ctx, m);
-+ for (i = 0; i < plen; i++)
-+ n[i] = 0;
-+ sfree(mem_ctx, n);
-+}
-+
-+/*
-+ * Simple remainder.
-+ */
-+Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
-+{
-+ Bignum r = newbn(mem_ctx, b[0]);
-+ bigdivmod(mem_ctx, a, b, r, NULL);
-+ return r;
-+}
-+
-+/*
-+ * Compute (base ^ exp) % mod.
-+ */
-+Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
-+{
-+ BignumInt *a, *b, *n, *m;
-+ int mshift;
-+ int mlen, i, j;
-+ Bignum base, result;
-+
-+ /*
-+ * The most significant word of mod needs to be non-zero. It
-+ * should already be, but let's make sure.
-+ */
-+ //assert(mod[mod[0]] != 0);
-+
-+ /*
-+ * Make sure the base is smaller than the modulus, by reducing
-+ * it modulo the modulus if not.
-+ */
-+ base = bigmod(mem_ctx, base_in, mod);
-+
-+ /* Allocate m of size mlen, copy mod to m */
-+ /* We use big endian internally */
-+ mlen = mod[0];
-+ m = snewn(mem_ctx, mlen, BignumInt);
-+ //if (!m)
-+ //abort(); /* FIXME */
-+ for (j = 0; j < mlen; j++)
-+ m[j] = mod[mod[0] - j];
-+
-+ /* Shift m left to make msb bit set */
-+ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
-+ if ((m[0] << mshift) & BIGNUM_TOP_BIT)
-+ break;
-+ if (mshift) {
-+ for (i = 0; i < mlen - 1; i++)
-+ m[i] =
-+ (m[i] << mshift) | (m[i + 1] >>
-+ (BIGNUM_INT_BITS - mshift));
-+ m[mlen - 1] = m[mlen - 1] << mshift;
-+ }
-+
-+ /* Allocate n of size mlen, copy base to n */
-+ n = snewn(mem_ctx, mlen, BignumInt);
-+ //if (!n)
-+ //abort(); /* FIXME */
-+ i = mlen - base[0];
-+ for (j = 0; j < i; j++)
-+ n[j] = 0;
-+ for (j = 0; j < base[0]; j++)
-+ n[i + j] = base[base[0] - j];
-+
-+ /* Allocate a and b of size 2*mlen. Set a = 1 */
-+ a = snewn(mem_ctx, 2 * mlen, BignumInt);
-+ //if (!a)
-+ //abort(); /* FIXME */
-+ b = snewn(mem_ctx, 2 * mlen, BignumInt);
-+ //if (!b)
-+ //abort(); /* FIXME */
-+ for (i = 0; i < 2 * mlen; i++)
-+ a[i] = 0;
-+ a[2 * mlen - 1] = 1;
-+
-+ /* Skip leading zero bits of exp. */
-+ i = 0;
-+ j = BIGNUM_INT_BITS - 1;
-+ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
-+ j--;
-+ if (j < 0) {
-+ i++;
-+ j = BIGNUM_INT_BITS - 1;
-+ }
-+ }
-+
-+ /* Main computation */
-+ while (i < exp[0]) {
-+ while (j >= 0) {
-+ internal_mul(a + mlen, a + mlen, b, mlen);
-+ internal_mod(b, mlen * 2, m, mlen, NULL, 0);
-+ if ((exp[exp[0] - i] & (1 << j)) != 0) {
-+ internal_mul(b + mlen, n, a, mlen);
-+ internal_mod(a, mlen * 2, m, mlen, NULL, 0);
-+ } else {
-+ BignumInt *t;
-+ t = a;
-+ a = b;
-+ b = t;
-+ }
-+ j--;
-+ }
-+ i++;
-+ j = BIGNUM_INT_BITS - 1;
-+ }
-+
-+ /* Fixup result in case the modulus was shifted */
-+ if (mshift) {
-+ for (i = mlen - 1; i < 2 * mlen - 1; i++)
-+ a[i] =
-+ (a[i] << mshift) | (a[i + 1] >>
-+ (BIGNUM_INT_BITS - mshift));
-+ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
-+ internal_mod(a, mlen * 2, m, mlen, NULL, 0);
-+ for (i = 2 * mlen - 1; i >= mlen; i--)
-+ a[i] =
-+ (a[i] >> mshift) | (a[i - 1] <<
-+ (BIGNUM_INT_BITS - mshift));
-+ }
-+
-+ /* Copy result to buffer */
-+ result = newbn(mem_ctx, mod[0]);
-+ for (i = 0; i < mlen; i++)
-+ result[result[0] - i] = a[i + mlen];
-+ while (result[0] > 1 && result[result[0]] == 0)
-+ result[0]--;
-+
-+ /* Free temporary arrays */
-+ for (i = 0; i < 2 * mlen; i++)
-+ a[i] = 0;
-+ sfree(mem_ctx, a);
-+ for (i = 0; i < 2 * mlen; i++)
-+ b[i] = 0;
-+ sfree(mem_ctx, b);
-+ for (i = 0; i < mlen; i++)
-+ m[i] = 0;
-+ sfree(mem_ctx, m);
-+ for (i = 0; i < mlen; i++)
-+ n[i] = 0;
-+ sfree(mem_ctx, n);
-+
-+ freebn(mem_ctx, base);
-+
-+ return result;
-+}
-+
-+
-+#ifdef UNITTEST
-+
-+static __u32 dh_p[] = {
-+ 96,
-+ 0xFFFFFFFF,
-+ 0xFFFFFFFF,
-+ 0xA93AD2CA,
-+ 0x4B82D120,
-+ 0xE0FD108E,
-+ 0x43DB5BFC,
-+ 0x74E5AB31,
-+ 0x08E24FA0,
-+ 0xBAD946E2,
-+ 0x770988C0,
-+ 0x7A615D6C,
-+ 0xBBE11757,
-+ 0x177B200C,
-+ 0x521F2B18,
-+ 0x3EC86A64,
-+ 0xD8760273,
-+ 0xD98A0864,
-+ 0xF12FFA06,
-+ 0x1AD2EE6B,
-+ 0xCEE3D226,
-+ 0x4A25619D,
-+ 0x1E8C94E0,
-+ 0xDB0933D7,
-+ 0xABF5AE8C,
-+ 0xA6E1E4C7,
-+ 0xB3970F85,
-+ 0x5D060C7D,
-+ 0x8AEA7157,
-+ 0x58DBEF0A,
-+ 0xECFB8504,
-+ 0xDF1CBA64,
-+ 0xA85521AB,
-+ 0x04507A33,
-+ 0xAD33170D,
-+ 0x8AAAC42D,
-+ 0x15728E5A,
-+ 0x98FA0510,
-+ 0x15D22618,
-+ 0xEA956AE5,
-+ 0x3995497C,
-+ 0x95581718,
-+ 0xDE2BCBF6,
-+ 0x6F4C52C9,
-+ 0xB5C55DF0,
-+ 0xEC07A28F,
-+ 0x9B2783A2,
-+ 0x180E8603,
-+ 0xE39E772C,
-+ 0x2E36CE3B,
-+ 0x32905E46,
-+ 0xCA18217C,
-+ 0xF1746C08,
-+ 0x4ABC9804,
-+ 0x670C354E,
-+ 0x7096966D,
-+ 0x9ED52907,
-+ 0x208552BB,
-+ 0x1C62F356,
-+ 0xDCA3AD96,
-+ 0x83655D23,
-+ 0xFD24CF5F,
-+ 0x69163FA8,
-+ 0x1C55D39A,
-+ 0x98DA4836,
-+ 0xA163BF05,
-+ 0xC2007CB8,
-+ 0xECE45B3D,
-+ 0x49286651,
-+ 0x7C4B1FE6,
-+ 0xAE9F2411,
-+ 0x5A899FA5,
-+ 0xEE386BFB,
-+ 0xF406B7ED,
-+ 0x0BFF5CB6,
-+ 0xA637ED6B,
-+ 0xF44C42E9,
-+ 0x625E7EC6,
-+ 0xE485B576,
-+ 0x6D51C245,
-+ 0x4FE1356D,
-+ 0xF25F1437,
-+ 0x302B0A6D,
-+ 0xCD3A431B,
-+ 0xEF9519B3,
-+ 0x8E3404DD,
-+ 0x514A0879,
-+ 0x3B139B22,
-+ 0x020BBEA6,
-+ 0x8A67CC74,
-+ 0x29024E08,
-+ 0x80DC1CD1,
-+ 0xC4C6628B,
-+ 0x2168C234,
-+ 0xC90FDAA2,
-+ 0xFFFFFFFF,
-+ 0xFFFFFFFF,
-+};
-+
-+static __u32 dh_a[] = {
-+ 8,
-+ 0xdf367516,
-+ 0x86459caa,
-+ 0xe2d459a4,
-+ 0xd910dae0,
-+ 0x8a8b5e37,
-+ 0x67ab31c6,
-+ 0xf0b55ea9,
-+ 0x440051d6,
-+};
-+
-+static __u32 dh_b[] = {
-+ 8,
-+ 0xded92656,
-+ 0xe07a048a,
-+ 0x6fa452cd,
-+ 0x2df89d30,
-+ 0xc75f1b0f,
-+ 0x8ce3578f,
-+ 0x7980a324,
-+ 0x5daec786,
-+};
-+
-+static __u32 dh_g[] = {
-+ 1,
-+ 2,
-+};
-+
-+int main(void)
-+{
-+ int i;
-+ __u32 *k;
-+ k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
-+
-+ printf("\n\n");
-+ for (i=0; i<k[0]; i++) {
-+ __u32 word32 = k[k[0] - i];
-+ __u16 l = word32 & 0xffff;
-+ __u16 m = (word32 & 0xffff0000) >> 16;
-+ printf("%04x %04x ", m, l);
-+ if (!((i + 1)%13)) printf("\n");
-+ }
-+ printf("\n\n");
-+
-+ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
-+ printf("PASS\n\n");
-+ }
-+ else {
-+ printf("FAIL\n\n");
-+ }
-+
-+}
-+
-+#endif /* UNITTEST */
-+
-+#endif /* CONFIG_MACH_IPMATE */
-+
-+#endif /*DWC_CRYPTOLIB */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_modpow.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_modpow.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,34 @@
-+/*
-+ * dwc_modpow.h
-+ * See dwc_modpow.c for license and changes
-+ */
-+#ifndef _DWC_MODPOW_H
-+#define _DWC_MODPOW_H
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * This file defines the module exponentiation function which is only used
-+ * internally by the DWC UWB modules for calculation of PKs during numeric
-+ * association. The routine is taken from the PUTTY, an open source terminal
-+ * emulator. The PUTTY License is preserved in the dwc_modpow.c file.
-+ *
-+ */
-+
-+typedef uint32_t BignumInt;
-+typedef uint64_t BignumDblInt;
-+typedef BignumInt *Bignum;
-+
-+/* Compute modular exponentiaion */
-+extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _LINUX_BIGNUM_H */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_notifier.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_notifier.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,319 @@
-+#ifdef DWC_NOTIFYLIB
-+
-+#include "dwc_notifier.h"
-+#include "dwc_list.h"
-+
-+typedef struct dwc_observer {
-+ void *observer;
-+ dwc_notifier_callback_t callback;
-+ void *data;
-+ char *notification;
-+ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
-+} observer_t;
-+
-+DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
-+
-+typedef struct dwc_notifier {
-+ void *mem_ctx;
-+ void *object;
-+ struct observer_queue observers;
-+ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
-+} notifier_t;
-+
-+DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
-+
-+typedef struct manager {
-+ void *mem_ctx;
-+ void *wkq_ctx;
-+ dwc_workq_t *wq;
-+// dwc_mutex_t *mutex;
-+ struct notifier_queue notifiers;
-+} manager_t;
-+
-+static manager_t *manager = NULL;
-+
-+static int create_manager(void *mem_ctx, void *wkq_ctx)
-+{
-+ manager = dwc_alloc(mem_ctx, sizeof(manager_t));
-+ if (!manager) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&manager->notifiers);
-+
-+ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
-+ if (!manager->wq) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ return 0;
-+}
-+
-+static void free_manager(void)
-+{
-+ dwc_workq_free(manager->wq);
-+
-+ /* All notifiers must have unregistered themselves before this module
-+ * can be removed. Hitting this assertion indicates a programmer
-+ * error. */
-+ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
-+ "Notification manager being freed before all notifiers have been removed");
-+ dwc_free(manager->mem_ctx, manager);
-+}
-+
-+#ifdef DEBUG
-+static void dump_manager(void)
-+{
-+ notifier_t *n;
-+ observer_t *o;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ DWC_DEBUG("List of all notifiers and observers:\n");
-+ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
-+ DWC_DEBUG("Notifier %p has observers:\n", n->object);
-+ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
-+ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification);
-+ }
-+ }
-+}
-+#else
-+#define dump_manager(...)
-+#endif
-+
-+static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
-+ dwc_notifier_callback_t callback, void *data)
-+{
-+ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
-+
-+ if (!new_observer) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
-+ new_observer->observer = observer;
-+ new_observer->notification = notification;
-+ new_observer->callback = callback;
-+ new_observer->data = data;
-+ return new_observer;
-+}
-+
-+static void free_observer(void *mem_ctx, observer_t *observer)
-+{
-+ dwc_free(mem_ctx, observer);
-+}
-+
-+static notifier_t *alloc_notifier(void *mem_ctx, void *object)
-+{
-+ notifier_t *notifier;
-+
-+ if (!object) {
-+ return NULL;
-+ }
-+
-+ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
-+ if (!notifier) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INIT(&notifier->observers);
-+ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
-+
-+ notifier->mem_ctx = mem_ctx;
-+ notifier->object = object;
-+ return notifier;
-+}
-+
-+static void free_notifier(notifier_t *notifier)
-+{
-+ observer_t *observer;
-+
-+ DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
-+ free_observer(notifier->mem_ctx, observer);
-+ }
-+
-+ dwc_free(notifier->mem_ctx, notifier);
-+}
-+
-+static notifier_t *find_notifier(void *object)
-+{
-+ notifier_t *notifier;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ if (!object) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
-+ if (notifier->object == object) {
-+ return notifier;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
-+{
-+ return create_manager(mem_ctx, wkq_ctx);
-+}
-+
-+void dwc_free_notification_manager(void)
-+{
-+ free_manager();
-+}
-+
-+dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
-+{
-+ notifier_t *notifier;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ notifier = find_notifier(object);
-+ if (notifier) {
-+ DWC_ERROR("Notifier %p is already registered\n", object);
-+ return NULL;
-+ }
-+
-+ notifier = alloc_notifier(mem_ctx, object);
-+ if (!notifier) {
-+ return NULL;
-+ }
-+
-+ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
-+
-+ DWC_INFO("Notifier %p registered", object);
-+ dump_manager();
-+
-+ return notifier;
-+}
-+
-+void dwc_unregister_notifier(dwc_notifier_t *notifier)
-+{
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
-+ observer_t *o;
-+
-+ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
-+ DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
-+ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification);
-+ }
-+
-+ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),
-+ "Notifier %p has active observers when removing", notifier);
-+ }
-+
-+ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
-+ free_notifier(notifier);
-+
-+ DWC_INFO("Notifier unregistered");
-+ dump_manager();
-+}
-+
-+/* Add an observer to observe the notifier for a particular state, event, or notification. */
-+int dwc_add_observer(void *observer, void *object, char *notification,
-+ dwc_notifier_callback_t callback, void *data)
-+{
-+ notifier_t *notifier = find_notifier(object);
-+ observer_t *new_observer;
-+
-+ if (!notifier) {
-+ DWC_ERROR("Notifier %p is not found when adding observer\n", object);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
-+ if (!new_observer) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
-+
-+ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
-+ observer, object, notification, callback, data);
-+
-+ dump_manager();
-+ return 0;
-+}
-+
-+int dwc_remove_observer(void *observer)
-+{
-+ notifier_t *n;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
-+ observer_t *o;
-+ observer_t *o2;
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
-+ if (o->observer == observer) {
-+ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
-+ DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
-+ o->observer, n->object, o->notification);
-+ free_observer(n->mem_ctx, o);
-+ }
-+ }
-+ }
-+
-+ dump_manager();
-+ return 0;
-+}
-+
-+typedef struct callback_data {
-+ void *mem_ctx;
-+ dwc_notifier_callback_t cb;
-+ void *observer;
-+ void *data;
-+ void *object;
-+ char *notification;
-+ void *notification_data;
-+} cb_data_t;
-+
-+static void cb_task(void *data)
-+{
-+ cb_data_t *cb = (cb_data_t *)data;
-+
-+ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
-+ dwc_free(cb->mem_ctx, cb);
-+}
-+
-+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
-+{
-+ observer_t *o;
-+
-+ DWC_ASSERT(manager, "Notification manager not found");
-+
-+ DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
-+ int len = DWC_STRLEN(notification);
-+
-+ if (DWC_STRLEN(o->notification) != len) {
-+ continue;
-+ }
-+
-+ if (DWC_STRNCMP(o->notification, notification, len) == 0) {
-+ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
-+
-+ if (!cb_data) {
-+ DWC_ERROR("Failed to allocate callback data\n");
-+ return;
-+ }
-+
-+ cb_data->mem_ctx = notifier->mem_ctx;
-+ cb_data->cb = o->callback;
-+ cb_data->observer = o->observer;
-+ cb_data->data = o->data;
-+ cb_data->object = notifier->object;
-+ cb_data->notification = notification;
-+ cb_data->notification_data = notification_data;
-+ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
-+ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
-+ "Notify callback from %p for Notification %s, to observer %p",
-+ cb_data->object, notification, cb_data->observer);
-+ }
-+ }
-+}
-+
-+#endif /* DWC_NOTIFYLIB */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_notifier.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_notifier.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,122 @@
-+
-+#ifndef __DWC_NOTIFIER_H__
-+#define __DWC_NOTIFIER_H__
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * A simple implementation of the Observer pattern. Any "module" can
-+ * register as an observer or notifier. The notion of "module" is abstract and
-+ * can mean anything used to identify either an observer or notifier. Usually
-+ * it will be a pointer to a data structure which contains some state, ie an
-+ * object.
-+ *
-+ * Before any notifiers can be added, the global notification manager must be
-+ * brought up with dwc_alloc_notification_manager().
-+ * dwc_free_notification_manager() will bring it down and free all resources.
-+ * These would typically be called upon module load and unload. The
-+ * notification manager is a single global instance that handles all registered
-+ * observable modules and observers so this should be done only once.
-+ *
-+ * A module can be observable by using Notifications to publicize some general
-+ * information about it's state or operation. It does not care who listens, or
-+ * even if anyone listens, or what they do with the information. The observable
-+ * modules do not need to know any information about it's observers or their
-+ * interface, or their state or data.
-+ *
-+ * Any module can register to emit Notifications. It should publish a list of
-+ * notifications that it can emit and their behavior, such as when they will get
-+ * triggered, and what information will be provided to the observer. Then it
-+ * should register itself as an observable module. See dwc_register_notifier().
-+ *
-+ * Any module can observe any observable, registered module, provided it has a
-+ * handle to the other module and knows what notifications to observe. See
-+ * dwc_add_observer().
-+ *
-+ * A function of type dwc_notifier_callback_t is called whenever a notification
-+ * is triggered with one or more observers observing it. This function is
-+ * called in it's own process so it may sleep or block if needed. It is
-+ * guaranteed to be called sometime after the notification has occurred and will
-+ * be called once per each time the notification is triggered. It will NOT be
-+ * called in the same process context used to trigger the notification.
-+ *
-+ * @section Limitiations
-+ *
-+ * Keep in mind that Notifications that can be triggered in rapid sucession may
-+ * schedule too many processes too handle. Be aware of this limitation when
-+ * designing to use notifications, and only add notifications for appropriate
-+ * observable information.
-+ *
-+ * Also Notification callbacks are not synchronous. If you need to synchronize
-+ * the behavior between module/observer you must use other means. And perhaps
-+ * that will mean Notifications are not the proper solution.
-+ */
-+
-+struct dwc_notifier;
-+typedef struct dwc_notifier dwc_notifier_t;
-+
-+/** The callback function must be of this type.
-+ *
-+ * @param object This is the object that is being observed.
-+ * @param notification This is the notification that was triggered.
-+ * @param observer This is the observer
-+ * @param notification_data This is notification-specific data that the notifier
-+ * has included in this notification. The value of this should be published in
-+ * the documentation of the observable module with the notifications.
-+ * @param user_data This is any custom data that the observer provided when
-+ * adding itself as an observer to the notification. */
-+typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
-+ void *notification_data, void *user_data);
-+
-+/** Brings up the notification manager. */
-+extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
-+/** Brings down the notification manager. */
-+extern void dwc_free_notification_manager(void);
-+
-+/** This function registers an observable module. A dwc_notifier_t object is
-+ * returned to the observable module. This is an opaque object that is used by
-+ * the observable module to trigger notifications. This object should only be
-+ * accessible to functions that are authorized to trigger notifications for this
-+ * module. Observers do not need this object. */
-+extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
-+
-+/** This function unregisters an observable module. All observers have to be
-+ * removed prior to unregistration. */
-+extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
-+
-+/** Add a module as an observer to the observable module. The observable module
-+ * needs to have previously registered with the notification manager.
-+ *
-+ * @param observer The observer module
-+ * @param object The module to observe
-+ * @param notification The notification to observe
-+ * @param callback The callback function to call
-+ * @param user_data Any additional user data to pass into the callback function */
-+extern int dwc_add_observer(void *observer, void *object, char *notification,
-+ dwc_notifier_callback_t callback, void *user_data);
-+
-+/** Removes the specified observer from all notifications that it is currently
-+ * observing. */
-+extern int dwc_remove_observer(void *observer);
-+
-+/** This function triggers a Notification. It should be called by the
-+ * observable module, or any module or library which the observable module
-+ * allows to trigger notification on it's behalf. Such as the dwc_cc_t.
-+ *
-+ * dwc_notify is a non-blocking function. Callbacks are scheduled called in
-+ * their own process context for each trigger. Callbacks can be blocking.
-+ * dwc_notify can be called from interrupt context if needed.
-+ *
-+ */
-+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* __DWC_NOTIFIER_H__ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_os.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/dwc_os.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,1276 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
-+ * $Revision: #14 $
-+ * $Date: 2010/11/04 $
-+ * $Change: 1621695 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_OS_H_
-+#define _DWC_OS_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * DWC portability library, low level os-wrapper functions
-+ *
-+ */
-+
-+/* These basic types need to be defined by some OS header file or custom header
-+ * file for your specific target architecture.
-+ *
-+ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
-+ *
-+ * Any custom or alternate header file must be added and enabled here.
-+ */
-+
-+#ifdef DWC_LINUX
-+# include <linux/types.h>
-+# ifdef CONFIG_DEBUG_MUTEXES
-+# include <linux/mutex.h>
-+# endif
-+# include <linux/spinlock.h>
-+# include <linux/errno.h>
-+# include <stdarg.h>
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+# include <os_dep.h>
-+#endif
-+
-+
-+/** @name Primitive Types and Values */
-+
-+/** We define a boolean type for consistency. Can be either YES or NO */
-+typedef uint8_t dwc_bool_t;
-+#define YES 1
-+#define NO 0
-+
-+#ifdef DWC_LINUX
-+
-+/** @name Error Codes */
-+#define DWC_E_INVALID EINVAL
-+#define DWC_E_NO_MEMORY ENOMEM
-+#define DWC_E_NO_DEVICE ENODEV
-+#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
-+#define DWC_E_TIMEOUT ETIMEDOUT
-+#define DWC_E_BUSY EBUSY
-+#define DWC_E_AGAIN EAGAIN
-+#define DWC_E_RESTART ERESTART
-+#define DWC_E_ABORT ECONNABORTED
-+#define DWC_E_SHUTDOWN ESHUTDOWN
-+#define DWC_E_NO_DATA ENODATA
-+#define DWC_E_DISCONNECT ECONNRESET
-+#define DWC_E_UNKNOWN EINVAL
-+#define DWC_E_NO_STREAM_RES ENOSR
-+#define DWC_E_COMMUNICATION ECOMM
-+#define DWC_E_OVERFLOW EOVERFLOW
-+#define DWC_E_PROTOCOL EPROTO
-+#define DWC_E_IN_PROGRESS EINPROGRESS
-+#define DWC_E_PIPE EPIPE
-+#define DWC_E_IO EIO
-+#define DWC_E_NO_SPACE ENOSPC
-+
-+#else
-+
-+/** @name Error Codes */
-+#define DWC_E_INVALID 1001
-+#define DWC_E_NO_MEMORY 1002
-+#define DWC_E_NO_DEVICE 1003
-+#define DWC_E_NOT_SUPPORTED 1004
-+#define DWC_E_TIMEOUT 1005
-+#define DWC_E_BUSY 1006
-+#define DWC_E_AGAIN 1007
-+#define DWC_E_RESTART 1008
-+#define DWC_E_ABORT 1009
-+#define DWC_E_SHUTDOWN 1010
-+#define DWC_E_NO_DATA 1011
-+#define DWC_E_DISCONNECT 2000
-+#define DWC_E_UNKNOWN 3000
-+#define DWC_E_NO_STREAM_RES 4001
-+#define DWC_E_COMMUNICATION 4002
-+#define DWC_E_OVERFLOW 4003
-+#define DWC_E_PROTOCOL 4004
-+#define DWC_E_IN_PROGRESS 4005
-+#define DWC_E_PIPE 4006
-+#define DWC_E_IO 4007
-+#define DWC_E_NO_SPACE 4008
-+
-+#endif
-+
-+
-+/** @name Tracing/Logging Functions
-+ *
-+ * These function provide the capability to add tracing, debugging, and error
-+ * messages, as well exceptions as assertions. The WUDEV uses these
-+ * extensively. These could be logged to the main console, the serial port, an
-+ * internal buffer, etc. These functions could also be no-op if they are too
-+ * expensive on your system. By default undefining the DEBUG macro already
-+ * no-ops some of these functions. */
-+
-+/** Returns non-zero if in interrupt context. */
-+extern dwc_bool_t DWC_IN_IRQ(void);
-+#define dwc_in_irq DWC_IN_IRQ
-+
-+/** Returns "IRQ" if DWC_IN_IRQ is true. */
-+static inline char *dwc_irq(void) {
-+ return DWC_IN_IRQ() ? "IRQ" : "";
-+}
-+
-+/** Returns non-zero if in bottom-half context. */
-+extern dwc_bool_t DWC_IN_BH(void);
-+#define dwc_in_bh DWC_IN_BH
-+
-+/** Returns "BH" if DWC_IN_BH is true. */
-+static inline char *dwc_bh(void) {
-+ return DWC_IN_BH() ? "BH" : "";
-+}
-+
-+/**
-+ * A vprintf() clone. Just call vprintf if you've got it.
-+ */
-+extern void DWC_VPRINTF(char *format, va_list args);
-+#define dwc_vprintf DWC_VPRINTF
-+
-+/**
-+ * A vsnprintf() clone. Just call vprintf if you've got it.
-+ */
-+extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
-+#define dwc_vsnprintf DWC_VSNPRINTF
-+
-+/**
-+ * printf() clone. Just call printf if you've go it.
-+ */
-+extern void DWC_PRINTF(char *format, ...)
-+/* This provides compiler level static checking of the parameters if you're
-+ * using GCC. */
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+#define dwc_printf DWC_PRINTF
-+
-+/**
-+ * sprintf() clone. Just call sprintf if you've got it.
-+ */
-+extern int DWC_SPRINTF(char *string, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 2, 3)));
-+#else
-+ ;
-+#endif
-+#define dwc_sprintf DWC_SPRINTF
-+
-+/**
-+ * snprintf() clone. Just call snprintf if you've got it.
-+ */
-+extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 3, 4)));
-+#else
-+ ;
-+#endif
-+#define dwc_snprintf DWC_SNPRINTF
-+
-+/**
-+ * Prints a WARNING message. On systems that don't differentiate between
-+ * warnings and regular log messages, just print it. Indicates that something
-+ * may be wrong with the driver. Works like printf().
-+ *
-+ * Use the DWC_WARN macro to call this function.
-+ */
-+extern void __DWC_WARN(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+
-+/**
-+ * Prints an error message. On systems that don't differentiate between errors
-+ * and regular log messages, just print it. Indicates that something went wrong
-+ * with the driver. Works like printf().
-+ *
-+ * Use the DWC_ERROR macro to call this function.
-+ */
-+extern void __DWC_ERROR(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+
-+/**
-+ * Prints an exception error message and takes some user-defined action such as
-+ * print out a backtrace or trigger a breakpoint. Indicates that something went
-+ * abnormally wrong with the driver such as programmer error, or other
-+ * exceptional condition. It should not be ignored so even on systems without
-+ * printing capability, some action should be taken to notify the developer of
-+ * it. Works like printf().
-+ */
-+extern void DWC_EXCEPTION(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+#define dwc_exception DWC_EXCEPTION
-+
-+#ifndef DWC_OTG_DEBUG_LEV
-+#define DWC_OTG_DEBUG_LEV 0
-+#endif
-+
-+#ifdef DEBUG
-+/**
-+ * Prints out a debug message. Used for logging/trace messages.
-+ *
-+ * Use the DWC_DEBUG macro to call this function
-+ */
-+extern void __DWC_DEBUG(char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 1, 2)));
-+#else
-+ ;
-+#endif
-+#else
-+#define __DWC_DEBUG printk
-+#endif
-+
-+/**
-+ * Prints out a Debug message.
-+ */
-+#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
-+ __func__, dwc_irq(), ## _args)
-+#define dwc_debug DWC_DEBUG
-+/**
-+ * Prints out a Debug message if enabled at compile time.
-+ */
-+#if DWC_OTG_DEBUG_LEV > 0
-+#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
-+#else
-+#define DWC_DEBUGC(_format, _args...)
-+#endif
-+#define dwc_debugc DWC_DEBUGC
-+/**
-+ * Prints out an informative message.
-+ */
-+#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
-+ dwc_irq(), ## _args)
-+#define dwc_info DWC_INFO
-+/**
-+ * Prints out an informative message if enabled at compile time.
-+ */
-+#if DWC_OTG_DEBUG_LEV > 1
-+#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
-+#else
-+#define DWC_INFOC(_format, _args...)
-+#endif
-+#define dwc_infoc DWC_INFOC
-+/**
-+ * Prints out a warning message.
-+ */
-+#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
-+ dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_warn DWC_WARN
-+/**
-+ * Prints out an error message.
-+ */
-+#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
-+ dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_error DWC_ERROR
-+
-+#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
-+ dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_proto_error DWC_PROTO_ERROR
-+
-+#ifdef DEBUG
-+/** Prints out a exception error message if the _expr expression fails. Disabled
-+ * if DEBUG is not enabled. */
-+#define DWC_ASSERT(_expr, _format, _args...) do { \
-+ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
-+ __FILE__, __LINE__, ## _args); } \
-+ } while (0)
-+#else
-+#define DWC_ASSERT(_x...)
-+#endif
-+#define dwc_assert DWC_ASSERT
-+
-+
-+/** @name Byte Ordering
-+ * The following functions are for conversions between processor's byte ordering
-+ * and specific ordering you want.
-+ */
-+
-+/** Converts 32 bit data in CPU byte ordering to little endian. */
-+extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
-+#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
-+
-+/** Converts 32 bit data in CPU byte orderint to big endian. */
-+extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
-+#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
-+
-+/** Converts 32 bit little endian data to CPU byte ordering. */
-+extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
-+#define dwc_le32_to_cpu DWC_LE32_TO_CPU
-+
-+/** Converts 32 bit big endian data to CPU byte ordering. */
-+extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
-+#define dwc_be32_to_cpu DWC_BE32_TO_CPU
-+
-+/** Converts 16 bit data in CPU byte ordering to little endian. */
-+extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
-+#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
-+
-+/** Converts 16 bit data in CPU byte orderint to big endian. */
-+extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
-+#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
-+
-+/** Converts 16 bit little endian data to CPU byte ordering. */
-+extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
-+#define dwc_le16_to_cpu DWC_LE16_TO_CPU
-+
-+/** Converts 16 bit bi endian data to CPU byte ordering. */
-+extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
-+#define dwc_be16_to_cpu DWC_BE16_TO_CPU
-+
-+
-+/** @name Register Read/Write
-+ *
-+ * The following six functions should be implemented to read/write registers of
-+ * 32-bit and 64-bit sizes. All modules use this to read/write register values.
-+ * The reg value is a pointer to the register calculated from the void *base
-+ * variable passed into the driver when it is started. */
-+
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any extra parameters for register read/write, so we
-+ * just throw away the IO context parameter.
-+ */
-+/** Reads the content of a 32-bit register. */
-+extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
-+#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
-+
-+/** Reads the content of a 64-bit register. */
-+extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
-+#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
-+
-+/** Writes to a 32-bit register. */
-+extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
-+#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
-+
-+/** Writes to a 64-bit register. */
-+extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
-+#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
-+
-+/**
-+ * Modify bit values in a register. Using the
-+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
-+ */
-+extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
-+#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
-+extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
-+#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
-+
-+#endif /* DWC_LINUX */
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+typedef struct dwc_ioctx {
-+ struct device *dev;
-+ bus_space_tag_t iot;
-+ bus_space_handle_t ioh;
-+} dwc_ioctx_t;
-+
-+/** BSD needs two extra parameters for register read/write, so we pass
-+ * them in using the IO context parameter.
-+ */
-+/** Reads the content of a 32-bit register. */
-+extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
-+#define dwc_read_reg32 DWC_READ_REG32
-+
-+/** Reads the content of a 64-bit register. */
-+extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
-+#define dwc_read_reg64 DWC_READ_REG64
-+
-+/** Writes to a 32-bit register. */
-+extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
-+#define dwc_write_reg32 DWC_WRITE_REG32
-+
-+/** Writes to a 64-bit register. */
-+extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
-+#define dwc_write_reg64 DWC_WRITE_REG64
-+
-+/**
-+ * Modify bit values in a register. Using the
-+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
-+ */
-+extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
-+#define dwc_modify_reg32 DWC_MODIFY_REG32
-+extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
-+#define dwc_modify_reg64 DWC_MODIFY_REG64
-+
-+#endif /* DWC_FREEBSD || DWC_NETBSD */
-+
-+/** @cond */
-+
-+/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
-+ * register writes. */
-+
-+#ifdef DWC_LINUX
-+
-+# ifdef DWC_DEBUG_REGS
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
-+ return DWC_READ_REG32(&container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
-+ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
-+ &(((uint32_t*)container->regs->_reg)[num]), data); \
-+ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
-+ return DWC_READ_REG32(&container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
-+ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
-+ DWC_WRITE_REG32(&container->regs->_reg, data); \
-+}
-+
-+# else /* DWC_DEBUG_REGS */
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
-+ return DWC_READ_REG32(&container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
-+ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
-+ return DWC_READ_REG32(&container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
-+ DWC_WRITE_REG32(&container->regs->_reg, data); \
-+}
-+
-+# endif /* DWC_DEBUG_REGS */
-+
-+#endif /* DWC_LINUX */
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+
-+# ifdef DWC_DEBUG_REGS
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
-+ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
-+ &(((uint32_t*)container->regs->_reg)[num]), data); \
-+ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
-+ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
-+ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
-+}
-+
-+# else /* DWC_DEBUG_REGS */
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
-+ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
-+ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
-+ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
-+}
-+
-+# endif /* DWC_DEBUG_REGS */
-+
-+#endif /* DWC_FREEBSD || DWC_NETBSD */
-+
-+/** @endcond */
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/** @name Crypto Functions
-+ *
-+ * These are the low-level cryptographic functions used by the driver. */
-+
-+/** Perform AES CBC */
-+extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
-+#define dwc_aes_cbc DWC_AES_CBC
-+
-+/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
-+extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
-+#define dwc_random_bytes DWC_RANDOM_BYTES
-+
-+/** Perform the SHA-256 hash function */
-+extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
-+#define dwc_sha256 DWC_SHA256
-+
-+/** Calculated the HMAC-SHA256 */
-+extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
-+#define dwc_hmac_sha256 DWC_HMAC_SHA256
-+
-+#endif /* DWC_CRYPTOLIB */
-+
-+
-+/** @name Memory Allocation
-+ *
-+ * These function provide access to memory allocation. There are only 2 DMA
-+ * functions and 3 Regular memory functions that need to be implemented. None
-+ * of the memory debugging routines need to be implemented. The allocation
-+ * routines all ZERO the contents of the memory.
-+ *
-+ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
-+ * This checks for memory leaks, keeping track of alloc/free pairs. It also
-+ * keeps track of how much memory the driver is using at any given time. */
-+
-+#define DWC_PAGE_SIZE 4096
-+#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
-+#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
-+
-+#define DWC_INVALID_DMA_ADDR 0x0
-+
-+#ifdef DWC_LINUX
-+/** Type for a DMA address */
-+typedef dma_addr_t dwc_dma_t;
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+typedef bus_addr_t dwc_dma_t;
-+#endif
-+
-+#ifdef DWC_FREEBSD
-+typedef struct dwc_dmactx {
-+ struct device *dev;
-+ bus_dma_tag_t dma_tag;
-+ bus_dmamap_t dma_map;
-+ bus_addr_t dma_paddr;
-+ void *dma_vaddr;
-+} dwc_dmactx_t;
-+#endif
-+
-+#ifdef DWC_NETBSD
-+typedef struct dwc_dmactx {
-+ struct device *dev;
-+ bus_dma_tag_t dma_tag;
-+ bus_dmamap_t dma_map;
-+ bus_dma_segment_t segs[1];
-+ int nsegs;
-+ bus_addr_t dma_paddr;
-+ void *dma_vaddr;
-+} dwc_dmactx_t;
-+#endif
-+
-+/* @todo these functions will be added in the future */
-+#if 0
-+/**
-+ * Creates a DMA pool from which you can allocate DMA buffers. Buffers
-+ * allocated from this pool will be guaranteed to meet the size, alignment, and
-+ * boundary requirements specified.
-+ *
-+ * @param[in] size Specifies the size of the buffers that will be allocated from
-+ * this pool.
-+ * @param[in] align Specifies the byte alignment requirements of the buffers
-+ * allocated from this pool. Must be a power of 2.
-+ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
-+ * this pool must not cross.
-+ *
-+ * @returns A pointer to an internal opaque structure which is not to be
-+ * accessed outside of these library functions. Use this handle to specify
-+ * which pools to allocate/free DMA buffers from and also to destroy the pool,
-+ * when you are done with it.
-+ */
-+extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
-+
-+/**
-+ * Destroy a DMA pool. All buffers allocated from that pool must be freed first.
-+ */
-+extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
-+
-+/**
-+ * Allocate a buffer from the specified DMA pool and zeros its contents.
-+ */
-+extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
-+
-+/**
-+ * Free a previously allocated buffer from the DMA pool.
-+ */
-+extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
-+#endif
-+
-+/** Allocates a DMA capable buffer and zeroes its contents. */
-+extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
-+
-+/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
-+extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
-+
-+/** Frees a previously allocated buffer. */
-+extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
-+
-+/** Allocates a block of memory and zeroes its contents. */
-+extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
-+
-+/** Allocates a block of memory and zeroes its contents, in an atomic manner
-+ * which can be used inside interrupt context. The size should be sufficiently
-+ * small, a few KB at most, such that failures are not likely to occur. Can just call
-+ * __DWC_ALLOC if it is atomic. */
-+extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
-+
-+/** Frees a previously allocated buffer. */
-+extern void __DWC_FREE(void *mem_ctx, void *addr);
-+
-+#ifndef DWC_DEBUG_MEMORY
-+
-+#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
-+#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
-+#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
-+
-+# ifdef DWC_LINUX
-+#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
-+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
-+#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
-+# endif
-+
-+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
-+#define DWC_DMA_FREE __DWC_DMA_FREE
-+# endif
-+extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
-+
-+#else /* DWC_DEBUG_MEMORY */
-+
-+extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
-+extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
-+extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
-+extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+ char const *func, int line);
-+extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+ char const *func, int line);
-+extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
-+ dwc_dma_t dma_addr, char const *func, int line);
-+
-+extern int dwc_memory_debug_start(void *mem_ctx);
-+extern void dwc_memory_debug_stop(void);
-+extern void dwc_memory_debug_report(void);
-+
-+#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
-+#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
-+ __func__, __LINE__)
-+#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
-+
-+# ifdef DWC_LINUX
-+#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \
-+ _dma_, __func__, __LINE__)
-+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \
-+ _dma_, __func__, __LINE__)
-+#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \
-+ _virt_, _dma_, __func__, __LINE__)
-+# endif
-+
-+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
-+ _dma_, __func__, __LINE__)
-+#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
-+ _virt_, _dma_, __func__, __LINE__)
-+# endif
-+
-+#endif /* DWC_DEBUG_MEMORY */
-+
-+#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
-+#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
-+#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
-+
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
-+ * just throw away the DMA context parameter.
-+ */
-+#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
-+#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
-+#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+/** BSD needs several extra parameters for DMA buffer allocation, so we pass
-+ * them in using the DMA context parameter.
-+ */
-+#define dwc_dma_alloc DWC_DMA_ALLOC
-+#define dwc_dma_free DWC_DMA_FREE
-+#endif
-+
-+
-+/** @name Memory and String Processing */
-+
-+/** memset() clone */
-+extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
-+#define dwc_memset DWC_MEMSET
-+
-+/** memcpy() clone */
-+extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
-+#define dwc_memcpy DWC_MEMCPY
-+
-+/** memmove() clone */
-+extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
-+#define dwc_memmove DWC_MEMMOVE
-+
-+/** memcmp() clone */
-+extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
-+#define dwc_memcmp DWC_MEMCMP
-+
-+/** strcmp() clone */
-+extern int DWC_STRCMP(void *s1, void *s2);
-+#define dwc_strcmp DWC_STRCMP
-+
-+/** strncmp() clone */
-+extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
-+#define dwc_strncmp DWC_STRNCMP
-+
-+/** strlen() clone, for NULL terminated ASCII strings */
-+extern int DWC_STRLEN(char const *str);
-+#define dwc_strlen DWC_STRLEN
-+
-+/** strcpy() clone, for NULL terminated ASCII strings */
-+extern char *DWC_STRCPY(char *to, const char *from);
-+#define dwc_strcpy DWC_STRCPY
-+
-+/** strdup() clone. If you wish to use memory allocation debugging, this
-+ * implementation of strdup should use the DWC_* memory routines instead of
-+ * calling a predefined strdup. Otherwise the memory allocated by this routine
-+ * will not be seen by the debugging routines. */
-+extern char *DWC_STRDUP(char const *str);
-+#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
-+
-+/** NOT an atoi() clone. Read the description carefully. Returns an integer
-+ * converted from the string str in base 10 unless the string begins with a "0x"
-+ * in which case it is base 16. String must be a NULL terminated sequence of
-+ * ASCII characters and may optionally begin with whitespace, a + or -, and a
-+ * "0x" prefix if base 16. The remaining characters must be valid digits for
-+ * the number and end with a NULL character. If any invalid characters are
-+ * encountered or it returns with a negative error code and the results of the
-+ * conversion are undefined. On sucess it returns 0. Overflow conditions are
-+ * undefined. An example implementation using atoi() can be referenced from the
-+ * Linux implementation. */
-+extern int DWC_ATOI(const char *str, int32_t *value);
-+#define dwc_atoi DWC_ATOI
-+
-+/** Same as above but for unsigned. */
-+extern int DWC_ATOUI(const char *str, uint32_t *value);
-+#define dwc_atoui DWC_ATOUI
-+
-+#ifdef DWC_UTFLIB
-+/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
-+extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
-+#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
-+#endif
-+
-+
-+/** @name Wait queues
-+ *
-+ * Wait queues provide a means of synchronizing between threads or processes. A
-+ * process can block on a waitq if some condition is not true, waiting for it to
-+ * become true. When the waitq is triggered all waiting process will get
-+ * unblocked and the condition will be check again. Waitqs should be triggered
-+ * every time a condition can potentially change.*/
-+struct dwc_waitq;
-+
-+/** Type for a waitq */
-+typedef struct dwc_waitq dwc_waitq_t;
-+
-+/** The type of waitq condition callback function. This is called every time
-+ * condition is evaluated. */
-+typedef int (*dwc_waitq_condition_t)(void *data);
-+
-+/** Allocate a waitq */
-+extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
-+#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
-+
-+/** Free a waitq */
-+extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
-+#define dwc_waitq_free DWC_WAITQ_FREE
-+
-+/** Check the condition and if it is false, block on the waitq. When unblocked, check the
-+ * condition again. The function returns when the condition becomes true. The return value
-+ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
-+extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
-+#define dwc_waitq_wait DWC_WAITQ_WAIT
-+
-+/** Check the condition and if it is false, block on the waitq. When unblocked,
-+ * check the condition again. The function returns when the condition become
-+ * true or the timeout has passed. The return value is 0 on condition true or
-+ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
-+ * error. */
-+extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+ void *data, int32_t msecs);
-+#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
-+
-+/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
-+ * has potentially changed. */
-+extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
-+#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
-+
-+/** Unblock all processes waiting on the waitq with an ABORTED result. */
-+extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
-+#define dwc_waitq_abort DWC_WAITQ_ABORT
-+
-+
-+/** @name Threads
-+ *
-+ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
-+ * whenever it is woken up, and then return. The DWC_THREAD_STOP function
-+ * returns the value from the thread.
-+ */
-+
-+struct dwc_thread;
-+
-+/** Type for a thread */
-+typedef struct dwc_thread dwc_thread_t;
-+
-+/** The thread function */
-+typedef int (*dwc_thread_function_t)(void *data);
-+
-+/** Create a thread and start it running the thread_function. Returns a handle
-+ * to the thread */
-+extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
-+#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
-+
-+/** Stops a thread. Return the value returned by the thread. Or will return
-+ * DWC_ABORT if the thread never started. */
-+extern int DWC_THREAD_STOP(dwc_thread_t *thread);
-+#define dwc_thread_stop DWC_THREAD_STOP
-+
-+/** Signifies to the thread that it must stop. */
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any parameters for kthread_should_stop() */
-+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
-+#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
-+
-+/* No thread_exit function in Linux */
-+#define dwc_thread_exit(_thrd_)
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+/** BSD needs the thread pointer for kthread_suspend_check() */
-+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
-+#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
-+
-+/** The thread must call this to exit. */
-+extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
-+#define dwc_thread_exit DWC_THREAD_EXIT
-+#endif
-+
-+
-+/** @name Work queues
-+ *
-+ * Workqs are used to queue a callback function to be called at some later time,
-+ * in another thread. */
-+struct dwc_workq;
-+
-+/** Type for a workq */
-+typedef struct dwc_workq dwc_workq_t;
-+
-+/** The type of the callback function to be called. */
-+typedef void (*dwc_work_callback_t)(void *data);
-+
-+/** Allocate a workq */
-+extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
-+#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
-+
-+/** Free a workq. All work must be completed before being freed. */
-+extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
-+#define dwc_workq_free DWC_WORKQ_FREE
-+
-+/** Schedule a callback on the workq, passing in data. The function will be
-+ * scheduled at some later time. */
-+extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
-+ void *data, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 4, 5)));
-+#else
-+ ;
-+#endif
-+#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
-+
-+/** Schedule a callback on the workq, that will be called until at least
-+ * given number miliseconds have passed. */
-+extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
-+ void *data, uint32_t time, char *format, ...)
-+#ifdef __GNUC__
-+ __attribute__ ((format(printf, 5, 6)));
-+#else
-+ ;
-+#endif
-+#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
-+
-+/** The number of processes in the workq */
-+extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
-+#define dwc_workq_pending DWC_WORKQ_PENDING
-+
-+/** Blocks until all the work in the workq is complete or timed out. Returns <
-+ * 0 on timeout. */
-+extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
-+#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
-+
-+
-+/** @name Tasklets
-+ *
-+ */
-+struct dwc_tasklet;
-+
-+/** Type for a tasklet */
-+typedef struct dwc_tasklet dwc_tasklet_t;
-+
-+/** The type of the callback function to be called */
-+typedef void (*dwc_tasklet_callback_t)(void *data);
-+
-+/** Allocates a tasklet */
-+extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
-+#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
-+
-+/** Frees a tasklet */
-+extern void DWC_TASK_FREE(dwc_tasklet_t *task);
-+#define dwc_task_free DWC_TASK_FREE
-+
-+/** Schedules a tasklet to run */
-+extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
-+#define dwc_task_schedule DWC_TASK_SCHEDULE
-+
-+extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
-+#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
-+
-+/** @name Timer
-+ *
-+ * Callbacks must be small and atomic.
-+ */
-+struct dwc_timer;
-+
-+/** Type for a timer */
-+typedef struct dwc_timer dwc_timer_t;
-+
-+/** The type of the callback function to be called */
-+typedef void (*dwc_timer_callback_t)(void *data);
-+
-+/** Allocates a timer */
-+extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
-+#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
-+
-+/** Frees a timer */
-+extern void DWC_TIMER_FREE(dwc_timer_t *timer);
-+#define dwc_timer_free DWC_TIMER_FREE
-+
-+/** Schedules the timer to run at time ms from now. And will repeat at every
-+ * repeat_interval msec therafter
-+ *
-+ * Modifies a timer that is still awaiting execution to a new expiration time.
-+ * The mod_time is added to the old time. */
-+extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
-+#define dwc_timer_schedule DWC_TIMER_SCHEDULE
-+
-+/** Disables the timer from execution. */
-+extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
-+#define dwc_timer_cancel DWC_TIMER_CANCEL
-+
-+
-+/** @name Spinlocks
-+ *
-+ * These locks are used when the work between the lock/unlock is atomic and
-+ * short. Interrupts are also disabled during the lock/unlock and thus they are
-+ * suitable to lock between interrupt/non-interrupt context. They also lock
-+ * between processes if you have multiple CPUs or Preemption. If you don't have
-+ * multiple CPUS or Preemption, then the you can simply implement the
-+ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
-+ * the work between the lock/unlock is atomic, the process context will never
-+ * change, and so you never have to lock between processes. */
-+
-+struct dwc_spinlock;
-+
-+/** Type for a spinlock */
-+typedef struct dwc_spinlock dwc_spinlock_t;
-+
-+/** Type for the 'flags' argument to spinlock funtions */
-+typedef unsigned long dwc_irqflags_t;
-+
-+/** Returns an initialized lock variable. This function should allocate and
-+ * initialize the OS-specific data structure used for locking. This data
-+ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
-+ * be freed by the DWC_FREE_LOCK when it is no longer used.
-+ *
-+ * For Linux Spinlock Debugging make it macro because the debugging routines use
-+ * the symbol name to determine recursive locking. Using a wrapper function
-+ * makes it falsely think recursive locking occurs. */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
-+#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
-+ lock = DWC_ALLOC(sizeof(spinlock_t)); \
-+ if (lock) { \
-+ spin_lock_init((spinlock_t *)lock); \
-+ } \
-+})
-+#else
-+extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
-+#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
-+#endif
-+
-+/** Frees an initialized lock variable. */
-+extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
-+#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
-+
-+/** Disables interrupts and blocks until it acquires the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ * @param flags Unsigned long for irq flags storage.
-+ */
-+extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
-+#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
-+
-+/** Re-enables the interrupt and releases the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ * @param flags Unsigned long for irq flags storage. Must be the same as was
-+ * passed into DWC_LOCK.
-+ */
-+extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
-+#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
-+
-+/** Blocks until it acquires the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ */
-+extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
-+#define dwc_spinlock DWC_SPINLOCK
-+
-+/** Releases the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ */
-+extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
-+#define dwc_spinunlock DWC_SPINUNLOCK
-+
-+
-+/** @name Mutexes
-+ *
-+ * Unlike spinlocks Mutexes lock only between processes and the work between the
-+ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
-+ */
-+
-+struct dwc_mutex;
-+
-+/** Type for a mutex */
-+typedef struct dwc_mutex dwc_mutex_t;
-+
-+/* For Linux Mutex Debugging make it inline because the debugging routines use
-+ * the symbol to determine recursive locking. This makes it falsely think
-+ * recursive locking occurs. */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
-+#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
-+ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
-+ mutex_init((struct mutex *)__mutexp); \
-+})
-+#endif
-+
-+/** Allocate a mutex */
-+extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
-+#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
-+
-+/* For memory leak debugging when using Linux Mutex Debugging */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
-+#define DWC_MUTEX_FREE(__mutexp) do { \
-+ mutex_destroy((struct mutex *)__mutexp); \
-+ DWC_FREE(__mutexp); \
-+} while(0)
-+#else
-+/** Free a mutex */
-+extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
-+#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
-+#endif
-+
-+/** Lock a mutex */
-+extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_lock DWC_MUTEX_LOCK
-+
-+/** Non-blocking lock returns 1 on successful lock. */
-+extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
-+
-+/** Unlock a mutex */
-+extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
-+
-+
-+/** @name Time */
-+
-+/** Microsecond delay.
-+ *
-+ * @param usecs Microseconds to delay.
-+ */
-+extern void DWC_UDELAY(uint32_t usecs);
-+#define dwc_udelay DWC_UDELAY
-+
-+/** Millisecond delay.
-+ *
-+ * @param msecs Milliseconds to delay.
-+ */
-+extern void DWC_MDELAY(uint32_t msecs);
-+#define dwc_mdelay DWC_MDELAY
-+
-+/** Non-busy waiting.
-+ * Sleeps for specified number of milliseconds.
-+ *
-+ * @param msecs Milliseconds to sleep.
-+ */
-+extern void DWC_MSLEEP(uint32_t msecs);
-+#define dwc_msleep DWC_MSLEEP
-+
-+/**
-+ * Returns number of milliseconds since boot.
-+ */
-+extern uint32_t DWC_TIME(void);
-+#define dwc_time DWC_TIME
-+
-+
-+
-+
-+/* @mainpage DWC Portability and Common Library
-+ *
-+ * This is the documentation for the DWC Portability and Common Library.
-+ *
-+ * @section intro Introduction
-+ *
-+ * The DWC Portability library consists of wrapper calls and data structures to
-+ * all low-level functions which are typically provided by the OS. The WUDEV
-+ * driver uses only these functions. In order to port the WUDEV driver, only
-+ * the functions in this library need to be re-implemented, with the same
-+ * behavior as documented here.
-+ *
-+ * The Common library consists of higher level functions, which rely only on
-+ * calling the functions from the DWC Portability library. These common
-+ * routines are shared across modules. Some of the common libraries need to be
-+ * used directly by the driver programmer when porting WUDEV. Such as the
-+ * parameter and notification libraries.
-+ *
-+ * @section low Portability Library OS Wrapper Functions
-+ *
-+ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
-+ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
-+ * these functions are included in the dwc_os.h file.
-+ *
-+ * There are many functions here covering a wide array of OS services. Please
-+ * see dwc_os.h for details, and implementation notes for each function.
-+ *
-+ * @section common Common Library Functions
-+ *
-+ * Any function starting with dwc and in all lowercase is a common library
-+ * routine. These functions have a portable implementation and do not need to
-+ * be reimplemented when porting. The common routines can be used by any
-+ * driver, and some must be used by the end user to control the drivers. For
-+ * example, you must use the Parameter common library in order to set the
-+ * parameters in the WUDEV module.
-+ *
-+ * The common libraries consist of the following:
-+ *
-+ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
-+ * - Parameters - Used internally and can be used by end-user. See dwc_params.h
-+ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
-+ * - Lists - Used internally and can be used by end-user. See dwc_list.h
-+ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
-+ * - Modpow - Used internally only. See dwc_modpow.h
-+ * - DH - Used internally only. See dwc_dh.h
-+ * - Crypto - Used internally only. See dwc_crypto.h
-+ *
-+ *
-+ * @section prereq Prerequistes For dwc_os.h
-+ * @subsection types Data Types
-+ *
-+ * The dwc_os.h file assumes that several low-level data types are pre defined for the
-+ * compilation environment. These data types are:
-+ *
-+ * - uint8_t - unsigned 8-bit data type
-+ * - int8_t - signed 8-bit data type
-+ * - uint16_t - unsigned 16-bit data type
-+ * - int16_t - signed 16-bit data type
-+ * - uint32_t - unsigned 32-bit data type
-+ * - int32_t - signed 32-bit data type
-+ * - uint64_t - unsigned 64-bit data type
-+ * - int64_t - signed 64-bit data type
-+ *
-+ * Ensure that these are defined before using dwc_os.h. The easiest way to do
-+ * that is to modify the top of the file to include the appropriate header.
-+ * This is already done for the Linux environment. If the DWC_LINUX macro is
-+ * defined, the correct header will be added. A standard header <stdint.h> is
-+ * also used for environments where standard C headers are available.
-+ *
-+ * @subsection stdarg Variable Arguments
-+ *
-+ * Variable arguments are provided by a standard C header <stdarg.h>. it is
-+ * available in Both the Linux and ANSI C enviornment. An equivalent must be
-+ * provided in your enviornment in order to use dwc_os.h with the debug and
-+ * tracing message functionality.
-+ *
-+ * @subsection thread Threading
-+ *
-+ * WUDEV Core must be run on an operating system that provides for multiple
-+ * threads/processes. Threading can be implemented in many ways, even in
-+ * embedded systems without an operating system. At the bare minimum, the
-+ * system should be able to start any number of processes at any time to handle
-+ * special work. It need not be a pre-emptive system. Process context can
-+ * change upon a call to a blocking function. The hardware interrupt context
-+ * that calls the module's ISR() function must be differentiable from process
-+ * context, even if your processes are impemented via a hardware interrupt.
-+ * Further locking mechanism between process must exist (or be implemented), and
-+ * process context must have a way to disable interrupts for a period of time to
-+ * lock them out. If all of this exists, the functions in dwc_os.h related to
-+ * threading should be able to be implemented with the defined behavior.
-+ *
-+ */
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_OS_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/Makefile linux-rpi/drivers/usb/host/dwc_common_port/Makefile
---- linux-3.18.14/drivers/usb/host/dwc_common_port/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,58 @@
-+#
-+# Makefile for DWC_common library
-+#
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+ccflags-y += -DDWC_LINUX
-+#ccflags-y += -DDEBUG
-+#ccflags-y += -DDWC_DEBUG_REGS
-+#ccflags-y += -DDWC_DEBUG_MEMORY
-+
-+ccflags-y += -DDWC_LIBMODULE
-+ccflags-y += -DDWC_CCLIB
-+#ccflags-y += -DDWC_CRYPTOLIB
-+ccflags-y += -DDWC_NOTIFYLIB
-+ccflags-y += -DDWC_UTFLIB
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o
-+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
-+ dwc_crypto.o dwc_notifier.o \
-+ dwc_common_linux.o dwc_mem.o
-+
-+kernrelwd := $(subst ., ,$(KERNELRELEASE))
-+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
-+
-+ifneq ($(kernrel3),2.6.20)
-+# grayg - I only know that we use ccflags-y in 2.6.31 actually
-+ccflags-y += $(CPPFLAGS)
-+endif
-+
-+else
-+
-+#ifeq ($(KDIR),)
-+#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
-+#endif
-+
-+ifeq ($(ARCH),)
-+$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
-+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
-+endif
-+
-+ifeq ($(DOXYGEN),)
-+DOXYGEN := doxygen
-+endif
-+
-+default:
-+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+docs: $(wildcard *.[hc]) doc/doxygen.cfg
-+ $(DOXYGEN) doc/doxygen.cfg
-+
-+tags: $(wildcard *.[hc])
-+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+endif
-+
-+clean:
-+ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/Makefile.fbsd linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd
---- linux-3.18.14/drivers/usb/host/dwc_common_port/Makefile.fbsd 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,17 @@
-+CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
-+CFLAGS += -DDWC_FREEBSD
-+CFLAGS += -DDEBUG
-+#CFLAGS += -DDWC_DEBUG_REGS
-+#CFLAGS += -DDWC_DEBUG_MEMORY
-+
-+#CFLAGS += -DDWC_LIBMODULE
-+#CFLAGS += -DDWC_CCLIB
-+#CFLAGS += -DDWC_CRYPTOLIB
-+#CFLAGS += -DDWC_NOTIFYLIB
-+#CFLAGS += -DDWC_UTFLIB
-+
-+KMOD = dwc_common_port_lib
-+SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
-+ dwc_common_fbsd.c dwc_mem.c
-+
-+.include <bsd.kmod.mk>
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/Makefile.linux linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux
---- linux-3.18.14/drivers/usb/host/dwc_common_port/Makefile.linux 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux 2015-05-31 14:46:12.889660961 -0500
-@@ -0,0 +1,49 @@
-+#
-+# Makefile for DWC_common library
-+#
-+ifneq ($(KERNELRELEASE),)
-+
-+ccflags-y += -DDWC_LINUX
-+#ccflags-y += -DDEBUG
-+#ccflags-y += -DDWC_DEBUG_REGS
-+#ccflags-y += -DDWC_DEBUG_MEMORY
-+
-+ccflags-y += -DDWC_LIBMODULE
-+ccflags-y += -DDWC_CCLIB
-+ccflags-y += -DDWC_CRYPTOLIB
-+ccflags-y += -DDWC_NOTIFYLIB
-+ccflags-y += -DDWC_UTFLIB
-+
-+obj-m := dwc_common_port_lib.o
-+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
-+ dwc_crypto.o dwc_notifier.o \
-+ dwc_common_linux.o dwc_mem.o
-+
-+else
-+
-+ifeq ($(KDIR),)
-+$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
-+endif
-+
-+ifeq ($(ARCH),)
-+$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
-+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
-+endif
-+
-+ifeq ($(DOXYGEN),)
-+DOXYGEN := doxygen
-+endif
-+
-+default:
-+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+docs: $(wildcard *.[hc]) doc/doxygen.cfg
-+ $(DOXYGEN) doc/doxygen.cfg
-+
-+tags: $(wildcard *.[hc])
-+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+endif
-+
-+clean:
-+ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_common_port/usb.h linux-rpi/drivers/usb/host/dwc_common_port/usb.h
---- linux-3.18.14/drivers/usb/host/dwc_common_port/usb.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_common_port/usb.h 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,946 @@
-+/*
-+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
-+ * All rights reserved.
-+ *
-+ * This code is derived from software contributed to The NetBSD Foundation
-+ * by Lennart Augustsson (lennart@augustsson.net) at
-+ * Carlstedt Research & Technology.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. All advertising materials mentioning features or use of this software
-+ * must display the following acknowledgement:
-+ * This product includes software developed by the NetBSD
-+ * Foundation, Inc. and its contributors.
-+ * 4. Neither the name of The NetBSD Foundation nor the names of its
-+ * contributors may be used to endorse or promote products derived
-+ * from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
-+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
-+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+/* Modified by Synopsys, Inc, 12/12/2007 */
-+
-+
-+#ifndef _USB_H_
-+#define _USB_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/*
-+ * The USB records contain some unaligned little-endian word
-+ * components. The U[SG]ETW macros take care of both the alignment
-+ * and endian problem and should always be used to access non-byte
-+ * values.
-+ */
-+typedef u_int8_t uByte;
-+typedef u_int8_t uWord[2];
-+typedef u_int8_t uDWord[4];
-+
-+#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
-+#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff }
-+#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \
-+ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
-+
-+#if 1
-+#define UGETW(w) ((w)[0] | ((w)[1] << 8))
-+#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
-+#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
-+#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
-+ (w)[1] = (u_int8_t)((v) >> 8), \
-+ (w)[2] = (u_int8_t)((v) >> 16), \
-+ (w)[3] = (u_int8_t)((v) >> 24))
-+#else
-+/*
-+ * On little-endian machines that can handle unanliged accesses
-+ * (e.g. i386) these macros can be replaced by the following.
-+ */
-+#define UGETW(w) (*(u_int16_t *)(w))
-+#define USETW(w,v) (*(u_int16_t *)(w) = (v))
-+#define UGETDW(w) (*(u_int32_t *)(w))
-+#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
-+#endif
-+
-+/*
-+ * Macros for accessing UAS IU fields, which are big-endian
-+ */
-+#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
-+#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff }
-+#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
-+ ((x) >> 8) & 0xff, (x) & 0xff }
-+#define IUGETW(w) (((w)[0] << 8) | (w)[1])
-+#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
-+#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
-+#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
-+ (w)[1] = (u_int8_t)((v) >> 16), \
-+ (w)[2] = (u_int8_t)((v) >> 8), \
-+ (w)[3] = (u_int8_t)(v))
-+
-+#define UPACKED __attribute__((__packed__))
-+
-+typedef struct {
-+ uByte bmRequestType;
-+ uByte bRequest;
-+ uWord wValue;
-+ uWord wIndex;
-+ uWord wLength;
-+} UPACKED usb_device_request_t;
-+
-+#define UT_GET_DIR(a) ((a) & 0x80)
-+#define UT_WRITE 0x00
-+#define UT_READ 0x80
-+
-+#define UT_GET_TYPE(a) ((a) & 0x60)
-+#define UT_STANDARD 0x00
-+#define UT_CLASS 0x20
-+#define UT_VENDOR 0x40
-+
-+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
-+#define UT_DEVICE 0x00
-+#define UT_INTERFACE 0x01
-+#define UT_ENDPOINT 0x02
-+#define UT_OTHER 0x03
-+
-+#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE)
-+#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE)
-+#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT)
-+#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE)
-+#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE)
-+#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
-+#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE)
-+#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE)
-+#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER)
-+#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT)
-+#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE)
-+#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
-+#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER)
-+#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT)
-+#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE)
-+#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE)
-+#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER)
-+#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT)
-+#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
-+#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
-+#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER)
-+#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
-+
-+/* Requests */
-+#define UR_GET_STATUS 0x00
-+#define USTAT_STANDARD_STATUS 0x00
-+#define WUSTAT_WUSB_FEATURE 0x01
-+#define WUSTAT_CHANNEL_INFO 0x02
-+#define WUSTAT_RECEIVED_DATA 0x03
-+#define WUSTAT_MAS_AVAILABILITY 0x04
-+#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05
-+#define UR_CLEAR_FEATURE 0x01
-+#define UR_SET_FEATURE 0x03
-+#define UR_SET_AND_TEST_FEATURE 0x0c
-+#define UR_SET_ADDRESS 0x05
-+#define UR_GET_DESCRIPTOR 0x06
-+#define UDESC_DEVICE 0x01
-+#define UDESC_CONFIG 0x02
-+#define UDESC_STRING 0x03
-+#define UDESC_INTERFACE 0x04
-+#define UDESC_ENDPOINT 0x05
-+#define UDESC_SS_USB_COMPANION 0x30
-+#define UDESC_DEVICE_QUALIFIER 0x06
-+#define UDESC_OTHER_SPEED_CONFIGURATION 0x07
-+#define UDESC_INTERFACE_POWER 0x08
-+#define UDESC_OTG 0x09
-+#define WUDESC_SECURITY 0x0c
-+#define WUDESC_KEY 0x0d
-+#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
-+#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
-+#define WUD_KEY_TYPE_ASSOC 0x01
-+#define WUD_KEY_TYPE_GTK 0x02
-+#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
-+#define WUD_KEY_ORIGIN_HOST 0x00
-+#define WUD_KEY_ORIGIN_DEVICE 0x01
-+#define WUDESC_ENCRYPTION_TYPE 0x0e
-+#define WUDESC_BOS 0x0f
-+#define WUDESC_DEVICE_CAPABILITY 0x10
-+#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
-+#define UDESC_BOS 0x0f
-+#define UDESC_DEVICE_CAPABILITY 0x10
-+#define UDESC_CS_DEVICE 0x21 /* class specific */
-+#define UDESC_CS_CONFIG 0x22
-+#define UDESC_CS_STRING 0x23
-+#define UDESC_CS_INTERFACE 0x24
-+#define UDESC_CS_ENDPOINT 0x25
-+#define UDESC_HUB 0x29
-+#define UR_SET_DESCRIPTOR 0x07
-+#define UR_GET_CONFIG 0x08
-+#define UR_SET_CONFIG 0x09
-+#define UR_GET_INTERFACE 0x0a
-+#define UR_SET_INTERFACE 0x0b
-+#define UR_SYNCH_FRAME 0x0c
-+#define WUR_SET_ENCRYPTION 0x0d
-+#define WUR_GET_ENCRYPTION 0x0e
-+#define WUR_SET_HANDSHAKE 0x0f
-+#define WUR_GET_HANDSHAKE 0x10
-+#define WUR_SET_CONNECTION 0x11
-+#define WUR_SET_SECURITY_DATA 0x12
-+#define WUR_GET_SECURITY_DATA 0x13
-+#define WUR_SET_WUSB_DATA 0x14
-+#define WUDATA_DRPIE_INFO 0x01
-+#define WUDATA_TRANSMIT_DATA 0x02
-+#define WUDATA_TRANSMIT_PARAMS 0x03
-+#define WUDATA_RECEIVE_PARAMS 0x04
-+#define WUDATA_TRANSMIT_POWER 0x05
-+#define WUR_LOOPBACK_DATA_WRITE 0x15
-+#define WUR_LOOPBACK_DATA_READ 0x16
-+#define WUR_SET_INTERFACE_DS 0x17
-+
-+/* Feature numbers */
-+#define UF_ENDPOINT_HALT 0
-+#define UF_DEVICE_REMOTE_WAKEUP 1
-+#define UF_TEST_MODE 2
-+#define UF_DEVICE_B_HNP_ENABLE 3
-+#define UF_DEVICE_A_HNP_SUPPORT 4
-+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
-+#define WUF_WUSB 3
-+#define WUF_TX_DRPIE 0x0
-+#define WUF_DEV_XMIT_PACKET 0x1
-+#define WUF_COUNT_PACKETS 0x2
-+#define WUF_CAPTURE_PACKETS 0x3
-+#define UF_FUNCTION_SUSPEND 0
-+#define UF_U1_ENABLE 48
-+#define UF_U2_ENABLE 49
-+#define UF_LTM_ENABLE 50
-+
-+/* Class requests from the USB 2.0 hub spec, table 11-15 */
-+#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE)
-+#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE)
-+#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR)
-+#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS)
-+#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS)
-+#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE)
-+#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE)
-+#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE)
-+
-+#ifdef _MSC_VER
-+#include <pshpack1.h>
-+#endif
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDescriptorSubtype;
-+} UPACKED usb_descriptor_t;
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+} UPACKED usb_descriptor_header_t;
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord bcdUSB;
-+#define UD_USB_2_0 0x0200
-+#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
-+ uByte bDeviceClass;
-+ uByte bDeviceSubClass;
-+ uByte bDeviceProtocol;
-+ uByte bMaxPacketSize;
-+ /* The fields below are not part of the initial descriptor. */
-+ uWord idVendor;
-+ uWord idProduct;
-+ uWord bcdDevice;
-+ uByte iManufacturer;
-+ uByte iProduct;
-+ uByte iSerialNumber;
-+ uByte bNumConfigurations;
-+} UPACKED usb_device_descriptor_t;
-+#define USB_DEVICE_DESCRIPTOR_SIZE 18
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord wTotalLength;
-+ uByte bNumInterface;
-+ uByte bConfigurationValue;
-+ uByte iConfiguration;
-+#define UC_ATT_ONE (1 << 7) /* must be set */
-+#define UC_ATT_SELFPOWER (1 << 6) /* self powered */
-+#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */
-+#define UC_ATT_BATTERY (1 << 4) /* battery powered */
-+ uByte bmAttributes;
-+#define UC_BUS_POWERED 0x80
-+#define UC_SELF_POWERED 0x40
-+#define UC_REMOTE_WAKEUP 0x20
-+ uByte bMaxPower; /* max current in 2 mA units */
-+#define UC_POWER_FACTOR 2
-+} UPACKED usb_config_descriptor_t;
-+#define USB_CONFIG_DESCRIPTOR_SIZE 9
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bInterfaceNumber;
-+ uByte bAlternateSetting;
-+ uByte bNumEndpoints;
-+ uByte bInterfaceClass;
-+ uByte bInterfaceSubClass;
-+ uByte bInterfaceProtocol;
-+ uByte iInterface;
-+} UPACKED usb_interface_descriptor_t;
-+#define USB_INTERFACE_DESCRIPTOR_SIZE 9
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bEndpointAddress;
-+#define UE_GET_DIR(a) ((a) & 0x80)
-+#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
-+#define UE_DIR_IN 0x80
-+#define UE_DIR_OUT 0x00
-+#define UE_ADDR 0x0f
-+#define UE_GET_ADDR(a) ((a) & UE_ADDR)
-+ uByte bmAttributes;
-+#define UE_XFERTYPE 0x03
-+#define UE_CONTROL 0x00
-+#define UE_ISOCHRONOUS 0x01
-+#define UE_BULK 0x02
-+#define UE_INTERRUPT 0x03
-+#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE)
-+#define UE_ISO_TYPE 0x0c
-+#define UE_ISO_ASYNC 0x04
-+#define UE_ISO_ADAPT 0x08
-+#define UE_ISO_SYNC 0x0c
-+#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE)
-+ uWord wMaxPacketSize;
-+ uByte bInterval;
-+} UPACKED usb_endpoint_descriptor_t;
-+#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
-+
-+typedef struct ss_endpoint_companion_descriptor {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bMaxBurst;
-+#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f)
-+#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f))
-+#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03)
-+#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03))
-+ uByte bmAttributes;
-+ uWord wBytesPerInterval;
-+} UPACKED ss_endpoint_companion_descriptor_t;
-+#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord bString[127];
-+} UPACKED usb_string_descriptor_t;
-+#define USB_MAX_STRING_LEN 128
-+#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
-+
-+/* Hub specific request */
-+#define UR_GET_BUS_STATE 0x02
-+#define UR_CLEAR_TT_BUFFER 0x08
-+#define UR_RESET_TT 0x09
-+#define UR_GET_TT_STATE 0x0a
-+#define UR_STOP_TT 0x0b
-+
-+/* Hub features */
-+#define UHF_C_HUB_LOCAL_POWER 0
-+#define UHF_C_HUB_OVER_CURRENT 1
-+#define UHF_PORT_CONNECTION 0
-+#define UHF_PORT_ENABLE 1
-+#define UHF_PORT_SUSPEND 2
-+#define UHF_PORT_OVER_CURRENT 3
-+#define UHF_PORT_RESET 4
-+#define UHF_PORT_L1 5
-+#define UHF_PORT_POWER 8
-+#define UHF_PORT_LOW_SPEED 9
-+#define UHF_PORT_HIGH_SPEED 10
-+#define UHF_C_PORT_CONNECTION 16
-+#define UHF_C_PORT_ENABLE 17
-+#define UHF_C_PORT_SUSPEND 18
-+#define UHF_C_PORT_OVER_CURRENT 19
-+#define UHF_C_PORT_RESET 20
-+#define UHF_C_PORT_L1 23
-+#define UHF_PORT_TEST 21
-+#define UHF_PORT_INDICATOR 22
-+
-+typedef struct {
-+ uByte bDescLength;
-+ uByte bDescriptorType;
-+ uByte bNbrPorts;
-+ uWord wHubCharacteristics;
-+#define UHD_PWR 0x0003
-+#define UHD_PWR_GANGED 0x0000
-+#define UHD_PWR_INDIVIDUAL 0x0001
-+#define UHD_PWR_NO_SWITCH 0x0002
-+#define UHD_COMPOUND 0x0004
-+#define UHD_OC 0x0018
-+#define UHD_OC_GLOBAL 0x0000
-+#define UHD_OC_INDIVIDUAL 0x0008
-+#define UHD_OC_NONE 0x0010
-+#define UHD_TT_THINK 0x0060
-+#define UHD_TT_THINK_8 0x0000
-+#define UHD_TT_THINK_16 0x0020
-+#define UHD_TT_THINK_24 0x0040
-+#define UHD_TT_THINK_32 0x0060
-+#define UHD_PORT_IND 0x0080
-+ uByte bPwrOn2PwrGood; /* delay in 2 ms units */
-+#define UHD_PWRON_FACTOR 2
-+ uByte bHubContrCurrent;
-+ uByte DeviceRemovable[32]; /* max 255 ports */
-+#define UHD_NOT_REMOV(desc, i) \
-+ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
-+ /* deprecated */ uByte PortPowerCtrlMask[1];
-+} UPACKED usb_hub_descriptor_t;
-+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord bcdUSB;
-+ uByte bDeviceClass;
-+ uByte bDeviceSubClass;
-+ uByte bDeviceProtocol;
-+ uByte bMaxPacketSize0;
-+ uByte bNumConfigurations;
-+ uByte bReserved;
-+} UPACKED usb_device_qualifier_t;
-+#define USB_DEVICE_QUALIFIER_SIZE 10
-+
-+typedef struct {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bmAttributes;
-+#define UOTG_SRP 0x01
-+#define UOTG_HNP 0x02
-+} UPACKED usb_otg_descriptor_t;
-+
-+/* OTG feature selectors */
-+#define UOTG_B_HNP_ENABLE 3
-+#define UOTG_A_HNP_SUPPORT 4
-+#define UOTG_A_ALT_HNP_SUPPORT 5
-+
-+typedef struct {
-+ uWord wStatus;
-+/* Device status flags */
-+#define UDS_SELF_POWERED 0x0001
-+#define UDS_REMOTE_WAKEUP 0x0002
-+/* Endpoint status flags */
-+#define UES_HALT 0x0001
-+} UPACKED usb_status_t;
-+
-+typedef struct {
-+ uWord wHubStatus;
-+#define UHS_LOCAL_POWER 0x0001
-+#define UHS_OVER_CURRENT 0x0002
-+ uWord wHubChange;
-+} UPACKED usb_hub_status_t;
-+
-+typedef struct {
-+ uWord wPortStatus;
-+#define UPS_CURRENT_CONNECT_STATUS 0x0001
-+#define UPS_PORT_ENABLED 0x0002
-+#define UPS_SUSPEND 0x0004
-+#define UPS_OVERCURRENT_INDICATOR 0x0008
-+#define UPS_RESET 0x0010
-+#define UPS_PORT_POWER 0x0100
-+#define UPS_LOW_SPEED 0x0200
-+#define UPS_HIGH_SPEED 0x0400
-+#define UPS_PORT_TEST 0x0800
-+#define UPS_PORT_INDICATOR 0x1000
-+ uWord wPortChange;
-+#define UPS_C_CONNECT_STATUS 0x0001
-+#define UPS_C_PORT_ENABLED 0x0002
-+#define UPS_C_SUSPEND 0x0004
-+#define UPS_C_OVERCURRENT_INDICATOR 0x0008
-+#define UPS_C_PORT_RESET 0x0010
-+} UPACKED usb_port_status_t;
-+
-+#ifdef _MSC_VER
-+#include <poppack.h>
-+#endif
-+
-+/* Device class codes */
-+#define UDCLASS_IN_INTERFACE 0x00
-+#define UDCLASS_COMM 0x02
-+#define UDCLASS_HUB 0x09
-+#define UDSUBCLASS_HUB 0x00
-+#define UDPROTO_FSHUB 0x00
-+#define UDPROTO_HSHUBSTT 0x01
-+#define UDPROTO_HSHUBMTT 0x02
-+#define UDCLASS_DIAGNOSTIC 0xdc
-+#define UDCLASS_WIRELESS 0xe0
-+#define UDSUBCLASS_RF 0x01
-+#define UDPROTO_BLUETOOTH 0x01
-+#define UDCLASS_VENDOR 0xff
-+
-+/* Interface class codes */
-+#define UICLASS_UNSPEC 0x00
-+
-+#define UICLASS_AUDIO 0x01
-+#define UISUBCLASS_AUDIOCONTROL 1
-+#define UISUBCLASS_AUDIOSTREAM 2
-+#define UISUBCLASS_MIDISTREAM 3
-+
-+#define UICLASS_CDC 0x02 /* communication */
-+#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
-+#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
-+#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
-+#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
-+#define UISUBCLASS_CAPI_CONTROLMODEL 5
-+#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
-+#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
-+#define UIPROTO_CDC_AT 1
-+
-+#define UICLASS_HID 0x03
-+#define UISUBCLASS_BOOT 1
-+#define UIPROTO_BOOT_KEYBOARD 1
-+
-+#define UICLASS_PHYSICAL 0x05
-+
-+#define UICLASS_IMAGE 0x06
-+
-+#define UICLASS_PRINTER 0x07
-+#define UISUBCLASS_PRINTER 1
-+#define UIPROTO_PRINTER_UNI 1
-+#define UIPROTO_PRINTER_BI 2
-+#define UIPROTO_PRINTER_1284 3
-+
-+#define UICLASS_MASS 0x08
-+#define UISUBCLASS_RBC 1
-+#define UISUBCLASS_SFF8020I 2
-+#define UISUBCLASS_QIC157 3
-+#define UISUBCLASS_UFI 4
-+#define UISUBCLASS_SFF8070I 5
-+#define UISUBCLASS_SCSI 6
-+#define UIPROTO_MASS_CBI_I 0
-+#define UIPROTO_MASS_CBI 1
-+#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
-+#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
-+
-+#define UICLASS_HUB 0x09
-+#define UISUBCLASS_HUB 0
-+#define UIPROTO_FSHUB 0
-+#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
-+#define UIPROTO_HSHUBMTT 1
-+
-+#define UICLASS_CDC_DATA 0x0a
-+#define UISUBCLASS_DATA 0
-+#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
-+#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
-+#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
-+#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
-+#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
-+#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
-+#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
-+#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
-+#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
-+#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
-+#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
-+#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
-+#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
-+
-+#define UICLASS_SMARTCARD 0x0b
-+
-+/*#define UICLASS_FIRM_UPD 0x0c*/
-+
-+#define UICLASS_SECURITY 0x0d
-+
-+#define UICLASS_DIAGNOSTIC 0xdc
-+
-+#define UICLASS_WIRELESS 0xe0
-+#define UISUBCLASS_RF 0x01
-+#define UIPROTO_BLUETOOTH 0x01
-+
-+#define UICLASS_APPL_SPEC 0xfe
-+#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
-+#define UISUBCLASS_IRDA 2
-+#define UIPROTO_IRDA 0
-+
-+#define UICLASS_VENDOR 0xff
-+
-+#define USB_HUB_MAX_DEPTH 5
-+
-+/*
-+ * Minimum time a device needs to be powered down to go through
-+ * a power cycle. XXX Are these time in the spec?
-+ */
-+#define USB_POWER_DOWN_TIME 200 /* ms */
-+#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
-+
-+#if 0
-+/* These are the values from the spec. */
-+#define USB_PORT_RESET_DELAY 10 /* ms */
-+#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */
-+#define USB_PORT_RESET_RECOVERY 10 /* ms */
-+#define USB_PORT_POWERUP_DELAY 100 /* ms */
-+#define USB_SET_ADDRESS_SETTLE 2 /* ms */
-+#define USB_RESUME_DELAY (20*5) /* ms */
-+#define USB_RESUME_WAIT 10 /* ms */
-+#define USB_RESUME_RECOVERY 10 /* ms */
-+#define USB_EXTRA_POWER_UP_TIME 0 /* ms */
-+#else
-+/* Allow for marginal (i.e. non-conforming) devices. */
-+#define USB_PORT_RESET_DELAY 50 /* ms */
-+#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
-+#define USB_PORT_RESET_RECOVERY 250 /* ms */
-+#define USB_PORT_POWERUP_DELAY 300 /* ms */
-+#define USB_SET_ADDRESS_SETTLE 10 /* ms */
-+#define USB_RESUME_DELAY (50*5) /* ms */
-+#define USB_RESUME_WAIT 50 /* ms */
-+#define USB_RESUME_RECOVERY 50 /* ms */
-+#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
-+#endif
-+
-+#define USB_MIN_POWER 100 /* mA */
-+#define USB_MAX_POWER 500 /* mA */
-+
-+#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
-+
-+#define USB_UNCONFIG_NO 0
-+#define USB_UNCONFIG_INDEX (-1)
-+
-+/*** ioctl() related stuff ***/
-+
-+struct usb_ctl_request {
-+ int ucr_addr;
-+ usb_device_request_t ucr_request;
-+ void *ucr_data;
-+ int ucr_flags;
-+#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
-+ int ucr_actlen; /* actual length transferred */
-+};
-+
-+struct usb_alt_interface {
-+ int uai_config_index;
-+ int uai_interface_index;
-+ int uai_alt_no;
-+};
-+
-+#define USB_CURRENT_CONFIG_INDEX (-1)
-+#define USB_CURRENT_ALT_INDEX (-1)
-+
-+struct usb_config_desc {
-+ int ucd_config_index;
-+ usb_config_descriptor_t ucd_desc;
-+};
-+
-+struct usb_interface_desc {
-+ int uid_config_index;
-+ int uid_interface_index;
-+ int uid_alt_index;
-+ usb_interface_descriptor_t uid_desc;
-+};
-+
-+struct usb_endpoint_desc {
-+ int ued_config_index;
-+ int ued_interface_index;
-+ int ued_alt_index;
-+ int ued_endpoint_index;
-+ usb_endpoint_descriptor_t ued_desc;
-+};
-+
-+struct usb_full_desc {
-+ int ufd_config_index;
-+ u_int ufd_size;
-+ u_char *ufd_data;
-+};
-+
-+struct usb_string_desc {
-+ int usd_string_index;
-+ int usd_language_id;
-+ usb_string_descriptor_t usd_desc;
-+};
-+
-+struct usb_ctl_report_desc {
-+ int ucrd_size;
-+ u_char ucrd_data[1024]; /* filled data size will vary */
-+};
-+
-+typedef struct { u_int32_t cookie; } usb_event_cookie_t;
-+
-+#define USB_MAX_DEVNAMES 4
-+#define USB_MAX_DEVNAMELEN 16
-+struct usb_device_info {
-+ u_int8_t udi_bus;
-+ u_int8_t udi_addr; /* device address */
-+ usb_event_cookie_t udi_cookie;
-+ char udi_product[USB_MAX_STRING_LEN];
-+ char udi_vendor[USB_MAX_STRING_LEN];
-+ char udi_release[8];
-+ u_int16_t udi_productNo;
-+ u_int16_t udi_vendorNo;
-+ u_int16_t udi_releaseNo;
-+ u_int8_t udi_class;
-+ u_int8_t udi_subclass;
-+ u_int8_t udi_protocol;
-+ u_int8_t udi_config;
-+ u_int8_t udi_speed;
-+#define USB_SPEED_UNKNOWN 0
-+#define USB_SPEED_LOW 1
-+#define USB_SPEED_FULL 2
-+#define USB_SPEED_HIGH 3
-+#define USB_SPEED_VARIABLE 4
-+#define USB_SPEED_SUPER 5
-+ int udi_power; /* power consumption in mA, 0 if selfpowered */
-+ int udi_nports;
-+ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
-+ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */
-+#define USB_PORT_ENABLED 0xff
-+#define USB_PORT_SUSPENDED 0xfe
-+#define USB_PORT_POWERED 0xfd
-+#define USB_PORT_DISABLED 0xfc
-+};
-+
-+struct usb_ctl_report {
-+ int ucr_report;
-+ u_char ucr_data[1024]; /* filled data size will vary */
-+};
-+
-+struct usb_device_stats {
-+ u_long uds_requests[4]; /* indexed by transfer type UE_* */
-+};
-+
-+#define WUSB_MIN_IE 0x80
-+#define WUSB_WCTA_IE 0x80
-+#define WUSB_WCONNECTACK_IE 0x81
-+#define WUSB_WHOSTINFO_IE 0x82
-+#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
-+#define WUHI_CA_RECONN 0x00
-+#define WUHI_CA_LIMITED 0x01
-+#define WUHI_CA_ALL 0x03
-+#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
-+#define WUSB_WCHCHANGEANNOUNCE_IE 0x83
-+#define WUSB_WDEV_DISCONNECT_IE 0x84
-+#define WUSB_WHOST_DISCONNECT_IE 0x85
-+#define WUSB_WRELEASE_CHANNEL_IE 0x86
-+#define WUSB_WWORK_IE 0x87
-+#define WUSB_WCHANNEL_STOP_IE 0x88
-+#define WUSB_WDEV_KEEPALIVE_IE 0x89
-+#define WUSB_WISOCH_DISCARD_IE 0x8A
-+#define WUSB_WRESETDEVICE_IE 0x8B
-+#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C
-+#define WUSB_MAX_IE 0x8C
-+
-+/* Device Notification Types */
-+
-+#define WUSB_DN_MIN 0x01
-+#define WUSB_DN_CONNECT 0x01
-+# define WUSB_DA_OLDCONN 0x00
-+# define WUSB_DA_NEWCONN 0x01
-+# define WUSB_DA_SELF_BEACON 0x02
-+# define WUSB_DA_DIR_BEACON 0x04
-+# define WUSB_DA_NO_BEACON 0x06
-+#define WUSB_DN_DISCONNECT 0x02
-+#define WUSB_DN_EPRDY 0x03
-+#define WUSB_DN_MASAVAILCHANGED 0x04
-+#define WUSB_DN_REMOTEWAKEUP 0x05
-+#define WUSB_DN_SLEEP 0x06
-+#define WUSB_DN_ALIVE 0x07
-+#define WUSB_DN_MAX 0x07
-+
-+#ifdef _MSC_VER
-+#include <pshpack1.h>
-+#endif
-+
-+/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */
-+typedef struct wusb_hndshk_data {
-+ uByte bMessageNumber;
-+ uByte bStatus;
-+ uByte tTKID[3];
-+ uByte bReserved;
-+ uByte CDID[16];
-+ uByte Nonce[16];
-+ uByte MIC[8];
-+} UPACKED wusb_hndshk_data_t;
-+#define WUSB_HANDSHAKE_LEN_FOR_MIC 38
-+
-+/* WUSB Connection Context */
-+typedef struct wusb_conn_context {
-+ uByte CHID [16];
-+ uByte CDID [16];
-+ uByte CK [16];
-+} UPACKED wusb_conn_context_t;
-+
-+/* WUSB Security Descriptor */
-+typedef struct wusb_security_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord wTotalLength;
-+ uByte bNumEncryptionTypes;
-+} UPACKED wusb_security_desc_t;
-+
-+/* WUSB Encryption Type Descriptor */
-+typedef struct wusb_encrypt_type_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+
-+ uByte bEncryptionType;
-+#define WUETD_UNSECURE 0
-+#define WUETD_WIRED 1
-+#define WUETD_CCM_1 2
-+#define WUETD_RSA_1 3
-+
-+ uByte bEncryptionValue;
-+ uByte bAuthKeyIndex;
-+} UPACKED wusb_encrypt_type_desc_t;
-+
-+/* WUSB Key Descriptor */
-+typedef struct wusb_key_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte tTKID[3];
-+ uByte bReserved;
-+ uByte KeyData[1]; /* variable length */
-+} UPACKED wusb_key_desc_t;
-+
-+/* WUSB BOS Descriptor (Binary device Object Store) */
-+typedef struct wusb_bos_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uWord wTotalLength;
-+ uByte bNumDeviceCaps;
-+} UPACKED wusb_bos_desc_t;
-+
-+#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02
-+typedef struct usb_dev_cap_20_ext_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+#define USB_20_EXT_LPM 0x02
-+ uDWord bmAttributes;
-+} UPACKED usb_dev_cap_20_ext_desc_t;
-+
-+#define USB_DEVICE_CAPABILITY_SS_USB 0x03
-+typedef struct usb_dev_cap_ss_usb {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+#define USB_DC_SS_USB_LTM_CAPABLE 0x02
-+ uByte bmAttributes;
-+#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01
-+#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02
-+#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04
-+#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08
-+ uWord wSpeedsSupported;
-+ uByte bFunctionalitySupport;
-+ uByte bU1DevExitLat;
-+ uWord wU2DevExitLat;
-+} UPACKED usb_dev_cap_ss_usb_t;
-+
-+#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04
-+typedef struct usb_dev_cap_container_id {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+ uByte bReserved;
-+ uByte containerID[16];
-+} UPACKED usb_dev_cap_container_id_t;
-+
-+/* Device Capability Type Codes */
-+#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
-+
-+/* Device Capability Descriptor */
-+typedef struct wusb_dev_cap_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+ uByte caps[1]; /* Variable length */
-+} UPACKED wusb_dev_cap_desc_t;
-+
-+/* Device Capability Descriptor */
-+typedef struct wusb_dev_cap_uwb_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bDevCapabilityType;
-+ uByte bmAttributes;
-+ uWord wPHYRates; /* Bitmap */
-+ uByte bmTFITXPowerInfo;
-+ uByte bmFFITXPowerInfo;
-+ uWord bmBandGroup;
-+ uByte bReserved;
-+} UPACKED wusb_dev_cap_uwb_desc_t;
-+
-+/* Wireless USB Endpoint Companion Descriptor */
-+typedef struct wusb_endpoint_companion_desc {
-+ uByte bLength;
-+ uByte bDescriptorType;
-+ uByte bMaxBurst;
-+ uByte bMaxSequence;
-+ uWord wMaxStreamDelay;
-+ uWord wOverTheAirPacketSize;
-+ uByte bOverTheAirInterval;
-+ uByte bmCompAttributes;
-+} UPACKED wusb_endpoint_companion_desc_t;
-+
-+/* Wireless USB Numeric Association M1 Data Structure */
-+typedef struct wusb_m1_data {
-+ uByte version;
-+ uWord langId;
-+ uByte deviceFriendlyNameLength;
-+ uByte sha_256_m3[32];
-+ uByte deviceFriendlyName[256];
-+} UPACKED wusb_m1_data_t;
-+
-+typedef struct wusb_m2_data {
-+ uByte version;
-+ uWord langId;
-+ uByte hostFriendlyNameLength;
-+ uByte pkh[384];
-+ uByte hostFriendlyName[256];
-+} UPACKED wusb_m2_data_t;
-+
-+typedef struct wusb_m3_data {
-+ uByte pkd[384];
-+ uByte nd;
-+} UPACKED wusb_m3_data_t;
-+
-+typedef struct wusb_m4_data {
-+ uDWord _attributeTypeIdAndLength_1;
-+ uWord associationTypeId;
-+
-+ uDWord _attributeTypeIdAndLength_2;
-+ uWord associationSubTypeId;
-+
-+ uDWord _attributeTypeIdAndLength_3;
-+ uDWord length;
-+
-+ uDWord _attributeTypeIdAndLength_4;
-+ uDWord associationStatus;
-+
-+ uDWord _attributeTypeIdAndLength_5;
-+ uByte chid[16];
-+
-+ uDWord _attributeTypeIdAndLength_6;
-+ uByte cdid[16];
-+
-+ uDWord _attributeTypeIdAndLength_7;
-+ uByte bandGroups[2];
-+} UPACKED wusb_m4_data_t;
-+
-+#ifdef _MSC_VER
-+#include <poppack.h>
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _USB_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg
---- linux-3.18.14/drivers/usb/host/dwc_otg/doc/doxygen.cfg 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,224 @@
-+# Doxyfile 1.3.9.1
-+
-+#---------------------------------------------------------------------------
-+# Project related configuration options
-+#---------------------------------------------------------------------------
-+PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
-+PROJECT_NUMBER = v3.00a
-+OUTPUT_DIRECTORY = ./doc/
-+CREATE_SUBDIRS = NO
-+OUTPUT_LANGUAGE = English
-+BRIEF_MEMBER_DESC = YES
-+REPEAT_BRIEF = YES
-+ABBREVIATE_BRIEF = "The $name class" \
-+ "The $name widget" \
-+ "The $name file" \
-+ is \
-+ provides \
-+ specifies \
-+ contains \
-+ represents \
-+ a \
-+ an \
-+ the
-+ALWAYS_DETAILED_SEC = NO
-+INLINE_INHERITED_MEMB = NO
-+FULL_PATH_NAMES = NO
-+STRIP_FROM_PATH =
-+STRIP_FROM_INC_PATH =
-+SHORT_NAMES = NO
-+JAVADOC_AUTOBRIEF = YES
-+MULTILINE_CPP_IS_BRIEF = NO
-+INHERIT_DOCS = YES
-+DISTRIBUTE_GROUP_DOC = NO
-+TAB_SIZE = 8
-+ALIASES =
-+OPTIMIZE_OUTPUT_FOR_C = YES
-+OPTIMIZE_OUTPUT_JAVA = NO
-+SUBGROUPING = YES
-+#---------------------------------------------------------------------------
-+# Build related configuration options
-+#---------------------------------------------------------------------------
-+EXTRACT_ALL = NO
-+EXTRACT_PRIVATE = YES
-+EXTRACT_STATIC = YES
-+EXTRACT_LOCAL_CLASSES = YES
-+EXTRACT_LOCAL_METHODS = NO
-+HIDE_UNDOC_MEMBERS = NO
-+HIDE_UNDOC_CLASSES = NO
-+HIDE_FRIEND_COMPOUNDS = NO
-+HIDE_IN_BODY_DOCS = NO
-+INTERNAL_DOCS = NO
-+CASE_SENSE_NAMES = NO
-+HIDE_SCOPE_NAMES = NO
-+SHOW_INCLUDE_FILES = YES
-+INLINE_INFO = YES
-+SORT_MEMBER_DOCS = NO
-+SORT_BRIEF_DOCS = NO
-+SORT_BY_SCOPE_NAME = NO
-+GENERATE_TODOLIST = YES
-+GENERATE_TESTLIST = YES
-+GENERATE_BUGLIST = YES
-+GENERATE_DEPRECATEDLIST= YES
-+ENABLED_SECTIONS =
-+MAX_INITIALIZER_LINES = 30
-+SHOW_USED_FILES = YES
-+SHOW_DIRECTORIES = YES
-+#---------------------------------------------------------------------------
-+# configuration options related to warning and progress messages
-+#---------------------------------------------------------------------------
-+QUIET = YES
-+WARNINGS = YES
-+WARN_IF_UNDOCUMENTED = NO
-+WARN_IF_DOC_ERROR = YES
-+WARN_FORMAT = "$file:$line: $text"
-+WARN_LOGFILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the input files
-+#---------------------------------------------------------------------------
-+INPUT = .
-+FILE_PATTERNS = *.c \
-+ *.h \
-+ ./linux/*.c \
-+ ./linux/*.h
-+RECURSIVE = NO
-+EXCLUDE = ./test/ \
-+ ./dwc_otg/.AppleDouble/
-+EXCLUDE_SYMLINKS = YES
-+EXCLUDE_PATTERNS = *.mod.*
-+EXAMPLE_PATH =
-+EXAMPLE_PATTERNS = *
-+EXAMPLE_RECURSIVE = NO
-+IMAGE_PATH =
-+INPUT_FILTER =
-+FILTER_PATTERNS =
-+FILTER_SOURCE_FILES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to source browsing
-+#---------------------------------------------------------------------------
-+SOURCE_BROWSER = YES
-+INLINE_SOURCES = NO
-+STRIP_CODE_COMMENTS = YES
-+REFERENCED_BY_RELATION = NO
-+REFERENCES_RELATION = NO
-+VERBATIM_HEADERS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the alphabetical class index
-+#---------------------------------------------------------------------------
-+ALPHABETICAL_INDEX = NO
-+COLS_IN_ALPHA_INDEX = 5
-+IGNORE_PREFIX =
-+#---------------------------------------------------------------------------
-+# configuration options related to the HTML output
-+#---------------------------------------------------------------------------
-+GENERATE_HTML = YES
-+HTML_OUTPUT = html
-+HTML_FILE_EXTENSION = .html
-+HTML_HEADER =
-+HTML_FOOTER =
-+HTML_STYLESHEET =
-+HTML_ALIGN_MEMBERS = YES
-+GENERATE_HTMLHELP = NO
-+CHM_FILE =
-+HHC_LOCATION =
-+GENERATE_CHI = NO
-+BINARY_TOC = NO
-+TOC_EXPAND = NO
-+DISABLE_INDEX = NO
-+ENUM_VALUES_PER_LINE = 4
-+GENERATE_TREEVIEW = YES
-+TREEVIEW_WIDTH = 250
-+#---------------------------------------------------------------------------
-+# configuration options related to the LaTeX output
-+#---------------------------------------------------------------------------
-+GENERATE_LATEX = NO
-+LATEX_OUTPUT = latex
-+LATEX_CMD_NAME = latex
-+MAKEINDEX_CMD_NAME = makeindex
-+COMPACT_LATEX = NO
-+PAPER_TYPE = a4wide
-+EXTRA_PACKAGES =
-+LATEX_HEADER =
-+PDF_HYPERLINKS = NO
-+USE_PDFLATEX = NO
-+LATEX_BATCHMODE = NO
-+LATEX_HIDE_INDICES = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the RTF output
-+#---------------------------------------------------------------------------
-+GENERATE_RTF = NO
-+RTF_OUTPUT = rtf
-+COMPACT_RTF = NO
-+RTF_HYPERLINKS = NO
-+RTF_STYLESHEET_FILE =
-+RTF_EXTENSIONS_FILE =
-+#---------------------------------------------------------------------------
-+# configuration options related to the man page output
-+#---------------------------------------------------------------------------
-+GENERATE_MAN = NO
-+MAN_OUTPUT = man
-+MAN_EXTENSION = .3
-+MAN_LINKS = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the XML output
-+#---------------------------------------------------------------------------
-+GENERATE_XML = NO
-+XML_OUTPUT = xml
-+XML_SCHEMA =
-+XML_DTD =
-+XML_PROGRAMLISTING = YES
-+#---------------------------------------------------------------------------
-+# configuration options for the AutoGen Definitions output
-+#---------------------------------------------------------------------------
-+GENERATE_AUTOGEN_DEF = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the Perl module output
-+#---------------------------------------------------------------------------
-+GENERATE_PERLMOD = NO
-+PERLMOD_LATEX = NO
-+PERLMOD_PRETTY = YES
-+PERLMOD_MAKEVAR_PREFIX =
-+#---------------------------------------------------------------------------
-+# Configuration options related to the preprocessor
-+#---------------------------------------------------------------------------
-+ENABLE_PREPROCESSING = YES
-+MACRO_EXPANSION = YES
-+EXPAND_ONLY_PREDEF = YES
-+SEARCH_INCLUDES = YES
-+INCLUDE_PATH =
-+INCLUDE_FILE_PATTERNS =
-+PREDEFINED = DEVICE_ATTR DWC_EN_ISOC
-+EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
-+SKIP_FUNCTION_MACROS = NO
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to external references
-+#---------------------------------------------------------------------------
-+TAGFILES =
-+GENERATE_TAGFILE =
-+ALLEXTERNALS = NO
-+EXTERNAL_GROUPS = YES
-+PERL_PATH = /usr/bin/perl
-+#---------------------------------------------------------------------------
-+# Configuration options related to the dot tool
-+#---------------------------------------------------------------------------
-+CLASS_DIAGRAMS = YES
-+HIDE_UNDOC_RELATIONS = YES
-+HAVE_DOT = NO
-+CLASS_GRAPH = YES
-+COLLABORATION_GRAPH = YES
-+UML_LOOK = NO
-+TEMPLATE_RELATIONS = NO
-+INCLUDE_GRAPH = YES
-+INCLUDED_BY_GRAPH = YES
-+CALL_GRAPH = NO
-+GRAPHICAL_HIERARCHY = YES
-+DOT_IMAGE_FORMAT = png
-+DOT_PATH =
-+DOTFILE_DIRS =
-+MAX_DOT_GRAPH_DEPTH = 1000
-+GENERATE_LEGEND = YES
-+DOT_CLEANUP = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to the search engine
-+#---------------------------------------------------------------------------
-+SEARCHENGINE = NO
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dummy_audio.c linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dummy_audio.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,1575 @@
-+/*
-+ * zero.c -- Gadget Zero, for USB development
-+ *
-+ * Copyright (C) 2003-2004 David Brownell
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions, and the following disclaimer,
-+ * without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ * to endorse or promote products derived from this software without
-+ * specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * Gadget Zero only needs two bulk endpoints, and is an example of how you
-+ * can write a hardware-agnostic gadget driver running inside a USB device.
-+ *
-+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
-+ * affect most of the driver.
-+ *
-+ * Use it with the Linux host/master side "usbtest" driver to get a basic
-+ * functional test of your device-side usb stack, or with "usb-skeleton".
-+ *
-+ * It supports two similar configurations. One sinks whatever the usb host
-+ * writes, and in return sources zeroes. The other loops whatever the host
-+ * writes back, so the host can read it. Module options include:
-+ *
-+ * buflen=N default N=4096, buffer size used
-+ * qlen=N default N=32, how many buffers in the loopback queue
-+ * loopdefault default false, list loopback config first
-+ *
-+ * Many drivers will only have one configuration, letting them be much
-+ * simpler if they also don't support high speed operation (like this
-+ * driver does).
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/delay.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/smp_lock.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/timer.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/uts.h>
-+#include <linux/version.h>
-+#include <linux/device.h>
-+#include <linux/moduleparam.h>
-+#include <linux/proc_fs.h>
-+
-+#include <asm/byteorder.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/system.h>
-+#include <asm/unaligned.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#include <linux/usb_gadget.h>
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
-+{
-+ int count = 0;
-+ u8 c;
-+ u16 uchar;
-+
-+ /* this insists on correct encodings, though not minimal ones.
-+ * BUT it currently rejects legit 4-byte UTF-8 code points,
-+ * which need surrogate pairs. (Unicode 3.1 can use them.)
-+ */
-+ while (len != 0 && (c = (u8) *s++) != 0) {
-+ if (unlikely(c & 0x80)) {
-+ // 2-byte sequence:
-+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+ if ((c & 0xe0) == 0xc0) {
-+ uchar = (c & 0x1f) << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ // 3-byte sequence (most CJKV characters):
-+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+ } else if ((c & 0xf0) == 0xe0) {
-+ uchar = (c & 0x0f) << 12;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c << 6;
-+
-+ c = (u8) *s++;
-+ if ((c & 0xc0) != 0xc0)
-+ goto fail;
-+ c &= 0x3f;
-+ uchar |= c;
-+
-+ /* no bogus surrogates */
-+ if (0xd800 <= uchar && uchar <= 0xdfff)
-+ goto fail;
-+
-+ // 4-byte sequence (surrogate pairs, currently rare):
-+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+ // (uuuuu = wwww + 1)
-+ // FIXME accept the surrogate code points (only)
-+
-+ } else
-+ goto fail;
-+ } else
-+ uchar = c;
-+ put_unaligned (cpu_to_le16 (uchar), cp++);
-+ count++;
-+ len--;
-+ }
-+ return count;
-+fail:
-+ return -1;
-+}
-+
-+
-+/**
-+ * usb_gadget_get_string - fill out a string descriptor
-+ * @table: of c strings encoded using UTF-8
-+ * @id: string id, from low byte of wValue in get string descriptor
-+ * @buf: at least 256 bytes
-+ *
-+ * Finds the UTF-8 string matching the ID, and converts it into a
-+ * string descriptor in utf16-le.
-+ * Returns length of descriptor (always even) or negative errno
-+ *
-+ * If your driver needs stings in multiple languages, you'll probably
-+ * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
-+ * using this routine after choosing which set of UTF-8 strings to use.
-+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
-+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
-+ * characters (which are also widely used in C strings).
-+ */
-+int
-+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
-+{
-+ struct usb_string *s;
-+ int len;
-+
-+ /* descriptor 0 has the language id */
-+ if (id == 0) {
-+ buf [0] = 4;
-+ buf [1] = USB_DT_STRING;
-+ buf [2] = (u8) table->language;
-+ buf [3] = (u8) (table->language >> 8);
-+ return 4;
-+ }
-+ for (s = table->strings; s && s->s; s++)
-+ if (s->id == id)
-+ break;
-+
-+ /* unrecognized: stall. */
-+ if (!s || !s->s)
-+ return -EINVAL;
-+
-+ /* string descriptors have length, tag, then UTF16-LE text */
-+ len = min ((size_t) 126, strlen (s->s));
-+ memset (buf + 2, 0, 2 * len); /* zero all the bytes */
-+ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
-+ if (len < 0)
-+ return -EINVAL;
-+ buf [0] = (len + 1) * 2;
-+ buf [1] = USB_DT_STRING;
-+ return buf [0];
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/**
-+ * usb_descriptor_fillbuf - fill buffer with descriptors
-+ * @buf: Buffer to be filled
-+ * @buflen: Size of buf
-+ * @src: Array of descriptor pointers, terminated by null pointer.
-+ *
-+ * Copies descriptors into the buffer, returning the length or a
-+ * negative error code if they can't all be copied. Useful when
-+ * assembling descriptors for an associated set of interfaces used
-+ * as part of configuring a composite device; or in other cases where
-+ * sets of descriptors need to be marshaled.
-+ */
-+int
-+usb_descriptor_fillbuf(void *buf, unsigned buflen,
-+ const struct usb_descriptor_header **src)
-+{
-+ u8 *dest = buf;
-+
-+ if (!src)
-+ return -EINVAL;
-+
-+ /* fill buffer from src[] until null descriptor ptr */
-+ for (; 0 != *src; src++) {
-+ unsigned len = (*src)->bLength;
-+
-+ if (len > buflen)
-+ return -EINVAL;
-+ memcpy(dest, *src, len);
-+ buflen -= len;
-+ dest += len;
-+ }
-+ return dest - (u8 *)buf;
-+}
-+
-+
-+/**
-+ * usb_gadget_config_buf - builts a complete configuration descriptor
-+ * @config: Header for the descriptor, including characteristics such
-+ * as power requirements and number of interfaces.
-+ * @desc: Null-terminated vector of pointers to the descriptors (interface,
-+ * endpoint, etc) defining all functions in this device configuration.
-+ * @buf: Buffer for the resulting configuration descriptor.
-+ * @length: Length of buffer. If this is not big enough to hold the
-+ * entire configuration descriptor, an error code will be returned.
-+ *
-+ * This copies descriptors into the response buffer, building a descriptor
-+ * for that configuration. It returns the buffer length or a negative
-+ * status code. The config.wTotalLength field is set to match the length
-+ * of the result, but other descriptor fields (including power usage and
-+ * interface count) must be set by the caller.
-+ *
-+ * Gadget drivers could use this when constructing a config descriptor
-+ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
-+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
-+ */
-+int usb_gadget_config_buf(
-+ const struct usb_config_descriptor *config,
-+ void *buf,
-+ unsigned length,
-+ const struct usb_descriptor_header **desc
-+)
-+{
-+ struct usb_config_descriptor *cp = buf;
-+ int len;
-+
-+ /* config descriptor first */
-+ if (length < USB_DT_CONFIG_SIZE || !desc)
-+ return -EINVAL;
-+ *cp = *config;
-+
-+ /* then interface/endpoint/class/vendor/... */
-+ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
-+ length - USB_DT_CONFIG_SIZE, desc);
-+ if (len < 0)
-+ return len;
-+ len += USB_DT_CONFIG_SIZE;
-+ if (len > 0xffff)
-+ return -EINVAL;
-+
-+ /* patch up the config descriptor */
-+ cp->bLength = USB_DT_CONFIG_SIZE;
-+ cp->bDescriptorType = USB_DT_CONFIG;
-+ cp->wTotalLength = cpu_to_le16(len);
-+ cp->bmAttributes |= USB_CONFIG_ATT_ONE;
-+ return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+#define RBUF_LEN (1024*1024)
-+static int rbuf_start;
-+static int rbuf_len;
-+static __u8 rbuf[RBUF_LEN];
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_VERSION "St Patrick's Day 2004"
-+
-+static const char shortname [] = "zero";
-+static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
-+
-+static const char source_sink [] = "source and sink data";
-+static const char loopback [] = "loop input to output";
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * driver assumes self-powered hardware, and
-+ * has no way for users to trigger remote wakeup.
-+ *
-+ * this version autoconfigures as much as possible,
-+ * which is reasonable for most "bulk-only" drivers.
-+ */
-+static const char *EP_IN_NAME; /* source */
-+static const char *EP_OUT_NAME; /* sink */
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* big enough to hold our biggest descriptor */
-+#define USB_BUFSIZ 512
-+
-+struct zero_dev {
-+ spinlock_t lock;
-+ struct usb_gadget *gadget;
-+ struct usb_request *req; /* for control responses */
-+
-+ /* when configured, we have one of two configs:
-+ * - source data (in to host) and sink it (out from host)
-+ * - or loop it back (out from host back in to host)
-+ */
-+ u8 config;
-+ struct usb_ep *in_ep, *out_ep;
-+
-+ /* autoresume timer */
-+ struct timer_list resume;
-+};
-+
-+#define xprintk(d,level,fmt,args...) \
-+ dev_printk(level , &(d)->gadget->dev , fmt , ## args)
-+
-+#ifdef DEBUG
-+#define DBG(dev,fmt,args...) \
-+ xprintk(dev , KERN_DEBUG , fmt , ## args)
-+#else
-+#define DBG(dev,fmt,args...) \
-+ do { } while (0)
-+#endif /* DEBUG */
-+
-+#ifdef VERBOSE
-+#define VDBG DBG
-+#else
-+#define VDBG(dev,fmt,args...) \
-+ do { } while (0)
-+#endif /* VERBOSE */
-+
-+#define ERROR(dev,fmt,args...) \
-+ xprintk(dev , KERN_ERR , fmt , ## args)
-+#define WARN(dev,fmt,args...) \
-+ xprintk(dev , KERN_WARNING , fmt , ## args)
-+#define INFO(dev,fmt,args...) \
-+ xprintk(dev , KERN_INFO , fmt , ## args)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static unsigned buflen = 4096;
-+static unsigned qlen = 32;
-+static unsigned pattern = 0;
-+
-+module_param (buflen, uint, S_IRUGO|S_IWUSR);
-+module_param (qlen, uint, S_IRUGO|S_IWUSR);
-+module_param (pattern, uint, S_IRUGO|S_IWUSR);
-+
-+/*
-+ * if it's nonzero, autoresume says how many seconds to wait
-+ * before trying to wake up the host after suspend.
-+ */
-+static unsigned autoresume = 0;
-+module_param (autoresume, uint, 0);
-+
-+/*
-+ * Normally the "loopback" configuration is second (index 1) so
-+ * it's not the default. Here's where to change that order, to
-+ * work better with hosts where config changes are problematic.
-+ * Or controllers (like superh) that only support one config.
-+ */
-+static int loopdefault = 0;
-+
-+module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Thanks to NetChip Technologies for donating this product ID.
-+ *
-+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
-+ * Instead: allocate your own, using normal USB-IF procedures.
-+ */
-+#ifndef CONFIG_USB_ZERO_HNPTEST
-+#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
-+#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
-+#else
-+#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
-+#define DRIVER_PRODUCT_NUM 0xbadd
-+#endif
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full)
-+ * configuration descriptors are built on demand.
-+ */
-+
-+/*
-+#define STRING_MANUFACTURER 25
-+#define STRING_PRODUCT 42
-+#define STRING_SERIAL 101
-+*/
-+#define STRING_MANUFACTURER 1
-+#define STRING_PRODUCT 2
-+#define STRING_SERIAL 3
-+
-+#define STRING_SOURCE_SINK 250
-+#define STRING_LOOPBACK 251
-+
-+/*
-+ * This device advertises two configurations; these numbers work
-+ * on a pxa250 as well as more flexible hardware.
-+ */
-+#define CONFIG_SOURCE_SINK 3
-+#define CONFIG_LOOPBACK 2
-+
-+/*
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+
-+ .bcdUSB = __constant_cpu_to_le16 (0x0200),
-+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-+
-+ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
-+ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
-+ .iManufacturer = STRING_MANUFACTURER,
-+ .iProduct = STRING_PRODUCT,
-+ .iSerialNumber = STRING_SERIAL,
-+ .bNumConfigurations = 2,
-+};
-+*/
-+static struct usb_device_descriptor
-+device_desc = {
-+ .bLength = sizeof device_desc,
-+ .bDescriptorType = USB_DT_DEVICE,
-+ .bcdUSB = __constant_cpu_to_le16 (0x0100),
-+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
-+ .bDeviceSubClass = 0,
-+ .bDeviceProtocol = 0,
-+ .bMaxPacketSize0 = 64,
-+ .bcdDevice = __constant_cpu_to_le16 (0x0100),
-+ .idVendor = __constant_cpu_to_le16 (0x0499),
-+ .idProduct = __constant_cpu_to_le16 (0x3002),
-+ .iManufacturer = STRING_MANUFACTURER,
-+ .iProduct = STRING_PRODUCT,
-+ .iSerialNumber = STRING_SERIAL,
-+ .bNumConfigurations = 1,
-+};
-+
-+static struct usb_config_descriptor
-+z_config = {
-+ .bLength = sizeof z_config,
-+ .bDescriptorType = USB_DT_CONFIG,
-+
-+ /* compute wTotalLength on the fly */
-+ .bNumInterfaces = 2,
-+ .bConfigurationValue = 1,
-+ .iConfiguration = 0,
-+ .bmAttributes = 0x40,
-+ .bMaxPower = 0, /* self-powered */
-+};
-+
-+
-+static struct usb_otg_descriptor
-+otg_descriptor = {
-+ .bLength = sizeof otg_descriptor,
-+ .bDescriptorType = USB_DT_OTG,
-+
-+ .bmAttributes = USB_OTG_SRP,
-+};
-+
-+/* one interface in each configuration */
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+
-+/*
-+ * usb 2.0 devices need to expose both high speed and full speed
-+ * descriptors, unless they only run at full speed.
-+ *
-+ * that means alternate endpoint descriptors (bigger packets)
-+ * and a "device qualifier" ... plus more construction options
-+ * for the config descriptor.
-+ */
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+ .bLength = sizeof dev_qualifier,
-+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
-+
-+ .bcdUSB = __constant_cpu_to_le16 (0x0200),
-+ .bDeviceClass = USB_CLASS_VENDOR_SPEC,
-+
-+ .bNumConfigurations = 2,
-+};
-+
-+
-+struct usb_cs_as_general_descriptor {
-+ __u8 bLength;
-+ __u8 bDescriptorType;
-+
-+ __u8 bDescriptorSubType;
-+ __u8 bTerminalLink;
-+ __u8 bDelay;
-+ __u16 wFormatTag;
-+} __attribute__ ((packed));
-+
-+struct usb_cs_as_format_descriptor {
-+ __u8 bLength;
-+ __u8 bDescriptorType;
-+
-+ __u8 bDescriptorSubType;
-+ __u8 bFormatType;
-+ __u8 bNrChannels;
-+ __u8 bSubframeSize;
-+ __u8 bBitResolution;
-+ __u8 bSamfreqType;
-+ __u8 tLowerSamFreq[3];
-+ __u8 tUpperSamFreq[3];
-+} __attribute__ ((packed));
-+
-+static const struct usb_interface_descriptor
-+z_audio_control_if_desc = {
-+ .bLength = sizeof z_audio_control_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 0,
-+ .bAlternateSetting = 0,
-+ .bNumEndpoints = 0,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x1,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc = {
-+ .bLength = sizeof z_audio_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 1,
-+ .bAlternateSetting = 0,
-+ .bNumEndpoints = 0,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x2,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc2 = {
-+ .bLength = sizeof z_audio_if_desc,
-+ .bDescriptorType = USB_DT_INTERFACE,
-+ .bInterfaceNumber = 1,
-+ .bAlternateSetting = 1,
-+ .bNumEndpoints = 1,
-+ .bInterfaceClass = USB_CLASS_AUDIO,
-+ .bInterfaceSubClass = 0x2,
-+ .bInterfaceProtocol = 0,
-+ .iInterface = 0,
-+};
-+
-+static const struct usb_cs_as_general_descriptor
-+z_audio_cs_as_if_desc = {
-+ .bLength = 7,
-+ .bDescriptorType = 0x24,
-+
-+ .bDescriptorSubType = 0x01,
-+ .bTerminalLink = 0x01,
-+ .bDelay = 0x0,
-+ .wFormatTag = __constant_cpu_to_le16 (0x0001)
-+};
-+
-+
-+static const struct usb_cs_as_format_descriptor
-+z_audio_cs_as_format_desc = {
-+ .bLength = 0xe,
-+ .bDescriptorType = 0x24,
-+
-+ .bDescriptorSubType = 2,
-+ .bFormatType = 1,
-+ .bNrChannels = 1,
-+ .bSubframeSize = 1,
-+ .bBitResolution = 8,
-+ .bSamfreqType = 0,
-+ .tLowerSamFreq = {0x7e, 0x13, 0x00},
-+ .tUpperSamFreq = {0xe2, 0xd6, 0x00},
-+};
-+
-+static const struct usb_endpoint_descriptor
-+z_iso_ep = {
-+ .bLength = 0x09,
-+ .bDescriptorType = 0x05,
-+ .bEndpointAddress = 0x04,
-+ .bmAttributes = 0x09,
-+ .wMaxPacketSize = 0x0038,
-+ .bInterval = 0x01,
-+ .bRefresh = 0x00,
-+ .bSynchAddress = 0x00,
-+};
-+
-+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+// 9 bytes
-+static char z_ac_interface_header_desc[] =
-+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
-+
-+// 12 bytes
-+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
-+ 0x03, 0x00, 0x00, 0x00};
-+// 13 bytes
-+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
-+ 0x02, 0x00, 0x02, 0x00, 0x00};
-+// 9 bytes
-+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
-+ 0x00};
-+
-+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
-+ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
-+ 0x00};
-+
-+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
-+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
-+ 0x00};
-+
-+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+
-+
-+static const struct usb_descriptor_header *z_function [] = {
-+ (struct usb_descriptor_header *) &z_audio_control_if_desc,
-+ (struct usb_descriptor_header *) &z_ac_interface_header_desc,
-+ (struct usb_descriptor_header *) &z_0,
-+ (struct usb_descriptor_header *) &z_1,
-+ (struct usb_descriptor_header *) &z_2,
-+ (struct usb_descriptor_header *) &z_audio_if_desc,
-+ (struct usb_descriptor_header *) &z_audio_if_desc2,
-+ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
-+ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
-+ (struct usb_descriptor_header *) &z_iso_ep,
-+ (struct usb_descriptor_header *) &z_iso_ep2,
-+ (struct usb_descriptor_header *) &za_0,
-+ (struct usb_descriptor_header *) &za_1,
-+ (struct usb_descriptor_header *) &za_2,
-+ (struct usb_descriptor_header *) &za_3,
-+ (struct usb_descriptor_header *) &za_4,
-+ (struct usb_descriptor_header *) &za_5,
-+ (struct usb_descriptor_header *) &za_6,
-+ (struct usb_descriptor_header *) &za_7,
-+ (struct usb_descriptor_header *) &za_8,
-+ (struct usb_descriptor_header *) &za_9,
-+ (struct usb_descriptor_header *) &za_10,
-+ (struct usb_descriptor_header *) &za_11,
-+ (struct usb_descriptor_header *) &za_12,
-+ (struct usb_descriptor_header *) &za_13,
-+ (struct usb_descriptor_header *) &za_14,
-+ (struct usb_descriptor_header *) &za_15,
-+ (struct usb_descriptor_header *) &za_16,
-+ (struct usb_descriptor_header *) &za_17,
-+ (struct usb_descriptor_header *) &za_18,
-+ (struct usb_descriptor_header *) &za_19,
-+ (struct usb_descriptor_header *) &za_20,
-+ (struct usb_descriptor_header *) &za_21,
-+ (struct usb_descriptor_header *) &za_22,
-+ (struct usb_descriptor_header *) &za_23,
-+ (struct usb_descriptor_header *) &za_24,
-+ NULL,
-+};
-+
-+/* maxpacket and other transfer characteristics vary by speed. */
-+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
-+
-+#else
-+
-+/* if there's no high speed support, maxpacket doesn't change. */
-+#define ep_desc(g,hs,fs) fs
-+
-+#endif /* !CONFIG_USB_GADGET_DUALSPEED */
-+
-+static char manufacturer [40];
-+//static char serial [40];
-+static char serial [] = "Ser 00 em";
-+
-+/* static strings, in UTF-8 */
-+static struct usb_string strings [] = {
-+ { STRING_MANUFACTURER, manufacturer, },
-+ { STRING_PRODUCT, longname, },
-+ { STRING_SERIAL, serial, },
-+ { STRING_LOOPBACK, loopback, },
-+ { STRING_SOURCE_SINK, source_sink, },
-+ { } /* end of list */
-+};
-+
-+static struct usb_gadget_strings stringtab = {
-+ .language = 0x0409, /* en-us */
-+ .strings = strings,
-+};
-+
-+/*
-+ * config descriptors are also handcrafted. these must agree with code
-+ * that sets configurations, and with code managing interfaces and their
-+ * altsettings. other complexity may come from:
-+ *
-+ * - high speed support, including "other speed config" rules
-+ * - multiple configurations
-+ * - interfaces with alternate settings
-+ * - embedded class or vendor-specific descriptors
-+ *
-+ * this handles high speed, and has a second config that could as easily
-+ * have been an alternate interface setting (on most hardware).
-+ *
-+ * NOTE: to demonstrate (and test) more USB capabilities, this driver
-+ * should include an altsetting to test interrupt transfers, including
-+ * high bandwidth modes at high speed. (Maybe work like Intel's test
-+ * device?)
-+ */
-+static int
-+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
-+{
-+ int len;
-+ const struct usb_descriptor_header **function;
-+
-+ function = z_function;
-+ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
-+ if (len < 0)
-+ return len;
-+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+ return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_request *
-+alloc_ep_req (struct usb_ep *ep, unsigned length)
-+{
-+ struct usb_request *req;
-+
-+ req = usb_ep_alloc_request (ep, GFP_ATOMIC);
-+ if (req) {
-+ req->length = length;
-+ req->buf = usb_ep_alloc_buffer (ep, length,
-+ &req->dma, GFP_ATOMIC);
-+ if (!req->buf) {
-+ usb_ep_free_request (ep, req);
-+ req = NULL;
-+ }
-+ }
-+ return req;
-+}
-+
-+static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
-+{
-+ if (req->buf)
-+ usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
-+ usb_ep_free_request (ep, req);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* optionally require specific source/sink data patterns */
-+
-+static int
-+check_read_data (
-+ struct zero_dev *dev,
-+ struct usb_ep *ep,
-+ struct usb_request *req
-+)
-+{
-+ unsigned i;
-+ u8 *buf = req->buf;
-+
-+ for (i = 0; i < req->actual; i++, buf++) {
-+ switch (pattern) {
-+ /* all-zeroes has no synchronization issues */
-+ case 0:
-+ if (*buf == 0)
-+ continue;
-+ break;
-+ /* mod63 stays in sync with short-terminated transfers,
-+ * or otherwise when host and gadget agree on how large
-+ * each usb transfer request should be. resync is done
-+ * with set_interface or set_config.
-+ */
-+ case 1:
-+ if (*buf == (u8)(i % 63))
-+ continue;
-+ break;
-+ }
-+ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
-+ usb_ep_set_halt (ep);
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_reset_config (struct zero_dev *dev)
-+{
-+ if (dev->config == 0)
-+ return;
-+
-+ DBG (dev, "reset config\n");
-+
-+ /* just disable endpoints, forcing completion of pending i/o.
-+ * all our completion handlers free their requests in this case.
-+ */
-+ if (dev->in_ep) {
-+ usb_ep_disable (dev->in_ep);
-+ dev->in_ep = NULL;
-+ }
-+ if (dev->out_ep) {
-+ usb_ep_disable (dev->out_ep);
-+ dev->out_ep = NULL;
-+ }
-+ dev->config = 0;
-+ del_timer (&dev->resume);
-+}
-+
-+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
-+
-+static void
-+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+ struct zero_dev *dev = ep->driver_data;
-+ int status = req->status;
-+ int i, j;
-+
-+ switch (status) {
-+
-+ case 0: /* normal completion? */
-+ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
-+ for (i=0, j=rbuf_start; i<req->actual; i++) {
-+ //printk ("%02x ", ((__u8*)req->buf)[i]);
-+ rbuf[j] = ((__u8*)req->buf)[i];
-+ j++;
-+ if (j >= RBUF_LEN) j=0;
-+ }
-+ rbuf_start = j;
-+ //printk ("\n\n");
-+
-+ if (rbuf_len < RBUF_LEN) {
-+ rbuf_len += req->actual;
-+ if (rbuf_len > RBUF_LEN) {
-+ rbuf_len = RBUF_LEN;
-+ }
-+ }
-+
-+ break;
-+
-+ /* this endpoint is normally active while we're configured */
-+ case -ECONNABORTED: /* hardware forced ep reset */
-+ case -ECONNRESET: /* request dequeued */
-+ case -ESHUTDOWN: /* disconnect from host */
-+ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
-+ req->actual, req->length);
-+ if (ep == dev->out_ep)
-+ check_read_data (dev, ep, req);
-+ free_ep_req (ep, req);
-+ return;
-+
-+ case -EOVERFLOW: /* buffer overrun on read means that
-+ * we didn't provide a big enough
-+ * buffer.
-+ */
-+ default:
-+#if 1
-+ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
-+ status, req->actual, req->length);
-+#endif
-+ case -EREMOTEIO: /* short read */
-+ break;
-+ }
-+
-+ status = usb_ep_queue (ep, req, GFP_ATOMIC);
-+ if (status) {
-+ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
-+ ep->name, req->length, status);
-+ usb_ep_set_halt (ep);
-+ /* FIXME recover later ... somehow */
-+ }
-+}
-+
-+static struct usb_request *
-+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
-+{
-+ struct usb_request *req;
-+ int status;
-+
-+ req = alloc_ep_req (ep, 512);
-+ if (!req)
-+ return NULL;
-+
-+ req->complete = zero_isoc_complete;
-+
-+ status = usb_ep_queue (ep, req, gfp_flags);
-+ if (status) {
-+ struct zero_dev *dev = ep->driver_data;
-+
-+ ERROR (dev, "start %s --> %d\n", ep->name, status);
-+ free_ep_req (ep, req);
-+ req = NULL;
-+ }
-+
-+ return req;
-+}
-+
-+/* change our operational config. this code must agree with the code
-+ * that returns config descriptors, and altsetting code.
-+ *
-+ * it's also responsible for power management interactions. some
-+ * configurations might not work with our current power sources.
-+ *
-+ * note that some device controller hardware will constrain what this
-+ * code can do, perhaps by disallowing more than one configuration or
-+ * by limiting configuration choices (like the pxa2xx).
-+ */
-+static int
-+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
-+{
-+ int result = 0;
-+ struct usb_gadget *gadget = dev->gadget;
-+ const struct usb_endpoint_descriptor *d;
-+ struct usb_ep *ep;
-+
-+ if (number == dev->config)
-+ return 0;
-+
-+ zero_reset_config (dev);
-+
-+ gadget_for_each_ep (ep, gadget) {
-+
-+ if (strcmp (ep->name, "ep4") == 0) {
-+
-+ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
-+ result = usb_ep_enable (ep, d);
-+
-+ if (result == 0) {
-+ ep->driver_data = dev;
-+ dev->in_ep = ep;
-+
-+ if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
-+
-+ dev->in_ep = ep;
-+ continue;
-+ }
-+
-+ usb_ep_disable (ep);
-+ result = -EIO;
-+ }
-+ }
-+
-+ }
-+
-+ dev->config = number;
-+ return result;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+ if (req->status || req->actual != req->length)
-+ DBG ((struct zero_dev *) ep->driver_data,
-+ "setup complete --> %d, %d/%d\n",
-+ req->status, req->actual, req->length);
-+}
-+
-+/*
-+ * The setup() callback implements all the ep0 functionality that's
-+ * not handled lower down, in hardware or the hardware driver (like
-+ * device and endpoint feature flags, and their status). It's all
-+ * housekeeping for the gadget function we're implementing. Most of
-+ * the work is in config-specific setup.
-+ */
-+static int
-+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+ struct usb_request *req = dev->req;
-+ int value = -EOPNOTSUPP;
-+
-+ /* usually this stores reply data in the pre-allocated ep0 buffer,
-+ * but config change events will reconfigure hardware.
-+ */
-+ req->zero = 0;
-+ switch (ctrl->bRequest) {
-+
-+ case USB_REQ_GET_DESCRIPTOR:
-+
-+ switch (ctrl->wValue >> 8) {
-+
-+ case USB_DT_DEVICE:
-+ value = min (ctrl->wLength, (u16) sizeof device_desc);
-+ memcpy (req->buf, &device_desc, value);
-+ break;
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ case USB_DT_DEVICE_QUALIFIER:
-+ if (!gadget->is_dualspeed)
-+ break;
-+ value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
-+ memcpy (req->buf, &dev_qualifier, value);
-+ break;
-+
-+ case USB_DT_OTHER_SPEED_CONFIG:
-+ if (!gadget->is_dualspeed)
-+ break;
-+ // FALLTHROUGH
-+#endif /* CONFIG_USB_GADGET_DUALSPEED */
-+ case USB_DT_CONFIG:
-+ value = config_buf (gadget, req->buf,
-+ ctrl->wValue >> 8,
-+ ctrl->wValue & 0xff);
-+ if (value >= 0)
-+ value = min (ctrl->wLength, (u16) value);
-+ break;
-+
-+ case USB_DT_STRING:
-+ /* wIndex == language code.
-+ * this driver only handles one language, you can
-+ * add string tables for other languages, using
-+ * any UTF-8 characters
-+ */
-+ value = usb_gadget_get_string (&stringtab,
-+ ctrl->wValue & 0xff, req->buf);
-+ if (value >= 0) {
-+ value = min (ctrl->wLength, (u16) value);
-+ }
-+ break;
-+ }
-+ break;
-+
-+ /* currently two configs, two speeds */
-+ case USB_REQ_SET_CONFIGURATION:
-+ if (ctrl->bRequestType != 0)
-+ goto unknown;
-+
-+ spin_lock (&dev->lock);
-+ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
-+ spin_unlock (&dev->lock);
-+ break;
-+ case USB_REQ_GET_CONFIGURATION:
-+ if (ctrl->bRequestType != USB_DIR_IN)
-+ goto unknown;
-+ *(u8 *)req->buf = dev->config;
-+ value = min (ctrl->wLength, (u16) 1);
-+ break;
-+
-+ /* until we add altsetting support, or other interfaces,
-+ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
-+ * and already killed pending endpoint I/O.
-+ */
-+ case USB_REQ_SET_INTERFACE:
-+
-+ if (ctrl->bRequestType != USB_RECIP_INTERFACE)
-+ goto unknown;
-+ spin_lock (&dev->lock);
-+ if (dev->config) {
-+ u8 config = dev->config;
-+
-+ /* resets interface configuration, forgets about
-+ * previous transaction state (queued bufs, etc)
-+ * and re-inits endpoint state (toggle etc)
-+ * no response queued, just zero status == success.
-+ * if we had more than one interface we couldn't
-+ * use this "reset the config" shortcut.
-+ */
-+ zero_reset_config (dev);
-+ zero_set_config (dev, config, GFP_ATOMIC);
-+ value = 0;
-+ }
-+ spin_unlock (&dev->lock);
-+ break;
-+ case USB_REQ_GET_INTERFACE:
-+ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
-+ value = ctrl->wLength;
-+ break;
-+ }
-+ else {
-+ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
-+ goto unknown;
-+ if (!dev->config)
-+ break;
-+ if (ctrl->wIndex != 0) {
-+ value = -EDOM;
-+ break;
-+ }
-+ *(u8 *)req->buf = 0;
-+ value = min (ctrl->wLength, (u16) 1);
-+ }
-+ break;
-+
-+ /*
-+ * These are the same vendor-specific requests supported by
-+ * Intel's USB 2.0 compliance test devices. We exceed that
-+ * device spec by allowing multiple-packet requests.
-+ */
-+ case 0x5b: /* control WRITE test -- fill the buffer */
-+ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
-+ goto unknown;
-+ if (ctrl->wValue || ctrl->wIndex)
-+ break;
-+ /* just read that many bytes into the buffer */
-+ if (ctrl->wLength > USB_BUFSIZ)
-+ break;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x5c: /* control READ test -- return the buffer */
-+ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
-+ goto unknown;
-+ if (ctrl->wValue || ctrl->wIndex)
-+ break;
-+ /* expect those bytes are still in the buffer; send back */
-+ if (ctrl->wLength > USB_BUFSIZ
-+ || ctrl->wLength != req->length)
-+ break;
-+ value = ctrl->wLength;
-+ break;
-+
-+ case 0x01: // SET_CUR
-+ case 0x02:
-+ case 0x03:
-+ case 0x04:
-+ case 0x05:
-+ value = ctrl->wLength;
-+ break;
-+ case 0x81:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0xe3;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x00;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x81;
-+ //((u8*)req->buf)[1] = 0x81;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x82:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0xc3;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x00;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x82;
-+ //((u8*)req->buf)[1] = 0x82;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x83:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0x00;
-+ break;
-+ case 0x0300:
-+ ((u8*)req->buf)[0] = 0x60;
-+ break;
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x18;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x83;
-+ //((u8*)req->buf)[1] = 0x83;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x84:
-+ switch (ctrl->wValue) {
-+ case 0x0201:
-+ case 0x0202:
-+ ((u8*)req->buf)[0] = 0x00;
-+ ((u8*)req->buf)[1] = 0x01;
-+ break;
-+ case 0x0300:
-+ case 0x0500:
-+ ((u8*)req->buf)[0] = 0x08;
-+ break;
-+ }
-+ //((u8*)req->buf)[0] = 0x84;
-+ //((u8*)req->buf)[1] = 0x84;
-+ value = ctrl->wLength;
-+ break;
-+ case 0x85:
-+ ((u8*)req->buf)[0] = 0x85;
-+ ((u8*)req->buf)[1] = 0x85;
-+ value = ctrl->wLength;
-+ break;
-+
-+
-+ default:
-+unknown:
-+ printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
-+ ctrl->bRequestType, ctrl->bRequest,
-+ ctrl->wValue, ctrl->wIndex, ctrl->wLength);
-+ }
-+
-+ /* respond with data transfer before status phase? */
-+ if (value >= 0) {
-+ req->length = value;
-+ req->zero = value < ctrl->wLength
-+ && (value % gadget->ep0->maxpacket) == 0;
-+ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
-+ if (value < 0) {
-+ DBG (dev, "ep_queue < 0 --> %d\n", value);
-+ req->status = 0;
-+ zero_setup_complete (gadget->ep0, req);
-+ }
-+ }
-+
-+ /* device either stalls (value < 0) or reports success */
-+ return value;
-+}
-+
-+static void
-+zero_disconnect (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave (&dev->lock, flags);
-+ zero_reset_config (dev);
-+
-+ /* a more significant application might have some non-usb
-+ * activities to quiesce here, saving resources like power
-+ * or pushing the notification up a network stack.
-+ */
-+ spin_unlock_irqrestore (&dev->lock, flags);
-+
-+ /* next we may get setup() calls to enumerate new connections;
-+ * or an unbind() during shutdown (including removing module).
-+ */
-+}
-+
-+static void
-+zero_autoresume (unsigned long _dev)
-+{
-+ struct zero_dev *dev = (struct zero_dev *) _dev;
-+ int status;
-+
-+ /* normally the host would be woken up for something
-+ * more significant than just a timer firing...
-+ */
-+ if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
-+ status = usb_gadget_wakeup (dev->gadget);
-+ DBG (dev, "wakeup --> %d\n", status);
-+ }
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_unbind (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ DBG (dev, "unbind\n");
-+
-+ /* we've already been disconnected ... no i/o is active */
-+ if (dev->req)
-+ free_ep_req (gadget->ep0, dev->req);
-+ del_timer_sync (&dev->resume);
-+ kfree (dev);
-+ set_gadget_data (gadget, NULL);
-+}
-+
-+static int
-+zero_bind (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev;
-+ //struct usb_ep *ep;
-+
-+ printk("binding\n");
-+ /*
-+ * DRIVER POLICY CHOICE: you may want to do this differently.
-+ * One thing to avoid is reusing a bcdDevice revision code
-+ * with different host-visible configurations or behavior
-+ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
-+ */
-+ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
-+
-+
-+ /* ok, we made sense of the hardware ... */
-+ dev = kmalloc (sizeof *dev, SLAB_KERNEL);
-+ if (!dev)
-+ return -ENOMEM;
-+ memset (dev, 0, sizeof *dev);
-+ spin_lock_init (&dev->lock);
-+ dev->gadget = gadget;
-+ set_gadget_data (gadget, dev);
-+
-+ /* preallocate control response and buffer */
-+ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
-+ if (!dev->req)
-+ goto enomem;
-+ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
-+ &dev->req->dma, GFP_KERNEL);
-+ if (!dev->req->buf)
-+ goto enomem;
-+
-+ dev->req->complete = zero_setup_complete;
-+
-+ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
-+
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ /* assume ep0 uses the same value for both speeds ... */
-+ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
-+
-+ /* and that all endpoints are dual-speed */
-+ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
-+ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
-+#endif
-+
-+ usb_gadget_set_selfpowered (gadget);
-+
-+ init_timer (&dev->resume);
-+ dev->resume.function = zero_autoresume;
-+ dev->resume.data = (unsigned long) dev;
-+
-+ gadget->ep0->driver_data = dev;
-+
-+ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
-+ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
-+ EP_OUT_NAME, EP_IN_NAME);
-+
-+ snprintf (manufacturer, sizeof manufacturer,
-+ UTS_SYSNAME " " UTS_RELEASE " with %s",
-+ gadget->name);
-+
-+ return 0;
-+
-+enomem:
-+ zero_unbind (gadget);
-+ return -ENOMEM;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_suspend (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ if (gadget->speed == USB_SPEED_UNKNOWN)
-+ return;
-+
-+ if (autoresume) {
-+ mod_timer (&dev->resume, jiffies + (HZ * autoresume));
-+ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
-+ } else
-+ DBG (dev, "suspend\n");
-+}
-+
-+static void
-+zero_resume (struct usb_gadget *gadget)
-+{
-+ struct zero_dev *dev = get_gadget_data (gadget);
-+
-+ DBG (dev, "resume\n");
-+ del_timer (&dev->resume);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver zero_driver = {
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+ .speed = USB_SPEED_HIGH,
-+#else
-+ .speed = USB_SPEED_FULL,
-+#endif
-+ .function = (char *) longname,
-+ .bind = zero_bind,
-+ .unbind = zero_unbind,
-+
-+ .setup = zero_setup,
-+ .disconnect = zero_disconnect,
-+
-+ .suspend = zero_suspend,
-+ .resume = zero_resume,
-+
-+ .driver = {
-+ .name = (char *) shortname,
-+ // .shutdown = ...
-+ // .suspend = ...
-+ // .resume = ...
-+ },
-+};
-+
-+MODULE_AUTHOR ("David Brownell");
-+MODULE_LICENSE ("Dual BSD/GPL");
-+
-+static struct proc_dir_entry *pdir, *pfile;
-+
-+static int isoc_read_data (char *page, char **start,
-+ off_t off, int count,
-+ int *eof, void *data)
-+{
-+ int i;
-+ static int c = 0;
-+ static int done = 0;
-+ static int s = 0;
-+
-+/*
-+ printk ("\ncount: %d\n", count);
-+ printk ("rbuf_start: %d\n", rbuf_start);
-+ printk ("rbuf_len: %d\n", rbuf_len);
-+ printk ("off: %d\n", off);
-+ printk ("start: %p\n\n", *start);
-+*/
-+ if (done) {
-+ c = 0;
-+ done = 0;
-+ *eof = 1;
-+ return 0;
-+ }
-+
-+ if (c == 0) {
-+ if (rbuf_len == RBUF_LEN)
-+ s = rbuf_start;
-+ else s = 0;
-+ }
-+
-+ for (i=0; i<count && c<rbuf_len; i++, c++) {
-+ page[i] = rbuf[(c+s) % RBUF_LEN];
-+ }
-+ *start = page;
-+
-+ if (c >= rbuf_len) {
-+ *eof = 1;
-+ done = 1;
-+ }
-+
-+
-+ return i;
-+}
-+
-+static int __init init (void)
-+{
-+
-+ int retval = 0;
-+
-+ pdir = proc_mkdir("isoc_test", NULL);
-+ if(pdir == NULL) {
-+ retval = -ENOMEM;
-+ printk("Error creating dir\n");
-+ goto done;
-+ }
-+ pdir->owner = THIS_MODULE;
-+
-+ pfile = create_proc_read_entry("isoc_data",
-+ 0444, pdir,
-+ isoc_read_data,
-+ NULL);
-+ if (pfile == NULL) {
-+ retval = -ENOMEM;
-+ printk("Error creating file\n");
-+ goto no_file;
-+ }
-+ pfile->owner = THIS_MODULE;
-+
-+ return usb_gadget_register_driver (&zero_driver);
-+
-+ no_file:
-+ remove_proc_entry("isoc_data", NULL);
-+ done:
-+ return retval;
-+}
-+module_init (init);
-+
-+static void __exit cleanup (void)
-+{
-+
-+ usb_gadget_unregister_driver (&zero_driver);
-+
-+ remove_proc_entry("isoc_data", pdir);
-+ remove_proc_entry("isoc_test", NULL);
-+}
-+module_exit (cleanup);
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_cfi_common.h linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_cfi_common.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,142 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CFI_COMMON_H__)
-+#define __DWC_CFI_COMMON_H__
-+
-+//#include <linux/types.h>
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the CFI specific common constants, interfaces
-+ * (functions and macros) and structures for Linux. No PCD specific
-+ * data structure or definition is to be included in this file.
-+ *
-+ */
-+
-+/** This is a request for all Core Features */
-+#define VEN_CORE_GET_FEATURES 0xB1
-+
-+/** This is a request to get the value of a specific Core Feature */
-+#define VEN_CORE_GET_FEATURE 0xB2
-+
-+/** This command allows the host to set the value of a specific Core Feature */
-+#define VEN_CORE_SET_FEATURE 0xB3
-+
-+/** This command allows the host to set the default values of
-+ * either all or any specific Core Feature
-+ */
-+#define VEN_CORE_RESET_FEATURES 0xB4
-+
-+/** This command forces the PCD to write the deferred values of a Core Features */
-+#define VEN_CORE_ACTIVATE_FEATURES 0xB5
-+
-+/** This request reads a DWORD value from a register at the specified offset */
-+#define VEN_CORE_READ_REGISTER 0xB6
-+
-+/** This request writes a DWORD value into a register at the specified offset */
-+#define VEN_CORE_WRITE_REGISTER 0xB7
-+
-+/** This structure is the header of the Core Features dataset returned to
-+ * the Host
-+ */
-+struct cfi_all_features_header {
-+/** The features header structure length is */
-+#define CFI_ALL_FEATURES_HDR_LEN 8
-+ /**
-+ * The total length of the features dataset returned to the Host
-+ */
-+ uint16_t wTotalLen;
-+
-+ /**
-+ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
-+ * This field identifies the version of the CFI Specification with which
-+ * the device is compliant.
-+ */
-+ uint16_t wVersion;
-+
-+ /** The ID of the Core */
-+ uint16_t wCoreID;
-+#define CFI_CORE_ID_UDC 1
-+#define CFI_CORE_ID_OTG 2
-+#define CFI_CORE_ID_WUDEV 3
-+
-+ /** Number of features returned by VEN_CORE_GET_FEATURES request */
-+ uint16_t wNumFeatures;
-+} UPACKED;
-+
-+typedef struct cfi_all_features_header cfi_all_features_header_t;
-+
-+/** This structure is a header of the Core Feature descriptor dataset returned to
-+ * the Host after the VEN_CORE_GET_FEATURES request
-+ */
-+struct cfi_feature_desc_header {
-+#define CFI_FEATURE_DESC_HDR_LEN 8
-+
-+ /** The feature ID */
-+ uint16_t wFeatureID;
-+
-+ /** Length of this feature descriptor in bytes - including the
-+ * length of the feature name string
-+ */
-+ uint16_t wLength;
-+
-+ /** The data length of this feature in bytes */
-+ uint16_t wDataLength;
-+
-+ /**
-+ * Attributes of this features
-+ * D0: Access rights
-+ * 0 - Read/Write
-+ * 1 - Read only
-+ */
-+ uint8_t bmAttributes;
-+#define CFI_FEATURE_ATTR_RO 1
-+#define CFI_FEATURE_ATTR_RW 0
-+
-+ /** Length of the feature name in bytes */
-+ uint8_t bNameLen;
-+
-+ /** The feature name buffer */
-+ //uint8_t *name;
-+} UPACKED;
-+
-+typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
-+
-+/**
-+ * This structure describes a NULL terminated string referenced by its id field.
-+ * It is very similar to usb_string structure but has the id field type set to 16-bit.
-+ */
-+struct cfi_string {
-+ uint16_t id;
-+ const uint8_t *s;
-+};
-+typedef struct cfi_string cfi_string_t;
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_adp.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_adp.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,854 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
-+ * $Revision: #12 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_adp.h"
-+
-+/** @file
-+ *
-+ * This file contains the most of the Attach Detect Protocol implementation for
-+ * the driver to support OTG Rev2.0.
-+ *
-+ */
-+
-+void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
-+{
-+ adpctl_data_t adpctl;
-+
-+ adpctl.d32 = value;
-+ adpctl.b.ar = 0x2;
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
-+
-+ while (adpctl.b.ar) {
-+ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
-+ }
-+
-+}
-+
-+/**
-+ * Function is called to read ADP registers
-+ */
-+uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ adpctl.d32 = 0;
-+ adpctl.b.ar = 0x1;
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
-+
-+ while (adpctl.b.ar) {
-+ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
-+ }
-+
-+ return adpctl.d32;
-+}
-+
-+/**
-+ * Function is called to read ADPCTL register and filter Write-clear bits
-+ */
-+uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_tmout_int = 0;
-+ adpctl.b.adp_prb_int = 0;
-+ adpctl.b.adp_tmout_int = 0;
-+
-+ return adpctl.d32;
-+}
-+
-+/**
-+ * Function is called to write ADP registers
-+ */
-+void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
-+ uint32_t set)
-+{
-+ dwc_otg_adp_write_reg(core_if,
-+ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
-+}
-+
-+static void adp_sense_timeout(void *ptr)
-+{
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+ core_if->adp.sense_timer_started = 0;
-+ DWC_PRINTF("ADP SENSE TIMEOUT\n");
-+ if (core_if->adp_enable) {
-+ dwc_otg_adp_sense_stop(core_if);
-+ dwc_otg_adp_probe_start(core_if);
-+ }
-+}
-+
-+/**
-+ * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
-+ */
-+static void adp_vbuson_timeout(void *ptr)
-+{
-+ gpwrdn_data_t gpwrdn;
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
-+ if (core_if) {
-+ core_if->adp.vbuson_timer_started = 0;
-+ /* Turn off vbus */
-+ hprt0.b.prtpwr = 1;
-+ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
-+ gpwrdn.d32 = 0;
-+
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ /* Enable Wakeup Logic */
-+// gpwrdn.b.wkupactiv = 1;
-+ gpwrdn.b.pmuactv = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+
-+ /* Suspend the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ /* Switch on VDD */
-+// gpwrdn.b.wkupactiv = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+ } else {
-+ /* Enable Power Down Logic */
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+ }
-+
-+ /* Unmask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+
-+ dwc_otg_adp_probe_start(core_if);
-+ dwc_otg_dump_global_registers(core_if);
-+ dwc_otg_dump_host_registers(core_if);
-+ }
-+
-+}
-+
-+/**
-+ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
-+ * not asserted within 1.1 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->adp.vbuson_timer_started = 1;
-+ if (core_if->adp.vbuson_timer)
-+ {
-+ DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
-+ /* 1.1 secs + 60ms necessary for cil_hcd_start*/
-+ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
-+ } else {
-+ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
-+ }
-+}
-+
-+#if 0
-+/**
-+ * Masks all DWC OTG core interrupts
-+ *
-+ */
-+static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+
-+ /* Mask Host Interrupts */
-+
-+ /* Clear and disable HCINTs */
-+ for (i = 0; i < core_if->core_params->host_channels; i++) {
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
-+
-+ }
-+
-+ /* Clear and disable HAINT */
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
-+
-+ /* Mask Device Interrupts */
-+ if (!core_if->multiproc_int_enable) {
-+ /* Clear and disable IN Endpoint interrupts */
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
-+ diepint, 0xFFFFFFFF);
-+ }
-+
-+ /* Clear and disable OUT Endpoint interrupts */
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
-+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
-+ doepint, 0xFFFFFFFF);
-+ }
-+
-+ /* Clear and disable DAINT */
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
-+ 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
-+ } else {
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ diepeachintmsk[i], 0);
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
-+ diepint, 0xFFFFFFFF);
-+ }
-+
-+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[i], 0);
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
-+ doepint, 0xFFFFFFFF);
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+ 0);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
-+ 0xFFFFFFFF);
-+
-+ }
-+
-+ /* Disable interrupts */
-+ ahbcfg.b.glblintrmsk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+
-+ /* Disable all interrupts. */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Clear any pending OTG Interrupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
-+}
-+
-+/**
-+ * Unmask Port Connection Detected interrupt
-+ *
-+ */
-+static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
-+}
-+#endif
-+
-+/**
-+ * Starts the ADP Probing
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ */
-+uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
-+{
-+
-+ adpctl_data_t adpctl = {.d32 = 0};
-+ gpwrdn_data_t gpwrdn;
-+#if 0
-+ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
-+ .b.adp_sns_int = 1, b.adp_tmout_int};
-+#endif
-+ dwc_otg_disable_global_interrupts(core_if);
-+ DWC_PRINTF("ADP Probe Start\n");
-+ core_if->adp.probe_enabled = 1;
-+
-+ adpctl.b.adpres = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ while (adpctl.b.adpres) {
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ }
-+
-+ adpctl.d32 = 0;
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ /* In Host mode unmask SRP detected interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.sts_chngint_msk = 1;
-+ if (!gpwrdn.b.idsts) {
-+ gpwrdn.b.srp_det_msk = 1;
-+ }
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+
-+ adpctl.b.adp_tmout_int_msk = 1;
-+ adpctl.b.adp_prb_int_msk = 1;
-+ adpctl.b.prb_dschg = 1;
-+ adpctl.b.prb_delta = 1;
-+ adpctl.b.prb_per = 1;
-+ adpctl.b.adpen = 1;
-+ adpctl.b.enaprb = 1;
-+
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+ DWC_PRINTF("ADP Probe Finish\n");
-+ return 0;
-+}
-+
-+/**
-+ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
-+ * within 3 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->adp.sense_timer_started = 1;
-+ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
-+}
-+
-+/**
-+ * Starts the ADP Sense
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ DWC_PRINTF("ADP Sense Start\n");
-+
-+ /* Unmask ADP sense interrupt and mask all other from the core */
-+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+ adpctl.b.adp_sns_int_msk = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+ dwc_otg_disable_global_interrupts(core_if); // vahrama
-+
-+ /* Set ADP reset bit*/
-+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+ adpctl.b.adpres = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ while (adpctl.b.adpres) {
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ }
-+
-+ adpctl.b.adpres = 0;
-+ adpctl.b.adpen = 1;
-+ adpctl.b.enasns = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ dwc_otg_adp_sense_timer_start(core_if);
-+
-+ return 0;
-+}
-+
-+/**
-+ * Stops the ADP Probing
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
-+{
-+
-+ adpctl_data_t adpctl;
-+ DWC_PRINTF("Stop ADP probe\n");
-+ core_if->adp.probe_enabled = 0;
-+ core_if->adp.probe_counter = 0;
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+
-+ adpctl.b.adpen = 0;
-+ adpctl.b.adp_prb_int = 1;
-+ adpctl.b.adp_tmout_int = 1;
-+ adpctl.b.adp_sns_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * Stops the ADP Sensing
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+
-+ core_if->adp.sense_enabled = 0;
-+
-+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+ adpctl.b.enasns = 0;
-+ adpctl.b.adp_sns_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * Called to turn on the VBUS after initial ADP probe in host mode.
-+ * If port power was already enabled in cil_hcd_start function then
-+ * only schedule a timer.
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ */
-+void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
-+
-+ if (hprt0.b.prtpwr == 0) {
-+ hprt0.b.prtpwr = 1;
-+ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+
-+ dwc_otg_adp_vbuson_timer_start(core_if);
-+}
-+
-+/**
-+ * Called right after driver is loaded
-+ * to perform initial actions for ADP
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
-+ */
-+void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
-+{
-+ gpwrdn_data_t gpwrdn;
-+
-+ DWC_PRINTF("ADP Initial Start\n");
-+ core_if->adp.adp_started = 1;
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+ dwc_otg_disable_global_interrupts(core_if);
-+ if (is_host) {
-+ DWC_PRINTF("HOST MODE\n");
-+ /* Enable Power Down Logic Interrupt*/
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ /* Initialize first ADP probe to obtain Ramp Time value */
-+ core_if->adp.initial_probe = 1;
-+ dwc_otg_adp_probe_start(core_if);
-+ } else {
-+ gotgctl_data_t gotgctl;
-+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ DWC_PRINTF("DEVICE MODE\n");
-+ if (gotgctl.b.bsesvld == 0) {
-+ /* Enable Power Down Logic Interrupt*/
-+ gpwrdn.d32 = 0;
-+ DWC_PRINTF("VBUS is not valid - start ADP probe\n");
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ core_if->adp.initial_probe = 1;
-+ dwc_otg_adp_probe_start(core_if);
-+ } else {
-+ DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ dwc_otg_dump_global_registers(core_if);
-+ dwc_otg_dump_dev_registers(core_if);
-+ }
-+ }
-+}
-+
-+void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->adp.adp_started = 0;
-+ core_if->adp.initial_probe = 0;
-+ core_if->adp.probe_timer_values[0] = -1;
-+ core_if->adp.probe_timer_values[1] = -1;
-+ core_if->adp.probe_enabled = 0;
-+ core_if->adp.sense_enabled = 0;
-+ core_if->adp.sense_timer_started = 0;
-+ core_if->adp.vbuson_timer_started = 0;
-+ core_if->adp.probe_counter = 0;
-+ core_if->adp.gpwrdn = 0;
-+ core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
-+ /* Initialize timers */
-+ core_if->adp.sense_timer =
-+ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
-+ core_if->adp.vbuson_timer =
-+ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
-+ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
-+ {
-+ DWC_ERROR("Could not allocate memory for ADP timers\n");
-+ }
-+}
-+
-+void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ if (core_if->adp.probe_enabled)
-+ dwc_otg_adp_probe_stop(core_if);
-+ if (core_if->adp.sense_enabled)
-+ dwc_otg_adp_sense_stop(core_if);
-+ if (core_if->adp.sense_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+ if (core_if->adp.vbuson_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
-+ DWC_TIMER_FREE(core_if->adp.sense_timer);
-+ DWC_TIMER_FREE(core_if->adp.vbuson_timer);
-+}
-+
-+/////////////////////////////////////////////////////////////////////
-+////////////// ADP Interrupt Handlers ///////////////////////////////
-+/////////////////////////////////////////////////////////////////////
-+/**
-+ * This function sets Ramp Timer values
-+ */
-+static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ if (core_if->adp.probe_timer_values[0] == -1) {
-+ core_if->adp.probe_timer_values[0] = val;
-+ core_if->adp.probe_timer_values[1] = -1;
-+ return 1;
-+ } else {
-+ core_if->adp.probe_timer_values[1] =
-+ core_if->adp.probe_timer_values[0];
-+ core_if->adp.probe_timer_values[0] = val;
-+ return 0;
-+ }
-+}
-+
-+/**
-+ * This function compares Ramp Timer values
-+ */
-+static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t diff;
-+ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
-+ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
-+ else
-+ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
-+ if(diff < 2) {
-+ return 0;
-+ } else {
-+ return 1;
-+ }
-+}
-+
-+/**
-+ * This function handles ADP Probe Interrupts
-+ */
-+static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
-+ uint32_t val)
-+{
-+ adpctl_data_t adpctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn, temp;
-+ adpctl.d32 = val;
-+
-+ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ core_if->adp.probe_counter++;
-+ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (adpctl.b.rtim == 0 && !temp.b.idsts){
-+ DWC_PRINTF("RTIM value is 0\n");
-+ goto exit;
-+ }
-+ if (set_timer_value(core_if, adpctl.b.rtim) &&
-+ core_if->adp.initial_probe) {
-+ core_if->adp.initial_probe = 0;
-+ dwc_otg_adp_probe_stop(core_if);
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* check which value is for device mode and which for Host mode */
-+ if (!temp.b.idsts) { /* considered host mode value is 0 */
-+ /*
-+ * Turn on VBUS after initial ADP probe.
-+ */
-+ core_if->op_state = A_HOST;
-+ dwc_otg_enable_global_interrupts(core_if);
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_start(core_if);
-+ dwc_otg_adp_turnon_vbus(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ } else {
-+ /*
-+ * Initiate SRP after initial ADP probe.
-+ */
-+ dwc_otg_enable_global_interrupts(core_if);
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+ } else if (core_if->adp.probe_counter > 2){
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (compare_timer_values(core_if)) {
-+ DWC_PRINTF("Difference in timer values !!! \n");
-+// core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Power on the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ /* check which value is for device mode and which for Host mode */
-+ if (!temp.b.idsts) { /* considered host mode value is 0 */
-+ /* Disable Interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ } else {
-+ gotgctl_data_t gotgctl;
-+ /* Mask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Disable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Device mode.
-+ */
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+
-+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ if (!gotgctl.b.bsesvld) {
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+ }
-+ }
-+ if (core_if->power_down == 2) {
-+ if (gpwrdn.b.bsessvld) {
-+ /* Mask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Disable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Device mode.
-+ */
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ }
-+ }
-+ }
-+exit:
-+ /* Clear interrupt */
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_prb_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function hadles ADP Sense Interrupt
-+ */
-+static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
-+{
-+ adpctl_data_t adpctl;
-+ /* Stop ADP Sense timer */
-+ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+
-+ /* Restart ADP Sense timer */
-+ dwc_otg_adp_sense_timer_start(core_if);
-+
-+ /* Clear interrupt */
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_sns_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function handles ADP Probe Interrupts
-+ */
-+static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
-+ uint32_t val)
-+{
-+ adpctl_data_t adpctl = {.d32 = 0 };
-+ adpctl.d32 = val;
-+ set_timer_value(core_if, adpctl.b.rtim);
-+
-+ /* Clear interrupt */
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ adpctl.b.adp_tmout_int = 1;
-+ dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+ return 0;
-+}
-+
-+/**
-+ * ADP Interrupt handler.
-+ *
-+ */
-+int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
-+{
-+ int retval = 0;
-+ adpctl_data_t adpctl = {.d32 = 0};
-+
-+ adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
-+
-+ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
-+ DWC_PRINTF("ADP Sense interrupt\n");
-+ retval |= dwc_otg_adp_handle_sns_intr(core_if);
-+ }
-+ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
-+ DWC_PRINTF("ADP timeout interrupt\n");
-+ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
-+ }
-+ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
-+ DWC_PRINTF("ADP Probe interrupt\n");
-+ adpctl.b.adp_prb_int = 1;
-+ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
-+ }
-+
-+// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
-+ //dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+ DWC_PRINTF("RETURN FROM ADP ISR\n");
-+
-+ return retval;
-+}
-+
-+/**
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
-+{
-+
-+#ifndef DWC_HOST_ONLY
-+ hprt0_data_t hprt0;
-+ gpwrdn_data_t gpwrdn;
-+ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ /* check which value is for device mode and which for Host mode */
-+ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */
-+ DWC_PRINTF("SRP: Host mode\n");
-+
-+ if (core_if->adp_enable) {
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Power on the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+
-+ /* Turn on the port power bit. */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Start the Connection timer. So a message can be displayed
-+ * if connect does not occur within 10 seconds. */
-+ cil_hcd_session_start(core_if);
-+ } else {
-+ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
-+ if (core_if->adp_enable) {
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Power on the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ }
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 0;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ }
-+ }
-+#endif
-+ return 1;
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_adp.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_adp.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,80 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
-+ * $Revision: #7 $
-+ * $Date: 2011/10/24 $
-+ * $Change: 1871159 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_ADP_H__
-+#define __DWC_OTG_ADP_H__
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the Attach Detect Protocol interfaces and defines
-+ * (functions) and structures for Linux.
-+ *
-+ */
-+
-+#define DWC_OTG_ADP_UNATTACHED 0
-+#define DWC_OTG_ADP_ATTACHED 1
-+#define DWC_OTG_ADP_UNKOWN 2
-+
-+typedef struct dwc_otg_adp {
-+ uint32_t adp_started;
-+ uint32_t initial_probe;
-+ int32_t probe_timer_values[2];
-+ uint32_t probe_enabled;
-+ uint32_t sense_enabled;
-+ dwc_timer_t *sense_timer;
-+ uint32_t sense_timer_started;
-+ dwc_timer_t *vbuson_timer;
-+ uint32_t vbuson_timer_started;
-+ uint32_t attached;
-+ uint32_t probe_counter;
-+ uint32_t gpwrdn;
-+} dwc_otg_adp_t;
-+
-+/**
-+ * Attach Detect Protocol functions
-+ */
-+
-+extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
-+extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
-+extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
-+extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
-+extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
-+
-+#endif //__DWC_OTG_ADP_H__
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_attr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_attr.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,1210 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
-+ * $Revision: #44 $
-+ * $Date: 2010/11/29 $
-+ * $Change: 1636033 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing. The Linux driver attributes
-+ * feature will be used to provide the Linux Diagnostic
-+ * Interface. These attributes are accessed through sysfs.
-+ */
-+
-+/** @page "Linux Module Attributes"
-+ *
-+ * The Linux module attributes feature is used to provide the Linux
-+ * Diagnostic Interface. These attributes are accessed through sysfs.
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing.
-+
-+ The following table shows the attributes.
-+ <table>
-+ <tr>
-+ <td><b> Name</b></td>
-+ <td><b> Description</b></td>
-+ <td><b> Access</b></td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode </td>
-+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnpcapable </td>
-+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srpcapable </td>
-+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hsic_connect </td>
-+ <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> inv_sel_hsic </td>
-+ <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnp </td>
-+ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srp </td>
-+ <td> Initiates the Session Request Protocol. Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> buspower </td>
-+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> bussuspend </td>
-+ <td> Suspends the USB bus.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> busconnected </td>
-+ <td> Gets the connection status of the bus</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gotgctl </td>
-+ <td> Gets or sets the Core Control Status Register.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gusbcfg </td>
-+ <td> Gets or sets the Core USB Configuration Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> grxfsiz </td>
-+ <td> Gets or sets the Receive FIFO Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gnptxfsiz </td>
-+ <td> Gets or sets the non-periodic Transmit Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gpvndctl </td>
-+ <td> Gets or sets the PHY Vendor Control Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> ggpio </td>
-+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
-+ or sets the upper 16 bits.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> guid </td>
-+ <td> Gets or sets the value of the User ID Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gsnpsid </td>
-+ <td> Gets the value of the Synopsys ID Regester</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> devspeed </td>
-+ <td> Gets or sets the device speed setting in the DCFG register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> enumspeed </td>
-+ <td> Gets the device enumeration Speed.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hptxfsiz </td>
-+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hprt0 </td>
-+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regoffset </td>
-+ <td> Sets the register offset for the next Register Access</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regvalue </td>
-+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> remote_wakeup </td>
-+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
-+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
-+ Wakeup signalling bit in the Device Control Register is set for 1
-+ milli-second.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rem_wakeup_pwrdn </td>
-+ <td> On read, shows the status core - hibernated or not. On write, initiates
-+ a remote wakeup of the device from Hibernation. </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode_ch_tim_en </td>
-+ <td> This bit is used to enable or disable the host core to wait for 200 PHY
-+ clock cycles at the end of Resume to change the opmode signal to the PHY to 00
-+ after Suspend or LPM. </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> fr_interval </td>
-+ <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
-+ reload HFIR register during runtime. The application can write a value to this
-+ register only after the Port Enable bit of the Host Port Control and Status
-+ register (HPRT.PrtEnaPort) has been set </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> disconnect_us </td>
-+ <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
-+ which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> spramdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcddump </td>
-+ <td> Dumps the current HCD state.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcd_frrem </td>
-+ <td> Shows the average value of the Frame Remaining
-+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
-+ occurs. This can be used to determine the average interrupt latency. Also
-+ shows the average Frame Remaining value for start_transfer and the "a" and
-+ "b" sample points. The "a" and "b" sample points may be used during debugging
-+ bto determine how long it takes to execute a section of the HCD code.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rd_reg_test </td>
-+ <td> Displays the time required to read the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is read).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> wr_reg_test </td>
-+ <td> Displays the time required to write the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is written).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> lpm_response </td>
-+ <td> Gets or sets lpm_response mode. Applicable only in device mode.
-+ <td> Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> sleep_status </td>
-+ <td> Shows sleep status of device.
-+ <td> Read</td>
-+ </tr>
-+
-+ </table>
-+
-+ Example usage:
-+ To get the current mode:
-+ cat /sys/devices/lm0/mode
-+
-+ To power down the USB:
-+ echo 0 > /sys/devices/lm0/buspower
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_os.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_hcd_if.h"
-+
-+/*
-+ * MACROs for defining sysfs attribute
-+ */
-+#ifdef LM_INTERFACE
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+ return count; \
-+}
-+
-+#elif defined(PCI_INTERFACE)
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+ return count; \
-+}
-+
-+#elif defined(PLATFORM_INTERFACE)
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct platform_device *platform_dev = \
-+ container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t val; \
-+ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
-+ __func__, _dev, platform_dev, otg_dev); \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t set = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+ return count; \
-+}
-+#endif
-+
-+/*
-+ * MACROs for defining sysfs attribute for 32-bit registers
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+ return count; \
-+}
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val; \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+ return count; \
-+}
-+
-+#elif defined(PLATFORM_INTERFACE)
-+#include "dwc_otg_dbg.h"
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t val; \
-+ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
-+ __func__, _dev, platform_dev, otg_dev); \
-+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+ const char *buf, size_t count) \
-+{ \
-+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+ uint32_t val = simple_strtoul(buf, NULL, 16); \
-+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+ return count; \
-+}
-+
-+#endif
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+/** @name Functions for Show/Store of Attributes */
-+/**@{*/
-+
-+/**
-+ * Helper function returning the otg_device structure of the given device
-+ */
-+static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
-+{
-+ dwc_otg_device_t *otg_dev;
-+ DWC_OTG_GETDRVDEV(otg_dev, _dev);
-+ return otg_dev;
-+}
-+
-+/**
-+ * Show the register offset of the Register Access.
-+ */
-+static ssize_t regoffset_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
-+ otg_dev->os_dep.reg_offset);
-+}
-+
-+/**
-+ * Set the register offset for the next Register Access Read/Write
-+ */
-+static ssize_t regoffset_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t offset = simple_strtoul(buf, NULL, 16);
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+ if (offset < SZ_256K) {
-+#elif defined(PCI_INTERFACE)
-+ if (offset < 0x00040000) {
-+#endif
-+ otg_dev->os_dep.reg_offset = offset;
-+ } else {
-+ dev_err(_dev, "invalid offset\n");
-+ }
-+
-+ return count;
-+}
-+
-+DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
-+
-+/**
-+ * Show the value of the register at the offset in the reg_offset
-+ * attribute.
-+ */
-+static ssize_t regvalue_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val;
-+ volatile uint32_t *addr;
-+
-+ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
-+ /* Calculate the address */
-+ addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
-+ (uint8_t *) otg_dev->os_dep.base);
-+ val = DWC_READ_REG32(addr);
-+ return snprintf(buf,
-+ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
-+ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
-+ val);
-+ } else {
-+ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
-+ return sprintf(buf, "invalid offset\n");
-+ }
-+}
-+
-+/**
-+ * Store the value in the register at the offset in the reg_offset
-+ * attribute.
-+ *
-+ */
-+static ssize_t regvalue_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ volatile uint32_t *addr;
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
-+ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
-+ /* Calculate the address */
-+ addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
-+ (uint8_t *) otg_dev->os_dep.base);
-+ DWC_WRITE_REG32(addr, val);
-+ } else {
-+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
-+ otg_dev->os_dep.reg_offset);
-+ }
-+ return count;
-+}
-+
-+DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
-+
-+/*
-+ * Attributes
-+ */
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
-+
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
-+ &(otg_dev->core_if->core_global_regs->gusbcfg),
-+ "GUSBCFG");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
-+ &(otg_dev->core_if->core_global_regs->grxfsiz),
-+ "GRXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
-+ &(otg_dev->core_if->core_global_regs->gnptxfsiz),
-+ "GNPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
-+ &(otg_dev->core_if->core_global_regs->gpvndctl),
-+ "GPVNDCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
-+ &(otg_dev->core_if->core_global_regs->ggpio),
-+ "GGPIO");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
-+ "GUID");
-+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
-+ &(otg_dev->core_if->core_global_regs->gsnpsid),
-+ "GSNPSID");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
-+ &(otg_dev->core_if->core_global_regs->hptxfsiz),
-+ "HPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
-+
-+/**
-+ * @todo Add code to initiate the HNP.
-+ */
-+/**
-+ * Show the HNP status bit
-+ */
-+static ssize_t hnp_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "HstNegScs = 0x%x\n",
-+ dwc_otg_get_hnpstatus(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the HNP Request bit
-+ */
-+static ssize_t hnp_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_hnpreq(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
-+
-+/**
-+ * @todo Add code to initiate the SRP.
-+ */
-+/**
-+ * Show the SRP status bit
-+ */
-+static ssize_t srp_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "SesReqScs = 0x%x\n",
-+ dwc_otg_get_srpstatus(otg_dev->core_if));
-+#else
-+ return sprintf(buf, "Host Only Mode!\n");
-+#endif
-+}
-+
-+/**
-+ * Set the SRP Request bit
-+ */
-+static ssize_t srp_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_pcd_initiate_srp(otg_dev->pcd);
-+#endif
-+ return count;
-+}
-+
-+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
-+
-+/**
-+ * @todo Need to do more for power on/off?
-+ */
-+/**
-+ * Show the Bus Power status
-+ */
-+static ssize_t buspower_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Bus Power = 0x%x\n",
-+ dwc_otg_get_prtpower(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Bus Power status
-+ */
-+static ssize_t buspower_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t on = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_prtpower(otg_dev->core_if, on);
-+ return count;
-+}
-+
-+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
-+
-+/**
-+ * @todo Need to do more for suspend?
-+ */
-+/**
-+ * Show the Bus Suspend status
-+ */
-+static ssize_t bussuspend_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Bus Suspend = 0x%x\n",
-+ dwc_otg_get_prtsuspend(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Bus Suspend status
-+ */
-+static ssize_t bussuspend_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_prtsuspend(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
-+
-+/**
-+ * Show the Mode Change Ready Timer status
-+ */
-+static ssize_t mode_ch_tim_en_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
-+ dwc_otg_get_mode_ch_tim(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Mode Change Ready Timer status
-+ */
-+static ssize_t mode_ch_tim_en_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 16);
-+ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
-+
-+/**
-+ * Show the value of HFIR Frame Interval bitfield
-+ */
-+static ssize_t fr_interval_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Frame Interval = 0x%x\n",
-+ dwc_otg_get_fr_interval(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the HFIR Frame Interval value
-+ */
-+static ssize_t fr_interval_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t in = simple_strtoul(buf, NULL, 10);
-+ dwc_otg_set_fr_interval(otg_dev->core_if, in);
-+ return count;
-+}
-+
-+DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
-+
-+/**
-+ * Show the status of Remote Wakeup.
-+ */
-+static ssize_t remote_wakeup_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ return sprintf(buf,
-+ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
-+ dwc_otg_get_remotewakesig(otg_dev->core_if),
-+ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
-+ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
-+#else
-+ return sprintf(buf, "Host Only Mode!\n");
-+#endif /* DWC_HOST_ONLY */
-+}
-+
-+/**
-+ * Initiate a remote wakeup of the host. The Device control register
-+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
-+ * flag is set.
-+ *
-+ */
-+static ssize_t remote_wakeup_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+
-+ if (val & 1) {
-+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
-+ } else {
-+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
-+ }
-+#endif /* DWC_HOST_ONLY */
-+ return count;
-+}
-+
-+DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
-+ remote_wakeup_store);
-+
-+/**
-+ * Show the whether core is hibernated or not.
-+ */
-+static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ if (dwc_otg_get_core_state(otg_dev->core_if)) {
-+ DWC_PRINTF("Core is in hibernation\n");
-+ } else {
-+ DWC_PRINTF("Core is not in hibernation\n");
-+ }
-+#endif /* DWC_HOST_ONLY */
-+ return 0;
-+}
-+
-+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset);
-+
-+/**
-+ * Initiate a remote wakeup of the device to exit from hibernation.
-+ */
-+static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
-+#endif
-+ return count;
-+}
-+
-+DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
-+ rem_wakeup_pwrdn_store);
-+
-+static ssize_t disconnect_us(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+
-+#ifndef DWC_HOST_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+ DWC_PRINTF("The Passed value is %04x\n", val);
-+
-+ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
-+
-+#endif /* DWC_HOST_ONLY */
-+ return count;
-+}
-+
-+DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t regdump_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ dwc_otg_dump_global_registers(otg_dev->core_if);
-+ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
-+ dwc_otg_dump_host_registers(otg_dev->core_if);
-+ } else {
-+ dwc_otg_dump_dev_registers(otg_dev->core_if);
-+
-+ }
-+ return sprintf(buf, "Register Dump\n");
-+}
-+
-+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t spramdump_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ //dwc_otg_dump_spram(otg_dev->core_if);
-+
-+ return sprintf(buf, "SPRAM Dump\n");
-+}
-+
-+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
-+
-+/**
-+ * Dump the current hcd state.
-+ */
-+static ssize_t hcddump_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_hcd_dump_state(otg_dev->hcd);
-+#endif /* DWC_DEVICE_ONLY */
-+ return sprintf(buf, "HCD Dump\n");
-+}
-+
-+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ */
-+static ssize_t hcd_frrem_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ dwc_otg_hcd_dump_frrem(otg_dev->hcd);
-+#endif /* DWC_DEVICE_ONLY */
-+ return sprintf(buf, "HCD Dump Frame Remaining\n");
-+}
-+
-+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
-+
-+/**
-+ * Displays the time required to read the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is read).
-+ */
-+#define RW_REG_COUNT 10000000
-+#define MSEC_PER_JIFFIE 1000/HZ
-+static ssize_t rd_reg_test_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ int i;
-+ int time;
-+ int start_jiffies;
-+
-+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+ start_jiffies = jiffies;
-+ for (i = 0; i < RW_REG_COUNT; i++) {
-+ dwc_otg_get_gnptxfsiz(otg_dev->core_if);
-+ }
-+ time = jiffies - start_jiffies;
-+ return sprintf(buf,
-+ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
-+
-+/**
-+ * Displays the time required to write the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is written).
-+ */
-+static ssize_t wr_reg_test_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t reg_val;
-+ int i;
-+ int time;
-+ int start_jiffies;
-+
-+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
-+ start_jiffies = jiffies;
-+ for (i = 0; i < RW_REG_COUNT; i++) {
-+ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
-+ }
-+ time = jiffies - start_jiffies;
-+ return sprintf(buf,
-+ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+
-+/**
-+* Show the lpm_response attribute.
-+*/
-+static ssize_t lpmresp_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
-+ return sprintf(buf, "** LPM is DISABLED **\n");
-+
-+ if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
-+ return sprintf(buf, "** Current mode is not device mode\n");
-+ }
-+ return sprintf(buf, "lpm_response = %d\n",
-+ dwc_otg_get_lpmresponse(otg_dev->core_if));
-+}
-+
-+/**
-+* Store the lpm_response attribute.
-+*/
-+static ssize_t lpmresp_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ uint32_t val = simple_strtoul(buf, NULL, 16);
-+
-+ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
-+ return 0;
-+ }
-+
-+ if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
-+ return 0;
-+ }
-+
-+ dwc_otg_set_lpmresponse(otg_dev->core_if, val);
-+ return count;
-+}
-+
-+DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
-+
-+/**
-+* Show the sleep_status attribute.
-+*/
-+static ssize_t sleepstatus_show(struct device *_dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ return sprintf(buf, "Sleep Status = %d\n",
-+ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
-+}
-+
-+/**
-+ * Store the sleep_status attribure.
-+ */
-+static ssize_t sleepstatus_store(struct device *_dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
-+ if (dwc_otg_is_host_mode(core_if)) {
-+
-+ DWC_PRINTF("Host initiated resume\n");
-+ dwc_otg_set_prtresume(otg_dev->core_if, 1);
-+ }
-+ }
-+
-+ return count;
-+}
-+
-+DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
-+ sleepstatus_store);
-+
-+#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
-+
-+/**@}*/
-+
-+/**
-+ * Create the device files
-+ */
-+void dwc_otg_attr_create(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ )
-+{
-+ int error;
-+
-+ error = device_create_file(&dev->dev, &dev_attr_regoffset);
-+ error = device_create_file(&dev->dev, &dev_attr_regvalue);
-+ error = device_create_file(&dev->dev, &dev_attr_mode);
-+ error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
-+ error = device_create_file(&dev->dev, &dev_attr_srpcapable);
-+ error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
-+ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
-+ error = device_create_file(&dev->dev, &dev_attr_hnp);
-+ error = device_create_file(&dev->dev, &dev_attr_srp);
-+ error = device_create_file(&dev->dev, &dev_attr_buspower);
-+ error = device_create_file(&dev->dev, &dev_attr_bussuspend);
-+ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
-+ error = device_create_file(&dev->dev, &dev_attr_fr_interval);
-+ error = device_create_file(&dev->dev, &dev_attr_busconnected);
-+ error = device_create_file(&dev->dev, &dev_attr_gotgctl);
-+ error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
-+ error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
-+ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
-+ error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
-+ error = device_create_file(&dev->dev, &dev_attr_ggpio);
-+ error = device_create_file(&dev->dev, &dev_attr_guid);
-+ error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
-+ error = device_create_file(&dev->dev, &dev_attr_devspeed);
-+ error = device_create_file(&dev->dev, &dev_attr_enumspeed);
-+ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
-+ error = device_create_file(&dev->dev, &dev_attr_hprt0);
-+ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
-+ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
-+ error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
-+ error = device_create_file(&dev->dev, &dev_attr_regdump);
-+ error = device_create_file(&dev->dev, &dev_attr_spramdump);
-+ error = device_create_file(&dev->dev, &dev_attr_hcddump);
-+ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
-+ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
-+ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ error = device_create_file(&dev->dev, &dev_attr_lpm_response);
-+ error = device_create_file(&dev->dev, &dev_attr_sleep_status);
-+#endif
-+}
-+
-+/**
-+ * Remove the device files
-+ */
-+void dwc_otg_attr_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ )
-+{
-+ device_remove_file(&dev->dev, &dev_attr_regoffset);
-+ device_remove_file(&dev->dev, &dev_attr_regvalue);
-+ device_remove_file(&dev->dev, &dev_attr_mode);
-+ device_remove_file(&dev->dev, &dev_attr_hnpcapable);
-+ device_remove_file(&dev->dev, &dev_attr_srpcapable);
-+ device_remove_file(&dev->dev, &dev_attr_hsic_connect);
-+ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
-+ device_remove_file(&dev->dev, &dev_attr_hnp);
-+ device_remove_file(&dev->dev, &dev_attr_srp);
-+ device_remove_file(&dev->dev, &dev_attr_buspower);
-+ device_remove_file(&dev->dev, &dev_attr_bussuspend);
-+ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
-+ device_remove_file(&dev->dev, &dev_attr_fr_interval);
-+ device_remove_file(&dev->dev, &dev_attr_busconnected);
-+ device_remove_file(&dev->dev, &dev_attr_gotgctl);
-+ device_remove_file(&dev->dev, &dev_attr_gusbcfg);
-+ device_remove_file(&dev->dev, &dev_attr_grxfsiz);
-+ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
-+ device_remove_file(&dev->dev, &dev_attr_gpvndctl);
-+ device_remove_file(&dev->dev, &dev_attr_ggpio);
-+ device_remove_file(&dev->dev, &dev_attr_guid);
-+ device_remove_file(&dev->dev, &dev_attr_gsnpsid);
-+ device_remove_file(&dev->dev, &dev_attr_devspeed);
-+ device_remove_file(&dev->dev, &dev_attr_enumspeed);
-+ device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
-+ device_remove_file(&dev->dev, &dev_attr_hprt0);
-+ device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
-+ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
-+ device_remove_file(&dev->dev, &dev_attr_disconnect_us);
-+ device_remove_file(&dev->dev, &dev_attr_regdump);
-+ device_remove_file(&dev->dev, &dev_attr_spramdump);
-+ device_remove_file(&dev->dev, &dev_attr_hcddump);
-+ device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
-+ device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
-+ device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ device_remove_file(&dev->dev, &dev_attr_lpm_response);
-+ device_remove_file(&dev->dev, &dev_attr_sleep_status);
-+#endif
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_attr.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_attr.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,89 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
-+ * $Revision: #13 $
-+ * $Date: 2010/06/21 $
-+ * $Change: 1532021 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_ATTR_H__)
-+#define __DWC_OTG_ATTR_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux device attributes.
-+ */
-+extern struct device_attribute dev_attr_regoffset;
-+extern struct device_attribute dev_attr_regvalue;
-+
-+extern struct device_attribute dev_attr_mode;
-+extern struct device_attribute dev_attr_hnpcapable;
-+extern struct device_attribute dev_attr_srpcapable;
-+extern struct device_attribute dev_attr_hnp;
-+extern struct device_attribute dev_attr_srp;
-+extern struct device_attribute dev_attr_buspower;
-+extern struct device_attribute dev_attr_bussuspend;
-+extern struct device_attribute dev_attr_mode_ch_tim_en;
-+extern struct device_attribute dev_attr_fr_interval;
-+extern struct device_attribute dev_attr_busconnected;
-+extern struct device_attribute dev_attr_gotgctl;
-+extern struct device_attribute dev_attr_gusbcfg;
-+extern struct device_attribute dev_attr_grxfsiz;
-+extern struct device_attribute dev_attr_gnptxfsiz;
-+extern struct device_attribute dev_attr_gpvndctl;
-+extern struct device_attribute dev_attr_ggpio;
-+extern struct device_attribute dev_attr_guid;
-+extern struct device_attribute dev_attr_gsnpsid;
-+extern struct device_attribute dev_attr_devspeed;
-+extern struct device_attribute dev_attr_enumspeed;
-+extern struct device_attribute dev_attr_hptxfsiz;
-+extern struct device_attribute dev_attr_hprt0;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+extern struct device_attribute dev_attr_lpm_response;
-+extern struct device_attribute devi_attr_sleep_status;
-+#endif
-+
-+void dwc_otg_attr_create(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+
-+void dwc_otg_attr_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+#endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cfi.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,1876 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * This file contains the most of the CFI(Core Feature Interface)
-+ * implementation for the OTG.
-+ */
-+
-+#ifdef DWC_UTE_CFI
-+
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_cfi.h"
-+
-+/** This definition should actually migrate to the Portability Library */
-+#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
-+
-+extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
-+
-+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
-+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
-+ struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *ctrl_req);
-+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
-+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req);
-+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
-+
-+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
-+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
-+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
-+
-+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
-+
-+/** This is the header of the all features descriptor */
-+static cfi_all_features_header_t all_props_desc_header = {
-+ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
-+ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
-+ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
-+};
-+
-+/** This is an array of statically allocated feature descriptors */
-+static cfi_feature_desc_header_t prop_descs[] = {
-+
-+ /* FT_ID_DMA_MODE */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
-+ },
-+
-+ /* FT_ID_DMA_BUFFER_SETUP */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_DMA_BUFF_ALIGN */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ },
-+
-+ /* FT_ID_DMA_CONCAT_SETUP */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_DMA_CIRCULAR */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_THRESHOLD_SETUP */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+ },
-+
-+ /* FT_ID_DFIFO_DEPTH */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
-+ .bmAttributes = CFI_FEATURE_ATTR_RO,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ },
-+
-+ /* FT_ID_TX_FIFO_DEPTH */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ },
-+
-+ /* FT_ID_RX_FIFO_DEPTH */
-+ {
-+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
-+ .bmAttributes = CFI_FEATURE_ATTR_RW,
-+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+ }
-+};
-+
-+/** The table of feature names */
-+cfi_string_t prop_name_table[] = {
-+ {FT_ID_DMA_MODE, "dma_mode"},
-+ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
-+ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
-+ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
-+ {FT_ID_DMA_CIRCULAR, "buffer_circular"},
-+ {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
-+ {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
-+ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
-+ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
-+ {}
-+};
-+
-+/************************************************************************/
-+
-+/**
-+ * Returns the name of the feature by its ID
-+ * or NULL if no featute ID matches.
-+ *
-+ */
-+const uint8_t *get_prop_name(uint16_t prop_id, int *len)
-+{
-+ cfi_string_t *pstr;
-+ *len = 0;
-+
-+ for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
-+ if (pstr->id == prop_id) {
-+ *len = DWC_STRLEN(pstr->s);
-+ return pstr->s;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+/**
-+ * This function handles all CFI specific control requests.
-+ *
-+ * Return a negative value to stall the DCE.
-+ */
-+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
-+{
-+ int retval = 0;
-+ dwc_otg_pcd_ep_t *ep = NULL;
-+ cfiobject_t *cfi = pcd->cfi;
-+ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
-+ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
-+ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
-+ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
-+ uint32_t regaddr = 0;
-+ uint32_t regval = 0;
-+
-+ /* Save this Control Request in the CFI object.
-+ * The data field will be assigned in the data stage completion CB function.
-+ */
-+ cfi->ctrl_req = *ctrl;
-+ cfi->ctrl_req.data = NULL;
-+
-+ cfi->need_gadget_att = 0;
-+ cfi->need_status_in_complete = 0;
-+
-+ switch (ctrl->bRequest) {
-+ case VEN_CORE_GET_FEATURES:
-+ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
-+ if (retval >= 0) {
-+ //dump_msg(cfi->buf_in.buf, retval);
-+ ep = &pcd->ep0;
-+
-+ retval = min((uint16_t) retval, wLen);
-+ /* Transfer this buffer to the host through the EP0-IN EP */
-+ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_len = retval;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ }
-+ retval = 0;
-+ break;
-+
-+ case VEN_CORE_GET_FEATURE:
-+ CFI_INFO("VEN_CORE_GET_FEATURE\n");
-+ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
-+ pcd, ctrl);
-+ if (retval >= 0) {
-+ ep = &pcd->ep0;
-+
-+ retval = min((uint16_t) retval, wLen);
-+ /* Transfer this buffer to the host through the EP0-IN EP */
-+ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_len = retval;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ }
-+ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
-+ dump_msg(cfi->buf_in.buf, retval);
-+ break;
-+
-+ case VEN_CORE_SET_FEATURE:
-+ CFI_INFO("VEN_CORE_SET_FEATURE\n");
-+ /* Set up an XFER to get the data stage of the control request,
-+ * which is the new value of the feature to be modified.
-+ */
-+ ep = &pcd->ep0;
-+ ep->dwc_ep.is_in = 0;
-+ ep->dwc_ep.dma_addr = cfi->buf_out.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_len = wLen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ /* Read the control write's data stage */
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ retval = 0;
-+ break;
-+
-+ case VEN_CORE_RESET_FEATURES:
-+ CFI_INFO("VEN_CORE_RESET_FEATURES\n");
-+ cfi->need_gadget_att = 1;
-+ cfi->need_status_in_complete = 1;
-+ retval = cfi_preproc_reset(pcd, ctrl);
-+ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
-+ break;
-+
-+ case VEN_CORE_ACTIVATE_FEATURES:
-+ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
-+ break;
-+
-+ case VEN_CORE_READ_REGISTER:
-+ CFI_INFO("VEN_CORE_READ_REGISTER\n");
-+ /* wValue optionally contains the HI WORD of the register offset and
-+ * wIndex contains the LOW WORD of the register offset
-+ */
-+ if (wValue == 0) {
-+ /* @TODO - MAS - fix the access to the base field */
-+ regaddr = 0;
-+ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
-+ //GET_CORE_IF(pcd)->co
-+ regaddr |= wIndex;
-+ } else {
-+ regaddr = (wValue << 16) | wIndex;
-+ }
-+
-+ /* Read a 32-bit value of the memory at the regaddr */
-+ regval = DWC_READ_REG32((uint32_t *) regaddr);
-+
-+ ep = &pcd->ep0;
-+ dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
-+ ep->dwc_ep.is_in = 1;
-+ ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+ ep->dwc_ep.xfer_len = wLen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ cfi->need_gadget_att = 0;
-+ retval = 0;
-+ break;
-+
-+ case VEN_CORE_WRITE_REGISTER:
-+ CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
-+ /* Set up an XFER to get the data stage of the control request,
-+ * which is the new value of the register to be modified.
-+ */
-+ ep = &pcd->ep0;
-+ ep->dwc_ep.is_in = 0;
-+ ep->dwc_ep.dma_addr = cfi->buf_out.addr;
-+ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
-+ ep->dwc_ep.xfer_len = wLen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ pcd->ep0_pending = 1;
-+ /* Read the control write's data stage */
-+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+ retval = 0;
-+ break;
-+
-+ default:
-+ retval = -DWC_E_NOT_SUPPORTED;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function prepares the core features descriptors and copies its
-+ * raw representation into the buffer <buf>.
-+ *
-+ * The buffer structure is as follows:
-+ * all_features_header (8 bytes)
-+ * features_#1 (8 bytes + feature name string length)
-+ * features_#2 (8 bytes + feature name string length)
-+ * .....
-+ * features_#n - where n=the total count of feature descriptors
-+ */
-+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
-+{
-+ cfi_feature_desc_header_t *prop_hdr = prop_descs;
-+ cfi_feature_desc_header_t *prop;
-+ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
-+ cfi_all_features_header_t *tmp;
-+ uint8_t *tmpbuf = buf;
-+ const uint8_t *pname = NULL;
-+ int i, j, namelen = 0, totlen;
-+
-+ /* Prepare and copy the core features into the buffer */
-+ CFI_INFO("%s:\n", __func__);
-+
-+ tmp = (cfi_all_features_header_t *) tmpbuf;
-+ *tmp = *all_props_hdr;
-+ tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
-+
-+ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
-+ for (i = 0; i < j; i++, prop_hdr++) {
-+ pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
-+ prop = (cfi_feature_desc_header_t *) tmpbuf;
-+ *prop = *prop_hdr;
-+
-+ prop->bNameLen = namelen;
-+ prop->wLength =
-+ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
-+ namelen);
-+
-+ tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
-+ dwc_memcpy(tmpbuf, pname, namelen);
-+ tmpbuf += namelen;
-+ }
-+
-+ totlen = tmpbuf - buf;
-+
-+ if (totlen > 0) {
-+ tmp = (cfi_all_features_header_t *) buf;
-+ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
-+ }
-+
-+ return totlen;
-+}
-+
-+/**
-+ * This function releases all the dynamic memory in the CFI object.
-+ */
-+static void cfi_release(cfiobject_t * cfiobj)
-+{
-+ cfi_ep_t *cfiep;
-+ dwc_list_link_t *tmp;
-+
-+ CFI_INFO("%s\n", __func__);
-+
-+ if (cfiobj->buf_in.buf) {
-+ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
-+ cfiobj->buf_in.addr);
-+ cfiobj->buf_in.buf = NULL;
-+ }
-+
-+ if (cfiobj->buf_out.buf) {
-+ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
-+ cfiobj->buf_out.addr);
-+ cfiobj->buf_out.buf = NULL;
-+ }
-+
-+ /* Free the Buffer Setup values for each EP */
-+ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ cfi_free_ep_bs_dyn_data(cfiep);
-+ }
-+}
-+
-+/**
-+ * This function frees the dynamically allocated EP buffer setup data.
-+ */
-+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
-+{
-+ if (cfiep->bm_sg) {
-+ DWC_FREE(cfiep->bm_sg);
-+ cfiep->bm_sg = NULL;
-+ }
-+
-+ if (cfiep->bm_align) {
-+ DWC_FREE(cfiep->bm_align);
-+ cfiep->bm_align = NULL;
-+ }
-+
-+ if (cfiep->bm_concat) {
-+ if (NULL != cfiep->bm_concat->wTxBytes) {
-+ DWC_FREE(cfiep->bm_concat->wTxBytes);
-+ cfiep->bm_concat->wTxBytes = NULL;
-+ }
-+ DWC_FREE(cfiep->bm_concat);
-+ cfiep->bm_concat = NULL;
-+ }
-+}
-+
-+/**
-+ * This function initializes the default values of the features
-+ * for a specific endpoint and should be called only once when
-+ * the EP is enabled first time.
-+ */
-+static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
-+{
-+ int retval = 0;
-+
-+ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
-+ if (NULL == cfiep->bm_sg) {
-+ CFI_INFO("Failed to allocate memory for SG feature value\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+
-+ /* For the Concatenation feature's default value we do not allocate
-+ * memory for the wTxBytes field - it will be done in the set_feature_value
-+ * request handler.
-+ */
-+ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
-+ if (NULL == cfiep->bm_concat) {
-+ CFI_INFO
-+ ("Failed to allocate memory for CONCATENATION feature value\n");
-+ DWC_FREE(cfiep->bm_sg);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
-+
-+ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
-+ if (NULL == cfiep->bm_align) {
-+ CFI_INFO
-+ ("Failed to allocate memory for Alignment feature value\n");
-+ DWC_FREE(cfiep->bm_sg);
-+ DWC_FREE(cfiep->bm_concat);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
-+
-+ return retval;
-+}
-+
-+/**
-+ * The callback function that notifies the CFI on the activation of
-+ * an endpoint in the PCD. The following steps are done in this function:
-+ *
-+ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
-+ * active endpoint)
-+ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
-+ * Set the Buffer Mode to standard
-+ * Initialize the default values for all EP modes (SG, Circular, Concat, Align)
-+ * Add the cfi_ep_t object to the list of active endpoints in the CFI object
-+ */
-+static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
-+ struct dwc_otg_pcd_ep *ep)
-+{
-+ cfi_ep_t *cfiep;
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+
-+ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
-+ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
-+ /* MAS - Check whether this endpoint already is in the list */
-+ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
-+
-+ if (NULL == cfiep) {
-+ /* Allocate a cfi_ep_t object */
-+ cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
-+ if (NULL == cfiep) {
-+ CFI_INFO
-+ ("Unable to allocate memory for <cfiep> in function %s\n",
-+ __func__);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
-+
-+ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
-+ cfiep->ep = ep;
-+
-+ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
-+ ep->dwc_ep.descs =
-+ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
-+ sizeof(dwc_otg_dma_desc_t),
-+ &ep->dwc_ep.descs_dma_addr);
-+
-+ if (NULL == ep->dwc_ep.descs) {
-+ DWC_FREE(cfiep);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ DWC_LIST_INIT(&cfiep->lh);
-+
-+ /* Set the buffer mode to BM_STANDARD. It will be modified
-+ * when building descriptors for a specific buffer mode */
-+ ep->dwc_ep.buff_mode = BM_STANDARD;
-+
-+ /* Create and initialize the default values for this EP's Buffer modes */
-+ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
-+ return retval;
-+
-+ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
-+ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
-+ retval = 0;
-+ } else { /* The sought EP already is in the list */
-+ CFI_INFO("%s: The sought EP already is in the list\n",
-+ __func__);
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function is called when the data stage of a 3-stage Control Write request
-+ * is complete.
-+ *
-+ */
-+static int cfi_ctrl_write_complete(struct cfiobject *cfi,
-+ struct dwc_otg_pcd *pcd)
-+{
-+ uint32_t addr, reg_value;
-+ uint16_t wIndex, wValue;
-+ uint8_t bRequest;
-+ uint8_t *buf = cfi->buf_out.buf;
-+ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
-+ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+
-+ CFI_INFO("%s\n", __func__);
-+
-+ bRequest = ctrl_req->bRequest;
-+ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
-+ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
-+
-+ /*
-+ * Save the pointer to the data stage in the ctrl_req's <data> field.
-+ * The request should be already saved in the command stage by now.
-+ */
-+ ctrl_req->data = cfi->buf_out.buf;
-+ cfi->need_status_in_complete = 0;
-+ cfi->need_gadget_att = 0;
-+
-+ switch (bRequest) {
-+ case VEN_CORE_WRITE_REGISTER:
-+ /* The buffer contains raw data of the new value for the register */
-+ reg_value = *((uint32_t *) buf);
-+ if (wValue == 0) {
-+ addr = 0;
-+ //addr = (uint32_t) pcd->otg_dev->os_dep.base;
-+ addr += wIndex;
-+ } else {
-+ addr = (wValue << 16) | wIndex;
-+ }
-+
-+ //writel(reg_value, addr);
-+
-+ retval = 0;
-+ cfi->need_status_in_complete = 1;
-+ break;
-+
-+ case VEN_CORE_SET_FEATURE:
-+ /* The buffer contains raw data of the new value of the feature */
-+ retval = cfi_set_feature_value(pcd);
-+ if (retval < 0)
-+ return retval;
-+
-+ cfi->need_status_in_complete = 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the SG buffer mode.
-+ */
-+static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
-+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
-+ dma_addr_t buff_addr = req->dma;
-+ int i;
-+ uint32_t txsize, off;
-+
-+ txsize = sgval->wSize;
-+ off = sgval->bOffset;
-+
-+// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
-+// __func__, cfiep->ep->ep.name, txsize, off);
-+
-+ for (i = 0; i < sgval->bCount; i++) {
-+ desc->status.b.bs = BS_HOST_BUSY;
-+ desc->buf = buff_addr;
-+ desc->status.b.l = 0;
-+ desc->status.b.ioc = 0;
-+ desc->status.b.sp = 0;
-+ desc->status.b.bytes = txsize;
-+ desc->status.b.bs = BS_HOST_READY;
-+
-+ /* Set the next address of the buffer */
-+ buff_addr += txsize + off;
-+ desc_last = desc;
-+ desc++;
-+ }
-+
-+ /* Set the last, ioc and sp bits on the Last DMA Descriptor */
-+ desc_last->status.b.l = 1;
-+ desc_last->status.b.ioc = 1;
-+ desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
-+ /* Save the last DMA descriptor pointer */
-+ cfiep->dma_desc_last = desc_last;
-+ cfiep->desc_count = sgval->bCount;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Concatenation buffer mode.
-+ */
-+static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
-+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
-+ dma_addr_t buff_addr = req->dma;
-+ int i;
-+ uint16_t *txsize;
-+
-+ txsize = concatval->wTxBytes;
-+
-+ for (i = 0; i < concatval->hdr.bDescCount; i++) {
-+ desc->buf = buff_addr;
-+ desc->status.b.bs = BS_HOST_BUSY;
-+ desc->status.b.l = 0;
-+ desc->status.b.ioc = 0;
-+ desc->status.b.sp = 0;
-+ desc->status.b.bytes = *txsize;
-+ desc->status.b.bs = BS_HOST_READY;
-+
-+ txsize++;
-+ /* Set the next address of the buffer */
-+ buff_addr += UGETW(ep->desc->wMaxPacketSize);
-+ desc_last = desc;
-+ desc++;
-+ }
-+
-+ /* Set the last, ioc and sp bits on the Last DMA Descriptor */
-+ desc_last->status.b.l = 1;
-+ desc_last->status.b.ioc = 1;
-+ desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
-+ cfiep->dma_desc_last = desc_last;
-+ cfiep->desc_count = concatval->hdr.bDescCount;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Circular buffer mode
-+ */
-+static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ /* @todo: MAS - add implementation when this feature needs to be tested */
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Alignment buffer mode
-+ */
-+static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+ ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
-+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+ dma_addr_t buff_addr = req->dma;
-+
-+ desc->status.b.bs = BS_HOST_BUSY;
-+ desc->status.b.l = 1;
-+ desc->status.b.ioc = 1;
-+ desc->status.b.sp = ep->dwc_ep.sent_zlp;
-+ desc->status.b.bytes = req->length;
-+ /* Adjust the buffer alignment */
-+ desc->buf = (buff_addr + alignval->bAlign);
-+ desc->status.b.bs = BS_HOST_READY;
-+ cfiep->dma_desc_last = desc;
-+ cfiep->desc_count = 1;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors chain for different modes of the
-+ * buffer setup of an endpoint.
-+ */
-+static void cfi_build_descriptors(struct cfiobject *cfi,
-+ struct dwc_otg_pcd *pcd,
-+ struct dwc_otg_pcd_ep *ep,
-+ dwc_otg_pcd_request_t * req)
-+{
-+ cfi_ep_t *cfiep;
-+
-+ /* Get the cfiep by the dwc_otg_pcd_ep */
-+ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Unable to find a matching active endpoint\n",
-+ __func__);
-+ return;
-+ }
-+
-+ cfiep->xfer_len = req->length;
-+
-+ /* Iterate through all the DMA descriptors */
-+ switch (cfiep->ep->dwc_ep.buff_mode) {
-+ case BM_SG:
-+ cfi_build_sg_descs(cfi, cfiep, req);
-+ break;
-+
-+ case BM_CONCAT:
-+ cfi_build_concat_descs(cfi, cfiep, req);
-+ break;
-+
-+ case BM_CIRCULAR:
-+ cfi_build_circ_descs(cfi, cfiep, req);
-+ break;
-+
-+ case BM_ALIGN:
-+ cfi_build_align_descs(cfi, cfiep, req);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+}
-+
-+/**
-+ * Allocate DMA buffer for different Buffer modes.
-+ */
-+static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
-+ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
-+ unsigned size, gfp_t flags)
-+{
-+ return DWC_DMA_ALLOC(size, dma);
-+}
-+
-+/**
-+ * This function initializes the CFI object.
-+ */
-+int init_cfi(cfiobject_t * cfiobj)
-+{
-+ CFI_INFO("%s\n", __func__);
-+
-+ /* Allocate a buffer for IN XFERs */
-+ cfiobj->buf_in.buf =
-+ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
-+ if (NULL == cfiobj->buf_in.buf) {
-+ CFI_INFO("Unable to allocate buffer for INs\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Allocate a buffer for OUT XFERs */
-+ cfiobj->buf_out.buf =
-+ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
-+ if (NULL == cfiobj->buf_out.buf) {
-+ CFI_INFO("Unable to allocate buffer for OUT\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Initialize the callback function pointers */
-+ cfiobj->ops.release = cfi_release;
-+ cfiobj->ops.ep_enable = cfi_ep_enable;
-+ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
-+ cfiobj->ops.build_descriptors = cfi_build_descriptors;
-+ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
-+
-+ /* Initialize the list of active endpoints in the CFI object */
-+ DWC_LIST_INIT(&cfiobj->active_eps);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function reads the required feature's current value into the buffer
-+ *
-+ * @retval: Returns negative as error, or the data length of the feature
-+ */
-+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
-+ struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *ctrl_req)
-+{
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
-+ uint16_t dfifo, rxfifo, txfifo;
-+
-+ switch (ctrl_req->wIndex) {
-+ /* Whether the DDMA is enabled or not */
-+ case FT_ID_DMA_MODE:
-+ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
-+ retval = 1;
-+ break;
-+
-+ case FT_ID_DMA_BUFFER_SETUP:
-+ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
-+ break;
-+
-+ case FT_ID_DMA_BUFF_ALIGN:
-+ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
-+ break;
-+
-+ case FT_ID_DMA_CONCAT_SETUP:
-+ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
-+ break;
-+
-+ case FT_ID_DMA_CIRCULAR:
-+ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
-+ break;
-+
-+ case FT_ID_THRESHOLD_SETUP:
-+ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
-+ break;
-+
-+ case FT_ID_DFIFO_DEPTH:
-+ dfifo = get_dfifo_size(coreif);
-+ *((uint16_t *) buf) = dfifo;
-+ retval = sizeof(uint16_t);
-+ break;
-+
-+ case FT_ID_TX_FIFO_DEPTH:
-+ retval = get_txfifo_size(pcd, ctrl_req->wValue);
-+ if (retval >= 0) {
-+ txfifo = retval;
-+ *((uint16_t *) buf) = txfifo;
-+ retval = sizeof(uint16_t);
-+ }
-+ break;
-+
-+ case FT_ID_RX_FIFO_DEPTH:
-+ retval = get_rxfifo_size(coreif, ctrl_req->wValue);
-+ if (retval >= 0) {
-+ rxfifo = retval;
-+ *((uint16_t *) buf) = rxfifo;
-+ retval = sizeof(uint16_t);
-+ }
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function resets the SG for the specified EP to its default value
-+ */
-+static int cfi_reset_sg_val(cfi_ep_t * cfiep)
-+{
-+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+ return 0;
-+}
-+
-+/**
-+ * This function resets the Alignment for the specified EP to its default value
-+ */
-+static int cfi_reset_align_val(cfi_ep_t * cfiep)
-+{
-+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+ return 0;
-+}
-+
-+/**
-+ * This function resets the Concatenation for the specified EP to its default value
-+ * This function will also set the value of the wTxBytes field to NULL after
-+ * freeing the memory previously allocated for this field.
-+ */
-+static int cfi_reset_concat_val(cfi_ep_t * cfiep)
-+{
-+ /* First we need to free the wTxBytes field */
-+ if (cfiep->bm_concat->wTxBytes) {
-+ DWC_FREE(cfiep->bm_concat->wTxBytes);
-+ cfiep->bm_concat->wTxBytes = NULL;
-+ }
-+
-+ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
-+ return 0;
-+}
-+
-+/**
-+ * This function resets all the buffer setups of the specified endpoint
-+ */
-+static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
-+{
-+ cfi_reset_sg_val(cfiep);
-+ cfi_reset_align_val(cfiep);
-+ cfi_reset_concat_val(cfiep);
-+ return 0;
-+}
-+
-+static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
-+ uint8_t rx_rst, uint8_t tx_rst)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint16_t tx_siz[15];
-+ uint16_t rx_siz = 0;
-+ dwc_otg_pcd_ep_t *ep = NULL;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+
-+ if (rx_rst) {
-+ rx_siz = params->dev_rx_fifo_size;
-+ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
-+ }
-+
-+ if (tx_rst) {
-+ if (ep_addr == 0) {
-+ int i;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ tx_siz[i] =
-+ core_if->core_params->dev_tx_fifo_size[i];
-+ core_if->core_params->dev_tx_fifo_size[i] =
-+ core_if->init_txfsiz[i];
-+ }
-+ } else {
-+
-+ ep = get_ep_by_addr(pcd, ep_addr);
-+
-+ if (NULL == ep) {
-+ CFI_INFO
-+ ("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, ep_addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ tx_siz[0] =
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
-+ 1];
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
-+ GET_CORE_IF(pcd)->init_txfsiz[ep->
-+ dwc_ep.tx_fifo_num -
-+ 1];
-+ }
-+ }
-+
-+ if (resize_fifos(GET_CORE_IF(pcd))) {
-+ retval = 0;
-+ } else {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Reset All(FIFO size)\n",
-+ __func__);
-+ if (rx_rst) {
-+ params->dev_rx_fifo_size = rx_siz;
-+ }
-+
-+ if (tx_rst) {
-+ if (ep_addr == 0) {
-+ int i;
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
-+ i++) {
-+ core_if->
-+ core_params->dev_tx_fifo_size[i] =
-+ tx_siz[i];
-+ }
-+ } else {
-+ params->dev_tx_fifo_size[ep->
-+ dwc_ep.tx_fifo_num -
-+ 1] = tx_siz[0];
-+ }
-+ }
-+ retval = -DWC_E_INVALID;
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
-+ if (retval < 0) {
-+ return retval;
-+ }
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_ep_reset_all_setup_vals(cfiep);
-+ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_ep_reset_all_setup_vals(cfiep);
-+ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Reset All\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
-+ uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_reset_sg_val(cfiep);
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_reset_sg_val(cfiep);
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Buffer Setup\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_reset_concat_val(cfiep);
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_reset_concat_val(cfiep);
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Concatenation Value\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+}
-+
-+static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+ int retval = 0;
-+ cfi_ep_t *cfiep;
-+ cfiobject_t *cfi = pcd->cfi;
-+ dwc_list_link_t *tmp;
-+
-+ /* If the EP address is known then reset the features for only that EP */
-+ if (addr) {
-+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == cfiep) {
-+ CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+ retval = cfi_reset_align_val(cfiep);
-+ }
-+ /* Otherwise (wValue == 0), reset all features of all EP's */
-+ else {
-+ /* Traverse all the active EP's and reset the feature(s) value(s) */
-+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ retval = cfi_reset_align_val(cfiep);
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("%s: Error resetting the feature Aliignment Value\n",
-+ __func__);
-+ return retval;
-+ }
-+ }
-+ }
-+ return retval;
-+
-+}
-+
-+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = 0;
-+
-+ switch (req->wIndex) {
-+ case 0:
-+ /* Reset all features */
-+ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_DMA_BUFFER_SETUP:
-+ /* Reset the SG buffer setup */
-+ retval =
-+ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_DMA_CONCAT_SETUP:
-+ /* Reset the Concatenation buffer setup */
-+ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_DMA_BUFF_ALIGN:
-+ /* Reset the Alignment buffer setup */
-+ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
-+ break;
-+
-+ case FT_ID_TX_FIFO_DEPTH:
-+ retval =
-+ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
-+ pcd->cfi->need_gadget_att = 0;
-+ break;
-+
-+ case FT_ID_RX_FIFO_DEPTH:
-+ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
-+ pcd->cfi->need_gadget_att = 0;
-+ break;
-+ default:
-+ break;
-+ }
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the SG buffer setup.
-+ */
-+static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+ uint8_t inaddr, outaddr;
-+ cfi_ep_t *epin, *epout;
-+ ddma_sg_buffer_setup_t *psgval;
-+ uint32_t desccount, size;
-+
-+ CFI_INFO("%s\n", __func__);
-+
-+ psgval = (ddma_sg_buffer_setup_t *) buf;
-+ desccount = (uint32_t) psgval->bCount;
-+ size = (uint32_t) psgval->wSize;
-+
-+ /* Check the DMA descriptor count */
-+ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
-+ CFI_INFO
-+ ("%s: The count of DMA Descriptors should be between 1 and %d\n",
-+ __func__, MAX_DMA_DESCS_PER_EP);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ /* Check the DMA descriptor count */
-+
-+ if (size == 0) {
-+
-+ CFI_INFO("%s: The transfer size should be at least 1 byte\n",
-+ __func__);
-+
-+ return -DWC_E_INVALID;
-+
-+ }
-+
-+ inaddr = psgval->bInEndpointAddress;
-+ outaddr = psgval->bOutEndpointAddress;
-+
-+ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
-+ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
-+
-+ if (NULL == epin || NULL == epout) {
-+ CFI_INFO
-+ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
-+ __func__, inaddr, outaddr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ epin->ep->dwc_ep.buff_mode = BM_SG;
-+ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
-+
-+ epout->ep->dwc_ep.buff_mode = BM_SG;
-+ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+ cfi_ep_t *ep;
-+ uint8_t addr;
-+ ddma_align_buffer_setup_t *palignval;
-+
-+ palignval = (ddma_align_buffer_setup_t *) buf;
-+ addr = palignval->bEndpointAddress;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ ep->ep->dwc_ep.buff_mode = BM_ALIGN;
-+ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function sets a new value for the Concatenation buffer setup.
-+ */
-+static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
-+ uint16_t *pVals;
-+ uint32_t desccount;
-+ int i;
-+ uint16_t mps;
-+
-+ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
-+ desccount = (uint32_t) pConcatValHdr->bDescCount;
-+ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
-+
-+ /* Check the DMA descriptor count */
-+ if (desccount > MAX_DMA_DESCS_PER_EP) {
-+ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
-+ __func__, MAX_DMA_DESCS_PER_EP);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ addr = pConcatValHdr->bEndpointAddress;
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ mps = UGETW(ep->ep->desc->wMaxPacketSize);
-+
-+#if 0
-+ for (i = 0; i < desccount; i++) {
-+ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
-+ }
-+ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
-+#endif
-+
-+ /* Check the wTxSizes to be less than or equal to the mps */
-+ for (i = 0; i < desccount; i++) {
-+ if (pVals[i] > mps) {
-+ CFI_INFO
-+ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
-+ __func__, i, pVals[i]);
-+ return -DWC_E_INVALID;
-+ }
-+ }
-+
-+ ep->ep->dwc_ep.buff_mode = BM_CONCAT;
-+ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
-+
-+ /* Free the previously allocated storage for the wTxBytes */
-+ if (ep->bm_concat->wTxBytes) {
-+ DWC_FREE(ep->bm_concat->wTxBytes);
-+ }
-+
-+ /* Allocate a new storage for the wTxBytes field */
-+ ep->bm_concat->wTxBytes =
-+ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
-+ if (NULL == ep->bm_concat->wTxBytes) {
-+ CFI_INFO("%s: Unable to allocate memory\n", __func__);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Copy the new values into the wTxBytes filed */
-+ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
-+ sizeof(uint16_t) * pConcatValHdr->bDescCount);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function calculates the total of all FIFO sizes
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ uint16_t dfifo_total = 0;
-+ int i;
-+
-+ /* The shared RxFIFO size */
-+ dfifo_total =
-+ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
-+
-+ /* Add up each TxFIFO size to the total */
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ dfifo_total += params->dev_tx_fifo_size[i];
-+ }
-+
-+ return dfifo_total;
-+}
-+
-+/**
-+ * This function returns Rx FIFO size
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
-+{
-+ switch (wValue >> 8) {
-+ case 0:
-+ return (core_if->pwron_rxfsiz <
-+ 32768) ? core_if->pwron_rxfsiz : 32768;
-+ break;
-+ case 1:
-+ return core_if->core_params->dev_rx_fifo_size;
-+ break;
-+ default:
-+ return -DWC_E_INVALID;
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function returns Tx FIFO size for IN EP
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ ep = get_ep_by_addr(pcd, wValue & 0xff);
-+
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, wValue & 0xff);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (!ep->dwc_ep.is_in) {
-+ CFI_INFO
-+ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
-+ __func__, wValue & 0xff);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ switch (wValue >> 8) {
-+ case 0:
-+ return (GET_CORE_IF(pcd)->pwron_txfsiz
-+ [ep->dwc_ep.tx_fifo_num - 1] <
-+ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
-+ dwc_ep.tx_fifo_num
-+ - 1] : 32768;
-+ break;
-+ case 1:
-+ return GET_CORE_IF(pcd)->core_params->
-+ dev_tx_fifo_size[ep->dwc_ep.num - 1];
-+ break;
-+ default:
-+ return -DWC_E_INVALID;
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function checks if the submitted combination of
-+ * device mode FIFO sizes is possible or not.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return 1 if possible, 0 otherwise.
-+ *
-+ */
-+static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
-+{
-+ uint16_t dfifo_actual = 0;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ uint16_t start_addr = 0;
-+ int i;
-+
-+ dfifo_actual =
-+ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ dfifo_actual += params->dev_tx_fifo_size[i];
-+ }
-+
-+ if (dfifo_actual > core_if->total_fifo_size) {
-+ return 0;
-+ }
-+
-+ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
-+ return 0;
-+
-+ if (params->dev_nperio_tx_fifo_size > 32768
-+ || params->dev_nperio_tx_fifo_size < 16)
-+ return 0;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+ if (params->dev_tx_fifo_size[i] > 768
-+ || params->dev_tx_fifo_size[i] < 4)
-+ return 0;
-+ }
-+
-+ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
-+ return 0;
-+ start_addr = params->dev_rx_fifo_size;
-+
-+ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
-+ return 0;
-+ start_addr += params->dev_nperio_tx_fifo_size;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
-+ return 0;
-+ start_addr += params->dev_tx_fifo_size[i];
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function resizes Device mode FIFOs
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return 1 if successful, 0 otherwise
-+ *
-+ */
-+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
-+{
-+ int i = 0;
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ uint32_t rx_fifo_size;
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t txfifosize[15];
-+
-+ uint32_t rx_fsz_bak;
-+ uint32_t nptxfsz_bak;
-+ uint32_t txfsz_bak[15];
-+
-+ uint16_t start_address;
-+ uint8_t retval = 1;
-+
-+ if (!check_fifo_sizes(core_if)) {
-+ return 0;
-+ }
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
-+ rx_fifo_size = params->dev_rx_fifo_size;
-+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+ /*
-+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_tx_fifo_size array and the FIFO size registers in
-+ * the dtxfsiz array run from 0 to 14.
-+ */
-+
-+ /* Non-periodic Tx FIFO */
-+ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ start_address = params->dev_rx_fifo_size;
-+ nptxfifosize.b.startaddr = start_address;
-+
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+
-+ start_address += nptxfifosize.b.depth;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
-+
-+ txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
-+ txfifosize[i].b.startaddr = start_address;
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ txfifosize[i].d32);
-+
-+ start_address += txfifosize[i].b.depth;
-+ }
-+
-+ /** Check if register values are set correctly */
-+ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
-+ retval = 0;
-+ }
-+
-+ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
-+ retval = 0;
-+ }
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ if (txfifosize[i].d32 !=
-+ DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
-+ retval = 0;
-+ }
-+ }
-+
-+ /** If register values are not set correctly, reset old values */
-+ if (retval == 0) {
-+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ txfsz_bak[i]);
-+ }
-+ }
-+ } else {
-+ return 0;
-+ }
-+
-+ /* Flush the FIFOs */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
-+{
-+ int retval;
-+ uint32_t fsiz;
-+ uint16_t size;
-+ uint16_t ep_addr;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+ tx_fifo_size_setup_t *ptxfifoval;
-+
-+ ptxfifoval = (tx_fifo_size_setup_t *) buf;
-+ ep_addr = ptxfifoval->bEndpointAddress;
-+ size = ptxfifoval->wDepth;
-+
-+ ep = get_ep_by_addr(pcd, ep_addr);
-+
-+ CFI_INFO
-+ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
-+ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
-+
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+ __func__, ep_addr);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
-+
-+ if (resize_fifos(GET_CORE_IF(pcd))) {
-+ retval = 0;
-+ } else {
-+ CFI_INFO
-+ ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
-+ __func__, ep_addr);
-+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
-+{
-+ int retval;
-+ uint32_t fsiz;
-+ uint16_t size;
-+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+ rx_fifo_size_setup_t *prxfifoval;
-+
-+ prxfifoval = (rx_fifo_size_setup_t *) buf;
-+ size = prxfifoval->wDepth;
-+
-+ fsiz = params->dev_rx_fifo_size;
-+ params->dev_rx_fifo_size = size;
-+
-+ if (resize_fifos(GET_CORE_IF(pcd))) {
-+ retval = 0;
-+ } else {
-+ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
-+ __func__);
-+ params->dev_rx_fifo_size = fsiz;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function reads the SG of an EP's buffer setup into the buffer buf
-+ */
-+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+
-+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+ addr = req->wValue & 0xFF;
-+ if (addr == 0) /* The address should be non-zero */
-+ return retval;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+ __func__, addr);
-+ return retval;
-+ }
-+
-+ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
-+ retval = BS_SG_VAL_DESC_LEN;
-+ return retval;
-+}
-+
-+/**
-+ * This function reads the Concatenation value of an EP's buffer mode into
-+ * the buffer buf
-+ */
-+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+ uint8_t desc_count;
-+
-+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+ addr = req->wValue & 0xFF;
-+ if (addr == 0) /* The address should be non-zero */
-+ return retval;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+ __func__, addr);
-+ return retval;
-+ }
-+
-+ /* Copy the header to the buffer */
-+ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
-+ /* Advance the buffer pointer by the header size */
-+ buf += BS_CONCAT_VAL_HDR_LEN;
-+
-+ desc_count = ep->bm_concat->hdr.bDescCount;
-+ /* Copy alll the wTxBytes to the buffer */
-+ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
-+
-+ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
-+ return retval;
-+}
-+
-+/**
-+ * This function reads the buffer Alignment value of an EP's buffer mode into
-+ * the buffer buf
-+ *
-+ * @return The total number of bytes copied to the buffer or negative error code.
-+ */
-+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+ struct cfi_usb_ctrlrequest *req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ uint8_t addr;
-+ cfi_ep_t *ep;
-+
-+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+ addr = req->wValue & 0xFF;
-+ if (addr == 0) /* The address should be non-zero */
-+ return retval;
-+
-+ ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+ if (NULL == ep) {
-+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+ __func__, addr);
-+ return retval;
-+ }
-+
-+ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
-+ retval = BS_ALIGN_VAL_HDR_LEN;
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the specified feature
-+ *
-+ * @param pcd A pointer to the PCD object
-+ *
-+ * @return 0 if successful, negative error code otherwise to stall the DCE.
-+ */
-+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
-+{
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+ uint16_t wIndex, wValue;
-+ uint8_t bRequest;
-+ struct dwc_otg_core_if *coreif;
-+ cfiobject_t *cfi = pcd->cfi;
-+ struct cfi_usb_ctrlrequest *ctrl_req;
-+ uint8_t *buf;
-+ ctrl_req = &cfi->ctrl_req;
-+
-+ buf = pcd->cfi->ctrl_req.data;
-+
-+ coreif = GET_CORE_IF(pcd);
-+ bRequest = ctrl_req->bRequest;
-+ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
-+ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
-+
-+ /* See which feature is to be modified */
-+ switch (wIndex) {
-+ case FT_ID_DMA_BUFFER_SETUP:
-+ /* Modify the feature */
-+ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
-+ return retval;
-+
-+ /* And send this request to the gadget */
-+ cfi->need_gadget_att = 1;
-+ break;
-+
-+ case FT_ID_DMA_BUFF_ALIGN:
-+ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 1;
-+ break;
-+
-+ case FT_ID_DMA_CONCAT_SETUP:
-+ /* Modify the feature */
-+ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 1;
-+ break;
-+
-+ case FT_ID_DMA_CIRCULAR:
-+ CFI_INFO("FT_ID_DMA_CIRCULAR\n");
-+ break;
-+
-+ case FT_ID_THRESHOLD_SETUP:
-+ CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
-+ break;
-+
-+ case FT_ID_DFIFO_DEPTH:
-+ CFI_INFO("FT_ID_DFIFO_DEPTH\n");
-+ break;
-+
-+ case FT_ID_TX_FIFO_DEPTH:
-+ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
-+ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 0;
-+ break;
-+
-+ case FT_ID_RX_FIFO_DEPTH:
-+ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
-+ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
-+ return retval;
-+ cfi->need_gadget_att = 0;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+#endif //DWC_UTE_CFI
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cfi.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,320 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_CFI_H__)
-+#define __DWC_OTG_CFI_H__
-+
-+#include "dwc_otg_pcd.h"
-+#include "dwc_cfi_common.h"
-+
-+/**
-+ * @file
-+ * This file contains the CFI related OTG PCD specific common constants,
-+ * interfaces(functions and macros) and data structures.The CFI Protocol is an
-+ * optional interface for internal testing purposes that a DUT may implement to
-+ * support testing of configurable features.
-+ *
-+ */
-+
-+struct dwc_otg_pcd;
-+struct dwc_otg_pcd_ep;
-+
-+/** OTG CFI Features (properties) ID constants */
-+/** This is a request for all Core Features */
-+#define FT_ID_DMA_MODE 0x0001
-+#define FT_ID_DMA_BUFFER_SETUP 0x0002
-+#define FT_ID_DMA_BUFF_ALIGN 0x0003
-+#define FT_ID_DMA_CONCAT_SETUP 0x0004
-+#define FT_ID_DMA_CIRCULAR 0x0005
-+#define FT_ID_THRESHOLD_SETUP 0x0006
-+#define FT_ID_DFIFO_DEPTH 0x0007
-+#define FT_ID_TX_FIFO_DEPTH 0x0008
-+#define FT_ID_RX_FIFO_DEPTH 0x0009
-+
-+/**********************************************************/
-+#define CFI_INFO_DEF
-+
-+#ifdef CFI_INFO_DEF
-+#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt);
-+#else
-+#define CFI_INFO(fmt...)
-+#endif
-+
-+#define min(x,y) ({ \
-+ x < y ? x : y; })
-+
-+#define max(x,y) ({ \
-+ x > y ? x : y; })
-+
-+/**
-+ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
-+ * also used for setting up a buffer for Circular DDMA.
-+ */
-+struct _ddma_sg_buffer_setup {
-+#define BS_SG_VAL_DESC_LEN 6
-+ /* The OUT EP address */
-+ uint8_t bOutEndpointAddress;
-+ /* The IN EP address */
-+ uint8_t bInEndpointAddress;
-+ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
-+ uint8_t bOffset;
-+ /* The number of transfer segments (a DMA descriptors per each segment) */
-+ uint8_t bCount;
-+ /* Size (in byte) of each transfer segment */
-+ uint16_t wSize;
-+} __attribute__ ((packed));
-+typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
-+
-+/** Descriptor DMA Concatenation Buffer setup structure */
-+struct _ddma_concat_buffer_setup_hdr {
-+#define BS_CONCAT_VAL_HDR_LEN 4
-+ /* The endpoint for which the buffer is to be set up */
-+ uint8_t bEndpointAddress;
-+ /* The count of descriptors to be used */
-+ uint8_t bDescCount;
-+ /* The total size of the transfer */
-+ uint16_t wSize;
-+} __attribute__ ((packed));
-+typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
-+
-+/** Descriptor DMA Concatenation Buffer setup structure */
-+struct _ddma_concat_buffer_setup {
-+ /* The SG header */
-+ ddma_concat_buffer_setup_hdr_t hdr;
-+
-+ /* The XFER sizes pointer (allocated dynamically) */
-+ uint16_t *wTxBytes;
-+} __attribute__ ((packed));
-+typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
-+
-+/** Descriptor DMA Alignment Buffer setup structure */
-+struct _ddma_align_buffer_setup {
-+#define BS_ALIGN_VAL_HDR_LEN 2
-+ uint8_t bEndpointAddress;
-+ uint8_t bAlign;
-+} __attribute__ ((packed));
-+typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
-+
-+/** Transmit FIFO Size setup structure */
-+struct _tx_fifo_size_setup {
-+ uint8_t bEndpointAddress;
-+ uint16_t wDepth;
-+} __attribute__ ((packed));
-+typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
-+
-+/** Transmit FIFO Size setup structure */
-+struct _rx_fifo_size_setup {
-+ uint16_t wDepth;
-+} __attribute__ ((packed));
-+typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
-+
-+/**
-+ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
-+ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
-+ * to the data returned in the data stage of a 3-stage Control Write requests.
-+ */
-+struct cfi_usb_ctrlrequest {
-+ uint8_t bRequestType;
-+ uint8_t bRequest;
-+ uint16_t wValue;
-+ uint16_t wIndex;
-+ uint16_t wLength;
-+ uint8_t *data;
-+} UPACKED;
-+
-+/*---------------------------------------------------------------------------*/
-+
-+/**
-+ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
-+ * This structure is used to store the buffer setup data for any
-+ * enabled endpoint in the PCD.
-+ */
-+struct cfi_ep {
-+ /* Entry for the list container */
-+ dwc_list_link_t lh;
-+ /* Pointer to the active PCD endpoint structure */
-+ struct dwc_otg_pcd_ep *ep;
-+ /* The last descriptor in the chain of DMA descriptors of the endpoint */
-+ struct dwc_otg_dma_desc *dma_desc_last;
-+ /* The SG feature value */
-+ ddma_sg_buffer_setup_t *bm_sg;
-+ /* The Circular feature value */
-+ ddma_sg_buffer_setup_t *bm_circ;
-+ /* The Concatenation feature value */
-+ ddma_concat_buffer_setup_t *bm_concat;
-+ /* The Alignment feature value */
-+ ddma_align_buffer_setup_t *bm_align;
-+ /* XFER length */
-+ uint32_t xfer_len;
-+ /*
-+ * Count of DMA descriptors currently used.
-+ * The total should not exceed the MAX_DMA_DESCS_PER_EP value
-+ * defined in the dwc_otg_cil.h
-+ */
-+ uint32_t desc_count;
-+};
-+typedef struct cfi_ep cfi_ep_t;
-+
-+typedef struct cfi_dma_buff {
-+#define CFI_IN_BUF_LEN 1024
-+#define CFI_OUT_BUF_LEN 1024
-+ dma_addr_t addr;
-+ uint8_t *buf;
-+} cfi_dma_buff_t;
-+
-+struct cfiobject;
-+
-+/**
-+ * This is the interface for the CFI operations.
-+ *
-+ * @param ep_enable Called when any endpoint is enabled and activated.
-+ * @param release Called when the CFI object is released and it needs to correctly
-+ * deallocate the dynamic memory
-+ * @param ctrl_write_complete Called when the data stage of the request is complete
-+ */
-+typedef struct cfi_ops {
-+ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
-+ struct dwc_otg_pcd_ep * ep);
-+ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
-+ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
-+ unsigned size, gfp_t flags);
-+ void (*release) (struct cfiobject * cfi);
-+ int (*ctrl_write_complete) (struct cfiobject * cfi,
-+ struct dwc_otg_pcd * pcd);
-+ void (*build_descriptors) (struct cfiobject * cfi,
-+ struct dwc_otg_pcd * pcd,
-+ struct dwc_otg_pcd_ep * ep,
-+ dwc_otg_pcd_request_t * req);
-+} cfi_ops_t;
-+
-+struct cfiobject {
-+ cfi_ops_t ops;
-+ struct dwc_otg_pcd *pcd;
-+ struct usb_gadget *gadget;
-+
-+ /* Buffers used to send/receive CFI-related request data */
-+ cfi_dma_buff_t buf_in;
-+ cfi_dma_buff_t buf_out;
-+
-+ /* CFI specific Control request wrapper */
-+ struct cfi_usb_ctrlrequest ctrl_req;
-+
-+ /* The list of active EP's in the PCD of type cfi_ep_t */
-+ dwc_list_link_t active_eps;
-+
-+ /* This flag shall control the propagation of a specific request
-+ * to the gadget's processing routines.
-+ * 0 - no gadget handling
-+ * 1 - the gadget needs to know about this request (w/o completing a status
-+ * phase - just return a 0 to the _setup callback)
-+ */
-+ uint8_t need_gadget_att;
-+
-+ /* Flag indicating whether the status IN phase needs to be
-+ * completed by the PCD
-+ */
-+ uint8_t need_status_in_complete;
-+};
-+typedef struct cfiobject cfiobject_t;
-+
-+#define DUMP_MSG
-+
-+#if defined(DUMP_MSG)
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+ unsigned int start, num, i;
-+ char line[52], *p;
-+
-+ if (length >= 512)
-+ return;
-+
-+ start = 0;
-+ while (length > 0) {
-+ num = min(length, 16u);
-+ p = line;
-+ for (i = 0; i < num; ++i) {
-+ if (i == 8)
-+ *p++ = ' ';
-+ DWC_SPRINTF(p, " %02x", buf[i]);
-+ p += 3;
-+ }
-+ *p = 0;
-+ DWC_DEBUG("%6x: %s\n", start, line);
-+ buf += num;
-+ start += num;
-+ length -= num;
-+ }
-+}
-+#else
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function returns a pointer to cfi_ep_t object with the addr address.
-+ */
-+static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
-+ uint8_t addr)
-+{
-+ struct cfi_ep *pcfiep;
-+ dwc_list_link_t *tmp;
-+
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+
-+ if (pcfiep->ep->desc->bEndpointAddress == addr) {
-+ return pcfiep;
-+ }
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * This function returns a pointer to cfi_ep_t object that matches
-+ * the dwc_otg_pcd_ep object.
-+ */
-+static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
-+ struct dwc_otg_pcd_ep *ep)
-+{
-+ struct cfi_ep *pcfiep = NULL;
-+ dwc_list_link_t *tmp;
-+
-+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+ if (pcfiep->ep == ep) {
-+ return pcfiep;
-+ }
-+ }
-+ return NULL;
-+}
-+
-+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
-+
-+#endif /* (__DWC_OTG_CFI_H__) */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cil.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cil.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,7141 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
-+ * $Revision: #191 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * The CIL manages the memory map for the core so that the HCD and PCD
-+ * don't have to do this separately. It also handles basic tasks like
-+ * reading/writing the registers and data FIFOs in the controller.
-+ * Some of the data access functions provide encapsulation of several
-+ * operations required to perform a task, such as writing multiple
-+ * registers to start a transfer. Finally, the CIL performs basic
-+ * services that are not specific to either the host or device modes
-+ * of operation. These services include management of the OTG Host
-+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
-+ * Diagnostic API is also provided to allow testing of the controller
-+ * hardware.
-+ *
-+ * The Core Interface Layer has the following requirements:
-+ * - Provides basic controller operations.
-+ * - Minimal use of OS services.
-+ * - The OS services used will be abstracted by using inline functions
-+ * or macros.
-+ *
-+ */
-+
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+
-+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * This function is called to initialize the DWC_otg CSR data
-+ * structures. The register addresses in the device and host
-+ * structures are initialized from the base address supplied by the
-+ * caller. The calling function must make the OS calls to get the
-+ * base address of the DWC_otg controller registers. The core_params
-+ * argument holds the parameters that specify how the core should be
-+ * configured.
-+ *
-+ * @param reg_base_addr Base address of DWC_otg core registers
-+ *
-+ */
-+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
-+{
-+ dwc_otg_core_if_t *core_if = 0;
-+ dwc_otg_dev_if_t *dev_if = 0;
-+ dwc_otg_host_if_t *host_if = 0;
-+ uint8_t *reg_base = (uint8_t *) reg_base_addr;
-+ int i = 0;
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
-+
-+ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
-+
-+ if (core_if == NULL) {
-+ DWC_DEBUGPL(DBG_CIL,
-+ "Allocation of dwc_otg_core_if_t failed\n");
-+ return 0;
-+ }
-+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
-+
-+ /*
-+ * Allocate the Device Mode structures.
-+ */
-+ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
-+
-+ if (dev_if == NULL) {
-+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ dev_if->dev_global_regs =
-+ (dwc_otg_device_global_regs_t *) (reg_base +
-+ DWC_DEV_GLOBAL_REG_OFFSET);
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
-+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
-+ (i * DWC_EP_REG_OFFSET));
-+
-+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
-+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
-+ (i * DWC_EP_REG_OFFSET));
-+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
-+ i, &dev_if->in_ep_regs[i]->diepctl);
-+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
-+ i, &dev_if->out_ep_regs[i]->doepctl);
-+ }
-+
-+ dev_if->speed = 0; // unknown
-+
-+ core_if->dev_if = dev_if;
-+
-+ /*
-+ * Allocate the Host Mode structures.
-+ */
-+ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
-+
-+ if (host_if == NULL) {
-+ DWC_DEBUGPL(DBG_CIL,
-+ "Allocation of dwc_otg_host_if_t failed\n");
-+ DWC_FREE(dev_if);
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
-+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
-+
-+ host_if->hprt0 =
-+ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
-+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
-+ (i * DWC_OTG_CHAN_REGS_OFFSET));
-+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
-+ i, &host_if->hc_regs[i]->hcchar);
-+ }
-+
-+ host_if->num_host_channels = MAX_EPS_CHANNELS;
-+ core_if->host_if = host_if;
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ core_if->data_fifo[i] =
-+ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
-+ (i * DWC_OTG_DATA_FIFO_SIZE));
-+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
-+ i, (unsigned long)core_if->data_fifo[i]);
-+ }
-+
-+ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
-+
-+ /* Initiate lx_state to L3 disconnected state */
-+ core_if->lx_state = DWC_OTG_L3;
-+ /*
-+ * Store the contents of the hardware configuration registers here for
-+ * easy access later.
-+ */
-+ core_if->hwcfg1.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
-+ core_if->hwcfg2.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
-+ core_if->hwcfg3.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
-+ core_if->hwcfg4.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
-+
-+ /* Force host mode to get HPTXFSIZ exact power on value */
-+ {
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ gusbcfg.b.force_host_mode = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+ dwc_mdelay(100);
-+ core_if->hptxfsiz.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ gusbcfg.b.force_host_mode = 0;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+ dwc_mdelay(100);
-+ }
-+
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
-+ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
-+
-+ core_if->hcfg.d32 =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ core_if->dcfg.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+
-+ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
-+ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
-+ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
-+ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
-+ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
-+ core_if->hwcfg2.b.num_host_chan);
-+ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
-+ core_if->hwcfg2.b.nonperio_tx_q_depth);
-+ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
-+ core_if->hwcfg2.b.host_perio_tx_q_depth);
-+ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
-+ core_if->hwcfg2.b.dev_token_q_depth);
-+
-+ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
-+ core_if->hwcfg3.b.dfifo_depth);
-+ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
-+ core_if->hwcfg3.b.xfer_size_cntr_width);
-+
-+ /*
-+ * Set the SRP sucess bit for FS-I2c
-+ */
-+ core_if->srp_success = 0;
-+ core_if->srp_timer_started = 0;
-+
-+ /*
-+ * Create new workqueue and init works
-+ */
-+ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
-+ if (core_if->wq_otg == 0) {
-+ DWC_WARN("DWC_WORKQ_ALLOC failed\n");
-+ DWC_FREE(host_if);
-+ DWC_FREE(dev_if);
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
-+
-+ DWC_PRINTF("Core Release: %x.%x%x%x\n",
-+ (core_if->snpsid >> 12 & 0xF),
-+ (core_if->snpsid >> 8 & 0xF),
-+ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
-+
-+ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
-+ w_wakeup_detected, core_if);
-+ if (core_if->wkp_timer == 0) {
-+ DWC_WARN("DWC_TIMER_ALLOC failed\n");
-+ DWC_FREE(host_if);
-+ DWC_FREE(dev_if);
-+ DWC_WORKQ_FREE(core_if->wq_otg);
-+ DWC_FREE(core_if);
-+ return 0;
-+ }
-+
-+ if (dwc_otg_setup_params(core_if)) {
-+ DWC_WARN("Error while setting core params\n");
-+ }
-+
-+ core_if->hibernation_suspend = 0;
-+
-+ /** ADP initialization */
-+ dwc_otg_adp_init(core_if);
-+
-+ return core_if;
-+}
-+
-+/**
-+ * This function frees the structures allocated by dwc_otg_cil_init().
-+ *
-+ * @param core_if The core interface pointer returned from
-+ * dwc_otg_cil_init().
-+ *
-+ */
-+void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
-+{
-+ dctl_data_t dctl = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
-+
-+ /* Disable all interrupts */
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
-+
-+ dctl.b.sftdiscon = 1;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
-+ dctl.d32);
-+ }
-+
-+ if (core_if->wq_otg) {
-+ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
-+ DWC_WORKQ_FREE(core_if->wq_otg);
-+ }
-+ if (core_if->dev_if) {
-+ DWC_FREE(core_if->dev_if);
-+ }
-+ if (core_if->host_if) {
-+ DWC_FREE(core_if->host_if);
-+ }
-+
-+ /** Remove ADP Stuff */
-+ dwc_otg_adp_remove(core_if);
-+ if (core_if->core_params) {
-+ DWC_FREE(core_if->core_params);
-+ }
-+ if (core_if->wkp_timer) {
-+ DWC_TIMER_FREE(core_if->wkp_timer);
-+ }
-+ if (core_if->srp_timer) {
-+ DWC_TIMER_FREE(core_if->srp_timer);
-+ }
-+ DWC_FREE(core_if);
-+}
-+
-+/**
-+ * This function enables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
-+}
-+
-+/**
-+ * This function disables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the commmon interrupts, used in both
-+ * device and host modes.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ /* Clear any pending OTG Interrupts */
-+ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
-+
-+ /* Clear any pending interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /*
-+ * Enable the interrupts in the GINTMSK.
-+ */
-+ intr_mask.b.modemismatch = 1;
-+ intr_mask.b.otgintr = 1;
-+
-+ if (!core_if->dma_enable) {
-+ intr_mask.b.rxstsqlvl = 1;
-+ }
-+
-+ intr_mask.b.conidstschng = 1;
-+ intr_mask.b.wkupintr = 1;
-+ intr_mask.b.disconnect = 0;
-+ intr_mask.b.usbsuspend = 1;
-+ intr_mask.b.sessreqintr = 1;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (core_if->core_params->lpm_enable) {
-+ intr_mask.b.lpmtranrcvd = 1;
-+ }
-+#endif
-+ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
-+}
-+
-+/*
-+ * The restore operation is modified to support Synopsys Emulated Powerdown and
-+ * Hibernation. This function is for exiting from Device mode hibernation by
-+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
-+ * @param reset - indicates whether resume is initiated by Reset.
-+ */
-+int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+
-+ int timeout = 2000;
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
-+ /* Switch-on voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Assert Restore signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ if (rem_wakeup) {
-+ dwc_udelay(70);
-+ }
-+
-+ /* Deassert Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Mask interrupts from gpwrdn */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.connect_det_msk = 1;
-+ gpwrdn.b.srp_det_msk = 1;
-+ gpwrdn.b.disconn_det_msk = 1;
-+ gpwrdn.b.rst_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Indicates that we are going out from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /*
-+ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
-+ * indicates restore from remote_wakeup
-+ */
-+ restore_essential_regs(core_if, rem_wakeup, 0);
-+
-+ /*
-+ * Wait a little for seeing new value of variable hibernation_suspend if
-+ * Restore done interrupt received before polling
-+ */
-+ dwc_udelay(10);
-+
-+ if (core_if->hibernation_suspend == 0) {
-+ /*
-+ * Wait For Restore_done Interrupt. This mechanism of polling the
-+ * interrupt is introduced to avoid any possible race conditions
-+ */
-+ do {
-+ gintsts_data_t gintsts;
-+ gintsts.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (gintsts.b.restoredone) {
-+ gintsts.d32 = 0;
-+ gintsts.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, gintsts.d32);
-+ DWC_PRINTF("Restore Done Interrupt seen\n");
-+ break;
-+ }
-+ dwc_udelay(10);
-+ } while (--timeout);
-+ if (!timeout) {
-+ DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
-+ }
-+ }
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* De-assert Restore */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ if (!rem_wakeup) {
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ }
-+
-+ /* Restore GUSBCFG and DCFG */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+ core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+ core_if->dr_backup->dcfg);
-+
-+ /* De-assert Wakeup Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ if (!rem_wakeup) {
-+ /* Set Device programming done bit */
-+ dctl.b.pwronprgdone = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ } else {
-+ /* Start Remote Wakeup Signaling */
-+ dctl.d32 = core_if->dr_backup->dctl;
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+ }
-+
-+ dwc_mdelay(2);
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Restore global registers */
-+ dwc_otg_restore_global_regs(core_if);
-+ /* Restore device global registers */
-+ dwc_otg_restore_dev_regs(core_if, rem_wakeup);
-+
-+ if (rem_wakeup) {
-+ dwc_mdelay(7);
-+ dctl.d32 = 0;
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+ }
-+
-+ core_if->hibernation_suspend = 0;
-+ /* The core will be in ON STATE */
-+ core_if->lx_state = DWC_OTG_L0;
-+ DWC_PRINTF("Hibernation recovery completes here\n");
-+
-+ return 1;
-+}
-+
-+/*
-+ * The restore operation is modified to support Synopsys Emulated Powerdown and
-+ * Hibernation. This function is for exiting from Host mode hibernation by
-+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
-+ * @param reset - indicates whether resume is initiated by Reset.
-+ */
-+int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+ int timeout = 2000;
-+
-+ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
-+ /* Switch-on voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Assert Restore signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ if (!rem_wakeup) {
-+ dwc_udelay(50);
-+ }
-+
-+ /* Deassert Reset core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.connect_det_msk = 1;
-+ gpwrdn.b.srp_det_msk = 1;
-+ gpwrdn.b.disconn_det_msk = 1;
-+ gpwrdn.b.rst_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Indicates that we are going out from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Set Restore Essential Regs bit in PCGCCTL register */
-+ restore_essential_regs(core_if, rem_wakeup, 1);
-+
-+ /* Wait a little for seeing new value of variable hibernation_suspend if
-+ * Restore done interrupt received before polling */
-+ dwc_udelay(10);
-+
-+ if (core_if->hibernation_suspend == 0) {
-+ /* Wait For Restore_done Interrupt. This mechanism of polling the
-+ * interrupt is introduced to avoid any possible race conditions
-+ */
-+ do {
-+ gintsts_data_t gintsts;
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (gintsts.b.restoredone) {
-+ gintsts.d32 = 0;
-+ gintsts.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
-+ break;
-+ }
-+ dwc_udelay(10);
-+ } while (--timeout);
-+ if (!timeout) {
-+ DWC_WARN("Restore Done interrupt wasn't generated\n");
-+ }
-+ }
-+
-+ /* Set the flag's value to 0 again after receiving restore done interrupt */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* This step is not described in functional spec but if not wait for this
-+ * delay, mismatch interrupts occurred because just after restore core is
-+ * in Device mode(gintsts.curmode == 0) */
-+ dwc_mdelay(100);
-+
-+ /* Clear all pending interrupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* De-assert Restore */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Restore GUSBCFG and HCFG */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+ core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
-+ core_if->hr_backup->hcfg_local);
-+
-+ /* De-assert Wakeup Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Start the Resume operation by programming HPRT0 */
-+ hprt0.d32 = core_if->hr_backup->hprt0_local;
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtsusp = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ DWC_PRINTF("Resume Starts Now\n");
-+ if (!reset) { // Indicates it is Resume Operation
-+ hprt0.d32 = core_if->hr_backup->hprt0_local;
-+ hprt0.b.prtres = 1;
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtsusp = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ if (!rem_wakeup)
-+ hprt0.b.prtres = 0;
-+ /* Wait for Resume time and then program HPRT again */
-+ dwc_mdelay(100);
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ } else { // Indicates it is Reset Operation
-+ hprt0.d32 = core_if->hr_backup->hprt0_local;
-+ hprt0.b.prtrst = 1;
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtsusp = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ /* Wait for Reset time and then program HPRT again */
-+ dwc_mdelay(60);
-+ hprt0.b.prtrst = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+ /* Clear all interrupt status */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtconndet = 1;
-+ hprt0.b.prtenchng = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Restore global registers */
-+ dwc_otg_restore_global_regs(core_if);
-+ /* Restore host global registers */
-+ dwc_otg_restore_host_regs(core_if, reset);
-+
-+ /* The core will be in ON STATE */
-+ core_if->lx_state = DWC_OTG_L0;
-+ DWC_PRINTF("Hibernation recovery is complete here\n");
-+ return 0;
-+}
-+
-+/** Saves some register values into system memory. */
-+int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+ int i;
-+
-+ gr = core_if->gr_backup;
-+ if (!gr) {
-+ gr = DWC_ALLOC(sizeof(*gr));
-+ if (!gr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->gr_backup = gr;
-+ }
-+
-+ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
-+ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
-+ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+#endif
-+ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
-+ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
-+ gr->gdfifocfg_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ gr->dtxfsiz_local[i] =
-+ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
-+ }
-+
-+ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
-+ gr->gnptxfsiz_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
-+ gr->hptxfsiz_local);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
-+#endif
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
-+ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
-+
-+ return 0;
-+}
-+
-+/** Saves GINTMSK register before setting the msk bits. */
-+int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+
-+ gr = core_if->gr_backup;
-+ if (!gr) {
-+ gr = DWC_ALLOC(sizeof(*gr));
-+ if (!gr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->gr_backup = gr;
-+ }
-+
-+ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
-+
-+ return 0;
-+}
-+
-+int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_dev_regs_backup *dr;
-+ int i;
-+
-+ dr = core_if->dr_backup;
-+ if (!dr) {
-+ dr = DWC_ALLOC(sizeof(*dr));
-+ if (!dr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->dr_backup = dr;
-+ }
-+
-+ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ dr->daintmsk =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ dr->diepmsk =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
-+ dr->doepmsk =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
-+
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ dr->diepctl[i] =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
-+ dr->dieptsiz[i] =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
-+ dr->diepdma[i] =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
-+ }
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "=============Backing Host registers==============\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
-+ dr->daintmsk);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
-+ dr->diepctl[i]);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
-+ i, dr->dieptsiz[i]);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
-+ dr->diepdma[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_host_regs_backup *hr;
-+ int i;
-+
-+ hr = core_if->hr_backup;
-+ if (!hr) {
-+ hr = DWC_ALLOC(sizeof(*hr));
-+ if (!hr) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ core_if->hr_backup = hr;
-+ }
-+
-+ hr->hcfg_local =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ hr->haintmsk_local =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
-+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+ hr->hcintmsk_local[i] =
-+ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
-+ }
-+ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
-+ hr->hfir_local =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "=============Backing Host registers===============\n");
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
-+ hr->hcfg_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
-+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
-+ hr->hcintmsk_local[i]);
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
-+ hr->hprt0_local);
-+ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
-+ hr->hfir_local);
-+
-+ return 0;
-+}
-+
-+int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+ int i;
-+
-+ gr = core_if->gr_backup;
-+ if (!gr) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
-+ gr->gnptxfsiz_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
-+ gr->hptxfsiz_local);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
-+ gr->gdfifocfg_local);
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
-+ gr->dtxfsiz_local[i]);
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
-+ (gr->gahbcfg_local));
-+ return 0;
-+}
-+
-+int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
-+{
-+ struct dwc_otg_dev_regs_backup *dr;
-+ int i;
-+
-+ dr = core_if->dr_backup;
-+
-+ if (!dr) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (!rem_wakeup) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ dr->dctl);
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
-+
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
-+{
-+ struct dwc_otg_host_regs_backup *hr;
-+ int i;
-+ hr = core_if->hr_backup;
-+
-+ if (!hr) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
-+ //if (!reset)
-+ //{
-+ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
-+ //}
-+
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
-+ hr->haintmsk_local);
-+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
-+ hr->hcintmsk_local[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+
-+ gr = core_if->gr_backup;
-+
-+ /* Restore values for LPM and I2C */
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
-+#endif
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
-+
-+ return 0;
-+}
-+
-+int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
-+{
-+ struct dwc_otg_global_regs_backup *gr;
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+ /* Restore LPM and I2C registers */
-+ restore_lpm_i2c_regs(core_if);
-+
-+ /* Set PCGCCTL to 0 */
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
-+
-+ gr = core_if->gr_backup;
-+ /* Load restore values for [31:14] bits */
-+ DWC_WRITE_REG32(core_if->pcgcctl,
-+ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
-+
-+ /* Umnask global Interrupt in GAHBCFG and restore it */
-+ gahbcfg.d32 = gr->gahbcfg_local;
-+ gahbcfg.b.glblintrmsk = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
-+
-+ /* Clear all pending interupts */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Unmask restore done interrupt */
-+ gintmsk.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
-+
-+ /* Restore GUSBCFG and HCFG/DCFG */
-+ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+
-+ if (is_host) {
-+ hcfg_data_t hcfg = {.d32 = 0 };
-+ hcfg.d32 = core_if->hr_backup->hcfg_local;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
-+ hcfg.d32);
-+
-+ /* Load restore values for [31:14] bits */
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+
-+ if (rmode)
-+ pcgcctl.b.restoremode = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ /* Load restore values for [31:14] bits and set EssRegRestored bit */
-+ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.b.ess_reg_restored = 1;
-+ if (rmode)
-+ pcgcctl.b.restoremode = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ } else {
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+ dcfg.d32 = core_if->dr_backup->dcfg;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* Load restore values for [31:14] bits */
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+ if (!rmode) {
-+ pcgcctl.d32 |= 0x208;
-+ }
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ /* Load restore values for [31:14] bits */
-+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+ pcgcctl.b.ess_reg_restored = 1;
-+ if (!rmode)
-+ pcgcctl.d32 |= 0x208;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
-+ * type.
-+ */
-+static void init_fslspclksel(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t val;
-+ hcfg_data_t hcfg;
-+
-+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) ||
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* Full speed PHY */
-+ val = DWC_HCFG_48_MHZ;
-+ } else {
-+ /* High speed PHY running at full speed or high speed */
-+ val = DWC_HCFG_30_60_MHZ;
-+ }
-+
-+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
-+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ hcfg.b.fslspclksel = val;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/**
-+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
-+ * and the enumeration speed of the device.
-+ */
-+static void init_devspd(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t val;
-+ dcfg_data_t dcfg;
-+
-+ if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) ||
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* Full speed PHY */
-+ val = 0x3;
-+ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+ /* High speed PHY running at full speed */
-+ val = 0x1;
-+ } else {
-+ /* High speed PHY running at high speed */
-+ val = 0x0;
-+ }
-+
-+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
-+
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devspd = val;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+/**
-+ * This function calculates the number of IN EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t num_in_eps = 0;
-+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
-+ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
-+ int i;
-+
-+ for (i = 0; i < num_eps; ++i) {
-+ if (!(hwcfg1 & 0x1))
-+ num_in_eps++;
-+
-+ hwcfg1 >>= 2;
-+ }
-+
-+ if (core_if->hwcfg4.b.ded_fifo_en) {
-+ num_in_eps =
-+ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
-+ }
-+
-+ return num_in_eps;
-+}
-+
-+/**
-+ * This function calculates the number of OUT EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t num_out_eps = 0;
-+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
-+ int i;
-+
-+ for (i = 0; i < num_eps; ++i) {
-+ if (!(hwcfg1 & 0x1))
-+ num_out_eps++;
-+
-+ hwcfg1 >>= 2;
-+ }
-+ return num_out_eps;
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers and
-+ * prepares the core for device mode or host mode operation.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
-+{
-+ int i = 0;
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+ gusbcfg_data_t usbcfg = {.d32 = 0 };
-+ gi2cctl_data_t i2cctl = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
-+ core_if, global_regs);
-+
-+ /* Common Initialization */
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+ /* Program the ULPI External VBUS bit if needed */
-+ usbcfg.b.ulpi_ext_vbus_drv =
-+ (core_if->core_params->phy_ulpi_ext_vbus ==
-+ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
-+
-+ /* Set external TS Dline pulsing */
-+ usbcfg.b.term_sel_dl_pulse =
-+ (core_if->core_params->ts_dline == 1) ? 1 : 0;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Reset the Controller */
-+ dwc_otg_core_reset(core_if);
-+
-+ core_if->adp_enable = core_if->core_params->adp_supp_enable;
-+ core_if->power_down = core_if->core_params->power_down;
-+ core_if->otg_sts = 0;
-+
-+ /* Initialize parameters from Hardware configuration registers. */
-+ dev_if->num_in_eps = calc_num_in_eps(core_if);
-+ dev_if->num_out_eps = calc_num_out_eps(core_if);
-+
-+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
-+ core_if->hwcfg4.b.num_dev_perio_in_ep);
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
-+ dev_if->perio_tx_fifo_size[i] =
-+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
-+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
-+ i, dev_if->perio_tx_fifo_size[i]);
-+ }
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+ dev_if->tx_fifo_size[i] =
-+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
-+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
-+ i, dev_if->tx_fifo_size[i]);
-+ }
-+
-+ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
-+ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
-+ core_if->nperio_tx_fifo_size =
-+ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
-+
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
-+ core_if->nperio_tx_fifo_size);
-+
-+ /* This programming sequence needs to happen in FS mode before any other
-+ * programming occurs */
-+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
-+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+ /* If FS mode with FS PHY */
-+
-+ /* core_init() is now called on every switch so only call the
-+ * following for the first time through. */
-+ if (!core_if->phy_init_done) {
-+ core_if->phy_init_done = 1;
-+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.physel = 1;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Reset after a PHY select */
-+ dwc_otg_core_reset(core_if);
-+ }
-+
-+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
-+ * do this on HNP Dev/Host mode switches (done in dev_init and
-+ * host_init). */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ init_fslspclksel(core_if);
-+ } else {
-+ init_devspd(core_if);
-+ }
-+
-+ if (core_if->core_params->i2c_enable) {
-+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
-+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.otgutmifssel = 1;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+ /* Program GI2CCTL.I2CEn */
-+ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
-+ i2cctl.b.i2cdevaddr = 1;
-+ i2cctl.b.i2cen = 0;
-+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
-+ i2cctl.b.i2cen = 1;
-+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
-+ }
-+
-+ } /* endif speed == DWC_SPEED_PARAM_FULL */
-+ else {
-+ /* High speed PHY. */
-+ if (!core_if->phy_init_done) {
-+ core_if->phy_init_done = 1;
-+ /* HS PHY parameters. These parameters are preserved
-+ * during soft reset so only program the first time. Do
-+ * a soft reset immediately after setting phyif. */
-+
-+ if (core_if->core_params->phy_type == 2) {
-+ /* ULPI interface */
-+ usbcfg.b.ulpi_utmi_sel = 1;
-+ usbcfg.b.phyif = 0;
-+ usbcfg.b.ddrsel =
-+ core_if->core_params->phy_ulpi_ddr;
-+ } else if (core_if->core_params->phy_type == 1) {
-+ /* UTMI+ interface */
-+ usbcfg.b.ulpi_utmi_sel = 0;
-+ if (core_if->core_params->phy_utmi_width == 16) {
-+ usbcfg.b.phyif = 1;
-+
-+ } else {
-+ usbcfg.b.phyif = 0;
-+ }
-+ } else {
-+ DWC_ERROR("FS PHY TYPE\n");
-+ }
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+ /* Reset after setting the PHY parameters */
-+ dwc_otg_core_reset(core_if);
-+ }
-+ }
-+
-+ if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls)) {
-+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.ulpi_fsls = 1;
-+ usbcfg.b.ulpi_clk_sus_m = 1;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+ } else {
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ usbcfg.b.ulpi_fsls = 0;
-+ usbcfg.b.ulpi_clk_sus_m = 0;
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+ }
-+
-+ /* Program the GAHBCFG Register. */
-+ switch (core_if->hwcfg2.b.architecture) {
-+
-+ case DWC_SLAVE_ONLY_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
-+ ahbcfg.b.nptxfemplvl_txfemplvl =
-+ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+ core_if->dma_enable = 0;
-+ core_if->dma_desc_enable = 0;
-+ break;
-+
-+ case DWC_EXT_DMA_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
-+ {
-+ uint8_t brst_sz = core_if->core_params->dma_burst_size;
-+ ahbcfg.b.hburstlen = 0;
-+ while (brst_sz > 1) {
-+ ahbcfg.b.hburstlen++;
-+ brst_sz >>= 1;
-+ }
-+ }
-+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+ core_if->dma_desc_enable =
-+ (core_if->core_params->dma_desc_enable != 0);
-+ break;
-+
-+ case DWC_INT_DMA_ARCH:
-+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
-+ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
-+ Host mode ISOC in issue fix - vahrama */
-+ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
-+ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
-+ core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+ core_if->dma_desc_enable =
-+ (core_if->core_params->dma_desc_enable != 0);
-+ break;
-+
-+ }
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ DWC_PRINTF("Using Descriptor DMA mode\n");
-+ } else {
-+ DWC_PRINTF("Using Buffer DMA mode\n");
-+
-+ }
-+ } else {
-+ DWC_PRINTF("Using Slave mode\n");
-+ core_if->dma_desc_enable = 0;
-+ }
-+
-+ if (core_if->core_params->ahb_single) {
-+ ahbcfg.b.ahbsingle = 1;
-+ }
-+
-+ ahbcfg.b.dmaenable = core_if->dma_enable;
-+ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
-+
-+ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
-+
-+ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
-+ core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
-+ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
-+ ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
-+ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
-+ ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
-+
-+ /*
-+ * Program the GUSBCFG register.
-+ */
-+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+ switch (core_if->hwcfg2.b.op_mode) {
-+ case DWC_MODE_HNP_SRP_CAPABLE:
-+ usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_SRP_ONLY_CAPABLE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_HNP_SRP_CAPABLE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+
-+ case DWC_MODE_SRP_CAPABLE_DEVICE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+
-+ case DWC_MODE_SRP_CAPABLE_HOST:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ break;
-+
-+ case DWC_MODE_NO_SRP_CAPABLE_HOST:
-+ usbcfg.b.hnpcap = 0;
-+ usbcfg.b.srpcap = 0;
-+ break;
-+ }
-+
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (core_if->core_params->lpm_enable) {
-+ glpmcfg_data_t lpmcfg = {.d32 = 0 };
-+
-+ /* To enable LPM support set lpm_cap_en bit */
-+ lpmcfg.b.lpm_cap_en = 1;
-+
-+ /* Make AppL1Res ACK */
-+ lpmcfg.b.appl_resp = 1;
-+
-+ /* Retry 3 times */
-+ lpmcfg.b.retry_count = 3;
-+
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
-+ 0, lpmcfg.d32);
-+
-+ }
-+#endif
-+ if (core_if->core_params->ic_usb_cap) {
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+ gusbcfg.b.ic_usb_cap = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
-+ 0, gusbcfg.d32);
-+ }
-+ {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gotgctl.b.otgver = core_if->core_params->otg_ver;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
-+ gotgctl.d32);
-+ /* Set OTG version supported */
-+ core_if->otg_ver = core_if->core_params->otg_ver;
-+ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
-+ core_if->core_params->otg_ver, core_if->otg_ver);
-+ }
-+
-+
-+ /* Enable common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /* Do device or host intialization based on mode during PCD
-+ * and HCD initialization */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
-+ core_if->op_state = A_HOST;
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
-+ core_if->op_state = B_PERIPHERAL;
-+#ifdef DWC_DEVICE_ONLY
-+ dwc_otg_core_dev_init(core_if);
-+#endif
-+ }
-+}
-+
-+/**
-+ * This function enables the Device mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
-+
-+ /* Disable all interrupts. */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Enable the common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /* Enable interrupts */
-+ intr_mask.b.usbreset = 1;
-+ intr_mask.b.enumdone = 1;
-+ /* Disable Disconnect interrupt in Device mode */
-+ intr_mask.b.disconnect = 0;
-+
-+ if (!core_if->multiproc_int_enable) {
-+ intr_mask.b.inepintr = 1;
-+ intr_mask.b.outepintr = 1;
-+ }
-+
-+ intr_mask.b.erlysuspend = 1;
-+
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.epmismatch = 1;
-+ }
-+
-+ //intr_mask.b.incomplisoout = 1;
-+ intr_mask.b.incomplisoin = 1;
-+
-+/* Enable the ignore frame number for ISOC xfers - MAS */
-+/* Disable to support high bandwith ISOC transfers - manukz */
-+#if 0
-+#ifdef DWC_UTE_PER_IO
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ dctl_data_t dctl1 = {.d32 = 0 };
-+ dctl1.b.ifrmnum = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, 0, dctl1.d32);
-+ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
-+ DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dctl));
-+ }
-+ }
-+#endif
-+#endif
-+#ifdef DWC_EN_ISOC
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ if (core_if->pti_enh_enable) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.ifrmnum = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dctl,
-+ 0, dctl.d32);
-+ } else {
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+ }
-+ }
-+ } else {
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+ }
-+#endif /* DWC_EN_ISOC */
-+
-+ /** @todo NGS: Should this be a module parameter? */
-+#ifdef USE_PERIODIC_EP
-+ intr_mask.b.isooutdrop = 1;
-+ intr_mask.b.eopframe = 1;
-+ intr_mask.b.incomplisoin = 1;
-+ intr_mask.b.incomplisoout = 1;
-+#endif
-+
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * device mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+ depctl_data_t diepctl = {.d32 = 0 };
-+ grstctl_t resetctl = {.d32 = 0 };
-+ uint32_t rx_fifo_size;
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t txfifosize;
-+ dthrctl_data_t dthrctl;
-+ fifosize_data_t ptxfifosize;
-+ uint16_t rxfsiz, nptxfsiz;
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ hwcfg3_data_t hwcfg3 = {.d32 = 0 };
-+
-+ /* Restart the Phy Clock */
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+
-+ /* Device configuration register */
-+ init_devspd(core_if);
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
-+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
-+ /* Enable Device OUT NAK in case of DDMA mode*/
-+ if (core_if->core_params->dev_out_nak) {
-+ dcfg.b.endevoutnak = 1;
-+ }
-+
-+ if (core_if->core_params->cont_on_bna) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.encontonbna = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
-+ core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
-+ params->dev_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
-+ params->dev_nperio_tx_fifo_size);
-+
-+ /* Rx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+#ifdef DWC_UTE_CFI
-+ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
-+ core_if->init_rxfsiz = params->dev_rx_fifo_size;
-+#endif
-+ rx_fifo_size = params->dev_rx_fifo_size;
-+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+ /** Set Periodic Tx FIFO Mask all bits 0 */
-+ core_if->p_tx_msk = 0;
-+
-+ /** Set Tx FIFO Mask all bits 0 */
-+ core_if->tx_msk = 0;
-+
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz,
-+ nptxfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ /**@todo NGS: Fix Periodic FIFO Sizing! */
-+ /*
-+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_perio_tx_fifo_size array and the FIFO size registers in
-+ * the dptxfsiz array run from 0 to 14.
-+ */
-+ /** @todo Finish debug of this */
-+ ptxfifosize.b.startaddr =
-+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
-+ ptxfifosize.b.depth =
-+ params->dev_perio_tx_fifo_size[i];
-+ DWC_DEBUGPL(DBG_CIL,
-+ "initial dtxfsiz[%d]=%08x\n", i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ ptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
-+ i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+ ptxfifosize.b.startaddr += ptxfifosize.b.depth;
-+ }
-+ } else {
-+ /*
-+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+ * Indexes of the FIFO size module parameters in the
-+ * dev_tx_fifo_size array and the FIFO size registers in
-+ * the dtxfsiz array run from 0 to 14.
-+ */
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+#ifdef DWC_UTE_CFI
-+ core_if->pwron_gnptxfsiz =
-+ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+ core_if->init_gnptxfsiz =
-+ params->dev_nperio_tx_fifo_size;
-+#endif
-+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz,
-+ nptxfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ txfifosize.b.startaddr =
-+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+ txfifosize.b.depth =
-+ params->dev_tx_fifo_size[i];
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ "initial dtxfsiz[%d]=%08x\n",
-+ i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+
-+#ifdef DWC_UTE_CFI
-+ core_if->pwron_txfsiz[i] =
-+ (DWC_READ_REG32
-+ (&global_regs->dtxfsiz[i]) >> 16);
-+ core_if->init_txfsiz[i] =
-+ params->dev_tx_fifo_size[i];
-+#endif
-+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+ txfifosize.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ "new dtxfsiz[%d]=%08x\n",
-+ i,
-+ DWC_READ_REG32(&global_regs->dtxfsiz
-+ [i]));
-+
-+ txfifosize.b.startaddr += txfifosize.b.depth;
-+ }
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
-+ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
-+ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
-+ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
-+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
-+ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
-+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+ }
-+ }
-+
-+ /* Flush the FIFOs */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ /* Flush the Learning Queue. */
-+ resetctl.b.intknqflsh = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
-+ core_if->start_predict = 0;
-+ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
-+ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
-+ }
-+ core_if->nextep_seq[0] = 0;
-+ core_if->first_in_nextep_seq = 0;
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+ diepctl.b.nextep = 0;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt = 2;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
-+ }
-+ DWC_DEBUGPL(DBG_CILV,"\n");
-+ }
-+
-+ /* Clear all pending Device Interrupts */
-+ /** @todo - if the condition needed to be checked
-+ * or in any case all pending interrutps should be cleared?
-+ */
-+ if (core_if->multiproc_int_enable) {
-+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+ DWC_WRITE_REG32(&dev_if->
-+ dev_global_regs->diepeachintmsk[i], 0);
-+ }
-+ }
-+
-+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ DWC_WRITE_REG32(&dev_if->
-+ dev_global_regs->doepeachintmsk[i], 0);
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
-+ } else {
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
-+ }
-+
-+ for (i = 0; i <= dev_if->num_in_eps; i++) {
-+ depctl_data_t depctl;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (depctl.b.epena) {
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ } else {
-+ depctl.d32 = 0;
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
-+ }
-+
-+ for (i = 0; i <= dev_if->num_out_eps; i++) {
-+ depctl_data_t depctl;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+ if (depctl.b.epena) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ gintmsk_data_t gintsts = {.d32 = 0 };
-+ doepint_data_t doepint = {.d32 = 0 };
-+ dctl.b.sgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ } while (!gintsts.b.goutnakeff);
-+ gintsts.d32 = 0;
-+ gintsts.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[i]->doepint);
-+ } while (!doepint.b.epdisabled);
-+
-+ doepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
-+
-+ dctl.d32 = 0;
-+ dctl.b.cgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ } else {
-+ depctl.d32 = 0;
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
-+ }
-+
-+ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
-+ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
-+ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
-+
-+ dev_if->rx_thr_length = params->rx_thr_length;
-+ dev_if->tx_thr_length = params->tx_thr_length;
-+
-+ dev_if->setup_desc_index = 0;
-+
-+ dthrctl.d32 = 0;
-+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
-+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
-+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
-+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
-+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
-+ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
-+ dthrctl.d32);
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
-+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
-+ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
-+ dthrctl.b.rx_thr_len);
-+
-+ }
-+
-+ dwc_otg_enable_device_interrupts(core_if);
-+
-+ {
-+ diepmsk_data_t msk = {.d32 = 0 };
-+ msk.b.txfifoundrn = 1;
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->
-+ diepeachintmsk[0], msk.d32, msk.d32);
-+ } else {
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
-+ msk.d32, msk.d32);
-+ }
-+ }
-+
-+ if (core_if->multiproc_int_enable) {
-+ /* Set NAK on Babble */
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.nakonbble = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+
-+ if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
-+ dctl.b.sftdiscon = 0;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function enables the Host mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
-+
-+ /* Disable all interrupts. */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* Clear any pending interrupts. */
-+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+ /* Enable the common interrupts */
-+ dwc_otg_enable_common_interrupts(core_if);
-+
-+ /*
-+ * Enable host mode interrupts without disturbing common
-+ * interrupts.
-+ */
-+
-+ intr_mask.b.disconnect = 1;
-+ intr_mask.b.portintr = 1;
-+ intr_mask.b.hcintr = 1;
-+
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+}
-+
-+/**
-+ * This function disables the Host Mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
-+
-+ /*
-+ * Disable host mode interrupts without disturbing common
-+ * interrupts.
-+ */
-+ intr_mask.b.sofintr = 1;
-+ intr_mask.b.portintr = 1;
-+ intr_mask.b.hcintr = 1;
-+ intr_mask.b.ptxfempty = 1;
-+ intr_mask.b.nptxfempty = 1;
-+
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * host mode.
-+ *
-+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
-+ * request queues. Host channels are reset to ensure that they are ready for
-+ * performing transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_host_if_t *host_if = core_if->host_if;
-+ dwc_otg_core_params_t *params = core_if->core_params;
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ fifosize_data_t nptxfifosize;
-+ fifosize_data_t ptxfifosize;
-+ uint16_t rxfsiz, nptxfsiz, hptxfsiz;
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ int i;
-+ hcchar_data_t hcchar;
-+ hcfg_data_t hcfg;
-+ hfir_data_t hfir;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ int num_channels;
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
-+
-+ /* Restart the Phy Clock */
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+
-+ /* Initialize Host Configuration Register */
-+ init_fslspclksel(core_if);
-+ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
-+ hcfg.b.fslssupp = 1;
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+
-+ }
-+
-+ /* This bit allows dynamic reloading of the HFIR register
-+ * during runtime. This bit needs to be programmed during
-+ * initial configuration and its value must not be changed
-+ * during runtime.*/
-+ if (core_if->core_params->reload_ctl == 1) {
-+ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
-+ hfir.b.hfirrldctrl = 1;
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
-+ }
-+
-+ if (core_if->core_params->dma_desc_enable) {
-+ uint8_t op_mode = core_if->hwcfg2.b.op_mode;
-+ if (!
-+ (core_if->hwcfg4.b.desc_dma
-+ && (core_if->snpsid >= OTG_CORE_REV_2_90a)
-+ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+ || (op_mode ==
-+ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
-+ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
-+ || (op_mode ==
-+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
-+
-+ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
-+ "Either core version is below 2.90a or "
-+ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
-+ "To run the driver in Buffer DMA host mode set dma_desc_enable "
-+ "module parameter to 0.\n");
-+ return;
-+ }
-+ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
-+ hcfg.b.descdma = 1;
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+ }
-+
-+ /* Configure data FIFO sizes */
-+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
-+ core_if->total_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
-+ params->host_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
-+ params->host_nperio_tx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
-+ params->host_perio_tx_fifo_size);
-+
-+ /* Rx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+ DWC_WRITE_REG32(&global_regs->grxfsiz,
-+ params->host_rx_fifo_size);
-+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+ /* Non-periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
-+ nptxfifosize.b.startaddr = params->host_rx_fifo_size;
-+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+ /* Periodic Tx FIFO */
-+ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->hptxfsiz));
-+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
-+ ptxfifosize.b.startaddr =
-+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
-+ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
-+ DWC_READ_REG32(&global_regs->hptxfsiz));
-+
-+ if (core_if->en_multiple_tx_fifo
-+ && core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
-+ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
-+ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
-+ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
-+ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
-+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+ }
-+ }
-+
-+ /* TODO - check this */
-+ /* Clear Host Set HNP Enable in the OTG Control Register */
-+ gotgctl.b.hstsethnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+ /* Make sure the FIFOs are flushed. */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
-+ dwc_otg_flush_rx_fifo(core_if);
-+
-+ /* Clear Host Set HNP Enable in the OTG Control Register */
-+ gotgctl.b.hstsethnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+
-+ if (!core_if->core_params->dma_desc_enable) {
-+ /* Flush out any leftover queued requests. */
-+ num_channels = core_if->core_params->host_channels;
-+
-+ for (i = 0; i < num_channels; i++) {
-+ hc_regs = core_if->host_if->hc_regs[i];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.chen = 0;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ }
-+
-+ /* Halt all channels to put them into a known state. */
-+ for (i = 0; i < num_channels; i++) {
-+ int count = 0;
-+ hc_regs = core_if->host_if->hc_regs[i];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
-+ do {
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (++count > 1000) {
-+ DWC_ERROR
-+ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
-+ __func__, i, hcchar.d32, &hc_regs->hcchar);
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (hcchar.b.chen);
-+ }
-+ }
-+
-+ /* Turn on the vbus power. */
-+ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
-+ if (core_if->op_state == A_HOST) {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
-+ if (hprt0.b.prtpwr == 0) {
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
-+ }
-+ }
-+
-+ dwc_otg_enable_host_interrupts(core_if);
-+}
-+
-+/**
-+ * Prepares a host channel for transferring packets to/from a specific
-+ * endpoint. The HCCHARn register is set up with the characteristics specified
-+ * in _hc. Host channel interrupts that may need to be serviced while this
-+ * transfer is in progress are enabled.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ * @param hc Information needed to initialize the host channel
-+ */
-+void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ hcintmsk_data_t hc_intr_mask;
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+
-+ uint8_t hc_num = hc->hc_num;
-+ dwc_otg_host_if_t *host_if = core_if->host_if;
-+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
-+
-+ /* Clear old interrupt conditions for this host channel. */
-+ hc_intr_mask.d32 = 0xFFFFFFFF;
-+ hc_intr_mask.b.reserved14_31 = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
-+
-+ /* Enable channel interrupts required for this transfer. */
-+ hc_intr_mask.d32 = 0;
-+ hc_intr_mask.b.chhltd = 1;
-+ if (core_if->dma_enable) {
-+ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
-+ if (!core_if->dma_desc_enable)
-+ hc_intr_mask.b.ahberr = 1;
-+ else {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ hc_intr_mask.b.xfercompl = 1;
-+ }
-+
-+ if (hc->error_state && !hc->do_split &&
-+ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ hc_intr_mask.b.ack = 1;
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.datatglerr = 1;
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+ hc_intr_mask.b.nak = 1;
-+ }
-+ }
-+ }
-+ } else {
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.stall = 1;
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.datatglerr = 1;
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.bblerr = 1;
-+ } else {
-+ hc_intr_mask.b.nak = 1;
-+ hc_intr_mask.b.nyet = 1;
-+ if (hc->do_ping) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+
-+ if (hc->do_split) {
-+ hc_intr_mask.b.nak = 1;
-+ if (hc->complete_split) {
-+ hc_intr_mask.b.nyet = 1;
-+ } else {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+
-+ if (hc->error_state) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ break;
-+ case DWC_OTG_EP_TYPE_INTR:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.nak = 1;
-+ hc_intr_mask.b.stall = 1;
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.datatglerr = 1;
-+ hc_intr_mask.b.frmovrun = 1;
-+
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ if (hc->error_state) {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ if (hc->do_split) {
-+ if (hc->complete_split) {
-+ hc_intr_mask.b.nyet = 1;
-+ } else {
-+ hc_intr_mask.b.ack = 1;
-+ }
-+ }
-+ break;
-+ case DWC_OTG_EP_TYPE_ISOC:
-+ hc_intr_mask.b.xfercompl = 1;
-+ hc_intr_mask.b.frmovrun = 1;
-+ hc_intr_mask.b.ack = 1;
-+
-+ if (hc->ep_is_in) {
-+ hc_intr_mask.b.xacterr = 1;
-+ hc_intr_mask.b.bblerr = 1;
-+ }
-+ break;
-+ }
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
-+
-+ /*
-+ * Program the HCCHARn register with the endpoint characteristics for
-+ * the current transfer.
-+ */
-+ hcchar.d32 = 0;
-+ hcchar.b.devaddr = hc->dev_addr;
-+ hcchar.b.epnum = hc->ep_num;
-+ hcchar.b.epdir = hc->ep_is_in;
-+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+ hcchar.b.eptype = hc->ep_type;
-+ hcchar.b.mps = hc->max_packet;
-+
-+ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
-+ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
-+ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, "
-+ "Max Pkt %d, Multi Cnt %d\n",
-+ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
-+ hcchar.b.mps, hcchar.b.multicnt);
-+
-+ /*
-+ * Program the HCSPLIT register for SPLITs
-+ */
-+ hcsplt.d32 = 0;
-+ if (hc->do_split) {
-+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
-+ hc->hc_num,
-+ hc->complete_split ? "CSPLIT" : "SSPLIT");
-+ hcsplt.b.compsplt = hc->complete_split;
-+ hcsplt.b.xactpos = hc->xact_pos;
-+ hcsplt.b.hubaddr = hc->hub_addr;
-+ hcsplt.b.prtaddr = hc->port_addr;
-+ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split);
-+ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos);
-+ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr);
-+ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr);
-+ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in);
-+ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps);
-+ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len);
-+ }
-+ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
-+
-+}
-+
-+/**
-+ * Attempts to halt a host channel. This function should only be called in
-+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
-+ * normal circumstances in DMA mode, the controller halts the channel when the
-+ * transfer is complete or a condition occurs that requires application
-+ * intervention.
-+ *
-+ * In slave mode, checks for a free request queue entry, then sets the Channel
-+ * Enable and Channel Disable bits of the Host Channel Characteristics
-+ * register of the specified channel to intiate the halt. If there is no free
-+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
-+ * register to flush requests for this channel. In the latter case, sets a
-+ * flag to indicate that the host channel needs to be halted when a request
-+ * queue slot is open.
-+ *
-+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
-+ * HCCHARn register. The controller ensures there is space in the request
-+ * queue before submitting the halt request.
-+ *
-+ * Some time may elapse before the core flushes any posted requests for this
-+ * host channel and halts. The Channel Halted interrupt handler completes the
-+ * deactivation of the host channel.
-+ *
-+ * @param core_if Controller register interface.
-+ * @param hc Host channel to halt.
-+ * @param halt_status Reason for halting the channel.
-+ */
-+void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
-+ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
-+{
-+ gnptxsts_data_t nptxsts;
-+ hptxsts_data_t hptxsts;
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ dwc_otg_core_global_regs_t *global_regs;
-+ dwc_otg_host_global_regs_t *host_global_regs;
-+
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ global_regs = core_if->core_global_regs;
-+ host_global_regs = core_if->host_if->host_global_regs;
-+
-+ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
-+ "halt_status = %d\n", halt_status);
-+
-+ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+ halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+ /*
-+ * Disable all channel interrupts except Ch Halted. The QTD
-+ * and QH state associated with this transfer has been cleared
-+ * (in the case of URB_DEQUEUE), so the channel needs to be
-+ * shut down carefully to prevent crashes.
-+ */
-+ hcintmsk_data_t hcintmsk;
-+ hcintmsk.d32 = 0;
-+ hcintmsk.b.chhltd = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
-+
-+ /*
-+ * Make sure no other interrupts besides halt are currently
-+ * pending. Handling another interrupt could cause a crash due
-+ * to the QTD and QH state.
-+ */
-+ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
-+
-+ /*
-+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
-+ * even if the channel was already halted for some other
-+ * reason.
-+ */
-+ hc->halt_status = halt_status;
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen == 0) {
-+ /*
-+ * The channel is either already halted or it hasn't
-+ * started yet. In DMA mode, the transfer may halt if
-+ * it finishes normally or a condition occurs that
-+ * requires driver intervention. Don't want to halt
-+ * the channel again. In either Slave or DMA mode,
-+ * it's possible that the transfer has been assigned
-+ * to a channel, but not started yet when an URB is
-+ * dequeued. Don't want to halt a channel that hasn't
-+ * started yet.
-+ */
-+ return;
-+ }
-+ }
-+ if (hc->halt_pending) {
-+ /*
-+ * A halt has already been issued for this channel. This might
-+ * happen when a transfer is aborted by a higher level in
-+ * the stack.
-+ */
-+#ifdef DEBUG
-+ DWC_PRINTF
-+ ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
-+ __func__, hc->hc_num);
-+
-+#endif
-+ return;
-+ }
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* No need to set the bit in DDMA for disabling the channel */
-+ //TODO check it everywhere channel is disabled
-+ if (!core_if->core_params->dma_desc_enable)
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 1;
-+
-+ if (!core_if->dma_enable) {
-+ /* Check for space in the request queue to issue the halt. */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ if (nptxsts.b.nptxqspcavail == 0) {
-+ hcchar.b.chen = 0;
-+ }
-+ } else {
-+ hptxsts.d32 =
-+ DWC_READ_REG32(&host_global_regs->hptxsts);
-+ if ((hptxsts.b.ptxqspcavail == 0)
-+ || (core_if->queuing_high_bandwidth)) {
-+ hcchar.b.chen = 0;
-+ }
-+ }
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->halt_status = halt_status;
-+
-+ if (hcchar.b.chen) {
-+ hc->halt_pending = 1;
-+ hc->halt_on_queue = 0;
-+ } else {
-+ hc->halt_on_queue = 1;
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
-+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
-+
-+ return;
-+}
-+
-+/**
-+ * Clears the transfer state for a host channel. This function is normally
-+ * called after a transfer is done and the host channel is being released.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to clean up.
-+ */
-+void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ dwc_otg_hc_regs_t *hc_regs;
-+
-+ hc->xfer_started = 0;
-+
-+ /*
-+ * Clear channel interrupt enables and any unhandled channel interrupt
-+ * conditions.
-+ */
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
-+ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
-+#ifdef DEBUG
-+ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
-+#endif
-+}
-+
-+/**
-+ * Sets the channel property that indicates in which frame a periodic transfer
-+ * should occur. This is always set to the _next_ frame. This function has no
-+ * effect on non-periodic transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to set up and its properties.
-+ * @param hcchar Current value of the HCCHAR register for the specified host
-+ * channel.
-+ */
-+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
-+ dwc_hc_t * hc, hcchar_data_t * hcchar)
-+{
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ hfnum_data_t hfnum;
-+ hfnum.d32 =
-+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
-+
-+ /* 1 if _next_ frame is odd, 0 if it's even */
-+ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
-+#ifdef DEBUG
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
-+ && !hc->complete_split) {
-+ switch (hfnum.b.frnum & 0x7) {
-+ case 7:
-+ core_if->hfnum_7_samples++;
-+ core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
-+ break;
-+ case 0:
-+ core_if->hfnum_0_samples++;
-+ core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
-+ break;
-+ default:
-+ core_if->hfnum_other_samples++;
-+ core_if->hfnum_other_frrem_accum +=
-+ hfnum.b.frrem;
-+ break;
-+ }
-+ }
-+#endif
-+ }
-+}
-+
-+#ifdef DEBUG
-+void hc_xfer_timeout(void *ptr)
-+{
-+ hc_xfer_info_t *xfer_info = NULL;
-+ int hc_num = 0;
-+
-+ if (ptr)
-+ xfer_info = (hc_xfer_info_t *) ptr;
-+
-+ if (!xfer_info->hc) {
-+ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
-+ return;
-+ }
-+
-+ hc_num = xfer_info->hc->hc_num;
-+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
-+ DWC_WARN(" start_hcchar_val 0x%08x\n",
-+ xfer_info->core_if->start_hcchar_val[hc_num]);
-+}
-+#endif
-+
-+void ep_xfer_timeout(void *ptr)
-+{
-+ ep_xfer_info_t *xfer_info = NULL;
-+ int ep_num = 0;
-+ dctl_data_t dctl = {.d32 = 0 };
-+ gintsts_data_t gintsts = {.d32 = 0 };
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+ if (ptr)
-+ xfer_info = (ep_xfer_info_t *) ptr;
-+
-+ if (!xfer_info->ep) {
-+ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
-+ return;
-+ }
-+
-+ ep_num = xfer_info->ep->num;
-+ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
-+ /* Put the sate to 2 as it was time outed */
-+ xfer_info->state = 2;
-+
-+ dctl.d32 =
-+ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
-+ gintsts.d32 =
-+ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
-+ gintmsk.d32 =
-+ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
-+
-+ if (!gintmsk.b.goutnakeff) {
-+ /* Unmask it */
-+ gintmsk.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
-+ gintmsk.d32);
-+
-+ }
-+
-+ if (!gintsts.b.goutnakeff) {
-+ dctl.b.sgoutnak = 1;
-+ }
-+ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+
-+}
-+
-+void set_pid_isoc(dwc_hc_t * hc)
-+{
-+ /* Set up the initial PID for the transfer. */
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ if (hc->ep_is_in) {
-+ if (hc->multi_count == 1) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ } else if (hc->multi_count == 2) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+ } else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
-+ }
-+ } else {
-+ if (hc->multi_count == 1) {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ } else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
-+ }
-+ }
-+ } else {
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for a host channel and
-+ * starts the transfer. May be called in either Slave mode or DMA mode. In
-+ * Slave mode, the caller must ensure that there is sufficient space in the
-+ * request queue and Tx Data FIFO.
-+ *
-+ * For an OUT transfer in Slave mode, it loads a data packet into the
-+ * appropriate FIFO. If necessary, additional data packets will be loaded in
-+ * the Host ISR.
-+ *
-+ * For an IN transfer in Slave mode, a data packet is requested. The data
-+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
-+ * additional data packets are requested in the Host ISR.
-+ *
-+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
-+ * register along with a packet count of 1 and the channel is enabled. This
-+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
-+ * simply set to 0 since no data transfer occurs in this case.
-+ *
-+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
-+ * all the information required to perform the subsequent data transfer. In
-+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
-+ * controller performs the entire PING protocol, then starts the data
-+ * transfer.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel. The xfer_len
-+ * value may be reduced to accommodate the max widths of the XferSize and
-+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
-+ * to reflect the final xfer_len value.
-+ */
-+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ uint16_t num_packets;
-+ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
-+ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ hctsiz.d32 = 0;
-+
-+ if (hc->do_ping) {
-+ if (!core_if->dma_enable) {
-+ dwc_otg_hc_do_ping(core_if, hc);
-+ hc->xfer_started = 1;
-+ return;
-+ } else {
-+ hctsiz.b.dopng = 1;
-+ }
-+ }
-+
-+ if (hc->do_split) {
-+ num_packets = 1;
-+
-+ if (hc->complete_split && !hc->ep_is_in) {
-+ /* For CSPLIT OUT Transfer, set the size to 0 so the
-+ * core doesn't expect any data written to the FIFO */
-+ hc->xfer_len = 0;
-+ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+ hc->xfer_len = hc->max_packet;
-+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+ hc->xfer_len = 188;
-+ }
-+
-+ hctsiz.b.xfersize = hc->xfer_len;
-+ } else {
-+ /*
-+ * Ensure that the transfer length and packet count will fit
-+ * in the widths allocated for them in the HCTSIZn register.
-+ */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * Make sure the transfer size is no larger than one
-+ * (micro)frame's worth of data. (A check was done
-+ * when the periodic transfer was accepted to ensure
-+ * that a (micro)frame's worth of data can be
-+ * programmed into a channel.)
-+ */
-+ uint32_t max_periodic_len =
-+ hc->multi_count * hc->max_packet;
-+ if (hc->xfer_len > max_periodic_len) {
-+ hc->xfer_len = max_periodic_len;
-+ } else {
-+ }
-+ } else if (hc->xfer_len > max_hc_xfer_size) {
-+ /* Make sure that xfer_len is a multiple of max packet size. */
-+ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
-+ }
-+
-+ if (hc->xfer_len > 0) {
-+ num_packets =
-+ (hc->xfer_len + hc->max_packet -
-+ 1) / hc->max_packet;
-+ if (num_packets > max_hc_pkt_count) {
-+ num_packets = max_hc_pkt_count;
-+ hc->xfer_len = num_packets * hc->max_packet;
-+ }
-+ } else {
-+ /* Need 1 packet for transfer length of 0. */
-+ num_packets = 1;
-+ }
-+
-+ if (hc->ep_is_in) {
-+ /* Always program an integral # of max packets for IN transfers. */
-+ hc->xfer_len = num_packets * hc->max_packet;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * Make sure that the multi_count field matches the
-+ * actual transfer length.
-+ */
-+ hc->multi_count = num_packets;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ set_pid_isoc(hc);
-+
-+ hctsiz.b.xfersize = hc->xfer_len;
-+ }
-+
-+ hc->start_pkt_count = num_packets;
-+ hctsiz.b.pktcnt = num_packets;
-+ hctsiz.b.pid = hc->data_pid_start;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
-+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
-+
-+ if (core_if->dma_enable) {
-+ dwc_dma_t dma_addr;
-+ if (hc->align_buff) {
-+ dma_addr = hc->align_buff;
-+ } else {
-+ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
-+ }
-+
-+ /* Start the split */
-+ if (hc->do_split) {
-+ hcsplt_data_t hcsplt;
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ hcsplt.b.spltena = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
-+ }
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.multicnt = hc->multi_count;
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+#ifdef DEBUG
-+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+ __func__, hc->hc_num, hcchar.d32);
-+ }
-+#endif
-+
-+ /* Set host channel enable after all other setup is complete. */
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->xfer_started = 1;
-+ hc->requests++;
-+
-+ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
-+ /* Load OUT packet into the appropriate Tx FIFO. */
-+ dwc_otg_hc_write_packet(core_if, hc);
-+ }
-+#ifdef DEBUG
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
-+ hc->hc_num, core_if);//GRAYG
-+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+ core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+
-+ /* Start a timer for this transfer. */
-+ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
-+ }
-+#endif
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for a host channel
-+ * and starts the transfer in Descriptor DMA mode.
-+ *
-+ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
-+ * Sets PID and NTD values. For periodic transfers
-+ * initializes SCHED_INFO field with micro-frame bitmap.
-+ *
-+ * Initializes HCDMA register with descriptor list address and CTD value
-+ * then starts the transfer via enabling the channel.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel.
-+ */
-+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ hcdma_data_t hcdma;
-+
-+ hctsiz.d32 = 0;
-+
-+ if (hc->do_ping)
-+ hctsiz.b_ddma.dopng = 1;
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ set_pid_isoc(hc);
-+
-+ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
-+ hctsiz.b_ddma.pid = hc->data_pid_start;
-+ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
-+ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
-+ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
-+
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ hcdma.d32 = 0;
-+ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
-+
-+ /* Always start from first descriptor. */
-+ hcdma.b.ctd = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.multicnt = hc->multi_count;
-+
-+#ifdef DEBUG
-+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+ __func__, hc->hc_num, hcchar.d32);
-+ }
-+#endif
-+
-+ /* Set host channel enable after all other setup is complete. */
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ hc->xfer_started = 1;
-+ hc->requests++;
-+
-+#ifdef DEBUG
-+ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
-+ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
-+ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
-+ hc->hc_num, core_if);//GRAYG
-+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+ core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+ /* Start a timer for this transfer. */
-+ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
-+ }
-+#endif
-+
-+}
-+
-+/**
-+ * This function continues a data transfer that was started by previous call
-+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
-+ * sufficient space in the request queue and Tx Data FIFO. This function
-+ * should only be called in Slave mode. In DMA mode, the controller acts
-+ * autonomously to complete transfers programmed to a host channel.
-+ *
-+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
-+ * if there is any data remaining to be queued. For an IN transfer, another
-+ * data packet is always requested. For the SETUP phase of a control transfer,
-+ * this function does nothing.
-+ *
-+ * @return 1 if a new request is queued, 0 if no more requests are required
-+ * for this transfer.
-+ */
-+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+ if (hc->do_split) {
-+ /* SPLITs always queue just once per channel */
-+ return 0;
-+ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+ /* SETUPs are queued only once since they can't be NAKed. */
-+ return 0;
-+ } else if (hc->ep_is_in) {
-+ /*
-+ * Always queue another request for other IN transfers. If
-+ * back-to-back INs are issued and NAKs are received for both,
-+ * the driver may still be processing the first NAK when the
-+ * second NAK is received. When the interrupt handler clears
-+ * the NAK interrupt for the first NAK, the second NAK will
-+ * not be seen. So we can't depend on the NAK interrupt
-+ * handler to requeue a NAKed request. Instead, IN requests
-+ * are issued each time this function is called. When the
-+ * transfer completes, the extra requests for the channel will
-+ * be flushed.
-+ */
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs =
-+ core_if->host_if->hc_regs[hc->hc_num];
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
-+ hcchar.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ hc->requests++;
-+ return 1;
-+ } else {
-+ /* OUT transfers. */
-+ if (hc->xfer_count < hc->xfer_len) {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ hcchar_data_t hcchar;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hc_set_even_odd_frame(core_if, hc, &hcchar);
-+ }
-+
-+ /* Load OUT packet into the appropriate Tx FIFO. */
-+ dwc_otg_hc_write_packet(core_if, hc);
-+ hc->requests++;
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+ }
-+}
-+
-+/**
-+ * Starts a PING transfer. This function should only be called in Slave mode.
-+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
-+ */
-+void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+ hctsiz.d32 = 0;
-+ hctsiz.b.dopng = 1;
-+ hctsiz.b.pktcnt = 1;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.chen = 1;
-+ hcchar.b.chdis = 0;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+}
-+
-+/*
-+ * This function writes a packet into the Tx FIFO associated with the Host
-+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
-+ * Tx FIFO is written. For a channel associated with a periodic EP, the
-+ * periodic Tx FIFO is written. This function should only be called in Slave
-+ * mode.
-+ *
-+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
-+ * then number of bytes written to the Tx FIFO.
-+ */
-+void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+ uint32_t i;
-+ uint32_t remaining_count;
-+ uint32_t byte_count;
-+ uint32_t dword_count;
-+
-+ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
-+ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
-+
-+ remaining_count = hc->xfer_len - hc->xfer_count;
-+ if (remaining_count > hc->max_packet) {
-+ byte_count = hc->max_packet;
-+ } else {
-+ byte_count = remaining_count;
-+ }
-+
-+ dword_count = (byte_count + 3) / 4;
-+
-+ if ((((unsigned long)data_buff) & 0x3) == 0) {
-+ /* xfer_buff is DWORD aligned. */
-+ for (i = 0; i < dword_count; i++, data_buff++) {
-+ DWC_WRITE_REG32(data_fifo, *data_buff);
-+ }
-+ } else {
-+ /* xfer_buff is not DWORD aligned. */
-+ for (i = 0; i < dword_count; i++, data_buff++) {
-+ uint32_t data;
-+ data =
-+ (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
-+ 16 | data_buff[3] << 24);
-+ DWC_WRITE_REG32(data_fifo, data);
-+ }
-+ }
-+
-+ hc->xfer_count += byte_count;
-+ hc->xfer_buff += byte_count;
-+}
-+
-+/**
-+ * Gets the current USB frame number. This is the frame number from the last
-+ * SOF packet.
-+ */
-+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ /* read current frame/microframe number from DSTS register */
-+ return dsts.b.soffn;
-+}
-+
-+/**
-+ * Calculates and gets the frame Interval value of HFIR register according PHY
-+ * type and speed.The application can modify a value of HFIR register only after
-+ * the Port Enable bit of the Host Port Control and Status register
-+ * (HPRT.PrtEnaPort) has been set.
-+*/
-+
-+uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
-+{
-+ gusbcfg_data_t usbcfg;
-+ hwcfg2_data_t hwcfg2;
-+ hprt0_data_t hprt0;
-+ int clock = 60; // default value
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
-+ clock = 60;
-+ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
-+ clock = 48;
-+ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
-+ clock = 30;
-+ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
-+ clock = 60;
-+ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
-+ clock = 48;
-+ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
-+ clock = 48;
-+ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
-+ clock = 48;
-+ if (hprt0.b.prtspd == 0)
-+ /* High speed case */
-+ return 125 * clock;
-+ else
-+ /* FS/LS case */
-+ return 1000 * clock;
-+}
-+
-+/**
-+ * This function reads a setup packet from the Rx FIFO into the destination
-+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
-+ * Interrupt routine when a SETUP packet has been received in Slave mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for packet data.
-+ */
-+void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
-+{
-+ device_grxsts_data_t status;
-+ /* Get the 8 bytes of a setup transaction data */
-+
-+ /* Pop 2 DWORDS off the receive data FIFO into memory */
-+ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
-+ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ status.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
-+ status.b.epnum, status.b.bcnt, status.b.pktsts,
-+ status.b.fn, status.b.fn);
-+ }
-+}
-+
-+/**
-+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
-+ * IN for transmitting packets. It is normally called when the
-+ * "Enumeration Done" interrupt occurs.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dsts_data_t dsts;
-+ depctl_data_t diepctl;
-+ depctl_data_t doepctl;
-+ dctl_data_t dctl = {.d32 = 0 };
-+
-+ ep->stp_rollover = 0;
-+ /* Read the Device Status and Endpoint 0 Control registers */
-+ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
-+
-+ /* Set the MPS of the IN EP based on the enumeration speed */
-+ switch (dsts.b.enumspd) {
-+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+ diepctl.b.mps = DWC_DEP0CTL_MPS_64;
-+ break;
-+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+ diepctl.b.mps = DWC_DEP0CTL_MPS_8;
-+ break;
-+ }
-+
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Enable OUT EP for receive */
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ doepctl.b.epena = 1;
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+ }
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+ dctl.b.cgnpinnak = 1;
-+
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
-+ DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
-+
-+}
-+
-+/**
-+ * This function activates an EP. The Device EP control register for
-+ * the EP is configured as defined in the ep structure. Note: This
-+ * function is not used for EP0.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to activate.
-+ */
-+void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ depctl_data_t depctl;
-+ volatile uint32_t *addr;
-+ daint_data_t daintmsk = {.d32 = 0 };
-+ dcfg_data_t dcfg;
-+ uint8_t i;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
-+ (ep->is_in ? "IN" : "OUT"));
-+
-+#ifdef DWC_UTE_PER_IO
-+ ep->xiso_frame_num = 0xFFFFFFFF;
-+ ep->xiso_active_xfers = 0;
-+ ep->xiso_queued_xfers = 0;
-+#endif
-+ /* Read DEPCTLn register */
-+ if (ep->is_in == 1) {
-+ addr = &dev_if->in_ep_regs[ep->num]->diepctl;
-+ daintmsk.ep.in = 1 << ep->num;
-+ } else {
-+ addr = &dev_if->out_ep_regs[ep->num]->doepctl;
-+ daintmsk.ep.out = 1 << ep->num;
-+ }
-+
-+ /* If the EP is already active don't change the EP Control
-+ * register. */
-+ depctl.d32 = DWC_READ_REG32(addr);
-+ if (!depctl.b.usbactep) {
-+ depctl.b.mps = ep->maxpacket;
-+ depctl.b.eptype = ep->type;
-+ depctl.b.txfnum = ep->tx_fifo_num;
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ depctl.b.setd0pid = 1; // ???
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ depctl.b.usbactep = 1;
-+
-+ /* Update nextep_seq array and EPMSCNT in DCFG*/
-+ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
-+ break;
-+ }
-+ core_if->nextep_seq[i] = ep->num;
-+ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt++;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV, "%2d\n",
-+ core_if->nextep_seq[i]);
-+ }
-+
-+ }
-+
-+
-+ DWC_WRITE_REG32(addr, depctl.d32);
-+ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
-+ }
-+
-+ /* Enable the Interrupt for this EP */
-+ if (core_if->multiproc_int_enable) {
-+ if (ep->is_in == 1) {
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ diepmsk.b.intknepmis = 1;
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+ diepmsk.b.intknepmis = 0;
-+ diepmsk.b.txfifoundrn = 1; //?????
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ diepmsk.b.nak = 1;
-+ }
-+
-+
-+
-+/*
-+ if (core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+*/
-+/*
-+ if (core_if->dma_enable) {
-+ doepmsk.b.nak = 1;
-+ }
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->
-+ diepeachintmsk[ep->num], diepmsk.d32);
-+
-+ } else {
-+ doepmsk_data_t doepmsk = {.d32 = 0 };
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
-+ doepmsk.b.outtknepdis = 1;
-+
-+/*
-+
-+ if (core_if->dma_desc_enable) {
-+ doepmsk.b.bna = 1;
-+ }
-+*/
-+/*
-+ doepmsk.b.babble = 1;
-+ doepmsk.b.nyet = 1;
-+ doepmsk.b.nak = 1;
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->
-+ doepeachintmsk[ep->num], doepmsk.d32);
-+ }
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
-+ 0, daintmsk.d32);
-+ } else {
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (ep->is_in) {
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.nak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
-+ } else {
-+ doepmsk_data_t doepmsk = {.d32 = 0 };
-+ doepmsk.b.outtknepdis = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
-+ }
-+ }
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
-+ 0, daintmsk.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
-+ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
-+
-+ ep->stall_clear_flag = 0;
-+
-+ return;
-+}
-+
-+/**
-+ * This function deactivates an EP. This is done by clearing the USB Active
-+ * EP bit in the Device EP control register. Note: This function is not used
-+ * for EP0. EP0 cannot be deactivated.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to deactivate.
-+ */
-+void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+ daint_data_t daintmsk = {.d32 = 0 };
-+ dcfg_data_t dcfg;
-+ uint8_t i = 0;
-+
-+#ifdef DWC_UTE_PER_IO
-+ ep->xiso_frame_num = 0xFFFFFFFF;
-+ ep->xiso_active_xfers = 0;
-+ ep->xiso_queued_xfers = 0;
-+#endif
-+
-+ /* Read DEPCTLn register */
-+ if (ep->is_in == 1) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ daintmsk.ep.in = 1 << ep->num;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ daintmsk.ep.out = 1 << ep->num;
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(addr);
-+
-+ depctl.b.usbactep = 0;
-+
-+ /* Update nextep_seq array and EPMSCNT in DCFG*/
-+ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ if (core_if->nextep_seq[i] == ep->num)
-+ break;
-+ }
-+ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
-+ if (core_if->first_in_nextep_seq == ep->num)
-+ core_if->first_in_nextep_seq = i;
-+ core_if->nextep_seq[ep->num] = 0xff;
-+ depctl.b.nextep = 0;
-+ dcfg.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt--;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+ dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
-+ }
-+ }
-+
-+ if (ep->is_in == 1)
-+ depctl.b.txfnum = 0;
-+
-+ if (core_if->dma_desc_enable)
-+ depctl.b.epdis = 1;
-+
-+ DWC_WRITE_REG32(addr, depctl.d32);
-+ depctl.d32 = DWC_READ_REG32(addr);
-+ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
-+ && depctl.b.epena) {
-+ depctl_data_t depctl = {.d32 = 0};
-+ if (ep->is_in) {
-+ diepint_data_t diepint = {.d32 = 0};
-+
-+ depctl.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepctl, depctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->in_ep_regs[ep->num]->
-+ diepint);
-+ } while (!diepint.b.inepnakeff);
-+ diepint.b.inepnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepint, diepint.d32);
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepctl, depctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->in_ep_regs[ep->num]->
-+ diepint);
-+ } while (!diepint.b.epdisabled);
-+ diepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ diepint, diepint.d32);
-+ } else {
-+ dctl_data_t dctl = {.d32 = 0};
-+ gintmsk_data_t gintsts = {.d32 = 0};
-+ doepint_data_t doepint = {.d32 = 0};
-+ dctl.b.sgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, 0, dctl.d32);
-+ do {
-+ dwc_udelay(10);
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ } while (!gintsts.b.goutnakeff);
-+ gintsts.d32 = 0;
-+ gintsts.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ depctl.d32 = 0;
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
-+ do
-+ {
-+ dwc_udelay(10);
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->num]->doepint);
-+ } while (!doepint.b.epdisabled);
-+
-+ doepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
-+
-+ dctl.d32 = 0;
-+ dctl.b.cgoutnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ }
-+ }
-+
-+ /* Disable the Interrupt for this EP */
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+ daintmsk.d32, 0);
-+
-+ if (ep->is_in == 1) {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ diepeachintmsk[ep->num], 0);
-+ } else {
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[ep->num], 0);
-+ }
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
-+ daintmsk.d32, 0);
-+ }
-+
-+}
-+
-+/**
-+ * This function initializes dma descriptor chain.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ uint32_t offset;
-+ uint32_t xfer_est;
-+ int i;
-+ unsigned maxxfer_local, total_len;
-+
-+ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
-+ (ep->maxpacket%4)) {
-+ maxxfer_local = ep->maxpacket;
-+ total_len = ep->xfer_len;
-+ } else {
-+ maxxfer_local = ep->maxxfer;
-+ total_len = ep->total_len;
-+ }
-+
-+ ep->desc_cnt = (total_len / maxxfer_local) +
-+ ((total_len % maxxfer_local) ? 1 : 0);
-+
-+ if (!ep->desc_cnt)
-+ ep->desc_cnt = 1;
-+
-+ if (ep->desc_cnt > MAX_DMA_DESC_CNT)
-+ ep->desc_cnt = MAX_DMA_DESC_CNT;
-+
-+ dma_desc = ep->desc_addr;
-+ if (maxxfer_local == ep->maxpacket) {
-+ if ((total_len % maxxfer_local) &&
-+ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
-+ xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
-+ (total_len % maxxfer_local);
-+ } else
-+ xfer_est = ep->desc_cnt * maxxfer_local;
-+ } else
-+ xfer_est = total_len;
-+ offset = 0;
-+ for (i = 0; i < ep->desc_cnt; ++i) {
-+ /** DMA Descriptor Setup */
-+ if (xfer_est > maxxfer_local) {
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 0;
-+ dma_desc->status.b.ioc = 0;
-+ dma_desc->status.b.sp = 0;
-+ dma_desc->status.b.bytes = maxxfer_local;
-+ dma_desc->buf = ep->dma_addr + offset;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ xfer_est -= maxxfer_local;
-+ offset += maxxfer_local;
-+ } else {
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ if (ep->is_in) {
-+ dma_desc->status.b.sp =
-+ (xfer_est %
-+ ep->maxpacket) ? 1 : ((ep->
-+ sent_zlp) ? 1 : 0);
-+ dma_desc->status.b.bytes = xfer_est;
-+ } else {
-+ if (maxxfer_local == ep->maxpacket)
-+ dma_desc->status.b.bytes = xfer_est;
-+ else
-+ dma_desc->status.b.bytes =
-+ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
-+ }
-+
-+ dma_desc->buf = ep->dma_addr + offset;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+ }
-+ dma_desc++;
-+ }
-+}
-+/**
-+ * This function is called when to write ISOC data into appropriate dedicated
-+ * periodic FIFO.
-+ */
-+static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0 };
-+ uint32_t len = 0;
-+ int epnum = dwc_ep->num;
-+ int dwords;
-+
-+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+ len = dwc_ep->xfer_len - dwc_ep->xfer_count;
-+
-+ if (len > dwc_ep->maxpacket) {
-+ len = dwc_ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
-+
-+ len = dwc_ep->xfer_len - dwc_ep->xfer_count;
-+ if (len > dwc_ep->maxpacket) {
-+ len = dwc_ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
-+ txstatus.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
-+
-+ return 1;
-+}
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
-+ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
-+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
-+ ep->total_len);
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[ep->num];
-+
-+ gnptxsts_data_t gtxstatus;
-+
-+ gtxstatus.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+
-+ if (core_if->en_multiple_tx_fifo == 0
-+ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
-+#ifdef DEBUG
-+ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
-+#endif
-+ return;
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
-+
-+ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
-+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+ ep->maxxfer : (ep->total_len - ep->xfer_len);
-+ else
-+ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
-+ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-+
-+
-+ /* Zero Length Packet? */
-+ if ((ep->xfer_len - ep->xfer_count) == 0) {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+ } else {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - ep->xfer_count - 1 +
-+ ep->maxpacket) / ep->maxpacket;
-+ if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
-+ deptsiz.b.pktcnt = MAX_PKT_CNT;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+ }
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC)
-+ deptsiz.b.mc = deptsiz.b.pktcnt;
-+ }
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ if (ep->type != DWC_OTG_EP_TYPE_ISOC)
-+ deptsiz.b.mc = 1;
-+ DWC_WRITE_REG32(&in_regs->dieptsiz,
-+ deptsiz.d32);
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+#ifdef DWC_UTE_CFI
-+ /* The descriptor chain should be already initialized by now */
-+ if (ep->buff_mode != BM_STANDARD) {
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ ep->descs_dma_addr);
-+ } else {
-+#endif
-+ init_dma_desc_chain(core_if, ep);
-+ /** DIEPDMAn Register write */
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ ep->dma_desc_addr);
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt,
-+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+ * the data will be written into the fifo by the ISR.
-+ */
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32
-+ (&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk = 1 << ep->num;
-+ DWC_MODIFY_REG32
-+ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+
-+ }
-+ }
-+ } else {
-+ write_isoc_tx_fifo(core_if, ep);
-+ }
-+ }
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ dsts_data_t dsts = {.d32 = 0};
-+ if (ep->bInterval == 1) {
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dsts);
-+ ep->frame_num = dsts.b.soffn + ep->bInterval;
-+ if (ep->frame_num > 0x3FFF) {
-+ ep->frm_overrun = 1;
-+ ep->frame_num &= 0x3FFF;
-+ } else
-+ ep->frm_overrun = 0;
-+ if (ep->frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ }
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ } else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[ep->num];
-+
-+ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
-+
-+ if (!core_if->dma_desc_enable) {
-+ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
-+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+ ep->maxxfer : (ep->total_len - ep->xfer_len);
-+ else
-+ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
-+ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-+ }
-+
-+ /* Program the transfer size and packet count as follows:
-+ *
-+ * pktcnt = N
-+ * xfersize = N * maxpacket
-+ */
-+ if ((ep->xfer_len - ep->xfer_count) == 0) {
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - ep->xfer_count +
-+ (ep->maxpacket - 1)) / ep->maxpacket;
-+ if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
-+ deptsiz.b.pktcnt = MAX_PKT_CNT;
-+ }
-+ if (!core_if->dma_desc_enable) {
-+ ep->xfer_len =
-+ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
-+ }
-+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
-+ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+#ifdef DWC_UTE_CFI
-+ /* The descriptor chain should be already initialized by now */
-+ if (ep->buff_mode != BM_STANDARD) {
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ ep->descs_dma_addr);
-+ } else {
-+#endif
-+ /** This is used for interrupt out transfers*/
-+ if (!ep->xfer_len)
-+ ep->xfer_len = ep->total_len;
-+ init_dma_desc_chain(core_if, ep);
-+
-+ if (core_if->core_params->dev_out_nak) {
-+ if (ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ deptsiz.b.pktcnt = (ep->total_len +
-+ (ep->maxpacket - 1)) / ep->maxpacket;
-+ deptsiz.b.xfersize = ep->total_len;
-+ /* Remember initial value of doeptsiz */
-+ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+ }
-+ }
-+ /** DOEPDMAn Register write */
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ ep->dma_desc_addr);
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ dsts_data_t dsts = {.d32 = 0};
-+ if (ep->bInterval == 1) {
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dsts);
-+ ep->frame_num = dsts.b.soffn + ep->bInterval;
-+ if (ep->frame_num > 0x3FFF) {
-+ ep->frm_overrun = 1;
-+ ep->frame_num &= 0x3FFF;
-+ } else
-+ ep->frm_overrun = 0;
-+
-+ if (ep->frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+
-+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
-+ DWC_READ_REG32(&out_regs->doepctl),
-+ DWC_READ_REG32(&out_regs->doeptsiz));
-+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
-+ daintmsk),
-+ DWC_READ_REG32(&core_if->core_global_regs->
-+ gintmsk));
-+
-+ /* Timer is scheduling only for out bulk transfers for
-+ * "Device DDMA OUT NAK Enhancement" feature to inform user
-+ * about received data payload in case of timeout
-+ */
-+ if (core_if->core_params->dev_out_nak) {
-+ if (ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ core_if->ep_xfer_info[ep->num].core_if = core_if;
-+ core_if->ep_xfer_info[ep->num].ep = ep;
-+ core_if->ep_xfer_info[ep->num].state = 1;
-+
-+ /* Start a timer for this transfer. */
-+ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * This function setup a zero length transfer in Buffer DMA and
-+ * Slave modes for usb requests with zero field set
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+
-+ depctl_data_t depctl;
-+ deptsiz_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+ DWC_PRINTF("zero length transfer is called\n");
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[ep->num];
-+
-+ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
-+
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.b.mc = 1;
-+ DWC_WRITE_REG32(&in_regs->dieptsiz,
-+ deptsiz.d32);
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt,
-+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+ * the data will be written into the fifo by the ISR.
-+ */
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk = 1 << ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ } else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[ep->num];
-+
-+ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
-+ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
-+
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+
-+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for EP0 and starts
-+ * the transfer. For an IN transfer, the packets will be loaded into
-+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
-+ * unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz0_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+
-+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+ "xfer_buff=%p start_xfer_buff=%p \n",
-+ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
-+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
-+
-+ ep->total_len = ep->xfer_len;
-+
-+ /* IN endpoint */
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[0];
-+
-+ gnptxsts_data_t gtxstatus;
-+
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+ if (depctl.b.epena)
-+ return;
-+ }
-+
-+ gtxstatus.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+
-+ /* If dedicated FIFO every time flush fifo before enable ep*/
-+ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
-+
-+ if (core_if->en_multiple_tx_fifo == 0
-+ && gtxstatus.b.nptxqspcavail == 0
-+ && !core_if->dma_enable) {
-+#ifdef DEBUG
-+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
-+ DWC_READ_REG32(&in_regs->diepctl));
-+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
-+ deptsiz.d32,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
-+ gtxstatus.d32);
-+#endif
-+ return;
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+
-+ /* Zero Length Packet? */
-+ if (ep->xfer_len == 0) {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 1;
-+ } else {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ if (ep->xfer_len > ep->maxpacket) {
-+ ep->xfer_len = ep->maxpacket;
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ } else {
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ }
-+ deptsiz.b.pktcnt = 1;
-+
-+ }
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+ dma_desc = core_if->dev_if->in_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.sp =
-+ (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+ dma_desc->status.b.bytes = ep->xfer_len;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DIEPDMA0 Register write */
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ core_if->
-+ dev_if->dma_in_desc_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ }
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+ * data will be written into the fifo by the ISR.
-+ */
-+ if (!core_if->dma_enable) {
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk |= 1 << ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+ } else {
-+ /* OUT endpoint */
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[0];
-+
-+ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
-+
-+ /* Program the transfer size and packet count as follows:
-+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
-+ * pktcnt = N */
-+ /* Zero Length Packet */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ deptsiz.b.supcnt = 3;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz,
-+ deptsiz.d32);
-+
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ } else {
-+ dma_desc = core_if->dev_if->out_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ dma_desc->status.b.mtrf = 0;
-+ dma_desc->status.b.sr = 0;
-+ }
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = ep->maxpacket;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ core_if->dev_if->
-+ dma_out_desc_addr);
-+ }
-+ } else {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ }
-+
-+ /* EP enable */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function continues control IN transfers started by
-+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
-+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
-+ * bit for the packet count.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ deptsiz0_data_t deptsiz;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+
-+ if (ep->is_in == 1) {
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[0];
-+ gnptxsts_data_t tx_status = {.d32 = 0 };
-+
-+ tx_status.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+ /** @todo Should there be check for room in the Tx
-+ * Status Queue. If not remove the code above this comment. */
-+
-+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.b.xfersize =
-+ (ep->total_len - ep->xfer_count) >
-+ ep->maxpacket ? ep->maxpacket : (ep->total_len -
-+ ep->xfer_count);
-+ deptsiz.b.pktcnt = 1;
-+ if (core_if->dma_enable == 0) {
-+ ep->xfer_len += deptsiz.b.xfersize;
-+ } else {
-+ ep->xfer_len = deptsiz.b.xfersize;
-+ }
-+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+ } else {
-+ ep->xfer_len =
-+ (ep->total_len - ep->xfer_count) >
-+ ep->maxpacket ? ep->maxpacket : (ep->total_len -
-+ ep->xfer_count);
-+
-+ dma_desc = core_if->dev_if->in_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.sp =
-+ (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+ dma_desc->status.b.bytes = ep->xfer_len;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DIEPDMA0 Register write */
-+ DWC_WRITE_REG32(&in_regs->diepdma,
-+ core_if->dev_if->dma_in_desc_addr);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+ if (core_if->dma_desc_enable == 0)
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+ depctl.b.nextep = core_if->nextep_seq[ep->num];
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+ /**
-+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+ * data will be written into the fifo by the ISR.
-+ */
-+ if (!core_if->dma_enable) {
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ /* First clear it from GINTSTS */
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gintmsk,
-+ intr_mask.d32, intr_mask.d32);
-+
-+ } else {
-+ /* Enable the Tx FIFO Empty Interrupt for this EP */
-+ if (ep->xfer_len > 0) {
-+ uint32_t fifoemptymsk = 0;
-+ fifoemptymsk |= 1 << ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ 0, fifoemptymsk);
-+ }
-+ }
-+ }
-+ } else {
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[0];
-+
-+ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
-+ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
-+
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->maxpacket;
-+ deptsiz.b.pktcnt = 1;
-+
-+ if (core_if->dma_desc_enable == 0) {
-+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+ } else {
-+ dma_desc = core_if->dev_if->out_desc_addr;
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = ep->maxpacket;
-+ dma_desc->buf = ep->dma_addr;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ DWC_WRITE_REG32(&out_regs->doepdma,
-+ core_if->dev_if->dma_out_desc_addr);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
-+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+ if (core_if->dma_desc_enable == 0)
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) ep->dma_addr);
-+
-+ }
-+
-+ /* EP enable, IN data in FIFO */
-+ depctl.b.cnak = 1;
-+ depctl.b.epena = 1;
-+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+ }
-+}
-+
-+#ifdef DEBUG
-+void dump_msg(const u8 * buf, unsigned int length)
-+{
-+ unsigned int start, num, i;
-+ char line[52], *p;
-+
-+ if (length >= 512)
-+ return;
-+ start = 0;
-+ while (length > 0) {
-+ num = length < 16u ? length : 16u;
-+ p = line;
-+ for (i = 0; i < num; ++i) {
-+ if (i == 8)
-+ *p++ = ' ';
-+ DWC_SPRINTF(p, " %02x", buf[i]);
-+ p += 3;
-+ }
-+ *p = 0;
-+ DWC_PRINTF("%6x: %s\n", start, line);
-+ buf += num;
-+ start += num;
-+ length -= num;
-+ }
-+}
-+#else
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function writes a packet into the Tx FIFO associated with the
-+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
-+ * periodic EPs the periodic Tx FIFO associated with the EP is written
-+ * with all packets for the next micro-frame.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to write packet for.
-+ * @param dma Indicates if DMA is being used.
-+ */
-+void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
-+ int dma)
-+{
-+ /**
-+ * The buffer is padded to DWORD on a per packet basis in
-+ * slave/dma mode if the MPS is not DWORD aligned. The last
-+ * packet, if short, is also padded to a multiple of DWORD.
-+ *
-+ * ep->xfer_buff always starts DWORD aligned in memory and is a
-+ * multiple of DWORD in length
-+ *
-+ * ep->xfer_len can be any number of bytes
-+ *
-+ * ep->xfer_count is a multiple of ep->maxpacket until the last
-+ * packet
-+ *
-+ * FIFO access is DWORD */
-+
-+ uint32_t i;
-+ uint32_t byte_count;
-+ uint32_t dword_count;
-+ uint32_t *fifo;
-+ uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
-+ ep);
-+ if (ep->xfer_count >= ep->xfer_len) {
-+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
-+ return;
-+ }
-+
-+ /* Find the byte length of the packet either short packet or MPS */
-+ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
-+ byte_count = ep->xfer_len - ep->xfer_count;
-+ } else {
-+ byte_count = ep->maxpacket;
-+ }
-+
-+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS
-+ * is not a multiple of DWORD */
-+ dword_count = (byte_count + 3) / 4;
-+
-+#ifdef VERBOSE
-+ dump_msg(ep->xfer_buff, byte_count);
-+#endif
-+
-+ /**@todo NGS Where are the Periodic Tx FIFO addresses
-+ * intialized? What should this be? */
-+
-+ fifo = core_if->data_fifo[ep->num];
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
-+ fifo, data_buff, *data_buff, byte_count);
-+
-+ if (!dma) {
-+ for (i = 0; i < dword_count; i++, data_buff++) {
-+ DWC_WRITE_REG32(fifo, *data_buff);
-+ }
-+ }
-+
-+ ep->xfer_count += byte_count;
-+ ep->xfer_buff += byte_count;
-+ ep->dma_addr += byte_count;
-+}
-+
-+/**
-+ * Set the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to set the stall on.
-+ */
-+void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ volatile uint32_t *depctl_addr;
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in ? "IN" : "OUT"));
-+
-+ if (ep->is_in == 1) {
-+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+ depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+ /* set the disable and stall bits */
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ }
-+ depctl.b.stall = 1;
-+ DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+ } else {
-+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+ depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+ /* set the stall bit */
-+ depctl.b.stall = 1;
-+ DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
-+
-+ return;
-+}
-+
-+/**
-+ * Clear the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to clear stall from.
-+ */
-+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl;
-+ volatile uint32_t *depctl_addr;
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+ (ep->is_in ? "IN" : "OUT"));
-+
-+ if (ep->is_in == 1) {
-+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+ } else {
-+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+ }
-+
-+ depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+ /* clear the stall bits */
-+ depctl.b.stall = 0;
-+
-+ /*
-+ * USB Spec 9.4.5: For endpoints using data toggle, regardless
-+ * of whether an endpoint has the Halt feature set, a
-+ * ClearFeature(ENDPOINT_HALT) request always results in the
-+ * data toggle being reinitialized to DATA0.
-+ */
-+ if (ep->type == DWC_OTG_EP_TYPE_INTR ||
-+ ep->type == DWC_OTG_EP_TYPE_BULK) {
-+ depctl.b.setd0pid = 1; /* DATA0 */
-+ }
-+
-+ DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
-+ return;
-+}
-+
-+/**
-+ * This function reads a packet from the Rx FIFO into the destination
-+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for the packet.
-+ * @param bytes Number of bytes to copy to the destination.
-+ */
-+void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
-+ uint8_t * dest, uint16_t bytes)
-+{
-+ int i;
-+ int word_count = (bytes + 3) / 4;
-+
-+ volatile uint32_t *fifo = core_if->data_fifo[0];
-+ uint32_t *data_buff = (uint32_t *) dest;
-+
-+ /**
-+ * @todo Account for the case where _dest is not dword aligned. This
-+ * requires reading data from the FIFO into a uint32_t temp buffer,
-+ * then moving it into the data buffer.
-+ */
-+
-+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
-+ core_if, dest, bytes);
-+
-+ for (i = 0; i < word_count; i++, data_buff++) {
-+ *data_buff = DWC_READ_REG32(fifo);
-+ }
-+
-+ return;
-+}
-+
-+/**
-+ * This functions reads the device registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINTF("Device Global Registers\n");
-+ addr = &core_if->dev_if->dev_global_regs->dcfg;
-+ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->dctl;
-+ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->dsts;
-+ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->diepmsk;
-+ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->doepmsk;
-+ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->daint;
-+ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->daintmsk;
-+ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr1;
-+ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr2;
-+ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ addr = &core_if->dev_if->dev_global_regs->dvbusdis;
-+ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
-+ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
-+ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+ if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ if (core_if->hwcfg2.b.multi_proc_int) {
-+
-+ addr = &core_if->dev_if->dev_global_regs->deachint;
-+ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->dev_global_regs->deachintmsk;
-+ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ addr =
-+ &core_if->dev_if->
-+ dev_global_regs->diepeachintmsk[i];
-+ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
-+ i, (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ }
-+
-+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+ addr =
-+ &core_if->dev_if->
-+ dev_global_regs->doepeachintmsk[i];
-+ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
-+ i, (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ }
-+ }
-+
-+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_PRINTF("Device IN EP %d Registers\n", i);
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
-+ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepint;
-+ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
-+ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
-+ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
-+ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
-+ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
-+ }
-+
-+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+ DWC_PRINTF("Device OUT EP %d Registers\n", i);
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
-+ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepint;
-+ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
-+ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
-+ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
-+ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
-+ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ }
-+}
-+
-+/**
-+ * This functions reads the SPRAM and prints its content
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
-+{
-+ volatile uint8_t *addr, *start_addr, *end_addr;
-+
-+ DWC_PRINTF("SPRAM Data:\n");
-+ start_addr = (void *)core_if->core_global_regs;
-+ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
-+ start_addr += 0x00028000;
-+ end_addr = (void *)core_if->core_global_regs;
-+ end_addr += 0x000280e0;
-+
-+ for (addr = start_addr; addr < end_addr; addr += 16) {
-+ DWC_PRINTF
-+ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
-+ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
-+ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
-+ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
-+ );
-+ }
-+
-+ return;
-+}
-+
-+/**
-+ * This function reads the host registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ volatile uint32_t *addr;
-+
-+ DWC_PRINTF("Host Global Registers\n");
-+ addr = &core_if->host_if->host_global_regs->hcfg;
-+ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->hfir;
-+ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->hfnum;
-+ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->hptxsts;
-+ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->haint;
-+ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->host_global_regs->haintmsk;
-+ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ if (core_if->dma_desc_enable) {
-+ addr = &core_if->host_if->host_global_regs->hflbaddr;
-+ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ addr = core_if->host_if->hprt0;
-+ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ for (i = 0; i < core_if->core_params->host_channels; i++) {
-+ DWC_PRINTF("Host Channel %d Specific Registers\n", i);
-+ addr = &core_if->host_if->hc_regs[i]->hcchar;
-+ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcsplt;
-+ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcint;
-+ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcintmsk;
-+ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hctsiz;
-+ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->host_if->hc_regs[i]->hcdma;
-+ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ if (core_if->dma_desc_enable) {
-+ addr = &core_if->host_if->hc_regs[i]->hcdmab;
-+ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+
-+ }
-+ return;
-+}
-+
-+/**
-+ * This function reads the core global registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
-+{
-+ int i, ep_num;
-+ volatile uint32_t *addr;
-+ char *txfsiz;
-+
-+ DWC_PRINTF("Core Global Registers\n");
-+ addr = &core_if->core_global_regs->gotgctl;
-+ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gotgint;
-+ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gahbcfg;
-+ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gusbcfg;
-+ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->grstctl;
-+ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gintsts;
-+ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gintmsk;
-+ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->grxstsr;
-+ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->grxfsiz;
-+ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gnptxfsiz;
-+ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gnptxsts;
-+ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gi2cctl;
-+ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gpvndctl;
-+ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ggpio;
-+ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->guid;
-+ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gsnpsid;
-+ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg1;
-+ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg2;
-+ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg3;
-+ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->ghwcfg4;
-+ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->glpmcfg;
-+ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gpwrdn;
-+ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->gdfifocfg;
-+ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+ addr = &core_if->core_global_regs->adpctl;
-+ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ dwc_otg_adp_read_reg(core_if));
-+ addr = &core_if->core_global_regs->hptxfsiz;
-+ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
-+ txfsiz = "DPTXFSIZ";
-+ } else {
-+ ep_num = core_if->hwcfg4.b.num_in_eps;
-+ txfsiz = "DIENPTXF";
-+ }
-+ for (i = 0; i < ep_num; i++) {
-+ addr = &core_if->core_global_regs->dtxfsiz[i];
-+ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
-+ (unsigned long)addr, DWC_READ_REG32(addr));
-+ }
-+ addr = core_if->pcgcctl;
-+ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+ DWC_READ_REG32(addr));
-+}
-+
-+/**
-+ * Flush a Tx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param num Tx FIFO to flush.
-+ */
-+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = {.d32 = 0 };
-+ int count = 0;
-+
-+ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
-+
-+ greset.b.txfflsh = 1;
-+ greset.b.txfnum = num;
-+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+
-+ do {
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
-+ __func__, greset.d32,
-+ DWC_READ_REG32(&global_regs->gnptxsts));
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (greset.b.txfflsh == 1);
-+
-+ /* Wait for 3 PHY Clocks */
-+ dwc_udelay(1);
-+}
-+
-+/**
-+ * Flush Rx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = {.d32 = 0 };
-+ int count = 0;
-+
-+ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
-+ /*
-+ *
-+ */
-+ greset.b.rxfflsh = 1;
-+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+
-+ do {
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (greset.b.rxfflsh == 1);
-+
-+ /* Wait for 3 PHY Clocks */
-+ dwc_udelay(1);
-+}
-+
-+/**
-+ * Do core a soft reset of the core. Be careful with this because it
-+ * resets all the internal state machines of the core.
-+ */
-+void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ volatile grstctl_t greset = {.d32 = 0 };
-+ int count = 0;
-+
-+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
-+ /* Wait for AHB master IDLE state. */
-+ do {
-+ dwc_udelay(10);
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 100000) {
-+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
-+ greset.d32);
-+ return;
-+ }
-+ }
-+ while (greset.b.ahbidle == 0);
-+
-+ /* Core Soft Reset */
-+ count = 0;
-+ greset.b.csftrst = 1;
-+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+ do {
-+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+ if (++count > 10000) {
-+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
-+ __func__, greset.d32);
-+ break;
-+ }
-+ dwc_udelay(1);
-+ }
-+ while (greset.b.csftrst == 1);
-+
-+ /* Wait for 3 PHY Clocks */
-+ dwc_mdelay(100);
-+}
-+
-+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
-+{
-+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
-+}
-+
-+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
-+{
-+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
-+}
-+
-+/**
-+ * Register HCD callbacks. The callbacks are used to start and stop
-+ * the HCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the HCD callback structure.
-+ * @param p pointer to be passed to callback function (usb_hcd*).
-+ */
-+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
-+ dwc_otg_cil_callbacks_t * cb, void *p)
-+{
-+ core_if->hcd_cb = cb;
-+ cb->p = p;
-+}
-+
-+/**
-+ * Register PCD callbacks. The callbacks are used to start and stop
-+ * the PCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the PCD callback structure.
-+ * @param p pointer to be passed to callback function (pcd*).
-+ */
-+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
-+ dwc_otg_cil_callbacks_t * cb, void *p)
-+{
-+ core_if->pcd_cb = cb;
-+ cb->p = p;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function writes isoc data per 1 (micro)frame into tx fifo
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0 };
-+ uint32_t len = 0;
-+ uint32_t dwords;
-+
-+ ep->xfer_len = ep->data_per_frame;
-+ ep->xfer_count = 0;
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[ep->num];
-+
-+ len = ep->xfer_len - ep->xfer_count;
-+
-+ if (len > ep->maxpacket) {
-+ len = ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, ep, 0);
-+
-+ len = ep->xfer_len - ep->xfer_count;
-+ if (len > ep->maxpacket) {
-+ len = ep->maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
-+ txstatus.d32);
-+ }
-+}
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dsts_data_t dsts = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if (ep->is_in) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ ep->xfer_len = ep->data_per_frame;
-+ ep->xfer_count = 0;
-+ ep->xfer_buff = ep->cur_pkt_addr;
-+ ep->dma_addr = ep->cur_pkt_dma_addr;
-+
-+ if (ep->is_in) {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+ deptsiz.b.mc = deptsiz.b.pktcnt;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
-+ deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ if (core_if->dma_enable) {
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->in_ep_regs[ep->num]->
-+ diepdma), (uint32_t) ep->dma_addr);
-+ }
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
-+
-+ if (core_if->dma_enable) {
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->
-+ out_ep_regs[ep->num]->doepdma),
-+ (uint32_t) ep->dma_addr);
-+ }
-+ }
-+
-+ /** Enable endpoint, clear nak */
-+
-+ depctl.d32 = 0;
-+ if (ep->bInterval == 1) {
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ ep->next_frame = dsts.b.soffn + ep->bInterval;
-+
-+ if (ep->next_frame & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ } else {
-+ ep->next_frame += ep->bInterval;
-+
-+ if (ep->next_frame & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ }
-+ }
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(addr, 0, depctl.d32);
-+ depctl.d32 = DWC_READ_REG32(addr);
-+
-+ if (ep->is_in && core_if->dma_enable == 0) {
-+ write_isoc_frame_data(core_if, ep);
-+ }
-+
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+static void dwc_otg_set_uninitialized(int32_t * p, int size)
-+{
-+ int i;
-+ for (i = 0; i < size; i++) {
-+ p[i] = -1;
-+ }
-+}
-+
-+static int dwc_otg_param_initialized(int32_t val)
-+{
-+ return val != -1;
-+}
-+
-+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
-+{
-+ int i;
-+ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
-+ if (!core_if->core_params) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
-+ sizeof(*core_if->core_params) /
-+ sizeof(int32_t));
-+ DWC_PRINTF("Setting default values for core params\n");
-+ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
-+ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
-+ dwc_otg_set_param_dma_desc_enable(core_if,
-+ dwc_param_dma_desc_enable_default);
-+ dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
-+ dwc_otg_set_param_dma_burst_size(core_if,
-+ dwc_param_dma_burst_size_default);
-+ dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
-+ dwc_param_host_support_fs_ls_low_power_default);
-+ dwc_otg_set_param_enable_dynamic_fifo(core_if,
-+ dwc_param_enable_dynamic_fifo_default);
-+ dwc_otg_set_param_data_fifo_size(core_if,
-+ dwc_param_data_fifo_size_default);
-+ dwc_otg_set_param_dev_rx_fifo_size(core_if,
-+ dwc_param_dev_rx_fifo_size_default);
-+ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
-+ dwc_param_dev_nperio_tx_fifo_size_default);
-+ dwc_otg_set_param_host_rx_fifo_size(core_if,
-+ dwc_param_host_rx_fifo_size_default);
-+ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
-+ dwc_param_host_nperio_tx_fifo_size_default);
-+ dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
-+ dwc_param_host_perio_tx_fifo_size_default);
-+ dwc_otg_set_param_max_transfer_size(core_if,
-+ dwc_param_max_transfer_size_default);
-+ dwc_otg_set_param_max_packet_count(core_if,
-+ dwc_param_max_packet_count_default);
-+ dwc_otg_set_param_host_channels(core_if,
-+ dwc_param_host_channels_default);
-+ dwc_otg_set_param_dev_endpoints(core_if,
-+ dwc_param_dev_endpoints_default);
-+ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
-+ dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
-+ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
-+ dwc_param_host_ls_low_power_phy_clk_default);
-+ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
-+ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
-+ dwc_param_phy_ulpi_ext_vbus_default);
-+ dwc_otg_set_param_phy_utmi_width(core_if,
-+ dwc_param_phy_utmi_width_default);
-+ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
-+ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
-+ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
-+ dwc_otg_set_param_en_multiple_tx_fifo(core_if,
-+ dwc_param_en_multiple_tx_fifo_default);
-+ for (i = 0; i < 15; i++) {
-+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
-+ dwc_param_dev_perio_tx_fifo_size_default,
-+ i);
-+ }
-+
-+ for (i = 0; i < 15; i++) {
-+ dwc_otg_set_param_dev_tx_fifo_size(core_if,
-+ dwc_param_dev_tx_fifo_size_default,
-+ i);
-+ }
-+ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
-+ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
-+ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
-+ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
-+ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
-+ dwc_otg_set_param_tx_thr_length(core_if,
-+ dwc_param_tx_thr_length_default);
-+ dwc_otg_set_param_rx_thr_length(core_if,
-+ dwc_param_rx_thr_length_default);
-+ dwc_otg_set_param_ahb_thr_ratio(core_if,
-+ dwc_param_ahb_thr_ratio_default);
-+ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
-+ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
-+ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
-+ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
-+ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
-+ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
-+ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
-+ DWC_PRINTF("Finished setting default values for core params\n");
-+
-+ return 0;
-+}
-+
-+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->dma_enable;
-+}
-+
-+/* Checks if the parameter is outside of its valid range of values */
-+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
-+ (((_param_) < (_low_)) || \
-+ ((_param_) > (_high_)))
-+
-+/* Parameter access functions */
-+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int valid;
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
-+ DWC_WARN("Wrong value for otg_cap parameter\n");
-+ DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ valid = 1;
-+ switch (val) {
-+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
-+ if (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ valid = 0;
-+ break;
-+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
-+ if ((core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ && (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+ && (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
-+ && (core_if->hwcfg2.b.op_mode !=
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
-+ valid = 0;
-+ }
-+ break;
-+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
-+ /* always valid */
-+ break;
-+ }
-+ if (!valid) {
-+ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
-+ DWC_ERROR
-+ ("%d invalid for otg_cap paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (((core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+ || (core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+ || (core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
-+ || (core_if->hwcfg2.b.op_mode ==
-+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
-+ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
-+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->otg_cap = val;
-+out:
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->otg_cap;
-+}
-+
-+int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for opt parameter\n");
-+ return -DWC_E_INVALID;
-+ }
-+ core_if->core_params->opt = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->opt;
-+}
-+
-+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for dma enable\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for dma_enable paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dma_enable = val;
-+ if (val == 0) {
-+ dwc_otg_set_param_dma_desc_enable(core_if, 0);
-+ }
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dma_enable;
-+}
-+
-+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for dma_enable\n");
-+ DWC_WARN("dma_desc_enable must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1)
-+ && ((dwc_otg_get_param_dma_enable(core_if) == 0)
-+ || (core_if->hwcfg4.b.desc_dma == 0))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dma_desc_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+ core_if->core_params->dma_desc_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dma_desc_enable;
-+}
-+
-+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for host_support_fs_low_power\n");
-+ DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+ core_if->core_params->host_support_fs_ls_low_power = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
-+ core_if)
-+{
-+ return core_if->core_params->host_support_fs_ls_low_power;
-+}
-+
-+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for enable_dynamic_fifo\n");
-+ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->enable_dynamic_fifo)) {
-+ DWC_ERROR
-+ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+ core_if->core_params->enable_dynamic_fifo = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->enable_dynamic_fifo;
-+}
-+
-+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
-+ DWC_WARN("Wrong value for data_fifo_size\n");
-+ DWC_WARN("data_fifo_size must be 32-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > core_if->hwcfg3.b.dfifo_depth) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->data_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
-+ val);
-+ }
-+ val = core_if->hwcfg3.b.dfifo_depth;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->data_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->data_fifo_size;
-+}
-+
-+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for dev_rx_fifo_size\n");
-+ DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
-+ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
-+ }
-+ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_rx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_rx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
-+ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_nperio_tx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
-+ 16);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_nperio_tx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_nperio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for host_rx_fifo_size\n");
-+ DWC_WARN("host_rx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_rx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_rx_fifo_size = val;
-+ return retval;
-+
-+}
-+
-+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_rx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
-+ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_nperio_tx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
-+ 16);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_nperio_tx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_nperio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
-+ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > ((core_if->hptxfsiz.d32) >> 16)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_perio_tx_fifo_size)) {
-+ DWC_ERROR
-+ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val = (core_if->hptxfsiz.d32) >> 16;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_perio_tx_fifo_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_perio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
-+ DWC_WARN("Wrong value for max_transfer_size\n");
-+ DWC_WARN("max_transfer_size must be 2047-524288\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->max_transfer_size)) {
-+ DWC_ERROR
-+ ("%d invalid for max_transfer_size. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
-+ 1);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->max_transfer_size = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->max_transfer_size;
-+}
-+
-+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
-+ DWC_WARN("Wrong value for max_packet_count\n");
-+ DWC_WARN("max_packet_count must be 15-511\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->max_packet_count)) {
-+ DWC_ERROR
-+ ("%d invalid for max_packet_count. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->max_packet_count = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->max_packet_count;
-+}
-+
-+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
-+ DWC_WARN("Wrong value for host_channels\n");
-+ DWC_WARN("host_channels must be 1-16\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_channels)) {
-+ DWC_ERROR
-+ ("%d invalid for host_channels. Check HW configurations.\n",
-+ val);
-+ }
-+ val = (core_if->hwcfg2.b.num_host_chan + 1);
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_channels = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_channels;
-+}
-+
-+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
-+ DWC_WARN("Wrong value for dev_endpoints\n");
-+ DWC_WARN("dev_endpoints must be 1-15\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val > (core_if->hwcfg2.b.num_dev_ep)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_endpoints)) {
-+ DWC_ERROR
-+ ("%d invalid for dev_endpoints. Check HW configurations.\n",
-+ val);
-+ }
-+ val = core_if->hwcfg2.b.num_dev_ep;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_endpoints = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_endpoints;
-+}
-+
-+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
-+ DWC_WARN("Wrong value for phy_type\n");
-+ DWC_WARN("phy_type must be 0,1 or 2\n");
-+ return -DWC_E_INVALID;
-+ }
-+#ifndef NO_FS_PHY_HW_CHECKS
-+ if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
-+ ((core_if->hwcfg2.b.hs_phy_type == 1) ||
-+ (core_if->hwcfg2.b.hs_phy_type == 3))) {
-+ valid = 1;
-+ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
-+ ((core_if->hwcfg2.b.hs_phy_type == 2) ||
-+ (core_if->hwcfg2.b.hs_phy_type == 3))) {
-+ valid = 1;
-+ } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1)) {
-+ valid = 1;
-+ }
-+ if (!valid) {
-+ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
-+ DWC_ERROR
-+ ("%d invalid for phy_type. Check HW configurations.\n",
-+ val);
-+ }
-+ if (core_if->hwcfg2.b.hs_phy_type) {
-+ if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
-+ (core_if->hwcfg2.b.hs_phy_type == 1)) {
-+ val = DWC_PHY_TYPE_PARAM_UTMI;
-+ } else {
-+ val = DWC_PHY_TYPE_PARAM_ULPI;
-+ }
-+ }
-+ retval = -DWC_E_INVALID;
-+ }
-+#endif
-+ core_if->core_params->phy_type = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_type;
-+}
-+
-+int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for speed parameter\n");
-+ DWC_WARN("max_speed parameter must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+ if ((val == 0)
-+ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
-+ if (dwc_otg_param_initialized(core_if->core_params->speed)) {
-+ DWC_ERROR
-+ ("%d invalid for speed paremter. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (dwc_otg_get_param_phy_type(core_if) ==
-+ DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
-+ retval = -DWC_E_INVALID;
-+ }
-+ core_if->core_params->speed = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->speed;
-+}
-+
-+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN
-+ ("Wrong value for host_ls_low_power_phy_clk parameter\n");
-+ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
-+ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->host_ls_low_power_phy_clk)) {
-+ DWC_ERROR
-+ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
-+ val);
-+ }
-+ val =
-+ (dwc_otg_get_param_phy_type(core_if) ==
-+ DWC_PHY_TYPE_PARAM_FS) ?
-+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
-+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->host_ls_low_power_phy_clk = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->host_ls_low_power_phy_clk;
-+}
-+
-+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for phy_ulpi_ddr\n");
-+ DWC_WARN("phy_upli_ddr must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->phy_ulpi_ddr = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_ulpi_ddr;
-+}
-+
-+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
-+ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->phy_ulpi_ext_vbus = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_ulpi_ext_vbus;
-+}
-+
-+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
-+ DWC_WARN("Wrong valaue for phy_utmi_width\n");
-+ DWC_WARN("phy_utmi_width must be 8 or 16\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->phy_utmi_width = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->phy_utmi_width;
-+}
-+
-+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
-+ DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->ulpi_fs_ls = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ulpi_fs_ls;
-+}
-+
-+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for ts_dline\n");
-+ DWC_WARN("ts_dline must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->ts_dline = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ts_dline;
-+}
-+
-+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for i2c_enable\n");
-+ DWC_WARN("i2c_enable must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+#ifndef NO_FS_PHY_HW_CHECK
-+ if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for i2c_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+#endif
-+
-+ core_if->core_params->i2c_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->i2c_enable;
-+}
-+
-+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val, int fifo_num)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
-+ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
-+ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val >
-+ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
-+ DWC_ERROR
-+ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
-+ val, fifo_num);
-+ }
-+ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num)
-+{
-+ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
-+}
-+
-+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
-+ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->en_multiple_tx_fifo)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->en_multiple_tx_fifo = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->en_multiple_tx_fifo;
-+}
-+
-+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
-+ int fifo_num)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
-+ DWC_WARN("Wrong value for dev_tx_fifo_size\n");
-+ DWC_WARN("dev_tx_fifo_size must be 4-768\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val >
-+ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
-+ DWC_ERROR
-+ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
-+ val, fifo_num);
-+ }
-+ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num)
-+{
-+ return core_if->core_params->dev_tx_fifo_size[fifo_num];
-+}
-+
-+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
-+ DWC_WARN("Wrong value for thr_ctl\n");
-+ DWC_WARN("thr_ctl must be 0-7\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val != 0) &&
-+ (!dwc_otg_get_param_dma_enable(core_if) ||
-+ !core_if->hwcfg4.b.ded_fifo_en)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->thr_ctl = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->thr_ctl;
-+}
-+
-+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("Wrong value for lpm_enable\n");
-+ DWC_WARN("lpm_enable must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val && !core_if->hwcfg3.b.otg_lpm_en) {
-+ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ val = 0;
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->lpm_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->lpm_enable;
-+}
-+
-+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
-+ DWC_WARN("Wrong valaue for tx_thr_length\n");
-+ DWC_WARN("tx_thr_length must be 8 - 128\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->tx_thr_length = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->tx_thr_length;
-+}
-+
-+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
-+ DWC_WARN("Wrong valaue for rx_thr_length\n");
-+ DWC_WARN("rx_thr_length must be 8 - 128\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->rx_thr_length = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->rx_thr_length;
-+}
-+
-+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
-+ DWC_OTG_PARAM_TEST(val, 4, 4) &&
-+ DWC_OTG_PARAM_TEST(val, 8, 8) &&
-+ DWC_OTG_PARAM_TEST(val, 16, 16) &&
-+ DWC_OTG_PARAM_TEST(val, 32, 32) &&
-+ DWC_OTG_PARAM_TEST(val, 64, 64) &&
-+ DWC_OTG_PARAM_TEST(val, 128, 128) &&
-+ DWC_OTG_PARAM_TEST(val, 256, 256)) {
-+ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ core_if->core_params->dma_burst_size = val;
-+ return 0;
-+}
-+
-+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dma_burst_size;
-+}
-+
-+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter pti_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->pti_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->pti_enable;
-+}
-+
-+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->mpi_enable = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->mpi_enable;
-+}
-+
-+int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
-+ return -DWC_E_INVALID;
-+ }
-+ if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->adp_supp_enable)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter adp_enable. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->adp_supp_enable = val;
-+ /*Set OTG version 2.0 in case of enabling ADP*/
-+ if (val)
-+ dwc_otg_set_param_otg_ver(core_if, 1);
-+
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->adp_supp_enable;
-+}
-+
-+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
-+ DWC_WARN("ic_usb_cap must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
-+ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->ic_usb_cap = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ic_usb_cap;
-+}
-+
-+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
-+ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
-+ DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (val
-+ && (core_if->snpsid < OTG_CORE_REV_2_81a
-+ || !dwc_otg_get_param_thr_ctl(core_if))) {
-+ valid = 0;
-+ } else if (val
-+ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
-+ 4)) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized
-+ (core_if->core_params->ahb_thr_ratio)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+
-+ core_if->core_params->ahb_thr_ratio = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ahb_thr_ratio;
-+}
-+
-+int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+ hwcfg4_data_t hwcfg4 = {.d32 = 0 };
-+ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
-+ DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
-+ DWC_WARN("power_down must be 0 - 2\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
-+ valid = 0;
-+ }
-+ if ((val == 3)
-+ && ((core_if->snpsid < OTG_CORE_REV_3_00a)
-+ || (hwcfg4.b.xhiber == 0))) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
-+ DWC_ERROR
-+ ("%d invalid for parameter power_down. Check HW configuration.\n",
-+ val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->power_down = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->power_down;
-+}
-+
-+int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
-+ DWC_WARN("reload_ctl must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
-+ DWC_ERROR("%d invalid for parameter reload_ctl."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->reload_ctl = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->reload_ctl;
-+}
-+
-+int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
-+ DWC_WARN("dev_out_nak must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
-+ !(core_if->core_params->dma_desc_enable))) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
-+ DWC_ERROR("%d invalid for parameter dev_out_nak."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->dev_out_nak = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->dev_out_nak;
-+}
-+
-+int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
-+ DWC_WARN("cont_on_bna must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
-+ !(core_if->core_params->dma_desc_enable))) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
-+ DWC_ERROR("%d invalid for parameter cont_on_bna."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->cont_on_bna = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->cont_on_bna;
-+}
-+
-+int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+ int valid = 1;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
-+ DWC_WARN("ahb_single must be 0 or 1\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
-+ valid = 0;
-+ }
-+ if (valid == 0) {
-+ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
-+ DWC_ERROR("%d invalid for parameter ahb_single."
-+ "Check HW configuration.\n", val);
-+ }
-+ retval = -DWC_E_INVALID;
-+ val = 0;
-+ }
-+ core_if->core_params->ahb_single = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->ahb_single;
-+}
-+
-+int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+ int retval = 0;
-+
-+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
-+ DWC_WARN
-+ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ core_if->core_params->otg_ver = val;
-+ return retval;
-+}
-+
-+int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->core_params->otg_ver;
-+}
-+
-+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
-+{
-+ gotgctl_data_t otgctl;
-+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ return otgctl.b.hstnegscs;
-+}
-+
-+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
-+{
-+ gotgctl_data_t otgctl;
-+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ return otgctl.b.sesreqscs;
-+}
-+
-+void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ if(core_if->otg_ver == 0) {
-+ gotgctl_data_t otgctl;
-+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ otgctl.b.hnpreq = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
-+ } else {
-+ core_if->otg_sts = val;
-+ }
-+}
-+
-+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->snpsid;
-+}
-+
-+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ return gintsts.b.curmode;
-+}
-+
-+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ return usbcfg.b.hnpcap;
-+}
-+
-+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ usbcfg.b.hnpcap = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ return usbcfg.b.srpcap;
-+}
-+
-+void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ gusbcfg_data_t usbcfg;
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ usbcfg.b.srpcap = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
-+{
-+ dcfg_data_t dcfg;
-+ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
-+
-+ dcfg.d32 = -1; //GRAYG
-+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
-+ if (NULL == core_if)
-+ DWC_ERROR("reg request with NULL core_if\n");
-+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
-+ core_if, core_if->dev_if);
-+ if (NULL == core_if->dev_if)
-+ DWC_ERROR("reg request with NULL dev_if\n");
-+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
-+ "dev_global_regs(%p)\n", __func__,
-+ core_if, core_if->dev_if,
-+ core_if->dev_if->dev_global_regs);
-+ if (NULL == core_if->dev_if->dev_global_regs)
-+ DWC_ERROR("reg request with NULL dev_global_regs\n");
-+ else {
-+ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
-+ "dev_global_regs(%p)->dcfg = %p\n", __func__,
-+ core_if, core_if->dev_if,
-+ core_if->dev_if->dev_global_regs,
-+ &core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ }
-+ return dcfg.b.devspd;
-+}
-+
-+void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ dcfg_data_t dcfg;
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devspd = val;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ return hprt0.b.prtconnsts;
-+}
-+
-+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ return dsts.b.enumspd;
-+}
-+
-+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ return hprt0.b.prtpwr;
-+
-+}
-+
-+uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
-+{
-+ return core_if->hibernation_suspend;
-+}
-+
-+void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = val;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ return hprt0.b.prtsusp;
-+
-+}
-+
-+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = val;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
-+{
-+ hfir_data_t hfir;
-+ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+ return hfir.b.frint;
-+
-+}
-+
-+void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hfir_data_t hfir;
-+ uint32_t fram_int;
-+ fram_int = calc_frame_interval(core_if);
-+ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+ if (!core_if->core_params->reload_ctl) {
-+ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
-+ "not set to 1.\nShould load driver with reload_ctl=1"
-+ " module parameter\n");
-+ return;
-+ }
-+ switch (fram_int) {
-+ case 3750:
-+ if ((val < 3350) || (val > 4150)) {
-+ DWC_WARN("HFIR interval for HS core and 30 MHz"
-+ "clock freq should be from 3350 to 4150\n");
-+ return;
-+ }
-+ break;
-+ case 30000:
-+ if ((val < 26820) || (val > 33180)) {
-+ DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
-+ "clock freq should be from 26820 to 33180\n");
-+ return;
-+ }
-+ break;
-+ case 6000:
-+ if ((val < 5360) || (val > 6640)) {
-+ DWC_WARN("HFIR interval for HS core and 48 MHz"
-+ "clock freq should be from 5360 to 6640\n");
-+ return;
-+ }
-+ break;
-+ case 48000:
-+ if ((val < 42912) || (val > 53088)) {
-+ DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
-+ "clock freq should be from 42912 to 53088\n");
-+ return;
-+ }
-+ break;
-+ case 7500:
-+ if ((val < 6700) || (val > 8300)) {
-+ DWC_WARN("HFIR interval for HS core and 60 MHz"
-+ "clock freq should be from 6700 to 8300\n");
-+ return;
-+ }
-+ break;
-+ case 60000:
-+ if ((val < 53640) || (val > 65536)) {
-+ DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
-+ "clock freq should be from 53640 to 65536\n");
-+ return;
-+ }
-+ break;
-+ default:
-+ DWC_WARN("Unknown frame interval\n");
-+ return;
-+ break;
-+
-+ }
-+ hfir.b.frint = val;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
-+}
-+
-+uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
-+{
-+ hcfg_data_t hcfg;
-+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ return hcfg.b.modechtimen;
-+
-+}
-+
-+void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hcfg_data_t hcfg;
-+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+ hcfg.b.modechtimen = val;
-+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtres = val;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
-+{
-+ dctl_data_t dctl;
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ return dctl.b.rmtwkupsig;
-+}
-+
-+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+
-+ DWC_ASSERT(!
-+ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
-+ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
-+ core_if->lx_state, lpmcfg.b.prt_sleep_sts);
-+
-+ return lpmcfg.b.prt_sleep_sts;
-+}
-+
-+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.rem_wkup_en;
-+}
-+
-+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.appl_resp;
-+}
-+
-+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.appl_resp = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.hsic_connect;
-+}
-+
-+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.hsic_connect = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ return lpmcfg.b.inv_sel_hsic;
-+
-+}
-+
-+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.inv_sel_hsic = val;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+}
-+
-+void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
-+}
-+
-+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+}
-+
-+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
-+}
-+
-+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+}
-+
-+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
-+}
-+
-+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
-+}
-+
-+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
-+}
-+
-+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
-+}
-+
-+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
-+}
-+
-+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
-+}
-+
-+void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
-+}
-+
-+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(core_if->host_if->hprt0);
-+
-+}
-+
-+void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, val);
-+}
-+
-+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->guid);
-+}
-+
-+void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
-+}
-+
-+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+}
-+
-+uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
-+{
-+ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
-+}
-+
-+/**
-+ * Start the SRP timer to detect when the SRP does not complete within
-+ * 6 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
-+{
-+ core_if->srp_timer_started = 1;
-+ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
-+}
-+
-+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
-+ gotgctl_data_t mem;
-+ gotgctl_data_t val;
-+
-+ val.d32 = DWC_READ_REG32(addr);
-+ if (val.b.sesreq) {
-+ DWC_ERROR("Session Request Already active!\n");
-+ return;
-+ }
-+
-+ DWC_INFO("Session Request Initated\n"); //NOTICE
-+ mem.d32 = DWC_READ_REG32(addr);
-+ mem.b.sesreq = 1;
-+ DWC_WRITE_REG32(addr, mem.d32);
-+
-+ /* Start the SRP timer */
-+ dwc_otg_pcd_start_srp_timer(core_if);
-+ return;
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cil.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cil.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,1464 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
-+ * $Revision: #123 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CIL_H__)
-+#define __DWC_CIL_H__
-+
-+#include "dwc_list.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_regs.h"
-+
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_adp.h"
-+
-+/**
-+ * @file
-+ * This file contains the interface to the Core Interface Layer.
-+ */
-+
-+#ifdef DWC_UTE_CFI
-+
-+#define MAX_DMA_DESCS_PER_EP 256
-+
-+/**
-+ * Enumeration for the data buffer mode
-+ */
-+typedef enum _data_buffer_mode {
-+ BM_STANDARD = 0, /* data buffer is in normal mode */
-+ BM_SG = 1, /* data buffer uses the scatter/gather mode */
-+ BM_CONCAT = 2, /* data buffer uses the concatenation mode */
-+ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
-+ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
-+} data_buffer_mode_e;
-+#endif //DWC_UTE_CFI
-+
-+/** Macros defined for DWC OTG HW Release version */
-+
-+#define OTG_CORE_REV_2_60a 0x4F54260A
-+#define OTG_CORE_REV_2_71a 0x4F54271A
-+#define OTG_CORE_REV_2_72a 0x4F54272A
-+#define OTG_CORE_REV_2_80a 0x4F54280A
-+#define OTG_CORE_REV_2_81a 0x4F54281A
-+#define OTG_CORE_REV_2_90a 0x4F54290A
-+#define OTG_CORE_REV_2_91a 0x4F54291A
-+#define OTG_CORE_REV_2_92a 0x4F54292A
-+#define OTG_CORE_REV_2_93a 0x4F54293A
-+#define OTG_CORE_REV_2_94a 0x4F54294A
-+#define OTG_CORE_REV_3_00a 0x4F54300A
-+
-+/**
-+ * Information for each ISOC packet.
-+ */
-+typedef struct iso_pkt_info {
-+ uint32_t offset;
-+ uint32_t length;
-+ int32_t status;
-+} iso_pkt_info_t;
-+
-+/**
-+ * The <code>dwc_ep</code> structure represents the state of a single
-+ * endpoint when acting in device mode. It contains the data items
-+ * needed for an endpoint to be activated and transfer packets.
-+ */
-+typedef struct dwc_ep {
-+ /** EP number used for register address lookup */
-+ uint8_t num;
-+ /** EP direction 0 = OUT */
-+ unsigned is_in:1;
-+ /** EP active. */
-+ unsigned active:1;
-+
-+ /**
-+ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
-+ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
-+ unsigned tx_fifo_num:4;
-+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
-+ unsigned type:2;
-+#define DWC_OTG_EP_TYPE_CONTROL 0
-+#define DWC_OTG_EP_TYPE_ISOC 1
-+#define DWC_OTG_EP_TYPE_BULK 2
-+#define DWC_OTG_EP_TYPE_INTR 3
-+
-+ /** DATA start PID for INTR and BULK EP */
-+ unsigned data_pid_start:1;
-+ /** Frame (even/odd) for ISOC EP */
-+ unsigned even_odd_frame:1;
-+ /** Max Packet bytes */
-+ unsigned maxpacket:11;
-+
-+ /** Max Transfer size */
-+ uint32_t maxxfer;
-+
-+ /** @name Transfer state */
-+ /** @{ */
-+
-+ /**
-+ * Pointer to the beginning of the transfer buffer -- do not modify
-+ * during transfer.
-+ */
-+
-+ dwc_dma_t dma_addr;
-+
-+ dwc_dma_t dma_desc_addr;
-+ dwc_otg_dev_dma_desc_t *desc_addr;
-+
-+ uint8_t *start_xfer_buff;
-+ /** pointer to the transfer buffer */
-+ uint8_t *xfer_buff;
-+ /** Number of bytes to transfer */
-+ unsigned xfer_len:19;
-+ /** Number of bytes transferred. */
-+ unsigned xfer_count:19;
-+ /** Sent ZLP */
-+ unsigned sent_zlp:1;
-+ /** Total len for control transfer */
-+ unsigned total_len:19;
-+
-+ /** stall clear flag */
-+ unsigned stall_clear_flag:1;
-+
-+ /** SETUP pkt cnt rollover flag for EP0 out*/
-+ unsigned stp_rollover;
-+
-+#ifdef DWC_UTE_CFI
-+ /* The buffer mode */
-+ data_buffer_mode_e buff_mode;
-+
-+ /* The chain of DMA descriptors.
-+ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
-+ */
-+ dwc_otg_dma_desc_t *descs;
-+
-+ /* The DMA address of the descriptors chain start */
-+ dma_addr_t descs_dma_addr;
-+ /** This variable stores the length of the last enqueued request */
-+ uint32_t cfi_req_len;
-+#endif //DWC_UTE_CFI
-+
-+/** Max DMA Descriptor count for any EP */
-+#define MAX_DMA_DESC_CNT 256
-+ /** Allocated DMA Desc count */
-+ uint32_t desc_cnt;
-+
-+ /** bInterval */
-+ uint32_t bInterval;
-+ /** Next frame num to setup next ISOC transfer */
-+ uint32_t frame_num;
-+ /** Indicates SOF number overrun in DSTS */
-+ uint8_t frm_overrun;
-+
-+#ifdef DWC_UTE_PER_IO
-+ /** Next frame num for which will be setup DMA Desc */
-+ uint32_t xiso_frame_num;
-+ /** bInterval */
-+ uint32_t xiso_bInterval;
-+ /** Count of currently active transfers - shall be either 0 or 1 */
-+ int xiso_active_xfers;
-+ int xiso_queued_xfers;
-+#endif
-+#ifdef DWC_EN_ISOC
-+ /**
-+ * Variables specific for ISOC EPs
-+ *
-+ */
-+ /** DMA addresses of ISOC buffers */
-+ dwc_dma_t dma_addr0;
-+ dwc_dma_t dma_addr1;
-+
-+ dwc_dma_t iso_dma_desc_addr;
-+ dwc_otg_dev_dma_desc_t *iso_desc_addr;
-+
-+ /** pointer to the transfer buffers */
-+ uint8_t *xfer_buff0;
-+ uint8_t *xfer_buff1;
-+
-+ /** number of ISOC Buffer is processing */
-+ uint32_t proc_buf_num;
-+ /** Interval of ISOC Buffer processing */
-+ uint32_t buf_proc_intrvl;
-+ /** Data size for regular frame */
-+ uint32_t data_per_frame;
-+
-+ /* todo - pattern data support is to be implemented in the future */
-+ /** Data size for pattern frame */
-+ uint32_t data_pattern_frame;
-+ /** Frame number of pattern data */
-+ uint32_t sync_frame;
-+
-+ /** bInterval */
-+ uint32_t bInterval;
-+ /** ISO Packet number per frame */
-+ uint32_t pkt_per_frm;
-+ /** Next frame num for which will be setup DMA Desc */
-+ uint32_t next_frame;
-+ /** Number of packets per buffer processing */
-+ uint32_t pkt_cnt;
-+ /** Info for all isoc packets */
-+ iso_pkt_info_t *pkt_info;
-+ /** current pkt number */
-+ uint32_t cur_pkt;
-+ /** current pkt number */
-+ uint8_t *cur_pkt_addr;
-+ /** current pkt number */
-+ uint32_t cur_pkt_dma_addr;
-+#endif /* DWC_EN_ISOC */
-+
-+/** @} */
-+} dwc_ep_t;
-+
-+/*
-+ * Reasons for halting a host channel.
-+ */
-+typedef enum dwc_otg_halt_status {
-+ DWC_OTG_HC_XFER_NO_HALT_STATUS,
-+ DWC_OTG_HC_XFER_COMPLETE,
-+ DWC_OTG_HC_XFER_URB_COMPLETE,
-+ DWC_OTG_HC_XFER_ACK,
-+ DWC_OTG_HC_XFER_NAK,
-+ DWC_OTG_HC_XFER_NYET,
-+ DWC_OTG_HC_XFER_STALL,
-+ DWC_OTG_HC_XFER_XACT_ERR,
-+ DWC_OTG_HC_XFER_FRAME_OVERRUN,
-+ DWC_OTG_HC_XFER_BABBLE_ERR,
-+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
-+ DWC_OTG_HC_XFER_AHB_ERR,
-+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE
-+} dwc_otg_halt_status_e;
-+
-+/**
-+ * Host channel descriptor. This structure represents the state of a single
-+ * host channel when acting in host mode. It contains the data items needed to
-+ * transfer packets to an endpoint via a host channel.
-+ */
-+typedef struct dwc_hc {
-+ /** Host channel number used for register address lookup */
-+ uint8_t hc_num;
-+
-+ /** Device to access */
-+ unsigned dev_addr:7;
-+
-+ /** EP to access */
-+ unsigned ep_num:4;
-+
-+ /** EP direction. 0: OUT, 1: IN */
-+ unsigned ep_is_in:1;
-+
-+ /**
-+ * EP speed.
-+ * One of the following values:
-+ * - DWC_OTG_EP_SPEED_LOW
-+ * - DWC_OTG_EP_SPEED_FULL
-+ * - DWC_OTG_EP_SPEED_HIGH
-+ */
-+ unsigned speed:2;
-+#define DWC_OTG_EP_SPEED_LOW 0
-+#define DWC_OTG_EP_SPEED_FULL 1
-+#define DWC_OTG_EP_SPEED_HIGH 2
-+
-+ /**
-+ * Endpoint type.
-+ * One of the following values:
-+ * - DWC_OTG_EP_TYPE_CONTROL: 0
-+ * - DWC_OTG_EP_TYPE_ISOC: 1
-+ * - DWC_OTG_EP_TYPE_BULK: 2
-+ * - DWC_OTG_EP_TYPE_INTR: 3
-+ */
-+ unsigned ep_type:2;
-+
-+ /** Max packet size in bytes */
-+ unsigned max_packet:11;
-+
-+ /**
-+ * PID for initial transaction.
-+ * 0: DATA0,<br>
-+ * 1: DATA2,<br>
-+ * 2: DATA1,<br>
-+ * 3: MDATA (non-Control EP),
-+ * SETUP (Control EP)
-+ */
-+ unsigned data_pid_start:2;
-+#define DWC_OTG_HC_PID_DATA0 0
-+#define DWC_OTG_HC_PID_DATA2 1
-+#define DWC_OTG_HC_PID_DATA1 2
-+#define DWC_OTG_HC_PID_MDATA 3
-+#define DWC_OTG_HC_PID_SETUP 3
-+
-+ /** Number of periodic transactions per (micro)frame */
-+ unsigned multi_count:2;
-+
-+ /** @name Transfer State */
-+ /** @{ */
-+
-+ /** Pointer to the current transfer buffer position. */
-+ uint8_t *xfer_buff;
-+ /**
-+ * In Buffer DMA mode this buffer will be used
-+ * if xfer_buff is not DWORD aligned.
-+ */
-+ dwc_dma_t align_buff;
-+ /** Total number of bytes to transfer. */
-+ uint32_t xfer_len;
-+ /** Number of bytes transferred so far. */
-+ uint32_t xfer_count;
-+ /** Packet count at start of transfer.*/
-+ uint16_t start_pkt_count;
-+
-+ /**
-+ * Flag to indicate whether the transfer has been started. Set to 1 if
-+ * it has been started, 0 otherwise.
-+ */
-+ uint8_t xfer_started;
-+
-+ /**
-+ * Set to 1 to indicate that a PING request should be issued on this
-+ * channel. If 0, process normally.
-+ */
-+ uint8_t do_ping;
-+
-+ /**
-+ * Set to 1 to indicate that the error count for this transaction is
-+ * non-zero. Set to 0 if the error count is 0.
-+ */
-+ uint8_t error_state;
-+
-+ /**
-+ * Set to 1 to indicate that this channel should be halted the next
-+ * time a request is queued for the channel. This is necessary in
-+ * slave mode if no request queue space is available when an attempt
-+ * is made to halt the channel.
-+ */
-+ uint8_t halt_on_queue;
-+
-+ /**
-+ * Set to 1 if the host channel has been halted, but the core is not
-+ * finished flushing queued requests. Otherwise 0.
-+ */
-+ uint8_t halt_pending;
-+
-+ /**
-+ * Reason for halting the host channel.
-+ */
-+ dwc_otg_halt_status_e halt_status;
-+
-+ /*
-+ * Split settings for the host channel
-+ */
-+ uint8_t do_split; /**< Enable split for the channel */
-+ uint8_t complete_split; /**< Enable complete split */
-+ uint8_t hub_addr; /**< Address of high speed hub */
-+
-+ uint8_t port_addr; /**< Port of the low/full speed device */
-+ /** Split transaction position
-+ * One of the following values:
-+ * - DWC_HCSPLIT_XACTPOS_MID
-+ * - DWC_HCSPLIT_XACTPOS_BEGIN
-+ * - DWC_HCSPLIT_XACTPOS_END
-+ * - DWC_HCSPLIT_XACTPOS_ALL */
-+ uint8_t xact_pos;
-+
-+ /** Set when the host channel does a short read. */
-+ uint8_t short_read;
-+
-+ /**
-+ * Number of requests issued for this channel since it was assigned to
-+ * the current transfer (not counting PINGs).
-+ */
-+ uint8_t requests;
-+
-+ /**
-+ * Queue Head for the transfer being processed by this channel.
-+ */
-+ struct dwc_otg_qh *qh;
-+
-+ /** @} */
-+
-+ /** Entry in list of host channels. */
-+ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
-+
-+ /** @name Descriptor DMA support */
-+ /** @{ */
-+
-+ /** Number of Transfer Descriptors */
-+ uint16_t ntd;
-+
-+ /** Descriptor List DMA address */
-+ dwc_dma_t desc_list_addr;
-+
-+ /** Scheduling micro-frame bitmap. */
-+ uint8_t schinfo;
-+
-+ /** @} */
-+} dwc_hc_t;
-+
-+/**
-+ * The following parameters may be specified when starting the module. These
-+ * parameters define how the DWC_otg controller should be configured.
-+ */
-+typedef struct dwc_otg_core_params {
-+ int32_t opt;
-+
-+ /**
-+ * Specifies the OTG capabilities. The driver will automatically
-+ * detect the value for this parameter if none is specified.
-+ * 0 - HNP and SRP capable (default)
-+ * 1 - SRP Only capable
-+ * 2 - No HNP/SRP capable
-+ */
-+ int32_t otg_cap;
-+
-+ /**
-+ * Specifies whether to use slave or DMA mode for accessing the data
-+ * FIFOs. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - Slave
-+ * 1 - DMA (default, if available)
-+ */
-+ int32_t dma_enable;
-+
-+ /**
-+ * When DMA mode is enabled specifies whether to use address DMA or DMA
-+ * Descriptor mode for accessing the data FIFOs in device mode. The driver
-+ * will automatically detect the value for this if none is specified.
-+ * 0 - address DMA
-+ * 1 - DMA Descriptor(default, if available)
-+ */
-+ int32_t dma_desc_enable;
-+ /** The DMA Burst size (applicable only for External DMA
-+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ */
-+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */
-+
-+ /**
-+ * Specifies the maximum speed of operation in host and device mode.
-+ * The actual speed depends on the speed of the attached device and
-+ * the value of phy_type. The actual speed depends on the speed of the
-+ * attached device.
-+ * 0 - High Speed (default)
-+ * 1 - Full Speed
-+ */
-+ int32_t speed;
-+ /** Specifies whether low power mode is supported when attached
-+ * to a Full Speed or Low Speed device in host mode.
-+ * 0 - Don't support low power mode (default)
-+ * 1 - Support low power mode
-+ */
-+ int32_t host_support_fs_ls_low_power;
-+
-+ /** Specifies the PHY clock rate in low power mode when connected to a
-+ * Low Speed device in host mode. This parameter is applicable only if
-+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+ * then defaults to 6 MHZ otherwise 48 MHZ.
-+ *
-+ * 0 - 48 MHz
-+ * 1 - 6 MHz
-+ */
-+ int32_t host_ls_low_power_phy_clk;
-+
-+ /**
-+ * 0 - Use cC FIFO size parameters
-+ * 1 - Allow dynamic FIFO sizing (default)
-+ */
-+ int32_t enable_dynamic_fifo;
-+
-+ /** Total number of 4-byte words in the data FIFO memory. This
-+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+ * Tx FIFOs.
-+ * 32 to 32768 (default 8192)
-+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ */
-+ int32_t data_fifo_size;
-+
-+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1064)
-+ */
-+ int32_t dev_rx_fifo_size;
-+
-+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+ * when dynamic FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t dev_nperio_tx_fifo_size;
-+
-+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+
-+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_rx_fifo_size;
-+
-+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+ * when Dynamic FIFO sizing is enabled in the core.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_nperio_tx_fifo_size;
-+
-+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+ int32_t host_perio_tx_fifo_size;
-+
-+ /** The maximum transfer size supported in bytes.
-+ * 2047 to 65,535 (default 65,535)
-+ */
-+ int32_t max_transfer_size;
-+
-+ /** The maximum number of packets in a transfer.
-+ * 15 to 511 (default 511)
-+ */
-+ int32_t max_packet_count;
-+
-+ /** The number of host channel registers to use.
-+ * 1 to 16 (default 12)
-+ * Note: The FPGA configuration supports a maximum of 12 host channels.
-+ */
-+ int32_t host_channels;
-+
-+ /** The number of endpoints in addition to EP0 available for device
-+ * mode operations.
-+ * 1 to 15 (default 6 IN and OUT)
-+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+ * endpoints in addition to EP0.
-+ */
-+ int32_t dev_endpoints;
-+
-+ /**
-+ * Specifies the type of PHY interface to use. By default, the driver
-+ * will automatically detect the phy_type.
-+ *
-+ * 0 - Full Speed PHY
-+ * 1 - UTMI+ (default)
-+ * 2 - ULPI
-+ */
-+ int32_t phy_type;
-+
-+ /**
-+ * Specifies the UTMI+ Data Width. This parameter is
-+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+ * PHY_TYPE, this parameter indicates the data width between
-+ * the MAC and the ULPI Wrapper.) Also, this parameter is
-+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+ * to "8 and 16 bits", meaning that the core has been
-+ * configured to work at either data path width.
-+ *
-+ * 8 or 16 bits (default 16)
-+ */
-+ int32_t phy_utmi_width;
-+
-+ /**
-+ * Specifies whether the ULPI operates at double or single
-+ * data rate. This parameter is only applicable if PHY_TYPE is
-+ * ULPI.
-+ *
-+ * 0 - single data rate ULPI interface with 8 bit wide data
-+ * bus (default)
-+ * 1 - double data rate ULPI interface with 4 bit wide data
-+ * bus
-+ */
-+ int32_t phy_ulpi_ddr;
-+
-+ /**
-+ * Specifies whether to use the internal or external supply to
-+ * drive the vbus with a ULPI phy.
-+ */
-+ int32_t phy_ulpi_ext_vbus;
-+
-+ /**
-+ * Specifies whether to use the I2Cinterface for full speed PHY. This
-+ * parameter is only applicable if PHY_TYPE is FS.
-+ * 0 - No (default)
-+ * 1 - Yes
-+ */
-+ int32_t i2c_enable;
-+
-+ int32_t ulpi_fs_ls;
-+
-+ int32_t ts_dline;
-+
-+ /**
-+ * Specifies whether dedicated transmit FIFOs are
-+ * enabled for non periodic IN endpoints in device mode
-+ * 0 - No
-+ * 1 - Yes
-+ */
-+ int32_t en_multiple_tx_fifo;
-+
-+ /** Number of 4-byte words in each of the Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+
-+ /** Thresholding enable flag-
-+ * bit 0 - enable non-ISO Tx thresholding
-+ * bit 1 - enable ISO Tx thresholding
-+ * bit 2 - enable Rx thresholding
-+ */
-+ uint32_t thr_ctl;
-+
-+ /** Thresholding length for Tx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+ uint32_t tx_thr_length;
-+
-+ /** Thresholding length for Rx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+ uint32_t rx_thr_length;
-+
-+ /**
-+ * Specifies whether LPM (Link Power Management) support is enabled
-+ */
-+ int32_t lpm_enable;
-+
-+ /** Per Transfer Interrupt
-+ * mode enable flag
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t pti_enable;
-+
-+ /** Multi Processor Interrupt
-+ * mode enable flag
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t mpi_enable;
-+
-+ /** IS_USB Capability
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t ic_usb_cap;
-+
-+ /** AHB Threshold Ratio
-+ * 2'b00 AHB Threshold = MAC Threshold
-+ * 2'b01 AHB Threshold = 1/2 MAC Threshold
-+ * 2'b10 AHB Threshold = 1/4 MAC Threshold
-+ * 2'b11 AHB Threshold = 1/8 MAC Threshold
-+ */
-+ int32_t ahb_thr_ratio;
-+
-+ /** ADP Support
-+ * 1 - Enabled
-+ * 0 - Disabled
-+ */
-+ int32_t adp_supp_enable;
-+
-+ /** HFIR Reload Control
-+ * 0 - The HFIR cannot be reloaded dynamically.
-+ * 1 - Allow dynamic reloading of the HFIR register during runtime.
-+ */
-+ int32_t reload_ctl;
-+
-+ /** DCFG: Enable device Out NAK
-+ * 0 - The core does not set NAK after Bulk Out transfer complete.
-+ * 1 - The core sets NAK after Bulk OUT transfer complete.
-+ */
-+ int32_t dev_out_nak;
-+
-+ /** DCFG: Enable Continue on BNA
-+ * After receiving BNA interrupt the core disables the endpoint,when the
-+ * endpoint is re-enabled by the application the core starts processing
-+ * 0 - from the DOEPDMA descriptor
-+ * 1 - from the descriptor which received the BNA.
-+ */
-+ int32_t cont_on_bna;
-+
-+ /** GAHBCFG: AHB Single Support
-+ * This bit when programmed supports SINGLE transfers for remainder
-+ * data in a transfer for DMA mode of operation.
-+ * 0 - in this case the remainder data will be sent using INCR burst size.
-+ * 1 - in this case the remainder data will be sent using SINGLE burst size.
-+ */
-+ int32_t ahb_single;
-+
-+ /** Core Power down mode
-+ * 0 - No Power Down is enabled
-+ * 1 - Reserved
-+ * 2 - Complete Power Down (Hibernation)
-+ */
-+ int32_t power_down;
-+
-+ /** OTG revision supported
-+ * 0 - OTG 1.3 revision
-+ * 1 - OTG 2.0 revision
-+ */
-+ int32_t otg_ver;
-+
-+} dwc_otg_core_params_t;
-+
-+#ifdef DEBUG
-+struct dwc_otg_core_if;
-+typedef struct hc_xfer_info {
-+ struct dwc_otg_core_if *core_if;
-+ dwc_hc_t *hc;
-+} hc_xfer_info_t;
-+#endif
-+
-+typedef struct ep_xfer_info {
-+ struct dwc_otg_core_if *core_if;
-+ dwc_ep_t *ep;
-+ uint8_t state;
-+} ep_xfer_info_t;
-+/*
-+ * Device States
-+ */
-+typedef enum dwc_otg_lx_state {
-+ /** On state */
-+ DWC_OTG_L0,
-+ /** LPM sleep state*/
-+ DWC_OTG_L1,
-+ /** USB suspend state*/
-+ DWC_OTG_L2,
-+ /** Off state*/
-+ DWC_OTG_L3
-+} dwc_otg_lx_state_e;
-+
-+struct dwc_otg_global_regs_backup {
-+ uint32_t gotgctl_local;
-+ uint32_t gintmsk_local;
-+ uint32_t gahbcfg_local;
-+ uint32_t gusbcfg_local;
-+ uint32_t grxfsiz_local;
-+ uint32_t gnptxfsiz_local;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ uint32_t glpmcfg_local;
-+#endif
-+ uint32_t gi2cctl_local;
-+ uint32_t hptxfsiz_local;
-+ uint32_t pcgcctl_local;
-+ uint32_t gdfifocfg_local;
-+ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
-+ uint32_t gpwrdn_local;
-+ uint32_t xhib_pcgcctl;
-+ uint32_t xhib_gpwrdn;
-+};
-+
-+struct dwc_otg_host_regs_backup {
-+ uint32_t hcfg_local;
-+ uint32_t haintmsk_local;
-+ uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
-+ uint32_t hprt0_local;
-+ uint32_t hfir_local;
-+};
-+
-+struct dwc_otg_dev_regs_backup {
-+ uint32_t dcfg;
-+ uint32_t dctl;
-+ uint32_t daintmsk;
-+ uint32_t diepmsk;
-+ uint32_t doepmsk;
-+ uint32_t diepctl[MAX_EPS_CHANNELS];
-+ uint32_t dieptsiz[MAX_EPS_CHANNELS];
-+ uint32_t diepdma[MAX_EPS_CHANNELS];
-+};
-+/**
-+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
-+ * the DWC_otg controller acting in either host or device mode. It
-+ * represents the programming view of the controller as a whole.
-+ */
-+struct dwc_otg_core_if {
-+ /** Parameters that define how the core should be configured.*/
-+ dwc_otg_core_params_t *core_params;
-+
-+ /** Core Global registers starting at offset 000h. */
-+ dwc_otg_core_global_regs_t *core_global_regs;
-+
-+ /** Device-specific information */
-+ dwc_otg_dev_if_t *dev_if;
-+ /** Host-specific information */
-+ dwc_otg_host_if_t *host_if;
-+
-+ /** Value from SNPSID register */
-+ uint32_t snpsid;
-+
-+ /*
-+ * Set to 1 if the core PHY interface bits in USBCFG have been
-+ * initialized.
-+ */
-+ uint8_t phy_init_done;
-+
-+ /*
-+ * SRP Success flag, set by srp success interrupt in FS I2C mode
-+ */
-+ uint8_t srp_success;
-+ uint8_t srp_timer_started;
-+ /** Timer for SRP. If it expires before SRP is successful
-+ * clear the SRP. */
-+ dwc_timer_t *srp_timer;
-+
-+#ifdef DWC_DEV_SRPCAP
-+ /* This timer is needed to power on the hibernated host core if SRP is not
-+ * initiated on connected SRP capable device for limited period of time
-+ */
-+ uint8_t pwron_timer_started;
-+ dwc_timer_t *pwron_timer;
-+#endif
-+ /* Common configuration information */
-+ /** Power and Clock Gating Control Register */
-+ volatile uint32_t *pcgcctl;
-+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
-+
-+ /** Push/pop addresses for endpoints or host channels.*/
-+ uint32_t *data_fifo[MAX_EPS_CHANNELS];
-+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
-+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
-+
-+ /** Total RAM for FIFOs (Bytes) */
-+ uint16_t total_fifo_size;
-+ /** Size of Rx FIFO (Bytes) */
-+ uint16_t rx_fifo_size;
-+ /** Size of Non-periodic Tx FIFO (Bytes) */
-+ uint16_t nperio_tx_fifo_size;
-+
-+ /** 1 if DMA is enabled, 0 otherwise. */
-+ uint8_t dma_enable;
-+
-+ /** 1 if DMA descriptor is enabled, 0 otherwise. */
-+ uint8_t dma_desc_enable;
-+
-+ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
-+ uint8_t pti_enh_enable;
-+
-+ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
-+ uint8_t multiproc_int_enable;
-+
-+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
-+ uint8_t en_multiple_tx_fifo;
-+
-+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in
-+ * process of being queued */
-+ uint8_t queuing_high_bandwidth;
-+
-+ /** Hardware Configuration -- stored here for convenience.*/
-+ hwcfg1_data_t hwcfg1;
-+ hwcfg2_data_t hwcfg2;
-+ hwcfg3_data_t hwcfg3;
-+ hwcfg4_data_t hwcfg4;
-+ fifosize_data_t hptxfsiz;
-+
-+ /** Host and Device Configuration -- stored here for convenience.*/
-+ hcfg_data_t hcfg;
-+ dcfg_data_t dcfg;
-+
-+ /** The operational State, during transations
-+ * (a_host>>a_peripherial and b_device=>b_host) this may not
-+ * match the core but allows the software to determine
-+ * transitions.
-+ */
-+ uint8_t op_state;
-+
-+ /**
-+ * Set to 1 if the HCD needs to be restarted on a session request
-+ * interrupt. This is required if no connector ID status change has
-+ * occurred since the HCD was last disconnected.
-+ */
-+ uint8_t restart_hcd_on_session_req;
-+
-+ /** HCD callbacks */
-+ /** A-Device is a_host */
-+#define A_HOST (1)
-+ /** A-Device is a_suspend */
-+#define A_SUSPEND (2)
-+ /** A-Device is a_peripherial */
-+#define A_PERIPHERAL (3)
-+ /** B-Device is operating as a Peripheral. */
-+#define B_PERIPHERAL (4)
-+ /** B-Device is operating as a Host. */
-+#define B_HOST (5)
-+
-+ /** HCD callbacks */
-+ struct dwc_otg_cil_callbacks *hcd_cb;
-+ /** PCD callbacks */
-+ struct dwc_otg_cil_callbacks *pcd_cb;
-+
-+ /** Device mode Periodic Tx FIFO Mask */
-+ uint32_t p_tx_msk;
-+ /** Device mode Periodic Tx FIFO Mask */
-+ uint32_t tx_msk;
-+
-+ /** Workqueue object used for handling several interrupts */
-+ dwc_workq_t *wq_otg;
-+
-+ /** Timer object used for handling "Wakeup Detected" Interrupt */
-+ dwc_timer_t *wkp_timer;
-+ /** This arrays used for debug purposes for DEV OUT NAK enhancement */
-+ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
-+ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
-+ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
-+#ifdef DEBUG
-+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
-+
-+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
-+ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
-+
-+ uint32_t hfnum_7_samples;
-+ uint64_t hfnum_7_frrem_accum;
-+ uint32_t hfnum_0_samples;
-+ uint64_t hfnum_0_frrem_accum;
-+ uint32_t hfnum_other_samples;
-+ uint64_t hfnum_other_frrem_accum;
-+#endif
-+
-+#ifdef DWC_UTE_CFI
-+ uint16_t pwron_rxfsiz;
-+ uint16_t pwron_gnptxfsiz;
-+ uint16_t pwron_txfsiz[15];
-+
-+ uint16_t init_rxfsiz;
-+ uint16_t init_gnptxfsiz;
-+ uint16_t init_txfsiz[15];
-+#endif
-+
-+ /** Lx state of device */
-+ dwc_otg_lx_state_e lx_state;
-+
-+ /** Saved Core Global registers */
-+ struct dwc_otg_global_regs_backup *gr_backup;
-+ /** Saved Host registers */
-+ struct dwc_otg_host_regs_backup *hr_backup;
-+ /** Saved Device registers */
-+ struct dwc_otg_dev_regs_backup *dr_backup;
-+
-+ /** Power Down Enable */
-+ uint32_t power_down;
-+
-+ /** ADP support Enable */
-+ uint32_t adp_enable;
-+
-+ /** ADP structure object */
-+ dwc_otg_adp_t adp;
-+
-+ /** hibernation/suspend flag */
-+ int hibernation_suspend;
-+
-+ /** Device mode extended hibernation flag */
-+ int xhib;
-+
-+ /** OTG revision supported */
-+ uint32_t otg_ver;
-+
-+ /** OTG status flag used for HNP polling */
-+ uint8_t otg_sts;
-+
-+ /** Pointer to either hcd->lock or pcd->lock */
-+ dwc_spinlock_t *lock;
-+
-+ /** Start predict NextEP based on Learning Queue if equal 1,
-+ * also used as counter of disabled NP IN EP's */
-+ uint8_t start_predict;
-+
-+ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
-+ * active, 0xff otherwise */
-+ uint8_t nextep_seq[MAX_EPS_CHANNELS];
-+
-+ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
-+ uint8_t first_in_nextep_seq;
-+
-+ /** Frame number while entering to ISR - needed for ISOCs **/
-+ uint32_t frame_num;
-+
-+};
-+
-+#ifdef DEBUG
-+/*
-+ * This function is called when transfer is timed out.
-+ */
-+extern void hc_xfer_timeout(void *ptr);
-+#endif
-+
-+/*
-+ * This function is called when transfer is timed out on endpoint.
-+ */
-+extern void ep_xfer_timeout(void *ptr);
-+
-+/*
-+ * The following functions are functions for works
-+ * using during handling some interrupts
-+ */
-+extern void w_conn_id_status_change(void *p);
-+
-+extern void w_wakeup_detected(void *p);
-+
-+/** Saves global register values into system memory. */
-+extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
-+/** Saves device register values into system memory. */
-+extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
-+/** Saves host register values into system memory. */
-+extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
-+/** Restore global register values. */
-+extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
-+/** Restore host register values. */
-+extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
-+/** Restore device register values. */
-+extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup);
-+extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
-+extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
-+ int is_host);
-+
-+extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int restore_mode, int reset);
-+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+ int rem_wakeup, int reset);
-+
-+/*
-+ * The following functions support initialization of the CIL driver component
-+ * and the DWC_otg controller.
-+ */
-+extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
-+
-+/** @name Device CIL Functions
-+ * The following functions support managing the DWC_otg controller in device
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
-+ uint32_t * _dest);
-+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep, int _dma);
-+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
-+ dwc_ep_t * _ep);
-+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+#ifdef DWC_EN_ISOC
-+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep);
-+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep);
-+#endif /* DWC_EN_ISOC */
-+/**@}*/
-+
-+/** @name Host CIL Functions
-+ * The following functions support managing the DWC_otg controller in host
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
-+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc);
-+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc);
-+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
-+ dwc_hc_t * _hc);
-+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
-+ dwc_hc_t * hc);
-+
-+extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
-+
-+/* Macro used to clear one channel interrupt */
-+#define clear_hc_int(_hc_regs_, _intr_) \
-+do { \
-+ hcint_data_t hcint_clear = {.d32 = 0}; \
-+ hcint_clear.b._intr_ = 1; \
-+ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
-+} while (0)
-+
-+/*
-+ * Macro used to disable one channel interrupt. Channel interrupts are
-+ * disabled when the channel is halted or released by the interrupt handler.
-+ * There is no need to handle further interrupts of that type until the
-+ * channel is re-assigned. In fact, subsequent handling may cause crashes
-+ * because the channel structures are cleaned up when the channel is released.
-+ */
-+#define disable_hc_int(_hc_regs_, _intr_) \
-+do { \
-+ hcintmsk_data_t hcintmsk = {.d32 = 0}; \
-+ hcintmsk.b._intr_ = 1; \
-+ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
-+} while (0)
-+
-+/**
-+ * This function Reads HPRT0 in preparation to modify. It keeps the
-+ * WC bits 0 so that if they are read as 1, they won't clear when you
-+ * write it back
-+ */
-+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
-+{
-+ hprt0_data_t hprt0;
-+ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
-+ hprt0.b.prtena = 0;
-+ hprt0.b.prtconndet = 0;
-+ hprt0.b.prtenchng = 0;
-+ hprt0.b.prtovrcurrchng = 0;
-+ return hprt0.d32;
-+}
-+
-+/**@}*/
-+
-+/** @name Common CIL Functions
-+ * The following functions support managing the DWC_otg controller in either
-+ * device or host mode.
-+ */
-+/**@{*/
-+
-+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
-+ uint8_t * dest, uint16_t bytes);
-+
-+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
-+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
-+{
-+ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
-+ DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function returns the OTG Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
-+{
-+ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the IN endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
-+ core_if)
-+{
-+
-+ uint32_t v;
-+
-+ if (core_if->multiproc_int_enable) {
-+ v = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->deachint) &
-+ DWC_READ_REG32(&core_if->
-+ dev_if->dev_global_regs->deachintmsk);
-+ } else {
-+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ }
-+ return (v & 0xffff);
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the OUT endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
-+ core_if)
-+{
-+ uint32_t v;
-+
-+ if (core_if->multiproc_int_enable) {
-+ v = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->deachint) &
-+ DWC_READ_REG32(&core_if->
-+ dev_if->dev_global_regs->deachintmsk);
-+ } else {
-+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+ }
-+
-+ return ((v & 0xffff0000) >> 16);
-+}
-+
-+/**
-+ * This function returns the Device IN EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ uint32_t v, msk, emp;
-+
-+ if (core_if->multiproc_int_enable) {
-+ msk =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->diepeachintmsk[ep->num]);
-+ emp =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->dtknqr4_fifoemptymsk);
-+ msk |= ((emp >> ep->num) & 0x1) << 7;
-+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+ } else {
-+ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
-+ emp =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->dtknqr4_fifoemptymsk);
-+ msk |= ((emp >> ep->num) & 0x1) << 7;
-+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+ }
-+
-+ return v;
-+}
-+
-+/**
-+ * This function returns the Device OUT EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
-+ _core_if, dwc_ep_t * _ep)
-+{
-+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
-+ uint32_t v;
-+ doepmsk_data_t msk = {.d32 = 0 };
-+
-+ if (_core_if->multiproc_int_enable) {
-+ msk.d32 =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->doepeachintmsk[_ep->num]);
-+ if (_core_if->pti_enh_enable) {
-+ msk.b.pktdrpsts = 1;
-+ }
-+ v = DWC_READ_REG32(&dev_if->
-+ out_ep_regs[_ep->num]->doepint) & msk.d32;
-+ } else {
-+ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
-+ if (_core_if->pti_enh_enable) {
-+ msk.b.pktdrpsts = 1;
-+ }
-+ v = DWC_READ_REG32(&dev_if->
-+ out_ep_regs[_ep->num]->doepint) & msk.d32;
-+ }
-+ return v;
-+}
-+
-+/**
-+ * This function returns the Host All Channel Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
-+ _core_if)
-+{
-+ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
-+}
-+
-+static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
-+ _core_if, dwc_hc_t * _hc)
-+{
-+ return (DWC_READ_REG32
-+ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
-+}
-+
-+/**
-+ * This function returns the mode of the operation, host or device.
-+ *
-+ * @return 0 - Device Mode, 1 - Host Mode
-+ */
-+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
-+{
-+ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
-+}
-+
-+/**@}*/
-+
-+/**
-+ * DWC_otg CIL callback structure. This structure allows the HCD and
-+ * PCD to register functions used for starting and stopping the PCD
-+ * and HCD for role change on for a DRD.
-+ */
-+typedef struct dwc_otg_cil_callbacks {
-+ /** Start function for role change */
-+ int (*start) (void *_p);
-+ /** Stop Function for role change */
-+ int (*stop) (void *_p);
-+ /** Disconnect Function for role change */
-+ int (*disconnect) (void *_p);
-+ /** Resume/Remote wakeup Function */
-+ int (*resume_wakeup) (void *_p);
-+ /** Suspend function */
-+ int (*suspend) (void *_p);
-+ /** Session Start (SRP) */
-+ int (*session_start) (void *_p);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ /** Sleep (switch to L0 state) */
-+ int (*sleep) (void *_p);
-+#endif
-+ /** Pointer passed to start() and stop() */
-+ void *p;
-+} dwc_otg_cil_callbacks_t;
-+
-+extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
-+ dwc_otg_cil_callbacks_t * _cb,
-+ void *_p);
-+extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
-+ dwc_otg_cil_callbacks_t * _cb,
-+ void *_p);
-+
-+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
-+
-+//////////////////////////////////////////////////////////////////////
-+/** Start the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->start) {
-+ core_if->hcd_cb->start(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Stop the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->stop) {
-+ core_if->hcd_cb->stop(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Disconnect the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
-+ core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Inform the HCD the a New Session has begun. Helper function for
-+ * using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
-+ core_if->hcd_cb->session_start(core_if->hcd_cb->p);
-+ }
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * Inform the HCD about LPM sleep.
-+ * Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
-+ core_if->hcd_cb->sleep(core_if->hcd_cb->p);
-+ }
-+}
-+#endif
-+
-+/** Resume the HCD. Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
-+ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
-+ }
-+}
-+
-+/** Start the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->start) {
-+ core_if->pcd_cb->start(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/** Stop the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->stop) {
-+ core_if->pcd_cb->stop(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/** Suspend the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
-+ core_if->pcd_cb->suspend(core_if->pcd_cb->p);
-+ }
-+}
-+
-+/** Resume the PCD. Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
-+{
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+}
-+
-+//////////////////////////////////////////////////////////////////////
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,1594 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
-+ * $Revision: #32 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * This file contains the Common Interrupt handlers.
-+ */
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_hcd.h"
-+
-+#ifdef DEBUG
-+inline const char *op_state_str(dwc_otg_core_if_t * core_if)
-+{
-+ return (core_if->op_state == A_HOST ? "a_host" :
-+ (core_if->op_state == A_SUSPEND ? "a_suspend" :
-+ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
-+ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
-+ (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
-+}
-+#endif
-+
-+/** This function will log a debug message
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
-+ dwc_otg_mode(core_if) ? "Host" : "Device");
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.modemismatch = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This function handles the OTG Interrupts. It reads the OTG
-+ * Interrupt Register (GOTGINT) to determine what interrupt has
-+ * occurred.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gotgint_data_t gotgint;
-+ gotgctl_data_t gotgctl;
-+ gintmsk_data_t gintmsk;
-+ gpwrdn_data_t gpwrdn;
-+
-+ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
-+ op_state_str(core_if));
-+
-+ if (gotgint.b.sesenddet) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Session End Detected++ (%s)\n",
-+ op_state_str(core_if));
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+
-+ if (core_if->op_state == B_HOST) {
-+ cil_pcd_start(core_if);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else {
-+ /* If not B_HOST and Device HNP still set. HNP
-+ * Did not succeed!*/
-+ if (gotgctl.b.devhnpen) {
-+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
-+ __DWC_ERROR("Device Not Connected/Responding!\n");
-+ }
-+
-+ /* If Session End Detected the B-Cable has
-+ * been disconnected. */
-+ /* Reset PCD and Gadget driver to a
-+ * clean state. */
-+ core_if->lx_state = DWC_OTG_L0;
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ if (core_if->adp_enable) {
-+ if (core_if->power_down == 2) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, gpwrdn.d32, 0);
-+ }
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ dwc_otg_adp_sense_start(core_if);
-+ }
-+ }
-+
-+ gotgctl.d32 = 0;
-+ gotgctl.b.devhnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+ }
-+ if (gotgint.b.sesreqsucstschng) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Session Reqeust Success Status Change++\n");
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+ if (gotgctl.b.sesreqscs) {
-+
-+ if ((core_if->core_params->phy_type ==
-+ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
-+ core_if->srp_success = 1;
-+ } else {
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_resume(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ /* Clear Session Request */
-+ gotgctl.d32 = 0;
-+ gotgctl.b.sesreq = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+ }
-+ }
-+ }
-+ if (gotgint.b.hstnegsucstschng) {
-+ /* Print statements during the HNP interrupt handling
-+ * can cause it to fail.*/
-+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+ /* WA for 3.00a- HW is not setting cur_mode, even sometimes
-+ * this does not help*/
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ dwc_udelay(100);
-+ if (gotgctl.b.hstnegscs) {
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ core_if->op_state = B_HOST;
-+ /*
-+ * Need to disable SOF interrupt immediately.
-+ * When switching from device to host, the PCD
-+ * interrupt handler won't handle the
-+ * interrupt if host mode is already set. The
-+ * HCD interrupt handler won't get called if
-+ * the HCD state is HALT. This means that the
-+ * interrupt does not get handled and Linux
-+ * complains loudly.
-+ */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk,
-+ gintmsk.d32, 0);
-+ /* Call callback function with spin lock released */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ cil_hcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = B_HOST;
-+ }
-+ } else {
-+ gotgctl.d32 = 0;
-+ gotgctl.b.hnpreq = 1;
-+ gotgctl.b.devhnpen = 1;
-+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
-+ __DWC_ERROR("Device Not Connected/Responding\n");
-+ }
-+ }
-+ if (gotgint.b.hstnegdet) {
-+ /* The disconnect interrupt is set at the same time as
-+ * Host Negotiation Detected. During the mode
-+ * switch all interrupts are cleared so the disconnect
-+ * interrupt handler will not get executed.
-+ */
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "Host Negotiation Detected++ (%s)\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" :
-+ "Device"));
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
-+ core_if->op_state);
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_disconnect(core_if);
-+ cil_pcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = A_PERIPHERAL;
-+ } else {
-+ /*
-+ * Need to disable SOF interrupt immediately. When
-+ * switching from device to host, the PCD interrupt
-+ * handler won't handle the interrupt if host mode is
-+ * already set. The HCD interrupt handler won't get
-+ * called if the HCD state is HALT. This means that
-+ * the interrupt does not get handled and Linux
-+ * complains loudly.
-+ */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ cil_hcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = A_HOST;
-+ }
-+ }
-+ if (gotgint.b.adevtoutchng) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+ "A-Device Timeout Change++\n");
-+ }
-+ if (gotgint.b.debdone) {
-+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
-+ }
-+
-+ /* Clear GOTGINT */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
-+
-+ return 1;
-+}
-+
-+void w_conn_id_status_change(void *p)
-+{
-+ dwc_otg_core_if_t *core_if = p;
-+ uint32_t count = 0;
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
-+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
-+
-+ /* B-Device connector (Device Mode) */
-+ if (gotgctl.b.conidsts) {
-+ /* Wait for switch to device mode. */
-+ while (!dwc_otg_is_device_mode(core_if)) {
-+ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" :
-+ "Peripheral"));
-+ dwc_mdelay(100);
-+ if (++count > 10000)
-+ break;
-+ }
-+ DWC_ASSERT(++count < 10000,
-+ "Connection id status change timed out");
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ } else {
-+ /* A-Device connector (Host Mode) */
-+ while (!dwc_otg_is_host_mode(core_if)) {
-+ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" :
-+ "Peripheral"));
-+ dwc_mdelay(100);
-+ if (++count > 10000)
-+ break;
-+ }
-+ DWC_ASSERT(++count < 10000,
-+ "Connection id status change timed out");
-+ core_if->op_state = A_HOST;
-+ /*
-+ * Initialize the Core for Host mode.
-+ */
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+}
-+
-+/**
-+ * This function handles the Connector ID Status Change Interrupt. It
-+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
-+ * is a Device to Host Mode transition or a Host Mode to Device
-+ * Transition.
-+ *
-+ * This only occurs when the cable is connected/removed from the PHY
-+ * connector.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
-+{
-+
-+ /*
-+ * Need to disable SOF interrupt immediately. If switching from device
-+ * to host, the PCD interrupt handler won't handle the interrupt if
-+ * host mode is already set. The HCD interrupt handler won't get
-+ * called if the HCD state is HALT. This means that the interrupt does
-+ * not get handled and Linux complains loudly.
-+ */
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ gintsts_data_t gintsts = {.d32 = 0 };
-+
-+ gintmsk.b.sofintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+ DWC_DEBUGPL(DBG_CIL,
-+ " ++Connector ID Status Change Interrupt++ (%s)\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
-+
-+ DWC_SPINUNLOCK(core_if->lock);
-+
-+ /*
-+ * Need to schedule a work, as there are possible DELAY function calls
-+ * Release lock before scheduling workq as it holds spinlock during scheduling
-+ */
-+
-+ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
-+ core_if, "connection id status change");
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ /* Set flag and clear interrupt */
-+ gintsts.b.conidstschng = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device is initiating the Session
-+ * Request Protocol to request the host to turn on bus power so a new
-+ * session can begin. The handler responds by turning on bus power. If
-+ * the DWC_otg controller is in low power mode, the handler brings the
-+ * controller out of low power mode before turning on bus power.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+#ifndef DWC_HOST_ONLY
-+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_PRINTF("SRP: Device mode\n");
-+ } else {
-+ hprt0_data_t hprt0;
-+ DWC_PRINTF("SRP: Host mode\n");
-+
-+ /* Turn on the port power bit. */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Start the Connection timer. So a message can be displayed
-+ * if connect does not occur within 10 seconds. */
-+ cil_hcd_session_start(core_if);
-+ }
-+#endif
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.sessreqintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+void w_wakeup_detected(void *p)
-+{
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
-+ /*
-+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
-+ * so that OPT tests pass with all PHYs).
-+ */
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+#if 0
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ /* Restart the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ dwc_udelay(10);
-+#endif //0
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
-+// dwc_mdelay(70);
-+ hprt0.b.prtres = 0; /* Resume */
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
-+ DWC_READ_REG32(core_if->host_if->hprt0));
-+
-+ cil_hcd_resume(core_if);
-+
-+ /** Change to L0 state*/
-+ core_if->lx_state = DWC_OTG_L0;
-+}
-+
-+/**
-+ * This interrupt indicates that the DWC_otg controller has detected a
-+ * resume or remote wakeup sequence. If the DWC_otg controller is in
-+ * low power mode, the handler must brings the controller out of low
-+ * power mode. The controller automatically begins resume
-+ * signaling. The handler schedules a time to stop resume signaling.
-+ */
-+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "++Resume and Remote Wakeup Detected Interrupt++\n");
-+
-+ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
-+ dsts));
-+ if (core_if->lx_state == DWC_OTG_L2) {
-+#ifdef PARTIAL_POWER_DOWN
-+ if (core_if->hwcfg4.b.power_optimiz) {
-+ pcgcctl_data_t power = {.d32 = 0 };
-+
-+ power.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
-+ power.d32);
-+
-+ power.b.stoppclk = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+ power.b.pwrclmp = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+ power.b.rstpdwnmodule = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+ }
-+#endif
-+ /* Clear the Remote Wakeup Signaling */
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, dctl.d32, 0);
-+
-+ DWC_SPINUNLOCK(core_if->lock);
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+ DWC_SPINLOCK(core_if->lock);
-+ } else {
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+ }
-+ /** Change to L0 state*/
-+ core_if->lx_state = DWC_OTG_L0;
-+ } else {
-+ if (core_if->lx_state != DWC_OTG_L1) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+
-+ /* Restart the Phy Clock */
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
-+ } else {
-+ /** Change to L0 state*/
-+ core_if->lx_state = DWC_OTG_L0;
-+ }
-+ }
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.wkupintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * Device disconnect.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
-+{
-+ gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
-+ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps*/
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ if (gpwrdn_temp.b.idsts) {
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ } else {
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * remote wakeup sequence.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_ANY,
-+ "++Powerdown Remote Wakeup Detected Interrupt++\n");
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (gpwrdn.b.idsts) { // Device Mode
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ dwc_otg_device_hibernation_restore(core_if, 0, 0);
-+ }
-+ } else {
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ dwc_otg_host_hibernation_restore(core_if, 1, 0);
-+ }
-+ }
-+ return 1;
-+}
-+
-+static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (core_if->power_down == 2) {
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /*Indicates that we are exiting from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
-+ if (gpwrdn.b.dis_vbus == 1) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ }
-+
-+ if (gpwrdn_temp.b.idsts) {
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ } else {
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+ }
-+ }
-+
-+ if (core_if->adp_enable) {
-+ uint8_t is_host = 0;
-+ DWC_SPINUNLOCK(core_if->lock);
-+ /* Change the core_if's lock to hcd/pcd lock depend on mode? */
-+#ifndef DWC_HOST_ONLY
-+ if (gpwrdn_temp.b.idsts)
-+ core_if->lock = otg_dev->pcd->lock;
-+#endif
-+#ifndef DWC_DEVICE_ONLY
-+ if (!gpwrdn_temp.b.idsts) {
-+ core_if->lock = otg_dev->hcd->lock;
-+ is_host = 1;
-+ }
-+#endif
-+ DWC_PRINTF("RESTART ADP\n");
-+ if (core_if->adp.probe_enabled)
-+ dwc_otg_adp_probe_stop(core_if);
-+ if (core_if->adp.sense_enabled)
-+ dwc_otg_adp_sense_stop(core_if);
-+ if (core_if->adp.sense_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+ if (core_if->adp.vbuson_timer_started)
-+ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
-+ core_if->adp.probe_timer_values[0] = -1;
-+ core_if->adp.probe_timer_values[1] = -1;
-+ core_if->adp.sense_timer_started = 0;
-+ core_if->adp.vbuson_timer_started = 0;
-+ core_if->adp.probe_counter = 0;
-+ core_if->adp.gpwrdn = 0;
-+
-+ /* Disable PMU and restart ADP */
-+ gpwrdn_temp.d32 = 0;
-+ gpwrdn_temp.b.pmuactv = 1;
-+ gpwrdn_temp.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ DWC_PRINTF("Check point 1\n");
-+ dwc_mdelay(110);
-+ dwc_otg_adp_start(core_if, is_host);
-+ DWC_SPINLOCK(core_if->lock);
-+ }
-+
-+
-+ return 1;
-+}
-+
-+static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ int32_t otg_cap_param = core_if->core_params->otg_cap;
-+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (core_if->power_down == 2) {
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+
-+ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
-+ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
-+ gpwrdn.b.bsessvld == 0) {
-+ /* Save gpwrdn register for further usage if stschng interrupt */
-+ core_if->gr_backup->gpwrdn_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
-+ return 1;
-+ }
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /*Indicates that we are exiting from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
-+ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
-+ /*
-+ * Initiate SRP after initial ADP probe.
-+ */
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+ }
-+
-+ return 1;
-+}
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * status change either on IDDIG or BSessVld.
-+ */
-+static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
-+{
-+ int retval;
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (core_if->power_down == 2) {
-+ if (core_if->hibernation_suspend <= 0) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ } else
-+ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
-+
-+ } else {
-+ gpwrdn_temp.d32 = core_if->adp.gpwrdn;
-+ }
-+
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
-+ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
-+ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
-+ retval = dwc_otg_handle_pwrdn_session_change(core_if);
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * SRP.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return 1;
-+ }
-+#ifdef DWC_DEV_SRPCAP
-+ if (core_if->pwron_timer_started) {
-+ core_if->pwron_timer_started = 0;
-+ DWC_TIMER_CANCEL(core_if->pwron_timer);
-+ }
-+#endif
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Indicates that we are exiting from hibernation */
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Programm Disable VBUS to 0 */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /*Initialize the core as Host */
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+
-+ return 1;
-+}
-+
-+/** This interrupt indicates that restore command after Hibernation
-+ * was completed by the core. */
-+int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
-+{
-+ pcgcctl_data_t pcgcctl;
-+ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
-+
-+ //TODO De-assert restore signal. 8.a
-+ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+ if (pcgcctl.b.restoremode == 1) {
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ /*
-+ * If restore mode is Remote Wakeup,
-+ * unmask Remote Wakeup interrupt.
-+ */
-+ gintmsk.b.wkupintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ 0, gintmsk.d32);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device has been disconnected from
-+ * the root port.
-+ */
-+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
-+ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
-+ op_state_str(core_if));
-+
-+/** @todo Consolidate this if statement. */
-+#ifndef DWC_HOST_ONLY
-+ if (core_if->op_state == B_HOST) {
-+ /* If in device mode Disconnect and stop the HCD, then
-+ * start the PCD. */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_disconnect(core_if);
-+ cil_pcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else if (dwc_otg_is_device_mode(core_if)) {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gotgctl.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+ if (gotgctl.b.hstsethnpen == 1) {
-+ /* Do nothing, if HNP in process the OTG
-+ * interrupt "Host Negotiation Detected"
-+ * interrupt will do the mode switch.
-+ */
-+ } else if (gotgctl.b.devhnpen == 0) {
-+ /* If in device mode Disconnect and stop the HCD, then
-+ * start the PCD. */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_hcd_disconnect(core_if);
-+ cil_pcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = B_PERIPHERAL;
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
-+ }
-+ } else {
-+ if (core_if->op_state == A_HOST) {
-+ /* A-Cable still connected but device disconnected. */
-+ cil_hcd_disconnect(core_if);
-+ if (core_if->adp_enable) {
-+ gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+ cil_hcd_stop(core_if);
-+ /* Enable Power Down Logic */
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_otg_adp_probe_start(core_if);
-+
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32
-+ (&core_if->core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+ }
-+ }
-+ }
-+ }
-+#endif
-+ /* Change to L3(OFF) state */
-+ core_if->lx_state = DWC_OTG_L3;
-+
-+ gintsts.d32 = 0;
-+ gintsts.b.disconnect = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that SUSPEND state has been detected on
-+ * the USB.
-+ *
-+ * For HNP the USB Suspend interrupt signals the change from
-+ * "a_peripheral" to "a_host".
-+ *
-+ * When power management is enabled the core will be put in low power
-+ * mode.
-+ */
-+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ gintsts_data_t gintsts;
-+ dcfg_data_t dcfg;
-+
-+ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ /* Check the Device status register to determine if the Suspend
-+ * state is active. */
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
-+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
-+ "HWCFG4.power Optimize=%d\n",
-+ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
-+
-+#ifdef PARTIAL_POWER_DOWN
-+/** @todo Add a module parameter for power management. */
-+
-+ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
-+ pcgcctl_data_t power = {.d32 = 0 };
-+ DWC_DEBUGPL(DBG_CIL, "suspend\n");
-+
-+ power.b.pwrclmp = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+ power.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
-+
-+ power.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
-+
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
-+ }
-+#endif
-+ /* PCD callback for suspend. Release the lock inside of callback function */
-+ cil_pcd_suspend(core_if);
-+ if (core_if->power_down == 2)
-+ {
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
-+ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
-+
-+ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+
-+ /* Change to L2(suspend) state */
-+ core_if->lx_state = DWC_OTG_L2;
-+
-+ /* Clear interrupt in gintsts */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, gintsts.d32);
-+ DWC_PRINTF("Start of hibernation completed\n");
-+ dwc_otg_save_global_regs(core_if);
-+ dwc_otg_save_dev_regs(core_if);
-+
-+ gusbcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->
-+ gusbcfg);
-+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ /* Suspend the Phy Clock */
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ } else {
-+ /* UTMI+ Interface */
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ }
-+
-+ /* Set flag to indicate that we are in hibernation */
-+ core_if->hibernation_suspend = 1;
-+ /* Enable interrupts from wake up logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Unmask device mode interrupts in GPWRDN */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.rst_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ gpwrdn.b.sts_chngint_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Enable Power Down Clamp */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Switch off VDD */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ /* Save gpwrdn register for further usage if stschng interrupt */
-+ core_if->gr_backup->gpwrdn_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ DWC_PRINTF("Hibernation completed\n");
-+
-+ return 1;
-+ }
-+ } else if (core_if->power_down == 3) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
-+ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
-+
-+ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
-+ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
-+ core_if->xhib = 1;
-+
-+ /* Clear interrupt in gintsts */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, gintsts.d32);
-+
-+ dwc_otg_save_global_regs(core_if);
-+ dwc_otg_save_dev_regs(core_if);
-+
-+ /* Wait for 10 PHY clocks */
-+ dwc_udelay(10);
-+
-+ /* Program GPIO register while entering to xHib */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
-+
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.extnd_hiber_pwrclmp = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.extnd_hiber_switch = 1;
-+ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
-+
-+ return 1;
-+ }
-+ }
-+ } else {
-+ if (core_if->op_state == A_PERIPHERAL) {
-+ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
-+ /* Clear the a_peripheral flag, back to a_host. */
-+ DWC_SPINUNLOCK(core_if->lock);
-+ cil_pcd_stop(core_if);
-+ cil_hcd_start(core_if);
-+ DWC_SPINLOCK(core_if->lock);
-+ core_if->op_state = A_HOST;
-+ }
-+ }
-+
-+ /* Change to L2(suspend) state */
-+ core_if->lx_state = DWC_OTG_L2;
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbsuspend = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+
-+ dwc_udelay(10);
-+
-+ /* Program GPIO register while entering to xHib */
-+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
-+
-+ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
-+ pcgcctl.b.extnd_hiber_pwrclmp = 0;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
-+ gpwrdn.b.restore = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ restore_lpm_i2c_regs(core_if);
-+
-+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+ pcgcctl.b.max_xcvrselect = 1;
-+ pcgcctl.b.ess_reg_restored = 0;
-+ pcgcctl.b.extnd_hiber_switch = 0;
-+ pcgcctl.b.extnd_hiber_pwrclmp = 0;
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+
-+ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
-+ gahbcfg.b.glblintrmsk = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+ core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+ core_if->dr_backup->dcfg);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+ pcgcctl.b.max_xcvrselect = 1;
-+ pcgcctl.d32 |= 0x608;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+ dwc_udelay(10);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+ pcgcctl.b.max_xcvrselect = 1;
-+ pcgcctl.b.ess_reg_restored = 1;
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ pcgcctl.b.rstpdwnmodule = 1;
-+ pcgcctl.b.restoremode = 1;
-+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+
-+ return 1;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * This function hadles LPM transaction received interrupt.
-+ */
-+static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ gintsts_data_t gintsts;
-+
-+ if (!core_if->core_params->lpm_enable) {
-+ DWC_PRINTF("Unexpected LPM interrupt\n");
-+ }
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
-+
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ cil_hcd_sleep(core_if);
-+ } else {
-+ lpmcfg.b.hird_thres |= (1 << 4);
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+ }
-+
-+ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
-+ dwc_udelay(10);
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.prt_sleep_sts) {
-+ /* Save the current state */
-+ core_if->lx_state = DWC_OTG_L1;
-+ }
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.lpmtranrcvd = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+ return 1;
-+}
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
-+{
-+ gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+ gintmsk_data_t gintmsk_common = {.d32 = 0 };
-+ gintmsk_common.b.wkupintr = 1;
-+ gintmsk_common.b.sessreqintr = 1;
-+ gintmsk_common.b.conidstschng = 1;
-+ gintmsk_common.b.otgintr = 1;
-+ gintmsk_common.b.modemismatch = 1;
-+ gintmsk_common.b.disconnect = 1;
-+ gintmsk_common.b.usbsuspend = 1;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ gintmsk_common.b.lpmtranrcvd = 1;
-+#endif
-+ gintmsk_common.b.restoredone = 1;
-+ if(dwc_otg_is_device_mode(core_if))
-+ {
-+ /** @todo: The port interrupt occurs while in device
-+ * mode. Added code to CIL to clear the interrupt for now!
-+ */
-+ gintmsk_common.b.portintr = 1;
-+ }
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+ if(fiq_enable) {
-+ local_fiq_disable();
-+ /* Pull in the interrupts that the FIQ has masked */
-+ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
-+ gintmsk.d32 |= gintmsk_common.d32;
-+ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
-+ reenable_gintmsk->d32 = gintmsk.d32;
-+ local_fiq_enable();
-+ }
-+
-+ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
-+
-+#ifdef DEBUG
-+ /* if any common interrupts set */
-+ if (gintsts.d32 & gintmsk_common.d32) {
-+ DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n",
-+ gintsts.d32, gintmsk.d32);
-+ }
-+#endif
-+ if (!fiq_enable){
-+ if (gahbcfg.b.glblintrmsk)
-+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+ else
-+ return 0;
-+ } else {
-+ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
-+ * Can't trust the global interrupt mask bit in this case.
-+ */
-+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+ }
-+
-+}
-+
-+/* MACRO for clearing interupt bits in GPWRDN register */
-+#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
-+do { \
-+ gpwrdn_data_t gpwrdn = {.d32=0}; \
-+ gpwrdn.b.__intr = 1; \
-+ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
-+ 0, gpwrdn.d32); \
-+} while (0)
-+
-+/**
-+ * Common interrupt handler.
-+ *
-+ * The common interrupts are those that occur in both Host and Device mode.
-+ * This handler handles the following interrupts:
-+ * - Mode Mismatch Interrupt
-+ * - Disconnect Interrupt
-+ * - OTG Interrupt
-+ * - Connector ID Status Change Interrupt
-+ * - Session Request Interrupt.
-+ * - Resume / Remote Wakeup Detected Interrupt.
-+ * - LPM Transaction Received Interrupt
-+ * - ADP Transaction Received Interrupt
-+ *
-+ */
-+int32_t dwc_otg_handle_common_intr(void *dev)
-+{
-+ int retval = 0;
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ dwc_otg_device_t *otg_dev = dev;
-+ dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+ if (dwc_otg_is_device_mode(core_if))
-+ core_if->frame_num = dwc_otg_get_frame_number(core_if);
-+
-+ if (core_if->lock)
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ if (core_if->power_down == 3 && core_if->xhib == 1) {
-+ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
-+ retval |= dwc_otg_handle_xhib_exit_intr(core_if);
-+ core_if->xhib = 2;
-+ if (core_if->lock)
-+ DWC_SPINUNLOCK(core_if->lock);
-+
-+ return retval;
-+ }
-+
-+ if (core_if->hibernation_suspend <= 0) {
-+ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
-+ * of this handler - god only knows why it's done like this
-+ */
-+ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
-+
-+ if (gintsts.b.modemismatch) {
-+ retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
-+ }
-+ if (gintsts.b.otgintr) {
-+ retval |= dwc_otg_handle_otg_intr(core_if);
-+ }
-+ if (gintsts.b.conidstschng) {
-+ retval |=
-+ dwc_otg_handle_conn_id_status_change_intr(core_if);
-+ }
-+ if (gintsts.b.disconnect) {
-+ retval |= dwc_otg_handle_disconnect_intr(core_if);
-+ }
-+ if (gintsts.b.sessreqintr) {
-+ retval |= dwc_otg_handle_session_req_intr(core_if);
-+ }
-+ if (gintsts.b.wkupintr) {
-+ retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
-+ }
-+ if (gintsts.b.usbsuspend) {
-+ retval |= dwc_otg_handle_usb_suspend_intr(core_if);
-+ }
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (gintsts.b.lpmtranrcvd) {
-+ retval |= dwc_otg_handle_lpm_intr(core_if);
-+ }
-+#endif
-+ if (gintsts.b.restoredone) {
-+ gintsts.d32 = 0;
-+ if (core_if->power_down == 2)
-+ core_if->hibernation_suspend = -1;
-+ else if (core_if->power_down == 3 && core_if->xhib == 2) {
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->
-+ gintsts, 0xFFFFFFFF);
-+
-+ DWC_DEBUGPL(DBG_ANY,
-+ "RESTORE DONE generated\n");
-+
-+ gpwrdn.b.restore = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ pcgcctl.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
-+ dwc_udelay(50);
-+
-+ dctl.b.pwronprgdone = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ dwc_udelay(10);
-+
-+ dwc_otg_restore_global_regs(core_if);
-+ dwc_otg_restore_dev_regs(core_if, 0);
-+
-+ dctl.d32 = 0;
-+ dctl.b.pwronprgdone = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+ dwc_udelay(10);
-+
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.enbl_extnd_hiber = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+ /* The core will be in ON STATE */
-+ core_if->lx_state = DWC_OTG_L0;
-+ core_if->xhib = 0;
-+
-+ DWC_SPINUNLOCK(core_if->lock);
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+ DWC_SPINLOCK(core_if->lock);
-+
-+ }
-+
-+ gintsts.b.restoredone = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
-+ DWC_PRINTF(" --Restore done interrupt received-- \n");
-+ retval |= 1;
-+ }
-+ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
-+ /* The port interrupt occurs while in device mode with HPRT0
-+ * Port Enable/Disable.
-+ */
-+ gintsts.d32 = 0;
-+ gintsts.b.portintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
-+ retval |= 1;
-+ gintmsk_reenable.b.portintr = 1;
-+
-+ }
-+ /* Did we actually handle anything? if so, unmask the interrupt */
-+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
-+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
-+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
-+ if (retval && fiq_enable) {
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
-+ }
-+
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
-+
-+ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, disconn_det);
-+ if (gpwrdn.b.linestate == 0) {
-+ dwc_otg_handle_pwrdn_disconnect_intr(core_if);
-+ } else {
-+ DWC_PRINTF("Disconnect detected while linestate is not 0\n");
-+ }
-+
-+ retval |= 1;
-+ }
-+ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, lnstschng);
-+ /* remote wakeup from hibernation */
-+ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
-+ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
-+ } else {
-+ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
-+ }
-+ retval |= 1;
-+ }
-+ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, rst_det);
-+ if (gpwrdn.b.linestate == 0) {
-+ DWC_PRINTF("Reset detected\n");
-+ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
-+ }
-+ }
-+ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
-+ CLEAR_GPWRDN_INTR(core_if, srp_det);
-+ dwc_otg_handle_pwrdn_srp_intr(core_if);
-+ retval |= 1;
-+ }
-+ }
-+ /* Handle ADP interrupt here */
-+ if (gpwrdn.b.adp_int) {
-+ DWC_PRINTF("ADP interrupt\n");
-+ CLEAR_GPWRDN_INTR(core_if, adp_int);
-+ dwc_otg_adp_handle_intr(core_if);
-+ retval |= 1;
-+ }
-+ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
-+ DWC_PRINTF("STS CHNG interrupt asserted\n");
-+ CLEAR_GPWRDN_INTR(core_if, sts_chngint);
-+ dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
-+
-+ retval |= 1;
-+ }
-+ if (core_if->lock)
-+ DWC_SPINUNLOCK(core_if->lock);
-+ return retval;
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_core_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,705 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
-+ * $Revision: #13 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#if !defined(__DWC_CORE_IF_H__)
-+#define __DWC_CORE_IF_H__
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ * This file defines DWC_OTG Core API
-+ */
-+
-+struct dwc_otg_core_if;
-+typedef struct dwc_otg_core_if dwc_otg_core_if_t;
-+
-+/** Maximum number of Periodic FIFOs */
-+#define MAX_PERIO_FIFOS 15
-+/** Maximum number of Periodic FIFOs */
-+#define MAX_TX_FIFOS 15
-+
-+/** Maximum number of Endpoints/HostChannels */
-+#define MAX_EPS_CHANNELS 16
-+
-+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
-+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
-+
-+extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
-+extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
-+
-+extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
-+
-+/** This function should be called on every hardware interrupt. */
-+extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
-+
-+/** @name OTG Core Parameters */
-+/** @{ */
-+
-+/**
-+ * Specifies the OTG capabilities. The driver will automatically
-+ * detect the value for this parameter if none is specified.
-+ * 0 - HNP and SRP capable (default)
-+ * 1 - SRP Only capable
-+ * 2 - No HNP/SRP capable
-+ */
-+extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
-+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
-+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
-+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
-+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
-+
-+extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
-+#define dwc_param_opt_default 1
-+
-+/**
-+ * Specifies whether to use slave or DMA mode for accessing the data
-+ * FIFOs. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - Slave
-+ * 1 - DMA (default, if available)
-+ */
-+extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dma_enable_default 1
-+
-+/**
-+ * When DMA mode is enabled specifies whether to use
-+ * address DMA or DMA Descritor mode for accessing the data
-+ * FIFOs in device mode. The driver will automatically detect
-+ * the value for this parameter if none is specified.
-+ * 0 - address DMA
-+ * 1 - DMA Descriptor(default, if available)
-+ */
-+extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_dma_desc_enable_default 1
-+#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
-+
-+/** The DMA Burst size (applicable only for External DMA
-+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ */
-+extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dma_burst_size_default 32
-+
-+/**
-+ * Specifies the maximum speed of operation in host and device mode.
-+ * The actual speed depends on the speed of the attached device and
-+ * the value of phy_type. The actual speed depends on the speed of the
-+ * attached device.
-+ * 0 - High Speed (default)
-+ * 1 - Full Speed
-+ */
-+extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
-+#define dwc_param_speed_default 0
-+#define DWC_SPEED_PARAM_HIGH 0
-+#define DWC_SPEED_PARAM_FULL 1
-+
-+/** Specifies whether low power mode is supported when attached
-+ * to a Full Speed or Low Speed device in host mode.
-+ * 0 - Don't support low power mode (default)
-+ * 1 - Support low power mode
-+ */
-+extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
-+ * core_if);
-+#define dwc_param_host_support_fs_ls_low_power_default 0
-+
-+/** Specifies the PHY clock rate in low power mode when connected to a
-+ * Low Speed device in host mode. This parameter is applicable only if
-+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+ * then defaults to 6 MHZ otherwise 48 MHZ.
-+ *
-+ * 0 - 48 MHz
-+ * 1 - 6 MHz
-+ */
-+extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_host_ls_low_power_phy_clk_default 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
-+
-+/**
-+ * 0 - Use cC FIFO size parameters
-+ * 1 - Allow dynamic FIFO sizing (default)
-+ */
-+extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_enable_dynamic_fifo_default 1
-+
-+/** Total number of 4-byte words in the data FIFO memory. This
-+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+ * Tx FIFOs.
-+ * 32 to 32768 (default 8192)
-+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ */
-+extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_data_fifo_size_default 8192
-+#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1064)
-+ */
-+extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_rx_fifo_size_default 1064
-+
-+/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+ * when dynamic FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
-+
-+/** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val, int fifo_num);
-+extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int fifo_num);
-+#define dwc_param_dev_perio_tx_fifo_size_default 256
-+
-+/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_host_rx_fifo_size_default 1024
-+#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+ * when Dynamic FIFO sizing is enabled in the core.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if);
-+//#define dwc_param_host_nperio_tx_fifo_size_default 1024
-+#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
-+ core_if);
-+//#define dwc_param_host_perio_tx_fifo_size_default 1024
-+#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
-+
-+/** The maximum transfer size supported in bytes.
-+ * 2047 to 65,535 (default 65,535)
-+ */
-+extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_max_transfer_size_default 65535
-+
-+/** The maximum number of packets in a transfer.
-+ * 15 to 511 (default 511)
-+ */
-+extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
-+#define dwc_param_max_packet_count_default 511
-+
-+/** The number of host channel registers to use.
-+ * 1 to 16 (default 12)
-+ * Note: The FPGA configuration supports a maximum of 12 host channels.
-+ */
-+extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_host_channels_default 12
-+#define dwc_param_host_channels_default 8 // Broadcom BCM2708
-+
-+/** The number of endpoints in addition to EP0 available for device
-+ * mode operations.
-+ * 1 to 15 (default 6 IN and OUT)
-+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+ * endpoints in addition to EP0.
-+ */
-+extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_endpoints_default 6
-+
-+/**
-+ * Specifies the type of PHY interface to use. By default, the driver
-+ * will automatically detect the phy_type.
-+ *
-+ * 0 - Full Speed PHY
-+ * 1 - UTMI+ (default)
-+ * 2 - ULPI
-+ */
-+extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
-+#define DWC_PHY_TYPE_PARAM_FS 0
-+#define DWC_PHY_TYPE_PARAM_UTMI 1
-+#define DWC_PHY_TYPE_PARAM_ULPI 2
-+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
-+
-+/**
-+ * Specifies the UTMI+ Data Width. This parameter is
-+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+ * PHY_TYPE, this parameter indicates the data width between
-+ * the MAC and the ULPI Wrapper.) Also, this parameter is
-+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+ * to "8 and 16 bits", meaning that the core has been
-+ * configured to work at either data path width.
-+ *
-+ * 8 or 16 bits (default 16)
-+ */
-+extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_phy_utmi_width_default 16
-+#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
-+
-+/**
-+ * Specifies whether the ULPI operates at double or single
-+ * data rate. This parameter is only applicable if PHY_TYPE is
-+ * ULPI.
-+ *
-+ * 0 - single data rate ULPI interface with 8 bit wide data
-+ * bus (default)
-+ * 1 - double data rate ULPI interface with 4 bit wide data
-+ * bus
-+ */
-+extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
-+#define dwc_param_phy_ulpi_ddr_default 0
-+
-+/**
-+ * Specifies whether to use the internal or external supply to
-+ * drive the vbus with a ULPI phy.
-+ */
-+extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
-+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
-+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
-+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
-+
-+/**
-+ * Specifies whether to use the I2Cinterface for full speed PHY. This
-+ * parameter is only applicable if PHY_TYPE is FS.
-+ * 0 - No (default)
-+ * 1 - Yes
-+ */
-+extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_i2c_enable_default 0
-+
-+extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ulpi_fs_ls_default 0
-+
-+extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ts_dline_default 0
-+
-+/**
-+ * Specifies whether dedicated transmit FIFOs are
-+ * enabled for non periodic IN endpoints in device mode
-+ * 0 - No
-+ * 1 - Yes
-+ */
-+extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
-+ core_if);
-+#define dwc_param_en_multiple_tx_fifo_default 1
-+
-+/** Number of 4-byte words in each of the Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num, int32_t val);
-+extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+ int fifo_num);
-+#define dwc_param_dev_tx_fifo_size_default 768
-+
-+/** Thresholding enable flag-
-+ * bit 0 - enable non-ISO Tx thresholding
-+ * bit 1 - enable ISO Tx thresholding
-+ * bit 2 - enable Rx thresholding
-+ */
-+extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
-+#define dwc_param_thr_ctl_default 0
-+
-+/** Thresholding length for Tx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
-+#define dwc_param_tx_thr_length_default 64
-+
-+/** Thresholding length for Rx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
-+#define dwc_param_rx_thr_length_default 64
-+
-+/**
-+ * Specifies whether LPM (Link Power Management) support is enabled
-+ */
-+extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_lpm_enable_default 1
-+
-+/**
-+ * Specifies whether PTI enhancement is enabled
-+ */
-+extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_pti_enable_default 0
-+
-+/**
-+ * Specifies whether MPI enhancement is enabled
-+ */
-+extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_mpi_enable_default 0
-+
-+/**
-+ * Specifies whether ADP capability is enabled
-+ */
-+extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_adp_enable_default 0
-+
-+/**
-+ * Specifies whether IC_USB capability is enabled
-+ */
-+
-+extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ic_usb_cap_default 0
-+
-+extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ahb_thr_ratio_default 0
-+
-+extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
-+#define dwc_param_power_down_default 0
-+
-+extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
-+#define dwc_param_reload_ctl_default 0
-+
-+extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_out_nak_default 0
-+
-+extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
-+#define dwc_param_cont_on_bna_default 0
-+
-+extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
-+ int32_t val);
-+extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ahb_single_default 0
-+
-+extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
-+#define dwc_param_otg_ver_default 0
-+
-+/** @} */
-+
-+/** @name Access to registers and bit-fields */
-+
-+/**
-+ * Dump core registers and SPRAM
-+ */
-+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
-+
-+/**
-+ * Get host negotiation status.
-+ */
-+extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get srp status
-+ */
-+extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Set hnpreq bit in the GOTGCTL register.
-+ */
-+extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get Content of SNPSID register.
-+ */
-+extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get current mode.
-+ * Returns 0 if in device mode, and 1 if in host mode.
-+ */
-+extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of hnpcapable field in the GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of hnpcapable field in the GUSBCFG register
-+ */
-+extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of srpcapable field in the GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of srpcapable field in the GUSBCFG register
-+ */
-+extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of devspeed field in the DCFG register
-+ */
-+extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of devspeed field in the DCFG register
-+ */
-+extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get the value of busconnected field from the HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Gets the device enumeration Speed.
-+ */
-+extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of prtpwr field from the HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of flag indicating core state - hibernated or not
-+ */
-+extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Set value of prtpwr field from the HPRT0 register
-+ */
-+extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of prtsusp field from the HPRT0 regsiter
-+ */
-+extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of prtpwr field from the HPRT0 register
-+ */
-+extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of ModeChTimEn field from the HCFG regsiter
-+ */
-+extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of ModeChTimEn field from the HCFG regsiter
-+ */
-+extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of Fram Interval field from the HFIR regsiter
-+ */
-+extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of Frame Interval field from the HFIR regsiter
-+ */
-+extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Set value of prtres field from the HPRT0 register
-+ *FIXME Remove?
-+ */
-+extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of rmtwkupsig bit in DCTL register
-+ */
-+extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of prt_sleep_sts field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of rem_wkup_en field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of appl_resp field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of appl_resp field from the GLPMCFG register
-+ */
-+extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of hsic_connect field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of hsic_connect field from the GLPMCFG register
-+ */
-+extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of inv_sel_hsic field from the GLPMCFG register.
-+ */
-+extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of inv_sel_hsic field from the GLPMFG register.
-+ */
-+extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/*
-+ * Some functions for accessing registers
-+ */
-+
-+/**
-+ * GOTGCTL register
-+ */
-+extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GRXFSIZ register
-+ */
-+extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GNPTXFSIZ register
-+ */
-+extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GGPIO register
-+ */
-+extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GUID register
-+ */
-+extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GHPTXFSIZE
-+ */
-+extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
-+
-+/** @} */
-+
-+#endif /* __DWC_CORE_IF_H__ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_dbg.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,117 @@
-+/* ==========================================================================
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_DBG_H__
-+#define __DWC_OTG_DBG_H__
-+
-+/** @file
-+ * This file defines debug levels.
-+ * Debugging support vanishes in non-debug builds.
-+ */
-+
-+/**
-+ * The Debug Level bit-mask variable.
-+ */
-+extern uint32_t g_dbg_lvl;
-+/**
-+ * Set the Debug Level variable.
-+ */
-+static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
-+{
-+ uint32_t old = g_dbg_lvl;
-+ g_dbg_lvl = new;
-+ return old;
-+}
-+
-+#define DBG_USER (0x1)
-+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
-+#define DBG_CIL (0x2)
-+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
-+ * messages */
-+#define DBG_CILV (0x20)
-+/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
-+ * messages */
-+#define DBG_PCD (0x4)
-+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
-+ * messages */
-+#define DBG_PCDV (0x40)
-+/** When debug level has the DBG_HCD bit set, display Host debug messages */
-+#define DBG_HCD (0x8)
-+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
-+ * messages */
-+#define DBG_HCDV (0x80)
-+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
-+ * mode. */
-+#define DBG_HCD_URB (0x800)
-+/** When debug level has the DBG_HCDI bit set, display host interrupt
-+ * messages. */
-+#define DBG_HCDI (0x1000)
-+
-+/** When debug level has any bit set, display debug messages */
-+#define DBG_ANY (0xFF)
-+
-+/** All debug messages off */
-+#define DBG_OFF 0
-+
-+/** Prefix string for DWC_DEBUG print macros. */
-+#define USB_DWC "DWC_otg: "
-+
-+/**
-+ * Print a debug message when the Global debug level variable contains
-+ * the bit defined in <code>lvl</code>.
-+ *
-+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
-+ * @param[in] x - like printf
-+ *
-+ * Example:<p>
-+ * <code>
-+ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
-+ * </code>
-+ * <br>
-+ * results in:<br>
-+ * <code>
-+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
-+ * </code>
-+ */
-+#ifdef DEBUG
-+
-+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
-+# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
-+
-+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
-+
-+#else
-+
-+# define DWC_DEBUGPL(lvl, x...) do{}while(0)
-+# define DWC_DEBUGP(x...)
-+
-+# define CHK_DEBUG_LEVEL(level) (0)
-+
-+#endif /*DEBUG*/
-+#endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_driver.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_driver.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,1749 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
-+ * $Revision: #92 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ * The dwc_otg_driver module provides the initialization and cleanup entry
-+ * points for the DWC_otg driver. This module will be dynamically installed
-+ * after Linux is booted using the insmod command. When the module is
-+ * installed, the dwc_otg_driver_init function is called. When the module is
-+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
-+ *
-+ * This module also defines a data structure for the dwc_otg_driver, which is
-+ * used in conjunction with the standard ARM lm_device structure. These
-+ * structures allow the OTG driver to comply with the standard Linux driver
-+ * model in which devices and drivers are registered with a bus driver. This
-+ * has the benefit that Linux can expose attributes of the driver and device
-+ * in its special sysfs file system. Users can then read or write files in
-+ * this file system to perform diagnostics on the driver components or the
-+ * device.
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_os.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
-+#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
-+
-+bool microframe_schedule=true;
-+
-+static const char dwc_driver_name[] = "dwc_otg";
-+
-+
-+extern int pcd_init(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+extern int hcd_init(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *dev
-+#endif
-+ );
-+
-+extern int pcd_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *_dev
-+#endif
-+ );
-+
-+extern void hcd_remove(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *_dev
-+#endif
-+ );
-+
-+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
-+
-+/*-------------------------------------------------------------------------*/
-+/* Encapsulate the module parameter settings */
-+
-+struct dwc_otg_driver_module_params {
-+ int32_t opt;
-+ int32_t otg_cap;
-+ int32_t dma_enable;
-+ int32_t dma_desc_enable;
-+ int32_t dma_burst_size;
-+ int32_t speed;
-+ int32_t host_support_fs_ls_low_power;
-+ int32_t host_ls_low_power_phy_clk;
-+ int32_t enable_dynamic_fifo;
-+ int32_t data_fifo_size;
-+ int32_t dev_rx_fifo_size;
-+ int32_t dev_nperio_tx_fifo_size;
-+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+ int32_t host_rx_fifo_size;
-+ int32_t host_nperio_tx_fifo_size;
-+ int32_t host_perio_tx_fifo_size;
-+ int32_t max_transfer_size;
-+ int32_t max_packet_count;
-+ int32_t host_channels;
-+ int32_t dev_endpoints;
-+ int32_t phy_type;
-+ int32_t phy_utmi_width;
-+ int32_t phy_ulpi_ddr;
-+ int32_t phy_ulpi_ext_vbus;
-+ int32_t i2c_enable;
-+ int32_t ulpi_fs_ls;
-+ int32_t ts_dline;
-+ int32_t en_multiple_tx_fifo;
-+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+ uint32_t thr_ctl;
-+ uint32_t tx_thr_length;
-+ uint32_t rx_thr_length;
-+ int32_t pti_enable;
-+ int32_t mpi_enable;
-+ int32_t lpm_enable;
-+ int32_t ic_usb_cap;
-+ int32_t ahb_thr_ratio;
-+ int32_t power_down;
-+ int32_t reload_ctl;
-+ int32_t dev_out_nak;
-+ int32_t cont_on_bna;
-+ int32_t ahb_single;
-+ int32_t otg_ver;
-+ int32_t adp_enable;
-+};
-+
-+static struct dwc_otg_driver_module_params dwc_otg_module_params = {
-+ .opt = -1,
-+ .otg_cap = -1,
-+ .dma_enable = -1,
-+ .dma_desc_enable = -1,
-+ .dma_burst_size = -1,
-+ .speed = -1,
-+ .host_support_fs_ls_low_power = -1,
-+ .host_ls_low_power_phy_clk = -1,
-+ .enable_dynamic_fifo = -1,
-+ .data_fifo_size = -1,
-+ .dev_rx_fifo_size = -1,
-+ .dev_nperio_tx_fifo_size = -1,
-+ .dev_perio_tx_fifo_size = {
-+ /* dev_perio_tx_fifo_size_1 */
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1
-+ /* 15 */
-+ },
-+ .host_rx_fifo_size = -1,
-+ .host_nperio_tx_fifo_size = -1,
-+ .host_perio_tx_fifo_size = -1,
-+ .max_transfer_size = -1,
-+ .max_packet_count = -1,
-+ .host_channels = -1,
-+ .dev_endpoints = -1,
-+ .phy_type = -1,
-+ .phy_utmi_width = -1,
-+ .phy_ulpi_ddr = -1,
-+ .phy_ulpi_ext_vbus = -1,
-+ .i2c_enable = -1,
-+ .ulpi_fs_ls = -1,
-+ .ts_dline = -1,
-+ .en_multiple_tx_fifo = -1,
-+ .dev_tx_fifo_size = {
-+ /* dev_tx_fifo_size */
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1,
-+ -1
-+ /* 15 */
-+ },
-+ .thr_ctl = -1,
-+ .tx_thr_length = -1,
-+ .rx_thr_length = -1,
-+ .pti_enable = -1,
-+ .mpi_enable = -1,
-+ .lpm_enable = 0,
-+ .ic_usb_cap = -1,
-+ .ahb_thr_ratio = -1,
-+ .power_down = -1,
-+ .reload_ctl = -1,
-+ .dev_out_nak = -1,
-+ .cont_on_bna = -1,
-+ .ahb_single = -1,
-+ .otg_ver = -1,
-+ .adp_enable = -1,
-+};
-+
-+//Global variable to switch the fiq fix on or off
-+bool fiq_enable = 1;
-+// Global variable to enable the split transaction fix
-+bool fiq_fsm_enable = true;
-+//Bulk split-transaction NAK holdoff in microframes
-+uint16_t nak_holdoff = 8;
-+
-+unsigned short fiq_fsm_mask = 0x07;
-+
-+/**
-+ * This function shows the Driver Version.
-+ */
-+static ssize_t version_show(struct device_driver *dev, char *buf)
-+{
-+ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
-+ DWC_DRIVER_VERSION);
-+}
-+
-+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
-+
-+/**
-+ * Global Debug Level Mask.
-+ */
-+uint32_t g_dbg_lvl = 0; /* OFF */
-+
-+/**
-+ * This function shows the driver Debug Level.
-+ */
-+static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
-+{
-+ return sprintf(buf, "0x%0x\n", g_dbg_lvl);
-+}
-+
-+/**
-+ * This function stores the driver Debug Level.
-+ */
-+static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
-+ size_t count)
-+{
-+ g_dbg_lvl = simple_strtoul(buf, NULL, 16);
-+ return count;
-+}
-+
-+static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
-+ dbg_level_store);
-+
-+/**
-+ * This function is called during module intialization
-+ * to pass module parameters to the DWC_OTG CORE.
-+ */
-+static int set_parameters(dwc_otg_core_if_t * core_if)
-+{
-+ int retval = 0;
-+ int i;
-+
-+ if (dwc_otg_module_params.otg_cap != -1) {
-+ retval +=
-+ dwc_otg_set_param_otg_cap(core_if,
-+ dwc_otg_module_params.otg_cap);
-+ }
-+ if (dwc_otg_module_params.dma_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_dma_enable(core_if,
-+ dwc_otg_module_params.
-+ dma_enable);
-+ }
-+ if (dwc_otg_module_params.dma_desc_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_dma_desc_enable(core_if,
-+ dwc_otg_module_params.
-+ dma_desc_enable);
-+ }
-+ if (dwc_otg_module_params.opt != -1) {
-+ retval +=
-+ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
-+ }
-+ if (dwc_otg_module_params.dma_burst_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_dma_burst_size(core_if,
-+ dwc_otg_module_params.
-+ dma_burst_size);
-+ }
-+ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
-+ dwc_otg_module_params.
-+ host_support_fs_ls_low_power);
-+ }
-+ if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
-+ retval +=
-+ dwc_otg_set_param_enable_dynamic_fifo(core_if,
-+ dwc_otg_module_params.
-+ enable_dynamic_fifo);
-+ }
-+ if (dwc_otg_module_params.data_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_data_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ data_fifo_size);
-+ }
-+ if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_rx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_rx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_nperio_tx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.host_rx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_rx_fifo_size(core_if,
-+ dwc_otg_module_params.host_rx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ host_nperio_tx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ host_perio_tx_fifo_size);
-+ }
-+ if (dwc_otg_module_params.max_transfer_size != -1) {
-+ retval +=
-+ dwc_otg_set_param_max_transfer_size(core_if,
-+ dwc_otg_module_params.
-+ max_transfer_size);
-+ }
-+ if (dwc_otg_module_params.max_packet_count != -1) {
-+ retval +=
-+ dwc_otg_set_param_max_packet_count(core_if,
-+ dwc_otg_module_params.
-+ max_packet_count);
-+ }
-+ if (dwc_otg_module_params.host_channels != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_channels(core_if,
-+ dwc_otg_module_params.
-+ host_channels);
-+ }
-+ if (dwc_otg_module_params.dev_endpoints != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_endpoints(core_if,
-+ dwc_otg_module_params.
-+ dev_endpoints);
-+ }
-+ if (dwc_otg_module_params.phy_type != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_type(core_if,
-+ dwc_otg_module_params.phy_type);
-+ }
-+ if (dwc_otg_module_params.speed != -1) {
-+ retval +=
-+ dwc_otg_set_param_speed(core_if,
-+ dwc_otg_module_params.speed);
-+ }
-+ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
-+ retval +=
-+ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
-+ dwc_otg_module_params.
-+ host_ls_low_power_phy_clk);
-+ }
-+ if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_ulpi_ddr(core_if,
-+ dwc_otg_module_params.
-+ phy_ulpi_ddr);
-+ }
-+ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
-+ dwc_otg_module_params.
-+ phy_ulpi_ext_vbus);
-+ }
-+ if (dwc_otg_module_params.phy_utmi_width != -1) {
-+ retval +=
-+ dwc_otg_set_param_phy_utmi_width(core_if,
-+ dwc_otg_module_params.
-+ phy_utmi_width);
-+ }
-+ if (dwc_otg_module_params.ulpi_fs_ls != -1) {
-+ retval +=
-+ dwc_otg_set_param_ulpi_fs_ls(core_if,
-+ dwc_otg_module_params.ulpi_fs_ls);
-+ }
-+ if (dwc_otg_module_params.ts_dline != -1) {
-+ retval +=
-+ dwc_otg_set_param_ts_dline(core_if,
-+ dwc_otg_module_params.ts_dline);
-+ }
-+ if (dwc_otg_module_params.i2c_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_i2c_enable(core_if,
-+ dwc_otg_module_params.
-+ i2c_enable);
-+ }
-+ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
-+ retval +=
-+ dwc_otg_set_param_en_multiple_tx_fifo(core_if,
-+ dwc_otg_module_params.
-+ en_multiple_tx_fifo);
-+ }
-+ for (i = 0; i < 15; i++) {
-+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_perio_tx_fifo_size
-+ [i], i);
-+ }
-+ }
-+
-+ for (i = 0; i < 15; i++) {
-+ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
-+ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
-+ dwc_otg_module_params.
-+ dev_tx_fifo_size
-+ [i], i);
-+ }
-+ }
-+ if (dwc_otg_module_params.thr_ctl != -1) {
-+ retval +=
-+ dwc_otg_set_param_thr_ctl(core_if,
-+ dwc_otg_module_params.thr_ctl);
-+ }
-+ if (dwc_otg_module_params.mpi_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_mpi_enable(core_if,
-+ dwc_otg_module_params.
-+ mpi_enable);
-+ }
-+ if (dwc_otg_module_params.pti_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_pti_enable(core_if,
-+ dwc_otg_module_params.
-+ pti_enable);
-+ }
-+ if (dwc_otg_module_params.lpm_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_lpm_enable(core_if,
-+ dwc_otg_module_params.
-+ lpm_enable);
-+ }
-+ if (dwc_otg_module_params.ic_usb_cap != -1) {
-+ retval +=
-+ dwc_otg_set_param_ic_usb_cap(core_if,
-+ dwc_otg_module_params.
-+ ic_usb_cap);
-+ }
-+ if (dwc_otg_module_params.tx_thr_length != -1) {
-+ retval +=
-+ dwc_otg_set_param_tx_thr_length(core_if,
-+ dwc_otg_module_params.tx_thr_length);
-+ }
-+ if (dwc_otg_module_params.rx_thr_length != -1) {
-+ retval +=
-+ dwc_otg_set_param_rx_thr_length(core_if,
-+ dwc_otg_module_params.
-+ rx_thr_length);
-+ }
-+ if (dwc_otg_module_params.ahb_thr_ratio != -1) {
-+ retval +=
-+ dwc_otg_set_param_ahb_thr_ratio(core_if,
-+ dwc_otg_module_params.ahb_thr_ratio);
-+ }
-+ if (dwc_otg_module_params.power_down != -1) {
-+ retval +=
-+ dwc_otg_set_param_power_down(core_if,
-+ dwc_otg_module_params.power_down);
-+ }
-+ if (dwc_otg_module_params.reload_ctl != -1) {
-+ retval +=
-+ dwc_otg_set_param_reload_ctl(core_if,
-+ dwc_otg_module_params.reload_ctl);
-+ }
-+
-+ if (dwc_otg_module_params.dev_out_nak != -1) {
-+ retval +=
-+ dwc_otg_set_param_dev_out_nak(core_if,
-+ dwc_otg_module_params.dev_out_nak);
-+ }
-+
-+ if (dwc_otg_module_params.cont_on_bna != -1) {
-+ retval +=
-+ dwc_otg_set_param_cont_on_bna(core_if,
-+ dwc_otg_module_params.cont_on_bna);
-+ }
-+
-+ if (dwc_otg_module_params.ahb_single != -1) {
-+ retval +=
-+ dwc_otg_set_param_ahb_single(core_if,
-+ dwc_otg_module_params.ahb_single);
-+ }
-+
-+ if (dwc_otg_module_params.otg_ver != -1) {
-+ retval +=
-+ dwc_otg_set_param_otg_ver(core_if,
-+ dwc_otg_module_params.otg_ver);
-+ }
-+ if (dwc_otg_module_params.adp_enable != -1) {
-+ retval +=
-+ dwc_otg_set_param_adp_enable(core_if,
-+ dwc_otg_module_params.
-+ adp_enable);
-+ }
-+ return retval;
-+}
-+
-+/**
-+ * This function is the top level interrupt handler for the Common
-+ * (Device and host modes) interrupts.
-+ */
-+static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
-+{
-+ int32_t retval = IRQ_NONE;
-+
-+ retval = dwc_otg_handle_common_intr(dev);
-+ if (retval != 0) {
-+ S3C2410X_CLEAR_EINTPEND();
-+ }
-+ return IRQ_RETVAL(retval);
-+}
-+
-+/**
-+ * This function is called when a lm_device is unregistered with the
-+ * dwc_otg_driver. This happens, for example, when the rmmod command is
-+ * executed. The device may or may not be electrically present. If it is
-+ * present, the driver stops device processing. Any resources used on behalf
-+ * of this device are freed.
-+ *
-+ * @param _dev
-+ */
-+#ifdef LM_INTERFACE
-+#define REM_RETVAL(n)
-+static void dwc_otg_driver_remove( struct lm_device *_dev )
-+{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
-+#elif defined(PCI_INTERFACE)
-+#define REM_RETVAL(n)
-+static void dwc_otg_driver_remove( struct pci_dev *_dev )
-+{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
-+#elif defined(PLATFORM_INTERFACE)
-+#define REM_RETVAL(n) n
-+static int dwc_otg_driver_remove( struct platform_device *_dev )
-+{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
-+#endif
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
-+
-+ if (!otg_dev) {
-+ /* Memory allocation for the dwc_otg_device failed. */
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
-+ return REM_RETVAL(-ENOMEM);
-+ }
-+#ifndef DWC_DEVICE_ONLY
-+ if (otg_dev->hcd) {
-+ hcd_remove(_dev);
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
-+ return REM_RETVAL(-EINVAL);
-+ }
-+#endif
-+
-+#ifndef DWC_HOST_ONLY
-+ if (otg_dev->pcd) {
-+ pcd_remove(_dev);
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
-+ return REM_RETVAL(-EINVAL);
-+ }
-+#endif
-+ /*
-+ * Free the IRQ
-+ */
-+ if (otg_dev->common_irq_installed) {
-+#ifdef PLATFORM_INTERFACE
-+ free_irq(platform_get_irq(_dev, 0), otg_dev);
-+#else
-+ free_irq(_dev->irq, otg_dev);
-+#endif
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
-+ return REM_RETVAL(-ENXIO);
-+ }
-+
-+ if (otg_dev->core_if) {
-+ dwc_otg_cil_remove(otg_dev->core_if);
-+ } else {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
-+ return REM_RETVAL(-ENXIO);
-+ }
-+
-+ /*
-+ * Remove the device attributes
-+ */
-+ dwc_otg_attr_remove(_dev);
-+
-+ /*
-+ * Return the memory.
-+ */
-+ if (otg_dev->os_dep.base) {
-+ iounmap(otg_dev->os_dep.base);
-+ }
-+ DWC_FREE(otg_dev);
-+
-+ /*
-+ * Clear the drvdata pointer.
-+ */
-+#ifdef LM_INTERFACE
-+ lm_set_drvdata(_dev, 0);
-+#elif defined(PCI_INTERFACE)
-+ release_mem_region(otg_dev->os_dep.rsrc_start,
-+ otg_dev->os_dep.rsrc_len);
-+ pci_set_drvdata(_dev, 0);
-+#elif defined(PLATFORM_INTERFACE)
-+ platform_set_drvdata(_dev, 0);
-+#endif
-+ return REM_RETVAL(0);
-+}
-+
-+/**
-+ * This function is called when an lm_device is bound to a
-+ * dwc_otg_driver. It creates the driver components required to
-+ * control the device (CIL, HCD, and PCD) and it initializes the
-+ * device. The driver components are stored in a dwc_otg_device
-+ * structure. A reference to the dwc_otg_device is saved in the
-+ * lm_device. This allows the driver to access the dwc_otg_device
-+ * structure on subsequent calls to driver methods for this device.
-+ *
-+ * @param _dev Bus device
-+ */
-+static int dwc_otg_driver_probe(
-+#ifdef LM_INTERFACE
-+ struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *_dev,
-+ const struct pci_device_id *id
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *_dev
-+#endif
-+ )
-+{
-+ int retval = 0;
-+ dwc_otg_device_t *dwc_otg_device;
-+ int devirq;
-+
-+ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
-+#ifdef LM_INTERFACE
-+ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
-+#elif defined(PCI_INTERFACE)
-+ if (!id) {
-+ DWC_ERROR("Invalid pci_device_id %p", id);
-+ return -EINVAL;
-+ }
-+
-+ if (!_dev || (pci_enable_device(_dev) < 0)) {
-+ DWC_ERROR("Invalid pci_device %p", _dev);
-+ return -ENODEV;
-+ }
-+ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
-+ /* other stuff needed as well? */
-+
-+#elif defined(PLATFORM_INTERFACE)
-+ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
-+ (unsigned)_dev->resource->start,
-+ (unsigned)(_dev->resource->end - _dev->resource->start));
-+#endif
-+
-+ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
-+
-+ if (!dwc_otg_device) {
-+ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
-+ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
-+
-+ /*
-+ * Map the DWC_otg Core memory into virtual address space.
-+ */
-+#ifdef LM_INTERFACE
-+ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
-+
-+ if (!dwc_otg_device->os_dep.base) {
-+ dev_err(&_dev->dev, "ioremap() failed\n");
-+ DWC_FREE(dwc_otg_device);
-+ return -ENOMEM;
-+ }
-+ dev_dbg(&_dev->dev, "base=0x%08x\n",
-+ (unsigned)dwc_otg_device->os_dep.base);
-+#elif defined(PCI_INTERFACE)
-+ _dev->current_state = PCI_D0;
-+ _dev->dev.power.power_state = PMSG_ON;
-+
-+ if (!_dev->irq) {
-+ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
-+ pci_name(_dev));
-+ iounmap(dwc_otg_device->os_dep.base);
-+ DWC_FREE(dwc_otg_device);
-+ return -ENODEV;
-+ }
-+
-+ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
-+ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
-+ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
-+ (unsigned)dwc_otg_device->os_dep.rsrc_start,
-+ (unsigned)dwc_otg_device->os_dep.rsrc_len);
-+ if (!request_mem_region
-+ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
-+ "dwc_otg")) {
-+ dev_dbg(&_dev->dev, "error requesting memory\n");
-+ iounmap(dwc_otg_device->os_dep.base);
-+ DWC_FREE(dwc_otg_device);
-+ return -EFAULT;
-+ }
-+
-+ dwc_otg_device->os_dep.base =
-+ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
-+ dwc_otg_device->os_dep.rsrc_len);
-+ if (dwc_otg_device->os_dep.base == NULL) {
-+ dev_dbg(&_dev->dev, "error mapping memory\n");
-+ release_mem_region(dwc_otg_device->os_dep.rsrc_start,
-+ dwc_otg_device->os_dep.rsrc_len);
-+ iounmap(dwc_otg_device->os_dep.base);
-+ DWC_FREE(dwc_otg_device);
-+ return -EFAULT;
-+ }
-+ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
-+ dwc_otg_device->os_dep.base);
-+ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
-+ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
-+ dwc_otg_device->os_dep.base);
-+ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
-+ (unsigned)dwc_otg_device->os_dep.rsrc_start,
-+ dwc_otg_device->os_dep.base);
-+
-+ pci_set_master(_dev);
-+ pci_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
-+ _dev->resource->start,
-+ _dev->resource->end - _dev->resource->start + 1);
-+#if 1
-+ if (!request_mem_region(_dev->resource[0].start,
-+ _dev->resource[0].end - _dev->resource[0].start + 1,
-+ "dwc_otg")) {
-+ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
-+ retval = -EFAULT;
-+ goto fail;
-+ }
-+
-+ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
-+ _dev->resource[0].end -
-+ _dev->resource[0].start+1);
-+ if (fiq_enable)
-+ {
-+ if (!request_mem_region(_dev->resource[1].start,
-+ _dev->resource[1].end - _dev->resource[1].start + 1,
-+ "dwc_otg")) {
-+ dev_dbg(&_dev->dev, "error reserving mapped memory\n");
-+ retval = -EFAULT;
-+ goto fail;
-+ }
-+
-+ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
-+ _dev->resource[1].end -
-+ _dev->resource[1].start + 1);
-+ }
-+
-+#else
-+ {
-+ struct map_desc desc = {
-+ .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
-+ .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
-+ .length = SZ_128K,
-+ .type = MT_DEVICE
-+ };
-+ iotable_init(&desc, 1);
-+ dwc_otg_device->os_dep.base = (void *)desc.virtual;
-+ }
-+#endif
-+ if (!dwc_otg_device->os_dep.base) {
-+ dev_err(&_dev->dev, "ioremap() failed\n");
-+ retval = -ENOMEM;
-+ goto fail;
-+ }
-+ dev_dbg(&_dev->dev, "base=0x%08x\n",
-+ (unsigned)dwc_otg_device->os_dep.base);
-+#endif
-+
-+ /*
-+ * Initialize driver data to point to the global DWC_otg
-+ * Device structure.
-+ */
-+#ifdef LM_INTERFACE
-+ lm_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+ platform_set_drvdata(_dev, dwc_otg_device);
-+#endif
-+ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
-+
-+ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
-+ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
-+ dwc_otg_device, dwc_otg_device->core_if);//GRAYG
-+
-+ if (!dwc_otg_device->core_if) {
-+ dev_err(&_dev->dev, "CIL initialization failed!\n");
-+ retval = -ENOMEM;
-+ goto fail;
-+ }
-+
-+ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
-+ /*
-+ * Attempt to ensure this device is really a DWC_otg Controller.
-+ * Read and verify the SNPSID register contents. The value should be
-+ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
-+ * as in "OTG version 2.XX" or "OTG version 3.XX".
-+ */
-+
-+ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
-+ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
-+ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
-+ dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
-+ retval = -EINVAL;
-+ goto fail;
-+ }
-+
-+ /*
-+ * Validate parameter values.
-+ */
-+ dev_dbg(&_dev->dev, "Calling set_parameters\n");
-+ if (set_parameters(dwc_otg_device->core_if)) {
-+ retval = -EINVAL;
-+ goto fail;
-+ }
-+
-+ /*
-+ * Create Device Attributes in sysfs
-+ */
-+ dev_dbg(&_dev->dev, "Calling attr_create\n");
-+ dwc_otg_attr_create(_dev);
-+
-+ /*
-+ * Disable the global interrupt until all the interrupt
-+ * handlers are installed.
-+ */
-+ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
-+ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
-+
-+ /*
-+ * Install the interrupt handler for the common interrupts before
-+ * enabling common interrupts in core_init below.
-+ */
-+
-+#if defined(PLATFORM_INTERFACE)
-+ devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
-+#else
-+ devirq = _dev->irq;
-+#endif
-+ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
-+ devirq);
-+ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
-+ retval = request_irq(devirq, dwc_otg_common_irq,
-+ IRQF_SHARED,
-+ "dwc_otg", dwc_otg_device);
-+ if (retval) {
-+ DWC_ERROR("request of irq%d failed\n", devirq);
-+ retval = -EBUSY;
-+ goto fail;
-+ } else {
-+ dwc_otg_device->common_irq_installed = 1;
-+ }
-+
-+#ifndef IRQF_TRIGGER_LOW
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+ dev_dbg(&_dev->dev, "Calling set_irq_type\n");
-+ set_irq_type(devirq,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
-+ IRQT_LOW
-+#else
-+ IRQ_TYPE_LEVEL_LOW
-+#endif
-+ );
-+#endif
-+#endif /*IRQF_TRIGGER_LOW*/
-+
-+ /*
-+ * Initialize the DWC_otg core.
-+ */
-+ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
-+ dwc_otg_core_init(dwc_otg_device->core_if);
-+
-+#ifndef DWC_HOST_ONLY
-+ /*
-+ * Initialize the PCD
-+ */
-+ dev_dbg(&_dev->dev, "Calling pcd_init\n");
-+ retval = pcd_init(_dev);
-+ if (retval != 0) {
-+ DWC_ERROR("pcd_init failed\n");
-+ dwc_otg_device->pcd = NULL;
-+ goto fail;
-+ }
-+#endif
-+#ifndef DWC_DEVICE_ONLY
-+ /*
-+ * Initialize the HCD
-+ */
-+ dev_dbg(&_dev->dev, "Calling hcd_init\n");
-+ retval = hcd_init(_dev);
-+ if (retval != 0) {
-+ DWC_ERROR("hcd_init failed\n");
-+ dwc_otg_device->hcd = NULL;
-+ goto fail;
-+ }
-+#endif
-+ /* Recover from drvdata having been overwritten by hcd_init() */
-+#ifdef LM_INTERFACE
-+ lm_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+ platform_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PCI_INTERFACE)
-+ pci_set_drvdata(_dev, dwc_otg_device);
-+ dwc_otg_device->os_dep.pcidev = _dev;
-+#endif
-+
-+ /*
-+ * Enable the global interrupt after all the interrupt
-+ * handlers are installed if there is no ADP support else
-+ * perform initial actions required for Internal ADP logic.
-+ */
-+ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
-+ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
-+ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
-+ dev_dbg(&_dev->dev, "Done\n");
-+ } else
-+ dwc_otg_adp_start(dwc_otg_device->core_if,
-+ dwc_otg_is_host_mode(dwc_otg_device->core_if));
-+
-+ return 0;
-+
-+fail:
-+ dwc_otg_driver_remove(_dev);
-+ return retval;
-+}
-+
-+/**
-+ * This structure defines the methods to be called by a bus driver
-+ * during the lifecycle of a device on that bus. Both drivers and
-+ * devices are registered with a bus driver. The bus driver matches
-+ * devices to drivers based on information in the device and driver
-+ * structures.
-+ *
-+ * The probe function is called when the bus driver matches a device
-+ * to this driver. The remove function is called when a device is
-+ * unregistered with the bus driver.
-+ */
-+#ifdef LM_INTERFACE
-+static struct lm_driver dwc_otg_driver = {
-+ .drv = {.name = (char *)dwc_driver_name,},
-+ .probe = dwc_otg_driver_probe,
-+ .remove = dwc_otg_driver_remove,
-+ // 'suspend' and 'resume' absent
-+};
-+#elif defined(PCI_INTERFACE)
-+static const struct pci_device_id pci_ids[] = { {
-+ PCI_DEVICE(0x16c3, 0xabcd),
-+ .driver_data =
-+ (unsigned long)0xdeadbeef,
-+ }, { /* end: all zeroes */ }
-+};
-+
-+MODULE_DEVICE_TABLE(pci, pci_ids);
-+
-+/* pci driver glue; this is a "new style" PCI driver module */
-+static struct pci_driver dwc_otg_driver = {
-+ .name = "dwc_otg",
-+ .id_table = pci_ids,
-+
-+ .probe = dwc_otg_driver_probe,
-+ .remove = dwc_otg_driver_remove,
-+
-+ .driver = {
-+ .name = (char *)dwc_driver_name,
-+ },
-+};
-+#elif defined(PLATFORM_INTERFACE)
-+static struct platform_device_id platform_ids[] = {
-+ {
-+ .name = "bcm2708_usb",
-+ .driver_data = (kernel_ulong_t) 0xdeadbeef,
-+ },
-+ { /* end: all zeroes */ }
-+};
-+MODULE_DEVICE_TABLE(platform, platform_ids);
-+
-+static struct platform_driver dwc_otg_driver = {
-+ .driver = {
-+ .name = (char *)dwc_driver_name,
-+ },
-+ .id_table = platform_ids,
-+
-+ .probe = dwc_otg_driver_probe,
-+ .remove = dwc_otg_driver_remove,
-+ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
-+};
-+#endif
-+
-+/**
-+ * This function is called when the dwc_otg_driver is installed with the
-+ * insmod command. It registers the dwc_otg_driver structure with the
-+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
-+ * to be called. In addition, the bus driver will automatically expose
-+ * attributes defined for the device and driver in the special sysfs file
-+ * system.
-+ *
-+ * @return
-+ */
-+static int __init dwc_otg_driver_init(void)
-+{
-+ int retval = 0;
-+ int error;
-+ struct device_driver *drv;
-+
-+ if(fiq_fsm_enable && !fiq_enable) {
-+ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
-+ fiq_enable = 1;
-+ }
-+
-+ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
-+ DWC_DRIVER_VERSION,
-+#ifdef LM_INTERFACE
-+ "logicmodule");
-+ retval = lm_driver_register(&dwc_otg_driver);
-+ drv = &dwc_otg_driver.drv;
-+#elif defined(PCI_INTERFACE)
-+ "pci");
-+ retval = pci_register_driver(&dwc_otg_driver);
-+ drv = &dwc_otg_driver.driver;
-+#elif defined(PLATFORM_INTERFACE)
-+ "platform");
-+ retval = platform_driver_register(&dwc_otg_driver);
-+ drv = &dwc_otg_driver.driver;
-+#endif
-+ if (retval < 0) {
-+ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
-+ return retval;
-+ }
-+ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
-+ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
-+ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
-+
-+ error = driver_create_file(drv, &driver_attr_version);
-+#ifdef DEBUG
-+ error = driver_create_file(drv, &driver_attr_debuglevel);
-+#endif
-+ return retval;
-+}
-+
-+module_init(dwc_otg_driver_init);
-+
-+/**
-+ * This function is called when the driver is removed from the kernel
-+ * with the rmmod command. The driver unregisters itself with its bus
-+ * driver.
-+ *
-+ */
-+static void __exit dwc_otg_driver_cleanup(void)
-+{
-+ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
-+
-+#ifdef LM_INTERFACE
-+ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
-+ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
-+ lm_driver_unregister(&dwc_otg_driver);
-+#elif defined(PCI_INTERFACE)
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
-+ pci_unregister_driver(&dwc_otg_driver);
-+#elif defined(PLATFORM_INTERFACE)
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
-+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
-+ platform_driver_unregister(&dwc_otg_driver);
-+#endif
-+
-+ printk(KERN_INFO "%s module removed\n", dwc_driver_name);
-+}
-+
-+module_exit(dwc_otg_driver_cleanup);
-+
-+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
-+MODULE_AUTHOR("Synopsys Inc.");
-+MODULE_LICENSE("GPL");
-+
-+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
-+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
-+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
-+MODULE_PARM_DESC(opt, "OPT Mode");
-+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
-+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
-+
-+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
-+ 0444);
-+MODULE_PARM_DESC(dma_desc_enable,
-+ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
-+
-+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
-+ 0444);
-+MODULE_PARM_DESC(dma_burst_size,
-+ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
-+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
-+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
-+module_param_named(host_support_fs_ls_low_power,
-+ dwc_otg_module_params.host_support_fs_ls_low_power, int,
-+ 0444);
-+MODULE_PARM_DESC(host_support_fs_ls_low_power,
-+ "Support Low Power w/FS or LS 0=Support 1=Don't Support");
-+module_param_named(host_ls_low_power_phy_clk,
-+ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
-+MODULE_PARM_DESC(host_ls_low_power_phy_clk,
-+ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
-+module_param_named(enable_dynamic_fifo,
-+ dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
-+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
-+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
-+ 0444);
-+MODULE_PARM_DESC(data_fifo_size,
-+ "Total number of words in the data FIFO memory 32-32768");
-+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
-+ int, 0444);
-+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
-+module_param_named(dev_nperio_tx_fifo_size,
-+ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
-+ "Number of words in the non-periodic Tx FIFO 16-32768");
-+module_param_named(dev_perio_tx_fifo_size_1,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_2,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_3,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_4,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_5,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_6,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_7,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_8,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_9,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_10,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_11,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_12,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_13,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_14,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_15,
-+ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
-+ "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
-+ int, 0444);
-+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
-+module_param_named(host_nperio_tx_fifo_size,
-+ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(host_nperio_tx_fifo_size,
-+ "Number of words in the non-periodic Tx FIFO 16-32768");
-+module_param_named(host_perio_tx_fifo_size,
-+ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(host_perio_tx_fifo_size,
-+ "Number of words in the host periodic Tx FIFO 16-32768");
-+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
-+ int, 0444);
-+/** @todo Set the max to 512K, modify checks */
-+MODULE_PARM_DESC(max_transfer_size,
-+ "The maximum transfer size supported in bytes 2047-65535");
-+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
-+ int, 0444);
-+MODULE_PARM_DESC(max_packet_count,
-+ "The maximum number of packets in a transfer 15-511");
-+module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
-+ 0444);
-+MODULE_PARM_DESC(host_channels,
-+ "The number of host channel registers to use 1-16");
-+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
-+ 0444);
-+MODULE_PARM_DESC(dev_endpoints,
-+ "The number of endpoints in addition to EP0 available for device mode 1-15");
-+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
-+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
-+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
-+ 0444);
-+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
-+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
-+MODULE_PARM_DESC(phy_ulpi_ddr,
-+ "ULPI at double or single data rate 0=Single 1=Double");
-+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
-+ int, 0444);
-+MODULE_PARM_DESC(phy_ulpi_ext_vbus,
-+ "ULPI PHY using internal or external vbus 0=Internal");
-+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
-+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
-+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
-+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
-+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
-+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
-+module_param_named(debug, g_dbg_lvl, int, 0444);
-+MODULE_PARM_DESC(debug, "");
-+
-+module_param_named(en_multiple_tx_fifo,
-+ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
-+MODULE_PARM_DESC(en_multiple_tx_fifo,
-+ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
-+module_param_named(dev_tx_fifo_size_1,
-+ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_2,
-+ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_3,
-+ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_4,
-+ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_5,
-+ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_6,
-+ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_7,
-+ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_8,
-+ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_9,
-+ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_10,
-+ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_11,
-+ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_12,
-+ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_13,
-+ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_14,
-+ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_15,
-+ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
-+
-+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
-+MODULE_PARM_DESC(thr_ctl,
-+ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
-+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
-+ 0444);
-+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
-+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
-+ 0444);
-+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
-+
-+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
-+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
-+module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
-+MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
-+module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
-+MODULE_PARM_DESC(ic_usb_cap,
-+ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
-+module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
-+ 0444);
-+MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
-+module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
-+MODULE_PARM_DESC(power_down, "Power Down Mode");
-+module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
-+MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
-+module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
-+MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
-+module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
-+MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
-+module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
-+MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
-+module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
-+MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
-+module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
-+MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
-+module_param(microframe_schedule, bool, 0444);
-+MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
-+
-+module_param(fiq_enable, bool, 0444);
-+MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
-+module_param(nak_holdoff, ushort, 0644);
-+MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
-+module_param(fiq_fsm_enable, bool, 0444);
-+MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
-+module_param(fiq_fsm_mask, ushort, 0444);
-+MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
-+ "Bit 0 : Non-periodic split transactions\n"
-+ "Bit 1 : Periodic split transactions\n"
-+ "Bit 2 : High-speed multi-transfer isochronous\n"
-+ "All other bits should be set 0.");
-+
-+
-+/** @page "Module Parameters"
-+ *
-+ * The following parameters may be specified when starting the module.
-+ * These parameters define how the DWC_otg controller should be
-+ * configured. Parameter values are passed to the CIL initialization
-+ * function dwc_otg_cil_init
-+ *
-+ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
-+ *
-+
-+ <table>
-+ <tr><td>Parameter Name</td><td>Meaning</td></tr>
-+
-+ <tr>
-+ <td>otg_cap</td>
-+ <td>Specifies the OTG capabilities. The driver will automatically detect the
-+ value for this parameter if none is specified.
-+ - 0: HNP and SRP capable (default, if available)
-+ - 1: SRP Only capable
-+ - 2: No HNP/SRP capable
-+ </td></tr>
-+
-+ <tr>
-+ <td>dma_enable</td>
-+ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Slave
-+ - 1: DMA (default, if available)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dma_burst_size</td>
-+ <td>The DMA Burst size (applicable only for External DMA Mode).
-+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ </td></tr>
-+
-+ <tr>
-+ <td>speed</td>
-+ <td>Specifies the maximum speed of operation in host and device mode. The
-+ actual speed depends on the speed of the attached device and the value of
-+ phy_type.
-+ - 0: High Speed (default)
-+ - 1: Full Speed
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_support_fs_ls_low_power</td>
-+ <td>Specifies whether low power mode is supported when attached to a Full
-+ Speed or Low Speed device in host mode.
-+ - 0: Don't support low power mode (default)
-+ - 1: Support low power mode
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_ls_low_power_phy_clk</td>
-+ <td>Specifies the PHY clock rate in low power mode when connected to a Low
-+ Speed device in host mode. This parameter is applicable only if
-+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
-+ - 0: 48 MHz (default)
-+ - 1: 6 MHz
-+ </td></tr>
-+
-+ <tr>
-+ <td>enable_dynamic_fifo</td>
-+ <td> Specifies whether FIFOs may be resized by the driver software.
-+ - 0: Use cC FIFO size parameters
-+ - 1: Allow dynamic FIFO sizing (default)
-+ </td></tr>
-+
-+ <tr>
-+ <td>data_fifo_size</td>
-+ <td>Total number of 4-byte words in the data FIFO memory. This memory
-+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
-+ - Values: 32 to 32768 (default 8192)
-+
-+ Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_rx_fifo_size</td>
-+ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ FIFO sizing is enabled.
-+ - Values: 16 to 32768 (default 1064)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_nperio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
-+ dynamic FIFO sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
-+ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
-+ when dynamic FIFO sizing is enabled.
-+ - Values: 4 to 768 (default 256)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_rx_fifo_size</td>
-+ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
-+ sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_nperio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
-+ dynamic FIFO sizing is enabled in the core.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_perio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
-+ sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>max_transfer_size</td>
-+ <td>The maximum transfer size supported in bytes.
-+ - Values: 2047 to 65,535 (default 65,535)
-+ </td></tr>
-+
-+ <tr>
-+ <td>max_packet_count</td>
-+ <td>The maximum number of packets in a transfer.
-+ - Values: 15 to 511 (default 511)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_channels</td>
-+ <td>The number of host channel registers to use.
-+ - Values: 1 to 16 (default 12)
-+
-+ Note: The FPGA configuration supports a maximum of 12 host channels.
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_endpoints</td>
-+ <td>The number of endpoints in addition to EP0 available for device mode
-+ operations.
-+ - Values: 1 to 15 (default 6 IN and OUT)
-+
-+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
-+ addition to EP0.
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_type</td>
-+ <td>Specifies the type of PHY interface to use. By default, the driver will
-+ automatically detect the phy_type.
-+ - 0: Full Speed
-+ - 1: UTMI+ (default, if available)
-+ - 2: ULPI
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_utmi_width</td>
-+ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
-+ phy_type of UTMI+. Also, this parameter is applicable only if the
-+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
-+ core has been configured to work at either data path width.
-+ - Values: 8 or 16 bits (default 16)
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_ulpi_ddr</td>
-+ <td>Specifies whether the ULPI operates at double or single data rate. This
-+ parameter is only applicable if phy_type is ULPI.
-+ - 0: single data rate ULPI interface with 8 bit wide data bus (default)
-+ - 1: double data rate ULPI interface with 4 bit wide data bus
-+ </td></tr>
-+
-+ <tr>
-+ <td>i2c_enable</td>
-+ <td>Specifies whether to use the I2C interface for full speed PHY. This
-+ parameter is only applicable if PHY_TYPE is FS.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>ulpi_fs_ls</td>
-+ <td>Specifies whether to use ULPI FS/LS mode only.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>ts_dline</td>
-+ <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>en_multiple_tx_fifo</td>
-+ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Disabled
-+ - 1: Enabled (default, if available)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
-+ <td>Number of 4-byte words in each of the Tx FIFOs in device mode
-+ when dynamic FIFO sizing is enabled.
-+ - Values: 4 to 768 (default 256)
-+ </td></tr>
-+
-+ <tr>
-+ <td>tx_thr_length</td>
-+ <td>Transmit Threshold length in 32 bit double words
-+ - Values: 8 to 128 (default 64)
-+ </td></tr>
-+
-+ <tr>
-+ <td>rx_thr_length</td>
-+ <td>Receive Threshold length in 32 bit double words
-+ - Values: 8 to 128 (default 64)
-+ </td></tr>
-+
-+<tr>
-+ <td>thr_ctl</td>
-+ <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
-+ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
-+ Rx transfers accordingly.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - Values: 0 to 7 (default 0)
-+ Bit values indicate:
-+ - 0: Thresholding disabled
-+ - 1: Thresholding enabled
-+ </td></tr>
-+
-+<tr>
-+ <td>dma_desc_enable</td>
-+ <td>Specifies whether to enable Descriptor DMA mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Descriptor DMA disabled
-+ - 1: Descriptor DMA (default, if available)
-+ </td></tr>
-+
-+<tr>
-+ <td>mpi_enable</td>
-+ <td>Specifies whether to enable MPI enhancement mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: MPI disabled (default)
-+ - 1: MPI enable
-+ </td></tr>
-+
-+<tr>
-+ <td>pti_enable</td>
-+ <td>Specifies whether to enable PTI enhancement support.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: PTI disabled (default)
-+ - 1: PTI enable
-+ </td></tr>
-+
-+<tr>
-+ <td>lpm_enable</td>
-+ <td>Specifies whether to enable LPM support.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: LPM disabled
-+ - 1: LPM enable (default, if available)
-+ </td></tr>
-+
-+<tr>
-+ <td>ic_usb_cap</td>
-+ <td>Specifies whether to enable IC_USB capability.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: IC_USB disabled (default, if available)
-+ - 1: IC_USB enable
-+ </td></tr>
-+
-+<tr>
-+ <td>ahb_thr_ratio</td>
-+ <td>Specifies AHB Threshold ratio.
-+ - Values: 0 to 3 (default 0)
-+ </td></tr>
-+
-+<tr>
-+ <td>power_down</td>
-+ <td>Specifies Power Down(Hibernation) Mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Power Down disabled (default)
-+ - 2: Power Down enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>reload_ctl</td>
-+ <td>Specifies whether dynamic reloading of the HFIR register is allowed during
-+ run time. The driver will automatically detect the value for this parameter if
-+ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
-+ the core might misbehave.
-+ - 0: Reload Control disabled (default)
-+ - 1: Reload Control enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_out_nak</td>
-+ <td>Specifies whether Device OUT NAK enhancement enabled or no.
-+ The driver will automatically detect the value for this parameter if
-+ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
-+ - 0: The core does not set NAK after Bulk OUT transfer complete (default)
-+ - 1: The core sets NAK after Bulk OUT transfer complete
-+ </td></tr>
-+
-+ <tr>
-+ <td>cont_on_bna</td>
-+ <td>Specifies whether Enable Continue on BNA enabled or no.
-+ After receiving BNA interrupt the core disables the endpoint,when the
-+ endpoint is re-enabled by the application the
-+ - 0: Core starts processing from the DOEPDMA descriptor (default)
-+ - 1: Core starts processing from the descriptor which received the BNA.
-+ This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
-+ </td></tr>
-+
-+ <tr>
-+ <td>ahb_single</td>
-+ <td>This bit when programmed supports SINGLE transfers for remainder data
-+ in a transfer for DMA mode of operation.
-+ - 0: The remainder data will be sent using INCR burst size (default)
-+ - 1: The remainder data will be sent using SINGLE burst size.
-+ </td></tr>
-+
-+<tr>
-+ <td>adp_enable</td>
-+ <td>Specifies whether ADP feature is enabled.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: ADP feature disabled (default)
-+ - 1: ADP feature enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>otg_ver</td>
-+ <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
-+ USB OTG device.
-+ - 0: OTG 2.0 support disabled (default)
-+ - 1: OTG 2.0 support enabled
-+ </td></tr>
-+
-+*/
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_driver.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_driver.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,86 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
-+ * $Revision: #19 $
-+ * $Date: 2010/11/15 $
-+ * $Change: 1627671 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_DRIVER_H__
-+#define __DWC_OTG_DRIVER_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux driver.
-+ */
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_otg_core_if.h"
-+
-+/* Type declarations */
-+struct dwc_otg_pcd;
-+struct dwc_otg_hcd;
-+
-+/**
-+ * This structure is a wrapper that encapsulates the driver components used to
-+ * manage a single DWC_otg controller.
-+ */
-+typedef struct dwc_otg_device {
-+ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
-+ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
-+ * require this. */
-+ struct os_dependent os_dep;
-+
-+ /** Pointer to the core interface structure. */
-+ dwc_otg_core_if_t *core_if;
-+
-+ /** Pointer to the PCD structure. */
-+ struct dwc_otg_pcd *pcd;
-+
-+ /** Pointer to the HCD structure. */
-+ struct dwc_otg_hcd *hcd;
-+
-+ /** Flag to indicate whether the common IRQ handler is installed. */
-+ uint8_t common_irq_installed;
-+
-+} dwc_otg_device_t;
-+
-+/*We must clear S3C24XX_EINTPEND external interrupt register
-+ * because after clearing in this register trigerred IRQ from
-+ * H/W core in kernel interrupt can be occured again before OTG
-+ * handlers clear all IRQ sources of Core registers because of
-+ * timing latencies and Low Level IRQ Type.
-+ */
-+#ifdef CONFIG_MACH_IPMATE
-+#define S3C2410X_CLEAR_EINTPEND() \
-+do { \
-+ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
-+} while (0)
-+#else
-+#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
-+#endif
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,1346 @@
-+/*
-+ * dwc_otg_fiq_fsm.c - The finite state machine FIQ
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Raspberry Pi nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This FIQ implements functionality that performs split transactions on
-+ * the dwc_otg hardware without any outside intervention. A split transaction
-+ * is "queued" by nominating a specific host channel to perform the entirety
-+ * of a split transaction. This FIQ will then perform the microframe-precise
-+ * scheduling required in each phase of the transaction until completion.
-+ *
-+ * The FIQ functionality is glued into the Synopsys driver via the entry point
-+ * in the FSM enqueue function, and at the exit point in handling a HC interrupt
-+ * for a FSM-enabled channel.
-+ *
-+ * NB: Large parts of this implementation have architecture-specific code.
-+ * For porting this functionality to other ARM machines, the minimum is required:
-+ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
-+ * to the FIQ
-+ * - A method of forcing a software generated interrupt from FIQ mode that then
-+ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
-+ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
-+ * processor core - there is no locking between the FIQ and IRQ (aside from
-+ * local_fiq_disable)
-+ *
-+ */
-+
-+#include "dwc_otg_fiq_fsm.h"
-+
-+
-+char buffer[1000*16];
-+int wptr;
-+void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
-+{
-+ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
-+ va_list args;
-+ char text[17];
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
-+
-+ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
-+ {
-+ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
-+ va_start(args, fmt);
-+ vsnprintf(text+8, 9, fmt, args);
-+ va_end(args);
-+
-+ memcpy(buffer + wptr, text, 16);
-+ wptr = (wptr + 16) % sizeof(buffer);
-+ }
-+}
-+
-+/**
-+ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
-+ * Must be called with local interrupts and FIQ disabled.
-+ */
-+#ifdef CONFIG_ARCH_BCM2709
-+inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
-+{
-+ unsigned long tmp;
-+ uint32_t newval;
-+ fiq_lock_t lockval;
-+ smp_mb__before_spinlock();
-+ /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable
-+ * will be sufficient. If we are on a different CPU, then the lock protects us. */
-+ prefetchw(&lock->slock);
-+ asm volatile (
-+ "1: ldrex %0, [%3]\n"
-+ " add %1, %0, %4\n"
-+ " strex %2, %1, [%3]\n"
-+ " teq %2, #0\n"
-+ " bne 1b"
-+ : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-+ : "r" (&lock->slock), "I" (1 << 16)
-+ : "cc");
-+
-+ while (lockval.tickets.next != lockval.tickets.owner) {
-+ wfe();
-+ lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
-+ }
-+ smp_mb();
-+}
-+#else
-+inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }
-+#endif
-+
-+/**
-+ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock
-+ */
-+#ifdef CONFIG_ARCH_BCM2709
-+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
-+{
-+ smp_mb();
-+ lock->tickets.owner++;
-+ dsb_sev();
-+}
-+#else
-+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
-+#endif
-+
-+/**
-+ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
-+ * @channel: channel to re-enable
-+ */
-+static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
-+{
-+ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
-+
-+ hcchar.b.chen = 0;
-+ if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+ /* Hardware bug workaround: update the ssplit index */
-+ if (st->channel[n].hcsplt_copy.b.spltena)
-+ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
-+
-+ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
-+ }
-+
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
-+ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ hcchar.b.chen = 1;
-+
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
-+ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
-+}
-+
-+/**
-+ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
-+ * @st: Pointer to the channel's state
-+ * @n : channel number
-+ *
-+ * Change host channel registers to perform a complete-split transaction. Being mindful of the
-+ * endpoint direction, set control regs up correctly.
-+ */
-+static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
-+{
-+ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
-+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+
-+ hcsplt.b.compsplt = 1;
-+ if (st->channel[n].hcchar_copy.b.epdir == 1) {
-+ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
-+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
-+ } else {
-+ // If OUT, the CSPLIT result contains handshake only.
-+ hctsiz.b.xfersize = 0;
-+ }
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+ mb();
-+}
-+
-+static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
-+{
-+ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
-+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+
-+ if (st->channel[n].hcchar_copy.b.epdir == 0) {
-+ return st->channel[n].hctsiz_copy.b.xfersize;
-+ } else {
-+ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
-+ }
-+
-+}
-+
-+
-+/**
-+ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
-+ *
-+ * Of use only for IN periodic transfers.
-+ */
-+static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
-+{
-+ hcdma_data_t hcdma;
-+ int i = st->channel[n].dma_info.index;
-+ int len;
-+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
-+
-+ len = fiq_get_xfer_len(st, n);
-+ fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
-+ st->channel[n].dma_info.slot_len[i] = len;
-+ i++;
-+ if (i > 6)
-+ BUG();
-+
-+ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
-+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+ st->channel[n].dma_info.index = i;
-+ return 0;
-+}
-+
-+/**
-+ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
-+ */
-+static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
-+{
-+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
-+ hctsiz.b.pktcnt = 1;
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+}
-+
-+/**
-+ * fiq_iso_out_advance() - update DMA address and split position bits
-+ * for isochronous OUT transactions.
-+ *
-+ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
-+ * Split-BEGIN states are not handled - this is done when the transaction was queued.
-+ *
-+ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
-+ */
-+static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
-+{
-+ hcsplt_data_t hcsplt;
-+ hctsiz_data_t hctsiz;
-+ hcdma_data_t hcdma;
-+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
-+ int last = 0;
-+ int i = st->channel[n].dma_info.index;
-+
-+ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
-+ i++;
-+ if (i == 4)
-+ last = 1;
-+ if (st->channel[n].dma_info.slot_len[i+1] == 255)
-+ last = 1;
-+
-+ /* New DMA address - address of bounce buffer referred to in index */
-+ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
-+ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
-+ //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
-+ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
-+ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
-+ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
-+ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
-+ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
-+ /* Set up new packet length */
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
-+ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
-+
-+ st->channel[n].dma_info.index++;
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
-+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+ return last;
-+}
-+
-+/**
-+ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
-+ *
-+ * Despite the limitations of the DWC core, we can force a microframe pipeline of
-+ * isochronous OUT start-split transactions while waiting for a corresponding other-type
-+ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
-+ * is very unlikely that filling the start-split FIFO will cause data loss.
-+ * This allows much better interleaving of transactions in an order-independent way-
-+ * there is no requirement to prioritise isochronous, just a state-space search has
-+ * to be performed on each periodic start-split complete interrupt.
-+ */
-+static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
-+{
-+ int hub_addr = st->channel[n].hub_addr;
-+ int port_addr = st->channel[n].port_addr;
-+ int i, poked = 0;
-+ for (i = 0; i < num_channels; i++) {
-+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
-+ continue;
-+ if (st->channel[i].hub_addr == hub_addr &&
-+ st->channel[i].port_addr == port_addr) {
-+ switch (st->channel[i].fsm) {
-+ case FIQ_PER_ISO_OUT_PENDING:
-+ if (st->channel[i].nrpackets == 1) {
-+ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
-+ } else {
-+ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ }
-+ fiq_fsm_restart_channel(st, i, 0);
-+ poked = 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ }
-+ if (poked)
-+ break;
-+ }
-+ return poked;
-+}
-+
-+/**
-+ * fiq_fsm_tt_in_use() - search for host channels using this TT
-+ * @n: Channel to use as reference
-+ *
-+ */
-+int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
-+{
-+ int hub_addr = st->channel[n].hub_addr;
-+ int port_addr = st->channel[n].port_addr;
-+ int i, in_use = 0;
-+ for (i = 0; i < num_channels; i++) {
-+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
-+ continue;
-+ switch (st->channel[i].fsm) {
-+ /* TT is reserved for channels that are in the middle of a periodic
-+ * split transaction.
-+ */
-+ case FIQ_PER_SSPLIT_STARTED:
-+ case FIQ_PER_CSPLIT_WAIT:
-+ case FIQ_PER_CSPLIT_NYET1:
-+ //case FIQ_PER_CSPLIT_POLL:
-+ case FIQ_PER_ISO_OUT_ACTIVE:
-+ case FIQ_PER_ISO_OUT_LAST:
-+ if (st->channel[i].hub_addr == hub_addr &&
-+ st->channel[i].port_addr == port_addr) {
-+ in_use = 1;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ if (in_use)
-+ break;
-+ }
-+ return in_use;
-+}
-+
-+/**
-+ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
-+ * to be issued for this IN transaction.
-+ *
-+ * We cannot tell the inbound PID of a data packet due to hardware limitations.
-+ * we need to make an educated guess as to whether we need to queue another CSPLIT
-+ * or not. A no-brainer is when we have received enough data to fill the endpoint
-+ * size, but for endpoints that give variable-length data then we have to resort
-+ * to heuristics.
-+ *
-+ * We also return whether this is the last CSPLIT to be queued, again based on
-+ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
-+ * Note: requires at least 1 CSPLIT to have been performed prior to being called.
-+ */
-+
-+/*
-+ * We need some way of guaranteeing if a returned periodic packet of size X
-+ * has a DATA0 PID.
-+ * The heuristic value of 144 bytes assumes that the received data has maximal
-+ * bit-stuffing and the clock frequency of the transmitting device is at the lowest
-+ * permissible limit. If the transfer length results in a final packet size
-+ * 144 < p <= 188, then an erroneous CSPLIT will be issued.
-+ * Also used to ensure that an endpoint will nominally only return a single
-+ * complete-split worth of data.
-+ */
-+#define DATA0_PID_HEURISTIC 144
-+
-+static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
-+{
-+
-+ int i;
-+ int total_len = 0;
-+ int more_needed = 1;
-+ struct fiq_channel_state *st = &state->channel[n];
-+
-+ for (i = 0; i < st->dma_info.index; i++) {
-+ total_len += st->dma_info.slot_len[i];
-+ }
-+
-+ *probably_last = 0;
-+
-+ if (st->hcchar_copy.b.eptype == 0x3) {
-+ /*
-+ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
-+ * then this is definitely the last CSPLIT.
-+ */
-+ *probably_last = 1;
-+ } else {
-+ /* Isoc IN. This is a bit risky if we are the first transaction:
-+ * we may have been held off slightly. */
-+ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
-+ more_needed = 0;
-+ }
-+ /* If in the next uframe we will receive enough data to fill the endpoint,
-+ * then only issue 1 more csplit.
-+ */
-+ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
-+ *probably_last = 1;
-+ }
-+
-+ if (total_len >= st->hctsiz_copy.b.xfersize ||
-+ i == 6 || total_len == 0)
-+ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
-+ * a single endpoint. Accepting more would completely break our scheduling mechanism though
-+ * - in these extreme cases we will pass through a truncated packet.
-+ */
-+ more_needed = 0;
-+
-+ return more_needed;
-+}
-+
-+/**
-+ * fiq_fsm_too_late() - Test transaction for lateness
-+ *
-+ * If a SSPLIT for a large IN transaction is issued too late in a frame,
-+ * the hub will disable the port to the device and respond with ERR handshakes.
-+ * The hub status endpoint will not reflect this change.
-+ * Returns 1 if we will issue a SSPLIT that will result in a device babble.
-+ */
-+int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
-+{
-+ int uframe;
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+ uframe = hfnum.b.frnum & 0x7;
-+ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
-+ return 1;
-+ } else {
-+ return 0;
-+ }
-+}
-+
-+
-+/**
-+ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
-+ *
-+ * Search pending transactions in the start-split pending state and queue them.
-+ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
-+ * Note: we specifically don't do isochronous OUT transactions first because better
-+ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
-+ */
-+static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
-+{
-+ int n;
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+ if ((hfnum.b.frnum & 0x7) == 5)
-+ return;
-+ for (n = 0; n < num_channels; n++) {
-+ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
-+ /* Check to see if any other transactions are using this TT */
-+ if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
-+ if (!fiq_fsm_too_late(st, n)) {
-+ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
-+ fiq_print(FIQDBG_INT, st, "NEXTPER ");
-+ fiq_fsm_restart_channel(st, n, 0);
-+ } else {
-+ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+ }
-+ break;
-+ }
-+ }
-+ }
-+ for (n = 0; n < num_channels; n++) {
-+ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
-+ if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
-+ fiq_print(FIQDBG_INT, st, "NEXTISO ");
-+ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ fiq_fsm_restart_channel(st, n, 0);
-+ break;
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
-+ * @state: Pointer to fiq_state
-+ * @n: Channel transaction is active on
-+ * @hcint: Copy of host channel interrupt register
-+ *
-+ * Returns 0 if there are no more transactions for this HC to do, 1
-+ * otherwise.
-+ */
-+static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
-+{
-+ struct fiq_channel_state *st = &state->channel[n];
-+ int xfer_len = 0, nrpackets = 0;
-+ hcdma_data_t hcdma;
-+ fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
-+
-+ xfer_len = fiq_get_xfer_len(state, n);
-+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
-+
-+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
-+
-+ st->hs_isoc_info.index++;
-+ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
-+ return 0;
-+ }
-+
-+ /* grab the next DMA address offset from the array */
-+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
-+ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+
-+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
-+ * the core needs to be told to send the correct number. Caution: for IN transfers,
-+ * this is always set to the maximum size of the endpoint. */
-+ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
-+ /* Integer divide in a FIQ: fun. FIXME: make this not suck */
-+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
-+ if (nrpackets == 0)
-+ nrpackets = 1;
-+ st->hcchar_copy.b.multicnt = nrpackets;
-+ st->hctsiz_copy.b.pktcnt = nrpackets;
-+
-+ /* Initial PID also needs to be set */
-+ if (st->hcchar_copy.b.epdir == 0) {
-+ st->hctsiz_copy.b.xfersize = xfer_len;
-+ switch (st->hcchar_copy.b.multicnt) {
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_MDATA;
-+ break;
-+ }
-+
-+ } else {
-+ switch (st->hcchar_copy.b.multicnt) {
-+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA1;
-+ break;
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA2;
-+ break;
-+ }
-+ }
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
-+ /* Channel is enabled on hcint handler exit */
-+ fiq_print(FIQDBG_INT, state, "HSISOOUT");
-+ return 1;
-+}
-+
-+
-+/**
-+ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
-+ * @state: Pointer to the state struct passed from banked FIQ mode registers.
-+ * @num_channels: set according to the DWC hardware configuration
-+ *
-+ * The SOF handler in FSM mode has two functions
-+ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
-+ * nothing to do
-+ * 2. Advance certain FSM states that require either a microframe delay, or a microframe
-+ * of holdoff.
-+ *
-+ * The second part is architecture-specific to mach-bcm2835 -
-+ * a sane interrupt controller would have a mask register for ARM interrupt sources
-+ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
-+ * number (USB) can be enabled. This means that certain parts of the USB specification
-+ * that require "wait a little while, then issue another packet" cannot be fulfilled with
-+ * the timing granularity required to achieve optimal throughout. The workaround is to use
-+ * the SOF "timer" (125uS) to perform this task.
-+ */
-+static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
-+{
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
-+ int n;
-+ int kick_irq = 0;
-+
-+ if ((hfnum.b.frnum & 0x7) == 1) {
-+ /* We cannot issue csplits for transactions in the last frame past (n+1).1
-+ * Check to see if there are any transactions that are stale.
-+ * Boot them out.
-+ */
-+ for (n = 0; n < num_channels; n++) {
-+ switch (state->channel[n].fsm) {
-+ case FIQ_PER_CSPLIT_WAIT:
-+ case FIQ_PER_CSPLIT_NYET1:
-+ case FIQ_PER_CSPLIT_POLL:
-+ case FIQ_PER_CSPLIT_LAST:
-+ /* Check if we are no longer in the same full-speed frame. */
-+ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
-+ (hfnum.b.frnum & ~0x7))
-+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+ }
-+
-+ for (n = 0; n < num_channels; n++) {
-+ switch (state->channel[n].fsm) {
-+
-+ case FIQ_NP_SSPLIT_RETRY:
-+ case FIQ_NP_IN_CSPLIT_RETRY:
-+ case FIQ_NP_OUT_CSPLIT_RETRY:
-+ fiq_fsm_restart_channel(state, n, 0);
-+ break;
-+
-+ case FIQ_HS_ISOC_SLEEPING:
-+ state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
-+ fiq_fsm_restart_channel(state, n, 0);
-+ break;
-+
-+ case FIQ_PER_SSPLIT_QUEUED:
-+ if ((hfnum.b.frnum & 0x7) == 5)
-+ break;
-+ if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
-+ if (!fiq_fsm_too_late(state, n)) {
-+ fiq_print(FIQDBG_INT, st, "SOF GO %01d", n);
-+ fiq_fsm_restart_channel(state, n, 0);
-+ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
-+ } else {
-+ /* Transaction cannot be started without risking a device babble error */
-+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+ state->haintmsk_saved.b2.chint &= ~(1 << n);
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
-+ kick_irq |= 1;
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_PENDING:
-+ /* Ordinarily, this should be poked after the SSPLIT
-+ * complete interrupt for a competing transfer on the same
-+ * TT. Doesn't happen for aborted transactions though.
-+ */
-+ if ((hfnum.b.frnum & 0x7) >= 5)
-+ break;
-+ if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
-+ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt
-+ * that caused this.
-+ */
-+ fiq_fsm_restart_channel(state, n, 0);
-+ fiq_print(FIQDBG_INT, state, "SOF ISOC");
-+ if (state->channel[n].nrpackets == 1) {
-+ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
-+ } else {
-+ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_WAIT:
-+ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt
-+ * occurred when the bus transaction occurred. The SOF interrupt reversal bug
-+ * will utterly bugger this up though.
-+ */
-+ if (hfnum.b.frnum != state->channel[n].expected_uframe) {
-+ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
-+ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
-+ fiq_fsm_restart_channel(state, n, 0);
-+ fiq_fsm_start_next_periodic(state, num_channels);
-+
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_TIMEOUT:
-+ case FIQ_DEQUEUE_ISSUED:
-+ /* Ugly: we have to force a HCD interrupt.
-+ * Poke the mask for the channel in question.
-+ * We will take a fake SOF because of this, but
-+ * that's OK.
-+ */
-+ state->haintmsk_saved.b2.chint &= ~(1 << n);
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
-+ kick_irq |= 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ }
-+
-+ if (state->kick_np_queues ||
-+ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
-+ kick_irq |= 1;
-+
-+ return !kick_irq;
-+}
-+
-+
-+/**
-+ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
-+ * @state: Pointer to the FIQ state struct
-+ * @num_channels: Number of channels as per hardware config
-+ * @n: channel for which HAINT(i) was raised
-+ *
-+ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
-+ */
-+static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
-+{
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ hcint_data_t hcint_probe;
-+ hcchar_data_t hcchar;
-+ int handled = 0;
-+ int restart = 0;
-+ int last_csplit = 0;
-+ int start_next_periodic = 0;
-+ struct fiq_channel_state *st = &state->channel[n];
-+ hfnum_data_t hfnum;
-+
-+ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
-+ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
-+ hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
-+
-+ if (st->fsm != FIQ_PASSTHROUGH) {
-+ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
-+ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
-+ }
-+
-+ switch (st->fsm) {
-+
-+ case FIQ_PASSTHROUGH:
-+ case FIQ_DEQUEUE_ISSUED:
-+ /* doesn't belong to us, kick it upstairs */
-+ break;
-+
-+ case FIQ_PASSTHROUGH_ERRORSTATE:
-+ /* We are here to emulate the error recovery mechanism of the dwc HCD.
-+ * Several interrupts are unmasked if a previous transaction failed - it's
-+ * death for the FIQ to attempt to handle them as the channel isn't halted.
-+ * Emulate what the HCD does in this situation: mask and continue.
-+ * The FSM has no other state setup so this has to be handled out-of-band.
-+ */
-+ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
-+ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
-+ fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
-+ /* In some random cases we can get a NAK interrupt coincident with a Xacterr
-+ * interrupt, after the device has disappeared.
-+ */
-+ if (!hcint.b.xacterr)
-+ st->nr_errors = 0;
-+ hcintmsk.b.nak = 0;
-+ hcintmsk.b.ack = 0;
-+ hcintmsk.b.datatglerr = 0;
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
-+ return 1;
-+ }
-+ if (hcint_probe.b.chhltd) {
-+ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
-+ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
-+ return 0;
-+ }
-+ break;
-+
-+ /* Non-periodic state groups */
-+ case FIQ_NP_SSPLIT_STARTED:
-+ case FIQ_NP_SSPLIT_RETRY:
-+ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
-+ if (hcint.b.ack) {
-+ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
-+ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
-+ */
-+ if(st->hcchar_copy.b.epdir == 1)
-+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
-+ else
-+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+ st->nr_errors = 0;
-+ handled = 1;
-+ fiq_fsm_setup_csplit(state, n);
-+ } else if (hcint.b.nak) {
-+ // No buffer space in TT. Retry on a uframe boundary.
-+ st->fsm = FIQ_NP_SSPLIT_RETRY;
-+ handled = 1;
-+ } else if (hcint.b.xacterr) {
-+ // The only other one we care about is xacterr. This implies HS bus error - retry.
-+ st->nr_errors++;
-+ st->fsm = FIQ_NP_SSPLIT_RETRY;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ restart = 1;
-+ }
-+ } else {
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ handled = 0;
-+ restart = 0;
-+ }
-+ break;
-+
-+ case FIQ_NP_IN_CSPLIT_RETRY:
-+ /* Received a CSPLIT done interrupt.
-+ * Expected Data/NAK/STALL/NYET for IN.
-+ */
-+ if (hcint.b.xfercomp) {
-+ /* For IN, data is present. */
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nak) {
-+ /* no endpoint data. Punt it upstairs */
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nyet) {
-+ /* CSPLIT NYET - retry on a uframe boundary. */
-+ handled = 1;
-+ st->nr_errors = 0;
-+ } else if (hcint.b.datatglerr) {
-+ /* data toggle errors do not set the xfercomp bit. */
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ } else if (hcint.b.xacterr) {
-+ /* HS error. Retry immediate */
-+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ restart = 1;
-+ }
-+ } else if (hcint.b.stall || hcint.b.bblerr) {
-+ /* A STALL implies either a LS bus error or a genuine STALL. */
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ } else {
-+ /* Hardware bug. It's possible in some cases to
-+ * get a channel halt with nothing else set when
-+ * the response was a NYET. Treat as local 3-strikes retry.
-+ */
-+ hcint_data_t hcint_test = hcint;
-+ hcint_test.b.chhltd = 0;
-+ if (!hcint_test.d32) {
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ }
-+ } else {
-+ /* Bail out if something unexpected happened */
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ }
-+ }
-+ break;
-+
-+ case FIQ_NP_OUT_CSPLIT_RETRY:
-+ /* Received a CSPLIT done interrupt.
-+ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
-+ if (hcint.b.xfercomp) {
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nak) {
-+ // The HCD will implement the holdoff on frame boundaries.
-+ st->fsm = FIQ_NP_SPLIT_DONE;
-+ } else if (hcint.b.nyet) {
-+ // Hub still processing.
-+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+ handled = 1;
-+ st->nr_errors = 0;
-+ //restart = 1;
-+ } else if (hcint.b.xacterr) {
-+ /* HS error. retry immediate */
-+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ restart = 1;
-+ }
-+ } else if (hcint.b.stall) {
-+ /* LS bus error or genuine stall */
-+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+ } else {
-+ /*
-+ * Hardware bug. It's possible in some cases to get a
-+ * channel halt with nothing else set when the response was a NYET.
-+ * Treat as local 3-strikes retry.
-+ */
-+ hcint_data_t hcint_test = hcint;
-+ hcint_test.b.chhltd = 0;
-+ if (!hcint_test.d32) {
-+ st->nr_errors++;
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ } else {
-+ handled = 1;
-+ }
-+ } else {
-+ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
-+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+ }
-+ }
-+ break;
-+
-+ /* Periodic split states (except isoc out) */
-+ case FIQ_PER_SSPLIT_STARTED:
-+ /* Expect an ACK or failure for SSPLIT */
-+ if (hcint.b.ack) {
-+ /*
-+ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
-+ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
-+ * point for microframe n-3, the packet will not appear on the bus until microframe n.
-+ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
-+ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
-+ * coincident with SOF for n+1.
-+ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
-+ * These appear to be caused by timing/clock crossing bugs within the core itself.
-+ * State machine workaround.
-+ */
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ fiq_fsm_setup_csplit(state, n);
-+ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
-+ * time. If not, then we're in the next SOF.
-+ */
-+ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
-+ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
-+ st->expected_uframe = hfnum.b.frnum;
-+ st->fsm = FIQ_PER_CSPLIT_WAIT;
-+ } else {
-+ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n);
-+ /* For isochronous IN endpoints,
-+ * we need to hold off if we are expecting a lot of data */
-+ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
-+ start_next_periodic = 1;
-+ }
-+ /* Danger will robinson: we are in a broken state. If our first interrupt after
-+ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
-+ * lag. Unmask the NYET interrupt.
-+ */
-+ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
-+ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
-+ restart = 1;
-+ }
-+ handled = 1;
-+ } else if (hcint.b.xacterr) {
-+ /* 3-strikes retry is enabled, we have hit our max nr_errors */
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ start_next_periodic = 1;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ start_next_periodic = 1;
-+ }
-+ /* We can now queue the next isochronous OUT transaction, if one is pending. */
-+ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
-+ fiq_print(FIQDBG_INT, state, "NEXTISO ");
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_NYET1:
-+ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
-+ * we are too late and the TT has dropped its CSPLIT fifo.
-+ */
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ start_next_periodic = 1;
-+ if (hcint.b.nak) {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ } else if (hcint.b.xfercomp) {
-+ fiq_increment_dma_buf(state, num_channels, n);
-+ st->fsm = FIQ_PER_CSPLIT_POLL;
-+ st->nr_errors = 0;
-+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+ handled = 1;
-+ restart = 1;
-+ if (!last_csplit)
-+ start_next_periodic = 0;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ } else if (hcint.b.nyet) {
-+ /* Doh. Data lost. */
-+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_BROKEN_NYET1:
-+ /*
-+ * we got here because our host channel is in the delayed-interrupt
-+ * state and we cannot take a NYET interrupt any later than when it
-+ * occurred. Disable then re-enable the channel if this happens to force
-+ * CSPLITs to occur at the right time.
-+ */
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
-+ if (hcint.b.nak) {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ start_next_periodic = 1;
-+ } else if (hcint.b.xfercomp) {
-+ fiq_increment_dma_buf(state, num_channels, n);
-+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+ st->fsm = FIQ_PER_CSPLIT_POLL;
-+ handled = 1;
-+ restart = 1;
-+ start_next_periodic = 1;
-+ /* Reload HCTSIZ for the next transfer */
-+ fiq_fsm_reload_hctsiz(state, n);
-+ if (!last_csplit)
-+ start_next_periodic = 0;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ } else if (hcint.b.nyet) {
-+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+ start_next_periodic = 1;
-+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/
-+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ }
-+ break;
-+
-+ case FIQ_PER_CSPLIT_POLL:
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+ start_next_periodic = 1;
-+ if (hcint.b.nak) {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ } else if (hcint.b.xfercomp) {
-+ fiq_increment_dma_buf(state, num_channels, n);
-+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+ handled = 1;
-+ restart = 1;
-+ /* Reload HCTSIZ for the next transfer */
-+ fiq_fsm_reload_hctsiz(state, n);
-+ if (!last_csplit)
-+ start_next_periodic = 0;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ } else if (hcint.b.nyet) {
-+ /* Are we a NYET after the first data packet? */
-+ if (st->nrpackets == 0) {
-+ st->fsm = FIQ_PER_CSPLIT_NYET1;
-+ handled = 1;
-+ restart = 1;
-+ } else {
-+ /* We got a NYET when polling CSPLITs. Can happen
-+ * if our heuristic fails, or if someone disables us
-+ * for any significant length of time.
-+ */
-+ if (st->nr_errors >= 3) {
-+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_DONE;
-+ }
-+ }
-+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
-+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+ } else {
-+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+ }
-+ break;
-+
-+ case FIQ_HS_ISOC_TURBO:
-+ if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
-+ /* more transactions to come */
-+ handled = 1;
-+ restart = 1;
-+ fiq_print(FIQDBG_INT, state, "HSISO M ");
-+ } else {
-+ st->fsm = FIQ_HS_ISOC_DONE;
-+ fiq_print(FIQDBG_INT, state, "HSISO F ");
-+ }
-+ break;
-+
-+ case FIQ_HS_ISOC_ABORTED:
-+ /* This abort is called by the driver rewriting the state mid-transaction
-+ * which allows the dequeue mechanism to work more effectively.
-+ */
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_ACTIVE:
-+ if (hcint.b.ack) {
-+ if(fiq_iso_out_advance(state, num_channels, n)) {
-+ /* last OUT transfer */
-+ st->fsm = FIQ_PER_ISO_OUT_LAST;
-+ /*
-+ * Assuming the periodic FIFO in the dwc core
-+ * actually does its job properly, we can queue
-+ * the next ssplit now and in theory, the wire
-+ * transactions will be in-order.
-+ */
-+ // No it doesn't. It appears to process requests in host channel order.
-+ //start_next_periodic = 1;
-+ }
-+ handled = 1;
-+ restart = 1;
-+ } else {
-+ /*
-+ * Isochronous transactions carry on regardless. Log the error
-+ * and continue.
-+ */
-+ //explode += 1;
-+ st->nr_errors++;
-+ if(fiq_iso_out_advance(state, num_channels, n)) {
-+ st->fsm = FIQ_PER_ISO_OUT_LAST;
-+ //start_next_periodic = 1;
-+ }
-+ handled = 1;
-+ restart = 1;
-+ }
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_LAST:
-+ if (hcint.b.ack) {
-+ /* All done here */
-+ st->fsm = FIQ_PER_ISO_OUT_DONE;
-+ } else {
-+ st->fsm = FIQ_PER_ISO_OUT_DONE;
-+ st->nr_errors++;
-+ }
-+ start_next_periodic = 1;
-+ break;
-+
-+ case FIQ_PER_SPLIT_TIMEOUT:
-+ /* SOF kicked us because we overran. */
-+ start_next_periodic = 1;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ if (handled) {
-+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
-+ } else {
-+ /* Copy the regs into the state so the IRQ knows what to do */
-+ st->hcint_copy.d32 = hcint.d32;
-+ }
-+
-+ if (restart) {
-+ /* Restart always implies handled. */
-+ if (restart == 2) {
-+ /* For complete-split INs, the show must go on.
-+ * Force a channel restart */
-+ fiq_fsm_restart_channel(state, n, 1);
-+ } else {
-+ fiq_fsm_restart_channel(state, n, 0);
-+ }
-+ }
-+ if (start_next_periodic) {
-+ fiq_fsm_start_next_periodic(state, num_channels);
-+ }
-+ if (st->fsm != FIQ_PASSTHROUGH)
-+ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
-+
-+ return handled;
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
-+ * @state: pointer to state struct passed from the banked FIQ mode registers.
-+ * @num_channels: set according to the DWC hardware configuration
-+ * @dma: pointer to DMA bounce buffers for split transaction slots
-+ *
-+ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
-+ * inside an EHCI or similar host controller regarding split transactions. The DWC core
-+ * interrupts each and every time a split transaction packet is received or sent successfully.
-+ * This results in either an interrupt storm when everything is working "properly", or
-+ * the interrupt latency of the system in general breaks time-sensitive periodic split
-+ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
-+ * solves these problems.
-+ *
-+ * Return: void
-+ */
-+void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
-+{
-+ gintsts_data_t gintsts, gintsts_handled;
-+ gintmsk_data_t gintmsk;
-+ //hfnum_data_t hfnum;
-+ haint_data_t haint, haint_handled;
-+ haintmsk_data_t haintmsk;
-+ int kick_irq = 0;
-+
-+ gintsts_handled.d32 = 0;
-+ haint_handled.d32 = 0;
-+
-+ fiq_fsm_spin_lock(&state->lock);
-+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
-+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
-+ gintsts.d32 &= gintmsk.d32;
-+
-+ if (gintsts.b.sofintr) {
-+ /* For FSM mode, SOF is required to keep the state machine advance for
-+ * certain stages of the periodic pipeline. It's death to mask this
-+ * interrupt in that case.
-+ */
-+
-+ if (!fiq_fsm_do_sof(state, num_channels)) {
-+ /* Kick IRQ once. Queue advancement means that all pending transactions
-+ * will get serviced when the IRQ finally executes.
-+ */
-+ if (state->gintmsk_saved.b.sofintr == 1)
-+ kick_irq |= 1;
-+ state->gintmsk_saved.b.sofintr = 0;
-+ }
-+ gintsts_handled.b.sofintr = 1;
-+ }
-+
-+ if (gintsts.b.hcintr) {
-+ int i;
-+ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
-+ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
-+ haint.d32 &= haintmsk.d32;
-+ haint_handled.d32 = 0;
-+ for (i=0; i<num_channels; i++) {
-+ if (haint.b2.chint & (1 << i)) {
-+ if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
-+ /* HCINT was not handled in FIQ
-+ * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
-+ * Mask HAINT(i) but keep top-level hcint unmasked.
-+ */
-+ state->haintmsk_saved.b2.chint &= ~(1 << i);
-+ } else {
-+ /* do_hcintr cleaned up after itself, but clear haint */
-+ haint_handled.b2.chint |= (1 << i);
-+ }
-+ }
-+ }
-+
-+ if (haint_handled.b2.chint) {
-+ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
-+ }
-+
-+ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
-+ /*
-+ * This is necessary to avoid multiple retriggers of the MPHI in the case
-+ * where interrupts are held off and HCINTs start to pile up.
-+ * Only wake up the IRQ if a new interrupt came in, was not handled and was
-+ * masked.
-+ */
-+ haintmsk.d32 &= state->haintmsk_saved.d32;
-+ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
-+ kick_irq |= 1;
-+ }
-+ /* Top-Level interrupt - always handled because it's level-sensitive */
-+ gintsts_handled.b.hcintr = 1;
-+ }
-+
-+
-+ /* Clear the bits in the saved register that were not handled but were triggered. */
-+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
-+
-+ /* FIQ didn't handle something - mask has changed - write new mask */
-+ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
-+ gintmsk.d32 &= state->gintmsk_saved.d32;
-+ gintmsk.b.sofintr = 1;
-+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+// fiq_print(FIQDBG_INT, state, "KICKGINT");
-+// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
-+// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
-+ kick_irq |= 1;
-+ }
-+
-+ if (gintsts_handled.d32) {
-+ /* Only applies to edge-sensitive bits in GINTSTS */
-+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
-+ }
-+
-+ /* We got an interrupt, didn't handle it. */
-+ if (kick_irq) {
-+ state->mphi_int_count++;
-+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
-+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
-+
-+ }
-+ state->fiq_done++;
-+ mb();
-+ fiq_fsm_spin_unlock(&state->lock);
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_nop() - FIQ "lite"
-+ * @state: pointer to state struct passed from the banked FIQ mode registers.
-+ *
-+ * The "nop" handler does not intervene on any interrupts other than SOF.
-+ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
-+ * with non-periodic/periodic queues) needs to be kicked.
-+ *
-+ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
-+ *
-+ * Return: void
-+ */
-+void notrace dwc_otg_fiq_nop(struct fiq_state *state)
-+{
-+ gintsts_data_t gintsts, gintsts_handled;
-+ gintmsk_data_t gintmsk;
-+ hfnum_data_t hfnum;
-+
-+ fiq_fsm_spin_lock(&state->lock);
-+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
-+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
-+ gintsts.d32 &= gintmsk.d32;
-+ gintsts_handled.d32 = 0;
-+
-+ if (gintsts.b.sofintr) {
-+ if (!state->kick_np_queues &&
-+ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
-+ /* SOF handled, no work to do, just ACK interrupt */
-+ gintsts_handled.b.sofintr = 1;
-+ } else {
-+ /* Kick IRQ */
-+ state->gintmsk_saved.b.sofintr = 0;
-+ }
-+ }
-+
-+ /* Reset handled interrupts */
-+ if(gintsts_handled.d32) {
-+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
-+ }
-+
-+ /* Clear the bits in the saved register that were not handled but were triggered. */
-+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
-+
-+ /* We got an interrupt, didn't handle it and want to mask it */
-+ if (~(state->gintmsk_saved.d32)) {
-+ state->mphi_int_count++;
-+ gintmsk.d32 &= state->gintmsk_saved.d32;
-+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+ /* Force a clear before another dummy send */
-+ FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
-+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
-+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
-+
-+ }
-+ state->fiq_done++;
-+ mb();
-+ fiq_fsm_spin_unlock(&state->lock);
-+}
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,367 @@
-+/*
-+ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Raspberry Pi nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This FIQ implements functionality that performs split transactions on
-+ * the dwc_otg hardware without any outside intervention. A split transaction
-+ * is "queued" by nominating a specific host channel to perform the entirety
-+ * of a split transaction. This FIQ will then perform the microframe-precise
-+ * scheduling required in each phase of the transaction until completion.
-+ *
-+ * The FIQ functionality has been surgically implanted into the Synopsys
-+ * vendor-provided driver.
-+ *
-+ */
-+
-+#ifndef DWC_OTG_FIQ_FSM_H_
-+#define DWC_OTG_FIQ_FSM_H_
-+
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_hcd.h"
-+#include <linux/kernel.h>
-+#include <linux/irqflags.h>
-+#include <linux/string.h>
-+#include <asm/barrier.h>
-+
-+#if 0
-+#define FLAME_ON(x) \
-+do { \
-+ int gpioreg; \
-+ \
-+ gpioreg = readl(__io_address(0x20200000+0x8)); \
-+ gpioreg &= ~(7 << (x-20)*3); \
-+ gpioreg |= 0x1 << (x-20)*3; \
-+ writel(gpioreg, __io_address(0x20200000+0x8)); \
-+ \
-+ writel(1<<x, __io_address(0x20200000+(0x1C))); \
-+} while (0)
-+
-+#define FLAME_OFF(x) \
-+do { \
-+ writel(1<<x, __io_address(0x20200000+(0x28))); \
-+} while (0)
-+#else
-+#define FLAME_ON(x) do { } while (0)
-+#define FLAME_OFF(X) do { } while (0)
-+#endif
-+
-+/* This is a quick-and-dirty arch-specific register read/write. We know that
-+ * writes to a peripheral on BCM2835 will always arrive in-order, also that
-+ * reads and writes are executed in-order therefore the need for memory barriers
-+ * is obviated if we're only talking to USB.
-+ */
-+#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
-+#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
-+
-+/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
-+#define GINTSTS 0x014
-+#define GINTMSK 0x018
-+/* Debug register. Poll the top of the received packets FIFO. */
-+#define GRXSTSR 0x01C
-+#define HFNUM 0x408
-+#define HAINT 0x414
-+#define HAINTMSK 0x418
-+#define HPRT0 0x440
-+
-+/* HC_regs start from an offset of 0x500 */
-+#define HC_START 0x500
-+#define HC_OFFSET 0x020
-+
-+#define HC_DMA 0x514
-+
-+#define HCCHAR 0x00
-+#define HCSPLT 0x04
-+#define HCINT 0x08
-+#define HCINTMSK 0x0C
-+#define HCTSIZ 0x10
-+
-+#define ISOC_XACTPOS_ALL 0b11
-+#define ISOC_XACTPOS_BEGIN 0b10
-+#define ISOC_XACTPOS_MID 0b00
-+#define ISOC_XACTPOS_END 0b01
-+
-+#define DWC_PID_DATA2 0b01
-+#define DWC_PID_MDATA 0b11
-+#define DWC_PID_DATA1 0b10
-+#define DWC_PID_DATA0 0b00
-+
-+typedef struct {
-+ volatile void* base;
-+ volatile void* ctrl;
-+ volatile void* outdda;
-+ volatile void* outddb;
-+ volatile void* intstat;
-+} mphi_regs_t;
-+
-+enum fiq_debug_level {
-+ FIQDBG_SCHED = (1 << 0),
-+ FIQDBG_INT = (1 << 1),
-+ FIQDBG_ERR = (1 << 2),
-+ FIQDBG_PORTHUB = (1 << 3),
-+};
-+
-+typedef struct {
-+ union {
-+ uint32_t slock;
-+ struct _tickets {
-+ uint16_t owner;
-+ uint16_t next;
-+ } tickets;
-+ };
-+} fiq_lock_t;
-+
-+struct fiq_state;
-+
-+extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
-+#if 0
-+#define fiq_print _fiq_print
-+#else
-+#define fiq_print(x, y, ...)
-+#endif
-+
-+extern bool fiq_enable, fiq_fsm_enable;
-+extern ushort nak_holdoff;
-+
-+/**
-+ * enum fiq_fsm_state - The FIQ FSM states.
-+ *
-+ * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
-+ * USB2.0 specification for host responses to various transaction states.
-+ * There are modifications to this host state machine because of a variety of
-+ * quirks and limitations in the dwc_otg hardware.
-+ *
-+ * The fsm state is also used to communicate back to the driver on completion of
-+ * a split transaction. The end states are used in conjunction with the interrupts
-+ * raised by the final transaction.
-+ */
-+enum fiq_fsm_state {
-+ /* FIQ isn't enabled for this host channel */
-+ FIQ_PASSTHROUGH = 0,
-+ /* For the first interrupt received for this channel,
-+ * the FIQ has to ack any interrupts indicating success. */
-+ FIQ_PASSTHROUGH_ERRORSTATE = 31,
-+ /* Nonperiodic state groups */
-+ FIQ_NP_SSPLIT_STARTED = 1,
-+ FIQ_NP_SSPLIT_RETRY = 2,
-+ FIQ_NP_OUT_CSPLIT_RETRY = 3,
-+ FIQ_NP_IN_CSPLIT_RETRY = 4,
-+ FIQ_NP_SPLIT_DONE = 5,
-+ FIQ_NP_SPLIT_LS_ABORTED = 6,
-+ /* This differentiates a HS transaction error from a LS one
-+ * (handling the hub state is different) */
-+ FIQ_NP_SPLIT_HS_ABORTED = 7,
-+
-+ /* Periodic state groups */
-+ /* Periodic transactions are either started directly by the IRQ handler
-+ * or deferred if the TT is already in use.
-+ */
-+ FIQ_PER_SSPLIT_QUEUED = 8,
-+ FIQ_PER_SSPLIT_STARTED = 9,
-+ FIQ_PER_SSPLIT_LAST = 10,
-+
-+
-+ FIQ_PER_ISO_OUT_PENDING = 11,
-+ FIQ_PER_ISO_OUT_ACTIVE = 12,
-+ FIQ_PER_ISO_OUT_LAST = 13,
-+ FIQ_PER_ISO_OUT_DONE = 27,
-+
-+ FIQ_PER_CSPLIT_WAIT = 14,
-+ FIQ_PER_CSPLIT_NYET1 = 15,
-+ FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
-+ FIQ_PER_CSPLIT_NYET_FAFF = 29,
-+ /* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
-+ FIQ_PER_CSPLIT_POLL = 16,
-+ /* The last CSPLIT for a transaction has been issued, differentiates
-+ * for the state machine to queue the next packet.
-+ */
-+ FIQ_PER_CSPLIT_LAST = 17,
-+
-+ FIQ_PER_SPLIT_DONE = 18,
-+ FIQ_PER_SPLIT_LS_ABORTED = 19,
-+ FIQ_PER_SPLIT_HS_ABORTED = 20,
-+ FIQ_PER_SPLIT_NYET_ABORTED = 21,
-+ /* Frame rollover has occurred without the transaction finishing. */
-+ FIQ_PER_SPLIT_TIMEOUT = 22,
-+
-+ /* FIQ-accelerated HS Isochronous state groups */
-+ FIQ_HS_ISOC_TURBO = 23,
-+ /* For interval > 1, SOF wakes up the isochronous FSM */
-+ FIQ_HS_ISOC_SLEEPING = 24,
-+ FIQ_HS_ISOC_DONE = 25,
-+ FIQ_HS_ISOC_ABORTED = 26,
-+ FIQ_DEQUEUE_ISSUED = 30,
-+ FIQ_TEST = 32,
-+};
-+
-+struct fiq_stack {
-+ int magic1;
-+ uint8_t stack[2048];
-+ int magic2;
-+};
-+
-+
-+/**
-+ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
-+ * @index: Number of slots reported used for IN transactions / number of slots
-+ * transmitted for an OUT transaction
-+ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
-+ *
-+ * Split transaction transfers can have variable length depending on other bus
-+ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
-+ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
-+ * can happen per-frame.
-+ */
-+struct fiq_dma_info {
-+ u8 index;
-+ u8 slot_len[6];
-+};
-+
-+struct __attribute__((packed)) fiq_split_dma_slot {
-+ u8 buf[188];
-+};
-+
-+struct fiq_dma_channel {
-+ struct __attribute__((packed)) fiq_split_dma_slot index[6];
-+};
-+
-+struct fiq_dma_blob {
-+ struct __attribute__((packed)) fiq_dma_channel channel[0];
-+};
-+
-+/**
-+ * struct fiq_hs_isoc_info - USB2.0 isochronous data
-+ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
-+ * @nrframes: Total length of iso_frame_desc array
-+ * @index: Current index (FIQ-maintained)
-+ *
-+ */
-+struct fiq_hs_isoc_info {
-+ struct dwc_otg_hcd_iso_packet_desc *iso_desc;
-+ unsigned int nrframes;
-+ unsigned int index;
-+};
-+
-+/**
-+ * struct fiq_channel_state - FIQ state machine storage
-+ * @fsm: Current state of the channel as understood by the FIQ
-+ * @nr_errors: Number of transaction errors on this split-transaction
-+ * @hub_addr: SSPLIT/CSPLIT destination hub
-+ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub
-+ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For
-+ * split-IN, number of CSPLIT data packets that were received.
-+ * @hcchar_copy:
-+ * @hcsplt_copy:
-+ * @hcintmsk_copy:
-+ * @hctsiz_copy: Copies of the host channel registers.
-+ * For use as scratch, or for returning state.
-+ *
-+ * The fiq_channel_state is state storage between interrupts for a host channel. The
-+ * FSM state is stored here. Members of this structure must only be set up by the
-+ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
-+ * has updated the state to either a COMPLETE state group or ABORT state group.
-+ */
-+
-+struct fiq_channel_state {
-+ enum fiq_fsm_state fsm;
-+ unsigned int nr_errors;
-+ unsigned int hub_addr;
-+ unsigned int port_addr;
-+ /* Hardware bug workaround: sometimes channel halt interrupts are
-+ * delayed until the next SOF. Keep track of when we expected to get interrupted. */
-+ unsigned int expected_uframe;
-+ /* in/out for communicating number of dma buffers used, or number of ISOC to do */
-+ unsigned int nrpackets;
-+ struct fiq_dma_info dma_info;
-+ struct fiq_hs_isoc_info hs_isoc_info;
-+ /* Copies of HC registers - in/out communication from/to IRQ handler
-+ * and for ease of channel setup. A bit of mungeing is performed - for
-+ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
-+ */
-+ hcchar_data_t hcchar_copy;
-+ hcsplt_data_t hcsplt_copy;
-+ hcint_data_t hcint_copy;
-+ hcintmsk_data_t hcintmsk_copy;
-+ hctsiz_data_t hctsiz_copy;
-+ hcdma_data_t hcdma_copy;
-+};
-+
-+/**
-+ * struct fiq_state - top-level FIQ state machine storage
-+ * @mphi_regs: virtual address of the MPHI peripheral register file
-+ * @dwc_regs_base: virtual address of the base of the DWC core register file
-+ * @dma_base: physical address for the base of the DMA bounce buffers
-+ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral
-+ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled.
-+ * Used for determining which interrupts fired to set off the IRQ handler.
-+ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally.
-+ * @np_count: Non-periodic transactions in the active queue
-+ * @np_sent: Count of non-periodic transactions that have completed
-+ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism,
-+ * this is the next frame on which a SOF interrupt is required. Used to hold off
-+ * passing SOF through to the driver until necessary.
-+ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host
-+ * channels configured into the core logic.
-+ *
-+ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
-+ * It contains top-level state information.
-+ */
-+struct fiq_state {
-+ fiq_lock_t lock;
-+ mphi_regs_t mphi_regs;
-+ void *dwc_regs_base;
-+ dma_addr_t dma_base;
-+ struct fiq_dma_blob *fiq_dmab;
-+ void *dummy_send;
-+ gintmsk_data_t gintmsk_saved;
-+ haintmsk_data_t haintmsk_saved;
-+ int mphi_int_count;
-+ unsigned int fiq_done;
-+ unsigned int kick_np_queues;
-+ unsigned int next_sched_frame;
-+#ifdef FIQ_DEBUG
-+ char * buffer;
-+ unsigned int bufsiz;
-+#endif
-+ struct fiq_channel_state channel[0];
-+};
-+
-+extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
-+
-+extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
-+
-+extern int fiq_fsm_too_late(struct fiq_state *st, int n);
-+
-+extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
-+
-+extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
-+
-+extern void dwc_otg_fiq_nop(struct fiq_state *state);
-+
-+#endif /* DWC_OTG_FIQ_FSM_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,81 @@
-+/*
-+ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of Raspberry Pi nor the
-+ * names of its contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+#include <asm/assembler.h>
-+#include <linux/linkage.h>
-+
-+
-+.text
-+
-+.global _dwc_otg_fiq_stub_end;
-+
-+/**
-+ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
-+ * a C-style function call with arguments from the FIQ banked registers.
-+ * r0 = &hcd->fiq_state
-+ * r1 = &hcd->num_channels
-+ * r2 = &hcd->dma_buffers
-+ * Tramples: r0, r1, r2, r4, fp, ip
-+ */
-+
-+ENTRY(_dwc_otg_fiq_stub)
-+ /* Stash unbanked regs - SP will have been set up for us */
-+ mov ip, sp;
-+ stmdb sp!, {r0-r12, lr};
-+#ifdef FIQ_DEBUG
-+ // Cycle profiling - read cycle counter at start
-+ mrc p15, 0, r5, c15, c12, 1;
-+#endif
-+ /* r11 = fp, don't trample it */
-+ mov r4, fp;
-+ /* set EABI frame size */
-+ sub fp, ip, #512;
-+
-+ /* for fiq NOP mode - just need state */
-+ mov r0, r8;
-+ /* r9 = num_channels */
-+ mov r1, r9;
-+ /* r10 = struct *dma_bufs */
-+// mov r2, r10;
-+
-+ /* r4 = &fiq_c_function */
-+ blx r4;
-+#ifdef FIQ_DEBUG
-+ mrc p15, 0, r4, c15, c12, 1;
-+ subs r5, r5, r4;
-+ // r5 is now the cycle count time for executing the FIQ. Store it somewhere?
-+#endif
-+ ldmia sp!, {r0-r12, lr};
-+ subs pc, lr, #4;
-+_dwc_otg_fiq_stub_end:
-+END(_dwc_otg_fiq_stub)
-+
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,4252 @@
-+
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
-+ * $Revision: #104 $
-+ * $Date: 2011/10/24 $
-+ * $Change: 1871159 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/** @file
-+ * This file implements HCD Core. All code in this file is portable and doesn't
-+ * use any OS specific functions.
-+ * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
-+ * header file.
-+ */
-+
-+#include <linux/usb.h>
-+#include <linux/usb/hcd.h>
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+extern bool microframe_schedule;
-+extern uint16_t fiq_fsm_mask, nak_holdoff;
-+
-+//#define DEBUG_HOST_CHANNELS
-+#ifdef DEBUG_HOST_CHANNELS
-+static int last_sel_trans_num_per_scheduled = 0;
-+static int last_sel_trans_num_nonper_scheduled = 0;
-+static int last_sel_trans_num_avail_hc_at_start = 0;
-+static int last_sel_trans_num_avail_hc_at_end = 0;
-+#endif /* DEBUG_HOST_CHANNELS */
-+
-+
-+dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
-+{
-+ return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
-+}
-+
-+/**
-+ * Connection timeout function. An OTG host is required to display a
-+ * message if the device does not connect within 10 seconds.
-+ */
-+void dwc_otg_hcd_connect_timeout(void *ptr)
-+{
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
-+ DWC_PRINTF("Connect Timeout\n");
-+ __DWC_ERROR("Device Not Connected/Responding\n");
-+}
-+
-+#if defined(DEBUG)
-+static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ if (qh->channel != NULL) {
-+ dwc_hc_t *hc = qh->channel;
-+ dwc_list_link_t *item;
-+ dwc_otg_qh_t *qh_item;
-+ int num_channels = hcd->core_if->core_params->host_channels;
-+ int i;
-+
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+ hctsiz_data_t hctsiz;
-+ uint32_t hcdma;
-+
-+ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ hcdma = DWC_READ_REG32(&hc_regs->hcdma);
-+
-+ DWC_PRINTF(" Assigned to channel %p:\n", hc);
-+ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
-+ hcsplt.d32);
-+ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
-+ hcdma);
-+ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
-+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
-+ DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
-+ DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
-+ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
-+ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
-+ DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
-+ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
-+ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
-+ DWC_PRINTF(" qh: %p\n", hc->qh);
-+ DWC_PRINTF(" NP inactive sched:\n");
-+ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
-+ qh_item =
-+ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+ DWC_PRINTF(" %p\n", qh_item);
-+ }
-+ DWC_PRINTF(" NP active sched:\n");
-+ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
-+ qh_item =
-+ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+ DWC_PRINTF(" %p\n", qh_item);
-+ }
-+ DWC_PRINTF(" Channels: \n");
-+ for (i = 0; i < num_channels; i++) {
-+ dwc_hc_t *hc = hcd->hc_ptr_array[i];
-+ DWC_PRINTF(" %2d: %p\n", i, hc);
-+ }
-+ }
-+}
-+#else
-+#define dump_channel_info(hcd, qh)
-+#endif /* DEBUG */
-+
-+/**
-+ * Work queue function for starting the HCD when A-Cable is connected.
-+ * The hcd_start() must be called in a process context.
-+ */
-+static void hcd_start_func(void *_vp)
-+{
-+ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
-+ if (hcd) {
-+ hcd->fops->start(hcd);
-+ }
-+}
-+
-+static void del_xfer_timers(dwc_otg_hcd_t * hcd)
-+{
-+#ifdef DEBUG
-+ int i;
-+ int num_channels = hcd->core_if->core_params->host_channels;
-+ for (i = 0; i < num_channels; i++) {
-+ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
-+ }
-+#endif
-+}
-+
-+static void del_timers(dwc_otg_hcd_t * hcd)
-+{
-+ del_xfer_timers(hcd);
-+ DWC_TIMER_CANCEL(hcd->conn_timer);
-+}
-+
-+/**
-+ * Processes all the URBs in a single list of QHs. Completes them with
-+ * -ESHUTDOWN and frees the QTD.
-+ */
-+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
-+{
-+ dwc_list_link_t *qh_item, *qh_tmp;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+
-+ DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
-+ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
-+ &qh->qtd_list, qtd_list_entry) {
-+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+ if (qtd->urb != NULL) {
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_SHUTDOWN);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+ }
-+
-+ }
-+ if(qh->channel) {
-+ /* Using hcchar.chen == 1 is not a reliable test.
-+ * It is possible that the channel has already halted
-+ * but not yet been through the IRQ handler.
-+ */
-+ dwc_otg_hc_halt(hcd->core_if, qh->channel,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE);
-+ if(microframe_schedule)
-+ hcd->available_host_channels++;
-+ qh->channel = NULL;
-+ }
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ }
-+}
-+
-+/**
-+ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
-+ * and periodic schedules. The QTD associated with each URB is removed from
-+ * the schedule and freed. This function may be called when a disconnect is
-+ * detected or when the HCD is being stopped.
-+ */
-+static void kill_all_urbs(dwc_otg_hcd_t * hcd)
-+{
-+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
-+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
-+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
-+}
-+
-+/**
-+ * Start the connection timer. An OTG host is required to display a
-+ * message if the device does not connect within 10 seconds. The
-+ * timer is deleted if a port connect interrupt occurs before the
-+ * timer expires.
-+ */
-+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
-+{
-+ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
-+}
-+
-+/**
-+ * HCD Callback function for disconnect of the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_session_start_cb(void *p)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
-+ dwc_otg_hcd = p;
-+ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
-+ return 1;
-+}
-+
-+/**
-+ * HCD Callback function for starting the HCD when A-Cable is
-+ * connected.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_start_cb(void *p)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = p;
-+ dwc_otg_core_if_t *core_if;
-+ hprt0_data_t hprt0;
-+
-+ core_if = dwc_otg_hcd->core_if;
-+
-+ if (core_if->op_state == B_HOST) {
-+ /*
-+ * Reset the port. During a HNP mode switch the reset
-+ * needs to occur within 1ms and have a duration of at
-+ * least 50ms.
-+ */
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtrst = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
-+ hcd_start_func, dwc_otg_hcd, 50,
-+ "start hcd");
-+
-+ return 1;
-+}
-+
-+/**
-+ * HCD Callback function for disconnect of the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_disconnect_cb(void *p)
-+{
-+ gintsts_data_t intr;
-+ dwc_otg_hcd_t *dwc_otg_hcd = p;
-+
-+ /*
-+ * Set status flags for the hub driver.
-+ */
-+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
-+ dwc_otg_hcd->flags.b.port_connect_status = 0;
-+ if(fiq_enable)
-+ local_fiq_disable();
-+ /*
-+ * Shutdown any transfers in process by clearing the Tx FIFO Empty
-+ * interrupt mask and status bits and disabling subsequent host
-+ * channel interrupts.
-+ */
-+ intr.d32 = 0;
-+ intr.b.nptxfempty = 1;
-+ intr.b.ptxfempty = 1;
-+ intr.b.hcintr = 1;
-+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
-+ intr.d32, 0);
-+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
-+ intr.d32, 0);
-+
-+ del_timers(dwc_otg_hcd);
-+
-+ /*
-+ * Turn off the vbus power only if the core has transitioned to device
-+ * mode. If still in host mode, need to keep power on to detect a
-+ * reconnection.
-+ */
-+ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
-+ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+ DWC_PRINTF("Disconnect: PortPower off\n");
-+ hprt0.b.prtpwr = 0;
-+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
-+ hprt0.d32);
-+ }
-+
-+ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
-+ }
-+
-+ /* Respond with an error status to all URBs in the schedule. */
-+ kill_all_urbs(dwc_otg_hcd);
-+
-+ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
-+ /* Clean up any host channels that were in use. */
-+ int num_channels;
-+ int i;
-+ dwc_hc_t *channel;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ hcchar_data_t hcchar;
-+
-+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
-+
-+ if (!dwc_otg_hcd->core_if->dma_enable) {
-+ /* Flush out any channel requests in slave mode. */
-+ for (i = 0; i < num_channels; i++) {
-+ channel = dwc_otg_hcd->hc_ptr_array[i];
-+ if (DWC_CIRCLEQ_EMPTY_ENTRY
-+ (channel, hc_list_entry)) {
-+ hc_regs =
-+ dwc_otg_hcd->core_if->
-+ host_if->hc_regs[i];
-+ hcchar.d32 =
-+ DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chen = 0;
-+ hcchar.b.chdis = 1;
-+ hcchar.b.epdir = 0;
-+ DWC_WRITE_REG32
-+ (&hc_regs->hcchar,
-+ hcchar.d32);
-+ }
-+ }
-+ }
-+ }
-+
-+ for (i = 0; i < num_channels; i++) {
-+ channel = dwc_otg_hcd->hc_ptr_array[i];
-+ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
-+ hc_regs =
-+ dwc_otg_hcd->core_if->host_if->hc_regs[i];
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ /* Halt the channel. */
-+ hcchar.b.chdis = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar,
-+ hcchar.d32);
-+ }
-+
-+ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
-+ channel);
-+ DWC_CIRCLEQ_INSERT_TAIL
-+ (&dwc_otg_hcd->free_hc_list, channel,
-+ hc_list_entry);
-+ /*
-+ * Added for Descriptor DMA to prevent channel double cleanup
-+ * in release_channel_ddma(). Which called from ep_disable
-+ * when device disconnect.
-+ */
-+ channel->qh = NULL;
-+ }
-+ }
-+ if(fiq_fsm_enable) {
-+ for(i=0; i < 128; i++) {
-+ dwc_otg_hcd->hub_port[i] = 0;
-+ }
-+ }
-+
-+ }
-+
-+ if(fiq_enable)
-+ local_fiq_enable();
-+
-+ if (dwc_otg_hcd->fops->disconnect) {
-+ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * HCD Callback function for stopping the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_stop_cb(void *p)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = p;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
-+ dwc_otg_hcd_stop(dwc_otg_hcd);
-+ return 1;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * HCD Callback function for sleep of HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int dwc_otg_hcd_sleep_cb(void *p)
-+{
-+ dwc_otg_hcd_t *hcd = p;
-+
-+ dwc_otg_hcd_free_hc_from_lpm(hcd);
-+
-+ return 0;
-+}
-+#endif
-+
-+
-+/**
-+ * HCD Callback function for Remote Wakeup.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int dwc_otg_hcd_rem_wakeup_cb(void *p)
-+{
-+ dwc_otg_hcd_t *hcd = p;
-+
-+ if (hcd->core_if->lx_state == DWC_OTG_L2) {
-+ hcd->flags.b.port_suspend_change = 1;
-+ }
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ else {
-+ hcd->flags.b.port_l1_change = 1;
-+ }
-+#endif
-+ return 0;
-+}
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ */
-+void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
-+{
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
-+
-+ /*
-+ * The root hub should be disconnected before this function is called.
-+ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
-+ * and the QH lists (via ..._hcd_endpoint_disable).
-+ */
-+
-+ /* Turn off all host-specific interrupts. */
-+ dwc_otg_disable_host_interrupts(hcd->core_if);
-+
-+ /* Turn off the vbus power */
-+ DWC_PRINTF("PortPower off\n");
-+ hprt0.b.prtpwr = 0;
-+ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
-+ dwc_mdelay(1);
-+}
-+
-+int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
-+ int atomic_alloc)
-+{
-+ int retval = 0;
-+ uint8_t needs_scheduling = 0;
-+ dwc_otg_transaction_type_e tr_type;
-+ dwc_otg_qtd_t *qtd;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ hprt0_data_t hprt0 = { .d32 = 0 };
-+
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+ if (NULL == hcd->core_if) {
-+ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
-+ /* No longer connected. */
-+ return -DWC_E_INVALID;
-+ }
-+#endif
-+ if (!hcd->flags.b.port_connect_status) {
-+ /* No longer connected. */
-+ DWC_ERROR("Not connected\n");
-+ return -DWC_E_NO_DEVICE;
-+ }
-+
-+ /* Some core configurations cannot support LS traffic on a FS root port */
-+ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
-+ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
-+ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+ return -DWC_E_NO_DEVICE;
-+ }
-+ }
-+
-+ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
-+ if (qtd == NULL) {
-+ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+ if (qtd->urb == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ if (qtd->urb->priv == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+#endif
-+ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
-+ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
-+ if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
-+ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
-+ needs_scheduling = 0;
-+
-+ retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
-+ // creates a new queue in ep_handle if it doesn't exist already
-+ if (retval < 0) {
-+ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
-+ "Error status %d\n", retval);
-+ dwc_otg_hcd_qtd_free(qtd);
-+ return retval;
-+ }
-+
-+ if(needs_scheduling) {
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ }
-+ }
-+ return retval;
-+}
-+
-+int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_qtd_t *urb_qtd;
-+ BUG_ON(!hcd);
-+ BUG_ON(!dwc_otg_urb);
-+
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+
-+ if (hcd == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
-+ return -DWC_E_INVALID;
-+ }
-+ if (dwc_otg_urb == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
-+ return -DWC_E_INVALID;
-+ }
-+ if (dwc_otg_urb->qtd == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
-+ return -DWC_E_INVALID;
-+ }
-+ urb_qtd = dwc_otg_urb->qtd;
-+ BUG_ON(!urb_qtd);
-+ if (urb_qtd->qh == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
-+ return -DWC_E_INVALID;
-+ }
-+#else
-+ urb_qtd = dwc_otg_urb->qtd;
-+ BUG_ON(!urb_qtd);
-+#endif
-+ qh = urb_qtd->qh;
-+ BUG_ON(!qh);
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ if (urb_qtd->in_process) {
-+ dump_channel_info(hcd, qh);
-+ }
-+ }
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+ if (hcd->core_if == NULL) {
-+ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
-+ return -DWC_E_INVALID;
-+ }
-+#endif
-+ if (urb_qtd->in_process && qh->channel) {
-+ /* The QTD is in process (it has been assigned to a channel). */
-+ if (hcd->flags.b.port_connect_status) {
-+ int n = qh->channel->hc_num;
-+ /*
-+ * If still connected (i.e. in host mode), halt the
-+ * channel so it can be used for other transfers. If
-+ * no longer connected, the host registers can't be
-+ * written to halt the channel since the core is in
-+ * device mode.
-+ */
-+ /* In FIQ FSM mode, we need to shut down carefully.
-+ * The FIQ may attempt to restart a disabled channel */
-+ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
-+ qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
-+ qh->channel->halt_pending = 1;
-+ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
-+ } else {
-+ dwc_otg_hc_halt(hcd->core_if, qh->channel,
-+ DWC_OTG_HC_XFER_URB_DEQUEUE);
-+ }
-+ }
-+ }
-+
-+ /*
-+ * Free the QTD and clean up the associated QH. Leave the QH in the
-+ * schedule if it has any remaining QTDs.
-+ */
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
-+ "delete %sQueue handler\n",
-+ hcd->core_if->dma_desc_enable?"DMA ":"");
-+ if (!hcd->core_if->dma_desc_enable) {
-+ uint8_t b = urb_qtd->in_process;
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
-+ if (b) {
-+ dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
-+ qh->channel = NULL;
-+ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ }
-+ } else {
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
-+ }
-+ return 0;
-+}
-+
-+int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
-+ int retry)
-+{
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ int retval = 0;
-+ dwc_irqflags_t flags;
-+
-+ if (retry < 0) {
-+ retval = -DWC_E_INVALID;
-+ goto done;
-+ }
-+
-+ if (!qh) {
-+ retval = -DWC_E_INVALID;
-+ goto done;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+
-+ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ retry--;
-+ dwc_msleep(5);
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ }
-+
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ /*
-+ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
-+ * and qh_free to prevent stack dump on DWC_DMA_FREE() with
-+ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
-+ * and dwc_otg_hcd_frame_list_alloc().
-+ */
-+ dwc_otg_hcd_qh_free(hcd, qh);
-+
-+done:
-+ return retval;
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ int retval = 0;
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ if (!qh)
-+ return -DWC_E_INVALID;
-+
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ return retval;
-+}
-+#endif
-+
-+/**
-+ * HCD Callback structure for handling mode switching.
-+ */
-+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
-+ .start = dwc_otg_hcd_start_cb,
-+ .stop = dwc_otg_hcd_stop_cb,
-+ .disconnect = dwc_otg_hcd_disconnect_cb,
-+ .session_start = dwc_otg_hcd_session_start_cb,
-+ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ .sleep = dwc_otg_hcd_sleep_cb,
-+#endif
-+ .p = 0,
-+};
-+
-+/**
-+ * Reset tasklet function
-+ */
-+static void reset_tasklet_func(void *data)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
-+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+ hprt0_data_t hprt0;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtrst = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ dwc_mdelay(60);
-+
-+ hprt0.b.prtrst = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ dwc_otg_hcd->flags.b.port_reset_change = 1;
-+}
-+
-+static void completion_tasklet_func(void *ptr)
-+{
-+ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
-+ struct urb *urb;
-+ urb_tq_entry_t *item;
-+ dwc_irqflags_t flags;
-+
-+ /* This could just be spin_lock_irq */
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
-+ item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
-+ urb = item->urb;
-+ DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
-+ urb_tq_entries);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ DWC_FREE(item);
-+
-+ usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
-+
-+
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ return;
-+}
-+
-+static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
-+{
-+ dwc_list_link_t *item;
-+ dwc_otg_qh_t *qh;
-+ dwc_irqflags_t flags;
-+
-+ if (!qh_list->next) {
-+ /* The list hasn't been initialized yet. */
-+ return;
-+ }
-+ /*
-+ * Hold spinlock here. Not needed in that case if bellow
-+ * function is being called from ISR
-+ */
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ /* Ensure there are no QTDs or URBs left. */
-+ kill_urbs_in_qh_list(hcd, qh_list);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+
-+ DWC_LIST_FOREACH(item, qh_list) {
-+ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+ dwc_otg_hcd_qh_remove_and_free(hcd, qh);
-+ }
-+}
-+
-+/**
-+ * Exit from Hibernation if Host did not detect SRP from connected SRP capable
-+ * Device during SRP time by host power up.
-+ */
-+void dwc_otg_hcd_power_up(void *ptr)
-+{
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+
-+ DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+ if (!core_if->hibernation_suspend) {
-+ DWC_PRINTF("Already exited from Hibernation\n");
-+ return;
-+ }
-+
-+ /* Switch on the voltage to the core */
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Reset the core */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Disable power clamps */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ /* Remove reset the core signal */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnrstn = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Disable PMU interrupt */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ core_if->hibernation_suspend = 0;
-+
-+ /* Disable PMU */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+ dwc_udelay(10);
-+
-+ /* Enable VBUS */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+ core_if->op_state = A_HOST;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_hcd_start(core_if);
-+}
-+
-+void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
-+{
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+ struct fiq_dma_blob *blob = hcd->fiq_dmab;
-+ int i;
-+
-+ st->fsm = FIQ_PASSTHROUGH;
-+ st->hcchar_copy.d32 = 0;
-+ st->hcsplt_copy.d32 = 0;
-+ st->hcint_copy.d32 = 0;
-+ st->hcintmsk_copy.d32 = 0;
-+ st->hctsiz_copy.d32 = 0;
-+ st->hcdma_copy.d32 = 0;
-+ st->nr_errors = 0;
-+ st->hub_addr = 0;
-+ st->port_addr = 0;
-+ st->expected_uframe = 0;
-+ st->nrpackets = 0;
-+ st->dma_info.index = 0;
-+ for (i = 0; i < 6; i++)
-+ st->dma_info.slot_len[i] = 255;
-+ st->hs_isoc_info.index = 0;
-+ st->hs_isoc_info.iso_desc = NULL;
-+ st->hs_isoc_info.nrframes = 0;
-+
-+ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
-+}
-+
-+/**
-+ * Frees secondary storage associated with the dwc_otg_hcd structure contained
-+ * in the struct usb_hcd field.
-+ */
-+static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int i;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
-+
-+ del_timers(dwc_otg_hcd);
-+
-+ /* Free memory for QH/QTD lists */
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
-+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
-+
-+ /* Free memory for the host channels. */
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
-+
-+#ifdef DEBUG
-+ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
-+ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
-+ }
-+#endif
-+ if (hc != NULL) {
-+ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
-+ i, hc);
-+ DWC_FREE(hc);
-+ }
-+ }
-+
-+ if (dwc_otg_hcd->core_if->dma_enable) {
-+ if (dwc_otg_hcd->status_buf_dma) {
-+ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
-+ dwc_otg_hcd->status_buf,
-+ dwc_otg_hcd->status_buf_dma);
-+ }
-+ } else if (dwc_otg_hcd->status_buf != NULL) {
-+ DWC_FREE(dwc_otg_hcd->status_buf);
-+ }
-+ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock);
-+ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
-+ /* Set core_if's lock pointer to NULL */
-+ dwc_otg_hcd->core_if->lock = NULL;
-+
-+ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
-+ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
-+ DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
-+ DWC_FREE(dwc_otg_hcd->fiq_state);
-+
-+#ifdef DWC_DEV_SRPCAP
-+ if (dwc_otg_hcd->core_if->power_down == 2 &&
-+ dwc_otg_hcd->core_if->pwron_timer) {
-+ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
-+ }
-+#endif
-+ DWC_FREE(dwc_otg_hcd);
-+}
-+
-+int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
-+
-+int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
-+{
-+ int retval = 0;
-+ int num_channels;
-+ int i;
-+ dwc_hc_t *channel;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);
-+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock);
-+#else
-+ hcd->lock = DWC_SPINLOCK_ALLOC();
-+ hcd->channel_lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
-+ hcd, core_if);
-+ if (!hcd->lock) {
-+ DWC_ERROR("Could not allocate lock for pcd");
-+ DWC_FREE(hcd);
-+ retval = -DWC_E_NO_MEMORY;
-+ goto out;
-+ }
-+ hcd->core_if = core_if;
-+
-+ /* Register the HCD CIL Callbacks */
-+ dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
-+ &hcd_cil_callbacks, hcd);
-+
-+ /* Initialize the non-periodic schedule. */
-+ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
-+ DWC_LIST_INIT(&hcd->non_periodic_sched_active);
-+
-+ /* Initialize the periodic schedule. */
-+ DWC_LIST_INIT(&hcd->periodic_sched_inactive);
-+ DWC_LIST_INIT(&hcd->periodic_sched_ready);
-+ DWC_LIST_INIT(&hcd->periodic_sched_assigned);
-+ DWC_LIST_INIT(&hcd->periodic_sched_queued);
-+ DWC_TAILQ_INIT(&hcd->completed_urb_list);
-+ /*
-+ * Create a host channel descriptor for each host channel implemented
-+ * in the controller. Initialize the channel descriptor array.
-+ */
-+ DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
-+ for (i = 0; i < num_channels; i++) {
-+ channel = DWC_ALLOC(sizeof(dwc_hc_t));
-+ if (channel == NULL) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: host channel allocation failed\n",
-+ __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+ channel->hc_num = i;
-+ hcd->hc_ptr_array[i] = channel;
-+#ifdef DEBUG
-+ hcd->core_if->hc_xfer_timer[i] =
-+ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
-+ &hcd->core_if->hc_xfer_info[i]);
-+#endif
-+ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
-+ channel);
-+ }
-+
-+ if (fiq_enable) {
-+ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
-+ if (!hcd->fiq_state) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
-+
-+ for (i = 0; i < num_channels; i++) {
-+ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
-+ }
-+ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
-+
-+ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
-+ if (!hcd->fiq_stack) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+ hcd->fiq_stack->magic1 = 0xDEADBEEF;
-+ hcd->fiq_stack->magic2 = 0xD00DFEED;
-+ hcd->fiq_state->gintmsk_saved.d32 = ~0;
-+ hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
-+
-+ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
-+ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
-+ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
-+ * moderately readable array casts.
-+ */
-+ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
-+ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
-+ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
-+ sizeof(struct fiq_dma_channel) * num_channels);
-+
-+ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
-+
-+ /* pointer for debug in fiq_print */
-+ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
-+ if (fiq_fsm_enable) {
-+ int i;
-+ for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
-+ dwc_otg_cleanup_fiq_channel(hcd, i);
-+ }
-+ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
-+ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
-+ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
-+ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
-+ (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
-+ }
-+ }
-+
-+ /* Initialize the Connection timeout timer. */
-+ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
-+ dwc_otg_hcd_connect_timeout, 0);
-+
-+ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
-+ if (microframe_schedule)
-+ init_hcd_usecs(hcd);
-+
-+ /* Initialize reset tasklet. */
-+ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
-+
-+ hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
-+ completion_tasklet_func, hcd);
-+#ifdef DWC_DEV_SRPCAP
-+ if (hcd->core_if->power_down == 2) {
-+ /* Initialize Power on timer for Host power up in case hibernation */
-+ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
-+ dwc_otg_hcd_power_up, core_if);
-+ }
-+#endif
-+
-+ /*
-+ * Allocate space for storing data on status transactions. Normally no
-+ * data is sent, but this space acts as a bit bucket. This must be
-+ * done after usb_add_hcd since that function allocates the DMA buffer
-+ * pool.
-+ */
-+ if (hcd->core_if->dma_enable) {
-+ hcd->status_buf =
-+ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
-+ &hcd->status_buf_dma);
-+ } else {
-+ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
-+ }
-+ if (!hcd->status_buf) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: status_buf allocation failed\n", __func__);
-+ dwc_otg_hcd_free(hcd);
-+ goto out;
-+ }
-+
-+ hcd->otg_port = 1;
-+ hcd->frame_list = NULL;
-+ hcd->frame_list_dma = 0;
-+ hcd->periodic_qh_count = 0;
-+
-+ DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
-+#ifdef FIQ_DEBUG
-+ DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
-+#endif
-+
-+out:
-+ return retval;
-+}
-+
-+void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
-+{
-+ /* Turn off all host-specific interrupts. */
-+ dwc_otg_disable_host_interrupts(hcd->core_if);
-+
-+ dwc_otg_hcd_free(hcd);
-+}
-+
-+/**
-+ * Initializes dynamic portions of the DWC_otg HCD state.
-+ */
-+static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
-+{
-+ int num_channels;
-+ int i;
-+ dwc_hc_t *channel;
-+ dwc_hc_t *channel_tmp;
-+
-+ hcd->flags.d32 = 0;
-+
-+ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
-+ if (!microframe_schedule) {
-+ hcd->non_periodic_channels = 0;
-+ hcd->periodic_channels = 0;
-+ } else {
-+ hcd->available_host_channels = hcd->core_if->core_params->host_channels;
-+ }
-+ /*
-+ * Put all channels in the free channel list and clean up channel
-+ * states.
-+ */
-+ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
-+ &hcd->free_hc_list, hc_list_entry) {
-+ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
-+ }
-+
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ for (i = 0; i < num_channels; i++) {
-+ channel = hcd->hc_ptr_array[i];
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
-+ hc_list_entry);
-+ dwc_otg_hc_cleanup(hcd->core_if, channel);
-+ }
-+
-+ /* Initialize the DWC core for host mode operation. */
-+ dwc_otg_core_host_init(hcd->core_if);
-+
-+ /* Set core_if's lock pointer to the hcd->lock */
-+ hcd->core_if->lock = hcd->lock;
-+}
-+
-+/**
-+ * Assigns transactions from a QTD to a free host channel and initializes the
-+ * host channel to perform the transactions. The host channel is removed from
-+ * the free list.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param qh Transactions from the first QTD for this QH are selected and
-+ * assigned to a free host channel.
-+ */
-+static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ dwc_hc_t *hc;
-+ dwc_otg_qtd_t *qtd;
-+ dwc_otg_hcd_urb_t *urb;
-+ void* ptr = NULL;
-+ uint32_t intr_enable;
-+ unsigned long flags;
-+ gintmsk_data_t gintmsk = { .d32 = 0, };
-+
-+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+ urb = qtd->urb;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
-+
-+ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
-+ urb->actual_length = urb->length;
-+
-+
-+ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
-+
-+ /* Remove the host channel from the free list. */
-+ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+ qh->channel = hc;
-+
-+ qtd->in_process = 1;
-+
-+ /*
-+ * Use usb_pipedevice to determine device address. This address is
-+ * 0 before the SET_ADDRESS command and the correct address afterward.
-+ */
-+ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
-+ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
-+ hc->speed = qh->dev_speed;
-+ hc->max_packet = dwc_max_packet(qh->maxp);
-+
-+ hc->xfer_started = 0;
-+ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
-+ hc->error_state = (qtd->error_count > 0);
-+ hc->halt_on_queue = 0;
-+ hc->halt_pending = 0;
-+ hc->requests = 0;
-+
-+ /*
-+ * The following values may be modified in the transfer type section
-+ * below. The xfer_len value may be reduced when the transfer is
-+ * started to accommodate the max widths of the XferSize and PktCnt
-+ * fields in the HCTSIZn register.
-+ */
-+
-+ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
-+ if (hc->ep_is_in) {
-+ hc->do_ping = 0;
-+ } else {
-+ hc->do_ping = qh->ping_state;
-+ }
-+
-+ hc->data_pid_start = qh->data_toggle;
-+ hc->multi_count = 1;
-+
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
-+
-+ /* For non-dword aligned case */
-+ if (((unsigned long)hc->xfer_buff & 0x3)
-+ && !hcd->core_if->dma_desc_enable) {
-+ ptr = (uint8_t *) urb->buf + urb->actual_length;
-+ }
-+ } else {
-+ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
-+ }
-+ hc->xfer_len = urb->length - urb->actual_length;
-+ hc->xfer_count = 0;
-+
-+ /*
-+ * Set the split attributes
-+ */
-+ hc->do_split = 0;
-+ if (qh->do_split) {
-+ uint32_t hub_addr, port_addr;
-+ hc->do_split = 1;
-+ hc->xact_pos = qtd->isoc_split_pos;
-+ /* We don't need to do complete splits anymore */
-+// if(fiq_fsm_enable)
-+ if (0)
-+ hc->complete_split = qtd->complete_split = 0;
-+ else
-+ hc->complete_split = qtd->complete_split;
-+
-+ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
-+ hc->hub_addr = (uint8_t) hub_addr;
-+ hc->port_addr = (uint8_t) port_addr;
-+ }
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
-+ case UE_CONTROL:
-+ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
-+ switch (qtd->control_phase) {
-+ case DWC_OTG_CONTROL_SETUP:
-+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
-+ hc->do_ping = 0;
-+ hc->ep_is_in = 0;
-+ hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) urb->setup_dma;
-+ } else {
-+ hc->xfer_buff = (uint8_t *) urb->setup_packet;
-+ }
-+ hc->xfer_len = 8;
-+ ptr = NULL;
-+ break;
-+ case DWC_OTG_CONTROL_DATA:
-+ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
-+ hc->data_pid_start = qtd->data_toggle;
-+ break;
-+ case DWC_OTG_CONTROL_STATUS:
-+ /*
-+ * Direction is opposite of data direction or IN if no
-+ * data.
-+ */
-+ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
-+ if (urb->length == 0) {
-+ hc->ep_is_in = 1;
-+ } else {
-+ hc->ep_is_in =
-+ dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
-+ }
-+ if (hc->ep_is_in) {
-+ hc->do_ping = 0;
-+ }
-+
-+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+
-+ hc->xfer_len = 0;
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
-+ } else {
-+ hc->xfer_buff = (uint8_t *) hcd->status_buf;
-+ }
-+ ptr = NULL;
-+ break;
-+ }
-+ break;
-+ case UE_BULK:
-+ hc->ep_type = DWC_OTG_EP_TYPE_BULK;
-+ break;
-+ case UE_INTERRUPT:
-+ hc->ep_type = DWC_OTG_EP_TYPE_INTR;
-+ break;
-+ case UE_ISOCHRONOUS:
-+ {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+ hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
-+
-+ if (hcd->core_if->dma_desc_enable)
-+ break;
-+
-+ frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
-+
-+ frame_desc->status = 0;
-+
-+ if (hcd->core_if->dma_enable) {
-+ hc->xfer_buff = (uint8_t *) urb->dma;
-+ } else {
-+ hc->xfer_buff = (uint8_t *) urb->buf;
-+ }
-+ hc->xfer_buff +=
-+ frame_desc->offset + qtd->isoc_split_offset;
-+ hc->xfer_len =
-+ frame_desc->length - qtd->isoc_split_offset;
-+
-+ /* For non-dword aligned buffers */
-+ if (((unsigned long)hc->xfer_buff & 0x3)
-+ && hcd->core_if->dma_enable) {
-+ ptr =
-+ (uint8_t *) urb->buf + frame_desc->offset +
-+ qtd->isoc_split_offset;
-+ } else
-+ ptr = NULL;
-+
-+ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
-+ if (hc->xfer_len <= 188) {
-+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+ } else {
-+ hc->xact_pos =
-+ DWC_HCSPLIT_XACTPOS_BEGIN;
-+ }
-+ }
-+ }
-+ break;
-+ }
-+ /* non DWORD-aligned buffer case */
-+ if (ptr) {
-+ uint32_t buf_size;
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ buf_size = hcd->core_if->core_params->max_transfer_size;
-+ } else {
-+ buf_size = 4096;
-+ }
-+ if (!qh->dw_align_buf) {
-+ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
-+ &qh->dw_align_buf_dma);
-+ if (!qh->dw_align_buf) {
-+ DWC_ERROR
-+ ("%s: Failed to allocate memory to handle "
-+ "non-dword aligned buffer case\n",
-+ __func__);
-+ return;
-+ }
-+ }
-+ if (!hc->ep_is_in) {
-+ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
-+ }
-+ hc->align_buff = qh->dw_align_buf_dma;
-+ } else {
-+ hc->align_buff = 0;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * This value may be modified when the transfer is started to
-+ * reflect the actual transfer length.
-+ */
-+ hc->multi_count = dwc_hb_mult(qh->maxp);
-+ }
-+
-+ if (hcd->core_if->dma_desc_enable)
-+ hc->desc_list_addr = qh->desc_list_dma;
-+
-+ dwc_otg_hc_init(hcd->core_if, hc);
-+
-+ local_irq_save(flags);
-+
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ }
-+
-+ /* Enable the top level host channel interrupt. */
-+ intr_enable = (1 << hc->hc_num);
-+ DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);
-+
-+ /* Make sure host channel interrupts are enabled. */
-+ gintmsk.b.hcintr = 1;
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+
-+ if (fiq_enable) {
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ }
-+
-+ local_irq_restore(flags);
-+ hc->qh = qh;
-+}
-+
-+
-+/**
-+ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
-+ * @qh: pointer to the endpoint's queue head
-+ *
-+ * Transaction start/end control flow is grafted onto the existing dwc_otg
-+ * mechanisms, to avoid spaghettifying the functions more than they already are.
-+ * This function's eligibility check is altered by debug parameter.
-+ *
-+ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
-+ */
-+
-+int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh)
-+{
-+ if (qh->do_split) {
-+ switch (qh->ep_type) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ if (fiq_fsm_mask & (1 << 0))
-+ return 1;
-+ break;
-+ case UE_INTERRUPT:
-+ case UE_ISOCHRONOUS:
-+ if (fiq_fsm_mask & (1 << 1))
-+ return 1;
-+ break;
-+ default:
-+ break;
-+ }
-+ } else if (qh->ep_type == UE_ISOCHRONOUS) {
-+ if (fiq_fsm_mask & (1 << 2)) {
-+ /* HS ISOCH support. We test for compatibility:
-+ * - DWORD aligned buffers
-+ * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
-+ * If yes, then the fsm enqueue function will handle the state machine setup.
-+ */
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs;
-+ int nr_iso_frames = urb->packet_count;
-+ int i;
-+ uint32_t ptr;
-+
-+ if (nr_iso_frames < 2)
-+ return 0;
-+ for (i = 0; i < nr_iso_frames; i++) {
-+ ptr = urb->dma + iso_descs[i]->offset;
-+ if (ptr & 0x3) {
-+ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset."
-+ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n",
-+ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num);
-+ return 0;
-+ }
-+ }
-+ return 1;
-+ }
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * Periodic split transactions are transmitted modulo 188 bytes.
-+ * This necessitates slicing data up into buckets for isochronous out
-+ * and fixing up the DMA address for all IN transfers.
-+ *
-+ * Returns 1 if the DMA bounce buffers have been used, 0 if the default
-+ * HC buffer has been used.
-+ */
-+int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
-+ {
-+ int frame_length, i = 0;
-+ uint8_t *ptr = NULL;
-+ dwc_hc_t *hc = qh->channel;
-+ struct fiq_dma_blob *blob;
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+ for (i = 0; i < 6; i++) {
-+ st->dma_info.slot_len[i] = 255;
-+ }
-+ st->dma_info.index = 0;
-+ i = 0;
-+ if (hc->ep_is_in) {
-+ /*
-+ * Set dma_regs to bounce buffer. FIQ will update the
-+ * state depending on transaction progress.
-+ */
-+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
-+ /* Calculate the max number of CSPLITS such that the FIQ can time out
-+ * a transaction if it fails.
-+ */
-+ frame_length = st->hcchar_copy.b.mps;
-+ do {
-+ i++;
-+ frame_length -= 188;
-+ } while (frame_length >= 0);
-+ st->nrpackets = i;
-+ return 1;
-+ } else {
-+ if (qh->ep_type == UE_ISOCHRONOUS) {
-+
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ frame_length = frame_desc->length;
-+
-+ /* Virtual address for bounce buffers */
-+ blob = hcd->fiq_dmab;
-+
-+ ptr = qtd->urb->buf + frame_desc->offset;
-+ if (frame_length == 0) {
-+ /*
-+ * for isochronous transactions, we must still transmit a packet
-+ * even if the length is zero.
-+ */
-+ st->dma_info.slot_len[0] = 0;
-+ st->nrpackets = 1;
-+ } else {
-+ do {
-+ if (frame_length <= 188) {
-+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
-+ st->dma_info.slot_len[i] = frame_length;
-+ ptr += frame_length;
-+ } else {
-+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
-+ st->dma_info.slot_len[i] = 188;
-+ ptr += 188;
-+ }
-+ i++;
-+ frame_length -= 188;
-+ } while (frame_length > 0);
-+ st->nrpackets = i;
-+ }
-+ ptr = qtd->urb->buf + frame_desc->offset;
-+ /* Point the HC at the DMA address of the bounce buffers */
-+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
-+
-+ /* fixup xfersize to the actual packet size */
-+ st->hctsiz_copy.b.pid = 0;
-+ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
-+ return 1;
-+ } else {
-+ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
-+ return 0;
-+ }
-+ }
-+}
-+
-+/*
-+ * Pushing a periodic request into the queue near the EOF1 point
-+ * in a microframe causes erroneous behaviour (frmovrun) interrupt.
-+ * Usually, the request goes out on the bus causing a transfer but
-+ * the core does not transfer the data to memory.
-+ * This guard interval (in number of 60MHz clocks) is required which
-+ * must cater for CPU latency between reading the value and enabling
-+ * the channel.
-+ */
-+#define PERIODIC_FRREM_BACKOFF 1000
-+
-+int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+ dwc_hc_t *hc = qh->channel;
-+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+ int frame;
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
-+ int xfer_len, nrpackets;
-+ hcdma_data_t hcdma;
-+ hfnum_data_t hfnum;
-+
-+ if (st->fsm != FIQ_PASSTHROUGH)
-+ return 0;
-+
-+ st->nr_errors = 0;
-+
-+ st->hcchar_copy.d32 = 0;
-+ st->hcchar_copy.b.mps = hc->max_packet;
-+ st->hcchar_copy.b.epdir = hc->ep_is_in;
-+ st->hcchar_copy.b.devaddr = hc->dev_addr;
-+ st->hcchar_copy.b.epnum = hc->ep_num;
-+ st->hcchar_copy.b.eptype = hc->ep_type;
-+
-+ st->hcintmsk_copy.b.chhltd = 1;
-+
-+ frame = dwc_otg_hcd_get_frame_number(hcd);
-+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
-+
-+ st->hcchar_copy.b.lspddev = 0;
-+ /* Enable the channel later as a final register write. */
-+
-+ st->hcsplt_copy.d32 = 0;
-+
-+ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
-+ st->hs_isoc_info.nrframes = qtd->urb->packet_count;
-+ /* grab the next DMA address offset from the array */
-+ st->hcdma_copy.d32 = qtd->urb->dma;
-+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
-+
-+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
-+ * the core needs to be told to send the correct number. Caution: for IN transfers,
-+ * this is always set to the maximum size of the endpoint. */
-+ xfer_len = st->hs_isoc_info.iso_desc[0].length;
-+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
-+ if (nrpackets == 0)
-+ nrpackets = 1;
-+ st->hcchar_copy.b.multicnt = nrpackets;
-+ st->hctsiz_copy.b.pktcnt = nrpackets;
-+
-+ /* Initial PID also needs to be set */
-+ if (st->hcchar_copy.b.epdir == 0) {
-+ st->hctsiz_copy.b.xfersize = xfer_len;
-+ switch (st->hcchar_copy.b.multicnt) {
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_MDATA;
-+ break;
-+ }
-+
-+ } else {
-+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+ switch (st->hcchar_copy.b.multicnt) {
-+ case 1:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+ break;
-+ case 2:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA1;
-+ break;
-+ case 3:
-+ st->hctsiz_copy.b.pid = DWC_PID_DATA2;
-+ break;
-+ }
-+ }
-+
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
-+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
-+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
-+ /* Prevent queueing near EOF1. Bad things happen if a periodic
-+ * split transaction is queued very close to EOF.
-+ */
-+ st->fsm = FIQ_HS_ISOC_SLEEPING;
-+ } else {
-+ st->fsm = FIQ_HS_ISOC_TURBO;
-+ st->hcchar_copy.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ }
-+ mb();
-+ st->hcchar_copy.b.chen = 0;
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ return 0;
-+}
-+
-+
-+/**
-+ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * This overrides the dwc_otg driver's normal method of queueing a transaction.
-+ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
-+ * for the nominated host channel.
-+ *
-+ * For periodic transfers, it also peeks at the FIQ state to see if an immediate
-+ * start is possible. If not, then the FIQ is left to start the transfer.
-+ */
-+int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+ int start_immediate = 1, i;
-+ hfnum_data_t hfnum;
-+ dwc_hc_t *hc = qh->channel;
-+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
-+ int hub_addr, port_addr, frame, uframe;
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
-+
-+ if (st->fsm != FIQ_PASSTHROUGH)
-+ return 0;
-+ st->nr_errors = 0;
-+
-+ st->hcchar_copy.d32 = 0;
-+ st->hcchar_copy.b.mps = hc->max_packet;
-+ st->hcchar_copy.b.epdir = hc->ep_is_in;
-+ st->hcchar_copy.b.devaddr = hc->dev_addr;
-+ st->hcchar_copy.b.epnum = hc->ep_num;
-+ st->hcchar_copy.b.eptype = hc->ep_type;
-+ if (hc->ep_type & 0x1) {
-+ if (hc->ep_is_in)
-+ st->hcchar_copy.b.multicnt = 3;
-+ else
-+ /* Docs say set this to 1, but driver sets to 0! */
-+ st->hcchar_copy.b.multicnt = 0;
-+ } else {
-+ st->hcchar_copy.b.multicnt = 1;
-+ st->hcchar_copy.b.oddfrm = 0;
-+ }
-+ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
-+ /* Enable the channel later as a final register write. */
-+
-+ st->hcsplt_copy.d32 = 0;
-+ if(qh->do_split) {
-+ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
-+ st->hcsplt_copy.b.compsplt = 0;
-+ st->hcsplt_copy.b.spltena = 1;
-+ // XACTPOS is for isoc-out only but needs initialising anyway.
-+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
-+ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
-+ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
-+ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
-+ * will update as necessary.
-+ */
-+ if (hc->xfer_len > 188) {
-+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
-+ }
-+ }
-+ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
-+ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
-+ st->hub_addr = hub_addr;
-+ st->port_addr = port_addr;
-+ }
-+
-+ st->hctsiz_copy.d32 = 0;
-+ st->hctsiz_copy.b.dopng = 0;
-+ st->hctsiz_copy.b.pid = hc->data_pid_start;
-+
-+ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+ hc->xfer_len = hc->max_packet;
-+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+ hc->xfer_len = 188;
-+ }
-+ st->hctsiz_copy.b.xfersize = hc->xfer_len;
-+
-+ st->hctsiz_copy.b.pktcnt = 1;
-+
-+ if (hc->ep_type & 0x1) {
-+ /*
-+ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
-+ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
-+ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
-+ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
-+ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
-+ * must not touch internal driver state.
-+ */
-+ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
-+ if (hc->align_buff) {
-+ st->hcdma_copy.d32 = hc->align_buff;
-+ } else {
-+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+ }
-+ }
-+ } else {
-+ if (hc->align_buff) {
-+ st->hcdma_copy.d32 = hc->align_buff;
-+ } else {
-+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+ }
-+ }
-+ /* The FIQ depends upon no other interrupts being enabled except channel halt.
-+ * Fixup channel interrupt mask. */
-+ st->hcintmsk_copy.d32 = 0;
-+ st->hcintmsk_copy.b.chhltd = 1;
-+ st->hcintmsk_copy.b.ahberr = 1;
-+
-+ /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
-+ * as Control puts the transfer into the non-periodic request queue and the
-+ * non-periodic handler in the hub. Makes things lots easier.
-+ */
-+ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
-+ st->hcchar_copy.b.multicnt = 0;
-+ st->hcchar_copy.b.oddfrm = 0;
-+ st->hcchar_copy.b.eptype = UE_CONTROL;
-+ if (hc->align_buff) {
-+ st->hcdma_copy.d32 = hc->align_buff;
-+ } else {
-+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+ }
-+ }
-+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
-+
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+
-+ if (hc->ep_type & 0x1) {
-+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+ frame = (hfnum.b.frnum & ~0x7) >> 3;
-+ uframe = hfnum.b.frnum & 0x7;
-+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
-+ /* Prevent queueing near EOF1. Bad things happen if a periodic
-+ * split transaction is queued very close to EOF.
-+ */
-+ start_immediate = 0;
-+ } else if (uframe == 5) {
-+ start_immediate = 0;
-+ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
-+ start_immediate = 0;
-+ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
-+ start_immediate = 0;
-+ } else {
-+ /* Search through all host channels to determine if a transaction
-+ * is currently in progress */
-+ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
-+ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
-+ continue;
-+ switch (hcd->fiq_state->channel[i].fsm) {
-+ /* TT is reserved for channels that are in the middle of a periodic
-+ * split transaction.
-+ */
-+ case FIQ_PER_SSPLIT_STARTED:
-+ case FIQ_PER_CSPLIT_WAIT:
-+ case FIQ_PER_CSPLIT_NYET1:
-+ case FIQ_PER_CSPLIT_POLL:
-+ case FIQ_PER_ISO_OUT_ACTIVE:
-+ case FIQ_PER_ISO_OUT_LAST:
-+ if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
-+ hcd->fiq_state->channel[i].port_addr == port_addr) {
-+ start_immediate = 0;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ if (!start_immediate)
-+ break;
-+ }
-+ }
-+ }
-+ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
-+ start_immediate = 1;
-+
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
-+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
-+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
-+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
-+ switch (hc->ep_type) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ st->fsm = FIQ_NP_SSPLIT_STARTED;
-+ break;
-+ case UE_ISOCHRONOUS:
-+ if (hc->ep_is_in) {
-+ if (start_immediate) {
-+ st->fsm = FIQ_PER_SSPLIT_STARTED;
-+ } else {
-+ st->fsm = FIQ_PER_SSPLIT_QUEUED;
-+ }
-+ } else {
-+ if (start_immediate) {
-+ /* Single-isoc OUT packets don't require FIQ involvement */
-+ if (st->nrpackets == 1) {
-+ st->fsm = FIQ_PER_ISO_OUT_LAST;
-+ } else {
-+ st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+ }
-+ } else {
-+ st->fsm = FIQ_PER_ISO_OUT_PENDING;
-+ }
-+ }
-+ break;
-+ case UE_INTERRUPT:
-+ if (fiq_fsm_mask & 0x8) {
-+ st->fsm = FIQ_NP_SSPLIT_STARTED;
-+ } else if (start_immediate) {
-+ st->fsm = FIQ_PER_SSPLIT_STARTED;
-+ } else {
-+ st->fsm = FIQ_PER_SSPLIT_QUEUED;
-+ }
-+ default:
-+ break;
-+ }
-+ if (start_immediate) {
-+ /* Set the oddfrm bit as close as possible to actual queueing */
-+ frame = dwc_otg_hcd_get_frame_number(hcd);
-+ st->expected_uframe = (frame + 1) & 0x3FFF;
-+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
-+ st->hcchar_copy.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+ }
-+ mb();
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ return 0;
-+}
-+
-+
-+/**
-+ * This function selects transactions from the HCD transfer schedule and
-+ * assigns them to available host channels. It is called from HCD interrupt
-+ * handler functions.
-+ *
-+ * @param hcd The HCD state structure.
-+ *
-+ * @return The types of new transactions that were assigned to host channels.
-+ */
-+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
-+{
-+ dwc_list_link_t *qh_ptr;
-+ dwc_otg_qh_t *qh;
-+ int num_channels;
-+ dwc_irqflags_t flags;
-+ dwc_spinlock_t *channel_lock = hcd->channel_lock;
-+ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
-+
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_per_scheduled = 0;
-+ last_sel_trans_num_nonper_scheduled = 0;
-+ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
-+#endif /* DEBUG_HOST_CHANNELS */
-+
-+ /* Process entries in the periodic ready list. */
-+ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
-+
-+ while (qh_ptr != &hcd->periodic_sched_ready &&
-+ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+
-+ if (microframe_schedule) {
-+ // Make sure we leave one channel for non periodic transactions.
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ if (hcd->available_host_channels <= 1) {
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ break;
-+ }
-+ hcd->available_host_channels--;
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_per_scheduled++;
-+#endif /* DEBUG_HOST_CHANNELS */
-+ }
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+ assign_and_init_hc(hcd, qh);
-+
-+ /*
-+ * Move the QH from the periodic ready schedule to the
-+ * periodic assigned schedule.
-+ */
-+ qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+ &qh->qh_list_entry);
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ }
-+
-+ /*
-+ * Process entries in the inactive portion of the non-periodic
-+ * schedule. Some free host channels may not be used if they are
-+ * reserved for periodic transfers.
-+ */
-+ qh_ptr = hcd->non_periodic_sched_inactive.next;
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ while (qh_ptr != &hcd->non_periodic_sched_inactive &&
-+ (microframe_schedule || hcd->non_periodic_channels <
-+ num_channels - hcd->periodic_channels) &&
-+ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+ /*
-+ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
-+ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
-+ * cheeky devices that just hold off using NAKs
-+ */
-+ if (nak_holdoff && qh->do_split) {
-+ if (qh->nak_frame != 0xffff) {
-+ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
-+ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
-+ if (dwc_frame_num_le(frame, next_frame)) {
-+ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
-+ hcd->fiq_state->next_sched_frame = next_frame;
-+ }
-+ qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+ continue;
-+ } else {
-+ qh->nak_frame = 0xFFFF;
-+ }
-+ }
-+ }
-+
-+ if (microframe_schedule) {
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ if (hcd->available_host_channels < 1) {
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ break;
-+ }
-+ hcd->available_host_channels--;
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_nonper_scheduled++;
-+#endif /* DEBUG_HOST_CHANNELS */
-+ }
-+
-+ assign_and_init_hc(hcd, qh);
-+
-+ /*
-+ * Move the QH from the non-periodic inactive schedule to the
-+ * non-periodic active schedule.
-+ */
-+ qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
-+ &qh->qh_list_entry);
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+
-+
-+ if (!microframe_schedule)
-+ hcd->non_periodic_channels++;
-+ }
-+ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
-+ * stop the FIQ from kicking us. We could potentially still have elements here if we
-+ * ran out of host channels.
-+ */
-+ if (fiq_enable) {
-+ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
-+ hcd->fiq_state->kick_np_queues = 0;
-+ } else {
-+ /* For each entry remaining in the NP inactive queue,
-+ * if this a NAK'd retransmit then don't set the kick flag.
-+ */
-+ if(nak_holdoff) {
-+ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+ if (qh->nak_frame == 0xFFFF) {
-+ hcd->fiq_state->kick_np_queues = 1;
-+ }
-+ }
-+ }
-+ }
-+ }
-+ if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
-+ ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
-+
-+ if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
-+ ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
-+
-+
-+#ifdef DEBUG_HOST_CHANNELS
-+ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
-+#endif /* DEBUG_HOST_CHANNELS */
-+ return ret_val;
-+}
-+
-+/**
-+ * Attempts to queue a single transaction request for a host channel
-+ * associated with either a periodic or non-periodic transfer. This function
-+ * assumes that there is space available in the appropriate request queue. For
-+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
-+ * is available in the appropriate Tx FIFO.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param hc Host channel descriptor associated with either a periodic or
-+ * non-periodic transfer.
-+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
-+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
-+ * transfers.
-+ *
-+ * @return 1 if a request is queued and more requests may be needed to
-+ * complete the transfer, 0 if no more requests are required for this
-+ * transfer, -1 if there is insufficient space in the Tx FIFO.
-+ */
-+static int queue_transaction(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc, uint16_t fifo_dwords_avail)
-+{
-+ int retval;
-+
-+ if (hcd->core_if->dma_enable) {
-+ if (hcd->core_if->dma_desc_enable) {
-+ if (!hc->xfer_started
-+ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
-+ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
-+ hc->qh->ping_state = 0;
-+ }
-+ } else if (!hc->xfer_started) {
-+ if (fiq_fsm_enable && hc->error_state) {
-+ hcd->fiq_state->channel[hc->hc_num].nr_errors =
-+ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
-+ hcd->fiq_state->channel[hc->hc_num].fsm =
-+ FIQ_PASSTHROUGH_ERRORSTATE;
-+ }
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ hc->qh->ping_state = 0;
-+ }
-+ retval = 0;
-+ } else if (hc->halt_pending) {
-+ /* Don't queue a request if the channel has been halted. */
-+ retval = 0;
-+ } else if (hc->halt_on_queue) {
-+ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
-+ retval = 0;
-+ } else if (hc->do_ping) {
-+ if (!hc->xfer_started) {
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ }
-+ retval = 0;
-+ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+ if ((fifo_dwords_avail * 4) >= hc->max_packet) {
-+ if (!hc->xfer_started) {
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ retval = 1;
-+ } else {
-+ retval =
-+ dwc_otg_hc_continue_transfer(hcd->core_if,
-+ hc);
-+ }
-+ } else {
-+ retval = -1;
-+ }
-+ } else {
-+ if (!hc->xfer_started) {
-+ dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+ retval = 1;
-+ } else {
-+ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
-+ }
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * Processes periodic channels for the next frame and queues transactions for
-+ * these channels to the DWC_otg controller. After queueing transactions, the
-+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
-+ * to queue as Periodic Tx FIFO or request queue space becomes available.
-+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
-+ */
-+static void process_periodic_channels(dwc_otg_hcd_t * hcd)
-+{
-+ hptxsts_data_t tx_status;
-+ dwc_list_link_t *qh_ptr;
-+ dwc_otg_qh_t *qh;
-+ int status = 0;
-+ int no_queue_space = 0;
-+ int no_fifo_space = 0;
-+
-+ dwc_otg_host_global_regs_t *host_regs;
-+ host_regs = hcd->core_if->host_if->host_global_regs;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " P Tx Req Queue Space Avail (before queue): %d\n",
-+ tx_status.b.ptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
-+ tx_status.b.ptxfspcavail);
-+#endif
-+
-+ qh_ptr = hcd->periodic_sched_assigned.next;
-+ while (qh_ptr != &hcd->periodic_sched_assigned) {
-+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+ if (tx_status.b.ptxqspcavail == 0) {
-+ no_queue_space = 1;
-+ break;
-+ }
-+
-+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+
-+ // Do not send a split start transaction any later than frame .6
-+ // Note, we have to schedule a periodic in .5 to make it go in .6
-+ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
-+ {
-+ qh_ptr = qh_ptr->next;
-+ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
-+ continue;
-+ }
-+
-+ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
-+ if (qh->do_split)
-+ fiq_fsm_queue_split_transaction(hcd, qh);
-+ else
-+ fiq_fsm_queue_isoc_transaction(hcd, qh);
-+ } else {
-+
-+ /*
-+ * Set a flag if we're queueing high-bandwidth in slave mode.
-+ * The flag prevents any halts to get into the request queue in
-+ * the middle of multiple high-bandwidth packets getting queued.
-+ */
-+ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
-+ hcd->core_if->queuing_high_bandwidth = 1;
-+ }
-+ status = queue_transaction(hcd, qh->channel,
-+ tx_status.b.ptxfspcavail);
-+ if (status < 0) {
-+ no_fifo_space = 1;
-+ break;
-+ }
-+ }
-+
-+ /*
-+ * In Slave mode, stay on the current transfer until there is
-+ * nothing more to do or the high-bandwidth request count is
-+ * reached. In DMA mode, only need to queue one request. The
-+ * controller automatically handles multiple packets for
-+ * high-bandwidth transfers.
-+ */
-+ if (hcd->core_if->dma_enable || status == 0 ||
-+ qh->channel->requests == qh->channel->multi_count) {
-+ qh_ptr = qh_ptr->next;
-+ /*
-+ * Move the QH from the periodic assigned schedule to
-+ * the periodic queued schedule.
-+ */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
-+ &qh->qh_list_entry);
-+
-+ /* done queuing high bandwidth */
-+ hcd->core_if->queuing_high_bandwidth = 0;
-+ }
-+ }
-+
-+ if (!hcd->core_if->dma_enable) {
-+ dwc_otg_core_global_regs_t *global_regs;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ global_regs = hcd->core_if->core_global_regs;
-+ intr_mask.b.ptxfempty = 1;
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " P Tx Req Queue Space Avail (after queue): %d\n",
-+ tx_status.b.ptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " P Tx FIFO Space Avail (after queue): %d\n",
-+ tx_status.b.ptxfspcavail);
-+#endif
-+ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
-+ no_queue_space || no_fifo_space) {
-+ /*
-+ * May need to queue more transactions as the request
-+ * queue or Tx FIFO empties. Enable the periodic Tx
-+ * FIFO empty interrupt. (Always use the half-empty
-+ * level to ensure that new requests are loaded as
-+ * soon as possible.)
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
-+ intr_mask.d32);
-+ } else {
-+ /*
-+ * Disable the Tx FIFO empty interrupt since there are
-+ * no more transactions that need to be queued right
-+ * now. This function is called from interrupt
-+ * handlers to queue more transactions as transfer
-+ * states change.
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
-+ 0);
-+ }
-+ }
-+}
-+
-+/**
-+ * Processes active non-periodic channels and queues transactions for these
-+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
-+ * FIFO Empty interrupt is enabled if there are more transactions to queue as
-+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
-+ * FIFO Empty interrupt is disabled.
-+ */
-+static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
-+{
-+ gnptxsts_data_t tx_status;
-+ dwc_list_link_t *orig_qh_ptr;
-+ dwc_otg_qh_t *qh;
-+ int status;
-+ int no_queue_space = 0;
-+ int no_fifo_space = 0;
-+ int more_to_do = 0;
-+
-+ dwc_otg_core_global_regs_t *global_regs =
-+ hcd->core_if->core_global_regs;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " NP Tx Req Queue Space Avail (before queue): %d\n",
-+ tx_status.b.nptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
-+ tx_status.b.nptxfspcavail);
-+#endif
-+ /*
-+ * Keep track of the starting point. Skip over the start-of-list
-+ * entry.
-+ */
-+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
-+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
-+ }
-+ orig_qh_ptr = hcd->non_periodic_qh_ptr;
-+
-+ /*
-+ * Process once through the active list or until no more space is
-+ * available in the request queue or the Tx FIFO.
-+ */
-+ do {
-+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
-+ no_queue_space = 1;
-+ break;
-+ }
-+
-+ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
-+ qh_list_entry);
-+
-+ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
-+ fiq_fsm_queue_split_transaction(hcd, qh);
-+ } else {
-+ status = queue_transaction(hcd, qh->channel,
-+ tx_status.b.nptxfspcavail);
-+
-+ if (status > 0) {
-+ more_to_do = 1;
-+ } else if (status < 0) {
-+ no_fifo_space = 1;
-+ break;
-+ }
-+ }
-+ /* Advance to next QH, skipping start-of-list entry. */
-+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
-+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
-+ hcd->non_periodic_qh_ptr =
-+ hcd->non_periodic_qh_ptr->next;
-+ }
-+
-+ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
-+
-+ if (!hcd->core_if->dma_enable) {
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ intr_mask.b.nptxfempty = 1;
-+
-+#ifdef DEBUG
-+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " NP Tx Req Queue Space Avail (after queue): %d\n",
-+ tx_status.b.nptxqspcavail);
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " NP Tx FIFO Space Avail (after queue): %d\n",
-+ tx_status.b.nptxfspcavail);
-+#endif
-+ if (more_to_do || no_queue_space || no_fifo_space) {
-+ /*
-+ * May need to queue more transactions as the request
-+ * queue or Tx FIFO empties. Enable the non-periodic
-+ * Tx FIFO empty interrupt. (Always use the half-empty
-+ * level to ensure that new requests are loaded as
-+ * soon as possible.)
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
-+ intr_mask.d32);
-+ } else {
-+ /*
-+ * Disable the Tx FIFO empty interrupt since there are
-+ * no more transactions that need to be queued right
-+ * now. This function is called from interrupt
-+ * handlers to queue more transactions as transfer
-+ * states change.
-+ */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
-+ 0);
-+ }
-+ }
-+}
-+
-+/**
-+ * This function processes the currently active host channels and queues
-+ * transactions for these channels to the DWC_otg controller. It is called
-+ * from HCD interrupt handler functions.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param tr_type The type(s) of transactions to queue (non-periodic,
-+ * periodic, or both).
-+ */
-+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
-+ dwc_otg_transaction_type_e tr_type)
-+{
-+#ifdef DEBUG_SOF
-+ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
-+#endif
-+ /* Process host channels associated with periodic transfers. */
-+ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
-+ tr_type == DWC_OTG_TRANSACTION_ALL) &&
-+ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
-+
-+ process_periodic_channels(hcd);
-+ }
-+
-+ /* Process host channels associated with non-periodic transfers. */
-+ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
-+ tr_type == DWC_OTG_TRANSACTION_ALL) {
-+ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
-+ process_non_periodic_channels(hcd);
-+ } else {
-+ /*
-+ * Ensure NP Tx FIFO empty interrupt is disabled when
-+ * there are no non-periodic transfers to process.
-+ */
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ gintmsk.b.nptxfempty = 1;
-+
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ } else {
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+ }
-+ }
-+ }
-+}
-+
-+#ifdef DWC_HS_ELECT_TST
-+/*
-+ * Quick and dirty hack to implement the HS Electrical Test
-+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
-+ *
-+ * This code was copied from our userspace app "hset". It sends a
-+ * Get Device Descriptor control sequence in two parts, first the
-+ * Setup packet by itself, followed some time later by the In and
-+ * Ack packets. Rather than trying to figure out how to add this
-+ * functionality to the normal driver code, we just hijack the
-+ * hardware, using these two function to drive the hardware
-+ * directly.
-+ */
-+
-+static dwc_otg_core_global_regs_t *global_regs;
-+static dwc_otg_host_global_regs_t *hc_global_regs;
-+static dwc_otg_hc_regs_t *hc_regs;
-+static uint32_t *data_fifo;
-+
-+static void do_setup(void)
-+{
-+ gintsts_data_t gintsts;
-+ hctsiz_data_t hctsiz;
-+ hcchar_data_t hcchar;
-+ haint_data_t haint;
-+ hcint_data_t hcint;
-+
-+ /* Enable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
-+
-+ /* Enable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /*
-+ * Send Setup packet (Get Device Descriptor)
-+ */
-+
-+ /* Make sure channel is disabled */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chdis = 1;
-+// hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ //sleep(1);
-+ dwc_mdelay(1000);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ }
-+
-+ /* Set HCTSIZ */
-+ hctsiz.d32 = 0;
-+ hctsiz.b.xfersize = 8;
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ /* Set HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.epdir = 0;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.mps = 8;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ /* Fill FIFO with Setup data for Get Device Descriptor */
-+ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
-+ DWC_WRITE_REG32(data_fifo++, 0x01000680);
-+ DWC_WRITE_REG32(data_fifo++, 0x00080000);
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for host channel interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.hcintr == 0);
-+
-+ /* Disable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
-+
-+ /* Disable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+}
-+
-+static void do_in_ack(void)
-+{
-+ gintsts_data_t gintsts;
-+ hctsiz_data_t hctsiz;
-+ hcchar_data_t hcchar;
-+ haint_data_t haint;
-+ hcint_data_t hcint;
-+ host_grxsts_data_t grxsts;
-+
-+ /* Enable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
-+
-+ /* Enable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /*
-+ * Receive Control In packet
-+ */
-+
-+ /* Make sure channel is disabled */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chdis = 1;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ //sleep(1);
-+ dwc_mdelay(1000);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ }
-+
-+ /* Set HCTSIZ */
-+ hctsiz.d32 = 0;
-+ hctsiz.b.xfersize = 8;
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ /* Set HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.epdir = 1;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.mps = 8;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for receive status queue interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.rxstsqlvl == 0);
-+
-+ /* Read RXSTS */
-+ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+ /* Clear RXSTSQLVL in GINTSTS */
-+ gintsts.d32 = 0;
-+ gintsts.b.rxstsqlvl = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ switch (grxsts.b.pktsts) {
-+ case DWC_GRXSTS_PKTSTS_IN:
-+ /* Read the data into the host buffer */
-+ if (grxsts.b.bcnt > 0) {
-+ int i;
-+ int word_count = (grxsts.b.bcnt + 3) / 4;
-+
-+ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
-+
-+ for (i = 0; i < word_count; i++) {
-+ (void)DWC_READ_REG32(data_fifo++);
-+ }
-+ }
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for receive status queue interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.rxstsqlvl == 0);
-+
-+ /* Read RXSTS */
-+ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+ /* Clear RXSTSQLVL in GINTSTS */
-+ gintsts.d32 = 0;
-+ gintsts.b.rxstsqlvl = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ switch (grxsts.b.pktsts) {
-+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for host channel interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.hcintr == 0);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+// usleep(100000);
-+// mdelay(100);
-+ dwc_mdelay(1);
-+
-+ /*
-+ * Send handshake packet
-+ */
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Make sure channel is disabled */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chen) {
-+ hcchar.b.chdis = 1;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+ //sleep(1);
-+ dwc_mdelay(1000);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ }
-+
-+ /* Set HCTSIZ */
-+ hctsiz.d32 = 0;
-+ hctsiz.b.xfersize = 0;
-+ hctsiz.b.pktcnt = 1;
-+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
-+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+ /* Set HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.epdir = 0;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.mps = 8;
-+ hcchar.b.chen = 1;
-+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+ /* Wait for host channel interrupt */
-+ do {
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+ } while (gintsts.b.hcintr == 0);
-+
-+ /* Disable HCINTs */
-+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
-+
-+ /* Disable HAINTs */
-+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
-+
-+ /* Read HAINT */
-+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+ /* Read HCINT */
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+ /* Read HCCHAR */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+ /* Clear HCINT */
-+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+ /* Clear HAINT */
-+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+ /* Clear GINTSTS */
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ /* Read GINTSTS */
-+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+}
-+#endif
-+
-+/** Handles hub class-specific requests. */
-+int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
-+ uint16_t typeReq,
-+ uint16_t wValue,
-+ uint16_t wIndex, uint8_t * buf, uint16_t wLength)
-+{
-+ int retval = 0;
-+
-+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+ usb_hub_descriptor_t *hub_desc;
-+ hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+ uint32_t port_status;
-+
-+ switch (typeReq) {
-+ case UCR_CLEAR_HUB_FEATURE:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearHubFeature 0x%x\n", wValue);
-+ switch (wValue) {
-+ case UHF_C_HUB_LOCAL_POWER:
-+ case UHF_C_HUB_OVER_CURRENT:
-+ /* Nothing required here */
-+ break;
-+ default:
-+ retval = -DWC_E_INVALID;
-+ DWC_ERROR("DWC OTG HCD - "
-+ "ClearHubFeature request %xh unknown\n",
-+ wValue);
-+ }
-+ break;
-+ case UCR_CLEAR_PORT_FEATURE:
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (wValue != UHF_PORT_L1)
-+#endif
-+ if (!wIndex || wIndex > 1)
-+ goto error;
-+
-+ switch (wValue) {
-+ case UHF_PORT_ENABLE:
-+ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtena = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ break;
-+ case UHF_PORT_SUSPEND:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-+
-+ if (core_if->power_down == 2) {
-+ dwc_otg_host_hibernation_restore(core_if, 0, 0);
-+ } else {
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+ dwc_mdelay(5);
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtres = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ hprt0.b.prtsusp = 0;
-+ /* Clear Resume bit */
-+ dwc_mdelay(100);
-+ hprt0.b.prtres = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ }
-+ break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ case UHF_PORT_L1:
-+ {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ glpmcfg_data_t lpmcfg = {.d32 = 0 };
-+
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->
-+ core_global_regs->glpmcfg);
-+ lpmcfg.b.en_utmi_sleep = 0;
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ lpmcfg.b.prt_sleep_sts = 1;
-+ DWC_WRITE_REG32(&core_if->
-+ core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+
-+ /* Clear Enbl_L1Gating bit. */
-+ pcgcctl.b.enbl_sleep_gating = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
-+ 0);
-+
-+ dwc_mdelay(5);
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtres = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+ /* This bit will be cleared in wakeup interrupt handle */
-+ break;
-+ }
-+#endif
-+ case UHF_PORT_POWER:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_POWER\n");
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ break;
-+ case UHF_PORT_INDICATOR:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
-+ /* Port inidicator not supported */
-+ break;
-+ case UHF_C_PORT_CONNECTION:
-+ /* Clears drivers internal connect status change
-+ * flag */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
-+ dwc_otg_hcd->flags.b.port_connect_status_change = 0;
-+ break;
-+ case UHF_C_PORT_RESET:
-+ /* Clears the driver's internal Port Reset Change
-+ * flag */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
-+ dwc_otg_hcd->flags.b.port_reset_change = 0;
-+ break;
-+ case UHF_C_PORT_ENABLE:
-+ /* Clears the driver's internal Port
-+ * Enable/Disable Change flag */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
-+ dwc_otg_hcd->flags.b.port_enable_change = 0;
-+ break;
-+ case UHF_C_PORT_SUSPEND:
-+ /* Clears the driver's internal Port Suspend
-+ * Change flag, which is set when resume signaling on
-+ * the host port is complete */
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
-+ dwc_otg_hcd->flags.b.port_suspend_change = 0;
-+ break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ case UHF_C_PORT_L1:
-+ dwc_otg_hcd->flags.b.port_l1_change = 0;
-+ break;
-+#endif
-+ case UHF_C_PORT_OVER_CURRENT:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
-+ dwc_otg_hcd->flags.b.port_over_current_change = 0;
-+ break;
-+ default:
-+ retval = -DWC_E_INVALID;
-+ DWC_ERROR("DWC OTG HCD - "
-+ "ClearPortFeature request %xh "
-+ "unknown or unsupported\n", wValue);
-+ }
-+ break;
-+ case UCR_GET_HUB_DESCRIPTOR:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "GetHubDescriptor\n");
-+ hub_desc = (usb_hub_descriptor_t *) buf;
-+ hub_desc->bDescLength = 9;
-+ hub_desc->bDescriptorType = 0x29;
-+ hub_desc->bNbrPorts = 1;
-+ USETW(hub_desc->wHubCharacteristics, 0x08);
-+ hub_desc->bPwrOn2PwrGood = 1;
-+ hub_desc->bHubContrCurrent = 0;
-+ hub_desc->DeviceRemovable[0] = 0;
-+ hub_desc->DeviceRemovable[1] = 0xff;
-+ break;
-+ case UCR_GET_HUB_STATUS:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "GetHubStatus\n");
-+ DWC_MEMSET(buf, 0, 4);
-+ break;
-+ case UCR_GET_PORT_STATUS:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
-+ wIndex, dwc_otg_hcd->flags.d32);
-+ if (!wIndex || wIndex > 1)
-+ goto error;
-+
-+ port_status = 0;
-+
-+ if (dwc_otg_hcd->flags.b.port_connect_status_change)
-+ port_status |= (1 << UHF_C_PORT_CONNECTION);
-+
-+ if (dwc_otg_hcd->flags.b.port_enable_change)
-+ port_status |= (1 << UHF_C_PORT_ENABLE);
-+
-+ if (dwc_otg_hcd->flags.b.port_suspend_change)
-+ port_status |= (1 << UHF_C_PORT_SUSPEND);
-+
-+ if (dwc_otg_hcd->flags.b.port_l1_change)
-+ port_status |= (1 << UHF_C_PORT_L1);
-+
-+ if (dwc_otg_hcd->flags.b.port_reset_change) {
-+ port_status |= (1 << UHF_C_PORT_RESET);
-+ }
-+
-+ if (dwc_otg_hcd->flags.b.port_over_current_change) {
-+ DWC_WARN("Overcurrent change detected\n");
-+ port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
-+ }
-+
-+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
-+ /*
-+ * The port is disconnected, which means the core is
-+ * either in device mode or it soon will be. Just
-+ * return 0's for the remainder of the port status
-+ * since the port register can't be read if the core
-+ * is in device mode.
-+ */
-+ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
-+ break;
-+ }
-+
-+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
-+
-+ if (hprt0.b.prtconnsts)
-+ port_status |= (1 << UHF_PORT_CONNECTION);
-+
-+ if (hprt0.b.prtena)
-+ port_status |= (1 << UHF_PORT_ENABLE);
-+
-+ if (hprt0.b.prtsusp)
-+ port_status |= (1 << UHF_PORT_SUSPEND);
-+
-+ if (hprt0.b.prtovrcurract)
-+ port_status |= (1 << UHF_PORT_OVER_CURRENT);
-+
-+ if (hprt0.b.prtrst)
-+ port_status |= (1 << UHF_PORT_RESET);
-+
-+ if (hprt0.b.prtpwr)
-+ port_status |= (1 << UHF_PORT_POWER);
-+
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
-+ port_status |= (1 << UHF_PORT_HIGH_SPEED);
-+ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
-+ port_status |= (1 << UHF_PORT_LOW_SPEED);
-+
-+ if (hprt0.b.prttstctl)
-+ port_status |= (1 << UHF_PORT_TEST);
-+ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
-+ port_status |= (1 << UHF_PORT_L1);
-+ }
-+ /*
-+ For Synopsys HW emulation of Power down wkup_control asserts the
-+ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
-+ We intentionally tell the software that port is in L2Suspend state.
-+ Only for STE.
-+ */
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ port_status |= (1 << UHF_PORT_SUSPEND);
-+ }
-+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
-+
-+ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
-+
-+ break;
-+ case UCR_SET_HUB_FEATURE:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetHubFeature\n");
-+ /* No HUB features supported */
-+ break;
-+ case UCR_SET_PORT_FEATURE:
-+ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
-+ goto error;
-+
-+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
-+ /*
-+ * The port is disconnected, which means the core is
-+ * either in device mode or it soon will be. Just
-+ * return without doing anything since the port
-+ * register can't be written if the core is in device
-+ * mode.
-+ */
-+ break;
-+ }
-+
-+ switch (wValue) {
-+ case UHF_PORT_SUSPEND:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
-+ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
-+ goto error;
-+ }
-+ if (core_if->power_down == 2) {
-+ int timeout = 300;
-+ dwc_irqflags_t flags;
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+#ifdef DWC_DEV_SRPCAP
-+ int32_t otg_cap_param = core_if->core_params->otg_cap;
-+#endif
-+ DWC_PRINTF("Preparing for complete power-off\n");
-+
-+ /* Save registers before hibernation */
-+ dwc_otg_save_global_regs(core_if);
-+ dwc_otg_save_host_regs(core_if);
-+
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 1;
-+ hprt0.b.prtena = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ /* Spin hprt0.b.prtsusp to became 1 */
-+ do {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ if (hprt0.b.prtsusp) {
-+ break;
-+ }
-+ dwc_mdelay(1);
-+ } while (--timeout);
-+ if (!timeout) {
-+ DWC_WARN("Suspend wasn't genereted\n");
-+ }
-+ dwc_udelay(10);
-+
-+ /*
-+ * We need to disable interrupts to prevent servicing of any IRQ
-+ * during going to hibernation
-+ */
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ core_if->lx_state = DWC_OTG_L2;
-+#ifdef DWC_DEV_SRPCAP
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 0;
-+ hprt0.b.prtena = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+#endif
-+ gusbcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->
-+ gusbcfg);
-+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ /* Suspend the Phy Clock */
-+ pcgcctl.d32 = 0;
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ } else {
-+ /* UTMI+ Interface */
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+ dwc_udelay(10);
-+ }
-+#ifdef DWC_DEV_SRPCAP
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.dis_vbus = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+#endif
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ gpwrdn.d32 = 0;
-+#ifdef DWC_DEV_SRPCAP
-+ gpwrdn.b.srp_det_msk = 1;
-+#endif
-+ gpwrdn.b.disconn_det_msk = 1;
-+ gpwrdn.b.lnstchng_msk = 1;
-+ gpwrdn.b.sts_chngint_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Enable Power Down Clamp and all interrupts in GPWRDN */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnclmp = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+ dwc_udelay(10);
-+
-+ /* Switch off VDD */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+#ifdef DWC_DEV_SRPCAP
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
-+ {
-+ core_if->pwron_timer_started = 1;
-+ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
-+ }
-+#endif
-+ /* Save gpwrdn register for further usage if stschng interrupt */
-+ core_if->gr_backup->gpwrdn_local =
-+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+ /* Set flag to indicate that we are in hibernation */
-+ core_if->hibernation_suspend = 1;
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
-+
-+ DWC_PRINTF("Host hibernation completed\n");
-+ // Exit from case statement
-+ break;
-+
-+ }
-+ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
-+ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gotgctl.b.hstsethnpen = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gotgctl, 0, gotgctl.d32);
-+ core_if->op_state = A_SUSPEND;
-+ }
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ {
-+ dwc_irqflags_t flags;
-+ /* Update lx_state */
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ core_if->lx_state = DWC_OTG_L2;
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+ }
-+ /* Suspend the Phy Clock */
-+ {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+ pcgcctl.d32);
-+ dwc_udelay(10);
-+ }
-+
-+ /* For HNP the bus must be suspended for at least 200ms. */
-+ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ dwc_mdelay(200);
-+ }
-+
-+ /** @todo - check how sw can wait for 1 sec to check asesvld??? */
-+#if 0 //vahrama !!!!!!!!!!!!!!!!!!
-+ if (core_if->adp_enable) {
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+ gpwrdn_data_t gpwrdn;
-+
-+ while (gotgctl.b.asesvld == 1) {
-+ gotgctl.d32 =
-+ DWC_READ_REG32(&core_if->
-+ core_global_regs->
-+ gotgctl);
-+ dwc_mdelay(100);
-+ }
-+
-+ /* Enable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ /* Unmask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->
-+ gpwrdn, 0, gpwrdn.d32);
-+
-+ dwc_otg_adp_probe_start(core_if);
-+ }
-+#endif
-+ break;
-+ case UHF_PORT_POWER:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_POWER\n");
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtpwr = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ break;
-+ case UHF_PORT_RESET:
-+ if ((core_if->power_down == 2)
-+ && (core_if->hibernation_suspend == 1)) {
-+ /* If we are going to exit from Hibernated
-+ * state via USB RESET.
-+ */
-+ dwc_otg_host_hibernation_restore(core_if, 0, 1);
-+ } else {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+
-+ DWC_DEBUGPL(DBG_HCD,
-+ "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_RESET\n");
-+ {
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ pcgcctl.b.enbl_sleep_gating = 1;
-+ pcgcctl.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+ DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+ }
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ {
-+ glpmcfg_data_t lpmcfg;
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.prt_sleep_sts) {
-+ lpmcfg.b.en_utmi_sleep = 0;
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ DWC_WRITE_REG32
-+ (&core_if->core_global_regs->glpmcfg,
-+ lpmcfg.d32);
-+ dwc_mdelay(1);
-+ }
-+ }
-+#endif
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ /* Clear suspend bit if resetting from suspended state. */
-+ hprt0.b.prtsusp = 0;
-+ /* When B-Host the Port reset bit is set in
-+ * the Start HCD Callback function, so that
-+ * the reset is started within 1ms of the HNP
-+ * success interrupt. */
-+ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
-+ hprt0.b.prtpwr = 1;
-+ hprt0.b.prtrst = 1;
-+ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+ }
-+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
-+ dwc_mdelay(60);
-+ hprt0.b.prtrst = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
-+ }
-+ break;
-+#ifdef DWC_HS_ELECT_TST
-+ case UHF_PORT_TEST:
-+ {
-+ uint32_t t;
-+ gintmsk_data_t gintmsk;
-+
-+ t = (wIndex >> 8); /* MSB wIndex USB */
-+ DWC_DEBUGPL(DBG_HCD,
-+ "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
-+ t);
-+ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
-+ if (t < 6) {
-+ hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prttstctl = t;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0,
-+ hprt0.d32);
-+ } else {
-+ /* Setup global vars with reg addresses (quick and
-+ * dirty hack, should be cleaned up)
-+ */
-+ global_regs = core_if->core_global_regs;
-+ hc_global_regs =
-+ core_if->host_if->host_global_regs;
-+ hc_regs =
-+ (dwc_otg_hc_regs_t *) ((char *)
-+ global_regs +
-+ 0x500);
-+ data_fifo =
-+ (uint32_t *) ((char *)global_regs +
-+ 0x1000);
-+
-+ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
-+ /* Save current interrupt mask */
-+ gintmsk.d32 =
-+ DWC_READ_REG32
-+ (&global_regs->gintmsk);
-+
-+ /* Disable all interrupts while we muck with
-+ * the hardware directly
-+ */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* 15 second delay per the test spec */
-+ dwc_mdelay(15000);
-+
-+ /* Drive suspend on the root port */
-+ hprt0.d32 =
-+ dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 1;
-+ hprt0.b.prtres = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* 15 second delay per the test spec */
-+ dwc_mdelay(15000);
-+
-+ /* Drive resume on the root port */
-+ hprt0.d32 =
-+ dwc_otg_read_hprt0(core_if);
-+ hprt0.b.prtsusp = 0;
-+ hprt0.b.prtres = 1;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+ dwc_mdelay(100);
-+
-+ /* Clear the resume bit */
-+ hprt0.b.prtres = 0;
-+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+ /* Restore interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
-+ /* Save current interrupt mask */
-+ gintmsk.d32 =
-+ DWC_READ_REG32
-+ (&global_regs->gintmsk);
-+
-+ /* Disable all interrupts while we muck with
-+ * the hardware directly
-+ */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* 15 second delay per the test spec */
-+ dwc_mdelay(15000);
-+
-+ /* Send the Setup packet */
-+ do_setup();
-+
-+ /* 15 second delay so nothing else happens for awhile */
-+ dwc_mdelay(15000);
-+
-+ /* Restore interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
-+ /* Save current interrupt mask */
-+ gintmsk.d32 =
-+ DWC_READ_REG32
-+ (&global_regs->gintmsk);
-+
-+ /* Disable all interrupts while we muck with
-+ * the hardware directly
-+ */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+ /* Send the Setup packet */
-+ do_setup();
-+
-+ /* 15 second delay so nothing else happens for awhile */
-+ dwc_mdelay(15000);
-+
-+ /* Send the In and Ack packets */
-+ do_in_ack();
-+
-+ /* 15 second delay so nothing else happens for awhile */
-+ dwc_mdelay(15000);
-+
-+ /* Restore interrupts */
-+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+ }
-+ }
-+ break;
-+ }
-+#endif /* DWC_HS_ELECT_TST */
-+
-+ case UHF_PORT_INDICATOR:
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
-+ /* Not supported */
-+ break;
-+ default:
-+ retval = -DWC_E_INVALID;
-+ DWC_ERROR("DWC OTG HCD - "
-+ "SetPortFeature request %xh "
-+ "unknown or unsupported\n", wValue);
-+ break;
-+ }
-+ break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ case UCR_SET_AND_TEST_PORT_FEATURE:
-+ if (wValue != UHF_PORT_L1) {
-+ goto error;
-+ }
-+ {
-+ int portnum, hird, devaddr, remwake;
-+ glpmcfg_data_t lpmcfg;
-+ uint32_t time_usecs;
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+
-+ if (!dwc_otg_get_param_lpm_enable(core_if)) {
-+ goto error;
-+ }
-+ if (wValue != UHF_PORT_L1 || wLength != 1) {
-+ goto error;
-+ }
-+ /* Check if the port currently is in SLEEP state */
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.prt_sleep_sts) {
-+ DWC_INFO("Port is already in sleep mode\n");
-+ buf[0] = 0; /* Return success */
-+ break;
-+ }
-+
-+ portnum = wIndex & 0xf;
-+ hird = (wIndex >> 4) & 0xf;
-+ devaddr = (wIndex >> 8) & 0x7f;
-+ remwake = (wIndex >> 15);
-+
-+ if (portnum != 1) {
-+ retval = -DWC_E_INVALID;
-+ DWC_WARN
-+ ("Wrong port number(%d) in SetandTestPortFeature request\n",
-+ portnum);
-+ break;
-+ }
-+
-+ DWC_PRINTF
-+ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
-+ portnum, hird, devaddr, remwake);
-+ /* Disable LPM interrupt */
-+ gintmsk.d32 = 0;
-+ gintmsk.b.lpmtranrcvd = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ gintmsk.d32, 0);
-+
-+ if (dwc_otg_hcd_send_lpm
-+ (dwc_otg_hcd, devaddr, hird, remwake)) {
-+ retval = -DWC_E_INVALID;
-+ break;
-+ }
-+
-+ time_usecs = 10 * (lpmcfg.b.retry_count + 1);
-+ /* We will consider timeout if time_usecs microseconds pass,
-+ * and we don't receive LPM transaction status.
-+ * After receiving non-error responce(ACK/NYET/STALL) from device,
-+ * core will set lpmtranrcvd bit.
-+ */
-+ do {
-+ gintsts.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (gintsts.b.lpmtranrcvd) {
-+ break;
-+ }
-+ dwc_udelay(1);
-+ } while (--time_usecs);
-+ /* lpm_int bit will be cleared in LPM interrupt handler */
-+
-+ /* Now fill status
-+ * 0x00 - Success
-+ * 0x10 - NYET
-+ * 0x11 - Timeout
-+ */
-+ if (!gintsts.b.lpmtranrcvd) {
-+ buf[0] = 0x3; /* Completion code is Timeout */
-+ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
-+ } else {
-+ lpmcfg.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ if (lpmcfg.b.lpm_resp == 0x3) {
-+ /* ACK responce from the device */
-+ buf[0] = 0x00; /* Success */
-+ } else if (lpmcfg.b.lpm_resp == 0x2) {
-+ /* NYET responce from the device */
-+ buf[0] = 0x2;
-+ } else {
-+ /* Otherwise responce with Timeout */
-+ buf[0] = 0x3;
-+ }
-+ }
-+ DWC_PRINTF("Device responce to LPM trans is %x\n",
-+ lpmcfg.b.lpm_resp);
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
-+ gintmsk.d32);
-+
-+ break;
-+ }
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+ default:
-+error:
-+ retval = -DWC_E_INVALID;
-+ DWC_WARN("DWC OTG HCD - "
-+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
-+ typeReq, wIndex, wValue);
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/** Returns index of host channel to perform LPM transaction. */
-+int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
-+{
-+ dwc_otg_core_if_t *core_if = hcd->core_if;
-+ dwc_hc_t *hc;
-+ hcchar_data_t hcchar;
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+ DWC_PRINTF("No free channel to select for LPM transaction\n");
-+ return -1;
-+ }
-+
-+ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
-+
-+ /* Mask host channel interrupts. */
-+ gintmsk.b.hcintr = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+ /* Fill fields that core needs for LPM transaction */
-+ hcchar.b.devaddr = devaddr;
-+ hcchar.b.epnum = 0;
-+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+ hcchar.b.mps = 64;
-+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+ hcchar.b.epdir = 0; /* OUT */
-+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
-+ hcchar.d32);
-+
-+ /* Remove the host channel from the free list. */
-+ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
-+
-+ return hc->hc_num;
-+}
-+
-+/** Release hc after performing LPM transaction */
-+void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
-+{
-+ dwc_hc_t *hc;
-+ glpmcfg_data_t lpmcfg;
-+ uint8_t hc_num;
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
-+ hc_num = lpmcfg.b.lpm_chan_index;
-+
-+ hc = hcd->hc_ptr_array[hc_num];
-+
-+ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
-+ /* Return host channel to free list */
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+}
-+
-+int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
-+ uint8_t bRemoteWake)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+ int channel;
-+
-+ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
-+ if (channel < 0) {
-+ return channel;
-+ }
-+
-+ pcgcctl.b.enbl_sleep_gating = 1;
-+ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+ /* Read LPM config register */
-+ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
-+
-+ /* Program LPM transaction fields */
-+ lpmcfg.b.rem_wkup_en = bRemoteWake;
-+ lpmcfg.b.hird = hird;
-+ lpmcfg.b.hird_thres = 0x1c;
-+ lpmcfg.b.lpm_chan_index = channel;
-+ lpmcfg.b.en_utmi_sleep = 1;
-+ /* Program LPM config register */
-+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+ /* Send LPM transaction */
-+ lpmcfg.b.send_lpm = 1;
-+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+ return 0;
-+}
-+
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+
-+int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
-+{
-+ int retval;
-+
-+ if (port != 1) {
-+ return -DWC_E_INVALID;
-+ }
-+
-+ retval = (hcd->flags.b.port_connect_status_change ||
-+ hcd->flags.b.port_reset_change ||
-+ hcd->flags.b.port_enable_change ||
-+ hcd->flags.b.port_suspend_change ||
-+ hcd->flags.b.port_over_current_change);
-+#ifdef DEBUG
-+ if (retval) {
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
-+ " Root port status changed\n");
-+ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
-+ hcd->flags.b.port_connect_status_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
-+ hcd->flags.b.port_reset_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
-+ hcd->flags.b.port_enable_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
-+ hcd->flags.b.port_suspend_change);
-+ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
-+ hcd->flags.b.port_over_current_change);
-+ }
-+#endif
-+ return retval;
-+}
-+
-+int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ hfnum_data_t hfnum;
-+ hfnum.d32 =
-+ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
-+ hfnum);
-+
-+#ifdef DEBUG_SOF
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
-+ hfnum.b.frnum);
-+#endif
-+ return hfnum.b.frnum;
-+}
-+
-+int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
-+ struct dwc_otg_hcd_function_ops *fops)
-+{
-+ int retval = 0;
-+
-+ hcd->fops = fops;
-+ if (!dwc_otg_is_device_mode(hcd->core_if) &&
-+ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
-+ dwc_otg_hcd_reinit(hcd);
-+ } else {
-+ retval = -DWC_E_NO_DEVICE;
-+ }
-+
-+ return retval;
-+}
-+
-+void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
-+{
-+ return hcd->priv;
-+}
-+
-+void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
-+{
-+ hcd->priv = priv_data;
-+}
-+
-+uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
-+{
-+ return hcd->otg_port;
-+}
-+
-+uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
-+{
-+ uint32_t is_b_host;
-+ if (hcd->core_if->op_state == B_HOST) {
-+ is_b_host = 1;
-+ } else {
-+ is_b_host = 0;
-+ }
-+
-+ return is_b_host;
-+}
-+
-+dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
-+ int iso_desc_count, int atomic_alloc)
-+{
-+ dwc_otg_hcd_urb_t *dwc_otg_urb;
-+ uint32_t size;
-+
-+ size =
-+ sizeof(*dwc_otg_urb) +
-+ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
-+ if (atomic_alloc)
-+ dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
-+ else
-+ dwc_otg_urb = DWC_ALLOC(size);
-+
-+ if (dwc_otg_urb)
-+ dwc_otg_urb->packet_count = iso_desc_count;
-+ else {
-+ DWC_ERROR("**** DWC OTG HCD URB alloc - "
-+ "%salloc of %db failed\n",
-+ atomic_alloc?"atomic ":"", size);
-+ }
-+ return dwc_otg_urb;
-+}
-+
-+void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ uint8_t dev_addr, uint8_t ep_num,
-+ uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
-+{
-+ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
-+ ep_type, ep_dir, mps);
-+#if 0
-+ DWC_PRINTF
-+ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
-+ dev_addr, ep_num, ep_dir, ep_type, mps);
-+#endif
-+}
-+
-+void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ void *urb_handle, void *buf, dwc_dma_t dma,
-+ uint32_t buflen, void *setup_packet,
-+ dwc_dma_t setup_dma, uint32_t flags,
-+ uint16_t interval)
-+{
-+ dwc_otg_urb->priv = urb_handle;
-+ dwc_otg_urb->buf = buf;
-+ dwc_otg_urb->dma = dma;
-+ dwc_otg_urb->length = buflen;
-+ dwc_otg_urb->setup_packet = setup_packet;
-+ dwc_otg_urb->setup_dma = setup_dma;
-+ dwc_otg_urb->flags = flags;
-+ dwc_otg_urb->interval = interval;
-+ dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ return dwc_otg_urb->status;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ return dwc_otg_urb->actual_length;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+ return dwc_otg_urb->error_count;
-+}
-+
-+void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int desc_num, uint32_t offset,
-+ uint32_t length)
-+{
-+ dwc_otg_urb->iso_descs[desc_num].offset = offset;
-+ dwc_otg_urb->iso_descs[desc_num].length = length;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int desc_num)
-+{
-+ return dwc_otg_urb->iso_descs[desc_num].status;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb, int desc_num)
-+{
-+ return dwc_otg_urb->iso_descs[desc_num].actual_length;
-+}
-+
-+int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ int allocated = 0;
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+
-+ if (qh) {
-+ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ allocated = 1;
-+ }
-+ }
-+ return allocated;
-+}
-+
-+int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ int freed = 0;
-+ DWC_ASSERT(qh, "qh is not allocated\n");
-+
-+ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ freed = 1;
-+ }
-+
-+ return freed;
-+}
-+
-+uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+ DWC_ASSERT(qh, "qh is not allocated\n");
-+ return qh->usecs;
-+}
-+
-+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
-+{
-+#ifdef DEBUG
-+ int num_channels;
-+ int i;
-+ gnptxsts_data_t np_tx_status;
-+ hptxsts_data_t p_tx_status;
-+
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF
-+ ("************************************************************\n");
-+ DWC_PRINTF("HCD State:\n");
-+ DWC_PRINTF(" Num channels: %d\n", num_channels);
-+ for (i = 0; i < num_channels; i++) {
-+ dwc_hc_t *hc = hcd->hc_ptr_array[i];
-+ DWC_PRINTF(" Channel %d:\n", i);
-+ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
-+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
-+ DWC_PRINTF(" speed: %d\n", hc->speed);
-+ DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
-+ DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
-+ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
-+ DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
-+ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
-+ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
-+ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
-+ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
-+ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
-+ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
-+ DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
-+ DWC_PRINTF(" do_split: %d\n", hc->do_split);
-+ DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
-+ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
-+ DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
-+ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
-+ DWC_PRINTF(" requests: %d\n", hc->requests);
-+ DWC_PRINTF(" qh: %p\n", hc->qh);
-+ if (hc->xfer_started) {
-+ hfnum_data_t hfnum;
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ hfnum.d32 =
-+ DWC_READ_REG32(&hcd->core_if->
-+ host_if->host_global_regs->hfnum);
-+ hcchar.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hcchar);
-+ hctsiz.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hctsiz);
-+ hcint.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hcint);
-+ hcintmsk.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->
-+ hc_regs[i]->hcintmsk);
-+ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
-+ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
-+ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
-+ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
-+ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
-+ }
-+ if (hc->xfer_started && hc->qh) {
-+ dwc_otg_qtd_t *qtd;
-+ dwc_otg_hcd_urb_t *urb;
-+
-+ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
-+ if (!qtd->in_process)
-+ break;
-+
-+ urb = qtd->urb;
-+ DWC_PRINTF(" URB Info:\n");
-+ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
-+ if (urb) {
-+ DWC_PRINTF(" Dev: %d, EP: %d %s\n",
-+ dwc_otg_hcd_get_dev_addr(&urb->
-+ pipe_info),
-+ dwc_otg_hcd_get_ep_num(&urb->
-+ pipe_info),
-+ dwc_otg_hcd_is_pipe_in(&urb->
-+ pipe_info) ?
-+ "IN" : "OUT");
-+ DWC_PRINTF(" Max packet size: %d\n",
-+ dwc_otg_hcd_get_mps(&urb->
-+ pipe_info));
-+ DWC_PRINTF(" transfer_buffer: %p\n",
-+ urb->buf);
-+ DWC_PRINTF(" transfer_dma: %p\n",
-+ (void *)urb->dma);
-+ DWC_PRINTF(" transfer_buffer_length: %d\n",
-+ urb->length);
-+ DWC_PRINTF(" actual_length: %d\n",
-+ urb->actual_length);
-+ }
-+ }
-+ }
-+ }
-+ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
-+ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
-+ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
-+ np_tx_status.d32 =
-+ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
-+ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
-+ np_tx_status.b.nptxqspcavail);
-+ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
-+ np_tx_status.b.nptxfspcavail);
-+ p_tx_status.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
-+ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
-+ p_tx_status.b.ptxqspcavail);
-+ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
-+ dwc_otg_hcd_dump_frrem(hcd);
-+ dwc_otg_dump_global_registers(hcd->core_if);
-+ dwc_otg_dump_host_registers(hcd->core_if);
-+ DWC_PRINTF
-+ ("************************************************************\n");
-+ DWC_PRINTF("\n");
-+#endif
-+}
-+
-+#ifdef DEBUG
-+void dwc_print_setup_data(uint8_t * setup)
-+{
-+ int i;
-+ if (CHK_DEBUG_LEVEL(DBG_HCD)) {
-+ DWC_PRINTF("Setup Data = MSB ");
-+ for (i = 7; i >= 0; i--)
-+ DWC_PRINTF("%02x ", setup[i]);
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF(" bmRequestType Tranfer = %s\n",
-+ (setup[0] & 0x80) ? "Device-to-Host" :
-+ "Host-to-Device");
-+ DWC_PRINTF(" bmRequestType Type = ");
-+ switch ((setup[0] & 0x60) >> 5) {
-+ case 0:
-+ DWC_PRINTF("Standard\n");
-+ break;
-+ case 1:
-+ DWC_PRINTF("Class\n");
-+ break;
-+ case 2:
-+ DWC_PRINTF("Vendor\n");
-+ break;
-+ case 3:
-+ DWC_PRINTF("Reserved\n");
-+ break;
-+ }
-+ DWC_PRINTF(" bmRequestType Recipient = ");
-+ switch (setup[0] & 0x1f) {
-+ case 0:
-+ DWC_PRINTF("Device\n");
-+ break;
-+ case 1:
-+ DWC_PRINTF("Interface\n");
-+ break;
-+ case 2:
-+ DWC_PRINTF("Endpoint\n");
-+ break;
-+ case 3:
-+ DWC_PRINTF("Other\n");
-+ break;
-+ default:
-+ DWC_PRINTF("Reserved\n");
-+ break;
-+ }
-+ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
-+ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
-+ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
-+ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
-+ }
-+}
-+#endif
-+
-+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
-+{
-+#if 0
-+ DWC_PRINTF("Frame remaining at SOF:\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->frrem_samples, hcd->frrem_accum,
-+ (hcd->frrem_samples > 0) ?
-+ hcd->frrem_accum / hcd->frrem_samples : 0);
-+
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->core_if->hfnum_7_samples,
-+ hcd->core_if->hfnum_7_frrem_accum,
-+ (hcd->core_if->hfnum_7_samples >
-+ 0) ? hcd->core_if->hfnum_7_frrem_accum /
-+ hcd->core_if->hfnum_7_samples : 0);
-+ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->core_if->hfnum_0_samples,
-+ hcd->core_if->hfnum_0_frrem_accum,
-+ (hcd->core_if->hfnum_0_samples >
-+ 0) ? hcd->core_if->hfnum_0_frrem_accum /
-+ hcd->core_if->hfnum_0_samples : 0);
-+ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->core_if->hfnum_other_samples,
-+ hcd->core_if->hfnum_other_frrem_accum,
-+ (hcd->core_if->hfnum_other_samples >
-+ 0) ? hcd->core_if->hfnum_other_frrem_accum /
-+ hcd->core_if->hfnum_other_samples : 0);
-+
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
-+ (hcd->hfnum_7_samples_a > 0) ?
-+ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
-+ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
-+ (hcd->hfnum_0_samples_a > 0) ?
-+ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
-+ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
-+ (hcd->hfnum_other_samples_a > 0) ?
-+ hcd->hfnum_other_frrem_accum_a /
-+ hcd->hfnum_other_samples_a : 0);
-+
-+ DWC_PRINTF("\n");
-+ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
-+ (hcd->hfnum_7_samples_b > 0) ?
-+ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
-+ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
-+ (hcd->hfnum_0_samples_b > 0) ?
-+ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
-+ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
-+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
-+ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
-+ (hcd->hfnum_other_samples_b > 0) ?
-+ hcd->hfnum_other_frrem_accum_b /
-+ hcd->hfnum_other_samples_b : 0);
-+#endif
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,1132 @@
-+/*==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
-+ * $Revision: #10 $
-+ * $Date: 2011/10/20 $
-+ * $Change: 1869464 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/** @file
-+ * This file contains Descriptor DMA support implementation for host mode.
-+ */
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+extern bool microframe_schedule;
-+
-+static inline uint8_t frame_list_idx(uint16_t frame)
-+{
-+ return (frame & (MAX_FRLIST_EN_NUM - 1));
-+}
-+
-+static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
-+{
-+ return (idx + inc) &
-+ (((speed ==
-+ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
-+ MAX_DMA_DESC_NUM_GENERIC) - 1);
-+}
-+
-+static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
-+{
-+ return (idx - inc) &
-+ (((speed ==
-+ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
-+ MAX_DMA_DESC_NUM_GENERIC) - 1);
-+}
-+
-+static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
-+{
-+ return (((qh->ep_type == UE_ISOCHRONOUS)
-+ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
-+ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
-+}
-+static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
-+{
-+ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
-+ ? ((qh->interval + 8 - 1) / 8)
-+ : qh->interval);
-+}
-+
-+static int desc_list_alloc(dwc_otg_qh_t * qh)
-+{
-+ int retval = 0;
-+
-+ qh->desc_list = (dwc_otg_host_dma_desc_t *)
-+ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
-+ &qh->desc_list_dma);
-+
-+ if (!qh->desc_list) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
-+
-+ }
-+
-+ dwc_memset(qh->desc_list, 0x00,
-+ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
-+
-+ qh->n_bytes =
-+ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
-+
-+ if (!qh->n_bytes) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR
-+ ("%s: Failed to allocate array for descriptors' size actual values\n",
-+ __func__);
-+
-+ }
-+ return retval;
-+
-+}
-+
-+static void desc_list_free(dwc_otg_qh_t * qh)
-+{
-+ if (qh->desc_list) {
-+ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
-+ qh->desc_list_dma);
-+ qh->desc_list = NULL;
-+ }
-+
-+ if (qh->n_bytes) {
-+ DWC_FREE(qh->n_bytes);
-+ qh->n_bytes = NULL;
-+ }
-+}
-+
-+static int frame_list_alloc(dwc_otg_hcd_t * hcd)
-+{
-+ int retval = 0;
-+ if (hcd->frame_list)
-+ return 0;
-+
-+ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
-+ &hcd->frame_list_dma);
-+ if (!hcd->frame_list) {
-+ retval = -DWC_E_NO_MEMORY;
-+ DWC_ERROR("%s: Frame List allocation failed\n", __func__);
-+ }
-+
-+ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
-+
-+ return retval;
-+}
-+
-+static void frame_list_free(dwc_otg_hcd_t * hcd)
-+{
-+ if (!hcd->frame_list)
-+ return;
-+
-+ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
-+ hcd->frame_list = NULL;
-+}
-+
-+static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
-+{
-+
-+ hcfg_data_t hcfg;
-+
-+ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
-+
-+ if (hcfg.b.perschedena) {
-+ /* already enabled */
-+ return;
-+ }
-+
-+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
-+ hcd->frame_list_dma);
-+
-+ switch (fr_list_en) {
-+ case 64:
-+ hcfg.b.frlisten = 3;
-+ break;
-+ case 32:
-+ hcfg.b.frlisten = 2;
-+ break;
-+ case 16:
-+ hcfg.b.frlisten = 1;
-+ break;
-+ case 8:
-+ hcfg.b.frlisten = 0;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ hcfg.b.perschedena = 1;
-+
-+ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
-+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+
-+}
-+
-+static void per_sched_disable(dwc_otg_hcd_t * hcd)
-+{
-+ hcfg_data_t hcfg;
-+
-+ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
-+
-+ if (!hcfg.b.perschedena) {
-+ /* already disabled */
-+ return;
-+ }
-+ hcfg.b.perschedena = 0;
-+
-+ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
-+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/*
-+ * Activates/Deactivates FrameList entries for the channel
-+ * based on endpoint servicing period.
-+ */
-+void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
-+{
-+ uint16_t i, j, inc;
-+ dwc_hc_t *hc = NULL;
-+
-+ if (!qh->channel) {
-+ DWC_ERROR("qh->channel = %p", qh->channel);
-+ return;
-+ }
-+
-+ if (!hcd) {
-+ DWC_ERROR("------hcd = %p", hcd);
-+ return;
-+ }
-+
-+ if (!hcd->frame_list) {
-+ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
-+ return;
-+ }
-+
-+ hc = qh->channel;
-+ inc = frame_incr_val(qh);
-+ if (qh->ep_type == UE_ISOCHRONOUS)
-+ i = frame_list_idx(qh->sched_frame);
-+ else
-+ i = 0;
-+
-+ j = i;
-+ do {
-+ if (enable)
-+ hcd->frame_list[j] |= (1 << hc->hc_num);
-+ else
-+ hcd->frame_list[j] &= ~(1 << hc->hc_num);
-+ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
-+ }
-+ while (j != i);
-+ if (!enable)
-+ return;
-+ hc->schinfo = 0;
-+ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ j = 1;
-+ /* TODO - check this */
-+ inc = (8 + qh->interval - 1) / qh->interval;
-+ for (i = 0; i < inc; i++) {
-+ hc->schinfo |= j;
-+ j = j << qh->interval;
-+ }
-+ } else {
-+ hc->schinfo = 0xff;
-+ }
-+}
-+
-+#if 1
-+void dump_frame_list(dwc_otg_hcd_t * hcd)
-+{
-+ int i = 0;
-+ DWC_PRINTF("--FRAME LIST (hex) --\n");
-+ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
-+ DWC_PRINTF("%x\t", hcd->frame_list[i]);
-+ if (!(i % 8) && i)
-+ DWC_PRINTF("\n");
-+ }
-+ DWC_PRINTF("\n----\n");
-+
-+}
-+#endif
-+
-+static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ dwc_irqflags_t flags;
-+ dwc_spinlock_t *channel_lock = hcd->channel_lock;
-+
-+ dwc_hc_t *hc = qh->channel;
-+ if (dwc_qh_is_non_per(qh)) {
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ if (!microframe_schedule)
-+ hcd->non_periodic_channels--;
-+ else
-+ hcd->available_host_channels++;
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ } else
-+ update_frame_list(hcd, qh, 0);
-+
-+ /*
-+ * The condition is added to prevent double cleanup try in case of device
-+ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
-+ */
-+ if (hc->qh) {
-+ dwc_otg_hc_cleanup(hcd->core_if, hc);
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+ hc->qh = NULL;
-+ }
-+
-+ qh->channel = NULL;
-+ qh->ntd = 0;
-+
-+ if (qh->desc_list) {
-+ dwc_memset(qh->desc_list, 0x00,
-+ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
-+ }
-+}
-+
-+/**
-+ * Initializes a QH structure's Descriptor DMA related members.
-+ * Allocates memory for descriptor list.
-+ * On first periodic QH, allocates memory for FrameList
-+ * and enables periodic scheduling.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int retval = 0;
-+
-+ if (qh->do_split) {
-+ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
-+ return -1;
-+ }
-+
-+ retval = desc_list_alloc(qh);
-+
-+ if ((retval == 0)
-+ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
-+ if (!hcd->frame_list) {
-+ retval = frame_list_alloc(hcd);
-+ /* Enable periodic schedule on first periodic QH */
-+ if (retval == 0)
-+ per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
-+ }
-+ }
-+
-+ qh->ntd = 0;
-+
-+ return retval;
-+}
-+
-+/**
-+ * Frees descriptor list memory associated with the QH.
-+ * If QH is periodic and the last, frees FrameList memory
-+ * and disables periodic scheduling.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ */
-+void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ desc_list_free(qh);
-+
-+ /*
-+ * Channel still assigned due to some reasons.
-+ * Seen on Isoc URB dequeue. Channel halted but no subsequent
-+ * ChHalted interrupt to release the channel. Afterwards
-+ * when it comes here from endpoint disable routine
-+ * channel remains assigned.
-+ */
-+ if (qh->channel)
-+ release_channel_ddma(hcd, qh);
-+
-+ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
-+ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
-+
-+ per_sched_disable(hcd);
-+ frame_list_free(hcd);
-+ }
-+}
-+
-+static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
-+{
-+ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
-+ /*
-+ * Descriptor set(8 descriptors) index
-+ * which is 8-aligned.
-+ */
-+ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
-+ } else {
-+ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
-+ }
-+}
-+
-+/*
-+ * Determine starting frame for Isochronous transfer.
-+ * Few frames skipped to prevent race condition with HC.
-+ */
-+static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ uint8_t * skip_frames)
-+{
-+ uint16_t frame = 0;
-+ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
-+
-+ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
-+
-+ /*
-+ * skip_frames is used to limit activated descriptors number
-+ * to avoid the situation when HC services the last activated
-+ * descriptor firstly.
-+ * Example for FS:
-+ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
-+ * corresponding to curr_frame+1, the descriptor corresponding to frame 2
-+ * will be fetched. If the number of descriptors is max=64 (or greather) the
-+ * list will be fully programmed with Active descriptors and it is possible
-+ * case(rare) that the latest descriptor(considering rollback) corresponding
-+ * to frame 2 will be serviced first. HS case is more probable because, in fact,
-+ * up to 11 uframes(16 in the code) may be skipped.
-+ */
-+ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
-+ /*
-+ * Consider uframe counter also, to start xfer asap.
-+ * If half of the frame elapsed skip 2 frames otherwise
-+ * just 1 frame.
-+ * Starting descriptor index must be 8-aligned, so
-+ * if the current frame is near to complete the next one
-+ * is skipped as well.
-+ */
-+
-+ if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
-+ *skip_frames = 2 * 8;
-+ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
-+ } else {
-+ *skip_frames = 1 * 8;
-+ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
-+ }
-+
-+ frame = dwc_full_frame_num(frame);
-+ } else {
-+ /*
-+ * Two frames are skipped for FS - the current and the next.
-+ * But for descriptor programming, 1 frame(descriptor) is enough,
-+ * see example above.
-+ */
-+ *skip_frames = 1;
-+ frame = dwc_frame_num_inc(hcd->frame_number, 2);
-+ }
-+
-+ return frame;
-+}
-+
-+/*
-+ * Calculate initial descriptor index for isochronous transfer
-+ * based on scheduled frame.
-+ */
-+static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ uint16_t frame = 0, fr_idx, fr_idx_tmp;
-+ uint8_t skip_frames = 0;
-+ /*
-+ * With current ISOC processing algorithm the channel is being
-+ * released when no more QTDs in the list(qh->ntd == 0).
-+ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
-+ *
-+ * So qh->channel != NULL branch is not used and just not removed from the
-+ * source file. It is required for another possible approach which is,
-+ * do not disable and release the channel when ISOC session completed,
-+ * just move QH to inactive schedule until new QTD arrives.
-+ * On new QTD, the QH moved back to 'ready' schedule,
-+ * starting frame and therefore starting desc_index are recalculated.
-+ * In this case channel is released only on ep_disable.
-+ */
-+
-+ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
-+ if (qh->channel) {
-+ frame = calc_starting_frame(hcd, qh, &skip_frames);
-+ /*
-+ * Calculate initial descriptor index based on FrameList current bitmap
-+ * and servicing period.
-+ */
-+ fr_idx_tmp = frame_list_idx(frame);
-+ fr_idx =
-+ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
-+ fr_idx_tmp)
-+ % frame_incr_val(qh);
-+ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
-+ } else {
-+ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
-+ fr_idx = frame_list_idx(qh->sched_frame);
-+ }
-+
-+ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
-+
-+ return skip_frames;
-+}
-+
-+#define ISOC_URB_GIVEBACK_ASAP
-+
-+#define MAX_ISOC_XFER_SIZE_FS 1023
-+#define MAX_ISOC_XFER_SIZE_HS 3072
-+#define DESCNUM_THRESHOLD 4
-+
-+static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ uint8_t skip_frames)
-+{
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+ dwc_otg_qtd_t *qtd;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
-+
-+ idx = qh->td_last;
-+ inc = qh->interval;
-+ n_desc = 0;
-+
-+ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
-+ if (skip_frames && !qh->channel)
-+ ntd_max = ntd_max - skip_frames / qh->interval;
-+
-+ max_xfer_size =
-+ (qh->dev_speed ==
-+ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
-+ MAX_ISOC_XFER_SIZE_FS;
-+
-+ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
-+ while ((qh->ntd < ntd_max)
-+ && (qtd->isoc_frame_index_last <
-+ qtd->urb->packet_count)) {
-+
-+ dma_desc = &qh->desc_list[idx];
-+ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
-+
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
-+
-+ if (frame_desc->length > max_xfer_size)
-+ qh->n_bytes[idx] = max_xfer_size;
-+ else
-+ qh->n_bytes[idx] = frame_desc->length;
-+ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
-+ dma_desc->status.b_isoc.a = 1;
-+ dma_desc->status.b_isoc.sts = 0;
-+
-+ dma_desc->buf = qtd->urb->dma + frame_desc->offset;
-+
-+ qh->ntd++;
-+
-+ qtd->isoc_frame_index_last++;
-+
-+#ifdef ISOC_URB_GIVEBACK_ASAP
-+ /*
-+ * Set IOC for each descriptor corresponding to the
-+ * last frame of the URB.
-+ */
-+ if (qtd->isoc_frame_index_last ==
-+ qtd->urb->packet_count)
-+ dma_desc->status.b_isoc.ioc = 1;
-+
-+#endif
-+ idx = desclist_idx_inc(idx, inc, qh->dev_speed);
-+ n_desc++;
-+
-+ }
-+ qtd->in_process = 1;
-+ }
-+
-+ qh->td_last = idx;
-+
-+#ifdef ISOC_URB_GIVEBACK_ASAP
-+ /* Set IOC for the last descriptor if descriptor list is full */
-+ if (qh->ntd == ntd_max) {
-+ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
-+ qh->desc_list[idx].status.b_isoc.ioc = 1;
-+ }
-+#else
-+ /*
-+ * Set IOC bit only for one descriptor.
-+ * Always try to be ahead of HW processing,
-+ * i.e. on IOC generation driver activates next descriptors but
-+ * core continues to process descriptors followed the one with IOC set.
-+ */
-+
-+ if (n_desc > DESCNUM_THRESHOLD) {
-+ /*
-+ * Move IOC "up". Required even if there is only one QTD
-+ * in the list, cause QTDs migth continue to be queued,
-+ * but during the activation it was only one queued.
-+ * Actually more than one QTD might be in the list if this function called
-+ * from XferCompletion - QTDs was queued during HW processing of the previous
-+ * descriptor chunk.
-+ */
-+ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
-+ } else {
-+ /*
-+ * Set the IOC for the latest descriptor
-+ * if either number of descriptor is not greather than threshold
-+ * or no more new descriptors activated.
-+ */
-+ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
-+ }
-+
-+ qh->desc_list[idx].status.b_isoc.ioc = 1;
-+#endif
-+}
-+
-+static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+
-+ dwc_hc_t *hc;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ dwc_otg_qtd_t *qtd;
-+ int num_packets, len, n_desc = 0;
-+
-+ hc = qh->channel;
-+
-+ /*
-+ * Start with hc->xfer_buff initialized in
-+ * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
-+ * this pointer re-assigned to the buffer of the currently processed QTD.
-+ * For non-SG request there is always one QTD active.
-+ */
-+
-+ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
-+
-+ if (n_desc) {
-+ /* SG request - more than 1 QTDs */
-+ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
-+ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
-+ }
-+
-+ qtd->n_desc = 0;
-+
-+ do {
-+ dma_desc = &qh->desc_list[n_desc];
-+ len = hc->xfer_len;
-+
-+ if (len > MAX_DMA_DESC_SIZE)
-+ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
-+
-+ if (hc->ep_is_in) {
-+ if (len > 0) {
-+ num_packets = (len + hc->max_packet - 1) / hc->max_packet;
-+ } else {
-+ /* Need 1 packet for transfer length of 0. */
-+ num_packets = 1;
-+ }
-+ /* Always program an integral # of max packets for IN transfers. */
-+ len = num_packets * hc->max_packet;
-+ }
-+
-+ dma_desc->status.b.n_bytes = len;
-+
-+ qh->n_bytes[n_desc] = len;
-+
-+ if ((qh->ep_type == UE_CONTROL)
-+ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
-+ dma_desc->status.b.sup = 1; /* Setup Packet */
-+
-+ dma_desc->status.b.a = 1; /* Active descriptor */
-+ dma_desc->status.b.sts = 0;
-+
-+ dma_desc->buf =
-+ ((unsigned long)hc->xfer_buff & 0xffffffff);
-+
-+ /*
-+ * Last descriptor(or single) of IN transfer
-+ * with actual size less than MaxPacket.
-+ */
-+ if (len > hc->xfer_len) {
-+ hc->xfer_len = 0;
-+ } else {
-+ hc->xfer_buff += len;
-+ hc->xfer_len -= len;
-+ }
-+
-+ qtd->n_desc++;
-+ n_desc++;
-+ }
-+ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
-+
-+
-+ qtd->in_process = 1;
-+
-+ if (qh->ep_type == UE_CONTROL)
-+ break;
-+
-+ if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
-+ break;
-+ }
-+
-+ if (n_desc) {
-+ /* Request Transfer Complete interrupt for the last descriptor */
-+ qh->desc_list[n_desc - 1].status.b.ioc = 1;
-+ /* End of List indicator */
-+ qh->desc_list[n_desc - 1].status.b.eol = 1;
-+
-+ hc->ntd = n_desc;
-+ }
-+}
-+
-+/**
-+ * For Control and Bulk endpoints initializes descriptor list
-+ * and starts the transfer.
-+ *
-+ * For Interrupt and Isochronous endpoints initializes descriptor list
-+ * then updates FrameList, marking appropriate entries as active.
-+ * In case of Isochronous, the starting descriptor index is calculated based
-+ * on the scheduled frame, but only on the first transfer descriptor within a session.
-+ * Then starts the transfer via enabling the channel.
-+ * For Isochronous endpoint the channel is not halted on XferComplete
-+ * interrupt so remains assigned to the endpoint(QH) until session is done.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ /* Channel is already assigned */
-+ dwc_hc_t *hc = qh->channel;
-+ uint8_t skip_frames = 0;
-+
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ init_non_isoc_dma_desc(hcd, qh);
-+
-+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+ break;
-+ case DWC_OTG_EP_TYPE_INTR:
-+ init_non_isoc_dma_desc(hcd, qh);
-+
-+ update_frame_list(hcd, qh, 1);
-+
-+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+ break;
-+ case DWC_OTG_EP_TYPE_ISOC:
-+
-+ if (!qh->ntd)
-+ skip_frames = recalc_initial_desc_idx(hcd, qh);
-+
-+ init_isoc_dma_desc(hcd, qh, skip_frames);
-+
-+ if (!hc->xfer_started) {
-+
-+ update_frame_list(hcd, qh, 1);
-+
-+ /*
-+ * Always set to max, instead of actual size.
-+ * Otherwise ntd will be changed with
-+ * channel being enabled. Not recommended.
-+ *
-+ */
-+ hc->ntd = max_desc_num(qh);
-+ /* Enable channel only once for ISOC */
-+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+ }
-+
-+ break;
-+ default:
-+
-+ break;
-+ }
-+}
-+
-+static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ uint16_t idx, remain;
-+ uint8_t urb_compl;
-+
-+ qh = hc->qh;
-+ idx = qh->td_first;
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
-+ qtd->in_process = 0;
-+ return;
-+ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
-+ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
-+ /*
-+ * Channel is halted in these error cases.
-+ * Considered as serious issues.
-+ * Complete all URBs marking all frames as failed,
-+ * irrespective whether some of the descriptors(frames) succeeded or no.
-+ * Pass error code to completion routine as well, to
-+ * update urb->status, some of class drivers might use it to stop
-+ * queing transfer requests.
-+ */
-+ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
-+ ? (-DWC_E_IO)
-+ : (-DWC_E_OVERFLOW);
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+ for (idx = 0; idx < qtd->urb->packet_count; idx++) {
-+ frame_desc = &qtd->urb->iso_descs[idx];
-+ frame_desc->status = err;
-+ }
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+ }
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+
-+ if (!qtd->in_process)
-+ break;
-+
-+ urb_compl = 0;
-+
-+ do {
-+
-+ dma_desc = &qh->desc_list[idx];
-+
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
-+
-+ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
-+ /*
-+ * XactError or, unable to complete all the transactions
-+ * in the scheduled micro-frame/frame,
-+ * both indicated by DMA_DESC_STS_PKTERR.
-+ */
-+ qtd->urb->error_count++;
-+ frame_desc->actual_length = qh->n_bytes[idx] - remain;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ } else {
-+ /* Success */
-+
-+ frame_desc->actual_length = qh->n_bytes[idx] - remain;
-+ frame_desc->status = 0;
-+ }
-+
-+ if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ /*
-+ * urb->status is not used for isoc transfers here.
-+ * The individual frame_desc status are used instead.
-+ */
-+
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+
-+ /*
-+ * This check is necessary because urb_dequeue can be called
-+ * from urb complete callback(sound driver example).
-+ * All pending URBs are dequeued there, so no need for
-+ * further processing.
-+ */
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ return;
-+ }
-+
-+ urb_compl = 1;
-+
-+ }
-+
-+ qh->ntd--;
-+
-+ /* Stop if IOC requested descriptor reached */
-+ if (dma_desc->status.b_isoc.ioc) {
-+ idx = desclist_idx_inc(idx, qh->interval, hc->speed);
-+ goto stop_scan;
-+ }
-+
-+ idx = desclist_idx_inc(idx, qh->interval, hc->speed);
-+
-+ if (urb_compl)
-+ break;
-+ }
-+ while (idx != qh->td_first);
-+ }
-+stop_scan:
-+ qh->td_first = idx;
-+}
-+
-+uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_host_dma_desc_t * dma_desc,
-+ dwc_otg_halt_status_e halt_status,
-+ uint32_t n_bytes, uint8_t * xfer_done)
-+{
-+
-+ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+ urb->status = -DWC_E_IO;
-+ return 1;
-+ }
-+ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
-+ switch (halt_status) {
-+ case DWC_OTG_HC_XFER_STALL:
-+ urb->status = -DWC_E_PIPE;
-+ break;
-+ case DWC_OTG_HC_XFER_BABBLE_ERR:
-+ urb->status = -DWC_E_OVERFLOW;
-+ break;
-+ case DWC_OTG_HC_XFER_XACT_ERR:
-+ urb->status = -DWC_E_PROTOCOL;
-+ break;
-+ default:
-+ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
-+ halt_status);
-+ break;
-+ }
-+ return 1;
-+ }
-+
-+ if (dma_desc->status.b.a == 1) {
-+ DWC_DEBUGPL(DBG_HCDV,
-+ "Active descriptor encountered on channel %d\n",
-+ hc->hc_num);
-+ return 0;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
-+ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
-+ urb->actual_length += n_bytes - remain;
-+ if (remain || urb->actual_length == urb->length) {
-+ /*
-+ * For Control Data stage do not set urb->status=0 to prevent
-+ * URB callback. Set it when Status phase done. See below.
-+ */
-+ *xfer_done = 1;
-+ }
-+
-+ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
-+ urb->status = 0;
-+ *xfer_done = 1;
-+ }
-+ /* No handling for SETUP stage */
-+ } else {
-+ /* BULK and INTR */
-+ urb->actual_length += n_bytes - remain;
-+ if (remain || urb->actual_length == urb->length) {
-+ urb->status = 0;
-+ *xfer_done = 1;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ dwc_otg_hcd_urb_t *urb = NULL;
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_host_dma_desc_t *dma_desc;
-+ uint32_t n_bytes, n_desc, i;
-+ uint8_t failed = 0, xfer_done;
-+
-+ n_desc = 0;
-+
-+ qh = hc->qh;
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+ qtd->in_process = 0;
-+ }
-+ return;
-+ }
-+
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
-+
-+ urb = qtd->urb;
-+
-+ n_bytes = 0;
-+ xfer_done = 0;
-+
-+ for (i = 0; i < qtd->n_desc; i++) {
-+ dma_desc = &qh->desc_list[n_desc];
-+
-+ n_bytes = qh->n_bytes[n_desc];
-+
-+ failed =
-+ update_non_isoc_urb_state_ddma(hcd, hc, qtd,
-+ dma_desc,
-+ halt_status, n_bytes,
-+ &xfer_done);
-+
-+ if (failed
-+ || (xfer_done
-+ && (urb->status != -DWC_E_IN_PROGRESS))) {
-+
-+ hcd->fops->complete(hcd, urb->priv, urb,
-+ urb->status);
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+
-+ if (failed)
-+ goto stop_scan;
-+ } else if (qh->ep_type == UE_CONTROL) {
-+ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
-+ if (urb->length > 0) {
-+ qtd->control_phase = DWC_OTG_CONTROL_DATA;
-+ } else {
-+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+ }
-+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
-+ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
-+ if (xfer_done) {
-+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
-+ } else if (i + 1 == qtd->n_desc) {
-+ /*
-+ * Last descriptor for Control data stage which is
-+ * not completed yet.
-+ */
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ }
-+ }
-+ }
-+
-+ n_desc++;
-+ }
-+
-+ }
-+
-+stop_scan:
-+
-+ if (qh->ep_type != UE_CONTROL) {
-+ /*
-+ * Resetting the data toggle for bulk
-+ * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
-+ */
-+ if (halt_status == DWC_OTG_HC_XFER_STALL)
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ else
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ }
-+
-+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+ hcint_data_t hcint;
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ if (hcint.b.nyet) {
-+ /*
-+ * Got a NYET on the last transaction of the transfer. It
-+ * means that the endpoint should be in the PING state at the
-+ * beginning of the next transfer.
-+ */
-+ qh->ping_state = 1;
-+ clear_hc_int(hc_regs, nyet);
-+ }
-+
-+ }
-+
-+}
-+
-+/**
-+ * This function is called from interrupt handlers.
-+ * Scans the descriptor list, updates URB's status and
-+ * calls completion routine for the URB if it's done.
-+ * Releases the channel to be used by other transfers.
-+ * In case of Isochronous endpoint the channel is not halted until
-+ * the end of the session, i.e. QTD list is empty.
-+ * If periodic channel released the FrameList is updated accordingly.
-+ *
-+ * Calls transaction selection routines to activate pending transfers.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param hc Host channel, the transfer is completed on.
-+ * @param hc_regs Host channel registers.
-+ * @param halt_status Reason the channel is being halted,
-+ * or just XferComplete for isochronous transfer
-+ */
-+void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ uint8_t continue_isoc_xfer = 0;
-+ dwc_otg_transaction_type_e tr_type;
-+ dwc_otg_qh_t *qh = hc->qh;
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+
-+ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+
-+ /* Release the channel if halted or session completed */
-+ if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
-+ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+
-+ /* Halt the channel if session completed */
-+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
-+ }
-+
-+ release_channel_ddma(hcd, qh);
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ } else {
-+ /* Keep in assigned schedule to continue transfer */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+ &qh->qh_list_entry);
-+ continue_isoc_xfer = 1;
-+
-+ }
-+ /** @todo Consider the case when period exceeds FrameList size.
-+ * Frame Rollover interrupt should be used.
-+ */
-+ } else {
-+ /* Scan descriptor list to complete the URB(s), then release the channel */
-+ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+
-+ release_channel_ddma(hcd, qh);
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ /* Add back to inactive non-periodic schedule on normal completion */
-+ dwc_otg_hcd_qh_add(hcd, qh);
-+ }
-+
-+ }
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
-+ if (continue_isoc_xfer) {
-+ if (tr_type == DWC_OTG_TRANSACTION_NONE) {
-+ tr_type = DWC_OTG_TRANSACTION_PERIODIC;
-+ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
-+ tr_type = DWC_OTG_TRANSACTION_ALL;
-+ }
-+ }
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ }
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,862 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
-+ * $Revision: #58 $
-+ * $Date: 2011/09/15 $
-+ * $Change: 1846647 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+#ifndef __DWC_HCD_H__
-+#define __DWC_HCD_H__
-+
-+#include "dwc_otg_os_dep.h"
-+#include "usb.h"
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_list.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the structures, constants, and interfaces for
-+ * the Host Contoller Driver (HCD).
-+ *
-+ * The Host Controller Driver (HCD) is responsible for translating requests
-+ * from the USB Driver into the appropriate actions on the DWC_otg controller.
-+ * It isolates the USBD from the specifics of the controller by providing an
-+ * API to the USBD.
-+ */
-+
-+struct dwc_otg_hcd_pipe_info {
-+ uint8_t dev_addr;
-+ uint8_t ep_num;
-+ uint8_t pipe_type;
-+ uint8_t pipe_dir;
-+ uint16_t mps;
-+};
-+
-+struct dwc_otg_hcd_iso_packet_desc {
-+ uint32_t offset;
-+ uint32_t length;
-+ uint32_t actual_length;
-+ uint32_t status;
-+};
-+
-+struct dwc_otg_qtd;
-+
-+struct dwc_otg_hcd_urb {
-+ void *priv;
-+ struct dwc_otg_qtd *qtd;
-+ void *buf;
-+ dwc_dma_t dma;
-+ void *setup_packet;
-+ dwc_dma_t setup_dma;
-+ uint32_t length;
-+ uint32_t actual_length;
-+ uint32_t status;
-+ uint32_t error_count;
-+ uint32_t packet_count;
-+ uint32_t flags;
-+ uint16_t interval;
-+ struct dwc_otg_hcd_pipe_info pipe_info;
-+ struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
-+};
-+
-+static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+ return pipe->ep_num;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return pipe->pipe_type;
-+}
-+
-+static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+ return pipe->mps;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return pipe->dev_addr;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_ISOCHRONOUS);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_INTERRUPT);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_BULK);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (pipe->pipe_type == UE_CONTROL);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+ return (pipe->pipe_dir == UE_DIR_IN);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
-+ *pipe)
-+{
-+ return (!dwc_otg_hcd_is_pipe_in(pipe));
-+}
-+
-+static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
-+ uint8_t devaddr, uint8_t ep_num,
-+ uint8_t pipe_type, uint8_t pipe_dir,
-+ uint16_t mps)
-+{
-+ pipe->dev_addr = devaddr;
-+ pipe->ep_num = ep_num;
-+ pipe->pipe_type = pipe_type;
-+ pipe->pipe_dir = pipe_dir;
-+ pipe->mps = mps;
-+}
-+
-+/**
-+ * Phases for control transfers.
-+ */
-+typedef enum dwc_otg_control_phase {
-+ DWC_OTG_CONTROL_SETUP,
-+ DWC_OTG_CONTROL_DATA,
-+ DWC_OTG_CONTROL_STATUS
-+} dwc_otg_control_phase_e;
-+
-+/** Transaction types. */
-+typedef enum dwc_otg_transaction_type {
-+ DWC_OTG_TRANSACTION_NONE = 0,
-+ DWC_OTG_TRANSACTION_PERIODIC = 1,
-+ DWC_OTG_TRANSACTION_NON_PERIODIC = 2,
-+ DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
-+} dwc_otg_transaction_type_e;
-+
-+struct dwc_otg_qh;
-+
-+/**
-+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
-+ * interrupt, or isochronous transfer. A single QTD is created for each URB
-+ * (of one of these types) submitted to the HCD. The transfer associated with
-+ * a QTD may require one or multiple transactions.
-+ *
-+ * A QTD is linked to a Queue Head, which is entered in either the
-+ * non-periodic or periodic schedule for execution. When a QTD is chosen for
-+ * execution, some or all of its transactions may be executed. After
-+ * execution, the state of the QTD is updated. The QTD may be retired if all
-+ * its transactions are complete or if an error occurred. Otherwise, it
-+ * remains in the schedule so more transactions can be executed later.
-+ */
-+typedef struct dwc_otg_qtd {
-+ /**
-+ * Determines the PID of the next data packet for the data phase of
-+ * control transfers. Ignored for other transfer types.<br>
-+ * One of the following values:
-+ * - DWC_OTG_HC_PID_DATA0
-+ * - DWC_OTG_HC_PID_DATA1
-+ */
-+ uint8_t data_toggle;
-+
-+ /** Current phase for control transfers (Setup, Data, or Status). */
-+ dwc_otg_control_phase_e control_phase;
-+
-+ /** Keep track of the current split type
-+ * for FS/LS endpoints on a HS Hub */
-+ uint8_t complete_split;
-+
-+ /** How many bytes transferred during SSPLIT OUT */
-+ uint32_t ssplit_out_xfer_count;
-+
-+ /**
-+ * Holds the number of bus errors that have occurred for a transaction
-+ * within this transfer.
-+ */
-+ uint8_t error_count;
-+
-+ /**
-+ * Index of the next frame descriptor for an isochronous transfer. A
-+ * frame descriptor describes the buffer position and length of the
-+ * data to be transferred in the next scheduled (micro)frame of an
-+ * isochronous transfer. It also holds status for that transaction.
-+ * The frame index starts at 0.
-+ */
-+ uint16_t isoc_frame_index;
-+
-+ /** Position of the ISOC split on full/low speed */
-+ uint8_t isoc_split_pos;
-+
-+ /** Position of the ISOC split in the buffer for the current frame */
-+ uint16_t isoc_split_offset;
-+
-+ /** URB for this transfer */
-+ struct dwc_otg_hcd_urb *urb;
-+
-+ struct dwc_otg_qh *qh;
-+
-+ /** This list of QTDs */
-+ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
-+
-+ /** Indicates if this QTD is currently processed by HW. */
-+ uint8_t in_process;
-+
-+ /** Number of DMA descriptors for this QTD */
-+ uint8_t n_desc;
-+
-+ /**
-+ * Last activated frame(packet) index.
-+ * Used in Descriptor DMA mode only.
-+ */
-+ uint16_t isoc_frame_index_last;
-+
-+} dwc_otg_qtd_t;
-+
-+DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
-+
-+/**
-+ * A Queue Head (QH) holds the static characteristics of an endpoint and
-+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
-+ * be entered in either the non-periodic or periodic schedule.
-+ */
-+typedef struct dwc_otg_qh {
-+ /**
-+ * Endpoint type.
-+ * One of the following values:
-+ * - UE_CONTROL
-+ * - UE_BULK
-+ * - UE_INTERRUPT
-+ * - UE_ISOCHRONOUS
-+ */
-+ uint8_t ep_type;
-+ uint8_t ep_is_in;
-+
-+ /** wMaxPacketSize Field of Endpoint Descriptor. */
-+ uint16_t maxp;
-+
-+ /**
-+ * Device speed.
-+ * One of the following values:
-+ * - DWC_OTG_EP_SPEED_LOW
-+ * - DWC_OTG_EP_SPEED_FULL
-+ * - DWC_OTG_EP_SPEED_HIGH
-+ */
-+ uint8_t dev_speed;
-+
-+ /**
-+ * Determines the PID of the next data packet for non-control
-+ * transfers. Ignored for control transfers.<br>
-+ * One of the following values:
-+ * - DWC_OTG_HC_PID_DATA0
-+ * - DWC_OTG_HC_PID_DATA1
-+ */
-+ uint8_t data_toggle;
-+
-+ /** Ping state if 1. */
-+ uint8_t ping_state;
-+
-+ /**
-+ * List of QTDs for this QH.
-+ */
-+ struct dwc_otg_qtd_list qtd_list;
-+
-+ /** Host channel currently processing transfers for this QH. */
-+ struct dwc_hc *channel;
-+
-+ /** Full/low speed endpoint on high-speed hub requires split. */
-+ uint8_t do_split;
-+
-+ /** @name Periodic schedule information */
-+ /** @{ */
-+
-+ /** Bandwidth in microseconds per (micro)frame. */
-+ uint16_t usecs;
-+
-+ /** Interval between transfers in (micro)frames. */
-+ uint16_t interval;
-+
-+ /**
-+ * (micro)frame to initialize a periodic transfer. The transfer
-+ * executes in the following (micro)frame.
-+ */
-+ uint16_t sched_frame;
-+
-+ /*
-+ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission
-+ */
-+ uint16_t nak_frame;
-+
-+ /** (micro)frame at which last start split was initialized. */
-+ uint16_t start_split_frame;
-+
-+ /** @} */
-+
-+ /**
-+ * Used instead of original buffer if
-+ * it(physical address) is not dword-aligned.
-+ */
-+ uint8_t *dw_align_buf;
-+ dwc_dma_t dw_align_buf_dma;
-+
-+ /** Entry for QH in either the periodic or non-periodic schedule. */
-+ dwc_list_link_t qh_list_entry;
-+
-+ /** @name Descriptor DMA support */
-+ /** @{ */
-+
-+ /** Descriptor List. */
-+ dwc_otg_host_dma_desc_t *desc_list;
-+
-+ /** Descriptor List physical address. */
-+ dwc_dma_t desc_list_dma;
-+
-+ /**
-+ * Xfer Bytes array.
-+ * Each element corresponds to a descriptor and indicates
-+ * original XferSize size value for the descriptor.
-+ */
-+ uint32_t *n_bytes;
-+
-+ /** Actual number of transfer descriptors in a list. */
-+ uint16_t ntd;
-+
-+ /** First activated isochronous transfer descriptor index. */
-+ uint8_t td_first;
-+ /** Last activated isochronous transfer descriptor index. */
-+ uint8_t td_last;
-+
-+ /** @} */
-+
-+
-+ uint16_t speed;
-+ uint16_t frame_usecs[8];
-+
-+ uint32_t skip_count;
-+} dwc_otg_qh_t;
-+
-+DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
-+
-+typedef struct urb_tq_entry {
-+ struct urb *urb;
-+ DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
-+} urb_tq_entry_t;
-+
-+DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
-+
-+/**
-+ * This structure holds the state of the HCD, including the non-periodic and
-+ * periodic schedules.
-+ */
-+struct dwc_otg_hcd {
-+ /** The DWC otg device pointer */
-+ struct dwc_otg_device *otg_dev;
-+ /** DWC OTG Core Interface Layer */
-+ dwc_otg_core_if_t *core_if;
-+
-+ /** Function HCD driver callbacks */
-+ struct dwc_otg_hcd_function_ops *fops;
-+
-+ /** Internal DWC HCD Flags */
-+ volatile union dwc_otg_hcd_internal_flags {
-+ uint32_t d32;
-+ struct {
-+ unsigned port_connect_status_change:1;
-+ unsigned port_connect_status:1;
-+ unsigned port_reset_change:1;
-+ unsigned port_enable_change:1;
-+ unsigned port_suspend_change:1;
-+ unsigned port_over_current_change:1;
-+ unsigned port_l1_change:1;
-+ unsigned reserved:26;
-+ } b;
-+ } flags;
-+
-+ /**
-+ * Inactive items in the non-periodic schedule. This is a list of
-+ * Queue Heads. Transfers associated with these Queue Heads are not
-+ * currently assigned to a host channel.
-+ */
-+ dwc_list_link_t non_periodic_sched_inactive;
-+
-+ /**
-+ * Active items in the non-periodic schedule. This is a list of
-+ * Queue Heads. Transfers associated with these Queue Heads are
-+ * currently assigned to a host channel.
-+ */
-+ dwc_list_link_t non_periodic_sched_active;
-+
-+ /**
-+ * Pointer to the next Queue Head to process in the active
-+ * non-periodic schedule.
-+ */
-+ dwc_list_link_t *non_periodic_qh_ptr;
-+
-+ /**
-+ * Inactive items in the periodic schedule. This is a list of QHs for
-+ * periodic transfers that are _not_ scheduled for the next frame.
-+ * Each QH in the list has an interval counter that determines when it
-+ * needs to be scheduled for execution. This scheduling mechanism
-+ * allows only a simple calculation for periodic bandwidth used (i.e.
-+ * must assume that all periodic transfers may need to execute in the
-+ * same frame). However, it greatly simplifies scheduling and should
-+ * be sufficient for the vast majority of OTG hosts, which need to
-+ * connect to a small number of peripherals at one time.
-+ *
-+ * Items move from this list to periodic_sched_ready when the QH
-+ * interval counter is 0 at SOF.
-+ */
-+ dwc_list_link_t periodic_sched_inactive;
-+
-+ /**
-+ * List of periodic QHs that are ready for execution in the next
-+ * frame, but have not yet been assigned to host channels.
-+ *
-+ * Items move from this list to periodic_sched_assigned as host
-+ * channels become available during the current frame.
-+ */
-+ dwc_list_link_t periodic_sched_ready;
-+
-+ /**
-+ * List of periodic QHs to be executed in the next frame that are
-+ * assigned to host channels.
-+ *
-+ * Items move from this list to periodic_sched_queued as the
-+ * transactions for the QH are queued to the DWC_otg controller.
-+ */
-+ dwc_list_link_t periodic_sched_assigned;
-+
-+ /**
-+ * List of periodic QHs that have been queued for execution.
-+ *
-+ * Items move from this list to either periodic_sched_inactive or
-+ * periodic_sched_ready when the channel associated with the transfer
-+ * is released. If the interval for the QH is 1, the item moves to
-+ * periodic_sched_ready because it must be rescheduled for the next
-+ * frame. Otherwise, the item moves to periodic_sched_inactive.
-+ */
-+ dwc_list_link_t periodic_sched_queued;
-+
-+ /**
-+ * Total bandwidth claimed so far for periodic transfers. This value
-+ * is in microseconds per (micro)frame. The assumption is that all
-+ * periodic transfers may occur in the same (micro)frame.
-+ */
-+ uint16_t periodic_usecs;
-+
-+ /**
-+ * Total bandwidth claimed so far for all periodic transfers
-+ * in a frame.
-+ * This will include a mixture of HS and FS transfers.
-+ * Units are microseconds per (micro)frame.
-+ * We have a budget per frame and have to schedule
-+ * transactions accordingly.
-+ * Watch out for the fact that things are actually scheduled for the
-+ * "next frame".
-+ */
-+ uint16_t frame_usecs[8];
-+
-+
-+ /**
-+ * Frame number read from the core at SOF. The value ranges from 0 to
-+ * DWC_HFNUM_MAX_FRNUM.
-+ */
-+ uint16_t frame_number;
-+
-+ /**
-+ * Count of periodic QHs, if using several eps. For SOF enable/disable.
-+ */
-+ uint16_t periodic_qh_count;
-+
-+ /**
-+ * Free host channels in the controller. This is a list of
-+ * dwc_hc_t items.
-+ */
-+ struct hc_list free_hc_list;
-+ /**
-+ * Number of host channels assigned to periodic transfers. Currently
-+ * assuming that there is a dedicated host channel for each periodic
-+ * transaction and at least one host channel available for
-+ * non-periodic transactions.
-+ */
-+ int periodic_channels; /* microframe_schedule==0 */
-+
-+ /**
-+ * Number of host channels assigned to non-periodic transfers.
-+ */
-+ int non_periodic_channels; /* microframe_schedule==0 */
-+
-+ /**
-+ * Number of host channels assigned to non-periodic transfers.
-+ */
-+ int available_host_channels;
-+
-+ /**
-+ * Array of pointers to the host channel descriptors. Allows accessing
-+ * a host channel descriptor given the host channel number. This is
-+ * useful in interrupt handlers.
-+ */
-+ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
-+
-+ /**
-+ * Buffer to use for any data received during the status phase of a
-+ * control transfer. Normally no data is transferred during the status
-+ * phase. This buffer is used as a bit bucket.
-+ */
-+ uint8_t *status_buf;
-+
-+ /**
-+ * DMA address for status_buf.
-+ */
-+ dma_addr_t status_buf_dma;
-+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
-+
-+ /**
-+ * Connection timer. An OTG host must display a message if the device
-+ * does not connect. Started when the VBus power is turned on via
-+ * sysfs attribute "buspower".
-+ */
-+ dwc_timer_t *conn_timer;
-+
-+ /* Tasket to do a reset */
-+ dwc_tasklet_t *reset_tasklet;
-+
-+ dwc_tasklet_t *completion_tasklet;
-+ struct urb_list completed_urb_list;
-+
-+ /* */
-+ dwc_spinlock_t *lock;
-+ dwc_spinlock_t *channel_lock;
-+ /**
-+ * Private data that could be used by OS wrapper.
-+ */
-+ void *priv;
-+
-+ uint8_t otg_port;
-+
-+ /** Frame List */
-+ uint32_t *frame_list;
-+
-+ /** Hub - Port assignment */
-+ int hub_port[128];
-+#ifdef FIQ_DEBUG
-+ int hub_port_alloc[2048];
-+#endif
-+
-+ /** Frame List DMA address */
-+ dma_addr_t frame_list_dma;
-+
-+ struct fiq_stack *fiq_stack;
-+ struct fiq_state *fiq_state;
-+
-+ /** Virtual address for split transaction DMA bounce buffers */
-+ struct fiq_dma_blob *fiq_dmab;
-+
-+#ifdef DEBUG
-+ uint32_t frrem_samples;
-+ uint64_t frrem_accum;
-+
-+ uint32_t hfnum_7_samples_a;
-+ uint64_t hfnum_7_frrem_accum_a;
-+ uint32_t hfnum_0_samples_a;
-+ uint64_t hfnum_0_frrem_accum_a;
-+ uint32_t hfnum_other_samples_a;
-+ uint64_t hfnum_other_frrem_accum_a;
-+
-+ uint32_t hfnum_7_samples_b;
-+ uint64_t hfnum_7_frrem_accum_b;
-+ uint32_t hfnum_0_samples_b;
-+ uint64_t hfnum_0_frrem_accum_b;
-+ uint32_t hfnum_other_samples_b;
-+ uint64_t hfnum_other_frrem_accum_b;
-+#endif
-+};
-+
-+/** @name Transaction Execution Functions */
-+/** @{ */
-+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
-+ * hcd);
-+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
-+ dwc_otg_transaction_type_e tr_type);
-+
-+int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
-+void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
-+
-+extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
-+extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh);
-+extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
-+
-+/** @} */
-+
-+/** @name Interrupt Handler Functions */
-+/** @{ */
-+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
-+ uint32_t num);
-+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
-+ dwc_otg_hcd);
-+/** @} */
-+
-+/** @name Schedule Queue Functions */
-+/** @{ */
-+
-+/* Implemented in dwc_otg_hcd_queue.c */
-+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * urb, int atomic_alloc);
-+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ int sched_csplit);
-+
-+/** Remove and free a QH */
-+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
-+ dwc_otg_qh_t * qh)
-+{
-+ dwc_irqflags_t flags;
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ dwc_otg_hcd_qh_free(hcd, qh);
-+}
-+
-+/** Allocates memory for a QH structure.
-+ * @return Returns the memory allocate or NULL on error. */
-+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
-+{
-+ if (atomic_alloc)
-+ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
-+ else
-+ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
-+}
-+
-+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
-+ int atomic_alloc);
-+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
-+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
-+ dwc_otg_qh_t ** qh, int atomic_alloc);
-+
-+/** Allocates memory for a QTD structure.
-+ * @return Returns the memory allocate or NULL on error. */
-+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
-+{
-+ if (atomic_alloc)
-+ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
-+ else
-+ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
-+}
-+
-+/** Frees the memory for a QTD structure. QTD should already be removed from
-+ * list.
-+ * @param qtd QTD to free.*/
-+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
-+{
-+ DWC_FREE(qtd);
-+}
-+
-+/** Removes a QTD from list.
-+ * @param hcd HCD instance.
-+ * @param qtd QTD to remove from list.
-+ * @param qh QTD belongs to.
-+ */
-+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_qh_t * qh)
-+{
-+ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
-+}
-+
-+/** Remove and free a QTD
-+ * Need to disable IRQ and hold hcd lock while calling this function out of
-+ * interrupt servicing chain */
-+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_qh_t * qh)
-+{
-+ dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
-+ dwc_otg_hcd_qtd_free(qtd);
-+}
-+
-+/** @} */
-+
-+/** @name Descriptor DMA Supporting Functions */
-+/** @{ */
-+
-+extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_halt_status_e halt_status);
-+
-+extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+
-+/** @} */
-+
-+/** @name Internal Functions */
-+/** @{ */
-+dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
-+/** @} */
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
-+ uint8_t devaddr);
-+extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
-+#endif
-+
-+/** Gets the QH that contains the list_head */
-+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
-+
-+/** Gets the QTD that contains the list_head */
-+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
-+
-+/** Check if QH is non-periodic */
-+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
-+ (_qh_ptr_->ep_type == UE_CONTROL))
-+
-+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
-+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
-+
-+/** Packet size for any kind of endpoint descriptor */
-+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
-+
-+/**
-+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
-+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
-+ * frame number when the max frame number is reached.
-+ */
-+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
-+{
-+ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
-+ (DWC_HFNUM_MAX_FRNUM >> 1);
-+}
-+
-+/**
-+ * Returns true if _frame1 is greater than _frame2. The comparison is done
-+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
-+ * number when the max frame number is reached.
-+ */
-+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
-+{
-+ return (frame1 != frame2) &&
-+ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
-+ (DWC_HFNUM_MAX_FRNUM >> 1));
-+}
-+
-+/**
-+ * Increments _frame by the amount specified by _inc. The addition is done
-+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
-+ */
-+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
-+{
-+ return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
-+}
-+
-+static inline uint16_t dwc_full_frame_num(uint16_t frame)
-+{
-+ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
-+}
-+
-+static inline uint16_t dwc_micro_frame_num(uint16_t frame)
-+{
-+ return frame & 0x7;
-+}
-+
-+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd);
-+
-+#ifdef DEBUG
-+/**
-+ * Macro to sample the remaining PHY clocks left in the current frame. This
-+ * may be used during debugging to determine the average time it takes to
-+ * execute sections of code. There are two possible sample points, "a" and
-+ * "b", so the _letter argument must be one of these values.
-+ *
-+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
-+ * example, "cat /sys/devices/lm0/hcd_frrem".
-+ */
-+#define dwc_sample_frrem(_hcd, _qh, _letter) \
-+{ \
-+ hfnum_data_t hfnum; \
-+ dwc_otg_qtd_t *qtd; \
-+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
-+ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
-+ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
-+ switch (hfnum.b.frnum & 0x7) { \
-+ case 7: \
-+ _hcd->hfnum_7_samples_##_letter++; \
-+ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
-+ break; \
-+ case 0: \
-+ _hcd->hfnum_0_samples_##_letter++; \
-+ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
-+ break; \
-+ default: \
-+ _hcd->hfnum_other_samples_##_letter++; \
-+ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
-+ break; \
-+ } \
-+ } \
-+}
-+#else
-+#define dwc_sample_frrem(_hcd, _qh, _letter)
-+#endif
-+#endif
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2015-05-31 14:46:12.905660961 -0500
-@@ -0,0 +1,417 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
-+ * $Revision: #12 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+#ifndef __DWC_HCD_IF_H__
-+#define __DWC_HCD_IF_H__
-+
-+#include "dwc_otg_core_if.h"
-+
-+/** @file
-+ * This file defines DWC_OTG HCD Core API.
-+ */
-+
-+struct dwc_otg_hcd;
-+typedef struct dwc_otg_hcd dwc_otg_hcd_t;
-+
-+struct dwc_otg_hcd_urb;
-+typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
-+
-+/** @name HCD Function Driver Callbacks */
-+/** @{ */
-+
-+/** This function is called whenever core switches to host mode. */
-+typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
-+
-+/** This function is called when device has been disconnected */
-+typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
-+
-+/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
-+typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+ void *urb_handle,
-+ uint32_t * hub_addr,
-+ uint32_t * port_addr);
-+/** Via this function HCD core gets device speed */
-+typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+ void *urb_handle);
-+
-+/** This function is called when urb is completed */
-+typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+ void *urb_handle,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int32_t status);
-+
-+/** Via this function HCD core gets b_hnp_enable parameter */
-+typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
-+
-+struct dwc_otg_hcd_function_ops {
-+ dwc_otg_hcd_start_cb_t start;
-+ dwc_otg_hcd_disconnect_cb_t disconnect;
-+ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
-+ dwc_otg_hcd_speed_from_urb_cb_t speed;
-+ dwc_otg_hcd_complete_urb_cb_t complete;
-+ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
-+};
-+/** @} */
-+
-+/** @name HCD Core API */
-+/** @{ */
-+/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
-+extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
-+
-+/** This function should be called to initiate HCD Core.
-+ *
-+ * @param hcd The HCD
-+ * @param core_if The DWC_OTG Core
-+ *
-+ * Returns -DWC_E_NO_MEMORY if no enough memory.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
-+
-+/** Frees HCD
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
-+
-+/** This function should be called on every hardware interrupt.
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ *
-+ * Returns non zero if interrupt is handled
-+ * Return 0 if interrupt is not handled
-+ */
-+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+
-+/** This function is used to handle the fast interrupt
-+ *
-+ */
-+extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
-+
-+/**
-+ * Returns private data set by
-+ * dwc_otg_hcd_set_priv_data function.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Set private data.
-+ *
-+ * @param hcd The HCD
-+ * @param priv_data pointer to be stored in private data
-+ */
-+extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
-+
-+/**
-+ * This function initializes the HCD Core.
-+ *
-+ * @param hcd The HCD
-+ * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
-+ *
-+ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
-+ struct dwc_otg_hcd_function_ops *fops);
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Handles hub class-specific requests.
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param typeReq Request Type
-+ * @param wValue wValue from control request
-+ * @param wIndex wIndex from control request
-+ * @param buf data buffer
-+ * @param wLength data buffer length
-+ *
-+ * Returns -DWC_E_INVALID if invalid argument is passed
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
-+ uint16_t typeReq, uint16_t wValue,
-+ uint16_t wIndex, uint8_t * buf,
-+ uint16_t wLength);
-+
-+/**
-+ * Returns otg port number.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Returns OTG version - either 1.3 or 2.0.
-+ *
-+ * @param core_if The core_if structure pointer
-+ */
-+extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Returns 1 if currently core is acting as B host, and 0 otherwise.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Returns current frame number.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Dumps hcd state.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ * Currently this function is not implemented.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Sends LPM transaction to the local device.
-+ *
-+ * @param hcd The HCD
-+ * @param devaddr Device Address
-+ * @param hird Host initiated resume duration
-+ * @param bRemoteWake Value of bRemoteWake field in LPM transaction
-+ *
-+ * Returns negative value if sending LPM transaction was not succeeded.
-+ * Returns 0 on success.
-+ */
-+extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
-+ uint8_t hird, uint8_t bRemoteWake);
-+
-+/* URB interface */
-+
-+/**
-+ * Allocates memory for dwc_otg_hcd_urb structure.
-+ * Allocated memory should be freed by call of DWC_FREE.
-+ *
-+ * @param hcd The HCD
-+ * @param iso_desc_count Count of ISOC descriptors
-+ * @param atomic_alloc Specefies whether to perform atomic allocation.
-+ */
-+extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
-+ int iso_desc_count,
-+ int atomic_alloc);
-+
-+/**
-+ * Set pipe information in URB.
-+ *
-+ * @param hcd_urb DWC_OTG URB
-+ * @param devaddr Device Address
-+ * @param ep_num Endpoint Number
-+ * @param ep_type Endpoint Type
-+ * @param ep_dir Endpoint Direction
-+ * @param mps Max Packet Size
-+ */
-+extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
-+ uint8_t devaddr, uint8_t ep_num,
-+ uint8_t ep_type, uint8_t ep_dir,
-+ uint16_t mps);
-+
-+/* Transfer flags */
-+#define URB_GIVEBACK_ASAP 0x1
-+#define URB_SEND_ZERO_PACKET 0x2
-+
-+/**
-+ * Sets dwc_otg_hcd_urb parameters.
-+ *
-+ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
-+ * @param urb_handle Unique handle for request, this will be passed back
-+ * to function driver in completion callback.
-+ * @param buf The buffer for the data
-+ * @param dma The DMA buffer for the data
-+ * @param buflen Transfer length
-+ * @param sp Buffer for setup data
-+ * @param sp_dma DMA address of setup data buffer
-+ * @param flags Transfer flags
-+ * @param interval Polling interval for interrupt or isochronous transfers.
-+ */
-+extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
-+ void *urb_handle, void *buf,
-+ dwc_dma_t dma, uint32_t buflen, void *sp,
-+ dwc_dma_t sp_dma, uint32_t flags,
-+ uint16_t interval);
-+
-+/** Gets status from dwc_otg_hcd_urb
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
-+
-+/** Gets actual length from dwc_otg_hcd_urb
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb);
-+
-+/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb);
-+
-+/** Set ISOC descriptor offset and length
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ * @param offset Offset from beginig of buffer.
-+ * @param length Transaction length
-+ */
-+extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ int desc_num, uint32_t offset,
-+ uint32_t length);
-+
-+/** Get status of ISOC descriptor, specified by desc_num
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb, int desc_num);
-+
-+/** Get actual length of ISOC descriptor, specified by desc_num
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
-+ dwc_otg_urb,
-+ int desc_num);
-+
-+/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param ep_handle Out parameter for returning endpoint handle
-+ * @param atomic_alloc Flag to do atomic allocation if needed
-+ *
-+ * Returns -DWC_E_NO_DEVICE if no device is connected.
-+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
-+ * Returns 0 on success.
-+ */
-+extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb,
-+ void **ep_handle, int atomic_alloc);
-+
-+/** De-queue the specified URB
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb);
-+
-+/** Frees resources in the DWC_otg controller related to a given endpoint.
-+ * Any URBs for the endpoint must already be dequeued.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
-+ * @param retry Number of retries if there are queued transfers.
-+ *
-+ * Returns -DWC_E_INVALID if invalid arguments are passed.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
-+ int retry);
-+
-+/* Resets the data toggle in qh structure. This function can be called from
-+ * usb_clear_halt routine.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
-+ *
-+ * Returns -DWC_E_INVALID if invalid arguments are passed.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
-+
-+/** Returns 1 if status of specified port is changed and 0 otherwise.
-+ *
-+ * @param hcd The HCD
-+ * @param port Port number
-+ */
-+extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
-+
-+/** Call this function to check if bandwidth was allocated for specified endpoint.
-+ * Only for ISOC and INTERRUPT endpoints.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
-+ void *ep_handle);
-+
-+/** Call this function to check if bandwidth was freed for specified endpoint.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
-+
-+/** Returns bandwidth allocated for specified endpoint in microseconds.
-+ * Only for ISOC and INTERRUPT endpoints.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
-+ void *ep_handle);
-+
-+/** @} */
-+
-+#endif /* __DWC_HCD_IF_H__ */
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,2713 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
-+ * $Revision: #89 $
-+ * $Date: 2011/10/20 $
-+ * $Change: 1869487 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+#include <linux/jiffies.h>
-+#include <mach/hardware.h>
-+#include <asm/fiq.h>
-+
-+
-+extern bool microframe_schedule;
-+
-+/** @file
-+ * This file contains the implementation of the HCD Interrupt handlers.
-+ */
-+
-+int fiq_done, int_done;
-+
-+#ifdef FIQ_DEBUG
-+char buffer[1000*16];
-+int wptr;
-+void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
-+{
-+ FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
-+ va_list args;
-+ char text[17];
-+ hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
-+
-+ if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
-+ {
-+ local_fiq_disable();
-+ snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
-+ va_start(args, fmt);
-+ vsnprintf(text+8, 9, fmt, args);
-+ va_end(args);
-+
-+ memcpy(buffer + wptr, text, 16);
-+ wptr = (wptr + 16) % sizeof(buffer);
-+ local_fiq_enable();
-+ }
-+}
-+#endif
-+
-+/** This function handles interrupts for the HCD. */
-+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int retval = 0;
-+ static int last_time;
-+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk;
-+ hfnum_data_t hfnum;
-+ haintmsk_data_t haintmsk;
-+
-+#ifdef DEBUG
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+
-+#endif
-+
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+ /* Exit from ISR if core is hibernated */
-+ if (core_if->hibernation_suspend == 1) {
-+ goto exit_handler_routine;
-+ }
-+ DWC_SPINLOCK(dwc_otg_hcd->lock);
-+ /* Check if HOST Mode */
-+ if (dwc_otg_is_host_mode(core_if)) {
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+ /* Pull in from the FIQ's disabled mask */
-+ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
-+ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
-+ }
-+
-+ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
-+ gintsts.b.hcintr = 1;
-+ }
-+
-+ /* Danger will robinson: fake a SOF if necessary */
-+ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
-+ gintsts.b.sofintr = 1;
-+ }
-+ gintsts.d32 &= gintmsk.d32;
-+
-+ if (fiq_enable) {
-+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ }
-+
-+ if (!gintsts.d32) {
-+ goto exit_handler_routine;
-+ }
-+
-+#ifdef DEBUG
-+ // We should be OK doing this because the common interrupts should already have been serviced
-+ /* Don't print debug message in the interrupt handler on SOF */
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ DWC_DEBUGPL(DBG_HCDI, "\n");
-+#endif
-+
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ DWC_DEBUGPL(DBG_HCDI,
-+ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
-+ gintsts.d32, core_if);
-+#endif
-+ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
-+ if (gintsts.b.sofintr) {
-+ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
-+ }
-+
-+ if (gintsts.b.rxstsqlvl) {
-+ retval |=
-+ dwc_otg_hcd_handle_rx_status_q_level_intr
-+ (dwc_otg_hcd);
-+ }
-+ if (gintsts.b.nptxfempty) {
-+ retval |=
-+ dwc_otg_hcd_handle_np_tx_fifo_empty_intr
-+ (dwc_otg_hcd);
-+ }
-+ if (gintsts.b.i2cintr) {
-+ /** @todo Implement i2cintr handler. */
-+ }
-+ if (gintsts.b.portintr) {
-+
-+ gintmsk_data_t gintmsk = { .b.portintr = 1};
-+ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ } else {
-+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+ }
-+ }
-+ if (gintsts.b.hcintr) {
-+ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
-+ }
-+ if (gintsts.b.ptxfempty) {
-+ retval |=
-+ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
-+ (dwc_otg_hcd);
-+ }
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ {
-+ DWC_DEBUGPL(DBG_HCDI,
-+ "DWC OTG HCD Finished Servicing Interrupts\n");
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
-+ DWC_READ_REG32(&global_regs->gintsts));
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+ }
-+#endif
-+
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+ DWC_DEBUGPL(DBG_HCDI, "\n");
-+#endif
-+
-+ }
-+
-+exit_handler_routine:
-+ if (fiq_enable) {
-+ gintmsk_data_t gintmsk_new;
-+ haintmsk_data_t haintmsk_new;
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
-+ if(fiq_fsm_enable)
-+ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
-+ else
-+ haintmsk_new.d32 = 0x0000FFFF;
-+
-+ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
-+ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
-+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
-+ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
-+ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
-+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
-+ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
-+ ;
-+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
-+ dwc_otg_hcd->fiq_state->mphi_int_count = 0;
-+ }
-+ int_done++;
-+ }
-+ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
-+ /* Re-enable interrupts that the FIQ masked (first time round) */
-+ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+ local_fiq_enable();
-+
-+ if ((jiffies / HZ) > last_time) {
-+ //dwc_otg_qh_t *qh;
-+ //dwc_list_link_t *cur;
-+ /* Once a second output the fiq and irq numbers, useful for debug */
-+ last_time = jiffies / HZ;
-+ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
-+ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
-+ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
-+ //printk(KERN_WARNING "Periodic queues:\n");
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK(dwc_otg_hcd->lock);
-+ return retval;
-+}
-+
-+#ifdef DWC_TRACK_MISSED_SOFS
-+
-+#warning Compiling code to track missed SOFs
-+#define FRAME_NUM_ARRAY_SIZE 1000
-+/**
-+ * This function is for debug only.
-+ */
-+static inline void track_missed_sofs(uint16_t curr_frame_number)
-+{
-+ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
-+ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
-+ static int frame_num_idx = 0;
-+ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
-+ static int dumped_frame_num_array = 0;
-+
-+ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
-+ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
-+ curr_frame_number) {
-+ frame_num_array[frame_num_idx] = curr_frame_number;
-+ last_frame_num_array[frame_num_idx++] = last_frame_num;
-+ }
-+ } else if (!dumped_frame_num_array) {
-+ int i;
-+ DWC_PRINTF("Frame Last Frame\n");
-+ DWC_PRINTF("----- ----------\n");
-+ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
-+ DWC_PRINTF("0x%04x 0x%04x\n",
-+ frame_num_array[i], last_frame_num_array[i]);
-+ }
-+ dumped_frame_num_array = 1;
-+ }
-+ last_frame_num = curr_frame_number;
-+}
-+#endif
-+
-+/**
-+ * Handles the start-of-frame interrupt in host mode. Non-periodic
-+ * transactions may be queued to the DWC_otg controller for the current
-+ * (micro)frame. Periodic transactions may be queued to the controller for the
-+ * next (micro)frame.
-+ */
-+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
-+{
-+ hfnum_data_t hfnum;
-+ gintsts_data_t gintsts = { .d32 = 0 };
-+ dwc_list_link_t *qh_entry;
-+ dwc_otg_qh_t *qh;
-+ dwc_otg_transaction_type_e tr_type;
-+ int did_something = 0;
-+ int32_t next_sched_frame = -1;
-+
-+ hfnum.d32 =
-+ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+
-+#ifdef DEBUG_SOF
-+ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
-+#endif
-+ hcd->frame_number = hfnum.b.frnum;
-+
-+#ifdef DEBUG
-+ hcd->frrem_accum += hfnum.b.frrem;
-+ hcd->frrem_samples++;
-+#endif
-+
-+#ifdef DWC_TRACK_MISSED_SOFS
-+ track_missed_sofs(hcd->frame_number);
-+#endif
-+ /* Determine whether any periodic QHs should be executed. */
-+ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
-+ while (qh_entry != &hcd->periodic_sched_inactive) {
-+ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
-+ qh_entry = qh_entry->next;
-+ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
-+
-+ /*
-+ * Move QH to the ready list to be executed next
-+ * (micro)frame.
-+ */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
-+ &qh->qh_list_entry);
-+
-+ did_something = 1;
-+ }
-+ else
-+ {
-+ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
-+ {
-+ next_sched_frame = qh->sched_frame;
-+ }
-+ }
-+ }
-+ if (fiq_enable)
-+ hcd->fiq_state->next_sched_frame = next_sched_frame;
-+
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ did_something = 1;
-+ }
-+
-+ /* Clear interrupt - but do not trample on the FIQ sof */
-+ if (!fiq_fsm_enable) {
-+ gintsts.b.sofintr = 1;
-+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
-+ }
-+ return 1;
-+}
-+
-+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
-+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
-+ * memory if the DWC_otg controller is operating in Slave mode. */
-+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ host_grxsts_data_t grxsts;
-+ dwc_hc_t *hc = NULL;
-+
-+ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
-+
-+ grxsts.d32 =
-+ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
-+
-+ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
-+ if (!hc) {
-+ DWC_ERROR("Unable to get corresponding channel\n");
-+ return 0;
-+ }
-+
-+ /* Packet Status */
-+ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
-+ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
-+ hc->data_pid_start);
-+ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
-+
-+ switch (grxsts.b.pktsts) {
-+ case DWC_GRXSTS_PKTSTS_IN:
-+ /* Read the data into the host buffer. */
-+ if (grxsts.b.bcnt > 0) {
-+ dwc_otg_read_packet(dwc_otg_hcd->core_if,
-+ hc->xfer_buff, grxsts.b.bcnt);
-+
-+ /* Update the HC fields for the next packet received. */
-+ hc->xfer_count += grxsts.b.bcnt;
-+ hc->xfer_buff += grxsts.b.bcnt;
-+ }
-+
-+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
-+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
-+ case DWC_GRXSTS_PKTSTS_CH_HALTED:
-+ /* Handled in interrupt, just ignore data */
-+ break;
-+ default:
-+ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
-+ grxsts.b.pktsts);
-+ break;
-+ }
-+
-+ return 1;
-+}
-+
-+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
-+ * data packets may be written to the FIFO for OUT transfers. More requests
-+ * may be written to the non-periodic request queue for IN transfers. This
-+ * interrupt is enabled only in Slave mode. */
-+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
-+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
-+ DWC_OTG_TRANSACTION_NON_PERIODIC);
-+ return 1;
-+}
-+
-+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
-+ * packets may be written to the FIFO for OUT transfers. More requests may be
-+ * written to the periodic request queue for IN transfers. This interrupt is
-+ * enabled only in Slave mode. */
-+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
-+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
-+ DWC_OTG_TRANSACTION_PERIODIC);
-+ return 1;
-+}
-+
-+/** There are multiple conditions that can cause a port interrupt. This function
-+ * determines which interrupt conditions have occurred and handles them
-+ * appropriately. */
-+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int retval = 0;
-+ hprt0_data_t hprt0;
-+ hprt0_data_t hprt0_modify;
-+
-+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+
-+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
-+ * GINTSTS */
-+
-+ hprt0_modify.b.prtena = 0;
-+ hprt0_modify.b.prtconndet = 0;
-+ hprt0_modify.b.prtenchng = 0;
-+ hprt0_modify.b.prtovrcurrchng = 0;
-+
-+ /* Port Connect Detected
-+ * Set flag and clear if detected */
-+ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
-+ // Dont modify port status if we are in hibernation state
-+ hprt0_modify.b.prtconndet = 1;
-+ hprt0_modify.b.prtenchng = 1;
-+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
-+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+ return retval;
-+ }
-+
-+ if (hprt0.b.prtconndet) {
-+ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
-+ if (dwc_otg_hcd->core_if->adp_enable &&
-+ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
-+ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
-+ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
-+ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
-+ /* TODO - check if this is required, as
-+ * host initialization was already performed
-+ * after initial ADP probing
-+ */
-+ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
-+ dwc_otg_core_init(dwc_otg_hcd->core_if);
-+ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
-+ cil_hcd_start(dwc_otg_hcd->core_if);*/
-+ } else {
-+
-+ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
-+ "Port Connect Detected--\n", hprt0.d32);
-+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
-+ dwc_otg_hcd->flags.b.port_connect_status = 1;
-+ hprt0_modify.b.prtconndet = 1;
-+
-+ /* B-Device has connected, Delete the connection timer. */
-+ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
-+ }
-+ /* The Hub driver asserts a reset when it sees port connect
-+ * status change flag */
-+ retval |= 1;
-+ }
-+
-+ /* Port Enable Changed
-+ * Clear if detected - Set internal flag if disabled */
-+ if (hprt0.b.prtenchng) {
-+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
-+ "Port Enable Changed--\n", hprt0.d32);
-+ hprt0_modify.b.prtenchng = 1;
-+ if (hprt0.b.prtena == 1) {
-+ hfir_data_t hfir;
-+ int do_reset = 0;
-+ dwc_otg_core_params_t *params =
-+ dwc_otg_hcd->core_if->core_params;
-+ dwc_otg_core_global_regs_t *global_regs =
-+ dwc_otg_hcd->core_if->core_global_regs;
-+ dwc_otg_host_if_t *host_if =
-+ dwc_otg_hcd->core_if->host_if;
-+
-+ /* Every time when port enables calculate
-+ * HFIR.FrInterval
-+ */
-+ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
-+ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
-+ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
-+
-+ /* Check if we need to adjust the PHY clock speed for
-+ * low power and adjust it */
-+ if (params->host_support_fs_ls_low_power) {
-+ gusbcfg_data_t usbcfg;
-+
-+ usbcfg.d32 =
-+ DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
-+ || hprt0.b.prtspd ==
-+ DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+ /*
-+ * Low power
-+ */
-+ hcfg_data_t hcfg;
-+ if (usbcfg.b.phylpwrclksel == 0) {
-+ /* Set PHY low power clock select for FS/LS devices */
-+ usbcfg.b.phylpwrclksel = 1;
-+ DWC_WRITE_REG32
-+ (&global_regs->gusbcfg,
-+ usbcfg.d32);
-+ do_reset = 1;
-+ }
-+
-+ hcfg.d32 =
-+ DWC_READ_REG32
-+ (&host_if->host_global_regs->hcfg);
-+
-+ if (hprt0.b.prtspd ==
-+ DWC_HPRT0_PRTSPD_LOW_SPEED
-+ && params->host_ls_low_power_phy_clk
-+ ==
-+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
-+ {
-+ /* 6 MHZ */
-+ DWC_DEBUGPL(DBG_CIL,
-+ "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
-+ if (hcfg.b.fslspclksel !=
-+ DWC_HCFG_6_MHZ) {
-+ hcfg.b.fslspclksel =
-+ DWC_HCFG_6_MHZ;
-+ DWC_WRITE_REG32
-+ (&host_if->host_global_regs->hcfg,
-+ hcfg.d32);
-+ do_reset = 1;
-+ }
-+ } else {
-+ /* 48 MHZ */
-+ DWC_DEBUGPL(DBG_CIL,
-+ "FS_PHY programming HCFG to 48 MHz ()\n");
-+ if (hcfg.b.fslspclksel !=
-+ DWC_HCFG_48_MHZ) {
-+ hcfg.b.fslspclksel =
-+ DWC_HCFG_48_MHZ;
-+ DWC_WRITE_REG32
-+ (&host_if->host_global_regs->hcfg,
-+ hcfg.d32);
-+ do_reset = 1;
-+ }
-+ }
-+ } else {
-+ /*
-+ * Not low power
-+ */
-+ if (usbcfg.b.phylpwrclksel == 1) {
-+ usbcfg.b.phylpwrclksel = 0;
-+ DWC_WRITE_REG32
-+ (&global_regs->gusbcfg,
-+ usbcfg.d32);
-+ do_reset = 1;
-+ }
-+ }
-+
-+ if (do_reset) {
-+ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
-+ }
-+ }
-+
-+ if (!do_reset) {
-+ /* Port has been enabled set the reset change flag */
-+ dwc_otg_hcd->flags.b.port_reset_change = 1;
-+ }
-+ } else {
-+ dwc_otg_hcd->flags.b.port_enable_change = 1;
-+ }
-+ retval |= 1;
-+ }
-+
-+ /** Overcurrent Change Interrupt */
-+ if (hprt0.b.prtovrcurrchng) {
-+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
-+ "Port Overcurrent Changed--\n", hprt0.d32);
-+ dwc_otg_hcd->flags.b.port_over_current_change = 1;
-+ hprt0_modify.b.prtovrcurrchng = 1;
-+ retval |= 1;
-+ }
-+
-+ /* Clear Port Interrupts */
-+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
-+
-+ return retval;
-+}
-+
-+/** This interrupt indicates that one or more host channels has a pending
-+ * interrupt. There are multiple conditions that can cause each host channel
-+ * interrupt. This function determines which conditions have occurred for each
-+ * host channel interrupt and handles them appropriately. */
-+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ int i;
-+ int retval = 0;
-+ haint_data_t haint = { .d32 = 0 } ;
-+
-+ /* Clear appropriate bits in HCINTn to clear the interrupt bit in
-+ * GINTSTS */
-+
-+ if (!fiq_fsm_enable)
-+ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
-+
-+ // Overwrite with saved interrupts from fiq handler
-+ if(fiq_fsm_enable)
-+ {
-+ /* check the mask? */
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
-+ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
-+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ }
-+
-+ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
-+ if (haint.b2.chint & (1 << i)) {
-+ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
-+ }
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * Gets the actual length of a transfer after the transfer halts. _halt_status
-+ * holds the reason for the halt.
-+ *
-+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
-+ * *short_read is set to 1 upon return if less than the requested
-+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
-+ * return. short_read may also be NULL on entry, in which case it remains
-+ * unchanged.
-+ */
-+static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status,
-+ int *short_read)
-+{
-+ hctsiz_data_t hctsiz;
-+ uint32_t length;
-+
-+ if (short_read != NULL) {
-+ *short_read = 0;
-+ }
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+
-+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+ if (hc->ep_is_in) {
-+ length = hc->xfer_len - hctsiz.b.xfersize;
-+ if (short_read != NULL) {
-+ *short_read = (hctsiz.b.xfersize != 0);
-+ }
-+ } else if (hc->qh->do_split) {
-+ //length = split_out_xfersize[hc->hc_num];
-+ length = qtd->ssplit_out_xfer_count;
-+ } else {
-+ length = hc->xfer_len;
-+ }
-+ } else {
-+ /*
-+ * Must use the hctsiz.pktcnt field to determine how much data
-+ * has been transferred. This field reflects the number of
-+ * packets that have been transferred via the USB. This is
-+ * always an integral number of packets if the transfer was
-+ * halted before its normal completion. (Can't use the
-+ * hctsiz.xfersize field because that reflects the number of
-+ * bytes transferred via the AHB, not the USB).
-+ */
-+ length =
-+ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
-+ }
-+
-+ return length;
-+}
-+
-+/**
-+ * Updates the state of the URB after a Transfer Complete interrupt on the
-+ * host channel. Updates the actual_length field of the URB based on the
-+ * number of bytes transferred via the host channel. Sets the URB status
-+ * if the data transfer is finished.
-+ *
-+ * @return 1 if the data transfer specified by the URB is completely finished,
-+ * 0 otherwise.
-+ */
-+static int update_urb_state_xfer_comp(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_hcd_urb_t * urb,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ int xfer_done = 0;
-+ int short_read = 0;
-+
-+ int xfer_length;
-+
-+ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_COMPLETE,
-+ &short_read);
-+
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && xfer_length && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
-+ xfer_length);
-+ }
-+
-+ urb->actual_length += xfer_length;
-+
-+ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
-+ (urb->flags & URB_SEND_ZERO_PACKET)
-+ && (urb->actual_length == urb->length)
-+ && !(urb->length % hc->max_packet)) {
-+ xfer_done = 0;
-+ } else if (short_read || urb->actual_length >= urb->length) {
-+ xfer_done = 1;
-+ urb->status = 0;
-+ }
-+
-+#ifdef DEBUG
-+ {
-+ hctsiz_data_t hctsiz;
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
-+ __func__, (hc->ep_is_in ? "IN" : "OUT"),
-+ hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
-+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
-+ hctsiz.b.xfersize);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
-+ urb->length);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
-+ urb->actual_length);
-+ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
-+ short_read, xfer_done);
-+ }
-+#endif
-+
-+ return xfer_done;
-+}
-+
-+/*
-+ * Save the starting data toggle for the next transfer. The data toggle is
-+ * saved in the QH for non-control transfers and it's saved in the QTD for
-+ * control transfers.
-+ */
-+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
-+{
-+ hctsiz_data_t hctsiz;
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
-+ dwc_otg_qh_t *qh = hc->qh;
-+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ } else {
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA1;
-+ }
-+ } else {
-+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+ qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ } else {
-+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
-+ }
-+ }
-+}
-+
-+/**
-+ * Updates the state of an Isochronous URB when the transfer is stopped for
-+ * any reason. The fields of the current entry in the frame descriptor array
-+ * are set based on the transfer state and the input _halt_status. Completes
-+ * the Isochronous URB if all the URB frames have been completed.
-+ *
-+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
-+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
-+ */
-+static dwc_otg_halt_status_e
-+update_isoc_urb_state(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
-+{
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ dwc_otg_halt_status_e ret_val = halt_status;
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+ frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
-+ switch (halt_status) {
-+ case DWC_OTG_HC_XFER_COMPLETE:
-+ frame_desc->status = 0;
-+ frame_desc->actual_length =
-+ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
-+
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
-+ hc->qh->dw_align_buf, frame_desc->actual_length);
-+ }
-+
-+ break;
-+ case DWC_OTG_HC_XFER_FRAME_OVERRUN:
-+ urb->error_count++;
-+ if (hc->ep_is_in) {
-+ frame_desc->status = -DWC_E_NO_STREAM_RES;
-+ } else {
-+ frame_desc->status = -DWC_E_COMMUNICATION;
-+ }
-+ frame_desc->actual_length = 0;
-+ break;
-+ case DWC_OTG_HC_XFER_BABBLE_ERR:
-+ urb->error_count++;
-+ frame_desc->status = -DWC_E_OVERFLOW;
-+ /* Don't need to update actual_length in this case. */
-+ break;
-+ case DWC_OTG_HC_XFER_XACT_ERR:
-+ urb->error_count++;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ frame_desc->actual_length =
-+ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
-+
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
-+ hc->qh->dw_align_buf, frame_desc->actual_length);
-+ }
-+ /* Skip whole frame */
-+ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
-+ hc->ep_is_in && hcd->core_if->dma_enable) {
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ }
-+
-+ break;
-+ default:
-+ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
-+ break;
-+ }
-+ if (++qtd->isoc_frame_index == urb->packet_count) {
-+ /*
-+ * urb->status is not used for isoc transfers.
-+ * The individual frame_desc statuses are used instead.
-+ */
-+ hcd->fops->complete(hcd, urb->priv, urb, 0);
-+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ } else {
-+ ret_val = DWC_OTG_HC_XFER_COMPLETE;
-+ }
-+ return ret_val;
-+}
-+
-+/**
-+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
-+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
-+ * still linked to the QH, the QH is added to the end of the inactive
-+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
-+ * schedule if no more QTDs are linked to the QH.
-+ */
-+static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
-+{
-+ int continue_split = 0;
-+ dwc_otg_qtd_t *qtd;
-+
-+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
-+
-+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+ if (qtd->complete_split) {
-+ continue_split = 1;
-+ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
-+ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
-+ continue_split = 1;
-+ }
-+
-+ if (free_qtd) {
-+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+ continue_split = 0;
-+ }
-+
-+ qh->channel = NULL;
-+ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
-+}
-+
-+/**
-+ * Releases a host channel for use by other transfers. Attempts to select and
-+ * queue more transactions since at least one host channel is available.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param hc The host channel to release.
-+ * @param qtd The QTD associated with the host channel. This QTD may be freed
-+ * if the transfer is complete or an error has occurred.
-+ * @param halt_status Reason the channel is being released. This status
-+ * determines the actions taken by this function.
-+ */
-+static void release_channel(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ dwc_otg_transaction_type_e tr_type;
-+ int free_qtd;
-+ dwc_irqflags_t flags;
-+ dwc_spinlock_t *channel_lock = hcd->channel_lock;
-+
-+ int hog_port = 0;
-+
-+ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
-+ __func__, hc->hc_num, halt_status, hc->xfer_len);
-+
-+ if(fiq_fsm_enable && hc->do_split) {
-+ if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
-+ if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
-+ hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
-+ hog_port = 0;
-+ }
-+ }
-+ }
-+
-+ switch (halt_status) {
-+ case DWC_OTG_HC_XFER_URB_COMPLETE:
-+ free_qtd = 1;
-+ break;
-+ case DWC_OTG_HC_XFER_AHB_ERR:
-+ case DWC_OTG_HC_XFER_STALL:
-+ case DWC_OTG_HC_XFER_BABBLE_ERR:
-+ free_qtd = 1;
-+ break;
-+ case DWC_OTG_HC_XFER_XACT_ERR:
-+ if (qtd->error_count >= 3) {
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Complete URB with transaction error\n");
-+ free_qtd = 1;
-+ qtd->urb->status = -DWC_E_PROTOCOL;
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_PROTOCOL);
-+ } else {
-+ free_qtd = 0;
-+ }
-+ break;
-+ case DWC_OTG_HC_XFER_URB_DEQUEUE:
-+ /*
-+ * The QTD has already been removed and the QH has been
-+ * deactivated. Don't want to do anything except release the
-+ * host channel and try to queue more transfers.
-+ */
-+ goto cleanup;
-+ case DWC_OTG_HC_XFER_NO_HALT_STATUS:
-+ free_qtd = 0;
-+ break;
-+ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Complete URB with I/O error\n");
-+ free_qtd = 1;
-+ qtd->urb->status = -DWC_E_IO;
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_IO);
-+ break;
-+ default:
-+ free_qtd = 0;
-+ break;
-+ }
-+
-+ deactivate_qh(hcd, hc->qh, free_qtd);
-+
-+cleanup:
-+ /*
-+ * Release the host channel for use by other transfers. The cleanup
-+ * function clears the channel interrupt enables and conditions, so
-+ * there's no need to clear the Channel Halted interrupt separately.
-+ */
-+ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
-+ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
-+ dwc_otg_hc_cleanup(hcd->core_if, hc);
-+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+ if (!microframe_schedule) {
-+ switch (hc->ep_type) {
-+ case DWC_OTG_EP_TYPE_CONTROL:
-+ case DWC_OTG_EP_TYPE_BULK:
-+ hcd->non_periodic_channels--;
-+ break;
-+
-+ default:
-+ /*
-+ * Don't release reservations for periodic channels here.
-+ * That's done when a periodic transfer is descheduled (i.e.
-+ * when the QH is removed from the periodic schedule).
-+ */
-+ break;
-+ }
-+ } else {
-+
-+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
-+ hcd->available_host_channels++;
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
-+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
-+ }
-+
-+ /* Try to queue more transfers now that there's a free channel. */
-+ tr_type = dwc_otg_hcd_select_transactions(hcd);
-+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+ }
-+}
-+
-+/**
-+ * Halts a host channel. If the channel cannot be halted immediately because
-+ * the request queue is full, this function ensures that the FIFO empty
-+ * interrupt for the appropriate queue is enabled so that the halt request can
-+ * be queued when there is space in the request queue.
-+ *
-+ * This function may also be called in DMA mode. In that case, the channel is
-+ * simply released since the core always halts the channel automatically in
-+ * DMA mode.
-+ */
-+static void halt_channel(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
-+{
-+ if (hcd->core_if->dma_enable) {
-+ release_channel(hcd, hc, qtd, halt_status);
-+ return;
-+ }
-+
-+ /* Slave mode processing... */
-+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
-+
-+ if (hc->halt_on_queue) {
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+ dwc_otg_core_global_regs_t *global_regs;
-+ global_regs = hcd->core_if->core_global_regs;
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+ /*
-+ * Make sure the Non-periodic Tx FIFO empty interrupt
-+ * is enabled so that the non-periodic schedule will
-+ * be processed.
-+ */
-+ gintmsk.b.nptxfempty = 1;
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ } else {
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+ }
-+ } else {
-+ /*
-+ * Move the QH from the periodic queued schedule to
-+ * the periodic assigned schedule. This allows the
-+ * halt to be queued when the periodic schedule is
-+ * processed.
-+ */
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+ &hc->qh->qh_list_entry);
-+
-+ /*
-+ * Make sure the Periodic Tx FIFO Empty interrupt is
-+ * enabled so that the periodic schedule will be
-+ * processed.
-+ */
-+ gintmsk.b.ptxfempty = 1;
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ } else {
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * Performs common cleanup for non-periodic transfers after a Transfer
-+ * Complete interrupt. This function should be called after any endpoint type
-+ * specific handling is finished to release the host channel.
-+ */
-+static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ hcint_data_t hcint;
-+
-+ qtd->error_count = 0;
-+
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ if (hcint.b.nyet) {
-+ /*
-+ * Got a NYET on the last transaction of the transfer. This
-+ * means that the endpoint should be in the PING state at the
-+ * beginning of the next transfer.
-+ */
-+ hc->qh->ping_state = 1;
-+ clear_hc_int(hc_regs, nyet);
-+ }
-+
-+ /*
-+ * Always halt and release the host channel to make it available for
-+ * more transfers. There may still be more phases for a control
-+ * transfer or more data packets for a bulk transfer at this point,
-+ * but the host channel is still halted. A channel will be reassigned
-+ * to the transfer when the non-periodic schedule is processed after
-+ * the channel is released. This allows transactions to be queued
-+ * properly via dwc_otg_hcd_queue_transactions, which also enables the
-+ * Tx FIFO Empty interrupt if necessary.
-+ */
-+ if (hc->ep_is_in) {
-+ /*
-+ * IN transfers in Slave mode require an explicit disable to
-+ * halt the channel. (In DMA mode, this call simply releases
-+ * the channel.)
-+ */
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ } else {
-+ /*
-+ * The channel is automatically disabled by the core for OUT
-+ * transfers in Slave mode.
-+ */
-+ release_channel(hcd, hc, qtd, halt_status);
-+ }
-+}
-+
-+/**
-+ * Performs common cleanup for periodic transfers after a Transfer Complete
-+ * interrupt. This function should be called after any endpoint type specific
-+ * handling is finished to release the host channel.
-+ */
-+static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ hctsiz_data_t hctsiz;
-+ qtd->error_count = 0;
-+
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
-+ /* Core halts channel in these cases. */
-+ release_channel(hcd, hc, qtd, halt_status);
-+ } else {
-+ /* Flush any outstanding requests from the Tx queue. */
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+}
-+
-+static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ uint32_t len;
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+
-+ len = get_actual_xfer_length(hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_COMPLETE, NULL);
-+
-+ if (!len) {
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ return 0;
-+ }
-+ frame_desc->actual_length += len;
-+
-+ if (hc->align_buff && len)
-+ dwc_memcpy(qtd->urb->buf + frame_desc->offset +
-+ qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
-+ qtd->isoc_split_offset += len;
-+
-+ if (frame_desc->length == frame_desc->actual_length) {
-+ frame_desc->status = 0;
-+ qtd->isoc_frame_index++;
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ }
-+
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+
-+ return 1; /* Indicates that channel released */
-+}
-+
-+/**
-+ * Handles a host channel Transfer Complete interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ int urb_xfer_done;
-+ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Transfer Complete--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+ if (pipe_type == UE_ISOCHRONOUS) {
-+ /* Do not disable the interrupt, just clear it */
-+ clear_hc_int(hc_regs, xfercomp);
-+ return 1;
-+ }
-+ goto handle_xfercomp_done;
-+ }
-+
-+ /*
-+ * Handle xfer complete on CSPLIT.
-+ */
-+
-+ if (hc->qh->do_split) {
-+ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
-+ && hcd->core_if->dma_enable) {
-+ if (qtd->complete_split
-+ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
-+ qtd))
-+ goto handle_xfercomp_done;
-+ } else {
-+ qtd->complete_split = 0;
-+ }
-+ }
-+
-+ /* Update the QTD and URB states. */
-+ switch (pipe_type) {
-+ case UE_CONTROL:
-+ switch (qtd->control_phase) {
-+ case DWC_OTG_CONTROL_SETUP:
-+ if (urb->length > 0) {
-+ qtd->control_phase = DWC_OTG_CONTROL_DATA;
-+ } else {
-+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+ }
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Control setup transaction done\n");
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ break;
-+ case DWC_OTG_CONTROL_DATA:{
-+ urb_xfer_done =
-+ update_urb_state_xfer_comp(hc, hc_regs, urb,
-+ qtd);
-+ if (urb_xfer_done) {
-+ qtd->control_phase =
-+ DWC_OTG_CONTROL_STATUS;
-+ DWC_DEBUGPL(DBG_HCDV,
-+ " Control data transfer done\n");
-+ } else {
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ }
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ break;
-+ }
-+ case DWC_OTG_CONTROL_STATUS:
-+ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
-+ if (urb->status == -DWC_E_IN_PROGRESS) {
-+ urb->status = 0;
-+ }
-+ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ break;
-+ }
-+
-+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ case UE_BULK:
-+ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
-+ urb_xfer_done =
-+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
-+ if (urb_xfer_done) {
-+ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ } else {
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ }
-+
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ case UE_INTERRUPT:
-+ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
-+ urb_xfer_done =
-+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
-+
-+ /*
-+ * Interrupt URB is done on the first transfer complete
-+ * interrupt.
-+ */
-+ if (urb_xfer_done) {
-+ hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+ } else {
-+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+ }
-+
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
-+ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
-+ halt_status =
-+ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+ break;
-+ }
-+
-+handle_xfercomp_done:
-+ disable_hc_int(hc_regs, xfercompl);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel STALL interrupt. This handler may be called in
-+ * either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+
-+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
-+ "STALL Received--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
-+ goto handle_stall_done;
-+ }
-+
-+ if (pipe_type == UE_CONTROL) {
-+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
-+ }
-+
-+ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
-+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
-+ /*
-+ * USB protocol requires resetting the data toggle for bulk
-+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
-+ * setup command is issued to the endpoint. Anticipate the
-+ * CLEAR_FEATURE command since a STALL has occurred and reset
-+ * the data toggle now.
-+ */
-+ hc->qh->data_toggle = 0;
-+ }
-+
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
-+
-+handle_stall_done:
-+ disable_hc_int(hc_regs, stall);
-+
-+ return 1;
-+}
-+
-+/*
-+ * Updates the state of the URB when a transfer has been stopped due to an
-+ * abnormal condition before the transfer completes. Modifies the
-+ * actual_length field of the URB to reflect the number of bytes that have
-+ * actually been transferred via the host channel.
-+ */
-+static void update_urb_state_xfer_intr(dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_hcd_urb_t * urb,
-+ dwc_otg_qtd_t * qtd,
-+ dwc_otg_halt_status_e halt_status)
-+{
-+ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
-+ halt_status, NULL);
-+ /* non DWORD-aligned buffer case handling. */
-+ if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
-+ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
-+ bytes_transferred);
-+ }
-+
-+ urb->actual_length += bytes_transferred;
-+
-+#ifdef DEBUG
-+ {
-+ hctsiz_data_t hctsiz;
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
-+ __func__, (hc->ep_is_in ? "IN" : "OUT"),
-+ hc->hc_num);
-+ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
-+ hc->start_pkt_count);
-+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
-+ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
-+ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
-+ bytes_transferred);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
-+ urb->actual_length);
-+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
-+ urb->length);
-+ }
-+#endif
-+}
-+
-+/**
-+ * Handles a host channel NAK interrupt. This handler may be called in either
-+ * DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "NAK Received--\n", hc->hc_num);
-+
-+ /*
-+ * When we get bulk NAKs then remember this so we holdoff on this qh until
-+ * the beginning of the next frame
-+ */
-+ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_BULK:
-+ case UE_CONTROL:
-+ if (nak_holdoff && qtd->qh->do_split)
-+ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
-+ }
-+
-+ /*
-+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
-+ * interrupt. Re-start the SSPLIT transfer.
-+ */
-+ if (hc->do_split) {
-+ if (hc->complete_split) {
-+ qtd->error_count = 0;
-+ }
-+ qtd->complete_split = 0;
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+ goto handle_nak_done;
-+ }
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ if (hcd->core_if->dma_enable && hc->ep_is_in) {
-+ /*
-+ * NAK interrupts are enabled on bulk/control IN
-+ * transfers in DMA mode for the sole purpose of
-+ * resetting the error count after a transaction error
-+ * occurs. The core will continue transferring data.
-+ * Disable other interrupts unmasked for the same
-+ * reason.
-+ */
-+ disable_hc_int(hc_regs, datatglerr);
-+ disable_hc_int(hc_regs, ack);
-+ qtd->error_count = 0;
-+ goto handle_nak_done;
-+ }
-+
-+ /*
-+ * NAK interrupts normally occur during OUT transfers in DMA
-+ * or Slave mode. For IN transfers, more requests will be
-+ * queued as request queue space is available.
-+ */
-+ qtd->error_count = 0;
-+
-+ if (!hc->qh->ping_state) {
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd,
-+ DWC_OTG_HC_XFER_NAK);
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
-+ hc->qh->ping_state = 1;
-+ }
-+
-+ /*
-+ * Halt the channel so the transfer can be re-started from
-+ * the appropriate point or the PING protocol will
-+ * start/continue.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+ break;
-+ case UE_INTERRUPT:
-+ qtd->error_count = 0;
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ /* Should never get called for isochronous transfers. */
-+ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
-+ break;
-+ }
-+
-+handle_nak_done:
-+ disable_hc_int(hc_regs, nak);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel ACK interrupt. This interrupt is enabled when
-+ * performing the PING protocol in Slave mode, when errors occur during
-+ * either Slave mode or DMA mode, and during Start Split transactions.
-+ */
-+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "ACK Received--\n", hc->hc_num);
-+
-+ if (hc->do_split) {
-+ /*
-+ * Handle ACK on SSPLIT.
-+ * ACK should not occur in CSPLIT.
-+ */
-+ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
-+ qtd->ssplit_out_xfer_count = hc->xfer_len;
-+ }
-+ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
-+ /* Don't need complete for isochronous out transfers. */
-+ qtd->complete_split = 1;
-+ }
-+
-+ /* ISOC OUT */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
-+ switch (hc->xact_pos) {
-+ case DWC_HCSPLIT_XACTPOS_ALL:
-+ break;
-+ case DWC_HCSPLIT_XACTPOS_END:
-+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+ qtd->isoc_split_offset = 0;
-+ break;
-+ case DWC_HCSPLIT_XACTPOS_BEGIN:
-+ case DWC_HCSPLIT_XACTPOS_MID:
-+ /*
-+ * For BEGIN or MID, calculate the length for
-+ * the next microframe to determine the correct
-+ * SSPLIT token, either MID or END.
-+ */
-+ {
-+ struct dwc_otg_hcd_iso_packet_desc
-+ *frame_desc;
-+
-+ frame_desc =
-+ &qtd->urb->
-+ iso_descs[qtd->isoc_frame_index];
-+ qtd->isoc_split_offset += 188;
-+
-+ if ((frame_desc->length -
-+ qtd->isoc_split_offset) <= 188) {
-+ qtd->isoc_split_pos =
-+ DWC_HCSPLIT_XACTPOS_END;
-+ } else {
-+ qtd->isoc_split_pos =
-+ DWC_HCSPLIT_XACTPOS_MID;
-+ }
-+
-+ }
-+ break;
-+ }
-+ } else {
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
-+ }
-+ } else {
-+ /*
-+ * An unmasked ACK on a non-split DMA transaction is
-+ * for the sole purpose of resetting error counts. Disable other
-+ * interrupts unmasked for the same reason.
-+ */
-+ if(hcd->core_if->dma_enable) {
-+ disable_hc_int(hc_regs, datatglerr);
-+ disable_hc_int(hc_regs, nak);
-+ }
-+ qtd->error_count = 0;
-+
-+ if (hc->qh->ping_state) {
-+ hc->qh->ping_state = 0;
-+ /*
-+ * Halt the channel so the transfer can be re-started
-+ * from the appropriate point. This only happens in
-+ * Slave mode. In DMA mode, the ping_state is cleared
-+ * when the transfer is started because the core
-+ * automatically executes the PING, then the transfer.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
-+ }
-+ }
-+
-+ /*
-+ * If the ACK occurred when _not_ in the PING state, let the channel
-+ * continue transferring data after clearing the error count.
-+ */
-+
-+ disable_hc_int(hc_regs, ack);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel NYET interrupt. This interrupt should only occur on
-+ * Bulk and Control OUT endpoints and for complete split transactions. If a
-+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
-+ * handled in the xfercomp interrupt handler, not here. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "NYET Received--\n", hc->hc_num);
-+
-+ /*
-+ * NYET on CSPLIT
-+ * re-do the CSPLIT immediately on non-periodic
-+ */
-+ if (hc->do_split && hc->complete_split) {
-+ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+ && hcd->core_if->dma_enable) {
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_offset = 0;
-+ if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ }
-+ else
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ goto handle_nyet_done;
-+ }
-+
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ int frnum = dwc_otg_hcd_get_frame_number(hcd);
-+
-+ // With the FIQ running we only ever see the failed NYET
-+ if (dwc_full_frame_num(frnum) !=
-+ dwc_full_frame_num(hc->qh->sched_frame) ||
-+ fiq_fsm_enable) {
-+ /*
-+ * No longer in the same full speed frame.
-+ * Treat this as a transaction error.
-+ */
-+#if 0
-+ /** @todo Fix system performance so this can
-+ * be treated as an error. Right now complete
-+ * splits cannot be scheduled precisely enough
-+ * due to other system activity, so this error
-+ * occurs regularly in Slave mode.
-+ */
-+ qtd->error_count++;
-+#endif
-+ qtd->complete_split = 0;
-+ halt_channel(hcd, hc, qtd,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+ /** @todo add support for isoc release */
-+ goto handle_nyet_done;
-+ }
-+ }
-+
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
-+ goto handle_nyet_done;
-+ }
-+
-+ hc->qh->ping_state = 1;
-+ qtd->error_count = 0;
-+
-+ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
-+ DWC_OTG_HC_XFER_NYET);
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+
-+ /*
-+ * Halt the channel and re-start the transfer so the PING
-+ * protocol will start.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
-+
-+handle_nyet_done:
-+ disable_hc_int(hc_regs, nyet);
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel babble interrupt. This handler may be called in
-+ * either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Babble Error--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ DWC_OTG_HC_XFER_BABBLE_ERR);
-+ goto handle_babble_done;
-+ }
-+
-+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+ hcd->fops->complete(hcd, qtd->urb->priv,
-+ qtd->urb, -DWC_E_OVERFLOW);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
-+ } else {
-+ dwc_otg_halt_status_e halt_status;
-+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_BABBLE_ERR);
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+
-+handle_babble_done:
-+ disable_hc_int(hc_regs, bblerr);
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel AHB error interrupt. This handler is only called in
-+ * DMA mode.
-+ */
-+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ hcchar_data_t hcchar;
-+ hcsplt_data_t hcsplt;
-+ hctsiz_data_t hctsiz;
-+ uint32_t hcdma;
-+ char *pipetype, *speed;
-+
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "AHB Error--\n", hc->hc_num);
-+
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ hcdma = DWC_READ_REG32(&hc_regs->hcdma);
-+
-+ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
-+ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
-+ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
-+ DWC_ERROR(" Device address: %d\n",
-+ dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
-+ DWC_ERROR(" Endpoint: %d, %s\n",
-+ dwc_otg_hcd_get_ep_num(&urb->pipe_info),
-+ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
-+ case UE_CONTROL:
-+ pipetype = "CONTROL";
-+ break;
-+ case UE_BULK:
-+ pipetype = "BULK";
-+ break;
-+ case UE_INTERRUPT:
-+ pipetype = "INTERRUPT";
-+ break;
-+ case UE_ISOCHRONOUS:
-+ pipetype = "ISOCHRONOUS";
-+ break;
-+ default:
-+ pipetype = "UNKNOWN";
-+ break;
-+ }
-+
-+ DWC_ERROR(" Endpoint type: %s\n", pipetype);
-+
-+ switch (hc->speed) {
-+ case DWC_OTG_EP_SPEED_HIGH:
-+ speed = "HIGH";
-+ break;
-+ case DWC_OTG_EP_SPEED_FULL:
-+ speed = "FULL";
-+ break;
-+ case DWC_OTG_EP_SPEED_LOW:
-+ speed = "LOW";
-+ break;
-+ default:
-+ speed = "UNKNOWN";
-+ break;
-+ };
-+
-+ DWC_ERROR(" Speed: %s\n", speed);
-+
-+ DWC_ERROR(" Max packet size: %d\n",
-+ dwc_otg_hcd_get_mps(&urb->pipe_info));
-+ DWC_ERROR(" Data buffer length: %d\n", urb->length);
-+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
-+ urb->buf, (void *)urb->dma);
-+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
-+ urb->setup_packet, (void *)urb->setup_dma);
-+ DWC_ERROR(" Interval: %d\n", urb->interval);
-+
-+ /* Core haltes the channel for Descriptor DMA mode */
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ DWC_OTG_HC_XFER_AHB_ERR);
-+ goto handle_ahberr_done;
-+ }
-+
-+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
-+
-+ /*
-+ * Force a channel halt. Don't call halt_channel because that won't
-+ * write to the HCCHARn register in DMA mode to force the halt.
-+ */
-+ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
-+handle_ahberr_done:
-+ disable_hc_int(hc_regs, ahberr);
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel transaction error interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Transaction Error--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+ goto handle_xacterr_done;
-+ }
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ qtd->error_count++;
-+ if (!hc->qh->ping_state) {
-+
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+ hc->qh->ping_state = 1;
-+ }
-+ }
-+
-+ /*
-+ * Halt the channel so the transfer can be re-started from
-+ * the appropriate point or the PING protocol will start.
-+ */
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ break;
-+ case UE_INTERRUPT:
-+ qtd->error_count++;
-+ if (hc->do_split && hc->complete_split) {
-+ qtd->complete_split = 0;
-+ }
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ {
-+ dwc_otg_halt_status_e halt_status;
-+ halt_status =
-+ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_XACT_ERR);
-+
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+ break;
-+ }
-+handle_xacterr_done:
-+ disable_hc_int(hc_regs, xacterr);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel frame overrun interrupt. This handler may be called
-+ * in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Frame Overrun--\n", hc->hc_num);
-+
-+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+ case UE_CONTROL:
-+ case UE_BULK:
-+ break;
-+ case UE_INTERRUPT:
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
-+ break;
-+ case UE_ISOCHRONOUS:
-+ {
-+ dwc_otg_halt_status_e halt_status;
-+ halt_status =
-+ update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+ DWC_OTG_HC_XFER_FRAME_OVERRUN);
-+
-+ halt_channel(hcd, hc, qtd, halt_status);
-+ }
-+ break;
-+ }
-+
-+ disable_hc_int(hc_regs, frmovrun);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handles a host channel data toggle error interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Data Toggle Error on %s transfer--\n",
-+ hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
-+
-+ /* Data toggles on split transactions cause the hc to halt.
-+ * restart transfer */
-+ if(hc->qh->do_split)
-+ {
-+ qtd->error_count++;
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ } else if (hc->ep_is_in) {
-+ /* An unmasked data toggle error on a non-split DMA transaction is
-+ * for the sole purpose of resetting error counts. Disable other
-+ * interrupts unmasked for the same reason.
-+ */
-+ if(hcd->core_if->dma_enable) {
-+ disable_hc_int(hc_regs, ack);
-+ disable_hc_int(hc_regs, nak);
-+ }
-+ qtd->error_count = 0;
-+ }
-+
-+ disable_hc_int(hc_regs, datatglerr);
-+
-+ return 1;
-+}
-+
-+#ifdef DEBUG
-+/**
-+ * This function is for debug only. It checks that a valid halt status is set
-+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
-+ * taken and a warning is issued.
-+ * @return 1 if halt status is ok, 0 otherwise.
-+ */
-+static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ hcchar_data_t hcchar;
-+ hctsiz_data_t hctsiz;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ hcsplt_data_t hcsplt;
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
-+ /*
-+ * This code is here only as a check. This condition should
-+ * never happen. Ignore the halt if it does occur.
-+ */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+ DWC_WARN
-+ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
-+ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
-+ "hcint 0x%08x, hcintmsk 0x%08x, "
-+ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
-+ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
-+ hcintmsk.d32, hcsplt.d32, qtd->complete_split);
-+
-+ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
-+ __func__, hc->hc_num);
-+ DWC_WARN("\n");
-+ clear_hc_int(hc_regs, chhltd);
-+ return 0;
-+ }
-+
-+ /*
-+ * This code is here only as a check. hcchar.chdis should
-+ * never be set when the halt interrupt occurs. Halt the
-+ * channel again if it does occur.
-+ */
-+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+ if (hcchar.b.chdis) {
-+ DWC_WARN("%s: hcchar.chdis set unexpectedly, "
-+ "hcchar 0x%08x, trying to halt again\n",
-+ __func__, hcchar.d32);
-+ clear_hc_int(hc_regs, chhltd);
-+ hc->halt_pending = 0;
-+ halt_channel(hcd, hc, qtd, hc->halt_status);
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+#endif
-+
-+/**
-+ * Handles a host Channel Halted interrupt in DMA mode. This handler
-+ * determines the reason the channel halted and proceeds accordingly.
-+ */
-+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ int out_nak_enh = 0;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ /* For core with OUT NAK enhancement, the flow for high-
-+ * speed CONTROL/BULK OUT is handled a little differently.
-+ */
-+ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
-+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
-+ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
-+ out_nak_enh = 1;
-+ }
-+ }
-+
-+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
-+ && !hcd->core_if->dma_desc_enable)) {
-+ /*
-+ * Just release the channel. A dequeue can happen on a
-+ * transfer timeout. In the case of an AHB Error, the channel
-+ * was forced to halt because there's no way to gracefully
-+ * recover.
-+ */
-+ if (hcd->core_if->dma_desc_enable)
-+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+ hc->halt_status);
-+ else
-+ release_channel(hcd, hc, qtd, hc->halt_status);
-+ return;
-+ }
-+
-+ /* Read the HCINTn register to determine the cause for the halt. */
-+
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+
-+ if (hcint.b.xfercomp) {
-+ /** @todo This is here because of a possible hardware bug. Spec
-+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
-+ * interrupt w/ACK bit set should occur, but I only see the
-+ * XFERCOMP bit, even with it masked out. This is a workaround
-+ * for that behavior. Should fix this when hardware is fixed.
-+ */
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
-+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
-+ }
-+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.stall) {
-+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
-+ if (out_nak_enh) {
-+ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
-+ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
-+ qtd->error_count = 0;
-+ } else {
-+ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
-+ }
-+ }
-+
-+ /*
-+ * Must handle xacterr before nak or ack. Could get a xacterr
-+ * at the same time as either of these on a BULK/CONTROL OUT
-+ * that started with a PING. The xacterr takes precedence.
-+ */
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
-+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.bblerr) {
-+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.frmovrun) {
-+ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.datatglerr) {
-+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (!out_nak_enh) {
-+ if (hcint.b.nyet) {
-+ /*
-+ * Must handle nyet before nak or ack. Could get a nyet at the
-+ * same time as either of those on a BULK/CONTROL OUT that
-+ * started with a PING. The nyet takes precedence.
-+ */
-+ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.nak && !hcintmsk.b.nak) {
-+ /*
-+ * If nak is not masked, it's because a non-split IN transfer
-+ * is in an error state. In that case, the nak is handled by
-+ * the nak interrupt handler, not here. Handle nak here for
-+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow
-+ * rewinding the buffer pointer.
-+ */
-+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ack && !hcintmsk.b.ack) {
-+ /*
-+ * If ack is not masked, it's because a non-split IN transfer
-+ * is in an error state. In that case, the ack is handled by
-+ * the ack interrupt handler, not here. Handle ack here for
-+ * split transfers. Start splits halt on ACK.
-+ */
-+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * A periodic transfer halted with no other channel
-+ * interrupts set. Assume it was halted by the core
-+ * because it could not be completed in its scheduled
-+ * (micro)frame.
-+ */
-+#ifdef DEBUG
-+ DWC_PRINTF
-+ ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
-+ __func__, hc->hc_num);
-+#endif
-+ halt_channel(hcd, hc, qtd,
-+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
-+ } else {
-+ DWC_ERROR
-+ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
-+ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
-+ __func__, hc->hc_num, hcint.d32,
-+ DWC_READ_REG32(&hcd->
-+ core_if->core_global_regs->
-+ gintsts));
-+ /* Failthrough: use 3-strikes rule */
-+ qtd->error_count++;
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ }
-+
-+ }
-+ } else {
-+ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
-+ hcint.d32);
-+ /* Failthrough: use 3-strikes rule */
-+ qtd->error_count++;
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ update_urb_state_xfer_intr(hc, hc_regs,
-+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+ }
-+}
-+
-+/**
-+ * Handles a host channel Channel Halted interrupt.
-+ *
-+ * In slave mode, this handler is called only when the driver specifically
-+ * requests a halt. This occurs during handling other host channel interrupts
-+ * (e.g. nak, xacterr, stall, nyet, etc.).
-+ *
-+ * In DMA mode, this is the interrupt that occurs when the core has finished
-+ * processing a transfer on a channel. Other host channel interrupts (except
-+ * ahberr) are disabled in DMA mode.
-+ */
-+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
-+ dwc_hc_t * hc,
-+ dwc_otg_hc_regs_t * hc_regs,
-+ dwc_otg_qtd_t * qtd)
-+{
-+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+ "Channel Halted--\n", hc->hc_num);
-+
-+ if (hcd->core_if->dma_enable) {
-+ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
-+ } else {
-+#ifdef DEBUG
-+ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
-+ return 1;
-+ }
-+#endif
-+ release_channel(hcd, hc, qtd, hc->halt_status);
-+ }
-+
-+ return 1;
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
-+ * FIQ transfer completion
-+ * @hcd: Pointer to dwc_otg_hcd struct
-+ * @num: Host channel number
-+ *
-+ * 1. Un-mangle the status as recorded in each iso_frame_desc status
-+ * 2. Copy it from the dwc_otg_urb into the real URB
-+ */
-+void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
-+{
-+ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
-+ int nr_frames = dwc_urb->packet_count;
-+ int i;
-+ hcint_data_t frame_hcint;
-+
-+ for (i = 0; i < nr_frames; i++) {
-+ frame_hcint.d32 = dwc_urb->iso_descs[i].status;
-+ if (frame_hcint.b.xfercomp) {
-+ dwc_urb->iso_descs[i].status = 0;
-+ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
-+ } else if (frame_hcint.b.frmovrun) {
-+ if (qh->ep_is_in)
-+ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
-+ else
-+ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
-+ dwc_urb->error_count++;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ } else if (frame_hcint.b.xacterr) {
-+ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
-+ dwc_urb->error_count++;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ } else if (frame_hcint.b.bblerr) {
-+ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
-+ dwc_urb->error_count++;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ } else {
-+ /* Something went wrong */
-+ dwc_urb->iso_descs[i].status = -1;
-+ dwc_urb->iso_descs[i].actual_length = 0;
-+ dwc_urb->error_count++;
-+ }
-+ }
-+ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
-+ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
-+ hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0);
-+ release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+}
-+
-+/**
-+ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
-+ * @hcd: Pointer to dwc_otg_hcd struct
-+ * @num: Host channel number
-+ *
-+ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
-+ * Returns total length of data or -1 if the buffers were not used.
-+ *
-+ */
-+int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
-+{
-+ dwc_hc_t *hc = qh->channel;
-+ struct fiq_dma_blob *blob = hcd->fiq_dmab;
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+ uint8_t *ptr = NULL;
-+ int index = 0, len = 0;
-+ int i = 0;
-+ if (hc->ep_is_in) {
-+ /* Copy data out of the DMA bounce buffers to the URB's buffer.
-+ * The align_buf is ignored as this is ignored on FSM enqueue. */
-+ ptr = qtd->urb->buf;
-+ if (qh->ep_type == UE_ISOCHRONOUS) {
-+ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
-+ index = qtd->isoc_frame_index;
-+ ptr += qtd->urb->iso_descs[index].offset;
-+ } else {
-+ /* Need to increment by actual_length for interrupt IN */
-+ ptr += qtd->urb->actual_length;
-+ }
-+
-+ for (i = 0; i < st->dma_info.index; i++) {
-+ len += st->dma_info.slot_len[i];
-+ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
-+ ptr += st->dma_info.slot_len[i];
-+ }
-+ return len;
-+ } else {
-+ /* OUT endpoints - nothing to do. */
-+ return -1;
-+ }
-+
-+}
-+/**
-+ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
-+ * from a channel handled in the FIQ
-+ * @hcd: Pointer to dwc_otg_hcd struct
-+ * @num: Host channel number
-+ *
-+ * If a host channel interrupt was received by the IRQ and this was a channel
-+ * used by the FIQ, the execution flow for transfer completion is substantially
-+ * different from the normal (messy) path. This function and its friends handles
-+ * channel cleanup and transaction completion from a FIQ transaction.
-+ */
-+void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
-+{
-+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+ dwc_hc_t *hc = hcd->hc_ptr_array[num];
-+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
-+ dwc_otg_qh_t *qh = hc->qh;
-+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
-+ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
-+ int hostchannels = 0;
-+ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
-+
-+ hostchannels = hcd->available_host_channels;
-+ switch (st->fsm) {
-+ case FIQ_TEST:
-+ break;
-+
-+ case FIQ_DEQUEUE_ISSUED:
-+ /* hc_halt was called. QTD no longer exists. */
-+ /* TODO: for a nonperiodic split transaction, need to issue a
-+ * CLEAR_TT_BUFFER hub command if we were in the start-split phase.
-+ */
-+ release_channel(hcd, hc, NULL, hc->halt_status);
-+ break;
-+
-+ case FIQ_NP_SPLIT_DONE:
-+ /* Nonperiodic transaction complete. */
-+ if (!hc->ep_is_in) {
-+ qtd->ssplit_out_xfer_count = hc->xfer_len;
-+ }
-+ if (hcint.b.xfercomp) {
-+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.nak) {
-+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+ }
-+ break;
-+
-+ case FIQ_NP_SPLIT_HS_ABORTED:
-+ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
-+ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
-+ * because there's no guarantee which order a non-periodic split happened in.
-+ * We could end up clearing a perfectly good transaction out of the buffer.
-+ */
-+ if (hcint.b.xacterr) {
-+ qtd->error_count += st->nr_errors;
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ahberr) {
-+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ local_fiq_disable();
-+ BUG();
-+ }
-+ break;
-+
-+ case FIQ_NP_SPLIT_LS_ABORTED:
-+ /* A few cases can cause this - either an unknown state on a SSPLIT or
-+ * STALL/data toggle error response on a CSPLIT */
-+ if (hcint.b.stall) {
-+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.datatglerr) {
-+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.bblerr) {
-+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.ahberr) {
-+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ local_fiq_disable();
-+ BUG();
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_DONE:
-+ /* Isoc IN or Interrupt IN/OUT */
-+
-+ /* Flow control here is different from the normal execution by the driver.
-+ * We need to completely ignore most of the driver's method of handling
-+ * split transactions and do it ourselves.
-+ */
-+ if (hc->ep_type == UE_INTERRUPT) {
-+ if (hcint.b.nak) {
-+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hc->ep_is_in) {
-+ int len;
-+ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
-+ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
-+ qtd->urb->actual_length += len;
-+ if (qtd->urb->actual_length >= qtd->urb->length) {
-+ qtd->urb->status = 0;
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ /* Interrupt transfer not complete yet - is it a short read? */
-+ if (len < hc->max_packet) {
-+ /* Interrupt transaction complete */
-+ qtd->urb->status = 0;
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ /* Further transactions required */
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ } else {
-+ /* Interrupt OUT complete. */
-+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+ qtd->urb->actual_length += hc->xfer_len;
-+ if (qtd->urb->actual_length >= qtd->urb->length) {
-+ qtd->urb->status = 0;
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ } else {
-+ /* ISOC IN complete. */
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ int len = 0;
-+ /* Record errors, update qtd. */
-+ if (st->nr_errors) {
-+ frame_desc->actual_length = 0;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ } else {
-+ frame_desc->status = 0;
-+ /* Unswizzle dma */
-+ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num);
-+ frame_desc->actual_length = len;
-+ }
-+ qtd->isoc_frame_index++;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_ISO_OUT_DONE: {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ /* Record errors, update qtd. */
-+ if (st->nr_errors) {
-+ frame_desc->actual_length = 0;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ } else {
-+ frame_desc->status = 0;
-+ frame_desc->actual_length = frame_desc->length;
-+ }
-+ qtd->isoc_frame_index++;
-+ qtd->isoc_split_offset = 0;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_NYET_ABORTED:
-+ /* Doh. lost the data. */
-+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
-+ "- FIQ reported NYET. Data may have been lost.\n",
-+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
-+ if (hc->ep_type == UE_ISOCHRONOUS) {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ /* Record errors, update qtd. */
-+ frame_desc->actual_length = 0;
-+ frame_desc->status = -DWC_E_PROTOCOL;
-+ qtd->isoc_frame_index++;
-+ qtd->isoc_split_offset = 0;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ break;
-+
-+ case FIQ_HS_ISOC_DONE:
-+ /* The FIQ has performed a whole pile of isochronous transactions.
-+ * The status is recorded as the interrupt state should the transaction
-+ * fail.
-+ */
-+ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num);
-+ break;
-+
-+ case FIQ_PER_SPLIT_LS_ABORTED:
-+ if (hcint.b.xacterr) {
-+ /* Hub has responded with an ERR packet. Device
-+ * has been unplugged or the port has been disabled.
-+ * TODO: need to issue a reset to the hub port. */
-+ qtd->error_count += 3;
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.stall) {
-+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+ } else if (hcint.b.bblerr) {
-+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+ } else {
-+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
-+ "- FIQ reported FSM=%d. Data may have been lost.\n",
-+ st->fsm, hc->dev_addr, hc->ep_num);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ break;
-+
-+ case FIQ_PER_SPLIT_HS_ABORTED:
-+ /* Either the SSPLIT phase suffered transaction errors or something
-+ * unexpected happened.
-+ */
-+ qtd->error_count += 3;
-+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ break;
-+
-+ case FIQ_PER_SPLIT_TIMEOUT:
-+ /* Couldn't complete in the nominated frame */
-+ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
-+ "- FIQ timed out. Data may have been lost.\n",
-+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
-+ if (hc->ep_type == UE_ISOCHRONOUS) {
-+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+ /* Record errors, update qtd. */
-+ frame_desc->actual_length = 0;
-+ if (hc->ep_is_in) {
-+ frame_desc->status = -DWC_E_NO_STREAM_RES;
-+ } else {
-+ frame_desc->status = -DWC_E_COMMUNICATION;
-+ }
-+ qtd->isoc_frame_index++;
-+ if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+ }
-+ } else {
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ break;
-+
-+ default:
-+ DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x",
-+ hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);
-+ qtd->error_count++;
-+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+ }
-+ return;
-+}
-+
-+/** Handles interrupt for a specific Host Channel */
-+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
-+{
-+ int retval = 0;
-+ hcint_data_t hcint;
-+ hcintmsk_data_t hcintmsk;
-+ dwc_hc_t *hc;
-+ dwc_otg_hc_regs_t *hc_regs;
-+ dwc_otg_qtd_t *qtd;
-+
-+ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
-+
-+ hc = dwc_otg_hcd->hc_ptr_array[num];
-+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
-+ if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+ /* We are responding to a channel disable. Driver
-+ * state is cleared - our qtd has gone away.
-+ */
-+ release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
-+ return 1;
-+ }
-+ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
-+
-+ /*
-+ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
-+ * Execution path is fundamentally different for the channels after a FIQ has completed
-+ * a split transaction.
-+ */
-+ if (fiq_fsm_enable) {
-+ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
-+ case FIQ_PASSTHROUGH:
-+ break;
-+ case FIQ_PASSTHROUGH_ERRORSTATE:
-+ /* Hook into the error count */
-+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
-+ if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
-+ qtd->error_count = 0;
-+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET ");
-+ }
-+ break;
-+ default:
-+ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
-+ return 1;
-+ }
-+ }
-+
-+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+ hcint.d32 = hcint.d32 & hcintmsk.d32;
-+ if (!dwc_otg_hcd->core_if->dma_enable) {
-+ if (hcint.b.chhltd && hcint.d32 != 0x2) {
-+ hcint.b.chhltd = 0;
-+ }
-+ }
-+
-+ if (hcint.b.xfercomp) {
-+ retval |=
-+ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ /*
-+ * If NYET occurred at same time as Xfer Complete, the NYET is
-+ * handled by the Xfer Complete interrupt handler. Don't want
-+ * to call the NYET interrupt handler in this case.
-+ */
-+ hcint.b.nyet = 0;
-+ }
-+ if (hcint.b.chhltd) {
-+ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.ahberr) {
-+ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.stall) {
-+ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.nak) {
-+ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.ack) {
-+ if(!hcint.b.chhltd)
-+ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.nyet) {
-+ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.xacterr) {
-+ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.bblerr) {
-+ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.frmovrun) {
-+ retval |=
-+ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+ if (hcint.b.datatglerr) {
-+ retval |=
-+ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+ }
-+
-+ return retval;
-+}
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,994 @@
-+
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
-+ * $Revision: #20 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1872981 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the implementation of the HCD. In Linux, the HCD
-+ * implements the hc_driver API.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/string.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/version.h>
-+#include <asm/io.h>
-+#include <asm/fiq.h>
-+#include <linux/usb.h>
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
-+#include <../drivers/usb/core/hcd.h>
-+#else
-+#include <linux/usb/hcd.h>
-+#endif
-+#include <asm/bug.h>
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
-+#define USB_URB_EP_LINKING 1
-+#else
-+#define USB_URB_EP_LINKING 0
-+#endif
-+
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_hcd.h"
-+
-+extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
-+
-+/**
-+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
-+ * qualified with its direction (possible 32 endpoints per device).
-+ */
-+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
-+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
-+
-+static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
-+
-+extern bool fiq_enable;
-+
-+/** @name Linux HC Driver API Functions */
-+/** @{ */
-+/* manage i/o requests, device state */
-+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ struct usb_host_endpoint *ep,
-+#endif
-+ struct urb *urb, gfp_t mem_flags);
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
-+#endif
-+#else /* kernels at or post 2.6.30 */
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
-+ struct urb *urb, int status);
-+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
-+
-+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
-+#endif
-+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
-+extern int hcd_start(struct usb_hcd *hcd);
-+extern void hcd_stop(struct usb_hcd *hcd);
-+static int get_frame_number(struct usb_hcd *hcd);
-+extern int hub_status_data(struct usb_hcd *hcd, char *buf);
-+extern int hub_control(struct usb_hcd *hcd,
-+ u16 typeReq,
-+ u16 wValue, u16 wIndex, char *buf, u16 wLength);
-+
-+struct wrapper_priv_data {
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+};
-+
-+/** @} */
-+
-+static struct hc_driver dwc_otg_hc_driver = {
-+
-+ .description = dwc_otg_hcd_name,
-+ .product_desc = "DWC OTG Controller",
-+ .hcd_priv_size = sizeof(struct wrapper_priv_data),
-+
-+ .irq = dwc_otg_hcd_irq,
-+
-+ .flags = HCD_MEMORY | HCD_USB2,
-+
-+ //.reset =
-+ .start = hcd_start,
-+ //.suspend =
-+ //.resume =
-+ .stop = hcd_stop,
-+
-+ .urb_enqueue = dwc_otg_urb_enqueue,
-+ .urb_dequeue = dwc_otg_urb_dequeue,
-+ .endpoint_disable = endpoint_disable,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+ .endpoint_reset = endpoint_reset,
-+#endif
-+ .get_frame_number = get_frame_number,
-+
-+ .hub_status_data = hub_status_data,
-+ .hub_control = hub_control,
-+ //.bus_suspend =
-+ //.bus_resume =
-+};
-+
-+/** Gets the dwc_otg_hcd from a struct usb_hcd */
-+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
-+{
-+ struct wrapper_priv_data *p;
-+ p = (struct wrapper_priv_data *)(hcd->hcd_priv);
-+ return p->dwc_otg_hcd;
-+}
-+
-+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
-+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
-+}
-+
-+/** Gets the usb_host_endpoint associated with an URB. */
-+inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
-+{
-+ struct usb_device *dev = urb->dev;
-+ int ep_num = usb_pipeendpoint(urb->pipe);
-+
-+ if (usb_pipein(urb->pipe))
-+ return dev->ep_in[ep_num];
-+ else
-+ return dev->ep_out[ep_num];
-+}
-+
-+static int _disconnect(dwc_otg_hcd_t * hcd)
-+{
-+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+
-+ usb_hcd->self.is_b_host = 0;
-+ return 0;
-+}
-+
-+static int _start(dwc_otg_hcd_t * hcd)
-+{
-+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+
-+ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
-+ hcd_start(usb_hcd);
-+
-+ return 0;
-+}
-+
-+static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
-+ uint32_t * port_addr)
-+{
-+ struct urb *urb = (struct urb *)urb_handle;
-+ struct usb_bus *bus;
-+#if 1 //GRAYG - temporary
-+ if (NULL == urb_handle)
-+ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
-+ if (NULL == urb->dev)
-+ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
-+ if (NULL == port_addr)
-+ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
-+#endif
-+ if (urb->dev->tt) {
-+ if (NULL == urb->dev->tt->hub) {
-+ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
-+ __func__); //GRAYG
-+ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
-+ *hub_addr = 0; //GRAYG
-+ // we probably shouldn't have a transaction translator if
-+ // there's no associated hub?
-+ } else {
-+ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
-+ if (urb->dev->tt->hub == bus->root_hub)
-+ *hub_addr = 0;
-+ else
-+ *hub_addr = urb->dev->tt->hub->devnum;
-+ }
-+ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
-+ } else {
-+ *hub_addr = 0;
-+ *port_addr = urb->dev->ttport;
-+ }
-+ return 0;
-+}
-+
-+static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
-+{
-+ struct urb *urb = (struct urb *)urb_handle;
-+ return urb->dev->speed;
-+}
-+
-+static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
-+{
-+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+ return usb_hcd->self.b_hnp_enable;
-+}
-+
-+static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
-+ struct urb *urb)
-+{
-+ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
-+ } else {
-+ hcd_to_bus(hcd)->bandwidth_int_reqs++;
-+ }
-+}
-+
-+static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
-+ struct urb *urb)
-+{
-+ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
-+ } else {
-+ hcd_to_bus(hcd)->bandwidth_int_reqs--;
-+ }
-+}
-+
-+/**
-+ * Sets the final status of an URB and returns it to the device driver. Any
-+ * required cleanup of the URB is performed. The HCD lock should be held on
-+ * entry.
-+ */
-+static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
-+ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
-+{
-+ struct urb *urb = (struct urb *)urb_handle;
-+ urb_tq_entry_t *new_entry;
-+ int rc = 0;
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
-+ __func__, urb, usb_pipedevice(urb->pipe),
-+ usb_pipeendpoint(urb->pipe),
-+ usb_pipein(urb->pipe) ? "IN" : "OUT", status);
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ int i;
-+ for (i = 0; i < urb->number_of_packets; i++) {
-+ DWC_PRINTF(" ISO Desc %d status: %d\n",
-+ i, urb->iso_frame_desc[i].status);
-+ }
-+ }
-+ }
-+ new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
-+ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
-+ /* Convert status value. */
-+ switch (status) {
-+ case -DWC_E_PROTOCOL:
-+ status = -EPROTO;
-+ break;
-+ case -DWC_E_IN_PROGRESS:
-+ status = -EINPROGRESS;
-+ break;
-+ case -DWC_E_PIPE:
-+ status = -EPIPE;
-+ break;
-+ case -DWC_E_IO:
-+ status = -EIO;
-+ break;
-+ case -DWC_E_TIMEOUT:
-+ status = -ETIMEDOUT;
-+ break;
-+ case -DWC_E_OVERFLOW:
-+ status = -EOVERFLOW;
-+ break;
-+ case -DWC_E_SHUTDOWN:
-+ status = -ESHUTDOWN;
-+ break;
-+ default:
-+ if (status) {
-+ DWC_PRINTF("Uknown urb status %d\n", status);
-+
-+ }
-+ }
-+
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ int i;
-+
-+ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
-+ for (i = 0; i < urb->number_of_packets; ++i) {
-+ urb->iso_frame_desc[i].actual_length =
-+ dwc_otg_hcd_urb_get_iso_desc_actual_length
-+ (dwc_otg_urb, i);
-+ urb->iso_frame_desc[i].status =
-+ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
-+ }
-+ }
-+
-+ urb->status = status;
-+ urb->hcpriv = NULL;
-+ if (!status) {
-+ if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
-+ (urb->actual_length < urb->transfer_buffer_length)) {
-+ urb->status = -EREMOTEIO;
-+ }
-+ }
-+
-+ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
-+ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
-+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
-+ if (ep) {
-+ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
-+ dwc_otg_hcd_get_ep_bandwidth(hcd,
-+ ep->hcpriv),
-+ urb);
-+ }
-+ }
-+ DWC_FREE(dwc_otg_urb);
-+ if (!new_entry) {
-+ DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
-+ urb->status = -EPROTO;
-+ /* don't schedule the tasklet -
-+ * directly return the packet here with error. */
-+#if USB_URB_EP_LINKING
-+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
-+#endif
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
-+#else
-+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
-+#endif
-+ } else {
-+ new_entry->urb = urb;
-+#if USB_URB_EP_LINKING
-+ rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
-+ if(0 == rc) {
-+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
-+ }
-+#endif
-+ if(0 == rc) {
-+ DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
-+ urb_tq_entries);
-+ DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
-+ }
-+ }
-+ return 0;
-+}
-+
-+static struct dwc_otg_hcd_function_ops hcd_fops = {
-+ .start = _start,
-+ .disconnect = _disconnect,
-+ .hub_info = _hub_info,
-+ .speed = _speed,
-+ .complete = _complete,
-+ .get_b_hnp_enable = _get_b_hnp_enable,
-+};
-+
-+static struct fiq_handler fh = {
-+ .name = "usb_fiq",
-+};
-+
-+static void hcd_init_fiq(void *cookie)
-+{
-+ dwc_otg_device_t *otg_dev = cookie;
-+ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
-+ struct pt_regs regs;
-+
-+ if (claim_fiq(&fh)) {
-+ DWC_ERROR("Can't claim FIQ");
-+ BUG();
-+ }
-+ DWC_WARN("FIQ on core %d at 0x%08x",
-+ smp_processor_id(),
-+ (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
-+ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
-+ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
-+ memset(&regs,0,sizeof(regs));
-+
-+ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
-+ if (fiq_fsm_enable) {
-+ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
-+ //regs.ARM_r10 = dwc_otg_hcd->dma;
-+ regs.ARM_fp = (long) dwc_otg_fiq_fsm;
-+ } else {
-+ regs.ARM_fp = (long) dwc_otg_fiq_nop;
-+ }
-+
-+ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
-+
-+// __show_regs(&regs);
-+ set_fiq_regs(&regs);
-+
-+ //Set the mphi periph to the required registers
-+ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base;
-+ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c;
-+ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28;
-+ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c;
-+ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
-+ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
-+ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
-+ //Enable mphi peripheral
-+ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
-+#ifdef DEBUG
-+ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
-+ DWC_WARN("MPHI periph has been enabled");
-+ else
-+ DWC_WARN("MPHI periph has NOT been enabled");
-+#endif
-+ // Enable FIQ interrupt from USB peripheral
-+ enable_fiq(INTERRUPT_VC_USB);
-+ local_fiq_enable();
-+}
-+
-+/**
-+ * Initializes the HCD. This function allocates memory for and initializes the
-+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
-+ * USB bus with the core and calls the hc_driver->start() function. It returns
-+ * a negative error on failure.
-+ */
-+int hcd_init(dwc_bus_dev_t *_dev)
-+{
-+ struct usb_hcd *hcd = NULL;
-+ dwc_otg_hcd_t *dwc_otg_hcd = NULL;
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ int retval = 0;
-+ u64 dmamask;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
-+
-+ /* Set device flags indicating whether the HCD supports DMA. */
-+ if (dwc_otg_is_dma_enable(otg_dev->core_if))
-+ dmamask = DMA_BIT_MASK(32);
-+ else
-+ dmamask = 0;
-+
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+ dma_set_mask(&_dev->dev, dmamask);
-+ dma_set_coherent_mask(&_dev->dev, dmamask);
-+#elif defined(PCI_INTERFACE)
-+ pci_set_dma_mask(_dev, dmamask);
-+ pci_set_consistent_dma_mask(_dev, dmamask);
-+#endif
-+
-+ /*
-+ * Allocate memory for the base HCD plus the DWC OTG HCD.
-+ * Initialize the base HCD.
-+ */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
-+#else
-+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
-+ hcd->has_tt = 1;
-+// hcd->uses_new_polling = 1;
-+// hcd->poll_rh = 0;
-+#endif
-+ if (!hcd) {
-+ retval = -ENOMEM;
-+ goto error1;
-+ }
-+
-+ hcd->regs = otg_dev->os_dep.base;
-+
-+
-+ /* Initialize the DWC OTG HCD. */
-+ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
-+ if (!dwc_otg_hcd) {
-+ goto error2;
-+ }
-+ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
-+ dwc_otg_hcd;
-+ otg_dev->hcd = dwc_otg_hcd;
-+
-+ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
-+ goto error2;
-+ }
-+
-+ if (fiq_enable) {
-+ if (num_online_cpus() > 1) {
-+ /* bcm2709: can run the FIQ on a separate core to IRQs */
-+ smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
-+ } else {
-+ smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
-+ }
-+ }
-+
-+ otg_dev->hcd->otg_dev = otg_dev;
-+ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
-+ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
-+#endif
-+ /* Don't support SG list at this point */
-+ hcd->self.sg_tablesize = 0;
-+#endif
-+ /*
-+ * Finish generic HCD initialization and start the HCD. This function
-+ * allocates the DMA buffer pool, registers the USB bus, requests the
-+ * IRQ line, and calls hcd_start method.
-+ */
-+#ifdef PLATFORM_INTERFACE
-+ retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED | IRQF_DISABLED);
-+#else
-+ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED | IRQF_DISABLED);
-+#endif
-+ if (retval < 0) {
-+ goto error2;
-+ }
-+
-+ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
-+ return 0;
-+
-+error2:
-+ usb_put_hcd(hcd);
-+error1:
-+ return retval;
-+}
-+
-+/**
-+ * Removes the HCD.
-+ * Frees memory and resources associated with the HCD and deregisters the bus.
-+ */
-+void hcd_remove(dwc_bus_dev_t *_dev)
-+{
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+ struct usb_hcd *hcd;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
-+
-+ if (!otg_dev) {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
-+ return;
-+ }
-+
-+ dwc_otg_hcd = otg_dev->hcd;
-+
-+ if (!dwc_otg_hcd) {
-+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
-+ return;
-+ }
-+
-+ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
-+
-+ if (!hcd) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
-+ __func__);
-+ return;
-+ }
-+ usb_remove_hcd(hcd);
-+ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
-+ dwc_otg_hcd_remove(dwc_otg_hcd);
-+ usb_put_hcd(hcd);
-+}
-+
-+/* =========================================================================
-+ * Linux HC Driver Functions
-+ * ========================================================================= */
-+
-+/** Initializes the DWC_otg controller and its root hub and prepares it for host
-+ * mode operation. Activates the root port. Returns 0 on success and a negative
-+ * error code on failure. */
-+int hcd_start(struct usb_hcd *hcd)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ struct usb_bus *bus;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
-+ bus = hcd_to_bus(hcd);
-+
-+ hcd->state = HC_STATE_RUNNING;
-+ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
-+ return 0;
-+ }
-+
-+ /* Initialize and connect root hub if one is not already attached */
-+ if (bus->root_hub) {
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
-+ /* Inform the HUB driver to resume. */
-+ usb_hcd_resume_root_hub(hcd);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ */
-+void hcd_stop(struct usb_hcd *hcd)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+ dwc_otg_hcd_stop(dwc_otg_hcd);
-+}
-+
-+/** Returns the current frame number. */
-+static int get_frame_number(struct usb_hcd *hcd)
-+{
-+ hprt0_data_t hprt0;
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
-+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
-+ else
-+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
-+}
-+
-+#ifdef DEBUG
-+static void dump_urb_info(struct urb *urb, char *fn_name)
-+{
-+ DWC_PRINTF("%s, urb %p\n", fn_name, urb);
-+ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
-+ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
-+ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
-+ DWC_PRINTF(" Endpoint type: %s\n", ( {
-+ char *pipetype;
-+ switch (usb_pipetype(urb->pipe)) {
-+case PIPE_CONTROL:
-+pipetype = "CONTROL"; break; case PIPE_BULK:
-+pipetype = "BULK"; break; case PIPE_INTERRUPT:
-+pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
-+pipetype = "ISOCHRONOUS"; break; default:
-+ pipetype = "UNKNOWN"; break;};
-+ pipetype;}
-+ )) ;
-+ DWC_PRINTF(" Speed: %s\n", ( {
-+ char *speed; switch (urb->dev->speed) {
-+case USB_SPEED_HIGH:
-+speed = "HIGH"; break; case USB_SPEED_FULL:
-+speed = "FULL"; break; case USB_SPEED_LOW:
-+speed = "LOW"; break; default:
-+ speed = "UNKNOWN"; break;};
-+ speed;}
-+ )) ;
-+ DWC_PRINTF(" Max packet size: %d\n",
-+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
-+ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length);
-+ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n",
-+ urb->transfer_buffer, (void *)urb->transfer_dma);
-+ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n",
-+ urb->setup_packet, (void *)urb->setup_dma);
-+ DWC_PRINTF(" Interval: %d\n", urb->interval);
-+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+ int i;
-+ for (i = 0; i < urb->number_of_packets; i++) {
-+ DWC_PRINTF(" ISO Desc %d:\n", i);
-+ DWC_PRINTF(" offset: %d, length %d\n",
-+ urb->iso_frame_desc[i].offset,
-+ urb->iso_frame_desc[i].length);
-+ }
-+ }
-+}
-+#endif
-+
-+/** Starts processing a USB transfer request specified by a USB Request Block
-+ * (URB). mem_flags indicates the type of memory allocation to use while
-+ * processing this URB. */
-+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ struct usb_host_endpoint *ep,
-+#endif
-+ struct urb *urb, gfp_t mem_flags)
-+{
-+ int retval = 0;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
-+ struct usb_host_endpoint *ep = urb->ep;
-+#endif
-+ dwc_irqflags_t irqflags;
-+ void **ref_ep_hcpriv = &ep->hcpriv;
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ dwc_otg_hcd_urb_t *dwc_otg_urb;
-+ int i;
-+ int alloc_bandwidth = 0;
-+ uint8_t ep_type = 0;
-+ uint32_t flags = 0;
-+ void *buf;
-+
-+#ifdef DEBUG
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ dump_urb_info(urb, "dwc_otg_urb_enqueue");
-+ }
-+#endif
-+
-+ if (!urb->transfer_buffer && urb->transfer_buffer_length)
-+ return -EINVAL;
-+
-+ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
-+ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
-+ if (!dwc_otg_hcd_is_bandwidth_allocated
-+ (dwc_otg_hcd, ref_ep_hcpriv)) {
-+ alloc_bandwidth = 1;
-+ }
-+ }
-+
-+ switch (usb_pipetype(urb->pipe)) {
-+ case PIPE_CONTROL:
-+ ep_type = USB_ENDPOINT_XFER_CONTROL;
-+ break;
-+ case PIPE_ISOCHRONOUS:
-+ ep_type = USB_ENDPOINT_XFER_ISOC;
-+ break;
-+ case PIPE_BULK:
-+ ep_type = USB_ENDPOINT_XFER_BULK;
-+ break;
-+ case PIPE_INTERRUPT:
-+ ep_type = USB_ENDPOINT_XFER_INT;
-+ break;
-+ default:
-+ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
-+ }
-+
-+ /* # of packets is often 0 - do we really need to call this then? */
-+ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
-+ urb->number_of_packets,
-+ mem_flags == GFP_ATOMIC ? 1 : 0);
-+
-+ if(dwc_otg_urb == NULL)
-+ return -ENOMEM;
-+
-+ if (!dwc_otg_urb && urb->number_of_packets)
-+ return -ENOMEM;
-+
-+ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
-+ usb_pipeendpoint(urb->pipe), ep_type,
-+ usb_pipein(urb->pipe),
-+ usb_maxpacket(urb->dev, urb->pipe,
-+ !(usb_pipein(urb->pipe))));
-+
-+ buf = urb->transfer_buffer;
-+ if (hcd->self.uses_dma) {
-+ /*
-+ * Calculate virtual address from physical address,
-+ * because some class driver may not fill transfer_buffer.
-+ * In Buffer DMA mode virual address is used,
-+ * when handling non DWORD aligned buffers.
-+ */
-+ //buf = phys_to_virt(urb->transfer_dma);
-+ // DMA addresses are bus addresses not physical addresses!
-+ buf = dma_to_virt(&urb->dev->dev, urb->transfer_dma);
-+ }
-+
-+ if (!(urb->transfer_flags & URB_NO_INTERRUPT))
-+ flags |= URB_GIVEBACK_ASAP;
-+ if (urb->transfer_flags & URB_ZERO_PACKET)
-+ flags |= URB_SEND_ZERO_PACKET;
-+
-+ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
-+ urb->transfer_dma,
-+ urb->transfer_buffer_length,
-+ urb->setup_packet,
-+ urb->setup_dma, flags, urb->interval);
-+
-+ for (i = 0; i < urb->number_of_packets; ++i) {
-+ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
-+ urb->
-+ iso_frame_desc[i].offset,
-+ urb->
-+ iso_frame_desc[i].length);
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
-+ urb->hcpriv = dwc_otg_urb;
-+#if USB_URB_EP_LINKING
-+ retval = usb_hcd_link_urb_to_ep(hcd, urb);
-+ if (0 == retval)
-+#endif
-+ {
-+ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
-+ /*(dwc_otg_qh_t **)*/
-+ ref_ep_hcpriv, 1);
-+ if (0 == retval) {
-+ if (alloc_bandwidth) {
-+ allocate_bus_bandwidth(hcd,
-+ dwc_otg_hcd_get_ep_bandwidth(
-+ dwc_otg_hcd, *ref_ep_hcpriv),
-+ urb);
-+ }
-+ } else {
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
-+#if USB_URB_EP_LINKING
-+ usb_hcd_unlink_urb_from_ep(hcd, urb);
-+#endif
-+ DWC_FREE(dwc_otg_urb);
-+ urb->hcpriv = NULL;
-+ if (retval == -DWC_E_NO_DEVICE)
-+ retval = -ENODEV;
-+ }
-+ }
-+#if USB_URB_EP_LINKING
-+ else
-+ {
-+ DWC_FREE(dwc_otg_urb);
-+ urb->hcpriv = NULL;
-+ }
-+#endif
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
-+ return retval;
-+}
-+
-+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
-+ * success. */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
-+#else
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
-+#endif
-+{
-+ dwc_irqflags_t flags;
-+ dwc_otg_hcd_t *dwc_otg_hcd;
-+ int rc;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
-+
-+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+#ifdef DEBUG
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ dump_urb_info(urb, "dwc_otg_urb_dequeue");
-+ }
-+#endif
-+
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ rc = usb_hcd_check_unlink_urb(hcd, urb, status);
-+ if (0 == rc) {
-+ if(urb->hcpriv != NULL) {
-+ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
-+ (dwc_otg_hcd_urb_t *)urb->hcpriv);
-+
-+ DWC_FREE(urb->hcpriv);
-+ urb->hcpriv = NULL;
-+ }
-+ }
-+
-+ if (0 == rc) {
-+ /* Higher layer software sets URB status. */
-+#if USB_URB_EP_LINKING
-+ usb_hcd_unlink_urb_from_ep(hcd, urb);
-+#endif
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ usb_hcd_giveback_urb(hcd, urb);
-+#else
-+ usb_hcd_giveback_urb(hcd, urb, status);
-+#endif
-+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+ DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
-+ DWC_PRINTF(" 1urb->status = %d\n", urb->status);
-+ }
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
-+ } else {
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
-+ rc);
-+ }
-+
-+ return rc;
-+}
-+
-+/* Frees resources in the DWC_otg controller related to a given endpoint. Also
-+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
-+ * must already be dequeued. */
-+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+ DWC_DEBUGPL(DBG_HCD,
-+ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
-+ "endpoint=%d\n", ep->desc.bEndpointAddress,
-+ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
-+ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
-+ ep->hcpriv = NULL;
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+/* Resets endpoint specific parameter values, in current version used to reset
-+ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
-+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
-+{
-+ dwc_irqflags_t flags;
-+ struct usb_device *udev = NULL;
-+ int epnum = usb_endpoint_num(&ep->desc);
-+ int is_out = usb_endpoint_dir_out(&ep->desc);
-+ int is_control = usb_endpoint_xfer_control(&ep->desc);
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
-+
-+ if (dev)
-+ udev = to_usb_device(dev);
-+ else
-+ return;
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
-+
-+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+ usb_settoggle(udev, epnum, is_out, 0);
-+ if (is_control)
-+ usb_settoggle(udev, epnum, !is_out, 0);
-+
-+ if (ep->hcpriv) {
-+ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+}
-+#endif
-+
-+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
-+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
-+ * interrupt.
-+ *
-+ * This function is called by the USB core when an interrupt occurs */
-+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
-+ if (retval != 0) {
-+ S3C2410X_CLEAR_EINTPEND();
-+ }
-+ return IRQ_RETVAL(retval);
-+}
-+
-+/** Creates Status Change bitmap for the root hub and root port. The bitmap is
-+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
-+ * is the status change indicator for the single root port. Returns 1 if either
-+ * change indicator is 1, otherwise returns 0. */
-+int hub_status_data(struct usb_hcd *hcd, char *buf)
-+{
-+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+ buf[0] = 0;
-+ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
-+
-+ return (buf[0] != 0);
-+}
-+
-+/** Handles hub class-specific requests. */
-+int hub_control(struct usb_hcd *hcd,
-+ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
-+{
-+ int retval;
-+
-+ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
-+ typeReq, wValue, wIndex, buf, wLength);
-+
-+ switch (retval) {
-+ case -DWC_E_INVALID:
-+ retval = -EINVAL;
-+ break;
-+ }
-+
-+ return retval;
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,957 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
-+ * $Revision: #44 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the functions to manage Queue Heads and Queue
-+ * Transfer Descriptors.
-+ */
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+extern bool microframe_schedule;
-+
-+/**
-+ * Free each QTD in the QH's QTD-list then free the QH. QH should already be
-+ * removed from a list. QTD list should already be empty if called from URB
-+ * Dequeue.
-+ *
-+ * @param hcd HCD instance.
-+ * @param qh The QH to free.
-+ */
-+void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ dwc_otg_qtd_t *qtd, *qtd_tmp;
-+ dwc_irqflags_t flags;
-+
-+ /* Free each QTD in the QTD list */
-+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
-+ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
-+ dwc_otg_hcd_qtd_free(qtd);
-+ }
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ dwc_otg_hcd_qh_free_ddma(hcd, qh);
-+ } else if (qh->dw_align_buf) {
-+ uint32_t buf_size;
-+ if (qh->ep_type == UE_ISOCHRONOUS) {
-+ buf_size = 4096;
-+ } else {
-+ buf_size = hcd->core_if->core_params->max_transfer_size;
-+ }
-+ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
-+ }
-+
-+ DWC_FREE(qh);
-+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+ return;
-+}
-+
-+#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6)
-+#define HS_HOST_DELAY 5 /* nanoseconds */
-+#define FS_LS_HOST_DELAY 1000 /* nanoseconds */
-+#define HUB_LS_SETUP 333 /* nanoseconds */
-+#define NS_TO_US(ns) ((ns + 500) / 1000)
-+ /* convert & round nanoseconds to microseconds */
-+
-+static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
-+{
-+ unsigned long retval;
-+
-+ switch (speed) {
-+ case USB_SPEED_HIGH:
-+ if (is_isoc) {
-+ retval =
-+ ((38 * 8 * 2083) +
-+ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
-+ HS_HOST_DELAY;
-+ } else {
-+ retval =
-+ ((55 * 8 * 2083) +
-+ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
-+ HS_HOST_DELAY;
-+ }
-+ break;
-+ case USB_SPEED_FULL:
-+ if (is_isoc) {
-+ retval =
-+ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
-+ if (is_in) {
-+ retval = 7268 + FS_LS_HOST_DELAY + retval;
-+ } else {
-+ retval = 6265 + FS_LS_HOST_DELAY + retval;
-+ }
-+ } else {
-+ retval =
-+ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
-+ retval = 9107 + FS_LS_HOST_DELAY + retval;
-+ }
-+ break;
-+ case USB_SPEED_LOW:
-+ if (is_in) {
-+ retval =
-+ (67667 * (31 + 10 * BitStuffTime(bytecount))) /
-+ 1000;
-+ retval =
-+ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
-+ retval;
-+ } else {
-+ retval =
-+ (66700 * (31 + 10 * BitStuffTime(bytecount))) /
-+ 1000;
-+ retval =
-+ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
-+ retval;
-+ }
-+ break;
-+ default:
-+ DWC_WARN("Unknown device speed\n");
-+ retval = -1;
-+ }
-+
-+ return NS_TO_US(retval);
-+}
-+
-+/**
-+ * Initializes a QH structure.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ * @param urb Holds the information about the device/endpoint that we need
-+ * to initialize the QH.
-+ */
-+#define SCHEDULE_SLOP 10
-+void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
-+{
-+ char *speed, *type;
-+ int dev_speed;
-+ uint32_t hub_addr, hub_port;
-+
-+ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
-+
-+ /* Initialize QH */
-+ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
-+
-+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
-+ DWC_CIRCLEQ_INIT(&qh->qtd_list);
-+ DWC_LIST_INIT(&qh->qh_list_entry);
-+ qh->channel = NULL;
-+
-+ /* FS/LS Enpoint on HS Hub
-+ * NOT virtual root hub */
-+ dev_speed = hcd->fops->speed(hcd, urb->priv);
-+
-+ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
-+ qh->do_split = 0;
-+ if (microframe_schedule)
-+ qh->speed = dev_speed;
-+
-+ qh->nak_frame = 0xffff;
-+
-+ if (((dev_speed == USB_SPEED_LOW) ||
-+ (dev_speed == USB_SPEED_FULL)) &&
-+ (hub_addr != 0 && hub_addr != 1)) {
-+ DWC_DEBUGPL(DBG_HCD,
-+ "QH init: EP %d: TT found at hub addr %d, for port %d\n",
-+ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
-+ hub_port);
-+ qh->do_split = 1;
-+ qh->skip_count = 0;
-+ }
-+
-+ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
-+ /* Compute scheduling parameters once and save them. */
-+ hprt0_data_t hprt;
-+
-+ /** @todo Account for split transfers in the bus time. */
-+ int bytecount =
-+ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
-+
-+ qh->usecs =
-+ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
-+ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
-+ bytecount);
-+ /* Start in a slightly future (micro)frame. */
-+ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
-+ SCHEDULE_SLOP);
-+ qh->interval = urb->interval;
-+
-+#if 0
-+ /* Increase interrupt polling rate for debugging. */
-+ if (qh->ep_type == UE_INTERRUPT) {
-+ qh->interval = 8;
-+ }
-+#endif
-+ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
-+ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
-+ ((dev_speed == USB_SPEED_LOW) ||
-+ (dev_speed == USB_SPEED_FULL))) {
-+ qh->interval *= 8;
-+ qh->sched_frame |= 0x7;
-+ qh->start_split_frame = qh->sched_frame;
-+ }
-+
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
-+ dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
-+ dwc_otg_hcd_get_ep_num(&urb->pipe_info),
-+ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
-+ switch (dev_speed) {
-+ case USB_SPEED_LOW:
-+ qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
-+ speed = "low";
-+ break;
-+ case USB_SPEED_FULL:
-+ qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
-+ speed = "full";
-+ break;
-+ case USB_SPEED_HIGH:
-+ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
-+ speed = "high";
-+ break;
-+ default:
-+ speed = "?";
-+ break;
-+ }
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
-+
-+ switch (qh->ep_type) {
-+ case UE_ISOCHRONOUS:
-+ type = "isochronous";
-+ break;
-+ case UE_INTERRUPT:
-+ type = "interrupt";
-+ break;
-+ case UE_CONTROL:
-+ type = "control";
-+ break;
-+ case UE_BULK:
-+ type = "bulk";
-+ break;
-+ default:
-+ type = "?";
-+ break;
-+ }
-+
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
-+
-+#ifdef DEBUG
-+ if (qh->ep_type == UE_INTERRUPT) {
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
-+ qh->usecs);
-+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
-+ qh->interval);
-+ }
-+#endif
-+
-+}
-+
-+/**
-+ * This function allocates and initializes a QH.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param urb Holds the information about the device/endpoint that we need
-+ * to initialize the QH.
-+ * @param atomic_alloc Flag to do atomic allocation if needed
-+ *
-+ * @return Returns pointer to the newly allocated QH, or NULL on error. */
-+dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
-+ dwc_otg_hcd_urb_t * urb, int atomic_alloc)
-+{
-+ dwc_otg_qh_t *qh;
-+
-+ /* Allocate memory */
-+ /** @todo add memflags argument */
-+ qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
-+ if (qh == NULL) {
-+ DWC_ERROR("qh allocation failed");
-+ return NULL;
-+ }
-+
-+ qh_init(hcd, qh, urb);
-+
-+ if (hcd->core_if->dma_desc_enable
-+ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
-+ dwc_otg_hcd_qh_free(hcd, qh);
-+ return NULL;
-+ }
-+
-+ return qh;
-+}
-+
-+/* microframe_schedule=0 start */
-+
-+/**
-+ * Checks that a channel is available for a periodic transfer.
-+ *
-+ * @return 0 if successful, negative error code otherise.
-+ */
-+static int periodic_channel_available(dwc_otg_hcd_t * hcd)
-+{
-+ /*
-+ * Currently assuming that there is a dedicated host channnel for each
-+ * periodic transaction plus at least one host channel for
-+ * non-periodic transactions.
-+ */
-+ int status;
-+ int num_channels;
-+
-+ num_channels = hcd->core_if->core_params->host_channels;
-+ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
-+ && (hcd->periodic_channels < num_channels - 1)) {
-+ status = 0;
-+ } else {
-+ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
-+ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE
-+ status = -DWC_E_NO_SPACE;
-+ }
-+
-+ return status;
-+}
-+
-+/**
-+ * Checks that there is sufficient bandwidth for the specified QH in the
-+ * periodic schedule. For simplicity, this calculation assumes that all the
-+ * transfers in the periodic schedule may occur in the same (micro)frame.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH containing periodic bandwidth required.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status;
-+ int16_t max_claimed_usecs;
-+
-+ status = 0;
-+
-+ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
-+ /*
-+ * High speed mode.
-+ * Max periodic usecs is 80% x 125 usec = 100 usec.
-+ */
-+
-+ max_claimed_usecs = 100 - qh->usecs;
-+ } else {
-+ /*
-+ * Full speed mode.
-+ * Max periodic usecs is 90% x 1000 usec = 900 usec.
-+ */
-+ max_claimed_usecs = 900 - qh->usecs;
-+ }
-+
-+ if (hcd->periodic_usecs > max_claimed_usecs) {
-+ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE
-+ status = -DWC_E_NO_SPACE;
-+ }
-+
-+ return status;
-+}
-+
-+/* microframe_schedule=0 end */
-+
-+/**
-+ * Microframe scheduler
-+ * track the total use in hcd->frame_usecs
-+ * keep each qh use in qh->frame_usecs
-+ * when surrendering the qh then donate the time back
-+ */
-+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
-+
-+/*
-+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
-+ */
-+int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
-+{
-+ int i;
-+ for (i=0; i<8; i++) {
-+ _hcd->frame_usecs[i] = max_uframe_usecs[i];
-+ }
-+ return 0;
-+}
-+
-+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+ int i;
-+ unsigned short utime;
-+ int t_left;
-+ int ret;
-+ int done;
-+
-+ ret = -1;
-+ utime = _qh->usecs;
-+ t_left = utime;
-+ i = 0;
-+ done = 0;
-+ while (done == 0) {
-+ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
-+ if (utime <= _hcd->frame_usecs[i]) {
-+ _hcd->frame_usecs[i] -= utime;
-+ _qh->frame_usecs[i] += utime;
-+ t_left -= utime;
-+ ret = i;
-+ done = 1;
-+ return ret;
-+ } else {
-+ i++;
-+ if (i == 8) {
-+ done = 1;
-+ ret = -1;
-+ }
-+ }
-+ }
-+ return ret;
-+ }
-+
-+/*
-+ * use this for FS apps that can span multiple uframes
-+ */
-+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+ int i;
-+ int j;
-+ unsigned short utime;
-+ int t_left;
-+ int ret;
-+ int done;
-+ unsigned short xtime;
-+
-+ ret = -1;
-+ utime = _qh->usecs;
-+ t_left = utime;
-+ i = 0;
-+ done = 0;
-+loop:
-+ while (done == 0) {
-+ if(_hcd->frame_usecs[i] <= 0) {
-+ i++;
-+ if (i == 8) {
-+ done = 1;
-+ ret = -1;
-+ }
-+ goto loop;
-+ }
-+
-+ /*
-+ * we need n consecutive slots
-+ * so use j as a start slot j plus j+1 must be enough time (for now)
-+ */
-+ xtime= _hcd->frame_usecs[i];
-+ for (j = i+1 ; j < 8 ; j++ ) {
-+ /*
-+ * if we add this frame remaining time to xtime we may
-+ * be OK, if not we need to test j for a complete frame
-+ */
-+ if ((xtime+_hcd->frame_usecs[j]) < utime) {
-+ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
-+ j = 8;
-+ ret = -1;
-+ continue;
-+ }
-+ }
-+ if (xtime >= utime) {
-+ ret = i;
-+ j = 8; /* stop loop with a good value ret */
-+ continue;
-+ }
-+ /* add the frame time to x time */
-+ xtime += _hcd->frame_usecs[j];
-+ /* we must have a fully available next frame or break */
-+ if ((xtime < utime)
-+ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
-+ ret = -1;
-+ j = 8; /* stop loop with a bad value ret */
-+ continue;
-+ }
-+ }
-+ if (ret >= 0) {
-+ t_left = utime;
-+ for (j = i; (t_left>0) && (j < 8); j++ ) {
-+ t_left -= _hcd->frame_usecs[j];
-+ if ( t_left <= 0 ) {
-+ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
-+ _hcd->frame_usecs[j]= -t_left;
-+ ret = i;
-+ done = 1;
-+ } else {
-+ _qh->frame_usecs[j] += _hcd->frame_usecs[j];
-+ _hcd->frame_usecs[j] = 0;
-+ }
-+ }
-+ } else {
-+ i++;
-+ if (i == 8) {
-+ done = 1;
-+ ret = -1;
-+ }
-+ }
-+ }
-+ return ret;
-+}
-+
-+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+ int ret;
-+ ret = -1;
-+
-+ if (_qh->speed == USB_SPEED_HIGH) {
-+ /* if this is a hs transaction we need a full frame */
-+ ret = find_single_uframe(_hcd, _qh);
-+ } else {
-+ /* if this is a fs transaction we may need a sequence of frames */
-+ ret = find_multi_uframe(_hcd, _qh);
-+ }
-+ return ret;
-+}
-+
-+/**
-+ * Checks that the max transfer size allowed in a host channel is large enough
-+ * to handle the maximum data transfer in a single (micro)frame for a periodic
-+ * transfer.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for a periodic endpoint.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status;
-+ uint32_t max_xfer_size;
-+ uint32_t max_channel_xfer_size;
-+
-+ status = 0;
-+
-+ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
-+ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
-+
-+ if (max_xfer_size > max_channel_xfer_size) {
-+ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
-+ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE
-+ status = -DWC_E_NO_SPACE;
-+ }
-+
-+ return status;
-+}
-+
-+
-+
-+/**
-+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for the periodic transfer. The QH should already contain the
-+ * scheduling information.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status = 0;
-+
-+ if (microframe_schedule) {
-+ int frame;
-+ status = find_uframe(hcd, qh);
-+ frame = -1;
-+ if (status == 0) {
-+ frame = 7;
-+ } else {
-+ if (status > 0 )
-+ frame = status-1;
-+ }
-+
-+ /* Set the new frame up */
-+ if (frame > -1) {
-+ qh->sched_frame &= ~0x7;
-+ qh->sched_frame |= (frame & 7);
-+ }
-+
-+ if (status != -1)
-+ status = 0;
-+ } else {
-+ status = periodic_channel_available(hcd);
-+ if (status) {
-+ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE
-+ return status;
-+ }
-+
-+ status = check_periodic_bandwidth(hcd, qh);
-+ }
-+ if (status) {
-+ DWC_INFO("%s: Insufficient periodic bandwidth for "
-+ "periodic transfer.\n", __func__);
-+ return status;
-+ }
-+ status = check_max_xfer_size(hcd, qh);
-+ if (status) {
-+ DWC_INFO("%s: Channel max transfer size too small "
-+ "for periodic transfer.\n", __func__);
-+ return status;
-+ }
-+
-+ if (hcd->core_if->dma_desc_enable) {
-+ /* Don't rely on SOF and start in ready schedule */
-+ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
-+ }
-+ else {
-+ if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
-+ {
-+ hcd->fiq_state->next_sched_frame = qh->sched_frame;
-+
-+ }
-+ /* Always start in the inactive schedule. */
-+ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
-+ }
-+
-+ if (!microframe_schedule) {
-+ /* Reserve the periodic channel. */
-+ hcd->periodic_channels++;
-+ }
-+
-+ /* Update claimed usecs per (micro)frame. */
-+ hcd->periodic_usecs += qh->usecs;
-+
-+ return status;
-+}
-+
-+
-+/**
-+ * This function adds a QH to either the non periodic or periodic schedule if
-+ * it is not already in the schedule. If the QH is already in the schedule, no
-+ * action is taken.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int status = 0;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ /* QH already in a schedule. */
-+ return status;
-+ }
-+
-+ /* Add the new QH to the appropriate schedule */
-+ if (dwc_qh_is_non_per(qh)) {
-+ /* Always start in the inactive schedule. */
-+ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
-+ &qh->qh_list_entry);
-+ //hcd->fiq_state->kick_np_queues = 1;
-+ } else {
-+ status = schedule_periodic(hcd, qh);
-+ if ( !hcd->periodic_qh_count ) {
-+ intr_mask.b.sofintr = 1;
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ } else {
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+ }
-+ }
-+ hcd->periodic_qh_count++;
-+ }
-+
-+ return status;
-+}
-+
-+/**
-+ * Removes an interrupt or isochronous transfer from the periodic schedule.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for the periodic transfer.
-+ */
-+static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ int i;
-+ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
-+
-+ /* Update claimed usecs per (micro)frame. */
-+ hcd->periodic_usecs -= qh->usecs;
-+
-+ if (!microframe_schedule) {
-+ /* Release the periodic channel reservation. */
-+ hcd->periodic_channels--;
-+ } else {
-+ for (i = 0; i < 8; i++) {
-+ hcd->frame_usecs[i] += qh->frame_usecs[i];
-+ qh->frame_usecs[i] = 0;
-+ }
-+ }
-+}
-+
-+/**
-+ * Removes a QH from either the non-periodic or periodic schedule. Memory is
-+ * not freed.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param qh QH to remove from schedule. */
-+void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+ /* QH is not in a schedule. */
-+ return;
-+ }
-+
-+ if (dwc_qh_is_non_per(qh)) {
-+ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
-+ hcd->non_periodic_qh_ptr =
-+ hcd->non_periodic_qh_ptr->next;
-+ }
-+ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
-+ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
-+ // hcd->fiq_state->kick_np_queues = 1;
-+ } else {
-+ deschedule_periodic(hcd, qh);
-+ hcd->periodic_qh_count--;
-+ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
-+ intr_mask.b.sofintr = 1;
-+ if (fiq_enable) {
-+ local_fiq_disable();
-+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+ local_fiq_enable();
-+ } else {
-+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
-+ * non-periodic schedule. The QH is added to the inactive non-periodic
-+ * schedule if any QTDs are still attached to the QH.
-+ *
-+ * For periodic QHs, the QH is removed from the periodic queued schedule. If
-+ * there are any QTDs still attached to the QH, the QH is added to either the
-+ * periodic inactive schedule or the periodic ready schedule and its next
-+ * scheduled frame is calculated. The QH is placed in the ready schedule if
-+ * the scheduled frame has been reached already. Otherwise it's placed in the
-+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
-+ * completely removed from the periodic schedule.
-+ */
-+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+ int sched_next_periodic_split)
-+{
-+ if (dwc_qh_is_non_per(qh)) {
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ /* Add back to inactive non-periodic schedule. */
-+ dwc_otg_hcd_qh_add(hcd, qh);
-+ //hcd->fiq_state->kick_np_queues = 1;
-+ }
-+ } else {
-+ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
-+
-+ if (qh->do_split) {
-+ /* Schedule the next continuing periodic split transfer */
-+ if (sched_next_periodic_split) {
-+
-+ qh->sched_frame = frame_number;
-+
-+ if (dwc_frame_num_le(frame_number,
-+ dwc_frame_num_inc
-+ (qh->start_split_frame,
-+ 1))) {
-+ /*
-+ * Allow one frame to elapse after start
-+ * split microframe before scheduling
-+ * complete split, but DONT if we are
-+ * doing the next start split in the
-+ * same frame for an ISOC out.
-+ */
-+ if ((qh->ep_type != UE_ISOCHRONOUS) ||
-+ (qh->ep_is_in != 0)) {
-+ qh->sched_frame =
-+ dwc_frame_num_inc(qh->sched_frame, 1);
-+ }
-+ }
-+ } else {
-+ qh->sched_frame =
-+ dwc_frame_num_inc(qh->start_split_frame,
-+ qh->interval);
-+ if (dwc_frame_num_le
-+ (qh->sched_frame, frame_number)) {
-+ qh->sched_frame = frame_number;
-+ }
-+ qh->sched_frame |= 0x7;
-+ qh->start_split_frame = qh->sched_frame;
-+ }
-+ } else {
-+ qh->sched_frame =
-+ dwc_frame_num_inc(qh->sched_frame, qh->interval);
-+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
-+ qh->sched_frame = frame_number;
-+ }
-+ }
-+
-+ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+ dwc_otg_hcd_qh_remove(hcd, qh);
-+ } else {
-+ /*
-+ * Remove from periodic_sched_queued and move to
-+ * appropriate queue.
-+ */
-+ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
-+ (!microframe_schedule && qh->sched_frame == frame_number)) {
-+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
-+ &qh->qh_list_entry);
-+ } else {
-+ if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
-+ {
-+ hcd->fiq_state->next_sched_frame = qh->sched_frame;
-+ }
-+
-+ DWC_LIST_MOVE_HEAD
-+ (&hcd->periodic_sched_inactive,
-+ &qh->qh_list_entry);
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * This function allocates and initializes a QTD.
-+ *
-+ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
-+ * pointing to each other so each pair should have a unique correlation.
-+ * @param atomic_alloc Flag to do atomic alloc if needed
-+ *
-+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
-+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
-+{
-+ dwc_otg_qtd_t *qtd;
-+
-+ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
-+ if (qtd == NULL) {
-+ return NULL;
-+ }
-+
-+ dwc_otg_hcd_qtd_init(qtd, urb);
-+ return qtd;
-+}
-+
-+/**
-+ * Initializes a QTD structure.
-+ *
-+ * @param qtd The QTD to initialize.
-+ * @param urb The URB to use for initialization. */
-+void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
-+{
-+ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
-+ qtd->urb = urb;
-+ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
-+ /*
-+ * The only time the QTD data toggle is used is on the data
-+ * phase of control transfers. This phase always starts with
-+ * DATA1.
-+ */
-+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
-+ qtd->control_phase = DWC_OTG_CONTROL_SETUP;
-+ }
-+
-+ /* start split */
-+ qtd->complete_split = 0;
-+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+ qtd->isoc_split_offset = 0;
-+ qtd->in_process = 0;
-+
-+ /* Store the qtd ptr in the urb to reference what QTD. */
-+ urb->qtd = qtd;
-+ return;
-+}
-+
-+/**
-+ * This function adds a QTD to the QTD-list of a QH. It will find the correct
-+ * QH to place the QTD into. If it does not find a QH, then it will create a
-+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
-+ * is placed into the proper schedule based on its EP type.
-+ * HCD lock must be held and interrupts must be disabled on entry
-+ *
-+ * @param[in] qtd The QTD to add
-+ * @param[in] hcd The DWC HCD structure
-+ * @param[out] qh out parameter to return queue head
-+ * @param atomic_alloc Flag to do atomic alloc if needed
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
-+ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
-+{
-+ int retval = 0;
-+ dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+ /*
-+ * Get the QH which holds the QTD-list to insert to. Create QH if it
-+ * doesn't exist.
-+ */
-+ if (*qh == NULL) {
-+ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
-+ if (*qh == NULL) {
-+ retval = -DWC_E_NO_MEMORY;
-+ goto done;
-+ } else {
-+ if (fiq_enable)
-+ hcd->fiq_state->kick_np_queues = 1;
-+ }
-+ }
-+ retval = dwc_otg_hcd_qh_add(hcd, *qh);
-+ if (retval == 0) {
-+ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
-+ qtd_list_entry);
-+ qtd->qh = *qh;
-+ }
-+done:
-+
-+ return retval;
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,188 @@
-+#ifndef _DWC_OS_DEP_H_
-+#define _DWC_OS_DEP_H_
-+
-+/**
-+ * @file
-+ *
-+ * This file contains OS dependent structures.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/slab.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/ctype.h>
-+#include <linux/string.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/jiffies.h>
-+#include <linux/delay.h>
-+#include <linux/timer.h>
-+#include <linux/workqueue.h>
-+#include <linux/stat.h>
-+#include <linux/pci.h>
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+# include <linux/irq.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+# include <linux/usb/gadget.h>
-+#else
-+# include <linux/usb_gadget.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+# include <asm/irq.h>
-+#endif
-+
-+#ifdef PCI_INTERFACE
-+# include <asm/io.h>
-+#endif
-+
-+#ifdef LM_INTERFACE
-+# include <asm/unaligned.h>
-+# include <asm/sizes.h>
-+# include <asm/param.h>
-+# include <asm/io.h>
-+# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
-+# include <asm/arch/hardware.h>
-+# include <asm/arch/lm.h>
-+# include <asm/arch/irqs.h>
-+# include <asm/arch/regs-irq.h>
-+# else
-+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
-+ here we assume that the machine architecture provides definitions
-+ in its own header
-+*/
-+# include <mach/lm.h>
-+# include <mach/hardware.h>
-+# endif
-+#endif
-+
-+#ifdef PLATFORM_INTERFACE
-+#include <linux/platform_device.h>
-+#include <asm/mach/map.h>
-+#endif
-+
-+/** The OS page size */
-+#define DWC_OS_PAGE_SIZE PAGE_SIZE
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
-+typedef int gfp_t;
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
-+# define IRQF_SHARED SA_SHIRQ
-+#endif
-+
-+typedef struct os_dependent {
-+ /** Base address returned from ioremap() */
-+ void *base;
-+
-+ /** Register offset for Diagnostic API */
-+ uint32_t reg_offset;
-+
-+ /** Base address for MPHI peripheral */
-+ void *mphi_base;
-+
-+#ifdef LM_INTERFACE
-+ struct lm_device *lmdev;
-+#elif defined(PCI_INTERFACE)
-+ struct pci_dev *pcidev;
-+
-+ /** Start address of a PCI region */
-+ resource_size_t rsrc_start;
-+
-+ /** Length address of a PCI region */
-+ resource_size_t rsrc_len;
-+#elif defined(PLATFORM_INTERFACE)
-+ struct platform_device *platformdev;
-+#endif
-+
-+} os_dependent_t;
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+
-+
-+/* Type for the our device on the chosen bus */
-+#if defined(LM_INTERFACE)
-+typedef struct lm_device dwc_bus_dev_t;
-+#elif defined(PCI_INTERFACE)
-+typedef struct pci_dev dwc_bus_dev_t;
-+#elif defined(PLATFORM_INTERFACE)
-+typedef struct platform_device dwc_bus_dev_t;
-+#endif
-+
-+/* Helper macro to retrieve drvdata from the device on the chosen bus */
-+#if defined(LM_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
-+#endif
-+
-+/**
-+ * Helper macro returning the otg_device structure of a given struct device
-+ *
-+ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+ struct lm_device *lm_dev = \
-+ container_of(_dev, struct lm_device, dev); \
-+ _var = lm_get_drvdata(lm_dev); \
-+ } while (0)
-+
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+ _var = dev_get_drvdata(_dev); \
-+ } while (0)
-+
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+ struct platform_device *platform_dev = \
-+ container_of(_dev, struct platform_device, dev); \
-+ _var = platform_get_drvdata(platform_dev); \
-+ } while (0)
-+#endif
-+
-+
-+/**
-+ * Helper macro returning the struct dev of the given struct os_dependent
-+ *
-+ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
-+#endif
-+
-+
-+
-+
-+#endif /* _DWC_OS_DEP_H_ */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,2712 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
-+ * $Revision: #101 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+/** @file
-+ * This file implements PCD Core. All code in this file is portable and doesn't
-+ * use any OS specific functions.
-+ * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
-+ * header file, which can be used to implement OS specific PCD interface.
-+ *
-+ * An important function of the PCD is managing interrupts generated
-+ * by the DWC_otg controller. The implementation of the DWC_otg device
-+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
-+ *
-+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
-+ * @todo Does it work when the request size is greater than DEPTSIZ
-+ * transfer size
-+ *
-+ */
-+
-+#include "dwc_otg_pcd.h"
-+
-+#ifdef DWC_UTE_CFI
-+#include "dwc_otg_cfi.h"
-+
-+extern int init_cfi(cfiobject_t * cfiobj);
-+#endif
-+
-+/**
-+ * Choose endpoint from ep arrays using usb_ep structure.
-+ */
-+static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
-+{
-+ int i;
-+ if (pcd->ep0.priv == handle) {
-+ return &pcd->ep0;
-+ }
-+ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
-+ if (pcd->in_ep[i].priv == handle)
-+ return &pcd->in_ep[i];
-+ if (pcd->out_ep[i].priv == handle)
-+ return &pcd->out_ep[i];
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * This function completes a request. It call's the request call back.
-+ */
-+void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
-+ int32_t status)
-+{
-+ unsigned stopped = ep->stopped;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
-+ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
-+
-+ /* don't modify queue heads during completion callback */
-+ ep->stopped = 1;
-+ /* spin_unlock/spin_lock now done in fops->complete() */
-+ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
-+ req->actual);
-+
-+ if (ep->pcd->request_pending > 0) {
-+ --ep->pcd->request_pending;
-+ }
-+
-+ ep->stopped = stopped;
-+ DWC_FREE(req);
-+}
-+
-+/**
-+ * This function terminates all the requsts in the EP request queue.
-+ */
-+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_pcd_request_t *req;
-+
-+ ep->stopped = 1;
-+
-+ /* called with irqs blocked?? */
-+ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
-+ }
-+}
-+
-+void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
-+ const struct dwc_otg_pcd_function_ops *fops)
-+{
-+ pcd->fops = fops;
-+}
-+
-+/**
-+ * PCD Callback function for initializing the PCD when switching to
-+ * device mode.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_start_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ /*
-+ * Initialized the Core for Device mode.
-+ */
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dwc_otg_core_dev_init(core_if);
-+ /* Set core_if's lock pointer to the pcd->lock */
-+ core_if->lock = pcd->lock;
-+ }
-+ return 1;
-+}
-+
-+/** CFI-specific buffer allocation function for EP */
-+#ifdef DWC_UTE_CFI
-+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
-+ size_t buflen, int flags)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ ep = get_ep_from_handle(pcd, pep);
-+ if (!ep) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
-+ flags);
-+}
-+#else
-+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
-+ size_t buflen, int flags);
-+#endif
-+
-+/**
-+ * PCD Callback function for notifying the PCD when resuming from
-+ * suspend.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_resume_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+
-+ if (pcd->fops->resume) {
-+ pcd->fops->resume(pcd);
-+ }
-+
-+ /* Stop the SRP timeout timer. */
-+ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
-+ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
-+ if (GET_CORE_IF(pcd)->srp_timer_started) {
-+ GET_CORE_IF(pcd)->srp_timer_started = 0;
-+ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
-+ }
-+ }
-+ return 1;
-+}
-+
-+/**
-+ * PCD Callback function for notifying the PCD device is suspended.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_suspend_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+
-+ if (pcd->fops->suspend) {
-+ DWC_SPINUNLOCK(pcd->lock);
-+ pcd->fops->suspend(pcd);
-+ DWC_SPINLOCK(pcd->lock);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * PCD Callback function for stopping the PCD when switching to Host
-+ * mode.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_stop_cb(void *p)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
-+
-+ dwc_otg_pcd_stop(pcd);
-+ return 1;
-+}
-+
-+/**
-+ * PCD Callback structure for handling mode switching.
-+ */
-+static dwc_otg_cil_callbacks_t pcd_callbacks = {
-+ .start = dwc_otg_pcd_start_cb,
-+ .stop = dwc_otg_pcd_stop_cb,
-+ .suspend = dwc_otg_pcd_suspend_cb,
-+ .resume_wakeup = dwc_otg_pcd_resume_cb,
-+ .p = 0, /* Set at registration */
-+};
-+
-+/**
-+ * This function allocates a DMA Descriptor chain for the Endpoint
-+ * buffer to be used for a transfer to/from the specified endpoint.
-+ */
-+dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
-+ uint32_t count)
-+{
-+ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
-+ dma_desc_addr);
-+}
-+
-+/**
-+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
-+ */
-+void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
-+ uint32_t dma_desc_addr, uint32_t count)
-+{
-+ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
-+ dma_desc_addr);
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * dwc_ep)
-+{
-+
-+ dsts_data_t dsts = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+ int i, j;
-+ uint32_t len;
-+
-+ if (dwc_ep->is_in)
-+ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
-+ else
-+ dwc_ep->desc_cnt =
-+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+ dwc_ep->bInterval;
-+
-+ /** Allocate descriptors for double buffering */
-+ dwc_ep->iso_desc_addr =
-+ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
-+ dwc_ep->desc_cnt * 2);
-+ if (dwc_ep->desc_addr) {
-+ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
-+ return;
-+ }
-+
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ /** ISO OUT EP */
-+ if (dwc_ep->is_in == 0) {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
-+ dma_addr_t dma_ad;
-+ uint32_t data_per_desc;
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[dwc_ep->num];
-+ int offset;
-+
-+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
-+ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
-+
-+ /** Buffer 0 descriptors setup */
-+ dma_ad = dwc_ep->dma_addr0;
-+
-+ sts.b_iso_out.bs = BS_HOST_READY;
-+ sts.b_iso_out.rxsts = 0;
-+ sts.b_iso_out.l = 0;
-+ sts.b_iso_out.sp = 0;
-+ sts.b_iso_out.ioc = 0;
-+ sts.b_iso_out.pid = 0;
-+ sts.b_iso_out.framenum = 0;
-+
-+ offset = 0;
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+ }
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+ uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+
-+ sts.b_iso_out.ioc = 1;
-+ len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ dma_desc++;
-+
-+ /** Buffer 1 descriptors setup */
-+ sts.b_iso_out.ioc = 0;
-+ dma_ad = dwc_ep->dma_addr1;
-+
-+ offset = 0;
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+ if (len > dwc_ep->data_per_frame)
-+ data_per_desc =
-+ dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket;
-+ else
-+ data_per_desc = dwc_ep->maxpacket;
-+ len = data_per_desc % 4;
-+ if (len)
-+ data_per_desc += 4 - len;
-+
-+ data_per_desc =
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+ }
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+
-+ sts.b_iso_out.ioc = 1;
-+ sts.b_iso_out.l = 1;
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dwc_ep->next_frame = 0;
-+
-+ /** Write dma_ad into DOEPDMA register */
-+ DWC_WRITE_REG32(&(out_regs->doepdma),
-+ (uint32_t) dwc_ep->iso_dma_desc_addr);
-+
-+ }
-+ /** ISO IN EP */
-+ else {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
-+ dma_addr_t dma_ad;
-+ dwc_otg_dev_in_ep_regs_t *in_regs =
-+ core_if->dev_if->in_ep_regs[dwc_ep->num];
-+ unsigned int frmnumber;
-+ fifosize_data_t txfifosize, rxfifosize;
-+
-+ txfifosize.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
-+ dtxfsts);
-+ rxfifosize.d32 =
-+ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+
-+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+
-+ dma_ad = dwc_ep->dma_addr0;
-+
-+ dsts.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ sts.b_iso_in.bs = BS_HOST_READY;
-+ sts.b_iso_in.txsts = 0;
-+ sts.b_iso_in.sp =
-+ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
-+ sts.b_iso_in.ioc = 0;
-+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
-+
-+ frmnumber = dwc_ep->next_frame;
-+
-+ sts.b_iso_in.framenum = frmnumber;
-+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
-+ sts.b_iso_in.l = 0;
-+
-+ /** Buffer 0 descriptors setup */
-+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ dma_desc++;
-+
-+ dma_ad += dwc_ep->data_per_frame;
-+ sts.b_iso_in.framenum += dwc_ep->bInterval;
-+ }
-+
-+ sts.b_iso_in.ioc = 1;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ ++dma_desc;
-+
-+ /** Buffer 1 descriptors setup */
-+ sts.b_iso_in.ioc = 0;
-+ dma_ad = dwc_ep->dma_addr1;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ dma_desc++;
-+
-+ dma_ad += dwc_ep->data_per_frame;
-+ sts.b_iso_in.framenum += dwc_ep->bInterval;
-+
-+ sts.b_iso_in.ioc = 0;
-+ }
-+ sts.b_iso_in.ioc = 1;
-+ sts.b_iso_in.l = 1;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
-+
-+ /** Write dma_ad into diepdma register */
-+ DWC_WRITE_REG32(&(in_regs->diepdma),
-+ (uint32_t) dwc_ep->iso_dma_desc_addr);
-+ }
-+ /** Enable endpoint, clear nak */
-+ depctl.d32 = 0;
-+ depctl.b.epena = 1;
-+ depctl.b.usbactep = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+ depctl.d32 = DWC_READ_REG32(addr);
-+}
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if (ep->is_in) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
-+ return;
-+ } else {
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+
-+ ep->xfer_len =
-+ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
-+ ep->pkt_cnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+ ep->xfer_count = 0;
-+ ep->xfer_buff =
-+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
-+ ep->dma_addr =
-+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
-+
-+ if (ep->is_in) {
-+ /* Program the transfer size and packet count
-+ * as follows: xfersize = N * maxpacket +
-+ * short_packet pktcnt = N + (short_packet
-+ * exist ? 1 : 0)
-+ */
-+ deptsiz.b.mc = ep->pkt_per_frm;
-+ deptsiz.b.xfersize = ep->xfer_len;
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ dieptsiz, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->in_ep_regs[ep->num]->
-+ diepdma), (uint32_t) ep->dma_addr);
-+
-+ } else {
-+ deptsiz.b.pktcnt =
-+ (ep->xfer_len + (ep->maxpacket - 1)) /
-+ ep->maxpacket;
-+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
-+ doeptsiz, deptsiz.d32);
-+
-+ /* Write the DMA register */
-+ DWC_WRITE_REG32(&
-+ (core_if->dev_if->out_ep_regs[ep->num]->
-+ doepdma), (uint32_t) ep->dma_addr);
-+
-+ }
-+ /** Enable endpoint, clear nak */
-+ depctl.d32 = 0;
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+ }
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * ep)
-+{
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ if (ep->is_in) {
-+ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
-+ } else {
-+ ep->desc_cnt = ep->pkt_cnt;
-+ }
-+ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
-+ } else {
-+ if (core_if->pti_enh_enable) {
-+ dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
-+ } else {
-+ ep->cur_pkt_addr =
-+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
-+ xfer_buff0;
-+ ep->cur_pkt_dma_addr =
-+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->
-+ dma_addr0;
-+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
-+ }
-+ }
-+ } else {
-+ ep->cur_pkt_addr =
-+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
-+ ep->cur_pkt_dma_addr =
-+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
-+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
-+ }
-+}
-+
-+/**
-+ * This function stops transfer for an EP and
-+ * resets the ep's variables.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ depctl_data_t depctl = {.d32 = 0 };
-+ volatile uint32_t *addr;
-+
-+ if (ep->is_in == 1) {
-+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+ } else {
-+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+ }
-+
-+ /* disable the ep */
-+ depctl.d32 = DWC_READ_REG32(addr);
-+
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+
-+ DWC_WRITE_REG32(addr, depctl.d32);
-+
-+ if (core_if->dma_desc_enable &&
-+ ep->iso_desc_addr && ep->iso_dma_desc_addr) {
-+ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
-+ ep->iso_dma_desc_addr,
-+ ep->desc_cnt * 2);
-+ }
-+
-+ /* reset varibales */
-+ ep->dma_addr0 = 0;
-+ ep->dma_addr1 = 0;
-+ ep->xfer_buff0 = 0;
-+ ep->xfer_buff1 = 0;
-+ ep->data_per_frame = 0;
-+ ep->data_pattern_frame = 0;
-+ ep->sync_frame = 0;
-+ ep->buf_proc_intrvl = 0;
-+ ep->bInterval = 0;
-+ ep->proc_buf_num = 0;
-+ ep->pkt_per_frm = 0;
-+ ep->pkt_per_frm = 0;
-+ ep->desc_cnt = 0;
-+ ep->iso_desc_addr = 0;
-+ ep->iso_dma_desc_addr = 0;
-+}
-+
-+int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
-+ dwc_dma_t dma1, int sync_frame, int dp_frame,
-+ int data_per_frame, int start_frame,
-+ int buf_proc_intrvl, void *req_handle,
-+ int atomic_alloc)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags = 0;
-+ dwc_ep_t *dwc_ep;
-+ int32_t frm_data;
-+ dsts_data_t dsts;
-+ dwc_otg_core_if_t *core_if;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ core_if = GET_CORE_IF(pcd);
-+ dwc_ep = &ep->dwc_ep;
-+
-+ if (ep->iso_req_handle) {
-+ DWC_WARN("ISO request in progress\n");
-+ }
-+
-+ dwc_ep->dma_addr0 = dma0;
-+ dwc_ep->dma_addr1 = dma1;
-+
-+ dwc_ep->xfer_buff0 = buf0;
-+ dwc_ep->xfer_buff1 = buf1;
-+
-+ dwc_ep->data_per_frame = data_per_frame;
-+
-+ /** @todo - pattern data support is to be implemented in the future */
-+ dwc_ep->data_pattern_frame = dp_frame;
-+ dwc_ep->sync_frame = sync_frame;
-+
-+ dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
-+
-+ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
-+
-+ dwc_ep->proc_buf_num = 0;
-+
-+ dwc_ep->pkt_per_frm = 0;
-+ frm_data = ep->dwc_ep.data_per_frame;
-+ while (frm_data > 0) {
-+ dwc_ep->pkt_per_frm++;
-+ frm_data -= ep->dwc_ep.maxpacket;
-+ }
-+
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ if (start_frame == -1) {
-+ dwc_ep->next_frame = dsts.b.soffn + 1;
-+ if (dwc_ep->bInterval != 1) {
-+ dwc_ep->next_frame =
-+ dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
-+ dwc_ep->next_frame %
-+ dwc_ep->bInterval);
-+ }
-+ } else {
-+ dwc_ep->next_frame = start_frame;
-+ }
-+
-+ if (!core_if->pti_enh_enable) {
-+ dwc_ep->pkt_cnt =
-+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+ dwc_ep->bInterval;
-+ } else {
-+ dwc_ep->pkt_cnt =
-+ (dwc_ep->data_per_frame *
-+ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
-+ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
-+ }
-+
-+ if (core_if->dma_desc_enable) {
-+ dwc_ep->desc_cnt =
-+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+ dwc_ep->bInterval;
-+ }
-+
-+ if (atomic_alloc) {
-+ dwc_ep->pkt_info =
-+ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+ } else {
-+ dwc_ep->pkt_info =
-+ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+ }
-+ if (!dwc_ep->pkt_info) {
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ if (core_if->pti_enh_enable) {
-+ dwc_memset(dwc_ep->pkt_info, 0,
-+ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+ }
-+
-+ dwc_ep->cur_pkt = 0;
-+ ep->iso_req_handle = req_handle;
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
-+ return 0;
-+}
-+
-+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle)
-+{
-+ dwc_irqflags_t flags = 0;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+ dwc_ep = &ep->dwc_ep;
-+
-+ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
-+
-+ DWC_FREE(dwc_ep->pkt_info);
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ if (ep->iso_req_handle != req_handle) {
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ ep->iso_req_handle = 0;
-+ return 0;
-+}
-+
-+/**
-+ * This function is used for perodical data exchnage between PCD and gadget drivers.
-+ * for Isochronous EPs
-+ *
-+ * - Every time a sync period completes this function is called to
-+ * perform data exchange between PCD and gadget
-+ */
-+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
-+ void *req_handle)
-+{
-+ int i;
-+ dwc_ep_t *dwc_ep;
-+
-+ dwc_ep = &ep->dwc_ep;
-+
-+ DWC_SPINUNLOCK(ep->pcd->lock);
-+ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
-+ dwc_ep->proc_buf_num ^ 0x1);
-+ DWC_SPINLOCK(ep->pcd->lock);
-+
-+ for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
-+ dwc_ep->pkt_info[i].status = 0;
-+ dwc_ep->pkt_info[i].offset = 0;
-+ dwc_ep->pkt_info[i].length = 0;
-+ }
-+}
-+
-+int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *iso_req_handle)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep->desc || ep->dwc_ep.num == 0) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+ dwc_ep = &ep->dwc_ep;
-+
-+ return dwc_ep->pkt_cnt;
-+}
-+
-+void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *iso_req_handle, int packet,
-+ int *status, int *actual, int *offset)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep)
-+ DWC_WARN("bad ep\n");
-+
-+ dwc_ep = &ep->dwc_ep;
-+
-+ *status = dwc_ep->pkt_info[packet].status;
-+ *actual = dwc_ep->pkt_info[packet].length;
-+ *offset = dwc_ep->pkt_info[packet].offset;
-+}
-+
-+#endif /* DWC_EN_ISOC */
-+
-+static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
-+ uint32_t is_in, uint32_t ep_num)
-+{
-+ /* Init EP structure */
-+ pcd_ep->desc = 0;
-+ pcd_ep->pcd = pcd;
-+ pcd_ep->stopped = 1;
-+ pcd_ep->queue_sof = 0;
-+
-+ /* Init DWC ep structure */
-+ pcd_ep->dwc_ep.is_in = is_in;
-+ pcd_ep->dwc_ep.num = ep_num;
-+ pcd_ep->dwc_ep.active = 0;
-+ pcd_ep->dwc_ep.tx_fifo_num = 0;
-+ /* Control until ep is actvated */
-+ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
-+ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
-+ pcd_ep->dwc_ep.dma_addr = 0;
-+ pcd_ep->dwc_ep.start_xfer_buff = 0;
-+ pcd_ep->dwc_ep.xfer_buff = 0;
-+ pcd_ep->dwc_ep.xfer_len = 0;
-+ pcd_ep->dwc_ep.xfer_count = 0;
-+ pcd_ep->dwc_ep.sent_zlp = 0;
-+ pcd_ep->dwc_ep.total_len = 0;
-+ pcd_ep->dwc_ep.desc_addr = 0;
-+ pcd_ep->dwc_ep.dma_desc_addr = 0;
-+ DWC_CIRCLEQ_INIT(&pcd_ep->queue);
-+}
-+
-+/**
-+ * Initialize ep's
-+ */
-+static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
-+{
-+ int i;
-+ uint32_t hwcfg1;
-+ dwc_otg_pcd_ep_t *ep;
-+ int in_ep_cntr, out_ep_cntr;
-+ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
-+ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
-+
-+ /**
-+ * Initialize the EP0 structure.
-+ */
-+ ep = &pcd->ep0;
-+ dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
-+
-+ in_ep_cntr = 0;
-+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
-+ for (i = 1; in_ep_cntr < num_in_eps; i++) {
-+ if ((hwcfg1 & 0x1) == 0) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
-+ in_ep_cntr++;
-+ /**
-+ * @todo NGS: Add direction to EP, based on contents
-+ * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
-+ * sprintf(";r
-+ */
-+ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
-+
-+ DWC_CIRCLEQ_INIT(&ep->queue);
-+ }
-+ hwcfg1 >>= 2;
-+ }
-+
-+ out_ep_cntr = 0;
-+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
-+ for (i = 1; out_ep_cntr < num_out_eps; i++) {
-+ if ((hwcfg1 & 0x1) == 0) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
-+ out_ep_cntr++;
-+ /**
-+ * @todo NGS: Add direction to EP, based on contents
-+ * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
-+ * sprintf(";r
-+ */
-+ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
-+ DWC_CIRCLEQ_INIT(&ep->queue);
-+ }
-+ hwcfg1 >>= 2;
-+ }
-+
-+ pcd->ep0state = EP0_DISCONNECT;
-+ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
-+ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
-+}
-+
-+/**
-+ * This function is called when the SRP timer expires. The SRP should
-+ * complete within 6 seconds.
-+ */
-+static void srp_timeout(void *ptr)
-+{
-+ gotgctl_data_t gotgctl;
-+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
-+
-+ gotgctl.d32 = DWC_READ_REG32(addr);
-+
-+ core_if->srp_timer_started = 0;
-+
-+ if (core_if->adp_enable) {
-+ if (gotgctl.b.bsesvld == 0) {
-+ gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
-+ /* Power off the core */
-+ if (core_if->power_down == 2) {
-+ gpwrdn.b.pwrdnswtch = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+ }
-+
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuintsel = 1;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+ gpwrdn.d32);
-+ dwc_otg_adp_probe_start(core_if);
-+ } else {
-+ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+ }
-+ }
-+
-+ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
-+ (core_if->core_params->i2c_enable)) {
-+ DWC_PRINTF("SRP Timeout\n");
-+
-+ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
-+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+ }
-+
-+ /* Clear Session Request */
-+ gotgctl.d32 = 0;
-+ gotgctl.b.sesreq = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
-+ gotgctl.d32, 0);
-+
-+ core_if->srp_success = 0;
-+ } else {
-+ __DWC_ERROR("Device not connected/responding\n");
-+ gotgctl.b.sesreq = 0;
-+ DWC_WRITE_REG32(addr, gotgctl.d32);
-+ }
-+ } else if (gotgctl.b.sesreq) {
-+ DWC_PRINTF("SRP Timeout\n");
-+
-+ __DWC_ERROR("Device not connected/responding\n");
-+ gotgctl.b.sesreq = 0;
-+ DWC_WRITE_REG32(addr, gotgctl.d32);
-+ } else {
-+ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
-+ }
-+}
-+
-+/**
-+ * Tasklet
-+ *
-+ */
-+extern void start_next_request(dwc_otg_pcd_ep_t * ep);
-+
-+static void start_xfer_tasklet_func(void *data)
-+{
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ int i;
-+ depctl_data_t diepctl;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
-+
-+ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
-+
-+ if (pcd->ep0.queue_sof) {
-+ pcd->ep0.queue_sof = 0;
-+ start_next_request(&pcd->ep0);
-+ // break;
-+ }
-+
-+ for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
-+ depctl_data_t diepctl;
-+ diepctl.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
-+
-+ if (pcd->in_ep[i].queue_sof) {
-+ pcd->in_ep[i].queue_sof = 0;
-+ start_next_request(&pcd->in_ep[i]);
-+ // break;
-+ }
-+ }
-+
-+ return;
-+}
-+
-+/**
-+ * This function initialized the PCD portion of the driver.
-+ *
-+ */
-+dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_pcd_t *pcd = NULL;
-+ dwc_otg_dev_if_t *dev_if;
-+ int i;
-+
-+ /*
-+ * Allocate PCD structure
-+ */
-+ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
-+
-+ if (pcd == NULL) {
-+ return NULL;
-+ }
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);
-+#else
-+ pcd->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
-+ pcd, core_if);//GRAYG
-+ if (!pcd->lock) {
-+ DWC_ERROR("Could not allocate lock for pcd");
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+ /* Set core_if's lock pointer to hcd->lock */
-+ core_if->lock = pcd->lock;
-+ pcd->core_if = core_if;
-+
-+ dev_if = core_if->dev_if;
-+ dev_if->isoc_ep = NULL;
-+
-+ if (core_if->hwcfg4.b.ded_fifo_en) {
-+ DWC_PRINTF("Dedicated Tx FIFOs mode\n");
-+ } else {
-+ DWC_PRINTF("Shared Tx FIFO mode\n");
-+ }
-+
-+ /*
-+ * Initialized the Core for Device mode here if there is nod ADP support.
-+ * Otherwise it will be done later in dwc_otg_adp_start routine.
-+ */
-+ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
-+ dwc_otg_core_dev_init(core_if);
-+ }
-+
-+ /*
-+ * Register the PCD Callbacks.
-+ */
-+ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
-+
-+ /*
-+ * Initialize the DMA buffer for SETUP packets
-+ */
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ pcd->setup_pkt =
-+ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
-+ &pcd->setup_pkt_dma_handle);
-+ if (pcd->setup_pkt == NULL) {
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+
-+ pcd->status_buf =
-+ DWC_DMA_ALLOC(sizeof(uint16_t),
-+ &pcd->status_buf_dma_handle);
-+ if (pcd->status_buf == NULL) {
-+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
-+ pcd->setup_pkt, pcd->setup_pkt_dma_handle);
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dev_if->setup_desc_addr[0] =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_setup_desc_addr[0], 1);
-+ dev_if->setup_desc_addr[1] =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_setup_desc_addr[1], 1);
-+ dev_if->in_desc_addr =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_in_desc_addr, 1);
-+ dev_if->out_desc_addr =
-+ dwc_otg_ep_alloc_desc_chain
-+ (&dev_if->dma_out_desc_addr, 1);
-+ pcd->data_terminated = 0;
-+
-+ if (dev_if->setup_desc_addr[0] == 0
-+ || dev_if->setup_desc_addr[1] == 0
-+ || dev_if->in_desc_addr == 0
-+ || dev_if->out_desc_addr == 0) {
-+
-+ if (dev_if->out_desc_addr)
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->out_desc_addr,
-+ dev_if->dma_out_desc_addr, 1);
-+ if (dev_if->in_desc_addr)
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->in_desc_addr,
-+ dev_if->dma_in_desc_addr, 1);
-+ if (dev_if->setup_desc_addr[1])
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->setup_desc_addr[1],
-+ dev_if->dma_setup_desc_addr[1], 1);
-+ if (dev_if->setup_desc_addr[0])
-+ dwc_otg_ep_free_desc_chain
-+ (dev_if->setup_desc_addr[0],
-+ dev_if->dma_setup_desc_addr[0], 1);
-+
-+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
-+ pcd->setup_pkt,
-+ pcd->setup_pkt_dma_handle);
-+ DWC_DMA_FREE(sizeof(*pcd->status_buf),
-+ pcd->status_buf,
-+ pcd->status_buf_dma_handle);
-+
-+ DWC_FREE(pcd);
-+
-+ return NULL;
-+ }
-+ }
-+ } else {
-+ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
-+ if (pcd->setup_pkt == NULL) {
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+
-+ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
-+ if (pcd->status_buf == NULL) {
-+ DWC_FREE(pcd->setup_pkt);
-+ DWC_FREE(pcd);
-+ return NULL;
-+ }
-+ }
-+
-+ dwc_otg_pcd_reinit(pcd);
-+
-+ /* Allocate the cfi object for the PCD */
-+#ifdef DWC_UTE_CFI
-+ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
-+ if (NULL == pcd->cfi)
-+ goto fail;
-+ if (init_cfi(pcd->cfi)) {
-+ CFI_INFO("%s: Failed to init the CFI object\n", __func__);
-+ goto fail;
-+ }
-+#endif
-+
-+ /* Initialize tasklets */
-+ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
-+ start_xfer_tasklet_func, pcd);
-+ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
-+ do_test_mode, pcd);
-+
-+ /* Initialize SRP timer */
-+ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
-+
-+ if (core_if->core_params->dev_out_nak) {
-+ /**
-+ * Initialize xfer timeout timer. Implemented for
-+ * 2.93a feature "Device DDMA OUT NAK Enhancement"
-+ */
-+ for(i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ pcd->core_if->ep_xfer_timer[i] =
-+ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
-+ &pcd->core_if->ep_xfer_info[i]);
-+ }
-+ }
-+
-+ return pcd;
-+#ifdef DWC_UTE_CFI
-+fail:
-+#endif
-+ if (pcd->setup_pkt)
-+ DWC_FREE(pcd->setup_pkt);
-+ if (pcd->status_buf)
-+ DWC_FREE(pcd->status_buf);
-+#ifdef DWC_UTE_CFI
-+ if (pcd->cfi)
-+ DWC_FREE(pcd->cfi);
-+#endif
-+ if (pcd)
-+ DWC_FREE(pcd);
-+ return NULL;
-+
-+}
-+
-+/**
-+ * Remove PCD specific data
-+ */
-+void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ int i;
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
-+ pcd->core_if->ep_xfer_info[i].state = 0;
-+ }
-+ }
-+
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
-+ pcd->setup_pkt_dma_handle);
-+ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
-+ pcd->status_buf_dma_handle);
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
-+ dev_if->dma_setup_desc_addr
-+ [0], 1);
-+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
-+ dev_if->dma_setup_desc_addr
-+ [1], 1);
-+ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
-+ dev_if->dma_in_desc_addr, 1);
-+ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
-+ dev_if->dma_out_desc_addr,
-+ 1);
-+ }
-+ } else {
-+ DWC_FREE(pcd->setup_pkt);
-+ DWC_FREE(pcd->status_buf);
-+ }
-+ DWC_SPINLOCK_FREE(pcd->lock);
-+ /* Set core_if's lock pointer to NULL */
-+ pcd->core_if->lock = NULL;
-+
-+ DWC_TASK_FREE(pcd->start_xfer_tasklet);
-+ DWC_TASK_FREE(pcd->test_mode_tasklet);
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+ if (pcd->core_if->ep_xfer_timer[i]) {
-+ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
-+ }
-+ }
-+ }
-+
-+/* Release the CFI object's dynamic memory */
-+#ifdef DWC_UTE_CFI
-+ if (pcd->cfi->ops.release) {
-+ pcd->cfi->ops.release(pcd->cfi);
-+ }
-+#endif
-+
-+ DWC_FREE(pcd);
-+}
-+
-+/**
-+ * Returns whether registered pcd is dual speed or not
-+ */
-+uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
-+ ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+ (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+ (core_if->core_params->ulpi_fs_ls))) {
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Returns whether registered pcd is OTG capable or not
-+ */
-+uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ gusbcfg_data_t usbcfg = {.d32 = 0 };
-+
-+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function assigns periodic Tx FIFO to an periodic EP
-+ * in shared Tx FIFO mode
-+ */
-+static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t TxMsk = 1;
-+ int i;
-+
-+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
-+ if ((TxMsk & core_if->tx_msk) == 0) {
-+ core_if->tx_msk |= TxMsk;
-+ return i + 1;
-+ }
-+ TxMsk <<= 1;
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * This function assigns periodic Tx FIFO to an periodic EP
-+ * in shared Tx FIFO mode
-+ */
-+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+ uint32_t PerTxMsk = 1;
-+ int i;
-+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
-+ if ((PerTxMsk & core_if->p_tx_msk) == 0) {
-+ core_if->p_tx_msk |= PerTxMsk;
-+ return i + 1;
-+ }
-+ PerTxMsk <<= 1;
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * This function releases periodic Tx FIFO
-+ * in shared Tx FIFO mode
-+ */
-+static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
-+ uint32_t fifo_num)
-+{
-+ core_if->p_tx_msk =
-+ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
-+}
-+
-+/**
-+ * This function releases periodic Tx FIFO
-+ * in shared Tx FIFO mode
-+ */
-+static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
-+{
-+ core_if->tx_msk =
-+ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
-+}
-+
-+/**
-+ * This function is being called from gadget
-+ * to enable PCD endpoint.
-+ */
-+int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
-+ const uint8_t * ep_desc, void *usb_ep)
-+{
-+ int num, dir;
-+ dwc_otg_pcd_ep_t *ep = NULL;
-+ const usb_endpoint_descriptor_t *desc;
-+ dwc_irqflags_t flags;
-+ fifosize_data_t dptxfsiz = {.d32 = 0 };
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
-+ int retval = 0;
-+ int i, epcount;
-+
-+ desc = (const usb_endpoint_descriptor_t *)ep_desc;
-+
-+ if (!desc) {
-+ pcd->ep0.priv = usb_ep;
-+ ep = &pcd->ep0;
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ num = UE_GET_ADDR(desc->bEndpointAddress);
-+ dir = UE_GET_DIR(desc->bEndpointAddress);
-+
-+ if (!desc->wMaxPacketSize) {
-+ DWC_WARN("bad maxpacketsize\n");
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ if (dir == UE_DIR_IN) {
-+ epcount = pcd->core_if->dev_if->num_in_eps;
-+ for (i = 0; i < epcount; i++) {
-+ if (num == pcd->in_ep[i].dwc_ep.num) {
-+ ep = &pcd->in_ep[i];
-+ break;
-+ }
-+ }
-+ } else {
-+ epcount = pcd->core_if->dev_if->num_out_eps;
-+ for (i = 0; i < epcount; i++) {
-+ if (num == pcd->out_ep[i].dwc_ep.num) {
-+ ep = &pcd->out_ep[i];
-+ break;
-+ }
-+ }
-+ }
-+
-+ if (!ep) {
-+ DWC_WARN("bad address\n");
-+ retval = -DWC_E_INVALID;
-+ goto out;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ ep->desc = desc;
-+ ep->priv = usb_ep;
-+
-+ /*
-+ * Activate the EP
-+ */
-+ ep->stopped = 0;
-+
-+ ep->dwc_ep.is_in = (dir == UE_DIR_IN);
-+ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
-+
-+ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
-+
-+ if (ep->dwc_ep.is_in) {
-+ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ ep->dwc_ep.tx_fifo_num = 0;
-+
-+ if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
-+ /*
-+ * if ISOC EP then assign a Periodic Tx FIFO.
-+ */
-+ ep->dwc_ep.tx_fifo_num =
-+ assign_perio_tx_fifo(GET_CORE_IF(pcd));
-+ }
-+ } else {
-+ /*
-+ * if Dedicated FIFOs mode is on then assign a Tx FIFO.
-+ */
-+ ep->dwc_ep.tx_fifo_num =
-+ assign_tx_fifo(GET_CORE_IF(pcd));
-+ }
-+
-+ /* Calculating EP info controller base address */
-+ if (ep->dwc_ep.tx_fifo_num
-+ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ gdfifocfg.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+ core_global_regs->gdfifocfg);
-+ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
-+ dptxfsiz.d32 =
-+ (DWC_READ_REG32
-+ (&GET_CORE_IF(pcd)->core_global_regs->
-+ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
-+ gdfifocfg.b.epinfobase =
-+ gdfifocfgbase.d32 + dptxfsiz.d32;
-+ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
-+ core_global_regs->gdfifocfg,
-+ gdfifocfg.d32);
-+ }
-+ }
-+ }
-+ /* Set initial data PID. */
-+ if (ep->dwc_ep.type == UE_BULK) {
-+ ep->dwc_ep.data_pid_start = 0;
-+ }
-+
-+ /* Alloc DMA Descriptors */
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+#ifndef DWC_UTE_PER_IO
-+ if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
-+#endif
-+ ep->dwc_ep.desc_addr =
-+ dwc_otg_ep_alloc_desc_chain(&ep->
-+ dwc_ep.dma_desc_addr,
-+ MAX_DMA_DESC_CNT);
-+ if (!ep->dwc_ep.desc_addr) {
-+ DWC_WARN("%s, can't allocate DMA descriptor\n",
-+ __func__);
-+ retval = -DWC_E_SHUTDOWN;
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ goto out;
-+ }
-+#ifndef DWC_UTE_PER_IO
-+ }
-+#endif
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
-+#ifdef DWC_UTE_PER_IO
-+ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
-+#endif
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
-+ ep->dwc_ep.frame_num = 0xFFFFFFFF;
-+ }
-+
-+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+
-+#ifdef DWC_UTE_CFI
-+ if (pcd->cfi->ops.ep_enable) {
-+ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
-+ }
-+#endif
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+out:
-+ return retval;
-+}
-+
-+/**
-+ * This function is being called from gadget
-+ * to disable PCD endpoint.
-+ */
-+int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ dwc_otg_dev_dma_desc_t *desc_addr;
-+ dwc_dma_t dma_desc_addr;
-+ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
-+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+ fifosize_data_t dptxfsiz = {.d32 = 0 };
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if (!ep || !ep->desc) {
-+ DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ dwc_otg_request_nuke(ep);
-+
-+ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
-+ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
-+ }
-+ ep->desc = NULL;
-+ ep->stopped = 1;
-+
-+ gdfifocfg.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
-+ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
-+
-+ if (ep->dwc_ep.is_in) {
-+ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ /* Flush the Tx FIFO */
-+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
-+ ep->dwc_ep.tx_fifo_num);
-+ }
-+ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
-+ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
-+ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+ /* Decreasing EPinfo Base Addr */
-+ dptxfsiz.d32 =
-+ (DWC_READ_REG32
-+ (&GET_CORE_IF(pcd)->
-+ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
-+ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
-+ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
-+ gdfifocfg.d32);
-+ }
-+ }
-+ }
-+
-+ /* Free DMA Descriptors */
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
-+ desc_addr = ep->dwc_ep.desc_addr;
-+ dma_desc_addr = ep->dwc_ep.dma_desc_addr;
-+
-+ /* Cannot call dma_free_coherent() with IRQs disabled */
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
-+ MAX_DMA_DESC_CNT);
-+
-+ goto out_unlocked;
-+ }
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+out_unlocked:
-+ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT");
-+ return 0;
-+
-+}
-+
-+/******************************************************************************/
-+#ifdef DWC_UTE_PER_IO
-+
-+/**
-+ * Free the request and its extended parts
-+ *
-+ */
-+void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
-+{
-+ DWC_FREE(req->ext_req.per_io_frame_descs);
-+ DWC_FREE(req);
-+}
-+
-+/**
-+ * Start the next request in the endpoint's queue.
-+ *
-+ */
-+int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
-+ dwc_otg_pcd_ep_t * ep)
-+{
-+ int i;
-+ dwc_otg_pcd_request_t *req = NULL;
-+ dwc_ep_t *dwcep = NULL;
-+ struct dwc_iso_xreq_port *ereq = NULL;
-+ struct dwc_iso_pkt_desc_port *ddesc_iso;
-+ uint16_t nat;
-+ depctl_data_t diepctl;
-+
-+ dwcep = &ep->dwc_ep;
-+
-+ if (dwcep->xiso_active_xfers > 0) {
-+#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers
-+ DWC_WARN("There are currently active transfers for EP%d \
-+ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
-+ dwcep->xiso_queued_xfers);
-+#endif
-+ return 0;
-+ }
-+
-+ nat = UGETW(ep->desc->wMaxPacketSize);
-+ nat = (nat >> 11) & 0x03;
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ ereq = &req->ext_req;
-+ ep->stopped = 0;
-+
-+ /* Get the frame number */
-+ dwcep->xiso_frame_num =
-+ dwc_otg_get_frame_number(GET_CORE_IF(pcd));
-+ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
-+
-+ ddesc_iso = ereq->per_io_frame_descs;
-+
-+ if (dwcep->is_in) {
-+ /* Setup DMA Descriptor chain for IN Isoc request */
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ //if ((i % (nat + 1)) == 0)
-+ if ( i > 0 )
-+ dwcep->xiso_frame_num =
-+ (dwcep->xiso_bInterval +
-+ dwcep->xiso_frame_num) & 0x3FFF;
-+ dwcep->desc_addr[i].buf =
-+ req->dma + ddesc_iso[i].offset;
-+ dwcep->desc_addr[i].status.b_iso_in.txbytes =
-+ ddesc_iso[i].length;
-+ dwcep->desc_addr[i].status.b_iso_in.framenum =
-+ dwcep->xiso_frame_num;
-+ dwcep->desc_addr[i].status.b_iso_in.bs =
-+ BS_HOST_READY;
-+ dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
-+ dwcep->desc_addr[i].status.b_iso_in.sp =
-+ (ddesc_iso[i].length %
-+ dwcep->maxpacket) ? 1 : 0;
-+ dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
-+ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
-+ dwcep->desc_addr[i].status.b_iso_in.l = 0;
-+
-+ /* Process the last descriptor */
-+ if (i == ereq->pio_pkt_count - 1) {
-+ dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
-+ dwcep->desc_addr[i].status.b_iso_in.l = 1;
-+ }
-+ }
-+
-+ /* Setup and start the transfer for this endpoint */
-+ dwcep->xiso_active_xfers++;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ in_ep_regs[dwcep->num]->diepdma,
-+ dwcep->dma_desc_addr);
-+ diepctl.d32 = 0;
-+ diepctl.b.epena = 1;
-+ diepctl.b.cnak = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ in_ep_regs[dwcep->num]->diepctl, 0,
-+ diepctl.d32);
-+ } else {
-+ /* Setup DMA Descriptor chain for OUT Isoc request */
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ //if ((i % (nat + 1)) == 0)
-+ dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
-+ dwcep->xiso_frame_num) & 0x3FFF;
-+ dwcep->desc_addr[i].buf =
-+ req->dma + ddesc_iso[i].offset;
-+ dwcep->desc_addr[i].status.b_iso_out.rxbytes =
-+ ddesc_iso[i].length;
-+ dwcep->desc_addr[i].status.b_iso_out.framenum =
-+ dwcep->xiso_frame_num;
-+ dwcep->desc_addr[i].status.b_iso_out.bs =
-+ BS_HOST_READY;
-+ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
-+ dwcep->desc_addr[i].status.b_iso_out.sp =
-+ (ddesc_iso[i].length %
-+ dwcep->maxpacket) ? 1 : 0;
-+ dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
-+ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
-+ dwcep->desc_addr[i].status.b_iso_out.l = 0;
-+
-+ /* Process the last descriptor */
-+ if (i == ereq->pio_pkt_count - 1) {
-+ dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
-+ dwcep->desc_addr[i].status.b_iso_out.l = 1;
-+ }
-+ }
-+
-+ /* Setup and start the transfer for this endpoint */
-+ dwcep->xiso_active_xfers++;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->out_ep_regs[dwcep->num]->
-+ doepdma, dwcep->dma_desc_addr);
-+ diepctl.d32 = 0;
-+ diepctl.b.epena = 1;
-+ diepctl.b.cnak = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->out_ep_regs[dwcep->num]->
-+ doepctl, 0, diepctl.d32);
-+ }
-+
-+ } else {
-+ ep->stopped = 1;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * - Remove the request from the queue
-+ */
-+void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_pcd_request_t *req = NULL;
-+ struct dwc_iso_xreq_port *ereq = NULL;
-+ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
-+ dwc_ep_t *dwcep = NULL;
-+ int i;
-+
-+ //DWC_DEBUG();
-+ dwcep = &ep->dwc_ep;
-+
-+ /* Get the first pending request from the queue */
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (!req) {
-+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+ return;
-+ }
-+ dwcep->xiso_active_xfers--;
-+ dwcep->xiso_queued_xfers--;
-+ /* Remove this request from the queue */
-+ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
-+ } else {
-+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+ return;
-+ }
-+
-+ ep->stopped = 1;
-+ ereq = &req->ext_req;
-+ ddesc_iso = ereq->per_io_frame_descs;
-+
-+ if (dwcep->xiso_active_xfers < 0) {
-+ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
-+ dwcep->xiso_active_xfers);
-+ }
-+
-+ /* Fill the Isoc descs of portable extended req from dma descriptors */
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ if (dwcep->is_in) { /* IN endpoints */
-+ ddesc_iso[i].actual_length = ddesc_iso[i].length -
-+ dwcep->desc_addr[i].status.b_iso_in.txbytes;
-+ ddesc_iso[i].status =
-+ dwcep->desc_addr[i].status.b_iso_in.txsts;
-+ } else { /* OUT endpoints */
-+ ddesc_iso[i].actual_length = ddesc_iso[i].length -
-+ dwcep->desc_addr[i].status.b_iso_out.rxbytes;
-+ ddesc_iso[i].status =
-+ dwcep->desc_addr[i].status.b_iso_out.rxsts;
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK(ep->pcd->lock);
-+
-+ /* Call the completion function in the non-portable logic */
-+ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
-+ &req->ext_req);
-+
-+ DWC_SPINLOCK(ep->pcd->lock);
-+
-+ /* Free the request - specific freeing needed for extended request object */
-+ dwc_pcd_xiso_ereq_free(ep, req);
-+
-+ /* Start the next request */
-+ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
-+
-+ return;
-+}
-+
-+/**
-+ * Create and initialize the Isoc pkt descriptors of the extended request.
-+ *
-+ */
-+static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
-+ void *ereq_nonport,
-+ int atomic_alloc)
-+{
-+ struct dwc_iso_xreq_port *ereq = NULL;
-+ struct dwc_iso_xreq_port *req_mapped = NULL;
-+ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */
-+ uint32_t pkt_count;
-+ int i;
-+
-+ ereq = &req->ext_req;
-+ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
-+ pkt_count = req_mapped->pio_pkt_count;
-+
-+ /* Create the isoc descs */
-+ if (atomic_alloc) {
-+ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
-+ } else {
-+ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
-+ }
-+
-+ if (!ipds) {
-+ DWC_ERROR("Failed to allocate isoc descriptors");
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Initialize the extended request fields */
-+ ereq->per_io_frame_descs = ipds;
-+ ereq->error_count = 0;
-+ ereq->pio_alloc_pkt_count = pkt_count;
-+ ereq->pio_pkt_count = pkt_count;
-+ ereq->tr_sub_flags = req_mapped->tr_sub_flags;
-+
-+ /* Init the Isoc descriptors */
-+ for (i = 0; i < pkt_count; i++) {
-+ ipds[i].length = req_mapped->per_io_frame_descs[i].length;
-+ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
-+ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */
-+ ipds[i].actual_length =
-+ req_mapped->per_io_frame_descs[i].actual_length;
-+ }
-+
-+ return 0;
-+}
-+
-+static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
-+{
-+ struct dwc_iso_pkt_desc_port *xfd = NULL;
-+ int i;
-+
-+ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
-+ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
-+ DWC_DEBUG("error_count=%d", ereq->error_count);
-+ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
-+ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
-+ DWC_DEBUG("res=%d", ereq->res);
-+
-+ for (i = 0; i < ereq->pio_pkt_count; i++) {
-+ xfd = &ereq->per_io_frame_descs[0];
-+ DWC_DEBUG("FD #%d", i);
-+
-+ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
-+ DWC_DEBUG("xfd->length=%d", xfd->length);
-+ DWC_DEBUG("xfd->offset=%d", xfd->offset);
-+ DWC_DEBUG("xfd->status=%d", xfd->status);
-+ }
-+}
-+
-+/**
-+ *
-+ */
-+int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
-+ int zero, void *req_handle, int atomic_alloc,
-+ void *ereq_nonport)
-+{
-+ dwc_otg_pcd_request_t *req = NULL;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ int res;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ /* We support this extension only for DDMA mode */
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
-+ if (!GET_CORE_IF(pcd)->dma_desc_enable)
-+ return -DWC_E_INVALID;
-+
-+ /* Create a dwc_otg_pcd_request_t object */
-+ if (atomic_alloc) {
-+ req = DWC_ALLOC_ATOMIC(sizeof(*req));
-+ } else {
-+ req = DWC_ALLOC(sizeof(*req));
-+ }
-+
-+ if (!req) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+
-+ /* Create the Isoc descs for this request which shall be the exact match
-+ * of the structure sent to us from the non-portable logic */
-+ res =
-+ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
-+ if (res) {
-+ DWC_WARN("Failed to init the Isoc descriptors");
-+ DWC_FREE(req);
-+ return res;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
-+ req->buf = buf;
-+ req->dma = dma_buf;
-+ req->length = buflen;
-+ req->sent_zlp = zero;
-+ req->priv = req_handle;
-+
-+ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ ep->dwc_ep.dma_addr = dma_buf;
-+ ep->dwc_ep.start_xfer_buff = buf;
-+ ep->dwc_ep.xfer_buff = buf;
-+ ep->dwc_ep.xfer_len = 0;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = buflen;
-+
-+ /* Add this request to the tail */
-+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+ ep->dwc_ep.xiso_queued_xfers++;
-+
-+//DWC_DEBUG("CP_0");
-+//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
-+//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
-+//prn_ext_request(&req->ext_req);
-+
-+ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ /* If the req->status == ASAP then check if there is any active transfer
-+ * for this endpoint. If no active transfers, then get the first entry
-+ * from the queue and start that transfer
-+ */
-+ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
-+ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
-+ if (res) {
-+ DWC_WARN("Failed to start the next Isoc transfer");
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ DWC_FREE(req);
-+ return res;
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return 0;
-+}
-+
-+#endif
-+/* END ifdef DWC_UTE_PER_IO ***************************************************/
-+int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
-+ int zero, void *req_handle, int atomic_alloc)
-+{
-+ dwc_irqflags_t flags;
-+ dwc_otg_pcd_request_t *req;
-+ dwc_otg_pcd_ep_t *ep;
-+ uint32_t max_transfer;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
-+ DWC_WARN("bad ep\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (atomic_alloc) {
-+ req = DWC_ALLOC_ATOMIC(sizeof(*req));
-+ } else {
-+ req = DWC_ALLOC(sizeof(*req));
-+ }
-+
-+ if (!req) {
-+ return -DWC_E_NO_MEMORY;
-+ }
-+ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
-+ if (!GET_CORE_IF(pcd)->core_params->opt) {
-+ if (ep->dwc_ep.num != 0) {
-+ DWC_ERROR("queue req %p, len %d buf %p\n",
-+ req_handle, buflen, buf);
-+ }
-+ }
-+
-+ req->buf = buf;
-+ req->dma = dma_buf;
-+ req->length = buflen;
-+ req->sent_zlp = zero;
-+ req->priv = req_handle;
-+ req->dw_align_buf = NULL;
-+ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
-+ && !GET_CORE_IF(pcd)->dma_desc_enable)
-+ req->dw_align_buf = DWC_DMA_ALLOC(buflen,
-+ &req->dw_align_buf_dma);
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ /*
-+ * After adding request to the queue for IN ISOC wait for In Token Received
-+ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
-+ * Received when EP is disabled interrupt to obtain starting microframe
-+ * (odd/even) start transfer
-+ */
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (req != 0) {
-+ depctl_data_t depctl = {.d32 =
-+ DWC_READ_REG32(&pcd->core_if->dev_if->
-+ in_ep_regs[ep->dwc_ep.num]->
-+ diepctl) };
-+ ++pcd->request_pending;
-+
-+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+ if (ep->dwc_ep.is_in) {
-+ depctl.b.cnak = 1;
-+ DWC_WRITE_REG32(&pcd->core_if->dev_if->
-+ in_ep_regs[ep->dwc_ep.num]->
-+ diepctl, depctl.d32);
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ }
-+ return 0;
-+ }
-+
-+ /*
-+ * For EP0 IN without premature status, zlp is required?
-+ */
-+ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
-+ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
-+ //_req->zero = 1;
-+ }
-+
-+ /* Start the transfer */
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
-+ /* EP0 Transfer? */
-+ if (ep->dwc_ep.num == 0) {
-+ switch (pcd->ep0state) {
-+ case EP0_IN_DATA_PHASE:
-+ DWC_DEBUGPL(DBG_PCD,
-+ "%s ep0: EP0_IN_DATA_PHASE\n",
-+ __func__);
-+ break;
-+
-+ case EP0_OUT_DATA_PHASE:
-+ DWC_DEBUGPL(DBG_PCD,
-+ "%s ep0: EP0_OUT_DATA_PHASE\n",
-+ __func__);
-+ if (pcd->request_config) {
-+ /* Complete STATUS PHASE */
-+ ep->dwc_ep.is_in = 1;
-+ pcd->ep0state = EP0_IN_STATUS_PHASE;
-+ }
-+ break;
-+
-+ case EP0_IN_STATUS_PHASE:
-+ DWC_DEBUGPL(DBG_PCD,
-+ "%s ep0: EP0_IN_STATUS_PHASE\n",
-+ __func__);
-+ break;
-+
-+ default:
-+ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
-+ pcd->ep0state);
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_SHUTDOWN;
-+ }
-+
-+ ep->dwc_ep.dma_addr = dma_buf;
-+ ep->dwc_ep.start_xfer_buff = buf;
-+ ep->dwc_ep.xfer_buff = buf;
-+ ep->dwc_ep.xfer_len = buflen;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+ if (zero) {
-+ if ((ep->dwc_ep.xfer_len %
-+ ep->dwc_ep.maxpacket == 0)
-+ && (ep->dwc_ep.xfer_len != 0)) {
-+ ep->dwc_ep.sent_zlp = 1;
-+ }
-+
-+ }
-+
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ } // non-ep0 endpoints
-+ else {
-+#ifdef DWC_UTE_CFI
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ /* store the request length */
-+ ep->dwc_ep.cfi_req_len = buflen;
-+ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
-+ ep, req);
-+ } else {
-+#endif
-+ max_transfer =
-+ GET_CORE_IF(ep->pcd)->core_params->
-+ max_transfer_size;
-+
-+ /* Setup and start the Transfer */
-+ if (req->dw_align_buf){
-+ if (ep->dwc_ep.is_in)
-+ dwc_memcpy(req->dw_align_buf,
-+ buf, buflen);
-+ ep->dwc_ep.dma_addr =
-+ req->dw_align_buf_dma;
-+ ep->dwc_ep.start_xfer_buff =
-+ req->dw_align_buf;
-+ ep->dwc_ep.xfer_buff =
-+ req->dw_align_buf;
-+ } else {
-+ ep->dwc_ep.dma_addr = dma_buf;
-+ ep->dwc_ep.start_xfer_buff = buf;
-+ ep->dwc_ep.xfer_buff = buf;
-+ }
-+ ep->dwc_ep.xfer_len = 0;
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = buflen;
-+
-+ ep->dwc_ep.maxxfer = max_transfer;
-+ if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+ uint32_t out_max_xfer =
-+ DDMA_MAX_TRANSFER_SIZE -
-+ (DDMA_MAX_TRANSFER_SIZE % 4);
-+ if (ep->dwc_ep.is_in) {
-+ if (ep->dwc_ep.maxxfer >
-+ DDMA_MAX_TRANSFER_SIZE) {
-+ ep->dwc_ep.maxxfer =
-+ DDMA_MAX_TRANSFER_SIZE;
-+ }
-+ } else {
-+ if (ep->dwc_ep.maxxfer >
-+ out_max_xfer) {
-+ ep->dwc_ep.maxxfer =
-+ out_max_xfer;
-+ }
-+ }
-+ }
-+ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
-+ ep->dwc_ep.maxxfer -=
-+ (ep->dwc_ep.maxxfer %
-+ ep->dwc_ep.maxpacket);
-+ }
-+
-+ if (zero) {
-+ if ((ep->dwc_ep.total_len %
-+ ep->dwc_ep.maxpacket == 0)
-+ && (ep->dwc_ep.total_len != 0)) {
-+ ep->dwc_ep.sent_zlp = 1;
-+ }
-+ }
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ }
-+ }
-+
-+ if (req != 0) {
-+ ++pcd->request_pending;
-+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+ if (ep->dwc_ep.is_in && ep->stopped
-+ && !(GET_CORE_IF(pcd)->dma_enable)) {
-+ /** @todo NGS Create a function for this. */
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.intktxfemp = 1;
-+ if (GET_CORE_IF(pcd)->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->dev_global_regs->diepeachintmsk
-+ [ep->dwc_ep.num], 0,
-+ diepmsk.d32);
-+ } else {
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->dev_global_regs->
-+ diepmsk, 0, diepmsk.d32);
-+ }
-+
-+ }
-+ }
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return 0;
-+}
-+
-+int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle)
-+{
-+ dwc_irqflags_t flags;
-+ dwc_otg_pcd_request_t *req;
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
-+ DWC_WARN("bad argument\n");
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+ /* make sure it's actually queued on this endpoint */
-+ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
-+ if (req->priv == (void *)req_handle) {
-+ break;
-+ }
-+ }
-+
-+ if (req->priv != (void *)req_handle) {
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
-+ dwc_otg_request_done(ep, req, -DWC_E_RESTART);
-+ } else {
-+ req = NULL;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return req ? 0 : -DWC_E_SHUTDOWN;
-+
-+}
-+
-+/**
-+ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
-+ *
-+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
-+ * requests. If the gadget driver clears the halt status, it will
-+ * automatically unwedge the endpoint.
-+ *
-+ * Returns zero on success, else negative DWC error code.
-+ */
-+int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ int retval = 0;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if ((!ep->desc && ep != &pcd->ep0) ||
-+ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
-+ DWC_WARN("%s, bad ep\n", __func__);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT");
-+ retval = -DWC_E_AGAIN;
-+ } else {
-+ /* This code needs to be reviewed */
-+ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dtxfsts_data_t txstatus;
-+ fifosize_data_t txfifosize;
-+
-+ txfifosize.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+ core_global_regs->dtxfsiz[ep->dwc_ep.
-+ tx_fifo_num]);
-+ txstatus.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+ dev_if->in_ep_regs[ep->dwc_ep.num]->
-+ dtxfsts);
-+
-+ if (txstatus.b.txfspcavail < txfifosize.b.depth) {
-+ DWC_WARN("%s() Data In Tx Fifo\n", __func__);
-+ retval = -DWC_E_AGAIN;
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ }
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ }
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return retval;
-+}
-+
-+int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_irqflags_t flags;
-+ int retval = 0;
-+
-+ ep = get_ep_from_handle(pcd, ep_handle);
-+
-+ if (!ep || (!ep->desc && ep != &pcd->ep0) ||
-+ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
-+ DWC_WARN("%s, bad ep\n", __func__);
-+ return -DWC_E_INVALID;
-+ }
-+
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT");
-+ retval = -DWC_E_AGAIN;
-+ } else if (value == 0) {
-+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ } else if (value == 1) {
-+ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
-+ dtxfsts_data_t txstatus;
-+ fifosize_data_t txfifosize;
-+
-+ txfifosize.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
-+ dtxfsiz[ep->dwc_ep.tx_fifo_num]);
-+ txstatus.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ in_ep_regs[ep->dwc_ep.num]->dtxfsts);
-+
-+ if (txstatus.b.txfspcavail < txfifosize.b.depth) {
-+ DWC_WARN("%s() Data In Tx Fifo\n", __func__);
-+ retval = -DWC_E_AGAIN;
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
-+ &ep->dwc_ep);
-+ }
-+ } else {
-+ if (ep->dwc_ep.num == 0) {
-+ pcd->ep0state = EP0_STALL;
-+ }
-+
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ }
-+ } else if (value == 2) {
-+ ep->dwc_ep.stall_clear_flag = 0;
-+ } else if (value == 3) {
-+ ep->dwc_ep.stall_clear_flag = 1;
-+ }
-+
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function initiates remote wakeup of the host from suspend state.
-+ */
-+void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
-+{
-+ dctl_data_t dctl = { 0 };
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dsts_data_t dsts;
-+
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+ if (!dsts.b.suspsts) {
-+ DWC_WARN("Remote wakeup while is not in suspend state\n");
-+ }
-+ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
-+ if (pcd->remote_wakeup_enable) {
-+ if (set) {
-+
-+ if (core_if->adp_enable) {
-+ gpwrdn_data_t gpwrdn;
-+
-+ dwc_otg_adp_probe_stop(core_if);
-+
-+ /* Mask SRP detected interrupt from Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.srp_det_msk = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+
-+ /* Disable Power Down Logic */
-+ gpwrdn.d32 = 0;
-+ gpwrdn.b.pmuactv = 1;
-+ DWC_MODIFY_REG32(&core_if->
-+ core_global_regs->gpwrdn,
-+ gpwrdn.d32, 0);
-+
-+ /*
-+ * Initialize the Core for Device mode.
-+ */
-+ core_if->op_state = B_PERIPHERAL;
-+ dwc_otg_core_init(core_if);
-+ dwc_otg_enable_global_interrupts(core_if);
-+ cil_pcd_start(core_if);
-+
-+ dwc_otg_initiate_srp(core_if);
-+ }
-+
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, 0, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
-+
-+ dwc_mdelay(2);
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ dctl, dctl.d32, 0);
-+ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
-+ }
-+ } else {
-+ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
-+ }
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * This function initiates remote wakeup of the host from L1 sleep state.
-+ */
-+void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
-+{
-+ glpmcfg_data_t lpmcfg;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+
-+ /* Check if we are in L1 state */
-+ if (!lpmcfg.b.prt_sleep_sts) {
-+ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
-+ return;
-+ }
-+
-+ /* Check if host allows remote wakeup */
-+ if (!lpmcfg.b.rem_wkup_en) {
-+ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
-+ return;
-+ }
-+
-+ /* Check if Resume OK */
-+ if (!lpmcfg.b.sleep_state_resumeok) {
-+ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
-+ return;
-+ }
-+
-+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+ lpmcfg.b.en_utmi_sleep = 0;
-+ lpmcfg.b.hird_thres &= (~(1 << 4));
-+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+ if (set) {
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dctl.b.rmtwkupsig = 1;
-+ /* Set RmtWkUpSig bit to start remote wakup signaling.
-+ * Hardware will automatically clear this bit.
-+ */
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ 0, dctl.d32);
-+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
-+ }
-+
-+}
-+#endif
-+
-+/**
-+ * Performs remote wakeup.
-+ */
-+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_irqflags_t flags;
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ if (core_if->lx_state == DWC_OTG_L1) {
-+ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
-+ } else {
-+#endif
-+ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ }
-+#endif
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+ }
-+ return;
-+}
-+
-+void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dctl_data_t dctl = { 0 };
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ dctl.b.sftdiscon = 1;
-+ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+ dwc_udelay(no_of_usecs);
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
-+
-+ } else{
-+ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
-+ }
-+ return;
-+
-+}
-+
-+int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
-+{
-+ dsts_data_t dsts;
-+ gotgctl_data_t gotgctl;
-+
-+ /*
-+ * This function starts the Protocol if no session is in progress. If
-+ * a session is already in progress, but the device is suspended,
-+ * remote wakeup signaling is started.
-+ */
-+
-+ /* Check if valid session */
-+ gotgctl.d32 =
-+ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
-+ if (gotgctl.b.bsesvld) {
-+ /* Check if suspend state */
-+ dsts.d32 =
-+ DWC_READ_REG32(&
-+ (GET_CORE_IF(pcd)->dev_if->
-+ dev_global_regs->dsts));
-+ if (dsts.b.suspsts) {
-+ dwc_otg_pcd_remote_wakeup(pcd, 1);
-+ }
-+ } else {
-+ dwc_otg_pcd_initiate_srp(pcd);
-+ }
-+
-+ return 0;
-+
-+}
-+
-+/**
-+ * Start the SRP timer to detect when the SRP does not complete within
-+ * 6 seconds.
-+ *
-+ * @param pcd the pcd structure.
-+ */
-+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_irqflags_t flags;
-+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+ dwc_otg_initiate_srp(GET_CORE_IF(pcd));
-+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+}
-+
-+int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
-+{
-+ return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
-+}
-+
-+int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
-+{
-+ return GET_CORE_IF(pcd)->core_params->lpm_enable;
-+}
-+
-+uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->b_hnp_enable;
-+}
-+
-+uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->a_hnp_support;
-+}
-+
-+uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->a_alt_hnp_support;
-+}
-+
-+int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
-+{
-+ return pcd->remote_wakeup_enable;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,266 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
-+ * $Revision: #48 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+#if !defined(__DWC_PCD_H__)
-+#define __DWC_PCD_H__
-+
-+#include "dwc_otg_os_dep.h"
-+#include "usb.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_pcd_if.h"
-+struct cfiobject;
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the structures, constants, and interfaces for
-+ * the Perpherial Contoller Driver (PCD).
-+ *
-+ * The Peripheral Controller Driver (PCD) for Linux will implement the
-+ * Gadget API, so that the existing Gadget drivers can be used. For
-+ * the Mass Storage Function driver the File-backed USB Storage Gadget
-+ * (FBS) driver will be used. The FBS driver supports the
-+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
-+ * transports.
-+ *
-+ */
-+
-+/** Invalid DMA Address */
-+#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
-+
-+/** Max Transfer size for any EP */
-+#define DDMA_MAX_TRANSFER_SIZE 65535
-+
-+/**
-+ * Get the pointer to the core_if from the pcd pointer.
-+ */
-+#define GET_CORE_IF( _pcd ) (_pcd->core_if)
-+
-+/**
-+ * States of EP0.
-+ */
-+typedef enum ep0_state {
-+ EP0_DISCONNECT, /* no host */
-+ EP0_IDLE,
-+ EP0_IN_DATA_PHASE,
-+ EP0_OUT_DATA_PHASE,
-+ EP0_IN_STATUS_PHASE,
-+ EP0_OUT_STATUS_PHASE,
-+ EP0_STALL,
-+} ep0state_e;
-+
-+/** Fordward declaration.*/
-+struct dwc_otg_pcd;
-+
-+/** DWC_otg iso request structure.
-+ *
-+ */
-+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
-+
-+#ifdef DWC_UTE_PER_IO
-+
-+/**
-+ * This shall be the exact analogy of the same type structure defined in the
-+ * usb_gadget.h. Each descriptor contains
-+ */
-+struct dwc_iso_pkt_desc_port {
-+ uint32_t offset;
-+ uint32_t length; /* expected length */
-+ uint32_t actual_length;
-+ uint32_t status;
-+};
-+
-+struct dwc_iso_xreq_port {
-+ /** transfer/submission flag */
-+ uint32_t tr_sub_flags;
-+ /** Start the request ASAP */
-+#define DWC_EREQ_TF_ASAP 0x00000002
-+ /** Just enqueue the request w/o initiating a transfer */
-+#define DWC_EREQ_TF_ENQUEUE 0x00000004
-+
-+ /**
-+ * count of ISO packets attached to this request - shall
-+ * not exceed the pio_alloc_pkt_count
-+ */
-+ uint32_t pio_pkt_count;
-+ /** count of ISO packets allocated for this request */
-+ uint32_t pio_alloc_pkt_count;
-+ /** number of ISO packet errors */
-+ uint32_t error_count;
-+ /** reserved for future extension */
-+ uint32_t res;
-+ /** Will be allocated and freed in the UTE gadget and based on the CFC value */
-+ struct dwc_iso_pkt_desc_port *per_io_frame_descs;
-+};
-+#endif
-+/** DWC_otg request structure.
-+ * This structure is a list of requests.
-+ */
-+typedef struct dwc_otg_pcd_request {
-+ void *priv;
-+ void *buf;
-+ dwc_dma_t dma;
-+ uint32_t length;
-+ uint32_t actual;
-+ unsigned sent_zlp:1;
-+ /**
-+ * Used instead of original buffer if
-+ * it(physical address) is not dword-aligned.
-+ **/
-+ uint8_t *dw_align_buf;
-+ dwc_dma_t dw_align_buf_dma;
-+
-+ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
-+#ifdef DWC_UTE_PER_IO
-+ struct dwc_iso_xreq_port ext_req;
-+ //void *priv_ereq_nport; /* */
-+#endif
-+} dwc_otg_pcd_request_t;
-+
-+DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
-+
-+/** PCD EP structure.
-+ * This structure describes an EP, there is an array of EPs in the PCD
-+ * structure.
-+ */
-+typedef struct dwc_otg_pcd_ep {
-+ /** USB EP Descriptor */
-+ const usb_endpoint_descriptor_t *desc;
-+
-+ /** queue of dwc_otg_pcd_requests. */
-+ struct req_list queue;
-+ unsigned stopped:1;
-+ unsigned disabling:1;
-+ unsigned dma:1;
-+ unsigned queue_sof:1;
-+
-+#ifdef DWC_EN_ISOC
-+ /** ISOC req handle passed */
-+ void *iso_req_handle;
-+#endif //_EN_ISOC_
-+
-+ /** DWC_otg ep data. */
-+ dwc_ep_t dwc_ep;
-+
-+ /** Pointer to PCD */
-+ struct dwc_otg_pcd *pcd;
-+
-+ void *priv;
-+} dwc_otg_pcd_ep_t;
-+
-+/** DWC_otg PCD Structure.
-+ * This structure encapsulates the data for the dwc_otg PCD.
-+ */
-+struct dwc_otg_pcd {
-+ const struct dwc_otg_pcd_function_ops *fops;
-+ /** The DWC otg device pointer */
-+ struct dwc_otg_device *otg_dev;
-+ /** Core Interface */
-+ dwc_otg_core_if_t *core_if;
-+ /** State of EP0 */
-+ ep0state_e ep0state;
-+ /** EP0 Request is pending */
-+ unsigned ep0_pending:1;
-+ /** Indicates when SET CONFIGURATION Request is in process */
-+ unsigned request_config:1;
-+ /** The state of the Remote Wakeup Enable. */
-+ unsigned remote_wakeup_enable:1;
-+ /** The state of the B-Device HNP Enable. */
-+ unsigned b_hnp_enable:1;
-+ /** The state of A-Device HNP Support. */
-+ unsigned a_hnp_support:1;
-+ /** The state of the A-Device Alt HNP support. */
-+ unsigned a_alt_hnp_support:1;
-+ /** Count of pending Requests */
-+ unsigned request_pending;
-+
-+ /** SETUP packet for EP0
-+ * This structure is allocated as a DMA buffer on PCD initialization
-+ * with enough space for up to 3 setup packets.
-+ */
-+ union {
-+ usb_device_request_t req;
-+ uint32_t d32[2];
-+ } *setup_pkt;
-+
-+ dwc_dma_t setup_pkt_dma_handle;
-+
-+ /* Additional buffer and flag for CTRL_WR premature case */
-+ uint8_t *backup_buf;
-+ unsigned data_terminated;
-+
-+ /** 2-byte dma buffer used to return status from GET_STATUS */
-+ uint16_t *status_buf;
-+ dwc_dma_t status_buf_dma_handle;
-+
-+ /** EP0 */
-+ dwc_otg_pcd_ep_t ep0;
-+
-+ /** Array of IN EPs. */
-+ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
-+ /** Array of OUT EPs. */
-+ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
-+ /** number of valid EPs in the above array. */
-+// unsigned num_eps : 4;
-+ dwc_spinlock_t *lock;
-+
-+ /** Tasklet to defer starting of TEST mode transmissions until
-+ * Status Phase has been completed.
-+ */
-+ dwc_tasklet_t *test_mode_tasklet;
-+
-+ /** Tasklet to delay starting of xfer in DMA mode */
-+ dwc_tasklet_t *start_xfer_tasklet;
-+
-+ /** The test mode to enter when the tasklet is executed. */
-+ unsigned test_mode;
-+ /** The cfi_api structure that implements most of the CFI API
-+ * and OTG specific core configuration functionality
-+ */
-+#ifdef DWC_UTE_CFI
-+ struct cfiobject *cfi;
-+#endif
-+
-+};
-+
-+//FIXME this functions should be static, and this prototypes should be removed
-+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
-+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
-+ dwc_otg_pcd_request_t * req, int32_t status);
-+
-+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
-+ void *req_handle);
-+
-+extern void do_test_mode(void *data);
-+#endif
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,360 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
-+ * $Revision: #11 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+#if !defined(__DWC_PCD_IF_H__)
-+#define __DWC_PCD_IF_H__
-+
-+//#include "dwc_os.h"
-+#include "dwc_otg_core_if.h"
-+
-+/** @file
-+ * This file defines DWC_OTG PCD Core API.
-+ */
-+
-+struct dwc_otg_pcd;
-+typedef struct dwc_otg_pcd dwc_otg_pcd_t;
-+
-+/** Maxpacket size for EP0 */
-+#define MAX_EP0_SIZE 64
-+/** Maxpacket size for any EP */
-+#define MAX_PACKET_SIZE 1024
-+
-+/** @name Function Driver Callbacks */
-+/** @{ */
-+
-+/** This function will be called whenever a previously queued request has
-+ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
-+ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
-+ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
-+ * parameters. */
-+typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status,
-+ uint32_t actual);
-+/**
-+ * This function will be called whenever a previousle queued ISOC request has
-+ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
-+ * function.
-+ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
-+ * functions.
-+ */
-+typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int proc_buf_num);
-+/** This function should handle any SETUP request that cannot be handled by the
-+ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
-+ * class-specific requests, etc. The function must non-blocking.
-+ *
-+ * Returns 0 on success.
-+ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
-+ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
-+ * Returns -DWC_E_SHUTDOWN on any other error. */
-+typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
-+/** This is called whenever the device has been disconnected. The function
-+ * driver should take appropriate action to clean up all pending requests in the
-+ * PCD Core, remove all endpoints (except ep0), and initialize back to reset
-+ * state. */
-+typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has been connected. */
-+typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
-+/** This function is called when device has been suspended */
-+typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has received LPM tokens, i.e.
-+ * device has been sent to sleep state. */
-+typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has been resumed
-+ * from suspend(L2) or L1 sleep state. */
-+typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called whenever hnp params has been changed.
-+ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
-+ * to get hnp parameters. */
-+typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called whenever USB RESET is detected. */
-+typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
-+
-+typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
-+
-+/**
-+ *
-+ * @param ep_handle Void pointer to the usb_ep structure
-+ * @param ereq_port Pointer to the extended request structure created in the
-+ * portable part.
-+ */
-+typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status,
-+ void *ereq_port);
-+/** Function Driver Ops Data Structure */
-+struct dwc_otg_pcd_function_ops {
-+ dwc_connect_cb_t connect;
-+ dwc_disconnect_cb_t disconnect;
-+ dwc_setup_cb_t setup;
-+ dwc_completion_cb_t complete;
-+ dwc_isoc_completion_cb_t isoc_complete;
-+ dwc_suspend_cb_t suspend;
-+ dwc_sleep_cb_t sleep;
-+ dwc_resume_cb_t resume;
-+ dwc_reset_cb_t reset;
-+ dwc_hnp_params_changed_cb_t hnp_changed;
-+ cfi_setup_cb_t cfi_setup;
-+#ifdef DWC_UTE_PER_IO
-+ xiso_completion_cb_t xisoc_complete;
-+#endif
-+};
-+/** @} */
-+
-+/** @name Function Driver Functions */
-+/** @{ */
-+
-+/** Call this function to get pointer on dwc_otg_pcd_t,
-+ * this pointer will be used for all PCD API functions.
-+ *
-+ * @param core_if The DWC_OTG Core
-+ */
-+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
-+
-+/** Frees PCD allocated by dwc_otg_pcd_init
-+ *
-+ * @param pcd The PCD
-+ */
-+extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
-+
-+/** Call this to bind the function driver to the PCD Core.
-+ *
-+ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
-+ * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
-+ */
-+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
-+ const struct dwc_otg_pcd_function_ops *fops);
-+
-+/** Enables an endpoint for use. This function enables an endpoint in
-+ * the PCD. The endpoint is described by the ep_desc which has the
-+ * same format as a USB ep descriptor. The ep_handle parameter is used to refer
-+ * to the endpoint from other API functions and in callbacks. Normally this
-+ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
-+ * core for that interface.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_desc Endpoint descriptor
-+ * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
-+ */
-+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
-+ const uint8_t * ep_desc, void *usb_ep);
-+
-+/** Disable the endpoint referenced by ep_handle.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error occurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
-+
-+/** Queue a data transfer request on the endpoint referenced by ep_handle.
-+ * After the transfer is completes, the complete callback will be called with
-+ * the request status.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param buf The buffer for the data
-+ * @param dma_buf The DMA buffer for the data
-+ * @param buflen The length of the data transfer
-+ * @param zero Specifies whether to send zero length last packet.
-+ * @param req_handle Set this handle to any value to use to reference this
-+ * request in the ep_dequeue function or from the complete callback
-+ * @param atomic_alloc If driver need to perform atomic allocations
-+ * for internal data structures.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf,
-+ uint32_t buflen, int zero, void *req_handle,
-+ int atomic_alloc);
-+#ifdef DWC_UTE_PER_IO
-+/**
-+ *
-+ * @param ereq_nonport Pointer to the extended request part of the
-+ * usb_request structure defined in usb_gadget.h file.
-+ */
-+extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf, dwc_dma_t dma_buf,
-+ uint32_t buflen, int zero,
-+ void *req_handle, int atomic_alloc,
-+ void *ereq_nonport);
-+
-+#endif
-+
-+/** De-queue the specified data transfer that has not yet completed.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle);
-+
-+/** Halt (STALL) an endpoint or clear it.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
-+
-+/** This function */
-+extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
-+
-+/** This function should be called on every hardware interrupt */
-+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns current frame number */
-+extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
-+
-+/**
-+ * Start isochronous transfers on the endpoint referenced by ep_handle.
-+ * For isochronous transfers duble buffering is used.
-+ * After processing each of buffers comlete callback will be called with
-+ * status for each transaction.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param buf0 The virtual address of first data buffer
-+ * @param buf1 The virtual address of second data buffer
-+ * @param dma0 The DMA address of first data buffer
-+ * @param dma1 The DMA address of second data buffer
-+ * @param sync_frame Data pattern frame number
-+ * @param dp_frame Data size for pattern frame
-+ * @param data_per_frame Data size for regular frame
-+ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
-+ * @param buf_proc_intrvl Interval of ISOC Buffer processing
-+ * @param req_handle Handle of ISOC request
-+ * @param atomic_alloc Specefies whether to perform atomic allocation for
-+ * internal data structures.
-+ *
-+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
-+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
-+ * Returns -DW_E_SHUTDOWN for any other error.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ uint8_t * buf0, uint8_t * buf1,
-+ dwc_dma_t dma0, dwc_dma_t dma1,
-+ int sync_frame, int dp_frame,
-+ int data_per_frame, int start_frame,
-+ int buf_proc_intrvl, void *req_handle,
-+ int atomic_alloc);
-+
-+/** Stop ISOC transfers on endpoint referenced by ep_handle.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param req_handle Handle of ISOC request
-+ *
-+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
-+ * Returns 0 on success
-+ */
-+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle);
-+
-+/** Get ISOC packet status.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param iso_req_handle Isochronoush request handle
-+ * @param packet Number of packet
-+ * @param status Out parameter for returning status
-+ * @param actual Out parameter for returning actual length
-+ * @param offset Out parameter for returning offset
-+ *
-+ */
-+extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
-+ void *ep_handle,
-+ void *iso_req_handle, int packet,
-+ int *status, int *actual,
-+ int *offset);
-+
-+/** Get ISOC packet count.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param iso_req_handle
-+ */
-+extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
-+ void *ep_handle,
-+ void *iso_req_handle);
-+
-+/** This function starts the SRP Protocol if no session is in progress. If
-+ * a session is already in progress, but the device is suspended,
-+ * remote wakeup signaling is started.
-+ */
-+extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
-+extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
-+extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
-+
-+/** Initiate SRP */
-+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
-+
-+/** Starts remote wakeup signaling. */
-+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
-+
-+/** Starts micorsecond soft disconnect. */
-+extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
-+/** This function returns whether device is dualspeed.*/
-+extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns whether device is otg. */
-+extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
-+
-+/** These functions allow to get hnp parameters */
-+extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
-+extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
-+extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
-+
-+/** CFI specific Interface functions */
-+/** Allocate a cfi buffer */
-+extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
-+ dwc_dma_t * addr, size_t buflen,
-+ int flags);
-+
-+/******************************************************************************/
-+
-+/** @} */
-+
-+#endif /* __DWC_PCD_IF_H__ */
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,5147 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
-+ * $Revision: #116 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+#include "dwc_otg_pcd.h"
-+
-+#ifdef DWC_UTE_CFI
-+#include "dwc_otg_cfi.h"
-+#endif
-+
-+#ifdef DWC_UTE_PER_IO
-+extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
-+#endif
-+//#define PRINT_CFI_DMA_DESCS
-+
-+#define DEBUG_EP0
-+
-+/**
-+ * This function updates OTG.
-+ */
-+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
-+{
-+
-+ if (reset) {
-+ pcd->b_hnp_enable = 0;
-+ pcd->a_hnp_support = 0;
-+ pcd->a_alt_hnp_support = 0;
-+ }
-+
-+ if (pcd->fops->hnp_changed) {
-+ pcd->fops->hnp_changed(pcd);
-+ }
-+}
-+
-+/** @file
-+ * This file contains the implementation of the PCD Interrupt handlers.
-+ *
-+ * The PCD handles the device interrupts. Many conditions can cause a
-+ * device interrupt. When an interrupt occurs, the device interrupt
-+ * service routine determines the cause of the interrupt and
-+ * dispatches handling to the appropriate function. These interrupt
-+ * handling functions are described below.
-+ * All interrupt registers are processed from LSB to MSB.
-+ */
-+
-+/**
-+ * This function prints the ep0 state for debug purposes.
-+ */
-+static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
-+{
-+#ifdef DEBUG
-+ char str[40];
-+
-+ switch (pcd->ep0state) {
-+ case EP0_DISCONNECT:
-+ dwc_strcpy(str, "EP0_DISCONNECT");
-+ break;
-+ case EP0_IDLE:
-+ dwc_strcpy(str, "EP0_IDLE");
-+ break;
-+ case EP0_IN_DATA_PHASE:
-+ dwc_strcpy(str, "EP0_IN_DATA_PHASE");
-+ break;
-+ case EP0_OUT_DATA_PHASE:
-+ dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
-+ break;
-+ case EP0_IN_STATUS_PHASE:
-+ dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
-+ break;
-+ case EP0_OUT_STATUS_PHASE:
-+ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
-+ break;
-+ case EP0_STALL:
-+ dwc_strcpy(str, "EP0_STALL");
-+ break;
-+ default:
-+ dwc_strcpy(str, "EP0_INVALID");
-+ }
-+
-+ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
-+#endif
-+}
-+
-+/**
-+ * This function calculate the size of the payload in the memory
-+ * for out endpoints and prints size for debug purposes(used in
-+ * 2.93a DevOutNak feature).
-+ */
-+static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
-+{
-+#ifdef DEBUG
-+ deptsiz_data_t deptsiz_init = {.d32 = 0 };
-+ deptsiz_data_t deptsiz_updt = {.d32 = 0 };
-+ int pack_num;
-+ unsigned payload;
-+
-+ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
-+ deptsiz_updt.d32 =
-+ DWC_READ_REG32(&pcd->core_if->dev_if->
-+ out_ep_regs[ep->num]->doeptsiz);
-+ /* Payload will be */
-+ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
-+ /* Packet count is decremented every time a packet
-+ * is written to the RxFIFO not in to the external memory
-+ * So, if payload == 0, then it means no packet was sent to ext memory*/
-+ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Payload for EP%d-%s\n",
-+ ep->num, (ep->is_in ? "IN" : "OUT"));
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Number of transfered bytes = 0x%08x\n", payload);
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Number of transfered packets = %d\n", pack_num);
-+#endif
-+}
-+
-+
-+#ifdef DWC_UTE_CFI
-+static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
-+ const uint8_t * epname, int descnum)
-+{
-+ CFI_INFO
-+ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
-+ epname, descnum, ddesc->buf, ddesc->status.b.bytes,
-+ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
-+ ddesc->status.b.bs);
-+}
-+#endif
-+
-+/**
-+ * This function returns pointer to in ep struct with number ep_num
-+ */
-+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
-+{
-+ int i;
-+ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
-+ if (ep_num == 0) {
-+ return &pcd->ep0;
-+ } else {
-+ for (i = 0; i < num_in_eps; ++i) {
-+ if (pcd->in_ep[i].dwc_ep.num == ep_num)
-+ return &pcd->in_ep[i];
-+ }
-+ return 0;
-+ }
-+}
-+
-+/**
-+ * This function returns pointer to out ep struct with number ep_num
-+ */
-+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
-+{
-+ int i;
-+ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
-+ if (ep_num == 0) {
-+ return &pcd->ep0;
-+ } else {
-+ for (i = 0; i < num_out_eps; ++i) {
-+ if (pcd->out_ep[i].dwc_ep.num == ep_num)
-+ return &pcd->out_ep[i];
-+ }
-+ return 0;
-+ }
-+}
-+
-+/**
-+ * This functions gets a pointer to an EP from the wIndex address
-+ * value of the control request.
-+ */
-+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
-+{
-+ dwc_otg_pcd_ep_t *ep;
-+ uint32_t ep_num = UE_GET_ADDR(wIndex);
-+
-+ if (ep_num == 0) {
-+ ep = &pcd->ep0;
-+ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */
-+ ep = &pcd->in_ep[ep_num - 1];
-+ } else {
-+ ep = &pcd->out_ep[ep_num - 1];
-+ }
-+
-+ return ep;
-+}
-+
-+/**
-+ * This function checks the EP request queue, if the queue is not
-+ * empty the next request is started.
-+ */
-+void start_next_request(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_pcd_request_t *req = 0;
-+ uint32_t max_transfer =
-+ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
-+
-+#ifdef DWC_UTE_CFI
-+ struct dwc_otg_pcd *pcd;
-+ pcd = ep->pcd;
-+#endif
-+
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+
-+#ifdef DWC_UTE_CFI
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ ep->dwc_ep.cfi_req_len = req->length;
-+ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
-+ } else {
-+#endif
-+ /* Setup and start the Transfer */
-+ if (req->dw_align_buf) {
-+ ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
-+ ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
-+ ep->dwc_ep.xfer_buff = req->dw_align_buf;
-+ } else {
-+ ep->dwc_ep.dma_addr = req->dma;
-+ ep->dwc_ep.start_xfer_buff = req->buf;
-+ ep->dwc_ep.xfer_buff = req->buf;
-+ }
-+ ep->dwc_ep.sent_zlp = 0;
-+ ep->dwc_ep.total_len = req->length;
-+ ep->dwc_ep.xfer_len = 0;
-+ ep->dwc_ep.xfer_count = 0;
-+
-+ ep->dwc_ep.maxxfer = max_transfer;
-+ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
-+ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
-+ - (DDMA_MAX_TRANSFER_SIZE % 4);
-+ if (ep->dwc_ep.is_in) {
-+ if (ep->dwc_ep.maxxfer >
-+ DDMA_MAX_TRANSFER_SIZE) {
-+ ep->dwc_ep.maxxfer =
-+ DDMA_MAX_TRANSFER_SIZE;
-+ }
-+ } else {
-+ if (ep->dwc_ep.maxxfer > out_max_xfer) {
-+ ep->dwc_ep.maxxfer =
-+ out_max_xfer;
-+ }
-+ }
-+ }
-+ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
-+ ep->dwc_ep.maxxfer -=
-+ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
-+ }
-+ if (req->sent_zlp) {
-+ if ((ep->dwc_ep.total_len %
-+ ep->dwc_ep.maxpacket == 0)
-+ && (ep->dwc_ep.total_len != 0)) {
-+ ep->dwc_ep.sent_zlp = 1;
-+ }
-+
-+ }
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
-+ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ DWC_PRINTF("There are no more ISOC requests \n");
-+ ep->dwc_ep.frame_num = 0xFFFFFFFF;
-+ }
-+}
-+
-+/**
-+ * This function handles the SOF Interrupts. At this time the SOF
-+ * Interrupt is disabled.
-+ */
-+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+ gintsts_data_t gintsts;
-+
-+ DWC_DEBUGPL(DBG_PCD, "SOF\n");
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.sofintr = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function handles the Rx Status Queue Level Interrupt, which
-+ * indicates that there is a least one packet in the Rx FIFO. The
-+ * packets are moved from the FIFO to memory, where they will be
-+ * processed when the Endpoint Interrupt Register indicates Transfer
-+ * Complete or SETUP Phase Done.
-+ *
-+ * Repeat the following until the Rx Status Queue is empty:
-+ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
-+ * info
-+ * -# If Receive FIFO is empty then skip to step Clear the interrupt
-+ * and exit
-+ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
-+ * SETUP data to the buffer
-+ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
-+ * to the destination buffer
-+ */
-+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ gintmsk_data_t gintmask = {.d32 = 0 };
-+ device_grxsts_data_t status;
-+ dwc_otg_pcd_ep_t *ep;
-+ gintsts_data_t gintsts;
-+#ifdef DEBUG
-+ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
-+#endif
-+
-+ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
-+ /* Disable the Rx Status Queue Level interrupt */
-+ gintmask.b.rxstsqlvl = 1;
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
-+
-+ /* Get the Status from the top of the FIFO */
-+ status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
-+ "pktsts:%x Frame:%d(0x%0x)\n",
-+ status.b.epnum, status.b.bcnt,
-+ dpid_str[status.b.dpid],
-+ status.b.pktsts, status.b.fn, status.b.fn);
-+ /* Get pointer to EP structure */
-+ ep = get_out_ep(pcd, status.b.epnum);
-+
-+ switch (status.b.pktsts) {
-+ case DWC_DSTS_GOUT_NAK:
-+ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
-+ break;
-+ case DWC_STS_DATA_UPDT:
-+ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
-+ if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
-+ /** @todo NGS Check for buffer overflow? */
-+ dwc_otg_read_packet(core_if,
-+ ep->dwc_ep.xfer_buff,
-+ status.b.bcnt);
-+ ep->dwc_ep.xfer_count += status.b.bcnt;
-+ ep->dwc_ep.xfer_buff += status.b.bcnt;
-+ }
-+ break;
-+ case DWC_STS_XFER_COMP:
-+ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
-+ break;
-+ case DWC_DSTS_SETUP_COMP:
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
-+#endif
-+ break;
-+ case DWC_DSTS_SETUP_UPDT:
-+ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD,
-+ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
-+ pcd->setup_pkt->req.bmRequestType,
-+ pcd->setup_pkt->req.bRequest,
-+ UGETW(pcd->setup_pkt->req.wValue),
-+ UGETW(pcd->setup_pkt->req.wIndex),
-+ UGETW(pcd->setup_pkt->req.wLength));
-+#endif
-+ ep->dwc_ep.xfer_count += status.b.bcnt;
-+ break;
-+ default:
-+ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
-+ status.b.pktsts);
-+ break;
-+ }
-+
-+ /* Enable the Rx Status Queue Level interrupt */
-+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.rxstsqlvl = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
-+ return 1;
-+}
-+
-+/**
-+ * This function examines the Device IN Token Learning Queue to
-+ * determine the EP number of the last IN token received. This
-+ * implementation is for the Mass Storage device where there are only
-+ * 2 IN EPs (Control-IN and BULK-IN).
-+ *
-+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
-+ * are 8 EP Numbers in each of the other possible DTKNQ Registers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ *
-+ */
-+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_device_global_regs_t *dev_global_regs =
-+ core_if->dev_if->dev_global_regs;
-+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
-+ /* Number of Token Queue Registers */
-+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
-+ dtknq1_data_t dtknqr1;
-+ uint32_t in_tkn_epnums[4];
-+ int ndx = 0;
-+ int i = 0;
-+ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
-+ int epnum = 0;
-+
-+ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
-+
-+ /* Read the DTKNQ Registers */
-+ for (i = 0; i < DTKNQ_REG_CNT; i++) {
-+ in_tkn_epnums[i] = DWC_READ_REG32(addr);
-+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
-+ in_tkn_epnums[i]);
-+ if (addr == &dev_global_regs->dvbusdis) {
-+ addr = &dev_global_regs->dtknqr3_dthrctl;
-+ } else {
-+ ++addr;
-+ }
-+
-+ }
-+
-+ /* Copy the DTKNQR1 data to the bit field. */
-+ dtknqr1.d32 = in_tkn_epnums[0];
-+ /* Get the EP numbers */
-+ in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
-+ ndx = dtknqr1.b.intknwptr - 1;
-+
-+ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
-+ if (ndx == -1) {
-+ /** @todo Find a simpler way to calculate the max
-+ * queue position.*/
-+ int cnt = TOKEN_Q_DEPTH;
-+ if (TOKEN_Q_DEPTH <= 6) {
-+ cnt = TOKEN_Q_DEPTH - 1;
-+ } else if (TOKEN_Q_DEPTH <= 14) {
-+ cnt = TOKEN_Q_DEPTH - 7;
-+ } else if (TOKEN_Q_DEPTH <= 22) {
-+ cnt = TOKEN_Q_DEPTH - 15;
-+ } else {
-+ cnt = TOKEN_Q_DEPTH - 23;
-+ }
-+ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
-+ } else {
-+ if (ndx <= 5) {
-+ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
-+ } else if (ndx <= 13) {
-+ ndx -= 6;
-+ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
-+ } else if (ndx <= 21) {
-+ ndx -= 14;
-+ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
-+ } else if (ndx <= 29) {
-+ ndx -= 22;
-+ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
-+ }
-+ }
-+ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
-+ return epnum;
-+}
-+
-+/**
-+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
-+ * The active request is checked for the next packet to be loaded into
-+ * the non-periodic Tx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ gnptxsts_data_t txstatus = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+
-+ int epnum = 0;
-+ dwc_otg_pcd_ep_t *ep = 0;
-+ uint32_t len = 0;
-+ int dwords;
-+
-+ /* Get the epnum from the IN Token Learning Queue. */
-+ epnum = get_ep_of_last_in_token(core_if);
-+ ep = get_in_ep(pcd, epnum);
-+
-+ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
-+
-+ while (txstatus.b.nptxqspcavail > 0 &&
-+ txstatus.b.nptxfspcavail > dwords &&
-+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
-+ DWC_READ_REG32(&global_regs->gnptxsts));
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.nptxfempty = 1;
-+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function is called when dedicated Tx FIFO Empty interrupt occurs.
-+ * The active request is checked for the next packet to be loaded into
-+ * apropriate Tx FIFO.
-+ */
-+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *ep_regs;
-+ dtxfsts_data_t txstatus = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep = 0;
-+ uint32_t len = 0;
-+ int dwords;
-+
-+ ep = get_in_ep(pcd, epnum);
-+
-+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
-+
-+ ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+
-+ /* While there is space in the queue and space in the FIFO and
-+ * More data to tranfer, Write packets to the Tx FIFO */
-+ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
-+
-+ while (txstatus.b.txfspcavail > dwords &&
-+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
-+ ep->dwc_ep.xfer_len != 0) {
-+ /* Write the FIFO */
-+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
-+
-+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+ if (len > ep->dwc_ep.maxpacket) {
-+ len = ep->dwc_ep.maxpacket;
-+ }
-+
-+ dwords = (len + 3) / 4;
-+ txstatus.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
-+ txstatus.d32);
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function is called when the Device is disconnected. It stops
-+ * any active requests and informs the Gadget driver of the
-+ * disconnect.
-+ */
-+void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
-+{
-+ int i, num_in_eps, num_out_eps;
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_SPINLOCK(pcd->lock);
-+
-+ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
-+ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
-+ /* don't disconnect drivers more than once */
-+ if (pcd->ep0state == EP0_DISCONNECT) {
-+ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
-+ DWC_SPINUNLOCK(pcd->lock);
-+ return;
-+ }
-+ pcd->ep0state = EP0_DISCONNECT;
-+
-+ /* Reset the OTG state. */
-+ dwc_otg_pcd_update_otg(pcd, 1);
-+
-+ /* Disable the NP Tx Fifo Empty Interrupt. */
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Flush the FIFOs */
-+ /**@todo NGS Flush Periodic FIFOs */
-+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
-+ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
-+
-+ /* prevent new request submissions, kill any outstanding requests */
-+ ep = &pcd->ep0;
-+ dwc_otg_request_nuke(ep);
-+ /* prevent new request submissions, kill any outstanding requests */
-+ for (i = 0; i < num_in_eps; i++) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
-+ dwc_otg_request_nuke(ep);
-+ }
-+ /* prevent new request submissions, kill any outstanding requests */
-+ for (i = 0; i < num_out_eps; i++) {
-+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
-+ dwc_otg_request_nuke(ep);
-+ }
-+
-+ /* report disconnect; the driver is already quiesced */
-+ if (pcd->fops->disconnect) {
-+ DWC_SPINUNLOCK(pcd->lock);
-+ pcd->fops->disconnect(pcd);
-+ DWC_SPINLOCK(pcd->lock);
-+ }
-+ DWC_SPINUNLOCK(pcd->lock);
-+}
-+
-+/**
-+ * This interrupt indicates that ...
-+ */
-+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
-+ intr_mask.b.i2cintr = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.i2cintr = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that ...
-+ */
-+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+#if defined(VERBOSE)
-+ DWC_PRINTF("Early Suspend Detected\n");
-+#endif
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.erlysuspend = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This function configures EPO to receive SETUP packets.
-+ *
-+ * @todo NGS: Update the comments from the HW FS.
-+ *
-+ * -# Program the following fields in the endpoint specific registers
-+ * for Control OUT EP 0, in order to receive a setup packet
-+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
-+ * setup packets)
-+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
-+ * to back setup packets)
-+ * - In DMA mode, DOEPDMA0 Register with a memory address to
-+ * store any setup packets received
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param pcd Programming view of the PCD.
-+ */
-+static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
-+ dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ depctl_data_t doepctl = {.d32 = 0 };
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
-+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+#endif
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
-+ if (doepctl.b.epena) {
-+ return;
-+ }
-+ }
-+
-+ doeptsize0.b.supcnt = 3;
-+ doeptsize0.b.pktcnt = 1;
-+ doeptsize0.b.xfersize = 8 * 3;
-+
-+ if (core_if->dma_enable) {
-+ if (!core_if->dma_desc_enable) {
-+ /** put here as for Hermes mode deptisz register should not be written */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
-+ doeptsize0.d32);
-+
-+ /** @todo dma needs to handle multiple setup packets (up to 3) */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
-+ pcd->setup_pkt_dma_handle);
-+ } else {
-+ dev_if->setup_desc_index =
-+ (dev_if->setup_desc_index + 1) & 1;
-+ dma_desc =
-+ dev_if->setup_desc_addr[dev_if->setup_desc_index];
-+
-+ /** DMA Descriptor Setup */
-+ dma_desc->status.b.bs = BS_HOST_BUSY;
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ dma_desc->status.b.sr = 0;
-+ dma_desc->status.b.mtrf = 0;
-+ }
-+ dma_desc->status.b.l = 1;
-+ dma_desc->status.b.ioc = 1;
-+ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
-+ dma_desc->buf = pcd->setup_pkt_dma_handle;
-+ dma_desc->status.b.sts = 0;
-+ dma_desc->status.b.bs = BS_HOST_READY;
-+
-+ /** DOEPDMA0 Register write */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
-+ dev_if->dma_setup_desc_addr
-+ [dev_if->setup_desc_index]);
-+ }
-+
-+ } else {
-+ /** put here as for Hermes mode deptisz register should not be written */
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
-+ doeptsize0.d32);
-+ }
-+
-+ /** DOEPCTL0 Register write cnak will be set after setup interrupt */
-+ doepctl.d32 = 0;
-+ doepctl.b.epena = 1;
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+ doepctl.b.cnak = 1;
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+ } else {
-+ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
-+ }
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
-+ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+}
-+
-+/**
-+ * This interrupt occurs when a USB Reset is detected. When the USB
-+ * Reset Interrupt occurs the device state is set to DEFAULT and the
-+ * EP0 state is set to IDLE.
-+ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
-+ * -# Unmask the following interrupt bits
-+ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
-+ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
-+ * - DOEPMSK.SETUP = 1
-+ * - DOEPMSK.XferCompl = 1
-+ * - DIEPMSK.XferCompl = 1
-+ * - DIEPMSK.TimeOut = 1
-+ * -# Program the following fields in the endpoint specific registers
-+ * for Control OUT EP 0, in order to receive a setup packet
-+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
-+ * setup packets)
-+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
-+ * to back setup packets)
-+ * - In DMA mode, DOEPDMA0 Register with a memory address to
-+ * store any setup packets received
-+ * At this point, all the required initialization, except for enabling
-+ * the control 0 OUT endpoint is done, for receiving SETUP packets.
-+ */
-+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ depctl_data_t doepctl = {.d32 = 0 };
-+ depctl_data_t diepctl = {.d32 = 0 };
-+ daint_data_t daintmsk = {.d32 = 0 };
-+ doepmsk_data_t doepmsk = {.d32 = 0 };
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+ grstctl_t resetctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+ int i = 0;
-+ gintsts_data_t gintsts;
-+ pcgcctl_data_t power = {.d32 = 0 };
-+
-+ power.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+ if (power.b.stoppclk) {
-+ power.d32 = 0;
-+ power.b.stoppclk = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+
-+ power.b.pwrclmp = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+
-+ power.b.rstpdwnmodule = 1;
-+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+ }
-+
-+ core_if->lx_state = DWC_OTG_L0;
-+
-+ DWC_PRINTF("USB RESET\n");
-+#ifdef DWC_EN_ISOC
-+ for (i = 1; i < 16; ++i) {
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ ep = get_in_ep(pcd, i);
-+ if (ep != 0) {
-+ dwc_ep = &ep->dwc_ep;
-+ dwc_ep->next_frame = 0xffffffff;
-+ }
-+ }
-+#endif /* DWC_EN_ISOC */
-+
-+ /* reset the HNP settings */
-+ dwc_otg_pcd_update_otg(pcd, 1);
-+
-+ /* Clear the Remote Wakeup Signalling */
-+ dctl.b.rmtwkupsig = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+
-+ /* Set NAK for all OUT EPs */
-+ doepctl.b.snak = 1;
-+ for (i = 0; i <= dev_if->num_out_eps; i++) {
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
-+ }
-+
-+ /* Flush the NP Tx FIFO */
-+ dwc_otg_flush_tx_fifo(core_if, 0x10);
-+ /* Flush the Learning Queue */
-+ resetctl.b.intknqflsh = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
-+ core_if->start_predict = 0;
-+ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
-+ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
-+ }
-+ core_if->nextep_seq[0] = 0;
-+ core_if->first_in_nextep_seq = 0;
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+ diepctl.b.nextep = 0;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.epmscnt = 2;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
-+ }
-+ }
-+
-+ if (core_if->multiproc_int_enable) {
-+ daintmsk.b.inep0 = 1;
-+ daintmsk.b.outep0 = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
-+ daintmsk.d32);
-+
-+ doepmsk.b.setup = 1;
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+
-+ if ((core_if->dma_desc_enable) ||
-+ (core_if->dma_enable
-+ && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
-+ doepmsk.b.stsphsercvd = 1;
-+ }
-+ if (core_if->dma_desc_enable)
-+ doepmsk.b.bna = 1;
-+/*
-+ doepmsk.b.babble = 1;
-+ doepmsk.b.nyet = 1;
-+
-+ if (core_if->dma_enable) {
-+ doepmsk.b.nak = 1;
-+ }
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
-+ doepmsk.d32);
-+
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ diepmsk.b.intknepmis = 1;
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+ diepmsk.b.intknepmis = 0;
-+
-+/* if (core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+*/
-+/*
-+ if (core_if->dma_enable) {
-+ diepmsk.b.nak = 1;
-+ }
-+*/
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
-+ diepmsk.d32);
-+ } else {
-+ daintmsk.b.inep0 = 1;
-+ daintmsk.b.outep0 = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
-+ daintmsk.d32);
-+
-+ doepmsk.b.setup = 1;
-+ doepmsk.b.xfercompl = 1;
-+ doepmsk.b.ahberr = 1;
-+ doepmsk.b.epdisabled = 1;
-+
-+ if ((core_if->dma_desc_enable) ||
-+ (core_if->dma_enable
-+ && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
-+ doepmsk.b.stsphsercvd = 1;
-+ }
-+ if (core_if->dma_desc_enable)
-+ doepmsk.b.bna = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
-+
-+ diepmsk.b.xfercompl = 1;
-+ diepmsk.b.timeout = 1;
-+ diepmsk.b.epdisabled = 1;
-+ diepmsk.b.ahberr = 1;
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+ diepmsk.b.intknepmis = 0;
-+/*
-+ if (core_if->dma_desc_enable) {
-+ diepmsk.b.bna = 1;
-+ }
-+*/
-+
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
-+ }
-+
-+ /* Reset Device Address */
-+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+ dcfg.b.devaddr = 0;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+ /* setup EP0 to receive SETUP packets */
-+ if (core_if->snpsid <= OTG_CORE_REV_2_94a)
-+ ep0_out_start(core_if, pcd);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.usbreset = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Get the device speed from the device status register and convert it
-+ * to USB speed constant.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static int get_device_speed(dwc_otg_core_if_t * core_if)
-+{
-+ dsts_data_t dsts;
-+ int speed = 0;
-+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+ switch (dsts.b.enumspd) {
-+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+ speed = USB_SPEED_HIGH;
-+ break;
-+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+ speed = USB_SPEED_FULL;
-+ break;
-+
-+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+ speed = USB_SPEED_LOW;
-+ break;
-+ }
-+
-+ return speed;
-+}
-+
-+/**
-+ * Read the device status register and set the device speed in the
-+ * data structure.
-+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
-+ */
-+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ gintsts_data_t gintsts;
-+ gusbcfg_data_t gusbcfg;
-+ dwc_otg_core_global_regs_t *global_regs =
-+ GET_CORE_IF(pcd)->core_global_regs;
-+ uint8_t utmi16b, utmi8b;
-+ int speed;
-+ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
-+
-+ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
-+ utmi16b = 6; //vahrama old value was 6;
-+ utmi8b = 9;
-+ } else {
-+ utmi16b = 4;
-+ utmi8b = 8;
-+ }
-+ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
-+ ep0_out_start(GET_CORE_IF(pcd), pcd);
-+ }
-+
-+#ifdef DEBUG_EP0
-+ print_ep0_state(pcd);
-+#endif
-+
-+ if (pcd->ep0state == EP0_DISCONNECT) {
-+ pcd->ep0state = EP0_IDLE;
-+ } else if (pcd->ep0state == EP0_STALL) {
-+ pcd->ep0state = EP0_IDLE;
-+ }
-+
-+ pcd->ep0state = EP0_IDLE;
-+
-+ ep0->stopped = 0;
-+
-+ speed = get_device_speed(GET_CORE_IF(pcd));
-+ pcd->fops->connect(pcd, speed);
-+
-+ /* Set USB turnaround time based on device speed and PHY interface. */
-+ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+ if (speed == USB_SPEED_HIGH) {
-+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+ DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
-+ /* ULPI interface */
-+ gusbcfg.b.usbtrdtim = 9;
-+ }
-+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+ DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
-+ /* UTMI+ interface */
-+ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
-+ gusbcfg.b.usbtrdtim = utmi8b;
-+ } else if (GET_CORE_IF(pcd)->hwcfg4.
-+ b.utmi_phy_data_width == 1) {
-+ gusbcfg.b.usbtrdtim = utmi16b;
-+ } else if (GET_CORE_IF(pcd)->
-+ core_params->phy_utmi_width == 8) {
-+ gusbcfg.b.usbtrdtim = utmi8b;
-+ } else {
-+ gusbcfg.b.usbtrdtim = utmi16b;
-+ }
-+ }
-+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
-+ /* UTMI+ OR ULPI interface */
-+ if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+ /* ULPI interface */
-+ gusbcfg.b.usbtrdtim = 9;
-+ } else {
-+ /* UTMI+ interface */
-+ if (GET_CORE_IF(pcd)->
-+ core_params->phy_utmi_width == 16) {
-+ gusbcfg.b.usbtrdtim = utmi16b;
-+ } else {
-+ gusbcfg.b.usbtrdtim = utmi8b;
-+ }
-+ }
-+ }
-+ } else {
-+ /* Full or low speed */
-+ gusbcfg.b.usbtrdtim = 9;
-+ }
-+ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.enumdone = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the ISO OUT Packet was dropped due to
-+ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
-+ * read all the data from the Rx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+
-+ DWC_WARN("INTERRUPT Handler not implemented for %s\n",
-+ "ISOC Out Dropped");
-+
-+ intr_mask.b.isooutdrop = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.isooutdrop = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates the end of the portion of the micro-frame
-+ * for periodic transactions. If there is a periodic transaction for
-+ * the next frame, load the packets into the EP periodic Tx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
-+
-+ intr_mask.b.eopframe = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.eopframe = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that EP of the packet on the top of the
-+ * non-periodic Tx FIFO does not match EP of the IN Token received.
-+ *
-+ * The "Device IN Token Queue" Registers are read to determine the
-+ * order the IN Tokens have been received. The non-periodic Tx FIFO
-+ * is flushed, so it can be reloaded in the order seen in the IN Token
-+ * Queue.
-+ */
-+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dctl_data_t dctl;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+ core_if->start_predict = 1;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-+
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ if (!gintsts.b.ginnakeff) {
-+ /* Disable EP Mismatch interrupt */
-+ intr_mask.d32 = 0;
-+ intr_mask.b.epmismatch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+ /* Enable the Global IN NAK Effective Interrupt */
-+ intr_mask.d32 = 0;
-+ intr_mask.b.ginnakeff = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
-+ /* Set the global non-periodic IN NAK handshake */
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ dctl.b.sgnpinnak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+ } else {
-+ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
-+ }
-+ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
-+ * handler after Global IN NAK Effective interrupt will be asserted */
-+ }
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.epmismatch = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt is valid only in DMA mode. This interrupt indicates that the
-+ * core has stopped fetching data for IN endpoints due to the unavailability of
-+ * TxFIFO space or Request Queue space. This interrupt is used by the
-+ * application for an endpoint mismatch algorithm.
-+ *
-+ * @param pcd The PCD
-+ */
-+int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+ gintmsk_data_t gintmsk_data;
-+ dctl_data_t dctl;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-+
-+ /* Clear the global non-periodic IN NAK handshake */
-+ dctl.d32 = 0;
-+ dctl.b.cgnpinnak = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+ /* Mask GINTSTS.FETSUSP interrupt */
-+ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+ gintmsk_data.b.fetsusp = 0;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.fetsusp = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+ return 1;
-+}
-+/**
-+ * This funcion stalls EP0.
-+ */
-+static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ usb_device_request_t *ctrl = &pcd->setup_pkt->req;
-+ DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
-+ ctrl->bmRequestType, ctrl->bRequest, err_val);
-+
-+ ep0->dwc_ep.is_in = 1;
-+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+ pcd->ep0.stopped = 1;
-+ pcd->ep0state = EP0_IDLE;
-+ ep0_out_start(GET_CORE_IF(pcd), pcd);
-+}
-+
-+/**
-+ * This functions delegates the setup command to the gadget driver.
-+ */
-+static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
-+ usb_device_request_t * ctrl)
-+{
-+ int ret = 0;
-+ DWC_SPINUNLOCK(pcd->lock);
-+ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
-+ DWC_SPINLOCK(pcd->lock);
-+ if (ret < 0) {
-+ ep0_do_stall(pcd, ret);
-+ }
-+
-+ /** @todo This is a g_file_storage gadget driver specific
-+ * workaround: a DELAYED_STATUS result from the fsg_setup
-+ * routine will result in the gadget queueing a EP0 IN status
-+ * phase for a two-stage control transfer. Exactly the same as
-+ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
-+ * specific request. Need a generic way to know when the gadget
-+ * driver will queue the status phase. Can we assume when we
-+ * call the gadget driver setup() function that it will always
-+ * queue and require the following flag? Need to look into
-+ * this.
-+ */
-+
-+ if (ret == 256 + 999) {
-+ pcd->request_config = 1;
-+ }
-+}
-+
-+#ifdef DWC_UTE_CFI
-+/**
-+ * This functions delegates the CFI setup commands to the gadget driver.
-+ * This function will return a negative value to indicate a failure.
-+ */
-+static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
-+ struct cfi_usb_ctrlrequest *ctrl_req)
-+{
-+ int ret = 0;
-+
-+ if (pcd->fops && pcd->fops->cfi_setup) {
-+ DWC_SPINUNLOCK(pcd->lock);
-+ ret = pcd->fops->cfi_setup(pcd, ctrl_req);
-+ DWC_SPINLOCK(pcd->lock);
-+ if (ret < 0) {
-+ ep0_do_stall(pcd, ret);
-+ return ret;
-+ }
-+ }
-+
-+ return ret;
-+}
-+#endif
-+
-+/**
-+ * This function starts the Zero-Length Packet for the IN status phase
-+ * of a 2 stage control transfer.
-+ */
-+static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ if (pcd->ep0state == EP0_STALL) {
-+ return;
-+ }
-+
-+ pcd->ep0state = EP0_IN_STATUS_PHASE;
-+
-+ /* Prepare for more SETUP Packets */
-+ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
-+ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
-+ && (pcd->core_if->dma_desc_enable)
-+ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Data terminated wait next packet in out_desc_addr\n");
-+ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
-+ pcd->data_terminated = 1;
-+ }
-+ ep0->dwc_ep.xfer_len = 0;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.is_in = 1;
-+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+
-+ /* Prepare for more SETUP Packets */
-+ //ep0_out_start(GET_CORE_IF(pcd), pcd);
-+}
-+
-+/**
-+ * This function starts the Zero-Length Packet for the OUT status phase
-+ * of a 2 stage control transfer.
-+ */
-+static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ if (pcd->ep0state == EP0_STALL) {
-+ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
-+ return;
-+ }
-+ pcd->ep0state = EP0_OUT_STATUS_PHASE;
-+
-+ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
-+ ep0->dwc_ep.xfer_len = 0;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.is_in = 0;
-+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+
-+ /* Prepare for more SETUP Packets */
-+ if (GET_CORE_IF(pcd)->dma_enable == 0) {
-+ ep0_out_start(GET_CORE_IF(pcd), pcd);
-+ }
-+}
-+
-+/**
-+ * Clear the EP halt (STALL) and if pending requests start the
-+ * transfer.
-+ */
-+static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
-+{
-+ if (ep->dwc_ep.stall_clear_flag == 0)
-+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+
-+ /* Reactive the EP */
-+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+ if (ep->stopped) {
-+ ep->stopped = 0;
-+ /* If there is a request in the EP queue start it */
-+
-+ /** @todo FIXME: this causes an EP mismatch in DMA mode.
-+ * epmismatch not yet implemented. */
-+
-+ /*
-+ * Above fixme is solved by implmenting a tasklet to call the
-+ * start_next_request(), outside of interrupt context at some
-+ * time after the current time, after a clear-halt setup packet.
-+ * Still need to implement ep mismatch in the future if a gadget
-+ * ever uses more than one endpoint at once
-+ */
-+ ep->queue_sof = 1;
-+ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
-+ }
-+ /* Start Control Status Phase */
-+ do_setup_in_status_phase(pcd);
-+}
-+
-+/**
-+ * This function is called when the SET_FEATURE TEST_MODE Setup packet
-+ * is sent from the host. The Device Control register is written with
-+ * the Test Mode bits set to the specified Test Mode. This is done as
-+ * a tasklet so that the "Status" phase of the control transfer
-+ * completes before transmitting the TEST packets.
-+ *
-+ * @todo This has not been tested since the tasklet struct was put
-+ * into the PCD struct!
-+ *
-+ */
-+void do_test_mode(void *data)
-+{
-+ dctl_data_t dctl;
-+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ int test_mode = pcd->test_mode;
-+
-+// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
-+
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ switch (test_mode) {
-+ case 1: // TEST_J
-+ dctl.b.tstctl = 1;
-+ break;
-+
-+ case 2: // TEST_K
-+ dctl.b.tstctl = 2;
-+ break;
-+
-+ case 3: // TEST_SE0_NAK
-+ dctl.b.tstctl = 3;
-+ break;
-+
-+ case 4: // TEST_PACKET
-+ dctl.b.tstctl = 4;
-+ break;
-+
-+ case 5: // TEST_FORCE_ENABLE
-+ dctl.b.tstctl = 5;
-+ break;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+}
-+
-+/**
-+ * This function process the GET_STATUS Setup Commands.
-+ */
-+static inline void do_get_status(dwc_otg_pcd_t * pcd)
-+{
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ uint16_t *status = pcd->status_buf;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD,
-+ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+#endif
-+
-+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+ case UT_DEVICE:
-+ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
-+ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
-+ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
-+ DWC_PRINTF("OTG CAP - %d, %d\n",
-+ core_if->core_params->otg_cap,
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+ if (core_if->otg_ver == 1
-+ && core_if->core_params->otg_cap ==
-+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ uint8_t *otgsts = (uint8_t*)pcd->status_buf;
-+ *otgsts = (core_if->otg_sts & 0x1);
-+ pcd->ep0_pending = 1;
-+ ep0->dwc_ep.start_xfer_buff =
-+ (uint8_t *) otgsts;
-+ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
-+ ep0->dwc_ep.dma_addr =
-+ pcd->status_buf_dma_handle;
-+ ep0->dwc_ep.xfer_len = 1;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ return;
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+ } else {
-+ *status = 0x1; /* Self powered */
-+ *status |= pcd->remote_wakeup_enable << 1;
-+ break;
-+ }
-+ case UT_INTERFACE:
-+ *status = 0;
-+ break;
-+
-+ case UT_ENDPOINT:
-+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+ if (ep == 0 || UGETW(ctrl.wLength) > 2) {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ /** @todo check for EP stall */
-+ *status = ep->stopped;
-+ break;
-+ }
-+ pcd->ep0_pending = 1;
-+ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
-+ ep0->dwc_ep.xfer_buff = (uint8_t *) status;
-+ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
-+ ep0->dwc_ep.xfer_len = 2;
-+ ep0->dwc_ep.xfer_count = 0;
-+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
-+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+}
-+
-+/**
-+ * This function process the SET_FEATURE Setup Commands.
-+ */
-+static inline void do_set_feature(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep = 0;
-+ int32_t otg_cap_param = core_if->core_params->otg_cap;
-+ gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
-+
-+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+ case UT_DEVICE:
-+ switch (UGETW(ctrl.wValue)) {
-+ case UF_DEVICE_REMOTE_WAKEUP:
-+ pcd->remote_wakeup_enable = 1;
-+ break;
-+
-+ case UF_TEST_MODE:
-+ /* Setup the Test Mode tasklet to do the Test
-+ * Packet generation after the SETUP Status
-+ * phase has completed. */
-+
-+ /** @todo This has not been tested since the
-+ * tasklet struct was put into the PCD
-+ * struct! */
-+ pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
-+ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
-+ break;
-+
-+ case UF_DEVICE_B_HNP_ENABLE:
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
-+
-+ /* dev may initiate HNP */
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ pcd->b_hnp_enable = 1;
-+ dwc_otg_pcd_update_otg(pcd, 0);
-+ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
-+ /**@todo Is the gotgctl.devhnpen cleared
-+ * by a USB Reset? */
-+ gotgctl.b.devhnpen = 1;
-+ gotgctl.b.hnpreq = 1;
-+ DWC_WRITE_REG32(&global_regs->gotgctl,
-+ gotgctl.d32);
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+
-+ case UF_DEVICE_A_HNP_SUPPORT:
-+ /* RH port supports HNP */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ pcd->a_hnp_support = 1;
-+ dwc_otg_pcd_update_otg(pcd, 0);
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+
-+ case UF_DEVICE_A_ALT_HNP_SUPPORT:
-+ /* other RH port does */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
-+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+ pcd->a_alt_hnp_support = 1;
-+ dwc_otg_pcd_update_otg(pcd, 0);
-+ } else {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ break;
-+
-+ default:
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+
-+ }
-+ do_setup_in_status_phase(pcd);
-+ break;
-+
-+ case UT_INTERFACE:
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+
-+ case UT_ENDPOINT:
-+ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
-+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+ if (ep == 0) {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ ep->stopped = 1;
-+ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
-+ }
-+ do_setup_in_status_phase(pcd);
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function process the CLEAR_FEATURE Setup Commands.
-+ */
-+static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
-+{
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep = 0;
-+
-+ DWC_DEBUGPL(DBG_PCD,
-+ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+
-+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+ case UT_DEVICE:
-+ switch (UGETW(ctrl.wValue)) {
-+ case UF_DEVICE_REMOTE_WAKEUP:
-+ pcd->remote_wakeup_enable = 0;
-+ break;
-+
-+ case UF_TEST_MODE:
-+ /** @todo Add CLEAR_FEATURE for TEST modes. */
-+ break;
-+
-+ default:
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+ do_setup_in_status_phase(pcd);
-+ break;
-+
-+ case UT_ENDPOINT:
-+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+ if (ep == 0) {
-+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+ return;
-+ }
-+
-+ pcd_clear_halt(pcd, ep);
-+
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function process the SET_ADDRESS Setup Commands.
-+ */
-+static inline void do_set_address(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+
-+ if (ctrl.bmRequestType == UT_DEVICE) {
-+ dcfg_data_t dcfg = {.d32 = 0 };
-+
-+#ifdef DEBUG_EP0
-+// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
-+#endif
-+ dcfg.b.devaddr = UGETW(ctrl.wValue);
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
-+ do_setup_in_status_phase(pcd);
-+ }
-+}
-+
-+/**
-+ * This function processes SETUP commands. In Linux, the USB Command
-+ * processing is done in two places - the first being the PCD and the
-+ * second in the Gadget Driver (for example, the File-Backed Storage
-+ * Gadget Driver).
-+ *
-+ * <table>
-+ * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
-+ *
-+ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
-+ * defined in chapter 9 of the USB 2.0 Specification chapter 9
-+ * </td></tr>
-+ *
-+ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
-+ * requests are the ENDPOINT_HALT feature is procesed, all others the
-+ * interface requests are ignored.</td></tr>
-+ *
-+ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
-+ * requests are processed by the PCD. Interface requests are passed
-+ * to the Gadget Driver.</td></tr>
-+ *
-+ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
-+ * with device address received </td></tr>
-+ *
-+ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
-+ * requested descriptor</td></tr>
-+ *
-+ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
-+ * not implemented by any of the existing Gadget Drivers.</td></tr>
-+ *
-+ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
-+ * all EPs and enable EPs for new configuration.</td></tr>
-+ *
-+ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
-+ * the current configuration</td></tr>
-+ *
-+ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
-+ * EPs and enable EPs for new configuration.</td></tr>
-+ *
-+ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
-+ * current interface.</td></tr>
-+ *
-+ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
-+ * message.</td></tr>
-+ * </table>
-+ *
-+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
-+ * processed by pcd_setup. Calling the Function Driver's setup function from
-+ * pcd_setup processes the gadget SETUP commands.
-+ */
-+static inline void pcd_setup(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ usb_device_request_t ctrl = pcd->setup_pkt->req;
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+
-+ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+
-+#ifdef DWC_UTE_CFI
-+ int retval = 0;
-+ struct cfi_usb_ctrlrequest cfi_req;
-+#endif
-+
-+ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
-+
-+ /** In BDMA more then 1 setup packet is not supported till 3.00a */
-+ if (core_if->dma_enable && core_if->dma_desc_enable == 0
-+ && (doeptsize0.b.supcnt < 2)
-+ && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
-+ DWC_ERROR
-+ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
-+ }
-+ if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
-+ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
-+ ctrl =
-+ (pcd->setup_pkt +
-+ (3 - doeptsize0.b.supcnt - 1 +
-+ ep0->dwc_ep.stp_rollover))->req;
-+ }
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
-+ ctrl.bmRequestType, ctrl.bRequest,
-+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+ UGETW(ctrl.wLength));
-+#endif
-+
-+ /* Clean up the request queue */
-+ dwc_otg_request_nuke(ep0);
-+ ep0->stopped = 0;
-+
-+ if (ctrl.bmRequestType & UE_DIR_IN) {
-+ ep0->dwc_ep.is_in = 1;
-+ pcd->ep0state = EP0_IN_DATA_PHASE;
-+ } else {
-+ ep0->dwc_ep.is_in = 0;
-+ pcd->ep0state = EP0_OUT_DATA_PHASE;
-+ }
-+
-+ if (UGETW(ctrl.wLength) == 0) {
-+ ep0->dwc_ep.is_in = 1;
-+ pcd->ep0state = EP0_IN_STATUS_PHASE;
-+ }
-+
-+ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
-+
-+#ifdef DWC_UTE_CFI
-+ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
-+
-+ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
-+ ctrl.bRequestType, ctrl.bRequest);
-+ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
-+ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
-+ retval = cfi_setup(pcd, &cfi_req);
-+ if (retval < 0) {
-+ ep0_do_stall(pcd, retval);
-+ pcd->ep0_pending = 0;
-+ return;
-+ }
-+
-+ /* if need gadget setup then call it and check the retval */
-+ if (pcd->cfi->need_gadget_att) {
-+ retval =
-+ cfi_gadget_setup(pcd,
-+ &pcd->
-+ cfi->ctrl_req);
-+ if (retval < 0) {
-+ pcd->ep0_pending = 0;
-+ return;
-+ }
-+ }
-+
-+ if (pcd->cfi->need_status_in_complete) {
-+ do_setup_in_status_phase(pcd);
-+ }
-+ return;
-+ }
-+ }
-+#endif
-+
-+ /* handle non-standard (class/vendor) requests in the gadget driver */
-+ do_gadget_setup(pcd, &ctrl);
-+ return;
-+ }
-+
-+ /** @todo NGS: Handle bad setup packet? */
-+
-+///////////////////////////////////////////
-+//// --- Standard Request handling --- ////
-+
-+ switch (ctrl.bRequest) {
-+ case UR_GET_STATUS:
-+ do_get_status(pcd);
-+ break;
-+
-+ case UR_CLEAR_FEATURE:
-+ do_clear_feature(pcd);
-+ break;
-+
-+ case UR_SET_FEATURE:
-+ do_set_feature(pcd);
-+ break;
-+
-+ case UR_SET_ADDRESS:
-+ do_set_address(pcd);
-+ break;
-+
-+ case UR_SET_INTERFACE:
-+ case UR_SET_CONFIG:
-+// _pcd->request_config = 1; /* Configuration changed */
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+
-+ case UR_SYNCH_FRAME:
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+
-+ default:
-+ /* Call the Gadget Driver's setup functions */
-+ do_gadget_setup(pcd, &ctrl);
-+ break;
-+ }
-+}
-+
-+/**
-+ * This function completes the ep0 control transfer.
-+ */
-+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
-+ dev_if->in_ep_regs[ep->dwc_ep.num];
-+#ifdef DEBUG_EP0
-+ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
-+ dev_if->out_ep_regs[ep->dwc_ep.num];
-+#endif
-+ deptsiz0_data_t deptsiz;
-+ dev_dma_desc_sts_t desc_sts;
-+ dwc_otg_pcd_request_t *req;
-+ int is_last = 0;
-+ dwc_otg_pcd_t *pcd = ep->pcd;
-+
-+#ifdef DWC_UTE_CFI
-+ struct cfi_usb_ctrlrequest *ctrlreq;
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+#endif
-+
-+ desc_sts.b.bytes = 0;
-+
-+ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ if (ep->dwc_ep.is_in) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
-+#endif
-+ do_setup_out_status_phase(pcd);
-+ } else {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
-+#endif
-+
-+#ifdef DWC_UTE_CFI
-+ ctrlreq = &pcd->cfi->ctrl_req;
-+
-+ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
-+ if (ctrlreq->bRequest > 0xB0
-+ && ctrlreq->bRequest < 0xBF) {
-+
-+ /* Return if the PCD failed to handle the request */
-+ if ((retval =
-+ pcd->cfi->ops.
-+ ctrl_write_complete(pcd->cfi,
-+ pcd)) < 0) {
-+ CFI_INFO
-+ ("ERROR setting a new value in the PCD(%d)\n",
-+ retval);
-+ ep0_do_stall(pcd, retval);
-+ pcd->ep0_pending = 0;
-+ return 0;
-+ }
-+
-+ /* If the gadget needs to be notified on the request */
-+ if (pcd->cfi->need_gadget_att == 1) {
-+ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
-+ retval =
-+ cfi_gadget_setup(pcd,
-+ &pcd->cfi->
-+ ctrl_req);
-+
-+ /* Return from the function if the gadget failed to process
-+ * the request properly - this should never happen !!!
-+ */
-+ if (retval < 0) {
-+ CFI_INFO
-+ ("ERROR setting a new value in the gadget(%d)\n",
-+ retval);
-+ pcd->ep0_pending = 0;
-+ return 0;
-+ }
-+ }
-+
-+ CFI_INFO("%s: RETVAL=%d\n", __func__,
-+ retval);
-+ /* If we hit here then the PCD and the gadget has properly
-+ * handled the request - so send the ZLP IN to the host.
-+ */
-+ /* @todo: MAS - decide whether we need to start the setup
-+ * stage based on the need_setup value of the cfi object
-+ */
-+ do_setup_in_status_phase(pcd);
-+ pcd->ep0_pending = 0;
-+ return 1;
-+ }
-+ }
-+#endif
-+
-+ do_setup_in_status_phase(pcd);
-+ }
-+ pcd->ep0_pending = 0;
-+ return 1;
-+ }
-+
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ return 0;
-+ }
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+
-+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE
-+ || pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ is_last = 1;
-+ } else if (ep->dwc_ep.is_in) {
-+ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
-+ if (core_if->dma_desc_enable != 0)
-+ desc_sts = dev_if->in_desc_addr->status;
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num, ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+#endif
-+
-+ if (((core_if->dma_desc_enable == 0)
-+ && (deptsiz.b.xfersize == 0))
-+ || ((core_if->dma_desc_enable != 0)
-+ && (desc_sts.b.bytes == 0))) {
-+ req->actual = ep->dwc_ep.xfer_count;
-+ /* Is a Zero Len Packet needed? */
-+ if (req->sent_zlp) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
-+#endif
-+ req->sent_zlp = 0;
-+ }
-+ do_setup_out_status_phase(pcd);
-+ }
-+ } else {
-+ /* ep0-OUT */
-+#ifdef DEBUG_EP0
-+ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
-+ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num, ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+#endif
-+ req->actual = ep->dwc_ep.xfer_count;
-+
-+ /* Is a Zero Len Packet needed? */
-+ if (req->sent_zlp) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
-+#endif
-+ req->sent_zlp = 0;
-+ }
-+ /* For older cores do setup in status phase in Slave/BDMA modes,
-+ * starting from 3.00 do that only in slave, and for DMA modes
-+ * just re-enable ep 0 OUT here*/
-+ if (core_if->dma_enable == 0
-+ || (core_if->dma_desc_enable == 0
-+ && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
-+ do_setup_in_status_phase(pcd);
-+ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "Enable out ep before in status phase\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+
-+ /* Complete the request */
-+ if (is_last) {
-+ dwc_otg_request_done(ep, req, 0);
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+ return 1;
-+ }
-+ return 0;
-+}
-+
-+#ifdef DWC_UTE_CFI
-+/**
-+ * This function calculates traverses all the CFI DMA descriptors and
-+ * and accumulates the bytes that are left to be transfered.
-+ *
-+ * @return The total bytes left to transfered, or a negative value as failure
-+ */
-+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
-+{
-+ int32_t ret = 0;
-+ int i;
-+ struct dwc_otg_dma_desc *ddesc = NULL;
-+ struct cfi_ep *cfiep;
-+
-+ /* See if the pcd_ep has its respective cfi_ep mapped */
-+ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
-+ if (!cfiep) {
-+ CFI_INFO("%s: Failed to find ep\n", __func__);
-+ return -1;
-+ }
-+
-+ ddesc = ep->dwc_ep.descs;
-+
-+ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
-+
-+#if defined(PRINT_CFI_DMA_DESCS)
-+ print_desc(ddesc, ep->ep.name, i);
-+#endif
-+ ret += ddesc->status.b.bytes;
-+ ddesc++;
-+ }
-+
-+ if (ret)
-+ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
-+ ret);
-+
-+ return ret;
-+}
-+#endif
-+
-+/**
-+ * This function completes the request for the EP. If there are
-+ * additional requests for the EP in the queue they will be started.
-+ */
-+static void complete_ep(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ dwc_otg_dev_in_ep_regs_t *in_ep_regs =
-+ dev_if->in_ep_regs[ep->dwc_ep.num];
-+ deptsiz_data_t deptsiz;
-+ dev_dma_desc_sts_t desc_sts;
-+ dwc_otg_pcd_request_t *req = 0;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ uint32_t byte_count = 0;
-+ int is_last = 0;
-+ int i;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"));
-+
-+ /* Get any pending requests */
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (!req) {
-+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+ return;
-+ }
-+ } else {
-+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+ return;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
-+
-+ if (ep->dwc_ep.is_in) {
-+ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
-+
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable == 0) {
-+ if (deptsiz.b.xfersize == 0
-+ && deptsiz.b.pktcnt == 0) {
-+ byte_count =
-+ ep->dwc_ep.xfer_len -
-+ ep->dwc_ep.xfer_count;
-+
-+ ep->dwc_ep.xfer_buff += byte_count;
-+ ep->dwc_ep.dma_addr += byte_count;
-+ ep->dwc_ep.xfer_count += byte_count;
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%d-%s len=%d xfersize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num,
-+ (ep->dwc_ep.
-+ is_in ? "IN" : "OUT"),
-+ ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize,
-+ deptsiz.b.pktcnt);
-+
-+ if (ep->dwc_ep.xfer_len <
-+ ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer
-+ (core_if, &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length transfer in case if it is queued
-+ * a transfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Descriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 length.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer
-+ (core_if, &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ } else {
-+ if (ep->dwc_ep.type ==
-+ DWC_OTG_EP_TYPE_ISOC) {
-+ req->actual = 0;
-+ dwc_otg_request_done(ep, req, 0);
-+
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+
-+ /* If there is a request in the queue start it. */
-+ start_next_request(ep);
-+ } else
-+ DWC_WARN
-+ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
-+ ep->dwc_ep.num,
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+ deptsiz.b.xfersize,
-+ deptsiz.b.pktcnt);
-+ }
-+ } else {
-+ dma_desc = ep->dwc_ep.desc_addr;
-+ byte_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+
-+#ifdef DWC_UTE_CFI
-+ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
-+ ep->dwc_ep.buff_mode);
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ int residue;
-+
-+ residue = cfi_calc_desc_residue(ep);
-+ if (residue < 0)
-+ return;
-+
-+ byte_count = residue;
-+ } else {
-+#endif
-+ for (i = 0; i < ep->dwc_ep.desc_cnt;
-+ ++i) {
-+ desc_sts = dma_desc->status;
-+ byte_count += desc_sts.b.bytes;
-+ dma_desc++;
-+ }
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ if (byte_count == 0) {
-+ ep->dwc_ep.xfer_count =
-+ ep->dwc_ep.total_len;
-+ is_last = 1;
-+ } else {
-+ DWC_WARN("Incomplete transfer\n");
-+ }
-+ }
-+ } else {
-+ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "%d-%s len=%d xfersize=%d pktcnt=%d\n",
-+ ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT",
-+ ep->dwc_ep.xfer_len,
-+ deptsiz.b.xfersize,
-+ deptsiz.b.pktcnt);
-+
-+ /* Check if the whole transfer was completed,
-+ * if no, setup transfer for next portion of data
-+ */
-+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length trasfer in case if it is queued
-+ * a trasfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Desriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 legth.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ } else {
-+ DWC_WARN
-+ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
-+ ep->dwc_ep.num,
-+ (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ }
-+ }
-+ } else {
-+ dwc_otg_dev_out_ep_regs_t *out_ep_regs =
-+ dev_if->out_ep_regs[ep->dwc_ep.num];
-+ desc_sts.d32 = 0;
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ dma_desc = ep->dwc_ep.desc_addr;
-+ byte_count = 0;
-+ ep->dwc_ep.sent_zlp = 0;
-+
-+#ifdef DWC_UTE_CFI
-+ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
-+ ep->dwc_ep.buff_mode);
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ int residue;
-+ residue = cfi_calc_desc_residue(ep);
-+ if (residue < 0)
-+ return;
-+ byte_count = residue;
-+ } else {
-+#endif
-+
-+ for (i = 0; i < ep->dwc_ep.desc_cnt;
-+ ++i) {
-+ desc_sts = dma_desc->status;
-+ byte_count += desc_sts.b.bytes;
-+ dma_desc++;
-+ }
-+
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ /* Checking for interrupt Out transfers with not
-+ * dword aligned mps sizes
-+ */
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
-+ (ep->dwc_ep.maxpacket%4)) {
-+ ep->dwc_ep.xfer_count =
-+ ep->dwc_ep.total_len - byte_count;
-+ if ((ep->dwc_ep.xfer_len %
-+ ep->dwc_ep.maxpacket)
-+ && (ep->dwc_ep.xfer_len /
-+ ep->dwc_ep.maxpacket <
-+ MAX_DMA_DESC_CNT))
-+ ep->dwc_ep.xfer_len -=
-+ (ep->dwc_ep.desc_cnt -
-+ 1) * ep->dwc_ep.maxpacket +
-+ ep->dwc_ep.xfer_len %
-+ ep->dwc_ep.maxpacket;
-+ else
-+ ep->dwc_ep.xfer_len -=
-+ ep->dwc_ep.desc_cnt *
-+ ep->dwc_ep.maxpacket;
-+ if (ep->dwc_ep.xfer_len > 0) {
-+ dwc_otg_ep_start_transfer
-+ (core_if, &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ } else {
-+ ep->dwc_ep.xfer_count =
-+ ep->dwc_ep.total_len - byte_count +
-+ ((4 -
-+ (ep->dwc_ep.
-+ total_len & 0x3)) & 0x3);
-+ is_last = 1;
-+ }
-+ } else {
-+ deptsiz.d32 = 0;
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&out_ep_regs->doeptsiz);
-+
-+ byte_count = (ep->dwc_ep.xfer_len -
-+ ep->dwc_ep.xfer_count -
-+ deptsiz.b.xfersize);
-+ ep->dwc_ep.xfer_buff += byte_count;
-+ ep->dwc_ep.dma_addr += byte_count;
-+ ep->dwc_ep.xfer_count += byte_count;
-+
-+ /* Check if the whole transfer was completed,
-+ * if no, setup transfer for next portion of data
-+ */
-+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length trasfer in case if it is queued
-+ * a trasfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Desriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 legth.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ }
-+ } else {
-+ /* Check if the whole transfer was completed,
-+ * if no, setup transfer for next portion of data
-+ */
-+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
-+ } else if (ep->dwc_ep.sent_zlp) {
-+ /*
-+ * This fragment of code should initiate 0
-+ * length transfer in case if it is queued
-+ * a transfer with size divisible to EPs max
-+ * packet size and with usb_request zero field
-+ * is set, which means that after data is transfered,
-+ * it is also should be transfered
-+ * a 0 length packet at the end. For Slave and
-+ * Buffer DMA modes in this case SW has
-+ * to initiate 2 transfers one with transfer size,
-+ * and the second with 0 size. For Descriptor
-+ * DMA mode SW is able to initiate a transfer,
-+ * which will handle all the packets including
-+ * the last 0 length.
-+ */
-+ ep->dwc_ep.sent_zlp = 0;
-+ dwc_otg_ep_start_zl_transfer(core_if,
-+ &ep->dwc_ep);
-+ } else {
-+ is_last = 1;
-+ }
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
-+ &out_ep_regs->doeptsiz, ep->dwc_ep.num,
-+ ep->dwc_ep.is_in ? "IN" : "OUT",
-+ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
-+ deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+ }
-+
-+ /* Complete the request */
-+ if (is_last) {
-+#ifdef DWC_UTE_CFI
-+ if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+ req->actual = ep->dwc_ep.cfi_req_len - byte_count;
-+ } else {
-+#endif
-+ req->actual = ep->dwc_ep.xfer_count;
-+#ifdef DWC_UTE_CFI
-+ }
-+#endif
-+ if (req->dw_align_buf) {
-+ if (!ep->dwc_ep.is_in) {
-+ dwc_memcpy(req->buf, req->dw_align_buf, req->length);
-+ }
-+ DWC_DMA_FREE(req->length, req->dw_align_buf,
-+ req->dw_align_buf_dma);
-+ }
-+
-+ dwc_otg_request_done(ep, req, 0);
-+
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+
-+ /* If there is a request in the queue start it. */
-+ start_next_request(ep);
-+ }
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function BNA interrupt for Isochronous EPs
-+ *
-+ */
-+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+ volatile uint32_t *addr;
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dwc_otg_pcd_t *pcd = ep->pcd;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ int i;
-+
-+ dma_desc =
-+ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
-+
-+ if (dwc_ep->is_in) {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+ sts.d32 = dma_desc->status.d32;
-+ sts.b_iso_in.bs = BS_HOST_READY;
-+ dma_desc->status.d32 = sts.d32;
-+ }
-+ } else {
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+ sts.d32 = dma_desc->status.d32;
-+ sts.b_iso_out.bs = BS_HOST_READY;
-+ dma_desc->status.d32 = sts.d32;
-+ }
-+ }
-+
-+ if (dwc_ep->is_in == 0) {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
-+ num]->doepctl;
-+ } else {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+ }
-+ depctl.b.epena = 1;
-+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+}
-+
-+/**
-+ * This function sets latest iso packet information(non-PTI mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ dma_addr_t dma_addr;
-+ uint32_t offset;
-+
-+ if (ep->proc_buf_num)
-+ dma_addr = ep->dma_addr1;
-+ else
-+ dma_addr = ep->dma_addr0;
-+
-+ if (ep->is_in) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[ep->num]->dieptsiz);
-+ offset = ep->data_per_frame;
-+ } else {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->num]->doeptsiz);
-+ offset =
-+ ep->data_per_frame +
-+ (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
-+ }
-+
-+ if (!deptsiz.b.xfersize) {
-+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
-+ ep->pkt_info[ep->cur_pkt].offset =
-+ ep->cur_pkt_dma_addr - dma_addr;
-+ ep->pkt_info[ep->cur_pkt].status = 0;
-+ } else {
-+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
-+ ep->pkt_info[ep->cur_pkt].offset =
-+ ep->cur_pkt_dma_addr - dma_addr;
-+ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
-+ }
-+ ep->cur_pkt_addr += offset;
-+ ep->cur_pkt_dma_addr += offset;
-+ ep->cur_pkt++;
-+}
-+
-+/**
-+ * This function sets latest iso packet information(DDMA mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * dwc_ep)
-+{
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ iso_pkt_info_t *iso_packet;
-+ uint32_t data_per_desc;
-+ uint32_t offset;
-+ int i, j;
-+
-+ iso_packet = dwc_ep->pkt_info;
-+
-+ /** Reinit closed DMA Descriptors*/
-+ /** ISO OUT EP */
-+ if (dwc_ep->is_in == 0) {
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+ offset = 0;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->
-+ data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 -
-+ data_per_desc %
-+ 4) : 0;
-+
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso_packet_decsriptor */
-+ iso_packet->status =
-+ sts.b_iso_out.rxsts +
-+ (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+
-+ /* Received data length */
-+ if (!sts.b_iso_out.rxbytes) {
-+ iso_packet->length =
-+ data_per_desc -
-+ sts.b_iso_out.rxbytes;
-+ } else {
-+ iso_packet->length =
-+ data_per_desc -
-+ sts.b_iso_out.rxbytes + (4 -
-+ dwc_ep->data_per_frame
-+ % 4);
-+ }
-+
-+ iso_packet->offset = offset;
-+
-+ offset += data_per_desc;
-+ dma_desc++;
-+ iso_packet++;
-+ }
-+ }
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso_packet_decsriptor */
-+ iso_packet->status =
-+ sts.b_iso_out.rxsts +
-+ (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+
-+ /* Received data length */
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
-+
-+ iso_packet->offset = offset;
-+
-+ offset += data_per_desc;
-+ iso_packet++;
-+ dma_desc++;
-+ }
-+
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso_packet_decsriptor */
-+ iso_packet->status =
-+ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+ /* Received data length */
-+ if (!sts.b_iso_out.rxbytes) {
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
-+ } else {
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
-+ (4 - dwc_ep->data_per_frame % 4);
-+ }
-+
-+ iso_packet->offset = offset;
-+ } else {
-+/** ISO IN EP */
-+
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+ sts.d32 = dma_desc->status.d32;
-+
-+ /* Write status in iso packet descriptor */
-+ iso_packet->status =
-+ sts.b_iso_in.txsts +
-+ (sts.b_iso_in.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status != 0) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+
-+ }
-+ /* Bytes has been transfered */
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
-+
-+ dma_desc++;
-+ iso_packet++;
-+ }
-+
-+ sts.d32 = dma_desc->status.d32;
-+ while (sts.b_iso_in.bs == BS_DMA_BUSY) {
-+ sts.d32 = dma_desc->status.d32;
-+ }
-+
-+ /* Write status in iso packet descriptor ??? do be done with ERROR codes */
-+ iso_packet->status =
-+ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
-+ if (iso_packet->status != 0) {
-+ iso_packet->status = -DWC_E_NO_DATA;
-+ }
-+
-+ /* Bytes has been transfered */
-+ iso_packet->length =
-+ dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
-+ }
-+}
-+
-+/**
-+ * This function reinitialize DMA Descriptors for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
-+{
-+ int i, j;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ dma_addr_t dma_ad;
-+ volatile uint32_t *addr;
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ uint32_t data_per_desc;
-+
-+ if (dwc_ep->is_in == 0) {
-+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
-+ } else {
-+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+ }
-+
-+ if (dwc_ep->proc_buf_num == 0) {
-+ /** Buffer 0 descriptors setup */
-+ dma_ad = dwc_ep->dma_addr0;
-+ } else {
-+ /** Buffer 1 descriptors setup */
-+ dma_ad = dwc_ep->dma_addr1;
-+ }
-+
-+ /** Reinit closed DMA Descriptors*/
-+ /** ISO OUT EP */
-+ if (dwc_ep->is_in == 0) {
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+ sts.b_iso_out.bs = BS_HOST_READY;
-+ sts.b_iso_out.rxsts = 0;
-+ sts.b_iso_out.l = 0;
-+ sts.b_iso_out.sp = 0;
-+ sts.b_iso_out.ioc = 0;
-+ sts.b_iso_out.pid = 0;
-+ sts.b_iso_out.framenum = 0;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+ i += dwc_ep->pkt_per_frm) {
-+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->
-+ data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 -
-+ data_per_desc %
-+ 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dma_ad += data_per_desc;
-+ dma_desc++;
-+ }
-+ }
-+
-+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dma_desc++;
-+ dma_ad += data_per_desc;
-+ }
-+
-+ sts.b_iso_out.ioc = 1;
-+ sts.b_iso_out.l = dwc_ep->proc_buf_num;
-+
-+ data_per_desc =
-+ ((j + 1) * dwc_ep->maxpacket >
-+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+ j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+ data_per_desc +=
-+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+ sts.b_iso_out.rxbytes = data_per_desc;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+ } else {
-+/** ISO IN EP */
-+
-+ dma_desc =
-+ dwc_ep->iso_desc_addr +
-+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+ sts.b_iso_in.bs = BS_HOST_READY;
-+ sts.b_iso_in.txsts = 0;
-+ sts.b_iso_in.sp = 0;
-+ sts.b_iso_in.ioc = 0;
-+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
-+ sts.b_iso_in.framenum = dwc_ep->next_frame;
-+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
-+ sts.b_iso_in.l = 0;
-+
-+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ sts.b_iso_in.framenum += dwc_ep->bInterval;
-+ dma_ad += dwc_ep->data_per_frame;
-+ dma_desc++;
-+ }
-+
-+ sts.b_iso_in.ioc = 1;
-+ sts.b_iso_in.l = dwc_ep->proc_buf_num;
-+
-+ dma_desc->buf = dma_ad;
-+ dma_desc->status.d32 = sts.d32;
-+
-+ dwc_ep->next_frame =
-+ sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
-+ }
-+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+}
-+
-+/**
-+ * This function is to handle Iso EP transfer complete interrupt
-+ * in case Iso out packet was dropped
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP for wihich transfer complete was asserted
-+ *
-+ */
-+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
-+ dwc_ep_t * dwc_ep)
-+{
-+ uint32_t dma_addr;
-+ uint32_t drp_pkt;
-+ uint32_t drp_pkt_cnt;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ int i;
-+
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[dwc_ep->num]->doeptsiz);
-+
-+ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
-+ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
-+
-+ /* Setting dropped packets status */
-+ for (i = 0; i < drp_pkt_cnt; ++i) {
-+ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
-+ drp_pkt++;
-+ deptsiz.b.pktcnt--;
-+ }
-+
-+ if (deptsiz.b.pktcnt > 0) {
-+ deptsiz.b.xfersize =
-+ dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
-+ deptsiz.b.pktcnt) * dwc_ep->maxpacket;
-+ } else {
-+ deptsiz.b.xfersize = 0;
-+ deptsiz.b.pktcnt = 0;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
-+ deptsiz.d32);
-+
-+ if (deptsiz.b.pktcnt > 0) {
-+ if (dwc_ep->proc_buf_num) {
-+ dma_addr =
-+ dwc_ep->dma_addr1 + dwc_ep->xfer_len -
-+ deptsiz.b.xfersize;
-+ } else {
-+ dma_addr =
-+ dwc_ep->dma_addr0 + dwc_ep->xfer_len -
-+ deptsiz.b.xfersize;;
-+ }
-+
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
-+
-+ /** Re-enable endpoint, clear nak */
-+ depctl.d32 = 0;
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+
-+ DWC_MODIFY_REG32(&core_if->dev_if->
-+ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
-+ depctl.d32);
-+ return 0;
-+ } else {
-+ return 1;
-+ }
-+}
-+
-+/**
-+ * This function sets iso packets information(PTI mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+ int i, j;
-+ dma_addr_t dma_ad;
-+ iso_pkt_info_t *packet_info = ep->pkt_info;
-+ uint32_t offset;
-+ uint32_t frame_data;
-+ deptsiz_data_t deptsiz;
-+
-+ if (ep->proc_buf_num == 0) {
-+ /** Buffer 0 descriptors setup */
-+ dma_ad = ep->dma_addr0;
-+ } else {
-+ /** Buffer 1 descriptors setup */
-+ dma_ad = ep->dma_addr1;
-+ }
-+
-+ if (ep->is_in) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+ dieptsiz);
-+ } else {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
-+ doeptsiz);
-+ }
-+
-+ if (!deptsiz.b.xfersize) {
-+ offset = 0;
-+ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
-+ frame_data = ep->data_per_frame;
-+ for (j = 0; j < ep->pkt_per_frm; ++j) {
-+
-+ /* Packet status - is not set as initially
-+ * it is set to 0 and if packet was sent
-+ successfully, status field will remain 0*/
-+
-+ /* Bytes has been transfered */
-+ packet_info->length =
-+ (ep->maxpacket <
-+ frame_data) ? ep->maxpacket : frame_data;
-+
-+ /* Received packet offset */
-+ packet_info->offset = offset;
-+ offset += packet_info->length;
-+ frame_data -= packet_info->length;
-+
-+ packet_info++;
-+ }
-+ }
-+ return 1;
-+ } else {
-+ /* This is a workaround for in case of Transfer Complete with
-+ * PktDrpSts interrupts merging - in this case Transfer complete
-+ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
-+ * set and with DOEPTSIZ register non zero. Investigations showed,
-+ * that this happens when Out packet is dropped, but because of
-+ * interrupts merging during first interrupt handling PktDrpSts
-+ * bit is cleared and for next merged interrupts it is not reset.
-+ * In this case SW hadles the interrupt as if PktDrpSts bit is set.
-+ */
-+ if (ep->is_in) {
-+ return 1;
-+ } else {
-+ return handle_iso_out_pkt_dropped(core_if, ep);
-+ }
-+ }
-+}
-+
-+/**
-+ * This function is to handle Iso EP transfer complete interrupt
-+ *
-+ * @param pcd The PCD
-+ * @param ep The EP for which transfer complete was asserted
-+ *
-+ */
-+static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+ uint8_t is_last = 0;
-+
-+ if (ep->dwc_ep.next_frame == 0xffffffff) {
-+ DWC_WARN("Next frame is not set!\n");
-+ return;
-+ }
-+
-+ if (core_if->dma_enable) {
-+ if (core_if->dma_desc_enable) {
-+ set_ddma_iso_pkts_info(core_if, dwc_ep);
-+ reinit_ddma_iso_xfer(core_if, dwc_ep);
-+ is_last = 1;
-+ } else {
-+ if (core_if->pti_enh_enable) {
-+ if (set_iso_pkts_info(core_if, dwc_ep)) {
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+ dwc_otg_iso_ep_start_buf_transfer
-+ (core_if, dwc_ep);
-+ is_last = 1;
-+ }
-+ } else {
-+ set_current_pkt_info(core_if, dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ is_last = 1;
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+ dwc_otg_iso_ep_start_frm_transfer(core_if,
-+ dwc_ep);
-+ }
-+ }
-+ } else {
-+ set_current_pkt_info(core_if, dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ is_last = 1;
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
-+ }
-+ if (is_last)
-+ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+/**
-+ * This function handle BNA interrupt for Non Isochronous EPs
-+ *
-+ */
-+static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
-+{
-+ dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+ volatile uint32_t *addr;
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dwc_otg_pcd_t *pcd = ep->pcd;
-+ dwc_otg_dev_dma_desc_t *dma_desc;
-+ dev_dma_desc_sts_t sts = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if = ep->pcd->core_if;
-+ int i, start;
-+
-+ if (!dwc_ep->desc_cnt)
-+ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
-+ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
-+
-+ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
-+ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
-+ uint32_t doepdma;
-+ dwc_otg_dev_out_ep_regs_t *out_regs =
-+ core_if->dev_if->out_ep_regs[dwc_ep->num];
-+ doepdma = DWC_READ_REG32(&(out_regs->doepdma));
-+ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
-+ dma_desc = &(dwc_ep->desc_addr[start]);
-+ } else {
-+ start = 0;
-+ dma_desc = dwc_ep->desc_addr;
-+ }
-+
-+
-+ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+ sts.d32 = dma_desc->status.d32;
-+ sts.b.bs = BS_HOST_READY;
-+ dma_desc->status.d32 = sts.d32;
-+ }
-+
-+ if (dwc_ep->is_in == 0) {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
-+ doepctl;
-+ } else {
-+ addr =
-+ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+ }
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+ DWC_MODIFY_REG32(addr, 0, depctl.d32);
-+}
-+
-+/**
-+ * This function handles EP0 Control transfers.
-+ *
-+ * The state of the control transfers are tracked in
-+ * <code>ep0state</code>.
-+ */
-+static void handle_ep0(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+ dev_dma_desc_sts_t desc_sts;
-+ deptsiz0_data_t deptsiz;
-+ uint32_t byte_count;
-+
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
-+ print_ep0_state(pcd);
-+#endif
-+
-+// DWC_PRINTF("HANDLE EP0\n");
-+
-+ switch (pcd->ep0state) {
-+ case EP0_DISCONNECT:
-+ break;
-+
-+ case EP0_IDLE:
-+ pcd->request_config = 0;
-+
-+ pcd_setup(pcd);
-+ break;
-+
-+ case EP0_IN_DATA_PHASE:
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
-+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
-+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
-+#endif
-+
-+ if (core_if->dma_enable != 0) {
-+ /*
-+ * For EP0 we can only program 1 packet at a time so we
-+ * need to do the make calculations after each complete.
-+ * Call write_packet to make the calculations, as in
-+ * slave mode, and use those values to determine if we
-+ * can complete.
-+ */
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->in_ep_regs[0]->
-+ dieptsiz);
-+ byte_count =
-+ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
-+ } else {
-+ desc_sts =
-+ core_if->dev_if->in_desc_addr->status;
-+ byte_count =
-+ ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
-+ }
-+ ep0->dwc_ep.xfer_count += byte_count;
-+ ep0->dwc_ep.xfer_buff += byte_count;
-+ ep0->dwc_ep.dma_addr += byte_count;
-+ }
-+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
-+ } else if (ep0->dwc_ep.sent_zlp) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ ep0->dwc_ep.sent_zlp = 0;
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
-+ } else {
-+ ep0_complete_request(ep0);
-+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
-+ }
-+ break;
-+ case EP0_OUT_DATA_PHASE:
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
-+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
-+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
-+#endif
-+ if (core_if->dma_enable != 0) {
-+ if (core_if->dma_desc_enable == 0) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->
-+ dev_if->out_ep_regs[0]->
-+ doeptsiz);
-+ byte_count =
-+ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
-+ } else {
-+ desc_sts =
-+ core_if->dev_if->out_desc_addr->status;
-+ byte_count =
-+ ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
-+ }
-+ ep0->dwc_ep.xfer_count += byte_count;
-+ ep0->dwc_ep.xfer_buff += byte_count;
-+ ep0->dwc_ep.dma_addr += byte_count;
-+ }
-+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
-+ } else if (ep0->dwc_ep.sent_zlp) {
-+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+ &ep0->dwc_ep);
-+ ep0->dwc_ep.sent_zlp = 0;
-+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
-+ } else {
-+ ep0_complete_request(ep0);
-+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
-+ }
-+ break;
-+
-+ case EP0_IN_STATUS_PHASE:
-+ case EP0_OUT_STATUS_PHASE:
-+ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
-+ ep0_complete_request(ep0);
-+ pcd->ep0state = EP0_IDLE;
-+ ep0->stopped = 1;
-+ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
-+
-+ /* Prepare for more SETUP Packets */
-+ if (core_if->dma_enable) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+ break;
-+
-+ case EP0_STALL:
-+ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
-+ break;
-+ }
-+#ifdef DEBUG_EP0
-+ print_ep0_state(pcd);
-+#endif
-+}
-+
-+/**
-+ * Restart transfer
-+ */
-+static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if;
-+ dwc_otg_dev_if_t *dev_if;
-+ deptsiz_data_t dieptsiz = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ ep = get_in_ep(pcd, epnum);
-+
-+#ifdef DWC_EN_ISOC
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ return;
-+ }
-+#endif /* DWC_EN_ISOC */
-+
-+ core_if = GET_CORE_IF(pcd);
-+ dev_if = core_if->dev_if;
-+
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
-+
-+ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
-+ " stopped=%d\n", ep->dwc_ep.xfer_buff,
-+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
-+ /*
-+ * If xfersize is 0 and pktcnt in not 0, resend the last packet.
-+ */
-+ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
-+ ep->dwc_ep.start_xfer_buff != 0) {
-+ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
-+ ep->dwc_ep.xfer_count = 0;
-+ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
-+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
-+ } else {
-+ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
-+ /* convert packet size to dwords. */
-+ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
-+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
-+ }
-+ ep->stopped = 0;
-+ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
-+ "xfer_len=%0x stopped=%d\n",
-+ ep->dwc_ep.xfer_buff,
-+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
-+ ep->stopped);
-+ if (epnum == 0) {
-+ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
-+ } else {
-+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
-+ }
-+ }
-+}
-+
-+/*
-+ * This function create new nextep sequnce based on Learn Queue.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void predict_nextep_seq( dwc_otg_core_if_t * core_if)
-+{
-+ dwc_otg_device_global_regs_t *dev_global_regs =
-+ core_if->dev_if->dev_global_regs;
-+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
-+ /* Number of Token Queue Registers */
-+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
-+ dtknq1_data_t dtknqr1;
-+ uint32_t in_tkn_epnums[4];
-+ uint8_t seqnum[MAX_EPS_CHANNELS];
-+ uint8_t intkn_seq[TOKEN_Q_DEPTH];
-+ grstctl_t resetctl = {.d32 = 0 };
-+ uint8_t temp;
-+ int ndx = 0;
-+ int start = 0;
-+ int end = 0;
-+ int sort_done = 0;
-+ int i = 0;
-+ volatile uint32_t *addr = &dev_global_regs->dtknqr1;
-+
-+
-+ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
-+
-+ /* Read the DTKNQ Registers */
-+ for (i = 0; i < DTKNQ_REG_CNT; i++) {
-+ in_tkn_epnums[i] = DWC_READ_REG32(addr);
-+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
-+ in_tkn_epnums[i]);
-+ if (addr == &dev_global_regs->dvbusdis) {
-+ addr = &dev_global_regs->dtknqr3_dthrctl;
-+ } else {
-+ ++addr;
-+ }
-+
-+ }
-+
-+ /* Copy the DTKNQR1 data to the bit field. */
-+ dtknqr1.d32 = in_tkn_epnums[0];
-+ if (dtknqr1.b.wrap_bit) {
-+ ndx = dtknqr1.b.intknwptr;
-+ end = ndx -1;
-+ if (end < 0)
-+ end = TOKEN_Q_DEPTH -1;
-+ } else {
-+ ndx = 0;
-+ end = dtknqr1.b.intknwptr -1;
-+ if (end < 0)
-+ end = 0;
-+ }
-+ start = ndx;
-+
-+ /* Fill seqnum[] by initial values: EP number + 31 */
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ seqnum[i] = i +31;
-+ }
-+
-+ /* Fill intkn_seq[] from in_tkn_epnums[0] */
-+ for (i=0; i < 6; i++)
-+ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
-+
-+ if (TOKEN_Q_DEPTH > 6) {
-+ /* Fill intkn_seq[] from in_tkn_epnums[1] */
-+ for (i=6; i < 14; i++)
-+ intkn_seq[i] =
-+ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
-+ }
-+
-+ if (TOKEN_Q_DEPTH > 14) {
-+ /* Fill intkn_seq[] from in_tkn_epnums[1] */
-+ for (i=14; i < 22; i++)
-+ intkn_seq[i] =
-+ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
-+ }
-+
-+ if (TOKEN_Q_DEPTH > 22) {
-+ /* Fill intkn_seq[] from in_tkn_epnums[1] */
-+ for (i=22; i < 30; i++)
-+ intkn_seq[i] =
-+ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
-+ start, end);
-+ for (i=0; i<TOKEN_Q_DEPTH; i++)
-+ DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
-+
-+ /* Update seqnum based on intkn_seq[] */
-+ i = 0;
-+ do {
-+ seqnum[intkn_seq[ndx]] = i;
-+ ndx++;
-+ i++;
-+ if (ndx == TOKEN_Q_DEPTH)
-+ ndx = 0;
-+ } while ( i < TOKEN_Q_DEPTH );
-+
-+ /* Mark non active EP's in seqnum[] by 0xff */
-+ for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
-+ if (core_if->nextep_seq[i] == 0xff )
-+ seqnum[i] = 0xff;
-+ }
-+
-+ /* Sort seqnum[] */
-+ sort_done = 0;
-+ while (!sort_done) {
-+ sort_done = 1;
-+ for (i=0; i<core_if->dev_if->num_in_eps; i++) {
-+ if (seqnum[i] > seqnum[i+1]) {
-+ temp = seqnum[i];
-+ seqnum[i] = seqnum[i+1];
-+ seqnum[i+1] = temp;
-+ sort_done = 0;
-+ }
-+ }
-+ }
-+
-+ ndx = start + seqnum[0];
-+ if (ndx >= TOKEN_Q_DEPTH)
-+ ndx = ndx % TOKEN_Q_DEPTH;
-+ core_if->first_in_nextep_seq = intkn_seq[ndx];
-+
-+ /* Update seqnum[] by EP numbers */
-+ for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
-+ ndx = start + i;
-+ if (seqnum[i] < 31) {
-+ ndx = start + seqnum[i];
-+ if (ndx >= TOKEN_Q_DEPTH)
-+ ndx = ndx % TOKEN_Q_DEPTH;
-+ seqnum[i] = intkn_seq[ndx];
-+ } else {
-+ if (seqnum[i] < 0xff) {
-+ seqnum[i] = seqnum[i] - 31;
-+ } else {
-+ break;
-+ }
-+ }
-+ }
-+
-+ /* Update nextep_seq[] based on seqnum[] */
-+ for (i=0; i<core_if->dev_if->num_in_eps; i++) {
-+ if (seqnum[i] != 0xff) {
-+ if (seqnum[i+1] != 0xff) {
-+ core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
-+ } else {
-+ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
-+ break;
-+ }
-+ } else {
-+ break;
-+ }
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+ __func__, core_if->first_in_nextep_seq);
-+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
-+ }
-+
-+ /* Flush the Learning Queue */
-+ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
-+ resetctl.b.intknqflsh = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+
-+}
-+
-+/**
-+ * handle the IN EP disable interrupt.
-+ */
-+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ deptsiz_data_t dieptsiz = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ gintmsk_data_t gintmsk_data;
-+ depctl_data_t depctl;
-+ uint32_t diepdma;
-+ uint32_t remain_to_transfer = 0;
-+ uint8_t i;
-+ uint32_t xfer_size;
-+
-+ ep = get_in_ep(pcd, epnum);
-+ dwc_ep = &ep->dwc_ep;
-+
-+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
-+ complete_ep(ep);
-+ return;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+
-+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
-+ dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
-+
-+ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
-+ if (ep->stopped) {
-+ if (core_if->en_multiple_tx_fifo)
-+ /* Flush the Tx FIFO */
-+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
-+ /* Clear the Global IN NP NAK */
-+ dctl.d32 = 0;
-+ dctl.b.cgnpinnak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+ /* Restart the transaction */
-+ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
-+ restart_transfer(pcd, epnum);
-+ }
-+ } else {
-+ /* Restart the transaction */
-+ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
-+ restart_transfer(pcd, epnum);
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
-+ }
-+ return;
-+ }
-+
-+ if (core_if->start_predict > 2) { // NP IN EP
-+ core_if->start_predict--;
-+ return;
-+ }
-+
-+ core_if->start_predict--;
-+
-+ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
-+
-+ predict_nextep_seq(core_if);
-+
-+ /* Update all active IN EP's NextEP field based of nextep_seq[] */
-+ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
-+ depctl.b.nextep = core_if->nextep_seq[i];
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+ }
-+ }
-+ /* Flush Shared NP TxFIFO */
-+ dwc_otg_flush_tx_fifo(core_if, 0);
-+ /* Rewind buffers */
-+ if (!core_if->dma_desc_enable) {
-+ i = core_if->first_in_nextep_seq;
-+ do {
-+ ep = get_in_ep(pcd, i);
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
-+ if (xfer_size > ep->dwc_ep.maxxfer)
-+ xfer_size = ep->dwc_ep.maxxfer;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (dieptsiz.b.pktcnt != 0) {
-+ if (xfer_size == 0) {
-+ remain_to_transfer = 0;
-+ } else {
-+ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
-+ remain_to_transfer =
-+ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
-+ } else {
-+ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
-+ + (xfer_size % ep->dwc_ep.maxpacket);
-+ }
-+ }
-+ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
-+ dieptsiz.b.xfersize = remain_to_transfer;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
-+ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
-+ }
-+ i = core_if->nextep_seq[i];
-+ } while (i != core_if->first_in_nextep_seq);
-+ } else { // dma_desc_enable
-+ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
-+ }
-+
-+ /* Restart transfers in predicted sequences */
-+ i = core_if->first_in_nextep_seq;
-+ do {
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (dieptsiz.b.pktcnt != 0) {
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ depctl.b.epena = 1;
-+ depctl.b.cnak = 1;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+ }
-+ i = core_if->nextep_seq[i];
-+ } while (i != core_if->first_in_nextep_seq);
-+
-+ /* Clear the global non-periodic IN NAK handshake */
-+ dctl.d32 = 0;
-+ dctl.b.cgnpinnak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+ /* Unmask EP Mismatch interrupt */
-+ gintmsk_data.d32 = 0;
-+ gintmsk_data.b.epmismatch = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
-+
-+ core_if->start_predict = 0;
-+
-+ }
-+}
-+
-+/**
-+ * Handler for the IN EP timeout handshake interrupt.
-+ */
-+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+
-+#ifdef DEBUG
-+ deptsiz_data_t dieptsiz = {.d32 = 0 };
-+ uint32_t num = 0;
-+#endif
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dwc_otg_pcd_ep_t *ep;
-+
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ ep = get_in_ep(pcd, epnum);
-+
-+ /* Disable the NP Tx Fifo Empty Interrrupt */
-+ if (!core_if->dma_enable) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+ }
-+ /** @todo NGS Check EP type.
-+ * Implement for Periodic EPs */
-+ /*
-+ * Non-periodic EP
-+ */
-+ /* Enable the Global IN NAK Effective Interrupt */
-+ intr_mask.b.ginnakeff = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
-+
-+ /* Set Global IN NAK */
-+ dctl.b.sgnpinnak = 1;
-+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+ ep->stopped = 1;
-+
-+#ifdef DEBUG
-+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
-+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
-+ dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
-+#endif
-+
-+#ifdef DISABLE_PERIODIC_EP
-+ /*
-+ * Set the NAK bit for this EP to
-+ * start the disable process.
-+ */
-+ diepctl.d32 = 0;
-+ diepctl.b.snak = 1;
-+ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
-+ diepctl.d32);
-+ ep->disabling = 1;
-+ ep->stopped = 1;
-+#endif
-+}
-+
-+/**
-+ * Handler for the IN EP NAK interrupt.
-+ */
-+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ diepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.nak = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ diepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP Babble interrupt.
-+ */
-+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
-+ "OUT EP Babble");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.babble = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP NAK interrupt.
-+ */
-+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.nak = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP NYET interrupt.
-+ */
-+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
-+ const uint32_t epnum)
-+{
-+ /** @todo implement ISR */
-+ dwc_otg_core_if_t *core_if;
-+ doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
-+ core_if = GET_CORE_IF(pcd);
-+ intr_mask.b.nyet = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+ doepeachintmsk[epnum], intr_mask.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ intr_mask.d32, 0);
-+ }
-+
-+ return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that an IN EP has a pending Interrupt.
-+ * The sequence for handling the IN EP interrupt is shown below:
-+ * -# Read the Device All Endpoint Interrupt register
-+ * -# Repeat the following for each IN EP interrupt bit set (from
-+ * LSB to MSB).
-+ * -# Read the Device Endpoint Interrupt (DIEPINTn) register
-+ * -# If "Transfer Complete" call the request complete function
-+ * -# If "Endpoint Disabled" complete the EP disable procedure.
-+ * -# If "AHB Error Interrupt" log error
-+ * -# If "Time-out Handshake" log error
-+ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
-+ * FIFO.
-+ * -# If "IN Token EP Mismatch" (disable, this is handled by EP
-+ * Mismatch Interrupt)
-+ */
-+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
-+{
-+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
-+do { \
-+ diepint_data_t diepint = {.d32=0}; \
-+ diepint.b.__intr = 1; \
-+ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
-+ diepint.d32); \
-+} while (0)
-+
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+ diepint_data_t diepint = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ uint32_t ep_intr;
-+ uint32_t epnum = 0;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
-+
-+ /* Read in the device interrupt bits */
-+ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
-+
-+ /* Service the Device IN interrupts for each endpoint */
-+ while (ep_intr) {
-+ if (ep_intr & 0x1) {
-+ uint32_t empty_msk;
-+ /* Get EP pointer */
-+ ep = get_in_ep(pcd, epnum);
-+ dwc_ep = &ep->dwc_ep;
-+
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+ empty_msk =
-+ DWC_READ_REG32(&dev_if->
-+ dev_global_regs->dtknqr4_fifoemptymsk);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
-+ epnum, empty_msk, depctl.d32);
-+
-+ DWC_DEBUGPL(DBG_PCD,
-+ "EP%d-%s: type=%d, mps=%d\n",
-+ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
-+ dwc_ep->type, dwc_ep->maxpacket);
-+
-+ diepint.d32 =
-+ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
-+
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP %d Interrupt Register - 0x%x\n", epnum,
-+ diepint.d32);
-+ /* Transfer complete */
-+ if (diepint.b.xfercompl) {
-+ /* Disable the NP Tx FIFO Empty
-+ * Interrupt */
-+ if (core_if->en_multiple_tx_fifo == 0) {
-+ intr_mask.b.nptxfempty = 1;
-+ DWC_MODIFY_REG32
-+ (&core_if->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+ } else {
-+ /* Disable the Tx FIFO Empty Interrupt for this EP */
-+ uint32_t fifoemptymsk =
-+ 0x1 << dwc_ep->num;
-+ DWC_MODIFY_REG32(&core_if->
-+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+ fifoemptymsk, 0);
-+ }
-+ /* Clear the bit in DIEPINTn for this interrupt */
-+ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
-+
-+ /* Complete the transfer */
-+ if (epnum == 0) {
-+ handle_ep0(pcd);
-+ }
-+#ifdef DWC_EN_ISOC
-+ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (!ep->stopped)
-+ complete_iso_ep(pcd, ep);
-+ }
-+#endif /* DWC_EN_ISOC */
-+#ifdef DWC_UTE_PER_IO
-+ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (!ep->stopped)
-+ complete_xiso_ep(ep);
-+ }
-+#endif /* DWC_UTE_PER_IO */
-+ else {
-+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
-+ dwc_ep->bInterval > 1) {
-+ dwc_ep->frame_num += dwc_ep->bInterval;
-+ if (dwc_ep->frame_num > 0x3FFF)
-+ {
-+ dwc_ep->frm_overrun = 1;
-+ dwc_ep->frame_num &= 0x3FFF;
-+ } else
-+ dwc_ep->frm_overrun = 0;
-+ }
-+ complete_ep(ep);
-+ if(diepint.b.nak)
-+ CLEAR_IN_EP_INTR(core_if, epnum, nak);
-+ }
-+ }
-+ /* Endpoint disable */
-+ if (diepint.b.epdisabled) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
-+ epnum);
-+ handle_in_ep_disable_intr(pcd, epnum);
-+
-+ /* Clear the bit in DIEPINTn for this interrupt */
-+ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
-+ }
-+ /* AHB Error */
-+ if (diepint.b.ahberr) {
-+ DWC_ERROR("EP%d IN AHB Error\n", epnum);
-+ /* Clear the bit in DIEPINTn for this interrupt */
-+ CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
-+ }
-+ /* TimeOUT Handshake (non-ISOC IN EPs) */
-+ if (diepint.b.timeout) {
-+ DWC_ERROR("EP%d IN Time-out\n", epnum);
-+ handle_in_ep_timeout_intr(pcd, epnum);
-+
-+ CLEAR_IN_EP_INTR(core_if, epnum, timeout);
-+ }
-+ /** IN Token received with TxF Empty */
-+ if (diepint.b.intktxfemp) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d IN TKN TxFifo Empty\n",
-+ epnum);
-+ if (!ep->stopped && epnum != 0) {
-+
-+ diepmsk_data_t diepmsk = {.d32 = 0 };
-+ diepmsk.b.intktxfemp = 1;
-+
-+ if (core_if->multiproc_int_enable) {
-+ DWC_MODIFY_REG32
-+ (&dev_if->dev_global_regs->diepeachintmsk
-+ [epnum], diepmsk.d32, 0);
-+ } else {
-+ DWC_MODIFY_REG32
-+ (&dev_if->dev_global_regs->diepmsk,
-+ diepmsk.d32, 0);
-+ }
-+ } else if (core_if->dma_desc_enable
-+ && epnum == 0
-+ && pcd->ep0state ==
-+ EP0_OUT_STATUS_PHASE) {
-+ // EP0 IN set STALL
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs
-+ [epnum]->diepctl);
-+
-+ /* set the disable and stall bits */
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ }
-+ depctl.b.stall = 1;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs
-+ [epnum]->diepctl,
-+ depctl.d32);
-+ }
-+ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
-+ }
-+ /** IN Token Received with EP mismatch */
-+ if (diepint.b.intknepmis) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d IN TKN EP Mismatch\n", epnum);
-+ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
-+ }
-+ /** IN Endpoint NAK Effective */
-+ if (diepint.b.inepnakeff) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d IN EP NAK Effective\n",
-+ epnum);
-+ /* Periodic EP */
-+ if (ep->disabling) {
-+ depctl.d32 = 0;
-+ depctl.b.snak = 1;
-+ depctl.b.epdis = 1;
-+ DWC_MODIFY_REG32(&dev_if->in_ep_regs
-+ [epnum]->diepctl,
-+ depctl.d32,
-+ depctl.d32);
-+ }
-+ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
-+
-+ }
-+
-+ /** IN EP Tx FIFO Empty Intr */
-+ if (diepint.b.emptyintr) {
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP%d Tx FIFO Empty Intr \n",
-+ epnum);
-+ write_empty_tx_fifo(pcd, epnum);
-+
-+ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
-+
-+ }
-+
-+ /** IN EP BNA Intr */
-+ if (diepint.b.bna) {
-+ CLEAR_IN_EP_INTR(core_if, epnum, bna);
-+ if (core_if->dma_desc_enable) {
-+#ifdef DWC_EN_ISOC
-+ if (dwc_ep->type ==
-+ DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * This checking is performed to prevent first "false" BNA
-+ * handling occuring right after reconnect
-+ */
-+ if (dwc_ep->next_frame !=
-+ 0xffffffff)
-+ dwc_otg_pcd_handle_iso_bna(ep);
-+ } else
-+#endif /* DWC_EN_ISOC */
-+ {
-+ dwc_otg_pcd_handle_noniso_bna(ep);
-+ }
-+ }
-+ }
-+ /* NAK Interrutp */
-+ if (diepint.b.nak) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
-+ epnum);
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ depctl_data_t depctl;
-+ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
-+ ep->dwc_ep.frame_num = core_if->frame_num;
-+ if (ep->dwc_ep.bInterval > 1) {
-+ depctl.d32 = 0;
-+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+ if (ep->dwc_ep.frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ depctl.b.setd0pid = 0;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ depctl.b.setd1pid = 0;
-+ }
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
-+ }
-+ start_next_request(ep);
-+ }
-+ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
-+ if (dwc_ep->frame_num > 0x3FFF) {
-+ dwc_ep->frm_overrun = 1;
-+ dwc_ep->frame_num &= 0x3FFF;
-+ } else
-+ dwc_ep->frm_overrun = 0;
-+ }
-+
-+ CLEAR_IN_EP_INTR(core_if, epnum, nak);
-+ }
-+ }
-+ epnum++;
-+ ep_intr >>= 1;
-+ }
-+
-+ return 1;
-+#undef CLEAR_IN_EP_INTR
-+}
-+
-+/**
-+ * This interrupt indicates that an OUT EP has a pending Interrupt.
-+ * The sequence for handling the OUT EP interrupt is shown below:
-+ * -# Read the Device All Endpoint Interrupt register
-+ * -# Repeat the following for each OUT EP interrupt bit set (from
-+ * LSB to MSB).
-+ * -# Read the Device Endpoint Interrupt (DOEPINTn) register
-+ * -# If "Transfer Complete" call the request complete function
-+ * -# If "Endpoint Disabled" complete the EP disable procedure.
-+ * -# If "AHB Error Interrupt" log error
-+ * -# If "Setup Phase Done" process Setup Packet (See Standard USB
-+ * Command Processing)
-+ */
-+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
-+{
-+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
-+do { \
-+ doepint_data_t doepint = {.d32=0}; \
-+ doepint.b.__intr = 1; \
-+ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
-+ doepint.d32); \
-+} while (0)
-+
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ uint32_t ep_intr;
-+ doepint_data_t doepint = {.d32 = 0 };
-+ uint32_t epnum = 0;
-+ dwc_otg_pcd_ep_t *ep;
-+ dwc_ep_t *dwc_ep;
-+ dctl_data_t dctl = {.d32 = 0 };
-+ gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
-+
-+ /* Read in the device interrupt bits */
-+ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
-+
-+ while (ep_intr) {
-+ if (ep_intr & 0x1) {
-+ /* Get EP pointer */
-+ ep = get_out_ep(pcd, epnum);
-+ dwc_ep = &ep->dwc_ep;
-+
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP%d-%s: type=%d, mps=%d\n",
-+ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
-+ dwc_ep->type, dwc_ep->maxpacket);
-+#endif
-+ doepint.d32 =
-+ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
-+ /* Moved this interrupt upper due to core deffect of asserting
-+ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
-+ if (doepint.b.stsphsercvd) {
-+ deptsiz0_data_t deptsiz;
-+ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doeptsiz);
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a
-+ && core_if->dma_enable
-+ && core_if->dma_desc_enable == 0
-+ && doepint.b.xfercompl
-+ && deptsiz.b.xfersize == 24) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum,
-+ xfercompl);
-+ doepint.b.xfercompl = 0;
-+ ep0_out_start(core_if, pcd);
-+ }
-+ if ((core_if->dma_desc_enable) ||
-+ (core_if->dma_enable
-+ && core_if->snpsid >=
-+ OTG_CORE_REV_3_00a)) {
-+ do_setup_in_status_phase(pcd);
-+ }
-+ }
-+ /* Transfer complete */
-+ if (doepint.b.xfercompl) {
-+
-+ if (epnum == 0) {
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
-+ doepint.d32);
-+ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
-+
-+ if (core_if->snpsid >= OTG_CORE_REV_3_00a
-+ && core_if->dma_enable == 0) {
-+ doepint_data_t doepint;
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doepint);
-+ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+ goto exit_xfercompl;
-+ }
-+ }
-+ /* In case of DDMA look at SR bit to go to the Data Stage */
-+ if (core_if->dma_desc_enable) {
-+ dev_dma_desc_sts_t status = {.d32 = 0};
-+ if (pcd->ep0state == EP0_IDLE) {
-+ status.d32 = core_if->dev_if->setup_desc_addr[core_if->
-+ dev_if->setup_desc_index]->status.d32;
-+ if(pcd->data_terminated) {
-+ pcd->data_terminated = 0;
-+ status.d32 = core_if->dev_if->out_desc_addr->status.d32;
-+ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
-+ }
-+ if (status.b.sr) {
-+ if (doepint.b.setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
-+ /* Already started data stage, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ /* Prepare for more setup packets */
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
-+ pcd->ep0state == EP0_IN_DATA_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP0_IDLE SR=1 setup=0 new setup comes\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+ } else {
-+ dwc_otg_pcd_request_t *req;
-+ dev_dma_desc_sts_t status = {.d32 = 0};
-+ diepint_data_t diepint0;
-+ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+
-+ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
-+ DWC_ERROR("EP0 is stalled/disconnected\n");
-+ }
-+
-+ /* Clear IN xfercompl if set */
-+ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
-+ || pcd->ep0state == EP0_IN_DATA_PHASE)) {
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint, diepint0.d32);
-+ }
-+
-+ status.d32 = core_if->dev_if->setup_desc_addr[core_if->
-+ dev_if->setup_desc_index]->status.d32;
-+
-+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
-+ && (pcd->ep0state == EP0_OUT_DATA_PHASE))
-+ status.d32 = core_if->dev_if->out_desc_addr->status.d32;
-+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
-+ status.d32 = core_if->dev_if->
-+ out_desc_addr->status.d32;
-+
-+ if (status.b.sr) {
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
-+ } else {
-+ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
-+ pcd->ep0state == EP0_OUT_DATA_PHASE) {
-+ /* Read arrived setup packet from req->buf */
-+ dwc_memcpy(&pcd->setup_pkt->req,
-+ req->buf + ep->dwc_ep.xfer_count, 8);
-+ }
-+ req->actual = ep->dwc_ep.xfer_count;
-+ dwc_otg_request_done(ep, req, -ECONNRESET);
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+ }
-+ pcd->ep0state = EP0_IDLE;
-+ if (doepint.b.setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
-+ /* Data stage started, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ /* Prepare for setup packets if ep0in was enabled*/
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+ }
-+ }
-+ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
-+ && core_if->dma_desc_enable == 0) {
-+ doepint_data_t doepint_temp = {.d32 = 0};
-+ deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->dwc_ep.num]->doepint);
-+ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->dwc_ep.num]->doeptsiz);
-+ if (pcd->ep0state == EP0_IDLE) {
-+ if (doepint_temp.b.sr) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+ }
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doepint);
-+ if (doeptsize0.b.supcnt == 3) {
-+ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
-+ ep->dwc_ep.stp_rollover = 1;
-+ }
-+ if (doepint.b.setup) {
-+retry:
-+ /* Already started data stage, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ ep->dwc_ep.stp_rollover = 0;
-+ /* Prepare for more setup packets */
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
-+ pcd->ep0state == EP0_IN_DATA_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_ANY,
-+ "EP0_IDLE SR=1 setup=0 new setup comes\n");
-+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[0]->doepint);
-+ if(doepint.b.setup)
-+ goto retry;
-+ ep0_out_start(core_if, pcd);
-+ }
-+ } else {
-+ dwc_otg_pcd_request_t *req;
-+ diepint_data_t diepint0 = {.d32 = 0};
-+ doepint_data_t doepint_temp = {.d32 = 0};
-+ depctl_data_t diepctl0;
-+ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepctl);
-+
-+ if (pcd->ep0state == EP0_IN_DATA_PHASE
-+ || pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ if (diepint0.b.xfercompl) {
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint, diepint0.d32);
-+ }
-+ if (diepctl0.b.epena) {
-+ diepint_data_t diepint = {.d32 = 0};
-+ diepctl0.b.snak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepctl, diepctl0.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+ } while (!diepint.b.inepnakeff);
-+ diepint.b.inepnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint, diepint.d32);
-+ diepctl0.d32 = 0;
-+ diepctl0.b.epdis = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
-+ diepctl0.d32);
-+ do {
-+ dwc_udelay(10);
-+ diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ in_ep_regs[0]->diepint);
-+ } while (!diepint.b.epdisabled);
-+ diepint.b.epdisabled = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
-+ diepint.d32);
-+ }
-+ }
-+ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[ep->dwc_ep.num]->doepint);
-+ if (doepint_temp.b.sr) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
-+ } else {
-+ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
-+ pcd->ep0state == EP0_OUT_DATA_PHASE) {
-+ /* Read arrived setup packet from req->buf */
-+ dwc_memcpy(&pcd->setup_pkt->req,
-+ req->buf + ep->dwc_ep.xfer_count, 8);
-+ }
-+ req->actual = ep->dwc_ep.xfer_count;
-+ dwc_otg_request_done(ep, req, -ECONNRESET);
-+ ep->dwc_ep.start_xfer_buff = 0;
-+ ep->dwc_ep.xfer_buff = 0;
-+ ep->dwc_ep.xfer_len = 0;
-+ }
-+ pcd->ep0state = EP0_IDLE;
-+ if (doepint.b.setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
-+ /* Data stage started, clear setup */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+ doepint.b.setup = 0;
-+ handle_ep0(pcd);
-+ /* Prepare for setup packets if ep0in was enabled*/
-+ if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+ ep0_out_start(core_if, pcd);
-+ }
-+ goto exit_xfercompl;
-+ } else {
-+ /* Prepare for more setup packets */
-+ DWC_DEBUGPL(DBG_PCDV,
-+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
-+ ep0_out_start(core_if, pcd);
-+ }
-+ }
-+ }
-+ }
-+ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
-+ handle_ep0(pcd);
-+exit_xfercompl:
-+ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
-+ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
-+ } else {
-+ if (core_if->dma_desc_enable == 0
-+ || pcd->ep0state != EP0_IDLE)
-+ handle_ep0(pcd);
-+ }
-+#ifdef DWC_EN_ISOC
-+ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (doepint.b.pktdrpsts == 0) {
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if,
-+ epnum,
-+ xfercompl);
-+ complete_iso_ep(pcd, ep);
-+ } else {
-+
-+ doepint_data_t doepint = {.d32 = 0 };
-+ doepint.b.xfercompl = 1;
-+ doepint.b.pktdrpsts = 1;
-+ DWC_WRITE_REG32
-+ (&core_if->dev_if->out_ep_regs
-+ [epnum]->doepint,
-+ doepint.d32);
-+ if (handle_iso_out_pkt_dropped
-+ (core_if, dwc_ep)) {
-+ complete_iso_ep(pcd,
-+ ep);
-+ }
-+ }
-+#endif /* DWC_EN_ISOC */
-+#ifdef DWC_UTE_PER_IO
-+ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
-+ if (!ep->stopped)
-+ complete_xiso_ep(ep);
-+#endif /* DWC_UTE_PER_IO */
-+ } else {
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if, epnum,
-+ xfercompl);
-+
-+ if (core_if->core_params->dev_out_nak) {
-+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
-+ pcd->core_if->ep_xfer_info[epnum].state = 0;
-+#ifdef DEBUG
-+ print_memory_payload(pcd, dwc_ep);
-+#endif
-+ }
-+ complete_ep(ep);
-+ }
-+
-+ }
-+
-+ /* Endpoint disable */
-+ if (doepint.b.epdisabled) {
-+
-+ /* Clear the bit in DOEPINTn for this interrupt */
-+ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
-+ if (core_if->core_params->dev_out_nak) {
-+#ifdef DEBUG
-+ print_memory_payload(pcd, dwc_ep);
-+#endif
-+ /* In case of timeout condition */
-+ if (core_if->ep_xfer_info[epnum].state == 2) {
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dctl);
-+ dctl.b.cgoutnak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+ /* Unmask goutnakeff interrupt which was masked
-+ * during handle nak out interrupt */
-+ gintmsk.b.goutnakeff = 1;
-+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+ 0, gintmsk.d32);
-+
-+ complete_ep(ep);
-+ }
-+ }
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
-+ {
-+ dctl_data_t dctl;
-+ gintmsk_data_t intr_mask = {.d32 = 0};
-+ dwc_otg_pcd_request_t *req = 0;
-+
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ dev_global_regs->dctl);
-+ dctl.b.cgoutnak = 1;
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+
-+ intr_mask.d32 = 0;
-+ intr_mask.b.incomplisoout = 1;
-+
-+ /* Get any pending requests */
-+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+ req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+ if (!req) {
-+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+ } else {
-+ dwc_otg_request_done(ep, req, 0);
-+ start_next_request(ep);
-+ }
-+ } else {
-+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+ }
-+ }
-+ }
-+ /* AHB Error */
-+ if (doepint.b.ahberr) {
-+ DWC_ERROR("EP%d OUT AHB Error\n", epnum);
-+ DWC_ERROR("EP%d DEPDMA=0x%08x \n",
-+ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
-+ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
-+ }
-+ /* Setup Phase Done (contorl EPs) */
-+ if (doepint.b.setup) {
-+#ifdef DEBUG_EP0
-+ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
-+#endif
-+ CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+
-+ handle_ep0(pcd);
-+ }
-+
-+ /** OUT EP BNA Intr */
-+ if (doepint.b.bna) {
-+ CLEAR_OUT_EP_INTR(core_if, epnum, bna);
-+ if (core_if->dma_desc_enable) {
-+#ifdef DWC_EN_ISOC
-+ if (dwc_ep->type ==
-+ DWC_OTG_EP_TYPE_ISOC) {
-+ /*
-+ * This checking is performed to prevent first "false" BNA
-+ * handling occuring right after reconnect
-+ */
-+ if (dwc_ep->next_frame !=
-+ 0xffffffff)
-+ dwc_otg_pcd_handle_iso_bna(ep);
-+ } else
-+#endif /* DWC_EN_ISOC */
-+ {
-+ dwc_otg_pcd_handle_noniso_bna(ep);
-+ }
-+ }
-+ }
-+ /* Babble Interrupt */
-+ if (doepint.b.babble) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
-+ epnum);
-+ handle_out_ep_babble_intr(pcd, epnum);
-+
-+ CLEAR_OUT_EP_INTR(core_if, epnum, babble);
-+ }
-+ if (doepint.b.outtknepdis) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
-+ disabled\n",epnum);
-+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ doepmsk_data_t doepmsk = {.d32 = 0};
-+ ep->dwc_ep.frame_num = core_if->frame_num;
-+ if (ep->dwc_ep.bInterval > 1) {
-+ depctl_data_t depctl;
-+ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+ out_ep_regs[epnum]->doepctl);
-+ if (ep->dwc_ep.frame_num & 0x1) {
-+ depctl.b.setd1pid = 1;
-+ depctl.b.setd0pid = 0;
-+ } else {
-+ depctl.b.setd0pid = 1;
-+ depctl.b.setd1pid = 0;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->
-+ out_ep_regs[epnum]->doepctl, depctl.d32);
-+ }
-+ start_next_request(ep);
-+ doepmsk.b.outtknepdis = 1;
-+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+ doepmsk.d32, 0);
-+ }
-+ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
-+ }
-+
-+ /* NAK Interrutp */
-+ if (doepint.b.nak) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
-+ handle_out_ep_nak_intr(pcd, epnum);
-+
-+ CLEAR_OUT_EP_INTR(core_if, epnum, nak);
-+ }
-+ /* NYET Interrutp */
-+ if (doepint.b.nyet) {
-+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
-+ handle_out_ep_nyet_intr(pcd, epnum);
-+
-+ CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
-+ }
-+ }
-+
-+ epnum++;
-+ ep_intr >>= 1;
-+ }
-+
-+ return 1;
-+
-+#undef CLEAR_OUT_EP_INTR
-+}
-+static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
-+{
-+ int retval = 0;
-+ if(!frm_overrun && curr_fr >= trgt_fr)
-+ retval = 1;
-+ else if (frm_overrun
-+ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
-+ retval = 1;
-+ return retval;
-+}
-+/**
-+ * Incomplete ISO IN Transfer Interrupt.
-+ * This interrupt indicates one of the following conditions occurred
-+ * while transmitting an ISOC transaction.
-+ * - Corrupted IN Token for ISOC EP.
-+ * - Packet not complete in FIFO.
-+ * The follow actions will be taken:
-+ * -# Determine the EP
-+ * -# Set incomplete flag in dwc_ep structure
-+ * -# Disable EP; when "Endpoint Disabled" interrupt is received
-+ * Flush FIFO
-+ */
-+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
-+{
-+ gintsts_data_t gintsts;
-+
-+#ifdef DWC_EN_ISOC
-+ dwc_otg_dev_if_t *dev_if;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dsts_data_t dsts = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep;
-+ int i;
-+
-+ dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+ for (i = 1; i <= dev_if->num_in_eps; ++i) {
-+ dwc_ep = &pcd->in_ep[i].dwc_ep;
-+ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+
-+ if (depctl.b.epdis && deptsiz.d32) {
-+ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+
-+ dsts.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ dev_global_regs->dsts);
-+ dwc_ep->next_frame = dsts.b.soffn;
-+
-+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
-+ (pcd),
-+ dwc_ep);
-+ }
-+ }
-+ }
-+
-+#else
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep;
-+ dwc_otg_dev_if_t *dev_if;
-+ int i;
-+ dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
-+
-+ for (i = 1; i <= dev_if->num_in_eps; ++i) {
-+ dwc_ep = &pcd->in_ep[i-1].dwc_ep;
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
-+ dwc_ep->frm_overrun))
-+ {
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ depctl.b.snak = 1;
-+ depctl.b.epdis = 1;
-+ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
-+ }
-+ }
-+ }
-+
-+ /*intr_mask.b.incomplisoin = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0); */
-+#endif //DWC_EN_ISOC
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.incomplisoin = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * Incomplete ISO OUT Transfer Interrupt.
-+ *
-+ * This interrupt indicates that the core has dropped an ISO OUT
-+ * packet. The following conditions can be the cause:
-+ * - FIFO Full, the entire packet would not fit in the FIFO.
-+ * - CRC Error
-+ * - Corrupted Token
-+ * The follow actions will be taken:
-+ * -# Determine the EP
-+ * -# Set incomplete flag in dwc_ep structure
-+ * -# Read any data from the FIFO
-+ * -# Disable EP. When "Endpoint Disabled" interrupt is received
-+ * re-enable EP.
-+ */
-+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
-+{
-+
-+ gintsts_data_t gintsts;
-+
-+#ifdef DWC_EN_ISOC
-+ dwc_otg_dev_if_t *dev_if;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dsts_data_t dsts = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep;
-+ int i;
-+
-+ dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+ for (i = 1; i <= dev_if->num_out_eps; ++i) {
-+ dwc_ep = &pcd->in_ep[i].dwc_ep;
-+ if (pcd->out_ep[i].dwc_ep.active &&
-+ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
-+ depctl.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+
-+ if (depctl.b.epdis && deptsiz.d32) {
-+ set_current_pkt_info(GET_CORE_IF(pcd),
-+ &pcd->out_ep[i].dwc_ep);
-+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+ dwc_ep->cur_pkt = 0;
-+ dwc_ep->proc_buf_num =
-+ (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+
-+ if (dwc_ep->proc_buf_num) {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff1;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr1;
-+ } else {
-+ dwc_ep->cur_pkt_addr =
-+ dwc_ep->xfer_buff0;
-+ dwc_ep->cur_pkt_dma_addr =
-+ dwc_ep->dma_addr0;
-+ }
-+
-+ }
-+
-+ dsts.d32 =
-+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+ dev_global_regs->dsts);
-+ dwc_ep->next_frame = dsts.b.soffn;
-+
-+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
-+ (pcd),
-+ dwc_ep);
-+ }
-+ }
-+ }
-+#else
-+ /** @todo implement ISR */
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ dwc_otg_core_if_t *core_if;
-+ deptsiz_data_t deptsiz = {.d32 = 0 };
-+ depctl_data_t depctl = {.d32 = 0 };
-+ dctl_data_t dctl = {.d32 = 0 };
-+ dwc_ep_t *dwc_ep = NULL;
-+ int i;
-+ core_if = GET_CORE_IF(pcd);
-+
-+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+ dwc_ep = &pcd->out_ep[i].dwc_ep;
-+ depctl.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
-+ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
-+ core_if->dev_if->isoc_ep = dwc_ep;
-+ deptsiz.d32 =
-+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
-+ break;
-+ }
-+ }
-+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+ if (!intr_mask.b.goutnakeff) {
-+ /* Unmask it */
-+ intr_mask.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
-+ }
-+ if (!gintsts.b.goutnakeff) {
-+ dctl.b.sgoutnak = 1;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+
-+ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
-+ if (depctl.b.epena) {
-+ depctl.b.epdis = 1;
-+ depctl.b.snak = 1;
-+ }
-+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
-+
-+ intr_mask.d32 = 0;
-+ intr_mask.b.incomplisoout = 1;
-+
-+#endif /* DWC_EN_ISOC */
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.incomplisoout = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * This function handles the Global IN NAK Effective interrupt.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ depctl_data_t diepctl = {.d32 = 0 };
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+ int i;
-+
-+ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
-+
-+ /* Disable all active IN EPs */
-+ for (i = 0; i <= dev_if->num_in_eps; i++) {
-+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
-+ if (core_if->start_predict > 0)
-+ core_if->start_predict++;
-+ diepctl.b.epdis = 1;
-+ diepctl.b.snak = 1;
-+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
-+ }
-+ }
-+
-+
-+ /* Disable the Global IN NAK Effective Interrupt */
-+ intr_mask.b.ginnakeff = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.ginnakeff = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * OUT NAK Effective.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+ gintmsk_data_t intr_mask = {.d32 = 0 };
-+ gintsts_data_t gintsts;
-+ depctl_data_t doepctl;
-+ int i;
-+
-+ /* Disable the Global OUT NAK Effective Interrupt */
-+ intr_mask.b.goutnakeff = 1;
-+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+ intr_mask.d32, 0);
-+
-+ /* If DEV OUT NAK enabled*/
-+ if (pcd->core_if->core_params->dev_out_nak) {
-+ /* Run over all out endpoints to determine the ep number on
-+ * which the timeout has happened
-+ */
-+ for (i = 0; i <= dev_if->num_out_eps; i++) {
-+ if ( pcd->core_if->ep_xfer_info[i].state == 2 )
-+ break;
-+ }
-+ if (i > dev_if->num_out_eps) {
-+ dctl_data_t dctl;
-+ dctl.d32 =
-+ DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
-+ dctl.b.cgoutnak = 1;
-+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
-+ dctl.d32);
-+ goto out;
-+ }
-+
-+ /* Disable the endpoint */
-+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+ if (doepctl.b.epena) {
-+ doepctl.b.epdis = 1;
-+ doepctl.b.snak = 1;
-+ }
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
-+ return 1;
-+ }
-+ /* We come here from Incomplete ISO OUT handler */
-+ if (dev_if->isoc_ep) {
-+ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
-+ uint32_t epnum = dwc_ep->num;
-+ doepint_data_t doepint;
-+ doepint.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
-+ dev_if->isoc_ep = NULL;
-+ doepctl.d32 =
-+ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
-+ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
-+ if (doepctl.b.epena) {
-+ doepctl.b.epdis = 1;
-+ doepctl.b.snak = 1;
-+ }
-+ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
-+ doepctl.d32);
-+ return 1;
-+ } else
-+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
-+ "Global OUT NAK Effective\n");
-+
-+out:
-+ /* Clear interrupt */
-+ gintsts.d32 = 0;
-+ gintsts.b.goutnakeff = 1;
-+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+ gintsts.d32);
-+
-+ return 1;
-+}
-+
-+/**
-+ * PCD interrupt handler.
-+ *
-+ * The PCD handles the device interrupts. Many conditions can cause a
-+ * device interrupt. When an interrupt occurs, the device interrupt
-+ * service routine determines the cause of the interrupt and
-+ * dispatches handling to the appropriate function. These interrupt
-+ * handling functions are described below.
-+ *
-+ * All interrupt registers are processed from LSB to MSB.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
-+{
-+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+#ifdef VERBOSE
-+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+#endif
-+ gintsts_data_t gintr_status;
-+ int32_t retval = 0;
-+
-+ /* Exit from ISR if core is hibernated */
-+ if (core_if->hibernation_suspend == 1) {
-+ return retval;
-+ }
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
-+ __func__,
-+ DWC_READ_REG32(&global_regs->gintsts),
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+#endif
-+
-+ if (dwc_otg_is_device_mode(core_if)) {
-+ DWC_SPINLOCK(pcd->lock);
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
-+ __func__,
-+ DWC_READ_REG32(&global_regs->gintsts),
-+ DWC_READ_REG32(&global_regs->gintmsk));
-+#endif
-+
-+ gintr_status.d32 = dwc_otg_read_core_intr(core_if);
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
-+ __func__, gintr_status.d32);
-+
-+ if (gintr_status.b.sofintr) {
-+ retval |= dwc_otg_pcd_handle_sof_intr(pcd);
-+ }
-+ if (gintr_status.b.rxstsqlvl) {
-+ retval |=
-+ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
-+ }
-+ if (gintr_status.b.nptxfempty) {
-+ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
-+ }
-+ if (gintr_status.b.goutnakeff) {
-+ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
-+ }
-+ if (gintr_status.b.i2cintr) {
-+ retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
-+ }
-+ if (gintr_status.b.erlysuspend) {
-+ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
-+ }
-+ if (gintr_status.b.usbreset) {
-+ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
-+ }
-+ if (gintr_status.b.enumdone) {
-+ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
-+ }
-+ if (gintr_status.b.isooutdrop) {
-+ retval |=
-+ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
-+ (pcd);
-+ }
-+ if (gintr_status.b.eopframe) {
-+ retval |=
-+ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
-+ }
-+ if (gintr_status.b.inepint) {
-+ if (!core_if->multiproc_int_enable) {
-+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
-+ }
-+ }
-+ if (gintr_status.b.outepintr) {
-+ if (!core_if->multiproc_int_enable) {
-+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
-+ }
-+ }
-+ if (gintr_status.b.epmismatch) {
-+ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
-+ }
-+ if (gintr_status.b.fetsusp) {
-+ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
-+ }
-+ if (gintr_status.b.ginnakeff) {
-+ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
-+ }
-+ if (gintr_status.b.incomplisoin) {
-+ retval |=
-+ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
-+ }
-+ if (gintr_status.b.incomplisoout) {
-+ retval |=
-+ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
-+ }
-+
-+ /* In MPI mode Device Endpoints interrupts are asserted
-+ * without setting outepintr and inepint bits set, so these
-+ * Interrupt handlers are called without checking these bit-fields
-+ */
-+ if (core_if->multiproc_int_enable) {
-+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
-+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
-+ }
-+#ifdef VERBOSE
-+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
-+ DWC_READ_REG32(&global_regs->gintsts));
-+#endif
-+ DWC_SPINUNLOCK(pcd->lock);
-+ }
-+ return retval;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,1360 @@
-+ /* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
-+ * $Revision: #21 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+/** @file
-+ * This file implements the Peripheral Controller Driver.
-+ *
-+ * The Peripheral Controller Driver (PCD) is responsible for
-+ * translating requests from the Function Driver into the appropriate
-+ * actions on the DWC_otg controller. It isolates the Function Driver
-+ * from the specifics of the controller by providing an API to the
-+ * Function Driver.
-+ *
-+ * The Peripheral Controller Driver for Linux will implement the
-+ * Gadget API, so that the existing Gadget drivers can be used.
-+ * (Gadget Driver is the Linux terminology for a Function Driver.)
-+ *
-+ * The Linux Gadget API is defined in the header file
-+ * <code><linux/usb_gadget.h></code>. The USB EP operations API is
-+ * defined in the structure <code>usb_ep_ops</code> and the USB
-+ * Controller API is defined in the structure
-+ * <code>usb_gadget_ops</code>.
-+ *
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_dbg.h"
-+
-+extern bool fiq_enable;
-+
-+static struct gadget_wrapper {
-+ dwc_otg_pcd_t *pcd;
-+
-+ struct usb_gadget gadget;
-+ struct usb_gadget_driver *driver;
-+
-+ struct usb_ep ep0;
-+ struct usb_ep in_ep[16];
-+ struct usb_ep out_ep[16];
-+
-+} *gadget_wrapper;
-+
-+/* Display the contents of the buffer */
-+extern void dump_msg(const u8 * buf, unsigned int length);
-+/**
-+ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
-+ * if the endpoint is not found
-+ */
-+static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
-+{
-+ int i;
-+ if (pcd->ep0.priv == handle) {
-+ return &pcd->ep0;
-+ }
-+
-+ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
-+ if (pcd->in_ep[i].priv == handle)
-+ return &pcd->in_ep[i];
-+ if (pcd->out_ep[i].priv == handle)
-+ return &pcd->out_ep[i];
-+ }
-+
-+ return NULL;
-+}
-+
-+/* USB Endpoint Operations */
-+/*
-+ * The following sections briefly describe the behavior of the Gadget
-+ * API endpoint operations implemented in the DWC_otg driver
-+ * software. Detailed descriptions of the generic behavior of each of
-+ * these functions can be found in the Linux header file
-+ * include/linux/usb_gadget.h.
-+ *
-+ * The Gadget API provides wrapper functions for each of the function
-+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
-+ * function, which then calls the underlying PCD function. The
-+ * following sections are named according to the wrapper
-+ * functions. Within each section, the corresponding DWC_otg PCD
-+ * function name is specified.
-+ *
-+ */
-+
-+/**
-+ * This function is called by the Gadget Driver for each EP to be
-+ * configured for the current configuration (SET_CONFIGURATION).
-+ *
-+ * This function initializes the dwc_otg_ep_t data structure, and then
-+ * calls dwc_otg_ep_activate.
-+ */
-+static int ep_enable(struct usb_ep *usb_ep,
-+ const struct usb_endpoint_descriptor *ep_desc)
-+{
-+ int retval;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
-+
-+ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
-+ DWC_WARN("%s, bad ep or descriptor\n", __func__);
-+ return -EINVAL;
-+ }
-+ if (usb_ep == &gadget_wrapper->ep0) {
-+ DWC_WARN("%s, bad ep(0)\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ /* Check FIFO size? */
-+ if (!ep_desc->wMaxPacketSize) {
-+ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
-+ return -ERANGE;
-+ }
-+
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_WARN("%s, bogus device state\n", __func__);
-+ return -ESHUTDOWN;
-+ }
-+
-+ /* Delete after check - MAS */
-+#if 0
-+ nat = (uint32_t) ep_desc->wMaxPacketSize;
-+ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
-+ nat = (nat >> 11) & 0x03;
-+ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
-+#endif
-+ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
-+ (const uint8_t *)ep_desc,
-+ (void *)usb_ep);
-+ if (retval) {
-+ DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
-+ return -EINVAL;
-+ }
-+
-+ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function is called when an EP is disabled due to disconnect or
-+ * change in configuration. Any pending requests will terminate with a
-+ * status of -ESHUTDOWN.
-+ *
-+ * This function modifies the dwc_otg_ep_t data structure for this EP,
-+ * and then calls dwc_otg_ep_deactivate.
-+ */
-+static int ep_disable(struct usb_ep *usb_ep)
-+{
-+ int retval;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
-+ if (!usb_ep) {
-+ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
-+ usb_ep ? usb_ep->name : NULL);
-+ return -EINVAL;
-+ }
-+
-+ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
-+ if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function allocates a request object to use with the specified
-+ * endpoint.
-+ *
-+ * @param ep The endpoint to be used with with the request
-+ * @param gfp_flags the GFP_* flags to use.
-+ */
-+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
-+ gfp_t gfp_flags)
-+{
-+ struct usb_request *usb_req;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
-+ if (0 == ep) {
-+ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
-+ return 0;
-+ }
-+ usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
-+ if (0 == usb_req) {
-+ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
-+ return 0;
-+ }
-+ memset(usb_req, 0, sizeof(*usb_req));
-+ usb_req->dma = DWC_DMA_ADDR_INVALID;
-+
-+ return usb_req;
-+}
-+
-+/**
-+ * This function frees a request object.
-+ *
-+ * @param ep The endpoint associated with the request
-+ * @param req The request being freed
-+ */
-+static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
-+{
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
-+
-+ if (0 == ep || 0 == req) {
-+ DWC_WARN("%s() %s\n", __func__,
-+ "Invalid ep or req argument!\n");
-+ return;
-+ }
-+
-+ kfree(req);
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+/**
-+ * This function allocates an I/O buffer to be used for a transfer
-+ * to/from the specified endpoint.
-+ *
-+ * @param usb_ep The endpoint to be used with with the request
-+ * @param bytes The desired number of bytes for the buffer
-+ * @param dma Pointer to the buffer's DMA address; must be valid
-+ * @param gfp_flags the GFP_* flags to use.
-+ * @return address of a new buffer or null is buffer could not be allocated.
-+ */
-+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
-+ dma_addr_t * dma, gfp_t gfp_flags)
-+{
-+ void *buf;
-+ dwc_otg_pcd_t *pcd = 0;
-+
-+ pcd = gadget_wrapper->pcd;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
-+ dma, gfp_flags);
-+
-+ /* Check dword alignment */
-+ if ((bytes & 0x3UL) != 0) {
-+ DWC_WARN("%s() Buffer size is not a multiple of"
-+ "DWORD size (%d)", __func__, bytes);
-+ }
-+
-+ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
-+
-+ /* Check dword alignment */
-+ if (((int)buf & 0x3UL) != 0) {
-+ DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
-+ __func__, buf);
-+ }
-+
-+ return buf;
-+}
-+
-+/**
-+ * This function frees an I/O buffer that was allocated by alloc_buffer.
-+ *
-+ * @param usb_ep the endpoint associated with the buffer
-+ * @param buf address of the buffer
-+ * @param dma The buffer's DMA address
-+ * @param bytes The number of bytes of the buffer
-+ */
-+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
-+ dma_addr_t dma, unsigned bytes)
-+{
-+ dwc_otg_pcd_t *pcd = 0;
-+
-+ pcd = gadget_wrapper->pcd;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
-+
-+ dma_free_coherent(NULL, bytes, buf, dma);
-+}
-+#endif
-+
-+/**
-+ * This function is used to submit an I/O Request to an EP.
-+ *
-+ * - When the request completes the request's completion callback
-+ * is called to return the request to the driver.
-+ * - An EP, except control EPs, may have multiple requests
-+ * pending.
-+ * - Once submitted the request cannot be examined or modified.
-+ * - Each request is turned into one or more packets.
-+ * - A BULK EP can queue any amount of data; the transfer is
-+ * packetized.
-+ * - Zero length Packets are specified with the request 'zero'
-+ * flag.
-+ */
-+static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
-+ gfp_t gfp_flags)
-+{
-+ dwc_otg_pcd_t *pcd;
-+ struct dwc_otg_pcd_ep *ep = NULL;
-+ int retval = 0, is_isoc_ep = 0;
-+ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
-+ __func__, usb_ep, usb_req, gfp_flags);
-+
-+ if (!usb_req || !usb_req->complete || !usb_req->buf) {
-+ DWC_WARN("bad params\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ return -EINVAL;
-+ }
-+
-+ pcd = gadget_wrapper->pcd;
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
-+ gadget_wrapper->gadget.speed);
-+ DWC_WARN("bogus device state\n");
-+ return -ESHUTDOWN;
-+ }
-+
-+ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
-+ usb_ep->name, usb_req, usb_req->length, usb_req->buf);
-+
-+ usb_req->status = -EINPROGRESS;
-+ usb_req->actual = 0;
-+
-+ ep = ep_from_handle(pcd, usb_ep);
-+ if (ep == NULL)
-+ is_isoc_ep = 0;
-+ else
-+ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ dma_addr = usb_req->dma;
-+#else
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
-+ struct device *dev = NULL;
-+
-+ if (otg_dev != NULL)
-+ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
-+
-+ if (usb_req->length != 0 &&
-+ usb_req->dma == DWC_DMA_ADDR_INVALID) {
-+ dma_addr = dma_map_single(dev, usb_req->buf,
-+ usb_req->length,
-+ ep->dwc_ep.is_in ?
-+ DMA_TO_DEVICE:
-+ DMA_FROM_DEVICE);
-+ }
-+ }
-+#endif
-+
-+#ifdef DWC_UTE_PER_IO
-+ if (is_isoc_ep == 1) {
-+ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
-+ usb_req->length, usb_req->zero, usb_req,
-+ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
-+ if (retval)
-+ return -EINVAL;
-+
-+ return 0;
-+ }
-+#endif
-+ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
-+ usb_req->length, usb_req->zero, usb_req,
-+ gfp_flags == GFP_ATOMIC ? 1 : 0);
-+ if (retval) {
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * This function cancels an I/O request from an EP.
-+ */
-+static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
-+{
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
-+
-+ if (!usb_ep || !usb_req) {
-+ DWC_WARN("bad argument\n");
-+ return -EINVAL;
-+ }
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_WARN("bogus device state\n");
-+ return -ESHUTDOWN;
-+ }
-+ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * usb_ep_set_halt stalls an endpoint.
-+ *
-+ * usb_ep_clear_halt clears an endpoint halt and resets its data
-+ * toggle.
-+ *
-+ * Both of these functions are implemented with the same underlying
-+ * function. The behavior depends on the value argument.
-+ *
-+ * @param[in] usb_ep the Endpoint to halt or clear halt.
-+ * @param[in] value
-+ * - 0 means clear_halt.
-+ * - 1 means set_halt,
-+ * - 2 means clear stall lock flag.
-+ * - 3 means set stall lock flag.
-+ */
-+static int ep_halt(struct usb_ep *usb_ep, int value)
-+{
-+ int retval = 0;
-+
-+ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
-+
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ return -EINVAL;
-+ }
-+
-+ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
-+ if (retval == -DWC_E_AGAIN) {
-+ return -EAGAIN;
-+ } else if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
-+#if 0
-+/**
-+ * ep_wedge: sets the halt feature and ignores clear requests
-+ *
-+ * @usb_ep: the endpoint being wedged
-+ *
-+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
-+ * requests. If the gadget driver clears the halt status, it will
-+ * automatically unwedge the endpoint.
-+ *
-+ * Returns zero on success, else negative errno. *
-+ * Check usb_ep_set_wedge() at "usb_gadget.h" for details
-+ */
-+static int ep_wedge(struct usb_ep *usb_ep)
-+{
-+ int retval = 0;
-+
-+ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
-+
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ return -EINVAL;
-+ }
-+
-+ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
-+ if (retval == -DWC_E_AGAIN) {
-+ retval = -EAGAIN;
-+ } else if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+#endif
-+
-+#ifdef DWC_EN_ISOC
-+/**
-+ * This function is used to submit an ISOC Transfer Request to an EP.
-+ *
-+ * - Every time a sync period completes the request's completion callback
-+ * is called to provide data to the gadget driver.
-+ * - Once submitted the request cannot be modified.
-+ * - Each request is turned into periodic data packets untill ISO
-+ * Transfer is stopped..
-+ */
-+static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
-+ gfp_t gfp_flags)
-+{
-+ int retval = 0;
-+
-+ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
-+ DWC_WARN("bad params\n");
-+ return -EINVAL;
-+ }
-+
-+ if (!usb_ep) {
-+ DWC_PRINTF("bad params\n");
-+ return -EINVAL;
-+ }
-+
-+ req->status = -EINPROGRESS;
-+
-+ retval =
-+ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
-+ req->buf1, req->dma0, req->dma1,
-+ req->sync_frame, req->data_pattern_frame,
-+ req->data_per_frame,
-+ req->
-+ flags & USB_REQ_ISO_ASAP ? -1 :
-+ req->start_frame, req->buf_proc_intrvl,
-+ req, gfp_flags == GFP_ATOMIC ? 1 : 0);
-+
-+ if (retval) {
-+ return -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+/**
-+ * This function stops ISO EP Periodic Data Transfer.
-+ */
-+static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
-+{
-+ int retval = 0;
-+ if (!usb_ep) {
-+ DWC_WARN("bad ep\n");
-+ }
-+
-+ if (!gadget_wrapper->driver ||
-+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
-+ gadget_wrapper->gadget.speed);
-+ DWC_WARN("bogus device state\n");
-+ }
-+
-+ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
-+ if (retval) {
-+ retval = -EINVAL;
-+ }
-+
-+ return retval;
-+}
-+
-+static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
-+ int packets, gfp_t gfp_flags)
-+{
-+ struct usb_iso_request *pReq = NULL;
-+ uint32_t req_size;
-+
-+ req_size = sizeof(struct usb_iso_request);
-+ req_size +=
-+ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
-+
-+ pReq = kmalloc(req_size, gfp_flags);
-+ if (!pReq) {
-+ DWC_WARN("Can't allocate Iso Request\n");
-+ return 0;
-+ }
-+ pReq->iso_packet_desc0 = (void *)(pReq + 1);
-+
-+ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
-+
-+ return pReq;
-+}
-+
-+static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
-+{
-+ kfree(req);
-+}
-+
-+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
-+ .ep_ops = {
-+ .enable = ep_enable,
-+ .disable = ep_disable,
-+
-+ .alloc_request = dwc_otg_pcd_alloc_request,
-+ .free_request = dwc_otg_pcd_free_request,
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ .alloc_buffer = dwc_otg_pcd_alloc_buffer,
-+ .free_buffer = dwc_otg_pcd_free_buffer,
-+#endif
-+
-+ .queue = ep_queue,
-+ .dequeue = ep_dequeue,
-+
-+ .set_halt = ep_halt,
-+ .fifo_status = 0,
-+ .fifo_flush = 0,
-+ },
-+ .iso_ep_start = iso_ep_start,
-+ .iso_ep_stop = iso_ep_stop,
-+ .alloc_iso_request = alloc_iso_request,
-+ .free_iso_request = free_iso_request,
-+};
-+
-+#else
-+
-+ int (*enable) (struct usb_ep *ep,
-+ const struct usb_endpoint_descriptor *desc);
-+ int (*disable) (struct usb_ep *ep);
-+
-+ struct usb_request *(*alloc_request) (struct usb_ep *ep,
-+ gfp_t gfp_flags);
-+ void (*free_request) (struct usb_ep *ep, struct usb_request *req);
-+
-+ int (*queue) (struct usb_ep *ep, struct usb_request *req,
-+ gfp_t gfp_flags);
-+ int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
-+
-+ int (*set_halt) (struct usb_ep *ep, int value);
-+ int (*set_wedge) (struct usb_ep *ep);
-+
-+ int (*fifo_status) (struct usb_ep *ep);
-+ void (*fifo_flush) (struct usb_ep *ep);
-+static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
-+ .enable = ep_enable,
-+ .disable = ep_disable,
-+
-+ .alloc_request = dwc_otg_pcd_alloc_request,
-+ .free_request = dwc_otg_pcd_free_request,
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+ .alloc_buffer = dwc_otg_pcd_alloc_buffer,
-+ .free_buffer = dwc_otg_pcd_free_buffer,
-+#else
-+ /* .set_wedge = ep_wedge, */
-+ .set_wedge = NULL, /* uses set_halt instead */
-+#endif
-+
-+ .queue = ep_queue,
-+ .dequeue = ep_dequeue,
-+
-+ .set_halt = ep_halt,
-+ .fifo_status = 0,
-+ .fifo_flush = 0,
-+
-+};
-+
-+#endif /* _EN_ISOC_ */
-+/* Gadget Operations */
-+/**
-+ * The following gadget operations will be implemented in the DWC_otg
-+ * PCD. Functions in the API that are not described below are not
-+ * implemented.
-+ *
-+ * The Gadget API provides wrapper functions for each of the function
-+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the
-+ * wrapper function, which then calls the underlying PCD function. The
-+ * following sections are named according to the wrapper functions
-+ * (except for ioctl, which doesn't have a wrapper function). Within
-+ * each section, the corresponding DWC_otg PCD function name is
-+ * specified.
-+ *
-+ */
-+
-+/**
-+ *Gets the USB Frame number of the last SOF.
-+ */
-+static int get_frame_number(struct usb_gadget *gadget)
-+{
-+ struct gadget_wrapper *d;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
-+
-+ if (gadget == 0) {
-+ return -ENODEV;
-+ }
-+
-+ d = container_of(gadget, struct gadget_wrapper, gadget);
-+ return dwc_otg_pcd_get_frame_number(d->pcd);
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+static int test_lpm_enabled(struct usb_gadget *gadget)
-+{
-+ struct gadget_wrapper *d;
-+
-+ d = container_of(gadget, struct gadget_wrapper, gadget);
-+
-+ return dwc_otg_pcd_is_lpm_enabled(d->pcd);
-+}
-+#endif
-+
-+/**
-+ * Initiates Session Request Protocol (SRP) to wakeup the host if no
-+ * session is in progress. If a session is already in progress, but
-+ * the device is suspended, remote wakeup signaling is started.
-+ *
-+ */
-+static int wakeup(struct usb_gadget *gadget)
-+{
-+ struct gadget_wrapper *d;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
-+
-+ if (gadget == 0) {
-+ return -ENODEV;
-+ } else {
-+ d = container_of(gadget, struct gadget_wrapper, gadget);
-+ }
-+ dwc_otg_pcd_wakeup(d->pcd);
-+ return 0;
-+}
-+
-+static const struct usb_gadget_ops dwc_otg_pcd_ops = {
-+ .get_frame = get_frame_number,
-+ .wakeup = wakeup,
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+ .lpm_support = test_lpm_enabled,
-+#endif
-+ // current versions must always be self-powered
-+};
-+
-+static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
-+{
-+ int retval = -DWC_E_NOT_SUPPORTED;
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
-+ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
-+ (struct usb_ctrlrequest
-+ *)bytes);
-+ }
-+
-+ if (retval == -ENOTSUPP) {
-+ retval = -DWC_E_NOT_SUPPORTED;
-+ } else if (retval < 0) {
-+ retval = -DWC_E_INVALID;
-+ }
-+
-+ return retval;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int proc_buf_num)
-+{
-+ int i, packet_count;
-+ struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
-+ struct usb_iso_request *iso_req = req_handle;
-+
-+ if (proc_buf_num) {
-+ iso_packet = iso_req->iso_packet_desc1;
-+ } else {
-+ iso_packet = iso_req->iso_packet_desc0;
-+ }
-+ packet_count =
-+ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
-+ for (i = 0; i < packet_count; ++i) {
-+ int status;
-+ int actual;
-+ int offset;
-+ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
-+ i, &status, &actual, &offset);
-+ switch (status) {
-+ case -DWC_E_NO_DATA:
-+ status = -ENODATA;
-+ break;
-+ default:
-+ if (status) {
-+ DWC_PRINTF("unknown status in isoc packet\n");
-+ }
-+
-+ }
-+ iso_packet[i].status = status;
-+ iso_packet[i].offset = offset;
-+ iso_packet[i].actual_length = actual;
-+ }
-+
-+ iso_req->status = 0;
-+ iso_req->process_buffer(ep_handle, iso_req);
-+
-+ return 0;
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+#ifdef DWC_UTE_PER_IO
-+/**
-+ * Copy the contents of the extended request to the Linux usb_request's
-+ * extended part and call the gadget's completion.
-+ *
-+ * @param pcd Pointer to the pcd structure
-+ * @param ep_handle Void pointer to the usb_ep structure
-+ * @param req_handle Void pointer to the usb_request structure
-+ * @param status Request status returned from the portable logic
-+ * @param ereq_port Void pointer to the extended request structure
-+ * created in the the portable part that contains the
-+ * results of the processed iso packets.
-+ */
-+static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status, void *ereq_port)
-+{
-+ struct dwc_ute_iso_req_ext *ereqorg = NULL;
-+ struct dwc_iso_xreq_port *ereqport = NULL;
-+ struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
-+ int i;
-+ struct usb_request *req;
-+ //struct dwc_ute_iso_packet_descriptor *
-+ //int status = 0;
-+
-+ req = (struct usb_request *)req_handle;
-+ ereqorg = &req->ext_req;
-+ ereqport = (struct dwc_iso_xreq_port *)ereq_port;
-+ desc_org = ereqorg->per_io_frame_descs;
-+
-+ if (req && req->complete) {
-+ /* Copy the request data from the portable logic to our request */
-+ for (i = 0; i < ereqport->pio_pkt_count; i++) {
-+ desc_org[i].actual_length =
-+ ereqport->per_io_frame_descs[i].actual_length;
-+ desc_org[i].status =
-+ ereqport->per_io_frame_descs[i].status;
-+ }
-+
-+ switch (status) {
-+ case -DWC_E_SHUTDOWN:
-+ req->status = -ESHUTDOWN;
-+ break;
-+ case -DWC_E_RESTART:
-+ req->status = -ECONNRESET;
-+ break;
-+ case -DWC_E_INVALID:
-+ req->status = -EINVAL;
-+ break;
-+ case -DWC_E_TIMEOUT:
-+ req->status = -ETIMEDOUT;
-+ break;
-+ default:
-+ req->status = status;
-+ }
-+
-+ /* And call the gadget's completion */
-+ req->complete(ep_handle, req);
-+ }
-+
-+ return 0;
-+}
-+#endif /* DWC_UTE_PER_IO */
-+
-+static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+ void *req_handle, int32_t status, uint32_t actual)
-+{
-+ struct usb_request *req = (struct usb_request *)req_handle;
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
-+ struct dwc_otg_pcd_ep *ep = NULL;
-+#endif
-+
-+ if (req && req->complete) {
-+ switch (status) {
-+ case -DWC_E_SHUTDOWN:
-+ req->status = -ESHUTDOWN;
-+ break;
-+ case -DWC_E_RESTART:
-+ req->status = -ECONNRESET;
-+ break;
-+ case -DWC_E_INVALID:
-+ req->status = -EINVAL;
-+ break;
-+ case -DWC_E_TIMEOUT:
-+ req->status = -ETIMEDOUT;
-+ break;
-+ default:
-+ req->status = status;
-+
-+ }
-+
-+ req->actual = actual;
-+ DWC_SPINUNLOCK(pcd->lock);
-+ req->complete(ep_handle, req);
-+ DWC_SPINLOCK(pcd->lock);
-+ }
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
-+ ep = ep_from_handle(pcd, ep_handle);
-+ if (GET_CORE_IF(pcd)->dma_enable) {
-+ if (req->length != 0) {
-+ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
-+ struct device *dev = NULL;
-+
-+ if (otg_dev != NULL)
-+ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
-+
-+ dma_unmap_single(dev, req->dma, req->length,
-+ ep->dwc_ep.is_in ?
-+ DMA_TO_DEVICE: DMA_FROM_DEVICE);
-+ }
-+ }
-+#endif
-+
-+ return 0;
-+}
-+
-+static int _connect(dwc_otg_pcd_t * pcd, int speed)
-+{
-+ gadget_wrapper->gadget.speed = speed;
-+ return 0;
-+}
-+
-+static int _disconnect(dwc_otg_pcd_t * pcd)
-+{
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
-+ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
-+ }
-+ return 0;
-+}
-+
-+static int _resume(dwc_otg_pcd_t * pcd)
-+{
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
-+ gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
-+ }
-+
-+ return 0;
-+}
-+
-+static int _suspend(dwc_otg_pcd_t * pcd)
-+{
-+ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
-+ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * This function updates the otg values in the gadget structure.
-+ */
-+static int _hnp_changed(dwc_otg_pcd_t * pcd)
-+{
-+
-+ if (!gadget_wrapper->gadget.is_otg)
-+ return 0;
-+
-+ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
-+ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
-+ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
-+ return 0;
-+}
-+
-+static int _reset(dwc_otg_pcd_t * pcd)
-+{
-+ return 0;
-+}
-+
-+#ifdef DWC_UTE_CFI
-+static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
-+{
-+ int retval = -DWC_E_INVALID;
-+ if (gadget_wrapper->driver->cfi_feature_setup) {
-+ retval =
-+ gadget_wrapper->driver->
-+ cfi_feature_setup(&gadget_wrapper->gadget,
-+ (struct cfi_usb_ctrlrequest *)cfi_req);
-+ }
-+
-+ return retval;
-+}
-+#endif
-+
-+static const struct dwc_otg_pcd_function_ops fops = {
-+ .complete = _complete,
-+#ifdef DWC_EN_ISOC
-+ .isoc_complete = _isoc_complete,
-+#endif
-+ .setup = _setup,
-+ .disconnect = _disconnect,
-+ .connect = _connect,
-+ .resume = _resume,
-+ .suspend = _suspend,
-+ .hnp_changed = _hnp_changed,
-+ .reset = _reset,
-+#ifdef DWC_UTE_CFI
-+ .cfi_setup = _cfi_setup,
-+#endif
-+#ifdef DWC_UTE_PER_IO
-+ .xisoc_complete = _xisoc_complete,
-+#endif
-+};
-+
-+/**
-+ * This function is the top level PCD interrupt handler.
-+ */
-+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
-+{
-+ dwc_otg_pcd_t *pcd = dev;
-+ int32_t retval = IRQ_NONE;
-+
-+ retval = dwc_otg_pcd_handle_intr(pcd);
-+ if (retval != 0) {
-+ S3C2410X_CLEAR_EINTPEND();
-+ }
-+ return IRQ_RETVAL(retval);
-+}
-+
-+/**
-+ * This function initialized the usb_ep structures to there default
-+ * state.
-+ *
-+ * @param d Pointer on gadget_wrapper.
-+ */
-+void gadget_add_eps(struct gadget_wrapper *d)
-+{
-+ static const char *names[] = {
-+
-+ "ep0",
-+ "ep1in",
-+ "ep2in",
-+ "ep3in",
-+ "ep4in",
-+ "ep5in",
-+ "ep6in",
-+ "ep7in",
-+ "ep8in",
-+ "ep9in",
-+ "ep10in",
-+ "ep11in",
-+ "ep12in",
-+ "ep13in",
-+ "ep14in",
-+ "ep15in",
-+ "ep1out",
-+ "ep2out",
-+ "ep3out",
-+ "ep4out",
-+ "ep5out",
-+ "ep6out",
-+ "ep7out",
-+ "ep8out",
-+ "ep9out",
-+ "ep10out",
-+ "ep11out",
-+ "ep12out",
-+ "ep13out",
-+ "ep14out",
-+ "ep15out"
-+ };
-+
-+ int i;
-+ struct usb_ep *ep;
-+ int8_t dev_endpoints;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
-+
-+ INIT_LIST_HEAD(&d->gadget.ep_list);
-+ d->gadget.ep0 = &d->ep0;
-+ d->gadget.speed = USB_SPEED_UNKNOWN;
-+
-+ INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
-+
-+ /**
-+ * Initialize the EP0 structure.
-+ */
-+ ep = &d->ep0;
-+
-+ /* Init the usb_ep structure. */
-+ ep->name = names[0];
-+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+ /**
-+ * @todo NGS: What should the max packet size be set to
-+ * here? Before EP type is set?
-+ */
-+ ep->maxpacket = MAX_PACKET_SIZE;
-+ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
-+
-+ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+
-+ /**
-+ * Initialize the EP structures.
-+ */
-+ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
-+
-+ for (i = 0; i < dev_endpoints; i++) {
-+ ep = &d->in_ep[i];
-+
-+ /* Init the usb_ep structure. */
-+ ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
-+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+ /**
-+ * @todo NGS: What should the max packet size be set to
-+ * here? Before EP type is set?
-+ */
-+ ep->maxpacket = MAX_PACKET_SIZE;
-+ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+ }
-+
-+ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
-+
-+ for (i = 0; i < dev_endpoints; i++) {
-+ ep = &d->out_ep[i];
-+
-+ /* Init the usb_ep structure. */
-+ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
-+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+ /**
-+ * @todo NGS: What should the max packet size be set to
-+ * here? Before EP type is set?
-+ */
-+ ep->maxpacket = MAX_PACKET_SIZE;
-+
-+ list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+ }
-+
-+ /* remove ep0 from the list. There is a ep0 pointer. */
-+ list_del_init(&d->ep0.ep_list);
-+
-+ d->ep0.maxpacket = MAX_EP0_SIZE;
-+}
-+
-+/**
-+ * This function releases the Gadget device.
-+ * required by device_unregister().
-+ *
-+ * @todo Should this do something? Should it free the PCD?
-+ */
-+static void dwc_otg_pcd_gadget_release(struct device *dev)
-+{
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
-+}
-+
-+static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
-+{
-+ static char pcd_name[] = "dwc_otg_pcd";
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ struct gadget_wrapper *d;
-+ int retval;
-+
-+ d = DWC_ALLOC(sizeof(*d));
-+ if (d == NULL) {
-+ return NULL;
-+ }
-+
-+ memset(d, 0, sizeof(*d));
-+
-+ d->gadget.name = pcd_name;
-+ d->pcd = otg_dev->pcd;
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+ strcpy(d->gadget.dev.bus_id, "gadget");
-+#else
-+ dev_set_name(&d->gadget.dev, "%s", "gadget");
-+#endif
-+
-+ d->gadget.dev.parent = &_dev->dev;
-+ d->gadget.dev.release = dwc_otg_pcd_gadget_release;
-+ d->gadget.ops = &dwc_otg_pcd_ops;
-+ d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
-+ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
-+
-+ d->driver = 0;
-+ /* Register the gadget device */
-+ retval = device_register(&d->gadget.dev);
-+ if (retval != 0) {
-+ DWC_ERROR("device_register failed\n");
-+ DWC_FREE(d);
-+ return NULL;
-+ }
-+
-+ return d;
-+}
-+
-+static void free_wrapper(struct gadget_wrapper *d)
-+{
-+ if (d->driver) {
-+ /* should have been done already by driver model core */
-+ DWC_WARN("driver '%s' is still registered\n",
-+ d->driver->driver.name);
-+ usb_gadget_unregister_driver(d->driver);
-+ }
-+
-+ device_unregister(&d->gadget.dev);
-+ DWC_FREE(d);
-+}
-+
-+/**
-+ * This function initialized the PCD portion of the driver.
-+ *
-+ */
-+int pcd_init(dwc_bus_dev_t *_dev)
-+{
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ int retval = 0;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
-+
-+ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
-+
-+ if (!otg_dev->pcd) {
-+ DWC_ERROR("dwc_otg_pcd_init failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ otg_dev->pcd->otg_dev = otg_dev;
-+ gadget_wrapper = alloc_wrapper(_dev);
-+
-+ /*
-+ * Initialize EP structures
-+ */
-+ gadget_add_eps(gadget_wrapper);
-+ /*
-+ * Setup interupt handler
-+ */
-+#ifdef PLATFORM_INTERFACE
-+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
-+ platform_get_irq(_dev, fiq_enable ? 0 : 1));
-+ retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq,
-+ IRQF_SHARED, gadget_wrapper->gadget.name,
-+ otg_dev->pcd);
-+ if (retval != 0) {
-+ DWC_ERROR("request of irq%d failed\n",
-+ platform_get_irq(_dev, fiq_enable ? 0 : 1));
-+ free_wrapper(gadget_wrapper);
-+ return -EBUSY;
-+ }
-+#else
-+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
-+ _dev->irq);
-+ retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
-+ IRQF_SHARED | IRQF_DISABLED,
-+ gadget_wrapper->gadget.name, otg_dev->pcd);
-+ if (retval != 0) {
-+ DWC_ERROR("request of irq%d failed\n", _dev->irq);
-+ free_wrapper(gadget_wrapper);
-+ return -EBUSY;
-+ }
-+#endif
-+
-+ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
-+
-+ return retval;
-+}
-+
-+/**
-+ * Cleanup the PCD.
-+ */
-+void pcd_remove(dwc_bus_dev_t *_dev)
-+{
-+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+ dwc_otg_pcd_t *pcd = otg_dev->pcd;
-+
-+ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
-+
-+ /*
-+ * Free the IRQ
-+ */
-+#ifdef PLATFORM_INTERFACE
-+ free_irq(platform_get_irq(_dev, 0), pcd);
-+#else
-+ free_irq(_dev->irq, pcd);
-+#endif
-+ dwc_otg_pcd_remove(otg_dev->pcd);
-+ free_wrapper(gadget_wrapper);
-+ otg_dev->pcd = 0;
-+}
-+
-+/**
-+ * This function registers a gadget driver with the PCD.
-+ *
-+ * When a driver is successfully registered, it will receive control
-+ * requests including set_configuration(), which enables non-control
-+ * requests. then usb traffic follows until a disconnect is reported.
-+ * then a host may connect again, or the driver might get unbound.
-+ *
-+ * @param driver The driver being registered
-+ * @param bind The bind function of gadget driver
-+ */
-+
-+int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
-+{
-+ int retval;
-+
-+ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
-+ driver->driver.name);
-+
-+ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
-+ !driver->bind ||
-+ !driver->unbind || !driver->disconnect || !driver->setup) {
-+ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
-+ return -EINVAL;
-+ }
-+ if (gadget_wrapper == 0) {
-+ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
-+ return -ENODEV;
-+ }
-+ if (gadget_wrapper->driver != 0) {
-+ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
-+ return -EBUSY;
-+ }
-+
-+ /* hook up the driver */
-+ gadget_wrapper->driver = driver;
-+ gadget_wrapper->gadget.dev.driver = &driver->driver;
-+
-+ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
-+ retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver);
-+ if (retval) {
-+ DWC_ERROR("bind to driver %s --> error %d\n",
-+ driver->driver.name, retval);
-+ gadget_wrapper->driver = 0;
-+ gadget_wrapper->gadget.dev.driver = 0;
-+ return retval;
-+ }
-+ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
-+ driver->driver.name);
-+ return 0;
-+}
-+EXPORT_SYMBOL(usb_gadget_probe_driver);
-+
-+/**
-+ * This function unregisters a gadget driver
-+ *
-+ * @param driver The driver being unregistered
-+ */
-+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
-+{
-+ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
-+
-+ if (gadget_wrapper == 0) {
-+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
-+ -ENODEV);
-+ return -ENODEV;
-+ }
-+ if (driver == 0 || driver != gadget_wrapper->driver) {
-+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
-+ -EINVAL);
-+ return -EINVAL;
-+ }
-+
-+ driver->unbind(&gadget_wrapper->gadget);
-+ gadget_wrapper->driver = 0;
-+
-+ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
-+ return 0;
-+}
-+
-+EXPORT_SYMBOL(usb_gadget_unregister_driver);
-+
-+#endif /* DWC_HOST_ONLY */
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_regs.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h
---- linux-3.18.14/drivers/usb/host/dwc_otg/dwc_otg_regs.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,2550 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
-+ * $Revision: #98 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_REGS_H__
-+#define __DWC_OTG_REGS_H__
-+
-+#include "dwc_otg_core_if.h"
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the data structures for accessing the DWC_otg core registers.
-+ *
-+ * The application interfaces with the HS OTG core by reading from and
-+ * writing to the Control and Status Register (CSR) space through the
-+ * AHB Slave interface. These registers are 32 bits wide, and the
-+ * addresses are 32-bit-block aligned.
-+ * CSRs are classified as follows:
-+ * - Core Global Registers
-+ * - Device Mode Registers
-+ * - Device Global Registers
-+ * - Device Endpoint Specific Registers
-+ * - Host Mode Registers
-+ * - Host Global Registers
-+ * - Host Port CSRs
-+ * - Host Channel Specific Registers
-+ *
-+ * Only the Core Global registers can be accessed in both Device and
-+ * Host modes. When the HS OTG core is operating in one mode, either
-+ * Device or Host, the application must not access registers from the
-+ * other mode. When the core switches from one mode to another, the
-+ * registers in the new mode of operation must be reprogrammed as they
-+ * would be after a power-on reset.
-+ */
-+
-+/****************************************************************************/
-+/** DWC_otg Core registers .
-+ * The dwc_otg_core_global_regs structure defines the size
-+ * and relative field offsets for the Core Global registers.
-+ */
-+typedef struct dwc_otg_core_global_regs {
-+ /** OTG Control and Status Register. <i>Offset: 000h</i> */
-+ volatile uint32_t gotgctl;
-+ /** OTG Interrupt Register. <i>Offset: 004h</i> */
-+ volatile uint32_t gotgint;
-+ /**Core AHB Configuration Register. <i>Offset: 008h</i> */
-+ volatile uint32_t gahbcfg;
-+
-+#define DWC_GLBINTRMASK 0x0001
-+#define DWC_DMAENABLE 0x0020
-+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
-+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
-+#define DWC_PTXEMPTYLVL_EMPTY 0x0100
-+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
-+
-+ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
-+ volatile uint32_t gusbcfg;
-+ /**Core Reset Register. <i>Offset: 010h</i> */
-+ volatile uint32_t grstctl;
-+ /**Core Interrupt Register. <i>Offset: 014h</i> */
-+ volatile uint32_t gintsts;
-+ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
-+ volatile uint32_t gintmsk;
-+ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
-+ volatile uint32_t grxstsr;
-+ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
-+ volatile uint32_t grxstsp;
-+ /**Receive FIFO Size Register. <i>Offset: 024h</i> */
-+ volatile uint32_t grxfsiz;
-+ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
-+ volatile uint32_t gnptxfsiz;
-+ /**Non Periodic Transmit FIFO/Queue Status Register (Read
-+ * Only). <i>Offset: 02Ch</i> */
-+ volatile uint32_t gnptxsts;
-+ /**I2C Access Register. <i>Offset: 030h</i> */
-+ volatile uint32_t gi2cctl;
-+ /**PHY Vendor Control Register. <i>Offset: 034h</i> */
-+ volatile uint32_t gpvndctl;
-+ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
-+ volatile uint32_t ggpio;
-+ /**User ID Register. <i>Offset: 03Ch</i> */
-+ volatile uint32_t guid;
-+ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
-+ volatile uint32_t gsnpsid;
-+ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
-+ volatile uint32_t ghwcfg1;
-+ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
-+ volatile uint32_t ghwcfg2;
-+#define DWC_SLAVE_ONLY_ARCH 0
-+#define DWC_EXT_DMA_ARCH 1
-+#define DWC_INT_DMA_ARCH 2
-+
-+#define DWC_MODE_HNP_SRP_CAPABLE 0
-+#define DWC_MODE_SRP_ONLY_CAPABLE 1
-+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
-+#define DWC_MODE_SRP_CAPABLE_DEVICE 3
-+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
-+#define DWC_MODE_SRP_CAPABLE_HOST 5
-+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
-+
-+ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
-+ volatile uint32_t ghwcfg3;
-+ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
-+ volatile uint32_t ghwcfg4;
-+ /** Core LPM Configuration register <i>Offset: 054h</i>*/
-+ volatile uint32_t glpmcfg;
-+ /** Global PowerDn Register <i>Offset: 058h</i> */
-+ volatile uint32_t gpwrdn;
-+ /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
-+ volatile uint32_t gdfifocfg;
-+ /** ADP Control Register <i>Offset: 060h</i> */
-+ volatile uint32_t adpctl;
-+ /** Reserved <i>Offset: 064h-0FFh</i> */
-+ volatile uint32_t reserved39[39];
-+ /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
-+ volatile uint32_t hptxfsiz;
-+ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
-+ otherwise Device Transmit FIFO#n Register.
-+ * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
-+ volatile uint32_t dtxfsiz[15];
-+} dwc_otg_core_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields of the Core OTG Control
-+ * and Status Register (GOTGCTL). Set the bits using the bit
-+ * fields then write the <i>d32</i> value to the register.
-+ */
-+typedef union gotgctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned sesreqscs:1;
-+ unsigned sesreq:1;
-+ unsigned vbvalidoven:1;
-+ unsigned vbvalidovval:1;
-+ unsigned avalidoven:1;
-+ unsigned avalidovval:1;
-+ unsigned bvalidoven:1;
-+ unsigned bvalidovval:1;
-+ unsigned hstnegscs:1;
-+ unsigned hnpreq:1;
-+ unsigned hstsethnpen:1;
-+ unsigned devhnpen:1;
-+ unsigned reserved12_15:4;
-+ unsigned conidsts:1;
-+ unsigned dbnctime:1;
-+ unsigned asesvld:1;
-+ unsigned bsesvld:1;
-+ unsigned otgver:1;
-+ unsigned reserved1:1;
-+ unsigned multvalidbc:5;
-+ unsigned chirpen:1;
-+ unsigned reserved28_31:4;
-+ } b;
-+} gotgctl_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core OTG Interrupt Register
-+ * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
-+ * value to the register.
-+ */
-+typedef union gotgint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Current Mode */
-+ unsigned reserved0_1:2;
-+
-+ /** Session End Detected */
-+ unsigned sesenddet:1;
-+
-+ unsigned reserved3_7:5;
-+
-+ /** Session Request Success Status Change */
-+ unsigned sesreqsucstschng:1;
-+ /** Host Negotiation Success Status Change */
-+ unsigned hstnegsucstschng:1;
-+
-+ unsigned reserved10_16:7;
-+
-+ /** Host Negotiation Detected */
-+ unsigned hstnegdet:1;
-+ /** A-Device Timeout Change */
-+ unsigned adevtoutchng:1;
-+ /** Debounce Done */
-+ unsigned debdone:1;
-+ /** Multi-Valued input changed */
-+ unsigned mvic:1;
-+
-+ unsigned reserved31_21:11;
-+
-+ } b;
-+} gotgint_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core AHB Configuration
-+ * Register (GAHBCFG). Set/clear the bits using the bit fields then
-+ * write the <i>d32</i> value to the register.
-+ */
-+typedef union gahbcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned glblintrmsk:1;
-+#define DWC_GAHBCFG_GLBINT_ENABLE 1
-+
-+ unsigned hburstlen:4;
-+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
-+
-+ unsigned dmaenable:1;
-+#define DWC_GAHBCFG_DMAENABLE 1
-+ unsigned reserved:1;
-+ unsigned nptxfemplvl_txfemplvl:1;
-+ unsigned ptxfemplvl:1;
-+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
-+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
-+ unsigned reserved9_20:12;
-+ unsigned remmemsupp:1;
-+ unsigned notialldmawrit:1;
-+ unsigned ahbsingle:1;
-+ unsigned reserved24_31:8;
-+ } b;
-+} gahbcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core USB Configuration
-+ * Register (GUSBCFG). Set the bits using the bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union gusbcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned toutcal:3;
-+ unsigned phyif:1;
-+ unsigned ulpi_utmi_sel:1;
-+ unsigned fsintf:1;
-+ unsigned physel:1;
-+ unsigned ddrsel:1;
-+ unsigned srpcap:1;
-+ unsigned hnpcap:1;
-+ unsigned usbtrdtim:4;
-+ unsigned reserved1:1;
-+ unsigned phylpwrclksel:1;
-+ unsigned otgutmifssel:1;
-+ unsigned ulpi_fsls:1;
-+ unsigned ulpi_auto_res:1;
-+ unsigned ulpi_clk_sus_m:1;
-+ unsigned ulpi_ext_vbus_drv:1;
-+ unsigned ulpi_int_vbus_indicator:1;
-+ unsigned term_sel_dl_pulse:1;
-+ unsigned indicator_complement:1;
-+ unsigned indicator_pass_through:1;
-+ unsigned ulpi_int_prot_dis:1;
-+ unsigned ic_usb_cap:1;
-+ unsigned ic_traffic_pull_remove:1;
-+ unsigned tx_end_delay:1;
-+ unsigned force_host_mode:1;
-+ unsigned force_dev_mode:1;
-+ unsigned reserved31:1;
-+ } b;
-+} gusbcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core Reset Register
-+ * (GRSTCTL). Set/clear the bits using the bit fields then write the
-+ * <i>d32</i> value to the register.
-+ */
-+typedef union grstctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Core Soft Reset (CSftRst) (Device and Host)
-+ *
-+ * The application can flush the control logic in the
-+ * entire core using this bit. This bit resets the
-+ * pipelines in the AHB Clock domain as well as the
-+ * PHY Clock domain.
-+ *
-+ * The state machines are reset to an IDLE state, the
-+ * control bits in the CSRs are cleared, all the
-+ * transmit FIFOs and the receive FIFO are flushed.
-+ *
-+ * The status mask bits that control the generation of
-+ * the interrupt, are cleared, to clear the
-+ * interrupt. The interrupt status bits are not
-+ * cleared, so the application can get the status of
-+ * any events that occurred in the core after it has
-+ * set this bit.
-+ *
-+ * Any transactions on the AHB are terminated as soon
-+ * as possible following the protocol. Any
-+ * transactions on the USB are terminated immediately.
-+ *
-+ * The configuration settings in the CSRs are
-+ * unchanged, so the software doesn't have to
-+ * reprogram these registers (Device
-+ * Configuration/Host Configuration/Core System
-+ * Configuration/Core PHY Configuration).
-+ *
-+ * The application can write to this bit, any time it
-+ * wants to reset the core. This is a self clearing
-+ * bit and the core clears this bit after all the
-+ * necessary logic is reset in the core, which may
-+ * take several clocks, depending on the current state
-+ * of the core.
-+ */
-+ unsigned csftrst:1;
-+ /** Hclk Soft Reset
-+ *
-+ * The application uses this bit to reset the control logic in
-+ * the AHB clock domain. Only AHB clock domain pipelines are
-+ * reset.
-+ */
-+ unsigned hsftrst:1;
-+ /** Host Frame Counter Reset (Host Only)<br>
-+ *
-+ * The application can reset the (micro)frame number
-+ * counter inside the core, using this bit. When the
-+ * (micro)frame counter is reset, the subsequent SOF
-+ * sent out by the core, will have a (micro)frame
-+ * number of 0.
-+ */
-+ unsigned hstfrm:1;
-+ /** In Token Sequence Learning Queue Flush
-+ * (INTknQFlsh) (Device Only)
-+ */
-+ unsigned intknqflsh:1;
-+ /** RxFIFO Flush (RxFFlsh) (Device and Host)
-+ *
-+ * The application can flush the entire Receive FIFO
-+ * using this bit. The application must first
-+ * ensure that the core is not in the middle of a
-+ * transaction. The application should write into
-+ * this bit, only after making sure that neither the
-+ * DMA engine is reading from the RxFIFO nor the MAC
-+ * is writing the data in to the FIFO. The
-+ * application should wait until the bit is cleared
-+ * before performing any other operations. This bit
-+ * will takes 8 clocks (slowest of PHY or AHB clock)
-+ * to clear.
-+ */
-+ unsigned rxfflsh:1;
-+ /** TxFIFO Flush (TxFFlsh) (Device and Host).
-+ *
-+ * This bit is used to selectively flush a single or
-+ * all transmit FIFOs. The application must first
-+ * ensure that the core is not in the middle of a
-+ * transaction. The application should write into
-+ * this bit, only after making sure that neither the
-+ * DMA engine is writing into the TxFIFO nor the MAC
-+ * is reading the data out of the FIFO. The
-+ * application should wait until the core clears this
-+ * bit, before performing any operations. This bit
-+ * will takes 8 clocks (slowest of PHY or AHB clock)
-+ * to clear.
-+ */
-+ unsigned txfflsh:1;
-+
-+ /** TxFIFO Number (TxFNum) (Device and Host).
-+ *
-+ * This is the FIFO number which needs to be flushed,
-+ * using the TxFIFO Flush bit. This field should not
-+ * be changed until the TxFIFO Flush bit is cleared by
-+ * the core.
-+ * - 0x0 : Non Periodic TxFIFO Flush
-+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
-+ * or Periodic TxFIFO in host mode
-+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
-+ * - ...
-+ * - 0xF : Periodic TxFIFO #15 Flush in device mode
-+ * - 0x10: Flush all the Transmit NonPeriodic and
-+ * Transmit Periodic FIFOs in the core
-+ */
-+ unsigned txfnum:5;
-+ /** Reserved */
-+ unsigned reserved11_29:19;
-+ /** DMA Request Signal. Indicated DMA request is in
-+ * probress. Used for debug purpose. */
-+ unsigned dmareq:1;
-+ /** AHB Master Idle. Indicates the AHB Master State
-+ * Machine is in IDLE condition. */
-+ unsigned ahbidle:1;
-+ } b;
-+} grstctl_t;
-+
-+/**
-+ * This union represents the bit fields of the Core Interrupt Mask
-+ * Register (GINTMSK). Set/clear the bits using the bit fields then
-+ * write the <i>d32</i> value to the register.
-+ */
-+typedef union gintmsk_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned reserved0:1;
-+ unsigned modemismatch:1;
-+ unsigned otgintr:1;
-+ unsigned sofintr:1;
-+ unsigned rxstsqlvl:1;
-+ unsigned nptxfempty:1;
-+ unsigned ginnakeff:1;
-+ unsigned goutnakeff:1;
-+ unsigned ulpickint:1;
-+ unsigned i2cintr:1;
-+ unsigned erlysuspend:1;
-+ unsigned usbsuspend:1;
-+ unsigned usbreset:1;
-+ unsigned enumdone:1;
-+ unsigned isooutdrop:1;
-+ unsigned eopframe:1;
-+ unsigned restoredone:1;
-+ unsigned epmismatch:1;
-+ unsigned inepintr:1;
-+ unsigned outepintr:1;
-+ unsigned incomplisoin:1;
-+ unsigned incomplisoout:1;
-+ unsigned fetsusp:1;
-+ unsigned resetdet:1;
-+ unsigned portintr:1;
-+ unsigned hcintr:1;
-+ unsigned ptxfempty:1;
-+ unsigned lpmtranrcvd:1;
-+ unsigned conidstschng:1;
-+ unsigned disconnect:1;
-+ unsigned sessreqintr:1;
-+ unsigned wkupintr:1;
-+ } b;
-+} gintmsk_data_t;
-+/**
-+ * This union represents the bit fields of the Core Interrupt Register
-+ * (GINTSTS). Set/clear the bits using the bit fields then write the
-+ * <i>d32</i> value to the register.
-+ */
-+typedef union gintsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+#define DWC_SOF_INTR_MASK 0x0008
-+ /** register bits */
-+ struct {
-+#define DWC_HOST_MODE 1
-+ unsigned curmode:1;
-+ unsigned modemismatch:1;
-+ unsigned otgintr:1;
-+ unsigned sofintr:1;
-+ unsigned rxstsqlvl:1;
-+ unsigned nptxfempty:1;
-+ unsigned ginnakeff:1;
-+ unsigned goutnakeff:1;
-+ unsigned ulpickint:1;
-+ unsigned i2cintr:1;
-+ unsigned erlysuspend:1;
-+ unsigned usbsuspend:1;
-+ unsigned usbreset:1;
-+ unsigned enumdone:1;
-+ unsigned isooutdrop:1;
-+ unsigned eopframe:1;
-+ unsigned restoredone:1;
-+ unsigned epmismatch:1;
-+ unsigned inepint:1;
-+ unsigned outepintr:1;
-+ unsigned incomplisoin:1;
-+ unsigned incomplisoout:1;
-+ unsigned fetsusp:1;
-+ unsigned resetdet:1;
-+ unsigned portintr:1;
-+ unsigned hcintr:1;
-+ unsigned ptxfempty:1;
-+ unsigned lpmtranrcvd:1;
-+ unsigned conidstschng:1;
-+ unsigned disconnect:1;
-+ unsigned sessreqintr:1;
-+ unsigned wkupintr:1;
-+ } b;
-+} gintsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Receive Status Read and
-+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
-+ * element then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union device_grxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned epnum:4;
-+ unsigned bcnt:11;
-+ unsigned dpid:2;
-+
-+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
-+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
-+
-+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
-+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
-+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
-+ unsigned pktsts:4;
-+ unsigned fn:4;
-+ unsigned reserved25_31:7;
-+ } b;
-+} device_grxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Receive Status Read and
-+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
-+ * element then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union host_grxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned chnum:4;
-+ unsigned bcnt:11;
-+ unsigned dpid:2;
-+
-+ unsigned pktsts:4;
-+#define DWC_GRXSTS_PKTSTS_IN 0x2
-+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
-+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
-+#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
-+
-+ unsigned reserved21_31:11;
-+ } b;
-+} host_grxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
-+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
-+ * then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union fifosize_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned startaddr:16;
-+ unsigned depth:16;
-+ } b;
-+} fifosize_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Non-Periodic Transmit
-+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
-+ * <i>d32</i> element then read out the bits using the <i>b</i>it
-+ * elements.
-+ */
-+typedef union gnptxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned nptxfspcavail:16;
-+ unsigned nptxqspcavail:8;
-+ /** Top of the Non-Periodic Transmit Request Queue
-+ * - bit 24 - Terminate (Last entry for the selected
-+ * channel/EP)
-+ * - bits 26:25 - Token Type
-+ * - 2'b00 - IN/OUT
-+ * - 2'b01 - Zero Length OUT
-+ * - 2'b10 - PING/Complete Split
-+ * - 2'b11 - Channel Halt
-+ * - bits 30:27 - Channel/EP Number
-+ */
-+ unsigned nptxqtop_terminate:1;
-+ unsigned nptxqtop_token:2;
-+ unsigned nptxqtop_chnep:4;
-+ unsigned reserved:1;
-+ } b;
-+} gnptxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Transmit
-+ * FIFO Status Register (DTXFSTS). Read the register into the
-+ * <i>d32</i> element then read out the bits using the <i>b</i>it
-+ * elements.
-+ */
-+typedef union dtxfsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned txfspcavail:16;
-+ unsigned reserved:16;
-+ } b;
-+} dtxfsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the I2C Control Register
-+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gi2cctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned rwdata:8;
-+ unsigned regaddr:8;
-+ unsigned addr:7;
-+ unsigned i2cen:1;
-+ unsigned ack:1;
-+ unsigned i2csuspctl:1;
-+ unsigned i2cdevaddr:2;
-+ unsigned i2cdatse0:1;
-+ unsigned reserved:1;
-+ unsigned rw:1;
-+ unsigned bsydne:1;
-+ } b;
-+} gi2cctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the PHY Vendor Control Register
-+ * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gpvndctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned regdata:8;
-+ unsigned vctrl:8;
-+ unsigned regaddr16_21:6;
-+ unsigned regwr:1;
-+ unsigned reserved23_24:2;
-+ unsigned newregreq:1;
-+ unsigned vstsbsy:1;
-+ unsigned vstsdone:1;
-+ unsigned reserved28_30:3;
-+ unsigned disulpidrvr:1;
-+ } b;
-+} gpvndctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the General Purpose
-+ * Input/Output Register (GGPIO).
-+ * Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union ggpio_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned gpi:16;
-+ unsigned gpo:16;
-+ } b;
-+} ggpio_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User ID Register
-+ * (GUID). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union guid_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned rwdata:32;
-+ } b;
-+} guid_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Synopsys ID Register
-+ * (GSNPSID). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gsnpsid_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned rwdata:32;
-+ } b;
-+} gsnpsid_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config1
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg1_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned ep_dir0:2;
-+ unsigned ep_dir1:2;
-+ unsigned ep_dir2:2;
-+ unsigned ep_dir3:2;
-+ unsigned ep_dir4:2;
-+ unsigned ep_dir5:2;
-+ unsigned ep_dir6:2;
-+ unsigned ep_dir7:2;
-+ unsigned ep_dir8:2;
-+ unsigned ep_dir9:2;
-+ unsigned ep_dir10:2;
-+ unsigned ep_dir11:2;
-+ unsigned ep_dir12:2;
-+ unsigned ep_dir13:2;
-+ unsigned ep_dir14:2;
-+ unsigned ep_dir15:2;
-+ } b;
-+} hwcfg1_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config2
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg2_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /* GHWCFG2 */
-+ unsigned op_mode:3;
-+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
-+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
-+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
-+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
-+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
-+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
-+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
-+
-+ unsigned architecture:2;
-+ unsigned point2point:1;
-+ unsigned hs_phy_type:2;
-+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
-+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
-+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
-+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
-+
-+ unsigned fs_phy_type:2;
-+ unsigned num_dev_ep:4;
-+ unsigned num_host_chan:4;
-+ unsigned perio_ep_supported:1;
-+ unsigned dynamic_fifo:1;
-+ unsigned multi_proc_int:1;
-+ unsigned reserved21:1;
-+ unsigned nonperio_tx_q_depth:2;
-+ unsigned host_perio_tx_q_depth:2;
-+ unsigned dev_token_q_depth:5;
-+ unsigned otg_enable_ic_usb:1;
-+ } b;
-+} hwcfg2_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config3
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg3_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /* GHWCFG3 */
-+ unsigned xfer_size_cntr_width:4;
-+ unsigned packet_size_cntr_width:3;
-+ unsigned otg_func:1;
-+ unsigned i2c:1;
-+ unsigned vendor_ctrl_if:1;
-+ unsigned optional_features:1;
-+ unsigned synch_reset_type:1;
-+ unsigned adp_supp:1;
-+ unsigned otg_enable_hsic:1;
-+ unsigned bc_support:1;
-+ unsigned otg_lpm_en:1;
-+ unsigned dfifo_depth:16;
-+ } b;
-+} hwcfg3_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config4
-+ * Register. Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg4_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned num_dev_perio_in_ep:4;
-+ unsigned power_optimiz:1;
-+ unsigned min_ahb_freq:1;
-+ unsigned hiber:1;
-+ unsigned xhiber:1;
-+ unsigned reserved:6;
-+ unsigned utmi_phy_data_width:2;
-+ unsigned num_dev_mode_ctrl_ep:4;
-+ unsigned iddig_filt_en:1;
-+ unsigned vbus_valid_filt_en:1;
-+ unsigned a_valid_filt_en:1;
-+ unsigned b_valid_filt_en:1;
-+ unsigned session_end_filt_en:1;
-+ unsigned ded_fifo_en:1;
-+ unsigned num_in_eps:4;
-+ unsigned desc_dma:1;
-+ unsigned desc_dma_dyn:1;
-+ } b;
-+} hwcfg4_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core LPM Configuration
-+ * Register (GLPMCFG). Set the bits using bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union glpmctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** LPM-Capable (LPMCap) (Device and Host)
-+ * The application uses this bit to control
-+ * the DWC_otg core LPM capabilities.
-+ */
-+ unsigned lpm_cap_en:1;
-+ /** LPM response programmed by application (AppL1Res) (Device)
-+ * Handshake response to LPM token pre-programmed
-+ * by device application software.
-+ */
-+ unsigned appl_resp:1;
-+ /** Host Initiated Resume Duration (HIRD) (Device and Host)
-+ * In Host mode this field indicates the value of HIRD
-+ * to be sent in an LPM transaction.
-+ * In Device mode this field is updated with the
-+ * Received LPM Token HIRD bmAttribute
-+ * when an ACK/NYET/STALL response is sent
-+ * to an LPM transaction.
-+ */
-+ unsigned hird:4;
-+ /** RemoteWakeEnable (bRemoteWake) (Device and Host)
-+ * In Host mode this bit indicates the value of remote
-+ * wake up to be sent in wIndex field of LPM transaction.
-+ * In Device mode this field is updated with the
-+ * Received LPM Token bRemoteWake bmAttribute
-+ * when an ACK/NYET/STALL response is sent
-+ * to an LPM transaction.
-+ */
-+ unsigned rem_wkup_en:1;
-+ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
-+ * The application uses this bit to control
-+ * the utmi_sleep_n assertion to the PHY when in L1 state.
-+ */
-+ unsigned en_utmi_sleep:1;
-+ /** HIRD Threshold (HIRD_Thres) (Device and Host)
-+ */
-+ unsigned hird_thres:5;
-+ /** LPM Response (CoreL1Res) (Device and Host)
-+ * In Host mode this bit contains handsake response to
-+ * LPM transaction.
-+ * In Device mode the response of the core to
-+ * LPM transaction received is reflected in these two bits.
-+ - 0x0 : ERROR (No handshake response)
-+ - 0x1 : STALL
-+ - 0x2 : NYET
-+ - 0x3 : ACK
-+ */
-+ unsigned lpm_resp:2;
-+ /** Port Sleep Status (SlpSts) (Device and Host)
-+ * This bit is set as long as a Sleep condition
-+ * is present on the USB bus.
-+ */
-+ unsigned prt_sleep_sts:1;
-+ /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
-+ * Indicates that the application or host
-+ * can start resume from Sleep state.
-+ */
-+ unsigned sleep_state_resumeok:1;
-+ /** LPM channel Index (LPM_Chnl_Indx) (Host)
-+ * The channel number on which the LPM transaction
-+ * has to be applied while sending
-+ * an LPM transaction to the local device.
-+ */
-+ unsigned lpm_chan_index:4;
-+ /** LPM Retry Count (LPM_Retry_Cnt) (Host)
-+ * Number host retries that would be performed
-+ * if the device response was not valid response.
-+ */
-+ unsigned retry_count:3;
-+ /** Send LPM Transaction (SndLPM) (Host)
-+ * When set by application software,
-+ * an LPM transaction containing two tokens
-+ * is sent.
-+ */
-+ unsigned send_lpm:1;
-+ /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
-+ * Number of LPM Host Retries still remaining
-+ * to be transmitted for the current LPM sequence
-+ */
-+ unsigned retry_count_sts:3;
-+ unsigned reserved28_29:2;
-+ /** In host mode once this bit is set, the host
-+ * configures to drive the HSIC Idle state on the bus.
-+ * It then waits for the device to initiate the Connect sequence.
-+ * In device mode once this bit is set, the device waits for
-+ * the HSIC Idle line state on the bus. Upon receving the Idle
-+ * line state, it initiates the HSIC Connect sequence.
-+ */
-+ unsigned hsic_connect:1;
-+ /** This bit overrides and functionally inverts
-+ * the if_select_hsic input port signal.
-+ */
-+ unsigned inv_sel_hsic:1;
-+ } b;
-+} glpmcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core ADP Timer, Control and
-+ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union adpctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Probe Discharge (PRB_DSCHG)
-+ * These bits set the times for TADP_DSCHG.
-+ * These bits are defined as follows:
-+ * 2'b00 - 4 msec
-+ * 2'b01 - 8 msec
-+ * 2'b10 - 16 msec
-+ * 2'b11 - 32 msec
-+ */
-+ unsigned prb_dschg:2;
-+ /** Probe Delta (PRB_DELTA)
-+ * These bits set the resolution for RTIM value.
-+ * The bits are defined in units of 32 kHz clock cycles as follows:
-+ * 2'b00 - 1 cycles
-+ * 2'b01 - 2 cycles
-+ * 2'b10 - 3 cycles
-+ * 2'b11 - 4 cycles
-+ * For example if this value is chosen to 2'b01, it means that RTIM
-+ * increments for every 3(three) 32Khz clock cycles.
-+ */
-+ unsigned prb_delta:2;
-+ /** Probe Period (PRB_PER)
-+ * These bits sets the TADP_PRD as shown in Figure 4 as follows:
-+ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
-+ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
-+ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
-+ * 2'b11 - Reserved
-+ */
-+ unsigned prb_per:2;
-+ /** These bits capture the latest time it took for VBUS to ramp from
-+ * VADP_SINK to VADP_PRB.
-+ * 0x000 - 1 cycles
-+ * 0x001 - 2 cycles
-+ * 0x002 - 3 cycles
-+ * etc
-+ * 0x7FF - 2048 cycles
-+ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
-+ */
-+ unsigned rtim:11;
-+ /** Enable Probe (EnaPrb)
-+ * When programmed to 1'b1, the core performs a probe operation.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned enaprb:1;
-+ /** Enable Sense (EnaSns)
-+ * When programmed to 1'b1, the core performs a Sense operation.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned enasns:1;
-+ /** ADP Reset (ADPRes)
-+ * When set, ADP controller is reset.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adpres:1;
-+ /** ADP Enable (ADPEn)
-+ * When set, the core performs either ADP probing or sensing
-+ * based on EnaPrb or EnaSns.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adpen:1;
-+ /** ADP Probe Interrupt (ADP_PRB_INT)
-+ * When this bit is set, it means that the VBUS
-+ * voltage is greater than VADP_PRB or VADP_PRB is reached.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_prb_int:1;
-+ /**
-+ * ADP Sense Interrupt (ADP_SNS_INT)
-+ * When this bit is set, it means that the VBUS voltage is greater than
-+ * VADP_SNS value or VADP_SNS is reached.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_sns_int:1;
-+ /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
-+ * This bit is relevant only for an ADP probe.
-+ * When this bit is set, it means that the ramp time has
-+ * completed ie ADPCTL.RTIM has reached its terminal value
-+ * of 0x7FF. This is a debug feature that allows software
-+ * to read the ramp time after each cycle.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_tmout_int:1;
-+ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
-+ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_prb_int_msk:1;
-+ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
-+ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_sns_int_msk:1;
-+ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
-+ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
-+ * This bit is valid only if OTG_Ver = 1'b1.
-+ */
-+ unsigned adp_tmout_int_msk:1;
-+ /** Access Request
-+ * 2'b00 - Read/Write Valid (updated by the core)
-+ * 2'b01 - Read
-+ * 2'b00 - Write
-+ * 2'b00 - Reserved
-+ */
-+ unsigned ar:2;
-+ /** Reserved */
-+ unsigned reserved29_31:3;
-+ } b;
-+} adpctl_data_t;
-+
-+////////////////////////////////////////////
-+// Device Registers
-+/**
-+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
-+ *
-+ * The following structures define the size and relative field offsets
-+ * for the Device Mode Registers.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_global_regs {
-+ /** Device Configuration Register. <i>Offset 800h</i> */
-+ volatile uint32_t dcfg;
-+ /** Device Control Register. <i>Offset: 804h</i> */
-+ volatile uint32_t dctl;
-+ /** Device Status Register (Read Only). <i>Offset: 808h</i> */
-+ volatile uint32_t dsts;
-+ /** Reserved. <i>Offset: 80Ch</i> */
-+ uint32_t unused;
-+ /** Device IN Endpoint Common Interrupt Mask
-+ * Register. <i>Offset: 810h</i> */
-+ volatile uint32_t diepmsk;
-+ /** Device OUT Endpoint Common Interrupt Mask
-+ * Register. <i>Offset: 814h</i> */
-+ volatile uint32_t doepmsk;
-+ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
-+ volatile uint32_t daint;
-+ /** Device All Endpoints Interrupt Mask Register. <i>Offset:
-+ * 81Ch</i> */
-+ volatile uint32_t daintmsk;
-+ /** Device IN Token Queue Read Register-1 (Read Only).
-+ * <i>Offset: 820h</i> */
-+ volatile uint32_t dtknqr1;
-+ /** Device IN Token Queue Read Register-2 (Read Only).
-+ * <i>Offset: 824h</i> */
-+ volatile uint32_t dtknqr2;
-+ /** Device VBUS discharge Register. <i>Offset: 828h</i> */
-+ volatile uint32_t dvbusdis;
-+ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
-+ volatile uint32_t dvbuspulse;
-+ /** Device IN Token Queue Read Register-3 (Read Only). /
-+ * Device Thresholding control register (Read/Write)
-+ * <i>Offset: 830h</i> */
-+ volatile uint32_t dtknqr3_dthrctl;
-+ /** Device IN Token Queue Read Register-4 (Read Only). /
-+ * Device IN EPs empty Inr. Mask Register (Read/Write)
-+ * <i>Offset: 834h</i> */
-+ volatile uint32_t dtknqr4_fifoemptymsk;
-+ /** Device Each Endpoint Interrupt Register (Read Only). /
-+ * <i>Offset: 838h</i> */
-+ volatile uint32_t deachint;
-+ /** Device Each Endpoint Interrupt mask Register (Read/Write). /
-+ * <i>Offset: 83Ch</i> */
-+ volatile uint32_t deachintmsk;
-+ /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
-+ * <i>Offset: 840h</i> */
-+ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
-+ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
-+ * <i>Offset: 880h</i> */
-+ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
-+} dwc_otg_device_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Configuration
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements. Write the
-+ * <i>d32</i> member to the dcfg register.
-+ */
-+typedef union dcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Device Speed */
-+ unsigned devspd:2;
-+ /** Non Zero Length Status OUT Handshake */
-+ unsigned nzstsouthshk:1;
-+#define DWC_DCFG_SEND_STALL 1
-+
-+ unsigned ena32khzs:1;
-+ /** Device Addresses */
-+ unsigned devaddr:7;
-+ /** Periodic Frame Interval */
-+ unsigned perfrint:2;
-+#define DWC_DCFG_FRAME_INTERVAL_80 0
-+#define DWC_DCFG_FRAME_INTERVAL_85 1
-+#define DWC_DCFG_FRAME_INTERVAL_90 2
-+#define DWC_DCFG_FRAME_INTERVAL_95 3
-+
-+ /** Enable Device OUT NAK for bulk in DDMA mode */
-+ unsigned endevoutnak:1;
-+
-+ unsigned reserved14_17:4;
-+ /** In Endpoint Mis-match count */
-+ unsigned epmscnt:5;
-+ /** Enable Descriptor DMA in Device mode */
-+ unsigned descdma:1;
-+ unsigned perschintvl:2;
-+ unsigned resvalid:6;
-+ } b;
-+} dcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Control
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union dctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Remote Wakeup */
-+ unsigned rmtwkupsig:1;
-+ /** Soft Disconnect */
-+ unsigned sftdiscon:1;
-+ /** Global Non-Periodic IN NAK Status */
-+ unsigned gnpinnaksts:1;
-+ /** Global OUT NAK Status */
-+ unsigned goutnaksts:1;
-+ /** Test Control */
-+ unsigned tstctl:3;
-+ /** Set Global Non-Periodic IN NAK */
-+ unsigned sgnpinnak:1;
-+ /** Clear Global Non-Periodic IN NAK */
-+ unsigned cgnpinnak:1;
-+ /** Set Global OUT NAK */
-+ unsigned sgoutnak:1;
-+ /** Clear Global OUT NAK */
-+ unsigned cgoutnak:1;
-+ /** Power-On Programming Done */
-+ unsigned pwronprgdone:1;
-+ /** Reserved */
-+ unsigned reserved:1;
-+ /** Global Multi Count */
-+ unsigned gmc:2;
-+ /** Ignore Frame Number for ISOC EPs */
-+ unsigned ifrmnum:1;
-+ /** NAK on Babble */
-+ unsigned nakonbble:1;
-+ /** Enable Continue on BNA */
-+ unsigned encontonbna:1;
-+
-+ unsigned reserved18_31:14;
-+ } b;
-+} dctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Status
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union dsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Suspend Status */
-+ unsigned suspsts:1;
-+ /** Enumerated Speed */
-+ unsigned enumspd:2;
-+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
-+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
-+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
-+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
-+ /** Erratic Error */
-+ unsigned errticerr:1;
-+ unsigned reserved4_7:4;
-+ /** Frame or Microframe Number of the received SOF */
-+ unsigned soffn:14;
-+ unsigned reserved22_31:10;
-+ } b;
-+} dsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN EP Interrupt
-+ * Register and the Device IN EP Common Mask Register.
-+ *
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union diepint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer complete mask */
-+ unsigned xfercompl:1;
-+ /** Endpoint disable mask */
-+ unsigned epdisabled:1;
-+ /** AHB Error mask */
-+ unsigned ahberr:1;
-+ /** TimeOUT Handshake mask (non-ISOC EPs) */
-+ unsigned timeout:1;
-+ /** IN Token received with TxF Empty mask */
-+ unsigned intktxfemp:1;
-+ /** IN Token Received with EP mismatch mask */
-+ unsigned intknepmis:1;
-+ /** IN Endpoint NAK Effective mask */
-+ unsigned inepnakeff:1;
-+ /** Reserved */
-+ unsigned emptyintr:1;
-+
-+ unsigned txfifoundrn:1;
-+
-+ /** BNA Interrupt mask */
-+ unsigned bna:1;
-+
-+ unsigned reserved10_12:3;
-+ /** BNA Interrupt mask */
-+ unsigned nak:1;
-+
-+ unsigned reserved14_31:18;
-+ } b;
-+} diepint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN EP
-+ * Common/Dedicated Interrupt Mask Register.
-+ */
-+typedef union diepint_data diepmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device OUT EP Interrupt
-+ * Registerand Device OUT EP Common Interrupt Mask Register.
-+ *
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union doepint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer complete */
-+ unsigned xfercompl:1;
-+ /** Endpoint disable */
-+ unsigned epdisabled:1;
-+ /** AHB Error */
-+ unsigned ahberr:1;
-+ /** Setup Phase Done (contorl EPs) */
-+ unsigned setup:1;
-+ /** OUT Token Received when Endpoint Disabled */
-+ unsigned outtknepdis:1;
-+
-+ unsigned stsphsercvd:1;
-+ /** Back-to-Back SETUP Packets Received */
-+ unsigned back2backsetup:1;
-+
-+ unsigned reserved7:1;
-+ /** OUT packet Error */
-+ unsigned outpkterr:1;
-+ /** BNA Interrupt */
-+ unsigned bna:1;
-+
-+ unsigned reserved10:1;
-+ /** Packet Drop Status */
-+ unsigned pktdrpsts:1;
-+ /** Babble Interrupt */
-+ unsigned babble:1;
-+ /** NAK Interrupt */
-+ unsigned nak:1;
-+ /** NYET Interrupt */
-+ unsigned nyet:1;
-+ /** Bit indicating setup packet received */
-+ unsigned sr:1;
-+
-+ unsigned reserved16_31:16;
-+ } b;
-+} doepint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device OUT EP
-+ * Common/Dedicated Interrupt Mask Register.
-+ */
-+typedef union doepint_data doepmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device All EP Interrupt
-+ * and Mask Registers.
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union daint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** IN Endpoint bits */
-+ unsigned in:16;
-+ /** OUT Endpoint bits */
-+ unsigned out:16;
-+ } ep;
-+ struct {
-+ /** IN Endpoint bits */
-+ unsigned inep0:1;
-+ unsigned inep1:1;
-+ unsigned inep2:1;
-+ unsigned inep3:1;
-+ unsigned inep4:1;
-+ unsigned inep5:1;
-+ unsigned inep6:1;
-+ unsigned inep7:1;
-+ unsigned inep8:1;
-+ unsigned inep9:1;
-+ unsigned inep10:1;
-+ unsigned inep11:1;
-+ unsigned inep12:1;
-+ unsigned inep13:1;
-+ unsigned inep14:1;
-+ unsigned inep15:1;
-+ /** OUT Endpoint bits */
-+ unsigned outep0:1;
-+ unsigned outep1:1;
-+ unsigned outep2:1;
-+ unsigned outep3:1;
-+ unsigned outep4:1;
-+ unsigned outep5:1;
-+ unsigned outep6:1;
-+ unsigned outep7:1;
-+ unsigned outep8:1;
-+ unsigned outep9:1;
-+ unsigned outep10:1;
-+ unsigned outep11:1;
-+ unsigned outep12:1;
-+ unsigned outep13:1;
-+ unsigned outep14:1;
-+ unsigned outep15:1;
-+ } b;
-+} daint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN Token Queue
-+ * Read Registers.
-+ * - Read the register into the <i>d32</i> member.
-+ * - READ-ONLY Register
-+ */
-+typedef union dtknq1_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** In Token Queue Write Pointer */
-+ unsigned intknwptr:5;
-+ /** Reserved */
-+ unsigned reserved05_06:2;
-+ /** write pointer has wrapped. */
-+ unsigned wrap_bit:1;
-+ /** EP Numbers of IN Tokens 0 ... 4 */
-+ unsigned epnums0_5:24;
-+ } b;
-+} dtknq1_data_t;
-+
-+/**
-+ * This union represents Threshold control Register
-+ * - Read and write the register into the <i>d32</i> member.
-+ * - READ-WRITABLE Register
-+ */
-+typedef union dthrctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** non ISO Tx Thr. Enable */
-+ unsigned non_iso_thr_en:1;
-+ /** ISO Tx Thr. Enable */
-+ unsigned iso_thr_en:1;
-+ /** Tx Thr. Length */
-+ unsigned tx_thr_len:9;
-+ /** AHB Threshold ratio */
-+ unsigned ahb_thr_ratio:2;
-+ /** Reserved */
-+ unsigned reserved13_15:3;
-+ /** Rx Thr. Enable */
-+ unsigned rx_thr_en:1;
-+ /** Rx Thr. Length */
-+ unsigned rx_thr_len:9;
-+ unsigned reserved26:1;
-+ /** Arbiter Parking Enable*/
-+ unsigned arbprken:1;
-+ /** Reserved */
-+ unsigned reserved28_31:4;
-+ } b;
-+} dthrctl_data_t;
-+
-+/**
-+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
-+ * 900h-AFCh</i>
-+ *
-+ * There will be one set of endpoint registers per logical endpoint
-+ * implemented.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_in_ep_regs {
-+ /** Device IN Endpoint Control Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 00h</i> */
-+ volatile uint32_t diepctl;
-+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
-+ uint32_t reserved04;
-+ /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 08h</i> */
-+ volatile uint32_t diepint;
-+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
-+ uint32_t reserved0C;
-+ /** Device IN Endpoint Transfer Size
-+ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
-+ volatile uint32_t dieptsiz;
-+ /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 14h</i> */
-+ volatile uint32_t diepdma;
-+ /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 18h</i> */
-+ volatile uint32_t dtxfsts;
-+ /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
-+ * (ep_num * 20h) + 1Ch</i> */
-+ volatile uint32_t diepdmab;
-+} dwc_otg_dev_in_ep_regs_t;
-+
-+/**
-+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
-+ * B00h-CFCh</i>
-+ *
-+ * There will be one set of endpoint registers per logical endpoint
-+ * implemented.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_out_ep_regs {
-+ /** Device OUT Endpoint Control Register. <i>Offset:B00h +
-+ * (ep_num * 20h) + 00h</i> */
-+ volatile uint32_t doepctl;
-+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
-+ uint32_t reserved04;
-+ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
-+ * (ep_num * 20h) + 08h</i> */
-+ volatile uint32_t doepint;
-+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
-+ uint32_t reserved0C;
-+ /** Device OUT Endpoint Transfer Size Register. <i>Offset:
-+ * B00h + (ep_num * 20h) + 10h</i> */
-+ volatile uint32_t doeptsiz;
-+ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
-+ * + (ep_num * 20h) + 14h</i> */
-+ volatile uint32_t doepdma;
-+ /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
-+ uint32_t unused;
-+ /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
-+ * + (ep_num * 20h) + 1Ch</i> */
-+ uint32_t doepdmab;
-+} dwc_otg_dev_out_ep_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP Control
-+ * Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union depctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Maximum Packet Size
-+ * IN/OUT EPn
-+ * IN/OUT EP0 - 2 bits
-+ * 2'b00: 64 Bytes
-+ * 2'b01: 32
-+ * 2'b10: 16
-+ * 2'b11: 8 */
-+ unsigned mps:11;
-+#define DWC_DEP0CTL_MPS_64 0
-+#define DWC_DEP0CTL_MPS_32 1
-+#define DWC_DEP0CTL_MPS_16 2
-+#define DWC_DEP0CTL_MPS_8 3
-+
-+ /** Next Endpoint
-+ * IN EPn/IN EP0
-+ * OUT EPn/OUT EP0 - reserved */
-+ unsigned nextep:4;
-+
-+ /** USB Active Endpoint */
-+ unsigned usbactep:1;
-+
-+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
-+ * This field contains the PID of the packet going to
-+ * be received or transmitted on this endpoint. The
-+ * application should program the PID of the first
-+ * packet going to be received or transmitted on this
-+ * endpoint , after the endpoint is
-+ * activated. Application use the SetD1PID and
-+ * SetD0PID fields of this register to program either
-+ * D0 or D1 PID.
-+ *
-+ * The encoding for this field is
-+ * - 0: D0
-+ * - 1: D1
-+ */
-+ unsigned dpid:1;
-+
-+ /** NAK Status */
-+ unsigned naksts:1;
-+
-+ /** Endpoint Type
-+ * 2'b00: Control
-+ * 2'b01: Isochronous
-+ * 2'b10: Bulk
-+ * 2'b11: Interrupt */
-+ unsigned eptype:2;
-+
-+ /** Snoop Mode
-+ * OUT EPn/OUT EP0
-+ * IN EPn/IN EP0 - reserved */
-+ unsigned snp:1;
-+
-+ /** Stall Handshake */
-+ unsigned stall:1;
-+
-+ /** Tx Fifo Number
-+ * IN EPn/IN EP0
-+ * OUT EPn/OUT EP0 - reserved */
-+ unsigned txfnum:4;
-+
-+ /** Clear NAK */
-+ unsigned cnak:1;
-+ /** Set NAK */
-+ unsigned snak:1;
-+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
-+ * Writing to this field sets the Endpoint DPID (DPID)
-+ * field in this register to DATA0. Set Even
-+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
-+ * Writing to this field sets the Even/Odd
-+ * (micro)frame (EO_FrNum) field to even (micro)
-+ * frame.
-+ */
-+ unsigned setd0pid:1;
-+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
-+ * Writing to this field sets the Endpoint DPID (DPID)
-+ * field in this register to DATA1 Set Odd
-+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
-+ * Writing to this field sets the Even/Odd
-+ * (micro)frame (EO_FrNum) field to odd (micro) frame.
-+ */
-+ unsigned setd1pid:1;
-+
-+ /** Endpoint Disable */
-+ unsigned epdis:1;
-+ /** Endpoint Enable */
-+ unsigned epena:1;
-+ } b;
-+} depctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP Transfer
-+ * Size Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union deptsiz_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer size */
-+ unsigned xfersize:19;
-+/** Max packet count for EP (pow(2,10)-1) */
-+#define MAX_PKT_CNT 1023
-+ /** Packet Count */
-+ unsigned pktcnt:10;
-+ /** Multi Count - Periodic IN endpoints */
-+ unsigned mc:2;
-+ unsigned reserved:1;
-+ } b;
-+} deptsiz_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP 0 Transfer
-+ * Size Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union deptsiz0_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer size */
-+ unsigned xfersize:7;
-+ /** Reserved */
-+ unsigned reserved7_18:12;
-+ /** Packet Count */
-+ unsigned pktcnt:2;
-+ /** Reserved */
-+ unsigned reserved21_28:8;
-+ /**Setup Packet Count (DOEPTSIZ0 Only) */
-+ unsigned supcnt:2;
-+ unsigned reserved31;
-+ } b;
-+} deptsiz0_data_t;
-+
-+/////////////////////////////////////////////////
-+// DMA Descriptor Specific Structures
-+//
-+
-+/** Buffer status definitions */
-+
-+#define BS_HOST_READY 0x0
-+#define BS_DMA_BUSY 0x1
-+#define BS_DMA_DONE 0x2
-+#define BS_HOST_BUSY 0x3
-+
-+/** Receive/Transmit status definitions */
-+
-+#define RTS_SUCCESS 0x0
-+#define RTS_BUFFLUSH 0x1
-+#define RTS_RESERVED 0x2
-+#define RTS_BUFERR 0x3
-+
-+/**
-+ * This union represents the bit fields in the DMA Descriptor
-+ * status quadlet. Read the quadlet into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
-+ * <i>b_iso_in</i> elements.
-+ */
-+typedef union dev_dma_desc_sts {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** quadlet bits */
-+ struct {
-+ /** Received number of bytes */
-+ unsigned bytes:16;
-+ /** NAK bit - only for OUT EPs */
-+ unsigned nak:1;
-+ unsigned reserved17_22:6;
-+ /** Multiple Transfer - only for OUT EPs */
-+ unsigned mtrf:1;
-+ /** Setup Packet received - only for OUT EPs */
-+ unsigned sr:1;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** Short Packet */
-+ unsigned sp:1;
-+ /** Last */
-+ unsigned l:1;
-+ /** Receive Status */
-+ unsigned sts:2;
-+ /** Buffer Status */
-+ unsigned bs:2;
-+ } b;
-+
-+//#ifdef DWC_EN_ISOC
-+ /** iso out quadlet bits */
-+ struct {
-+ /** Received number of bytes */
-+ unsigned rxbytes:11;
-+
-+ unsigned reserved11:1;
-+ /** Frame Number */
-+ unsigned framenum:11;
-+ /** Received ISO Data PID */
-+ unsigned pid:2;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** Short Packet */
-+ unsigned sp:1;
-+ /** Last */
-+ unsigned l:1;
-+ /** Receive Status */
-+ unsigned rxsts:2;
-+ /** Buffer Status */
-+ unsigned bs:2;
-+ } b_iso_out;
-+
-+ /** iso in quadlet bits */
-+ struct {
-+ /** Transmited number of bytes */
-+ unsigned txbytes:12;
-+ /** Frame Number */
-+ unsigned framenum:11;
-+ /** Transmited ISO Data PID */
-+ unsigned pid:2;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** Short Packet */
-+ unsigned sp:1;
-+ /** Last */
-+ unsigned l:1;
-+ /** Transmit Status */
-+ unsigned txsts:2;
-+ /** Buffer Status */
-+ unsigned bs:2;
-+ } b_iso_in;
-+//#endif /* DWC_EN_ISOC */
-+} dev_dma_desc_sts_t;
-+
-+/**
-+ * DMA Descriptor structure
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+typedef struct dwc_otg_dev_dma_desc {
-+ /** DMA Descriptor status quadlet */
-+ dev_dma_desc_sts_t status;
-+ /** DMA Descriptor data buffer pointer */
-+ uint32_t buf;
-+} dwc_otg_dev_dma_desc_t;
-+
-+/**
-+ * The dwc_otg_dev_if structure contains information needed to manage
-+ * the DWC_otg controller acting in device mode. It represents the
-+ * programming view of the device-specific aspects of the controller.
-+ */
-+typedef struct dwc_otg_dev_if {
-+ /** Pointer to device Global registers.
-+ * Device Global Registers starting at offset 800h
-+ */
-+ dwc_otg_device_global_regs_t *dev_global_regs;
-+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
-+
-+ /**
-+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh
-+ */
-+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
-+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
-+#define DWC_EP_REG_OFFSET 0x20
-+
-+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
-+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
-+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
-+
-+ /* Device configuration information */
-+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
-+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
-+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
-+
-+ /** Size of periodic FIFOs (Bytes) */
-+ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+
-+ /** Size of Tx FIFOs (Bytes) */
-+ uint16_t tx_fifo_size[MAX_TX_FIFOS];
-+
-+ /** Thresholding enable flags and length varaiables **/
-+ uint16_t rx_thr_en;
-+ uint16_t iso_tx_thr_en;
-+ uint16_t non_iso_tx_thr_en;
-+
-+ uint16_t rx_thr_length;
-+ uint16_t tx_thr_length;
-+
-+ /**
-+ * Pointers to the DMA Descriptors for EP0 Control
-+ * transfers (virtual and physical)
-+ */
-+
-+ /** 2 descriptors for SETUP packets */
-+ dwc_dma_t dma_setup_desc_addr[2];
-+ dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
-+
-+ /** Pointer to Descriptor with latest SETUP packet */
-+ dwc_otg_dev_dma_desc_t *psetup;
-+
-+ /** Index of current SETUP handler descriptor */
-+ uint32_t setup_desc_index;
-+
-+ /** Descriptor for Data In or Status In phases */
-+ dwc_dma_t dma_in_desc_addr;
-+ dwc_otg_dev_dma_desc_t *in_desc_addr;
-+
-+ /** Descriptor for Data Out or Status Out phases */
-+ dwc_dma_t dma_out_desc_addr;
-+ dwc_otg_dev_dma_desc_t *out_desc_addr;
-+
-+ /** Setup Packet Detected - if set clear NAK when queueing */
-+ uint32_t spd;
-+ /** Isoc ep pointer on which incomplete happens */
-+ void *isoc_ep;
-+
-+} dwc_otg_dev_if_t;
-+
-+/////////////////////////////////////////////////
-+// Host Mode Register Structures
-+//
-+/**
-+ * The Host Global Registers structure defines the size and relative
-+ * field offsets for the Host Mode Global Registers. Host Global
-+ * Registers offsets 400h-7FFh.
-+*/
-+typedef struct dwc_otg_host_global_regs {
-+ /** Host Configuration Register. <i>Offset: 400h</i> */
-+ volatile uint32_t hcfg;
-+ /** Host Frame Interval Register. <i>Offset: 404h</i> */
-+ volatile uint32_t hfir;
-+ /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
-+ volatile uint32_t hfnum;
-+ /** Reserved. <i>Offset: 40Ch</i> */
-+ uint32_t reserved40C;
-+ /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
-+ volatile uint32_t hptxsts;
-+ /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
-+ volatile uint32_t haint;
-+ /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
-+ volatile uint32_t haintmsk;
-+ /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
-+ volatile uint32_t hflbaddr;
-+} dwc_otg_host_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Configuration Register.
-+ * Read the register into the <i>d32</i> member then set/clear the bits using
-+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
-+ */
-+typedef union hcfg_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** FS/LS Phy Clock Select */
-+ unsigned fslspclksel:2;
-+#define DWC_HCFG_30_60_MHZ 0
-+#define DWC_HCFG_48_MHZ 1
-+#define DWC_HCFG_6_MHZ 2
-+
-+ /** FS/LS Only Support */
-+ unsigned fslssupp:1;
-+ unsigned reserved3_6:4;
-+ /** Enable 32-KHz Suspend Mode */
-+ unsigned ena32khzs:1;
-+ /** Resume Validation Periiod */
-+ unsigned resvalid:8;
-+ unsigned reserved16_22:7;
-+ /** Enable Scatter/gather DMA in Host mode */
-+ unsigned descdma:1;
-+ /** Frame List Entries */
-+ unsigned frlisten:2;
-+ /** Enable Periodic Scheduling */
-+ unsigned perschedena:1;
-+ unsigned reserved27_30:4;
-+ unsigned modechtimen:1;
-+ } b;
-+} hcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Frame Remaing/Number
-+ * Register.
-+ */
-+typedef union hfir_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned frint:16;
-+ unsigned hfirrldctrl:1;
-+ unsigned reserved:15;
-+ } b;
-+} hfir_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Frame Remaing/Number
-+ * Register.
-+ */
-+typedef union hfnum_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned frnum:16;
-+#define DWC_HFNUM_MAX_FRNUM 0x3FFF
-+ unsigned frrem:16;
-+ } b;
-+} hfnum_data_t;
-+
-+typedef union hptxsts_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned ptxfspcavail:16;
-+ unsigned ptxqspcavail:8;
-+ /** Top of the Periodic Transmit Request Queue
-+ * - bit 24 - Terminate (last entry for the selected channel)
-+ * - bits 26:25 - Token Type
-+ * - 2'b00 - Zero length
-+ * - 2'b01 - Ping
-+ * - 2'b10 - Disable
-+ * - bits 30:27 - Channel Number
-+ * - bit 31 - Odd/even microframe
-+ */
-+ unsigned ptxqtop_terminate:1;
-+ unsigned ptxqtop_token:2;
-+ unsigned ptxqtop_chnum:4;
-+ unsigned ptxqtop_odd:1;
-+ } b;
-+} hptxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Port Control and Status
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hprt0 register.
-+ */
-+typedef union hprt0_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned prtconnsts:1;
-+ unsigned prtconndet:1;
-+ unsigned prtena:1;
-+ unsigned prtenchng:1;
-+ unsigned prtovrcurract:1;
-+ unsigned prtovrcurrchng:1;
-+ unsigned prtres:1;
-+ unsigned prtsusp:1;
-+ unsigned prtrst:1;
-+ unsigned reserved9:1;
-+ unsigned prtlnsts:2;
-+ unsigned prtpwr:1;
-+ unsigned prttstctl:4;
-+ unsigned prtspd:2;
-+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
-+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
-+#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
-+ unsigned reserved19_31:13;
-+ } b;
-+} hprt0_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union haint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned ch0:1;
-+ unsigned ch1:1;
-+ unsigned ch2:1;
-+ unsigned ch3:1;
-+ unsigned ch4:1;
-+ unsigned ch5:1;
-+ unsigned ch6:1;
-+ unsigned ch7:1;
-+ unsigned ch8:1;
-+ unsigned ch9:1;
-+ unsigned ch10:1;
-+ unsigned ch11:1;
-+ unsigned ch12:1;
-+ unsigned ch13:1;
-+ unsigned ch14:1;
-+ unsigned ch15:1;
-+ unsigned reserved:16;
-+ } b;
-+
-+ struct {
-+ unsigned chint:16;
-+ unsigned reserved:16;
-+ } b2;
-+} haint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union haintmsk_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned ch0:1;
-+ unsigned ch1:1;
-+ unsigned ch2:1;
-+ unsigned ch3:1;
-+ unsigned ch4:1;
-+ unsigned ch5:1;
-+ unsigned ch6:1;
-+ unsigned ch7:1;
-+ unsigned ch8:1;
-+ unsigned ch9:1;
-+ unsigned ch10:1;
-+ unsigned ch11:1;
-+ unsigned ch12:1;
-+ unsigned ch13:1;
-+ unsigned ch14:1;
-+ unsigned ch15:1;
-+ unsigned reserved:16;
-+ } b;
-+
-+ struct {
-+ unsigned chint:16;
-+ unsigned reserved:16;
-+ } b2;
-+} haintmsk_data_t;
-+
-+/**
-+ * Host Channel Specific Registers. <i>500h-5FCh</i>
-+ */
-+typedef struct dwc_otg_hc_regs {
-+ /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
-+ volatile uint32_t hcchar;
-+ /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
-+ volatile uint32_t hcsplt;
-+ /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
-+ volatile uint32_t hcint;
-+ /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
-+ volatile uint32_t hcintmsk;
-+ /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
-+ volatile uint32_t hctsiz;
-+ /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
-+ volatile uint32_t hcdma;
-+ volatile uint32_t reserved;
-+ /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
-+ volatile uint32_t hcdmab;
-+} dwc_otg_hc_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Characteristics
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcchar register.
-+ */
-+typedef union hcchar_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Maximum packet size in bytes */
-+ unsigned mps:11;
-+
-+ /** Endpoint number */
-+ unsigned epnum:4;
-+
-+ /** 0: OUT, 1: IN */
-+ unsigned epdir:1;
-+
-+ unsigned reserved:1;
-+
-+ /** 0: Full/high speed device, 1: Low speed device */
-+ unsigned lspddev:1;
-+
-+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
-+ unsigned eptype:2;
-+
-+ /** Packets per frame for periodic transfers. 0 is reserved. */
-+ unsigned multicnt:2;
-+
-+ /** Device address */
-+ unsigned devaddr:7;
-+
-+ /**
-+ * Frame to transmit periodic transaction.
-+ * 0: even, 1: odd
-+ */
-+ unsigned oddfrm:1;
-+
-+ /** Channel disable */
-+ unsigned chdis:1;
-+
-+ /** Channel enable */
-+ unsigned chen:1;
-+ } b;
-+} hcchar_data_t;
-+
-+typedef union hcsplt_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Port Address */
-+ unsigned prtaddr:7;
-+
-+ /** Hub Address */
-+ unsigned hubaddr:7;
-+
-+ /** Transaction Position */
-+ unsigned xactpos:2;
-+#define DWC_HCSPLIT_XACTPOS_MID 0
-+#define DWC_HCSPLIT_XACTPOS_END 1
-+#define DWC_HCSPLIT_XACTPOS_BEGIN 2
-+#define DWC_HCSPLIT_XACTPOS_ALL 3
-+
-+ /** Do Complete Split */
-+ unsigned compsplt:1;
-+
-+ /** Reserved */
-+ unsigned reserved:14;
-+
-+ /** Split Enble */
-+ unsigned spltena:1;
-+ } b;
-+} hcsplt_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union hcint_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** Transfer Complete */
-+ unsigned xfercomp:1;
-+ /** Channel Halted */
-+ unsigned chhltd:1;
-+ /** AHB Error */
-+ unsigned ahberr:1;
-+ /** STALL Response Received */
-+ unsigned stall:1;
-+ /** NAK Response Received */
-+ unsigned nak:1;
-+ /** ACK Response Received */
-+ unsigned ack:1;
-+ /** NYET Response Received */
-+ unsigned nyet:1;
-+ /** Transaction Err */
-+ unsigned xacterr:1;
-+ /** Babble Error */
-+ unsigned bblerr:1;
-+ /** Frame Overrun */
-+ unsigned frmovrun:1;
-+ /** Data Toggle Error */
-+ unsigned datatglerr:1;
-+ /** Buffer Not Available (only for DDMA mode) */
-+ unsigned bna:1;
-+ /** Exessive transaction error (only for DDMA mode) */
-+ unsigned xcs_xact:1;
-+ /** Frame List Rollover interrupt */
-+ unsigned frm_list_roll:1;
-+ /** Reserved */
-+ unsigned reserved14_31:18;
-+ } b;
-+} hcint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Interrupt Mask
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcintmsk register.
-+ */
-+typedef union hcintmsk_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ unsigned xfercompl:1;
-+ unsigned chhltd:1;
-+ unsigned ahberr:1;
-+ unsigned stall:1;
-+ unsigned nak:1;
-+ unsigned ack:1;
-+ unsigned nyet:1;
-+ unsigned xacterr:1;
-+ unsigned bblerr:1;
-+ unsigned frmovrun:1;
-+ unsigned datatglerr:1;
-+ unsigned bna:1;
-+ unsigned xcs_xact:1;
-+ unsigned frm_list_roll:1;
-+ unsigned reserved14_31:18;
-+ } b;
-+} hcintmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Transfer Size
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcchar register.
-+ */
-+
-+typedef union hctsiz_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Total transfer size in bytes */
-+ unsigned xfersize:19;
-+
-+ /** Data packets to transfer */
-+ unsigned pktcnt:10;
-+
-+ /**
-+ * Packet ID for next data packet
-+ * 0: DATA0
-+ * 1: DATA2
-+ * 2: DATA1
-+ * 3: MDATA (non-Control), SETUP (Control)
-+ */
-+ unsigned pid:2;
-+#define DWC_HCTSIZ_DATA0 0
-+#define DWC_HCTSIZ_DATA1 2
-+#define DWC_HCTSIZ_DATA2 1
-+#define DWC_HCTSIZ_MDATA 3
-+#define DWC_HCTSIZ_SETUP 3
-+
-+ /** Do PING protocol when 1 */
-+ unsigned dopng:1;
-+ } b;
-+
-+ /** register bits */
-+ struct {
-+ /** Scheduling information */
-+ unsigned schinfo:8;
-+
-+ /** Number of transfer descriptors.
-+ * Max value:
-+ * 64 in general,
-+ * 256 only for HS isochronous endpoint.
-+ */
-+ unsigned ntd:8;
-+
-+ /** Data packets to transfer */
-+ unsigned reserved16_28:13;
-+
-+ /**
-+ * Packet ID for next data packet
-+ * 0: DATA0
-+ * 1: DATA2
-+ * 2: DATA1
-+ * 3: MDATA (non-Control)
-+ */
-+ unsigned pid:2;
-+
-+ /** Do PING protocol when 1 */
-+ unsigned dopng:1;
-+ } b_ddma;
-+} hctsiz_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host DMA Address
-+ * Register used in Descriptor DMA mode.
-+ */
-+typedef union hcdma_data {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ unsigned reserved0_2:3;
-+ /** Current Transfer Descriptor. Not used for ISOC */
-+ unsigned ctd:8;
-+ /** Start Address of Descriptor List */
-+ unsigned dma_addr:21;
-+ } b;
-+} hcdma_data_t;
-+
-+/**
-+ * This union represents the bit fields in the DMA Descriptor
-+ * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union host_dma_desc_sts {
-+ /** raw register data */
-+ uint32_t d32;
-+ /** quadlet bits */
-+
-+ /* for non-isochronous */
-+ struct {
-+ /** Number of bytes */
-+ unsigned n_bytes:17;
-+ /** QTD offset to jump when Short Packet received - only for IN EPs */
-+ unsigned qtd_offset:6;
-+ /**
-+ * Set to request the core to jump to alternate QTD if
-+ * Short Packet received - only for IN EPs
-+ */
-+ unsigned a_qtd:1;
-+ /**
-+ * Setup Packet bit. When set indicates that buffer contains
-+ * setup packet.
-+ */
-+ unsigned sup:1;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ /** End of List */
-+ unsigned eol:1;
-+ unsigned reserved27:1;
-+ /** Rx/Tx Status */
-+ unsigned sts:2;
-+#define DMA_DESC_STS_PKTERR 1
-+ unsigned reserved30:1;
-+ /** Active Bit */
-+ unsigned a:1;
-+ } b;
-+ /* for isochronous */
-+ struct {
-+ /** Number of bytes */
-+ unsigned n_bytes:12;
-+ unsigned reserved12_24:13;
-+ /** Interrupt On Complete */
-+ unsigned ioc:1;
-+ unsigned reserved26_27:2;
-+ /** Rx/Tx Status */
-+ unsigned sts:2;
-+ unsigned reserved30:1;
-+ /** Active Bit */
-+ unsigned a:1;
-+ } b_isoc;
-+} host_dma_desc_sts_t;
-+
-+#define MAX_DMA_DESC_SIZE 131071
-+#define MAX_DMA_DESC_NUM_GENERIC 64
-+#define MAX_DMA_DESC_NUM_HS_ISOC 256
-+#define MAX_FRLIST_EN_NUM 64
-+/**
-+ * Host-mode DMA Descriptor structure
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+typedef struct dwc_otg_host_dma_desc {
-+ /** DMA Descriptor status quadlet */
-+ host_dma_desc_sts_t status;
-+ /** DMA Descriptor data buffer pointer */
-+ uint32_t buf;
-+} dwc_otg_host_dma_desc_t;
-+
-+/** OTG Host Interface Structure.
-+ *
-+ * The OTG Host Interface Structure structure contains information
-+ * needed to manage the DWC_otg controller acting in host mode. It
-+ * represents the programming view of the host-specific aspects of the
-+ * controller.
-+ */
-+typedef struct dwc_otg_host_if {
-+ /** Host Global Registers starting at offset 400h.*/
-+ dwc_otg_host_global_regs_t *host_global_regs;
-+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
-+
-+ /** Host Port 0 Control and Status Register */
-+ volatile uint32_t *hprt0;
-+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
-+
-+ /** Host Channel Specific Registers at offsets 500h-5FCh. */
-+ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
-+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
-+#define DWC_OTG_CHAN_REGS_OFFSET 0x20
-+
-+ /* Host configuration information */
-+ /** Number of Host Channels (range: 1-16) */
-+ uint8_t num_host_channels;
-+ /** Periodic EPs supported (0: no, 1: yes) */
-+ uint8_t perio_eps_supported;
-+ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
-+ uint16_t perio_tx_fifo_size;
-+
-+} dwc_otg_host_if_t;
-+
-+/**
-+ * This union represents the bit fields in the Power and Clock Gating Control
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union pcgcctl_data {
-+ /** raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** Stop Pclk */
-+ unsigned stoppclk:1;
-+ /** Gate Hclk */
-+ unsigned gatehclk:1;
-+ /** Power Clamp */
-+ unsigned pwrclmp:1;
-+ /** Reset Power Down Modules */
-+ unsigned rstpdwnmodule:1;
-+ /** Reserved */
-+ unsigned reserved:1;
-+ /** Enable Sleep Clock Gating (Enbl_L1Gating) */
-+ unsigned enbl_sleep_gating:1;
-+ /** PHY In Sleep (PhySleep) */
-+ unsigned phy_in_sleep:1;
-+ /** Deep Sleep*/
-+ unsigned deep_sleep:1;
-+ unsigned resetaftsusp:1;
-+ unsigned restoremode:1;
-+ unsigned enbl_extnd_hiber:1;
-+ unsigned extnd_hiber_pwrclmp:1;
-+ unsigned extnd_hiber_switch:1;
-+ unsigned ess_reg_restored:1;
-+ unsigned prt_clk_sel:2;
-+ unsigned port_power:1;
-+ unsigned max_xcvrselect:2;
-+ unsigned max_termsel:1;
-+ unsigned mac_dev_addr:7;
-+ unsigned p2hd_dev_enum_spd:2;
-+ unsigned p2hd_prt_spd:2;
-+ unsigned if_dev_mode:1;
-+ } b;
-+} pcgcctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Global Data FIFO Software
-+ * Configuration Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union gdfifocfg_data {
-+ /* raw register data */
-+ uint32_t d32;
-+ /** register bits */
-+ struct {
-+ /** OTG Data FIFO depth */
-+ unsigned gdfifocfg:16;
-+ /** Start address of EP info controller */
-+ unsigned epinfobase:16;
-+ } b;
-+} gdfifocfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Global Power Down Register
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gpwrdn_data {
-+ /* raw register data */
-+ uint32_t d32;
-+
-+ /** register bits */
-+ struct {
-+ /** PMU Interrupt Select */
-+ unsigned pmuintsel:1;
-+ /** PMU Active */
-+ unsigned pmuactv:1;
-+ /** Restore */
-+ unsigned restore:1;
-+ /** Power Down Clamp */
-+ unsigned pwrdnclmp:1;
-+ /** Power Down Reset */
-+ unsigned pwrdnrstn:1;
-+ /** Power Down Switch */
-+ unsigned pwrdnswtch:1;
-+ /** Disable VBUS */
-+ unsigned dis_vbus:1;
-+ /** Line State Change */
-+ unsigned lnstschng:1;
-+ /** Line state change mask */
-+ unsigned lnstchng_msk:1;
-+ /** Reset Detected */
-+ unsigned rst_det:1;
-+ /** Reset Detect mask */
-+ unsigned rst_det_msk:1;
-+ /** Disconnect Detected */
-+ unsigned disconn_det:1;
-+ /** Disconnect Detect mask */
-+ unsigned disconn_det_msk:1;
-+ /** Connect Detected*/
-+ unsigned connect_det:1;
-+ /** Connect Detected Mask*/
-+ unsigned connect_det_msk:1;
-+ /** SRP Detected */
-+ unsigned srp_det:1;
-+ /** SRP Detect mask */
-+ unsigned srp_det_msk:1;
-+ /** Status Change Interrupt */
-+ unsigned sts_chngint:1;
-+ /** Status Change Interrupt Mask */
-+ unsigned sts_chngint_msk:1;
-+ /** Line State */
-+ unsigned linestate:2;
-+ /** Indicates current mode(status of IDDIG signal) */
-+ unsigned idsts:1;
-+ /** B Session Valid signal status*/
-+ unsigned bsessvld:1;
-+ /** ADP Event Detected */
-+ unsigned adp_int:1;
-+ /** Multi Valued ID pin */
-+ unsigned mult_val_id_bc:5;
-+ /** Reserved 24_31 */
-+ unsigned reserved29_31:3;
-+ } b;
-+} gpwrdn_data_t;
-+
-+#endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/Makefile linux-rpi/drivers/usb/host/dwc_otg/Makefile
---- linux-3.18.14/drivers/usb/host/dwc_otg/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/Makefile 2015-05-31 14:46:12.901660961 -0500
-@@ -0,0 +1,82 @@
-+#
-+# Makefile for DWC_otg Highspeed USB controller driver
-+#
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+# Use the BUS_INTERFACE variable to compile the software for either
-+# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
-+ifeq ($(BUS_INTERFACE),)
-+# BUS_INTERFACE = -DPCI_INTERFACE
-+# BUS_INTERFACE = -DLM_INTERFACE
-+ BUS_INTERFACE = -DPLATFORM_INTERFACE
-+endif
-+
-+#ccflags-y += -DDEBUG
-+#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
-+
-+# Use one of the following flags to compile the software in host-only or
-+# device-only mode.
-+#ccflags-y += -DDWC_HOST_ONLY
-+#ccflags-y += -DDWC_DEVICE_ONLY
-+
-+ccflags-y += -Dlinux -DDWC_HS_ELECT_TST
-+#ccflags-y += -DDWC_EN_ISOC
-+ccflags-y += -I$(obj)/../dwc_common_port
-+#ccflags-y += -I$(PORTLIB)
-+ccflags-y += -DDWC_LINUX
-+ccflags-y += $(CFI)
-+ccflags-y += $(BUS_INTERFACE)
-+#ccflags-y += -DDWC_DEV_SRPCAP
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
-+
-+dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
-+dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
-+dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
-+dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
-+dwc_otg-objs += dwc_otg_adp.o
-+dwc_otg-objs += dwc_otg_fiq_fsm.o
-+dwc_otg-objs += dwc_otg_fiq_stub.o
-+ifneq ($(CFI),)
-+dwc_otg-objs += dwc_otg_cfi.o
-+endif
-+
-+kernrelwd := $(subst ., ,$(KERNELRELEASE))
-+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
-+
-+ifneq ($(kernrel3),2.6.20)
-+ccflags-y += $(CPPFLAGS)
-+endif
-+
-+else
-+
-+PWD := $(shell pwd)
-+PORTLIB := $(PWD)/../dwc_common_port
-+
-+# Command paths
-+CTAGS := $(CTAGS)
-+DOXYGEN := $(DOXYGEN)
-+
-+default: portlib
-+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+install: default
-+ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
-+ $(MAKE) -C$(KDIR) M=$(PWD) modules_install
-+
-+portlib:
-+ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+ cp $(PORTLIB)/Module.symvers $(PWD)/
-+
-+docs: $(wildcard *.[hc]) doc/doxygen.cfg
-+ $(DOXYGEN) doc/doxygen.cfg
-+
-+tags: $(wildcard *.[hc])
-+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+
-+clean:
-+ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
-+
-+endif
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
---- linux-3.18.14/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,337 @@
-+package dwc_otg_test;
-+
-+use strict;
-+use Exporter ();
-+
-+use vars qw(@ISA @EXPORT
-+$sysfsdir $paramdir $errors $params
-+);
-+
-+@ISA = qw(Exporter);
-+
-+#
-+# Globals
-+#
-+$sysfsdir = "/sys/devices/lm0";
-+$paramdir = "/sys/module/dwc_otg";
-+$errors = 0;
-+
-+$params = [
-+ {
-+ NAME => "otg_cap",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 2
-+ },
-+ {
-+ NAME => "dma_enable",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "dma_burst_size",
-+ DEFAULT => 32,
-+ ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
-+ LOW => 1,
-+ HIGH => 256
-+ },
-+ {
-+ NAME => "host_speed",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "host_support_fs_ls_low_power",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "host_ls_low_power_phy_clk",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "dev_speed",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "enable_dynamic_fifo",
-+ DEFAULT => 1,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ {
-+ NAME => "data_fifo_size",
-+ DEFAULT => 8192,
-+ ENUM => [],
-+ LOW => 32,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "dev_rx_fifo_size",
-+ DEFAULT => 1064,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "dev_nperio_tx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_1",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_2",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_3",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_4",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_5",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_6",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_7",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_8",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_9",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_10",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_11",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_12",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_13",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_14",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "dev_perio_tx_fifo_size_15",
-+ DEFAULT => 256,
-+ ENUM => [],
-+ LOW => 4,
-+ HIGH => 768
-+ },
-+ {
-+ NAME => "host_rx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "host_nperio_tx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "host_perio_tx_fifo_size",
-+ DEFAULT => 1024,
-+ ENUM => [],
-+ LOW => 16,
-+ HIGH => 32768
-+ },
-+ {
-+ NAME => "max_transfer_size",
-+ DEFAULT => 65535,
-+ ENUM => [],
-+ LOW => 2047,
-+ HIGH => 65535
-+ },
-+ {
-+ NAME => "max_packet_count",
-+ DEFAULT => 511,
-+ ENUM => [],
-+ LOW => 15,
-+ HIGH => 511
-+ },
-+ {
-+ NAME => "host_channels",
-+ DEFAULT => 12,
-+ ENUM => [],
-+ LOW => 1,
-+ HIGH => 16
-+ },
-+ {
-+ NAME => "dev_endpoints",
-+ DEFAULT => 6,
-+ ENUM => [],
-+ LOW => 1,
-+ HIGH => 15
-+ },
-+ {
-+ NAME => "phy_type",
-+ DEFAULT => 1,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 2
-+ },
-+ {
-+ NAME => "phy_utmi_width",
-+ DEFAULT => 16,
-+ ENUM => [8, 16],
-+ LOW => 8,
-+ HIGH => 16
-+ },
-+ {
-+ NAME => "phy_ulpi_ddr",
-+ DEFAULT => 0,
-+ ENUM => [],
-+ LOW => 0,
-+ HIGH => 1
-+ },
-+ ];
-+
-+
-+#
-+#
-+sub check_arch {
-+ $_ = `uname -m`;
-+ chomp;
-+ unless (m/armv4tl/) {
-+ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n";
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+#
-+#
-+sub load_module {
-+ my $params = shift;
-+ print "\nRemoving Module\n";
-+ system "rmmod dwc_otg";
-+ print "Loading Module\n";
-+ if ($params ne "") {
-+ print "Module Parameters: $params\n";
-+ }
-+ if (system("modprobe dwc_otg $params")) {
-+ warn "Unable to load module\n";
-+ return 0;
-+ }
-+ return 1;
-+}
-+
-+#
-+#
-+sub test_status {
-+ my $arg = shift;
-+
-+ print "\n";
-+
-+ if (defined $arg) {
-+ warn "WARNING: $arg\n";
-+ }
-+
-+ if ($errors > 0) {
-+ warn "TEST FAILED with $errors errors\n";
-+ return 0;
-+ } else {
-+ print "TEST PASSED\n";
-+ return 0 if (defined $arg);
-+ }
-+ return 1;
-+}
-+
-+#
-+#
-+@EXPORT = qw(
-+$sysfsdir
-+$paramdir
-+$params
-+$errors
-+check_arch
-+load_module
-+test_status
-+);
-+
-+1;
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/test/Makefile linux-rpi/drivers/usb/host/dwc_otg/test/Makefile
---- linux-3.18.14/drivers/usb/host/dwc_otg/test/Makefile 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/Makefile 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,16 @@
-+
-+PERL=/usr/bin/perl
-+PL_TESTS=test_sysfs.pl test_mod_param.pl
-+
-+.PHONY : test
-+test : perl_tests
-+
-+perl_tests :
-+ @echo
-+ @echo Running perl tests
-+ @for test in $(PL_TESTS); do \
-+ if $(PERL) ./$$test ; then \
-+ echo "=======> $$test, PASSED" ; \
-+ else echo "=======> $$test, FAILED" ; \
-+ fi \
-+ done
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/test/test_mod_param.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl
---- linux-3.18.14/drivers/usb/host/dwc_otg/test/test_mod_param.pl 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,133 @@
-+#!/usr/bin/perl -w
-+#
-+# Run this program on the integrator.
-+#
-+# - Tests module parameter default values.
-+# - Tests setting of valid module parameter values via modprobe.
-+# - Tests invalid module parameter values.
-+# -----------------------------------------------------------------------------
-+use strict;
-+use dwc_otg_test;
-+
-+check_arch() or die;
-+
-+#
-+#
-+sub test {
-+ my ($param,$expected) = @_;
-+ my $value = get($param);
-+
-+ if ($value == $expected) {
-+ print "$param = $value, okay\n";
-+ }
-+
-+ else {
-+ warn "ERROR: value of $param != $expected, $value\n";
-+ $errors ++;
-+ }
-+}
-+
-+#
-+#
-+sub get {
-+ my $param = shift;
-+ my $tmp = `cat $paramdir/$param`;
-+ chomp $tmp;
-+ return $tmp;
-+}
-+
-+#
-+#
-+sub test_main {
-+
-+ print "\nTesting Module Parameters\n";
-+
-+ load_module("") or die;
-+
-+ # Test initial values
-+ print "\nTesting Default Values\n";
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+
-+ # Test low value
-+ print "\nTesting Low Value\n";
-+ my $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{LOW});
-+ }
-+
-+ # Test high value
-+ print "\nTesting High Value\n";
-+ $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{HIGH});
-+ }
-+
-+ # Test Enum
-+ print "\nTesting Enumerated\n";
-+ foreach (@{$params}) {
-+ if (defined $_->{ENUM}) {
-+ my $value;
-+ foreach $value (@{$_->{ENUM}}) {
-+ $cmd_params = "$_->{NAME}=$value";
-+ load_module($cmd_params) or die;
-+ test ($_->{NAME}, $value);
-+ }
-+ }
-+ }
-+
-+ # Test Invalid Values
-+ print "\nTesting Invalid Values\n";
-+ $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+
-+ $cmd_params = "";
-+ foreach (@{$params}) {
-+ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
-+ }
-+ load_module($cmd_params) or die;
-+
-+ foreach (@{$params}) {
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+
-+ print "\nTesting Enumerated\n";
-+ foreach (@{$params}) {
-+ if (defined $_->{ENUM}) {
-+ my $value;
-+ foreach $value (@{$_->{ENUM}}) {
-+ $value = $value + 1;
-+ $cmd_params = "$_->{NAME}=$value";
-+ load_module($cmd_params) or die;
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ $value = $value - 2;
-+ $cmd_params = "$_->{NAME}=$value";
-+ load_module($cmd_params) or die;
-+ test ($_->{NAME}, $_->{DEFAULT});
-+ }
-+ }
-+ }
-+
-+ test_status() or die;
-+}
-+
-+test_main();
-+0;
-diff -Nur linux-3.18.14/drivers/usb/host/dwc_otg/test/test_sysfs.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl
---- linux-3.18.14/drivers/usb/host/dwc_otg/test/test_sysfs.pl 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl 2015-05-31 14:46:12.909660961 -0500
-@@ -0,0 +1,193 @@
-+#!/usr/bin/perl -w
-+#
-+# Run this program on the integrator
-+# - Tests select sysfs attributes.
-+# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
-+# -----------------------------------------------------------------------------
-+use strict;
-+use dwc_otg_test;
-+
-+check_arch() or die;
-+
-+#
-+#
-+sub test {
-+ my ($attr,$expected) = @_;
-+ my $string = get($attr);
-+
-+ if ($string eq $expected) {
-+ printf("$attr = $string, okay\n");
-+ }
-+ else {
-+ warn "ERROR: value of $attr != $expected, $string\n";
-+ $errors ++;
-+ }
-+}
-+
-+#
-+#
-+sub set {
-+ my ($reg, $value) = @_;
-+ system "echo $value > $sysfsdir/$reg";
-+}
-+
-+#
-+#
-+sub get {
-+ my $attr = shift;
-+ my $string = `cat $sysfsdir/$attr`;
-+ chomp $string;
-+ if ($string =~ m/\s\=\s/) {
-+ my $tmp;
-+ ($tmp, $string) = split /\s=\s/, $string;
-+ }
-+ return $string;
-+}
-+
-+#
-+#
-+sub test_main {
-+ print("\nTesting Sysfs Attributes\n");
-+
-+ load_module("") or die;
-+
-+ # Test initial values of regoffset/regvalue/guid/gsnpsid
-+ print("\nTesting Default Values\n");
-+
-+ test("regoffset", "0xffffffff");
-+ test("regvalue", "invalid offset");
-+ test("guid", "0x12345678"); # this will fail if it has been changed
-+ test("gsnpsid", "0x4f54200a");
-+
-+ # Test operation of regoffset/regvalue
-+ print("\nTesting regoffset\n");
-+ set('regoffset', '5a5a5a5a');
-+ test("regoffset", "0xffffffff");
-+
-+ set('regoffset', '0');
-+ test("regoffset", "0x00000000");
-+
-+ set('regoffset', '40000');
-+ test("regoffset", "0x00000000");
-+
-+ set('regoffset', '3ffff');
-+ test("regoffset", "0x0003ffff");
-+
-+ set('regoffset', '1');
-+ test("regoffset", "0x00000001");
-+
-+ print("\nTesting regvalue\n");
-+ set('regoffset', '3c');
-+ test("regvalue", "0x12345678");
-+ set('regvalue', '5a5a5a5a');
-+ test("regvalue", "0x5a5a5a5a");
-+ set('regvalue','a5a5a5a5');
-+ test("regvalue", "0xa5a5a5a5");
-+ set('guid','12345678');
-+
-+ # Test HNP Capable
-+ print("\nTesting HNP Capable bit\n");
-+ set('hnpcapable', '1');
-+ test("hnpcapable", "0x1");
-+ set('hnpcapable','0');
-+ test("hnpcapable", "0x0");
-+
-+ set('regoffset','0c');
-+
-+ my $old = get('gusbcfg');
-+ print("setting hnpcapable\n");
-+ set('hnpcapable', '1');
-+ test("hnpcapable", "0x1");
-+ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
-+ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
-+
-+ $old = get('gusbcfg');
-+ print("clearing hnpcapable\n");
-+ set('hnpcapable', '0');
-+ test("hnpcapable", "0x0");
-+ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
-+ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
-+
-+ # Test SRP Capable
-+ print("\nTesting SRP Capable bit\n");
-+ set('srpcapable', '1');
-+ test("srpcapable", "0x1");
-+ set('srpcapable','0');
-+ test("srpcapable", "0x0");
-+
-+ set('regoffset','0c');
-+
-+ $old = get('gusbcfg');
-+ print("setting srpcapable\n");
-+ set('srpcapable', '1');
-+ test("srpcapable", "0x1");
-+ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
-+ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
-+
-+ $old = get('gusbcfg');
-+ print("clearing srpcapable\n");
-+ set('srpcapable', '0');
-+ test("srpcapable", "0x0");
-+ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
-+ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
-+
-+ # Test GGPIO
-+ print("\nTesting GGPIO\n");
-+ set('ggpio','5a5a5a5a');
-+ test('ggpio','0x5a5a0000');
-+ set('ggpio','a5a5a5a5');
-+ test('ggpio','0xa5a50000');
-+ set('ggpio','11110000');
-+ test('ggpio','0x11110000');
-+ set('ggpio','00001111');
-+ test('ggpio','0x00000000');
-+
-+ # Test DEVSPEED
-+ print("\nTesting DEVSPEED\n");
-+ set('regoffset','800');
-+ $old = get('regvalue');
-+ set('devspeed','0');
-+ test('devspeed','0x0');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
-+ set('devspeed','1');
-+ test('devspeed','0x1');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
-+ set('devspeed','2');
-+ test('devspeed','0x2');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
-+ set('devspeed','3');
-+ test('devspeed','0x3');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
-+ set('devspeed','4');
-+ test('devspeed','0x0');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
-+ set('devspeed','5');
-+ test('devspeed','0x1');
-+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
-+
-+
-+ # mode Returns the current mode:0 for device mode1 for host mode Read
-+ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write
-+ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write
-+ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write
-+ # bussuspend Suspend the USB bus. Read/Write
-+ # busconnected Get the connection status of the bus Read
-+
-+ # gotgctl Get or set the Core Control Status Register. Read/Write
-+ ## gusbcfg Get or set the Core USB Configuration Register Read/Write
-+ # grxfsiz Get or set the Receive FIFO Size Register Read/Write
-+ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write
-+ # gpvndctl Get or set the PHY Vendor Control Register Read/Write
-+ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
-+ ## guid Get or set the value of the User ID Register Read/Write
-+ ## gsnpsid Get the value of the Synopsys ID Regester Read
-+ ## devspeed Get or set the device speed setting in the DCFG register Read/Write
-+ # enumspeed Gets the device enumeration Speed. Read
-+ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read
-+ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write
-+
-+ test_status("TEST NYI") or die;
-+}
-+
-+test_main();
-+0;
-diff -Nur linux-3.18.14/drivers/usb/host/Kconfig linux-rpi/drivers/usb/host/Kconfig
---- linux-3.18.14/drivers/usb/host/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/host/Kconfig 2015-05-31 14:46:12.889660961 -0500
-@@ -744,6 +744,19 @@
- To compile this driver a module, choose M here: the module
- will be called "hwa-hc".
-
-+config USB_DWCOTG
-+ tristate "Synopsis DWC host support"
-+ depends on USB
-+ help
-+ The Synopsis DWC controller is a dual-role
-+ host/peripheral/OTG ("On The Go") USB controllers.
-+
-+ Enable this option to support this IP in host controller mode.
-+ If unsure, say N.
-+
-+ To compile this driver as a module, choose M here: the
-+ modules built will be called dwc_otg and dwc_common_port.
-+
- config USB_IMX21_HCD
- tristate "i.MX21 HCD support"
- depends on ARM && ARCH_MXC
-diff -Nur linux-3.18.14/drivers/usb/host/Makefile linux-rpi/drivers/usb/host/Makefile
---- linux-3.18.14/drivers/usb/host/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/host/Makefile 2015-05-31 14:46:12.889660961 -0500
-@@ -71,6 +71,8 @@
- obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
- obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
- obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/
- obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
- obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
- obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
-diff -Nur linux-3.18.14/drivers/usb/Makefile linux-rpi/drivers/usb/Makefile
---- linux-3.18.14/drivers/usb/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/usb/Makefile 2015-05-31 14:46:12.845660962 -0500
-@@ -24,6 +24,7 @@
- obj-$(CONFIG_USB_R8A66597_HCD) += host/
- obj-$(CONFIG_USB_HWA_HCD) += host/
- obj-$(CONFIG_USB_ISP1760_HCD) += host/
-+obj-$(CONFIG_USB_DWCOTG) += host/
- obj-$(CONFIG_USB_IMX21_HCD) += host/
- obj-$(CONFIG_USB_FSL_MPH_DR_OF) += host/
- obj-$(CONFIG_USB_FUSBH200_HCD) += host/
-diff -Nur linux-3.18.14/drivers/video/fbdev/bcm2708_fb.c linux-rpi/drivers/video/fbdev/bcm2708_fb.c
---- linux-3.18.14/drivers/video/fbdev/bcm2708_fb.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/video/fbdev/bcm2708_fb.c 2015-05-31 14:46:13.001660960 -0500
-@@ -0,0 +1,818 @@
-+/*
-+ * linux/drivers/video/bcm2708_fb.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Broadcom simple framebuffer driver
-+ *
-+ * This file is derived from cirrusfb.c
-+ * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/list.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/printk.h>
-+#include <linux/console.h>
-+#include <linux/debugfs.h>
-+
-+#include <mach/dma.h>
-+#include <mach/platform.h>
-+#include <mach/vcio.h>
-+
-+#include <asm/sizes.h>
-+#include <linux/io.h>
-+#include <linux/dma-mapping.h>
-+
-+//#define BCM2708_FB_DEBUG
-+#define MODULE_NAME "bcm2708_fb"
-+
-+#ifdef BCM2708_FB_DEBUG
-+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+
-+/* This is limited to 16 characters when displayed by X startup */
-+static const char *bcm2708_name = "BCM2708 FB";
-+
-+#define DRIVER_NAME "bcm2708_fb"
-+
-+static int fbwidth = 800; /* module parameter */
-+static int fbheight = 480; /* module parameter */
-+static int fbdepth = 16; /* module parameter */
-+static int fbswap = 0; /* module parameter */
-+
-+static u32 dma_busy_wait_threshold = 1<<15;
-+module_param(dma_busy_wait_threshold, int, 0644);
-+MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area");
-+
-+/* this data structure describes each frame buffer device we find */
-+
-+struct fbinfo_s {
-+ u32 xres, yres, xres_virtual, yres_virtual;
-+ u32 pitch, bpp;
-+ u32 xoffset, yoffset;
-+ u32 base;
-+ u32 screen_size;
-+ u16 cmap[256];
-+};
-+
-+struct bcm2708_fb_stats {
-+ struct debugfs_regset32 regset;
-+ u32 dma_copies;
-+ u32 dma_irqs;
-+};
-+
-+struct bcm2708_fb {
-+ struct fb_info fb;
-+ struct platform_device *dev;
-+ struct fbinfo_s *info;
-+ dma_addr_t dma;
-+ u32 cmap[16];
-+ int dma_chan;
-+ int dma_irq;
-+ void __iomem *dma_chan_base;
-+ void *cb_base; /* DMA control blocks */
-+ dma_addr_t cb_handle;
-+ struct dentry *debugfs_dir;
-+ wait_queue_head_t dma_waitq;
-+ struct bcm2708_fb_stats stats;
-+ unsigned long fb_bus_address;
-+};
-+
-+#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb)
-+
-+static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb)
-+{
-+ debugfs_remove_recursive(fb->debugfs_dir);
-+ fb->debugfs_dir = NULL;
-+}
-+
-+static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb)
-+{
-+ static struct debugfs_reg32 stats_registers[] = {
-+ {
-+ "dma_copies",
-+ offsetof(struct bcm2708_fb_stats, dma_copies)
-+ },
-+ {
-+ "dma_irqs",
-+ offsetof(struct bcm2708_fb_stats, dma_irqs)
-+ },
-+ };
-+
-+ fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);
-+ if (!fb->debugfs_dir) {
-+ pr_warn("%s: could not create debugfs entry\n",
-+ __func__);
-+ return -EFAULT;
-+ }
-+
-+ fb->stats.regset.regs = stats_registers;
-+ fb->stats.regset.nregs = ARRAY_SIZE(stats_registers);
-+ fb->stats.regset.base = &fb->stats;
-+
-+ if (!debugfs_create_regset32(
-+ "stats", 0444, fb->debugfs_dir, &fb->stats.regset)) {
-+ pr_warn("%s: could not create statistics registers\n",
-+ __func__);
-+ goto fail;
-+ }
-+ return 0;
-+
-+fail:
-+ bcm2708_fb_debugfs_deinit(fb);
-+ return -EFAULT;
-+}
-+
-+static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var)
-+{
-+ int ret = 0;
-+
-+ memset(&var->transp, 0, sizeof(var->transp));
-+
-+ var->red.msb_right = 0;
-+ var->green.msb_right = 0;
-+ var->blue.msb_right = 0;
-+
-+ switch (var->bits_per_pixel) {
-+ case 1:
-+ case 2:
-+ case 4:
-+ case 8:
-+ var->red.length = var->bits_per_pixel;
-+ var->red.offset = 0;
-+ var->green.length = var->bits_per_pixel;
-+ var->green.offset = 0;
-+ var->blue.length = var->bits_per_pixel;
-+ var->blue.offset = 0;
-+ break;
-+ case 16:
-+ var->red.length = 5;
-+ var->blue.length = 5;
-+ /*
-+ * Green length can be 5 or 6 depending whether
-+ * we're operating in RGB555 or RGB565 mode.
-+ */
-+ if (var->green.length != 5 && var->green.length != 6)
-+ var->green.length = 6;
-+ break;
-+ case 24:
-+ var->red.length = 8;
-+ var->blue.length = 8;
-+ var->green.length = 8;
-+ break;
-+ case 32:
-+ var->red.length = 8;
-+ var->green.length = 8;
-+ var->blue.length = 8;
-+ var->transp.length = 8;
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ /*
-+ * >= 16bpp displays have separate colour component bitfields
-+ * encoded in the pixel data. Calculate their position from
-+ * the bitfield length defined above.
-+ */
-+ if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) {
-+ var->blue.offset = 0;
-+ var->green.offset = var->blue.offset + var->blue.length;
-+ var->red.offset = var->green.offset + var->green.length;
-+ var->transp.offset = var->red.offset + var->red.length;
-+ } else if (ret == 0 && var->bits_per_pixel >= 24) {
-+ var->red.offset = 0;
-+ var->green.offset = var->red.offset + var->red.length;
-+ var->blue.offset = var->green.offset + var->green.length;
-+ var->transp.offset = var->blue.offset + var->blue.length;
-+ } else if (ret == 0 && var->bits_per_pixel >= 16) {
-+ var->blue.offset = 0;
-+ var->green.offset = var->blue.offset + var->blue.length;
-+ var->red.offset = var->green.offset + var->green.length;
-+ var->transp.offset = var->red.offset + var->red.length;
-+ }
-+
-+ return ret;
-+}
-+
-+static int bcm2708_fb_check_var(struct fb_var_screeninfo *var,
-+ struct fb_info *info)
-+{
-+ /* info input, var output */
-+ int yres;
-+
-+ /* info input, var output */
-+ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+ info->var.xres, info->var.yres, info->var.xres_virtual,
-+ info->var.yres_virtual, (int)info->screen_size,
-+ info->var.bits_per_pixel);
-+ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var,
-+ var->xres, var->yres, var->xres_virtual, var->yres_virtual,
-+ var->bits_per_pixel);
-+
-+ if (!var->bits_per_pixel)
-+ var->bits_per_pixel = 16;
-+
-+ if (bcm2708_fb_set_bitfields(var) != 0) {
-+ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n",
-+ var->bits_per_pixel);
-+ return -EINVAL;
-+ }
-+
-+
-+ if (var->xres_virtual < var->xres)
-+ var->xres_virtual = var->xres;
-+ /* use highest possible virtual resolution */
-+ if (var->yres_virtual == -1) {
-+ var->yres_virtual = 480;
-+
-+ pr_err
-+ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n",
-+ var->xres_virtual, var->yres_virtual);
-+ }
-+ if (var->yres_virtual < var->yres)
-+ var->yres_virtual = var->yres;
-+
-+ if (var->xoffset < 0)
-+ var->xoffset = 0;
-+ if (var->yoffset < 0)
-+ var->yoffset = 0;
-+
-+ /* truncate xoffset and yoffset to maximum if too high */
-+ if (var->xoffset > var->xres_virtual - var->xres)
-+ var->xoffset = var->xres_virtual - var->xres - 1;
-+ if (var->yoffset > var->yres_virtual - var->yres)
-+ var->yoffset = var->yres_virtual - var->yres - 1;
-+
-+ yres = var->yres;
-+ if (var->vmode & FB_VMODE_DOUBLE)
-+ yres *= 2;
-+ else if (var->vmode & FB_VMODE_INTERLACED)
-+ yres = (yres + 1) / 2;
-+
-+ return 0;
-+}
-+
-+static int bcm2708_fb_set_par(struct fb_info *info)
-+{
-+ uint32_t val = 0;
-+ struct bcm2708_fb *fb = to_bcm2708(info);
-+ volatile struct fbinfo_s *fbinfo = fb->info;
-+ fbinfo->xres = info->var.xres;
-+ fbinfo->yres = info->var.yres;
-+ fbinfo->xres_virtual = info->var.xres_virtual;
-+ fbinfo->yres_virtual = info->var.yres_virtual;
-+ fbinfo->bpp = info->var.bits_per_pixel;
-+ fbinfo->xoffset = info->var.xoffset;
-+ fbinfo->yoffset = info->var.yoffset;
-+ fbinfo->base = 0; /* filled in by VC */
-+ fbinfo->pitch = 0; /* filled in by VC */
-+
-+ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+ info->var.xres, info->var.yres, info->var.xres_virtual,
-+ info->var.yres_virtual, (int)info->screen_size,
-+ info->var.bits_per_pixel);
-+
-+ /* ensure last write to fbinfo is visible to GPU */
-+ wmb();
-+
-+ /* inform vc about new framebuffer */
-+ bcm_mailbox_write(MBOX_CHAN_FB, fb->dma);
-+
-+ /* TODO: replace fb driver with vchiq version */
-+ /* wait for response */
-+ bcm_mailbox_read(MBOX_CHAN_FB, &val);
-+
-+ /* ensure GPU writes are visible to us */
-+ rmb();
-+
-+ if (val == 0) {
-+ fb->fb.fix.line_length = fbinfo->pitch;
-+
-+ if (info->var.bits_per_pixel <= 8)
-+ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
-+ else
-+ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
-+
-+ fb->fb_bus_address = fbinfo->base;
-+ fbinfo->base &= ~0xc0000000;
-+ fb->fb.fix.smem_start = fbinfo->base;
-+ fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual;
-+ fb->fb.screen_size = fbinfo->screen_size;
-+ if (fb->fb.screen_base)
-+ iounmap(fb->fb.screen_base);
-+ fb->fb.screen_base =
-+ (void *)ioremap_wc(fbinfo->base, fb->fb.screen_size);
-+ if (!fb->fb.screen_base) {
-+ /* the console may currently be locked */
-+ console_trylock();
-+ console_unlock();
-+
-+ BUG(); /* what can we do here */
-+ }
-+ }
-+ print_debug
-+ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n",
-+ (void *)fb->fb.screen_base, (void *)fb->fb_bus_address,
-+ fbinfo->xres, fbinfo->yres, fbinfo->bpp,
-+ fbinfo->pitch, (int)fb->fb.screen_size, val);
-+
-+ return val;
-+}
-+
-+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
-+{
-+ unsigned int mask = (1 << bf->length) - 1;
-+
-+ return (val >> (16 - bf->length) & mask) << bf->offset;
-+}
-+
-+
-+static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red,
-+ unsigned int green, unsigned int blue,
-+ unsigned int transp, struct fb_info *info)
-+{
-+ struct bcm2708_fb *fb = to_bcm2708(info);
-+
-+ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/
-+ if (fb->fb.var.bits_per_pixel <= 8) {
-+ if (regno < 256) {
-+ /* blue [0:4], green [5:10], red [11:15] */
-+ fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 |
-+ ((green >> (16-6)) & 0x3f) << 5 |
-+ ((blue >> (16-5)) & 0x1f) << 0;
-+ }
-+ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */
-+ /* So just call it for what looks like the last colour in a list for now. */
-+ if (regno == 15 || regno == 255)
-+ bcm2708_fb_set_par(info);
-+ } else if (regno < 16) {
-+ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
-+ convert_bitfield(blue, &fb->fb.var.blue) |
-+ convert_bitfield(green, &fb->fb.var.green) |
-+ convert_bitfield(red, &fb->fb.var.red);
-+ }
-+ return regno > 255;
-+}
-+
-+static int bcm2708_fb_blank(int blank_mode, struct fb_info *info)
-+{
-+ s32 result = -1;
-+ u32 p[7];
-+ if ( (blank_mode == FB_BLANK_NORMAL) ||
-+ (blank_mode == FB_BLANK_UNBLANK)) {
-+
-+ p[0] = 28; // size = sizeof u32 * length of p
-+ p[1] = VCMSG_PROCESS_REQUEST; // process request
-+ p[2] = VCMSG_SET_BLANK_SCREEN; // (the tag id)
-+ p[3] = 4; // (size of the response buffer)
-+ p[4] = 4; // (size of the request data)
-+ p[5] = blank_mode;
-+ p[6] = VCMSG_PROPERTY_END; // end tag
-+
-+ bcm_mailbox_property(&p, p[0]);
-+
-+ if ( p[1] == VCMSG_REQUEST_SUCCESSFUL )
-+ result = 0;
-+ else
-+ pr_err("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]);
-+ }
-+ return result;
-+}
-+
-+static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-+{
-+ s32 result = -1;
-+ info->var.xoffset = var->xoffset;
-+ info->var.yoffset = var->yoffset;
-+ result = bcm2708_fb_set_par(info);
-+ if (result != 0)
-+ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result);
-+ return result;
-+}
-+
-+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
-+{
-+ s32 result = -1;
-+ u32 p[7];
-+ if (cmd == FBIO_WAITFORVSYNC) {
-+ p[0] = 28; // size = sizeof u32 * length of p
-+ p[1] = VCMSG_PROCESS_REQUEST; // process request
-+ p[2] = VCMSG_SET_VSYNC; // (the tag id)
-+ p[3] = 4; // (size of the response buffer)
-+ p[4] = 4; // (size of the request data)
-+ p[5] = 0; // dummy
-+ p[6] = VCMSG_PROPERTY_END; // end tag
-+
-+ bcm_mailbox_property(&p, p[0]);
-+
-+ if ( p[1] == VCMSG_REQUEST_SUCCESSFUL )
-+ result = 0;
-+ else
-+ pr_err("bcm2708_fb_ioctl %x,%lx returns=%d p[1]=0x%x\n", cmd, arg, p[5], p[1]);
-+ }
-+ return result;
-+}
-+static void bcm2708_fb_fillrect(struct fb_info *info,
-+ const struct fb_fillrect *rect)
-+{
-+ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */
-+ cfb_fillrect(info, rect);
-+}
-+
-+/* A helper function for configuring dma control block */
-+static void set_dma_cb(struct bcm2708_dma_cb *cb,
-+ int burst_size,
-+ dma_addr_t dst,
-+ int dst_stride,
-+ dma_addr_t src,
-+ int src_stride,
-+ int w,
-+ int h)
-+{
-+ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |
-+ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |
-+ BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;
-+ cb->dst = dst;
-+ cb->src = src;
-+ /*
-+ * This is not really obvious from the DMA documentation,
-+ * but the top 16 bits must be programmmed to "height -1"
-+ * and not "height" in 2D mode.
-+ */
-+ cb->length = ((h - 1) << 16) | w;
-+ cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w);
-+ cb->pad[0] = 0;
-+ cb->pad[1] = 0;
-+}
-+
-+static void bcm2708_fb_copyarea(struct fb_info *info,
-+ const struct fb_copyarea *region)
-+{
-+ struct bcm2708_fb *fb = to_bcm2708(info);
-+ struct bcm2708_dma_cb *cb = fb->cb_base;
-+ int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;
-+ /* Channel 0 supports larger bursts and is a bit faster */
-+ int burst_size = (fb->dma_chan == 0) ? 8 : 2;
-+ int pixels = region->width * region->height;
-+
-+ /* Fallback to cfb_copyarea() if we don't like something */
-+ if (in_atomic() ||
-+ bytes_per_pixel > 4 ||
-+ info->var.xres * info->var.yres > 1920 * 1200 ||
-+ region->width <= 0 || region->width > info->var.xres ||
-+ region->height <= 0 || region->height > info->var.yres ||
-+ region->sx < 0 || region->sx >= info->var.xres ||
-+ region->sy < 0 || region->sy >= info->var.yres ||
-+ region->dx < 0 || region->dx >= info->var.xres ||
-+ region->dy < 0 || region->dy >= info->var.yres ||
-+ region->sx + region->width > info->var.xres ||
-+ region->dx + region->width > info->var.xres ||
-+ region->sy + region->height > info->var.yres ||
-+ region->dy + region->height > info->var.yres) {
-+ cfb_copyarea(info, region);
-+ return;
-+ }
-+
-+ if (region->dy == region->sy && region->dx > region->sx) {
-+ /*
-+ * A difficult case of overlapped copy. Because DMA can't
-+ * copy individual scanlines in backwards direction, we need
-+ * two-pass processing. We do it by programming a chain of dma
-+ * control blocks in the first 16K part of the buffer and use
-+ * the remaining 48K as the intermediate temporary scratch
-+ * buffer. The buffer size is sufficient to handle up to
-+ * 1920x1200 resolution at 32bpp pixel depth.
-+ */
-+ int y;
-+ dma_addr_t control_block_pa = fb->cb_handle;
-+ dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024;
-+ int scanline_size = bytes_per_pixel * region->width;
-+ int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size;
-+
-+ for (y = 0; y < region->height; y += scanlines_per_cb) {
-+ dma_addr_t src =
-+ fb->fb_bus_address +
-+ bytes_per_pixel * region->sx +
-+ (region->sy + y) * fb->fb.fix.line_length;
-+ dma_addr_t dst =
-+ fb->fb_bus_address +
-+ bytes_per_pixel * region->dx +
-+ (region->dy + y) * fb->fb.fix.line_length;
-+
-+ if (region->height - y < scanlines_per_cb)
-+ scanlines_per_cb = region->height - y;
-+
-+ set_dma_cb(cb, burst_size, scratchbuf, scanline_size,
-+ src, fb->fb.fix.line_length,
-+ scanline_size, scanlines_per_cb);
-+ control_block_pa += sizeof(struct bcm2708_dma_cb);
-+ cb->next = control_block_pa;
-+ cb++;
-+
-+ set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length,
-+ scratchbuf, scanline_size,
-+ scanline_size, scanlines_per_cb);
-+ control_block_pa += sizeof(struct bcm2708_dma_cb);
-+ cb->next = control_block_pa;
-+ cb++;
-+ }
-+ /* move the pointer back to the last dma control block */
-+ cb--;
-+ } else {
-+ /* A single dma control block is enough. */
-+ int sy, dy, stride;
-+ if (region->dy <= region->sy) {
-+ /* processing from top to bottom */
-+ dy = region->dy;
-+ sy = region->sy;
-+ stride = fb->fb.fix.line_length;
-+ } else {
-+ /* processing from bottom to top */
-+ dy = region->dy + region->height - 1;
-+ sy = region->sy + region->height - 1;
-+ stride = -fb->fb.fix.line_length;
-+ }
-+ set_dma_cb(cb, burst_size,
-+ fb->fb_bus_address + dy * fb->fb.fix.line_length +
-+ bytes_per_pixel * region->dx,
-+ stride,
-+ fb->fb_bus_address + sy * fb->fb.fix.line_length +
-+ bytes_per_pixel * region->sx,
-+ stride,
-+ region->width * bytes_per_pixel,
-+ region->height);
-+ }
-+
-+ /* end of dma control blocks chain */
-+ cb->next = 0;
-+
-+
-+ if (pixels < dma_busy_wait_threshold) {
-+ bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+ bcm_dma_wait_idle(fb->dma_chan_base);
-+ } else {
-+ void __iomem *dma_chan = fb->dma_chan_base;
-+ cb->info |= BCM2708_DMA_INT_EN;
-+ bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+ while (bcm_dma_is_busy(dma_chan)) {
-+ wait_event_interruptible(
-+ fb->dma_waitq,
-+ !bcm_dma_is_busy(dma_chan));
-+ }
-+ fb->stats.dma_irqs++;
-+ }
-+ fb->stats.dma_copies++;
-+}
-+
-+static void bcm2708_fb_imageblit(struct fb_info *info,
-+ const struct fb_image *image)
-+{
-+ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */
-+ cfb_imageblit(info, image);
-+}
-+
-+static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt)
-+{
-+ struct bcm2708_fb *fb = cxt;
-+
-+ /* FIXME: should read status register to check if this is
-+ * actually interrupting us or not, in case this interrupt
-+ * ever becomes shared amongst several DMA channels
-+ *
-+ * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ;
-+ */
-+
-+ /* acknowledge the interrupt */
-+ writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS);
-+
-+ wake_up(&fb->dma_waitq);
-+ return IRQ_HANDLED;
-+}
-+
-+static struct fb_ops bcm2708_fb_ops = {
-+ .owner = THIS_MODULE,
-+ .fb_check_var = bcm2708_fb_check_var,
-+ .fb_set_par = bcm2708_fb_set_par,
-+ .fb_setcolreg = bcm2708_fb_setcolreg,
-+ .fb_blank = bcm2708_fb_blank,
-+ .fb_fillrect = bcm2708_fb_fillrect,
-+ .fb_copyarea = bcm2708_fb_copyarea,
-+ .fb_imageblit = bcm2708_fb_imageblit,
-+ .fb_pan_display = bcm2708_fb_pan_display,
-+ .fb_ioctl = bcm2708_ioctl,
-+};
-+
-+static int bcm2708_fb_register(struct bcm2708_fb *fb)
-+{
-+ int ret;
-+ dma_addr_t dma;
-+ void *mem;
-+
-+ mem =
-+ dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), &dma,
-+ GFP_KERNEL);
-+
-+ if (NULL == mem) {
-+ pr_err(": unable to allocate fbinfo buffer\n");
-+ ret = -ENOMEM;
-+ } else {
-+ fb->info = (struct fbinfo_s *)mem;
-+ fb->dma = dma;
-+ }
-+ fb->fb.fbops = &bcm2708_fb_ops;
-+ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA;
-+ fb->fb.pseudo_palette = fb->cmap;
-+
-+ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id));
-+ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
-+ fb->fb.fix.type_aux = 0;
-+ fb->fb.fix.xpanstep = 1;
-+ fb->fb.fix.ypanstep = 1;
-+ fb->fb.fix.ywrapstep = 0;
-+ fb->fb.fix.accel = FB_ACCEL_NONE;
-+
-+ fb->fb.var.xres = fbwidth;
-+ fb->fb.var.yres = fbheight;
-+ fb->fb.var.xres_virtual = fbwidth;
-+ fb->fb.var.yres_virtual = fbheight;
-+ fb->fb.var.bits_per_pixel = fbdepth;
-+ fb->fb.var.vmode = FB_VMODE_NONINTERLACED;
-+ fb->fb.var.activate = FB_ACTIVATE_NOW;
-+ fb->fb.var.nonstd = 0;
-+ fb->fb.var.height = -1; /* height of picture in mm */
-+ fb->fb.var.width = -1; /* width of picture in mm */
-+ fb->fb.var.accel_flags = 0;
-+
-+ fb->fb.monspecs.hfmin = 0;
-+ fb->fb.monspecs.hfmax = 100000;
-+ fb->fb.monspecs.vfmin = 0;
-+ fb->fb.monspecs.vfmax = 400;
-+ fb->fb.monspecs.dclkmin = 1000000;
-+ fb->fb.monspecs.dclkmax = 100000000;
-+
-+ bcm2708_fb_set_bitfields(&fb->fb.var);
-+ init_waitqueue_head(&fb->dma_waitq);
-+
-+ /*
-+ * Allocate colourmap.
-+ */
-+
-+ fb_set_var(&fb->fb, &fb->fb.var);
-+ bcm2708_fb_set_par(&fb->fb);
-+
-+ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth,
-+ fbheight, fbdepth, fbswap);
-+
-+ ret = register_framebuffer(&fb->fb);
-+ print_debug("BCM2708FB: register framebuffer (%d)\n", ret);
-+ if (ret == 0)
-+ goto out;
-+
-+ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret);
-+out:
-+ return ret;
-+}
-+
-+static int bcm2708_fb_probe(struct platform_device *dev)
-+{
-+ struct bcm2708_fb *fb;
-+ int ret;
-+
-+ fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL);
-+ if (!fb) {
-+ dev_err(&dev->dev,
-+ "could not allocate new bcm2708_fb struct\n");
-+ ret = -ENOMEM;
-+ goto free_region;
-+ }
-+
-+ bcm2708_fb_debugfs_init(fb);
-+
-+ fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K,
-+ &fb->cb_handle, GFP_KERNEL);
-+ if (!fb->cb_base) {
-+ dev_err(&dev->dev, "cannot allocate DMA CBs\n");
-+ ret = -ENOMEM;
-+ goto free_fb;
-+ }
-+
-+ pr_info("BCM2708FB: allocated DMA memory %08x\n",
-+ fb->cb_handle);
-+
-+ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK,
-+ &fb->dma_chan_base, &fb->dma_irq);
-+ if (ret < 0) {
-+ dev_err(&dev->dev, "couldn't allocate a DMA channel\n");
-+ goto free_cb;
-+ }
-+ fb->dma_chan = ret;
-+
-+ ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq,
-+ 0, "bcm2708_fb dma", fb);
-+ if (ret) {
-+ pr_err("%s: failed to request DMA irq\n", __func__);
-+ goto free_dma_chan;
-+ }
-+
-+
-+ pr_info("BCM2708FB: allocated DMA channel %d @ %p\n",
-+ fb->dma_chan, fb->dma_chan_base);
-+
-+ fb->dev = dev;
-+
-+ ret = bcm2708_fb_register(fb);
-+ if (ret == 0) {
-+ platform_set_drvdata(dev, fb);
-+ goto out;
-+ }
-+
-+free_dma_chan:
-+ bcm_dma_chan_free(fb->dma_chan);
-+free_cb:
-+ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
-+free_fb:
-+ kfree(fb);
-+free_region:
-+ dev_err(&dev->dev, "probe failed, err %d\n", ret);
-+out:
-+ return ret;
-+}
-+
-+static int bcm2708_fb_remove(struct platform_device *dev)
-+{
-+ struct bcm2708_fb *fb = platform_get_drvdata(dev);
-+
-+ platform_set_drvdata(dev, NULL);
-+
-+ if (fb->fb.screen_base)
-+ iounmap(fb->fb.screen_base);
-+ unregister_framebuffer(&fb->fb);
-+
-+ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
-+ bcm_dma_chan_free(fb->dma_chan);
-+
-+ dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info,
-+ fb->dma);
-+ bcm2708_fb_debugfs_deinit(fb);
-+
-+ free_irq(fb->dma_irq, fb);
-+
-+ kfree(fb);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm2708_fb_driver = {
-+ .probe = bcm2708_fb_probe,
-+ .remove = bcm2708_fb_remove,
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init bcm2708_fb_init(void)
-+{
-+ return platform_driver_register(&bcm2708_fb_driver);
-+}
-+
-+module_init(bcm2708_fb_init);
-+
-+static void __exit bcm2708_fb_exit(void)
-+{
-+ platform_driver_unregister(&bcm2708_fb_driver);
-+}
-+
-+module_exit(bcm2708_fb_exit);
-+
-+module_param(fbwidth, int, 0644);
-+module_param(fbheight, int, 0644);
-+module_param(fbdepth, int, 0644);
-+module_param(fbswap, int, 0644);
-+
-+MODULE_DESCRIPTION("BCM2708 framebuffer driver");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer");
-+MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer");
-+MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer");
-+MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes");
-diff -Nur linux-3.18.14/drivers/video/fbdev/core/cfbimgblt.c linux-rpi/drivers/video/fbdev/core/cfbimgblt.c
---- linux-3.18.14/drivers/video/fbdev/core/cfbimgblt.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/video/fbdev/core/cfbimgblt.c 2015-05-31 14:46:13.001660960 -0500
-@@ -28,6 +28,11 @@
- *
- * Also need to add code to deal with cards endians that are different than
- * the native cpu endians. I also need to deal with MSB position in the word.
-+ * Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013:
-+ * - Provide optimized versions of fast_imageblit for 16 and 32bpp that are
-+ * significantly faster than the previous implementation.
-+ * - Simplify the fast/slow_imageblit selection code, avoiding integer
-+ * divides.
- */
- #include <linux/module.h>
- #include <linux/string.h>
-@@ -262,6 +267,133 @@
- }
- }
-
-+/*
-+ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded
-+ * into the code, main loop unrolled.
-+ */
-+
-+static inline void fast_imageblit16(const struct fb_image *image,
-+ struct fb_info *p, u8 __iomem * dst1,
-+ u32 fgcolor, u32 bgcolor)
-+{
-+ u32 fgx = fgcolor, bgx = bgcolor;
-+ u32 spitch = (image->width + 7) / 8;
-+ u32 end_mask, eorx;
-+ const char *s = image->data, *src;
-+ u32 __iomem *dst;
-+ const u32 *tab = NULL;
-+ int i, j, k;
-+
-+ tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;
-+
-+ fgx <<= 16;
-+ bgx <<= 16;
-+ fgx |= fgcolor;
-+ bgx |= bgcolor;
-+
-+ eorx = fgx ^ bgx;
-+ k = image->width / 2;
-+
-+ for (i = image->height; i--;) {
-+ dst = (u32 __iomem *) dst1;
-+ src = s;
-+
-+ j = k;
-+ while (j >= 4) {
-+ u8 bits = *src;
-+ end_mask = tab[(bits >> 6) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 4) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 2) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[bits & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ src++;
-+ j -= 4;
-+ }
-+ if (j != 0) {
-+ u8 bits = *src;
-+ end_mask = tab[(bits >> 6) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ if (j >= 2) {
-+ end_mask = tab[(bits >> 4) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ if (j == 3) {
-+ end_mask = tab[(bits >> 2) & 3];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst);
-+ }
-+ }
-+ }
-+ dst1 += p->fix.line_length;
-+ s += spitch;
-+ }
-+}
-+
-+/*
-+ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded
-+ * into the code, main loop unrolled.
-+ */
-+
-+static inline void fast_imageblit32(const struct fb_image *image,
-+ struct fb_info *p, u8 __iomem * dst1,
-+ u32 fgcolor, u32 bgcolor)
-+{
-+ u32 fgx = fgcolor, bgx = bgcolor;
-+ u32 spitch = (image->width + 7) / 8;
-+ u32 end_mask, eorx;
-+ const char *s = image->data, *src;
-+ u32 __iomem *dst;
-+ const u32 *tab = NULL;
-+ int i, j, k;
-+
-+ tab = cfb_tab32;
-+
-+ eorx = fgx ^ bgx;
-+ k = image->width;
-+
-+ for (i = image->height; i--;) {
-+ dst = (u32 __iomem *) dst1;
-+ src = s;
-+
-+ j = k;
-+ while (j >= 8) {
-+ u8 bits = *src;
-+ end_mask = tab[(bits >> 7) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 6) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 5) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 4) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 3) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 2) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[(bits >> 1) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ end_mask = tab[bits & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ src++;
-+ j -= 8;
-+ }
-+ if (j != 0) {
-+ u32 bits = (u32) * src;
-+ while (j > 1) {
-+ end_mask = tab[(bits >> 7) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+ bits <<= 1;
-+ j--;
-+ }
-+ end_mask = tab[(bits >> 7) & 1];
-+ FB_WRITEL((end_mask & eorx) ^ bgx, dst);
-+ }
-+ dst1 += p->fix.line_length;
-+ s += spitch;
-+ }
-+}
-+
- void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
- {
- u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
-@@ -294,11 +426,21 @@
- bgcolor = image->bg_color;
- }
-
-- if (32 % bpp == 0 && !start_index && !pitch_index &&
-- ((width & (32/bpp-1)) == 0) &&
-- bpp >= 8 && bpp <= 32)
-- fast_imageblit(image, p, dst1, fgcolor, bgcolor);
-- else
-+ if (!start_index && !pitch_index) {
-+ if (bpp == 32)
-+ fast_imageblit32(image, p, dst1, fgcolor,
-+ bgcolor);
-+ else if (bpp == 16 && (width & 1) == 0)
-+ fast_imageblit16(image, p, dst1, fgcolor,
-+ bgcolor);
-+ else if (bpp == 8 && (width & 3) == 0)
-+ fast_imageblit(image, p, dst1, fgcolor,
-+ bgcolor);
-+ else
-+ slow_imageblit(image, p, dst1, fgcolor,
-+ bgcolor,
-+ start_index, pitch_index);
-+ } else
- slow_imageblit(image, p, dst1, fgcolor, bgcolor,
- start_index, pitch_index);
- } else
-diff -Nur linux-3.18.14/drivers/video/fbdev/core/fbmem.c linux-rpi/drivers/video/fbdev/core/fbmem.c
---- linux-3.18.14/drivers/video/fbdev/core/fbmem.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/video/fbdev/core/fbmem.c 2015-05-31 14:46:13.005660960 -0500
-@@ -1084,6 +1084,25 @@
- }
- EXPORT_SYMBOL(fb_blank);
-
-+static int fb_copyarea_user(struct fb_info *info,
-+ struct fb_copyarea *copy)
-+{
-+ int ret = 0;
-+ if (!lock_fb_info(info))
-+ return -ENODEV;
-+ if (copy->dx + copy->width > info->var.xres ||
-+ copy->sx + copy->width > info->var.xres ||
-+ copy->dy + copy->height > info->var.yres ||
-+ copy->sy + copy->height > info->var.yres) {
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+ info->fbops->fb_copyarea(info, copy);
-+out:
-+ unlock_fb_info(info);
-+ return ret;
-+}
-+
- static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
- unsigned long arg)
- {
-@@ -1094,6 +1113,7 @@
- struct fb_cmap cmap_from;
- struct fb_cmap_user cmap;
- struct fb_event event;
-+ struct fb_copyarea copy;
- void __user *argp = (void __user *)arg;
- long ret = 0;
-
-@@ -1211,6 +1231,15 @@
- unlock_fb_info(info);
- console_unlock();
- break;
-+ case FBIOCOPYAREA:
-+ if (info->flags & FBINFO_HWACCEL_COPYAREA) {
-+ /* only provide this ioctl if it is accelerated */
-+ if (copy_from_user(&copy, argp, sizeof(copy)))
-+ return -EFAULT;
-+ ret = fb_copyarea_user(info, &copy);
-+ break;
-+ }
-+ /* fall through */
- default:
- if (!lock_fb_info(info))
- return -ENODEV;
-@@ -1365,6 +1394,7 @@
- case FBIOPAN_DISPLAY:
- case FBIOGET_CON2FBMAP:
- case FBIOPUT_CON2FBMAP:
-+ case FBIOCOPYAREA:
- arg = (unsigned long) compat_ptr(arg);
- case FBIOBLANK:
- ret = do_fb_ioctl(info, cmd, arg);
-diff -Nur linux-3.18.14/drivers/video/fbdev/Kconfig linux-rpi/drivers/video/fbdev/Kconfig
---- linux-3.18.14/drivers/video/fbdev/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/video/fbdev/Kconfig 2015-05-31 14:46:12.993660961 -0500
-@@ -224,6 +224,20 @@
- comment "Frame buffer hardware drivers"
- depends on FB
-
-+config FB_BCM2708
-+ tristate "BCM2708 framebuffer support"
-+ depends on FB && ARM
-+ select FB_CFB_FILLRECT
-+ select FB_CFB_COPYAREA
-+ select FB_CFB_IMAGEBLIT
-+ help
-+ This framebuffer device driver is for the BCM2708 framebuffer.
-+
-+ If you want to compile this as a module (=code which can be
-+ inserted into and removed from the running kernel), say M
-+ here and read <file:Documentation/kbuild/modules.txt>. The module
-+ will be called bcm2708_fb.
-+
- config FB_GRVGA
- tristate "Aeroflex Gaisler framebuffer support"
- depends on FB && SPARC
-diff -Nur linux-3.18.14/drivers/video/fbdev/Makefile linux-rpi/drivers/video/fbdev/Makefile
---- linux-3.18.14/drivers/video/fbdev/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/video/fbdev/Makefile 2015-05-31 14:46:12.993660961 -0500
-@@ -12,6 +12,7 @@
- obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o
-
- # Hardware specific drivers go first
-+obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o
- obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o
- obj-$(CONFIG_FB_ARC) += arcfb.o
- obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o
-diff -Nur linux-3.18.14/drivers/video/logo/logo_linux_clut224.ppm linux-rpi/drivers/video/logo/logo_linux_clut224.ppm
---- linux-3.18.14/drivers/video/logo/logo_linux_clut224.ppm 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/video/logo/logo_linux_clut224.ppm 2015-05-31 14:46:13.093660960 -0500
-@@ -1,1604 +1,883 @@
- P3
--# Standard 224-color Linux logo
--80 80
-+63 80
- 255
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 6 6 6 10 10 10 10 10 10
-- 10 10 10 6 6 6 6 6 6 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 10 10 10 14 14 14
-- 22 22 22 26 26 26 30 30 30 34 34 34
-- 30 30 30 30 30 30 26 26 26 18 18 18
-- 14 14 14 10 10 10 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 14 14 14 26 26 26 42 42 42
-- 54 54 54 66 66 66 78 78 78 78 78 78
-- 78 78 78 74 74 74 66 66 66 54 54 54
-- 42 42 42 26 26 26 18 18 18 10 10 10
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 22 22 22 42 42 42 66 66 66 86 86 86
-- 66 66 66 38 38 38 38 38 38 22 22 22
-- 26 26 26 34 34 34 54 54 54 66 66 66
-- 86 86 86 70 70 70 46 46 46 26 26 26
-- 14 14 14 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 10 10 10 26 26 26
-- 50 50 50 82 82 82 58 58 58 6 6 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 6 6 6 54 54 54 86 86 86 66 66 66
-- 38 38 38 18 18 18 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 22 22 22 50 50 50
-- 78 78 78 34 34 34 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 6 6 6 70 70 70
-- 78 78 78 46 46 46 22 22 22 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 18 18 18 42 42 42 82 82 82
-- 26 26 26 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 14 14 14
-- 46 46 46 34 34 34 6 6 6 2 2 6
-- 42 42 42 78 78 78 42 42 42 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 0 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 10 10 10 30 30 30 66 66 66 58 58 58
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 26 26 26
-- 86 86 86 101 101 101 46 46 46 10 10 10
-- 2 2 6 58 58 58 70 70 70 34 34 34
-- 10 10 10 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 14 14 14 42 42 42 86 86 86 10 10 10
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 30 30 30
-- 94 94 94 94 94 94 58 58 58 26 26 26
-- 2 2 6 6 6 6 78 78 78 54 54 54
-- 22 22 22 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 22 22 22 62 62 62 62 62 62 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 26 26 26
-- 54 54 54 38 38 38 18 18 18 10 10 10
-- 2 2 6 2 2 6 34 34 34 82 82 82
-- 38 38 38 14 14 14 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 30 30 30 78 78 78 30 30 30 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 10 10 10
-- 10 10 10 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 78 78 78
-- 50 50 50 18 18 18 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 38 38 38 86 86 86 14 14 14 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 54 54 54
-- 66 66 66 26 26 26 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 42 42 42 82 82 82 2 2 6 2 2 6
-- 2 2 6 6 6 6 10 10 10 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 6 6 6
-- 14 14 14 10 10 10 2 2 6 2 2 6
-- 2 2 6 2 2 6 2 2 6 18 18 18
-- 82 82 82 34 34 34 10 10 10 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 46 46 46 86 86 86 2 2 6 2 2 6
-- 6 6 6 6 6 6 22 22 22 34 34 34
-- 6 6 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 18 18 18 34 34 34
-- 10 10 10 50 50 50 22 22 22 2 2 6
-- 2 2 6 2 2 6 2 2 6 10 10 10
-- 86 86 86 42 42 42 14 14 14 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 1 0 0 1 0 0 1 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 46 46 46 86 86 86 2 2 6 2 2 6
-- 38 38 38 116 116 116 94 94 94 22 22 22
-- 22 22 22 2 2 6 2 2 6 2 2 6
-- 14 14 14 86 86 86 138 138 138 162 162 162
--154 154 154 38 38 38 26 26 26 6 6 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 86 86 86 46 46 46 14 14 14 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 46 46 46 86 86 86 2 2 6 14 14 14
--134 134 134 198 198 198 195 195 195 116 116 116
-- 10 10 10 2 2 6 2 2 6 6 6 6
--101 98 89 187 187 187 210 210 210 218 218 218
--214 214 214 134 134 134 14 14 14 6 6 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
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-- 46 46 46 82 82 82 2 2 6 106 106 106
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-- 42 42 42 86 86 86 6 6 6 116 116 116
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-- 38 38 38 90 90 90 14 14 14 58 58 58
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--238 238 238 198 198 198 6 6 6 38 38 38
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-- 2 2 6 2 2 6 2 2 6 46 46 46
-- 78 78 78 30 30 30 10 10 10 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 10 10 10 30 30 30
-- 74 74 74 58 58 58 2 2 6 42 42 42
-- 2 2 6 22 22 22 231 231 231 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 246 246 246 46 46 46 38 38 38
-- 42 42 42 14 14 14 38 38 38 14 14 14
-- 2 2 6 2 2 6 2 2 6 6 6 6
-- 86 86 86 46 46 46 14 14 14 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 14 14 14 42 42 42
-- 90 90 90 18 18 18 18 18 18 26 26 26
-- 2 2 6 116 116 116 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 250 250 250 238 238 238
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 94 94 94 6 6 6
-- 2 2 6 2 2 6 10 10 10 34 34 34
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 74 74 74 58 58 58 22 22 22 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 10 10 10 26 26 26 66 66 66
-- 82 82 82 2 2 6 38 38 38 6 6 6
-- 14 14 14 210 210 210 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 246 246 246 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 144 144 144 2 2 6
-- 2 2 6 2 2 6 2 2 6 46 46 46
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 42 42 42 74 74 74 30 30 30 10 10 10
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 14 14 14 42 42 42 90 90 90
-- 26 26 26 6 6 6 42 42 42 2 2 6
-- 74 74 74 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 242 242 242 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 182 182 182 2 2 6
-- 2 2 6 2 2 6 2 2 6 46 46 46
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 10 10 10 86 86 86 38 38 38 10 10 10
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 10 10 10 26 26 26 66 66 66 82 82 82
-- 2 2 6 22 22 22 18 18 18 2 2 6
--149 149 149 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 206 206 206 2 2 6
-- 2 2 6 2 2 6 2 2 6 38 38 38
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 6 6 6 86 86 86 46 46 46 14 14 14
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 18 18 18 46 46 46 86 86 86 18 18 18
-- 2 2 6 34 34 34 10 10 10 6 6 6
--210 210 210 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 221 221 221 6 6 6
-- 2 2 6 2 2 6 6 6 6 30 30 30
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 82 82 82 54 54 54 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 26 26 26 66 66 66 62 62 62 2 2 6
-- 2 2 6 38 38 38 10 10 10 26 26 26
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 238 238 238
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 6 6 6
-- 2 2 6 2 2 6 10 10 10 30 30 30
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 58 58 58 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 38 38 38 78 78 78 6 6 6 2 2 6
-- 2 2 6 46 46 46 14 14 14 42 42 42
--246 246 246 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 10 10 10
-- 2 2 6 2 2 6 22 22 22 14 14 14
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 62 62 62 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 18 18 18
-- 50 50 50 74 74 74 2 2 6 2 2 6
-- 14 14 14 70 70 70 34 34 34 62 62 62
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 14 14 14
-- 2 2 6 2 2 6 30 30 30 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 62 62 62 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 18 18 18
-- 54 54 54 62 62 62 2 2 6 2 2 6
-- 2 2 6 30 30 30 46 46 46 70 70 70
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 226 226 226 10 10 10
-- 2 2 6 6 6 6 30 30 30 2 2 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 66 66 66 58 58 58 22 22 22
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 22 22 22
-- 58 58 58 62 62 62 2 2 6 2 2 6
-- 2 2 6 2 2 6 30 30 30 78 78 78
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 206 206 206 2 2 6
-- 22 22 22 34 34 34 18 14 6 22 22 22
-- 26 26 26 18 18 18 6 6 6 2 2 6
-- 2 2 6 82 82 82 54 54 54 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 26 26 26
-- 62 62 62 106 106 106 74 54 14 185 133 11
--210 162 10 121 92 8 6 6 6 62 62 62
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 158 158 158 18 18 18
-- 14 14 14 2 2 6 2 2 6 2 2 6
-- 6 6 6 18 18 18 66 66 66 38 38 38
-- 6 6 6 94 94 94 50 50 50 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 10 10 10 10 10 10 18 18 18 38 38 38
-- 78 78 78 142 134 106 216 158 10 242 186 14
--246 190 14 246 190 14 156 118 10 10 10 10
-- 90 90 90 238 238 238 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 230 190
--238 204 91 238 204 91 181 142 44 37 26 9
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 38 38 38 46 46 46
-- 26 26 26 106 106 106 54 54 54 18 18 18
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 6 6 6 14 14 14 22 22 22
-- 30 30 30 38 38 38 50 50 50 70 70 70
--106 106 106 190 142 34 226 170 11 242 186 14
--246 190 14 246 190 14 246 190 14 154 114 10
-- 6 6 6 74 74 74 226 226 226 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 228 184 62
--241 196 14 241 208 19 232 195 16 38 30 10
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 6 6 6 30 30 30 26 26 26
--203 166 17 154 142 90 66 66 66 26 26 26
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 6 6 6 18 18 18 38 38 38 58 58 58
-- 78 78 78 86 86 86 101 101 101 123 123 123
--175 146 61 210 150 10 234 174 13 246 186 14
--246 190 14 246 190 14 246 190 14 238 190 10
--102 78 10 2 2 6 46 46 46 198 198 198
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 224 178 62
--242 186 14 241 196 14 210 166 10 22 18 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 6 6 6 121 92 8
--238 202 15 232 195 16 82 82 82 34 34 34
-- 10 10 10 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 14 14 14 38 38 38 70 70 70 154 122 46
--190 142 34 200 144 11 197 138 11 197 138 11
--213 154 11 226 170 11 242 186 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--225 175 15 46 32 6 2 2 6 22 22 22
--158 158 158 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 242 242 242 224 178 62
--239 182 13 236 186 11 213 154 11 46 32 6
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 61 42 6 225 175 15
--238 190 10 236 186 11 112 100 78 42 42 42
-- 14 14 14 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 22 22 22 54 54 54 154 122 46 213 154 11
--226 170 11 230 174 11 226 170 11 226 170 11
--236 178 12 242 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--241 196 14 184 144 12 10 10 10 2 2 6
-- 6 6 6 116 116 116 242 242 242 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 231 231 231 198 198 198 214 170 54
--236 178 12 236 178 12 210 150 10 137 92 6
-- 18 14 6 2 2 6 2 2 6 2 2 6
-- 6 6 6 70 47 6 200 144 11 236 178 12
--239 182 13 239 182 13 124 112 88 58 58 58
-- 22 22 22 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 30 30 30 70 70 70 180 133 36 226 170 11
--239 182 13 242 186 14 242 186 14 246 186 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 232 195 16 98 70 6 2 2 6
-- 2 2 6 2 2 6 66 66 66 221 221 221
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 206 206 206 198 198 198 214 166 58
--230 174 11 230 174 11 216 158 10 192 133 9
--163 110 8 116 81 8 102 78 10 116 81 8
--167 114 7 197 138 11 226 170 11 239 182 13
--242 186 14 242 186 14 162 146 94 78 78 78
-- 34 34 34 14 14 14 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 30 30 30 78 78 78 190 142 34 226 170 11
--239 182 13 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 241 196 14 203 166 17 22 18 6
-- 2 2 6 2 2 6 2 2 6 38 38 38
--218 218 218 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 206 206 206 198 198 198 202 162 69
--226 170 11 236 178 12 224 166 10 210 150 10
--200 144 11 197 138 11 192 133 9 197 138 11
--210 150 10 226 170 11 242 186 14 246 190 14
--246 190 14 246 186 14 225 175 15 124 112 88
-- 62 62 62 30 30 30 14 14 14 6 6 6
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 30 30 30 78 78 78 174 135 50 224 166 10
--239 182 13 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 241 196 14 139 102 15
-- 2 2 6 2 2 6 2 2 6 2 2 6
-- 78 78 78 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 214 214 214 198 198 198 190 150 46
--219 162 10 236 178 12 234 174 13 224 166 10
--216 158 10 213 154 11 213 154 11 216 158 10
--226 170 11 239 182 13 246 190 14 246 190 14
--246 190 14 246 190 14 242 186 14 206 162 42
--101 101 101 58 58 58 30 30 30 14 14 14
-- 6 6 6 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 30 30 30 74 74 74 174 135 50 216 158 10
--236 178 12 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 241 196 14 226 184 13
-- 61 42 6 2 2 6 2 2 6 2 2 6
-- 22 22 22 238 238 238 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 226 226 226 187 187 187 180 133 36
--216 158 10 236 178 12 239 182 13 236 178 12
--230 174 11 226 170 11 226 170 11 230 174 11
--236 178 12 242 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 186 14 239 182 13
--206 162 42 106 106 106 66 66 66 34 34 34
-- 14 14 14 6 6 6 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 26 26 26 70 70 70 163 133 67 213 154 11
--236 178 12 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 241 196 14
--190 146 13 18 14 6 2 2 6 2 2 6
-- 46 46 46 246 246 246 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 221 221 221 86 86 86 156 107 11
--216 158 10 236 178 12 242 186 14 246 186 14
--242 186 14 239 182 13 239 182 13 242 186 14
--242 186 14 246 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--242 186 14 225 175 15 142 122 72 66 66 66
-- 30 30 30 10 10 10 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 6 6 6
-- 26 26 26 70 70 70 163 133 67 210 150 10
--236 178 12 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--232 195 16 121 92 8 34 34 34 106 106 106
--221 221 221 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--242 242 242 82 82 82 18 14 6 163 110 8
--216 158 10 236 178 12 242 186 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 242 186 14 163 133 67
-- 46 46 46 18 18 18 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 10 10 10
-- 30 30 30 78 78 78 163 133 67 210 150 10
--236 178 12 246 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--241 196 14 215 174 15 190 178 144 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 218 218 218
-- 58 58 58 2 2 6 22 18 6 167 114 7
--216 158 10 236 178 12 246 186 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 186 14 242 186 14 190 150 46
-- 54 54 54 22 22 22 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 14 14 14
-- 38 38 38 86 86 86 180 133 36 213 154 11
--236 178 12 246 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 232 195 16 190 146 13 214 214 214
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 170 170 170 26 26 26
-- 2 2 6 2 2 6 37 26 9 163 110 8
--219 162 10 239 182 13 246 186 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 186 14 236 178 12 224 166 10 142 122 72
-- 46 46 46 18 18 18 6 6 6 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 18 18 18
-- 50 50 50 109 106 95 192 133 9 224 166 10
--242 186 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--242 186 14 226 184 13 210 162 10 142 110 46
--226 226 226 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--198 198 198 66 66 66 2 2 6 2 2 6
-- 2 2 6 2 2 6 50 34 6 156 107 11
--219 162 10 239 182 13 246 186 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 242 186 14
--234 174 13 213 154 11 154 122 46 66 66 66
-- 30 30 30 10 10 10 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 0 0 0 0 0 0
-- 0 0 0 0 0 0 6 6 6 22 22 22
-- 58 58 58 154 121 60 206 145 10 234 174 13
--242 186 14 246 186 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 186 14 236 178 12 210 162 10 163 110 8
-- 61 42 6 138 138 138 218 218 218 250 250 250
--253 253 253 253 253 253 253 253 253 250 250 250
--242 242 242 210 210 210 144 144 144 66 66 66
-- 6 6 6 2 2 6 2 2 6 2 2 6
-- 2 2 6 2 2 6 61 42 6 163 110 8
--216 158 10 236 178 12 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 246 190 14 246 190 14 246 190 14
--246 190 14 239 182 13 230 174 11 216 158 10
--190 142 34 124 112 88 70 70 70 38 38 38
-- 18 18 18 6 6 6 0 0 0 0 0 0
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-diff -Nur linux-3.18.14/drivers/w1/masters/w1-gpio.c linux-rpi/drivers/w1/masters/w1-gpio.c
---- linux-3.18.14/drivers/w1/masters/w1-gpio.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/w1/masters/w1-gpio.c 2015-05-31 14:46:13.101660959 -0500
-@@ -23,6 +23,19 @@
- #include "../w1.h"
- #include "../w1_int.h"
-
-+static int w1_gpio_pullup = 0;
-+static int w1_gpio_pullup_orig = 0;
-+module_param_named(pullup, w1_gpio_pullup, int, 0);
-+MODULE_PARM_DESC(pullup, "Enable parasitic power (power on data) mode");
-+static int w1_gpio_pullup_pin = -1;
-+static int w1_gpio_pullup_pin_orig = -1;
-+module_param_named(extpullup, w1_gpio_pullup_pin, int, 0);
-+MODULE_PARM_DESC(extpullup, "GPIO external pullup pin number");
-+static int w1_gpio_pin = -1;
-+static int w1_gpio_pin_orig = -1;
-+module_param_named(gpiopin, w1_gpio_pin, int, 0);
-+MODULE_PARM_DESC(gpiopin, "GPIO pin number");
-+
- static u8 w1_gpio_set_pullup(void *data, int delay)
- {
- struct w1_gpio_platform_data *pdata = data;
-@@ -67,6 +80,16 @@
- return gpio_get_value(pdata->pin) ? 1 : 0;
- }
-
-+static void w1_gpio_bitbang_pullup(void *data, u8 on)
-+{
-+ struct w1_gpio_platform_data *pdata = data;
-+
-+ if (on)
-+ gpio_direction_output(pdata->pin, 1);
-+ else
-+ gpio_direction_input(pdata->pin);
-+}
-+
- #if defined(CONFIG_OF)
- static struct of_device_id w1_gpio_dt_ids[] = {
- { .compatible = "w1-gpio" },
-@@ -80,6 +103,7 @@
- struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct device_node *np = pdev->dev.of_node;
- int gpio;
-+ u32 value;
-
- pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
- if (!pdata)
-@@ -88,6 +112,9 @@
- if (of_get_property(np, "linux,open-drain", NULL))
- pdata->is_open_drain = 1;
-
-+ if (of_property_read_u32(np, "rpi,parasitic-power", &value) == 0)
-+ pdata->parasitic_power = (value != 0);
-+
- gpio = of_get_gpio(np, 0);
- if (gpio < 0) {
- if (gpio != -EPROBE_DEFER)
-@@ -103,7 +130,7 @@
- if (gpio == -EPROBE_DEFER)
- return gpio;
- /* ignore other errors as the pullup gpio is optional */
-- pdata->ext_pullup_enable_pin = gpio;
-+ pdata->ext_pullup_enable_pin = (gpio >= 0) ? gpio : -1;
-
- pdev->dev.platform_data = pdata;
-
-@@ -113,13 +140,15 @@
- static int w1_gpio_probe(struct platform_device *pdev)
- {
- struct w1_bus_master *master;
-- struct w1_gpio_platform_data *pdata;
-+ struct w1_gpio_platform_data *pdata = pdev->dev.platform_data;
- int err;
-
-- if (of_have_populated_dt()) {
-- err = w1_gpio_probe_dt(pdev);
-- if (err < 0)
-- return err;
-+ if(pdata == NULL) {
-+ if (of_have_populated_dt()) {
-+ err = w1_gpio_probe_dt(pdev);
-+ if (err < 0)
-+ return err;
-+ }
- }
-
- pdata = dev_get_platdata(&pdev->dev);
-@@ -136,6 +165,22 @@
- return -ENOMEM;
- }
-
-+ w1_gpio_pin_orig = pdata->pin;
-+ w1_gpio_pullup_pin_orig = pdata->ext_pullup_enable_pin;
-+ w1_gpio_pullup_orig = pdata->parasitic_power;
-+
-+ if(gpio_is_valid(w1_gpio_pin)) {
-+ pdata->pin = w1_gpio_pin;
-+ pdata->ext_pullup_enable_pin = -1;
-+ pdata->parasitic_power = -1;
-+ }
-+ pdata->parasitic_power |= w1_gpio_pullup;
-+ if(gpio_is_valid(w1_gpio_pullup_pin)) {
-+ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin;
-+ }
-+
-+ dev_info(&pdev->dev, "gpio pin %d, external pullup pin %d, parasitic power %d\n", pdata->pin, pdata->ext_pullup_enable_pin, pdata->parasitic_power);
-+
- err = devm_gpio_request(&pdev->dev, pdata->pin, "w1");
- if (err) {
- dev_err(&pdev->dev, "gpio_request (pin) failed\n");
-@@ -165,6 +210,14 @@
- master->set_pullup = w1_gpio_set_pullup;
- }
-
-+ if (pdata->parasitic_power) {
-+ if (pdata->is_open_drain)
-+ printk(KERN_ERR "w1-gpio 'pullup'(parasitic power) "
-+ "option doesn't work with open drain GPIO\n");
-+ else
-+ master->bitbang_pullup = w1_gpio_bitbang_pullup;
-+ }
-+
- err = w1_add_master_device(master);
- if (err) {
- dev_err(&pdev->dev, "w1_add_master device failed\n");
-@@ -195,6 +248,10 @@
-
- w1_remove_master_device(master);
-
-+ pdata->pin = w1_gpio_pin_orig;
-+ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin_orig;
-+ pdata->parasitic_power = w1_gpio_pullup_orig;
-+
- return 0;
- }
-
-diff -Nur linux-3.18.14/drivers/w1/w1.h linux-rpi/drivers/w1/w1.h
---- linux-3.18.14/drivers/w1/w1.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/w1/w1.h 2015-05-31 14:46:13.101660959 -0500
-@@ -171,6 +171,12 @@
-
- u8 (*set_pullup)(void *, int);
-
-+ /**
-+ * Turns the pullup on/off in bitbanging mode, takes an on/off argument.
-+ * @return -1=Error, 0=completed
-+ */
-+ void (*bitbang_pullup) (void *, u8);
-+
- void (*search)(void *, struct w1_master *,
- u8, w1_slave_found_callback);
- };
-diff -Nur linux-3.18.14/drivers/w1/w1_int.c linux-rpi/drivers/w1/w1_int.c
---- linux-3.18.14/drivers/w1/w1_int.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/w1/w1_int.c 2015-05-31 14:46:13.105660959 -0500
-@@ -123,6 +123,20 @@
- return(-EINVAL);
- }
-
-+ /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup
-+ * and takes care of timing itself */
-+ if (!master->write_byte && !master->touch_bit && master->set_pullup) {
-+ printk(KERN_ERR "w1_add_master_device: set_pullup requires "
-+ "write_byte or touch_bit, disabling\n");
-+ master->set_pullup = NULL;
-+ }
-+
-+ if (master->set_pullup && master->bitbang_pullup) {
-+ printk(KERN_ERR "w1_add_master_device: set_pullup should not "
-+ "be set when bitbang_pullup is used, disabling\n");
-+ master->set_pullup = NULL;
-+ }
-+
- /* Lock until the device is added (or not) to w1_masters. */
- mutex_lock(&w1_mlock);
- /* Search for the first available id (starting at 1). */
-diff -Nur linux-3.18.14/drivers/w1/w1_io.c linux-rpi/drivers/w1/w1_io.c
---- linux-3.18.14/drivers/w1/w1_io.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/w1/w1_io.c 2015-05-31 14:46:13.105660959 -0500
-@@ -134,10 +134,22 @@
- static void w1_post_write(struct w1_master *dev)
- {
- if (dev->pullup_duration) {
-- if (dev->enable_pullup && dev->bus_master->set_pullup)
-- dev->bus_master->set_pullup(dev->bus_master->data, 0);
-- else
-+ if (dev->enable_pullup) {
-+ if (dev->bus_master->set_pullup) {
-+ dev->bus_master->set_pullup(dev->
-+ bus_master->data,
-+ 0);
-+ } else if (dev->bus_master->bitbang_pullup) {
-+ dev->bus_master->
-+ bitbang_pullup(dev->bus_master->data, 1);
- msleep(dev->pullup_duration);
-+ dev->bus_master->
-+ bitbang_pullup(dev->bus_master->data, 0);
-+ }
-+ } else {
-+ msleep(dev->pullup_duration);
-+ }
-+
- dev->pullup_duration = 0;
- }
- }
-diff -Nur linux-3.18.14/drivers/watchdog/bcm2708_wdog.c linux-rpi/drivers/watchdog/bcm2708_wdog.c
---- linux-3.18.14/drivers/watchdog/bcm2708_wdog.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/drivers/watchdog/bcm2708_wdog.c 2015-05-31 14:46:13.105660959 -0500
-@@ -0,0 +1,382 @@
-+/*
-+ * Broadcom BCM2708 watchdog driver.
-+ *
-+ * (c) Copyright 2010 Broadcom Europe Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ *
-+ * BCM2708 watchdog driver. Loosely based on wdt driver.
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/miscdevice.h>
-+#include <linux/watchdog.h>
-+#include <linux/fs.h>
-+#include <linux/ioport.h>
-+#include <linux/notifier.h>
-+#include <linux/reboot.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <mach/platform.h>
-+
-+#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
-+#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
-+
-+static unsigned long wdog_is_open;
-+static uint32_t wdog_ticks; /* Ticks to load into wdog timer */
-+static char expect_close;
-+
-+/*
-+ * Module parameters
-+ */
-+
-+#define WD_TIMO 10 /* Default heartbeat = 60 seconds */
-+static int heartbeat = WD_TIMO; /* Heartbeat in seconds */
-+
-+module_param(heartbeat, int, 0);
-+MODULE_PARM_DESC(heartbeat,
-+ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default="
-+ __MODULE_STRING(WD_TIMO) ")");
-+
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout,
-+ "Watchdog cannot be stopped once started (default="
-+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-+
-+static DEFINE_SPINLOCK(wdog_lock);
-+
-+/**
-+ * Start the watchdog driver.
-+ */
-+
-+static int wdog_start(unsigned long timeout)
-+{
-+ uint32_t cur;
-+ unsigned long flags;
-+ spin_lock_irqsave(&wdog_lock, flags);
-+
-+ /* enable the watchdog */
-+ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET),
-+ __io_address(PM_WDOG));
-+ cur = ioread32(__io_address(PM_RSTC));
-+ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) |
-+ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC));
-+
-+ spin_unlock_irqrestore(&wdog_lock, flags);
-+ return 0;
-+}
-+
-+/**
-+ * Stop the watchdog driver.
-+ */
-+
-+static int wdog_stop(void)
-+{
-+ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC));
-+ printk(KERN_INFO "watchdog stopped\n");
-+ return 0;
-+}
-+
-+/**
-+ * Reload counter one with the watchdog heartbeat. We don't bother
-+ * reloading the cascade counter.
-+ */
-+
-+static void wdog_ping(void)
-+{
-+ wdog_start(wdog_ticks);
-+}
-+
-+/**
-+ * @t: the new heartbeat value that needs to be set.
-+ *
-+ * Set a new heartbeat value for the watchdog device. If the heartbeat
-+ * value is incorrect we keep the old value and return -EINVAL. If
-+ * successful we return 0.
-+ */
-+
-+static int wdog_set_heartbeat(int t)
-+{
-+ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET))
-+ return -EINVAL;
-+
-+ heartbeat = t;
-+ wdog_ticks = SECS_TO_WDOG_TICKS(t);
-+ return 0;
-+}
-+
-+/**
-+ * @file: file handle to the watchdog
-+ * @buf: buffer to write (unused as data does not matter here
-+ * @count: count of bytes
-+ * @ppos: pointer to the position to write. No seeks allowed
-+ *
-+ * A write to a watchdog device is defined as a keepalive signal.
-+ *
-+ * if 'nowayout' is set then normally a close() is ignored. But
-+ * if you write 'V' first then the close() will stop the timer.
-+ */
-+
-+static ssize_t wdog_write(struct file *file, const char __user *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ if (count) {
-+ if (!nowayout) {
-+ size_t i;
-+
-+ /* In case it was set long ago */
-+ expect_close = 0;
-+
-+ for (i = 0; i != count; i++) {
-+ char c;
-+ if (get_user(c, buf + i))
-+ return -EFAULT;
-+ if (c == 'V')
-+ expect_close = 42;
-+ }
-+ }
-+ wdog_ping();
-+ }
-+ return count;
-+}
-+
-+static int wdog_get_status(void)
-+{
-+ unsigned long flags;
-+ int status = 0;
-+ spin_lock_irqsave(&wdog_lock, flags);
-+ /* FIXME: readback reset reason */
-+ spin_unlock_irqrestore(&wdog_lock, flags);
-+ return status;
-+}
-+
-+static uint32_t wdog_get_remaining(void)
-+{
-+ uint32_t ret = ioread32(__io_address(PM_WDOG));
-+ return ret & PM_WDOG_TIME_SET;
-+}
-+
-+/**
-+ * @file: file handle to the device
-+ * @cmd: watchdog command
-+ * @arg: argument pointer
-+ *
-+ * The watchdog API defines a common set of functions for all watchdogs
-+ * according to their available features. We only actually usefully support
-+ * querying capabilities and current status.
-+ */
-+
-+static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+ void __user *argp = (void __user *)arg;
-+ int __user *p = argp;
-+ int new_heartbeat;
-+ int status;
-+ int options;
-+ uint32_t remaining;
-+
-+ struct watchdog_info ident = {
-+ .options = WDIOF_SETTIMEOUT|
-+ WDIOF_MAGICCLOSE|
-+ WDIOF_KEEPALIVEPING,
-+ .firmware_version = 1,
-+ .identity = "BCM2708",
-+ };
-+
-+ switch (cmd) {
-+ case WDIOC_GETSUPPORT:
-+ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
-+ case WDIOC_GETSTATUS:
-+ status = wdog_get_status();
-+ return put_user(status, p);
-+ case WDIOC_GETBOOTSTATUS:
-+ return put_user(0, p);
-+ case WDIOC_KEEPALIVE:
-+ wdog_ping();
-+ return 0;
-+ case WDIOC_SETTIMEOUT:
-+ if (get_user(new_heartbeat, p))
-+ return -EFAULT;
-+ if (wdog_set_heartbeat(new_heartbeat))
-+ return -EINVAL;
-+ wdog_ping();
-+ /* Fall */
-+ case WDIOC_GETTIMEOUT:
-+ return put_user(heartbeat, p);
-+ case WDIOC_GETTIMELEFT:
-+ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining());
-+ return put_user(remaining, p);
-+ case WDIOC_SETOPTIONS:
-+ if (get_user(options, p))
-+ return -EFAULT;
-+ if (options & WDIOS_DISABLECARD)
-+ wdog_stop();
-+ if (options & WDIOS_ENABLECARD)
-+ wdog_start(wdog_ticks);
-+ return 0;
-+ default:
-+ return -ENOTTY;
-+ }
-+}
-+
-+/**
-+ * @inode: inode of device
-+ * @file: file handle to device
-+ *
-+ * The watchdog device has been opened. The watchdog device is single
-+ * open and on opening we load the counters.
-+ */
-+
-+static int wdog_open(struct inode *inode, struct file *file)
-+{
-+ if (test_and_set_bit(0, &wdog_is_open))
-+ return -EBUSY;
-+ /*
-+ * Activate
-+ */
-+ wdog_start(wdog_ticks);
-+ return nonseekable_open(inode, file);
-+}
-+
-+/**
-+ * @inode: inode to board
-+ * @file: file handle to board
-+ *
-+ * The watchdog has a configurable API. There is a religious dispute
-+ * between people who want their watchdog to be able to shut down and
-+ * those who want to be sure if the watchdog manager dies the machine
-+ * reboots. In the former case we disable the counters, in the latter
-+ * case you have to open it again very soon.
-+ */
-+
-+static int wdog_release(struct inode *inode, struct file *file)
-+{
-+ if (expect_close == 42) {
-+ wdog_stop();
-+ } else {
-+ printk(KERN_CRIT
-+ "wdt: WDT device closed unexpectedly. WDT will not stop!\n");
-+ wdog_ping();
-+ }
-+ clear_bit(0, &wdog_is_open);
-+ expect_close = 0;
-+ return 0;
-+}
-+
-+/**
-+ * @this: our notifier block
-+ * @code: the event being reported
-+ * @unused: unused
-+ *
-+ * Our notifier is called on system shutdowns. Turn the watchdog
-+ * off so that it does not fire during the next reboot.
-+ */
-+
-+static int wdog_notify_sys(struct notifier_block *this, unsigned long code,
-+ void *unused)
-+{
-+ if (code == SYS_DOWN || code == SYS_HALT)
-+ wdog_stop();
-+ return NOTIFY_DONE;
-+}
-+
-+/*
-+ * Kernel Interfaces
-+ */
-+
-+
-+static const struct file_operations wdog_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .write = wdog_write,
-+ .unlocked_ioctl = wdog_ioctl,
-+ .open = wdog_open,
-+ .release = wdog_release,
-+};
-+
-+static struct miscdevice wdog_miscdev = {
-+ .minor = WATCHDOG_MINOR,
-+ .name = "watchdog",
-+ .fops = &wdog_fops,
-+};
-+
-+/*
-+ * The WDT card needs to learn about soft shutdowns in order to
-+ * turn the timebomb registers off.
-+ */
-+
-+static struct notifier_block wdog_notifier = {
-+ .notifier_call = wdog_notify_sys,
-+};
-+
-+/**
-+ * cleanup_module:
-+ *
-+ * Unload the watchdog. You cannot do this with any file handles open.
-+ * If your watchdog is set to continue ticking on close and you unload
-+ * it, well it keeps ticking. We won't get the interrupt but the board
-+ * will not touch PC memory so all is fine. You just have to load a new
-+ * module in 60 seconds or reboot.
-+ */
-+
-+static void __exit wdog_exit(void)
-+{
-+ misc_deregister(&wdog_miscdev);
-+ unregister_reboot_notifier(&wdog_notifier);
-+}
-+
-+static int __init wdog_init(void)
-+{
-+ int ret;
-+
-+ /* Check that the heartbeat value is within it's range;
-+ if not reset to the default */
-+ if (wdog_set_heartbeat(heartbeat)) {
-+ wdog_set_heartbeat(WD_TIMO);
-+ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be "
-+ "0 < heartbeat < %d, using %d\n",
-+ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET),
-+ WD_TIMO);
-+ }
-+
-+ ret = register_reboot_notifier(&wdog_notifier);
-+ if (ret) {
-+ printk(KERN_ERR
-+ "wdt: cannot register reboot notifier (err=%d)\n", ret);
-+ goto out_reboot;
-+ }
-+
-+ ret = misc_register(&wdog_miscdev);
-+ if (ret) {
-+ printk(KERN_ERR
-+ "wdt: cannot register miscdev on minor=%d (err=%d)\n",
-+ WATCHDOG_MINOR, ret);
-+ goto out_misc;
-+ }
-+
-+ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n",
-+ heartbeat, nowayout);
-+ return 0;
-+
-+out_misc:
-+ unregister_reboot_notifier(&wdog_notifier);
-+out_reboot:
-+ return ret;
-+}
-+
-+module_init(wdog_init);
-+module_exit(wdog_exit);
-+
-+MODULE_AUTHOR("Luke Diamand");
-+MODULE_DESCRIPTION("Driver for BCM2708 watchdog");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS_MISCDEV(TEMP_MINOR);
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/drivers/watchdog/Kconfig linux-rpi/drivers/watchdog/Kconfig
---- linux-3.18.14/drivers/watchdog/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/watchdog/Kconfig 2015-05-31 14:46:13.105660959 -0500
-@@ -452,6 +452,12 @@
- To compile this driver as a module, choose M here: the
- module will be called retu_wdt.
-
-+config BCM2708_WDT
-+ tristate "BCM2708 Watchdog"
-+ depends on ARCH_BCM2708 || ARCH_BCM2709
-+ help
-+ Enables BCM2708 watchdog support.
-+
- config MOXART_WDT
- tristate "MOXART watchdog"
- depends on ARCH_MOXART
-diff -Nur linux-3.18.14/drivers/watchdog/Makefile linux-rpi/drivers/watchdog/Makefile
---- linux-3.18.14/drivers/watchdog/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/drivers/watchdog/Makefile 2015-05-31 14:46:13.105660959 -0500
-@@ -56,6 +56,7 @@
- obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
- obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
- obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
-+obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o
- obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
- obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
- obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
-diff -Nur linux-3.18.14/include/linux/broadcom/vc_cma.h linux-rpi/include/linux/broadcom/vc_cma.h
---- linux-3.18.14/include/linux/broadcom/vc_cma.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/include/linux/broadcom/vc_cma.h 2015-05-31 14:46:13.529660956 -0500
-@@ -0,0 +1,29 @@
-+/*****************************************************************************
-+* Copyright 2012 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#if !defined( VC_CMA_H )
-+#define VC_CMA_H
-+
-+#include <linux/ioctl.h>
-+
-+#define VC_CMA_IOC_MAGIC 0xc5
-+
-+#define VC_CMA_IOC_RESERVE _IO(VC_CMA_IOC_MAGIC, 0)
-+
-+#ifdef __KERNEL__
-+extern void __init vc_cma_early_init(void);
-+extern void __init vc_cma_reserve(void);
-+#endif
-+
-+#endif /* VC_CMA_H */
-diff -Nur linux-3.18.14/include/linux/mmc/host.h linux-rpi/include/linux/mmc/host.h
---- linux-3.18.14/include/linux/mmc/host.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/include/linux/mmc/host.h 2015-05-31 14:46:13.613660955 -0500
-@@ -146,7 +146,9 @@
- * I/O. Returns the number of supported blocks for the request.
- */
- int (*multi_io_quirk)(struct mmc_card *card,
-- unsigned int direction, int blk_size);
-+ unsigned int direction,
-+ u32 blk_pos,
-+ int blk_size);
- };
-
- struct mmc_card;
-@@ -290,6 +292,7 @@
- #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
- MMC_CAP2_HS400_1_2V)
- #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
-+#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
-
- mmc_pm_flag_t pm_caps; /* supported pm features */
-
-diff -Nur linux-3.18.14/include/linux/mmc/sdhci.h linux-rpi/include/linux/mmc/sdhci.h
---- linux-3.18.14/include/linux/mmc/sdhci.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/include/linux/mmc/sdhci.h 2015-05-31 14:46:13.613660955 -0500
-@@ -130,6 +130,7 @@
- #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
- #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
- #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
-+#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
-
- unsigned int version; /* SDHCI spec. version */
-
-diff -Nur linux-3.18.14/include/linux/platform_data/bcm2708.h linux-rpi/include/linux/platform_data/bcm2708.h
---- linux-3.18.14/include/linux/platform_data/bcm2708.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/include/linux/platform_data/bcm2708.h 2015-05-31 14:46:13.633660955 -0500
-@@ -0,0 +1,23 @@
-+/*
-+ * include/linux/platform_data/bcm2708.h
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * (C) 2014 Julian Scheel <julian@jusst.de>
-+ *
-+ */
-+#ifndef __BCM2708_H_
-+#define __BCM2708_H_
-+
-+typedef enum {
-+ BCM2708_PULL_OFF,
-+ BCM2708_PULL_UP,
-+ BCM2708_PULL_DOWN
-+} bcm2708_gpio_pull_t;
-+
-+extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
-+ bcm2708_gpio_pull_t value);
-+
-+#endif
-diff -Nur linux-3.18.14/include/linux/vmstat.h linux-rpi/include/linux/vmstat.h
---- linux-3.18.14/include/linux/vmstat.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/include/linux/vmstat.h 2015-05-31 14:46:13.681660954 -0500
-@@ -241,7 +241,11 @@
- static inline void __dec_zone_state(struct zone *zone, enum zone_stat_item item)
- {
- atomic_long_dec(&zone->vm_stat[item]);
-+ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&zone->vm_stat[item]) < 0))
-+ atomic_long_set(&zone->vm_stat[item], 0);
- atomic_long_dec(&vm_stat[item]);
-+ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&vm_stat[item]) < 0))
-+ atomic_long_set(&vm_stat[item], 0);
- }
-
- static inline void __inc_zone_page_state(struct page *page,
-diff -Nur linux-3.18.14/include/linux/w1-gpio.h linux-rpi/include/linux/w1-gpio.h
---- linux-3.18.14/include/linux/w1-gpio.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/include/linux/w1-gpio.h 2015-05-31 14:46:13.681660954 -0500
-@@ -18,6 +18,7 @@
- struct w1_gpio_platform_data {
- unsigned int pin;
- unsigned int is_open_drain:1;
-+ unsigned int parasitic_power:1;
- void (*enable_external_pullup)(int enable);
- unsigned int ext_pullup_enable_pin;
- unsigned int pullup_duration;
-diff -Nur linux-3.18.14/include/uapi/linux/fb.h linux-rpi/include/uapi/linux/fb.h
---- linux-3.18.14/include/uapi/linux/fb.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/include/uapi/linux/fb.h 2015-05-31 14:46:13.761660954 -0500
-@@ -34,6 +34,11 @@
- #define FBIOPUT_MODEINFO 0x4617
- #define FBIOGET_DISPINFO 0x4618
- #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
-+/*
-+ * HACK: use 'z' in order not to clash with any other ioctl numbers which might
-+ * be concurrently added to the mainline kernel
-+ */
-+#define FBIOCOPYAREA _IOW('z', 0x21, struct fb_copyarea)
-
- #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
- #define FB_TYPE_PLANES 1 /* Non interleaved planes */
-diff -Nur linux-3.18.14/kernel/cgroup.c linux-rpi/kernel/cgroup.c
---- linux-3.18.14/kernel/cgroup.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/kernel/cgroup.c 2015-05-31 14:46:13.841660953 -0500
-@@ -5322,6 +5322,29 @@
- }
- __setup("cgroup_disable=", cgroup_disable);
-
-+static int __init cgroup_enable(char *str)
-+{
-+ struct cgroup_subsys *ss;
-+ char *token;
-+ int i;
-+
-+ while ((token = strsep(&str, ",")) != NULL) {
-+ if (!*token)
-+ continue;
-+
-+ for_each_subsys(ss, i) {
-+ if (!strcmp(token, ss->name)) {
-+ ss->disabled = 0;
-+ printk(KERN_INFO "Enabling %s control group"
-+ " subsystem\n", ss->name);
-+ break;
-+ }
-+ }
-+ }
-+ return 1;
-+}
-+__setup("cgroup_enable=", cgroup_enable);
-+
- static int __init cgroup_set_legacy_files_on_dfl(char *str)
- {
- printk("cgroup: using legacy files on the default hierarchy\n");
-diff -Nur linux-3.18.14/mm/memcontrol.c linux-rpi/mm/memcontrol.c
---- linux-3.18.14/mm/memcontrol.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/mm/memcontrol.c 2015-05-31 14:46:13.937660952 -0500
-@@ -6207,6 +6207,7 @@
- .bind = mem_cgroup_bind,
- .legacy_cftypes = mem_cgroup_files,
- .early_init = 0,
-+ .disabled = 1,
- };
-
- #ifdef CONFIG_MEMCG_SWAP
-diff -Nur linux-3.18.14/scripts/dtc/checks.c linux-rpi/scripts/dtc/checks.c
---- linux-3.18.14/scripts/dtc/checks.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/checks.c 2015-05-31 14:46:14.185660950 -0500
-@@ -53,7 +53,7 @@
- void *data;
- bool warn, error;
- enum checkstatus status;
-- int inprogress;
-+ bool inprogress;
- int num_prereqs;
- struct check **prereq;
- };
-@@ -113,6 +113,7 @@
- vfprintf(stderr, fmt, ap);
- fprintf(stderr, "\n");
- }
-+ va_end(ap);
- }
-
- #define FAIL(c, ...) \
-@@ -141,9 +142,9 @@
- check_nodes_props(c, dt, child);
- }
-
--static int run_check(struct check *c, struct node *dt)
-+static bool run_check(struct check *c, struct node *dt)
- {
-- int error = 0;
-+ bool error = false;
- int i;
-
- assert(!c->inprogress);
-@@ -151,11 +152,11 @@
- if (c->status != UNCHECKED)
- goto out;
-
-- c->inprogress = 1;
-+ c->inprogress = true;
-
- for (i = 0; i < c->num_prereqs; i++) {
- struct check *prq = c->prereq[i];
-- error |= run_check(prq, dt);
-+ error = error || run_check(prq, dt);
- if (prq->status != PASSED) {
- c->status = PREREQ;
- check_msg(c, "Failed prerequisite '%s'",
-@@ -177,9 +178,9 @@
- TRACE(c, "\tCompleted, status %d", c->status);
-
- out:
-- c->inprogress = 0;
-+ c->inprogress = false;
- if ((c->status != PASSED) && (c->error))
-- error = 1;
-+ error = true;
- return error;
- }
-
-@@ -457,22 +458,93 @@
- struct node *node, struct property *prop)
- {
- struct marker *m = prop->val.markers;
-+ struct fixup *f, **fp;
-+ struct fixup_entry *fe, **fep;
- struct node *refnode;
- cell_t phandle;
-+ int has_phandle_refs;
-+
-+ has_phandle_refs = 0;
-+ for_each_marker_of_type(m, REF_PHANDLE) {
-+ has_phandle_refs = 1;
-+ break;
-+ }
-+
-+ if (!has_phandle_refs)
-+ return;
-
- for_each_marker_of_type(m, REF_PHANDLE) {
- assert(m->offset + sizeof(cell_t) <= prop->val.len);
-
- refnode = get_node_by_ref(dt, m->ref);
-- if (! refnode) {
-+ if (!refnode && !symbol_fixup_support) {
- FAIL(c, "Reference to non-existent node or label \"%s\"\n",
-- m->ref);
-+ m->ref);
- continue;
- }
-
-- phandle = get_node_phandle(dt, refnode);
-- *((cell_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle);
-+ if (!refnode) {
-+ /* allocate fixup entry */
-+ fe = xmalloc(sizeof(*fe));
-+
-+ fe->node = node;
-+ fe->prop = prop;
-+ fe->offset = m->offset;
-+ fe->next = NULL;
-+
-+ /* search for an already existing fixup */
-+ for_each_fixup(dt, f)
-+ if (strcmp(f->ref, m->ref) == 0)
-+ break;
-+
-+ /* no fixup found, add new */
-+ if (f == NULL) {
-+ f = xmalloc(sizeof(*f));
-+ f->ref = m->ref;
-+ f->entries = NULL;
-+ f->next = NULL;
-+
-+ /* add it to the tree */
-+ fp = &dt->fixups;
-+ while (*fp)
-+ fp = &(*fp)->next;
-+ *fp = f;
-+ }
-+
-+ /* and now append fixup entry */
-+ fep = &f->entries;
-+ while (*fep)
-+ fep = &(*fep)->next;
-+ *fep = fe;
-+
-+ /* mark the entry as unresolved */
-+ phandle = 0xdeadbeef;
-+ } else {
-+ phandle = get_node_phandle(dt, refnode);
-+
-+ /* if it's a plugin, we need to record it */
-+ if (symbol_fixup_support && dt->is_plugin) {
-+
-+ /* allocate a new local fixup entry */
-+ fe = xmalloc(sizeof(*fe));
-+
-+ fe->node = node;
-+ fe->prop = prop;
-+ fe->offset = m->offset;
-+ fe->next = NULL;
-+
-+ /* append it to the local fixups */
-+ fep = &dt->local_fixups;
-+ while (*fep)
-+ fep = &(*fep)->next;
-+ *fep = fe;
-+ }
-+ }
-+
-+ *((cell_t *)(prop->val.val + m->offset)) =
-+ cpu_to_fdt32(phandle);
- }
-+
- }
- ERROR(phandle_references, NULL, NULL, fixup_phandle_references, NULL,
- &duplicate_node_names, &explicit_phandles);
-@@ -624,11 +696,11 @@
- if (!reg && !ranges)
- return;
-
-- if ((node->parent->addr_cells == -1))
-+ if (node->parent->addr_cells == -1)
- FAIL(c, "Relying on default #address-cells value for %s",
- node->fullpath);
-
-- if ((node->parent->size_cells == -1))
-+ if (node->parent->size_cells == -1)
- FAIL(c, "Relying on default #size-cells value for %s",
- node->fullpath);
- }
-@@ -651,6 +723,45 @@
- }
- TREE_WARNING(obsolete_chosen_interrupt_controller, NULL);
-
-+static void check_auto_label_phandles(struct check *c, struct node *dt,
-+ struct node *node)
-+{
-+ struct label *l;
-+ struct symbol *s, **sp;
-+ int has_label;
-+
-+ if (!symbol_fixup_support)
-+ return;
-+
-+ has_label = 0;
-+ for_each_label(node->labels, l) {
-+ has_label = 1;
-+ break;
-+ }
-+
-+ if (!has_label)
-+ return;
-+
-+ /* force allocation of a phandle for this node */
-+ (void)get_node_phandle(dt, node);
-+
-+ /* add the symbol */
-+ for_each_label(node->labels, l) {
-+
-+ s = xmalloc(sizeof(*s));
-+ s->label = l;
-+ s->node = node;
-+ s->next = NULL;
-+
-+ /* add it to the symbols list */
-+ sp = &dt->symbols;
-+ while (*sp)
-+ sp = &((*sp)->next);
-+ *sp = s;
-+ }
-+}
-+NODE_WARNING(auto_label_phandles, NULL);
-+
- static struct check *check_table[] = {
- &duplicate_node_names, &duplicate_property_names,
- &node_name_chars, &node_name_format, &property_name_chars,
-@@ -669,6 +780,8 @@
- &avoid_default_addr_size,
- &obsolete_chosen_interrupt_controller,
-
-+ &auto_label_phandles,
-+
- &always_fail,
- };
-
-@@ -706,15 +819,15 @@
- c->error = c->error && !error;
- }
-
--void parse_checks_option(bool warn, bool error, const char *optarg)
-+void parse_checks_option(bool warn, bool error, const char *arg)
- {
- int i;
-- const char *name = optarg;
-+ const char *name = arg;
- bool enable = true;
-
-- if ((strncmp(optarg, "no-", 3) == 0)
-- || (strncmp(optarg, "no_", 3) == 0)) {
-- name = optarg + 3;
-+ if ((strncmp(arg, "no-", 3) == 0)
-+ || (strncmp(arg, "no_", 3) == 0)) {
-+ name = arg + 3;
- enable = false;
- }
-
-@@ -733,7 +846,7 @@
- die("Unrecognized check name \"%s\"\n", name);
- }
-
--void process_checks(int force, struct boot_info *bi)
-+void process_checks(bool force, struct boot_info *bi)
- {
- struct node *dt = bi->dt;
- int i;
-diff -Nur linux-3.18.14/scripts/dtc/data.c linux-rpi/scripts/dtc/data.c
---- linux-3.18.14/scripts/dtc/data.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/data.c 2015-05-31 14:46:14.185660950 -0500
-@@ -74,7 +74,7 @@
- struct data d;
- char *q;
-
-- d = data_grow_for(empty_data, strlen(s)+1);
-+ d = data_grow_for(empty_data, len + 1);
-
- q = d.val;
- while (i < len) {
-@@ -250,20 +250,20 @@
- return data_append_markers(d, m);
- }
-
--int data_is_one_string(struct data d)
-+bool data_is_one_string(struct data d)
- {
- int i;
- int len = d.len;
-
- if (len == 0)
-- return 0;
-+ return false;
-
- for (i = 0; i < len-1; i++)
- if (d.val[i] == '\0')
-- return 0;
-+ return false;
-
- if (d.val[len-1] != '\0')
-- return 0;
-+ return false;
-
-- return 1;
-+ return true;
- }
-diff -Nur linux-3.18.14/scripts/dtc/dtc.c linux-rpi/scripts/dtc/dtc.c
---- linux-3.18.14/scripts/dtc/dtc.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc.c 2015-05-31 14:46:14.189660949 -0500
-@@ -29,6 +29,7 @@
- int minsize; /* Minimum blob size */
- int padsize; /* Additional padding to blob */
- int phandle_format = PHANDLE_BOTH; /* Use linux,phandle or phandle properties */
-+int symbol_fixup_support = 0;
-
- static void fill_fullpaths(struct node *tree, const char *prefix)
- {
-@@ -48,8 +49,10 @@
- }
-
- /* Usage related data. */
-+#define FDT_VERSION(version) _FDT_VERSION(version)
-+#define _FDT_VERSION(version) #version
- static const char usage_synopsis[] = "dtc [options] <input file>";
--static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv";
-+static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv@";
- static struct option const usage_long_opts[] = {
- {"quiet", no_argument, NULL, 'q'},
- {"in-format", a_argument, NULL, 'I'},
-@@ -67,6 +70,7 @@
- {"phandle", a_argument, NULL, 'H'},
- {"warning", a_argument, NULL, 'W'},
- {"error", a_argument, NULL, 'E'},
-+ {"symbols", a_argument, NULL, '@'},
- {"help", no_argument, NULL, 'h'},
- {"version", no_argument, NULL, 'v'},
- {NULL, no_argument, NULL, 0x0},
-@@ -82,9 +86,9 @@
- "\t\tdts - device tree source text\n"
- "\t\tdtb - device tree blob\n"
- "\t\tasm - assembler source",
-- "\n\tBlob version to produce, defaults to %d (for dtb and asm output)", //, DEFAULT_FDT_VERSION);
-+ "\n\tBlob version to produce, defaults to "FDT_VERSION(DEFAULT_FDT_VERSION)" (for dtb and asm output)",
- "\n\tOutput dependency file",
-- "\n\ttMake space for <number> reserve map entries (for dtb and asm output)",
-+ "\n\tMake space for <number> reserve map entries (for dtb and asm output)",
- "\n\tMake the blob at least <bytes> long (extra space)",
- "\n\tAdd padding to the blob of <bytes> long (extra space)",
- "\n\tSet the physical boot cpu",
-@@ -97,6 +101,7 @@
- "\t\tboth - Both \"linux,phandle\" and \"phandle\" properties",
- "\n\tEnable/disable warnings (prefix with \"no-\")",
- "\n\tEnable/disable errors (prefix with \"no-\")",
-+ "\n\tSymbols and Fixups support",
- "\n\tPrint this help and exit",
- "\n\tPrint version and exit",
- NULL,
-@@ -109,7 +114,7 @@
- const char *outform = "dts";
- const char *outname = "-";
- const char *depname = NULL;
-- int force = 0, sort = 0;
-+ bool force = false, sort = false;
- const char *arg;
- int opt;
- FILE *outf = NULL;
-@@ -148,7 +153,7 @@
- padsize = strtol(optarg, NULL, 0);
- break;
- case 'f':
-- force = 1;
-+ force = true;
- break;
- case 'q':
- quiet++;
-@@ -174,7 +179,7 @@
- break;
-
- case 's':
-- sort = 1;
-+ sort = true;
- break;
-
- case 'W':
-@@ -184,7 +189,9 @@
- case 'E':
- parse_checks_option(false, true, optarg);
- break;
--
-+ case '@':
-+ symbol_fixup_support = 1;
-+ break;
- case 'h':
- usage(NULL);
- default:
-@@ -237,7 +244,7 @@
- if (streq(outname, "-")) {
- outf = stdout;
- } else {
-- outf = fopen(outname, "w");
-+ outf = fopen(outname, "wb");
- if (! outf)
- die("Couldn't open output file %s: %s\n",
- outname, strerror(errno));
-diff -Nur linux-3.18.14/scripts/dtc/dtc.h linux-rpi/scripts/dtc/dtc.h
---- linux-3.18.14/scripts/dtc/dtc.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc.h 2015-05-31 14:46:14.189660949 -0500
-@@ -38,9 +38,9 @@
- #include "util.h"
-
- #ifdef DEBUG
--#define debug(fmt,args...) printf(fmt, ##args)
-+#define debug(...) printf(__VA_ARGS__)
- #else
--#define debug(fmt,args...)
-+#define debug(...)
- #endif
-
-
-@@ -54,6 +54,7 @@
- extern int minsize; /* Minimum blob size */
- extern int padsize; /* Additional padding to blob */
- extern int phandle_format; /* Use linux,phandle or phandle properties */
-+extern int symbol_fixup_support;/* enable symbols & fixup support */
-
- #define PHANDLE_LEGACY 0x1
- #define PHANDLE_EPAPR 0x2
-@@ -88,7 +89,7 @@
- };
-
-
--#define empty_data ((struct data){ /* all .members = 0 or NULL */ })
-+#define empty_data ((struct data){ 0 /* all .members = 0 or NULL */ })
-
- #define for_each_marker(m) \
- for (; (m); (m) = (m)->next)
-@@ -118,7 +119,7 @@
-
- struct data data_add_marker(struct data d, enum markertype type, char *ref);
-
--int data_is_one_string(struct data d);
-+bool data_is_one_string(struct data d);
-
- /* DT constraints */
-
-@@ -127,13 +128,32 @@
-
- /* Live trees */
- struct label {
-- int deleted;
-+ bool deleted;
- char *label;
- struct label *next;
- };
-
-+struct fixup_entry {
-+ int offset;
-+ struct node *node;
-+ struct property *prop;
-+ struct fixup_entry *next;
-+};
-+
-+struct fixup {
-+ char *ref;
-+ struct fixup_entry *entries;
-+ struct fixup *next;
-+};
-+
-+struct symbol {
-+ struct label *label;
-+ struct node *node;
-+ struct symbol *next;
-+};
-+
- struct property {
-- int deleted;
-+ bool deleted;
- char *name;
- struct data val;
-
-@@ -143,7 +163,7 @@
- };
-
- struct node {
-- int deleted;
-+ bool deleted;
- char *name;
- struct property *proplist;
- struct node *children;
-@@ -158,6 +178,12 @@
- int addr_cells, size_cells;
-
- struct label *labels;
-+
-+ int is_root;
-+ int is_plugin;
-+ struct fixup *fixups;
-+ struct symbol *symbols;
-+ struct fixup_entry *local_fixups;
- };
-
- #define for_each_label_withdel(l0, l) \
-@@ -181,6 +207,18 @@
- for_each_child_withdel(n, c) \
- if (!(c)->deleted)
-
-+#define for_each_fixup(n, f) \
-+ for ((f) = (n)->fixups; (f); (f) = (f)->next)
-+
-+#define for_each_fixup_entry(f, fe) \
-+ for ((fe) = (f)->entries; (fe); (fe) = (fe)->next)
-+
-+#define for_each_symbol(n, s) \
-+ for ((s) = (n)->symbols; (s); (s) = (s)->next)
-+
-+#define for_each_local_fixup_entry(n, fe) \
-+ for ((fe) = (n)->local_fixups; (fe); (fe) = (fe)->next)
-+
- void add_label(struct label **labels, char *label);
- void delete_labels(struct label **labels);
-
-@@ -247,8 +285,8 @@
-
- /* Checks */
-
--void parse_checks_option(bool warn, bool error, const char *optarg);
--void process_checks(int force, struct boot_info *bi);
-+void parse_checks_option(bool warn, bool error, const char *arg);
-+void process_checks(bool force, struct boot_info *bi);
-
- /* Flattened trees */
-
-diff -Nur linux-3.18.14/scripts/dtc/dtc-lexer.l linux-rpi/scripts/dtc/dtc-lexer.l
---- linux-3.18.14/scripts/dtc/dtc-lexer.l 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc-lexer.l 2015-05-31 14:46:14.185660950 -0500
-@@ -20,7 +20,6 @@
-
- %option noyywrap nounput noinput never-interactive
-
--%x INCLUDE
- %x BYTESTRING
- %x PROPNODENAME
- %s V1
-@@ -40,6 +39,7 @@
- #include "dtc-parser.tab.h"
-
- YYLTYPE yylloc;
-+extern bool treesource_error;
-
- /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
- #define YY_USER_ACTION \
-@@ -61,7 +61,8 @@
- BEGIN(V1); \
-
- static void push_input_file(const char *filename);
--static int pop_input_file(void);
-+static bool pop_input_file(void);
-+static void lexical_error(const char *fmt, ...);
- %}
-
- %%
-@@ -75,11 +76,11 @@
- char *line, *tmp, *fn;
- /* skip text before line # */
- line = yytext;
-- while (!isdigit(*line))
-+ while (!isdigit((unsigned char)*line))
- line++;
- /* skip digits in line # */
- tmp = line;
-- while (!isspace(*tmp))
-+ while (!isspace((unsigned char)*tmp))
- tmp++;
- /* "NULL"-terminate line # */
- *tmp = '\0';
-@@ -112,6 +113,11 @@
- return DT_V1;
- }
-
-+<*>"/plugin/" {
-+ DPRINT("Keyword: /plugin/\n");
-+ return DT_PLUGIN;
-+ }
-+
- <*>"/memreserve/" {
- DPRINT("Keyword: /memreserve/\n");
- BEGIN_DEFAULT();
-@@ -146,15 +152,42 @@
- }
-
- <V1>([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? {
-- yylval.literal = xstrdup(yytext);
-- DPRINT("Literal: '%s'\n", yylval.literal);
-+ char *e;
-+ DPRINT("Integer Literal: '%s'\n", yytext);
-+
-+ errno = 0;
-+ yylval.integer = strtoull(yytext, &e, 0);
-+
-+ assert(!(*e) || !e[strspn(e, "UL")]);
-+
-+ if (errno == ERANGE)
-+ lexical_error("Integer literal '%s' out of range",
-+ yytext);
-+ else
-+ /* ERANGE is the only strtoull error triggerable
-+ * by strings matching the pattern */
-+ assert(errno == 0);
- return DT_LITERAL;
- }
-
- <*>{CHAR_LITERAL} {
-- yytext[yyleng-1] = '\0';
-- yylval.literal = xstrdup(yytext+1);
-- DPRINT("Character literal: %s\n", yylval.literal);
-+ struct data d;
-+ DPRINT("Character literal: %s\n", yytext);
-+
-+ d = data_copy_escape_string(yytext+1, yyleng-2);
-+ if (d.len == 1) {
-+ lexical_error("Empty character literal");
-+ yylval.integer = 0;
-+ return DT_CHAR_LITERAL;
-+ }
-+
-+ yylval.integer = (unsigned char)d.val[0];
-+
-+ if (d.len > 2)
-+ lexical_error("Character literal has %d"
-+ " characters instead of 1",
-+ d.len - 1);
-+
- return DT_CHAR_LITERAL;
- }
-
-@@ -164,7 +197,7 @@
- return DT_REF;
- }
-
--<*>"&{/"{PATHCHAR}+\} { /* new-style path reference */
-+<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */
- yytext[yyleng-1] = '\0';
- DPRINT("Ref: %s\n", yytext+2);
- yylval.labelref = xstrdup(yytext+2);
-@@ -238,13 +271,24 @@
- }
-
-
--static int pop_input_file(void)
-+static bool pop_input_file(void)
- {
- if (srcfile_pop() == 0)
-- return 0;
-+ return false;
-
- yypop_buffer_state();
- yyin = current_srcfile->f;
-
-- return 1;
-+ return true;
-+}
-+
-+static void lexical_error(const char *fmt, ...)
-+{
-+ va_list ap;
-+
-+ va_start(ap, fmt);
-+ srcpos_verror(&yylloc, "Lexical error", fmt, ap);
-+ va_end(ap);
-+
-+ treesource_error = true;
- }
-diff -Nur linux-3.18.14/scripts/dtc/dtc-lexer.lex.c_shipped linux-rpi/scripts/dtc/dtc-lexer.lex.c_shipped
---- linux-3.18.14/scripts/dtc/dtc-lexer.lex.c_shipped 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc-lexer.lex.c_shipped 2015-05-31 14:46:14.185660950 -0500
-@@ -372,8 +372,8 @@
- *yy_cp = '\0'; \
- (yy_c_buf_p) = yy_cp;
-
--#define YY_NUM_RULES 30
--#define YY_END_OF_BUFFER 31
-+#define YY_NUM_RULES 31
-+#define YY_END_OF_BUFFER 32
- /* This struct is not used in this scanner,
- but its presence is necessary. */
- struct yy_trans_info
-@@ -381,25 +381,26 @@
- flex_int32_t yy_verify;
- flex_int32_t yy_nxt;
- };
--static yyconst flex_int16_t yy_accept[161] =
-+static yyconst flex_int16_t yy_accept[166] =
- { 0,
-+ 0, 0, 0, 0, 0, 0, 0, 0, 32, 30,
-+ 19, 19, 30, 30, 30, 30, 30, 30, 30, 30,
-+ 30, 30, 30, 30, 30, 30, 16, 17, 17, 30,
-+ 17, 11, 11, 19, 27, 0, 3, 0, 28, 13,
-+ 0, 0, 12, 0, 0, 0, 0, 0, 0, 0,
-+ 0, 22, 24, 26, 25, 23, 0, 10, 29, 0,
-+ 0, 0, 15, 15, 17, 17, 17, 11, 11, 11,
-+ 0, 13, 0, 12, 0, 0, 0, 21, 0, 0,
-+ 0, 0, 0, 0, 0, 0, 0, 17, 11, 11,
-+ 11, 0, 14, 20, 0, 0, 0, 0, 0, 0,
-+
-+ 0, 0, 0, 0, 17, 0, 0, 0, 0, 0,
-+ 0, 0, 0, 0, 0, 17, 7, 0, 0, 0,
-+ 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
-+ 0, 0, 0, 0, 4, 18, 0, 0, 5, 2,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-- 31, 29, 18, 18, 29, 29, 29, 29, 29, 29,
-- 29, 29, 29, 29, 29, 29, 29, 29, 15, 16,
-- 16, 29, 16, 10, 10, 18, 26, 0, 3, 0,
-- 27, 12, 0, 0, 11, 0, 0, 0, 0, 0,
-- 0, 0, 21, 23, 25, 24, 22, 0, 9, 28,
-- 0, 0, 0, 14, 14, 16, 16, 16, 10, 10,
-- 10, 0, 12, 0, 11, 0, 0, 0, 20, 0,
-- 0, 0, 0, 0, 0, 0, 0, 16, 10, 10,
-- 10, 0, 19, 0, 0, 0, 0, 0, 0, 0,
--
-- 0, 0, 16, 13, 0, 0, 0, 0, 0, 0,
-- 0, 0, 0, 16, 6, 0, 0, 0, 0, 0,
-- 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
-- 4, 17, 0, 0, 2, 0, 0, 0, 0, 0,
-- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
-- 0, 0, 5, 8, 0, 0, 0, 0, 7, 0
-+ 0, 0, 1, 0, 0, 0, 0, 6, 9, 0,
-+ 0, 0, 0, 8, 0
- } ;
-
- static yyconst flex_int32_t yy_ec[256] =
-@@ -415,9 +416,9 @@
- 22, 22, 22, 22, 24, 22, 22, 25, 22, 22,
- 1, 26, 27, 1, 22, 1, 21, 28, 29, 30,
-
-- 31, 21, 22, 22, 32, 22, 22, 33, 34, 35,
-- 36, 37, 22, 38, 39, 40, 41, 42, 22, 25,
-- 43, 22, 44, 45, 46, 1, 1, 1, 1, 1,
-+ 31, 21, 32, 22, 33, 22, 22, 34, 35, 36,
-+ 37, 38, 22, 39, 40, 41, 42, 43, 22, 25,
-+ 44, 22, 45, 46, 47, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-@@ -434,163 +435,165 @@
- 1, 1, 1, 1, 1
- } ;
-
--static yyconst flex_int32_t yy_meta[47] =
-+static yyconst flex_int32_t yy_meta[48] =
- { 0,
- 1, 1, 1, 1, 1, 1, 2, 3, 1, 2,
- 2, 2, 4, 5, 5, 5, 6, 1, 1, 1,
- 7, 8, 8, 8, 8, 1, 1, 7, 7, 7,
- 7, 8, 8, 8, 8, 8, 8, 8, 8, 8,
-- 8, 8, 8, 3, 1, 1
-+ 8, 8, 8, 8, 3, 1, 4
- } ;
-
--static yyconst flex_int16_t yy_base[175] =
-+static yyconst flex_int16_t yy_base[180] =
- { 0,
-- 0, 385, 378, 40, 41, 383, 72, 382, 34, 44,
-- 388, 393, 61, 117, 368, 116, 115, 115, 115, 48,
-- 367, 107, 368, 339, 127, 120, 0, 147, 393, 0,
-- 127, 0, 133, 156, 168, 153, 393, 125, 393, 380,
-- 393, 0, 369, 127, 393, 160, 371, 377, 347, 21,
-- 343, 346, 393, 393, 393, 393, 393, 359, 393, 393,
-- 183, 343, 339, 393, 356, 0, 183, 340, 187, 348,
-- 347, 0, 0, 0, 178, 359, 195, 365, 354, 326,
-- 332, 325, 334, 328, 204, 326, 331, 324, 393, 335,
-- 150, 311, 343, 342, 315, 322, 340, 179, 313, 207,
--
-- 319, 316, 317, 393, 337, 333, 305, 302, 311, 301,
-- 310, 190, 338, 337, 393, 307, 322, 301, 305, 277,
-- 208, 311, 307, 278, 271, 270, 248, 246, 213, 130,
-- 393, 393, 263, 235, 207, 221, 218, 229, 213, 213,
-- 206, 234, 218, 210, 208, 193, 219, 393, 223, 204,
-- 176, 157, 393, 393, 120, 106, 97, 119, 393, 393,
-- 245, 251, 259, 263, 267, 273, 280, 284, 292, 300,
-- 304, 310, 318, 326
-+ 0, 393, 35, 392, 66, 391, 38, 107, 397, 401,
-+ 55, 113, 377, 112, 111, 111, 114, 42, 376, 106,
-+ 377, 347, 126, 120, 0, 147, 401, 0, 124, 0,
-+ 137, 158, 170, 163, 401, 153, 401, 389, 401, 0,
-+ 378, 120, 401, 131, 380, 386, 355, 139, 351, 355,
-+ 351, 401, 401, 401, 401, 401, 367, 401, 401, 185,
-+ 350, 346, 401, 364, 0, 185, 347, 189, 356, 355,
-+ 0, 0, 330, 180, 366, 141, 372, 361, 332, 338,
-+ 331, 341, 334, 326, 205, 331, 337, 329, 401, 341,
-+ 167, 316, 401, 349, 348, 320, 328, 346, 180, 318,
-+
-+ 324, 209, 324, 320, 322, 342, 338, 309, 306, 315,
-+ 305, 315, 312, 192, 342, 341, 401, 293, 306, 282,
-+ 268, 252, 255, 203, 285, 282, 272, 268, 252, 233,
-+ 232, 239, 208, 107, 401, 401, 238, 211, 401, 211,
-+ 212, 208, 228, 203, 215, 207, 233, 222, 212, 211,
-+ 203, 227, 401, 237, 225, 204, 185, 401, 401, 149,
-+ 128, 88, 42, 401, 401, 253, 259, 267, 271, 275,
-+ 281, 288, 292, 300, 308, 312, 318, 326, 334
- } ;
-
--static yyconst flex_int16_t yy_def[175] =
-+static yyconst flex_int16_t yy_def[180] =
- { 0,
-- 160, 1, 1, 1, 1, 5, 160, 7, 1, 1,
-- 160, 160, 160, 160, 160, 161, 162, 163, 160, 160,
-- 160, 160, 164, 160, 160, 160, 165, 164, 160, 166,
-- 167, 166, 166, 160, 160, 160, 160, 161, 160, 161,
-- 160, 168, 160, 163, 160, 163, 169, 170, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 164, 160, 160,
-- 160, 160, 160, 160, 164, 166, 167, 166, 160, 160,
-- 160, 171, 168, 172, 163, 169, 169, 170, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 166, 160, 160,
-- 171, 172, 160, 160, 160, 160, 160, 160, 160, 160,
--
-- 160, 160, 166, 160, 160, 160, 160, 160, 160, 160,
-- 160, 173, 160, 166, 160, 160, 160, 160, 160, 160,
-- 173, 160, 173, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 174, 160, 160, 160, 174, 160, 174, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 0,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160
-+ 165, 1, 1, 3, 165, 5, 1, 1, 165, 165,
-+ 165, 165, 165, 166, 167, 168, 165, 165, 165, 165,
-+ 169, 165, 165, 165, 170, 169, 165, 171, 172, 171,
-+ 171, 165, 165, 165, 165, 166, 165, 166, 165, 173,
-+ 165, 168, 165, 168, 174, 175, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 169, 165, 165, 165,
-+ 165, 165, 165, 169, 171, 172, 171, 165, 165, 165,
-+ 176, 173, 177, 168, 174, 174, 175, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 171, 165, 165,
-+ 176, 177, 165, 165, 165, 165, 165, 165, 165, 165,
-+
-+ 165, 165, 165, 165, 171, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 178, 165, 171, 165, 165, 165, 165,
-+ 165, 165, 165, 178, 165, 178, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 179, 165, 165,
-+ 165, 179, 165, 179, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 0, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165
- } ;
-
--static yyconst flex_int16_t yy_nxt[440] =
-+static yyconst flex_int16_t yy_nxt[449] =
- { 0,
-- 12, 13, 14, 13, 15, 16, 12, 17, 18, 12,
-- 12, 12, 19, 12, 12, 12, 12, 20, 21, 22,
-- 23, 23, 23, 23, 23, 12, 12, 23, 23, 23,
-- 23, 23, 23, 23, 23, 23, 23, 23, 23, 23,
-- 23, 23, 23, 12, 24, 12, 25, 34, 35, 35,
-- 25, 81, 26, 26, 27, 27, 27, 34, 35, 35,
-- 82, 28, 36, 36, 36, 53, 54, 29, 28, 28,
-- 28, 28, 12, 13, 14, 13, 15, 16, 30, 17,
-- 18, 30, 30, 30, 26, 30, 30, 30, 12, 20,
-- 21, 22, 31, 31, 31, 31, 31, 32, 12, 31,
--
-- 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
-- 31, 31, 31, 31, 31, 12, 24, 12, 36, 36,
-- 36, 39, 41, 45, 47, 56, 57, 48, 61, 47,
-- 39, 159, 48, 66, 61, 45, 66, 66, 66, 158,
-- 46, 40, 49, 59, 50, 157, 51, 49, 52, 50,
-- 40, 63, 46, 52, 36, 36, 36, 156, 43, 62,
-- 65, 65, 65, 59, 136, 68, 137, 65, 75, 69,
-- 69, 69, 70, 71, 65, 65, 65, 65, 70, 71,
-- 72, 69, 69, 69, 61, 46, 45, 155, 154, 66,
-- 70, 71, 66, 66, 66, 122, 85, 85, 85, 59,
--
-- 69, 69, 69, 46, 77, 100, 109, 93, 100, 70,
-- 71, 110, 112, 122, 129, 123, 153, 85, 85, 85,
-- 135, 135, 135, 148, 148, 160, 135, 135, 135, 152,
-- 142, 142, 142, 123, 143, 142, 142, 142, 151, 143,
-- 150, 146, 145, 149, 149, 38, 38, 38, 38, 38,
-- 38, 38, 38, 42, 144, 141, 140, 42, 42, 44,
-- 44, 44, 44, 44, 44, 44, 44, 58, 58, 58,
-- 58, 64, 139, 64, 66, 138, 134, 66, 133, 66,
-- 66, 67, 132, 131, 67, 67, 67, 67, 73, 130,
-- 73, 73, 76, 76, 76, 76, 76, 76, 76, 76,
--
-- 78, 78, 78, 78, 78, 78, 78, 78, 91, 160,
-- 91, 92, 129, 92, 92, 128, 92, 92, 121, 121,
-- 121, 121, 121, 121, 121, 121, 147, 147, 147, 147,
-- 147, 147, 147, 147, 127, 126, 125, 124, 61, 61,
-- 120, 119, 118, 117, 116, 115, 47, 114, 110, 113,
-- 111, 108, 107, 106, 48, 105, 104, 89, 103, 102,
-- 101, 99, 98, 97, 96, 95, 94, 79, 77, 90,
-- 89, 88, 59, 87, 86, 59, 84, 83, 80, 79,
-- 77, 74, 160, 60, 59, 55, 37, 160, 33, 25,
-- 26, 25, 11, 160, 160, 160, 160, 160, 160, 160,
--
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160
-+ 10, 11, 12, 11, 13, 14, 10, 15, 16, 10,
-+ 10, 10, 17, 10, 10, 10, 10, 18, 19, 20,
-+ 21, 21, 21, 21, 21, 10, 10, 21, 21, 21,
-+ 21, 21, 21, 21, 21, 21, 21, 21, 21, 21,
-+ 21, 21, 21, 21, 10, 22, 10, 24, 25, 25,
-+ 25, 32, 33, 33, 164, 26, 34, 34, 34, 52,
-+ 53, 27, 26, 26, 26, 26, 10, 11, 12, 11,
-+ 13, 14, 28, 15, 16, 28, 28, 28, 24, 28,
-+ 28, 28, 10, 18, 19, 20, 29, 29, 29, 29,
-+ 29, 30, 10, 29, 29, 29, 29, 29, 29, 29,
-+
-+ 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
-+ 10, 22, 10, 23, 34, 34, 34, 37, 39, 43,
-+ 32, 33, 33, 45, 55, 56, 46, 60, 43, 45,
-+ 65, 163, 46, 65, 65, 65, 44, 38, 60, 74,
-+ 58, 47, 141, 48, 142, 44, 49, 47, 50, 48,
-+ 76, 51, 62, 94, 50, 41, 44, 51, 37, 61,
-+ 64, 64, 64, 58, 34, 34, 34, 64, 162, 80,
-+ 67, 68, 68, 68, 64, 64, 64, 64, 38, 81,
-+ 69, 70, 71, 68, 68, 68, 60, 161, 43, 69,
-+ 70, 65, 69, 70, 65, 65, 65, 125, 85, 85,
-+
-+ 85, 58, 68, 68, 68, 44, 102, 110, 125, 133,
-+ 102, 69, 70, 111, 114, 160, 159, 126, 85, 85,
-+ 85, 140, 140, 140, 140, 140, 140, 153, 126, 147,
-+ 147, 147, 153, 148, 147, 147, 147, 158, 148, 165,
-+ 157, 156, 155, 151, 150, 149, 146, 154, 145, 144,
-+ 143, 139, 154, 36, 36, 36, 36, 36, 36, 36,
-+ 36, 40, 138, 137, 136, 40, 40, 42, 42, 42,
-+ 42, 42, 42, 42, 42, 57, 57, 57, 57, 63,
-+ 135, 63, 65, 134, 165, 65, 133, 65, 65, 66,
-+ 132, 131, 66, 66, 66, 66, 72, 130, 72, 72,
-+
-+ 75, 75, 75, 75, 75, 75, 75, 75, 77, 77,
-+ 77, 77, 77, 77, 77, 77, 91, 129, 91, 92,
-+ 128, 92, 92, 127, 92, 92, 124, 124, 124, 124,
-+ 124, 124, 124, 124, 152, 152, 152, 152, 152, 152,
-+ 152, 152, 60, 60, 123, 122, 121, 120, 119, 118,
-+ 117, 45, 116, 111, 115, 113, 112, 109, 108, 107,
-+ 46, 106, 93, 89, 105, 104, 103, 101, 100, 99,
-+ 98, 97, 96, 95, 78, 76, 93, 90, 89, 88,
-+ 58, 87, 86, 58, 84, 83, 82, 79, 78, 76,
-+ 73, 165, 59, 58, 54, 35, 165, 31, 23, 23,
-+
-+ 9, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165
- } ;
-
--static yyconst flex_int16_t yy_chk[440] =
-+static yyconst flex_int16_t yy_chk[449] =
- { 0,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-- 1, 1, 1, 1, 1, 1, 4, 9, 9, 9,
-- 10, 50, 4, 5, 5, 5, 5, 10, 10, 10,
-- 50, 5, 13, 13, 13, 20, 20, 5, 5, 5,
-- 5, 5, 7, 7, 7, 7, 7, 7, 7, 7,
-- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
--
-- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-- 7, 7, 7, 7, 7, 7, 7, 7, 14, 14,
-- 14, 16, 17, 18, 19, 22, 22, 19, 25, 26,
-- 38, 158, 26, 31, 33, 44, 31, 31, 31, 157,
-- 18, 16, 19, 31, 19, 156, 19, 26, 19, 26,
-- 38, 26, 44, 26, 36, 36, 36, 155, 17, 25,
-- 28, 28, 28, 28, 130, 33, 130, 28, 46, 34,
-- 34, 34, 91, 91, 28, 28, 28, 28, 34, 34,
-- 34, 35, 35, 35, 61, 46, 75, 152, 151, 67,
-- 35, 35, 67, 67, 67, 112, 61, 61, 61, 67,
--
-- 69, 69, 69, 75, 77, 85, 98, 77, 100, 69,
-- 69, 98, 100, 121, 129, 112, 150, 85, 85, 85,
-- 135, 135, 135, 143, 147, 149, 129, 129, 129, 146,
-- 138, 138, 138, 121, 138, 142, 142, 142, 145, 142,
-- 144, 141, 140, 143, 147, 161, 161, 161, 161, 161,
-- 161, 161, 161, 162, 139, 137, 136, 162, 162, 163,
-- 163, 163, 163, 163, 163, 163, 163, 164, 164, 164,
-- 164, 165, 134, 165, 166, 133, 128, 166, 127, 166,
-- 166, 167, 126, 125, 167, 167, 167, 167, 168, 124,
-- 168, 168, 169, 169, 169, 169, 169, 169, 169, 169,
--
-- 170, 170, 170, 170, 170, 170, 170, 170, 171, 123,
-- 171, 172, 122, 172, 172, 120, 172, 172, 173, 173,
-- 173, 173, 173, 173, 173, 173, 174, 174, 174, 174,
-- 174, 174, 174, 174, 119, 118, 117, 116, 114, 113,
-- 111, 110, 109, 108, 107, 106, 105, 103, 102, 101,
-- 99, 97, 96, 95, 94, 93, 92, 90, 88, 87,
-- 86, 84, 83, 82, 81, 80, 79, 78, 76, 71,
-- 70, 68, 65, 63, 62, 58, 52, 51, 49, 48,
-- 47, 43, 40, 24, 23, 21, 15, 11, 8, 6,
-- 3, 2, 160, 160, 160, 160, 160, 160, 160, 160,
--
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
-- 160, 160, 160, 160, 160, 160, 160, 160, 160
-+ 1, 1, 1, 1, 1, 1, 1, 3, 3, 3,
-+ 3, 7, 7, 7, 163, 3, 11, 11, 11, 18,
-+ 18, 3, 3, 3, 3, 3, 5, 5, 5, 5,
-+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-+
-+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-+ 5, 5, 5, 8, 12, 12, 12, 14, 15, 16,
-+ 8, 8, 8, 17, 20, 20, 17, 23, 42, 24,
-+ 29, 162, 24, 29, 29, 29, 16, 14, 31, 44,
-+ 29, 17, 134, 17, 134, 42, 17, 24, 17, 24,
-+ 76, 17, 24, 76, 24, 15, 44, 24, 36, 23,
-+ 26, 26, 26, 26, 34, 34, 34, 26, 161, 48,
-+ 31, 32, 32, 32, 26, 26, 26, 26, 36, 48,
-+ 32, 32, 32, 33, 33, 33, 60, 160, 74, 91,
-+ 91, 66, 33, 33, 66, 66, 66, 114, 60, 60,
-+
-+ 60, 66, 68, 68, 68, 74, 85, 99, 124, 133,
-+ 102, 68, 68, 99, 102, 157, 156, 114, 85, 85,
-+ 85, 133, 133, 133, 140, 140, 140, 148, 124, 143,
-+ 143, 143, 152, 143, 147, 147, 147, 155, 147, 154,
-+ 151, 150, 149, 146, 145, 144, 142, 148, 141, 138,
-+ 137, 132, 152, 166, 166, 166, 166, 166, 166, 166,
-+ 166, 167, 131, 130, 129, 167, 167, 168, 168, 168,
-+ 168, 168, 168, 168, 168, 169, 169, 169, 169, 170,
-+ 128, 170, 171, 127, 126, 171, 125, 171, 171, 172,
-+ 123, 122, 172, 172, 172, 172, 173, 121, 173, 173,
-+
-+ 174, 174, 174, 174, 174, 174, 174, 174, 175, 175,
-+ 175, 175, 175, 175, 175, 175, 176, 120, 176, 177,
-+ 119, 177, 177, 118, 177, 177, 178, 178, 178, 178,
-+ 178, 178, 178, 178, 179, 179, 179, 179, 179, 179,
-+ 179, 179, 116, 115, 113, 112, 111, 110, 109, 108,
-+ 107, 106, 105, 104, 103, 101, 100, 98, 97, 96,
-+ 95, 94, 92, 90, 88, 87, 86, 84, 83, 82,
-+ 81, 80, 79, 78, 77, 75, 73, 70, 69, 67,
-+ 64, 62, 61, 57, 51, 50, 49, 47, 46, 45,
-+ 41, 38, 22, 21, 19, 13, 9, 6, 4, 2,
-+
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165,
-+ 165, 165, 165, 165, 165, 165, 165, 165
- } ;
-
- static yy_state_type yy_last_accepting_state;
-@@ -631,13 +634,13 @@
-
-
-
--
--#line 38 "dtc-lexer.l"
-+#line 37 "dtc-lexer.l"
- #include "dtc.h"
- #include "srcpos.h"
- #include "dtc-parser.tab.h"
-
- YYLTYPE yylloc;
-+extern bool treesource_error;
-
- /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
- #define YY_USER_ACTION \
-@@ -659,14 +662,14 @@
- BEGIN(V1); \
-
- static void push_input_file(const char *filename);
--static int pop_input_file(void);
--#line 664 "dtc-lexer.lex.c"
-+static bool pop_input_file(void);
-+static void lexical_error(const char *fmt, ...);
-+#line 668 "dtc-lexer.lex.c"
-
- #define INITIAL 0
--#define INCLUDE 1
--#define BYTESTRING 2
--#define PROPNODENAME 3
--#define V1 4
-+#define BYTESTRING 1
-+#define PROPNODENAME 2
-+#define V1 3
-
- #ifndef YY_NO_UNISTD_H
- /* Special case for "unistd.h", since it is non-ANSI. We include it way
-@@ -852,9 +855,9 @@
- register char *yy_cp, *yy_bp;
- register int yy_act;
-
--#line 67 "dtc-lexer.l"
-+#line 68 "dtc-lexer.l"
-
--#line 858 "dtc-lexer.lex.c"
-+#line 861 "dtc-lexer.lex.c"
-
- if ( !(yy_init) )
- {
-@@ -908,13 +911,13 @@
- while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
- {
- yy_current_state = (int) yy_def[yy_current_state];
-- if ( yy_current_state >= 161 )
-+ if ( yy_current_state >= 166 )
- yy_c = yy_meta[(unsigned int) yy_c];
- }
- yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
- ++yy_cp;
- }
-- while ( yy_current_state != 160 );
-+ while ( yy_current_state != 165 );
- yy_cp = (yy_last_accepting_cpos);
- yy_current_state = (yy_last_accepting_state);
-
-@@ -937,7 +940,7 @@
- case 1:
- /* rule 1 can match eol */
- YY_RULE_SETUP
--#line 68 "dtc-lexer.l"
-+#line 69 "dtc-lexer.l"
- {
- char *name = strchr(yytext, '\"') + 1;
- yytext[yyleng-1] = '\0';
-@@ -947,16 +950,16 @@
- case 2:
- /* rule 2 can match eol */
- YY_RULE_SETUP
--#line 74 "dtc-lexer.l"
-+#line 75 "dtc-lexer.l"
- {
- char *line, *tmp, *fn;
- /* skip text before line # */
- line = yytext;
-- while (!isdigit(*line))
-+ while (!isdigit((unsigned char)*line))
- line++;
- /* skip digits in line # */
- tmp = line;
-- while (!isspace(*tmp))
-+ while (!isspace((unsigned char)*tmp))
- tmp++;
- /* "NULL"-terminate line # */
- *tmp = '\0';
-@@ -970,11 +973,10 @@
- }
- YY_BREAK
- case YY_STATE_EOF(INITIAL):
--case YY_STATE_EOF(INCLUDE):
- case YY_STATE_EOF(BYTESTRING):
- case YY_STATE_EOF(PROPNODENAME):
- case YY_STATE_EOF(V1):
--#line 95 "dtc-lexer.l"
-+#line 96 "dtc-lexer.l"
- {
- if (!pop_input_file()) {
- yyterminate();
-@@ -984,7 +986,7 @@
- case 3:
- /* rule 3 can match eol */
- YY_RULE_SETUP
--#line 101 "dtc-lexer.l"
-+#line 102 "dtc-lexer.l"
- {
- DPRINT("String: %s\n", yytext);
- yylval.data = data_copy_escape_string(yytext+1,
-@@ -994,7 +996,7 @@
- YY_BREAK
- case 4:
- YY_RULE_SETUP
--#line 108 "dtc-lexer.l"
-+#line 109 "dtc-lexer.l"
- {
- DPRINT("Keyword: /dts-v1/\n");
- dts_version = 1;
-@@ -1004,25 +1006,33 @@
- YY_BREAK
- case 5:
- YY_RULE_SETUP
--#line 115 "dtc-lexer.l"
-+#line 116 "dtc-lexer.l"
-+{
-+ DPRINT("Keyword: /plugin/\n");
-+ return DT_PLUGIN;
-+ }
-+ YY_BREAK
-+case 6:
-+YY_RULE_SETUP
-+#line 121 "dtc-lexer.l"
- {
- DPRINT("Keyword: /memreserve/\n");
- BEGIN_DEFAULT();
- return DT_MEMRESERVE;
- }
- YY_BREAK
--case 6:
-+case 7:
- YY_RULE_SETUP
--#line 121 "dtc-lexer.l"
-+#line 127 "dtc-lexer.l"
- {
- DPRINT("Keyword: /bits/\n");
- BEGIN_DEFAULT();
- return DT_BITS;
- }
- YY_BREAK
--case 7:
-+case 8:
- YY_RULE_SETUP
--#line 127 "dtc-lexer.l"
-+#line 133 "dtc-lexer.l"
- {
- DPRINT("Keyword: /delete-property/\n");
- DPRINT("<PROPNODENAME>\n");
-@@ -1030,9 +1040,9 @@
- return DT_DEL_PROP;
- }
- YY_BREAK
--case 8:
-+case 9:
- YY_RULE_SETUP
--#line 134 "dtc-lexer.l"
-+#line 140 "dtc-lexer.l"
- {
- DPRINT("Keyword: /delete-node/\n");
- DPRINT("<PROPNODENAME>\n");
-@@ -1040,9 +1050,9 @@
- return DT_DEL_NODE;
- }
- YY_BREAK
--case 9:
-+case 10:
- YY_RULE_SETUP
--#line 141 "dtc-lexer.l"
-+#line 147 "dtc-lexer.l"
- {
- DPRINT("Label: %s\n", yytext);
- yylval.labelref = xstrdup(yytext);
-@@ -1050,38 +1060,65 @@
- return DT_LABEL;
- }
- YY_BREAK
--case 10:
-+case 11:
- YY_RULE_SETUP
--#line 148 "dtc-lexer.l"
-+#line 154 "dtc-lexer.l"
- {
-- yylval.literal = xstrdup(yytext);
-- DPRINT("Literal: '%s'\n", yylval.literal);
-+ char *e;
-+ DPRINT("Integer Literal: '%s'\n", yytext);
-+
-+ errno = 0;
-+ yylval.integer = strtoull(yytext, &e, 0);
-+
-+ assert(!(*e) || !e[strspn(e, "UL")]);
-+
-+ if (errno == ERANGE)
-+ lexical_error("Integer literal '%s' out of range",
-+ yytext);
-+ else
-+ /* ERANGE is the only strtoull error triggerable
-+ * by strings matching the pattern */
-+ assert(errno == 0);
- return DT_LITERAL;
- }
- YY_BREAK
--case 11:
--/* rule 11 can match eol */
-+case 12:
-+/* rule 12 can match eol */
- YY_RULE_SETUP
--#line 154 "dtc-lexer.l"
-+#line 173 "dtc-lexer.l"
- {
-- yytext[yyleng-1] = '\0';
-- yylval.literal = xstrdup(yytext+1);
-- DPRINT("Character literal: %s\n", yylval.literal);
-+ struct data d;
-+ DPRINT("Character literal: %s\n", yytext);
-+
-+ d = data_copy_escape_string(yytext+1, yyleng-2);
-+ if (d.len == 1) {
-+ lexical_error("Empty character literal");
-+ yylval.integer = 0;
-+ return DT_CHAR_LITERAL;
-+ }
-+
-+ yylval.integer = (unsigned char)d.val[0];
-+
-+ if (d.len > 2)
-+ lexical_error("Character literal has %d"
-+ " characters instead of 1",
-+ d.len - 1);
-+
- return DT_CHAR_LITERAL;
- }
- YY_BREAK
--case 12:
-+case 13:
- YY_RULE_SETUP
--#line 161 "dtc-lexer.l"
-+#line 194 "dtc-lexer.l"
- { /* label reference */
- DPRINT("Ref: %s\n", yytext+1);
- yylval.labelref = xstrdup(yytext+1);
- return DT_REF;
- }
- YY_BREAK
--case 13:
-+case 14:
- YY_RULE_SETUP
--#line 167 "dtc-lexer.l"
-+#line 200 "dtc-lexer.l"
- { /* new-style path reference */
- yytext[yyleng-1] = '\0';
- DPRINT("Ref: %s\n", yytext+2);
-@@ -1089,27 +1126,27 @@
- return DT_REF;
- }
- YY_BREAK
--case 14:
-+case 15:
- YY_RULE_SETUP
--#line 174 "dtc-lexer.l"
-+#line 207 "dtc-lexer.l"
- {
- yylval.byte = strtol(yytext, NULL, 16);
- DPRINT("Byte: %02x\n", (int)yylval.byte);
- return DT_BYTE;
- }
- YY_BREAK
--case 15:
-+case 16:
- YY_RULE_SETUP
--#line 180 "dtc-lexer.l"
-+#line 213 "dtc-lexer.l"
- {
- DPRINT("/BYTESTRING\n");
- BEGIN_DEFAULT();
- return ']';
- }
- YY_BREAK
--case 16:
-+case 17:
- YY_RULE_SETUP
--#line 186 "dtc-lexer.l"
-+#line 219 "dtc-lexer.l"
- {
- DPRINT("PropNodeName: %s\n", yytext);
- yylval.propnodename = xstrdup((yytext[0] == '\\') ?
-@@ -1118,75 +1155,75 @@
- return DT_PROPNODENAME;
- }
- YY_BREAK
--case 17:
-+case 18:
- YY_RULE_SETUP
--#line 194 "dtc-lexer.l"
-+#line 227 "dtc-lexer.l"
- {
- DPRINT("Binary Include\n");
- return DT_INCBIN;
- }
- YY_BREAK
--case 18:
--/* rule 18 can match eol */
--YY_RULE_SETUP
--#line 199 "dtc-lexer.l"
--/* eat whitespace */
-- YY_BREAK
- case 19:
- /* rule 19 can match eol */
- YY_RULE_SETUP
--#line 200 "dtc-lexer.l"
--/* eat C-style comments */
-+#line 232 "dtc-lexer.l"
-+/* eat whitespace */
- YY_BREAK
- case 20:
- /* rule 20 can match eol */
- YY_RULE_SETUP
--#line 201 "dtc-lexer.l"
--/* eat C++-style comments */
-+#line 233 "dtc-lexer.l"
-+/* eat C-style comments */
- YY_BREAK
- case 21:
-+/* rule 21 can match eol */
- YY_RULE_SETUP
--#line 203 "dtc-lexer.l"
--{ return DT_LSHIFT; };
-+#line 234 "dtc-lexer.l"
-+/* eat C++-style comments */
- YY_BREAK
- case 22:
- YY_RULE_SETUP
--#line 204 "dtc-lexer.l"
--{ return DT_RSHIFT; };
-+#line 236 "dtc-lexer.l"
-+{ return DT_LSHIFT; };
- YY_BREAK
- case 23:
- YY_RULE_SETUP
--#line 205 "dtc-lexer.l"
--{ return DT_LE; };
-+#line 237 "dtc-lexer.l"
-+{ return DT_RSHIFT; };
- YY_BREAK
- case 24:
- YY_RULE_SETUP
--#line 206 "dtc-lexer.l"
--{ return DT_GE; };
-+#line 238 "dtc-lexer.l"
-+{ return DT_LE; };
- YY_BREAK
- case 25:
- YY_RULE_SETUP
--#line 207 "dtc-lexer.l"
--{ return DT_EQ; };
-+#line 239 "dtc-lexer.l"
-+{ return DT_GE; };
- YY_BREAK
- case 26:
- YY_RULE_SETUP
--#line 208 "dtc-lexer.l"
--{ return DT_NE; };
-+#line 240 "dtc-lexer.l"
-+{ return DT_EQ; };
- YY_BREAK
- case 27:
- YY_RULE_SETUP
--#line 209 "dtc-lexer.l"
--{ return DT_AND; };
-+#line 241 "dtc-lexer.l"
-+{ return DT_NE; };
- YY_BREAK
- case 28:
- YY_RULE_SETUP
--#line 210 "dtc-lexer.l"
--{ return DT_OR; };
-+#line 242 "dtc-lexer.l"
-+{ return DT_AND; };
- YY_BREAK
- case 29:
- YY_RULE_SETUP
--#line 212 "dtc-lexer.l"
-+#line 243 "dtc-lexer.l"
-+{ return DT_OR; };
-+ YY_BREAK
-+case 30:
-+YY_RULE_SETUP
-+#line 245 "dtc-lexer.l"
- {
- DPRINT("Char: %c (\\x%02x)\n", yytext[0],
- (unsigned)yytext[0]);
-@@ -1202,12 +1239,12 @@
- return yytext[0];
- }
- YY_BREAK
--case 30:
-+case 31:
- YY_RULE_SETUP
--#line 227 "dtc-lexer.l"
-+#line 260 "dtc-lexer.l"
- ECHO;
- YY_BREAK
--#line 1211 "dtc-lexer.lex.c"
-+#line 1248 "dtc-lexer.lex.c"
-
- case YY_END_OF_BUFFER:
- {
-@@ -1499,7 +1536,7 @@
- while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
- {
- yy_current_state = (int) yy_def[yy_current_state];
-- if ( yy_current_state >= 161 )
-+ if ( yy_current_state >= 166 )
- yy_c = yy_meta[(unsigned int) yy_c];
- }
- yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-@@ -1527,11 +1564,11 @@
- while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
- {
- yy_current_state = (int) yy_def[yy_current_state];
-- if ( yy_current_state >= 161 )
-+ if ( yy_current_state >= 166 )
- yy_c = yy_meta[(unsigned int) yy_c];
- }
- yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-- yy_is_jam = (yy_current_state == 160);
-+ yy_is_jam = (yy_current_state == 165);
-
- return yy_is_jam ? 0 : yy_current_state;
- }
-@@ -2166,7 +2203,7 @@
-
- #define YYTABLES_NAME "yytables"
-
--#line 227 "dtc-lexer.l"
-+#line 260 "dtc-lexer.l"
-
-
-
-@@ -2182,14 +2219,25 @@
- }
-
-
--static int pop_input_file(void)
-+static bool pop_input_file(void)
- {
- if (srcfile_pop() == 0)
-- return 0;
-+ return false;
-
- yypop_buffer_state();
- yyin = current_srcfile->f;
-
-- return 1;
-+ return true;
-+}
-+
-+static void lexical_error(const char *fmt, ...)
-+{
-+ va_list ap;
-+
-+ va_start(ap, fmt);
-+ srcpos_verror(&yylloc, "Lexical error", fmt, ap);
-+ va_end(ap);
-+
-+ treesource_error = true;
- }
-
-diff -Nur linux-3.18.14/scripts/dtc/dtc-parser.tab.c_shipped linux-rpi/scripts/dtc/dtc-parser.tab.c_shipped
---- linux-3.18.14/scripts/dtc/dtc-parser.tab.c_shipped 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc-parser.tab.c_shipped 2015-05-31 14:46:14.189660949 -0500
-@@ -1,19 +1,19 @@
--/* A Bison parser, made by GNU Bison 2.7.12-4996. */
-+/* A Bison parser, made by GNU Bison 3.0.2. */
-
- /* Bison implementation for Yacc-like parsers in C
--
-- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
--
-+
-+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
-+
- This program is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 3 of the License, or
- (at your option) any later version.
--
-+
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
--
-+
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-@@ -26,7 +26,7 @@
- special exception, which will cause the skeleton and the resulting
- Bison output files to be licensed under the GNU General Public
- License without this special exception.
--
-+
- This special exception was added by the Free Software Foundation in
- version 2.2 of Bison. */
-
-@@ -44,7 +44,7 @@
- #define YYBISON 1
-
- /* Bison version. */
--#define YYBISON_VERSION "2.7.12-4996"
-+#define YYBISON_VERSION "3.0.2"
-
- /* Skeleton name. */
- #define YYSKELETON_NAME "yacc.c"
-@@ -62,34 +62,32 @@
-
-
- /* Copy the first part of user declarations. */
--/* Line 371 of yacc.c */
--#line 21 "dtc-parser.y"
-+#line 20 "dtc-parser.y" /* yacc.c:339 */
-
- #include <stdio.h>
-+#include <inttypes.h>
-
- #include "dtc.h"
- #include "srcpos.h"
-
--YYLTYPE yylloc;
--
- extern int yylex(void);
--extern void print_error(char const *fmt, ...);
- extern void yyerror(char const *s);
-+#define ERROR(loc, ...) \
-+ do { \
-+ srcpos_error((loc), "Error", __VA_ARGS__); \
-+ treesource_error = true; \
-+ } while (0)
-
- extern struct boot_info *the_boot_info;
--extern int treesource_error;
--
--static unsigned long long eval_literal(const char *s, int base, int bits);
--static unsigned char eval_char_literal(const char *s);
-+extern bool treesource_error;
-
--/* Line 371 of yacc.c */
--#line 87 "dtc-parser.tab.c"
-+#line 85 "dtc-parser.tab.c" /* yacc.c:339 */
-
--# ifndef YY_NULL
-+# ifndef YY_NULLPTR
- # if defined __cplusplus && 201103L <= __cplusplus
--# define YY_NULL nullptr
-+# define YY_NULLPTR nullptr
- # else
--# define YY_NULL 0
-+# define YY_NULLPTR 0
- # endif
- # endif
-
-@@ -105,7 +103,7 @@
- by #include "dtc-parser.tab.h". */
- #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED
- # define YY_YY_DTC_PARSER_TAB_H_INCLUDED
--/* Enabling traces. */
-+/* Debug traces. */
- #ifndef YYDEBUG
- # define YYDEBUG 0
- #endif
-@@ -113,48 +111,45 @@
- extern int yydebug;
- #endif
-
--/* Tokens. */
-+/* Token type. */
- #ifndef YYTOKENTYPE
- # define YYTOKENTYPE
-- /* Put the tokens into the symbol table, so that GDB and other debuggers
-- know about them. */
-- enum yytokentype {
-- DT_V1 = 258,
-- DT_MEMRESERVE = 259,
-- DT_LSHIFT = 260,
-- DT_RSHIFT = 261,
-- DT_LE = 262,
-- DT_GE = 263,
-- DT_EQ = 264,
-- DT_NE = 265,
-- DT_AND = 266,
-- DT_OR = 267,
-- DT_BITS = 268,
-- DT_DEL_PROP = 269,
-- DT_DEL_NODE = 270,
-- DT_PROPNODENAME = 271,
-- DT_LITERAL = 272,
-- DT_CHAR_LITERAL = 273,
-- DT_BASE = 274,
-- DT_BYTE = 275,
-- DT_STRING = 276,
-- DT_LABEL = 277,
-- DT_REF = 278,
-- DT_INCBIN = 279
-- };
-+ enum yytokentype
-+ {
-+ DT_V1 = 258,
-+ DT_PLUGIN = 259,
-+ DT_MEMRESERVE = 260,
-+ DT_LSHIFT = 261,
-+ DT_RSHIFT = 262,
-+ DT_LE = 263,
-+ DT_GE = 264,
-+ DT_EQ = 265,
-+ DT_NE = 266,
-+ DT_AND = 267,
-+ DT_OR = 268,
-+ DT_BITS = 269,
-+ DT_DEL_PROP = 270,
-+ DT_DEL_NODE = 271,
-+ DT_PROPNODENAME = 272,
-+ DT_LITERAL = 273,
-+ DT_CHAR_LITERAL = 274,
-+ DT_BYTE = 275,
-+ DT_STRING = 276,
-+ DT_LABEL = 277,
-+ DT_REF = 278,
-+ DT_INCBIN = 279
-+ };
- #endif
-
--
-+/* Value type. */
- #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
--typedef union YYSTYPE
-+typedef union YYSTYPE YYSTYPE;
-+union YYSTYPE
- {
--/* Line 387 of yacc.c */
--#line 40 "dtc-parser.y"
-+#line 39 "dtc-parser.y" /* yacc.c:355 */
-
- char *propnodename;
-- char *literal;
- char *labelref;
-- unsigned int cbase;
- uint8_t byte;
- struct data data;
-
-@@ -169,38 +164,38 @@
- struct node *nodelist;
- struct reserve_info *re;
- uint64_t integer;
-+ int is_plugin;
-
--
--/* Line 387 of yacc.c */
--#line 176 "dtc-parser.tab.c"
--} YYSTYPE;
-+#line 170 "dtc-parser.tab.c" /* yacc.c:355 */
-+};
- # define YYSTYPE_IS_TRIVIAL 1
--# define yystype YYSTYPE /* obsolescent; will be withdrawn */
- # define YYSTYPE_IS_DECLARED 1
- #endif
-
--extern YYSTYPE yylval;
--
--#ifdef YYPARSE_PARAM
--#if defined __STDC__ || defined __cplusplus
--int yyparse (void *YYPARSE_PARAM);
--#else
--int yyparse ();
-+/* Location type. */
-+#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED
-+typedef struct YYLTYPE YYLTYPE;
-+struct YYLTYPE
-+{
-+ int first_line;
-+ int first_column;
-+ int last_line;
-+ int last_column;
-+};
-+# define YYLTYPE_IS_DECLARED 1
-+# define YYLTYPE_IS_TRIVIAL 1
- #endif
--#else /* ! YYPARSE_PARAM */
--#if defined __STDC__ || defined __cplusplus
-+
-+
-+extern YYSTYPE yylval;
-+extern YYLTYPE yylloc;
- int yyparse (void);
--#else
--int yyparse ();
--#endif
--#endif /* ! YYPARSE_PARAM */
-
- #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */
-
- /* Copy the second part of user declarations. */
-
--/* Line 390 of yacc.c */
--#line 204 "dtc-parser.tab.c"
-+#line 199 "dtc-parser.tab.c" /* yacc.c:358 */
-
- #ifdef short
- # undef short
-@@ -214,11 +209,8 @@
-
- #ifdef YYTYPE_INT8
- typedef YYTYPE_INT8 yytype_int8;
--#elif (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--typedef signed char yytype_int8;
- #else
--typedef short int yytype_int8;
-+typedef signed char yytype_int8;
- #endif
-
- #ifdef YYTYPE_UINT16
-@@ -238,8 +230,7 @@
- # define YYSIZE_T __SIZE_TYPE__
- # elif defined size_t
- # define YYSIZE_T size_t
--# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
-+# elif ! defined YYSIZE_T
- # include <stddef.h> /* INFRINGES ON USER NAME SPACE */
- # define YYSIZE_T size_t
- # else
-@@ -261,11 +252,30 @@
- # endif
- #endif
-
--#ifndef __attribute__
--/* This feature is available in gcc versions 2.5 and later. */
--# if (! defined __GNUC__ || __GNUC__ < 2 \
-- || (__GNUC__ == 2 && __GNUC_MINOR__ < 5))
--# define __attribute__(Spec) /* empty */
-+#ifndef YY_ATTRIBUTE
-+# if (defined __GNUC__ \
-+ && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \
-+ || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C
-+# define YY_ATTRIBUTE(Spec) __attribute__(Spec)
-+# else
-+# define YY_ATTRIBUTE(Spec) /* empty */
-+# endif
-+#endif
-+
-+#ifndef YY_ATTRIBUTE_PURE
-+# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__))
-+#endif
-+
-+#ifndef YY_ATTRIBUTE_UNUSED
-+# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__))
-+#endif
-+
-+#if !defined _Noreturn \
-+ && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112)
-+# if defined _MSC_VER && 1200 <= _MSC_VER
-+# define _Noreturn __declspec (noreturn)
-+# else
-+# define _Noreturn YY_ATTRIBUTE ((__noreturn__))
- # endif
- #endif
-
-@@ -276,24 +286,25 @@
- # define YYUSE(E) /* empty */
- #endif
-
--
--/* Identity function, used to suppress warnings about constant conditions. */
--#ifndef lint
--# define YYID(N) (N)
--#else
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--static int
--YYID (int yyi)
-+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
-+/* Suppress an incorrect diagnostic about yylval being uninitialized. */
-+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
-+ _Pragma ("GCC diagnostic push") \
-+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\
-+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"")
-+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \
-+ _Pragma ("GCC diagnostic pop")
- #else
--static int
--YYID (yyi)
-- int yyi;
-+# define YY_INITIAL_VALUE(Value) Value
- #endif
--{
-- return yyi;
--}
-+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
-+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
-+# define YY_IGNORE_MAYBE_UNINITIALIZED_END
- #endif
-+#ifndef YY_INITIAL_VALUE
-+# define YY_INITIAL_VALUE(Value) /* Nothing. */
-+#endif
-+
-
- #if ! defined yyoverflow || YYERROR_VERBOSE
-
-@@ -312,8 +323,7 @@
- # define alloca _alloca
- # else
- # define YYSTACK_ALLOC alloca
--# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
-+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS
- # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
- /* Use EXIT_SUCCESS as a witness for stdlib.h. */
- # ifndef EXIT_SUCCESS
-@@ -325,8 +335,8 @@
- # endif
-
- # ifdef YYSTACK_ALLOC
-- /* Pacify GCC's `empty if-body' warning. */
--# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
-+ /* Pacify GCC's 'empty if-body' warning. */
-+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
- # ifndef YYSTACK_ALLOC_MAXIMUM
- /* The OS might guarantee only one guard page at the bottom of the stack,
- and a page size can be as small as 4096 bytes. So we cannot safely
-@@ -342,7 +352,7 @@
- # endif
- # if (defined __cplusplus && ! defined EXIT_SUCCESS \
- && ! ((defined YYMALLOC || defined malloc) \
-- && (defined YYFREE || defined free)))
-+ && (defined YYFREE || defined free)))
- # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
- # ifndef EXIT_SUCCESS
- # define EXIT_SUCCESS 0
-@@ -350,15 +360,13 @@
- # endif
- # ifndef YYMALLOC
- # define YYMALLOC malloc
--# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
-+# if ! defined malloc && ! defined EXIT_SUCCESS
- void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
- # endif
- # endif
- # ifndef YYFREE
- # define YYFREE free
--# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
-+# if ! defined free && ! defined EXIT_SUCCESS
- void free (void *); /* INFRINGES ON USER NAME SPACE */
- # endif
- # endif
-@@ -368,13 +376,15 @@
-
- #if (! defined yyoverflow \
- && (! defined __cplusplus \
-- || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
-+ || (defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL \
-+ && defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
-
- /* A type that is properly aligned for any stack member. */
- union yyalloc
- {
- yytype_int16 yyss_alloc;
- YYSTYPE yyvs_alloc;
-+ YYLTYPE yyls_alloc;
- };
-
- /* The size of the maximum gap between one aligned stack and the next. */
-@@ -383,8 +393,8 @@
- /* The size of an array large to enough to hold all stacks, each with
- N elements. */
- # define YYSTACK_BYTES(N) \
-- ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
-- + YYSTACK_GAP_MAXIMUM)
-+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE) + sizeof (YYLTYPE)) \
-+ + 2 * YYSTACK_GAP_MAXIMUM)
-
- # define YYCOPY_NEEDED 1
-
-@@ -393,16 +403,16 @@
- elements in the stack, and YYPTR gives the new location of the
- stack. Advance YYPTR to a properly aligned location for the next
- stack. */
--# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
-- do \
-- { \
-- YYSIZE_T yynewbytes; \
-- YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
-- Stack = &yyptr->Stack_alloc; \
-- yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-- yyptr += yynewbytes / sizeof (*yyptr); \
-- } \
-- while (YYID (0))
-+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
-+ do \
-+ { \
-+ YYSIZE_T yynewbytes; \
-+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
-+ Stack = &yyptr->Stack_alloc; \
-+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-+ yyptr += yynewbytes / sizeof (*yyptr); \
-+ } \
-+ while (0)
-
- #endif
-
-@@ -421,7 +431,7 @@
- for (yyi = 0; yyi < (Count); yyi++) \
- (Dst)[yyi] = (Src)[yyi]; \
- } \
-- while (YYID (0))
-+ while (0)
- # endif
- # endif
- #endif /* !YYCOPY_NEEDED */
-@@ -429,25 +439,27 @@
- /* YYFINAL -- State number of the termination state. */
- #define YYFINAL 4
- /* YYLAST -- Last index in YYTABLE. */
--#define YYLAST 133
-+#define YYLAST 135
-
- /* YYNTOKENS -- Number of terminals. */
- #define YYNTOKENS 48
- /* YYNNTS -- Number of nonterminals. */
--#define YYNNTS 28
-+#define YYNNTS 29
- /* YYNRULES -- Number of rules. */
--#define YYNRULES 79
--/* YYNRULES -- Number of states. */
--#define YYNSTATES 141
-+#define YYNRULES 81
-+/* YYNSTATES -- Number of states. */
-+#define YYNSTATES 144
-
--/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */
-+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
-+ by yylex, with out-of-bounds checking. */
- #define YYUNDEFTOK 2
- #define YYMAXUTOK 279
-
--#define YYTRANSLATE(YYX) \
-+#define YYTRANSLATE(YYX) \
- ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
-
--/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */
-+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
-+ as returned by yylex, without out-of-bounds checking. */
- static const yytype_uint8 yytranslate[] =
- {
- 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-@@ -481,63 +493,18 @@
- };
-
- #if YYDEBUG
--/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
-- YYRHS. */
--static const yytype_uint16 yyprhs[] =
--{
-- 0, 0, 3, 8, 9, 12, 17, 20, 23, 27,
-- 31, 36, 42, 43, 46, 51, 54, 58, 61, 64,
-- 68, 73, 76, 86, 92, 95, 96, 99, 102, 106,
-- 108, 111, 114, 117, 119, 121, 125, 127, 129, 135,
-- 137, 141, 143, 147, 149, 153, 155, 159, 161, 165,
-- 167, 171, 175, 177, 181, 185, 189, 193, 197, 201,
-- 203, 207, 211, 213, 217, 221, 225, 227, 229, 232,
-- 235, 238, 239, 242, 245, 246, 249, 252, 255, 259
--};
--
--/* YYRHS -- A `-1'-separated list of the rules' RHS. */
--static const yytype_int8 yyrhs[] =
--{
-- 49, 0, -1, 3, 25, 50, 52, -1, -1, 51,
-- 50, -1, 4, 59, 59, 25, -1, 22, 51, -1,
-- 26, 53, -1, 52, 26, 53, -1, 52, 23, 53,
-- -1, 52, 15, 23, 25, -1, 27, 54, 74, 28,
-- 25, -1, -1, 54, 55, -1, 16, 29, 56, 25,
-- -1, 16, 25, -1, 14, 16, 25, -1, 22, 55,
-- -1, 57, 21, -1, 57, 58, 30, -1, 57, 31,
-- 73, 32, -1, 57, 23, -1, 57, 24, 33, 21,
-- 34, 59, 34, 59, 35, -1, 57, 24, 33, 21,
-- 35, -1, 56, 22, -1, -1, 56, 34, -1, 57,
-- 22, -1, 13, 17, 36, -1, 36, -1, 58, 59,
-- -1, 58, 23, -1, 58, 22, -1, 17, -1, 18,
-- -1, 33, 60, 35, -1, 61, -1, 62, -1, 62,
-- 37, 60, 38, 61, -1, 63, -1, 62, 12, 63,
-- -1, 64, -1, 63, 11, 64, -1, 65, -1, 64,
-- 39, 65, -1, 66, -1, 65, 40, 66, -1, 67,
-- -1, 66, 41, 67, -1, 68, -1, 67, 9, 68,
-- -1, 67, 10, 68, -1, 69, -1, 68, 36, 69,
-- -1, 68, 30, 69, -1, 68, 7, 69, -1, 68,
-- 8, 69, -1, 69, 5, 70, -1, 69, 6, 70,
-- -1, 70, -1, 70, 42, 71, -1, 70, 43, 71,
-- -1, 71, -1, 71, 44, 72, -1, 71, 26, 72,
-- -1, 71, 45, 72, -1, 72, -1, 59, -1, 43,
-- 72, -1, 46, 72, -1, 47, 72, -1, -1, 73,
-- 20, -1, 73, 22, -1, -1, 75, 74, -1, 75,
-- 55, -1, 16, 53, -1, 15, 16, 25, -1, 22,
-- 75, -1
--};
--
--/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
-+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */
- static const yytype_uint16 yyrline[] =
- {
-- 0, 109, 109, 118, 121, 128, 132, 140, 144, 148,
-- 158, 172, 180, 183, 190, 194, 198, 202, 210, 214,
-- 218, 222, 226, 243, 253, 261, 264, 268, 275, 290,
-- 295, 315, 329, 336, 340, 344, 351, 355, 356, 360,
-- 361, 365, 366, 370, 371, 375, 376, 380, 381, 385,
-- 386, 387, 391, 392, 393, 394, 395, 399, 400, 401,
-- 405, 406, 407, 411, 412, 413, 414, 418, 419, 420,
-- 421, 426, 429, 433, 441, 444, 448, 456, 460, 464
-+ 0, 108, 108, 119, 122, 130, 133, 140, 144, 152,
-+ 156, 160, 170, 185, 193, 196, 203, 207, 211, 215,
-+ 223, 227, 231, 235, 239, 255, 265, 273, 276, 280,
-+ 287, 303, 308, 327, 341, 348, 349, 350, 357, 361,
-+ 362, 366, 367, 371, 372, 376, 377, 381, 382, 386,
-+ 387, 391, 392, 393, 397, 398, 399, 400, 401, 405,
-+ 406, 407, 411, 412, 413, 417, 418, 419, 420, 424,
-+ 425, 426, 427, 432, 435, 439, 447, 450, 454, 462,
-+ 466, 470
- };
- #endif
-
-@@ -546,25 +513,25 @@
- First, the terminals, then, starting at YYNTOKENS, nonterminals. */
- static const char *const yytname[] =
- {
-- "$end", "error", "$undefined", "DT_V1", "DT_MEMRESERVE", "DT_LSHIFT",
-- "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", "DT_OR",
-- "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", "DT_LITERAL",
-- "DT_CHAR_LITERAL", "DT_BASE", "DT_BYTE", "DT_STRING", "DT_LABEL",
-+ "$end", "error", "$undefined", "DT_V1", "DT_PLUGIN", "DT_MEMRESERVE",
-+ "DT_LSHIFT", "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND",
-+ "DT_OR", "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME",
-+ "DT_LITERAL", "DT_CHAR_LITERAL", "DT_BYTE", "DT_STRING", "DT_LABEL",
- "DT_REF", "DT_INCBIN", "';'", "'/'", "'{'", "'}'", "'='", "'>'", "'['",
- "']'", "'('", "','", "')'", "'<'", "'?'", "':'", "'|'", "'^'", "'&'",
- "'+'", "'-'", "'*'", "'%'", "'~'", "'!'", "$accept", "sourcefile",
-- "memreserves", "memreserve", "devicetree", "nodedef", "proplist",
-- "propdef", "propdata", "propdataprefix", "arrayprefix", "integer_prim",
-- "integer_expr", "integer_trinary", "integer_or", "integer_and",
-- "integer_bitor", "integer_bitxor", "integer_bitand", "integer_eq",
-- "integer_rela", "integer_shift", "integer_add", "integer_mul",
-- "integer_unary", "bytestring", "subnodes", "subnode", YY_NULL
-+ "plugindecl", "memreserves", "memreserve", "devicetree", "nodedef",
-+ "proplist", "propdef", "propdata", "propdataprefix", "arrayprefix",
-+ "integer_prim", "integer_expr", "integer_trinary", "integer_or",
-+ "integer_and", "integer_bitor", "integer_bitxor", "integer_bitand",
-+ "integer_eq", "integer_rela", "integer_shift", "integer_add",
-+ "integer_mul", "integer_unary", "bytestring", "subnodes", "subnode", YY_NULLPTR
- };
- #endif
-
- # ifdef YYPRINT
--/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
-- token YYLEX-NUM. */
-+/* YYTOKNUM[NUM] -- (External) token number corresponding to the
-+ (internal) symbol number NUM (which must be that of a token). */
- static const yytype_uint16 yytoknum[] =
- {
- 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
-@@ -575,183 +542,173 @@
- };
- # endif
-
--/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
--static const yytype_uint8 yyr1[] =
--{
-- 0, 48, 49, 50, 50, 51, 51, 52, 52, 52,
-- 52, 53, 54, 54, 55, 55, 55, 55, 56, 56,
-- 56, 56, 56, 56, 56, 57, 57, 57, 58, 58,
-- 58, 58, 58, 59, 59, 59, 60, 61, 61, 62,
-- 62, 63, 63, 64, 64, 65, 65, 66, 66, 67,
-- 67, 67, 68, 68, 68, 68, 68, 69, 69, 69,
-- 70, 70, 70, 71, 71, 71, 71, 72, 72, 72,
-- 72, 73, 73, 73, 74, 74, 74, 75, 75, 75
--};
-+#define YYPACT_NINF -41
-
--/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
--static const yytype_uint8 yyr2[] =
-+#define yypact_value_is_default(Yystate) \
-+ (!!((Yystate) == (-41)))
-+
-+#define YYTABLE_NINF -1
-+
-+#define yytable_value_is_error(Yytable_value) \
-+ 0
-+
-+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-+ STATE-NUM. */
-+static const yytype_int8 yypact[] =
- {
-- 0, 2, 4, 0, 2, 4, 2, 2, 3, 3,
-- 4, 5, 0, 2, 4, 2, 3, 2, 2, 3,
-- 4, 2, 9, 5, 2, 0, 2, 2, 3, 1,
-- 2, 2, 2, 1, 1, 3, 1, 1, 5, 1,
-- 3, 1, 3, 1, 3, 1, 3, 1, 3, 1,
-- 3, 3, 1, 3, 3, 3, 3, 3, 3, 1,
-- 3, 3, 1, 3, 3, 3, 1, 1, 2, 2,
-- 2, 0, 2, 2, 0, 2, 2, 2, 3, 2
-+ 37, 10, 24, 78, -41, 20, 9, -41, 8, 9,
-+ 59, 9, -41, -41, -10, 8, -41, 60, 39, -41,
-+ -10, -10, -10, -41, 51, -41, -7, 76, 50, 52,
-+ 53, 49, 2, 65, 32, -1, -41, 66, -41, -41,
-+ 67, 60, 60, -41, -41, -41, -41, -10, -10, -10,
-+ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10,
-+ -10, -10, -10, -10, -10, -10, -41, 41, 68, -41,
-+ -41, 76, 57, 50, 52, 53, 49, 2, 2, 65,
-+ 65, 65, 65, 32, 32, -1, -1, -41, -41, -41,
-+ 79, 80, -12, 41, -41, 70, 41, -41, -10, 74,
-+ 75, -41, -41, -41, -41, -41, 77, -41, -41, -41,
-+ -41, -41, 17, -2, -41, -41, -41, -41, 83, -41,
-+ -41, -41, 71, -41, -41, 31, 69, 82, -4, -41,
-+ -41, -41, -41, -41, 42, -41, -41, -41, 8, -41,
-+ 72, 8, 73, -41
- };
-
--/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM.
-- Performed when YYTABLE doesn't specify something else to do. Zero
-- means the default is an error. */
-+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
-+ Performed when YYTABLE does not specify something else to do. Zero
-+ means the default is an error. */
- static const yytype_uint8 yydefact[] =
- {
-- 0, 0, 0, 3, 1, 0, 0, 0, 3, 33,
-- 34, 0, 0, 6, 0, 2, 4, 0, 0, 0,
-- 67, 0, 36, 37, 39, 41, 43, 45, 47, 49,
-- 52, 59, 62, 66, 0, 12, 7, 0, 0, 0,
-- 68, 69, 70, 35, 0, 0, 0, 0, 0, 0,
-+ 0, 0, 0, 3, 1, 0, 5, 4, 0, 0,
-+ 0, 5, 35, 36, 0, 0, 8, 0, 2, 6,
-+ 0, 0, 0, 69, 0, 38, 39, 41, 43, 45,
-+ 47, 49, 51, 54, 61, 64, 68, 0, 14, 9,
-+ 0, 0, 0, 70, 71, 72, 37, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-- 0, 0, 0, 5, 74, 0, 9, 8, 40, 0,
-- 42, 44, 46, 48, 50, 51, 55, 56, 54, 53,
-- 57, 58, 60, 61, 64, 63, 65, 0, 0, 0,
-- 0, 13, 0, 74, 10, 0, 0, 0, 15, 25,
-- 77, 17, 79, 0, 76, 75, 38, 16, 78, 0,
-- 0, 11, 24, 14, 26, 0, 18, 27, 21, 0,
-- 71, 29, 0, 0, 0, 0, 32, 31, 19, 30,
-- 28, 0, 72, 73, 20, 0, 23, 0, 0, 0,
-- 22
-+ 0, 0, 0, 0, 0, 0, 7, 76, 0, 11,
-+ 10, 42, 0, 44, 46, 48, 50, 52, 53, 57,
-+ 58, 56, 55, 59, 60, 62, 63, 66, 65, 67,
-+ 0, 0, 0, 0, 15, 0, 76, 12, 0, 0,
-+ 0, 17, 27, 79, 19, 81, 0, 78, 77, 40,
-+ 18, 80, 0, 0, 13, 26, 16, 28, 0, 20,
-+ 29, 23, 0, 73, 31, 0, 0, 0, 0, 34,
-+ 33, 21, 32, 30, 0, 74, 75, 22, 0, 25,
-+ 0, 0, 0, 24
- };
-
--/* YYDEFGOTO[NTERM-NUM]. */
--static const yytype_int8 yydefgoto[] =
-+ /* YYPGOTO[NTERM-NUM]. */
-+static const yytype_int8 yypgoto[] =
- {
-- -1, 2, 7, 8, 15, 36, 64, 91, 109, 110,
-- 122, 20, 21, 22, 23, 24, 25, 26, 27, 28,
-- 29, 30, 31, 32, 33, 125, 92, 93
-+ -41, -41, -41, 96, 100, -41, -40, -41, -23, -41,
-+ -41, -41, -8, 62, 13, -41, 81, 63, 64, 84,
-+ 61, 25, 11, 21, 22, -17, -41, 19, 23
- };
-
--/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-- STATE-NUM. */
--#define YYPACT_NINF -78
--static const yytype_int8 yypact[] =
-+ /* YYDEFGOTO[NTERM-NUM]. */
-+static const yytype_int16 yydefgoto[] =
- {
-- 22, 11, 51, 10, -78, 23, 10, 2, 10, -78,
-- -78, -9, 23, -78, 30, 38, -78, -9, -9, -9,
-- -78, 35, -78, -6, 52, 29, 48, 49, 33, 3,
-- 71, 36, 0, -78, 64, -78, -78, 68, 30, 30,
-- -78, -78, -78, -78, -9, -9, -9, -9, -9, -9,
-- -9, -9, -9, -9, -9, -9, -9, -9, -9, -9,
-- -9, -9, -9, -78, 44, 67, -78, -78, 52, 55,
-- 29, 48, 49, 33, 3, 3, 71, 71, 71, 71,
-- 36, 36, 0, 0, -78, -78, -78, 78, 79, 42,
-- 44, -78, 69, 44, -78, -9, 73, 74, -78, -78,
-- -78, -78, -78, 75, -78, -78, -78, -78, -78, -7,
-- -1, -78, -78, -78, -78, 84, -78, -78, -78, 63,
-- -78, -78, 32, 66, 82, -3, -78, -78, -78, -78,
-- -78, 46, -78, -78, -78, 23, -78, 70, 23, 72,
-- -78
-+ -1, 2, 6, 10, 11, 18, 39, 67, 94, 112,
-+ 113, 125, 23, 24, 25, 26, 27, 28, 29, 30,
-+ 31, 32, 33, 34, 35, 36, 128, 95, 96
- };
-
--/* YYPGOTO[NTERM-NUM]. */
--static const yytype_int8 yypgoto[] =
-+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
-+ positive, shift that token. If negative, reduce the rule whose
-+ number is the opposite. If YYTABLE_NINF, syntax error. */
-+static const yytype_uint8 yytable[] =
- {
-- -78, -78, 97, 100, -78, -37, -78, -77, -78, -78,
-- -78, -5, 65, 13, -78, 76, 77, 62, 80, 83,
-- 34, 20, 26, 28, -14, -78, 18, 24
-+ 15, 69, 70, 43, 44, 45, 47, 37, 12, 13,
-+ 55, 56, 118, 101, 8, 38, 135, 102, 136, 119,
-+ 120, 121, 122, 14, 4, 63, 12, 13, 137, 123,
-+ 48, 9, 57, 20, 124, 3, 21, 22, 58, 115,
-+ 1, 14, 116, 64, 65, 7, 87, 88, 89, 12,
-+ 13, 117, 103, 129, 130, 40, 90, 91, 92, 53,
-+ 54, 131, 41, 93, 14, 42, 79, 80, 81, 82,
-+ 104, 59, 60, 107, 61, 62, 138, 139, 77, 78,
-+ 83, 84, 5, 85, 86, 17, 46, 38, 49, 50,
-+ 68, 66, 51, 97, 52, 98, 99, 100, 106, 110,
-+ 111, 126, 114, 134, 127, 133, 141, 19, 143, 16,
-+ 72, 109, 73, 76, 74, 108, 105, 132, 0, 0,
-+ 0, 0, 0, 0, 0, 0, 0, 0, 71, 0,
-+ 140, 0, 0, 142, 0, 75
- };
-
--/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If
-- positive, shift that token. If negative, reduce the rule which
-- number is the opposite. If YYTABLE_NINF, syntax error. */
--#define YYTABLE_NINF -1
--static const yytype_uint8 yytable[] =
-+static const yytype_int16 yycheck[] =
- {
-- 12, 66, 67, 40, 41, 42, 44, 34, 9, 10,
-- 52, 53, 115, 101, 5, 112, 104, 132, 113, 133,
-- 116, 117, 118, 119, 11, 1, 60, 114, 14, 134,
-- 120, 45, 6, 54, 17, 121, 3, 18, 19, 55,
-- 9, 10, 50, 51, 61, 62, 84, 85, 86, 9,
-- 10, 4, 100, 37, 126, 127, 11, 35, 87, 88,
-- 89, 38, 128, 46, 39, 11, 90, 98, 47, 35,
-- 43, 99, 76, 77, 78, 79, 56, 57, 58, 59,
-- 135, 136, 80, 81, 74, 75, 82, 83, 48, 63,
-- 49, 65, 94, 95, 96, 97, 124, 103, 107, 108,
-- 111, 123, 130, 131, 138, 16, 13, 140, 106, 71,
-- 69, 105, 0, 0, 102, 0, 0, 129, 0, 0,
-- 68, 0, 0, 70, 0, 0, 0, 0, 72, 0,
-- 137, 0, 73, 139
-+ 8, 41, 42, 20, 21, 22, 13, 15, 18, 19,
-+ 8, 9, 14, 25, 5, 27, 20, 29, 22, 21,
-+ 22, 23, 24, 33, 0, 26, 18, 19, 32, 31,
-+ 37, 22, 30, 43, 36, 25, 46, 47, 36, 22,
-+ 3, 33, 25, 44, 45, 25, 63, 64, 65, 18,
-+ 19, 34, 92, 22, 23, 16, 15, 16, 17, 10,
-+ 11, 30, 23, 22, 33, 26, 55, 56, 57, 58,
-+ 93, 6, 7, 96, 42, 43, 34, 35, 53, 54,
-+ 59, 60, 4, 61, 62, 26, 35, 27, 12, 39,
-+ 23, 25, 40, 25, 41, 38, 17, 17, 28, 25,
-+ 25, 18, 25, 21, 33, 36, 34, 11, 35, 9,
-+ 48, 98, 49, 52, 50, 96, 93, 125, -1, -1,
-+ -1, -1, -1, -1, -1, -1, -1, -1, 47, -1,
-+ 138, -1, -1, 141, -1, 51
- };
-
--#define yypact_value_is_default(Yystate) \
-- (!!((Yystate) == (-78)))
--
--#define yytable_value_is_error(Yytable_value) \
-- YYID (0)
-+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-+ symbol of state STATE-NUM. */
-+static const yytype_uint8 yystos[] =
-+{
-+ 0, 3, 49, 25, 0, 4, 50, 25, 5, 22,
-+ 51, 52, 18, 19, 33, 60, 52, 26, 53, 51,
-+ 43, 46, 47, 60, 61, 62, 63, 64, 65, 66,
-+ 67, 68, 69, 70, 71, 72, 73, 60, 27, 54,
-+ 16, 23, 26, 73, 73, 73, 35, 13, 37, 12,
-+ 39, 40, 41, 10, 11, 8, 9, 30, 36, 6,
-+ 7, 42, 43, 26, 44, 45, 25, 55, 23, 54,
-+ 54, 64, 61, 65, 66, 67, 68, 69, 69, 70,
-+ 70, 70, 70, 71, 71, 72, 72, 73, 73, 73,
-+ 15, 16, 17, 22, 56, 75, 76, 25, 38, 17,
-+ 17, 25, 29, 54, 56, 76, 28, 56, 75, 62,
-+ 25, 25, 57, 58, 25, 22, 25, 34, 14, 21,
-+ 22, 23, 24, 31, 36, 59, 18, 33, 74, 22,
-+ 23, 30, 60, 36, 21, 20, 22, 32, 34, 35,
-+ 60, 34, 60, 35
-+};
-
--static const yytype_int16 yycheck[] =
-+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
-+static const yytype_uint8 yyr1[] =
- {
-- 5, 38, 39, 17, 18, 19, 12, 12, 17, 18,
-- 7, 8, 13, 90, 4, 22, 93, 20, 25, 22,
-- 21, 22, 23, 24, 33, 3, 26, 34, 26, 32,
-- 31, 37, 22, 30, 43, 36, 25, 46, 47, 36,
-- 17, 18, 9, 10, 44, 45, 60, 61, 62, 17,
-- 18, 0, 89, 15, 22, 23, 33, 27, 14, 15,
-- 16, 23, 30, 11, 26, 33, 22, 25, 39, 27,
-- 35, 29, 52, 53, 54, 55, 5, 6, 42, 43,
-- 34, 35, 56, 57, 50, 51, 58, 59, 40, 25,
-- 41, 23, 25, 38, 16, 16, 33, 28, 25, 25,
-- 25, 17, 36, 21, 34, 8, 6, 35, 95, 47,
-- 45, 93, -1, -1, 90, -1, -1, 122, -1, -1,
-- 44, -1, -1, 46, -1, -1, -1, -1, 48, -1,
-- 135, -1, 49, 138
-+ 0, 48, 49, 50, 50, 51, 51, 52, 52, 53,
-+ 53, 53, 53, 54, 55, 55, 56, 56, 56, 56,
-+ 57, 57, 57, 57, 57, 57, 57, 58, 58, 58,
-+ 59, 59, 59, 59, 59, 60, 60, 60, 61, 62,
-+ 62, 63, 63, 64, 64, 65, 65, 66, 66, 67,
-+ 67, 68, 68, 68, 69, 69, 69, 69, 69, 70,
-+ 70, 70, 71, 71, 71, 72, 72, 72, 72, 73,
-+ 73, 73, 73, 74, 74, 74, 75, 75, 75, 76,
-+ 76, 76
- };
-
--/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-- symbol of state STATE-NUM. */
--static const yytype_uint8 yystos[] =
-+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
-+static const yytype_uint8 yyr2[] =
- {
-- 0, 3, 49, 25, 0, 4, 22, 50, 51, 17,
-- 18, 33, 59, 51, 26, 52, 50, 43, 46, 47,
-- 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
-- 69, 70, 71, 72, 59, 27, 53, 15, 23, 26,
-- 72, 72, 72, 35, 12, 37, 11, 39, 40, 41,
-- 9, 10, 7, 8, 30, 36, 5, 6, 42, 43,
-- 26, 44, 45, 25, 54, 23, 53, 53, 63, 60,
-- 64, 65, 66, 67, 68, 68, 69, 69, 69, 69,
-- 70, 70, 71, 71, 72, 72, 72, 14, 15, 16,
-- 22, 55, 74, 75, 25, 38, 16, 16, 25, 29,
-- 53, 55, 75, 28, 55, 74, 61, 25, 25, 56,
-- 57, 25, 22, 25, 34, 13, 21, 22, 23, 24,
-- 31, 36, 58, 17, 33, 73, 22, 23, 30, 59,
-- 36, 21, 20, 22, 32, 34, 35, 59, 34, 59,
-- 35
-+ 0, 2, 5, 0, 2, 0, 2, 4, 2, 2,
-+ 3, 3, 4, 5, 0, 2, 4, 2, 3, 2,
-+ 2, 3, 4, 2, 9, 5, 2, 0, 2, 2,
-+ 3, 1, 2, 2, 2, 1, 1, 3, 1, 1,
-+ 5, 1, 3, 1, 3, 1, 3, 1, 3, 1,
-+ 3, 1, 3, 3, 1, 3, 3, 3, 3, 3,
-+ 3, 1, 3, 3, 1, 3, 3, 3, 1, 1,
-+ 2, 2, 2, 0, 2, 2, 0, 2, 2, 2,
-+ 3, 2
- };
-
--#define yyerrok (yyerrstatus = 0)
--#define yyclearin (yychar = YYEMPTY)
--#define YYEMPTY (-2)
--#define YYEOF 0
--
--#define YYACCEPT goto yyacceptlab
--#define YYABORT goto yyabortlab
--#define YYERROR goto yyerrorlab
--
--
--/* Like YYERROR except do call yyerror. This remains here temporarily
-- to ease the transition to the new meaning of YYERROR, for GCC.
-- Once GCC version 2 has supplanted version 1, this can go. However,
-- YYFAIL appears to be in use. Nevertheless, it is formally deprecated
-- in Bison 2.4.2's NEWS entry, where a plan to phase it out is
-- discussed. */
--
--#define YYFAIL goto yyerrlab
--#if defined YYFAIL
-- /* This is here to suppress warnings from the GCC cpp's
-- -Wunused-macros. Normally we don't worry about that warning, but
-- some users do, and we want to make it easy for users to remove
-- YYFAIL uses, which will produce warnings from Bison 2.5. */
--#endif
-+
-+#define yyerrok (yyerrstatus = 0)
-+#define yyclearin (yychar = YYEMPTY)
-+#define YYEMPTY (-2)
-+#define YYEOF 0
-+
-+#define YYACCEPT goto yyacceptlab
-+#define YYABORT goto yyabortlab
-+#define YYERROR goto yyerrorlab
-+
-
- #define YYRECOVERING() (!!yyerrstatus)
-
-@@ -768,27 +725,41 @@
- else \
- { \
- yyerror (YY_("syntax error: cannot back up")); \
-- YYERROR; \
-- } \
--while (YYID (0))
-+ YYERROR; \
-+ } \
-+while (0)
-
- /* Error token number */
--#define YYTERROR 1
--#define YYERRCODE 256
-+#define YYTERROR 1
-+#define YYERRCODE 256
-
-
--/* This macro is provided for backward compatibility. */
--#ifndef YY_LOCATION_PRINT
--# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
-+ If N is 0, then set CURRENT to the empty location which ends
-+ the previous symbol: RHS[0] (always defined). */
-+
-+#ifndef YYLLOC_DEFAULT
-+# define YYLLOC_DEFAULT(Current, Rhs, N) \
-+ do \
-+ if (N) \
-+ { \
-+ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
-+ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
-+ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
-+ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
-+ } \
-+ else \
-+ { \
-+ (Current).first_line = (Current).last_line = \
-+ YYRHSLOC (Rhs, 0).last_line; \
-+ (Current).first_column = (Current).last_column = \
-+ YYRHSLOC (Rhs, 0).last_column; \
-+ } \
-+ while (0)
- #endif
-
-+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
-
--/* YYLEX -- calling `yylex' with the right arguments. */
--#ifdef YYLEX_PARAM
--# define YYLEX yylex (YYLEX_PARAM)
--#else
--# define YYLEX yylex ()
--#endif
-
- /* Enable debugging if requested. */
- #if YYDEBUG
-@@ -798,50 +769,84 @@
- # define YYFPRINTF fprintf
- # endif
-
--# define YYDPRINTF(Args) \
--do { \
-- if (yydebug) \
-- YYFPRINTF Args; \
--} while (YYID (0))
--
--# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
--do { \
-- if (yydebug) \
-- { \
-- YYFPRINTF (stderr, "%s ", Title); \
-- yy_symbol_print (stderr, \
-- Type, Value); \
-- YYFPRINTF (stderr, "\n"); \
-- } \
--} while (YYID (0))
-+# define YYDPRINTF(Args) \
-+do { \
-+ if (yydebug) \
-+ YYFPRINTF Args; \
-+} while (0)
-
-
--/*--------------------------------.
--| Print this symbol on YYOUTPUT. |
--`--------------------------------*/
-+/* YY_LOCATION_PRINT -- Print the location on the stream.
-+ This macro was not mandated originally: define only if we know
-+ we won't break user code: when these are the locations we know. */
-
--/*ARGSUSED*/
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--static void
--yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
--#else
--static void
--yy_symbol_value_print (yyoutput, yytype, yyvaluep)
-- FILE *yyoutput;
-- int yytype;
-- YYSTYPE const * const yyvaluep;
-+#ifndef YY_LOCATION_PRINT
-+# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL
-+
-+/* Print *YYLOCP on YYO. Private, do not rely on its existence. */
-+
-+YY_ATTRIBUTE_UNUSED
-+static unsigned
-+yy_location_print_ (FILE *yyo, YYLTYPE const * const yylocp)
-+{
-+ unsigned res = 0;
-+ int end_col = 0 != yylocp->last_column ? yylocp->last_column - 1 : 0;
-+ if (0 <= yylocp->first_line)
-+ {
-+ res += YYFPRINTF (yyo, "%d", yylocp->first_line);
-+ if (0 <= yylocp->first_column)
-+ res += YYFPRINTF (yyo, ".%d", yylocp->first_column);
-+ }
-+ if (0 <= yylocp->last_line)
-+ {
-+ if (yylocp->first_line < yylocp->last_line)
-+ {
-+ res += YYFPRINTF (yyo, "-%d", yylocp->last_line);
-+ if (0 <= end_col)
-+ res += YYFPRINTF (yyo, ".%d", end_col);
-+ }
-+ else if (0 <= end_col && yylocp->first_column < end_col)
-+ res += YYFPRINTF (yyo, "-%d", end_col);
-+ }
-+ return res;
-+ }
-+
-+# define YY_LOCATION_PRINT(File, Loc) \
-+ yy_location_print_ (File, &(Loc))
-+
-+# else
-+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-+# endif
- #endif
-+
-+
-+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
-+do { \
-+ if (yydebug) \
-+ { \
-+ YYFPRINTF (stderr, "%s ", Title); \
-+ yy_symbol_print (stderr, \
-+ Type, Value, Location); \
-+ YYFPRINTF (stderr, "\n"); \
-+ } \
-+} while (0)
-+
-+
-+/*----------------------------------------.
-+| Print this symbol's value on YYOUTPUT. |
-+`----------------------------------------*/
-+
-+static void
-+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp)
- {
- FILE *yyo = yyoutput;
- YYUSE (yyo);
-+ YYUSE (yylocationp);
- if (!yyvaluep)
- return;
- # ifdef YYPRINT
- if (yytype < YYNTOKENS)
- YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
--# else
-- YYUSE (yyoutput);
- # endif
- YYUSE (yytype);
- }
-@@ -851,24 +856,15 @@
- | Print this symbol on YYOUTPUT. |
- `--------------------------------*/
-
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--static void
--yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
--#else
- static void
--yy_symbol_print (yyoutput, yytype, yyvaluep)
-- FILE *yyoutput;
-- int yytype;
-- YYSTYPE const * const yyvaluep;
--#endif
-+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp)
- {
-- if (yytype < YYNTOKENS)
-- YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
-- else
-- YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
-+ YYFPRINTF (yyoutput, "%s %s (",
-+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
-
-- yy_symbol_value_print (yyoutput, yytype, yyvaluep);
-+ YY_LOCATION_PRINT (yyoutput, *yylocationp);
-+ YYFPRINTF (yyoutput, ": ");
-+ yy_symbol_value_print (yyoutput, yytype, yyvaluep, yylocationp);
- YYFPRINTF (yyoutput, ")");
- }
-
-@@ -877,16 +873,8 @@
- | TOP (included). |
- `------------------------------------------------------------------*/
-
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
- static void
- yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
--#else
--static void
--yy_stack_print (yybottom, yytop)
-- yytype_int16 *yybottom;
-- yytype_int16 *yytop;
--#endif
- {
- YYFPRINTF (stderr, "Stack now");
- for (; yybottom <= yytop; yybottom++)
-@@ -897,49 +885,42 @@
- YYFPRINTF (stderr, "\n");
- }
-
--# define YY_STACK_PRINT(Bottom, Top) \
--do { \
-- if (yydebug) \
-- yy_stack_print ((Bottom), (Top)); \
--} while (YYID (0))
-+# define YY_STACK_PRINT(Bottom, Top) \
-+do { \
-+ if (yydebug) \
-+ yy_stack_print ((Bottom), (Top)); \
-+} while (0)
-
-
- /*------------------------------------------------.
- | Report that the YYRULE is going to be reduced. |
- `------------------------------------------------*/
-
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--static void
--yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
--#else
- static void
--yy_reduce_print (yyvsp, yyrule)
-- YYSTYPE *yyvsp;
-- int yyrule;
--#endif
-+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, YYLTYPE *yylsp, int yyrule)
- {
-+ unsigned long int yylno = yyrline[yyrule];
- int yynrhs = yyr2[yyrule];
- int yyi;
-- unsigned long int yylno = yyrline[yyrule];
- YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
-- yyrule - 1, yylno);
-+ yyrule - 1, yylno);
- /* The symbols being reduced. */
- for (yyi = 0; yyi < yynrhs; yyi++)
- {
- YYFPRINTF (stderr, " $%d = ", yyi + 1);
-- yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
-- &(yyvsp[(yyi + 1) - (yynrhs)])
-- );
-+ yy_symbol_print (stderr,
-+ yystos[yyssp[yyi + 1 - yynrhs]],
-+ &(yyvsp[(yyi + 1) - (yynrhs)])
-+ , &(yylsp[(yyi + 1) - (yynrhs)]) );
- YYFPRINTF (stderr, "\n");
- }
- }
-
--# define YY_REDUCE_PRINT(Rule) \
--do { \
-- if (yydebug) \
-- yy_reduce_print (yyvsp, Rule); \
--} while (YYID (0))
-+# define YY_REDUCE_PRINT(Rule) \
-+do { \
-+ if (yydebug) \
-+ yy_reduce_print (yyssp, yyvsp, yylsp, Rule); \
-+} while (0)
-
- /* Nonzero means print parse trace. It is left uninitialized so that
- multiple parsers can coexist. */
-@@ -953,7 +934,7 @@
-
-
- /* YYINITDEPTH -- initial size of the parser's stacks. */
--#ifndef YYINITDEPTH
-+#ifndef YYINITDEPTH
- # define YYINITDEPTH 200
- #endif
-
-@@ -976,15 +957,8 @@
- # define yystrlen strlen
- # else
- /* Return the length of YYSTR. */
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
- static YYSIZE_T
- yystrlen (const char *yystr)
--#else
--static YYSIZE_T
--yystrlen (yystr)
-- const char *yystr;
--#endif
- {
- YYSIZE_T yylen;
- for (yylen = 0; yystr[yylen]; yylen++)
-@@ -1000,16 +974,8 @@
- # else
- /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
- YYDEST. */
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
- static char *
- yystpcpy (char *yydest, const char *yysrc)
--#else
--static char *
--yystpcpy (yydest, yysrc)
-- char *yydest;
-- const char *yysrc;
--#endif
- {
- char *yyd = yydest;
- const char *yys = yysrc;
-@@ -1039,27 +1005,27 @@
- char const *yyp = yystr;
-
- for (;;)
-- switch (*++yyp)
-- {
-- case '\'':
-- case ',':
-- goto do_not_strip_quotes;
--
-- case '\\':
-- if (*++yyp != '\\')
-- goto do_not_strip_quotes;
-- /* Fall through. */
-- default:
-- if (yyres)
-- yyres[yyn] = *yyp;
-- yyn++;
-- break;
--
-- case '"':
-- if (yyres)
-- yyres[yyn] = '\0';
-- return yyn;
-- }
-+ switch (*++yyp)
-+ {
-+ case '\'':
-+ case ',':
-+ goto do_not_strip_quotes;
-+
-+ case '\\':
-+ if (*++yyp != '\\')
-+ goto do_not_strip_quotes;
-+ /* Fall through. */
-+ default:
-+ if (yyres)
-+ yyres[yyn] = *yyp;
-+ yyn++;
-+ break;
-+
-+ case '"':
-+ if (yyres)
-+ yyres[yyn] = '\0';
-+ return yyn;
-+ }
- do_not_strip_quotes: ;
- }
-
-@@ -1082,11 +1048,11 @@
- yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
- yytype_int16 *yyssp, int yytoken)
- {
-- YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]);
-+ YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]);
- YYSIZE_T yysize = yysize0;
- enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
- /* Internationalized format string. */
-- const char *yyformat = YY_NULL;
-+ const char *yyformat = YY_NULLPTR;
- /* Arguments of yyformat. */
- char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
- /* Number of reported tokens (one for the "unexpected", one per
-@@ -1094,10 +1060,6 @@
- int yycount = 0;
-
- /* There are many possibilities here to consider:
-- - Assume YYFAIL is not used. It's too flawed to consider. See
-- <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html>
-- for details. YYERROR is fine as it does not invoke this
-- function.
- - If this state is a consistent state with a default action, then
- the only way this function was invoked is if the default action
- is an error action. In that case, don't check for expected
-@@ -1147,7 +1109,7 @@
- }
- yyarg[yycount++] = yytname[yyx];
- {
-- YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]);
-+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);
- if (! (yysize <= yysize1
- && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
- return 2;
-@@ -1214,26 +1176,18 @@
- | Release the memory associated to this symbol. |
- `-----------------------------------------------*/
-
--/*ARGSUSED*/
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--static void
--yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
--#else
- static void
--yydestruct (yymsg, yytype, yyvaluep)
-- const char *yymsg;
-- int yytype;
-- YYSTYPE *yyvaluep;
--#endif
-+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp)
- {
- YYUSE (yyvaluep);
--
-+ YYUSE (yylocationp);
- if (!yymsg)
- yymsg = "Deleting";
- YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
-
-+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
- YYUSE (yytype);
-+ YY_IGNORE_MAYBE_UNINITIALIZED_END
- }
-
-
-@@ -1242,18 +1196,14 @@
- /* The lookahead symbol. */
- int yychar;
-
--
--#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
--# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
--# define YY_IGNORE_MAYBE_UNINITIALIZED_END
--#endif
--#ifndef YY_INITIAL_VALUE
--# define YY_INITIAL_VALUE(Value) /* Nothing. */
--#endif
--
- /* The semantic value of the lookahead symbol. */
--YYSTYPE yylval YY_INITIAL_VALUE(yyval_default);
--
-+YYSTYPE yylval;
-+/* Location data for the lookahead symbol. */
-+YYLTYPE yylloc
-+# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL
-+ = { 1, 1, 1, 1 }
-+# endif
-+;
- /* Number of syntax errors so far. */
- int yynerrs;
-
-@@ -1262,35 +1212,17 @@
- | yyparse. |
- `----------*/
-
--#ifdef YYPARSE_PARAM
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
--int
--yyparse (void *YYPARSE_PARAM)
--#else
--int
--yyparse (YYPARSE_PARAM)
-- void *YYPARSE_PARAM;
--#endif
--#else /* ! YYPARSE_PARAM */
--#if (defined __STDC__ || defined __C99__FUNC__ \
-- || defined __cplusplus || defined _MSC_VER)
- int
- yyparse (void)
--#else
--int
--yyparse ()
--
--#endif
--#endif
- {
- int yystate;
- /* Number of tokens to shift before error messages enabled. */
- int yyerrstatus;
-
- /* The stacks and their tools:
-- `yyss': related to states.
-- `yyvs': related to semantic values.
-+ 'yyss': related to states.
-+ 'yyvs': related to semantic values.
-+ 'yyls': related to locations.
-
- Refer to the stacks through separate pointers, to allow yyoverflow
- to reallocate them elsewhere. */
-@@ -1305,6 +1237,14 @@
- YYSTYPE *yyvs;
- YYSTYPE *yyvsp;
-
-+ /* The location stack. */
-+ YYLTYPE yylsa[YYINITDEPTH];
-+ YYLTYPE *yyls;
-+ YYLTYPE *yylsp;
-+
-+ /* The locations where the error started and ended. */
-+ YYLTYPE yyerror_range[3];
-+
- YYSIZE_T yystacksize;
-
- int yyn;
-@@ -1314,6 +1254,7 @@
- /* The variables used to return semantic value and location from the
- action routines. */
- YYSTYPE yyval;
-+ YYLTYPE yyloc;
-
- #if YYERROR_VERBOSE
- /* Buffer for error messages, and its allocated size. */
-@@ -1322,7 +1263,7 @@
- YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
- #endif
-
--#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
-+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N), yylsp -= (N))
-
- /* The number of symbols on the RHS of the reduced rule.
- Keep to zero when no symbol should be popped. */
-@@ -1330,6 +1271,7 @@
-
- yyssp = yyss = yyssa;
- yyvsp = yyvs = yyvsa;
-+ yylsp = yyls = yylsa;
- yystacksize = YYINITDEPTH;
-
- YYDPRINTF ((stderr, "Starting parse\n"));
-@@ -1338,6 +1280,7 @@
- yyerrstatus = 0;
- yynerrs = 0;
- yychar = YYEMPTY; /* Cause a token to be read. */
-+ yylsp[0] = yylloc;
- goto yysetstate;
-
- /*------------------------------------------------------------.
-@@ -1358,23 +1301,26 @@
-
- #ifdef yyoverflow
- {
-- /* Give user a chance to reallocate the stack. Use copies of
-- these so that the &'s don't force the real ones into
-- memory. */
-- YYSTYPE *yyvs1 = yyvs;
-- yytype_int16 *yyss1 = yyss;
--
-- /* Each stack pointer address is followed by the size of the
-- data in use in that stack, in bytes. This used to be a
-- conditional around just the two extra args, but that might
-- be undefined if yyoverflow is a macro. */
-- yyoverflow (YY_("memory exhausted"),
-- &yyss1, yysize * sizeof (*yyssp),
-- &yyvs1, yysize * sizeof (*yyvsp),
-- &yystacksize);
--
-- yyss = yyss1;
-- yyvs = yyvs1;
-+ /* Give user a chance to reallocate the stack. Use copies of
-+ these so that the &'s don't force the real ones into
-+ memory. */
-+ YYSTYPE *yyvs1 = yyvs;
-+ yytype_int16 *yyss1 = yyss;
-+ YYLTYPE *yyls1 = yyls;
-+
-+ /* Each stack pointer address is followed by the size of the
-+ data in use in that stack, in bytes. This used to be a
-+ conditional around just the two extra args, but that might
-+ be undefined if yyoverflow is a macro. */
-+ yyoverflow (YY_("memory exhausted"),
-+ &yyss1, yysize * sizeof (*yyssp),
-+ &yyvs1, yysize * sizeof (*yyvsp),
-+ &yyls1, yysize * sizeof (*yylsp),
-+ &yystacksize);
-+
-+ yyls = yyls1;
-+ yyss = yyss1;
-+ yyvs = yyvs1;
- }
- #else /* no yyoverflow */
- # ifndef YYSTACK_RELOCATE
-@@ -1382,34 +1328,36 @@
- # else
- /* Extend the stack our own way. */
- if (YYMAXDEPTH <= yystacksize)
-- goto yyexhaustedlab;
-+ goto yyexhaustedlab;
- yystacksize *= 2;
- if (YYMAXDEPTH < yystacksize)
-- yystacksize = YYMAXDEPTH;
-+ yystacksize = YYMAXDEPTH;
-
- {
-- yytype_int16 *yyss1 = yyss;
-- union yyalloc *yyptr =
-- (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-- if (! yyptr)
-- goto yyexhaustedlab;
-- YYSTACK_RELOCATE (yyss_alloc, yyss);
-- YYSTACK_RELOCATE (yyvs_alloc, yyvs);
-+ yytype_int16 *yyss1 = yyss;
-+ union yyalloc *yyptr =
-+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-+ if (! yyptr)
-+ goto yyexhaustedlab;
-+ YYSTACK_RELOCATE (yyss_alloc, yyss);
-+ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
-+ YYSTACK_RELOCATE (yyls_alloc, yyls);
- # undef YYSTACK_RELOCATE
-- if (yyss1 != yyssa)
-- YYSTACK_FREE (yyss1);
-+ if (yyss1 != yyssa)
-+ YYSTACK_FREE (yyss1);
- }
- # endif
- #endif /* no yyoverflow */
-
- yyssp = yyss + yysize - 1;
- yyvsp = yyvs + yysize - 1;
-+ yylsp = yyls + yysize - 1;
-
- YYDPRINTF ((stderr, "Stack size increased to %lu\n",
-- (unsigned long int) yystacksize));
-+ (unsigned long int) yystacksize));
-
- if (yyss + yystacksize - 1 <= yyssp)
-- YYABORT;
-+ YYABORT;
- }
-
- YYDPRINTF ((stderr, "Entering state %d\n", yystate));
-@@ -1438,7 +1386,7 @@
- if (yychar == YYEMPTY)
- {
- YYDPRINTF ((stderr, "Reading a token: "));
-- yychar = YYLEX;
-+ yychar = yylex ();
- }
-
- if (yychar <= YYEOF)
-@@ -1481,7 +1429,7 @@
- YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN
- *++yyvsp = yylval;
- YY_IGNORE_MAYBE_UNINITIALIZED_END
--
-+ *++yylsp = yylloc;
- goto yynewstate;
-
-
-@@ -1503,7 +1451,7 @@
- yylen = yyr2[yyn];
-
- /* If YYLEN is nonzero, implement the default value of the action:
-- `$$ = $1'.
-+ '$$ = $1'.
-
- Otherwise, the following line sets YYVAL to garbage.
- This behavior is undocumented and Bison
-@@ -1512,287 +1460,306 @@
- GCC warning that YYVAL may be used uninitialized. */
- yyval = yyvsp[1-yylen];
-
--
-+ /* Default location. */
-+ YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen);
- YY_REDUCE_PRINT (yyn);
- switch (yyn)
- {
- case 2:
--/* Line 1787 of yacc.c */
--#line 110 "dtc-parser.y"
-+#line 109 "dtc-parser.y" /* yacc.c:1646 */
- {
-- the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node),
-- guess_boot_cpuid((yyvsp[(4) - (4)].node)));
-+ (yyvsp[0].node)->is_plugin = (yyvsp[-2].is_plugin);
-+ (yyvsp[0].node)->is_root = 1;
-+ the_boot_info = build_boot_info((yyvsp[-1].re), (yyvsp[0].node),
-+ guess_boot_cpuid((yyvsp[0].node)));
- }
-+#line 1477 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 3:
--/* Line 1787 of yacc.c */
--#line 118 "dtc-parser.y"
-+#line 119 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.re) = NULL;
-+ (yyval.is_plugin) = 0;
- }
-+#line 1485 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 4:
--/* Line 1787 of yacc.c */
--#line 122 "dtc-parser.y"
-+#line 123 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re));
-+ (yyval.is_plugin) = 1;
- }
-+#line 1493 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 5:
--/* Line 1787 of yacc.c */
--#line 129 "dtc-parser.y"
-+#line 130 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer));
-+ (yyval.re) = NULL;
- }
-+#line 1501 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 6:
--/* Line 1787 of yacc.c */
--#line 133 "dtc-parser.y"
-+#line 134 "dtc-parser.y" /* yacc.c:1646 */
- {
-- add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref));
-- (yyval.re) = (yyvsp[(2) - (2)].re);
-+ (yyval.re) = chain_reserve_entry((yyvsp[-1].re), (yyvsp[0].re));
- }
-+#line 1509 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 7:
--/* Line 1787 of yacc.c */
--#line 141 "dtc-parser.y"
-+#line 141 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.node) = name_node((yyvsp[(2) - (2)].node), "");
-+ (yyval.re) = build_reserve_entry((yyvsp[-2].integer), (yyvsp[-1].integer));
- }
-+#line 1517 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 8:
--/* Line 1787 of yacc.c */
--#line 145 "dtc-parser.y"
-+#line 145 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node));
-+ add_label(&(yyvsp[0].re)->labels, (yyvsp[-1].labelref));
-+ (yyval.re) = (yyvsp[0].re);
- }
-+#line 1526 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 9:
--/* Line 1787 of yacc.c */
--#line 149 "dtc-parser.y"
-+#line 153 "dtc-parser.y" /* yacc.c:1646 */
- {
-- struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref));
--
-- if (target)
-- merge_nodes(target, (yyvsp[(3) - (3)].node));
-- else
-- print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref));
-- (yyval.node) = (yyvsp[(1) - (3)].node);
-+ (yyval.node) = name_node((yyvsp[0].node), "");
- }
-+#line 1534 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 10:
--/* Line 1787 of yacc.c */
--#line 159 "dtc-parser.y"
-+#line 157 "dtc-parser.y" /* yacc.c:1646 */
- {
-- struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref));
--
-- if (!target)
-- print_error("label or path, '%s', not found", (yyvsp[(3) - (4)].labelref));
-- else
-- delete_node(target);
--
-- (yyval.node) = (yyvsp[(1) - (4)].node);
-+ (yyval.node) = merge_nodes((yyvsp[-2].node), (yyvsp[0].node));
- }
-+#line 1542 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 11:
--/* Line 1787 of yacc.c */
--#line 173 "dtc-parser.y"
-+#line 161 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist));
-+ struct node *target = get_node_by_ref((yyvsp[-2].node), (yyvsp[-1].labelref));
-+
-+ if (target)
-+ merge_nodes(target, (yyvsp[0].node));
-+ else
-+ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref));
-+ (yyval.node) = (yyvsp[-2].node);
- }
-+#line 1556 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 12:
--/* Line 1787 of yacc.c */
--#line 180 "dtc-parser.y"
-+#line 171 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.proplist) = NULL;
-+ struct node *target = get_node_by_ref((yyvsp[-3].node), (yyvsp[-1].labelref));
-+
-+ if (target)
-+ delete_node(target);
-+ else
-+ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref));
-+
-+
-+ (yyval.node) = (yyvsp[-3].node);
- }
-+#line 1572 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 13:
--/* Line 1787 of yacc.c */
--#line 184 "dtc-parser.y"
-+#line 186 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist));
-+ (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist));
- }
-+#line 1580 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 14:
--/* Line 1787 of yacc.c */
--#line 191 "dtc-parser.y"
-+#line 193 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data));
-+ (yyval.proplist) = NULL;
- }
-+#line 1588 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 15:
--/* Line 1787 of yacc.c */
--#line 195 "dtc-parser.y"
-+#line 197 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data);
-+ (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist));
- }
-+#line 1596 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 16:
--/* Line 1787 of yacc.c */
--#line 199 "dtc-parser.y"
-+#line 204 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename));
-+ (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data));
- }
-+#line 1604 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 17:
--/* Line 1787 of yacc.c */
--#line 203 "dtc-parser.y"
-+#line 208 "dtc-parser.y" /* yacc.c:1646 */
- {
-- add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref));
-- (yyval.prop) = (yyvsp[(2) - (2)].prop);
-+ (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data);
- }
-+#line 1612 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 18:
--/* Line 1787 of yacc.c */
--#line 211 "dtc-parser.y"
-+#line 212 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data));
-+ (yyval.prop) = build_property_delete((yyvsp[-1].propnodename));
- }
-+#line 1620 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 19:
--/* Line 1787 of yacc.c */
--#line 215 "dtc-parser.y"
-+#line 216 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data);
-+ add_label(&(yyvsp[0].prop)->labels, (yyvsp[-1].labelref));
-+ (yyval.prop) = (yyvsp[0].prop);
- }
-+#line 1629 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 20:
--/* Line 1787 of yacc.c */
--#line 219 "dtc-parser.y"
-+#line 224 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data));
-+ (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data));
- }
-+#line 1637 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 21:
--/* Line 1787 of yacc.c */
--#line 223 "dtc-parser.y"
-+#line 228 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref));
-+ (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data);
- }
-+#line 1645 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 22:
--/* Line 1787 of yacc.c */
--#line 227 "dtc-parser.y"
-+#line 232 "dtc-parser.y" /* yacc.c:1646 */
- {
-- FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL);
-+ (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data));
-+ }
-+#line 1653 "dtc-parser.tab.c" /* yacc.c:1646 */
-+ break;
-+
-+ case 23:
-+#line 236 "dtc-parser.y" /* yacc.c:1646 */
-+ {
-+ (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref));
-+ }
-+#line 1661 "dtc-parser.tab.c" /* yacc.c:1646 */
-+ break;
-+
-+ case 24:
-+#line 240 "dtc-parser.y" /* yacc.c:1646 */
-+ {
-+ FILE *f = srcfile_relative_open((yyvsp[-5].data).val, NULL);
- struct data d;
-
-- if ((yyvsp[(6) - (9)].integer) != 0)
-- if (fseek(f, (yyvsp[(6) - (9)].integer), SEEK_SET) != 0)
-- print_error("Couldn't seek to offset %llu in \"%s\": %s",
-- (unsigned long long)(yyvsp[(6) - (9)].integer),
-- (yyvsp[(4) - (9)].data).val,
-- strerror(errno));
-+ if ((yyvsp[-3].integer) != 0)
-+ if (fseek(f, (yyvsp[-3].integer), SEEK_SET) != 0)
-+ die("Couldn't seek to offset %llu in \"%s\": %s",
-+ (unsigned long long)(yyvsp[-3].integer), (yyvsp[-5].data).val,
-+ strerror(errno));
-
-- d = data_copy_file(f, (yyvsp[(8) - (9)].integer));
-+ d = data_copy_file(f, (yyvsp[-1].integer));
-
-- (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d);
-+ (yyval.data) = data_merge((yyvsp[-8].data), d);
- fclose(f);
- }
-+#line 1681 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 23:
--/* Line 1787 of yacc.c */
--#line 244 "dtc-parser.y"
-+ case 25:
-+#line 256 "dtc-parser.y" /* yacc.c:1646 */
- {
-- FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL);
-+ FILE *f = srcfile_relative_open((yyvsp[-1].data).val, NULL);
- struct data d = empty_data;
-
- d = data_copy_file(f, -1);
-
-- (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d);
-+ (yyval.data) = data_merge((yyvsp[-4].data), d);
- fclose(f);
- }
-+#line 1695 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 24:
--/* Line 1787 of yacc.c */
--#line 254 "dtc-parser.y"
-+ case 26:
-+#line 266 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-+ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref));
- }
-+#line 1703 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 25:
--/* Line 1787 of yacc.c */
--#line 261 "dtc-parser.y"
-+ case 27:
-+#line 273 "dtc-parser.y" /* yacc.c:1646 */
- {
- (yyval.data) = empty_data;
- }
-+#line 1711 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 26:
--/* Line 1787 of yacc.c */
--#line 265 "dtc-parser.y"
-+ case 28:
-+#line 277 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = (yyvsp[(1) - (2)].data);
-+ (yyval.data) = (yyvsp[-1].data);
- }
-+#line 1719 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 27:
--/* Line 1787 of yacc.c */
--#line 269 "dtc-parser.y"
-+ case 29:
-+#line 281 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-+ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref));
- }
-+#line 1727 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 28:
--/* Line 1787 of yacc.c */
--#line 276 "dtc-parser.y"
-+ case 30:
-+#line 288 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.array).data = empty_data;
-- (yyval.array).bits = eval_literal((yyvsp[(2) - (3)].literal), 0, 7);
-+ unsigned long long bits;
-
-- if (((yyval.array).bits != 8) &&
-- ((yyval.array).bits != 16) &&
-- ((yyval.array).bits != 32) &&
-- ((yyval.array).bits != 64))
-- {
-- print_error("Only 8, 16, 32 and 64-bit elements"
-- " are currently supported");
-- (yyval.array).bits = 32;
-+ bits = (yyvsp[-1].integer);
-+
-+ if ((bits != 8) && (bits != 16) &&
-+ (bits != 32) && (bits != 64)) {
-+ ERROR(&(yylsp[-1]), "Array elements must be"
-+ " 8, 16, 32 or 64-bits");
-+ bits = 32;
- }
-+
-+ (yyval.array).data = empty_data;
-+ (yyval.array).bits = bits;
- }
-+#line 1747 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 29:
--/* Line 1787 of yacc.c */
--#line 291 "dtc-parser.y"
-+ case 31:
-+#line 304 "dtc-parser.y" /* yacc.c:1646 */
- {
- (yyval.array).data = empty_data;
- (yyval.array).bits = 32;
- }
-+#line 1756 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 30:
--/* Line 1787 of yacc.c */
--#line 296 "dtc-parser.y"
-+ case 32:
-+#line 309 "dtc-parser.y" /* yacc.c:1646 */
- {
-- if ((yyvsp[(1) - (2)].array).bits < 64) {
-- uint64_t mask = (1ULL << (yyvsp[(1) - (2)].array).bits) - 1;
-+ if ((yyvsp[-1].array).bits < 64) {
-+ uint64_t mask = (1ULL << (yyvsp[-1].array).bits) - 1;
- /*
- * Bits above mask must either be all zero
- * (positive within range of mask) or all one
-@@ -1801,275 +1768,258 @@
- * within the mask to one (i.e. | in the
- * mask), all bits are one.
- */
-- if (((yyvsp[(2) - (2)].integer) > mask) && (((yyvsp[(2) - (2)].integer) | mask) != -1ULL))
-- print_error(
-- "integer value out of range "
-- "%016lx (%d bits)", (yyvsp[(1) - (2)].array).bits);
-+ if (((yyvsp[0].integer) > mask) && (((yyvsp[0].integer) | mask) != -1ULL))
-+ ERROR(&(yylsp[0]), "Value out of range for"
-+ " %d-bit array element", (yyvsp[-1].array).bits);
- }
-
-- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits);
-+ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, (yyvsp[0].integer), (yyvsp[-1].array).bits);
- }
-+#line 1779 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 31:
--/* Line 1787 of yacc.c */
--#line 316 "dtc-parser.y"
-+ case 33:
-+#line 328 "dtc-parser.y" /* yacc.c:1646 */
- {
-- uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits);
-+ uint64_t val = ~0ULL >> (64 - (yyvsp[-1].array).bits);
-
-- if ((yyvsp[(1) - (2)].array).bits == 32)
-- (yyvsp[(1) - (2)].array).data = data_add_marker((yyvsp[(1) - (2)].array).data,
-+ if ((yyvsp[-1].array).bits == 32)
-+ (yyvsp[-1].array).data = data_add_marker((yyvsp[-1].array).data,
- REF_PHANDLE,
-- (yyvsp[(2) - (2)].labelref));
-+ (yyvsp[0].labelref));
- else
-- print_error("References are only allowed in "
-+ ERROR(&(yylsp[0]), "References are only allowed in "
- "arrays with 32-bit elements.");
-
-- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits);
-- }
-- break;
--
-- case 32:
--/* Line 1787 of yacc.c */
--#line 330 "dtc-parser.y"
-- {
-- (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref));
-- }
-- break;
--
-- case 33:
--/* Line 1787 of yacc.c */
--#line 337 "dtc-parser.y"
-- {
-- (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64);
-+ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, val, (yyvsp[-1].array).bits);
- }
-+#line 1797 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 34:
--/* Line 1787 of yacc.c */
--#line 341 "dtc-parser.y"
-+#line 342 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal));
-+ (yyval.array).data = data_add_marker((yyvsp[-1].array).data, LABEL, (yyvsp[0].labelref));
- }
-+#line 1805 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 35:
--/* Line 1787 of yacc.c */
--#line 345 "dtc-parser.y"
-+ case 37:
-+#line 351 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.integer) = (yyvsp[(2) - (3)].integer);
-+ (yyval.integer) = (yyvsp[-1].integer);
- }
-- break;
--
-- case 38:
--/* Line 1787 of yacc.c */
--#line 356 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); }
-+#line 1813 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 40:
--/* Line 1787 of yacc.c */
--#line 361 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); }
-+#line 362 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); }
-+#line 1819 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 42:
--/* Line 1787 of yacc.c */
--#line 366 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); }
-+#line 367 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); }
-+#line 1825 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 44:
--/* Line 1787 of yacc.c */
--#line 371 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); }
-+#line 372 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); }
-+#line 1831 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 46:
--/* Line 1787 of yacc.c */
--#line 376 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); }
-+#line 377 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); }
-+#line 1837 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 48:
--/* Line 1787 of yacc.c */
--#line 381 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); }
-+#line 382 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); }
-+#line 1843 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 50:
--/* Line 1787 of yacc.c */
--#line 386 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); }
-+#line 387 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); }
-+#line 1849 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 51:
--/* Line 1787 of yacc.c */
--#line 387 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); }
-+ case 52:
-+#line 392 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); }
-+#line 1855 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 53:
--/* Line 1787 of yacc.c */
--#line 392 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); }
-- break;
--
-- case 54:
--/* Line 1787 of yacc.c */
--#line 393 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); }
-+#line 393 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); }
-+#line 1861 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 55:
--/* Line 1787 of yacc.c */
--#line 394 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); }
-+#line 398 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); }
-+#line 1867 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 56:
--/* Line 1787 of yacc.c */
--#line 395 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); }
-+#line 399 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); }
-+#line 1873 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 57:
--/* Line 1787 of yacc.c */
--#line 399 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); }
-+#line 400 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); }
-+#line 1879 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 58:
--/* Line 1787 of yacc.c */
--#line 400 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); }
-+#line 401 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); }
-+#line 1885 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 60:
--/* Line 1787 of yacc.c */
--#line 405 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); }
-+ case 59:
-+#line 405 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); }
-+#line 1891 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 61:
--/* Line 1787 of yacc.c */
--#line 406 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); }
-+ case 60:
-+#line 406 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); }
-+#line 1897 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 63:
--/* Line 1787 of yacc.c */
--#line 411 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); }
-+ case 62:
-+#line 411 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); }
-+#line 1903 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 64:
--/* Line 1787 of yacc.c */
--#line 412 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); }
-+ case 63:
-+#line 412 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); }
-+#line 1909 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 65:
--/* Line 1787 of yacc.c */
--#line 413 "dtc-parser.y"
-- { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); }
-+#line 417 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); }
-+#line 1915 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 68:
--/* Line 1787 of yacc.c */
--#line 419 "dtc-parser.y"
-- { (yyval.integer) = -(yyvsp[(2) - (2)].integer); }
-+ case 66:
-+#line 418 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) / (yyvsp[0].integer); }
-+#line 1921 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-- case 69:
--/* Line 1787 of yacc.c */
--#line 420 "dtc-parser.y"
-- { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); }
-+ case 67:
-+#line 419 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = (yyvsp[-2].integer) % (yyvsp[0].integer); }
-+#line 1927 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 70:
--/* Line 1787 of yacc.c */
--#line 421 "dtc-parser.y"
-- { (yyval.integer) = !(yyvsp[(2) - (2)].integer); }
-+#line 425 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = -(yyvsp[0].integer); }
-+#line 1933 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 71:
--/* Line 1787 of yacc.c */
--#line 426 "dtc-parser.y"
-- {
-- (yyval.data) = empty_data;
-- }
-+#line 426 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = ~(yyvsp[0].integer); }
-+#line 1939 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 72:
--/* Line 1787 of yacc.c */
--#line 430 "dtc-parser.y"
-- {
-- (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte));
-- }
-+#line 427 "dtc-parser.y" /* yacc.c:1646 */
-+ { (yyval.integer) = !(yyvsp[0].integer); }
-+#line 1945 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 73:
--/* Line 1787 of yacc.c */
--#line 434 "dtc-parser.y"
-+#line 432 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-+ (yyval.data) = empty_data;
- }
-+#line 1953 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 74:
--/* Line 1787 of yacc.c */
--#line 441 "dtc-parser.y"
-+#line 436 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.nodelist) = NULL;
-+ (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte));
- }
-+#line 1961 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 75:
--/* Line 1787 of yacc.c */
--#line 445 "dtc-parser.y"
-+#line 440 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist));
-+ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref));
- }
-+#line 1969 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 76:
--/* Line 1787 of yacc.c */
--#line 449 "dtc-parser.y"
-+#line 447 "dtc-parser.y" /* yacc.c:1646 */
- {
-- print_error("syntax error: properties must precede subnodes");
-- YYERROR;
-+ (yyval.nodelist) = NULL;
- }
-+#line 1977 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 77:
--/* Line 1787 of yacc.c */
--#line 457 "dtc-parser.y"
-+#line 451 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename));
-+ (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist));
- }
-+#line 1985 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 78:
--/* Line 1787 of yacc.c */
--#line 461 "dtc-parser.y"
-+#line 455 "dtc-parser.y" /* yacc.c:1646 */
- {
-- (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename));
-+ ERROR(&(yylsp[0]), "Properties must precede subnodes");
-+ YYERROR;
- }
-+#line 1994 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
- case 79:
--/* Line 1787 of yacc.c */
--#line 465 "dtc-parser.y"
-+#line 463 "dtc-parser.y" /* yacc.c:1646 */
- {
-- add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref));
-- (yyval.node) = (yyvsp[(2) - (2)].node);
-+ (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename));
- }
-+#line 2002 "dtc-parser.tab.c" /* yacc.c:1646 */
- break;
-
-+ case 80:
-+#line 467 "dtc-parser.y" /* yacc.c:1646 */
-+ {
-+ (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename));
-+ }
-+#line 2010 "dtc-parser.tab.c" /* yacc.c:1646 */
-+ break;
-+
-+ case 81:
-+#line 471 "dtc-parser.y" /* yacc.c:1646 */
-+ {
-+ add_label(&(yyvsp[0].node)->labels, (yyvsp[-1].labelref));
-+ (yyval.node) = (yyvsp[0].node);
-+ }
-+#line 2019 "dtc-parser.tab.c" /* yacc.c:1646 */
-+ break;
-
--/* Line 1787 of yacc.c */
--#line 2073 "dtc-parser.tab.c"
-+
-+#line 2023 "dtc-parser.tab.c" /* yacc.c:1646 */
- default: break;
- }
- /* User semantic actions sometimes alter yychar, and that requires
-@@ -2090,8 +2040,9 @@
- YY_STACK_PRINT (yyss, yyssp);
-
- *++yyvsp = yyval;
-+ *++yylsp = yyloc;
-
-- /* Now `shift' the result of the reduction. Determine what state
-+ /* Now 'shift' the result of the reduction. Determine what state
- that goes to, based on the state we popped back to and the rule
- number reduced by. */
-
-@@ -2106,9 +2057,9 @@
- goto yynewstate;
-
-
--/*------------------------------------.
--| yyerrlab -- here on detecting error |
--`------------------------------------*/
-+/*--------------------------------------.
-+| yyerrlab -- here on detecting error. |
-+`--------------------------------------*/
- yyerrlab:
- /* Make sure we have latest lookahead translation. See comments at
- user semantic actions for why this is necessary. */
-@@ -2154,25 +2105,25 @@
- #endif
- }
-
--
-+ yyerror_range[1] = yylloc;
-
- if (yyerrstatus == 3)
- {
- /* If just tried and failed to reuse lookahead token after an
-- error, discard it. */
-+ error, discard it. */
-
- if (yychar <= YYEOF)
-- {
-- /* Return failure if at end of input. */
-- if (yychar == YYEOF)
-- YYABORT;
-- }
-+ {
-+ /* Return failure if at end of input. */
-+ if (yychar == YYEOF)
-+ YYABORT;
-+ }
- else
-- {
-- yydestruct ("Error: discarding",
-- yytoken, &yylval);
-- yychar = YYEMPTY;
-- }
-+ {
-+ yydestruct ("Error: discarding",
-+ yytoken, &yylval, &yylloc);
-+ yychar = YYEMPTY;
-+ }
- }
-
- /* Else will try to reuse lookahead token after shifting the error
-@@ -2191,7 +2142,8 @@
- if (/*CONSTCOND*/ 0)
- goto yyerrorlab;
-
-- /* Do not reclaim the symbols of the rule which action triggered
-+ yyerror_range[1] = yylsp[1-yylen];
-+ /* Do not reclaim the symbols of the rule whose action triggered
- this YYERROR. */
- YYPOPSTACK (yylen);
- yylen = 0;
-@@ -2204,29 +2156,29 @@
- | yyerrlab1 -- common code for both syntax error and YYERROR. |
- `-------------------------------------------------------------*/
- yyerrlab1:
-- yyerrstatus = 3; /* Each real token shifted decrements this. */
-+ yyerrstatus = 3; /* Each real token shifted decrements this. */
-
- for (;;)
- {
- yyn = yypact[yystate];
- if (!yypact_value_is_default (yyn))
-- {
-- yyn += YYTERROR;
-- if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-- {
-- yyn = yytable[yyn];
-- if (0 < yyn)
-- break;
-- }
-- }
-+ {
-+ yyn += YYTERROR;
-+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-+ {
-+ yyn = yytable[yyn];
-+ if (0 < yyn)
-+ break;
-+ }
-+ }
-
- /* Pop the current state because it cannot handle the error token. */
- if (yyssp == yyss)
-- YYABORT;
--
-+ YYABORT;
-
-+ yyerror_range[1] = *yylsp;
- yydestruct ("Error: popping",
-- yystos[yystate], yyvsp);
-+ yystos[yystate], yyvsp, yylsp);
- YYPOPSTACK (1);
- yystate = *yyssp;
- YY_STACK_PRINT (yyss, yyssp);
-@@ -2236,6 +2188,11 @@
- *++yyvsp = yylval;
- YY_IGNORE_MAYBE_UNINITIALIZED_END
-
-+ yyerror_range[2] = yylloc;
-+ /* Using YYLLOC is tempting, but would change the location of
-+ the lookahead. YYLOC is available though. */
-+ YYLLOC_DEFAULT (yyloc, yyerror_range, 2);
-+ *++yylsp = yyloc;
-
- /* Shift the error token. */
- YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
-@@ -2275,16 +2232,16 @@
- user semantic actions for why this is necessary. */
- yytoken = YYTRANSLATE (yychar);
- yydestruct ("Cleanup: discarding lookahead",
-- yytoken, &yylval);
-+ yytoken, &yylval, &yylloc);
- }
-- /* Do not reclaim the symbols of the rule which action triggered
-+ /* Do not reclaim the symbols of the rule whose action triggered
- this YYABORT or YYACCEPT. */
- YYPOPSTACK (yylen);
- YY_STACK_PRINT (yyss, yyssp);
- while (yyssp != yyss)
- {
- yydestruct ("Cleanup: popping",
-- yystos[*yyssp], yyvsp);
-+ yystos[*yyssp], yyvsp, yylsp);
- YYPOPSTACK (1);
- }
- #ifndef yyoverflow
-@@ -2295,72 +2252,12 @@
- if (yymsg != yymsgbuf)
- YYSTACK_FREE (yymsg);
- #endif
-- /* Make sure YYID is used. */
-- return YYID (yyresult);
-+ return yyresult;
- }
-+#line 477 "dtc-parser.y" /* yacc.c:1906 */
-
-
--/* Line 2050 of yacc.c */
--#line 471 "dtc-parser.y"
--
--
--void print_error(char const *fmt, ...)
-+void yyerror(char const *s)
- {
-- va_list va;
--
-- va_start(va, fmt);
-- srcpos_verror(&yylloc, fmt, va);
-- va_end(va);
--
-- treesource_error = 1;
--}
--
--void yyerror(char const *s) {
-- print_error("%s", s);
--}
--
--static unsigned long long eval_literal(const char *s, int base, int bits)
--{
-- unsigned long long val;
-- char *e;
--
-- errno = 0;
-- val = strtoull(s, &e, base);
-- if (*e) {
-- size_t uls = strspn(e, "UL");
-- if (e[uls])
-- print_error("bad characters in literal");
-- }
-- if ((errno == ERANGE)
-- || ((bits < 64) && (val >= (1ULL << bits))))
-- print_error("literal out of range");
-- else if (errno != 0)
-- print_error("bad literal");
-- return val;
--}
--
--static unsigned char eval_char_literal(const char *s)
--{
-- int i = 1;
-- char c = s[0];
--
-- if (c == '\0')
-- {
-- print_error("empty character literal");
-- return 0;
-- }
--
-- /*
-- * If the first character in the character literal is a \ then process
-- * the remaining characters as an escape encoding. If the first
-- * character is neither an escape or a terminator it should be the only
-- * character in the literal and will be returned.
-- */
-- if (c == '\\')
-- c = get_escape_char(s, &i);
--
-- if (s[i] != '\0')
-- print_error("malformed character literal");
--
-- return c;
-+ ERROR(&yylloc, "%s", s);
- }
-diff -Nur linux-3.18.14/scripts/dtc/dtc-parser.tab.h_shipped linux-rpi/scripts/dtc/dtc-parser.tab.h_shipped
---- linux-3.18.14/scripts/dtc/dtc-parser.tab.h_shipped 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc-parser.tab.h_shipped 2015-05-31 14:46:14.189660949 -0500
-@@ -1,19 +1,19 @@
--/* A Bison parser, made by GNU Bison 2.7.12-4996. */
-+/* A Bison parser, made by GNU Bison 3.0.2. */
-
- /* Bison interface for Yacc-like parsers in C
--
-- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
--
-+
-+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc.
-+
- This program is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 3 of the License, or
- (at your option) any later version.
--
-+
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
--
-+
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-@@ -26,13 +26,13 @@
- special exception, which will cause the skeleton and the resulting
- Bison output files to be licensed under the GNU General Public
- License without this special exception.
--
-+
- This special exception was added by the Free Software Foundation in
- version 2.2 of Bison. */
-
- #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED
- # define YY_YY_DTC_PARSER_TAB_H_INCLUDED
--/* Enabling traces. */
-+/* Debug traces. */
- #ifndef YYDEBUG
- # define YYDEBUG 0
- #endif
-@@ -40,48 +40,45 @@
- extern int yydebug;
- #endif
-
--/* Tokens. */
-+/* Token type. */
- #ifndef YYTOKENTYPE
- # define YYTOKENTYPE
-- /* Put the tokens into the symbol table, so that GDB and other debuggers
-- know about them. */
-- enum yytokentype {
-- DT_V1 = 258,
-- DT_MEMRESERVE = 259,
-- DT_LSHIFT = 260,
-- DT_RSHIFT = 261,
-- DT_LE = 262,
-- DT_GE = 263,
-- DT_EQ = 264,
-- DT_NE = 265,
-- DT_AND = 266,
-- DT_OR = 267,
-- DT_BITS = 268,
-- DT_DEL_PROP = 269,
-- DT_DEL_NODE = 270,
-- DT_PROPNODENAME = 271,
-- DT_LITERAL = 272,
-- DT_CHAR_LITERAL = 273,
-- DT_BASE = 274,
-- DT_BYTE = 275,
-- DT_STRING = 276,
-- DT_LABEL = 277,
-- DT_REF = 278,
-- DT_INCBIN = 279
-- };
-+ enum yytokentype
-+ {
-+ DT_V1 = 258,
-+ DT_PLUGIN = 259,
-+ DT_MEMRESERVE = 260,
-+ DT_LSHIFT = 261,
-+ DT_RSHIFT = 262,
-+ DT_LE = 263,
-+ DT_GE = 264,
-+ DT_EQ = 265,
-+ DT_NE = 266,
-+ DT_AND = 267,
-+ DT_OR = 268,
-+ DT_BITS = 269,
-+ DT_DEL_PROP = 270,
-+ DT_DEL_NODE = 271,
-+ DT_PROPNODENAME = 272,
-+ DT_LITERAL = 273,
-+ DT_CHAR_LITERAL = 274,
-+ DT_BYTE = 275,
-+ DT_STRING = 276,
-+ DT_LABEL = 277,
-+ DT_REF = 278,
-+ DT_INCBIN = 279
-+ };
- #endif
-
--
-+/* Value type. */
- #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
--typedef union YYSTYPE
-+typedef union YYSTYPE YYSTYPE;
-+union YYSTYPE
- {
--/* Line 2053 of yacc.c */
--#line 40 "dtc-parser.y"
-+#line 39 "dtc-parser.y" /* yacc.c:1909 */
-
- char *propnodename;
-- char *literal;
- char *labelref;
-- unsigned int cbase;
- uint8_t byte;
- struct data data;
-
-@@ -96,30 +93,31 @@
- struct node *nodelist;
- struct reserve_info *re;
- uint64_t integer;
-+ int is_plugin;
-
--
--/* Line 2053 of yacc.c */
--#line 103 "dtc-parser.tab.h"
--} YYSTYPE;
-+#line 99 "dtc-parser.tab.h" /* yacc.c:1909 */
-+};
- # define YYSTYPE_IS_TRIVIAL 1
--# define yystype YYSTYPE /* obsolescent; will be withdrawn */
- # define YYSTYPE_IS_DECLARED 1
- #endif
-
--extern YYSTYPE yylval;
--
--#ifdef YYPARSE_PARAM
--#if defined __STDC__ || defined __cplusplus
--int yyparse (void *YYPARSE_PARAM);
--#else
--int yyparse ();
-+/* Location type. */
-+#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED
-+typedef struct YYLTYPE YYLTYPE;
-+struct YYLTYPE
-+{
-+ int first_line;
-+ int first_column;
-+ int last_line;
-+ int last_column;
-+};
-+# define YYLTYPE_IS_DECLARED 1
-+# define YYLTYPE_IS_TRIVIAL 1
- #endif
--#else /* ! YYPARSE_PARAM */
--#if defined __STDC__ || defined __cplusplus
-+
-+
-+extern YYSTYPE yylval;
-+extern YYLTYPE yylloc;
- int yyparse (void);
--#else
--int yyparse ();
--#endif
--#endif /* ! YYPARSE_PARAM */
-
- #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */
-diff -Nur linux-3.18.14/scripts/dtc/dtc-parser.y linux-rpi/scripts/dtc/dtc-parser.y
---- linux-3.18.14/scripts/dtc/dtc-parser.y 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/dtc-parser.y 2015-05-31 14:46:14.189660949 -0500
-@@ -17,31 +17,28 @@
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
- * USA
- */
--
- %{
- #include <stdio.h>
-+#include <inttypes.h>
-
- #include "dtc.h"
- #include "srcpos.h"
-
--YYLTYPE yylloc;
--
- extern int yylex(void);
--extern void print_error(char const *fmt, ...);
- extern void yyerror(char const *s);
-+#define ERROR(loc, ...) \
-+ do { \
-+ srcpos_error((loc), "Error", __VA_ARGS__); \
-+ treesource_error = true; \
-+ } while (0)
-
- extern struct boot_info *the_boot_info;
--extern int treesource_error;
--
--static unsigned long long eval_literal(const char *s, int base, int bits);
--static unsigned char eval_char_literal(const char *s);
-+extern bool treesource_error;
- %}
-
- %union {
- char *propnodename;
-- char *literal;
- char *labelref;
-- unsigned int cbase;
- uint8_t byte;
- struct data data;
-
-@@ -56,18 +53,19 @@
- struct node *nodelist;
- struct reserve_info *re;
- uint64_t integer;
-+ int is_plugin;
- }
-
- %token DT_V1
-+%token DT_PLUGIN
- %token DT_MEMRESERVE
- %token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR
- %token DT_BITS
- %token DT_DEL_PROP
- %token DT_DEL_NODE
- %token <propnodename> DT_PROPNODENAME
--%token <literal> DT_LITERAL
--%token <literal> DT_CHAR_LITERAL
--%token <cbase> DT_BASE
-+%token <integer> DT_LITERAL
-+%token <integer> DT_CHAR_LITERAL
- %token <byte> DT_BYTE
- %token <data> DT_STRING
- %token <labelref> DT_LABEL
-@@ -76,6 +74,7 @@
-
- %type <data> propdata
- %type <data> propdataprefix
-+%type <is_plugin> plugindecl
- %type <re> memreserve
- %type <re> memreserves
- %type <array> arrayprefix
-@@ -106,10 +105,23 @@
- %%
-
- sourcefile:
-- DT_V1 ';' memreserves devicetree
-+ DT_V1 ';' plugindecl memreserves devicetree
-+ {
-+ $5->is_plugin = $3;
-+ $5->is_root = 1;
-+ the_boot_info = build_boot_info($4, $5,
-+ guess_boot_cpuid($5));
-+ }
-+ ;
-+
-+plugindecl:
-+ /* empty */
-+ {
-+ $$ = 0;
-+ }
-+ | DT_PLUGIN ';'
- {
-- the_boot_info = build_boot_info($3, $4,
-- guess_boot_cpuid($4));
-+ $$ = 1;
- }
- ;
-
-@@ -152,17 +164,18 @@
- if (target)
- merge_nodes(target, $3);
- else
-- print_error("label or path, '%s', not found", $2);
-+ ERROR(&@2, "Label or path %s not found", $2);
- $$ = $1;
- }
- | devicetree DT_DEL_NODE DT_REF ';'
- {
- struct node *target = get_node_by_ref($1, $3);
-
-- if (!target)
-- print_error("label or path, '%s', not found", $3);
-- else
-+ if (target)
- delete_node(target);
-+ else
-+ ERROR(&@3, "Label or path %s not found", $3);
-+
-
- $$ = $1;
- }
-@@ -230,10 +243,9 @@
-
- if ($6 != 0)
- if (fseek(f, $6, SEEK_SET) != 0)
-- print_error("Couldn't seek to offset %llu in \"%s\": %s",
-- (unsigned long long)$6,
-- $4.val,
-- strerror(errno));
-+ die("Couldn't seek to offset %llu in \"%s\": %s",
-+ (unsigned long long)$6, $4.val,
-+ strerror(errno));
-
- d = data_copy_file(f, $8);
-
-@@ -274,18 +286,19 @@
- arrayprefix:
- DT_BITS DT_LITERAL '<'
- {
-- $$.data = empty_data;
-- $$.bits = eval_literal($2, 0, 7);
-+ unsigned long long bits;
-
-- if (($$.bits != 8) &&
-- ($$.bits != 16) &&
-- ($$.bits != 32) &&
-- ($$.bits != 64))
-- {
-- print_error("Only 8, 16, 32 and 64-bit elements"
-- " are currently supported");
-- $$.bits = 32;
-+ bits = $2;
-+
-+ if ((bits != 8) && (bits != 16) &&
-+ (bits != 32) && (bits != 64)) {
-+ ERROR(&@2, "Array elements must be"
-+ " 8, 16, 32 or 64-bits");
-+ bits = 32;
- }
-+
-+ $$.data = empty_data;
-+ $$.bits = bits;
- }
- | '<'
- {
-@@ -305,9 +318,8 @@
- * mask), all bits are one.
- */
- if (($2 > mask) && (($2 | mask) != -1ULL))
-- print_error(
-- "integer value out of range "
-- "%016lx (%d bits)", $1.bits);
-+ ERROR(&@2, "Value out of range for"
-+ " %d-bit array element", $1.bits);
- }
-
- $$.data = data_append_integer($1.data, $2, $1.bits);
-@@ -321,7 +333,7 @@
- REF_PHANDLE,
- $2);
- else
-- print_error("References are only allowed in "
-+ ERROR(&@2, "References are only allowed in "
- "arrays with 32-bit elements.");
-
- $$.data = data_append_integer($1.data, val, $1.bits);
-@@ -334,13 +346,7 @@
-
- integer_prim:
- DT_LITERAL
-- {
-- $$ = eval_literal($1, 0, 64);
-- }
- | DT_CHAR_LITERAL
-- {
-- $$ = eval_char_literal($1);
-- }
- | '(' integer_expr ')'
- {
- $$ = $2;
-@@ -447,7 +453,7 @@
- }
- | subnode propdef
- {
-- print_error("syntax error: properties must precede subnodes");
-+ ERROR(&@2, "Properties must precede subnodes");
- YYERROR;
- }
- ;
-@@ -470,63 +476,7 @@
-
- %%
-
--void print_error(char const *fmt, ...)
-+void yyerror(char const *s)
- {
-- va_list va;
--
-- va_start(va, fmt);
-- srcpos_verror(&yylloc, fmt, va);
-- va_end(va);
--
-- treesource_error = 1;
--}
--
--void yyerror(char const *s) {
-- print_error("%s", s);
--}
--
--static unsigned long long eval_literal(const char *s, int base, int bits)
--{
-- unsigned long long val;
-- char *e;
--
-- errno = 0;
-- val = strtoull(s, &e, base);
-- if (*e) {
-- size_t uls = strspn(e, "UL");
-- if (e[uls])
-- print_error("bad characters in literal");
-- }
-- if ((errno == ERANGE)
-- || ((bits < 64) && (val >= (1ULL << bits))))
-- print_error("literal out of range");
-- else if (errno != 0)
-- print_error("bad literal");
-- return val;
--}
--
--static unsigned char eval_char_literal(const char *s)
--{
-- int i = 1;
-- char c = s[0];
--
-- if (c == '\0')
-- {
-- print_error("empty character literal");
-- return 0;
-- }
--
-- /*
-- * If the first character in the character literal is a \ then process
-- * the remaining characters as an escape encoding. If the first
-- * character is neither an escape or a terminator it should be the only
-- * character in the literal and will be returned.
-- */
-- if (c == '\\')
-- c = get_escape_char(s, &i);
--
-- if (s[i] != '\0')
-- print_error("malformed character literal");
--
-- return c;
-+ ERROR(&yylloc, "%s", s);
- }
-diff -Nur linux-3.18.14/scripts/dtc/flattree.c linux-rpi/scripts/dtc/flattree.c
---- linux-3.18.14/scripts/dtc/flattree.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/flattree.c 2015-05-31 14:46:14.189660949 -0500
-@@ -261,7 +261,13 @@
- {
- struct property *prop;
- struct node *child;
-- int seen_name_prop = 0;
-+ bool seen_name_prop = false;
-+ struct symbol *sym;
-+ struct fixup *f;
-+ struct fixup_entry *fe;
-+ char *name, *s;
-+ const char *fullpath;
-+ int namesz, nameoff, vallen;
-
- if (tree->deleted)
- return;
-@@ -276,10 +282,8 @@
- emit->align(etarget, sizeof(cell_t));
-
- for_each_property(tree, prop) {
-- int nameoff;
--
- if (streq(prop->name, "name"))
-- seen_name_prop = 1;
-+ seen_name_prop = true;
-
- nameoff = stringtable_insert(strbuf, prop->name);
-
-@@ -310,6 +314,139 @@
- flatten_tree(child, emit, etarget, strbuf, vi);
- }
-
-+ if (!symbol_fixup_support)
-+ goto no_symbols;
-+
-+ /* add the symbol nodes (if any) */
-+ if (tree->symbols) {
-+
-+ emit->beginnode(etarget, NULL);
-+ emit->string(etarget, "__symbols__", 0);
-+ emit->align(etarget, sizeof(cell_t));
-+
-+ for_each_symbol(tree, sym) {
-+
-+ vallen = strlen(sym->node->fullpath);
-+
-+ nameoff = stringtable_insert(strbuf, sym->label->label);
-+
-+ emit->property(etarget, NULL);
-+ emit->cell(etarget, vallen + 1);
-+ emit->cell(etarget, nameoff);
-+
-+ if ((vi->flags & FTF_VARALIGN) && vallen >= 8)
-+ emit->align(etarget, 8);
-+
-+ emit->string(etarget, sym->node->fullpath,
-+ strlen(sym->node->fullpath));
-+ emit->align(etarget, sizeof(cell_t));
-+ }
-+
-+ emit->endnode(etarget, NULL);
-+ }
-+
-+ /* add the fixup nodes */
-+ if (tree->fixups) {
-+
-+ /* emit the external fixups */
-+ emit->beginnode(etarget, NULL);
-+ emit->string(etarget, "__fixups__", 0);
-+ emit->align(etarget, sizeof(cell_t));
-+
-+ for_each_fixup(tree, f) {
-+
-+ namesz = 0;
-+ for_each_fixup_entry(f, fe) {
-+ fullpath = fe->node->fullpath;
-+ if (fullpath[0] == '\0')
-+ fullpath = "/";
-+ namesz += strlen(fullpath) + 1;
-+ namesz += strlen(fe->prop->name) + 1;
-+ namesz += 32; /* space for :<number> + '\0' */
-+ }
-+
-+ name = xmalloc(namesz);
-+
-+ s = name;
-+ for_each_fixup_entry(f, fe) {
-+ fullpath = fe->node->fullpath;
-+ if (fullpath[0] == '\0')
-+ fullpath = "/";
-+ snprintf(s, name + namesz - s, "%s:%s:%d",
-+ fullpath,
-+ fe->prop->name, fe->offset);
-+ s += strlen(s) + 1;
-+ }
-+
-+ nameoff = stringtable_insert(strbuf, f->ref);
-+ vallen = s - name - 1;
-+
-+ emit->property(etarget, NULL);
-+ emit->cell(etarget, vallen + 1);
-+ emit->cell(etarget, nameoff);
-+
-+ if ((vi->flags & FTF_VARALIGN) && vallen >= 8)
-+ emit->align(etarget, 8);
-+
-+ emit->string(etarget, name, vallen);
-+ emit->align(etarget, sizeof(cell_t));
-+
-+ free(name);
-+ }
-+
-+ emit->endnode(etarget, tree->labels);
-+ }
-+
-+ /* add the local fixup property */
-+ if (tree->local_fixups) {
-+
-+ /* emit the external fixups */
-+ emit->beginnode(etarget, NULL);
-+ emit->string(etarget, "__local_fixups__", 0);
-+ emit->align(etarget, sizeof(cell_t));
-+
-+ namesz = 0;
-+ for_each_local_fixup_entry(tree, fe) {
-+ fullpath = fe->node->fullpath;
-+ if (fullpath[0] == '\0')
-+ fullpath = "/";
-+ namesz += strlen(fullpath) + 1;
-+ namesz += strlen(fe->prop->name) + 1;
-+ namesz += 32; /* space for :<number> + '\0' */
-+ }
-+
-+ name = xmalloc(namesz);
-+
-+ s = name;
-+ for_each_local_fixup_entry(tree, fe) {
-+ fullpath = fe->node->fullpath;
-+ if (fullpath[0] == '\0')
-+ fullpath = "/";
-+ snprintf(s, name + namesz - s, "%s:%s:%d",
-+ fullpath, fe->prop->name,
-+ fe->offset);
-+ s += strlen(s) + 1;
-+ }
-+
-+ nameoff = stringtable_insert(strbuf, "fixup");
-+ vallen = s - name - 1;
-+
-+ emit->property(etarget, NULL);
-+ emit->cell(etarget, vallen + 1);
-+ emit->cell(etarget, nameoff);
-+
-+ if ((vi->flags & FTF_VARALIGN) && vallen >= 8)
-+ emit->align(etarget, 8);
-+
-+ emit->string(etarget, name, vallen);
-+ emit->align(etarget, sizeof(cell_t));
-+
-+ free(name);
-+
-+ emit->endnode(etarget, tree->labels);
-+ }
-+
-+no_symbols:
- emit->endnode(etarget, tree->labels);
- }
-
-diff -Nur linux-3.18.14/scripts/dtc/fstree.c linux-rpi/scripts/dtc/fstree.c
---- linux-3.18.14/scripts/dtc/fstree.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/fstree.c 2015-05-31 14:46:14.189660949 -0500
-@@ -37,26 +37,26 @@
- tree = build_node(NULL, NULL);
-
- while ((de = readdir(d)) != NULL) {
-- char *tmpnam;
-+ char *tmpname;
-
- if (streq(de->d_name, ".")
- || streq(de->d_name, ".."))
- continue;
-
-- tmpnam = join_path(dirname, de->d_name);
-+ tmpname = join_path(dirname, de->d_name);
-
-- if (lstat(tmpnam, &st) < 0)
-- die("stat(%s): %s\n", tmpnam, strerror(errno));
-+ if (lstat(tmpname, &st) < 0)
-+ die("stat(%s): %s\n", tmpname, strerror(errno));
-
- if (S_ISREG(st.st_mode)) {
- struct property *prop;
- FILE *pfile;
-
-- pfile = fopen(tmpnam, "r");
-+ pfile = fopen(tmpname, "rb");
- if (! pfile) {
- fprintf(stderr,
- "WARNING: Cannot open %s: %s\n",
-- tmpnam, strerror(errno));
-+ tmpname, strerror(errno));
- } else {
- prop = build_property(xstrdup(de->d_name),
- data_copy_file(pfile,
-@@ -67,12 +67,12 @@
- } else if (S_ISDIR(st.st_mode)) {
- struct node *newchild;
-
-- newchild = read_fstree(tmpnam);
-+ newchild = read_fstree(tmpname);
- newchild = name_node(newchild, xstrdup(de->d_name));
- add_child(tree, newchild);
- }
-
-- free(tmpnam);
-+ free(tmpname);
- }
-
- closedir(d);
-diff -Nur linux-3.18.14/scripts/dtc/livetree.c linux-rpi/scripts/dtc/livetree.c
---- linux-3.18.14/scripts/dtc/livetree.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/livetree.c 2015-05-31 14:46:14.197660949 -0500
-@@ -511,7 +511,9 @@
-
- struct node *get_node_by_ref(struct node *tree, const char *ref)
- {
-- if (ref[0] == '/')
-+ if (streq(ref, "/"))
-+ return tree;
-+ else if (ref[0] == '/')
- return get_node_by_path(tree, ref);
- else
- return get_node_by_label(tree, ref);
-diff -Nur linux-3.18.14/scripts/dtc/srcpos.c linux-rpi/scripts/dtc/srcpos.c
---- linux-3.18.14/scripts/dtc/srcpos.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/srcpos.c 2015-05-31 14:46:14.197660949 -0500
-@@ -34,7 +34,7 @@
- static struct search_path *search_path_head, **search_path_tail;
-
-
--static char *dirname(const char *path)
-+static char *get_dirname(const char *path)
- {
- const char *slash = strrchr(path, '/');
-
-@@ -77,7 +77,7 @@
- else
- fullname = join_path(dirname, fname);
-
-- *fp = fopen(fullname, "r");
-+ *fp = fopen(fullname, "rb");
- if (!*fp) {
- free(fullname);
- fullname = NULL;
-@@ -150,7 +150,7 @@
- srcfile = xmalloc(sizeof(*srcfile));
-
- srcfile->f = srcfile_relative_open(fname, &srcfile->name);
-- srcfile->dir = dirname(srcfile->name);
-+ srcfile->dir = get_dirname(srcfile->name);
- srcfile->prev = current_srcfile;
-
- srcfile->lineno = 1;
-@@ -159,7 +159,7 @@
- current_srcfile = srcfile;
- }
-
--int srcfile_pop(void)
-+bool srcfile_pop(void)
- {
- struct srcfile_state *srcfile = current_srcfile;
-
-@@ -177,7 +177,7 @@
- * fix this we could either allocate all the files from a
- * table, or use a pool allocator. */
-
-- return current_srcfile ? 1 : 0;
-+ return current_srcfile ? true : false;
- }
-
- void srcfile_add_search_path(const char *dirname)
-@@ -290,42 +290,27 @@
- return pos_str;
- }
-
--void
--srcpos_verror(struct srcpos *pos, char const *fmt, va_list va)
-+void srcpos_verror(struct srcpos *pos, const char *prefix,
-+ const char *fmt, va_list va)
- {
-- const char *srcstr;
--
-- srcstr = srcpos_string(pos);
-+ char *srcstr;
-
-- fprintf(stderr, "Error: %s ", srcstr);
-- vfprintf(stderr, fmt, va);
-- fprintf(stderr, "\n");
--}
-+ srcstr = srcpos_string(pos);
-
--void
--srcpos_error(struct srcpos *pos, char const *fmt, ...)
--{
-- va_list va;
-+ fprintf(stderr, "%s: %s ", prefix, srcstr);
-+ vfprintf(stderr, fmt, va);
-+ fprintf(stderr, "\n");
-
-- va_start(va, fmt);
-- srcpos_verror(pos, fmt, va);
-- va_end(va);
-+ free(srcstr);
- }
-
--
--void
--srcpos_warn(struct srcpos *pos, char const *fmt, ...)
-+void srcpos_error(struct srcpos *pos, const char *prefix,
-+ const char *fmt, ...)
- {
-- const char *srcstr;
- va_list va;
-- va_start(va, fmt);
--
-- srcstr = srcpos_string(pos);
--
-- fprintf(stderr, "Warning: %s ", srcstr);
-- vfprintf(stderr, fmt, va);
-- fprintf(stderr, "\n");
-
-+ va_start(va, fmt);
-+ srcpos_verror(pos, prefix, fmt, va);
- va_end(va);
- }
-
-diff -Nur linux-3.18.14/scripts/dtc/srcpos.h linux-rpi/scripts/dtc/srcpos.h
---- linux-3.18.14/scripts/dtc/srcpos.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/srcpos.h 2015-05-31 14:46:14.197660949 -0500
-@@ -21,6 +21,7 @@
- #define _SRCPOS_H_
-
- #include <stdio.h>
-+#include <stdbool.h>
-
- struct srcfile_state {
- FILE *f;
-@@ -55,7 +56,7 @@
- FILE *srcfile_relative_open(const char *fname, char **fullnamep);
-
- void srcfile_push(const char *fname);
--int srcfile_pop(void);
-+bool srcfile_pop(void);
-
- /**
- * Add a new directory to the search path for input files
-@@ -106,12 +107,12 @@
- extern char *srcpos_string(struct srcpos *pos);
- extern void srcpos_dump(struct srcpos *pos);
-
--extern void srcpos_verror(struct srcpos *pos, char const *, va_list va)
-- __attribute__((format(printf, 2, 0)));
--extern void srcpos_error(struct srcpos *pos, char const *, ...)
-- __attribute__((format(printf, 2, 3)));
--extern void srcpos_warn(struct srcpos *pos, char const *, ...)
-- __attribute__((format(printf, 2, 3)));
-+extern void srcpos_verror(struct srcpos *pos, const char *prefix,
-+ const char *fmt, va_list va)
-+ __attribute__((format(printf, 3, 0)));
-+extern void srcpos_error(struct srcpos *pos, const char *prefix,
-+ const char *fmt, ...)
-+ __attribute__((format(printf, 3, 4)));
-
- extern void srcpos_set_line(char *f, int l);
-
-diff -Nur linux-3.18.14/scripts/dtc/treesource.c linux-rpi/scripts/dtc/treesource.c
---- linux-3.18.14/scripts/dtc/treesource.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/treesource.c 2015-05-31 14:46:14.197660949 -0500
-@@ -26,12 +26,12 @@
- extern YYLTYPE yylloc;
-
- struct boot_info *the_boot_info;
--int treesource_error;
-+bool treesource_error;
-
- struct boot_info *dt_from_source(const char *fname)
- {
- the_boot_info = NULL;
-- treesource_error = 0;
-+ treesource_error = false;
-
- srcfile_push(fname);
- yyin = current_srcfile->f;
-@@ -54,9 +54,9 @@
- fputc('\t', f);
- }
-
--static int isstring(char c)
-+static bool isstring(char c)
- {
-- return (isprint(c)
-+ return (isprint((unsigned char)c)
- || (c == '\0')
- || strchr("\a\b\t\n\v\f\r", c));
- }
-@@ -109,7 +109,7 @@
- break;
- case '\0':
- fprintf(f, "\", ");
-- while (m && (m->offset < i)) {
-+ while (m && (m->offset <= (i + 1))) {
- if (m->type == LABEL) {
- assert(m->offset == (i+1));
- fprintf(f, "%s: ", m->ref);
-@@ -119,7 +119,7 @@
- fprintf(f, "\"");
- break;
- default:
-- if (isprint(c))
-+ if (isprint((unsigned char)c))
- fprintf(f, "%c", c);
- else
- fprintf(f, "\\x%02hhx", c);
-@@ -178,7 +178,7 @@
- m = m->next;
- }
-
-- fprintf(f, "%02hhx", *bp++);
-+ fprintf(f, "%02hhx", (unsigned char)(*bp++));
- if ((const void *)bp >= propend)
- break;
- fprintf(f, " ");
-diff -Nur linux-3.18.14/scripts/dtc/util.c linux-rpi/scripts/dtc/util.c
---- linux-3.18.14/scripts/dtc/util.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/util.c 2015-05-31 14:46:14.197660949 -0500
-@@ -39,11 +39,11 @@
- char *xstrdup(const char *s)
- {
- int len = strlen(s) + 1;
-- char *dup = xmalloc(len);
-+ char *d = xmalloc(len);
-
-- memcpy(dup, s, len);
-+ memcpy(d, s, len);
-
-- return dup;
-+ return d;
- }
-
- char *join_path(const char *path, const char *name)
-@@ -70,7 +70,7 @@
- return str;
- }
-
--int util_is_printable_string(const void *data, int len)
-+bool util_is_printable_string(const void *data, int len)
- {
- const char *s = data;
- const char *ss, *se;
-@@ -87,7 +87,7 @@
-
- while (s < se) {
- ss = s;
-- while (s < se && *s && isprint(*s))
-+ while (s < se && *s && isprint((unsigned char)*s))
- s++;
-
- /* not zero, or not done yet */
-@@ -219,10 +219,6 @@
- if (offset == bufsize) {
- bufsize *= 2;
- buf = xrealloc(buf, bufsize);
-- if (!buf) {
-- ret = ENOMEM;
-- break;
-- }
- }
-
- ret = read(fd, &buf[offset], bufsize - offset);
-@@ -375,9 +371,9 @@
- const uint32_t *cell = (const uint32_t *)data;
-
- printf(" = <");
-- for (i = 0; i < len; i += 4)
-+ for (i = 0, len /= 4; i < len; i++)
- printf("0x%08x%s", fdt32_to_cpu(cell[i]),
-- i < (len - 4) ? " " : "");
-+ i < (len - 1) ? " " : "");
- printf(">");
- } else {
- printf(" = [");
-diff -Nur linux-3.18.14/scripts/dtc/util.h linux-rpi/scripts/dtc/util.h
---- linux-3.18.14/scripts/dtc/util.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/util.h 2015-05-31 14:46:14.197660949 -0500
-@@ -2,6 +2,7 @@
- #define _UTIL_H
-
- #include <stdarg.h>
-+#include <stdbool.h>
- #include <getopt.h>
-
- /*
-@@ -33,6 +34,7 @@
- va_start(ap, str);
- fprintf(stderr, "FATAL ERROR: ");
- vfprintf(stderr, str, ap);
-+ va_end(ap);
- exit(1);
- }
-
-@@ -68,7 +70,7 @@
- * @param len The string length including terminator
- * @return 1 if a valid printable string, 0 if not
- */
--int util_is_printable_string(const void *data, int len);
-+bool util_is_printable_string(const void *data, int len);
-
- /*
- * Parse an escaped character starting at index i in string s. The resulting
-diff -Nur linux-3.18.14/scripts/dtc/version_gen.h linux-rpi/scripts/dtc/version_gen.h
---- linux-3.18.14/scripts/dtc/version_gen.h 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/scripts/dtc/version_gen.h 2015-05-31 14:46:14.197660949 -0500
-@@ -1 +1 @@
--#define DTC_VERSION "DTC 1.4.0-dirty"
-+#define DTC_VERSION "DTC 1.4.1-g36c70742"
-diff -Nur linux-3.18.14/scripts/knlinfo linux-rpi/scripts/knlinfo
---- linux-3.18.14/scripts/knlinfo 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/scripts/knlinfo 2015-05-31 14:46:14.205660949 -0500
-@@ -0,0 +1,167 @@
-+#!/usr/bin/env perl
-+# ----------------------------------------------------------------------
-+# knlinfo by Phil Elwell for Raspberry Pi
-+#
-+# (c) 2014,2015 Raspberry Pi (Trading) Limited <info@raspberrypi.org>
-+#
-+# Licensed under the terms of the GNU General Public License.
-+# ----------------------------------------------------------------------
-+
-+use strict;
-+use integer;
-+
-+use Fcntl ":seek";
-+
-+my $trailer_magic = 'RPTL';
-+
-+my %atom_formats =
-+(
-+ 'DTOK' => \&format_bool,
-+ 'KVer' => \&format_string,
-+);
-+
-+if (@ARGV != 1)
-+{
-+ print ("Usage: knlinfo <kernel image>\n");
-+ exit(1);
-+}
-+
-+my $kernel_file = $ARGV[0];
-+
-+
-+my ($atoms, $pos) = read_trailer($kernel_file);
-+
-+exit(1) if (!$atoms);
-+
-+printf("Kernel trailer found at %d/0x%x:\n", $pos, $pos);
-+
-+foreach my $atom (@$atoms)
-+{
-+ printf(" %s: %s\n", $atom->[0], format_atom($atom));
-+}
-+
-+exit(0);
-+
-+sub read_trailer
-+{
-+ my ($kernel_file) = @_;
-+ my $fh;
-+
-+ if (!open($fh, '<', $kernel_file))
-+ {
-+ print ("* Failed to open '$kernel_file'\n");
-+ return undef;
-+ }
-+
-+ if (!seek($fh, -12, SEEK_END))
-+ {
-+ print ("* seek error in '$kernel_file'\n");
-+ return undef;
-+ }
-+
-+ my $last_bytes;
-+ sysread($fh, $last_bytes, 12);
-+
-+ my ($trailer_len, $data_len, $magic) = unpack('VVa4', $last_bytes);
-+
-+ if (($magic ne $trailer_magic) || ($data_len != 4))
-+ {
-+ print ("* no trailer\n");
-+ return undef;
-+ }
-+ if (!seek($fh, -12, SEEK_END))
-+ {
-+ print ("* seek error in '$kernel_file'\n");
-+ return undef;
-+ }
-+
-+ $trailer_len -= 12;
-+
-+ while ($trailer_len > 0)
-+ {
-+ if ($trailer_len < 8)
-+ {
-+ print ("* truncated atom header in trailer\n");
-+ return undef;
-+ }
-+ if (!seek($fh, -8, SEEK_CUR))
-+ {
-+ print ("* seek error in '$kernel_file'\n");
-+ return undef;
-+ }
-+ $trailer_len -= 8;
-+
-+ my $atom_hdr;
-+ sysread($fh, $atom_hdr, 8);
-+ my ($atom_len, $atom_type) = unpack('Va4', $atom_hdr);
-+
-+ if ($trailer_len < $atom_len)
-+ {
-+ print ("* truncated atom data in trailer\n");
-+ return undef;
-+ }
-+
-+ my $rounded_len = (($atom_len + 3) & ~3);
-+ if (!seek($fh, -(8 + $rounded_len), SEEK_CUR))
-+ {
-+ print ("* seek error in '$kernel_file'\n");
-+ return undef;
-+ }
-+ $trailer_len -= $rounded_len;
-+
-+ my $atom_data;
-+ sysread($fh, $atom_data, $atom_len);
-+
-+ if (!seek($fh, -$atom_len, SEEK_CUR))
-+ {
-+ print ("* seek error in '$kernel_file'\n");
-+ return undef;
-+ }
-+
-+ push @$atoms, [ $atom_type, $atom_data ];
-+ }
-+
-+ if (($$atoms[-1][0] eq "\x00\x00\x00\x00") &&
-+ ($$atoms[-1][1] eq ""))
-+ {
-+ pop @$atoms;
-+ }
-+ else
-+ {
-+ print ("* end marker missing from trailer\n");
-+ }
-+
-+ return ($atoms, tell($fh));
-+}
-+
-+sub format_atom
-+{
-+ my ($atom) = @_;
-+
-+ my $format_func = $atom_formats{$atom->[0]} || \&format_hex;
-+ return $format_func->($atom->[1]);
-+}
-+
-+sub format_bool
-+{
-+ my ($data) = @_;
-+ return unpack('V', $data) ? 'true' : 'false';
-+}
-+
-+sub format_int
-+{
-+ my ($data) = @_;
-+ return unpack('V', $data);
-+}
-+
-+sub format_string
-+{
-+ my ($data) = @_;
-+ return '"'.$data.'"';
-+}
-+
-+sub format_hex
-+{
-+ my ($data) = @_;
-+ return unpack('H*', $data);
-+}
-diff -Nur linux-3.18.14/scripts/mkknlimg linux-rpi/scripts/mkknlimg
---- linux-3.18.14/scripts/mkknlimg 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/scripts/mkknlimg 2015-05-31 14:46:14.205660949 -0500
-@@ -0,0 +1,260 @@
-+#!/usr/bin/env perl
-+# ----------------------------------------------------------------------
-+# mkknlimg by Phil Elwell for Raspberry Pi
-+# based on extract-ikconfig Dick Streefland
-+#
-+# (c) 2009,2010 Dick Streefland <dick@streefland.net>
-+# (c) 2014,2015 Raspberry Pi (Trading) Limited <info@raspberrypi.org>
-+#
-+# Licensed under the terms of the GNU General Public License.
-+# ----------------------------------------------------------------------
-+
-+use strict;
-+use warnings;
-+use integer;
-+
-+my $trailer_magic = 'RPTL';
-+
-+my $tmpfile1 = "/tmp/mkknlimg_$$.1";
-+my $tmpfile2 = "/tmp/mkknlimg_$$.2";
-+
-+my $dtok = 0;
-+
-+while (@ARGV && ($ARGV[0] =~ /^-/))
-+{
-+ my $arg = shift(@ARGV);
-+ if ($arg eq '--dtok')
-+ {
-+ $dtok = 1;
-+ }
-+ else
-+ {
-+ print ("* Unknown option '$arg'\n");
-+ usage();
-+ }
-+}
-+
-+usage() if (@ARGV != 2);
-+
-+my $kernel_file = $ARGV[0];
-+my $out_file = $ARGV[1];
-+
-+if (! -r $kernel_file)
-+{
-+ print ("* File '$kernel_file' not found\n");
-+ usage();
-+}
-+
-+my @wanted_config_lines =
-+(
-+ 'CONFIG_BCM2708_DT'
-+);
-+
-+my @wanted_strings =
-+(
-+ 'bcm2708_fb',
-+ 'brcm,bcm2708-pinctrl',
-+ 'brcm,bcm2835-gpio',
-+ 'of_find_property'
-+);
-+
-+my $res = try_extract($kernel_file, $tmpfile1);
-+$res = try_decompress('\037\213\010', 'xy', 'gunzip', 0,
-+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
-+$res = try_decompress('\3757zXZ\000', 'abcde', 'unxz --single-stream', -1,
-+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
-+$res = try_decompress('BZh', 'xy', 'bunzip2', 0,
-+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
-+$res = try_decompress('\135\0\0\0', 'xxx', 'unlzma', 0,
-+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
-+$res = try_decompress('\211\114\132', 'xy', 'lzop -d', 0,
-+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
-+$res = try_decompress('\002\041\114\030', 'xy', 'lz4 -d', 1,
-+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res);
-+
-+my $append_trailer;
-+my $trailer;
-+my $kver = '?';
-+
-+$append_trailer = $dtok;
-+
-+if ($res)
-+{
-+ $kver = $res->{''} || '?';
-+ print("Version: $kver\n");
-+
-+ $append_trailer = $dtok;
-+ if (!$dtok)
-+ {
-+ if (config_bool($res, 'bcm2708_fb'))
-+ {
-+ $dtok ||= config_bool($res, 'CONFIG_BCM2708_DT');
-+ $dtok ||= config_bool($res, 'brcm,bcm2708-pinctrl');
-+ $dtok ||= config_bool($res, 'brcm,bcm2835-gpio');
-+ $append_trailer = 1;
-+ }
-+ else
-+ {
-+ print ("* This doesn't look like a Raspberry Pi kernel. In pass-through mode.\n");
-+ }
-+ }
-+}
-+elsif (!$dtok)
-+{
-+ print ("* Is this a valid kernel? In pass-through mode.\n");
-+}
-+
-+if ($append_trailer)
-+{
-+ printf("DT: %s\n", $dtok ? "y" : "n");
-+
-+ my @atoms;
-+
-+ push @atoms, [ $trailer_magic, pack('V', 0) ];
-+ push @atoms, [ 'KVer', $kver ];
-+ push @atoms, [ 'DTOK', pack('V', $dtok) ];
-+
-+ $trailer = pack_trailer(\@atoms);
-+ $atoms[0]->[1] = pack('V', length($trailer));
-+
-+ $trailer = pack_trailer(\@atoms);
-+}
-+
-+my $ofh;
-+my $total_len = 0;
-+
-+if ($out_file eq $kernel_file)
-+{
-+ die "* Failed to open '$out_file' for append\n"
-+ if (!open($ofh, '>>', $out_file));
-+ $total_len = tell($ofh);
-+}
-+else
-+{
-+ die "* Failed to open '$kernel_file'\n"
-+ if (!open(my $ifh, '<', $kernel_file));
-+ die "* Failed to create '$out_file'\n"
-+ if (!open($ofh, '>', $out_file));
-+
-+ my $copybuf;
-+ while (1)
-+ {
-+ my $bytes = sysread($ifh, $copybuf, 64*1024);
-+ last if (!$bytes);
-+ syswrite($ofh, $copybuf, $bytes);
-+ $total_len += $bytes;
-+ }
-+ close($ifh);
-+}
-+
-+if ($trailer)
-+{
-+ # Pad to word-alignment
-+ syswrite($ofh, "\x000\x000\x000", (-$total_len & 0x3));
-+ syswrite($ofh, $trailer);
-+}
-+
-+close($ofh);
-+
-+exit($trailer ? 0 : 1);
-+
-+END {
-+ unlink($tmpfile1) if ($tmpfile1);
-+ unlink($tmpfile2) if ($tmpfile2);
-+}
-+
-+
-+sub usage
-+{
-+ print ("Usage: mkknlimg [--dtok] <vmlinux|zImage|bzImage> <outfile>\n");
-+ exit(1);
-+}
-+
-+sub try_extract
-+{
-+ my ($knl, $tmp) = @_;
-+
-+ my $ver = `strings "$knl" | grep -a -E "^Linux version [1-9]"`;
-+
-+ return undef if (!$ver);
-+
-+ chomp($ver);
-+
-+ my $res = { ''=>$ver };
-+ my $string_pattern = '^('.join('|', @wanted_strings).')$';
-+
-+ my @matches = `strings \"$knl\" | grep -E \"$string_pattern\"`;
-+ foreach my $match (@matches)
-+ {
-+ chomp($match);
-+ $res->{$match} = 1;
-+ }
-+
-+ my $config_pattern = '^('.join('|', @wanted_config_lines).')=(.*)$';
-+ my $cf1 = 'IKCFG_ST\037\213\010';
-+ my $cf2 = '0123456789';
-+
-+ my $pos = `tr "$cf1\n$cf2" "\n$cf2=" < "$knl" | grep -abo "^$cf2"`;
-+ if ($pos)
-+ {
-+ $pos =~ s/:.*[\r\n]*$//s;
-+ $pos += 8;
-+ my $err = (system("tail -c+$pos \"$knl\" | zcat > $tmp 2> /dev/null") >> 8);
-+ if (($err == 0) || ($err == 2))
-+ {
-+ if (open(my $fh, '<', $tmp))
-+ {
-+ while (my $line = <$fh>)
-+ {
-+ chomp($line);
-+ $res->{$1} = $2 if ($line =~ /$config_pattern/);
-+ }
-+
-+ close($fh);
-+ }
-+ }
-+ }
-+
-+ return $res;
-+}
-+
-+
-+sub try_decompress
-+{
-+ my ($magic, $subst, $zcat, $idx, $knl, $tmp1, $tmp2) = @_;
-+
-+ my $pos = `tr "$magic\n$subst" "\n$subst=" < "$knl" | grep -abo "^$subst"`;
-+ if ($pos)
-+ {
-+ chomp($pos);
-+ $pos = (split(/[\r\n]+/, $pos))[$idx];
-+ return undef if (!defined($pos));
-+ $pos =~ s/:.*[\r\n]*$//s;
-+ my $cmd = "tail -c+$pos \"$knl\" | $zcat > $tmp2 2> /dev/null";
-+ my $err = (system($cmd) >> 8);
-+ return undef if (($err != 0) && ($err != 2));
-+
-+ return try_extract($tmp2, $tmp1);
-+ }
-+
-+ return undef;
-+}
-+
-+sub pack_trailer
-+{
-+ my ($atoms) = @_;
-+ my $trailer = pack('VV', 0, 0);
-+ for (my $i = $#$atoms; $i>=0; $i--)
-+ {
-+ my $atom = $atoms->[$i];
-+ $trailer .= pack('a*x!4Va4', $atom->[1], length($atom->[1]), $atom->[0]);
-+ }
-+ return $trailer;
-+}
-+
-+sub config_bool
-+{
-+ my ($configs, $wanted) = @_;
-+ my $val = $configs->{$wanted} || 'n';
-+ return (($val eq 'y') || ($val eq '1'));
-+}
-diff -Nur linux-3.18.14/sound/arm/bcm2835.c linux-rpi/sound/arm/bcm2835.c
---- linux-3.18.14/sound/arm/bcm2835.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/arm/bcm2835.c 2015-05-31 14:46:14.233660949 -0500
-@@ -0,0 +1,420 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/platform_device.h>
-+
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+
-+#include "bcm2835.h"
-+
-+/* module parameters (see "Module Parameters") */
-+/* SNDRV_CARDS: maximum number of cards supported by this module */
-+static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 };
-+static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL };
-+static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 };
-+
-+/* HACKY global pointers needed for successive probes to work : ssp
-+ * But compared against the changes we will have to do in VC audio_ipc code
-+ * to export 8 audio_ipc devices as a single IPC device and then monitor all
-+ * four devices in a thread, this gets things done quickly and should be easier
-+ * to debug if we run into issues
-+ */
-+
-+static struct snd_card *g_card = NULL;
-+static bcm2835_chip_t *g_chip = NULL;
-+
-+static int snd_bcm2835_free(bcm2835_chip_t * chip)
-+{
-+ kfree(chip);
-+ return 0;
-+}
-+
-+/* component-destructor
-+ * (see "Management of Cards and Components")
-+ */
-+static int snd_bcm2835_dev_free(struct snd_device *device)
-+{
-+ return snd_bcm2835_free(device->device_data);
-+}
-+
-+/* chip-specific constructor
-+ * (see "Management of Cards and Components")
-+ */
-+static int snd_bcm2835_create(struct snd_card *card,
-+ struct platform_device *pdev,
-+ bcm2835_chip_t ** rchip)
-+{
-+ bcm2835_chip_t *chip;
-+ int err;
-+ static struct snd_device_ops ops = {
-+ .dev_free = snd_bcm2835_dev_free,
-+ };
-+
-+ *rchip = NULL;
-+
-+ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
-+ if (chip == NULL)
-+ return -ENOMEM;
-+
-+ chip->card = card;
-+
-+ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
-+ if (err < 0) {
-+ snd_bcm2835_free(chip);
-+ return err;
-+ }
-+
-+ *rchip = chip;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_alsa_probe(struct platform_device *pdev)
-+{
-+ static int dev;
-+ bcm2835_chip_t *chip;
-+ struct snd_card *card;
-+ int err;
-+
-+ if (dev >= MAX_SUBSTREAMS)
-+ return -ENODEV;
-+
-+ if (!enable[dev]) {
-+ dev++;
-+ return -ENOENT;
-+ }
-+
-+ if (dev > 0)
-+ goto add_register_map;
-+
-+ err = snd_card_new(NULL, index[dev], id[dev], THIS_MODULE, 0, &g_card);
-+ if (err < 0)
-+ goto out;
-+
-+ snd_card_set_dev(g_card, &pdev->dev);
-+ strcpy(g_card->driver, "bcm2835");
-+ strcpy(g_card->shortname, "bcm2835 ALSA");
-+ sprintf(g_card->longname, "%s", g_card->shortname);
-+
-+ err = snd_bcm2835_create(g_card, pdev, &chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create bcm2835 chip\n");
-+ goto out_bcm2835_create;
-+ }
-+
-+ g_chip = chip;
-+ err = snd_bcm2835_new_pcm(chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create new BCM2835 pcm device\n");
-+ goto out_bcm2835_new_pcm;
-+ }
-+
-+ err = snd_bcm2835_new_spdif_pcm(chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create new BCM2835 spdif pcm device\n");
-+ goto out_bcm2835_new_spdif;
-+ }
-+
-+ err = snd_bcm2835_new_ctl(chip);
-+ if (err < 0) {
-+ dev_err(&pdev->dev, "Failed to create new BCM2835 ctl\n");
-+ goto out_bcm2835_new_ctl;
-+ }
-+
-+add_register_map:
-+ card = g_card;
-+ chip = g_chip;
-+
-+ BUG_ON(!(card && chip));
-+
-+ chip->avail_substreams |= (1 << dev);
-+ chip->pdev[dev] = pdev;
-+
-+ if (dev == 0) {
-+ err = snd_card_register(card);
-+ if (err < 0) {
-+ dev_err(&pdev->dev,
-+ "Failed to register bcm2835 ALSA card \n");
-+ goto out_card_register;
-+ }
-+ platform_set_drvdata(pdev, card);
-+ audio_info("bcm2835 ALSA card created!\n");
-+ } else {
-+ audio_info("bcm2835 ALSA chip created!\n");
-+ platform_set_drvdata(pdev, (void *)dev);
-+ }
-+
-+ dev++;
-+
-+ return 0;
-+
-+out_card_register:
-+out_bcm2835_new_ctl:
-+out_bcm2835_new_spdif:
-+out_bcm2835_new_pcm:
-+out_bcm2835_create:
-+ BUG_ON(!g_card);
-+ if (snd_card_free(g_card))
-+ dev_err(&pdev->dev, "Failed to free Registered alsa card\n");
-+ g_card = NULL;
-+out:
-+ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */
-+ dev_err(&pdev->dev, "BCM2835 ALSA Probe failed !!\n");
-+ return err;
-+}
-+
-+static int snd_bcm2835_alsa_remove(struct platform_device *pdev)
-+{
-+ uint32_t idx;
-+ void *drv_data;
-+
-+ drv_data = platform_get_drvdata(pdev);
-+
-+ if (drv_data == (void *)g_card) {
-+ /* This is the card device */
-+ snd_card_free((struct snd_card *)drv_data);
-+ g_card = NULL;
-+ g_chip = NULL;
-+ } else {
-+ idx = (uint32_t) drv_data;
-+ if (g_card != NULL) {
-+ BUG_ON(!g_chip);
-+ /* We pass chip device numbers in audio ipc devices
-+ * other than the one we registered our card with
-+ */
-+ idx = (uint32_t) drv_data;
-+ BUG_ON(!idx || idx > MAX_SUBSTREAMS);
-+ g_chip->avail_substreams &= ~(1 << idx);
-+ /* There should be atleast one substream registered
-+ * after we are done here, as it wil be removed when
-+ * the *remove* is called for the card device
-+ */
-+ BUG_ON(!g_chip->avail_substreams);
-+ }
-+ }
-+
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM
-+static int snd_bcm2835_alsa_suspend(struct platform_device *pdev,
-+ pm_message_t state)
-+{
-+ return 0;
-+}
-+
-+static int snd_bcm2835_alsa_resume(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+
-+#endif
-+
-+static struct platform_driver bcm2835_alsa0_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD0",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa1_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD1",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa2_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD2",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa3_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD3",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa4_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD4",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa5_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD5",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa6_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD6",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static struct platform_driver bcm2835_alsa7_driver = {
-+ .probe = snd_bcm2835_alsa_probe,
-+ .remove = snd_bcm2835_alsa_remove,
-+#ifdef CONFIG_PM
-+ .suspend = snd_bcm2835_alsa_suspend,
-+ .resume = snd_bcm2835_alsa_resume,
-+#endif
-+ .driver = {
-+ .name = "bcm2835_AUD7",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int bcm2835_alsa_device_init(void)
-+{
-+ int err;
-+ err = platform_driver_register(&bcm2835_alsa0_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto out;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa1_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_0;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa2_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_1;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa3_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_2;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa4_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_3;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa5_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_4;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa6_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_5;
-+ }
-+
-+ err = platform_driver_register(&bcm2835_alsa7_driver);
-+ if (err) {
-+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err);
-+ goto unregister_6;
-+ }
-+
-+ return 0;
-+
-+unregister_6:
-+ platform_driver_unregister(&bcm2835_alsa6_driver);
-+unregister_5:
-+ platform_driver_unregister(&bcm2835_alsa5_driver);
-+unregister_4:
-+ platform_driver_unregister(&bcm2835_alsa4_driver);
-+unregister_3:
-+ platform_driver_unregister(&bcm2835_alsa3_driver);
-+unregister_2:
-+ platform_driver_unregister(&bcm2835_alsa2_driver);
-+unregister_1:
-+ platform_driver_unregister(&bcm2835_alsa1_driver);
-+unregister_0:
-+ platform_driver_unregister(&bcm2835_alsa0_driver);
-+out:
-+ return err;
-+}
-+
-+static void bcm2835_alsa_device_exit(void)
-+{
-+ platform_driver_unregister(&bcm2835_alsa0_driver);
-+ platform_driver_unregister(&bcm2835_alsa1_driver);
-+ platform_driver_unregister(&bcm2835_alsa2_driver);
-+ platform_driver_unregister(&bcm2835_alsa3_driver);
-+ platform_driver_unregister(&bcm2835_alsa4_driver);
-+ platform_driver_unregister(&bcm2835_alsa5_driver);
-+ platform_driver_unregister(&bcm2835_alsa6_driver);
-+ platform_driver_unregister(&bcm2835_alsa7_driver);
-+}
-+
-+late_initcall(bcm2835_alsa_device_init);
-+module_exit(bcm2835_alsa_device_exit);
-+
-+MODULE_AUTHOR("Dom Cobley");
-+MODULE_DESCRIPTION("Alsa driver for BCM2835 chip");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:bcm2835_alsa");
-diff -Nur linux-3.18.14/sound/arm/bcm2835-ctl.c linux-rpi/sound/arm/bcm2835-ctl.c
---- linux-3.18.14/sound/arm/bcm2835-ctl.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/arm/bcm2835-ctl.c 2015-05-31 14:46:14.233660949 -0500
-@@ -0,0 +1,323 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/platform_device.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/jiffies.h>
-+#include <linux/slab.h>
-+#include <linux/time.h>
-+#include <linux/wait.h>
-+#include <linux/delay.h>
-+#include <linux/moduleparam.h>
-+#include <linux/sched.h>
-+
-+#include <sound/core.h>
-+#include <sound/control.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/rawmidi.h>
-+#include <sound/initval.h>
-+#include <sound/tlv.h>
-+#include <sound/asoundef.h>
-+
-+#include "bcm2835.h"
-+
-+/* volume maximum and minimum in terms of 0.01dB */
-+#define CTRL_VOL_MAX 400
-+#define CTRL_VOL_MIN -10239 /* originally -10240 */
-+
-+
-+static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ audio_info(" ... IN\n");
-+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) {
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = CTRL_VOL_MIN;
-+ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) {
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = 1;
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) {
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+ uinfo->count = 1;
-+ uinfo->value.integer.min = 0;
-+ uinfo->value.integer.max = AUDIO_DEST_MAX-1;
-+ }
-+ audio_info(" ... OUT\n");
-+ return 0;
-+}
-+
-+/* toggles mute on or off depending on the value of nmute, and returns
-+ * 1 if the mute value was changed, otherwise 0
-+ */
-+static int toggle_mute(struct bcm2835_chip *chip, int nmute)
-+{
-+ /* if settings are ok, just return 0 */
-+ if(chip->mute == nmute)
-+ return 0;
-+
-+ /* if the sound is muted then we need to unmute */
-+ if(chip->mute == CTRL_VOL_MUTE)
-+ {
-+ chip->volume = chip->old_volume; /* copy the old volume back */
-+ audio_info("Unmuting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume);
-+ }
-+ else /* otherwise we mute */
-+ {
-+ chip->old_volume = chip->volume;
-+ chip->volume = 26214; /* set volume to minimum level AKA mute */
-+ audio_info("Muting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume);
-+ }
-+
-+ chip->mute = nmute;
-+ return 1;
-+}
-+
-+static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+
-+ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK));
-+
-+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME)
-+ ucontrol->value.integer.value[0] = chip2alsa(chip->volume);
-+ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE)
-+ ucontrol->value.integer.value[0] = chip->mute;
-+ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE)
-+ ucontrol->value.integer.value[0] = chip->dest;
-+
-+ return 0;
-+}
-+
-+static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ int changed = 0;
-+
-+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) {
-+ audio_info("Volume change attempted.. volume = %d new_volume = %d\n", chip->volume, (int)ucontrol->value.integer.value[0]);
-+ if (chip->mute == CTRL_VOL_MUTE) {
-+ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */
-+ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */
-+ }
-+ if (changed
-+ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) {
-+
-+ chip->volume = alsa2chip(ucontrol->value.integer.value[0]);
-+ changed = 1;
-+ }
-+
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) {
-+ /* Now implemented */
-+ audio_info(" Mute attempted\n");
-+ changed = toggle_mute(chip, ucontrol->value.integer.value[0]);
-+
-+ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) {
-+ if (ucontrol->value.integer.value[0] != chip->dest) {
-+ chip->dest = ucontrol->value.integer.value[0];
-+ changed = 1;
-+ }
-+ }
-+
-+ if (changed) {
-+ if (bcm2835_audio_set_ctls(chip))
-+ printk(KERN_ERR "Failed to set ALSA controls..\n");
-+ }
-+
-+ return changed;
-+}
-+
-+static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1);
-+
-+static struct snd_kcontrol_new snd_bcm2835_ctl[] = {
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "PCM Playback Volume",
-+ .index = 0,
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ,
-+ .private_value = PCM_PLAYBACK_VOLUME,
-+ .info = snd_bcm2835_ctl_info,
-+ .get = snd_bcm2835_ctl_get,
-+ .put = snd_bcm2835_ctl_put,
-+ .count = 1,
-+ .tlv = {.p = snd_bcm2835_db_scale}
-+ },
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "PCM Playback Switch",
-+ .index = 0,
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
-+ .private_value = PCM_PLAYBACK_MUTE,
-+ .info = snd_bcm2835_ctl_info,
-+ .get = snd_bcm2835_ctl_get,
-+ .put = snd_bcm2835_ctl_put,
-+ .count = 1,
-+ },
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+ .name = "PCM Playback Route",
-+ .index = 0,
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
-+ .private_value = PCM_PLAYBACK_DEVICE,
-+ .info = snd_bcm2835_ctl_info,
-+ .get = snd_bcm2835_ctl_get,
-+ .put = snd_bcm2835_ctl_put,
-+ .count = 1,
-+ },
-+};
-+
-+static int snd_bcm2835_spdif_default_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+ uinfo->count = 1;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_default_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ int i;
-+
-+ for (i = 0; i < 4; i++)
-+ ucontrol->value.iec958.status[i] =
-+ (chip->spdif_status >> (i * 8)) && 0xff;
-+
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_default_put(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ unsigned int val = 0;
-+ int i, change;
-+
-+ for (i = 0; i < 4; i++)
-+ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
-+
-+ change = val != chip->spdif_status;
-+ chip->spdif_status = val;
-+
-+ return change;
-+}
-+
-+static int snd_bcm2835_spdif_mask_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+ uinfo->count = 1;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_mask_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ /* bcm2835 supports only consumer mode and sets all other format flags
-+ * automatically. So the only thing left is signalling non-audio
-+ * content */
-+ ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_stream_info(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_info *uinfo)
-+{
-+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+ uinfo->count = 1;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_stream_get(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ int i;
-+
-+ for (i = 0; i < 4; i++)
-+ ucontrol->value.iec958.status[i] =
-+ (chip->spdif_status >> (i * 8)) & 0xff;
-+ return 0;
-+}
-+
-+static int snd_bcm2835_spdif_stream_put(struct snd_kcontrol *kcontrol,
-+ struct snd_ctl_elem_value *ucontrol)
-+{
-+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol);
-+ unsigned int val = 0;
-+ int i, change;
-+
-+ for (i = 0; i < 4; i++)
-+ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
-+ change = val != chip->spdif_status;
-+ chip->spdif_status = val;
-+
-+ return change;
-+}
-+
-+static struct snd_kcontrol_new snd_bcm2835_spdif[] = {
-+ {
-+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
-+ .info = snd_bcm2835_spdif_default_info,
-+ .get = snd_bcm2835_spdif_default_get,
-+ .put = snd_bcm2835_spdif_default_put
-+ },
-+ {
-+ .access = SNDRV_CTL_ELEM_ACCESS_READ,
-+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
-+ .info = snd_bcm2835_spdif_mask_info,
-+ .get = snd_bcm2835_spdif_mask_get,
-+ },
-+ {
-+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
-+ SNDRV_CTL_ELEM_ACCESS_INACTIVE,
-+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
-+ .info = snd_bcm2835_spdif_stream_info,
-+ .get = snd_bcm2835_spdif_stream_get,
-+ .put = snd_bcm2835_spdif_stream_put,
-+ },
-+};
-+
-+int snd_bcm2835_new_ctl(bcm2835_chip_t * chip)
-+{
-+ int err;
-+ unsigned int idx;
-+
-+ strcpy(chip->card->mixername, "Broadcom Mixer");
-+ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) {
-+ err =
-+ snd_ctl_add(chip->card,
-+ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip));
-+ if (err < 0)
-+ return err;
-+ }
-+ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_spdif); idx++) {
-+ err = snd_ctl_add(chip->card,
-+ snd_ctl_new1(&snd_bcm2835_spdif[idx], chip));
-+ if (err < 0)
-+ return err;
-+ }
-+ return 0;
-+}
-diff -Nur linux-3.18.14/sound/arm/bcm2835.h linux-rpi/sound/arm/bcm2835.h
---- linux-3.18.14/sound/arm/bcm2835.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/arm/bcm2835.h 2015-05-31 14:46:14.233660949 -0500
-@@ -0,0 +1,167 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef __SOUND_ARM_BCM2835_H
-+#define __SOUND_ARM_BCM2835_H
-+
-+#include <linux/device.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/wait.h>
-+#include <sound/core.h>
-+#include <sound/initval.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/pcm-indirect.h>
-+#include <linux/workqueue.h>
-+
-+/*
-+#define AUDIO_DEBUG_ENABLE
-+#define AUDIO_VERBOSE_DEBUG_ENABLE
-+*/
-+
-+/* Debug macros */
-+
-+#ifdef AUDIO_DEBUG_ENABLE
-+#ifdef AUDIO_VERBOSE_DEBUG_ENABLE
-+
-+#define audio_debug(fmt, arg...) \
-+ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define audio_info(fmt, arg...) \
-+ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#else
-+
-+#define audio_debug(fmt, arg...)
-+
-+#define audio_info(fmt, arg...)
-+
-+#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */
-+
-+#else
-+
-+#define audio_debug(fmt, arg...)
-+
-+#define audio_info(fmt, arg...)
-+
-+#endif /* AUDIO_DEBUG_ENABLE */
-+
-+#define audio_error(fmt, arg...) \
-+ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define audio_warning(fmt, arg...) \
-+ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define audio_alert(fmt, arg...) \
-+ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg)
-+
-+#define MAX_SUBSTREAMS (8)
-+#define AVAIL_SUBSTREAMS_MASK (0xff)
-+enum {
-+ CTRL_VOL_MUTE,
-+ CTRL_VOL_UNMUTE
-+};
-+
-+/* macros for alsa2chip and chip2alsa, instead of functions */
-+
-+#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */
-+#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */
-+
-+/* Some constants for values .. */
-+typedef enum {
-+ AUDIO_DEST_AUTO = 0,
-+ AUDIO_DEST_HEADPHONES = 1,
-+ AUDIO_DEST_HDMI = 2,
-+ AUDIO_DEST_MAX,
-+} SND_BCM2835_ROUTE_T;
-+
-+typedef enum {
-+ PCM_PLAYBACK_VOLUME,
-+ PCM_PLAYBACK_MUTE,
-+ PCM_PLAYBACK_DEVICE,
-+} SND_BCM2835_CTRL_T;
-+
-+/* definition of the chip-specific record */
-+typedef struct bcm2835_chip {
-+ struct snd_card *card;
-+ struct snd_pcm *pcm;
-+ struct snd_pcm *pcm_spdif;
-+ /* Bitmat for valid reg_base and irq numbers */
-+ uint32_t avail_substreams;
-+ struct platform_device *pdev[MAX_SUBSTREAMS];
-+ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS];
-+
-+ int volume;
-+ int old_volume; /* stores the volume value whist muted */
-+ int dest;
-+ int mute;
-+
-+ unsigned int opened;
-+ unsigned int spdif_status;
-+ struct mutex audio_mutex;
-+} bcm2835_chip_t;
-+
-+typedef struct bcm2835_alsa_stream {
-+ bcm2835_chip_t *chip;
-+ struct snd_pcm_substream *substream;
-+ struct snd_pcm_indirect pcm_indirect;
-+
-+ struct semaphore buffers_update_sem;
-+ struct semaphore control_sem;
-+ spinlock_t lock;
-+ volatile uint32_t control;
-+ volatile uint32_t status;
-+
-+ int open;
-+ int running;
-+ int draining;
-+
-+ int channels;
-+ int params_rate;
-+ int pcm_format_width;
-+
-+ unsigned int pos;
-+ unsigned int buffer_size;
-+ unsigned int period_size;
-+
-+ uint32_t enable_fifo_irq;
-+ irq_handler_t fifo_irq_handler;
-+
-+ atomic_t retrieved;
-+ struct opaque_AUDIO_INSTANCE_T *instance;
-+ struct workqueue_struct *my_wq;
-+ int idx;
-+} bcm2835_alsa_stream_t;
-+
-+int snd_bcm2835_new_ctl(bcm2835_chip_t * chip);
-+int snd_bcm2835_new_pcm(bcm2835_chip_t * chip);
-+int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip);
-+
-+int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream,
-+ uint32_t channels, uint32_t samplerate,
-+ uint32_t bps);
-+int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream);
-+int bcm2835_audio_set_ctls(bcm2835_chip_t * chip);
-+int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count,
-+ void *src);
-+uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream);
-+void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream);
-+void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream);
-+
-+#endif /* __SOUND_ARM_BCM2835_H */
-diff -Nur linux-3.18.14/sound/arm/bcm2835-pcm.c linux-rpi/sound/arm/bcm2835-pcm.c
---- linux-3.18.14/sound/arm/bcm2835-pcm.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/arm/bcm2835-pcm.c 2015-05-31 14:46:14.233660949 -0500
-@@ -0,0 +1,557 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+
-+#include <sound/asoundef.h>
-+
-+#include "bcm2835.h"
-+
-+/* hardware definition */
-+static struct snd_pcm_hardware snd_bcm2835_playback_hw = {
-+ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
-+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
-+ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
-+ .rate_min = 8000,
-+ .rate_max = 48000,
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .buffer_bytes_max = 128 * 1024,
-+ .period_bytes_min = 1 * 1024,
-+ .period_bytes_max = 128 * 1024,
-+ .periods_min = 1,
-+ .periods_max = 128,
-+};
-+
-+static struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = {
-+ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
-+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 |
-+ SNDRV_PCM_RATE_48000,
-+ .rate_min = 44100,
-+ .rate_max = 48000,
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .buffer_bytes_max = 128 * 1024,
-+ .period_bytes_min = 1 * 1024,
-+ .period_bytes_max = 128 * 1024,
-+ .periods_min = 1,
-+ .periods_max = 128,
-+};
-+
-+static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime)
-+{
-+ audio_info("Freeing up alsa stream here ..\n");
-+ if (runtime->private_data)
-+ kfree(runtime->private_data);
-+ runtime->private_data = NULL;
-+}
-+
-+static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id)
-+{
-+ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id;
-+ uint32_t consumed = 0;
-+ int new_period = 0;
-+
-+ audio_info(" .. IN\n");
-+
-+ audio_info("alsa_stream=%p substream=%p\n", alsa_stream,
-+ alsa_stream ? alsa_stream->substream : 0);
-+
-+ if (alsa_stream->open)
-+ consumed = bcm2835_audio_retrieve_buffers(alsa_stream);
-+
-+ /* We get called only if playback was triggered, So, the number of buffers we retrieve in
-+ * each iteration are the buffers that have been played out already
-+ */
-+
-+ if (alsa_stream->period_size) {
-+ if ((alsa_stream->pos / alsa_stream->period_size) !=
-+ ((alsa_stream->pos + consumed) / alsa_stream->period_size))
-+ new_period = 1;
-+ }
-+ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n",
-+ alsa_stream->pos,
-+ consumed,
-+ alsa_stream->buffer_size,
-+ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods),
-+ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr),
-+ new_period);
-+ if (alsa_stream->buffer_size) {
-+ alsa_stream->pos += consumed &~ (1<<30);
-+ alsa_stream->pos %= alsa_stream->buffer_size;
-+ }
-+
-+ if (alsa_stream->substream) {
-+ if (new_period)
-+ snd_pcm_period_elapsed(alsa_stream->substream);
-+ } else {
-+ audio_warning(" unexpected NULL substream\n");
-+ }
-+ audio_info(" .. OUT\n");
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/* open callback */
-+static int snd_bcm2835_playback_open_generic(
-+ struct snd_pcm_substream *substream, int spdif)
-+{
-+ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream);
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+ int idx;
-+ int err;
-+
-+ audio_info(" .. IN (%d)\n", substream->number);
-+
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ audio_info("Alsa open (%d)\n", substream->number);
-+ idx = substream->number;
-+
-+ if (spdif && chip->opened != 0) {
-+ err = -EBUSY;
-+ goto out;
-+ }
-+ else if (!spdif && (chip->opened & (1 << idx))) {
-+ err = -EBUSY;
-+ goto out;
-+ }
-+ if (idx > MAX_SUBSTREAMS) {
-+ audio_error
-+ ("substream(%d) device doesn't exist max(%d) substreams allowed\n",
-+ idx, MAX_SUBSTREAMS);
-+ err = -ENODEV;
-+ goto out;
-+ }
-+
-+ /* Check if we are ready */
-+ if (!(chip->avail_substreams & (1 << idx))) {
-+ /* We are not ready yet */
-+ audio_error("substream(%d) device is not ready yet\n", idx);
-+ err = -EAGAIN;
-+ goto out;
-+ }
-+
-+ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL);
-+ if (alsa_stream == NULL) {
-+ err = -ENOMEM;
-+ goto out;
-+ }
-+
-+ /* Initialise alsa_stream */
-+ alsa_stream->chip = chip;
-+ alsa_stream->substream = substream;
-+ alsa_stream->idx = idx;
-+
-+ sema_init(&alsa_stream->buffers_update_sem, 0);
-+ sema_init(&alsa_stream->control_sem, 0);
-+ spin_lock_init(&alsa_stream->lock);
-+
-+ /* Enabled in start trigger, called on each "fifo irq" after that */
-+ alsa_stream->enable_fifo_irq = 0;
-+ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq;
-+
-+ err = bcm2835_audio_open(alsa_stream);
-+ if (err != 0) {
-+ kfree(alsa_stream);
-+ goto out;
-+ }
-+ runtime->private_data = alsa_stream;
-+ runtime->private_free = snd_bcm2835_playback_free;
-+ if (spdif) {
-+ runtime->hw = snd_bcm2835_playback_spdif_hw;
-+ } else {
-+ /* clear spdif status, as we are not in spdif mode */
-+ chip->spdif_status = 0;
-+ runtime->hw = snd_bcm2835_playback_hw;
-+ }
-+ /* minimum 16 bytes alignment (for vchiq bulk transfers) */
-+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
-+ 16);
-+
-+ chip->alsa_stream[idx] = alsa_stream;
-+
-+ chip->opened |= (1 << idx);
-+ alsa_stream->open = 1;
-+ alsa_stream->draining = 1;
-+
-+out:
-+ mutex_unlock(&chip->audio_mutex);
-+
-+ audio_info(" .. OUT =%d\n", err);
-+
-+ return err;
-+}
-+
-+static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream)
-+{
-+ return snd_bcm2835_playback_open_generic(substream, 0);
-+}
-+
-+static int snd_bcm2835_playback_spdif_open(struct snd_pcm_substream *substream)
-+{
-+ return snd_bcm2835_playback_open_generic(substream, 1);
-+}
-+
-+/* close callback */
-+static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream)
-+{
-+ /* the hardware-specific codes will be here */
-+
-+ bcm2835_chip_t *chip;
-+ struct snd_pcm_runtime *runtime;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+
-+ audio_info(" .. IN\n");
-+
-+ chip = snd_pcm_substream_chip(substream);
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ runtime = substream->runtime;
-+ alsa_stream = runtime->private_data;
-+
-+ audio_info("Alsa close\n");
-+
-+ /*
-+ * Call stop if it's still running. This happens when app
-+ * is force killed and we don't get a stop trigger.
-+ */
-+ if (alsa_stream->running) {
-+ int err;
-+ err = bcm2835_audio_stop(alsa_stream);
-+ alsa_stream->running = 0;
-+ if (err != 0)
-+ audio_error(" Failed to STOP alsa device\n");
-+ }
-+
-+ alsa_stream->period_size = 0;
-+ alsa_stream->buffer_size = 0;
-+
-+ if (alsa_stream->open) {
-+ alsa_stream->open = 0;
-+ bcm2835_audio_close(alsa_stream);
-+ }
-+ if (alsa_stream->chip)
-+ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL;
-+ /*
-+ * Do not free up alsa_stream here, it will be freed up by
-+ * runtime->private_free callback we registered in *_open above
-+ */
-+
-+ chip->opened &= ~(1 << substream->number);
-+
-+ mutex_unlock(&chip->audio_mutex);
-+ audio_info(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+/* hw_params callback */
-+static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+
-+ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
-+ if (err < 0) {
-+ audio_error
-+ (" pcm_lib_malloc failed to allocated pages for buffers\n");
-+ return err;
-+ }
-+
-+ alsa_stream->channels = params_channels(params);
-+ alsa_stream->params_rate = params_rate(params);
-+ alsa_stream->pcm_format_width = snd_pcm_format_width(params_format (params));
-+ audio_info(" .. OUT\n");
-+
-+ return err;
-+}
-+
-+/* hw_free callback */
-+static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream)
-+{
-+ audio_info(" .. IN\n");
-+ return snd_pcm_lib_free_pages(substream);
-+}
-+
-+/* prepare callback */
-+static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream)
-+{
-+ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream);
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ int channels;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+
-+ /* notify the vchiq that it should enter spdif passthrough mode by
-+ * setting channels=0 (see
-+ * https://github.com/raspberrypi/linux/issues/528) */
-+ if (chip->spdif_status & IEC958_AES0_NONAUDIO)
-+ channels = 0;
-+ else
-+ channels = alsa_stream->channels;
-+
-+ err = bcm2835_audio_set_params(alsa_stream, channels,
-+ alsa_stream->params_rate,
-+ alsa_stream->pcm_format_width);
-+ if (err < 0) {
-+ audio_error(" error setting hw params\n");
-+ }
-+
-+ bcm2835_audio_setup(alsa_stream);
-+
-+ /* in preparation of the stream, set the controls (volume level) of the stream */
-+ bcm2835_audio_set_ctls(alsa_stream->chip);
-+
-+
-+ memset(&alsa_stream->pcm_indirect, 0, sizeof(alsa_stream->pcm_indirect));
-+
-+ alsa_stream->pcm_indirect.hw_buffer_size =
-+ alsa_stream->pcm_indirect.sw_buffer_size =
-+ snd_pcm_lib_buffer_bytes(substream);
-+
-+ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream);
-+ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream);
-+ alsa_stream->pos = 0;
-+
-+ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n",
-+ alsa_stream->buffer_size, alsa_stream->period_size,
-+ alsa_stream->pos, runtime->frame_bits);
-+
-+ audio_info(" .. OUT\n");
-+ return 0;
-+}
-+
-+static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream,
-+ struct snd_pcm_indirect *rec, size_t bytes)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ void *src = (void *)(substream->runtime->dma_area + rec->sw_data);
-+ int err;
-+
-+ err = bcm2835_audio_write(alsa_stream, bytes, src);
-+ if (err)
-+ audio_error(" Failed to transfer to alsa device (%d)\n", err);
-+
-+}
-+
-+static int snd_bcm2835_pcm_ack(struct snd_pcm_substream *substream)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ struct snd_pcm_indirect *pcm_indirect = &alsa_stream->pcm_indirect;
-+
-+ pcm_indirect->hw_queue_size = runtime->hw.buffer_bytes_max;
-+ snd_pcm_indirect_playback_transfer(substream, pcm_indirect,
-+ snd_bcm2835_pcm_transfer);
-+ return 0;
-+}
-+
-+/* trigger callback */
-+static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+ int err = 0;
-+
-+ audio_info(" .. IN\n");
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n",
-+ alsa_stream->running);
-+ if (!alsa_stream->running) {
-+ err = bcm2835_audio_start(alsa_stream);
-+ if (err == 0) {
-+ alsa_stream->pcm_indirect.hw_io =
-+ alsa_stream->pcm_indirect.hw_data =
-+ bytes_to_frames(runtime,
-+ alsa_stream->pos);
-+ substream->ops->ack(substream);
-+ alsa_stream->running = 1;
-+ alsa_stream->draining = 1;
-+ } else {
-+ audio_error(" Failed to START alsa device (%d)\n", err);
-+ }
-+ }
-+ break;
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ audio_debug
-+ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n",
-+ alsa_stream->running, runtime->status->state == SNDRV_PCM_STATE_DRAINING);
-+ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) {
-+ audio_info("DRAINING\n");
-+ alsa_stream->draining = 1;
-+ } else {
-+ audio_info("DROPPING\n");
-+ alsa_stream->draining = 0;
-+ }
-+ if (alsa_stream->running) {
-+ err = bcm2835_audio_stop(alsa_stream);
-+ if (err != 0)
-+ audio_error(" Failed to STOP alsa device (%d)\n", err);
-+ alsa_stream->running = 0;
-+ }
-+ break;
-+ default:
-+ err = -EINVAL;
-+ }
-+
-+ audio_info(" .. OUT\n");
-+ return err;
-+}
-+
-+/* pointer callback */
-+static snd_pcm_uframes_t
-+snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream)
-+{
-+ struct snd_pcm_runtime *runtime = substream->runtime;
-+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data;
-+
-+ audio_info(" .. IN\n");
-+
-+ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0,
-+ frames_to_bytes(runtime, runtime->status->hw_ptr),
-+ frames_to_bytes(runtime, runtime->control->appl_ptr),
-+ alsa_stream->pos);
-+
-+ audio_info(" .. OUT\n");
-+ return snd_pcm_indirect_playback_pointer(substream,
-+ &alsa_stream->pcm_indirect,
-+ alsa_stream->pos);
-+}
-+
-+static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream,
-+ unsigned int cmd, void *arg)
-+{
-+ int ret = snd_pcm_lib_ioctl(substream, cmd, arg);
-+ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream,
-+ cmd, arg, arg ? *(unsigned *)arg : 0, ret);
-+ return ret;
-+}
-+
-+/* operators */
-+static struct snd_pcm_ops snd_bcm2835_playback_ops = {
-+ .open = snd_bcm2835_playback_open,
-+ .close = snd_bcm2835_playback_close,
-+ .ioctl = snd_bcm2835_pcm_lib_ioctl,
-+ .hw_params = snd_bcm2835_pcm_hw_params,
-+ .hw_free = snd_bcm2835_pcm_hw_free,
-+ .prepare = snd_bcm2835_pcm_prepare,
-+ .trigger = snd_bcm2835_pcm_trigger,
-+ .pointer = snd_bcm2835_pcm_pointer,
-+ .ack = snd_bcm2835_pcm_ack,
-+};
-+
-+static struct snd_pcm_ops snd_bcm2835_playback_spdif_ops = {
-+ .open = snd_bcm2835_playback_spdif_open,
-+ .close = snd_bcm2835_playback_close,
-+ .ioctl = snd_bcm2835_pcm_lib_ioctl,
-+ .hw_params = snd_bcm2835_pcm_hw_params,
-+ .hw_free = snd_bcm2835_pcm_hw_free,
-+ .prepare = snd_bcm2835_pcm_prepare,
-+ .trigger = snd_bcm2835_pcm_trigger,
-+ .pointer = snd_bcm2835_pcm_pointer,
-+ .ack = snd_bcm2835_pcm_ack,
-+};
-+
-+/* create a pcm device */
-+int snd_bcm2835_new_pcm(bcm2835_chip_t * chip)
-+{
-+ struct snd_pcm *pcm;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+ mutex_init(&chip->audio_mutex);
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ err =
-+ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm);
-+ if (err < 0)
-+ goto out;
-+ pcm->private_data = chip;
-+ strcpy(pcm->name, "bcm2835 ALSA");
-+ chip->pcm = pcm;
-+ chip->dest = AUDIO_DEST_AUTO;
-+ chip->volume = alsa2chip(0);
-+ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */
-+ /* set operators */
-+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
-+ &snd_bcm2835_playback_ops);
-+
-+ /* pre-allocation of buffers */
-+ /* NOTE: this may fail */
-+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
-+ snd_dma_continuous_data
-+ (GFP_KERNEL), 64 * 1024,
-+ 64 * 1024);
-+
-+out:
-+ mutex_unlock(&chip->audio_mutex);
-+ audio_info(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip)
-+{
-+ struct snd_pcm *pcm;
-+ int err;
-+
-+ audio_info(" .. IN\n");
-+ if(mutex_lock_interruptible(&chip->audio_mutex))
-+ {
-+ audio_error("Interrupted whilst waiting for lock\n");
-+ return -EINTR;
-+ }
-+ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 1, 1, 0, &pcm);
-+ if (err < 0)
-+ goto out;
-+
-+ pcm->private_data = chip;
-+ strcpy(pcm->name, "bcm2835 IEC958/HDMI");
-+ chip->pcm_spdif = pcm;
-+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
-+ &snd_bcm2835_playback_spdif_ops);
-+
-+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
-+ snd_dma_continuous_data (GFP_KERNEL),
-+ 64 * 1024, 64 * 1024);
-+out:
-+ mutex_unlock(&chip->audio_mutex);
-+ audio_info(" .. OUT\n");
-+
-+ return 0;
-+}
-diff -Nur linux-3.18.14/sound/arm/bcm2835-vchiq.c linux-rpi/sound/arm/bcm2835-vchiq.c
---- linux-3.18.14/sound/arm/bcm2835-vchiq.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/arm/bcm2835-vchiq.c 2015-05-31 14:46:14.233660949 -0500
-@@ -0,0 +1,902 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/device.h>
-+#include <sound/core.h>
-+#include <sound/initval.h>
-+#include <sound/pcm.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include <linux/fs.h>
-+#include <linux/file.h>
-+#include <linux/mm.h>
-+#include <linux/syscalls.h>
-+#include <asm/uaccess.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/atomic.h>
-+#include <linux/module.h>
-+#include <linux/completion.h>
-+
-+#include "bcm2835.h"
-+
-+/* ---- Include Files -------------------------------------------------------- */
-+
-+#include "interface/vchi/vchi.h"
-+#include "vc_vchi_audioserv_defs.h"
-+
-+/* ---- Private Constants and Types ------------------------------------------ */
-+
-+#define BCM2835_AUDIO_STOP 0
-+#define BCM2835_AUDIO_START 1
-+#define BCM2835_AUDIO_WRITE 2
-+
-+/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */
-+#ifdef AUDIO_DEBUG_ENABLE
-+ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+#else
-+ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg)
-+ #define LOG_WARN( fmt, arg... )
-+ #define LOG_INFO( fmt, arg... )
-+ #define LOG_DBG( fmt, arg... )
-+#endif
-+
-+typedef struct opaque_AUDIO_INSTANCE_T {
-+ uint32_t num_connections;
-+ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
-+ struct completion msg_avail_comp;
-+ struct mutex vchi_mutex;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+ int32_t result;
-+ short peer_version;
-+} AUDIO_INSTANCE_T;
-+
-+bool force_bulk = false;
-+
-+/* ---- Private Variables ---------------------------------------------------- */
-+
-+/* ---- Private Function Prototypes ------------------------------------------ */
-+
-+/* ---- Private Functions ---------------------------------------------------- */
-+
-+static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream);
-+static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream);
-+static int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream,
-+ uint32_t count, void *src);
-+
-+typedef struct {
-+ struct work_struct my_work;
-+ bcm2835_alsa_stream_t *alsa_stream;
-+ int cmd;
-+ void *src;
-+ uint32_t count;
-+} my_work_t;
-+
-+static void my_wq_function(struct work_struct *work)
-+{
-+ my_work_t *w = (my_work_t *) work;
-+ int ret = -9;
-+ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->cmd);
-+ switch (w->cmd) {
-+ case BCM2835_AUDIO_START:
-+ ret = bcm2835_audio_start_worker(w->alsa_stream);
-+ break;
-+ case BCM2835_AUDIO_STOP:
-+ ret = bcm2835_audio_stop_worker(w->alsa_stream);
-+ break;
-+ case BCM2835_AUDIO_WRITE:
-+ ret = bcm2835_audio_write_worker(w->alsa_stream, w->count,
-+ w->src);
-+ break;
-+ default:
-+ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->cmd);
-+ break;
-+ }
-+ kfree((void *)work);
-+ LOG_DBG(" .. OUT %d\n", ret);
-+}
-+
-+int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ int ret = -1;
-+ LOG_DBG(" .. IN\n");
-+ if (alsa_stream->my_wq) {
-+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
-+ /*--- Queue some work (item 1) ---*/
-+ if (work) {
-+ INIT_WORK((struct work_struct *)work, my_wq_function);
-+ work->alsa_stream = alsa_stream;
-+ work->cmd = BCM2835_AUDIO_START;
-+ if (queue_work
-+ (alsa_stream->my_wq, (struct work_struct *)work))
-+ ret = 0;
-+ } else
-+ LOG_ERR(" .. Error: NULL work kmalloc\n");
-+ }
-+ LOG_DBG(" .. OUT %d\n", ret);
-+ return ret;
-+}
-+
-+int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ int ret = -1;
-+ LOG_DBG(" .. IN\n");
-+ if (alsa_stream->my_wq) {
-+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
-+ /*--- Queue some work (item 1) ---*/
-+ if (work) {
-+ INIT_WORK((struct work_struct *)work, my_wq_function);
-+ work->alsa_stream = alsa_stream;
-+ work->cmd = BCM2835_AUDIO_STOP;
-+ if (queue_work
-+ (alsa_stream->my_wq, (struct work_struct *)work))
-+ ret = 0;
-+ } else
-+ LOG_ERR(" .. Error: NULL work kmalloc\n");
-+ }
-+ LOG_DBG(" .. OUT %d\n", ret);
-+ return ret;
-+}
-+
-+int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream,
-+ uint32_t count, void *src)
-+{
-+ int ret = -1;
-+ LOG_DBG(" .. IN\n");
-+ if (alsa_stream->my_wq) {
-+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC);
-+ /*--- Queue some work (item 1) ---*/
-+ if (work) {
-+ INIT_WORK((struct work_struct *)work, my_wq_function);
-+ work->alsa_stream = alsa_stream;
-+ work->cmd = BCM2835_AUDIO_WRITE;
-+ work->src = src;
-+ work->count = count;
-+ if (queue_work
-+ (alsa_stream->my_wq, (struct work_struct *)work))
-+ ret = 0;
-+ } else
-+ LOG_ERR(" .. Error: NULL work kmalloc\n");
-+ }
-+ LOG_DBG(" .. OUT %d\n", ret);
-+ return ret;
-+}
-+
-+void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ alsa_stream->my_wq = alloc_workqueue("my_queue", WQ_HIGHPRI, 1);
-+ return;
-+}
-+
-+void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ if (alsa_stream->my_wq) {
-+ flush_workqueue(alsa_stream->my_wq);
-+ destroy_workqueue(alsa_stream->my_wq);
-+ alsa_stream->my_wq = NULL;
-+ }
-+ return;
-+}
-+
-+static void audio_vchi_callback(void *param,
-+ const VCHI_CALLBACK_REASON_T reason,
-+ void *msg_handle)
-+{
-+ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param;
-+ int32_t status;
-+ int32_t msg_len;
-+ VC_AUDIO_MSG_T m;
-+ LOG_DBG(" .. IN instance=%p, handle=%p, alsa=%p, reason=%d, handle=%p\n",
-+ instance, instance ? instance->vchi_handle[0] : NULL, instance ? instance->alsa_stream : NULL, reason, msg_handle);
-+
-+ if (reason != VCHI_CALLBACK_MSG_AVAILABLE) {
-+ return;
-+ }
-+ if (!instance) {
-+ LOG_ERR(" .. instance is null\n");
-+ BUG();
-+ return;
-+ }
-+ if (!instance->vchi_handle[0]) {
-+ LOG_ERR(" .. instance->vchi_handle[0] is null\n");
-+ BUG();
-+ return;
-+ }
-+ status = vchi_msg_dequeue(instance->vchi_handle[0],
-+ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE);
-+ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) {
-+ LOG_DBG
-+ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n",
-+ instance, m.u.result.success);
-+ instance->result = m.u.result.success;
-+ complete(&instance->msg_avail_comp);
-+ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) {
-+ bcm2835_alsa_stream_t *alsa_stream = instance->alsa_stream;
-+ irq_handler_t callback = (irq_handler_t) m.u.complete.callback;
-+ LOG_DBG
-+ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n",
-+ instance, m.u.complete.count);
-+ if (alsa_stream && callback) {
-+ atomic_add(m.u.complete.count, &alsa_stream->retrieved);
-+ callback(0, alsa_stream);
-+ } else {
-+ LOG_ERR(" .. unexpected alsa_stream=%p, callback=%p\n",
-+ alsa_stream, callback);
-+ }
-+ } else {
-+ LOG_ERR(" .. unexpected m.type=%d\n", m.type);
-+ }
-+ LOG_DBG(" .. OUT\n");
-+}
-+
-+static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance,
-+ VCHI_CONNECTION_T **
-+ vchi_connections,
-+ uint32_t num_connections)
-+{
-+ uint32_t i;
-+ AUDIO_INSTANCE_T *instance;
-+ int status;
-+
-+ LOG_DBG("%s: start", __func__);
-+
-+ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
-+ LOG_ERR("%s: unsupported number of connections %u (max=%u)\n",
-+ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
-+
-+ return NULL;
-+ }
-+ /* Allocate memory for this instance */
-+ instance = kmalloc(sizeof(*instance), GFP_KERNEL);
-+ if (!instance)
-+ return NULL;
-+
-+ memset(instance, 0, sizeof(*instance));
-+ instance->num_connections = num_connections;
-+
-+ /* Create a lock for exclusive, serialized VCHI connection access */
-+ mutex_init(&instance->vchi_mutex);
-+ /* Open the VCHI service connections */
-+ for (i = 0; i < num_connections; i++) {
-+ SERVICE_CREATION_T params = {
-+ VCHI_VERSION_EX(VC_AUDIOSERV_VER, VC_AUDIOSERV_MIN_VER),
-+ VC_AUDIO_SERVER_NAME, // 4cc service code
-+ vchi_connections[i], // passed in fn pointers
-+ 0, // rx fifo size (unused)
-+ 0, // tx fifo size (unused)
-+ audio_vchi_callback, // service callback
-+ instance, // service callback parameter
-+ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves
-+ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits
-+ 0 // want crc check on bulk transfers
-+ };
-+
-+ LOG_DBG("%s: about to open %i\n", __func__, i);
-+ status = vchi_service_open(vchi_instance, &params,
-+ &instance->vchi_handle[i]);
-+ LOG_DBG("%s: opened %i: %p=%d\n", __func__, i, instance->vchi_handle[i], status);
-+ if (status) {
-+ LOG_ERR
-+ ("%s: failed to open VCHI service connection (status=%d)\n",
-+ __func__, status);
-+
-+ goto err_close_services;
-+ }
-+ /* Finished with the service for now */
-+ vchi_service_release(instance->vchi_handle[i]);
-+ }
-+
-+ LOG_DBG("%s: okay\n", __func__);
-+ return instance;
-+
-+err_close_services:
-+ for (i = 0; i < instance->num_connections; i++) {
-+ LOG_ERR("%s: closing %i: %p\n", __func__, i, instance->vchi_handle[i]);
-+ if (instance->vchi_handle[i])
-+ vchi_service_close(instance->vchi_handle[i]);
-+ }
-+
-+ kfree(instance);
-+ LOG_ERR("%s: error\n", __func__);
-+
-+ return NULL;
-+}
-+
-+static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance)
-+{
-+ uint32_t i;
-+
-+ LOG_DBG(" .. IN\n");
-+
-+ if (instance == NULL) {
-+ LOG_ERR("%s: invalid handle %p\n", __func__, instance);
-+
-+ return -1;
-+ }
-+
-+ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections);
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+
-+ /* Close all VCHI service connections */
-+ for (i = 0; i < instance->num_connections; i++) {
-+ int32_t success;
-+ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]);
-+ vchi_service_use(instance->vchi_handle[i]);
-+
-+ success = vchi_service_close(instance->vchi_handle[i]);
-+ if (success != 0) {
-+ LOG_DBG
-+ ("%s: failed to close VCHI service connection (status=%d)\n",
-+ __func__, success);
-+ }
-+ }
-+
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ kfree(instance);
-+
-+ LOG_DBG(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ static VCHI_INSTANCE_T vchi_instance;
-+ static VCHI_CONNECTION_T *vchi_connection;
-+ static int initted;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO("%s: start\n", __func__);
-+ BUG_ON(instance);
-+ if (instance) {
-+ LOG_ERR("%s: VCHI instance already open (%p)\n",
-+ __func__, instance);
-+ instance->alsa_stream = alsa_stream;
-+ alsa_stream->instance = instance;
-+ ret = 0; // xxx todo -1;
-+ goto err_free_mem;
-+ }
-+
-+ /* Initialize and create a VCHI connection */
-+ if (!initted) {
-+ ret = vchi_initialise(&vchi_instance);
-+ if (ret != 0) {
-+ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+ ret = vchi_connect(NULL, 0, vchi_instance);
-+ if (ret != 0) {
-+ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)\n",
-+ __func__, ret);
-+
-+ ret = -EIO;
-+ goto err_free_mem;
-+ }
-+ initted = 1;
-+ }
-+
-+ /* Initialize an instance of the audio service */
-+ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1);
-+
-+ if (instance == NULL) {
-+ LOG_ERR("%s: failed to initialize audio service\n", __func__);
-+
-+ ret = -EPERM;
-+ goto err_free_mem;
-+ }
-+
-+ instance->alsa_stream = alsa_stream;
-+ alsa_stream->instance = instance;
-+
-+ LOG_DBG(" success !\n");
-+err_free_mem:
-+ LOG_DBG(" .. OUT\n");
-+
-+ return ret;
-+}
-+
-+int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ AUDIO_INSTANCE_T *instance;
-+ VC_AUDIO_MSG_T m;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ my_workqueue_init(alsa_stream);
-+
-+ ret = bcm2835_audio_open_connection(alsa_stream);
-+ if (ret != 0) {
-+ ret = -1;
-+ goto exit;
-+ }
-+ instance = alsa_stream->instance;
-+ LOG_DBG(" instance (%p)\n", instance);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_OPEN;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+exit:
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream,
-+ bcm2835_chip_t * chip)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO
-+ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ instance->result = -1;
-+
-+ m.type = VC_AUDIO_MSG_TYPE_CONTROL;
-+ m.u.control.dest = chip->dest;
-+ m.u.control.volume = chip->volume;
-+
-+ /* Create the message available completion */
-+ init_completion(&instance->msg_avail_comp);
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ /* We are expecting a reply from the videocore */
-+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
-+ if (ret) {
-+ LOG_DBG("%s: failed on waiting for event (status=%d)\n",
-+ __func__, success);
-+ goto unlock;
-+ }
-+
-+ if (instance->result != 0) {
-+ LOG_ERR("%s: result=%d\n", __func__, instance->result);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_set_ctls(bcm2835_chip_t * chip)
-+{
-+ int i;
-+ int ret = 0;
-+ LOG_DBG(" .. IN\n");
-+ LOG_DBG(" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume);
-+
-+ /* change ctls for all substreams */
-+ for (i = 0; i < MAX_SUBSTREAMS; i++) {
-+ if (chip->avail_substreams & (1 << i)) {
-+ if (!chip->alsa_stream[i])
-+ {
-+ LOG_DBG(" No ALSA stream available?! %i:%p (%x)\n", i, chip->alsa_stream[i], chip->avail_substreams);
-+ ret = 0;
-+ }
-+ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */
-+ (chip->alsa_stream[i], chip) != 0)
-+ {
-+ LOG_ERR("Couldn't set the controls for stream %d\n", i);
-+ ret = -1;
-+ }
-+ else LOG_DBG(" Controls set for stream %d\n", i);
-+ }
-+ }
-+ LOG_DBG(" .. OUT ret=%d\n", ret);
-+ return ret;
-+}
-+
-+int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream,
-+ uint32_t channels, uint32_t samplerate,
-+ uint32_t bps)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO
-+ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n",
-+ channels, samplerate, bps);
-+
-+ /* resend ctls - alsa_stream may not have been open when first send */
-+ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip);
-+ if (ret != 0) {
-+ LOG_ERR(" Alsa controls not supported\n");
-+ return -EINVAL;
-+ }
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ instance->result = -1;
-+
-+ m.type = VC_AUDIO_MSG_TYPE_CONFIG;
-+ m.u.config.channels = channels;
-+ m.u.config.samplerate = samplerate;
-+ m.u.config.bps = bps;
-+
-+ /* Create the message available completion */
-+ init_completion(&instance->msg_avail_comp);
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ /* We are expecting a reply from the videocore */
-+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
-+ if (ret) {
-+ LOG_DBG("%s: failed on waiting for event (status=%d)\n",
-+ __func__, success);
-+ goto unlock;
-+ }
-+
-+ if (instance->result != 0) {
-+ LOG_ERR("%s: result=%d", __func__, instance->result);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_DBG(" .. OUT\n");
-+
-+ return 0;
-+}
-+
-+static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_START;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_STOP;
-+ m.u.stop.draining = alsa_stream->draining;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+ LOG_DBG(" .. IN\n");
-+
-+ my_workqueue_quit(alsa_stream);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ m.type = VC_AUDIO_MSG_TYPE_CLOSE;
-+
-+ /* Create the message available completion */
-+ init_completion(&instance->msg_avail_comp);
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp);
-+ if (ret) {
-+ LOG_DBG("%s: failed on waiting for event (status=%d)\n",
-+ __func__, success);
-+ goto unlock;
-+ }
-+ if (instance->result != 0) {
-+ LOG_ERR("%s: failed result (status=%d)\n",
-+ __func__, instance->result);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+
-+ /* Stop the audio service */
-+ if (instance) {
-+ vc_vchi_audio_deinit(instance);
-+ alsa_stream->instance = NULL;
-+ }
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream,
-+ uint32_t count, void *src)
-+{
-+ VC_AUDIO_MSG_T m;
-+ AUDIO_INSTANCE_T *instance = alsa_stream->instance;
-+ int32_t success;
-+ int ret;
-+
-+ LOG_DBG(" .. IN\n");
-+
-+ LOG_INFO(" Writing %d bytes from %p\n", count, src);
-+
-+ if(mutex_lock_interruptible(&instance->vchi_mutex))
-+ {
-+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections);
-+ return -EINTR;
-+ }
-+ vchi_service_use(instance->vchi_handle[0]);
-+
-+ if ( instance->peer_version==0 && vchi_get_peer_version(instance->vchi_handle[0], &instance->peer_version) == 0 ) {
-+ LOG_DBG("%s: client version %d connected\n", __func__, instance->peer_version);
-+ }
-+ m.type = VC_AUDIO_MSG_TYPE_WRITE;
-+ m.u.write.count = count;
-+ // old version uses bulk, new version uses control
-+ m.u.write.max_packet = instance->peer_version < 2 || force_bulk ? 0:4000;
-+ m.u.write.callback = alsa_stream->fifo_irq_handler;
-+ m.u.write.cookie = alsa_stream;
-+ m.u.write.silence = src == NULL;
-+
-+ /* Send the message to the videocore */
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ &m, sizeof m,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+
-+ if (success != 0) {
-+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+ if (!m.u.write.silence) {
-+ if (m.u.write.max_packet == 0) {
-+ /* Send the message to the videocore */
-+ success = vchi_bulk_queue_transmit(instance->vchi_handle[0],
-+ src, count,
-+ 0 *
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED
-+ +
-+ 1 *
-+ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ,
-+ NULL);
-+ } else {
-+ while (count > 0) {
-+ int bytes = min((int)m.u.write.max_packet, (int)count);
-+ success = vchi_msg_queue(instance->vchi_handle[0],
-+ src, bytes,
-+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL);
-+ src = (char *)src + bytes;
-+ count -= bytes;
-+ }
-+ }
-+ if (success != 0) {
-+ LOG_ERR
-+ ("%s: failed on vchi_bulk_queue_transmit (status=%d)\n",
-+ __func__, success);
-+
-+ ret = -1;
-+ goto unlock;
-+ }
-+ }
-+ ret = 0;
-+
-+unlock:
-+ vchi_service_release(instance->vchi_handle[0]);
-+ mutex_unlock(&instance->vchi_mutex);
-+ LOG_DBG(" .. OUT\n");
-+ return ret;
-+}
-+
-+/**
-+ * Returns all buffers from arm->vc
-+ */
-+void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ LOG_DBG(" .. IN\n");
-+ LOG_DBG(" .. OUT\n");
-+ return;
-+}
-+
-+/**
-+ * Forces VC to flush(drop) its filled playback buffers and
-+ * return them the us. (VC->ARM)
-+ */
-+void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ LOG_DBG(" .. IN\n");
-+ LOG_DBG(" .. OUT\n");
-+}
-+
-+uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream)
-+{
-+ uint32_t count = atomic_read(&alsa_stream->retrieved);
-+ atomic_sub(count, &alsa_stream->retrieved);
-+ return count;
-+}
-+
-+module_param(force_bulk, bool, 0444);
-+MODULE_PARM_DESC(force_bulk, "Force use of vchiq bulk for audio");
-diff -Nur linux-3.18.14/sound/arm/Kconfig linux-rpi/sound/arm/Kconfig
---- linux-3.18.14/sound/arm/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/arm/Kconfig 2015-05-31 14:46:14.233660949 -0500
-@@ -39,5 +39,12 @@
- Say Y or M if you want to support any AC97 codec attached to
- the PXA2xx AC97 interface.
-
-+config SND_BCM2835
-+ tristate "BCM2835 ALSA driver"
-+ depends on (ARCH_BCM2708 || ARCH_BCM2709) && BCM2708_VCHIQ && SND
-+ select SND_PCM
-+ help
-+ Say Y or M if you want to support BCM2835 Alsa pcm card driver
-+
- endif # SND_ARM
-
-diff -Nur linux-3.18.14/sound/arm/Makefile linux-rpi/sound/arm/Makefile
---- linux-3.18.14/sound/arm/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/arm/Makefile 2015-05-31 14:46:14.233660949 -0500
-@@ -14,3 +14,8 @@
-
- obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o
- snd-pxa2xx-ac97-objs := pxa2xx-ac97.o
-+
-+obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o
-+snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o
-+
-+ccflags-y += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000
-diff -Nur linux-3.18.14/sound/arm/vc_vchi_audioserv_defs.h linux-rpi/sound/arm/vc_vchi_audioserv_defs.h
---- linux-3.18.14/sound/arm/vc_vchi_audioserv_defs.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/arm/vc_vchi_audioserv_defs.h 2015-05-31 14:46:14.233660949 -0500
-@@ -0,0 +1,116 @@
-+/*****************************************************************************
-+* Copyright 2011 Broadcom Corporation. All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef _VC_AUDIO_DEFS_H_
-+#define _VC_AUDIO_DEFS_H_
-+
-+#define VC_AUDIOSERV_MIN_VER 1
-+#define VC_AUDIOSERV_VER 2
-+
-+// FourCC code used for VCHI connection
-+#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS")
-+
-+// Maximum message length
-+#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T ))
-+
-+// List of screens that are currently supported
-+// All message types supported for HOST->VC direction
-+typedef enum {
-+ VC_AUDIO_MSG_TYPE_RESULT, // Generic result
-+ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result
-+ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio
-+ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio
-+ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio
-+ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio
-+ VC_AUDIO_MSG_TYPE_START, // Configure audio
-+ VC_AUDIO_MSG_TYPE_STOP, // Configure audio
-+ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio
-+ VC_AUDIO_MSG_TYPE_MAX
-+} VC_AUDIO_MSG_TYPE;
-+
-+// configure the audio
-+typedef struct {
-+ uint32_t channels;
-+ uint32_t samplerate;
-+ uint32_t bps;
-+
-+} VC_AUDIO_CONFIG_T;
-+
-+typedef struct {
-+ uint32_t volume;
-+ uint32_t dest;
-+
-+} VC_AUDIO_CONTROL_T;
-+
-+// audio
-+typedef struct {
-+ uint32_t dummy;
-+
-+} VC_AUDIO_OPEN_T;
-+
-+// audio
-+typedef struct {
-+ uint32_t dummy;
-+
-+} VC_AUDIO_CLOSE_T;
-+// audio
-+typedef struct {
-+ uint32_t dummy;
-+
-+} VC_AUDIO_START_T;
-+// audio
-+typedef struct {
-+ uint32_t draining;
-+
-+} VC_AUDIO_STOP_T;
-+
-+// configure the write audio samples
-+typedef struct {
-+ uint32_t count; // in bytes
-+ void *callback;
-+ void *cookie;
-+ uint16_t silence;
-+ uint16_t max_packet;
-+} VC_AUDIO_WRITE_T;
-+
-+// Generic result for a request (VC->HOST)
-+typedef struct {
-+ int32_t success; // Success value
-+
-+} VC_AUDIO_RESULT_T;
-+
-+// Generic result for a request (VC->HOST)
-+typedef struct {
-+ int32_t count; // Success value
-+ void *callback;
-+ void *cookie;
-+} VC_AUDIO_COMPLETE_T;
-+
-+// Message header for all messages in HOST->VC direction
-+typedef struct {
-+ int32_t type; // Message type (VC_AUDIO_MSG_TYPE)
-+ union {
-+ VC_AUDIO_CONFIG_T config;
-+ VC_AUDIO_CONTROL_T control;
-+ VC_AUDIO_OPEN_T open;
-+ VC_AUDIO_CLOSE_T close;
-+ VC_AUDIO_START_T start;
-+ VC_AUDIO_STOP_T stop;
-+ VC_AUDIO_WRITE_T write;
-+ VC_AUDIO_RESULT_T result;
-+ VC_AUDIO_COMPLETE_T complete;
-+ } u;
-+} VC_AUDIO_MSG_T;
-+
-+#endif // _VC_AUDIO_DEFS_H_
-diff -Nur linux-3.18.14/sound/soc/bcm/bcm2708-i2s.c linux-rpi/sound/soc/bcm/bcm2708-i2s.c
---- linux-3.18.14/sound/soc/bcm/bcm2708-i2s.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/bcm2708-i2s.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,1009 @@
-+/*
-+ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * Based on
-+ * Raspberry Pi PCM I2S ALSA Driver
-+ * Copyright (c) by Phil Poole 2013
-+ *
-+ * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
-+ * Vladimir Barinov, <vbarinov@embeddedalley.com>
-+ * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
-+ *
-+ * OMAP ALSA SoC DAI driver using McBSP port
-+ * Copyright (C) 2008 Nokia Corporation
-+ * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
-+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
-+ *
-+ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
-+ * Author: Timur Tabi <timur@freescale.com>
-+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include "bcm2708-i2s.h"
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <mach/gpio.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/initval.h>
-+#include <sound/soc.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include <asm/system_info.h>
-+
-+/* Clock registers */
-+#define BCM2708_CLK_PCMCTL_REG 0x00
-+#define BCM2708_CLK_PCMDIV_REG 0x04
-+
-+/* Clock register settings */
-+#define BCM2708_CLK_PASSWD (0x5a000000)
-+#define BCM2708_CLK_PASSWD_MASK (0xff000000)
-+#define BCM2708_CLK_MASH(v) ((v) << 9)
-+#define BCM2708_CLK_FLIP BIT(8)
-+#define BCM2708_CLK_BUSY BIT(7)
-+#define BCM2708_CLK_KILL BIT(5)
-+#define BCM2708_CLK_ENAB BIT(4)
-+#define BCM2708_CLK_SRC(v) (v)
-+
-+#define BCM2708_CLK_SHIFT (12)
-+#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
-+#define BCM2708_CLK_DIVF(v) (v)
-+#define BCM2708_CLK_DIVF_MASK (0xFFF)
-+
-+enum {
-+ BCM2708_CLK_MASH_0 = 0,
-+ BCM2708_CLK_MASH_1,
-+ BCM2708_CLK_MASH_2,
-+ BCM2708_CLK_MASH_3,
-+};
-+
-+enum {
-+ BCM2708_CLK_SRC_GND = 0,
-+ BCM2708_CLK_SRC_OSC,
-+ BCM2708_CLK_SRC_DBG0,
-+ BCM2708_CLK_SRC_DBG1,
-+ BCM2708_CLK_SRC_PLLA,
-+ BCM2708_CLK_SRC_PLLC,
-+ BCM2708_CLK_SRC_PLLD,
-+ BCM2708_CLK_SRC_HDMI,
-+};
-+
-+/* Most clocks are not useable (freq = 0) */
-+static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
-+ [BCM2708_CLK_SRC_GND] = 0,
-+ [BCM2708_CLK_SRC_OSC] = 19200000,
-+ [BCM2708_CLK_SRC_DBG0] = 0,
-+ [BCM2708_CLK_SRC_DBG1] = 0,
-+ [BCM2708_CLK_SRC_PLLA] = 0,
-+ [BCM2708_CLK_SRC_PLLC] = 0,
-+ [BCM2708_CLK_SRC_PLLD] = 500000000,
-+ [BCM2708_CLK_SRC_HDMI] = 0,
-+};
-+
-+/* I2S registers */
-+#define BCM2708_I2S_CS_A_REG 0x00
-+#define BCM2708_I2S_FIFO_A_REG 0x04
-+#define BCM2708_I2S_MODE_A_REG 0x08
-+#define BCM2708_I2S_RXC_A_REG 0x0c
-+#define BCM2708_I2S_TXC_A_REG 0x10
-+#define BCM2708_I2S_DREQ_A_REG 0x14
-+#define BCM2708_I2S_INTEN_A_REG 0x18
-+#define BCM2708_I2S_INTSTC_A_REG 0x1c
-+#define BCM2708_I2S_GRAY_REG 0x20
-+
-+/* I2S register settings */
-+#define BCM2708_I2S_STBY BIT(25)
-+#define BCM2708_I2S_SYNC BIT(24)
-+#define BCM2708_I2S_RXSEX BIT(23)
-+#define BCM2708_I2S_RXF BIT(22)
-+#define BCM2708_I2S_TXE BIT(21)
-+#define BCM2708_I2S_RXD BIT(20)
-+#define BCM2708_I2S_TXD BIT(19)
-+#define BCM2708_I2S_RXR BIT(18)
-+#define BCM2708_I2S_TXW BIT(17)
-+#define BCM2708_I2S_CS_RXERR BIT(16)
-+#define BCM2708_I2S_CS_TXERR BIT(15)
-+#define BCM2708_I2S_RXSYNC BIT(14)
-+#define BCM2708_I2S_TXSYNC BIT(13)
-+#define BCM2708_I2S_DMAEN BIT(9)
-+#define BCM2708_I2S_RXTHR(v) ((v) << 7)
-+#define BCM2708_I2S_TXTHR(v) ((v) << 5)
-+#define BCM2708_I2S_RXCLR BIT(4)
-+#define BCM2708_I2S_TXCLR BIT(3)
-+#define BCM2708_I2S_TXON BIT(2)
-+#define BCM2708_I2S_RXON BIT(1)
-+#define BCM2708_I2S_EN (1)
-+
-+#define BCM2708_I2S_CLKDIS BIT(28)
-+#define BCM2708_I2S_PDMN BIT(27)
-+#define BCM2708_I2S_PDME BIT(26)
-+#define BCM2708_I2S_FRXP BIT(25)
-+#define BCM2708_I2S_FTXP BIT(24)
-+#define BCM2708_I2S_CLKM BIT(23)
-+#define BCM2708_I2S_CLKI BIT(22)
-+#define BCM2708_I2S_FSM BIT(21)
-+#define BCM2708_I2S_FSI BIT(20)
-+#define BCM2708_I2S_FLEN(v) ((v) << 10)
-+#define BCM2708_I2S_FSLEN(v) (v)
-+
-+#define BCM2708_I2S_CHWEX BIT(15)
-+#define BCM2708_I2S_CHEN BIT(14)
-+#define BCM2708_I2S_CHPOS(v) ((v) << 4)
-+#define BCM2708_I2S_CHWID(v) (v)
-+#define BCM2708_I2S_CH1(v) ((v) << 16)
-+#define BCM2708_I2S_CH2(v) (v)
-+
-+#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
-+#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
-+#define BCM2708_I2S_TX(v) ((v) << 8)
-+#define BCM2708_I2S_RX(v) (v)
-+
-+#define BCM2708_I2S_INT_RXERR BIT(3)
-+#define BCM2708_I2S_INT_TXERR BIT(2)
-+#define BCM2708_I2S_INT_RXR BIT(1)
-+#define BCM2708_I2S_INT_TXW BIT(0)
-+
-+/* I2S DMA interface */
-+#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
-+#define BCM2708_DMA_DREQ_PCM_TX 2
-+#define BCM2708_DMA_DREQ_PCM_RX 3
-+
-+/* I2S pin configuration */
-+static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO;
-+
-+/* General device struct */
-+struct bcm2708_i2s_dev {
-+ struct device *dev;
-+ struct snd_dmaengine_dai_dma_data dma_data[2];
-+ unsigned int fmt;
-+ unsigned int bclk_ratio;
-+
-+ struct regmap *i2s_regmap;
-+ struct regmap *clk_regmap;
-+};
-+
-+void bcm2708_i2s_set_gpio(int gpio) {
-+ bcm2708_i2s_gpio=gpio;
-+}
-+EXPORT_SYMBOL(bcm2708_i2s_set_gpio);
-+
-+
-+static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
-+{
-+ /* Start the clock if in master mode */
-+ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
-+
-+ switch (master) {
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ case SND_SOC_DAIFMT_CBS_CFM:
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
-+ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
-+{
-+ uint32_t clkreg;
-+ int timeout = 1000;
-+
-+ /* Stop clock */
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
-+ BCM2708_CLK_PASSWD);
-+
-+ /* Wait for the BUSY flag going down */
-+ while (--timeout) {
-+ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
-+ if (!(clkreg & BCM2708_CLK_BUSY))
-+ break;
-+ }
-+
-+ if (!timeout) {
-+ /* KILL the clock */
-+ dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
-+ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
-+ }
-+}
-+
-+static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
-+ bool tx, bool rx)
-+{
-+ int timeout = 1000;
-+ uint32_t syncval;
-+ uint32_t csreg;
-+ uint32_t i2s_active_state;
-+ uint32_t clkreg;
-+ uint32_t clk_active_state;
-+ uint32_t off;
-+ uint32_t clr;
-+
-+ off = tx ? BCM2708_I2S_TXON : 0;
-+ off |= rx ? BCM2708_I2S_RXON : 0;
-+
-+ clr = tx ? BCM2708_I2S_TXCLR : 0;
-+ clr |= rx ? BCM2708_I2S_RXCLR : 0;
-+
-+ /* Backup the current state */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
-+ i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
-+
-+ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
-+ clk_active_state = clkreg & BCM2708_CLK_ENAB;
-+
-+ /* Start clock if not running */
-+ if (!clk_active_state) {
-+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
-+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
-+ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
-+ }
-+
-+ /* Stop I2S module */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
-+
-+ /*
-+ * Clear the FIFOs
-+ * Requires at least 2 PCM clock cycles to take effect
-+ */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
-+
-+ /* Wait for 2 PCM clock cycles */
-+
-+ /*
-+ * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
-+ * FIXME: This does not seem to work for slave mode!
-+ */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
-+ syncval &= BCM2708_I2S_SYNC;
-+
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_SYNC, ~syncval);
-+
-+ /* Wait for the SYNC flag changing it's state */
-+ while (--timeout) {
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
-+ if ((csreg & BCM2708_I2S_SYNC) != syncval)
-+ break;
-+ }
-+
-+ if (!timeout)
-+ dev_err(dev->dev, "I2S SYNC error!\n");
-+
-+ /* Stop clock if it was not running before */
-+ if (!clk_active_state)
-+ bcm2708_i2s_stop_clock(dev);
-+
-+ /* Restore I2S state */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
-+}
-+
-+static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
-+ unsigned int fmt)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ dev->fmt = fmt;
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
-+ unsigned int ratio)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ dev->bclk_ratio = ratio;
-+ return 0;
-+}
-+
-+
-+static int bcm2708_i2s_set_function(unsigned offset, int function)
-+{
-+ #define GPIOFSEL(x) (0x00+(x)*4)
-+ void __iomem *gpio = __io_address(GPIO_BASE);
-+ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2;
-+ unsigned gpiodir;
-+ unsigned gpio_bank = offset / 10;
-+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
-+
-+ if (offset >= BCM2708_NR_GPIOS)
-+ return -EINVAL;
-+
-+ gpiodir = readl(gpio + GPIOFSEL(gpio_bank));
-+ gpiodir &= ~(7 << gpio_field_offset);
-+ gpiodir |= alt << gpio_field_offset;
-+ writel(gpiodir, gpio + GPIOFSEL(gpio_bank));
-+ return 0;
-+}
-+
-+static void bcm2708_i2s_setup_gpio(void)
-+{
-+ /*
-+ * This is the common way to handle the GPIO pins for
-+ * the Raspberry Pi.
-+ * TODO Better way would be to handle
-+ * this in the device tree!
-+ */
-+ int pin,pinconfig,startpin,alt;
-+
-+ /* SPI is on different GPIOs on different boards */
-+ /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */
-+ if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) {
-+ if ((system_rev & 0xffffff) >= 0x10) {
-+ /* Model B+ */
-+ pinconfig=BCM2708_I2S_GPIO_PIN18;
-+ } else {
-+ /* original */
-+ pinconfig=BCM2708_I2S_GPIO_PIN28;
-+ }
-+ } else {
-+ pinconfig=bcm2708_i2s_gpio;
-+ }
-+
-+ if (pinconfig==BCM2708_I2S_GPIO_PIN18) {
-+ startpin=18;
-+ alt=BCM2708_I2S_GPIO_PIN18_ALT;
-+ } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) {
-+ startpin=28;
-+ alt=BCM2708_I2S_GPIO_PIN28_ALT;
-+ } else {
-+ printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig);
-+ return;
-+ }
-+
-+ /* configure I2S pins to correct ALT mode */
-+ for (pin = startpin; pin <= startpin+3; pin++) {
-+ bcm2708_i2s_set_function(pin, alt);
-+ }
-+}
-+
-+static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ unsigned int sampling_rate = params_rate(params);
-+ unsigned int data_length, data_delay, bclk_ratio;
-+ unsigned int ch1pos, ch2pos, mode, format;
-+ unsigned int mash = BCM2708_CLK_MASH_1;
-+ unsigned int divi, divf, target_frequency;
-+ int clk_src = -1;
-+ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
-+ bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
-+ || master == SND_SOC_DAIFMT_CBS_CFM);
-+
-+ bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
-+ || master == SND_SOC_DAIFMT_CBM_CFS);
-+ uint32_t csreg;
-+
-+ /*
-+ * If a stream is already enabled,
-+ * the registers are already set properly.
-+ */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
-+
-+ if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
-+ return 0;
-+
-+
-+ bcm2708_i2s_setup_gpio();
-+
-+ /*
-+ * Adjust the data length according to the format.
-+ * We prefill the half frame length with an integer
-+ * divider of 2400 as explained at the clock settings.
-+ * Maybe it is overwritten there, if the Integer mode
-+ * does not apply.
-+ */
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ data_length = 16;
-+ bclk_ratio = 50;
-+ break;
-+ case SNDRV_PCM_FORMAT_S24_LE:
-+ data_length = 24;
-+ bclk_ratio = 50;
-+ break;
-+ case SNDRV_PCM_FORMAT_S32_LE:
-+ data_length = 32;
-+ bclk_ratio = 100;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /* If bclk_ratio already set, use that one. */
-+ if (dev->bclk_ratio)
-+ bclk_ratio = dev->bclk_ratio;
-+
-+ /*
-+ * Clock Settings
-+ *
-+ * The target frequency of the bit clock is
-+ * sampling rate * frame length
-+ *
-+ * Integer mode:
-+ * Sampling rates that are multiples of 8000 kHz
-+ * can be driven by the oscillator of 19.2 MHz
-+ * with an integer divider as long as the frame length
-+ * is an integer divider of 19200000/8000=2400 as set up above.
-+ * This is no longer possible if the sampling rate
-+ * is too high (e.g. 192 kHz), because the oscillator is too slow.
-+ *
-+ * MASH mode:
-+ * For all other sampling rates, it is not possible to
-+ * have an integer divider. Approximate the clock
-+ * with the MASH module that induces a slight frequency
-+ * variance. To minimize that it is best to have the fastest
-+ * clock here. That is PLLD with 500 MHz.
-+ */
-+ target_frequency = sampling_rate * bclk_ratio;
-+ clk_src = BCM2708_CLK_SRC_OSC;
-+ mash = BCM2708_CLK_MASH_0;
-+
-+ if (bcm2708_clk_freq[clk_src] % target_frequency == 0
-+ && bit_master && frame_master) {
-+ divi = bcm2708_clk_freq[clk_src] / target_frequency;
-+ divf = 0;
-+ } else {
-+ uint64_t dividend;
-+
-+ if (!dev->bclk_ratio) {
-+ /*
-+ * Overwrite bclk_ratio, because the
-+ * above trick is not needed or can
-+ * not be used.
-+ */
-+ bclk_ratio = 2 * data_length;
-+ }
-+
-+ target_frequency = sampling_rate * bclk_ratio;
-+
-+ clk_src = BCM2708_CLK_SRC_PLLD;
-+ mash = BCM2708_CLK_MASH_1;
-+
-+ dividend = bcm2708_clk_freq[clk_src];
-+ dividend <<= BCM2708_CLK_SHIFT;
-+ do_div(dividend, target_frequency);
-+ divi = dividend >> BCM2708_CLK_SHIFT;
-+ divf = dividend & BCM2708_CLK_DIVF_MASK;
-+ }
-+
-+ /* Clock should only be set up here if CPU is clock master */
-+ if (((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) ||
-+ ((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFM)) {
-+ /* Set clock divider */
-+ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
-+ | BCM2708_CLK_DIVI(divi)
-+ | BCM2708_CLK_DIVF(divf));
-+
-+ /* Setup clock, but don't start it yet */
-+ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
-+ | BCM2708_CLK_MASH(mash)
-+ | BCM2708_CLK_SRC(clk_src));
-+ }
-+
-+ /* Setup the frame format */
-+ format = BCM2708_I2S_CHEN;
-+
-+ if (data_length >= 24)
-+ format |= BCM2708_I2S_CHWEX;
-+
-+ format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
-+
-+ switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+ case SND_SOC_DAIFMT_I2S:
-+ data_delay = 1;
-+ break;
-+ default:
-+ /*
-+ * TODO
-+ * Others are possible but are not implemented at the moment.
-+ */
-+ dev_err(dev->dev, "%s:bad format\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ ch1pos = data_delay;
-+ ch2pos = bclk_ratio / 2 + data_delay;
-+
-+ switch (params_channels(params)) {
-+ case 2:
-+ format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
-+ format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
-+ format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * Set format for both streams.
-+ * We cannot set another frame length
-+ * (and therefore word length) anyway,
-+ * so the format will be the same.
-+ */
-+ regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
-+ regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
-+
-+ /* Setup the I2S mode */
-+ mode = 0;
-+
-+ if (data_length <= 16) {
-+ /*
-+ * Use frame packed mode (2 channels per 32 bit word)
-+ * We cannot set another frame length in the second stream
-+ * (and therefore word length) anyway,
-+ * so the format will be the same.
-+ */
-+ mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
-+ }
-+
-+ mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
-+ mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
-+
-+ /* Master or slave? */
-+ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ /* CPU is master */
-+ break;
-+ case SND_SOC_DAIFMT_CBM_CFS:
-+ /*
-+ * CODEC is bit clock master
-+ * CPU is frame master
-+ */
-+ mode |= BCM2708_I2S_CLKM;
-+ break;
-+ case SND_SOC_DAIFMT_CBS_CFM:
-+ /*
-+ * CODEC is frame master
-+ * CPU is bit clock master
-+ */
-+ mode |= BCM2708_I2S_FSM;
-+ break;
-+ case SND_SOC_DAIFMT_CBM_CFM:
-+ /* CODEC is master */
-+ mode |= BCM2708_I2S_CLKM;
-+ mode |= BCM2708_I2S_FSM;
-+ break;
-+ default:
-+ dev_err(dev->dev, "%s:bad master\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * Invert clocks?
-+ *
-+ * The BCM approach seems to be inverted to the classical I2S approach.
-+ */
-+ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
-+ case SND_SOC_DAIFMT_NB_NF:
-+ /* None. Therefore, both for BCM */
-+ mode |= BCM2708_I2S_CLKI;
-+ mode |= BCM2708_I2S_FSI;
-+ break;
-+ case SND_SOC_DAIFMT_IB_IF:
-+ /* Both. Therefore, none for BCM */
-+ break;
-+ case SND_SOC_DAIFMT_NB_IF:
-+ /*
-+ * Invert only frame sync. Therefore,
-+ * invert only bit clock for BCM
-+ */
-+ mode |= BCM2708_I2S_CLKI;
-+ break;
-+ case SND_SOC_DAIFMT_IB_NF:
-+ /*
-+ * Invert only bit clock. Therefore,
-+ * invert only frame sync for BCM
-+ */
-+ mode |= BCM2708_I2S_FSI;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
-+
-+ /* Setup the DMA parameters */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_RXTHR(1)
-+ | BCM2708_I2S_TXTHR(1)
-+ | BCM2708_I2S_DMAEN, 0xffffffff);
-+
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
-+ BCM2708_I2S_TX_PANIC(0x10)
-+ | BCM2708_I2S_RX_PANIC(0x30)
-+ | BCM2708_I2S_TX(0x30)
-+ | BCM2708_I2S_RX(0x20), 0xffffffff);
-+
-+ /* Clear FIFOs */
-+ bcm2708_i2s_clear_fifos(dev, true, true);
-+
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ uint32_t cs_reg;
-+
-+ bcm2708_i2s_start_clock(dev);
-+
-+ /*
-+ * Clear both FIFOs if the one that should be started
-+ * is not empty at the moment. This should only happen
-+ * after overrun. Otherwise, hw_params would have cleared
-+ * the FIFO.
-+ */
-+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
-+ && !(cs_reg & BCM2708_I2S_TXE))
-+ bcm2708_i2s_clear_fifos(dev, true, false);
-+ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
-+ && (cs_reg & BCM2708_I2S_RXD))
-+ bcm2708_i2s_clear_fifos(dev, false, true);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
-+ struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ uint32_t mask;
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-+ mask = BCM2708_I2S_RXON;
-+ else
-+ mask = BCM2708_I2S_TXON;
-+
-+ regmap_update_bits(dev->i2s_regmap,
-+ BCM2708_I2S_CS_A_REG, mask, 0);
-+
-+ /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
-+ if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
-+ bcm2708_i2s_stop_clock(dev);
-+}
-+
-+static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+ uint32_t mask;
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+ bcm2708_i2s_start_clock(dev);
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
-+ mask = BCM2708_I2S_RXON;
-+ else
-+ mask = BCM2708_I2S_TXON;
-+
-+ regmap_update_bits(dev->i2s_regmap,
-+ BCM2708_I2S_CS_A_REG, mask, mask);
-+ break;
-+
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+ bcm2708_i2s_stop(dev, substream, dai);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ if (dai->active)
-+ return 0;
-+
-+ /* Should this still be running stop it */
-+ bcm2708_i2s_stop_clock(dev);
-+
-+ /* Enable PCM block */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_EN, BCM2708_I2S_EN);
-+
-+ /*
-+ * Disable STBY.
-+ * Requires at least 4 PCM clock cycles to take effect.
-+ */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_STBY, BCM2708_I2S_STBY);
-+
-+ return 0;
-+}
-+
-+static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ bcm2708_i2s_stop(dev, substream, dai);
-+
-+ /* If both streams are stopped, disable module and clock */
-+ if (dai->active)
-+ return;
-+
-+ /* Disable the module */
-+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
-+ BCM2708_I2S_EN, 0);
-+
-+ /*
-+ * Stopping clock is necessary, because stop does
-+ * not stop the clock when SND_SOC_DAIFMT_CONT
-+ */
-+ bcm2708_i2s_stop_clock(dev);
-+}
-+
-+static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
-+ .startup = bcm2708_i2s_startup,
-+ .shutdown = bcm2708_i2s_shutdown,
-+ .prepare = bcm2708_i2s_prepare,
-+ .trigger = bcm2708_i2s_trigger,
-+ .hw_params = bcm2708_i2s_hw_params,
-+ .set_fmt = bcm2708_i2s_set_dai_fmt,
-+ .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
-+};
-+
-+static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
-+{
-+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+ dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
-+ dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
-+
-+ return 0;
-+}
-+
-+static struct snd_soc_dai_driver bcm2708_i2s_dai = {
-+ .name = "bcm2708-i2s",
-+ .probe = bcm2708_i2s_dai_probe,
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE
-+ | SNDRV_PCM_FMTBIT_S24_LE
-+ | SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+ .capture = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE
-+ | SNDRV_PCM_FMTBIT_S24_LE
-+ | SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+ .ops = &bcm2708_i2s_dai_ops,
-+ .symmetric_rates = 1
-+};
-+
-+static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case BCM2708_I2S_CS_A_REG:
-+ case BCM2708_I2S_FIFO_A_REG:
-+ case BCM2708_I2S_INTSTC_A_REG:
-+ case BCM2708_I2S_GRAY_REG:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case BCM2708_I2S_FIFO_A_REG:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case BCM2708_CLK_PCMCTL_REG:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static const struct regmap_config bcm2708_regmap_config[] = {
-+ {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .max_register = BCM2708_I2S_GRAY_REG,
-+ .precious_reg = bcm2708_i2s_precious_reg,
-+ .volatile_reg = bcm2708_i2s_volatile_reg,
-+ .cache_type = REGCACHE_RBTREE,
-+ .name = "i2s",
-+ },
-+ {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .max_register = BCM2708_CLK_PCMDIV_REG,
-+ .volatile_reg = bcm2708_clk_volatile_reg,
-+ .cache_type = REGCACHE_RBTREE,
-+ .name = "clk",
-+ },
-+};
-+
-+static const struct snd_soc_component_driver bcm2708_i2s_component = {
-+ .name = "bcm2708-i2s-comp",
-+};
-+
-+static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
-+ .info = SNDRV_PCM_INFO_INTERLEAVED |
-+ SNDRV_PCM_INFO_JOINT_DUPLEX,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE |
-+ SNDRV_PCM_FMTBIT_S32_LE,
-+ .period_bytes_min = 32,
-+ .period_bytes_max = 64 * PAGE_SIZE,
-+ .periods_min = 2,
-+ .periods_max = 255,
-+ .buffer_bytes_max = 128 * PAGE_SIZE,
-+};
-+
-+static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
-+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
-+ .pcm_hardware = &bcm2708_pcm_hardware,
-+ .prealloc_buffer_size = 256 * PAGE_SIZE,
-+};
-+
-+
-+static int bcm2708_i2s_probe(struct platform_device *pdev)
-+{
-+ struct bcm2708_i2s_dev *dev;
-+ int i;
-+ int ret;
-+ struct regmap *regmap[2];
-+ struct resource *mem[2];
-+
-+ /* Request both ioareas */
-+ for (i = 0; i <= 1; i++) {
-+ void __iomem *base;
-+
-+ mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
-+ base = devm_ioremap_resource(&pdev->dev, mem[i]);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
-+ &bcm2708_regmap_config[i]);
-+ if (IS_ERR(regmap[i])) {
-+ dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
-+ return PTR_ERR(regmap[i]);
-+ }
-+ }
-+
-+ dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
-+ GFP_KERNEL);
-+ if (IS_ERR(dev))
-+ return PTR_ERR(dev);
-+
-+ dev->i2s_regmap = regmap[0];
-+ dev->clk_regmap = regmap[1];
-+
-+ /* Set the DMA address */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
-+ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
-+
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
-+ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
-+
-+ /* Set the DREQ */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
-+ BCM2708_DMA_DREQ_PCM_TX;
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
-+ BCM2708_DMA_DREQ_PCM_RX;
-+
-+ /* Set the bus width */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
-+ DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
-+ DMA_SLAVE_BUSWIDTH_4_BYTES;
-+
-+ /* Set burst */
-+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
-+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
-+
-+ /* BCLK ratio - use default */
-+ dev->bclk_ratio = 0;
-+
-+ /* Store the pdev */
-+ dev->dev = &pdev->dev;
-+ dev_set_drvdata(&pdev->dev, dev);
-+
-+ ret = snd_soc_register_component(&pdev->dev,
-+ &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
-+
-+ if (ret) {
-+ dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
-+ ret = -ENOMEM;
-+ return ret;
-+ }
-+
-+ ret = snd_dmaengine_pcm_register(&pdev->dev,
-+ &bcm2708_dmaengine_pcm_config,
-+ SND_DMAENGINE_PCM_FLAG_COMPAT);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
-+ snd_soc_unregister_component(&pdev->dev);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int bcm2708_i2s_remove(struct platform_device *pdev)
-+{
-+ snd_dmaengine_pcm_unregister(&pdev->dev);
-+ snd_soc_unregister_component(&pdev->dev);
-+ return 0;
-+}
-+
-+static const struct of_device_id bcm2708_i2s_of_match[] = {
-+ { .compatible = "brcm,bcm2708-i2s", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, bcm2708_i2s_of_match);
-+
-+static struct platform_driver bcm2708_i2s_driver = {
-+ .probe = bcm2708_i2s_probe,
-+ .remove = bcm2708_i2s_remove,
-+ .driver = {
-+ .name = "bcm2708-i2s",
-+ .owner = THIS_MODULE,
-+ .of_match_table = bcm2708_i2s_of_match,
-+ },
-+};
-+
-+module_platform_driver(bcm2708_i2s_driver);
-+
-+MODULE_ALIAS("platform:bcm2708-i2s");
-+MODULE_DESCRIPTION("BCM2708 I2S interface");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/bcm2708-i2s.h linux-rpi/sound/soc/bcm/bcm2708-i2s.h
---- linux-3.18.14/sound/soc/bcm/bcm2708-i2s.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/bcm2708-i2s.h 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,35 @@
-+/*
-+ * I2S configuration for sound cards.
-+ *
-+ * Copyright (c) 2014 Daniel Matuschek <daniel@hifiberry.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ */
-+
-+#ifndef BCM2708_I2S_H
-+#define BCM2708_I2S_H
-+
-+/* I2S pin assignment */
-+#define BCM2708_I2S_GPIO_AUTO 0
-+#define BCM2708_I2S_GPIO_PIN18 1
-+#define BCM2708_I2S_GPIO_PIN28 2
-+
-+/* Alt mode to enable I2S */
-+#define BCM2708_I2S_GPIO_PIN18_ALT 0
-+#define BCM2708_I2S_GPIO_PIN28_ALT 2
-+
-+extern void bcm2708_i2s_set_gpio(int gpio);
-+
-+#endif
-diff -Nur linux-3.18.14/sound/soc/bcm/bcm2835-i2s.c linux-rpi/sound/soc/bcm/bcm2835-i2s.c
---- linux-3.18.14/sound/soc/bcm/bcm2835-i2s.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/soc/bcm/bcm2835-i2s.c 2015-05-31 14:46:14.493660947 -0500
-@@ -861,6 +861,7 @@
- { .compatible = "brcm,bcm2835-i2s", },
- {},
- };
-+MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
-
- static struct platform_driver bcm2835_i2s_driver = {
- .probe = bcm2835_i2s_probe,
-diff -Nur linux-3.18.14/sound/soc/bcm/hifiberry_amp.c linux-rpi/sound/soc/bcm/hifiberry_amp.c
---- linux-3.18.14/sound/soc/bcm/hifiberry_amp.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/hifiberry_amp.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,127 @@
-+/*
-+ * ASoC Driver for HifiBerry AMP
-+ *
-+ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ * Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ // ToDo: init of the dsp-registers.
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params )
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = {
-+ .hw_params = snd_rpi_hifiberry_amp_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = {
-+ {
-+ .name = "HifiBerry AMP",
-+ .stream_name = "HifiBerry AMP HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "tas5713-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "tas5713.1-001b",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S |
-+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_hifiberry_amp_ops,
-+ .init = snd_rpi_hifiberry_amp_init,
-+ },
-+};
-+
-+
-+static struct snd_soc_card snd_rpi_hifiberry_amp = {
-+ .name = "snd_rpi_hifiberry_amp",
-+ .dai_link = snd_rpi_hifiberry_amp_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai),
-+};
-+
-+static const struct of_device_id snd_rpi_hifiberry_amp_of_match[] = {
-+ { .compatible = "hifiberry,hifiberry-amp", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_amp_of_match);
-+
-+
-+static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_amp.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_amp_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node,
-+ "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_amp);
-+
-+ if (ret != 0) {
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+ }
-+
-+ return ret;
-+}
-+
-+
-+static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_amp);
-+}
-+
-+
-+static struct platform_driver snd_rpi_hifiberry_amp_driver = {
-+ .driver = {
-+ .name = "snd-hifiberry-amp",
-+ .owner = THIS_MODULE,
-+ .of_match_table = snd_rpi_hifiberry_amp_of_match,
-+ },
-+ .probe = snd_rpi_hifiberry_amp_probe,
-+ .remove = snd_rpi_hifiberry_amp_remove,
-+};
-+
-+
-+module_platform_driver(snd_rpi_hifiberry_amp_driver);
-+
-+
-+MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
-+MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/hifiberry_dac.c linux-rpi/sound/soc/bcm/hifiberry_dac.c
---- linux-3.18.14/sound/soc/bcm/hifiberry_dac.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/hifiberry_dac.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,122 @@
-+/*
-+ * ASoC Driver for HifiBerry DAC
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ unsigned int sample_bits =
-+ snd_pcm_format_physical_width(params_format(params));
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = {
-+ .hw_params = snd_rpi_hifiberry_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = {
-+{
-+ .name = "HifiBerry DAC",
-+ .stream_name = "HifiBerry DAC HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm5102a-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm5102a-codec",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_hifiberry_dac_ops,
-+ .init = snd_rpi_hifiberry_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_dac = {
-+ .name = "snd_rpi_hifiberry_dac",
-+ .dai_link = snd_rpi_hifiberry_dac_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai),
-+};
-+
-+static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_dac.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node,
-+ "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_dac);
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_dac);
-+}
-+
-+static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = {
-+ { .compatible = "hifiberry,hifiberry-dac", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match);
-+
-+static struct platform_driver snd_rpi_hifiberry_dac_driver = {
-+ .driver = {
-+ .name = "snd-hifiberry-dac",
-+ .owner = THIS_MODULE,
-+ .of_match_table = snd_rpi_hifiberry_dac_of_match,
-+ },
-+ .probe = snd_rpi_hifiberry_dac_probe,
-+ .remove = snd_rpi_hifiberry_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/hifiberry_dacplus.c linux-rpi/sound/soc/bcm/hifiberry_dacplus.c
---- linux-3.18.14/sound/soc/bcm/hifiberry_dacplus.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/hifiberry_dacplus.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,141 @@
-+/*
-+ * ASoC Driver for HiFiBerry DAC+
-+ *
-+ * Author: Daniel Matuschek
-+ * Copyright 2014
-+ * based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/pcm512x.h"
-+
-+static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
-+ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
-+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_startup(struct snd_pcm_substream *substream) {
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+ return 0;
-+}
-+
-+static void snd_rpi_hifiberry_dacplus_shutdown(struct snd_pcm_substream *substream) {
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = {
-+ .hw_params = snd_rpi_hifiberry_dacplus_hw_params,
-+ .startup = snd_rpi_hifiberry_dacplus_startup,
-+ .shutdown = snd_rpi_hifiberry_dacplus_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = {
-+{
-+ .name = "HiFiBerry DAC+",
-+ .stream_name = "HiFiBerry DAC+ HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm512x-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm512x.1-004d",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_hifiberry_dacplus_ops,
-+ .init = snd_rpi_hifiberry_dacplus_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_dacplus = {
-+ .name = "snd_rpi_hifiberry_dacplus",
-+ .dai_link = snd_rpi_hifiberry_dacplus_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai),
-+};
-+
-+static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_dacplus.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node,
-+ "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus);
-+ if (ret)
-+ dev_err(&pdev->dev,
-+ "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus);
-+}
-+
-+static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = {
-+ { .compatible = "hifiberry,hifiberry-dacplus", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match);
-+
-+static struct platform_driver snd_rpi_hifiberry_dacplus_driver = {
-+ .driver = {
-+ .name = "snd-rpi-hifiberry-dacplus",
-+ .owner = THIS_MODULE,
-+ .of_match_table = snd_rpi_hifiberry_dacplus_of_match,
-+ },
-+ .probe = snd_rpi_hifiberry_dacplus_probe,
-+ .remove = snd_rpi_hifiberry_dacplus_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_dacplus_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <daniel@hifiberry.com>");
-+MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/hifiberry_digi.c linux-rpi/sound/soc/bcm/hifiberry_digi.c
---- linux-3.18.14/sound/soc/bcm/hifiberry_digi.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/hifiberry_digi.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,223 @@
-+/*
-+ * ASoC Driver for HifiBerry Digi
-+ *
-+ * Author: Daniel Matuschek <info@crazy-audio.com>
-+ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8804.h"
-+
-+static short int auto_shutdown_output = 0;
-+module_param(auto_shutdown_output, short, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped");
-+
-+
-+static int samplerate=44100;
-+
-+static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ struct snd_soc_codec *codec = rtd->codec;
-+
-+ /* enable TX output */
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+ return 0;
-+}
-+
-+static int snd_rpi_hifiberry_digi_startup(struct snd_pcm_substream *substream) {
-+ /* turn on digital output */
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
-+ return 0;
-+}
-+
-+static void snd_rpi_hifiberry_digi_shutdown(struct snd_pcm_substream *substream) {
-+ /* turn off output */
-+ if (auto_shutdown_output) {
-+ /* turn off output */
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
-+ }
-+}
-+
-+
-+static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+ struct snd_soc_codec *codec = rtd->codec;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ int sysclk = 27000000; /* This is fixed on this board */
-+
-+ long mclk_freq=0;
-+ int mclk_div=1;
-+ int sampling_freq=1;
-+
-+ int ret;
-+
-+ samplerate = params_rate(params);
-+
-+ if (samplerate<=96000) {
-+ mclk_freq=samplerate*256;
-+ mclk_div=WM8804_MCLKDIV_256FS;
-+ } else {
-+ mclk_freq=samplerate*128;
-+ mclk_div=WM8804_MCLKDIV_128FS;
-+ }
-+
-+ switch (samplerate) {
-+ case 32000:
-+ sampling_freq=0x03;
-+ break;
-+ case 44100:
-+ sampling_freq=0x00;
-+ break;
-+ case 48000:
-+ sampling_freq=0x02;
-+ break;
-+ case 88200:
-+ sampling_freq=0x08;
-+ break;
-+ case 96000:
-+ sampling_freq=0x0a;
-+ break;
-+ case 176400:
-+ sampling_freq=0x0c;
-+ break;
-+ case 192000:
-+ sampling_freq=0x0e;
-+ break;
-+ default:
-+ dev_err(substream->pcm->dev,
-+ "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
-+ samplerate);
-+ }
-+
-+ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+ sysclk, SND_SOC_CLOCK_OUT);
-+ if (ret < 0) {
-+ dev_err(substream->pcm->dev,
-+ "Failed to set WM8804 SYSCLK: %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Enable TX output */
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+ /* Power on */
-+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+ /* set sampling frequency status bits */
-+ snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai,64);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = {
-+ .hw_params = snd_rpi_hifiberry_digi_hw_params,
-+ .startup = snd_rpi_hifiberry_digi_startup,
-+ .shutdown = snd_rpi_hifiberry_digi_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = {
-+{
-+ .name = "HifiBerry Digi",
-+ .stream_name = "HifiBerry Digi HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "wm8804-spdif",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "wm8804.1-003b",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBM_CFM,
-+ .ops = &snd_rpi_hifiberry_digi_ops,
-+ .init = snd_rpi_hifiberry_digi_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_digi = {
-+ .name = "snd_rpi_hifiberry_digi",
-+ .dai_link = snd_rpi_hifiberry_digi_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai),
-+};
-+
-+static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_hifiberry_digi.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node,
-+ "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_hifiberry_digi);
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_hifiberry_digi);
-+}
-+
-+static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = {
-+ { .compatible = "hifiberry,hifiberry-digi", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match);
-+
-+static struct platform_driver snd_rpi_hifiberry_digi_driver = {
-+ .driver = {
-+ .name = "snd-hifiberry-digi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = snd_rpi_hifiberry_digi_of_match,
-+ },
-+ .probe = snd_rpi_hifiberry_digi_probe,
-+ .remove = snd_rpi_hifiberry_digi_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_digi_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <info@crazy-audio.com>");
-+MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/iqaudio-dac.c linux-rpi/sound/soc/bcm/iqaudio-dac.c
---- linux-3.18.14/sound/soc/bcm/iqaudio-dac.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/iqaudio-dac.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,133 @@
-+/*
-+ * ASoC Driver for IQaudIO DAC
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ int ret;
-+ struct snd_soc_card *card = rtd->card;
-+ struct snd_soc_codec *codec = rtd->codec;
-+
-+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207);
-+ if (ret < 0)
-+ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
-+
-+ return 0;
-+}
-+
-+static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+// NOT USED struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+// NOT USED struct snd_soc_codec *codec = rtd->codec;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ unsigned int sample_bits =
-+ snd_pcm_format_physical_width(params_format(params));
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = {
-+ .hw_params = snd_rpi_iqaudio_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {
-+{
-+ .name = "IQaudIO DAC",
-+ .stream_name = "IQaudIO DAC HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm512x-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm512x.1-004c",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_iqaudio_dac_ops,
-+ .init = snd_rpi_iqaudio_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_iqaudio_dac = {
-+ .name = "IQaudIODAC",
-+ .dai_link = snd_rpi_iqaudio_dac_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai),
-+};
-+
-+static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_iqaudio_dac.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node,
-+ "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac);
-+ if (ret)
-+ dev_err(&pdev->dev,
-+ "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_iqaudio_dac);
-+}
-+
-+static const struct of_device_id iqaudio_of_match[] = {
-+ { .compatible = "iqaudio,iqaudio-dac", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, iqaudio_of_match);
-+
-+static struct platform_driver snd_rpi_iqaudio_dac_driver = {
-+ .driver = {
-+ .name = "snd-rpi-iqaudio-dac",
-+ .owner = THIS_MODULE,
-+ .of_match_table = iqaudio_of_match,
-+ },
-+ .probe = snd_rpi_iqaudio_dac_probe,
-+ .remove = snd_rpi_iqaudio_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_iqaudio_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/Kconfig linux-rpi/sound/soc/bcm/Kconfig
---- linux-3.18.14/sound/soc/bcm/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/soc/bcm/Kconfig 2015-05-31 14:46:14.493660947 -0500
-@@ -7,3 +7,63 @@
- Say Y or M if you want to add support for codecs attached to
- the BCM2835 I2S interface. You will also need
- to select the audio interfaces to support below.
-+
-+config SND_BCM2708_SOC_I2S
-+ tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
-+ depends on MACH_BCM2708 || MACH_BCM2709
-+ select REGMAP_MMIO
-+ select SND_SOC_DMAENGINE_PCM
-+ select SND_SOC_GENERIC_DMAENGINE_PCM
-+ help
-+ Say Y or M if you want to add support for codecs attached to
-+ the BCM2708 I2S interface. You will also need
-+ to select the audio interfaces to support below.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DAC
-+ tristate "Support for HifiBerry DAC"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM5102A
-+ help
-+ Say Y or M if you want to add support for HifiBerry DAC.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DACPLUS
-+ tristate "Support for HifiBerry DAC+"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM512x
-+ help
-+ Say Y or M if you want to add support for HifiBerry DAC+.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DIGI
-+ tristate "Support for HifiBerry Digi"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_WM8804
-+ help
-+ Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_AMP
-+ tristate "Support for the HifiBerry Amp"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_TAS5713
-+ help
-+ Say Y or M if you want to add support for the HifiBerry Amp amplifier board.
-+
-+config SND_BCM2708_SOC_RPI_DAC
-+ tristate "Support for RPi-DAC"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM1794A
-+ help
-+ Say Y or M if you want to add support for RPi-DAC.
-+
-+config SND_BCM2708_SOC_RPI_PROTO
-+ tristate "Support for Rpi-PROTO"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_WM8731
-+ help
-+ Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731).
-+
-+config SND_BCM2708_SOC_IQAUDIO_DAC
-+ tristate "Support for IQaudIO-DAC"
-+ depends on SND_BCM2708_SOC_I2S
-+ select SND_SOC_PCM512x_I2C
-+ help
-+ Say Y or M if you want to add support for IQaudIO-DAC.
-diff -Nur linux-3.18.14/sound/soc/bcm/Makefile linux-rpi/sound/soc/bcm/Makefile
---- linux-3.18.14/sound/soc/bcm/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/soc/bcm/Makefile 2015-05-31 14:46:14.493660947 -0500
-@@ -3,3 +3,24 @@
-
- obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o
-
-+# BCM2708 Platform Support
-+snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
-+
-+obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
-+
-+# BCM2708 Machine Support
-+snd-soc-hifiberry-dac-objs := hifiberry_dac.o
-+snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
-+snd-soc-hifiberry-digi-objs := hifiberry_digi.o
-+snd-soc-hifiberry-amp-objs := hifiberry_amp.o
-+snd-soc-rpi-dac-objs := rpi-dac.o
-+snd-soc-rpi-proto-objs := rpi-proto.o
-+snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-+
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
-+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
-diff -Nur linux-3.18.14/sound/soc/bcm/rpi-dac.c linux-rpi/sound/soc/bcm/rpi-dac.c
---- linux-3.18.14/sound/soc/bcm/rpi-dac.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/rpi-dac.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,118 @@
-+/*
-+ * ASoC Driver for RPi-DAC.
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+ return 0;
-+}
-+
-+static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_rpi_dac_ops = {
-+ .hw_params = snd_rpi_rpi_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = {
-+{
-+ .name = "RPi-DAC",
-+ .stream_name = "RPi-DAC HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "pcm1794a-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "pcm1794a-codec",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
-+ .ops = &snd_rpi_rpi_dac_ops,
-+ .init = snd_rpi_rpi_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_rpi_dac = {
-+ .name = "snd_rpi_rpi_dac",
-+ .dai_link = snd_rpi_rpi_dac_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_rpi_dac_dai),
-+};
-+
-+static int snd_rpi_rpi_dac_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_rpi_dac.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_rpi_dac);
-+ if (ret)
-+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int snd_rpi_rpi_dac_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_rpi_dac);
-+}
-+
-+static const struct of_device_id snd_rpi_rpi_dac_of_match[] = {
-+ { .compatible = "rpi,rpi-dac", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match);
-+
-+static struct platform_driver snd_rpi_rpi_dac_driver = {
-+ .driver = {
-+ .name = "snd-rpi-dac",
-+ .owner = THIS_MODULE,
-+ .of_match_table = snd_rpi_rpi_dac_of_match,
-+ },
-+ .probe = snd_rpi_rpi_dac_probe,
-+ .remove = snd_rpi_rpi_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_rpi_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for RPi-DAC");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/bcm/rpi-proto.c linux-rpi/sound/soc/bcm/rpi-proto.c
---- linux-3.18.14/sound/soc/bcm/rpi-proto.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/bcm/rpi-proto.c 2015-05-31 14:46:14.493660947 -0500
-@@ -0,0 +1,152 @@
-+/*
-+ * ASoC driver for PROTO AudioCODEC (with a WM8731)
-+ * connected to a Raspberry Pi
-+ *
-+ * Author: Florian Meier, <koalo@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8731.h"
-+
-+static const unsigned int wm8731_rates_12288000[] = {
-+ 8000, 32000, 48000, 96000,
-+};
-+
-+static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {
-+ .list = wm8731_rates_12288000,
-+ .count = ARRAY_SIZE(wm8731_rates_12288000),
-+};
-+
-+static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)
-+{
-+ /* Setup constraints, because there is a 12.288 MHz XTAL on the board */
-+ snd_pcm_hw_constraint_list(substream->runtime, 0,
-+ SNDRV_PCM_HW_PARAM_RATE,
-+ &wm8731_constraints_12288000);
-+ return 0;
-+}
-+
-+static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+ int sysclk = 12288000; /* This is fixed on this board */
-+
-+ /* Set proto bclk */
-+ int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2);
-+ if (ret < 0){
-+ dev_err(substream->pcm->dev,
-+ "Failed to set BCLK ratio %d\n", ret);
-+ return ret;
-+ }
-+
-+ /* Set proto sysclk */
-+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
-+ sysclk, SND_SOC_CLOCK_IN);
-+ if (ret < 0) {
-+ dev_err(substream->pcm->dev,
-+ "Failed to set WM8731 SYSCLK: %d\n", ret);
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_proto_ops = {
-+ .startup = snd_rpi_proto_startup,
-+ .hw_params = snd_rpi_proto_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_proto_dai[] = {
-+{
-+ .name = "WM8731",
-+ .stream_name = "WM8731 HiFi",
-+ .cpu_dai_name = "bcm2708-i2s.0",
-+ .codec_dai_name = "wm8731-hifi",
-+ .platform_name = "bcm2708-i2s.0",
-+ .codec_name = "wm8731.1-001a",
-+ .dai_fmt = SND_SOC_DAIFMT_I2S
-+ | SND_SOC_DAIFMT_NB_NF
-+ | SND_SOC_DAIFMT_CBM_CFM,
-+ .ops = &snd_rpi_proto_ops,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_proto = {
-+ .name = "snd_rpi_proto",
-+ .dai_link = snd_rpi_proto_dai,
-+ .num_links = ARRAY_SIZE(snd_rpi_proto_dai),
-+};
-+
-+static int snd_rpi_proto_probe(struct platform_device *pdev)
-+{
-+ int ret = 0;
-+
-+ snd_rpi_proto.dev = &pdev->dev;
-+
-+ if (pdev->dev.of_node) {
-+ struct device_node *i2s_node;
-+ struct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0];
-+ i2s_node = of_parse_phandle(pdev->dev.of_node,
-+ "i2s-controller", 0);
-+
-+ if (i2s_node) {
-+ dai->cpu_dai_name = NULL;
-+ dai->cpu_of_node = i2s_node;
-+ dai->platform_name = NULL;
-+ dai->platform_of_node = i2s_node;
-+ }
-+ }
-+
-+ ret = snd_soc_register_card(&snd_rpi_proto);
-+ if (ret) {
-+ dev_err(&pdev->dev,
-+ "snd_soc_register_card() failed: %d\n", ret);
-+ }
-+
-+ return ret;
-+}
-+
-+
-+static int snd_rpi_proto_remove(struct platform_device *pdev)
-+{
-+ return snd_soc_unregister_card(&snd_rpi_proto);
-+}
-+
-+static const struct of_device_id snd_rpi_proto_of_match[] = {
-+ { .compatible = "rpi,rpi-proto", },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match);
-+
-+static struct platform_driver snd_rpi_proto_driver = {
-+ .driver = {
-+ .name = "snd-rpi-proto",
-+ .owner = THIS_MODULE,
-+ .of_match_table = snd_rpi_proto_of_match,
-+ },
-+ .probe = snd_rpi_proto_probe,
-+ .remove = snd_rpi_proto_remove,
-+};
-+
-+module_platform_driver(snd_rpi_proto_driver);
-+
-+MODULE_AUTHOR("Florian Meier");
-+MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)");
-+MODULE_LICENSE("GPL");
-diff -Nur linux-3.18.14/sound/soc/codecs/Kconfig linux-rpi/sound/soc/codecs/Kconfig
---- linux-3.18.14/sound/soc/codecs/Kconfig 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/soc/codecs/Kconfig 2015-05-31 14:46:14.497660947 -0500
-@@ -80,6 +80,8 @@
- select SND_SOC_PCM512x_I2C if I2C
- select SND_SOC_PCM512x_SPI if SPI_MASTER
- select SND_SOC_RT286 if I2C
-+ select SND_SOC_PCM5102A if I2C
-+ select SND_SOC_PCM1794A if I2C
- select SND_SOC_RT5631 if I2C
- select SND_SOC_RT5640 if I2C
- select SND_SOC_RT5645 if I2C
-@@ -103,6 +105,7 @@
- select SND_SOC_TAS5086 if I2C
- select SND_SOC_TLV320AIC23_I2C if I2C
- select SND_SOC_TLV320AIC23_SPI if SPI_MASTER
-+ select SND_SOC_TAS5713 if I2C
- select SND_SOC_TLV320AIC26 if SPI_MASTER
- select SND_SOC_TLV320AIC31XX if I2C
- select SND_SOC_TLV320AIC32X4 if I2C
-@@ -486,6 +489,12 @@
- tristate
- depends on I2C
-
-+config SND_SOC_PCM1794A
-+ tristate
-+
-+config SND_SOC_PCM5102A
-+ tristate
-+
- config SND_SOC_RT5631
- tristate
-
-@@ -577,6 +586,9 @@
- tristate "Texas Instruments TAS5086 speaker amplifier"
- depends on I2C
-
-+config SND_SOC_TAS5713
-+ tristate
-+
- config SND_SOC_TLV320AIC23
- tristate
-
-diff -Nur linux-3.18.14/sound/soc/codecs/Makefile linux-rpi/sound/soc/codecs/Makefile
---- linux-3.18.14/sound/soc/codecs/Makefile 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/soc/codecs/Makefile 2015-05-31 14:46:14.497660947 -0500
-@@ -74,6 +74,8 @@
- snd-soc-pcm512x-spi-objs := pcm512x-spi.o
- snd-soc-rl6231-objs := rl6231.o
- snd-soc-rt286-objs := rt286.o
-+snd-soc-pcm1794a-objs := pcm1794a.o
-+snd-soc-pcm5102a-objs := pcm5102a.o
- snd-soc-rt5631-objs := rt5631.o
- snd-soc-rt5640-objs := rt5640.o
- snd-soc-rt5645-objs := rt5645.o
-@@ -101,6 +103,7 @@
- snd-soc-sta529-objs := sta529.o
- snd-soc-stac9766-objs := stac9766.o
- snd-soc-tas5086-objs := tas5086.o
-+snd-soc-tas5713-objs := tas5713.o
- snd-soc-tlv320aic23-objs := tlv320aic23.o
- snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o
- snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o
-@@ -250,6 +253,8 @@
- obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
- obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
- obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o
-+obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o
-+obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o
- obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
- obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
- obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
-@@ -274,6 +279,7 @@
- obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
- obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
- obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
-+obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o
-diff -Nur linux-3.18.14/sound/soc/codecs/pcm1794a.c linux-rpi/sound/soc/codecs/pcm1794a.c
---- linux-3.18.14/sound/soc/codecs/pcm1794a.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/codecs/pcm1794a.c 2015-05-31 14:46:14.525660946 -0500
-@@ -0,0 +1,69 @@
-+/*
-+ * Driver for the PCM1794A codec
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/soc.h>
-+
-+static struct snd_soc_dai_driver pcm1794a_dai = {
-+ .name = "pcm1794a-hifi",
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE
-+ },
-+};
-+
-+static struct snd_soc_codec_driver soc_codec_dev_pcm1794a;
-+
-+static int pcm1794a_probe(struct platform_device *pdev)
-+{
-+ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a,
-+ &pcm1794a_dai, 1);
-+}
-+
-+static int pcm1794a_remove(struct platform_device *pdev)
-+{
-+ snd_soc_unregister_codec(&pdev->dev);
-+ return 0;
-+}
-+
-+static const struct of_device_id pcm1794a_of_match[] = {
-+ { .compatible = "ti,pcm1794a", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, pcm1794a_of_match);
-+
-+static struct platform_driver pcm1794a_codec_driver = {
-+ .probe = pcm1794a_probe,
-+ .remove = pcm1794a_remove,
-+ .driver = {
-+ .name = "pcm1794a-codec",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(pcm1794a_of_match),
-+ },
-+};
-+
-+module_platform_driver(pcm1794a_codec_driver);
-+
-+MODULE_DESCRIPTION("ASoC PCM1794A codec driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/codecs/pcm5102a.c linux-rpi/sound/soc/codecs/pcm5102a.c
---- linux-3.18.14/sound/soc/codecs/pcm5102a.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/codecs/pcm5102a.c 2015-05-31 14:46:14.525660946 -0500
-@@ -0,0 +1,70 @@
-+/*
-+ * Driver for the PCM5102A codec
-+ *
-+ * Author: Florian Meier <florian.meier@koalo.de>
-+ * Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/soc.h>
-+
-+static struct snd_soc_dai_driver pcm5102a_dai = {
-+ .name = "pcm5102a-hifi",
-+ .playback = {
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_192000,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE |
-+ SNDRV_PCM_FMTBIT_S32_LE
-+ },
-+};
-+
-+static struct snd_soc_codec_driver soc_codec_dev_pcm5102a;
-+
-+static int pcm5102a_probe(struct platform_device *pdev)
-+{
-+ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm5102a,
-+ &pcm5102a_dai, 1);
-+}
-+
-+static int pcm5102a_remove(struct platform_device *pdev)
-+{
-+ snd_soc_unregister_codec(&pdev->dev);
-+ return 0;
-+}
-+
-+static const struct of_device_id pcm5102a_of_match[] = {
-+ { .compatible = "ti,pcm5102a", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, pcm5102a_of_match);
-+
-+static struct platform_driver pcm5102a_codec_driver = {
-+ .probe = pcm5102a_probe,
-+ .remove = pcm5102a_remove,
-+ .driver = {
-+ .name = "pcm5102a-codec",
-+ .owner = THIS_MODULE,
-+ .of_match_table = pcm5102a_of_match,
-+ },
-+};
-+
-+module_platform_driver(pcm5102a_codec_driver);
-+
-+MODULE_DESCRIPTION("ASoC PCM5102A codec driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/codecs/tas5713.c linux-rpi/sound/soc/codecs/tas5713.c
---- linux-3.18.14/sound/soc/codecs/tas5713.c 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/codecs/tas5713.c 2015-05-31 14:46:14.533660946 -0500
-@@ -0,0 +1,369 @@
-+/*
-+ * ASoC Driver for TAS5713
-+ *
-+ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ * Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/pm.h>
-+#include <linux/i2c.h>
-+#include <linux/of_device.h>
-+#include <linux/spi/spi.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/slab.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/initval.h>
-+#include <sound/tlv.h>
-+
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/fs.h>
-+#include <asm/uaccess.h>
-+
-+#include "tas5713.h"
-+
-+
-+static struct i2c_client *i2c;
-+
-+struct tas5713_priv {
-+ struct regmap *regmap;
-+ int mclk_div;
-+ struct snd_soc_codec *codec;
-+};
-+
-+static struct tas5713_priv *priv_data;
-+
-+
-+
-+
-+/*
-+ * _ _ ___ _ ___ _ _
-+ * /_\ | | / __| /_\ / __|___ _ _| |_ _ _ ___| |___
-+ * / _ \| |__\__ \/ _ \ | (__/ _ \ ' \ _| '_/ _ \ (_-<
-+ * /_/ \_\____|___/_/ \_\ \___\___/_||_\__|_| \___/_/__/
-+ *
-+ */
-+
-+static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1);
-+
-+
-+static const struct snd_kcontrol_new tas5713_snd_controls[] = {
-+ SOC_SINGLE_TLV ("Master" , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv),
-+ SOC_DOUBLE_R_TLV("Channels" , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv)
-+};
-+
-+
-+
-+
-+/*
-+ * __ __ _ _ ___ _
-+ * | \/ |__ _ __| |_ (_)_ _ ___ | \ _ _(_)_ _____ _ _
-+ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_|
-+ * |_| |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static int tas5713_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ u16 blen = 0x00;
-+
-+ struct snd_soc_codec *codec;
-+ codec = dai->codec;
-+ priv_data->codec = dai->codec;
-+
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ blen = 0x03;
-+ break;
-+ case SNDRV_PCM_FORMAT_S20_3LE:
-+ blen = 0x1;
-+ break;
-+ case SNDRV_PCM_FORMAT_S24_LE:
-+ blen = 0x04;
-+ break;
-+ case SNDRV_PCM_FORMAT_S32_LE:
-+ blen = 0x05;
-+ break;
-+ default:
-+ dev_err(dai->dev, "Unsupported word length: %u\n",
-+ params_format(params));
-+ return -EINVAL;
-+ }
-+
-+ // set word length
-+ snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen);
-+
-+ return 0;
-+}
-+
-+
-+static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
-+{
-+ unsigned int val = 0;
-+
-+ struct tas5713_priv *tas5713;
-+ struct snd_soc_codec *codec = dai->codec;
-+ tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+ if (mute) {
-+ val = TAS5713_SOFT_MUTE_ALL;
-+ }
-+
-+ return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val);
-+}
-+
-+
-+static const struct snd_soc_dai_ops tas5713_dai_ops = {
-+ .hw_params = tas5713_hw_params,
-+ .mute_stream = tas5713_mute_stream,
-+};
-+
-+
-+static struct snd_soc_dai_driver tas5713_dai = {
-+ .name = "tas5713-hifi",
-+ .playback = {
-+ .stream_name = "Playback",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_8000_48000,
-+ .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ),
-+ },
-+ .ops = &tas5713_dai_ops,
-+};
-+
-+
-+
-+
-+/*
-+ * ___ _ ___ _
-+ * / __|___ __| |___ __ | \ _ _(_)_ _____ _ _
-+ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_|
-+ * \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static int tas5713_remove(struct snd_soc_codec *codec)
-+{
-+ struct tas5713_priv *tas5713;
-+
-+ tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+ return 0;
-+}
-+
-+
-+static int tas5713_probe(struct snd_soc_codec *codec)
-+{
-+ struct tas5713_priv *tas5713;
-+ int i, ret;
-+
-+ i2c = container_of(codec->dev, struct i2c_client, dev);
-+
-+ tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+ // Reset error
-+ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
-+ if (ret < 0) return ret;
-+
-+ // Trim oscillator
-+ ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00);
-+ if (ret < 0) return ret;
-+ msleep(1000);
-+
-+ // Reset error
-+ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
-+ if (ret < 0) return ret;
-+
-+ // Clock mode: 44/48kHz, MCLK=64xfs
-+ ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60);
-+ if (ret < 0) return ret;
-+
-+ // I2S 24bit
-+ ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05);
-+ if (ret < 0) return ret;
-+
-+ // Unmute
-+ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
-+ if (ret < 0) return ret;
-+ ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00);
-+ if (ret < 0) return ret;
-+
-+ // Set volume to 0db
-+ ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00);
-+ if (ret < 0) return ret;
-+
-+ // Now start programming the default initialization sequence
-+ for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) {
-+ ret = i2c_master_send(i2c,
-+ tas5713_init_sequence[i].data,
-+ tas5713_init_sequence[i].size);
-+ if (ret < 0) {
-+ printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret);
-+ }
-+ }
-+
-+ // Unmute
-+ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
-+ if (ret < 0) return ret;
-+
-+ return 0;
-+}
-+
-+
-+static struct snd_soc_codec_driver soc_codec_dev_tas5713 = {
-+ .probe = tas5713_probe,
-+ .remove = tas5713_remove,
-+ .controls = tas5713_snd_controls,
-+ .num_controls = ARRAY_SIZE(tas5713_snd_controls),
-+};
-+
-+
-+
-+
-+/*
-+ * ___ ___ ___ ___ _
-+ * |_ _|_ ) __| | \ _ _(_)_ _____ _ _
-+ * | | / / (__ | |) | '_| \ V / -_) '_|
-+ * |___/___\___| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static const struct reg_default tas5713_reg_defaults[] = {
-+ { 0x07 ,0x80 }, // R7 - VOL_MASTER - -40dB
-+ { 0x08 , 30 }, // R8 - VOL_CH1 - 0dB
-+ { 0x09 , 30 }, // R9 - VOL_CH2 - 0dB
-+ { 0x0A ,0x80 }, // R10 - VOL_HEADPHONE - -40dB
-+};
-+
-+
-+static bool tas5713_reg_volatile(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case TAS5713_DEVICE_ID:
-+ case TAS5713_ERROR_STATUS:
-+ return true;
-+ default:
-+ return false;
-+ }
-+}
-+
-+
-+static const struct of_device_id tas5713_of_match[] = {
-+ { .compatible = "ti,tas5713", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, tas5713_of_match);
-+
-+
-+static struct regmap_config tas5713_regmap_config = {
-+ .reg_bits = 8,
-+ .val_bits = 8,
-+
-+ .max_register = TAS5713_MAX_REGISTER,
-+ .volatile_reg = tas5713_reg_volatile,
-+
-+ .cache_type = REGCACHE_RBTREE,
-+ .reg_defaults = tas5713_reg_defaults,
-+ .num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults),
-+};
-+
-+
-+static int tas5713_i2c_probe(struct i2c_client *i2c,
-+ const struct i2c_device_id *id)
-+{
-+ int ret;
-+
-+ priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL);
-+ if (!priv_data)
-+ return -ENOMEM;
-+
-+ priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config);
-+ if (IS_ERR(priv_data->regmap)) {
-+ ret = PTR_ERR(priv_data->regmap);
-+ return ret;
-+ }
-+
-+ i2c_set_clientdata(i2c, priv_data);
-+
-+ ret = snd_soc_register_codec(&i2c->dev,
-+ &soc_codec_dev_tas5713, &tas5713_dai, 1);
-+
-+ return ret;
-+}
-+
-+
-+static int tas5713_i2c_remove(struct i2c_client *i2c)
-+{
-+ snd_soc_unregister_codec(&i2c->dev);
-+ i2c_set_clientdata(i2c, NULL);
-+
-+ kfree(priv_data);
-+
-+ return 0;
-+}
-+
-+
-+static const struct i2c_device_id tas5713_i2c_id[] = {
-+ { "tas5713", 0 },
-+ { }
-+};
-+
-+MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id);
-+
-+
-+static struct i2c_driver tas5713_i2c_driver = {
-+ .driver = {
-+ .name = "tas5713",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tas5713_of_match,
-+ },
-+ .probe = tas5713_i2c_probe,
-+ .remove = tas5713_i2c_remove,
-+ .id_table = tas5713_i2c_id
-+};
-+
-+
-+static int __init tas5713_modinit(void)
-+{
-+ int ret = 0;
-+
-+ ret = i2c_add_driver(&tas5713_i2c_driver);
-+ if (ret) {
-+ printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n",
-+ ret);
-+ }
-+
-+ return ret;
-+}
-+module_init(tas5713_modinit);
-+
-+
-+static void __exit tas5713_exit(void)
-+{
-+ i2c_del_driver(&tas5713_i2c_driver);
-+}
-+module_exit(tas5713_exit);
-+
-+
-+MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
-+MODULE_DESCRIPTION("ASoC driver for TAS5713");
-+MODULE_LICENSE("GPL v2");
-diff -Nur linux-3.18.14/sound/soc/codecs/tas5713.h linux-rpi/sound/soc/codecs/tas5713.h
---- linux-3.18.14/sound/soc/codecs/tas5713.h 1969-12-31 18:00:00.000000000 -0600
-+++ linux-rpi/sound/soc/codecs/tas5713.h 2015-05-31 14:46:14.533660946 -0500
-@@ -0,0 +1,210 @@
-+/*
-+ * ASoC Driver for TAS5713
-+ *
-+ * Author: Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ * Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#ifndef _TAS5713_H
-+#define _TAS5713_H
-+
-+
-+// TAS5713 I2C-bus register addresses
-+
-+#define TAS5713_CLOCK_CTRL 0x00
-+#define TAS5713_DEVICE_ID 0x01
-+#define TAS5713_ERROR_STATUS 0x02
-+#define TAS5713_SYSTEM_CTRL1 0x03
-+#define TAS5713_SERIAL_DATA_INTERFACE 0x04
-+#define TAS5713_SYSTEM_CTRL2 0x05
-+#define TAS5713_SOFT_MUTE 0x06
-+#define TAS5713_VOL_MASTER 0x07
-+#define TAS5713_VOL_CH1 0x08
-+#define TAS5713_VOL_CH2 0x09
-+#define TAS5713_VOL_HEADPHONE 0x0A
-+#define TAS5713_VOL_CONFIG 0x0E
-+#define TAS5713_MODULATION_LIMIT 0x10
-+#define TAS5713_IC_DLY_CH1 0x11
-+#define TAS5713_IC_DLY_CH2 0x12
-+#define TAS5713_IC_DLY_CH3 0x13
-+#define TAS5713_IC_DLY_CH4 0x14
-+
-+#define TAS5713_START_STOP_PERIOD 0x1A
-+#define TAS5713_OSC_TRIM 0x1B
-+#define TAS5713_BKND_ERR 0x1C
-+
-+#define TAS5713_INPUT_MUX 0x20
-+#define TAS5713_SRC_SELECT_CH4 0x21
-+#define TAS5713_PWM_MUX 0x25
-+
-+#define TAS5713_CH1_BQ0 0x29
-+#define TAS5713_CH1_BQ1 0x2A
-+#define TAS5713_CH1_BQ2 0x2B
-+#define TAS5713_CH1_BQ3 0x2C
-+#define TAS5713_CH1_BQ4 0x2D
-+#define TAS5713_CH1_BQ5 0x2E
-+#define TAS5713_CH1_BQ6 0x2F
-+#define TAS5713_CH1_BQ7 0x58
-+#define TAS5713_CH1_BQ8 0x59
-+
-+#define TAS5713_CH2_BQ0 0x30
-+#define TAS5713_CH2_BQ1 0x31
-+#define TAS5713_CH2_BQ2 0x32
-+#define TAS5713_CH2_BQ3 0x33
-+#define TAS5713_CH2_BQ4 0x34
-+#define TAS5713_CH2_BQ5 0x35
-+#define TAS5713_CH2_BQ6 0x36
-+#define TAS5713_CH2_BQ7 0x5C
-+#define TAS5713_CH2_BQ8 0x5D
-+
-+#define TAS5713_CH4_BQ0 0x5A
-+#define TAS5713_CH4_BQ1 0x5B
-+#define TAS5713_CH3_BQ0 0x5E
-+#define TAS5713_CH3_BQ1 0x5F
-+
-+#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA 0x3B
-+#define TAS5713_DRC1_ATTACK_RELEASE_RATE 0x3C
-+#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA 0x3E
-+#define TAS5713_DRC2_ATTACK_RELEASE_RATE 0x3F
-+#define TAS5713_DRC1_ATTACK_RELEASE_THRES 0x40
-+#define TAS5713_DRC2_ATTACK_RELEASE_THRES 0x43
-+#define TAS5713_DRC_CTRL 0x46
-+
-+#define TAS5713_BANK_SW_CTRL 0x50
-+#define TAS5713_CH1_OUTPUT_MIXER 0x51
-+#define TAS5713_CH2_OUTPUT_MIXER 0x52
-+#define TAS5713_CH1_INPUT_MIXER 0x53
-+#define TAS5713_CH2_INPUT_MIXER 0x54
-+#define TAS5713_OUTPUT_POST_SCALE 0x56
-+#define TAS5713_OUTPUT_PRESCALE 0x57
-+
-+#define TAS5713_IDF_POST_SCALE 0x62
-+
-+#define TAS5713_CH1_INLINE_MIXER 0x70
-+#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71
-+#define TAS5713_CH1_R_CHANNEL_MIXER 0x72
-+#define TAS5713_CH1_L_CHANNEL_MIXER 0x73
-+#define TAS5713_CH2_INLINE_MIXER 0x74
-+#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75
-+#define TAS5713_CH2_L_CHANNEL_MIXER 0x76
-+#define TAS5713_CH2_R_CHANNEL_MIXER 0x77
-+
-+#define TAS5713_UPDATE_DEV_ADDR_KEY 0xF8
-+#define TAS5713_UPDATE_DEV_ADDR_REG 0xF9
-+
-+#define TAS5713_REGISTER_COUNT 0x46
-+#define TAS5713_MAX_REGISTER 0xF9
-+
-+
-+// Bitmasks for registers
-+#define TAS5713_SOFT_MUTE_ALL 0x07
-+
-+
-+
-+struct tas5713_init_command {
-+ const int size;
-+ const char *const data;
-+};
-+
-+static const struct tas5713_init_command tas5713_init_sequence[] = {
-+
-+ // Trim oscillator
-+ { .size = 2, .data = "\x1B\x00" },
-+ // System control register 1 (0x03): block DC
-+ { .size = 2, .data = "\x03\x80" },
-+ // Mute everything
-+ { .size = 2, .data = "\x05\x40" },
-+ // Modulation limit register (0x10): 97.7%
-+ { .size = 2, .data = "\x10\x02" },
-+ // Interchannel delay registers
-+ // (0x11, 0x12, 0x13, and 0x14): BD mode
-+ { .size = 2, .data = "\x11\xB8" },
-+ { .size = 2, .data = "\x12\x60" },
-+ { .size = 2, .data = "\x13\xA0" },
-+ { .size = 2, .data = "\x14\x48" },
-+ // PWM shutdown group register (0x19): no shutdown
-+ { .size = 2, .data = "\x19\x00" },
-+ // Input multiplexer register (0x20): BD mode
-+ { .size = 2, .data = "\x20\x00\x89\x77\x72" },
-+ // PWM output mux register (0x25)
-+ // Channel 1 --> OUTA, channel 1 neg --> OUTB
-+ // Channel 2 --> OUTC, channel 2 neg --> OUTD
-+ { .size = 5, .data = "\x25\x01\x02\x13\x45" },
-+ // DRC control (0x46): DRC off
-+ { .size = 5, .data = "\x46\x00\x00\x00\x00" },
-+ // BKND_ERR register (0x1C): 299ms reset period
-+ { .size = 2, .data = "\x1C\x07" },
-+ // Mute channel 3
-+ { .size = 2, .data = "\x0A\xFF" },
-+ // Volume configuration register (0x0E): volume slew 512 steps
-+ { .size = 2, .data = "\x0E\x90" },
-+ // Clock control register (0x00): 44/48kHz, MCLK=64xfs
-+ { .size = 2, .data = "\x00\x60" },
-+ // Bank switch and eq control (0x50): no bank switching
-+ { .size = 5, .data = "\x50\x00\x00\x00\x00" },
-+ // Volume registers (0x07, 0x08, 0x09, 0x0A)
-+ { .size = 2, .data = "\x07\x20" },
-+ { .size = 2, .data = "\x08\x30" },
-+ { .size = 2, .data = "\x09\x30" },
-+ { .size = 2, .data = "\x0A\xFF" },
-+ // 0x72, 0x73, 0x76, 0x77 input mixer:
-+ // no intermix between channels
-+ { .size = 5, .data = "\x72\x00\x00\x00\x00" },
-+ { .size = 5, .data = "\x73\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x76\x00\x00\x00\x00" },
-+ { .size = 5, .data = "\x77\x00\x80\x00\x00" },
-+ // 0x70, 0x71, 0x74, 0x75 inline DRC mixer:
-+ // no inline DRC inmix
-+ { .size = 5, .data = "\x70\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x71\x00\x00\x00\x00" },
-+ { .size = 5, .data = "\x74\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x75\x00\x00\x00\x00" },
-+ // 0x56, 0x57 Output scale
-+ { .size = 5, .data = "\x56\x00\x80\x00\x00" },
-+ { .size = 5, .data = "\x57\x00\x02\x00\x00" },
-+ // 0x3B, 0x3c
-+ { .size = 9, .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" },
-+ { .size = 9, .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ { .size = 9, .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" },
-+ { .size = 9, .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ { .size = 9, .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ { .size = 9, .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+ // 0x51, 0x52: output mixer
-+ { .size = 9, .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" },
-+ { .size = 9, .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" },
-+ // PEQ defaults
-+ { .size = 21, .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+ { .size = 21, .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+};
-+
-+
-+#endif /* _TAS5713_H */
-diff -Nur linux-3.18.14/sound/soc/codecs/wm8804.c linux-rpi/sound/soc/codecs/wm8804.c
---- linux-3.18.14/sound/soc/codecs/wm8804.c 2015-05-20 10:04:50.000000000 -0500
-+++ linux-rpi/sound/soc/codecs/wm8804.c 2015-05-31 14:46:14.565660946 -0500
-@@ -278,6 +278,7 @@
- blen = 0x1;
- break;
- case 24:
-+ case 32:
- blen = 0x2;
- break;
- default:
-@@ -624,7 +625,7 @@
- };
-
- #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
-- SNDRV_PCM_FMTBIT_S24_LE)
-+ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
-
- #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
- SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
-@@ -655,7 +656,7 @@
- .probe = wm8804_probe,
- .remove = wm8804_remove,
- .set_bias_level = wm8804_set_bias_level,
-- .idle_bias_off = true,
-+ .idle_bias_off = false,
-
- .controls = wm8804_snd_controls,
- .num_controls = ARRAY_SIZE(wm8804_snd_controls),
diff --git a/target/arm/bcm28xx/patches/3.18.16/0001-i2s-allow-to-enable-ALSA-MMAP.patch b/target/arm/bcm28xx/patches/3.18.16/0001-i2s-allow-to-enable-ALSA-MMAP.patch
deleted file mode 100644
index 2df6ea512..000000000
--- a/target/arm/bcm28xx/patches/3.18.16/0001-i2s-allow-to-enable-ALSA-MMAP.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From d017ad0179e407a81ed2423f7620d46584470ad4 Mon Sep 17 00:00:00 2001
-From: Waldemar Brodkorb <wbrodkorb@conet.de>
-Date: Thu, 26 Mar 2015 13:00:07 +0100
-Subject: [PATCH] i2s: allow to enable ALSA MMAP
-
-For some ALSA plugins like dmix MMAP is required.
-Allow to enable it via a module parameter called use_mmap.
-
-Signed-off-by: Waldemar Brodkorb <wbrodkorb@conet.de>
----
- sound/soc/bcm/bcm2708-i2s.c | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c
-index 7570e50..3d3692f 100644
---- a/sound/soc/bcm/bcm2708-i2s.c
-+++ b/sound/soc/bcm/bcm2708-i2s.c
-@@ -171,6 +171,11 @@ static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
- /* I2S pin configuration */
- static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO;
-
-+static bool use_mmap = 0;
-+module_param(use_mmap, bool, S_IRUGO);
-+MODULE_PARM_DESC(use_mmap, "Use MMAP");
-+
-+
- /* General device struct */
- struct bcm2708_i2s_dev {
- struct device *dev;
-@@ -874,7 +879,7 @@ static const struct snd_soc_component_driver bcm2708_i2s_component = {
- .name = "bcm2708-i2s-comp",
- };
-
--static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
-+static struct snd_pcm_hardware bcm2708_pcm_hardware = {
- .info = SNDRV_PCM_INFO_INTERLEAVED |
- SNDRV_PCM_INFO_JOINT_DUPLEX,
- .formats = SNDRV_PCM_FMTBIT_S16_LE |
-@@ -966,6 +971,12 @@ static int bcm2708_i2s_probe(struct platform_device *pdev)
- return ret;
- }
-
-+ if (use_mmap) {
-+ printk("Enable ALSA MMAP support for I2S\n");
-+ bcm2708_pcm_hardware.info |= SNDRV_PCM_INFO_MMAP;
-+ bcm2708_pcm_hardware.info |= SNDRV_PCM_INFO_MMAP_VALID;
-+ }
-+
- ret = snd_dmaengine_pcm_register(&pdev->dev,
- &bcm2708_dmaengine_pcm_config,
- SND_DMAENGINE_PCM_FLAG_COMPAT);
---
-1.9.1
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-26 03:04:27 +0000