From 3e0b19f27bba5c47cfe4ea836ef94aad687c14b4 Mon Sep 17 00:00:00 2001
From: Carmelo Amoroso <carmelo.amoroso@st.com>
Date: Mon, 14 Jun 2010 09:39:44 +0200
Subject: sh4: Fixes for SH-4 without an FPU

This patch disables SH-4 optimizations that rely on the FPU when
building for variants that don't have an FPU, such as SH-4AL.

Signed-off-by: Andrew Stubbs <ams@codesourcery.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
---
 libc/string/sh/sh4/memcpy.S  | 2 +-
 libc/string/sh/sh4/memmove.c | 6 +++++-
 libc/string/sh/sh4/memset.S  | 2 +-
 3 files changed, 7 insertions(+), 3 deletions(-)

(limited to 'libc/string/sh')

diff --git a/libc/string/sh/sh4/memcpy.S b/libc/string/sh/sh4/memcpy.S
index efdaf8bba..252ef36eb 100644
--- a/libc/string/sh/sh4/memcpy.S
+++ b/libc/string/sh/sh4/memcpy.S
@@ -21,7 +21,7 @@
 #include <sysdep.h>
 #include <endian.h>
 
-#ifdef __LITTLE_ENDIAN__
+#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__)
 #define	MEMCPY_USES_FPU
 /* Use paired single precision load or store mode for 64-bit tranfering.
  * FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.
diff --git a/libc/string/sh/sh4/memmove.c b/libc/string/sh/sh4/memmove.c
index 4d52db2ca..62fe8187d 100644
--- a/libc/string/sh/sh4/memmove.c
+++ b/libc/string/sh/sh4/memmove.c
@@ -7,8 +7,11 @@
  * Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
  */
 
-#include <string.h>
+#ifndef __SH_FPU_ANY__
+#include "../../generic/memmove.c"
+#else
 
+#include <string.h>
 
 #define FPSCR_SR	(1 << 20)
 #define STORE_FPSCR(x)	__asm__ volatile("sts fpscr, %0" : "=r"(x))
@@ -115,3 +118,4 @@ void *memmove(void *dest, const void *src, size_t len)
 }
 
 libc_hidden_def(memmove)
+#endif /*__SH_FPU_ANY__ */
diff --git a/libc/string/sh/sh4/memset.S b/libc/string/sh/sh4/memset.S
index 1a57cb969..83f874612 100644
--- a/libc/string/sh/sh4/memset.S
+++ b/libc/string/sh/sh4/memset.S
@@ -17,7 +17,7 @@
 
 #include <sysdep.h>
 
-#ifdef __LITTLE_ENDIAN__
+#if defined (__LITTLE_ENDIAN__) && defined (__SH_FPU_ANY__)
 #define MEMSET_USES_FPU
 /* Use paired single precision load or store mode for 64-bit tranfering.
  * FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.
-- 
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