From 033e30653835c5c3fc785ab60e6a110203e6241d Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Fri, 23 May 2014 12:05:38 +0200 Subject: resolve merge --- target/arm/cubox-i/patches/3.15-rc5/rmk.patch | 12476 -------------- .../patches/3.15-rc5/sdma-firmware-cubox-i.patch | 131 - target/arm/cubox-i/patches/3.15-rc6/rmk.patch | 12452 ++++++++++++++ .../patches/3.15-rc6/sdma-firmware-cubox-i.patch | 131 + target/linux/config/Config.in.graphics | 2 +- .../linux/patches/3.15-rc5/bsd-compatibility.patch | 2538 --- target/linux/patches/3.15-rc5/defaults.patch | 46 - .../linux/patches/3.15-rc5/disable-netfilter.patch | 160 - .../patches/3.15-rc5/export-symbol-for-exmap.patch | 11 - target/linux/patches/3.15-rc5/gemalto.patch | 11 - .../patches/3.15-rc5/initramfs-nosizelimit.patch | 57 - target/linux/patches/3.15-rc5/lemote-rfkill.patch | 21 - target/linux/patches/3.15-rc5/microblaze-axi.patch | 11 - .../patches/3.15-rc5/microblaze-ethernet.patch | 11 - target/linux/patches/3.15-rc5/mtd-rootfs.patch | 26 - target/linux/patches/3.15-rc5/nfsv3-tcp.patch | 12 - target/linux/patches/3.15-rc5/non-static.patch | 33 - .../patches/3.15-rc5/ppc64-missing-zlib.patch | 11 - target/linux/patches/3.15-rc5/startup.patch | 37 - target/linux/patches/3.15-rc5/uuid.patch | 263 - target/linux/patches/3.15-rc5/wlan-cf.patch | 11 - target/linux/patches/3.15-rc5/xargs.patch | 12 - target/linux/patches/3.15-rc5/yaffs2.patch | 16551 ------------------- target/linux/patches/3.15-rc5/zlib-inflate.patch | 12 - .../linux/patches/3.15-rc6/bsd-compatibility.patch | 2538 +++ target/linux/patches/3.15-rc6/defaults.patch | 46 + .../linux/patches/3.15-rc6/disable-netfilter.patch | 160 + .../patches/3.15-rc6/export-symbol-for-exmap.patch | 11 + target/linux/patches/3.15-rc6/gemalto.patch | 11 + .../patches/3.15-rc6/initramfs-nosizelimit.patch | 57 + target/linux/patches/3.15-rc6/lemote-rfkill.patch | 21 + target/linux/patches/3.15-rc6/microblaze-axi.patch | 11 + .../patches/3.15-rc6/microblaze-ethernet.patch | 11 + target/linux/patches/3.15-rc6/mtd-rootfs.patch | 26 + target/linux/patches/3.15-rc6/nfsv3-tcp.patch | 12 + target/linux/patches/3.15-rc6/non-static.patch | 33 + .../patches/3.15-rc6/ppc64-missing-zlib.patch | 11 + target/linux/patches/3.15-rc6/startup.patch | 37 + target/linux/patches/3.15-rc6/uuid.patch | 263 + target/linux/patches/3.15-rc6/wlan-cf.patch | 11 + target/linux/patches/3.15-rc6/xargs.patch | 12 + target/linux/patches/3.15-rc6/yaffs2.patch | 16551 +++++++++++++++++++ target/linux/patches/3.15-rc6/zlib-inflate.patch | 12 + 43 files changed, 32418 insertions(+), 32442 deletions(-) delete mode 100644 target/arm/cubox-i/patches/3.15-rc5/rmk.patch delete mode 100644 target/arm/cubox-i/patches/3.15-rc5/sdma-firmware-cubox-i.patch create mode 100644 target/arm/cubox-i/patches/3.15-rc6/rmk.patch create mode 100644 target/arm/cubox-i/patches/3.15-rc6/sdma-firmware-cubox-i.patch delete mode 100644 target/linux/patches/3.15-rc5/bsd-compatibility.patch delete mode 100644 target/linux/patches/3.15-rc5/defaults.patch delete mode 100644 target/linux/patches/3.15-rc5/disable-netfilter.patch delete mode 100644 target/linux/patches/3.15-rc5/export-symbol-for-exmap.patch delete mode 100644 target/linux/patches/3.15-rc5/gemalto.patch delete mode 100644 target/linux/patches/3.15-rc5/initramfs-nosizelimit.patch delete mode 100644 target/linux/patches/3.15-rc5/lemote-rfkill.patch delete mode 100644 target/linux/patches/3.15-rc5/microblaze-axi.patch delete mode 100644 target/linux/patches/3.15-rc5/microblaze-ethernet.patch delete mode 100644 target/linux/patches/3.15-rc5/mtd-rootfs.patch delete mode 100644 target/linux/patches/3.15-rc5/nfsv3-tcp.patch delete mode 100644 target/linux/patches/3.15-rc5/non-static.patch delete mode 100644 target/linux/patches/3.15-rc5/ppc64-missing-zlib.patch delete mode 100644 target/linux/patches/3.15-rc5/startup.patch delete mode 100644 target/linux/patches/3.15-rc5/uuid.patch delete mode 100644 target/linux/patches/3.15-rc5/wlan-cf.patch delete mode 100644 target/linux/patches/3.15-rc5/xargs.patch delete mode 100644 target/linux/patches/3.15-rc5/yaffs2.patch delete mode 100644 target/linux/patches/3.15-rc5/zlib-inflate.patch create mode 100644 target/linux/patches/3.15-rc6/bsd-compatibility.patch create mode 100644 target/linux/patches/3.15-rc6/defaults.patch create mode 100644 target/linux/patches/3.15-rc6/disable-netfilter.patch create mode 100644 target/linux/patches/3.15-rc6/export-symbol-for-exmap.patch create mode 100644 target/linux/patches/3.15-rc6/gemalto.patch create mode 100644 target/linux/patches/3.15-rc6/initramfs-nosizelimit.patch create mode 100644 target/linux/patches/3.15-rc6/lemote-rfkill.patch create mode 100644 target/linux/patches/3.15-rc6/microblaze-axi.patch create mode 100644 target/linux/patches/3.15-rc6/microblaze-ethernet.patch create mode 100644 target/linux/patches/3.15-rc6/mtd-rootfs.patch create mode 100644 target/linux/patches/3.15-rc6/nfsv3-tcp.patch create mode 100644 target/linux/patches/3.15-rc6/non-static.patch create mode 100644 target/linux/patches/3.15-rc6/ppc64-missing-zlib.patch create mode 100644 target/linux/patches/3.15-rc6/startup.patch create mode 100644 target/linux/patches/3.15-rc6/uuid.patch create mode 100644 target/linux/patches/3.15-rc6/wlan-cf.patch create mode 100644 target/linux/patches/3.15-rc6/xargs.patch create mode 100644 target/linux/patches/3.15-rc6/yaffs2.patch create mode 100644 target/linux/patches/3.15-rc6/zlib-inflate.patch (limited to 'target') diff --git a/target/arm/cubox-i/patches/3.15-rc5/rmk.patch b/target/arm/cubox-i/patches/3.15-rc5/rmk.patch deleted file mode 100644 index ae847fc06..000000000 --- a/target/arm/cubox-i/patches/3.15-rc5/rmk.patch +++ /dev/null @@ -1,12476 +0,0 @@ -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts linux-3.15-rc4/arch/arm/boot/dts/imx6dl-hummingboard.dts ---- linux-3.15-rc4.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/imx6dl-hummingboard.dts 2014-05-07 17:05:41.464107257 +0200 -@@ -67,6 +67,14 @@ - status = "okay"; - }; - -+&hdmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard_hdmi>; -+ ddc-i2c-bus = <&i2c2>; -+ status = "okay"; -+ crtcs = <&ipu1 0>; -+}; -+ - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; -@@ -82,6 +90,13 @@ - */ - }; - -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard_i2c2>; -+ status = "okay"; -+}; -+ - &iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { -@@ -97,6 +112,12 @@ - >; - }; - -+ pinctrl_hummingboard_hdmi: hummingboard-hdmi { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 -+ >; -+ }; -+ - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -@@ -104,6 +125,13 @@ - >; - }; - -+ pinctrl_hummingboard_i2c2: hummingboard-i2c2 { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = ; - }; -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/imx6q-cubox-i.dts linux-3.15-rc4/arch/arm/boot/dts/imx6q-cubox-i.dts ---- linux-3.15-rc4.orig/arch/arm/boot/dts/imx6q-cubox-i.dts 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/imx6q-cubox-i.dts 2014-05-07 17:05:41.464107257 +0200 -@@ -13,4 +13,8 @@ - - &sata { - status = "okay"; -+ fsl,transmit-level-mV = <1104>; -+ fsl,transmit-boost-mdB = <0>; -+ fsl,transmit-atten-16ths = <9>; -+ fsl,no-spread-spectrum; - }; -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-3.15-rc4/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi ---- linux-3.15-rc4.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2014-05-07 17:05:41.464107257 +0200 -@@ -12,6 +12,19 @@ - pinctrl-0 = <&pinctrl_cubox_i_ir>; - }; - -+ pwmleds { -+ compatible = "pwm-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cubox_i_pwm1>; -+ -+ front { -+ active-low; -+ label = "imx6:red:front"; -+ max-brightness = <248>; -+ pwms = <&pwm1 0 50000>; -+ }; -+ }; -+ - regulators { - compatible = "simple-bus"; - -@@ -55,6 +68,21 @@ - }; - }; - -+&hdmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cubox_i_hdmi>; -+ ddc-i2c-bus = <&i2c2>; -+ status = "okay"; -+ crtcs = <&ipu1 0>; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cubox_i_i2c2>; -+ status = "okay"; -+}; -+ - &i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c3>; -@@ -69,6 +97,19 @@ - - &iomuxc { - cubox_i { -+ pinctrl_cubox_i_hdmi: cubox-i-hdmi { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 -+ >; -+ }; -+ -+ pinctrl_cubox_i_i2c2: cubox-i-i2c2 { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ - pinctrl_cubox_i_i2c3: cubox-i-i2c3 { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 -@@ -82,6 +123,10 @@ - >; - }; - -+ pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led { -+ fsl,pins = ; -+ }; -+ - pinctrl_cubox_i_spdif: cubox-i-spdif { - fsl,pins = ; - }; -@@ -111,6 +156,28 @@ - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; -+ -+ pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 -+ >; -+ }; -+ -+ pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 -+ >; -+ }; - }; - }; - -@@ -130,9 +197,19 @@ - status = "okay"; - }; - -+&uart4 { -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ status = "okay"; -+}; -+ - &usdhc2 { -- pinctrl-names = "default"; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>; -+ pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>; -+ pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 0>; - status = "okay"; -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/imx6qdl.dtsi linux-3.15-rc4/arch/arm/boot/dts/imx6qdl.dtsi ---- linux-3.15-rc4.orig/arch/arm/boot/dts/imx6qdl.dtsi 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/imx6qdl.dtsi 2014-05-07 17:05:41.464107257 +0200 -@@ -128,6 +128,8 @@ - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; -+ arm,dynamic-clk-gating; -+ arm,standby-mode; - }; - - pcie: pcie@0x01000000 { -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-3.15-rc4/arch/arm/boot/dts/imx6qdl-microsom.dtsi ---- linux-3.15-rc4.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2014-05-07 17:05:49.488157029 +0200 -@@ -1,9 +1,69 @@ - /* - * Copyright (C) 2013,2014 Russell King - */ -+#include -+/ { -+ regulators { -+ compatible = "simple-bus"; -+ -+ reg_brcm_osc: brcm-osc-reg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio5 5 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_osc_reg>; -+ regulator-name = "brcm_osc_reg"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ reg_brcm: brcm-reg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 19 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_reg>; -+ regulator-name = "brcm_reg"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <200000>; -+ }; -+ }; -+}; - - &iomuxc { - microsom { -+ pinctrl_microsom_brcm_osc_reg: microsom-brcm-osc-reg { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_reg: microsom-brcm-reg { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 -+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 -+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 -+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_bt: microsom-brcm-bt { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 -+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 -+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 -+ >; -+ }; -+ - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 -@@ -11,6 +71,15 @@ - >; - }; - -+ pinctrl_microsom_uart4_1: microsom-uart4 { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 -+ >; -+ }; -+ - pinctrl_microsom_usbotg: microsom-usbotg { - /* - * Similar to pinctrl_usbotg_2, but we want it -@@ -18,6 +87,17 @@ - */ - fsl,pins = ; - }; -+ -+ pinctrl_microsom_usdhc1: microsom-usdhc1 { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 -+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 -+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 -+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 -+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 -+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 -+ >; -+ }; - }; - }; - -@@ -27,7 +107,25 @@ - status = "okay"; - }; - -+/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4_1>; -+ fsl,uart-has-rtscts; -+}; -+ - &usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_microsom_usbotg>; - }; -+ -+/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -+&usdhc1 { -+ card-external-vcc-supply = <®_brcm>; -+ card-reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, <&gpio6 0 GPIO_ACTIVE_LOW>; -+ keep-power-in-suspend; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; -+ vmmc-supply = <®_brcm>; -+}; -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/imx6sl.dtsi linux-3.15-rc4/arch/arm/boot/dts/imx6sl.dtsi ---- linux-3.15-rc4.orig/arch/arm/boot/dts/imx6sl.dtsi 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/imx6sl.dtsi 2014-05-07 17:05:49.488157029 +0200 -@@ -111,6 +111,8 @@ - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; -+ arm,dynamic-clk-gating; -+ arm,standby-mode; - }; - - pmu { -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/marco.dtsi linux-3.15-rc4/arch/arm/boot/dts/marco.dtsi ---- linux-3.15-rc4.orig/arch/arm/boot/dts/marco.dtsi 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/marco.dtsi 2014-05-07 17:05:49.488157029 +0200 -@@ -36,7 +36,7 @@ - ranges = <0x40000000 0x40000000 0xa0000000>; - - l2-cache-controller@c0030000 { -- compatible = "sirf,marco-pl310-cache", "arm,pl310-cache"; -+ compatible = "arm,pl310-cache"; - reg = <0xc0030000 0x1000>; - interrupts = <0 59 0>; - arm,tag-latency = <1 1 1>; -diff -Nur linux-3.15-rc4.orig/arch/arm/boot/dts/prima2.dtsi linux-3.15-rc4/arch/arm/boot/dts/prima2.dtsi ---- linux-3.15-rc4.orig/arch/arm/boot/dts/prima2.dtsi 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/boot/dts/prima2.dtsi 2014-05-07 17:05:49.488157029 +0200 -@@ -48,7 +48,7 @@ - ranges = <0x40000000 0x40000000 0x80000000>; - - l2-cache-controller@80040000 { -- compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; -+ compatible = "arm,pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; -diff -Nur linux-3.15-rc4.orig/arch/arm/configs/imx_v6_v7_defconfig linux-3.15-rc4/arch/arm/configs/imx_v6_v7_defconfig ---- linux-3.15-rc4.orig/arch/arm/configs/imx_v6_v7_defconfig 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/configs/imx_v6_v7_defconfig 2014-05-07 17:05:49.488157029 +0200 -@@ -245,6 +245,7 @@ - CONFIG_DRM_IMX_LDB=y - CONFIG_DRM_IMX_IPUV3_CORE=y - CONFIG_DRM_IMX_IPUV3=y -+CONFIG_DRM_IMX_HDMI=y - CONFIG_COMMON_CLK_DEBUG=y - # CONFIG_IOMMU_SUPPORT is not set - CONFIG_PWM=y -diff -Nur linux-3.15-rc4.orig/arch/arm/include/asm/hardware/cache-l2x0.h linux-3.15-rc4/arch/arm/include/asm/hardware/cache-l2x0.h ---- linux-3.15-rc4.orig/arch/arm/include/asm/hardware/cache-l2x0.h 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/include/asm/hardware/cache-l2x0.h 2014-05-07 17:05:49.488157029 +0200 -@@ -26,8 +26,8 @@ - #define L2X0_CACHE_TYPE 0x004 - #define L2X0_CTRL 0x100 - #define L2X0_AUX_CTRL 0x104 --#define L2X0_TAG_LATENCY_CTRL 0x108 --#define L2X0_DATA_LATENCY_CTRL 0x10C -+#define L310_TAG_LATENCY_CTRL 0x108 -+#define L310_DATA_LATENCY_CTRL 0x10C - #define L2X0_EVENT_CNT_CTRL 0x200 - #define L2X0_EVENT_CNT1_CFG 0x204 - #define L2X0_EVENT_CNT0_CFG 0x208 -@@ -54,53 +54,93 @@ - #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 - #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 - #define L2X0_LOCKDOWN_STRIDE 0x08 --#define L2X0_ADDR_FILTER_START 0xC00 --#define L2X0_ADDR_FILTER_END 0xC04 -+#define L310_ADDR_FILTER_START 0xC00 -+#define L310_ADDR_FILTER_END 0xC04 - #define L2X0_TEST_OPERATION 0xF00 - #define L2X0_LINE_DATA 0xF10 - #define L2X0_LINE_TAG 0xF30 - #define L2X0_DEBUG_CTRL 0xF40 --#define L2X0_PREFETCH_CTRL 0xF60 --#define L2X0_POWER_CTRL 0xF80 --#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) --#define L2X0_STNDBY_MODE_EN (1 << 0) -+#define L310_PREFETCH_CTRL 0xF60 -+#define L310_POWER_CTRL 0xF80 -+#define L310_DYNAMIC_CLK_GATING_EN (1 << 1) -+#define L310_STNDBY_MODE_EN (1 << 0) - - /* Registers shifts and masks */ - #define L2X0_CACHE_ID_PART_MASK (0xf << 6) - #define L2X0_CACHE_ID_PART_L210 (1 << 6) -+#define L2X0_CACHE_ID_PART_L220 (2 << 6) - #define L2X0_CACHE_ID_PART_L310 (3 << 6) - #define L2X0_CACHE_ID_RTL_MASK 0x3f --#define L2X0_CACHE_ID_RTL_R0P0 0x0 --#define L2X0_CACHE_ID_RTL_R1P0 0x2 --#define L2X0_CACHE_ID_RTL_R2P0 0x4 --#define L2X0_CACHE_ID_RTL_R3P0 0x5 --#define L2X0_CACHE_ID_RTL_R3P1 0x6 --#define L2X0_CACHE_ID_RTL_R3P2 0x8 -- --#define L2X0_AUX_CTRL_MASK 0xc0000fff -+#define L210_CACHE_ID_RTL_R0P2_02 0x00 -+#define L210_CACHE_ID_RTL_R0P1 0x01 -+#define L210_CACHE_ID_RTL_R0P2_01 0x02 -+#define L210_CACHE_ID_RTL_R0P3 0x03 -+#define L210_CACHE_ID_RTL_R0P4 0x0b -+#define L210_CACHE_ID_RTL_R0P5 0x0f -+#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06 -+#define L310_CACHE_ID_RTL_R0P0 0x00 -+#define L310_CACHE_ID_RTL_R1P0 0x02 -+#define L310_CACHE_ID_RTL_R2P0 0x04 -+#define L310_CACHE_ID_RTL_R3P0 0x05 -+#define L310_CACHE_ID_RTL_R3P1 0x06 -+#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07 -+#define L310_CACHE_ID_RTL_R3P2 0x08 -+#define L310_CACHE_ID_RTL_R3P3 0x09 -+ -+/* L2C auxiliary control register - bits common to L2C-210/220/310 */ -+#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17 -+#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17) -+#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17) -+#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20) -+#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21) -+#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22) -+/* L2C-210/220 common bits */ - #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 --#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 -+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0) - #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 --#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) -+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3) - #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 --#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) -+#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6) - #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 --#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) --#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 --#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 --#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) --#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 --#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 --#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 --#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 --#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 --#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 -- --#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0 --#define L2X0_LATENCY_CTRL_RD_SHIFT 4 --#define L2X0_LATENCY_CTRL_WR_SHIFT 8 -- --#define L2X0_ADDR_FILTER_EN 1 -+#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) -+#define L2X0_AUX_CTRL_ASSOC_SHIFT 13 -+#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) -+/* L2C-210 specific bits */ -+#define L210_AUX_CTRL_WRAP_DISABLE BIT(12) -+#define L210_AUX_CTRL_WA_OVERRIDE BIT(23) -+#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24) -+/* L2C-220 specific bits */ -+#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) -+#define L220_AUX_CTRL_FWA_SHIFT 23 -+#define L220_AUX_CTRL_FWA_MASK (3 << 23) -+#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) -+#define L220_AUX_CTRL_NS_INT_CTRL BIT(27) -+/* L2C-310 specific bits */ -+#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ -+#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */ -+#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */ -+#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) -+#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) -+#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ -+#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) -+#define L310_AUX_CTRL_NS_INT_CTRL BIT(27) -+#define L310_AUX_CTRL_DATA_PREFETCH BIT(28) -+#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) -+#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ -+ -+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) -+#define L310_LATENCY_CTRL_RD(n) ((n) << 4) -+#define L310_LATENCY_CTRL_WR(n) ((n) << 8) -+ -+#define L310_ADDR_FILTER_EN 1 -+ -+#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f -+#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23) -+#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24) -+#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27) -+#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) -+#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29) -+#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30) - - #define L2X0_CTRL_EN 1 - -diff -Nur linux-3.15-rc4.orig/arch/arm/include/asm/outercache.h linux-3.15-rc4/arch/arm/include/asm/outercache.h ---- linux-3.15-rc4.orig/arch/arm/include/asm/outercache.h 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/include/asm/outercache.h 2014-05-07 17:05:49.488157029 +0200 -@@ -21,6 +21,7 @@ - #ifndef __ASM_OUTERCACHE_H - #define __ASM_OUTERCACHE_H - -+#include - #include - - struct outer_cache_fns { -@@ -28,53 +29,84 @@ - void (*clean_range)(unsigned long, unsigned long); - void (*flush_range)(unsigned long, unsigned long); - void (*flush_all)(void); -- void (*inv_all)(void); - void (*disable)(void); - #ifdef CONFIG_OUTER_CACHE_SYNC - void (*sync)(void); - #endif -- void (*set_debug)(unsigned long); - void (*resume)(void); -+ -+ /* This is an ARM L2C thing */ -+ void (*write_sec)(unsigned long, unsigned); - }; - - extern struct outer_cache_fns outer_cache; - - #ifdef CONFIG_OUTER_CACHE -- -+/** -+ * outer_inv_range - invalidate range of outer cache lines -+ * @start: starting physical address, inclusive -+ * @end: end physical address, exclusive -+ */ - static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) - { - if (outer_cache.inv_range) - outer_cache.inv_range(start, end); - } -+ -+/** -+ * outer_clean_range - clean dirty outer cache lines -+ * @start: starting physical address, inclusive -+ * @end: end physical address, exclusive -+ */ - static inline void outer_clean_range(phys_addr_t start, phys_addr_t end) - { - if (outer_cache.clean_range) - outer_cache.clean_range(start, end); - } -+ -+/** -+ * outer_flush_range - clean and invalidate outer cache lines -+ * @start: starting physical address, inclusive -+ * @end: end physical address, exclusive -+ */ - static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) - { - if (outer_cache.flush_range) - outer_cache.flush_range(start, end); - } - -+/** -+ * outer_flush_all - clean and invalidate all cache lines in the outer cache -+ * -+ * Note: depending on implementation, this may not be atomic - it must -+ * only be called with interrupts disabled and no other active outer -+ * cache masters. -+ * -+ * It is intended that this function is only used by implementations -+ * needing to override the outer_cache.disable() method due to security. -+ * (Some implementations perform this as a clean followed by an invalidate.) -+ */ - static inline void outer_flush_all(void) - { - if (outer_cache.flush_all) - outer_cache.flush_all(); - } - --static inline void outer_inv_all(void) --{ -- if (outer_cache.inv_all) -- outer_cache.inv_all(); --} -- --static inline void outer_disable(void) --{ -- if (outer_cache.disable) -- outer_cache.disable(); --} -- -+/** -+ * outer_disable - clean, invalidate and disable the outer cache -+ * -+ * Disable the outer cache, ensuring that any data contained in the outer -+ * cache is pushed out to lower levels of system memory. The note and -+ * conditions above concerning outer_flush_all() applies here. -+ */ -+extern void outer_disable(void); -+ -+/** -+ * outer_resume - restore the cache configuration and re-enable outer cache -+ * -+ * Restore any configuration that the cache had when previously enabled, -+ * and re-enable the outer cache. -+ */ - static inline void outer_resume(void) - { - if (outer_cache.resume) -@@ -90,13 +122,18 @@ - static inline void outer_flush_range(phys_addr_t start, phys_addr_t end) - { } - static inline void outer_flush_all(void) { } --static inline void outer_inv_all(void) { } - static inline void outer_disable(void) { } - static inline void outer_resume(void) { } - - #endif - - #ifdef CONFIG_OUTER_CACHE_SYNC -+/** -+ * outer_sync - perform a sync point for outer cache -+ * -+ * Ensure that all outer cache operations are complete and any store -+ * buffers are drained. -+ */ - static inline void outer_sync(void) - { - if (outer_cache.sync) -diff -Nur linux-3.15-rc4.orig/arch/arm/Kconfig linux-3.15-rc4/arch/arm/Kconfig ---- linux-3.15-rc4.orig/arch/arm/Kconfig 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/Kconfig 2014-05-07 17:05:49.488157029 +0200 -@@ -1230,19 +1230,6 @@ - register of the Cortex-A9 which reduces the linefill issuing - capabilities of the processor. - --config PL310_ERRATA_588369 -- bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" -- depends on CACHE_L2X0 -- help -- The PL310 L2 cache controller implements three types of Clean & -- Invalidate maintenance operations: by Physical Address -- (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). -- They are architecturally defined to behave as the execution of a -- clean operation followed immediately by an invalidate operation, -- both performing to the same memory location. This functionality -- is not correctly implemented in PL310 as clean lines are not -- invalidated as a result of these operations. -- - config ARM_ERRATA_643719 - bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" - depends on CPU_V7 && SMP -@@ -1265,17 +1252,6 @@ - tables. The workaround changes the TLB flushing routines to invalidate - entries regardless of the ASID. - --config PL310_ERRATA_727915 -- bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" -- depends on CACHE_L2X0 -- help -- PL310 implements the Clean & Invalidate by Way L2 cache maintenance -- operation (offset 0x7FC). This operation runs in background so that -- PL310 can handle normal accesses while it is in progress. Under very -- rare circumstances, due to this erratum, write data can be lost when -- PL310 treats a cacheable write transaction during a Clean & -- Invalidate by Way operation. -- - config ARM_ERRATA_743622 - bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" - depends on CPU_V7 -@@ -1301,21 +1277,6 @@ - operation is received by a CPU before the ICIALLUIS has completed, - potentially leading to corrupted entries in the cache or TLB. - --config PL310_ERRATA_753970 -- bool "PL310 errata: cache sync operation may be faulty" -- depends on CACHE_PL310 -- help -- This option enables the workaround for the 753970 PL310 (r3p0) erratum. -- -- Under some condition the effect of cache sync operation on -- the store buffer still remains when the operation completes. -- This means that the store buffer is always asked to drain and -- this prevents it from merging any further writes. The workaround -- is to replace the normal offset of cache sync operation (0x730) -- by another offset targeting an unmapped PL310 register 0x740. -- This has the same effect as the cache sync operation: store buffer -- drain and waiting for all buffers empty. -- - config ARM_ERRATA_754322 - bool "ARM errata: possible faulty MMU translations following an ASID switch" - depends on CPU_V7 -@@ -1364,18 +1325,6 @@ - relevant cache maintenance functions and sets a specific bit - in the diagnostic control register of the SCU. - --config PL310_ERRATA_769419 -- bool "PL310 errata: no automatic Store Buffer drain" -- depends on CACHE_L2X0 -- help -- On revisions of the PL310 prior to r3p2, the Store Buffer does -- not automatically drain. This can cause normal, non-cacheable -- writes to be retained when the memory system is idle, leading -- to suboptimal I/O performance for drivers using coherent DMA. -- This option adds a write barrier to the cpu_idle loop so that, -- on systems with an outer cache, the store buffer is drained -- explicitly. -- - config ARM_ERRATA_775420 - bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" - depends on CPU_V7 -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-berlin/berlin.c linux-3.15-rc4/arch/arm/mach-berlin/berlin.c ---- linux-3.15-rc4.orig/arch/arm/mach-berlin/berlin.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-berlin/berlin.c 2014-05-07 17:05:49.492157054 +0200 -@@ -24,7 +24,7 @@ - * with DT probing for L2CCs, berlin_init_machine can be removed. - * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc - */ -- l2x0_of_init(0x70c00000, 0xfeffffff); -+ l2x0_of_init(0x30c00000, 0xfeffffff); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-cns3xxx/core.c linux-3.15-rc4/arch/arm/mach-cns3xxx/core.c ---- linux-3.15-rc4.orig/arch/arm/mach-cns3xxx/core.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-cns3xxx/core.c 2014-05-07 17:05:49.492157054 +0200 -@@ -272,9 +272,9 @@ - * - * 1 cycle of latency for setup, read and write accesses - */ -- val = readl(base + L2X0_TAG_LATENCY_CTRL); -+ val = readl(base + L310_TAG_LATENCY_CTRL); - val &= 0xfffff888; -- writel(val, base + L2X0_TAG_LATENCY_CTRL); -+ writel(val, base + L310_TAG_LATENCY_CTRL); - - /* - * Data RAM Control register -@@ -285,12 +285,12 @@ - * - * 1 cycle of latency for setup, read and write accesses - */ -- val = readl(base + L2X0_DATA_LATENCY_CTRL); -+ val = readl(base + L310_DATA_LATENCY_CTRL); - val &= 0xfffff888; -- writel(val, base + L2X0_DATA_LATENCY_CTRL); -+ writel(val, base + L310_DATA_LATENCY_CTRL); - - /* 32 KiB, 8-way, parity disable */ -- l2x0_init(base, 0x00540000, 0xfe000fff); -+ l2x0_init(base, 0x00500000, 0xfe0f0fff); - } - - #endif /* CONFIG_CACHE_L2X0 */ -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-exynos/common.h linux-3.15-rc4/arch/arm/mach-exynos/common.h ---- linux-3.15-rc4.orig/arch/arm/mach-exynos/common.h 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-exynos/common.h 2014-05-07 17:05:49.492157054 +0200 -@@ -55,7 +55,6 @@ - NUM_SYS_POWERDOWN, - }; - --extern unsigned long l2x0_regs_phys; - struct exynos_pmu_conf { - void __iomem *reg; - unsigned int val[NUM_SYS_POWERDOWN]; -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-exynos/exynos.c linux-3.15-rc4/arch/arm/mach-exynos/exynos.c ---- linux-3.15-rc4.orig/arch/arm/mach-exynos/exynos.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-exynos/exynos.c 2014-05-07 17:05:49.492157054 +0200 -@@ -32,9 +32,6 @@ - #include "mfc.h" - #include "regs-pmu.h" - --#define L2_AUX_VAL 0x7C470001 --#define L2_AUX_MASK 0xC200ffff -- - static struct map_desc exynos4_iodesc[] __initdata = { - { - .virtual = (unsigned long)S3C_VA_SYS, -@@ -321,17 +318,7 @@ - - static int __init exynos4_l2x0_cache_init(void) - { -- int ret; -- -- ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); -- if (ret) -- return ret; -- -- if (IS_ENABLED(CONFIG_S5P_SLEEP)) { -- l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); -- clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); -- } -- return 0; -+ return l2x0_of_init(0x3c400001, 0xc20fffff); - } - early_initcall(exynos4_l2x0_cache_init); - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-exynos/sleep.S linux-3.15-rc4/arch/arm/mach-exynos/sleep.S ---- linux-3.15-rc4.orig/arch/arm/mach-exynos/sleep.S 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-exynos/sleep.S 2014-05-07 17:05:49.492157054 +0200 -@@ -16,8 +16,6 @@ - */ - - #include --#include --#include - - #define CPU_MASK 0xff0ffff0 - #define CPU_CORTEX_A9 0x410fc090 -@@ -53,33 +51,7 @@ - and r0, r0, r1 - ldr r1, =CPU_CORTEX_A9 - cmp r0, r1 -- bne skip_l2_resume -- adr r0, l2x0_regs_phys -- ldr r0, [r0] -- cmp r0, #0 -- beq skip_l2_resume -- ldr r1, [r0, #L2X0_R_PHY_BASE] -- ldr r2, [r1, #L2X0_CTRL] -- tst r2, #0x1 -- bne skip_l2_resume -- ldr r2, [r0, #L2X0_R_AUX_CTRL] -- str r2, [r1, #L2X0_AUX_CTRL] -- ldr r2, [r0, #L2X0_R_TAG_LATENCY] -- str r2, [r1, #L2X0_TAG_LATENCY_CTRL] -- ldr r2, [r0, #L2X0_R_DATA_LATENCY] -- str r2, [r1, #L2X0_DATA_LATENCY_CTRL] -- ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] -- str r2, [r1, #L2X0_PREFETCH_CTRL] -- ldr r2, [r0, #L2X0_R_PWR_CTRL] -- str r2, [r1, #L2X0_POWER_CTRL] -- mov r2, #1 -- str r2, [r1, #L2X0_CTRL] --skip_l2_resume: -+ bleq l2c310_early_resume - #endif - b cpu_resume - ENDPROC(exynos_cpu_resume) --#ifdef CONFIG_CACHE_L2X0 -- .globl l2x0_regs_phys --l2x0_regs_phys: -- .long 0 --#endif -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-highbank/highbank.c linux-3.15-rc4/arch/arm/mach-highbank/highbank.c ---- linux-3.15-rc4.orig/arch/arm/mach-highbank/highbank.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-highbank/highbank.c 2014-05-07 17:05:49.492157054 +0200 -@@ -51,11 +51,13 @@ - } - - --static void highbank_l2x0_disable(void) -+static void highbank_l2c310_write_sec(unsigned long val, unsigned reg) - { -- outer_flush_all(); -- /* Disable PL310 L2 Cache controller */ -- highbank_smc1(0x102, 0x0); -+ if (reg == L2X0_CTRL) -+ highbank_smc1(0x102, val); -+ else -+ WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n", -+ reg); - } - - static void __init highbank_init_irq(void) -@@ -66,11 +68,9 @@ - highbank_scu_map_io(); - - /* Enable PL310 L2 Cache controller */ -- if (IS_ENABLED(CONFIG_CACHE_L2X0) && -- of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) { -- highbank_smc1(0x102, 0x1); -- l2x0_of_init(0, ~0UL); -- outer_cache.disable = highbank_l2x0_disable; -+ if (IS_ENABLED(CONFIG_CACHE_L2X0)) { -+ outer_cache.write_sec = highbank_l2c310_write_sec; -+ l2x0_of_init(0, ~0); - } - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-imx/clk-pllv3.c linux-3.15-rc4/arch/arm/mach-imx/clk-pllv3.c ---- linux-3.15-rc4.orig/arch/arm/mach-imx/clk-pllv3.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-imx/clk-pllv3.c 2014-05-07 17:05:51.040166651 +0200 -@@ -273,9 +273,10 @@ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long min_rate = parent_rate * 27; - unsigned long max_rate = parent_rate * 54; -- u32 val, div; -+ u32 val, newval, div; - u32 mfn, mfd = 1000000; - s64 temp64; -+ int ret; - - if (rate < min_rate || rate > max_rate) - return -EINVAL; -@@ -287,13 +288,27 @@ - mfn = temp64; - - val = readl_relaxed(pll->base); -- val &= ~pll->div_mask; -- val |= div; -- writel_relaxed(val, pll->base); -+ -+ /* set the PLL into bypass mode */ -+ newval = val | BM_PLL_BYPASS; -+ writel_relaxed(newval, pll->base); -+ -+ /* configure the new frequency */ -+ newval &= ~pll->div_mask; -+ newval |= div; -+ writel_relaxed(newval, pll->base); - writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); -- writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); -+ writel(mfd, pll->base + PLL_DENOM_OFFSET); -+ -+ ret = clk_pllv3_wait_lock(pll); -+ if (ret == 0 && val & BM_PLL_POWER) { -+ /* only if it locked can we switch back to the PLL */ -+ newval &= ~BM_PLL_BYPASS; -+ newval |= val & BM_PLL_BYPASS; -+ writel(newval, pll->base); -+ } - -- return clk_pllv3_wait_lock(pll); -+ return ret; - } - - static const struct clk_ops clk_pllv3_av_ops = { -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-imx/mach-vf610.c linux-3.15-rc4/arch/arm/mach-imx/mach-vf610.c ---- linux-3.15-rc4.orig/arch/arm/mach-imx/mach-vf610.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-imx/mach-vf610.c 2014-05-07 17:05:51.040166651 +0200 -@@ -22,7 +22,7 @@ - - static void __init vf610_init_irq(void) - { -- l2x0_of_init(0, ~0UL); -+ l2x0_of_init(0, ~0); - irqchip_init(); - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-imx/suspend-imx6.S linux-3.15-rc4/arch/arm/mach-imx/suspend-imx6.S ---- linux-3.15-rc4.orig/arch/arm/mach-imx/suspend-imx6.S 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-imx/suspend-imx6.S 2014-05-07 17:05:51.040166651 +0200 -@@ -334,28 +334,10 @@ - * turned into relative ones. - */ - --#ifdef CONFIG_CACHE_L2X0 -- .macro pl310_resume -- adr r0, l2x0_saved_regs_offset -- ldr r2, [r0] -- add r2, r2, r0 -- ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 -- ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value -- str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl -- mov r1, #0x1 -- str r1, [r0, #L2X0_CTRL] @ re-enable L2 -- .endm -- --l2x0_saved_regs_offset: -- .word l2x0_saved_regs - . -- --#else -- .macro pl310_resume -- .endm --#endif -- - ENTRY(v7_cpu_resume) - bl v7_invalidate_l1 -- pl310_resume -+#ifdef CONFIG_CACHE_L2X0 -+ bl l2c310_early_resume -+#endif - b cpu_resume - ENDPROC(v7_cpu_resume) -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-imx/system.c linux-3.15-rc4/arch/arm/mach-imx/system.c ---- linux-3.15-rc4.orig/arch/arm/mach-imx/system.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-imx/system.c 2014-05-07 17:05:51.040166651 +0200 -@@ -124,7 +124,7 @@ - } - - /* Configure the L2 PREFETCH and POWER registers */ -- val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); -+ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); - val |= 0x70800000; - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 -@@ -137,14 +137,12 @@ - */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); -- writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); -- val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; -- writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); -+ writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); - - iounmap(l2x0_base); - of_node_put(np); - - out: -- l2x0_of_init(0, ~0UL); -+ l2x0_of_init(0, ~0); - } - #endif -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-mvebu/board-v7.c linux-3.15-rc4/arch/arm/mach-mvebu/board-v7.c ---- linux-3.15-rc4.orig/arch/arm/mach-mvebu/board-v7.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-mvebu/board-v7.c 2014-05-07 17:05:51.040166651 +0200 -@@ -60,7 +60,7 @@ - coherency_init(); - BUG_ON(mvebu_mbus_dt_init()); - #ifdef CONFIG_CACHE_L2X0 -- l2x0_of_init(0, ~0UL); -+ l2x0_of_init(0, ~0); - #endif - - if (of_machine_is_compatible("marvell,armada375")) -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-nomadik/cpu-8815.c linux-3.15-rc4/arch/arm/mach-nomadik/cpu-8815.c ---- linux-3.15-rc4.orig/arch/arm/mach-nomadik/cpu-8815.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-nomadik/cpu-8815.c 2014-05-07 17:05:51.040166651 +0200 -@@ -147,7 +147,7 @@ - { - #ifdef CONFIG_CACHE_L2X0 - /* At full speed latency must be >=2, so 0x249 in low bits */ -- l2x0_of_init(0x00730249, 0xfe000fff); -+ l2x0_of_init(0x00700249, 0xfe0fefff); - #endif - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - } -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-omap2/common.h linux-3.15-rc4/arch/arm/mach-omap2/common.h ---- linux-3.15-rc4.orig/arch/arm/mach-omap2/common.h 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-omap2/common.h 2014-05-07 17:05:51.040166651 +0200 -@@ -91,6 +91,7 @@ - extern void omap3_secure_sync32k_timer_init(void); - extern void omap3_gptimer_timer_init(void); - extern void omap4_local_timer_init(void); -+int omap_l2_cache_init(void); - extern void omap5_realtime_timer_init(void); - - void omap2420_init_early(void); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-omap2/io.c linux-3.15-rc4/arch/arm/mach-omap2/io.c ---- linux-3.15-rc4.orig/arch/arm/mach-omap2/io.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-omap2/io.c 2014-05-07 17:05:51.040166651 +0200 -@@ -609,6 +609,7 @@ - am43xx_clockdomains_init(); - am43xx_hwmod_init(); - omap_hwmod_init_postsetup(); -+ omap_l2_cache_init(); - omap_clk_soc_init = am43xx_dt_clk_init; - } - -@@ -640,6 +641,7 @@ - omap44xx_clockdomains_init(); - omap44xx_hwmod_init(); - omap_hwmod_init_postsetup(); -+ omap_l2_cache_init(); - omap_clk_soc_init = omap4xxx_dt_clk_init; - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-omap2/Kconfig linux-3.15-rc4/arch/arm/mach-omap2/Kconfig ---- linux-3.15-rc4.orig/arch/arm/mach-omap2/Kconfig 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-omap2/Kconfig 2014-05-07 17:05:51.040166651 +0200 -@@ -65,6 +65,7 @@ - select ARCH_HAS_OPP - select ARM_GIC - select MACH_OMAP_GENERIC -+ select MIGHT_HAVE_CACHE_L2X0 - - config SOC_DRA7XX - bool "TI DRA7XX" -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-omap2/omap4-common.c linux-3.15-rc4/arch/arm/mach-omap2/omap4-common.c ---- linux-3.15-rc4.orig/arch/arm/mach-omap2/omap4-common.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-omap2/omap4-common.c 2014-05-07 17:05:51.040166651 +0200 -@@ -167,75 +167,57 @@ - return l2cache_base; - } - --static void omap4_l2x0_disable(void) -+static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) - { -- outer_flush_all(); -- /* Disable PL310 L2 Cache controller */ -- omap_smc1(0x102, 0x0); --} -+ unsigned smc_op; - --static void omap4_l2x0_set_debug(unsigned long val) --{ -- /* Program PL310 L2 Cache controller debug register */ -- omap_smc1(0x100, val); -+ switch (reg) { -+ case L2X0_CTRL: -+ smc_op = OMAP4_MON_L2X0_CTRL_INDEX; -+ break; -+ -+ case L2X0_AUX_CTRL: -+ smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX; -+ break; -+ -+ case L2X0_DEBUG_CTRL: -+ smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX; -+ break; -+ -+ case L310_PREFETCH_CTRL: -+ smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX; -+ break; -+ -+ default: -+ WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); -+ return; -+ } -+ -+ omap_smc1(smc_op, val); - } - --static int __init omap_l2_cache_init(void) -+int __init omap_l2_cache_init(void) - { -- u32 aux_ctrl = 0; -- -- /* -- * To avoid code running on other OMAPs in -- * multi-omap builds -- */ -- if (!cpu_is_omap44xx()) -- return -ENODEV; -+ u32 aux_ctrl; - - /* Static mapping, never released */ - l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); - if (WARN_ON(!l2cache_base)) - return -ENOMEM; - -- /* -- * 16-way associativity, parity disabled -- * Way size - 32KB (es1.0) -- * Way size - 64KB (es2.0 +) -- */ -- aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | -- (0x1 << 25) | -- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | -- (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); -- -- if (omap_rev() == OMAP4430_REV_ES1_0) { -- aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; -- } else { -- aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | -- (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | -- (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | -- (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | -- (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); -- } -- if (omap_rev() != OMAP4430_REV_ES1_0) -- omap_smc1(0x109, aux_ctrl); -- -- /* Enable PL310 L2 Cache controller */ -- omap_smc1(0x102, 0x1); -+ /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ -+ aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE | -+ L310_AUX_CTRL_DATA_PREFETCH | -+ L310_AUX_CTRL_INSTR_PREFETCH; - -+ outer_cache.write_sec = omap4_l2c310_write_sec; - if (of_have_populated_dt()) -- l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); -+ l2x0_of_init(aux_ctrl, 0xcf9fffff); - else -- l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); -- -- /* -- * Override default outer_cache.disable with a OMAP4 -- * specific one -- */ -- outer_cache.disable = omap4_l2x0_disable; -- outer_cache.set_debug = omap4_l2x0_set_debug; -+ l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff); - - return 0; - } --omap_early_initcall(omap_l2_cache_init); - #endif - - void __iomem *omap4_get_sar_ram_base(void) -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-omap2/omap-mpuss-lowpower.c linux-3.15-rc4/arch/arm/mach-omap2/omap-mpuss-lowpower.c ---- linux-3.15-rc4.orig/arch/arm/mach-omap2/omap-mpuss-lowpower.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-omap2/omap-mpuss-lowpower.c 2014-05-07 17:05:51.040166651 +0200 -@@ -187,19 +187,15 @@ - * in every restore MPUSS OFF path. - */ - #ifdef CONFIG_CACHE_L2X0 --static void save_l2x0_context(void) -+static void __init save_l2x0_context(void) - { -- u32 val; -- void __iomem *l2x0_base = omap4_get_l2cache_base(); -- if (l2x0_base) { -- val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); -- __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); -- val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); -- __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); -- } -+ __raw_writel(l2x0_saved_regs.aux_ctrl, -+ sar_base + L2X0_AUXCTRL_OFFSET); -+ __raw_writel(l2x0_saved_regs.prefetch_ctrl, -+ sar_base + L2X0_PREFETCH_CTRL_OFFSET); - } - #else --static void save_l2x0_context(void) -+static void __init save_l2x0_context(void) - {} - #endif - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-prima2/l2x0.c linux-3.15-rc4/arch/arm/mach-prima2/l2x0.c ---- linux-3.15-rc4.orig/arch/arm/mach-prima2/l2x0.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-prima2/l2x0.c 2014-05-07 17:05:51.040166651 +0200 -@@ -8,42 +8,10 @@ - - #include - #include --#include - #include - --struct l2x0_aux { -- u32 val; -- u32 mask; --}; -- --static const struct l2x0_aux prima2_l2x0_aux __initconst = { -- .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT, -- .mask = 0, --}; -- --static const struct l2x0_aux marco_l2x0_aux __initconst = { -- .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | -- (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT), -- .mask = L2X0_AUX_CTRL_MASK, --}; -- --static const struct of_device_id sirf_l2x0_ids[] __initconst = { -- { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, }, -- { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, }, -- {}, --}; -- - static int __init sirfsoc_l2x0_init(void) - { -- struct device_node *np; -- const struct l2x0_aux *aux; -- -- np = of_find_matching_node(NULL, sirf_l2x0_ids); -- if (np) { -- aux = of_match_node(sirf_l2x0_ids, np)->data; -- return l2x0_of_init(aux->val, aux->mask); -- } -- -- return 0; -+ return l2x0_of_init(0, ~0); - } - early_initcall(sirfsoc_l2x0_init); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-prima2/pm.c linux-3.15-rc4/arch/arm/mach-prima2/pm.c ---- linux-3.15-rc4.orig/arch/arm/mach-prima2/pm.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-prima2/pm.c 2014-05-07 17:05:51.044166676 +0200 -@@ -71,7 +71,6 @@ - case PM_SUSPEND_MEM: - sirfsoc_pre_suspend_power_off(); - -- outer_flush_all(); - outer_disable(); - /* go zzz */ - cpu_suspend(0, sirfsoc_finish_suspend); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-realview/realview_eb.c linux-3.15-rc4/arch/arm/mach-realview/realview_eb.c ---- linux-3.15-rc4.orig/arch/arm/mach-realview/realview_eb.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-realview/realview_eb.c 2014-05-07 17:05:51.044166676 +0200 -@@ -442,8 +442,13 @@ - realview_eb11mp_fixup(); - - #ifdef CONFIG_CACHE_L2X0 -- /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled -- * Bits: .... ...0 0111 1001 0000 .... .... .... */ -+ /* -+ * The PL220 needs to be manually configured as the hardware -+ * doesn't report the correct sizes. -+ * 1MB (128KB/way), 8-way associativity, event monitor and -+ * parity enabled, ignore share bit, no force write allocate -+ * Bits: .... ...0 0111 1001 0000 .... .... .... -+ */ - l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); - #endif - platform_device_register(&pmu_device); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-realview/realview_pb1176.c linux-3.15-rc4/arch/arm/mach-realview/realview_pb1176.c ---- linux-3.15-rc4.orig/arch/arm/mach-realview/realview_pb1176.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-realview/realview_pb1176.c 2014-05-07 17:05:51.044166676 +0200 -@@ -355,7 +355,13 @@ - int i; - - #ifdef CONFIG_CACHE_L2X0 -- /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */ -+ /* -+ * The PL220 needs to be manually configured as the hardware -+ * doesn't report the correct sizes. -+ * 128kB (16kB/way), 8-way associativity, event monitor and -+ * parity enabled, ignore share bit, no force write allocate -+ * Bits: .... ...0 0111 0011 0000 .... .... .... -+ */ - l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); - #endif - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-realview/realview_pb11mp.c linux-3.15-rc4/arch/arm/mach-realview/realview_pb11mp.c ---- linux-3.15-rc4.orig/arch/arm/mach-realview/realview_pb11mp.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-realview/realview_pb11mp.c 2014-05-07 17:05:51.044166676 +0200 -@@ -337,8 +337,13 @@ - int i; - - #ifdef CONFIG_CACHE_L2X0 -- /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled -- * Bits: .... ...0 0111 1001 0000 .... .... .... */ -+ /* -+ * The PL220 needs to be manually configured as the hardware -+ * doesn't report the correct sizes. -+ * 1MB (128KB/way), 8-way associativity, event monitor and -+ * parity enabled, ignore share bit, no force write allocate -+ * Bits: .... ...0 0111 1001 0000 .... .... .... -+ */ - l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff); - #endif - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-realview/realview_pbx.c linux-3.15-rc4/arch/arm/mach-realview/realview_pbx.c ---- linux-3.15-rc4.orig/arch/arm/mach-realview/realview_pbx.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-realview/realview_pbx.c 2014-05-07 17:05:51.044166676 +0200 -@@ -370,8 +370,8 @@ - __io_address(REALVIEW_PBX_TILE_L220_BASE); - - /* set RAM latencies to 1 cycle for eASIC */ -- writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL); -- writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL); -+ writel(0, l2x0_base + L310_TAG_LATENCY_CTRL); -+ writel(0, l2x0_base + L310_DATA_LATENCY_CTRL); - - /* 16KB way size, 8-way associativity, parity disabled - * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */ -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-rockchip/rockchip.c linux-3.15-rc4/arch/arm/mach-rockchip/rockchip.c ---- linux-3.15-rc4.orig/arch/arm/mach-rockchip/rockchip.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-rockchip/rockchip.c 2014-05-07 17:05:51.044166676 +0200 -@@ -26,7 +26,7 @@ - - static void __init rockchip_dt_init(void) - { -- l2x0_of_init(0, ~0UL); -+ l2x0_of_init(0, ~0); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-armadillo800eva.c linux-3.15-rc4/arch/arm/mach-shmobile/board-armadillo800eva.c ---- linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-armadillo800eva.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-shmobile/board-armadillo800eva.c 2014-05-07 17:05:51.044166676 +0200 -@@ -1271,8 +1271,8 @@ - - - #ifdef CONFIG_CACHE_L2X0 -- /* Early BRESP enable, Shared attribute override enable, 32K*8way */ -- l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); -+ /* Shared attribute override enable, 32K*8way */ -+ l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); - #endif - - i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-armadillo800eva-reference.c linux-3.15-rc4/arch/arm/mach-shmobile/board-armadillo800eva-reference.c ---- linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-armadillo800eva-reference.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-shmobile/board-armadillo800eva-reference.c 2014-05-07 17:05:51.044166676 +0200 -@@ -164,8 +164,8 @@ - r8a7740_meram_workaround(); - - #ifdef CONFIG_CACHE_L2X0 -- /* Early BRESP enable, Shared attribute override enable, 32K*8way */ -- l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); -+ /* Shared attribute override enable, 32K*8way */ -+ l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); - #endif - - r8a7740_add_standard_devices_dt(); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-kzm9g.c linux-3.15-rc4/arch/arm/mach-shmobile/board-kzm9g.c ---- linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-kzm9g.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-shmobile/board-kzm9g.c 2014-05-07 17:05:51.044166676 +0200 -@@ -876,8 +876,8 @@ - gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ - - #ifdef CONFIG_CACHE_L2X0 -- /* Early BRESP enable, Shared attribute override enable, 64K*8way */ -- l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); -+ /* Shared attribute override enable, 64K*8way */ -+ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); - #endif - - i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-kzm9g-reference.c linux-3.15-rc4/arch/arm/mach-shmobile/board-kzm9g-reference.c ---- linux-3.15-rc4.orig/arch/arm/mach-shmobile/board-kzm9g-reference.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-shmobile/board-kzm9g-reference.c 2014-05-07 17:05:51.044166676 +0200 -@@ -36,8 +36,8 @@ - sh73a0_add_standard_devices_dt(); - - #ifdef CONFIG_CACHE_L2X0 -- /* Early BRESP enable, Shared attribute override enable, 64K*8way */ -- l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff); -+ /* Shared attribute override enable, 64K*8way */ -+ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); - #endif - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-shmobile/setup-r8a7778.c linux-3.15-rc4/arch/arm/mach-shmobile/setup-r8a7778.c ---- linux-3.15-rc4.orig/arch/arm/mach-shmobile/setup-r8a7778.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-shmobile/setup-r8a7778.c 2014-05-07 17:05:51.044166676 +0200 -@@ -298,10 +298,10 @@ - void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); - if (base) { - /* -- * Early BRESP enable, Shared attribute override enable, 64K*16way -+ * Shared attribute override enable, 64K*16way - * don't call iounmap(base) - */ -- l2x0_init(base, 0x40470000, 0x82000fff); -+ l2x0_init(base, 0x00400000, 0xc20f0fff); - } - #endif - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-shmobile/setup-r8a7779.c linux-3.15-rc4/arch/arm/mach-shmobile/setup-r8a7779.c ---- linux-3.15-rc4.orig/arch/arm/mach-shmobile/setup-r8a7779.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-shmobile/setup-r8a7779.c 2014-05-07 17:05:51.048166700 +0200 -@@ -700,8 +700,8 @@ - void __init r8a7779_add_standard_devices(void) - { - #ifdef CONFIG_CACHE_L2X0 -- /* Early BRESP enable, Shared attribute override enable, 64K*16way */ -- l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff); -+ /* Shared attribute override enable, 64K*16way */ -+ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); - #endif - r8a7779_pm_init(); - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-socfpga/socfpga.c linux-3.15-rc4/arch/arm/mach-socfpga/socfpga.c ---- linux-3.15-rc4.orig/arch/arm/mach-socfpga/socfpga.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-socfpga/socfpga.c 2014-05-07 17:05:51.048166700 +0200 -@@ -100,7 +100,7 @@ - - static void __init socfpga_cyclone5_init(void) - { -- l2x0_of_init(0, ~0UL); -+ l2x0_of_init(0, ~0); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - } - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-spear/platsmp.c linux-3.15-rc4/arch/arm/mach-spear/platsmp.c ---- linux-3.15-rc4.orig/arch/arm/mach-spear/platsmp.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-spear/platsmp.c 2014-05-07 17:05:51.048166700 +0200 -@@ -20,6 +20,18 @@ - #include - #include "generic.h" - -+/* -+ * Write pen_release in a way that is guaranteed to be visible to all -+ * observers, irrespective of whether they're taking part in coherency -+ * or not. This is necessary for the hotplug code to work reliably. -+ */ -+static void write_pen_release(int val) -+{ -+ pen_release = val; -+ smp_wmb(); -+ sync_cache_w(&pen_release); -+} -+ - static DEFINE_SPINLOCK(boot_lock); - - static void __iomem *scu_base = IOMEM(VA_SCU_BASE); -@@ -30,8 +42,7 @@ - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ -- pen_release = -1; -- smp_wmb(); -+ write_pen_release(-1); - - /* - * Synchronise with the boot thread. -@@ -58,9 +69,7 @@ - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. - */ -- pen_release = cpu; -- flush_cache_all(); -- outer_flush_all(); -+ write_pen_release(cpu); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-spear/spear13xx.c linux-3.15-rc4/arch/arm/mach-spear/spear13xx.c ---- linux-3.15-rc4.orig/arch/arm/mach-spear/spear13xx.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-spear/spear13xx.c 2014-05-07 17:05:51.048166700 +0200 -@@ -38,15 +38,15 @@ - if (!IS_ENABLED(CONFIG_CACHE_L2X0)) - return; - -- writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); -+ writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); - - /* - * Program following latencies in order to make - * SPEAr1340 work at 600 MHz - */ -- writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); -- writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); -- l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); -+ writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); -+ writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); -+ l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); - } - - /* -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-sti/board-dt.c linux-3.15-rc4/arch/arm/mach-sti/board-dt.c ---- linux-3.15-rc4.orig/arch/arm/mach-sti/board-dt.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-sti/board-dt.c 2014-05-07 17:05:51.048166700 +0200 -@@ -16,15 +16,9 @@ - - void __init stih41x_l2x0_init(void) - { -- u32 way_size = 0x4; -- u32 aux_ctrl; -- /* may be this can be encoded in macros like BIT*() */ -- aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | -- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | -- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | -- (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); -- -- l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); -+ l2x0_of_init(L2C_AUX_CTRL_SHARED_OVERRIDE | -+ L310_AUX_CTRL_DATA_PREFETCH | -+ L310_AUX_CTRL_INSTR_PREFETCH, 0xc00f0fff); - } - - static void __init stih41x_machine_init(void) -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-tegra/pm.h linux-3.15-rc4/arch/arm/mach-tegra/pm.h ---- linux-3.15-rc4.orig/arch/arm/mach-tegra/pm.h 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-tegra/pm.h 2014-05-07 17:05:51.048166700 +0200 -@@ -35,8 +35,6 @@ - void tegra30_lp1_iram_hook(void); - void tegra30_sleep_core_init(void); - --extern unsigned long l2x0_saved_regs_addr; -- - void tegra_clear_cpu_in_lp2(void); - bool tegra_set_cpu_in_lp2(void); - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-tegra/reset-handler.S linux-3.15-rc4/arch/arm/mach-tegra/reset-handler.S ---- linux-3.15-rc4.orig/arch/arm/mach-tegra/reset-handler.S 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-tegra/reset-handler.S 2014-05-07 17:05:51.048166700 +0200 -@@ -19,7 +19,6 @@ - - #include - #include --#include - - #include "flowctrl.h" - #include "fuse.h" -@@ -78,8 +77,10 @@ - str r1, [r0] - #endif - -+#ifdef CONFIG_CACHE_L2X0 - /* L2 cache resume & re-enable */ -- l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr -+ bl l2c310_early_resume -+#endif - end_ca9_scu_l2_resume: - mov32 r9, 0xc0f - cmp r8, r9 -@@ -89,12 +90,6 @@ - ENDPROC(tegra_resume) - #endif - --#ifdef CONFIG_CACHE_L2X0 -- .globl l2x0_saved_regs_addr --l2x0_saved_regs_addr: -- .long 0 --#endif -- - .align L1_CACHE_SHIFT - ENTRY(__tegra_cpu_reset_handler_start) - -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-tegra/sleep.h linux-3.15-rc4/arch/arm/mach-tegra/sleep.h ---- linux-3.15-rc4.orig/arch/arm/mach-tegra/sleep.h 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-tegra/sleep.h 2014-05-07 17:05:51.048166700 +0200 -@@ -120,37 +120,6 @@ - mov \tmp1, \tmp1, lsr #8 - .endm - --/* Macro to resume & re-enable L2 cache */ --#ifndef L2X0_CTRL_EN --#define L2X0_CTRL_EN 1 --#endif -- --#ifdef CONFIG_CACHE_L2X0 --.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs -- W(adr) \tmp1, \phys_l2x0_saved_regs -- ldr \tmp1, [\tmp1] -- ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] -- ldr \tmp3, [\tmp2, #L2X0_CTRL] -- tst \tmp3, #L2X0_CTRL_EN -- bne exit_l2_resume -- ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY] -- str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL] -- ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY] -- str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL] -- ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL] -- str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL] -- ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL] -- str \tmp3, [\tmp2, #L2X0_POWER_CTRL] -- ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL] -- str \tmp3, [\tmp2, #L2X0_AUX_CTRL] -- mov \tmp3, #L2X0_CTRL_EN -- str \tmp3, [\tmp2, #L2X0_CTRL] --exit_l2_resume: --.endm --#else /* CONFIG_CACHE_L2X0 */ --.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs --.endm --#endif /* CONFIG_CACHE_L2X0 */ - #else - void tegra_pen_lock(void); - void tegra_pen_unlock(void); -diff -Nur linux-3.15-rc4.orig/arch/arm/mach-tegra/tegra.c linux-3.15-rc4/arch/arm/mach-tegra/tegra.c ---- linux-3.15-rc4.orig/arch/arm/mach-tegra/tegra.c 2014-05-05 03:14:42.000000000 +0200 -+++ linux-3.15-rc4/arch/arm/mach-tegra/tegra.c 2014-05-07 17:05:51.048166700 +0200 -@@ -73,27 +73,7 @@ - static void __init tegra_init_cache(void) - { - #ifdef CONFIG_CACHE_L2X0 -- static const struct of_device_id pl310_ids[] __initconst = { -- { .compatible